11f4d4ed6SAlexander Lobakin // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 3e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 4663eacd8SAlexander Lobakin * Copyright (c) 2019-2020 Marvell International Ltd. 5fe56b9e6SYuval Mintz */ 6fe56b9e6SYuval Mintz 7fe56b9e6SYuval Mintz #include <linux/types.h> 8fe56b9e6SYuval Mintz #include <asm/byteorder.h> 9fe56b9e6SYuval Mintz #include <linux/io.h> 10fe56b9e6SYuval Mintz #include <linux/bitops.h> 11fe56b9e6SYuval Mintz #include <linux/delay.h> 12fe56b9e6SYuval Mintz #include <linux/dma-mapping.h> 13fe56b9e6SYuval Mintz #include <linux/errno.h> 14fe56b9e6SYuval Mintz #include <linux/interrupt.h> 15fe56b9e6SYuval Mintz #include <linux/kernel.h> 16fe56b9e6SYuval Mintz #include <linux/pci.h> 17fe56b9e6SYuval Mintz #include <linux/slab.h> 18fe56b9e6SYuval Mintz #include <linux/string.h> 19fe56b9e6SYuval Mintz #include "qed.h" 20fe56b9e6SYuval Mintz #include "qed_hsi.h" 21fe56b9e6SYuval Mintz #include "qed_hw.h" 22fe56b9e6SYuval Mintz #include "qed_init_ops.h" 23fe56b9e6SYuval Mintz #include "qed_int.h" 24fe56b9e6SYuval Mintz #include "qed_mcp.h" 25fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 26fe56b9e6SYuval Mintz #include "qed_sp.h" 271408cc1fSYuval Mintz #include "qed_sriov.h" 281408cc1fSYuval Mintz #include "qed_vf.h" 29fe56b9e6SYuval Mintz 30fe56b9e6SYuval Mintz struct qed_pi_info { 31fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb; 32fe56b9e6SYuval Mintz void *cookie; 33fe56b9e6SYuval Mintz }; 34fe56b9e6SYuval Mintz 35fe56b9e6SYuval Mintz struct qed_sb_sp_info { 36fe56b9e6SYuval Mintz struct qed_sb_info sb_info; 37fe56b9e6SYuval Mintz 38fe56b9e6SYuval Mintz /* per protocol index data */ 3921dd79e8STomer Tayar struct qed_pi_info pi_info_arr[PIS_PER_SB_E4]; 40fe56b9e6SYuval Mintz }; 41fe56b9e6SYuval Mintz 42ff38577aSYuval Mintz enum qed_attention_type { 43ff38577aSYuval Mintz QED_ATTN_TYPE_ATTN, 44ff38577aSYuval Mintz QED_ATTN_TYPE_PARITY, 45ff38577aSYuval Mintz }; 46ff38577aSYuval Mintz 47cc875c2eSYuval Mintz #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \ 48cc875c2eSYuval Mintz ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn) 49cc875c2eSYuval Mintz 500d956e8aSYuval Mintz struct aeu_invert_reg_bit { 510d956e8aSYuval Mintz char bit_name[30]; 520d956e8aSYuval Mintz 530d956e8aSYuval Mintz #define ATTENTION_PARITY (1 << 0) 540d956e8aSYuval Mintz 550d956e8aSYuval Mintz #define ATTENTION_LENGTH_MASK (0x00000ff0) 560d956e8aSYuval Mintz #define ATTENTION_LENGTH_SHIFT (4) 570d956e8aSYuval Mintz #define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \ 580d956e8aSYuval Mintz ATTENTION_LENGTH_SHIFT) 59a2e7699eSTomer Tayar #define ATTENTION_SINGLE BIT(ATTENTION_LENGTH_SHIFT) 600d956e8aSYuval Mintz #define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY) 610d956e8aSYuval Mintz #define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \ 620d956e8aSYuval Mintz ATTENTION_PARITY) 630d956e8aSYuval Mintz 640d956e8aSYuval Mintz /* Multiple bits start with this offset */ 650d956e8aSYuval Mintz #define ATTENTION_OFFSET_MASK (0x000ff000) 660d956e8aSYuval Mintz #define ATTENTION_OFFSET_SHIFT (12) 67ba36f718SMintz, Yuval 68ba36f718SMintz, Yuval #define ATTENTION_BB_MASK (0x00700000) 69ba36f718SMintz, Yuval #define ATTENTION_BB_SHIFT (20) 70ba36f718SMintz, Yuval #define ATTENTION_BB(value) (value << ATTENTION_BB_SHIFT) 71ba36f718SMintz, Yuval #define ATTENTION_BB_DIFFERENT BIT(23) 72ba36f718SMintz, Yuval 73936c7ba4SIgor Russkikh #define ATTENTION_CLEAR_ENABLE BIT(28) 740d956e8aSYuval Mintz unsigned int flags; 75ff38577aSYuval Mintz 76b4149dc7SYuval Mintz /* Callback to call if attention will be triggered */ 77b4149dc7SYuval Mintz int (*cb)(struct qed_hwfn *p_hwfn); 78b4149dc7SYuval Mintz 79ff38577aSYuval Mintz enum block_id block_index; 800d956e8aSYuval Mintz }; 810d956e8aSYuval Mintz 820d956e8aSYuval Mintz struct aeu_invert_reg { 830d956e8aSYuval Mintz struct aeu_invert_reg_bit bits[32]; 840d956e8aSYuval Mintz }; 850d956e8aSYuval Mintz 860d956e8aSYuval Mintz #define MAX_ATTN_GRPS (8) 870d956e8aSYuval Mintz #define NUM_ATTN_REGS (9) 880d956e8aSYuval Mintz 89b4149dc7SYuval Mintz /* Specific HW attention callbacks */ 90b4149dc7SYuval Mintz static int qed_mcp_attn_cb(struct qed_hwfn *p_hwfn) 91b4149dc7SYuval Mintz { 92b4149dc7SYuval Mintz u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE); 93b4149dc7SYuval Mintz 94b4149dc7SYuval Mintz /* This might occur on certain instances; Log it once then mask it */ 95b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, "MCP_REG_CPU_STATE: %08x - Masking...\n", 96b4149dc7SYuval Mintz tmp); 97b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, 98b4149dc7SYuval Mintz 0xffffffff); 99b4149dc7SYuval Mintz 100b4149dc7SYuval Mintz return 0; 101b4149dc7SYuval Mintz } 102b4149dc7SYuval Mintz 103b4149dc7SYuval Mintz #define QED_PSWHST_ATTENTION_INCORRECT_ACCESS (0x1) 104b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_WR_MASK (0x1) 105b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_WR_SHIFT (0) 106b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_CLIENT_MASK (0xf) 107b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT (1) 108b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK (0x1) 109b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT (5) 110b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_ID_MASK (0xff) 111b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT (6) 112b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_PF_ID_MASK (0xf) 113b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT (14) 114b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK (0xff) 115b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT (18) 116b4149dc7SYuval Mintz static int qed_pswhst_attn_cb(struct qed_hwfn *p_hwfn) 117b4149dc7SYuval Mintz { 118b4149dc7SYuval Mintz u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 119b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_VALID); 120b4149dc7SYuval Mintz 121b4149dc7SYuval Mintz if (tmp & QED_PSWHST_ATTENTION_INCORRECT_ACCESS) { 122b4149dc7SYuval Mintz u32 addr, data, length; 123b4149dc7SYuval Mintz 124b4149dc7SYuval Mintz addr = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 125b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_ADDRESS); 126b4149dc7SYuval Mintz data = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 127b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_DATA); 128b4149dc7SYuval Mintz length = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 129b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_LENGTH); 130b4149dc7SYuval Mintz 131b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, 132b4149dc7SYuval Mintz "Incorrect access to %08x of length %08x - PF [%02x] VF [%04x] [valid %02x] client [%02x] write [%02x] Byte-Enable [%04x] [%08x]\n", 133b4149dc7SYuval Mintz addr, length, 134b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_PF_ID), 135b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_VF_ID), 136b4149dc7SYuval Mintz (u8) GET_FIELD(data, 137b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_VF_VALID), 138b4149dc7SYuval Mintz (u8) GET_FIELD(data, 139b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_CLIENT), 140b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_WR), 141b4149dc7SYuval Mintz (u8) GET_FIELD(data, 142b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_BYTE_EN), 143b4149dc7SYuval Mintz data); 144b4149dc7SYuval Mintz } 145b4149dc7SYuval Mintz 146b4149dc7SYuval Mintz return 0; 147b4149dc7SYuval Mintz } 148b4149dc7SYuval Mintz 149b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VALID_BIT (1 << 0) 150b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_ADDRESS_MASK (0x7fffff) 151b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_ADDRESS_SHIFT (0) 152b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_RDWR_BIT (1 << 23) 153b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_MASTER_MASK (0xf) 154b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_MASTER_SHIFT (24) 155b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PF_MASK (0xf) 156b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PF_SHIFT (0) 157b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VF_MASK (0xff) 158b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VF_SHIFT (4) 159b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_MASK (0x3) 160b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_SHIFT (14) 161b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_VF (0) 162b4149dc7SYuval Mintz static const char *attn_master_to_str(u8 master) 163b4149dc7SYuval Mintz { 164b4149dc7SYuval Mintz switch (master) { 165b4149dc7SYuval Mintz case 1: return "PXP"; 166b4149dc7SYuval Mintz case 2: return "MCP"; 167b4149dc7SYuval Mintz case 3: return "MSDM"; 168b4149dc7SYuval Mintz case 4: return "PSDM"; 169b4149dc7SYuval Mintz case 5: return "YSDM"; 170b4149dc7SYuval Mintz case 6: return "USDM"; 171b4149dc7SYuval Mintz case 7: return "TSDM"; 172b4149dc7SYuval Mintz case 8: return "XSDM"; 173b4149dc7SYuval Mintz case 9: return "DBU"; 174b4149dc7SYuval Mintz case 10: return "DMAE"; 175b4149dc7SYuval Mintz default: 1769165dabbSMasanari Iida return "Unknown"; 177b4149dc7SYuval Mintz } 178b4149dc7SYuval Mintz } 179b4149dc7SYuval Mintz 180b4149dc7SYuval Mintz static int qed_grc_attn_cb(struct qed_hwfn *p_hwfn) 181b4149dc7SYuval Mintz { 182b4149dc7SYuval Mintz u32 tmp, tmp2; 183b4149dc7SYuval Mintz 184b4149dc7SYuval Mintz /* We've already cleared the timeout interrupt register, so we learn 185b4149dc7SYuval Mintz * of interrupts via the validity register 186b4149dc7SYuval Mintz */ 187b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 188b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_VALID); 189b4149dc7SYuval Mintz if (!(tmp & QED_GRC_ATTENTION_VALID_BIT)) 190b4149dc7SYuval Mintz goto out; 191b4149dc7SYuval Mintz 192b4149dc7SYuval Mintz /* Read the GRC timeout information */ 193b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 194b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0); 195b4149dc7SYuval Mintz tmp2 = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 196b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1); 197b4149dc7SYuval Mintz 198b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, 199b4149dc7SYuval Mintz "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n", 200b4149dc7SYuval Mintz tmp2, tmp, 201b4149dc7SYuval Mintz (tmp & QED_GRC_ATTENTION_RDWR_BIT) ? "Write to" : "Read from", 202b4149dc7SYuval Mintz GET_FIELD(tmp, QED_GRC_ATTENTION_ADDRESS) << 2, 203b4149dc7SYuval Mintz attn_master_to_str(GET_FIELD(tmp, QED_GRC_ATTENTION_MASTER)), 204b4149dc7SYuval Mintz GET_FIELD(tmp2, QED_GRC_ATTENTION_PF), 205b4149dc7SYuval Mintz (GET_FIELD(tmp2, QED_GRC_ATTENTION_PRIV) == 206fbe1222cSColin Ian King QED_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Irrelevant)", 207b4149dc7SYuval Mintz GET_FIELD(tmp2, QED_GRC_ATTENTION_VF)); 208b4149dc7SYuval Mintz 209b4149dc7SYuval Mintz out: 210b4149dc7SYuval Mintz /* Regardles of anything else, clean the validity bit */ 211b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 212b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0); 213b4149dc7SYuval Mintz return 0; 214b4149dc7SYuval Mintz } 215b4149dc7SYuval Mintz 216b4149dc7SYuval Mintz #define PGLUE_ATTENTION_VALID (1 << 29) 217b4149dc7SYuval Mintz #define PGLUE_ATTENTION_RD_VALID (1 << 26) 218b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf) 219b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20) 220b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VF_VALID_MASK (0x1) 221b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VF_VALID_SHIFT (19) 222b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff) 223b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24) 224b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_MASK (0x1) 225b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_SHIFT (21) 226b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_BME_MASK (0x1) 227b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_BME_SHIFT (22) 228b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_FID_EN_MASK (0x1) 229b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_FID_EN_SHIFT (23) 230b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ICPL_VALID (1 << 23) 231b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ZLR_VALID (1 << 25) 232b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ILT_VALID (1 << 23) 233666db486STomer Tayar 234eb61c2d6SAlexander Lobakin int qed_pglueb_rbc_attn_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 235eb61c2d6SAlexander Lobakin bool hw_init) 236b4149dc7SYuval Mintz { 237eb61c2d6SAlexander Lobakin char msg[256]; 238b4149dc7SYuval Mintz u32 tmp; 239b4149dc7SYuval Mintz 240666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS2); 241b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_VALID) { 242b4149dc7SYuval Mintz u32 addr_lo, addr_hi, details; 243b4149dc7SYuval Mintz 244666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 245b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_ADD_31_0); 246666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 247b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_ADD_63_32); 248666db486STomer Tayar details = qed_rd(p_hwfn, p_ptt, 249b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_DETAILS); 250b4149dc7SYuval Mintz 251eb61c2d6SAlexander Lobakin snprintf(msg, sizeof(msg), 252b4149dc7SYuval Mintz "Illegal write by chip to [%08x:%08x] blocked.\n" 253b4149dc7SYuval Mintz "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 254eb61c2d6SAlexander Lobakin "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]", 255b4149dc7SYuval Mintz addr_hi, addr_lo, details, 256b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 257b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 258eb61c2d6SAlexander Lobakin !!GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VF_VALID), 259b4149dc7SYuval Mintz tmp, 260eb61c2d6SAlexander Lobakin !!GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_WAS_ERR), 261eb61c2d6SAlexander Lobakin !!GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_BME), 262eb61c2d6SAlexander Lobakin !!GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_FID_EN)); 263eb61c2d6SAlexander Lobakin 264eb61c2d6SAlexander Lobakin if (hw_init) 265eb61c2d6SAlexander Lobakin DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "%s\n", msg); 266eb61c2d6SAlexander Lobakin else 267eb61c2d6SAlexander Lobakin DP_NOTICE(p_hwfn, "%s\n", msg); 268b4149dc7SYuval Mintz } 269b4149dc7SYuval Mintz 270666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_RD_DETAILS2); 271b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_RD_VALID) { 272b4149dc7SYuval Mintz u32 addr_lo, addr_hi, details; 273b4149dc7SYuval Mintz 274666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 275b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_ADD_31_0); 276666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 277b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_ADD_63_32); 278666db486STomer Tayar details = qed_rd(p_hwfn, p_ptt, 279b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_DETAILS); 280b4149dc7SYuval Mintz 281666db486STomer Tayar DP_NOTICE(p_hwfn, 282b4149dc7SYuval Mintz "Illegal read by chip from [%08x:%08x] blocked.\n" 283b4149dc7SYuval Mintz "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 284b4149dc7SYuval Mintz "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 285b4149dc7SYuval Mintz addr_hi, addr_lo, details, 286b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 287b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 288b4149dc7SYuval Mintz GET_FIELD(details, 289b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0, 290b4149dc7SYuval Mintz tmp, 291666db486STomer Tayar GET_FIELD(tmp, 292666db486STomer Tayar PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0, 293666db486STomer Tayar GET_FIELD(tmp, 294666db486STomer Tayar PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0, 295666db486STomer Tayar GET_FIELD(tmp, 296666db486STomer Tayar PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0); 297b4149dc7SYuval Mintz } 298b4149dc7SYuval Mintz 299666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL); 300eb61c2d6SAlexander Lobakin if (tmp & PGLUE_ATTENTION_ICPL_VALID) { 301eb61c2d6SAlexander Lobakin snprintf(msg, sizeof(msg), "ICPL error - %08x", tmp); 302eb61c2d6SAlexander Lobakin 303eb61c2d6SAlexander Lobakin if (hw_init) 304eb61c2d6SAlexander Lobakin DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "%s\n", msg); 305eb61c2d6SAlexander Lobakin else 306eb61c2d6SAlexander Lobakin DP_NOTICE(p_hwfn, "%s\n", msg); 307eb61c2d6SAlexander Lobakin } 308b4149dc7SYuval Mintz 309666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS); 310b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ZLR_VALID) { 311b4149dc7SYuval Mintz u32 addr_hi, addr_lo; 312b4149dc7SYuval Mintz 313666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 314b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0); 315666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 316b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32); 317b4149dc7SYuval Mintz 318666db486STomer Tayar DP_NOTICE(p_hwfn, "ZLR error - %08x [Address %08x:%08x]\n", 319b4149dc7SYuval Mintz tmp, addr_hi, addr_lo); 320b4149dc7SYuval Mintz } 321b4149dc7SYuval Mintz 322666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_VF_ILT_ERR_DETAILS2); 323b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ILT_VALID) { 324b4149dc7SYuval Mintz u32 addr_hi, addr_lo, details; 325b4149dc7SYuval Mintz 326666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 327b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_ADD_31_0); 328666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 329b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_ADD_63_32); 330666db486STomer Tayar details = qed_rd(p_hwfn, p_ptt, 331b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_DETAILS); 332b4149dc7SYuval Mintz 333666db486STomer Tayar DP_NOTICE(p_hwfn, 334b4149dc7SYuval Mintz "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n", 335b4149dc7SYuval Mintz details, tmp, addr_hi, addr_lo); 336b4149dc7SYuval Mintz } 337b4149dc7SYuval Mintz 338b4149dc7SYuval Mintz /* Clear the indications */ 339666db486STomer Tayar qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_LATCHED_ERRORS_CLR, BIT(2)); 340b4149dc7SYuval Mintz 341b4149dc7SYuval Mintz return 0; 342b4149dc7SYuval Mintz } 343b4149dc7SYuval Mintz 344666db486STomer Tayar static int qed_pglueb_rbc_attn_cb(struct qed_hwfn *p_hwfn) 345666db486STomer Tayar { 346eb61c2d6SAlexander Lobakin return qed_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_dpc_ptt, false); 347666db486STomer Tayar } 348666db486STomer Tayar 3492ec276d5SIgor Russkikh static int qed_fw_assertion(struct qed_hwfn *p_hwfn) 3502ec276d5SIgor Russkikh { 3512ec276d5SIgor Russkikh qed_hw_err_notify(p_hwfn, p_hwfn->p_dpc_ptt, QED_HW_ERR_FW_ASSERT, 3522ec276d5SIgor Russkikh "FW assertion!\n"); 3532ec276d5SIgor Russkikh 3542ec276d5SIgor Russkikh return -EINVAL; 3552ec276d5SIgor Russkikh } 3562ec276d5SIgor Russkikh 357936c7ba4SIgor Russkikh static int qed_general_attention_35(struct qed_hwfn *p_hwfn) 358936c7ba4SIgor Russkikh { 359936c7ba4SIgor Russkikh DP_INFO(p_hwfn, "General attention 35!\n"); 360936c7ba4SIgor Russkikh 361936c7ba4SIgor Russkikh return 0; 362936c7ba4SIgor Russkikh } 363936c7ba4SIgor Russkikh 364b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_REASON_MASK (0xfffff) 365b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_OPAQUE_MASK (0xffff) 366a1b469b8SAriel Elior #define QED_DORQ_ATTENTION_OPAQUE_SHIFT (0x0) 367b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_SIZE_MASK (0x7f) 368b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_SIZE_SHIFT (16) 369a1b469b8SAriel Elior 370a1b469b8SAriel Elior #define QED_DB_REC_COUNT 1000 371a1b469b8SAriel Elior #define QED_DB_REC_INTERVAL 100 372a1b469b8SAriel Elior 373a1b469b8SAriel Elior static int qed_db_rec_flush_queue(struct qed_hwfn *p_hwfn, 374a1b469b8SAriel Elior struct qed_ptt *p_ptt) 375a1b469b8SAriel Elior { 376a1b469b8SAriel Elior u32 count = QED_DB_REC_COUNT; 377a1b469b8SAriel Elior u32 usage = 1; 378a1b469b8SAriel Elior 3790d72c2acSDenis Bolotin /* Flush any pending (e)dpms as they may never arrive */ 3800d72c2acSDenis Bolotin qed_wr(p_hwfn, p_ptt, DORQ_REG_DPM_FORCE_ABORT, 0x1); 3810d72c2acSDenis Bolotin 382a1b469b8SAriel Elior /* wait for usage to zero or count to run out. This is necessary since 383a1b469b8SAriel Elior * EDPM doorbell transactions can take multiple 64b cycles, and as such 384a1b469b8SAriel Elior * can "split" over the pci. Possibly, the doorbell drop can happen with 385a1b469b8SAriel Elior * half an EDPM in the queue and other half dropped. Another EDPM 386a1b469b8SAriel Elior * doorbell to the same address (from doorbell recovery mechanism or 387a1b469b8SAriel Elior * from the doorbelling entity) could have first half dropped and second 388a1b469b8SAriel Elior * half interpreted as continuation of the first. To prevent such 389a1b469b8SAriel Elior * malformed doorbells from reaching the device, flush the queue before 390a1b469b8SAriel Elior * releasing the overflow sticky indication. 391a1b469b8SAriel Elior */ 392a1b469b8SAriel Elior while (count-- && usage) { 393a1b469b8SAriel Elior usage = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_USAGE_CNT); 394a1b469b8SAriel Elior udelay(QED_DB_REC_INTERVAL); 395a1b469b8SAriel Elior } 396a1b469b8SAriel Elior 397a1b469b8SAriel Elior /* should have been depleted by now */ 398a1b469b8SAriel Elior if (usage) { 399a1b469b8SAriel Elior DP_NOTICE(p_hwfn->cdev, 400a1b469b8SAriel Elior "DB recovery: doorbell usage failed to zero after %d usec. usage was %x\n", 401a1b469b8SAriel Elior QED_DB_REC_INTERVAL * QED_DB_REC_COUNT, usage); 402a1b469b8SAriel Elior return -EBUSY; 403a1b469b8SAriel Elior } 404a1b469b8SAriel Elior 405a1b469b8SAriel Elior return 0; 406a1b469b8SAriel Elior } 407a1b469b8SAriel Elior 408a1b469b8SAriel Elior int qed_db_rec_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 409a1b469b8SAriel Elior { 4100d72c2acSDenis Bolotin u32 attn_ovfl, cur_ovfl; 411a1b469b8SAriel Elior int rc; 412a1b469b8SAriel Elior 4130d72c2acSDenis Bolotin attn_ovfl = test_and_clear_bit(QED_OVERFLOW_BIT, 4140d72c2acSDenis Bolotin &p_hwfn->db_recovery_info.overflow); 4150d72c2acSDenis Bolotin cur_ovfl = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY); 4160d72c2acSDenis Bolotin if (!cur_ovfl && !attn_ovfl) 417a1b469b8SAriel Elior return 0; 418a1b469b8SAriel Elior 4190d72c2acSDenis Bolotin DP_NOTICE(p_hwfn, "PF Overflow sticky: attn %u current %u\n", 4200d72c2acSDenis Bolotin attn_ovfl, cur_ovfl); 4210d72c2acSDenis Bolotin 4220d72c2acSDenis Bolotin if (cur_ovfl && !p_hwfn->db_bar_no_edpm) { 423a1b469b8SAriel Elior rc = qed_db_rec_flush_queue(p_hwfn, p_ptt); 424a1b469b8SAriel Elior if (rc) 425a1b469b8SAriel Elior return rc; 426a1b469b8SAriel Elior } 427a1b469b8SAriel Elior 428a1b469b8SAriel Elior /* Release overflow sticky indication (stop silently dropping everything) */ 429a1b469b8SAriel Elior qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0); 430a1b469b8SAriel Elior 431a1b469b8SAriel Elior /* Repeat all last doorbells (doorbell drop recovery) */ 4329ac6bb14SDenis Bolotin qed_db_recovery_execute(p_hwfn); 433a1b469b8SAriel Elior 434a1b469b8SAriel Elior return 0; 435a1b469b8SAriel Elior } 436a1b469b8SAriel Elior 4370d72c2acSDenis Bolotin static void qed_dorq_attn_overflow(struct qed_hwfn *p_hwfn) 4380d72c2acSDenis Bolotin { 4390d72c2acSDenis Bolotin struct qed_ptt *p_ptt = p_hwfn->p_dpc_ptt; 4400d72c2acSDenis Bolotin u32 overflow; 4410d72c2acSDenis Bolotin int rc; 4420d72c2acSDenis Bolotin 4430d72c2acSDenis Bolotin overflow = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY); 4440d72c2acSDenis Bolotin if (!overflow) 4450d72c2acSDenis Bolotin goto out; 4460d72c2acSDenis Bolotin 4470d72c2acSDenis Bolotin /* Run PF doorbell recovery in next periodic handler */ 4480d72c2acSDenis Bolotin set_bit(QED_OVERFLOW_BIT, &p_hwfn->db_recovery_info.overflow); 4490d72c2acSDenis Bolotin 4500d72c2acSDenis Bolotin if (!p_hwfn->db_bar_no_edpm) { 4510d72c2acSDenis Bolotin rc = qed_db_rec_flush_queue(p_hwfn, p_ptt); 4520d72c2acSDenis Bolotin if (rc) 4530d72c2acSDenis Bolotin goto out; 4540d72c2acSDenis Bolotin } 4550d72c2acSDenis Bolotin 4560d72c2acSDenis Bolotin qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0); 4570d72c2acSDenis Bolotin out: 4580d72c2acSDenis Bolotin /* Schedule the handler even if overflow was not detected */ 4590d72c2acSDenis Bolotin qed_periodic_db_rec_start(p_hwfn); 4600d72c2acSDenis Bolotin } 4610d72c2acSDenis Bolotin 4620d72c2acSDenis Bolotin static int qed_dorq_attn_int_sts(struct qed_hwfn *p_hwfn) 463b4149dc7SYuval Mintz { 464a1b469b8SAriel Elior u32 int_sts, first_drop_reason, details, address, all_drops_reason; 465a1b469b8SAriel Elior struct qed_ptt *p_ptt = p_hwfn->p_dpc_ptt; 466a1b469b8SAriel Elior 467a1b469b8SAriel Elior /* int_sts may be zero since all PFs were interrupted for doorbell 468a1b469b8SAriel Elior * overflow but another one already handled it. Can abort here. If 469a1b469b8SAriel Elior * This PF also requires overflow recovery we will be interrupted again. 470a1b469b8SAriel Elior * The masked almost full indication may also be set. Ignoring. 471a1b469b8SAriel Elior */ 472d4476b8aSDenis Bolotin int_sts = qed_rd(p_hwfn, p_ptt, DORQ_REG_INT_STS); 473a1b469b8SAriel Elior if (!(int_sts & ~DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) 474a1b469b8SAriel Elior return 0; 475a1b469b8SAriel Elior 476d4476b8aSDenis Bolotin DP_NOTICE(p_hwfn->cdev, "DORQ attention. int_sts was %x\n", int_sts); 477d4476b8aSDenis Bolotin 478a1b469b8SAriel Elior /* check if db_drop or overflow happened */ 479a1b469b8SAriel Elior if (int_sts & (DORQ_REG_INT_STS_DB_DROP | 480a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR)) { 481a1b469b8SAriel Elior /* Obtain data about db drop/overflow */ 482a1b469b8SAriel Elior first_drop_reason = qed_rd(p_hwfn, p_ptt, 483a1b469b8SAriel Elior DORQ_REG_DB_DROP_REASON) & 484b4149dc7SYuval Mintz QED_DORQ_ATTENTION_REASON_MASK; 485a1b469b8SAriel Elior details = qed_rd(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS); 486a1b469b8SAriel Elior address = qed_rd(p_hwfn, p_ptt, 487a1b469b8SAriel Elior DORQ_REG_DB_DROP_DETAILS_ADDRESS); 488a1b469b8SAriel Elior all_drops_reason = qed_rd(p_hwfn, p_ptt, 489a1b469b8SAriel Elior DORQ_REG_DB_DROP_DETAILS_REASON); 490b4149dc7SYuval Mintz 491a1b469b8SAriel Elior /* Log info */ 492a1b469b8SAriel Elior DP_NOTICE(p_hwfn->cdev, 493a1b469b8SAriel Elior "Doorbell drop occurred\n" 494a1b469b8SAriel Elior "Address\t\t0x%08x\t(second BAR address)\n" 495a1b469b8SAriel Elior "FID\t\t0x%04x\t\t(Opaque FID)\n" 496a1b469b8SAriel Elior "Size\t\t0x%04x\t\t(in bytes)\n" 497a1b469b8SAriel Elior "1st drop reason\t0x%08x\t(details on first drop since last handling)\n" 498a1b469b8SAriel Elior "Sticky reasons\t0x%08x\t(all drop reasons since last handling)\n", 499a1b469b8SAriel Elior address, 500a1b469b8SAriel Elior GET_FIELD(details, QED_DORQ_ATTENTION_OPAQUE), 501b4149dc7SYuval Mintz GET_FIELD(details, QED_DORQ_ATTENTION_SIZE) * 4, 502a1b469b8SAriel Elior first_drop_reason, all_drops_reason); 503a1b469b8SAriel Elior 504a1b469b8SAriel Elior /* Clear the doorbell drop details and prepare for next drop */ 505a1b469b8SAriel Elior qed_wr(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS_REL, 0); 506a1b469b8SAriel Elior 507a1b469b8SAriel Elior /* Mark interrupt as handled (note: even if drop was due to a different 508a1b469b8SAriel Elior * reason than overflow we mark as handled) 509a1b469b8SAriel Elior */ 510a1b469b8SAriel Elior qed_wr(p_hwfn, 511a1b469b8SAriel Elior p_ptt, 512a1b469b8SAriel Elior DORQ_REG_INT_STS_WR, 513a1b469b8SAriel Elior DORQ_REG_INT_STS_DB_DROP | 514a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR); 515a1b469b8SAriel Elior 516a1b469b8SAriel Elior /* If there are no indications other than drop indications, success */ 517a1b469b8SAriel Elior if ((int_sts & ~(DORQ_REG_INT_STS_DB_DROP | 518a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR | 519a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) == 0) 520a1b469b8SAriel Elior return 0; 521b4149dc7SYuval Mintz } 522b4149dc7SYuval Mintz 523a1b469b8SAriel Elior /* Some other indication was present - non recoverable */ 524a1b469b8SAriel Elior DP_INFO(p_hwfn, "DORQ fatal attention\n"); 525a1b469b8SAriel Elior 526b4149dc7SYuval Mintz return -EINVAL; 527b4149dc7SYuval Mintz } 528b4149dc7SYuval Mintz 5290d72c2acSDenis Bolotin static int qed_dorq_attn_cb(struct qed_hwfn *p_hwfn) 5300d72c2acSDenis Bolotin { 5310d72c2acSDenis Bolotin p_hwfn->db_recovery_info.dorq_attn = true; 5320d72c2acSDenis Bolotin qed_dorq_attn_overflow(p_hwfn); 5330d72c2acSDenis Bolotin 5340d72c2acSDenis Bolotin return qed_dorq_attn_int_sts(p_hwfn); 5350d72c2acSDenis Bolotin } 5360d72c2acSDenis Bolotin 537d4476b8aSDenis Bolotin static void qed_dorq_attn_handler(struct qed_hwfn *p_hwfn) 538d4476b8aSDenis Bolotin { 539d4476b8aSDenis Bolotin if (p_hwfn->db_recovery_info.dorq_attn) 540d4476b8aSDenis Bolotin goto out; 541d4476b8aSDenis Bolotin 542d4476b8aSDenis Bolotin /* Call DORQ callback if the attention was missed */ 543d4476b8aSDenis Bolotin qed_dorq_attn_cb(p_hwfn); 544d4476b8aSDenis Bolotin out: 545d4476b8aSDenis Bolotin p_hwfn->db_recovery_info.dorq_attn = false; 546d4476b8aSDenis Bolotin } 547d4476b8aSDenis Bolotin 548ba36f718SMintz, Yuval /* Instead of major changes to the data-structure, we have a some 'special' 549ba36f718SMintz, Yuval * identifiers for sources that changed meaning between adapters. 550ba36f718SMintz, Yuval */ 551ba36f718SMintz, Yuval enum aeu_invert_reg_special_type { 552ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_0, 553ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_1, 554ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_2, 555ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_3, 556ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_MAX, 557ba36f718SMintz, Yuval }; 558ba36f718SMintz, Yuval 559ba36f718SMintz, Yuval static struct aeu_invert_reg_bit 560ba36f718SMintz, Yuval aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = { 561ba36f718SMintz, Yuval {"CNIG port 0", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 562ba36f718SMintz, Yuval {"CNIG port 1", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 563ba36f718SMintz, Yuval {"CNIG port 2", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 564ba36f718SMintz, Yuval {"CNIG port 3", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 565ba36f718SMintz, Yuval }; 566ba36f718SMintz, Yuval 5670d956e8aSYuval Mintz /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */ 5680d956e8aSYuval Mintz static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = { 5690d956e8aSYuval Mintz { 5700d956e8aSYuval Mintz { /* After Invert 1 */ 5710d956e8aSYuval Mintz {"GPIO0 function%d", 572b4149dc7SYuval Mintz (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 5730d956e8aSYuval Mintz } 5740d956e8aSYuval Mintz }, 5750d956e8aSYuval Mintz 5760d956e8aSYuval Mintz { 5770d956e8aSYuval Mintz { /* After Invert 2 */ 578b4149dc7SYuval Mintz {"PGLUE config_space", ATTENTION_SINGLE, 579b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 580b4149dc7SYuval Mintz {"PGLUE misc_flr", ATTENTION_SINGLE, 581b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 582b4149dc7SYuval Mintz {"PGLUE B RBC", ATTENTION_PAR_INT, 583666db486STomer Tayar qed_pglueb_rbc_attn_cb, BLOCK_PGLUE_B}, 584b4149dc7SYuval Mintz {"PGLUE misc_mctp", ATTENTION_SINGLE, 585b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 586b4149dc7SYuval Mintz {"Flash event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 587b4149dc7SYuval Mintz {"SMB event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 588b4149dc7SYuval Mintz {"Main Power", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 5890d956e8aSYuval Mintz {"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) | 590ff38577aSYuval Mintz (1 << ATTENTION_OFFSET_SHIFT), 591b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 5920d956e8aSYuval Mintz {"PCIE glue/PXP VPD %d", 593b4149dc7SYuval Mintz (16 << ATTENTION_LENGTH_SHIFT), NULL, BLOCK_PGLCS}, 5940d956e8aSYuval Mintz } 5950d956e8aSYuval Mintz }, 5960d956e8aSYuval Mintz 5970d956e8aSYuval Mintz { 5980d956e8aSYuval Mintz { /* After Invert 3 */ 5990d956e8aSYuval Mintz {"General Attention %d", 600b4149dc7SYuval Mintz (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 6010d956e8aSYuval Mintz } 6020d956e8aSYuval Mintz }, 6030d956e8aSYuval Mintz 6040d956e8aSYuval Mintz { 6050d956e8aSYuval Mintz { /* After Invert 4 */ 606936c7ba4SIgor Russkikh {"General Attention 32", ATTENTION_SINGLE | 607936c7ba4SIgor Russkikh ATTENTION_CLEAR_ENABLE, qed_fw_assertion, 6082ec276d5SIgor Russkikh MAX_BLOCK_ID}, 6090d956e8aSYuval Mintz {"General Attention %d", 6100d956e8aSYuval Mintz (2 << ATTENTION_LENGTH_SHIFT) | 611b4149dc7SYuval Mintz (33 << ATTENTION_OFFSET_SHIFT), NULL, MAX_BLOCK_ID}, 612936c7ba4SIgor Russkikh {"General Attention 35", ATTENTION_SINGLE | 613936c7ba4SIgor Russkikh ATTENTION_CLEAR_ENABLE, qed_general_attention_35, 614936c7ba4SIgor Russkikh MAX_BLOCK_ID}, 615ba36f718SMintz, Yuval {"NWS Parity", 616ba36f718SMintz, Yuval ATTENTION_PAR | ATTENTION_BB_DIFFERENT | 617ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_0), 618ba36f718SMintz, Yuval NULL, BLOCK_NWS}, 619ba36f718SMintz, Yuval {"NWS Interrupt", 620ba36f718SMintz, Yuval ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT | 621ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_1), 622ba36f718SMintz, Yuval NULL, BLOCK_NWS}, 623ba36f718SMintz, Yuval {"NWM Parity", 624ba36f718SMintz, Yuval ATTENTION_PAR | ATTENTION_BB_DIFFERENT | 625ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_2), 626ba36f718SMintz, Yuval NULL, BLOCK_NWM}, 627ba36f718SMintz, Yuval {"NWM Interrupt", 628ba36f718SMintz, Yuval ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT | 629ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_3), 630ba36f718SMintz, Yuval NULL, BLOCK_NWM}, 631b4149dc7SYuval Mintz {"MCP CPU", ATTENTION_SINGLE, 632b4149dc7SYuval Mintz qed_mcp_attn_cb, MAX_BLOCK_ID}, 633b4149dc7SYuval Mintz {"MCP Watchdog timer", ATTENTION_SINGLE, 634b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 635b4149dc7SYuval Mintz {"MCP M2P", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 636ff38577aSYuval Mintz {"AVS stop status ready", ATTENTION_SINGLE, 637b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 638b4149dc7SYuval Mintz {"MSTAT", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 639b4149dc7SYuval Mintz {"MSTAT per-path", ATTENTION_PAR_INT, 640b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 641ff38577aSYuval Mintz {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), 642b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 643b4149dc7SYuval Mintz {"NIG", ATTENTION_PAR_INT, NULL, BLOCK_NIG}, 644b4149dc7SYuval Mintz {"BMB/OPTE/MCP", ATTENTION_PAR_INT, NULL, BLOCK_BMB}, 645b4149dc7SYuval Mintz {"BTB", ATTENTION_PAR_INT, NULL, BLOCK_BTB}, 646b4149dc7SYuval Mintz {"BRB", ATTENTION_PAR_INT, NULL, BLOCK_BRB}, 647b4149dc7SYuval Mintz {"PRS", ATTENTION_PAR_INT, NULL, BLOCK_PRS}, 6480d956e8aSYuval Mintz } 6490d956e8aSYuval Mintz }, 6500d956e8aSYuval Mintz 6510d956e8aSYuval Mintz { 6520d956e8aSYuval Mintz { /* After Invert 5 */ 653b4149dc7SYuval Mintz {"SRC", ATTENTION_PAR_INT, NULL, BLOCK_SRC}, 654b4149dc7SYuval Mintz {"PB Client1", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB1}, 655b4149dc7SYuval Mintz {"PB Client2", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB2}, 656b4149dc7SYuval Mintz {"RPB", ATTENTION_PAR_INT, NULL, BLOCK_RPB}, 657b4149dc7SYuval Mintz {"PBF", ATTENTION_PAR_INT, NULL, BLOCK_PBF}, 658b4149dc7SYuval Mintz {"QM", ATTENTION_PAR_INT, NULL, BLOCK_QM}, 659b4149dc7SYuval Mintz {"TM", ATTENTION_PAR_INT, NULL, BLOCK_TM}, 660b4149dc7SYuval Mintz {"MCM", ATTENTION_PAR_INT, NULL, BLOCK_MCM}, 661b4149dc7SYuval Mintz {"MSDM", ATTENTION_PAR_INT, NULL, BLOCK_MSDM}, 662b4149dc7SYuval Mintz {"MSEM", ATTENTION_PAR_INT, NULL, BLOCK_MSEM}, 663b4149dc7SYuval Mintz {"PCM", ATTENTION_PAR_INT, NULL, BLOCK_PCM}, 664b4149dc7SYuval Mintz {"PSDM", ATTENTION_PAR_INT, NULL, BLOCK_PSDM}, 665b4149dc7SYuval Mintz {"PSEM", ATTENTION_PAR_INT, NULL, BLOCK_PSEM}, 666b4149dc7SYuval Mintz {"TCM", ATTENTION_PAR_INT, NULL, BLOCK_TCM}, 667b4149dc7SYuval Mintz {"TSDM", ATTENTION_PAR_INT, NULL, BLOCK_TSDM}, 668b4149dc7SYuval Mintz {"TSEM", ATTENTION_PAR_INT, NULL, BLOCK_TSEM}, 6690d956e8aSYuval Mintz } 6700d956e8aSYuval Mintz }, 6710d956e8aSYuval Mintz 6720d956e8aSYuval Mintz { 6730d956e8aSYuval Mintz { /* After Invert 6 */ 674b4149dc7SYuval Mintz {"UCM", ATTENTION_PAR_INT, NULL, BLOCK_UCM}, 675b4149dc7SYuval Mintz {"USDM", ATTENTION_PAR_INT, NULL, BLOCK_USDM}, 676b4149dc7SYuval Mintz {"USEM", ATTENTION_PAR_INT, NULL, BLOCK_USEM}, 677b4149dc7SYuval Mintz {"XCM", ATTENTION_PAR_INT, NULL, BLOCK_XCM}, 678b4149dc7SYuval Mintz {"XSDM", ATTENTION_PAR_INT, NULL, BLOCK_XSDM}, 679b4149dc7SYuval Mintz {"XSEM", ATTENTION_PAR_INT, NULL, BLOCK_XSEM}, 680b4149dc7SYuval Mintz {"YCM", ATTENTION_PAR_INT, NULL, BLOCK_YCM}, 681b4149dc7SYuval Mintz {"YSDM", ATTENTION_PAR_INT, NULL, BLOCK_YSDM}, 682b4149dc7SYuval Mintz {"YSEM", ATTENTION_PAR_INT, NULL, BLOCK_YSEM}, 683b4149dc7SYuval Mintz {"XYLD", ATTENTION_PAR_INT, NULL, BLOCK_XYLD}, 684b4149dc7SYuval Mintz {"TMLD", ATTENTION_PAR_INT, NULL, BLOCK_TMLD}, 685b4149dc7SYuval Mintz {"MYLD", ATTENTION_PAR_INT, NULL, BLOCK_MULD}, 686b4149dc7SYuval Mintz {"YULD", ATTENTION_PAR_INT, NULL, BLOCK_YULD}, 687b4149dc7SYuval Mintz {"DORQ", ATTENTION_PAR_INT, 688b4149dc7SYuval Mintz qed_dorq_attn_cb, BLOCK_DORQ}, 689b4149dc7SYuval Mintz {"DBG", ATTENTION_PAR_INT, NULL, BLOCK_DBG}, 690b4149dc7SYuval Mintz {"IPC", ATTENTION_PAR_INT, NULL, BLOCK_IPC}, 6910d956e8aSYuval Mintz } 6920d956e8aSYuval Mintz }, 6930d956e8aSYuval Mintz 6940d956e8aSYuval Mintz { 6950d956e8aSYuval Mintz { /* After Invert 7 */ 696b4149dc7SYuval Mintz {"CCFC", ATTENTION_PAR_INT, NULL, BLOCK_CCFC}, 697b4149dc7SYuval Mintz {"CDU", ATTENTION_PAR_INT, NULL, BLOCK_CDU}, 698b4149dc7SYuval Mintz {"DMAE", ATTENTION_PAR_INT, NULL, BLOCK_DMAE}, 699b4149dc7SYuval Mintz {"IGU", ATTENTION_PAR_INT, NULL, BLOCK_IGU}, 700b4149dc7SYuval Mintz {"ATC", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 701b4149dc7SYuval Mintz {"CAU", ATTENTION_PAR_INT, NULL, BLOCK_CAU}, 702b4149dc7SYuval Mintz {"PTU", ATTENTION_PAR_INT, NULL, BLOCK_PTU}, 703b4149dc7SYuval Mintz {"PRM", ATTENTION_PAR_INT, NULL, BLOCK_PRM}, 704b4149dc7SYuval Mintz {"TCFC", ATTENTION_PAR_INT, NULL, BLOCK_TCFC}, 705b4149dc7SYuval Mintz {"RDIF", ATTENTION_PAR_INT, NULL, BLOCK_RDIF}, 706b4149dc7SYuval Mintz {"TDIF", ATTENTION_PAR_INT, NULL, BLOCK_TDIF}, 707b4149dc7SYuval Mintz {"RSS", ATTENTION_PAR_INT, NULL, BLOCK_RSS}, 708b4149dc7SYuval Mintz {"MISC", ATTENTION_PAR_INT, NULL, BLOCK_MISC}, 709b4149dc7SYuval Mintz {"MISCS", ATTENTION_PAR_INT, NULL, BLOCK_MISCS}, 710b4149dc7SYuval Mintz {"PCIE", ATTENTION_PAR, NULL, BLOCK_PCIE}, 711b4149dc7SYuval Mintz {"Vaux PCI core", ATTENTION_SINGLE, NULL, BLOCK_PGLCS}, 712b4149dc7SYuval Mintz {"PSWRQ", ATTENTION_PAR_INT, NULL, BLOCK_PSWRQ}, 7130d956e8aSYuval Mintz } 7140d956e8aSYuval Mintz }, 7150d956e8aSYuval Mintz 7160d956e8aSYuval Mintz { 7170d956e8aSYuval Mintz { /* After Invert 8 */ 718b4149dc7SYuval Mintz {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, 719b4149dc7SYuval Mintz NULL, BLOCK_PSWRQ2}, 720b4149dc7SYuval Mintz {"PSWWR", ATTENTION_PAR_INT, NULL, BLOCK_PSWWR}, 721b4149dc7SYuval Mintz {"PSWWR (pci_clk)", ATTENTION_PAR_INT, 722b4149dc7SYuval Mintz NULL, BLOCK_PSWWR2}, 723b4149dc7SYuval Mintz {"PSWRD", ATTENTION_PAR_INT, NULL, BLOCK_PSWRD}, 724b4149dc7SYuval Mintz {"PSWRD (pci_clk)", ATTENTION_PAR_INT, 725b4149dc7SYuval Mintz NULL, BLOCK_PSWRD2}, 726b4149dc7SYuval Mintz {"PSWHST", ATTENTION_PAR_INT, 727b4149dc7SYuval Mintz qed_pswhst_attn_cb, BLOCK_PSWHST}, 728b4149dc7SYuval Mintz {"PSWHST (pci_clk)", ATTENTION_PAR_INT, 729b4149dc7SYuval Mintz NULL, BLOCK_PSWHST2}, 730b4149dc7SYuval Mintz {"GRC", ATTENTION_PAR_INT, 731b4149dc7SYuval Mintz qed_grc_attn_cb, BLOCK_GRC}, 732b4149dc7SYuval Mintz {"CPMU", ATTENTION_PAR_INT, NULL, BLOCK_CPMU}, 733b4149dc7SYuval Mintz {"NCSI", ATTENTION_PAR_INT, NULL, BLOCK_NCSI}, 734b4149dc7SYuval Mintz {"MSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 735b4149dc7SYuval Mintz {"PSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 736b4149dc7SYuval Mintz {"TSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 737b4149dc7SYuval Mintz {"USEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 738b4149dc7SYuval Mintz {"XSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 739b4149dc7SYuval Mintz {"YSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 740b4149dc7SYuval Mintz {"pxp_misc_mps", ATTENTION_PAR, NULL, BLOCK_PGLCS}, 741ff38577aSYuval Mintz {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, 742b4149dc7SYuval Mintz NULL, BLOCK_PGLCS}, 743b4149dc7SYuval Mintz {"PERST_B assertion", ATTENTION_SINGLE, 744b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 745ff38577aSYuval Mintz {"PERST_B deassertion", ATTENTION_SINGLE, 746b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 747ff38577aSYuval Mintz {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), 748b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 7490d956e8aSYuval Mintz } 7500d956e8aSYuval Mintz }, 7510d956e8aSYuval Mintz 7520d956e8aSYuval Mintz { 7530d956e8aSYuval Mintz { /* After Invert 9 */ 754b4149dc7SYuval Mintz {"MCP Latched memory", ATTENTION_PAR, 755b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 756ff38577aSYuval Mintz {"MCP Latched scratchpad cache", ATTENTION_SINGLE, 757b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 758b4149dc7SYuval Mintz {"MCP Latched ump_tx", ATTENTION_PAR, 759b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 760ff38577aSYuval Mintz {"MCP Latched scratchpad", ATTENTION_PAR, 761b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 762ff38577aSYuval Mintz {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT), 763b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 7640d956e8aSYuval Mintz } 7650d956e8aSYuval Mintz }, 7660d956e8aSYuval Mintz }; 7670d956e8aSYuval Mintz 768ba36f718SMintz, Yuval static struct aeu_invert_reg_bit * 769ba36f718SMintz, Yuval qed_int_aeu_translate(struct qed_hwfn *p_hwfn, 770ba36f718SMintz, Yuval struct aeu_invert_reg_bit *p_bit) 771ba36f718SMintz, Yuval { 772ba36f718SMintz, Yuval if (!QED_IS_BB(p_hwfn->cdev)) 773ba36f718SMintz, Yuval return p_bit; 774ba36f718SMintz, Yuval 775ba36f718SMintz, Yuval if (!(p_bit->flags & ATTENTION_BB_DIFFERENT)) 776ba36f718SMintz, Yuval return p_bit; 777ba36f718SMintz, Yuval 778ba36f718SMintz, Yuval return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >> 779ba36f718SMintz, Yuval ATTENTION_BB_SHIFT]; 780ba36f718SMintz, Yuval } 781ba36f718SMintz, Yuval 782ba36f718SMintz, Yuval static bool qed_int_is_parity_flag(struct qed_hwfn *p_hwfn, 783ba36f718SMintz, Yuval struct aeu_invert_reg_bit *p_bit) 784ba36f718SMintz, Yuval { 785ba36f718SMintz, Yuval return !!(qed_int_aeu_translate(p_hwfn, p_bit)->flags & 786ba36f718SMintz, Yuval ATTENTION_PARITY); 787ba36f718SMintz, Yuval } 788ba36f718SMintz, Yuval 789cc875c2eSYuval Mintz #define ATTN_STATE_BITS (0xfff) 790cc875c2eSYuval Mintz #define ATTN_BITS_MASKABLE (0x3ff) 791cc875c2eSYuval Mintz struct qed_sb_attn_info { 792cc875c2eSYuval Mintz /* Virtual & Physical address of the SB */ 793cc875c2eSYuval Mintz struct atten_status_block *sb_attn; 794cc875c2eSYuval Mintz dma_addr_t sb_phys; 795cc875c2eSYuval Mintz 796cc875c2eSYuval Mintz /* Last seen running index */ 797cc875c2eSYuval Mintz u16 index; 798cc875c2eSYuval Mintz 7990d956e8aSYuval Mintz /* A mask of the AEU bits resulting in a parity error */ 8000d956e8aSYuval Mintz u32 parity_mask[NUM_ATTN_REGS]; 8010d956e8aSYuval Mintz 8020d956e8aSYuval Mintz /* A pointer to the attention description structure */ 8030d956e8aSYuval Mintz struct aeu_invert_reg *p_aeu_desc; 8040d956e8aSYuval Mintz 805cc875c2eSYuval Mintz /* Previously asserted attentions, which are still unasserted */ 806cc875c2eSYuval Mintz u16 known_attn; 807cc875c2eSYuval Mintz 808cc875c2eSYuval Mintz /* Cleanup address for the link's general hw attention */ 809cc875c2eSYuval Mintz u32 mfw_attn_addr; 810cc875c2eSYuval Mintz }; 811cc875c2eSYuval Mintz 812cc875c2eSYuval Mintz static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn, 813cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb_desc) 814cc875c2eSYuval Mintz { 8151a635e48SYuval Mintz u16 rc = 0, index; 816cc875c2eSYuval Mintz 817cc875c2eSYuval Mintz index = le16_to_cpu(p_sb_desc->sb_attn->sb_index); 818cc875c2eSYuval Mintz if (p_sb_desc->index != index) { 819cc875c2eSYuval Mintz p_sb_desc->index = index; 820cc875c2eSYuval Mintz rc = QED_SB_ATT_IDX; 821cc875c2eSYuval Mintz } 822cc875c2eSYuval Mintz 823cc875c2eSYuval Mintz return rc; 824cc875c2eSYuval Mintz } 825cc875c2eSYuval Mintz 826cc875c2eSYuval Mintz /** 82771e11a3fSAlexander Lobakin * qed_int_assertion() - Handle asserted attention bits. 828cc875c2eSYuval Mintz * 82971e11a3fSAlexander Lobakin * @p_hwfn: HW device data. 83071e11a3fSAlexander Lobakin * @asserted_bits: Newly asserted bits. 83171e11a3fSAlexander Lobakin * 83271e11a3fSAlexander Lobakin * Return: Zero value. 833cc875c2eSYuval Mintz */ 8341a635e48SYuval Mintz static int qed_int_assertion(struct qed_hwfn *p_hwfn, u16 asserted_bits) 835cc875c2eSYuval Mintz { 836cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 837cc875c2eSYuval Mintz u32 igu_mask; 838cc875c2eSYuval Mintz 839cc875c2eSYuval Mintz /* Mask the source of the attention in the IGU */ 8401a635e48SYuval Mintz igu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); 841cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n", 842cc875c2eSYuval Mintz igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE)); 843cc875c2eSYuval Mintz igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE); 844cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask); 845cc875c2eSYuval Mintz 846cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 847cc875c2eSYuval Mintz "inner known ATTN state: 0x%04x --> 0x%04x\n", 848cc875c2eSYuval Mintz sb_attn_sw->known_attn, 849cc875c2eSYuval Mintz sb_attn_sw->known_attn | asserted_bits); 850cc875c2eSYuval Mintz sb_attn_sw->known_attn |= asserted_bits; 851cc875c2eSYuval Mintz 852cc875c2eSYuval Mintz /* Handle MCP events */ 853cc875c2eSYuval Mintz if (asserted_bits & 0x100) { 854cc875c2eSYuval Mintz qed_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt); 855cc875c2eSYuval Mintz /* Clean the MCP attention */ 856cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 857cc875c2eSYuval Mintz sb_attn_sw->mfw_attn_addr, 0); 858cc875c2eSYuval Mintz } 859cc875c2eSYuval Mintz 860cc875c2eSYuval Mintz DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 861cc875c2eSYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 862cc875c2eSYuval Mintz ((IGU_CMD_ATTN_BIT_SET_UPPER - 863cc875c2eSYuval Mintz IGU_CMD_INT_ACK_BASE) << 3), 864cc875c2eSYuval Mintz (u32)asserted_bits); 865cc875c2eSYuval Mintz 866cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "set cmd IGU: 0x%04x\n", 867cc875c2eSYuval Mintz asserted_bits); 868cc875c2eSYuval Mintz 869cc875c2eSYuval Mintz return 0; 870cc875c2eSYuval Mintz } 871cc875c2eSYuval Mintz 8720ebbd1c8SMintz, Yuval static void qed_int_attn_print(struct qed_hwfn *p_hwfn, 8730ebbd1c8SMintz, Yuval enum block_id id, 8740ebbd1c8SMintz, Yuval enum dbg_attn_type type, bool b_clear) 875ff38577aSYuval Mintz { 8760ebbd1c8SMintz, Yuval struct dbg_attn_block_result attn_results; 8770ebbd1c8SMintz, Yuval enum dbg_status status; 878ff38577aSYuval Mintz 8790ebbd1c8SMintz, Yuval memset(&attn_results, 0, sizeof(attn_results)); 880ff38577aSYuval Mintz 8810ebbd1c8SMintz, Yuval status = qed_dbg_read_attn(p_hwfn, p_hwfn->p_dpc_ptt, id, type, 8820ebbd1c8SMintz, Yuval b_clear, &attn_results); 8830ebbd1c8SMintz, Yuval if (status != DBG_STATUS_OK) 884ff38577aSYuval Mintz DP_NOTICE(p_hwfn, 8850ebbd1c8SMintz, Yuval "Failed to parse attention information [status: %s]\n", 8860ebbd1c8SMintz, Yuval qed_dbg_get_status_str(status)); 8870ebbd1c8SMintz, Yuval else 8880ebbd1c8SMintz, Yuval qed_dbg_parse_attn(p_hwfn, &attn_results); 889ff38577aSYuval Mintz } 890ff38577aSYuval Mintz 891cc875c2eSYuval Mintz /** 89271e11a3fSAlexander Lobakin * qed_int_deassertion_aeu_bit() - Handles the effects of a single 89371e11a3fSAlexander Lobakin * cause of the attention. 8940d956e8aSYuval Mintz * 89571e11a3fSAlexander Lobakin * @p_hwfn: HW device data. 89671e11a3fSAlexander Lobakin * @p_aeu: Descriptor of an AEU bit which caused the attention. 89771e11a3fSAlexander Lobakin * @aeu_en_reg: Register offset of the AEU enable reg. which configured 8980d956e8aSYuval Mintz * this bit to this group. 89971e11a3fSAlexander Lobakin * @p_bit_name: AEU bit description for logging purposes. 90071e11a3fSAlexander Lobakin * @bitmask: Index of this bit in the aeu_en_reg. 9010d956e8aSYuval Mintz * 90271e11a3fSAlexander Lobakin * Return: Zero on success, negative errno otherwise. 9030d956e8aSYuval Mintz */ 9040d956e8aSYuval Mintz static int 9050d956e8aSYuval Mintz qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn, 9060d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_aeu, 9070d956e8aSYuval Mintz u32 aeu_en_reg, 9086010179dSMintz, Yuval const char *p_bit_name, u32 bitmask) 9090d956e8aSYuval Mintz { 9100ebbd1c8SMintz, Yuval bool b_fatal = false; 9110d956e8aSYuval Mintz int rc = -EINVAL; 912b4149dc7SYuval Mintz u32 val; 9130d956e8aSYuval Mintz 9140d956e8aSYuval Mintz DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n", 9156010179dSMintz, Yuval p_bit_name, bitmask); 9160d956e8aSYuval Mintz 917b4149dc7SYuval Mintz /* Call callback before clearing the interrupt status */ 918b4149dc7SYuval Mintz if (p_aeu->cb) { 919b4149dc7SYuval Mintz DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n", 9206010179dSMintz, Yuval p_bit_name); 921b4149dc7SYuval Mintz rc = p_aeu->cb(p_hwfn); 922b4149dc7SYuval Mintz } 923b4149dc7SYuval Mintz 9240ebbd1c8SMintz, Yuval if (rc) 9250ebbd1c8SMintz, Yuval b_fatal = true; 926ff38577aSYuval Mintz 9270ebbd1c8SMintz, Yuval /* Print HW block interrupt registers */ 9280ebbd1c8SMintz, Yuval if (p_aeu->block_index != MAX_BLOCK_ID) 9290ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, p_aeu->block_index, 9300ebbd1c8SMintz, Yuval ATTN_TYPE_INTERRUPT, !b_fatal); 931ff38577aSYuval Mintz 9322ec276d5SIgor Russkikh /* Reach assertion if attention is fatal */ 9332ec276d5SIgor Russkikh if (b_fatal) 9342ec276d5SIgor Russkikh qed_hw_err_notify(p_hwfn, p_hwfn->p_dpc_ptt, QED_HW_ERR_HW_ATTN, 9352ec276d5SIgor Russkikh "`%s': Fatal attention\n", 9362ec276d5SIgor Russkikh p_bit_name); 9372ec276d5SIgor Russkikh else /* If the attention is benign, no need to prevent it */ 938b4149dc7SYuval Mintz goto out; 939b4149dc7SYuval Mintz 9400d956e8aSYuval Mintz /* Prevent this Attention from being asserted in the future */ 9410d956e8aSYuval Mintz val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 942b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & ~bitmask)); 9430d956e8aSYuval Mintz DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n", 9446010179dSMintz, Yuval p_bit_name); 9450d956e8aSYuval Mintz 946b4149dc7SYuval Mintz out: 9470d956e8aSYuval Mintz return rc; 9480d956e8aSYuval Mintz } 9490d956e8aSYuval Mintz 950ff38577aSYuval Mintz /** 95171e11a3fSAlexander Lobakin * qed_int_deassertion_parity() - Handle a single parity AEU source. 952ff38577aSYuval Mintz * 95371e11a3fSAlexander Lobakin * @p_hwfn: HW device data. 95471e11a3fSAlexander Lobakin * @p_aeu: Descriptor of an AEU bit which caused the parity. 95571e11a3fSAlexander Lobakin * @aeu_en_reg: Address of the AEU enable register. 95671e11a3fSAlexander Lobakin * @bit_index: Index (0-31) of an AEU bit. 957ff38577aSYuval Mintz */ 958ff38577aSYuval Mintz static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn, 959ff38577aSYuval Mintz struct aeu_invert_reg_bit *p_aeu, 9609790c35eSMintz, Yuval u32 aeu_en_reg, u8 bit_index) 961ff38577aSYuval Mintz { 9629790c35eSMintz, Yuval u32 block_id = p_aeu->block_index, mask, val; 963ff38577aSYuval Mintz 9649790c35eSMintz, Yuval DP_NOTICE(p_hwfn->cdev, 9659790c35eSMintz, Yuval "%s parity attention is set [address 0x%08x, bit %d]\n", 9669790c35eSMintz, Yuval p_aeu->bit_name, aeu_en_reg, bit_index); 967ff38577aSYuval Mintz 968ff38577aSYuval Mintz if (block_id != MAX_BLOCK_ID) { 9690ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, block_id, ATTN_TYPE_PARITY, false); 970ff38577aSYuval Mintz 971ff38577aSYuval Mintz /* In BB, there's a single parity bit for several blocks */ 972ff38577aSYuval Mintz if (block_id == BLOCK_BTB) { 9730ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, BLOCK_OPTE, 9740ebbd1c8SMintz, Yuval ATTN_TYPE_PARITY, false); 9750ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, BLOCK_MCP, 9760ebbd1c8SMintz, Yuval ATTN_TYPE_PARITY, false); 977ff38577aSYuval Mintz } 978ff38577aSYuval Mintz } 9799790c35eSMintz, Yuval 9809790c35eSMintz, Yuval /* Prevent this parity error from being re-asserted */ 9819790c35eSMintz, Yuval mask = ~BIT(bit_index); 9829790c35eSMintz, Yuval val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 9839790c35eSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask); 9849790c35eSMintz, Yuval DP_INFO(p_hwfn, "`%s' - Disabled future parity errors\n", 9859790c35eSMintz, Yuval p_aeu->bit_name); 986ff38577aSYuval Mintz } 987ff38577aSYuval Mintz 9880d956e8aSYuval Mintz /** 98971e11a3fSAlexander Lobakin * qed_int_deassertion() - Handle deassertion of previously asserted 99071e11a3fSAlexander Lobakin * attentions. 991cc875c2eSYuval Mintz * 99271e11a3fSAlexander Lobakin * @p_hwfn: HW device data. 99371e11a3fSAlexander Lobakin * @deasserted_bits: newly deasserted bits. 994cc875c2eSYuval Mintz * 99571e11a3fSAlexander Lobakin * Return: Zero value. 996cc875c2eSYuval Mintz */ 997cc875c2eSYuval Mintz static int qed_int_deassertion(struct qed_hwfn *p_hwfn, 998cc875c2eSYuval Mintz u16 deasserted_bits) 999cc875c2eSYuval Mintz { 1000cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 10019790c35eSMintz, Yuval u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask, aeu_en, en; 10020d956e8aSYuval Mintz u8 i, j, k, bit_idx; 10030d956e8aSYuval Mintz int rc = 0; 1004cc875c2eSYuval Mintz 10050d956e8aSYuval Mintz /* Read the attention registers in the AEU */ 10060d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 10070d956e8aSYuval Mintz aeu_inv_arr[i] = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 10080d956e8aSYuval Mintz MISC_REG_AEU_AFTER_INVERT_1_IGU + 10090d956e8aSYuval Mintz i * 0x4); 10100d956e8aSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 10110d956e8aSYuval Mintz "Deasserted bits [%d]: %08x\n", 10120d956e8aSYuval Mintz i, aeu_inv_arr[i]); 10130d956e8aSYuval Mintz } 10140d956e8aSYuval Mintz 10150d956e8aSYuval Mintz /* Find parity attentions first */ 10160d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 10170d956e8aSYuval Mintz struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i]; 10180d956e8aSYuval Mintz u32 parities; 10190d956e8aSYuval Mintz 10209790c35eSMintz, Yuval aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + i * sizeof(u32); 10219790c35eSMintz, Yuval en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 10229790c35eSMintz, Yuval 10230d956e8aSYuval Mintz /* Skip register in which no parity bit is currently set */ 10240d956e8aSYuval Mintz parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en; 10250d956e8aSYuval Mintz if (!parities) 10260d956e8aSYuval Mintz continue; 10270d956e8aSYuval Mintz 10280d956e8aSYuval Mintz for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 10290d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j]; 10300d956e8aSYuval Mintz 1031ba36f718SMintz, Yuval if (qed_int_is_parity_flag(p_hwfn, p_bit) && 10321a635e48SYuval Mintz !!(parities & BIT(bit_idx))) 1033ff38577aSYuval Mintz qed_int_deassertion_parity(p_hwfn, p_bit, 10349790c35eSMintz, Yuval aeu_en, bit_idx); 10350d956e8aSYuval Mintz 10360d956e8aSYuval Mintz bit_idx += ATTENTION_LENGTH(p_bit->flags); 10370d956e8aSYuval Mintz } 10380d956e8aSYuval Mintz } 10390d956e8aSYuval Mintz 10400d956e8aSYuval Mintz /* Find non-parity cause for attention and act */ 10410d956e8aSYuval Mintz for (k = 0; k < MAX_ATTN_GRPS; k++) { 10420d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_aeu; 10430d956e8aSYuval Mintz 10440d956e8aSYuval Mintz /* Handle only groups whose attention is currently deasserted */ 10450d956e8aSYuval Mintz if (!(deasserted_bits & (1 << k))) 10460d956e8aSYuval Mintz continue; 10470d956e8aSYuval Mintz 10480d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 10499790c35eSMintz, Yuval u32 bits; 10509790c35eSMintz, Yuval 10519790c35eSMintz, Yuval aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + 10520d956e8aSYuval Mintz i * sizeof(u32) + 10530d956e8aSYuval Mintz k * sizeof(u32) * NUM_ATTN_REGS; 10540d956e8aSYuval Mintz 10550d956e8aSYuval Mintz en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 10560d956e8aSYuval Mintz bits = aeu_inv_arr[i] & en; 10570d956e8aSYuval Mintz 10580d956e8aSYuval Mintz /* Skip if no bit from this group is currently set */ 10590d956e8aSYuval Mintz if (!bits) 10600d956e8aSYuval Mintz continue; 10610d956e8aSYuval Mintz 10620d956e8aSYuval Mintz /* Find all set bits from current register which belong 10630d956e8aSYuval Mintz * to current group, making them responsible for the 10640d956e8aSYuval Mintz * previous assertion. 10650d956e8aSYuval Mintz */ 10660d956e8aSYuval Mintz for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 10676010179dSMintz, Yuval long unsigned int bitmask; 10680d956e8aSYuval Mintz u8 bit, bit_len; 10690d956e8aSYuval Mintz 10700d956e8aSYuval Mintz p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j]; 1071ba36f718SMintz, Yuval p_aeu = qed_int_aeu_translate(p_hwfn, p_aeu); 10720d956e8aSYuval Mintz 10730d956e8aSYuval Mintz bit = bit_idx; 10740d956e8aSYuval Mintz bit_len = ATTENTION_LENGTH(p_aeu->flags); 1075ba36f718SMintz, Yuval if (qed_int_is_parity_flag(p_hwfn, p_aeu)) { 10760d956e8aSYuval Mintz /* Skip Parity */ 10770d956e8aSYuval Mintz bit++; 10780d956e8aSYuval Mintz bit_len--; 10790d956e8aSYuval Mintz } 10800d956e8aSYuval Mintz 10810d956e8aSYuval Mintz bitmask = bits & (((1 << bit_len) - 1) << bit); 10826010179dSMintz, Yuval bitmask >>= bit; 10836010179dSMintz, Yuval 10840d956e8aSYuval Mintz if (bitmask) { 10856010179dSMintz, Yuval u32 flags = p_aeu->flags; 10866010179dSMintz, Yuval char bit_name[30]; 10876010179dSMintz, Yuval u8 num; 10886010179dSMintz, Yuval 10896010179dSMintz, Yuval num = (u8)find_first_bit(&bitmask, 10906010179dSMintz, Yuval bit_len); 10916010179dSMintz, Yuval 10926010179dSMintz, Yuval /* Some bits represent more than a 10936010179dSMintz, Yuval * a single interrupt. Correctly print 10946010179dSMintz, Yuval * their name. 10956010179dSMintz, Yuval */ 10966010179dSMintz, Yuval if (ATTENTION_LENGTH(flags) > 2 || 10976010179dSMintz, Yuval ((flags & ATTENTION_PAR_INT) && 10986010179dSMintz, Yuval ATTENTION_LENGTH(flags) > 1)) 10996010179dSMintz, Yuval snprintf(bit_name, 30, 11006010179dSMintz, Yuval p_aeu->bit_name, num); 11016010179dSMintz, Yuval else 11023690c8c9SWang Xiayang strlcpy(bit_name, 11036010179dSMintz, Yuval p_aeu->bit_name, 30); 11046010179dSMintz, Yuval 11056010179dSMintz, Yuval /* We now need to pass bitmask in its 11066010179dSMintz, Yuval * correct position. 11076010179dSMintz, Yuval */ 11086010179dSMintz, Yuval bitmask <<= bit; 11096010179dSMintz, Yuval 11100d956e8aSYuval Mintz /* Handle source of the attention */ 11110d956e8aSYuval Mintz qed_int_deassertion_aeu_bit(p_hwfn, 11120d956e8aSYuval Mintz p_aeu, 11130d956e8aSYuval Mintz aeu_en, 11146010179dSMintz, Yuval bit_name, 11150d956e8aSYuval Mintz bitmask); 11160d956e8aSYuval Mintz } 11170d956e8aSYuval Mintz 11180d956e8aSYuval Mintz bit_idx += ATTENTION_LENGTH(p_aeu->flags); 11190d956e8aSYuval Mintz } 11200d956e8aSYuval Mintz } 11210d956e8aSYuval Mintz } 1122cc875c2eSYuval Mintz 1123d4476b8aSDenis Bolotin /* Handle missed DORQ attention */ 1124d4476b8aSDenis Bolotin qed_dorq_attn_handler(p_hwfn); 1125d4476b8aSDenis Bolotin 1126cc875c2eSYuval Mintz /* Clear IGU indication for the deasserted bits */ 1127cc875c2eSYuval Mintz DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 1128cc875c2eSYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 1129cc875c2eSYuval Mintz ((IGU_CMD_ATTN_BIT_CLR_UPPER - 1130cc875c2eSYuval Mintz IGU_CMD_INT_ACK_BASE) << 3), 1131cc875c2eSYuval Mintz ~((u32)deasserted_bits)); 1132cc875c2eSYuval Mintz 1133cc875c2eSYuval Mintz /* Unmask deasserted attentions in IGU */ 11341a635e48SYuval Mintz aeu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); 1135cc875c2eSYuval Mintz aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE); 1136cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask); 1137cc875c2eSYuval Mintz 1138cc875c2eSYuval Mintz /* Clear deassertion from inner state */ 1139cc875c2eSYuval Mintz sb_attn_sw->known_attn &= ~deasserted_bits; 1140cc875c2eSYuval Mintz 11410d956e8aSYuval Mintz return rc; 1142cc875c2eSYuval Mintz } 1143cc875c2eSYuval Mintz 1144cc875c2eSYuval Mintz static int qed_int_attentions(struct qed_hwfn *p_hwfn) 1145cc875c2eSYuval Mintz { 1146cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn; 1147cc875c2eSYuval Mintz struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn; 1148cc875c2eSYuval Mintz u32 attn_bits = 0, attn_acks = 0; 1149cc875c2eSYuval Mintz u16 asserted_bits, deasserted_bits; 1150cc875c2eSYuval Mintz __le16 index; 1151cc875c2eSYuval Mintz int rc = 0; 1152cc875c2eSYuval Mintz 1153cc875c2eSYuval Mintz /* Read current attention bits/acks - safeguard against attentions 1154cc875c2eSYuval Mintz * by guaranting work on a synchronized timeframe 1155cc875c2eSYuval Mintz */ 1156cc875c2eSYuval Mintz do { 1157cc875c2eSYuval Mintz index = p_sb_attn->sb_index; 1158ed4eac20SDenis Bolotin /* finish reading index before the loop condition */ 1159ed4eac20SDenis Bolotin dma_rmb(); 1160cc875c2eSYuval Mintz attn_bits = le32_to_cpu(p_sb_attn->atten_bits); 1161cc875c2eSYuval Mintz attn_acks = le32_to_cpu(p_sb_attn->atten_ack); 1162cc875c2eSYuval Mintz } while (index != p_sb_attn->sb_index); 1163cc875c2eSYuval Mintz p_sb_attn->sb_index = index; 1164cc875c2eSYuval Mintz 1165cc875c2eSYuval Mintz /* Attention / Deassertion are meaningful (and in correct state) 1166cc875c2eSYuval Mintz * only when they differ and consistent with known state - deassertion 1167cc875c2eSYuval Mintz * when previous attention & current ack, and assertion when current 1168cc875c2eSYuval Mintz * attention with no previous attention 1169cc875c2eSYuval Mintz */ 1170cc875c2eSYuval Mintz asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) & 1171cc875c2eSYuval Mintz ~p_sb_attn_sw->known_attn; 1172cc875c2eSYuval Mintz deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) & 1173cc875c2eSYuval Mintz p_sb_attn_sw->known_attn; 1174cc875c2eSYuval Mintz 1175cc875c2eSYuval Mintz if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100)) { 1176cc875c2eSYuval Mintz DP_INFO(p_hwfn, 1177cc875c2eSYuval Mintz "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n", 1178cc875c2eSYuval Mintz index, attn_bits, attn_acks, asserted_bits, 1179cc875c2eSYuval Mintz deasserted_bits, p_sb_attn_sw->known_attn); 1180cc875c2eSYuval Mintz } else if (asserted_bits == 0x100) { 11811d61e218SLaurence Oberman DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 11821d61e218SLaurence Oberman "MFW indication via attention\n"); 1183cc875c2eSYuval Mintz } else { 1184cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1185cc875c2eSYuval Mintz "MFW indication [deassertion]\n"); 1186cc875c2eSYuval Mintz } 1187cc875c2eSYuval Mintz 1188cc875c2eSYuval Mintz if (asserted_bits) { 1189cc875c2eSYuval Mintz rc = qed_int_assertion(p_hwfn, asserted_bits); 1190cc875c2eSYuval Mintz if (rc) 1191cc875c2eSYuval Mintz return rc; 1192cc875c2eSYuval Mintz } 1193cc875c2eSYuval Mintz 11941a635e48SYuval Mintz if (deasserted_bits) 1195cc875c2eSYuval Mintz rc = qed_int_deassertion(p_hwfn, deasserted_bits); 1196cc875c2eSYuval Mintz 1197cc875c2eSYuval Mintz return rc; 1198cc875c2eSYuval Mintz } 1199cc875c2eSYuval Mintz 1200cc875c2eSYuval Mintz static void qed_sb_ack_attn(struct qed_hwfn *p_hwfn, 12011a635e48SYuval Mintz void __iomem *igu_addr, u32 ack_cons) 1202cc875c2eSYuval Mintz { 12035ab90341SAlexander Lobakin u32 igu_ack; 1204cc875c2eSYuval Mintz 12055ab90341SAlexander Lobakin igu_ack = ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 1206cc875c2eSYuval Mintz (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 1207cc875c2eSYuval Mintz (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 1208cc875c2eSYuval Mintz (IGU_SEG_ACCESS_ATTN << 1209cc875c2eSYuval Mintz IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 1210cc875c2eSYuval Mintz 12115ab90341SAlexander Lobakin DIRECT_REG_WR(igu_addr, igu_ack); 1212cc875c2eSYuval Mintz 1213cc875c2eSYuval Mintz /* Both segments (interrupts & acks) are written to same place address; 1214cc875c2eSYuval Mintz * Need to guarantee all commands will be received (in-order) by HW. 1215cc875c2eSYuval Mintz */ 1216cc875c2eSYuval Mintz barrier(); 1217cc875c2eSYuval Mintz } 1218cc875c2eSYuval Mintz 1219b5f0a3bfSAllen Pais void qed_int_sp_dpc(struct tasklet_struct *t) 1220fe56b9e6SYuval Mintz { 1221b5f0a3bfSAllen Pais struct qed_hwfn *p_hwfn = from_tasklet(p_hwfn, t, sp_dpc); 1222fe56b9e6SYuval Mintz struct qed_pi_info *pi_info = NULL; 1223cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn; 1224fe56b9e6SYuval Mintz struct qed_sb_info *sb_info; 1225fe56b9e6SYuval Mintz int arr_size; 1226fe56b9e6SYuval Mintz u16 rc = 0; 1227fe56b9e6SYuval Mintz 1228fe56b9e6SYuval Mintz if (!p_hwfn->p_sp_sb) { 1229fe56b9e6SYuval Mintz DP_ERR(p_hwfn->cdev, "DPC called - no p_sp_sb\n"); 1230fe56b9e6SYuval Mintz return; 1231fe56b9e6SYuval Mintz } 1232fe56b9e6SYuval Mintz 1233fe56b9e6SYuval Mintz sb_info = &p_hwfn->p_sp_sb->sb_info; 1234fe56b9e6SYuval Mintz arr_size = ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr); 1235fe56b9e6SYuval Mintz if (!sb_info) { 1236fe56b9e6SYuval Mintz DP_ERR(p_hwfn->cdev, 1237fe56b9e6SYuval Mintz "Status block is NULL - cannot ack interrupts\n"); 1238fe56b9e6SYuval Mintz return; 1239fe56b9e6SYuval Mintz } 1240fe56b9e6SYuval Mintz 1241cc875c2eSYuval Mintz if (!p_hwfn->p_sb_attn) { 1242cc875c2eSYuval Mintz DP_ERR(p_hwfn->cdev, "DPC called - no p_sb_attn"); 1243cc875c2eSYuval Mintz return; 1244cc875c2eSYuval Mintz } 1245cc875c2eSYuval Mintz sb_attn = p_hwfn->p_sb_attn; 1246cc875c2eSYuval Mintz 1247fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "DPC Called! (hwfn %p %d)\n", 1248fe56b9e6SYuval Mintz p_hwfn, p_hwfn->my_id); 1249fe56b9e6SYuval Mintz 1250fe56b9e6SYuval Mintz /* Disable ack for def status block. Required both for msix + 1251fe56b9e6SYuval Mintz * inta in non-mask mode, in inta does no harm. 1252fe56b9e6SYuval Mintz */ 1253fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_DISABLE, 0); 1254fe56b9e6SYuval Mintz 1255fe56b9e6SYuval Mintz /* Gather Interrupts/Attentions information */ 1256fe56b9e6SYuval Mintz if (!sb_info->sb_virt) { 12571a635e48SYuval Mintz DP_ERR(p_hwfn->cdev, 1258fe56b9e6SYuval Mintz "Interrupt Status block is NULL - cannot check for new interrupts!\n"); 1259fe56b9e6SYuval Mintz } else { 1260fe56b9e6SYuval Mintz u32 tmp_index = sb_info->sb_ack; 1261fe56b9e6SYuval Mintz 1262fe56b9e6SYuval Mintz rc = qed_sb_update_sb_idx(sb_info); 1263fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 1264fe56b9e6SYuval Mintz "Interrupt indices: 0x%08x --> 0x%08x\n", 1265fe56b9e6SYuval Mintz tmp_index, sb_info->sb_ack); 1266fe56b9e6SYuval Mintz } 1267fe56b9e6SYuval Mintz 1268cc875c2eSYuval Mintz if (!sb_attn || !sb_attn->sb_attn) { 12691a635e48SYuval Mintz DP_ERR(p_hwfn->cdev, 1270cc875c2eSYuval Mintz "Attentions Status block is NULL - cannot check for new attentions!\n"); 1271cc875c2eSYuval Mintz } else { 1272cc875c2eSYuval Mintz u16 tmp_index = sb_attn->index; 1273cc875c2eSYuval Mintz 1274cc875c2eSYuval Mintz rc |= qed_attn_update_idx(p_hwfn, sb_attn); 1275cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 1276cc875c2eSYuval Mintz "Attention indices: 0x%08x --> 0x%08x\n", 1277cc875c2eSYuval Mintz tmp_index, sb_attn->index); 1278cc875c2eSYuval Mintz } 1279cc875c2eSYuval Mintz 1280fe56b9e6SYuval Mintz /* Check if we expect interrupts at this time. if not just ack them */ 1281fe56b9e6SYuval Mintz if (!(rc & QED_SB_EVENT_MASK)) { 1282fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1283fe56b9e6SYuval Mintz return; 1284fe56b9e6SYuval Mintz } 1285fe56b9e6SYuval Mintz 1286fe56b9e6SYuval Mintz /* Check the validity of the DPC ptt. If not ack interrupts and fail */ 1287fe56b9e6SYuval Mintz if (!p_hwfn->p_dpc_ptt) { 1288fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn->cdev, "Failed to allocate PTT\n"); 1289fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1290fe56b9e6SYuval Mintz return; 1291fe56b9e6SYuval Mintz } 1292fe56b9e6SYuval Mintz 1293cc875c2eSYuval Mintz if (rc & QED_SB_ATT_IDX) 1294cc875c2eSYuval Mintz qed_int_attentions(p_hwfn); 1295cc875c2eSYuval Mintz 1296fe56b9e6SYuval Mintz if (rc & QED_SB_IDX) { 1297fe56b9e6SYuval Mintz int pi; 1298fe56b9e6SYuval Mintz 1299fe56b9e6SYuval Mintz /* Look for a free index */ 1300fe56b9e6SYuval Mintz for (pi = 0; pi < arr_size; pi++) { 1301fe56b9e6SYuval Mintz pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi]; 1302fe56b9e6SYuval Mintz if (pi_info->comp_cb) 1303fe56b9e6SYuval Mintz pi_info->comp_cb(p_hwfn, pi_info->cookie); 1304fe56b9e6SYuval Mintz } 1305fe56b9e6SYuval Mintz } 1306fe56b9e6SYuval Mintz 1307cc875c2eSYuval Mintz if (sb_attn && (rc & QED_SB_ATT_IDX)) 1308cc875c2eSYuval Mintz /* This should be done before the interrupts are enabled, 1309cc875c2eSYuval Mintz * since otherwise a new attention will be generated. 1310cc875c2eSYuval Mintz */ 1311cc875c2eSYuval Mintz qed_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index); 1312cc875c2eSYuval Mintz 1313fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1314fe56b9e6SYuval Mintz } 1315fe56b9e6SYuval Mintz 1316cc875c2eSYuval Mintz static void qed_int_sb_attn_free(struct qed_hwfn *p_hwfn) 1317cc875c2eSYuval Mintz { 1318cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb = p_hwfn->p_sb_attn; 1319cc875c2eSYuval Mintz 13204ac801b7SYuval Mintz if (!p_sb) 13214ac801b7SYuval Mintz return; 13224ac801b7SYuval Mintz 1323cc875c2eSYuval Mintz if (p_sb->sb_attn) 13244ac801b7SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1325cc875c2eSYuval Mintz SB_ATTN_ALIGNED_SIZE(p_hwfn), 13261a635e48SYuval Mintz p_sb->sb_attn, p_sb->sb_phys); 1327cc875c2eSYuval Mintz kfree(p_sb); 13283587cb87STomer Tayar p_hwfn->p_sb_attn = NULL; 1329cc875c2eSYuval Mintz } 1330cc875c2eSYuval Mintz 1331cc875c2eSYuval Mintz static void qed_int_sb_attn_setup(struct qed_hwfn *p_hwfn, 1332cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1333cc875c2eSYuval Mintz { 1334cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 1335cc875c2eSYuval Mintz 1336cc875c2eSYuval Mintz memset(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn)); 1337cc875c2eSYuval Mintz 1338cc875c2eSYuval Mintz sb_info->index = 0; 1339cc875c2eSYuval Mintz sb_info->known_attn = 0; 1340cc875c2eSYuval Mintz 1341cc875c2eSYuval Mintz /* Configure Attention Status Block in IGU */ 1342cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L, 1343cc875c2eSYuval Mintz lower_32_bits(p_hwfn->p_sb_attn->sb_phys)); 1344cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H, 1345cc875c2eSYuval Mintz upper_32_bits(p_hwfn->p_sb_attn->sb_phys)); 1346cc875c2eSYuval Mintz } 1347cc875c2eSYuval Mintz 1348cc875c2eSYuval Mintz static void qed_int_sb_attn_init(struct qed_hwfn *p_hwfn, 1349cc875c2eSYuval Mintz struct qed_ptt *p_ptt, 13501a635e48SYuval Mintz void *sb_virt_addr, dma_addr_t sb_phy_addr) 1351cc875c2eSYuval Mintz { 1352cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 13530d956e8aSYuval Mintz int i, j, k; 1354cc875c2eSYuval Mintz 1355cc875c2eSYuval Mintz sb_info->sb_attn = sb_virt_addr; 1356cc875c2eSYuval Mintz sb_info->sb_phys = sb_phy_addr; 1357cc875c2eSYuval Mintz 13580d956e8aSYuval Mintz /* Set the pointer to the AEU descriptors */ 13590d956e8aSYuval Mintz sb_info->p_aeu_desc = aeu_descs; 13600d956e8aSYuval Mintz 13610d956e8aSYuval Mintz /* Calculate Parity Masks */ 13620d956e8aSYuval Mintz memset(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS); 13630d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 13640d956e8aSYuval Mintz /* j is array index, k is bit index */ 13650d956e8aSYuval Mintz for (j = 0, k = 0; k < 32; j++) { 1366ba36f718SMintz, Yuval struct aeu_invert_reg_bit *p_aeu; 13670d956e8aSYuval Mintz 1368ba36f718SMintz, Yuval p_aeu = &aeu_descs[i].bits[j]; 1369ba36f718SMintz, Yuval if (qed_int_is_parity_flag(p_hwfn, p_aeu)) 13700d956e8aSYuval Mintz sb_info->parity_mask[i] |= 1 << k; 13710d956e8aSYuval Mintz 1372ba36f718SMintz, Yuval k += ATTENTION_LENGTH(p_aeu->flags); 13730d956e8aSYuval Mintz } 13740d956e8aSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 13750d956e8aSYuval Mintz "Attn Mask [Reg %d]: 0x%08x\n", 13760d956e8aSYuval Mintz i, sb_info->parity_mask[i]); 13770d956e8aSYuval Mintz } 13780d956e8aSYuval Mintz 1379cc875c2eSYuval Mintz /* Set the address of cleanup for the mcp attention */ 1380cc875c2eSYuval Mintz sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) + 1381cc875c2eSYuval Mintz MISC_REG_AEU_GENERAL_ATTN_0; 1382cc875c2eSYuval Mintz 1383cc875c2eSYuval Mintz qed_int_sb_attn_setup(p_hwfn, p_ptt); 1384cc875c2eSYuval Mintz } 1385cc875c2eSYuval Mintz 1386cc875c2eSYuval Mintz static int qed_int_sb_attn_alloc(struct qed_hwfn *p_hwfn, 1387cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1388cc875c2eSYuval Mintz { 1389cc875c2eSYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 1390cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb; 1391cc875c2eSYuval Mintz dma_addr_t p_phys = 0; 13921a635e48SYuval Mintz void *p_virt; 1393cc875c2eSYuval Mintz 1394cc875c2eSYuval Mintz /* SB struct */ 139560fffb3bSYuval Mintz p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 13962591c280SJoe Perches if (!p_sb) 1397cc875c2eSYuval Mintz return -ENOMEM; 1398cc875c2eSYuval Mintz 1399cc875c2eSYuval Mintz /* SB ring */ 1400cc875c2eSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 1401cc875c2eSYuval Mintz SB_ATTN_ALIGNED_SIZE(p_hwfn), 1402cc875c2eSYuval Mintz &p_phys, GFP_KERNEL); 1403cc875c2eSYuval Mintz 1404cc875c2eSYuval Mintz if (!p_virt) { 1405cc875c2eSYuval Mintz kfree(p_sb); 1406cc875c2eSYuval Mintz return -ENOMEM; 1407cc875c2eSYuval Mintz } 1408cc875c2eSYuval Mintz 1409cc875c2eSYuval Mintz /* Attention setup */ 1410cc875c2eSYuval Mintz p_hwfn->p_sb_attn = p_sb; 1411cc875c2eSYuval Mintz qed_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys); 1412cc875c2eSYuval Mintz 1413cc875c2eSYuval Mintz return 0; 1414cc875c2eSYuval Mintz } 1415cc875c2eSYuval Mintz 1416fe56b9e6SYuval Mintz /* coalescing timeout = timeset << (timer_res + 1) */ 1417fe56b9e6SYuval Mintz #define QED_CAU_DEF_RX_USECS 24 1418fe56b9e6SYuval Mintz #define QED_CAU_DEF_TX_USECS 48 1419fe56b9e6SYuval Mintz 1420fe56b9e6SYuval Mintz void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn, 1421fe56b9e6SYuval Mintz struct cau_sb_entry *p_sb_entry, 14221a635e48SYuval Mintz u8 pf_id, u16 vf_number, u8 vf_valid) 1423fe56b9e6SYuval Mintz { 14244ac801b7SYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 14255ab90341SAlexander Lobakin u32 cau_state, params = 0, data = 0; 1426722003acSSudarsana Reddy Kalluru u8 timer_res; 1427fe56b9e6SYuval Mintz 1428fe56b9e6SYuval Mintz memset(p_sb_entry, 0, sizeof(*p_sb_entry)); 1429fe56b9e6SYuval Mintz 14305ab90341SAlexander Lobakin SET_FIELD(params, CAU_SB_ENTRY_PF_NUMBER, pf_id); 14315ab90341SAlexander Lobakin SET_FIELD(params, CAU_SB_ENTRY_VF_NUMBER, vf_number); 14325ab90341SAlexander Lobakin SET_FIELD(params, CAU_SB_ENTRY_VF_VALID, vf_valid); 14335ab90341SAlexander Lobakin SET_FIELD(params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F); 14345ab90341SAlexander Lobakin SET_FIELD(params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F); 1435fe56b9e6SYuval Mintz 1436fe56b9e6SYuval Mintz cau_state = CAU_HC_DISABLE_STATE; 1437fe56b9e6SYuval Mintz 14384ac801b7SYuval Mintz if (cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 1439fe56b9e6SYuval Mintz cau_state = CAU_HC_ENABLE_STATE; 14404ac801b7SYuval Mintz if (!cdev->rx_coalesce_usecs) 14414ac801b7SYuval Mintz cdev->rx_coalesce_usecs = QED_CAU_DEF_RX_USECS; 14424ac801b7SYuval Mintz if (!cdev->tx_coalesce_usecs) 14434ac801b7SYuval Mintz cdev->tx_coalesce_usecs = QED_CAU_DEF_TX_USECS; 1444fe56b9e6SYuval Mintz } 1445fe56b9e6SYuval Mintz 1446722003acSSudarsana Reddy Kalluru /* Coalesce = (timeset << timer-res), timeset is 7bit wide */ 1447722003acSSudarsana Reddy Kalluru if (cdev->rx_coalesce_usecs <= 0x7F) 1448722003acSSudarsana Reddy Kalluru timer_res = 0; 1449722003acSSudarsana Reddy Kalluru else if (cdev->rx_coalesce_usecs <= 0xFF) 1450722003acSSudarsana Reddy Kalluru timer_res = 1; 1451722003acSSudarsana Reddy Kalluru else 1452722003acSSudarsana Reddy Kalluru timer_res = 2; 14535ab90341SAlexander Lobakin 14545ab90341SAlexander Lobakin SET_FIELD(params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 1455722003acSSudarsana Reddy Kalluru 1456722003acSSudarsana Reddy Kalluru if (cdev->tx_coalesce_usecs <= 0x7F) 1457722003acSSudarsana Reddy Kalluru timer_res = 0; 1458722003acSSudarsana Reddy Kalluru else if (cdev->tx_coalesce_usecs <= 0xFF) 1459722003acSSudarsana Reddy Kalluru timer_res = 1; 1460722003acSSudarsana Reddy Kalluru else 1461722003acSSudarsana Reddy Kalluru timer_res = 2; 1462722003acSSudarsana Reddy Kalluru 14635ab90341SAlexander Lobakin SET_FIELD(params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 14645ab90341SAlexander Lobakin p_sb_entry->params = cpu_to_le32(params); 14655ab90341SAlexander Lobakin 14665ab90341SAlexander Lobakin SET_FIELD(data, CAU_SB_ENTRY_STATE0, cau_state); 14675ab90341SAlexander Lobakin SET_FIELD(data, CAU_SB_ENTRY_STATE1, cau_state); 14685ab90341SAlexander Lobakin p_sb_entry->data = cpu_to_le32(data); 1469fe56b9e6SYuval Mintz } 1470fe56b9e6SYuval Mintz 14718befd73cSMintz, Yuval static void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn, 14728befd73cSMintz, Yuval struct qed_ptt *p_ptt, 14738befd73cSMintz, Yuval u16 igu_sb_id, 14748befd73cSMintz, Yuval u32 pi_index, 14758befd73cSMintz, Yuval enum qed_coalescing_fsm coalescing_fsm, 14768befd73cSMintz, Yuval u8 timeset) 14778befd73cSMintz, Yuval { 14788befd73cSMintz, Yuval u32 sb_offset, pi_offset; 14795ab90341SAlexander Lobakin u32 prod = 0; 14808befd73cSMintz, Yuval 14818befd73cSMintz, Yuval if (IS_VF(p_hwfn->cdev)) 14828befd73cSMintz, Yuval return; 14838befd73cSMintz, Yuval 14845ab90341SAlexander Lobakin SET_FIELD(prod, CAU_PI_ENTRY_PI_TIMESET, timeset); 14858befd73cSMintz, Yuval if (coalescing_fsm == QED_COAL_RX_STATE_MACHINE) 14865ab90341SAlexander Lobakin SET_FIELD(prod, CAU_PI_ENTRY_FSM_SEL, 0); 14878befd73cSMintz, Yuval else 14885ab90341SAlexander Lobakin SET_FIELD(prod, CAU_PI_ENTRY_FSM_SEL, 1); 14898befd73cSMintz, Yuval 14905ab90341SAlexander Lobakin sb_offset = igu_sb_id * PIS_PER_SB_E4; 14918befd73cSMintz, Yuval pi_offset = sb_offset + pi_index; 14925ab90341SAlexander Lobakin 14935ab90341SAlexander Lobakin if (p_hwfn->hw_init_done) 14948befd73cSMintz, Yuval qed_wr(p_hwfn, p_ptt, 14955ab90341SAlexander Lobakin CAU_REG_PI_MEMORY + pi_offset * sizeof(u32), prod); 14965ab90341SAlexander Lobakin else 14975ab90341SAlexander Lobakin STORE_RT_REG(p_hwfn, CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset, 14985ab90341SAlexander Lobakin prod); 14998befd73cSMintz, Yuval } 15008befd73cSMintz, Yuval 1501fe56b9e6SYuval Mintz void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn, 1502fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1503fe56b9e6SYuval Mintz dma_addr_t sb_phys, 15041a635e48SYuval Mintz u16 igu_sb_id, u16 vf_number, u8 vf_valid) 1505fe56b9e6SYuval Mintz { 1506fe56b9e6SYuval Mintz struct cau_sb_entry sb_entry; 1507fe56b9e6SYuval Mintz 1508fe56b9e6SYuval Mintz qed_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id, 1509fe56b9e6SYuval Mintz vf_number, vf_valid); 1510fe56b9e6SYuval Mintz 1511fe56b9e6SYuval Mintz if (p_hwfn->hw_init_done) { 15120a0c5d3bSYuval Mintz /* Wide-bus, initialize via DMAE */ 15130a0c5d3bSYuval Mintz u64 phys_addr = (u64)sb_phys; 1514fe56b9e6SYuval Mintz 15150a0c5d3bSYuval Mintz qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&phys_addr, 15160a0c5d3bSYuval Mintz CAU_REG_SB_ADDR_MEMORY + 151783bf76e3SMichal Kalderon igu_sb_id * sizeof(u64), 2, NULL); 15180a0c5d3bSYuval Mintz qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&sb_entry, 15190a0c5d3bSYuval Mintz CAU_REG_SB_VAR_MEMORY + 152083bf76e3SMichal Kalderon igu_sb_id * sizeof(u64), 2, NULL); 1521fe56b9e6SYuval Mintz } else { 1522fe56b9e6SYuval Mintz /* Initialize Status Block Address */ 1523fe56b9e6SYuval Mintz STORE_RT_REG_AGG(p_hwfn, 1524fe56b9e6SYuval Mintz CAU_REG_SB_ADDR_MEMORY_RT_OFFSET + 1525fe56b9e6SYuval Mintz igu_sb_id * 2, 1526fe56b9e6SYuval Mintz sb_phys); 1527fe56b9e6SYuval Mintz 1528fe56b9e6SYuval Mintz STORE_RT_REG_AGG(p_hwfn, 1529fe56b9e6SYuval Mintz CAU_REG_SB_VAR_MEMORY_RT_OFFSET + 1530fe56b9e6SYuval Mintz igu_sb_id * 2, 1531fe56b9e6SYuval Mintz sb_entry); 1532fe56b9e6SYuval Mintz } 1533fe56b9e6SYuval Mintz 1534fe56b9e6SYuval Mintz /* Configure pi coalescing if set */ 1535fe56b9e6SYuval Mintz if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 1536b5a9ee7cSAriel Elior u8 num_tc = p_hwfn->hw_info.num_hw_tc; 1537722003acSSudarsana Reddy Kalluru u8 timeset, timer_res; 1538b5a9ee7cSAriel Elior u8 i; 1539fe56b9e6SYuval Mintz 1540722003acSSudarsana Reddy Kalluru /* timeset = (coalesce >> timer-res), timeset is 7bit wide */ 1541722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->rx_coalesce_usecs <= 0x7F) 1542722003acSSudarsana Reddy Kalluru timer_res = 0; 1543722003acSSudarsana Reddy Kalluru else if (p_hwfn->cdev->rx_coalesce_usecs <= 0xFF) 1544722003acSSudarsana Reddy Kalluru timer_res = 1; 1545722003acSSudarsana Reddy Kalluru else 1546722003acSSudarsana Reddy Kalluru timer_res = 2; 1547722003acSSudarsana Reddy Kalluru timeset = (u8)(p_hwfn->cdev->rx_coalesce_usecs >> timer_res); 1548fe56b9e6SYuval Mintz qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI, 15491a635e48SYuval Mintz QED_COAL_RX_STATE_MACHINE, timeset); 1550fe56b9e6SYuval Mintz 1551722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->tx_coalesce_usecs <= 0x7F) 1552722003acSSudarsana Reddy Kalluru timer_res = 0; 1553722003acSSudarsana Reddy Kalluru else if (p_hwfn->cdev->tx_coalesce_usecs <= 0xFF) 1554722003acSSudarsana Reddy Kalluru timer_res = 1; 1555722003acSSudarsana Reddy Kalluru else 1556722003acSSudarsana Reddy Kalluru timer_res = 2; 1557722003acSSudarsana Reddy Kalluru timeset = (u8)(p_hwfn->cdev->tx_coalesce_usecs >> timer_res); 1558fe56b9e6SYuval Mintz for (i = 0; i < num_tc; i++) { 1559fe56b9e6SYuval Mintz qed_int_cau_conf_pi(p_hwfn, p_ptt, 1560fe56b9e6SYuval Mintz igu_sb_id, TX_PI(i), 1561fe56b9e6SYuval Mintz QED_COAL_TX_STATE_MACHINE, 1562fe56b9e6SYuval Mintz timeset); 1563fe56b9e6SYuval Mintz } 1564fe56b9e6SYuval Mintz } 1565fe56b9e6SYuval Mintz } 1566fe56b9e6SYuval Mintz 1567fe56b9e6SYuval Mintz void qed_int_sb_setup(struct qed_hwfn *p_hwfn, 15681a635e48SYuval Mintz struct qed_ptt *p_ptt, struct qed_sb_info *sb_info) 1569fe56b9e6SYuval Mintz { 1570fe56b9e6SYuval Mintz /* zero status block and ack counter */ 1571fe56b9e6SYuval Mintz sb_info->sb_ack = 0; 1572fe56b9e6SYuval Mintz memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 1573fe56b9e6SYuval Mintz 15741408cc1fSYuval Mintz if (IS_PF(p_hwfn->cdev)) 1575fe56b9e6SYuval Mintz qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys, 1576fe56b9e6SYuval Mintz sb_info->igu_sb_id, 0, 0); 1577fe56b9e6SYuval Mintz } 1578fe56b9e6SYuval Mintz 157909b6b147SMintz, Yuval struct qed_igu_block *qed_get_igu_free_sb(struct qed_hwfn *p_hwfn, bool b_is_pf) 158009b6b147SMintz, Yuval { 158109b6b147SMintz, Yuval struct qed_igu_block *p_block; 158209b6b147SMintz, Yuval u16 igu_id; 158309b6b147SMintz, Yuval 158409b6b147SMintz, Yuval for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); 158509b6b147SMintz, Yuval igu_id++) { 158609b6b147SMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id]; 158709b6b147SMintz, Yuval 158809b6b147SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID) || 158909b6b147SMintz, Yuval !(p_block->status & QED_IGU_STATUS_FREE)) 159009b6b147SMintz, Yuval continue; 159109b6b147SMintz, Yuval 159209b6b147SMintz, Yuval if (!!(p_block->status & QED_IGU_STATUS_PF) == b_is_pf) 159309b6b147SMintz, Yuval return p_block; 159409b6b147SMintz, Yuval } 159509b6b147SMintz, Yuval 159609b6b147SMintz, Yuval return NULL; 159709b6b147SMintz, Yuval } 159809b6b147SMintz, Yuval 1599a333f7f3SMintz, Yuval static u16 qed_get_pf_igu_sb_id(struct qed_hwfn *p_hwfn, u16 vector_id) 1600a333f7f3SMintz, Yuval { 1601a333f7f3SMintz, Yuval struct qed_igu_block *p_block; 1602a333f7f3SMintz, Yuval u16 igu_id; 1603a333f7f3SMintz, Yuval 1604a333f7f3SMintz, Yuval for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); 1605a333f7f3SMintz, Yuval igu_id++) { 1606a333f7f3SMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id]; 1607a333f7f3SMintz, Yuval 1608a333f7f3SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID) || 1609a333f7f3SMintz, Yuval !p_block->is_pf || 1610a333f7f3SMintz, Yuval p_block->vector_number != vector_id) 1611a333f7f3SMintz, Yuval continue; 1612a333f7f3SMintz, Yuval 1613a333f7f3SMintz, Yuval return igu_id; 1614a333f7f3SMintz, Yuval } 1615a333f7f3SMintz, Yuval 1616a333f7f3SMintz, Yuval return QED_SB_INVALID_IDX; 1617a333f7f3SMintz, Yuval } 1618a333f7f3SMintz, Yuval 161950a20714SMintz, Yuval u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id) 1620fe56b9e6SYuval Mintz { 1621fe56b9e6SYuval Mintz u16 igu_sb_id; 1622fe56b9e6SYuval Mintz 1623fe56b9e6SYuval Mintz /* Assuming continuous set of IGU SBs dedicated for given PF */ 1624fe56b9e6SYuval Mintz if (sb_id == QED_SP_SB_ID) 1625fe56b9e6SYuval Mintz igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id; 16261408cc1fSYuval Mintz else if (IS_PF(p_hwfn->cdev)) 1627a333f7f3SMintz, Yuval igu_sb_id = qed_get_pf_igu_sb_id(p_hwfn, sb_id + 1); 16281408cc1fSYuval Mintz else 16291408cc1fSYuval Mintz igu_sb_id = qed_vf_get_igu_sb_id(p_hwfn, sb_id); 1630fe56b9e6SYuval Mintz 1631525ef5c0SYuval Mintz if (sb_id == QED_SP_SB_ID) 1632525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1633525ef5c0SYuval Mintz "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id); 1634525ef5c0SYuval Mintz else 1635525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1636525ef5c0SYuval Mintz "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id); 1637fe56b9e6SYuval Mintz 1638fe56b9e6SYuval Mintz return igu_sb_id; 1639fe56b9e6SYuval Mintz } 1640fe56b9e6SYuval Mintz 1641fe56b9e6SYuval Mintz int qed_int_sb_init(struct qed_hwfn *p_hwfn, 1642fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1643fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 16441a635e48SYuval Mintz void *sb_virt_addr, dma_addr_t sb_phy_addr, u16 sb_id) 1645fe56b9e6SYuval Mintz { 1646fe56b9e6SYuval Mintz sb_info->sb_virt = sb_virt_addr; 1647fe56b9e6SYuval Mintz sb_info->sb_phys = sb_phy_addr; 1648fe56b9e6SYuval Mintz 1649fe56b9e6SYuval Mintz sb_info->igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id); 1650fe56b9e6SYuval Mintz 1651fe56b9e6SYuval Mintz if (sb_id != QED_SP_SB_ID) { 165250a20714SMintz, Yuval if (IS_PF(p_hwfn->cdev)) { 165350a20714SMintz, Yuval struct qed_igu_info *p_info; 165450a20714SMintz, Yuval struct qed_igu_block *p_block; 165550a20714SMintz, Yuval 165650a20714SMintz, Yuval p_info = p_hwfn->hw_info.p_igu_info; 165750a20714SMintz, Yuval p_block = &p_info->entry[sb_info->igu_sb_id]; 165850a20714SMintz, Yuval 165950a20714SMintz, Yuval p_block->sb_info = sb_info; 166050a20714SMintz, Yuval p_block->status &= ~QED_IGU_STATUS_FREE; 166150a20714SMintz, Yuval p_info->usage.free_cnt--; 166250a20714SMintz, Yuval } else { 166350a20714SMintz, Yuval qed_vf_set_sb_info(p_hwfn, sb_id, sb_info); 166450a20714SMintz, Yuval } 1665fe56b9e6SYuval Mintz } 1666fe56b9e6SYuval Mintz 1667fe56b9e6SYuval Mintz sb_info->cdev = p_hwfn->cdev; 1668fe56b9e6SYuval Mintz 1669fe56b9e6SYuval Mintz /* The igu address will hold the absolute address that needs to be 1670fe56b9e6SYuval Mintz * written to for a specific status block 1671fe56b9e6SYuval Mintz */ 16721408cc1fSYuval Mintz if (IS_PF(p_hwfn->cdev)) { 1673fe56b9e6SYuval Mintz sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 1674fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 1675fe56b9e6SYuval Mintz (sb_info->igu_sb_id << 3); 16761408cc1fSYuval Mintz } else { 16771408cc1fSYuval Mintz sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 16781408cc1fSYuval Mintz PXP_VF_BAR0_START_IGU + 16791408cc1fSYuval Mintz ((IGU_CMD_INT_ACK_BASE + 16801408cc1fSYuval Mintz sb_info->igu_sb_id) << 3); 16811408cc1fSYuval Mintz } 1682fe56b9e6SYuval Mintz 1683fe56b9e6SYuval Mintz sb_info->flags |= QED_SB_INFO_INIT; 1684fe56b9e6SYuval Mintz 1685fe56b9e6SYuval Mintz qed_int_sb_setup(p_hwfn, p_ptt, sb_info); 1686fe56b9e6SYuval Mintz 1687fe56b9e6SYuval Mintz return 0; 1688fe56b9e6SYuval Mintz } 1689fe56b9e6SYuval Mintz 1690fe56b9e6SYuval Mintz int qed_int_sb_release(struct qed_hwfn *p_hwfn, 16911a635e48SYuval Mintz struct qed_sb_info *sb_info, u16 sb_id) 1692fe56b9e6SYuval Mintz { 169350a20714SMintz, Yuval struct qed_igu_block *p_block; 169450a20714SMintz, Yuval struct qed_igu_info *p_info; 169550a20714SMintz, Yuval 169650a20714SMintz, Yuval if (!sb_info) 169750a20714SMintz, Yuval return 0; 1698fe56b9e6SYuval Mintz 1699fe56b9e6SYuval Mintz /* zero status block and ack counter */ 1700fe56b9e6SYuval Mintz sb_info->sb_ack = 0; 1701fe56b9e6SYuval Mintz memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 1702fe56b9e6SYuval Mintz 170350a20714SMintz, Yuval if (IS_VF(p_hwfn->cdev)) { 170450a20714SMintz, Yuval qed_vf_set_sb_info(p_hwfn, sb_id, NULL); 170550a20714SMintz, Yuval return 0; 17064ac801b7SYuval Mintz } 1707fe56b9e6SYuval Mintz 170850a20714SMintz, Yuval p_info = p_hwfn->hw_info.p_igu_info; 170950a20714SMintz, Yuval p_block = &p_info->entry[sb_info->igu_sb_id]; 171050a20714SMintz, Yuval 171150a20714SMintz, Yuval /* Vector 0 is reserved to Default SB */ 171250a20714SMintz, Yuval if (!p_block->vector_number) { 171350a20714SMintz, Yuval DP_ERR(p_hwfn, "Do Not free sp sb using this function"); 171450a20714SMintz, Yuval return -EINVAL; 171550a20714SMintz, Yuval } 171650a20714SMintz, Yuval 171750a20714SMintz, Yuval /* Lose reference to client's SB info, and fix counters */ 171850a20714SMintz, Yuval p_block->sb_info = NULL; 171950a20714SMintz, Yuval p_block->status |= QED_IGU_STATUS_FREE; 172050a20714SMintz, Yuval p_info->usage.free_cnt++; 172150a20714SMintz, Yuval 1722fe56b9e6SYuval Mintz return 0; 1723fe56b9e6SYuval Mintz } 1724fe56b9e6SYuval Mintz 1725fe56b9e6SYuval Mintz static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn) 1726fe56b9e6SYuval Mintz { 1727fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb; 1728fe56b9e6SYuval Mintz 17294ac801b7SYuval Mintz if (!p_sb) 17304ac801b7SYuval Mintz return; 17314ac801b7SYuval Mintz 1732fe56b9e6SYuval Mintz if (p_sb->sb_info.sb_virt) 1733fe56b9e6SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1734fe56b9e6SYuval Mintz SB_ALIGNED_SIZE(p_hwfn), 1735fe56b9e6SYuval Mintz p_sb->sb_info.sb_virt, 1736fe56b9e6SYuval Mintz p_sb->sb_info.sb_phys); 1737fe56b9e6SYuval Mintz kfree(p_sb); 17383587cb87STomer Tayar p_hwfn->p_sp_sb = NULL; 1739fe56b9e6SYuval Mintz } 1740fe56b9e6SYuval Mintz 17411a635e48SYuval Mintz static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1742fe56b9e6SYuval Mintz { 1743fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sb; 1744fe56b9e6SYuval Mintz dma_addr_t p_phys = 0; 1745fe56b9e6SYuval Mintz void *p_virt; 1746fe56b9e6SYuval Mintz 1747fe56b9e6SYuval Mintz /* SB struct */ 174860fffb3bSYuval Mintz p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 17492591c280SJoe Perches if (!p_sb) 1750fe56b9e6SYuval Mintz return -ENOMEM; 1751fe56b9e6SYuval Mintz 1752fe56b9e6SYuval Mintz /* SB ring */ 1753fe56b9e6SYuval Mintz p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1754fe56b9e6SYuval Mintz SB_ALIGNED_SIZE(p_hwfn), 1755fe56b9e6SYuval Mintz &p_phys, GFP_KERNEL); 1756fe56b9e6SYuval Mintz if (!p_virt) { 1757fe56b9e6SYuval Mintz kfree(p_sb); 1758fe56b9e6SYuval Mintz return -ENOMEM; 1759fe56b9e6SYuval Mintz } 1760fe56b9e6SYuval Mintz 1761fe56b9e6SYuval Mintz /* Status Block setup */ 1762fe56b9e6SYuval Mintz p_hwfn->p_sp_sb = p_sb; 1763fe56b9e6SYuval Mintz qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt, 1764fe56b9e6SYuval Mintz p_phys, QED_SP_SB_ID); 1765fe56b9e6SYuval Mintz 1766fe56b9e6SYuval Mintz memset(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr)); 1767fe56b9e6SYuval Mintz 1768fe56b9e6SYuval Mintz return 0; 1769fe56b9e6SYuval Mintz } 1770fe56b9e6SYuval Mintz 1771fe56b9e6SYuval Mintz int qed_int_register_cb(struct qed_hwfn *p_hwfn, 1772fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb, 17731a635e48SYuval Mintz void *cookie, u8 *sb_idx, __le16 **p_fw_cons) 1774fe56b9e6SYuval Mintz { 1775fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 17764ac801b7SYuval Mintz int rc = -ENOMEM; 1777fe56b9e6SYuval Mintz u8 pi; 1778fe56b9e6SYuval Mintz 1779fe56b9e6SYuval Mintz /* Look for a free index */ 1780fe56b9e6SYuval Mintz for (pi = 0; pi < ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) { 17814ac801b7SYuval Mintz if (p_sp_sb->pi_info_arr[pi].comp_cb) 17824ac801b7SYuval Mintz continue; 17834ac801b7SYuval Mintz 1784fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb; 1785fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].cookie = cookie; 1786fe56b9e6SYuval Mintz *sb_idx = pi; 1787fe56b9e6SYuval Mintz *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi]; 17884ac801b7SYuval Mintz rc = 0; 1789fe56b9e6SYuval Mintz break; 1790fe56b9e6SYuval Mintz } 1791fe56b9e6SYuval Mintz 17924ac801b7SYuval Mintz return rc; 1793fe56b9e6SYuval Mintz } 1794fe56b9e6SYuval Mintz 1795fe56b9e6SYuval Mintz int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi) 1796fe56b9e6SYuval Mintz { 1797fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 1798fe56b9e6SYuval Mintz 17994ac801b7SYuval Mintz if (p_sp_sb->pi_info_arr[pi].comp_cb == NULL) 18004ac801b7SYuval Mintz return -ENOMEM; 18014ac801b7SYuval Mintz 1802fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].comp_cb = NULL; 1803fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].cookie = NULL; 1804fe56b9e6SYuval Mintz 18054ac801b7SYuval Mintz return 0; 1806fe56b9e6SYuval Mintz } 1807fe56b9e6SYuval Mintz 1808fe56b9e6SYuval Mintz u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn) 1809fe56b9e6SYuval Mintz { 1810fe56b9e6SYuval Mintz return p_hwfn->p_sp_sb->sb_info.igu_sb_id; 1811fe56b9e6SYuval Mintz } 1812fe56b9e6SYuval Mintz 1813fe56b9e6SYuval Mintz void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn, 18141a635e48SYuval Mintz struct qed_ptt *p_ptt, enum qed_int_mode int_mode) 1815fe56b9e6SYuval Mintz { 1816cc875c2eSYuval Mintz u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN; 1817fe56b9e6SYuval Mintz 1818fe56b9e6SYuval Mintz p_hwfn->cdev->int_mode = int_mode; 1819fe56b9e6SYuval Mintz switch (p_hwfn->cdev->int_mode) { 1820fe56b9e6SYuval Mintz case QED_INT_MODE_INTA: 1821fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN; 1822fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 1823fe56b9e6SYuval Mintz break; 1824fe56b9e6SYuval Mintz 1825fe56b9e6SYuval Mintz case QED_INT_MODE_MSI: 1826fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 1827fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 1828fe56b9e6SYuval Mintz break; 1829fe56b9e6SYuval Mintz 1830fe56b9e6SYuval Mintz case QED_INT_MODE_MSIX: 1831fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 1832fe56b9e6SYuval Mintz break; 1833fe56b9e6SYuval Mintz case QED_INT_MODE_POLL: 1834fe56b9e6SYuval Mintz break; 1835fe56b9e6SYuval Mintz } 1836fe56b9e6SYuval Mintz 1837fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf); 1838fe56b9e6SYuval Mintz } 1839fe56b9e6SYuval Mintz 1840979cead3SMintz, Yuval static void qed_int_igu_enable_attn(struct qed_hwfn *p_hwfn, 1841979cead3SMintz, Yuval struct qed_ptt *p_ptt) 1842fe56b9e6SYuval Mintz { 1843fe56b9e6SYuval Mintz 18440d956e8aSYuval Mintz /* Configure AEU signal change to produce attentions */ 18450d956e8aSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0); 1846cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff); 1847cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff); 18480d956e8aSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff); 1849cc875c2eSYuval Mintz 1850cc875c2eSYuval Mintz /* Unmask AEU signals toward IGU */ 1851cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff); 1852979cead3SMintz, Yuval } 1853979cead3SMintz, Yuval 1854979cead3SMintz, Yuval int 1855979cead3SMintz, Yuval qed_int_igu_enable(struct qed_hwfn *p_hwfn, 1856979cead3SMintz, Yuval struct qed_ptt *p_ptt, enum qed_int_mode int_mode) 1857979cead3SMintz, Yuval { 1858979cead3SMintz, Yuval int rc = 0; 1859979cead3SMintz, Yuval 1860979cead3SMintz, Yuval qed_int_igu_enable_attn(p_hwfn, p_ptt); 1861979cead3SMintz, Yuval 18628f16bc97SSudarsana Kalluru if ((int_mode != QED_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) { 18638f16bc97SSudarsana Kalluru rc = qed_slowpath_irq_req(p_hwfn); 18641a635e48SYuval Mintz if (rc) { 18658f16bc97SSudarsana Kalluru DP_NOTICE(p_hwfn, "Slowpath IRQ request failed\n"); 18668f16bc97SSudarsana Kalluru return -EINVAL; 18678f16bc97SSudarsana Kalluru } 18688f16bc97SSudarsana Kalluru p_hwfn->b_int_requested = true; 18698f16bc97SSudarsana Kalluru } 18708f16bc97SSudarsana Kalluru /* Enable interrupt Generation */ 18718f16bc97SSudarsana Kalluru qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode); 18728f16bc97SSudarsana Kalluru p_hwfn->b_int_enabled = 1; 18738f16bc97SSudarsana Kalluru 18748f16bc97SSudarsana Kalluru return rc; 1875fe56b9e6SYuval Mintz } 1876fe56b9e6SYuval Mintz 18771a635e48SYuval Mintz void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1878fe56b9e6SYuval Mintz { 1879fe56b9e6SYuval Mintz p_hwfn->b_int_enabled = 0; 1880fe56b9e6SYuval Mintz 18811408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 18821408cc1fSYuval Mintz return; 18831408cc1fSYuval Mintz 1884fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0); 1885fe56b9e6SYuval Mintz } 1886fe56b9e6SYuval Mintz 1887fe56b9e6SYuval Mintz #define IGU_CLEANUP_SLEEP_LENGTH (1000) 1888b2b897ebSYuval Mintz static void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn, 1889fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1890d031548eSMintz, Yuval u16 igu_sb_id, 1891d031548eSMintz, Yuval bool cleanup_set, u16 opaque_fid) 1892fe56b9e6SYuval Mintz { 1893b2b897ebSYuval Mintz u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0; 1894d031548eSMintz, Yuval u32 pxp_addr = IGU_CMD_INT_ACK_BASE + igu_sb_id; 1895fe56b9e6SYuval Mintz u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH; 1896fe56b9e6SYuval Mintz 1897fe56b9e6SYuval Mintz /* Set the data field */ 1898fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0); 1899fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, 0); 1900fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET); 1901fe56b9e6SYuval Mintz 1902fe56b9e6SYuval Mintz /* Set the control register */ 1903fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr); 1904fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid); 1905fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR); 1906fe56b9e6SYuval Mintz 1907fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data); 1908fe56b9e6SYuval Mintz 1909fe56b9e6SYuval Mintz barrier(); 1910fe56b9e6SYuval Mintz 1911fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl); 1912fe56b9e6SYuval Mintz 1913fe56b9e6SYuval Mintz /* calculate where to read the status bit from */ 1914d031548eSMintz, Yuval sb_bit = 1 << (igu_sb_id % 32); 1915d031548eSMintz, Yuval sb_bit_addr = igu_sb_id / 32 * sizeof(u32); 1916fe56b9e6SYuval Mintz 1917fe56b9e6SYuval Mintz sb_bit_addr += IGU_REG_CLEANUP_STATUS_0; 1918fe56b9e6SYuval Mintz 1919fe56b9e6SYuval Mintz /* Now wait for the command to complete */ 1920fe56b9e6SYuval Mintz do { 1921fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, sb_bit_addr); 1922fe56b9e6SYuval Mintz 1923fe56b9e6SYuval Mintz if ((val & sb_bit) == (cleanup_set ? sb_bit : 0)) 1924fe56b9e6SYuval Mintz break; 1925fe56b9e6SYuval Mintz 1926fe56b9e6SYuval Mintz usleep_range(5000, 10000); 1927fe56b9e6SYuval Mintz } while (--sleep_cnt); 1928fe56b9e6SYuval Mintz 1929fe56b9e6SYuval Mintz if (!sleep_cnt) 1930fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 1931fe56b9e6SYuval Mintz "Timeout waiting for clear status 0x%08x [for sb %d]\n", 1932d031548eSMintz, Yuval val, igu_sb_id); 1933fe56b9e6SYuval Mintz } 1934fe56b9e6SYuval Mintz 1935fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn, 1936fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1937d031548eSMintz, Yuval u16 igu_sb_id, u16 opaque, bool b_set) 1938fe56b9e6SYuval Mintz { 19391ac72433SMintz, Yuval struct qed_igu_block *p_block; 1940b2b897ebSYuval Mintz int pi, i; 1941fe56b9e6SYuval Mintz 19421ac72433SMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id]; 19431ac72433SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 19441ac72433SMintz, Yuval "Cleaning SB [%04x]: func_id= %d is_pf = %d vector_num = 0x%0x\n", 19451ac72433SMintz, Yuval igu_sb_id, 19461ac72433SMintz, Yuval p_block->function_id, 19471ac72433SMintz, Yuval p_block->is_pf, p_block->vector_number); 19481ac72433SMintz, Yuval 1949fe56b9e6SYuval Mintz /* Set */ 1950fe56b9e6SYuval Mintz if (b_set) 1951d031548eSMintz, Yuval qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 1, opaque); 1952fe56b9e6SYuval Mintz 1953fe56b9e6SYuval Mintz /* Clear */ 1954d031548eSMintz, Yuval qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 0, opaque); 1955fe56b9e6SYuval Mintz 1956b2b897ebSYuval Mintz /* Wait for the IGU SB to cleanup */ 1957b2b897ebSYuval Mintz for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) { 1958b2b897ebSYuval Mintz u32 val; 1959b2b897ebSYuval Mintz 1960b2b897ebSYuval Mintz val = qed_rd(p_hwfn, p_ptt, 1961d031548eSMintz, Yuval IGU_REG_WRITE_DONE_PENDING + 1962d031548eSMintz, Yuval ((igu_sb_id / 32) * 4)); 1963d031548eSMintz, Yuval if (val & BIT((igu_sb_id % 32))) 1964b2b897ebSYuval Mintz usleep_range(10, 20); 1965b2b897ebSYuval Mintz else 1966b2b897ebSYuval Mintz break; 1967b2b897ebSYuval Mintz } 1968b2b897ebSYuval Mintz if (i == IGU_CLEANUP_SLEEP_LENGTH) 1969b2b897ebSYuval Mintz DP_NOTICE(p_hwfn, 1970b2b897ebSYuval Mintz "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n", 1971d031548eSMintz, Yuval igu_sb_id); 1972b2b897ebSYuval Mintz 1973fe56b9e6SYuval Mintz /* Clear the CAU for the SB */ 1974fe56b9e6SYuval Mintz for (pi = 0; pi < 12; pi++) 1975fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 1976d031548eSMintz, Yuval CAU_REG_PI_MEMORY + (igu_sb_id * 12 + pi) * 4, 0); 1977fe56b9e6SYuval Mintz } 1978fe56b9e6SYuval Mintz 1979fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn, 1980fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1981b2b897ebSYuval Mintz bool b_set, bool b_slowpath) 1982fe56b9e6SYuval Mintz { 19831ac72433SMintz, Yuval struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info; 19841ac72433SMintz, Yuval struct qed_igu_block *p_block; 19851ac72433SMintz, Yuval u16 igu_sb_id = 0; 19861ac72433SMintz, Yuval u32 val = 0; 1987fe56b9e6SYuval Mintz 1988fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION); 1989fe56b9e6SYuval Mintz val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN; 1990fe56b9e6SYuval Mintz val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN; 1991fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val); 1992fe56b9e6SYuval Mintz 19931ac72433SMintz, Yuval for (igu_sb_id = 0; 19941ac72433SMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 19951ac72433SMintz, Yuval p_block = &p_info->entry[igu_sb_id]; 1996fe56b9e6SYuval Mintz 19971ac72433SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID) || 19981ac72433SMintz, Yuval !p_block->is_pf || 19991ac72433SMintz, Yuval (p_block->status & QED_IGU_STATUS_DSB)) 20001ac72433SMintz, Yuval continue; 20011ac72433SMintz, Yuval 2002d031548eSMintz, Yuval qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, igu_sb_id, 2003fe56b9e6SYuval Mintz p_hwfn->hw_info.opaque_fid, 2004fe56b9e6SYuval Mintz b_set); 20051ac72433SMintz, Yuval } 2006fe56b9e6SYuval Mintz 20071ac72433SMintz, Yuval if (b_slowpath) 20081ac72433SMintz, Yuval qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, 20091ac72433SMintz, Yuval p_info->igu_dsb_id, 20101ac72433SMintz, Yuval p_hwfn->hw_info.opaque_fid, 20111ac72433SMintz, Yuval b_set); 2012fe56b9e6SYuval Mintz } 2013fe56b9e6SYuval Mintz 2014ebbdcc66SMintz, Yuval int qed_int_igu_reset_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2015ebbdcc66SMintz, Yuval { 2016ebbdcc66SMintz, Yuval struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info; 2017ebbdcc66SMintz, Yuval struct qed_igu_block *p_block; 2018ebbdcc66SMintz, Yuval int pf_sbs, vf_sbs; 2019ebbdcc66SMintz, Yuval u16 igu_sb_id; 2020ebbdcc66SMintz, Yuval u32 val, rval; 2021ebbdcc66SMintz, Yuval 2022ebbdcc66SMintz, Yuval if (!RESC_NUM(p_hwfn, QED_SB)) { 2023ebbdcc66SMintz, Yuval p_info->b_allow_pf_vf_change = false; 2024ebbdcc66SMintz, Yuval } else { 2025ebbdcc66SMintz, Yuval /* Use the numbers the MFW have provided - 2026ebbdcc66SMintz, Yuval * don't forget MFW accounts for the default SB as well. 2027ebbdcc66SMintz, Yuval */ 2028ebbdcc66SMintz, Yuval p_info->b_allow_pf_vf_change = true; 2029ebbdcc66SMintz, Yuval 2030ebbdcc66SMintz, Yuval if (p_info->usage.cnt != RESC_NUM(p_hwfn, QED_SB) - 1) { 2031ebbdcc66SMintz, Yuval DP_INFO(p_hwfn, 2032ebbdcc66SMintz, Yuval "MFW notifies of 0x%04x PF SBs; IGU indicates of only 0x%04x\n", 2033ebbdcc66SMintz, Yuval RESC_NUM(p_hwfn, QED_SB) - 1, 2034ebbdcc66SMintz, Yuval p_info->usage.cnt); 2035ebbdcc66SMintz, Yuval p_info->usage.cnt = RESC_NUM(p_hwfn, QED_SB) - 1; 2036ebbdcc66SMintz, Yuval } 2037ebbdcc66SMintz, Yuval 2038ebbdcc66SMintz, Yuval if (IS_PF_SRIOV(p_hwfn)) { 2039ebbdcc66SMintz, Yuval u16 vfs = p_hwfn->cdev->p_iov_info->total_vfs; 2040ebbdcc66SMintz, Yuval 2041ebbdcc66SMintz, Yuval if (vfs != p_info->usage.iov_cnt) 2042ebbdcc66SMintz, Yuval DP_VERBOSE(p_hwfn, 2043ebbdcc66SMintz, Yuval NETIF_MSG_INTR, 2044ebbdcc66SMintz, Yuval "0x%04x VF SBs in IGU CAM != PCI configuration 0x%04x\n", 2045ebbdcc66SMintz, Yuval p_info->usage.iov_cnt, vfs); 2046ebbdcc66SMintz, Yuval 2047ebbdcc66SMintz, Yuval /* At this point we know how many SBs we have totally 2048ebbdcc66SMintz, Yuval * in IGU + number of PF SBs. So we can validate that 2049ebbdcc66SMintz, Yuval * we'd have sufficient for VF. 2050ebbdcc66SMintz, Yuval */ 2051ebbdcc66SMintz, Yuval if (vfs > p_info->usage.free_cnt + 2052ebbdcc66SMintz, Yuval p_info->usage.free_cnt_iov - p_info->usage.cnt) { 2053ebbdcc66SMintz, Yuval DP_NOTICE(p_hwfn, 2054ebbdcc66SMintz, Yuval "Not enough SBs for VFs - 0x%04x SBs, from which %04x PFs and %04x are required\n", 2055ebbdcc66SMintz, Yuval p_info->usage.free_cnt + 2056ebbdcc66SMintz, Yuval p_info->usage.free_cnt_iov, 2057ebbdcc66SMintz, Yuval p_info->usage.cnt, vfs); 2058ebbdcc66SMintz, Yuval return -EINVAL; 2059ebbdcc66SMintz, Yuval } 2060ebbdcc66SMintz, Yuval 2061ebbdcc66SMintz, Yuval /* Currently cap the number of VFs SBs by the 2062ebbdcc66SMintz, Yuval * number of VFs. 2063ebbdcc66SMintz, Yuval */ 2064ebbdcc66SMintz, Yuval p_info->usage.iov_cnt = vfs; 2065ebbdcc66SMintz, Yuval } 2066ebbdcc66SMintz, Yuval } 2067ebbdcc66SMintz, Yuval 2068ebbdcc66SMintz, Yuval /* Mark all SBs as free, now in the right PF/VFs division */ 2069ebbdcc66SMintz, Yuval p_info->usage.free_cnt = p_info->usage.cnt; 2070ebbdcc66SMintz, Yuval p_info->usage.free_cnt_iov = p_info->usage.iov_cnt; 2071ebbdcc66SMintz, Yuval p_info->usage.orig = p_info->usage.cnt; 2072ebbdcc66SMintz, Yuval p_info->usage.iov_orig = p_info->usage.iov_cnt; 2073ebbdcc66SMintz, Yuval 2074ebbdcc66SMintz, Yuval /* We now proceed to re-configure the IGU cam to reflect the initial 2075ebbdcc66SMintz, Yuval * configuration. We can start with the Default SB. 2076ebbdcc66SMintz, Yuval */ 2077ebbdcc66SMintz, Yuval pf_sbs = p_info->usage.cnt; 2078ebbdcc66SMintz, Yuval vf_sbs = p_info->usage.iov_cnt; 2079ebbdcc66SMintz, Yuval 2080ebbdcc66SMintz, Yuval for (igu_sb_id = p_info->igu_dsb_id; 2081ebbdcc66SMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 2082ebbdcc66SMintz, Yuval p_block = &p_info->entry[igu_sb_id]; 2083ebbdcc66SMintz, Yuval val = 0; 2084ebbdcc66SMintz, Yuval 2085ebbdcc66SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID)) 2086ebbdcc66SMintz, Yuval continue; 2087ebbdcc66SMintz, Yuval 2088ebbdcc66SMintz, Yuval if (p_block->status & QED_IGU_STATUS_DSB) { 2089ebbdcc66SMintz, Yuval p_block->function_id = p_hwfn->rel_pf_id; 2090ebbdcc66SMintz, Yuval p_block->is_pf = 1; 2091ebbdcc66SMintz, Yuval p_block->vector_number = 0; 2092ebbdcc66SMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2093ebbdcc66SMintz, Yuval QED_IGU_STATUS_PF | 2094ebbdcc66SMintz, Yuval QED_IGU_STATUS_DSB; 2095ebbdcc66SMintz, Yuval } else if (pf_sbs) { 2096ebbdcc66SMintz, Yuval pf_sbs--; 2097ebbdcc66SMintz, Yuval p_block->function_id = p_hwfn->rel_pf_id; 2098ebbdcc66SMintz, Yuval p_block->is_pf = 1; 2099ebbdcc66SMintz, Yuval p_block->vector_number = p_info->usage.cnt - pf_sbs; 2100ebbdcc66SMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2101ebbdcc66SMintz, Yuval QED_IGU_STATUS_PF | 2102ebbdcc66SMintz, Yuval QED_IGU_STATUS_FREE; 2103ebbdcc66SMintz, Yuval } else if (vf_sbs) { 2104ebbdcc66SMintz, Yuval p_block->function_id = 2105ebbdcc66SMintz, Yuval p_hwfn->cdev->p_iov_info->first_vf_in_pf + 2106ebbdcc66SMintz, Yuval p_info->usage.iov_cnt - vf_sbs; 2107ebbdcc66SMintz, Yuval p_block->is_pf = 0; 2108ebbdcc66SMintz, Yuval p_block->vector_number = 0; 2109ebbdcc66SMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2110ebbdcc66SMintz, Yuval QED_IGU_STATUS_FREE; 2111ebbdcc66SMintz, Yuval vf_sbs--; 2112ebbdcc66SMintz, Yuval } else { 2113ebbdcc66SMintz, Yuval p_block->function_id = 0; 2114ebbdcc66SMintz, Yuval p_block->is_pf = 0; 2115ebbdcc66SMintz, Yuval p_block->vector_number = 0; 2116ebbdcc66SMintz, Yuval } 2117ebbdcc66SMintz, Yuval 2118ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER, 2119ebbdcc66SMintz, Yuval p_block->function_id); 2120ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf); 2121ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER, 2122ebbdcc66SMintz, Yuval p_block->vector_number); 2123ebbdcc66SMintz, Yuval 2124ebbdcc66SMintz, Yuval /* VF entries would be enabled when VF is initializaed */ 2125ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf); 2126ebbdcc66SMintz, Yuval 2127ebbdcc66SMintz, Yuval rval = qed_rd(p_hwfn, p_ptt, 2128ebbdcc66SMintz, Yuval IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id); 2129ebbdcc66SMintz, Yuval 2130ebbdcc66SMintz, Yuval if (rval != val) { 2131ebbdcc66SMintz, Yuval qed_wr(p_hwfn, p_ptt, 2132ebbdcc66SMintz, Yuval IGU_REG_MAPPING_MEMORY + 2133ebbdcc66SMintz, Yuval sizeof(u32) * igu_sb_id, val); 2134ebbdcc66SMintz, Yuval 2135ebbdcc66SMintz, Yuval DP_VERBOSE(p_hwfn, 2136ebbdcc66SMintz, Yuval NETIF_MSG_INTR, 2137ebbdcc66SMintz, Yuval "IGU reset: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x [%08x -> %08x]\n", 2138ebbdcc66SMintz, Yuval igu_sb_id, 2139ebbdcc66SMintz, Yuval p_block->function_id, 2140ebbdcc66SMintz, Yuval p_block->is_pf, 2141ebbdcc66SMintz, Yuval p_block->vector_number, rval, val); 2142ebbdcc66SMintz, Yuval } 2143ebbdcc66SMintz, Yuval } 2144ebbdcc66SMintz, Yuval 2145ebbdcc66SMintz, Yuval return 0; 2146ebbdcc66SMintz, Yuval } 2147ebbdcc66SMintz, Yuval 2148d749dd0dSMintz, Yuval static void qed_int_igu_read_cam_block(struct qed_hwfn *p_hwfn, 2149d749dd0dSMintz, Yuval struct qed_ptt *p_ptt, u16 igu_sb_id) 21504ac801b7SYuval Mintz { 21514ac801b7SYuval Mintz u32 val = qed_rd(p_hwfn, p_ptt, 2152d749dd0dSMintz, Yuval IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id); 21534ac801b7SYuval Mintz struct qed_igu_block *p_block; 21544ac801b7SYuval Mintz 2155d749dd0dSMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id]; 21564ac801b7SYuval Mintz 21574ac801b7SYuval Mintz /* Fill the block information */ 2158d749dd0dSMintz, Yuval p_block->function_id = GET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER); 21594ac801b7SYuval Mintz p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID); 2160d749dd0dSMintz, Yuval p_block->vector_number = GET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER); 21611ac72433SMintz, Yuval p_block->igu_sb_id = igu_sb_id; 21624ac801b7SYuval Mintz } 21634ac801b7SYuval Mintz 21641a635e48SYuval Mintz int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2165fe56b9e6SYuval Mintz { 2166fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 2167d749dd0dSMintz, Yuval struct qed_igu_block *p_block; 2168d749dd0dSMintz, Yuval u32 min_vf = 0, max_vf = 0; 2169d749dd0dSMintz, Yuval u16 igu_sb_id; 2170fe56b9e6SYuval Mintz 217160fffb3bSYuval Mintz p_hwfn->hw_info.p_igu_info = kzalloc(sizeof(*p_igu_info), GFP_KERNEL); 2172fe56b9e6SYuval Mintz if (!p_hwfn->hw_info.p_igu_info) 2173fe56b9e6SYuval Mintz return -ENOMEM; 2174fe56b9e6SYuval Mintz 2175fe56b9e6SYuval Mintz p_igu_info = p_hwfn->hw_info.p_igu_info; 2176fe56b9e6SYuval Mintz 2177d749dd0dSMintz, Yuval /* Distinguish between existent and non-existent default SB */ 2178d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id = QED_SB_INVALID_IDX; 2179d749dd0dSMintz, Yuval 2180d749dd0dSMintz, Yuval /* Find the range of VF ids whose SB belong to this PF */ 21811408cc1fSYuval Mintz if (p_hwfn->cdev->p_iov_info) { 21821408cc1fSYuval Mintz struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info; 21831408cc1fSYuval Mintz 21841408cc1fSYuval Mintz min_vf = p_iov->first_vf_in_pf; 21851408cc1fSYuval Mintz max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs; 21861408cc1fSYuval Mintz } 21871408cc1fSYuval Mintz 2188d749dd0dSMintz, Yuval for (igu_sb_id = 0; 2189d749dd0dSMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 2190d749dd0dSMintz, Yuval /* Read current entry; Notice it might not belong to this PF */ 2191d749dd0dSMintz, Yuval qed_int_igu_read_cam_block(p_hwfn, p_ptt, igu_sb_id); 2192d749dd0dSMintz, Yuval p_block = &p_igu_info->entry[igu_sb_id]; 2193fe56b9e6SYuval Mintz 2194d749dd0dSMintz, Yuval if ((p_block->is_pf) && 2195d749dd0dSMintz, Yuval (p_block->function_id == p_hwfn->rel_pf_id)) { 2196d749dd0dSMintz, Yuval p_block->status = QED_IGU_STATUS_PF | 2197d749dd0dSMintz, Yuval QED_IGU_STATUS_VALID | 2198d749dd0dSMintz, Yuval QED_IGU_STATUS_FREE; 2199fe56b9e6SYuval Mintz 22001ac72433SMintz, Yuval if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX) 2201726fdbe9SMintz, Yuval p_igu_info->usage.cnt++; 2202d749dd0dSMintz, Yuval } else if (!(p_block->is_pf) && 2203d749dd0dSMintz, Yuval (p_block->function_id >= min_vf) && 2204d749dd0dSMintz, Yuval (p_block->function_id < max_vf)) { 22051408cc1fSYuval Mintz /* Available for VFs of this PF */ 2206d749dd0dSMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2207d749dd0dSMintz, Yuval QED_IGU_STATUS_FREE; 2208d749dd0dSMintz, Yuval 22091ac72433SMintz, Yuval if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX) 2210726fdbe9SMintz, Yuval p_igu_info->usage.iov_cnt++; 22111408cc1fSYuval Mintz } 22125a1f965aSMintz, Yuval 2213d749dd0dSMintz, Yuval /* Mark the First entry belonging to the PF or its VFs 2214ebbdcc66SMintz, Yuval * as the default SB [we'll reset IGU prior to first usage]. 22155a1f965aSMintz, Yuval */ 2216d749dd0dSMintz, Yuval if ((p_block->status & QED_IGU_STATUS_VALID) && 2217d749dd0dSMintz, Yuval (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX)) { 2218d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id = igu_sb_id; 2219d749dd0dSMintz, Yuval p_block->status |= QED_IGU_STATUS_DSB; 2220d749dd0dSMintz, Yuval } 22215a1f965aSMintz, Yuval 2222d749dd0dSMintz, Yuval /* limit number of prints by having each PF print only its 2223d749dd0dSMintz, Yuval * entries with the exception of PF0 which would print 2224d749dd0dSMintz, Yuval * everything. 2225d749dd0dSMintz, Yuval */ 2226d749dd0dSMintz, Yuval if ((p_block->status & QED_IGU_STATUS_VALID) || 2227d749dd0dSMintz, Yuval (p_hwfn->abs_pf_id == 0)) { 2228d749dd0dSMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2229d749dd0dSMintz, Yuval "IGU_BLOCK: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n", 2230d749dd0dSMintz, Yuval igu_sb_id, p_block->function_id, 2231d749dd0dSMintz, Yuval p_block->is_pf, p_block->vector_number); 2232d749dd0dSMintz, Yuval } 2233d749dd0dSMintz, Yuval } 2234d749dd0dSMintz, Yuval 2235d749dd0dSMintz, Yuval if (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX) { 22365a1f965aSMintz, Yuval DP_NOTICE(p_hwfn, 2237d749dd0dSMintz, Yuval "IGU CAM returned invalid values igu_dsb_id=0x%x\n", 2238d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id); 22395a1f965aSMintz, Yuval return -EINVAL; 22405a1f965aSMintz, Yuval } 2241d749dd0dSMintz, Yuval 2242d749dd0dSMintz, Yuval /* All non default SB are considered free at this point */ 2243726fdbe9SMintz, Yuval p_igu_info->usage.free_cnt = p_igu_info->usage.cnt; 2244726fdbe9SMintz, Yuval p_igu_info->usage.free_cnt_iov = p_igu_info->usage.iov_cnt; 2245fe56b9e6SYuval Mintz 2246d749dd0dSMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2247ebbdcc66SMintz, Yuval "igu_dsb_id=0x%x, num Free SBs - PF: %04x VF: %04x [might change after resource allocation]\n", 2248d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id, 2249726fdbe9SMintz, Yuval p_igu_info->usage.cnt, p_igu_info->usage.iov_cnt); 2250fe56b9e6SYuval Mintz 2251fe56b9e6SYuval Mintz return 0; 2252fe56b9e6SYuval Mintz } 2253fe56b9e6SYuval Mintz 2254fe56b9e6SYuval Mintz /** 225571e11a3fSAlexander Lobakin * qed_int_igu_init_rt() - Initialize IGU runtime registers. 2256fe56b9e6SYuval Mintz * 225771e11a3fSAlexander Lobakin * @p_hwfn: HW device data. 2258fe56b9e6SYuval Mintz */ 2259fe56b9e6SYuval Mintz void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn) 2260fe56b9e6SYuval Mintz { 22611a635e48SYuval Mintz u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN; 2262fe56b9e6SYuval Mintz 2263fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf); 2264fe56b9e6SYuval Mintz } 2265fe56b9e6SYuval Mintz 2266fe56b9e6SYuval Mintz u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn) 2267fe56b9e6SYuval Mintz { 2268fe56b9e6SYuval Mintz u32 lsb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - 2269fe56b9e6SYuval Mintz IGU_CMD_INT_ACK_BASE; 2270fe56b9e6SYuval Mintz u32 msb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - 2271fe56b9e6SYuval Mintz IGU_CMD_INT_ACK_BASE; 22721a635e48SYuval Mintz u32 intr_status_hi = 0, intr_status_lo = 0; 22731a635e48SYuval Mintz u64 intr_status = 0; 2274fe56b9e6SYuval Mintz 2275fe56b9e6SYuval Mintz intr_status_lo = REG_RD(p_hwfn, 2276fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 2277fe56b9e6SYuval Mintz lsb_igu_cmd_addr * 8); 2278fe56b9e6SYuval Mintz intr_status_hi = REG_RD(p_hwfn, 2279fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 2280fe56b9e6SYuval Mintz msb_igu_cmd_addr * 8); 2281fe56b9e6SYuval Mintz intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo; 2282fe56b9e6SYuval Mintz 2283fe56b9e6SYuval Mintz return intr_status; 2284fe56b9e6SYuval Mintz } 2285fe56b9e6SYuval Mintz 2286fe56b9e6SYuval Mintz static void qed_int_sp_dpc_setup(struct qed_hwfn *p_hwfn) 2287fe56b9e6SYuval Mintz { 2288b5f0a3bfSAllen Pais tasklet_setup(&p_hwfn->sp_dpc, qed_int_sp_dpc); 2289fe56b9e6SYuval Mintz p_hwfn->b_sp_dpc_enabled = true; 2290fe56b9e6SYuval Mintz } 2291fe56b9e6SYuval Mintz 22921a635e48SYuval Mintz int qed_int_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2293fe56b9e6SYuval Mintz { 2294fe56b9e6SYuval Mintz int rc = 0; 2295fe56b9e6SYuval Mintz 22962591c280SJoe Perches rc = qed_int_sp_sb_alloc(p_hwfn, p_ptt); 22972591c280SJoe Perches if (rc) 22982591c280SJoe Perches return rc; 22992591c280SJoe Perches 23002591c280SJoe Perches rc = qed_int_sb_attn_alloc(p_hwfn, p_ptt); 230183aeb933SYuval Mintz 2302fe56b9e6SYuval Mintz return rc; 2303fe56b9e6SYuval Mintz } 2304fe56b9e6SYuval Mintz 2305fe56b9e6SYuval Mintz void qed_int_free(struct qed_hwfn *p_hwfn) 2306fe56b9e6SYuval Mintz { 2307fe56b9e6SYuval Mintz qed_int_sp_sb_free(p_hwfn); 2308cc875c2eSYuval Mintz qed_int_sb_attn_free(p_hwfn); 2309fe56b9e6SYuval Mintz } 2310fe56b9e6SYuval Mintz 23111a635e48SYuval Mintz void qed_int_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2312fe56b9e6SYuval Mintz { 23130d956e8aSYuval Mintz qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info); 23140d956e8aSYuval Mintz qed_int_sb_attn_setup(p_hwfn, p_ptt); 2315fe56b9e6SYuval Mintz qed_int_sp_dpc_setup(p_hwfn); 2316fe56b9e6SYuval Mintz } 2317fe56b9e6SYuval Mintz 23184ac801b7SYuval Mintz void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn, 23194ac801b7SYuval Mintz struct qed_sb_cnt_info *p_sb_cnt_info) 2320fe56b9e6SYuval Mintz { 2321fe56b9e6SYuval Mintz struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info; 2322fe56b9e6SYuval Mintz 23234ac801b7SYuval Mintz if (!info || !p_sb_cnt_info) 23244ac801b7SYuval Mintz return; 2325fe56b9e6SYuval Mintz 2326726fdbe9SMintz, Yuval memcpy(p_sb_cnt_info, &info->usage, sizeof(*p_sb_cnt_info)); 2327fe56b9e6SYuval Mintz } 23288f16bc97SSudarsana Kalluru 23298f16bc97SSudarsana Kalluru void qed_int_disable_post_isr_release(struct qed_dev *cdev) 23308f16bc97SSudarsana Kalluru { 23318f16bc97SSudarsana Kalluru int i; 23328f16bc97SSudarsana Kalluru 23338f16bc97SSudarsana Kalluru for_each_hwfn(cdev, i) 23348f16bc97SSudarsana Kalluru cdev->hwfns[i].b_int_requested = false; 23358f16bc97SSudarsana Kalluru } 2336722003acSSudarsana Reddy Kalluru 2337936c7ba4SIgor Russkikh void qed_int_attn_clr_enable(struct qed_dev *cdev, bool clr_enable) 2338936c7ba4SIgor Russkikh { 2339936c7ba4SIgor Russkikh cdev->attn_clr_en = clr_enable; 2340936c7ba4SIgor Russkikh } 2341936c7ba4SIgor Russkikh 2342722003acSSudarsana Reddy Kalluru int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2343722003acSSudarsana Reddy Kalluru u8 timer_res, u16 sb_id, bool tx) 2344722003acSSudarsana Reddy Kalluru { 2345722003acSSudarsana Reddy Kalluru struct cau_sb_entry sb_entry; 23465ab90341SAlexander Lobakin u32 params; 2347722003acSSudarsana Reddy Kalluru int rc; 2348722003acSSudarsana Reddy Kalluru 2349722003acSSudarsana Reddy Kalluru if (!p_hwfn->hw_init_done) { 2350722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "hardware not initialized yet\n"); 2351722003acSSudarsana Reddy Kalluru return -EINVAL; 2352722003acSSudarsana Reddy Kalluru } 2353722003acSSudarsana Reddy Kalluru 2354722003acSSudarsana Reddy Kalluru rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY + 2355722003acSSudarsana Reddy Kalluru sb_id * sizeof(u64), 235683bf76e3SMichal Kalderon (u64)(uintptr_t)&sb_entry, 2, NULL); 2357722003acSSudarsana Reddy Kalluru if (rc) { 2358722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc); 2359722003acSSudarsana Reddy Kalluru return rc; 2360722003acSSudarsana Reddy Kalluru } 2361722003acSSudarsana Reddy Kalluru 23625ab90341SAlexander Lobakin params = le32_to_cpu(sb_entry.params); 23635ab90341SAlexander Lobakin 2364722003acSSudarsana Reddy Kalluru if (tx) 23655ab90341SAlexander Lobakin SET_FIELD(params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 2366722003acSSudarsana Reddy Kalluru else 23675ab90341SAlexander Lobakin SET_FIELD(params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 23685ab90341SAlexander Lobakin 23695ab90341SAlexander Lobakin sb_entry.params = cpu_to_le32(params); 2370722003acSSudarsana Reddy Kalluru 2371722003acSSudarsana Reddy Kalluru rc = qed_dmae_host2grc(p_hwfn, p_ptt, 2372722003acSSudarsana Reddy Kalluru (u64)(uintptr_t)&sb_entry, 2373722003acSSudarsana Reddy Kalluru CAU_REG_SB_VAR_MEMORY + 237483bf76e3SMichal Kalderon sb_id * sizeof(u64), 2, NULL); 2375722003acSSudarsana Reddy Kalluru if (rc) { 2376722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc); 2377722003acSSudarsana Reddy Kalluru return rc; 2378722003acSSudarsana Reddy Kalluru } 2379722003acSSudarsana Reddy Kalluru 2380722003acSSudarsana Reddy Kalluru return rc; 2381722003acSSudarsana Reddy Kalluru } 2382