1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2fe56b9e6SYuval Mintz * Copyright (c) 2015 QLogic Corporation 3fe56b9e6SYuval Mintz * 4fe56b9e6SYuval Mintz * This software is available under the terms of the GNU General Public License 5fe56b9e6SYuval Mintz * (GPL) Version 2, available from the file COPYING in the main directory of 6fe56b9e6SYuval Mintz * this source tree. 7fe56b9e6SYuval Mintz */ 8fe56b9e6SYuval Mintz 9fe56b9e6SYuval Mintz #include <linux/types.h> 10fe56b9e6SYuval Mintz #include <asm/byteorder.h> 11fe56b9e6SYuval Mintz #include <linux/io.h> 12fe56b9e6SYuval Mintz #include <linux/bitops.h> 13fe56b9e6SYuval Mintz #include <linux/delay.h> 14fe56b9e6SYuval Mintz #include <linux/dma-mapping.h> 15fe56b9e6SYuval Mintz #include <linux/errno.h> 16fe56b9e6SYuval Mintz #include <linux/interrupt.h> 17fe56b9e6SYuval Mintz #include <linux/kernel.h> 18fe56b9e6SYuval Mintz #include <linux/pci.h> 19fe56b9e6SYuval Mintz #include <linux/slab.h> 20fe56b9e6SYuval Mintz #include <linux/string.h> 21fe56b9e6SYuval Mintz #include "qed.h" 22fe56b9e6SYuval Mintz #include "qed_hsi.h" 23fe56b9e6SYuval Mintz #include "qed_hw.h" 24fe56b9e6SYuval Mintz #include "qed_init_ops.h" 25fe56b9e6SYuval Mintz #include "qed_int.h" 26fe56b9e6SYuval Mintz #include "qed_mcp.h" 27fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 28fe56b9e6SYuval Mintz #include "qed_sp.h" 29fe56b9e6SYuval Mintz 30fe56b9e6SYuval Mintz struct qed_pi_info { 31fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb; 32fe56b9e6SYuval Mintz void *cookie; 33fe56b9e6SYuval Mintz }; 34fe56b9e6SYuval Mintz 35fe56b9e6SYuval Mintz struct qed_sb_sp_info { 36fe56b9e6SYuval Mintz struct qed_sb_info sb_info; 37fe56b9e6SYuval Mintz 38fe56b9e6SYuval Mintz /* per protocol index data */ 39fe56b9e6SYuval Mintz struct qed_pi_info pi_info_arr[PIS_PER_SB]; 40fe56b9e6SYuval Mintz }; 41fe56b9e6SYuval Mintz 42ff38577aSYuval Mintz enum qed_attention_type { 43ff38577aSYuval Mintz QED_ATTN_TYPE_ATTN, 44ff38577aSYuval Mintz QED_ATTN_TYPE_PARITY, 45ff38577aSYuval Mintz }; 46ff38577aSYuval Mintz 47cc875c2eSYuval Mintz #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \ 48cc875c2eSYuval Mintz ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn) 49cc875c2eSYuval Mintz 500d956e8aSYuval Mintz struct aeu_invert_reg_bit { 510d956e8aSYuval Mintz char bit_name[30]; 520d956e8aSYuval Mintz 530d956e8aSYuval Mintz #define ATTENTION_PARITY (1 << 0) 540d956e8aSYuval Mintz 550d956e8aSYuval Mintz #define ATTENTION_LENGTH_MASK (0x00000ff0) 560d956e8aSYuval Mintz #define ATTENTION_LENGTH_SHIFT (4) 570d956e8aSYuval Mintz #define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \ 580d956e8aSYuval Mintz ATTENTION_LENGTH_SHIFT) 590d956e8aSYuval Mintz #define ATTENTION_SINGLE (1 << ATTENTION_LENGTH_SHIFT) 600d956e8aSYuval Mintz #define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY) 610d956e8aSYuval Mintz #define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \ 620d956e8aSYuval Mintz ATTENTION_PARITY) 630d956e8aSYuval Mintz 640d956e8aSYuval Mintz /* Multiple bits start with this offset */ 650d956e8aSYuval Mintz #define ATTENTION_OFFSET_MASK (0x000ff000) 660d956e8aSYuval Mintz #define ATTENTION_OFFSET_SHIFT (12) 670d956e8aSYuval Mintz unsigned int flags; 68ff38577aSYuval Mintz 69b4149dc7SYuval Mintz /* Callback to call if attention will be triggered */ 70b4149dc7SYuval Mintz int (*cb)(struct qed_hwfn *p_hwfn); 71b4149dc7SYuval Mintz 72ff38577aSYuval Mintz enum block_id block_index; 730d956e8aSYuval Mintz }; 740d956e8aSYuval Mintz 750d956e8aSYuval Mintz struct aeu_invert_reg { 760d956e8aSYuval Mintz struct aeu_invert_reg_bit bits[32]; 770d956e8aSYuval Mintz }; 780d956e8aSYuval Mintz 790d956e8aSYuval Mintz #define MAX_ATTN_GRPS (8) 800d956e8aSYuval Mintz #define NUM_ATTN_REGS (9) 810d956e8aSYuval Mintz 82ff38577aSYuval Mintz /* HW Attention register */ 83ff38577aSYuval Mintz struct attn_hw_reg { 84ff38577aSYuval Mintz u16 reg_idx; /* Index of this register in its block */ 85ff38577aSYuval Mintz u16 num_of_bits; /* number of valid attention bits */ 86ff38577aSYuval Mintz u32 sts_addr; /* Address of the STS register */ 87ff38577aSYuval Mintz u32 sts_clr_addr; /* Address of the STS_CLR register */ 88ff38577aSYuval Mintz u32 sts_wr_addr; /* Address of the STS_WR register */ 89ff38577aSYuval Mintz u32 mask_addr; /* Address of the MASK register */ 90ff38577aSYuval Mintz }; 91ff38577aSYuval Mintz 92ff38577aSYuval Mintz /* HW block attention registers */ 93ff38577aSYuval Mintz struct attn_hw_regs { 94ff38577aSYuval Mintz u16 num_of_int_regs; /* Number of interrupt regs */ 95ff38577aSYuval Mintz u16 num_of_prty_regs; /* Number of parity regs */ 96ff38577aSYuval Mintz struct attn_hw_reg **int_regs; /* interrupt regs */ 97ff38577aSYuval Mintz struct attn_hw_reg **prty_regs; /* parity regs */ 98ff38577aSYuval Mintz }; 99ff38577aSYuval Mintz 100ff38577aSYuval Mintz /* HW block attention registers */ 101ff38577aSYuval Mintz struct attn_hw_block { 102ff38577aSYuval Mintz const char *name; /* Block name */ 103ff38577aSYuval Mintz struct attn_hw_regs chip_regs[1]; 104ff38577aSYuval Mintz }; 105ff38577aSYuval Mintz 106ff38577aSYuval Mintz static struct attn_hw_reg grc_int0_bb_b0 = { 107ff38577aSYuval Mintz 0, 4, 0x50180, 0x5018c, 0x50188, 0x50184}; 108ff38577aSYuval Mintz 109ff38577aSYuval Mintz static struct attn_hw_reg *grc_int_bb_b0_regs[1] = { 110ff38577aSYuval Mintz &grc_int0_bb_b0}; 111ff38577aSYuval Mintz 112ff38577aSYuval Mintz static struct attn_hw_reg grc_prty1_bb_b0 = { 113ff38577aSYuval Mintz 0, 2, 0x50200, 0x5020c, 0x50208, 0x50204}; 114ff38577aSYuval Mintz 115ff38577aSYuval Mintz static struct attn_hw_reg *grc_prty_bb_b0_regs[1] = { 116ff38577aSYuval Mintz &grc_prty1_bb_b0}; 117ff38577aSYuval Mintz 118ff38577aSYuval Mintz static struct attn_hw_reg miscs_int0_bb_b0 = { 119ff38577aSYuval Mintz 0, 3, 0x9180, 0x918c, 0x9188, 0x9184}; 120ff38577aSYuval Mintz 121ff38577aSYuval Mintz static struct attn_hw_reg miscs_int1_bb_b0 = { 122ff38577aSYuval Mintz 1, 11, 0x9190, 0x919c, 0x9198, 0x9194}; 123ff38577aSYuval Mintz 124ff38577aSYuval Mintz static struct attn_hw_reg *miscs_int_bb_b0_regs[2] = { 125ff38577aSYuval Mintz &miscs_int0_bb_b0, &miscs_int1_bb_b0}; 126ff38577aSYuval Mintz 127ff38577aSYuval Mintz static struct attn_hw_reg miscs_prty0_bb_b0 = { 128ff38577aSYuval Mintz 0, 1, 0x91a0, 0x91ac, 0x91a8, 0x91a4}; 129ff38577aSYuval Mintz 130ff38577aSYuval Mintz static struct attn_hw_reg *miscs_prty_bb_b0_regs[1] = { 131ff38577aSYuval Mintz &miscs_prty0_bb_b0}; 132ff38577aSYuval Mintz 133ff38577aSYuval Mintz static struct attn_hw_reg misc_int0_bb_b0 = { 134ff38577aSYuval Mintz 0, 1, 0x8180, 0x818c, 0x8188, 0x8184}; 135ff38577aSYuval Mintz 136ff38577aSYuval Mintz static struct attn_hw_reg *misc_int_bb_b0_regs[1] = { 137ff38577aSYuval Mintz &misc_int0_bb_b0}; 138ff38577aSYuval Mintz 139ff38577aSYuval Mintz static struct attn_hw_reg pglue_b_int0_bb_b0 = { 140ff38577aSYuval Mintz 0, 23, 0x2a8180, 0x2a818c, 0x2a8188, 0x2a8184}; 141ff38577aSYuval Mintz 142ff38577aSYuval Mintz static struct attn_hw_reg *pglue_b_int_bb_b0_regs[1] = { 143ff38577aSYuval Mintz &pglue_b_int0_bb_b0}; 144ff38577aSYuval Mintz 145ff38577aSYuval Mintz static struct attn_hw_reg pglue_b_prty0_bb_b0 = { 146ff38577aSYuval Mintz 0, 1, 0x2a8190, 0x2a819c, 0x2a8198, 0x2a8194}; 147ff38577aSYuval Mintz 148ff38577aSYuval Mintz static struct attn_hw_reg pglue_b_prty1_bb_b0 = { 149ff38577aSYuval Mintz 1, 22, 0x2a8200, 0x2a820c, 0x2a8208, 0x2a8204}; 150ff38577aSYuval Mintz 151ff38577aSYuval Mintz static struct attn_hw_reg *pglue_b_prty_bb_b0_regs[2] = { 152ff38577aSYuval Mintz &pglue_b_prty0_bb_b0, &pglue_b_prty1_bb_b0}; 153ff38577aSYuval Mintz 154ff38577aSYuval Mintz static struct attn_hw_reg cnig_int0_bb_b0 = { 155ff38577aSYuval Mintz 0, 6, 0x2182e8, 0x2182f4, 0x2182f0, 0x2182ec}; 156ff38577aSYuval Mintz 157ff38577aSYuval Mintz static struct attn_hw_reg *cnig_int_bb_b0_regs[1] = { 158ff38577aSYuval Mintz &cnig_int0_bb_b0}; 159ff38577aSYuval Mintz 160ff38577aSYuval Mintz static struct attn_hw_reg cnig_prty0_bb_b0 = { 161ff38577aSYuval Mintz 0, 2, 0x218348, 0x218354, 0x218350, 0x21834c}; 162ff38577aSYuval Mintz 163ff38577aSYuval Mintz static struct attn_hw_reg *cnig_prty_bb_b0_regs[1] = { 164ff38577aSYuval Mintz &cnig_prty0_bb_b0}; 165ff38577aSYuval Mintz 166ff38577aSYuval Mintz static struct attn_hw_reg cpmu_int0_bb_b0 = { 167ff38577aSYuval Mintz 0, 1, 0x303e0, 0x303ec, 0x303e8, 0x303e4}; 168ff38577aSYuval Mintz 169ff38577aSYuval Mintz static struct attn_hw_reg *cpmu_int_bb_b0_regs[1] = { 170ff38577aSYuval Mintz &cpmu_int0_bb_b0}; 171ff38577aSYuval Mintz 172ff38577aSYuval Mintz static struct attn_hw_reg ncsi_int0_bb_b0 = { 173ff38577aSYuval Mintz 0, 1, 0x404cc, 0x404d8, 0x404d4, 0x404d0}; 174ff38577aSYuval Mintz 175ff38577aSYuval Mintz static struct attn_hw_reg *ncsi_int_bb_b0_regs[1] = { 176ff38577aSYuval Mintz &ncsi_int0_bb_b0}; 177ff38577aSYuval Mintz 178ff38577aSYuval Mintz static struct attn_hw_reg ncsi_prty1_bb_b0 = { 179ff38577aSYuval Mintz 0, 1, 0x40000, 0x4000c, 0x40008, 0x40004}; 180ff38577aSYuval Mintz 181ff38577aSYuval Mintz static struct attn_hw_reg *ncsi_prty_bb_b0_regs[1] = { 182ff38577aSYuval Mintz &ncsi_prty1_bb_b0}; 183ff38577aSYuval Mintz 184ff38577aSYuval Mintz static struct attn_hw_reg opte_prty1_bb_b0 = { 185ff38577aSYuval Mintz 0, 11, 0x53000, 0x5300c, 0x53008, 0x53004}; 186ff38577aSYuval Mintz 187ff38577aSYuval Mintz static struct attn_hw_reg opte_prty0_bb_b0 = { 188ff38577aSYuval Mintz 1, 1, 0x53208, 0x53214, 0x53210, 0x5320c}; 189ff38577aSYuval Mintz 190ff38577aSYuval Mintz static struct attn_hw_reg *opte_prty_bb_b0_regs[2] = { 191ff38577aSYuval Mintz &opte_prty1_bb_b0, &opte_prty0_bb_b0}; 192ff38577aSYuval Mintz 193ff38577aSYuval Mintz static struct attn_hw_reg bmb_int0_bb_b0 = { 194ff38577aSYuval Mintz 0, 16, 0x5400c0, 0x5400cc, 0x5400c8, 0x5400c4}; 195ff38577aSYuval Mintz 196ff38577aSYuval Mintz static struct attn_hw_reg bmb_int1_bb_b0 = { 197ff38577aSYuval Mintz 1, 28, 0x5400d8, 0x5400e4, 0x5400e0, 0x5400dc}; 198ff38577aSYuval Mintz 199ff38577aSYuval Mintz static struct attn_hw_reg bmb_int2_bb_b0 = { 200ff38577aSYuval Mintz 2, 26, 0x5400f0, 0x5400fc, 0x5400f8, 0x5400f4}; 201ff38577aSYuval Mintz 202ff38577aSYuval Mintz static struct attn_hw_reg bmb_int3_bb_b0 = { 203ff38577aSYuval Mintz 3, 31, 0x540108, 0x540114, 0x540110, 0x54010c}; 204ff38577aSYuval Mintz 205ff38577aSYuval Mintz static struct attn_hw_reg bmb_int4_bb_b0 = { 206ff38577aSYuval Mintz 4, 27, 0x540120, 0x54012c, 0x540128, 0x540124}; 207ff38577aSYuval Mintz 208ff38577aSYuval Mintz static struct attn_hw_reg bmb_int5_bb_b0 = { 209ff38577aSYuval Mintz 5, 29, 0x540138, 0x540144, 0x540140, 0x54013c}; 210ff38577aSYuval Mintz 211ff38577aSYuval Mintz static struct attn_hw_reg bmb_int6_bb_b0 = { 212ff38577aSYuval Mintz 6, 30, 0x540150, 0x54015c, 0x540158, 0x540154}; 213ff38577aSYuval Mintz 214ff38577aSYuval Mintz static struct attn_hw_reg bmb_int7_bb_b0 = { 215ff38577aSYuval Mintz 7, 32, 0x540168, 0x540174, 0x540170, 0x54016c}; 216ff38577aSYuval Mintz 217ff38577aSYuval Mintz static struct attn_hw_reg bmb_int8_bb_b0 = { 218ff38577aSYuval Mintz 8, 32, 0x540184, 0x540190, 0x54018c, 0x540188}; 219ff38577aSYuval Mintz 220ff38577aSYuval Mintz static struct attn_hw_reg bmb_int9_bb_b0 = { 221ff38577aSYuval Mintz 9, 32, 0x54019c, 0x5401a8, 0x5401a4, 0x5401a0}; 222ff38577aSYuval Mintz 223ff38577aSYuval Mintz static struct attn_hw_reg bmb_int10_bb_b0 = { 224ff38577aSYuval Mintz 10, 3, 0x5401b4, 0x5401c0, 0x5401bc, 0x5401b8}; 225ff38577aSYuval Mintz 226ff38577aSYuval Mintz static struct attn_hw_reg bmb_int11_bb_b0 = { 227ff38577aSYuval Mintz 11, 4, 0x5401cc, 0x5401d8, 0x5401d4, 0x5401d0}; 228ff38577aSYuval Mintz 229ff38577aSYuval Mintz static struct attn_hw_reg *bmb_int_bb_b0_regs[12] = { 230ff38577aSYuval Mintz &bmb_int0_bb_b0, &bmb_int1_bb_b0, &bmb_int2_bb_b0, &bmb_int3_bb_b0, 231ff38577aSYuval Mintz &bmb_int4_bb_b0, &bmb_int5_bb_b0, &bmb_int6_bb_b0, &bmb_int7_bb_b0, 232ff38577aSYuval Mintz &bmb_int8_bb_b0, &bmb_int9_bb_b0, &bmb_int10_bb_b0, &bmb_int11_bb_b0}; 233ff38577aSYuval Mintz 234ff38577aSYuval Mintz static struct attn_hw_reg bmb_prty0_bb_b0 = { 235ff38577aSYuval Mintz 0, 5, 0x5401dc, 0x5401e8, 0x5401e4, 0x5401e0}; 236ff38577aSYuval Mintz 237ff38577aSYuval Mintz static struct attn_hw_reg bmb_prty1_bb_b0 = { 238ff38577aSYuval Mintz 1, 31, 0x540400, 0x54040c, 0x540408, 0x540404}; 239ff38577aSYuval Mintz 240ff38577aSYuval Mintz static struct attn_hw_reg bmb_prty2_bb_b0 = { 241ff38577aSYuval Mintz 2, 15, 0x540410, 0x54041c, 0x540418, 0x540414}; 242ff38577aSYuval Mintz 243ff38577aSYuval Mintz static struct attn_hw_reg *bmb_prty_bb_b0_regs[3] = { 244ff38577aSYuval Mintz &bmb_prty0_bb_b0, &bmb_prty1_bb_b0, &bmb_prty2_bb_b0}; 245ff38577aSYuval Mintz 246ff38577aSYuval Mintz static struct attn_hw_reg pcie_prty1_bb_b0 = { 247ff38577aSYuval Mintz 0, 17, 0x54000, 0x5400c, 0x54008, 0x54004}; 248ff38577aSYuval Mintz 249ff38577aSYuval Mintz static struct attn_hw_reg *pcie_prty_bb_b0_regs[1] = { 250ff38577aSYuval Mintz &pcie_prty1_bb_b0}; 251ff38577aSYuval Mintz 252ff38577aSYuval Mintz static struct attn_hw_reg mcp2_prty0_bb_b0 = { 253ff38577aSYuval Mintz 0, 1, 0x52040, 0x5204c, 0x52048, 0x52044}; 254ff38577aSYuval Mintz 255ff38577aSYuval Mintz static struct attn_hw_reg mcp2_prty1_bb_b0 = { 256ff38577aSYuval Mintz 1, 12, 0x52204, 0x52210, 0x5220c, 0x52208}; 257ff38577aSYuval Mintz 258ff38577aSYuval Mintz static struct attn_hw_reg *mcp2_prty_bb_b0_regs[2] = { 259ff38577aSYuval Mintz &mcp2_prty0_bb_b0, &mcp2_prty1_bb_b0}; 260ff38577aSYuval Mintz 261ff38577aSYuval Mintz static struct attn_hw_reg pswhst_int0_bb_b0 = { 262ff38577aSYuval Mintz 0, 18, 0x2a0180, 0x2a018c, 0x2a0188, 0x2a0184}; 263ff38577aSYuval Mintz 264ff38577aSYuval Mintz static struct attn_hw_reg *pswhst_int_bb_b0_regs[1] = { 265ff38577aSYuval Mintz &pswhst_int0_bb_b0}; 266ff38577aSYuval Mintz 267ff38577aSYuval Mintz static struct attn_hw_reg pswhst_prty0_bb_b0 = { 268ff38577aSYuval Mintz 0, 1, 0x2a0190, 0x2a019c, 0x2a0198, 0x2a0194}; 269ff38577aSYuval Mintz 270ff38577aSYuval Mintz static struct attn_hw_reg pswhst_prty1_bb_b0 = { 271ff38577aSYuval Mintz 1, 17, 0x2a0200, 0x2a020c, 0x2a0208, 0x2a0204}; 272ff38577aSYuval Mintz 273ff38577aSYuval Mintz static struct attn_hw_reg *pswhst_prty_bb_b0_regs[2] = { 274ff38577aSYuval Mintz &pswhst_prty0_bb_b0, &pswhst_prty1_bb_b0}; 275ff38577aSYuval Mintz 276ff38577aSYuval Mintz static struct attn_hw_reg pswhst2_int0_bb_b0 = { 277ff38577aSYuval Mintz 0, 5, 0x29e180, 0x29e18c, 0x29e188, 0x29e184}; 278ff38577aSYuval Mintz 279ff38577aSYuval Mintz static struct attn_hw_reg *pswhst2_int_bb_b0_regs[1] = { 280ff38577aSYuval Mintz &pswhst2_int0_bb_b0}; 281ff38577aSYuval Mintz 282ff38577aSYuval Mintz static struct attn_hw_reg pswhst2_prty0_bb_b0 = { 283ff38577aSYuval Mintz 0, 1, 0x29e190, 0x29e19c, 0x29e198, 0x29e194}; 284ff38577aSYuval Mintz 285ff38577aSYuval Mintz static struct attn_hw_reg *pswhst2_prty_bb_b0_regs[1] = { 286ff38577aSYuval Mintz &pswhst2_prty0_bb_b0}; 287ff38577aSYuval Mintz 288ff38577aSYuval Mintz static struct attn_hw_reg pswrd_int0_bb_b0 = { 289ff38577aSYuval Mintz 0, 3, 0x29c180, 0x29c18c, 0x29c188, 0x29c184}; 290ff38577aSYuval Mintz 291ff38577aSYuval Mintz static struct attn_hw_reg *pswrd_int_bb_b0_regs[1] = { 292ff38577aSYuval Mintz &pswrd_int0_bb_b0}; 293ff38577aSYuval Mintz 294ff38577aSYuval Mintz static struct attn_hw_reg pswrd_prty0_bb_b0 = { 295ff38577aSYuval Mintz 0, 1, 0x29c190, 0x29c19c, 0x29c198, 0x29c194}; 296ff38577aSYuval Mintz 297ff38577aSYuval Mintz static struct attn_hw_reg *pswrd_prty_bb_b0_regs[1] = { 298ff38577aSYuval Mintz &pswrd_prty0_bb_b0}; 299ff38577aSYuval Mintz 300ff38577aSYuval Mintz static struct attn_hw_reg pswrd2_int0_bb_b0 = { 301ff38577aSYuval Mintz 0, 5, 0x29d180, 0x29d18c, 0x29d188, 0x29d184}; 302ff38577aSYuval Mintz 303ff38577aSYuval Mintz static struct attn_hw_reg *pswrd2_int_bb_b0_regs[1] = { 304ff38577aSYuval Mintz &pswrd2_int0_bb_b0}; 305ff38577aSYuval Mintz 306ff38577aSYuval Mintz static struct attn_hw_reg pswrd2_prty0_bb_b0 = { 307ff38577aSYuval Mintz 0, 1, 0x29d190, 0x29d19c, 0x29d198, 0x29d194}; 308ff38577aSYuval Mintz 309ff38577aSYuval Mintz static struct attn_hw_reg pswrd2_prty1_bb_b0 = { 310ff38577aSYuval Mintz 1, 31, 0x29d200, 0x29d20c, 0x29d208, 0x29d204}; 311ff38577aSYuval Mintz 312ff38577aSYuval Mintz static struct attn_hw_reg pswrd2_prty2_bb_b0 = { 313ff38577aSYuval Mintz 2, 3, 0x29d210, 0x29d21c, 0x29d218, 0x29d214}; 314ff38577aSYuval Mintz 315ff38577aSYuval Mintz static struct attn_hw_reg *pswrd2_prty_bb_b0_regs[3] = { 316ff38577aSYuval Mintz &pswrd2_prty0_bb_b0, &pswrd2_prty1_bb_b0, &pswrd2_prty2_bb_b0}; 317ff38577aSYuval Mintz 318ff38577aSYuval Mintz static struct attn_hw_reg pswwr_int0_bb_b0 = { 319ff38577aSYuval Mintz 0, 16, 0x29a180, 0x29a18c, 0x29a188, 0x29a184}; 320ff38577aSYuval Mintz 321ff38577aSYuval Mintz static struct attn_hw_reg *pswwr_int_bb_b0_regs[1] = { 322ff38577aSYuval Mintz &pswwr_int0_bb_b0}; 323ff38577aSYuval Mintz 324ff38577aSYuval Mintz static struct attn_hw_reg pswwr_prty0_bb_b0 = { 325ff38577aSYuval Mintz 0, 1, 0x29a190, 0x29a19c, 0x29a198, 0x29a194}; 326ff38577aSYuval Mintz 327ff38577aSYuval Mintz static struct attn_hw_reg *pswwr_prty_bb_b0_regs[1] = { 328ff38577aSYuval Mintz &pswwr_prty0_bb_b0}; 329ff38577aSYuval Mintz 330ff38577aSYuval Mintz static struct attn_hw_reg pswwr2_int0_bb_b0 = { 331ff38577aSYuval Mintz 0, 19, 0x29b180, 0x29b18c, 0x29b188, 0x29b184}; 332ff38577aSYuval Mintz 333ff38577aSYuval Mintz static struct attn_hw_reg *pswwr2_int_bb_b0_regs[1] = { 334ff38577aSYuval Mintz &pswwr2_int0_bb_b0}; 335ff38577aSYuval Mintz 336ff38577aSYuval Mintz static struct attn_hw_reg pswwr2_prty0_bb_b0 = { 337ff38577aSYuval Mintz 0, 1, 0x29b190, 0x29b19c, 0x29b198, 0x29b194}; 338ff38577aSYuval Mintz 339ff38577aSYuval Mintz static struct attn_hw_reg pswwr2_prty1_bb_b0 = { 340ff38577aSYuval Mintz 1, 31, 0x29b200, 0x29b20c, 0x29b208, 0x29b204}; 341ff38577aSYuval Mintz 342ff38577aSYuval Mintz static struct attn_hw_reg pswwr2_prty2_bb_b0 = { 343ff38577aSYuval Mintz 2, 31, 0x29b210, 0x29b21c, 0x29b218, 0x29b214}; 344ff38577aSYuval Mintz 345ff38577aSYuval Mintz static struct attn_hw_reg pswwr2_prty3_bb_b0 = { 346ff38577aSYuval Mintz 3, 31, 0x29b220, 0x29b22c, 0x29b228, 0x29b224}; 347ff38577aSYuval Mintz 348ff38577aSYuval Mintz static struct attn_hw_reg pswwr2_prty4_bb_b0 = { 349ff38577aSYuval Mintz 4, 20, 0x29b230, 0x29b23c, 0x29b238, 0x29b234}; 350ff38577aSYuval Mintz 351ff38577aSYuval Mintz static struct attn_hw_reg *pswwr2_prty_bb_b0_regs[5] = { 352ff38577aSYuval Mintz &pswwr2_prty0_bb_b0, &pswwr2_prty1_bb_b0, &pswwr2_prty2_bb_b0, 353ff38577aSYuval Mintz &pswwr2_prty3_bb_b0, &pswwr2_prty4_bb_b0}; 354ff38577aSYuval Mintz 355ff38577aSYuval Mintz static struct attn_hw_reg pswrq_int0_bb_b0 = { 356ff38577aSYuval Mintz 0, 21, 0x280180, 0x28018c, 0x280188, 0x280184}; 357ff38577aSYuval Mintz 358ff38577aSYuval Mintz static struct attn_hw_reg *pswrq_int_bb_b0_regs[1] = { 359ff38577aSYuval Mintz &pswrq_int0_bb_b0}; 360ff38577aSYuval Mintz 361ff38577aSYuval Mintz static struct attn_hw_reg pswrq_prty0_bb_b0 = { 362ff38577aSYuval Mintz 0, 1, 0x280190, 0x28019c, 0x280198, 0x280194}; 363ff38577aSYuval Mintz 364ff38577aSYuval Mintz static struct attn_hw_reg *pswrq_prty_bb_b0_regs[1] = { 365ff38577aSYuval Mintz &pswrq_prty0_bb_b0}; 366ff38577aSYuval Mintz 367ff38577aSYuval Mintz static struct attn_hw_reg pswrq2_int0_bb_b0 = { 368ff38577aSYuval Mintz 0, 15, 0x240180, 0x24018c, 0x240188, 0x240184}; 369ff38577aSYuval Mintz 370ff38577aSYuval Mintz static struct attn_hw_reg *pswrq2_int_bb_b0_regs[1] = { 371ff38577aSYuval Mintz &pswrq2_int0_bb_b0}; 372ff38577aSYuval Mintz 373ff38577aSYuval Mintz static struct attn_hw_reg pswrq2_prty1_bb_b0 = { 374ff38577aSYuval Mintz 0, 9, 0x240200, 0x24020c, 0x240208, 0x240204}; 375ff38577aSYuval Mintz 376ff38577aSYuval Mintz static struct attn_hw_reg *pswrq2_prty_bb_b0_regs[1] = { 377ff38577aSYuval Mintz &pswrq2_prty1_bb_b0}; 378ff38577aSYuval Mintz 379ff38577aSYuval Mintz static struct attn_hw_reg pglcs_int0_bb_b0 = { 380ff38577aSYuval Mintz 0, 1, 0x1d00, 0x1d0c, 0x1d08, 0x1d04}; 381ff38577aSYuval Mintz 382ff38577aSYuval Mintz static struct attn_hw_reg *pglcs_int_bb_b0_regs[1] = { 383ff38577aSYuval Mintz &pglcs_int0_bb_b0}; 384ff38577aSYuval Mintz 385ff38577aSYuval Mintz static struct attn_hw_reg dmae_int0_bb_b0 = { 386ff38577aSYuval Mintz 0, 2, 0xc180, 0xc18c, 0xc188, 0xc184}; 387ff38577aSYuval Mintz 388ff38577aSYuval Mintz static struct attn_hw_reg *dmae_int_bb_b0_regs[1] = { 389ff38577aSYuval Mintz &dmae_int0_bb_b0}; 390ff38577aSYuval Mintz 391ff38577aSYuval Mintz static struct attn_hw_reg dmae_prty1_bb_b0 = { 392ff38577aSYuval Mintz 0, 3, 0xc200, 0xc20c, 0xc208, 0xc204}; 393ff38577aSYuval Mintz 394ff38577aSYuval Mintz static struct attn_hw_reg *dmae_prty_bb_b0_regs[1] = { 395ff38577aSYuval Mintz &dmae_prty1_bb_b0}; 396ff38577aSYuval Mintz 397ff38577aSYuval Mintz static struct attn_hw_reg ptu_int0_bb_b0 = { 398ff38577aSYuval Mintz 0, 8, 0x560180, 0x56018c, 0x560188, 0x560184}; 399ff38577aSYuval Mintz 400ff38577aSYuval Mintz static struct attn_hw_reg *ptu_int_bb_b0_regs[1] = { 401ff38577aSYuval Mintz &ptu_int0_bb_b0}; 402ff38577aSYuval Mintz 403ff38577aSYuval Mintz static struct attn_hw_reg ptu_prty1_bb_b0 = { 404ff38577aSYuval Mintz 0, 18, 0x560200, 0x56020c, 0x560208, 0x560204}; 405ff38577aSYuval Mintz 406ff38577aSYuval Mintz static struct attn_hw_reg *ptu_prty_bb_b0_regs[1] = { 407ff38577aSYuval Mintz &ptu_prty1_bb_b0}; 408ff38577aSYuval Mintz 409ff38577aSYuval Mintz static struct attn_hw_reg tcm_int0_bb_b0 = { 410ff38577aSYuval Mintz 0, 8, 0x1180180, 0x118018c, 0x1180188, 0x1180184}; 411ff38577aSYuval Mintz 412ff38577aSYuval Mintz static struct attn_hw_reg tcm_int1_bb_b0 = { 413ff38577aSYuval Mintz 1, 32, 0x1180190, 0x118019c, 0x1180198, 0x1180194}; 414ff38577aSYuval Mintz 415ff38577aSYuval Mintz static struct attn_hw_reg tcm_int2_bb_b0 = { 416ff38577aSYuval Mintz 2, 1, 0x11801a0, 0x11801ac, 0x11801a8, 0x11801a4}; 417ff38577aSYuval Mintz 418ff38577aSYuval Mintz static struct attn_hw_reg *tcm_int_bb_b0_regs[3] = { 419ff38577aSYuval Mintz &tcm_int0_bb_b0, &tcm_int1_bb_b0, &tcm_int2_bb_b0}; 420ff38577aSYuval Mintz 421ff38577aSYuval Mintz static struct attn_hw_reg tcm_prty1_bb_b0 = { 422ff38577aSYuval Mintz 0, 31, 0x1180200, 0x118020c, 0x1180208, 0x1180204}; 423ff38577aSYuval Mintz 424ff38577aSYuval Mintz static struct attn_hw_reg tcm_prty2_bb_b0 = { 425ff38577aSYuval Mintz 1, 2, 0x1180210, 0x118021c, 0x1180218, 0x1180214}; 426ff38577aSYuval Mintz 427ff38577aSYuval Mintz static struct attn_hw_reg *tcm_prty_bb_b0_regs[2] = { 428ff38577aSYuval Mintz &tcm_prty1_bb_b0, &tcm_prty2_bb_b0}; 429ff38577aSYuval Mintz 430ff38577aSYuval Mintz static struct attn_hw_reg mcm_int0_bb_b0 = { 431ff38577aSYuval Mintz 0, 14, 0x1200180, 0x120018c, 0x1200188, 0x1200184}; 432ff38577aSYuval Mintz 433ff38577aSYuval Mintz static struct attn_hw_reg mcm_int1_bb_b0 = { 434ff38577aSYuval Mintz 1, 26, 0x1200190, 0x120019c, 0x1200198, 0x1200194}; 435ff38577aSYuval Mintz 436ff38577aSYuval Mintz static struct attn_hw_reg mcm_int2_bb_b0 = { 437ff38577aSYuval Mintz 2, 1, 0x12001a0, 0x12001ac, 0x12001a8, 0x12001a4}; 438ff38577aSYuval Mintz 439ff38577aSYuval Mintz static struct attn_hw_reg *mcm_int_bb_b0_regs[3] = { 440ff38577aSYuval Mintz &mcm_int0_bb_b0, &mcm_int1_bb_b0, &mcm_int2_bb_b0}; 441ff38577aSYuval Mintz 442ff38577aSYuval Mintz static struct attn_hw_reg mcm_prty1_bb_b0 = { 443ff38577aSYuval Mintz 0, 31, 0x1200200, 0x120020c, 0x1200208, 0x1200204}; 444ff38577aSYuval Mintz 445ff38577aSYuval Mintz static struct attn_hw_reg mcm_prty2_bb_b0 = { 446ff38577aSYuval Mintz 1, 4, 0x1200210, 0x120021c, 0x1200218, 0x1200214}; 447ff38577aSYuval Mintz 448ff38577aSYuval Mintz static struct attn_hw_reg *mcm_prty_bb_b0_regs[2] = { 449ff38577aSYuval Mintz &mcm_prty1_bb_b0, &mcm_prty2_bb_b0}; 450ff38577aSYuval Mintz 451ff38577aSYuval Mintz static struct attn_hw_reg ucm_int0_bb_b0 = { 452ff38577aSYuval Mintz 0, 17, 0x1280180, 0x128018c, 0x1280188, 0x1280184}; 453ff38577aSYuval Mintz 454ff38577aSYuval Mintz static struct attn_hw_reg ucm_int1_bb_b0 = { 455ff38577aSYuval Mintz 1, 29, 0x1280190, 0x128019c, 0x1280198, 0x1280194}; 456ff38577aSYuval Mintz 457ff38577aSYuval Mintz static struct attn_hw_reg ucm_int2_bb_b0 = { 458ff38577aSYuval Mintz 2, 1, 0x12801a0, 0x12801ac, 0x12801a8, 0x12801a4}; 459ff38577aSYuval Mintz 460ff38577aSYuval Mintz static struct attn_hw_reg *ucm_int_bb_b0_regs[3] = { 461ff38577aSYuval Mintz &ucm_int0_bb_b0, &ucm_int1_bb_b0, &ucm_int2_bb_b0}; 462ff38577aSYuval Mintz 463ff38577aSYuval Mintz static struct attn_hw_reg ucm_prty1_bb_b0 = { 464ff38577aSYuval Mintz 0, 31, 0x1280200, 0x128020c, 0x1280208, 0x1280204}; 465ff38577aSYuval Mintz 466ff38577aSYuval Mintz static struct attn_hw_reg ucm_prty2_bb_b0 = { 467ff38577aSYuval Mintz 1, 7, 0x1280210, 0x128021c, 0x1280218, 0x1280214}; 468ff38577aSYuval Mintz 469ff38577aSYuval Mintz static struct attn_hw_reg *ucm_prty_bb_b0_regs[2] = { 470ff38577aSYuval Mintz &ucm_prty1_bb_b0, &ucm_prty2_bb_b0}; 471ff38577aSYuval Mintz 472ff38577aSYuval Mintz static struct attn_hw_reg xcm_int0_bb_b0 = { 473ff38577aSYuval Mintz 0, 16, 0x1000180, 0x100018c, 0x1000188, 0x1000184}; 474ff38577aSYuval Mintz 475ff38577aSYuval Mintz static struct attn_hw_reg xcm_int1_bb_b0 = { 476ff38577aSYuval Mintz 1, 25, 0x1000190, 0x100019c, 0x1000198, 0x1000194}; 477ff38577aSYuval Mintz 478ff38577aSYuval Mintz static struct attn_hw_reg xcm_int2_bb_b0 = { 479ff38577aSYuval Mintz 2, 8, 0x10001a0, 0x10001ac, 0x10001a8, 0x10001a4}; 480ff38577aSYuval Mintz 481ff38577aSYuval Mintz static struct attn_hw_reg *xcm_int_bb_b0_regs[3] = { 482ff38577aSYuval Mintz &xcm_int0_bb_b0, &xcm_int1_bb_b0, &xcm_int2_bb_b0}; 483ff38577aSYuval Mintz 484ff38577aSYuval Mintz static struct attn_hw_reg xcm_prty1_bb_b0 = { 485ff38577aSYuval Mintz 0, 31, 0x1000200, 0x100020c, 0x1000208, 0x1000204}; 486ff38577aSYuval Mintz 487ff38577aSYuval Mintz static struct attn_hw_reg xcm_prty2_bb_b0 = { 488ff38577aSYuval Mintz 1, 11, 0x1000210, 0x100021c, 0x1000218, 0x1000214}; 489ff38577aSYuval Mintz 490ff38577aSYuval Mintz static struct attn_hw_reg *xcm_prty_bb_b0_regs[2] = { 491ff38577aSYuval Mintz &xcm_prty1_bb_b0, &xcm_prty2_bb_b0}; 492ff38577aSYuval Mintz 493ff38577aSYuval Mintz static struct attn_hw_reg ycm_int0_bb_b0 = { 494ff38577aSYuval Mintz 0, 13, 0x1080180, 0x108018c, 0x1080188, 0x1080184}; 495ff38577aSYuval Mintz 496ff38577aSYuval Mintz static struct attn_hw_reg ycm_int1_bb_b0 = { 497ff38577aSYuval Mintz 1, 23, 0x1080190, 0x108019c, 0x1080198, 0x1080194}; 498ff38577aSYuval Mintz 499ff38577aSYuval Mintz static struct attn_hw_reg ycm_int2_bb_b0 = { 500ff38577aSYuval Mintz 2, 1, 0x10801a0, 0x10801ac, 0x10801a8, 0x10801a4}; 501ff38577aSYuval Mintz 502ff38577aSYuval Mintz static struct attn_hw_reg *ycm_int_bb_b0_regs[3] = { 503ff38577aSYuval Mintz &ycm_int0_bb_b0, &ycm_int1_bb_b0, &ycm_int2_bb_b0}; 504ff38577aSYuval Mintz 505ff38577aSYuval Mintz static struct attn_hw_reg ycm_prty1_bb_b0 = { 506ff38577aSYuval Mintz 0, 31, 0x1080200, 0x108020c, 0x1080208, 0x1080204}; 507ff38577aSYuval Mintz 508ff38577aSYuval Mintz static struct attn_hw_reg ycm_prty2_bb_b0 = { 509ff38577aSYuval Mintz 1, 3, 0x1080210, 0x108021c, 0x1080218, 0x1080214}; 510ff38577aSYuval Mintz 511ff38577aSYuval Mintz static struct attn_hw_reg *ycm_prty_bb_b0_regs[2] = { 512ff38577aSYuval Mintz &ycm_prty1_bb_b0, &ycm_prty2_bb_b0}; 513ff38577aSYuval Mintz 514ff38577aSYuval Mintz static struct attn_hw_reg pcm_int0_bb_b0 = { 515ff38577aSYuval Mintz 0, 5, 0x1100180, 0x110018c, 0x1100188, 0x1100184}; 516ff38577aSYuval Mintz 517ff38577aSYuval Mintz static struct attn_hw_reg pcm_int1_bb_b0 = { 518ff38577aSYuval Mintz 1, 14, 0x1100190, 0x110019c, 0x1100198, 0x1100194}; 519ff38577aSYuval Mintz 520ff38577aSYuval Mintz static struct attn_hw_reg pcm_int2_bb_b0 = { 521ff38577aSYuval Mintz 2, 1, 0x11001a0, 0x11001ac, 0x11001a8, 0x11001a4}; 522ff38577aSYuval Mintz 523ff38577aSYuval Mintz static struct attn_hw_reg *pcm_int_bb_b0_regs[3] = { 524ff38577aSYuval Mintz &pcm_int0_bb_b0, &pcm_int1_bb_b0, &pcm_int2_bb_b0}; 525ff38577aSYuval Mintz 526ff38577aSYuval Mintz static struct attn_hw_reg pcm_prty1_bb_b0 = { 527ff38577aSYuval Mintz 0, 11, 0x1100200, 0x110020c, 0x1100208, 0x1100204}; 528ff38577aSYuval Mintz 529ff38577aSYuval Mintz static struct attn_hw_reg *pcm_prty_bb_b0_regs[1] = { 530ff38577aSYuval Mintz &pcm_prty1_bb_b0}; 531ff38577aSYuval Mintz 532ff38577aSYuval Mintz static struct attn_hw_reg qm_int0_bb_b0 = { 533ff38577aSYuval Mintz 0, 22, 0x2f0180, 0x2f018c, 0x2f0188, 0x2f0184}; 534ff38577aSYuval Mintz 535ff38577aSYuval Mintz static struct attn_hw_reg *qm_int_bb_b0_regs[1] = { 536ff38577aSYuval Mintz &qm_int0_bb_b0}; 537ff38577aSYuval Mintz 538ff38577aSYuval Mintz static struct attn_hw_reg qm_prty0_bb_b0 = { 539ff38577aSYuval Mintz 0, 11, 0x2f0190, 0x2f019c, 0x2f0198, 0x2f0194}; 540ff38577aSYuval Mintz 541ff38577aSYuval Mintz static struct attn_hw_reg qm_prty1_bb_b0 = { 542ff38577aSYuval Mintz 1, 31, 0x2f0200, 0x2f020c, 0x2f0208, 0x2f0204}; 543ff38577aSYuval Mintz 544ff38577aSYuval Mintz static struct attn_hw_reg qm_prty2_bb_b0 = { 545ff38577aSYuval Mintz 2, 31, 0x2f0210, 0x2f021c, 0x2f0218, 0x2f0214}; 546ff38577aSYuval Mintz 547ff38577aSYuval Mintz static struct attn_hw_reg qm_prty3_bb_b0 = { 548ff38577aSYuval Mintz 3, 11, 0x2f0220, 0x2f022c, 0x2f0228, 0x2f0224}; 549ff38577aSYuval Mintz 550ff38577aSYuval Mintz static struct attn_hw_reg *qm_prty_bb_b0_regs[4] = { 551ff38577aSYuval Mintz &qm_prty0_bb_b0, &qm_prty1_bb_b0, &qm_prty2_bb_b0, &qm_prty3_bb_b0}; 552ff38577aSYuval Mintz 553ff38577aSYuval Mintz static struct attn_hw_reg tm_int0_bb_b0 = { 554ff38577aSYuval Mintz 0, 32, 0x2c0180, 0x2c018c, 0x2c0188, 0x2c0184}; 555ff38577aSYuval Mintz 556ff38577aSYuval Mintz static struct attn_hw_reg tm_int1_bb_b0 = { 557ff38577aSYuval Mintz 1, 11, 0x2c0190, 0x2c019c, 0x2c0198, 0x2c0194}; 558ff38577aSYuval Mintz 559ff38577aSYuval Mintz static struct attn_hw_reg *tm_int_bb_b0_regs[2] = { 560ff38577aSYuval Mintz &tm_int0_bb_b0, &tm_int1_bb_b0}; 561ff38577aSYuval Mintz 562ff38577aSYuval Mintz static struct attn_hw_reg tm_prty1_bb_b0 = { 563ff38577aSYuval Mintz 0, 17, 0x2c0200, 0x2c020c, 0x2c0208, 0x2c0204}; 564ff38577aSYuval Mintz 565ff38577aSYuval Mintz static struct attn_hw_reg *tm_prty_bb_b0_regs[1] = { 566ff38577aSYuval Mintz &tm_prty1_bb_b0}; 567ff38577aSYuval Mintz 568ff38577aSYuval Mintz static struct attn_hw_reg dorq_int0_bb_b0 = { 569ff38577aSYuval Mintz 0, 9, 0x100180, 0x10018c, 0x100188, 0x100184}; 570ff38577aSYuval Mintz 571ff38577aSYuval Mintz static struct attn_hw_reg *dorq_int_bb_b0_regs[1] = { 572ff38577aSYuval Mintz &dorq_int0_bb_b0}; 573ff38577aSYuval Mintz 574ff38577aSYuval Mintz static struct attn_hw_reg dorq_prty0_bb_b0 = { 575ff38577aSYuval Mintz 0, 1, 0x100190, 0x10019c, 0x100198, 0x100194}; 576ff38577aSYuval Mintz 577ff38577aSYuval Mintz static struct attn_hw_reg dorq_prty1_bb_b0 = { 578ff38577aSYuval Mintz 1, 6, 0x100200, 0x10020c, 0x100208, 0x100204}; 579ff38577aSYuval Mintz 580ff38577aSYuval Mintz static struct attn_hw_reg *dorq_prty_bb_b0_regs[2] = { 581ff38577aSYuval Mintz &dorq_prty0_bb_b0, &dorq_prty1_bb_b0}; 582ff38577aSYuval Mintz 583ff38577aSYuval Mintz static struct attn_hw_reg brb_int0_bb_b0 = { 584ff38577aSYuval Mintz 0, 32, 0x3400c0, 0x3400cc, 0x3400c8, 0x3400c4}; 585ff38577aSYuval Mintz 586ff38577aSYuval Mintz static struct attn_hw_reg brb_int1_bb_b0 = { 587ff38577aSYuval Mintz 1, 30, 0x3400d8, 0x3400e4, 0x3400e0, 0x3400dc}; 588ff38577aSYuval Mintz 589ff38577aSYuval Mintz static struct attn_hw_reg brb_int2_bb_b0 = { 590ff38577aSYuval Mintz 2, 28, 0x3400f0, 0x3400fc, 0x3400f8, 0x3400f4}; 591ff38577aSYuval Mintz 592ff38577aSYuval Mintz static struct attn_hw_reg brb_int3_bb_b0 = { 593ff38577aSYuval Mintz 3, 31, 0x340108, 0x340114, 0x340110, 0x34010c}; 594ff38577aSYuval Mintz 595ff38577aSYuval Mintz static struct attn_hw_reg brb_int4_bb_b0 = { 596ff38577aSYuval Mintz 4, 27, 0x340120, 0x34012c, 0x340128, 0x340124}; 597ff38577aSYuval Mintz 598ff38577aSYuval Mintz static struct attn_hw_reg brb_int5_bb_b0 = { 599ff38577aSYuval Mintz 5, 1, 0x340138, 0x340144, 0x340140, 0x34013c}; 600ff38577aSYuval Mintz 601ff38577aSYuval Mintz static struct attn_hw_reg brb_int6_bb_b0 = { 602ff38577aSYuval Mintz 6, 8, 0x340150, 0x34015c, 0x340158, 0x340154}; 603ff38577aSYuval Mintz 604ff38577aSYuval Mintz static struct attn_hw_reg brb_int7_bb_b0 = { 605ff38577aSYuval Mintz 7, 32, 0x340168, 0x340174, 0x340170, 0x34016c}; 606ff38577aSYuval Mintz 607ff38577aSYuval Mintz static struct attn_hw_reg brb_int8_bb_b0 = { 608ff38577aSYuval Mintz 8, 17, 0x340184, 0x340190, 0x34018c, 0x340188}; 609ff38577aSYuval Mintz 610ff38577aSYuval Mintz static struct attn_hw_reg brb_int9_bb_b0 = { 611ff38577aSYuval Mintz 9, 1, 0x34019c, 0x3401a8, 0x3401a4, 0x3401a0}; 612ff38577aSYuval Mintz 613ff38577aSYuval Mintz static struct attn_hw_reg brb_int10_bb_b0 = { 614ff38577aSYuval Mintz 10, 14, 0x3401b4, 0x3401c0, 0x3401bc, 0x3401b8}; 615ff38577aSYuval Mintz 616ff38577aSYuval Mintz static struct attn_hw_reg brb_int11_bb_b0 = { 617ff38577aSYuval Mintz 11, 8, 0x3401cc, 0x3401d8, 0x3401d4, 0x3401d0}; 618ff38577aSYuval Mintz 619ff38577aSYuval Mintz static struct attn_hw_reg *brb_int_bb_b0_regs[12] = { 620ff38577aSYuval Mintz &brb_int0_bb_b0, &brb_int1_bb_b0, &brb_int2_bb_b0, &brb_int3_bb_b0, 621ff38577aSYuval Mintz &brb_int4_bb_b0, &brb_int5_bb_b0, &brb_int6_bb_b0, &brb_int7_bb_b0, 622ff38577aSYuval Mintz &brb_int8_bb_b0, &brb_int9_bb_b0, &brb_int10_bb_b0, &brb_int11_bb_b0}; 623ff38577aSYuval Mintz 624ff38577aSYuval Mintz static struct attn_hw_reg brb_prty0_bb_b0 = { 625ff38577aSYuval Mintz 0, 5, 0x3401dc, 0x3401e8, 0x3401e4, 0x3401e0}; 626ff38577aSYuval Mintz 627ff38577aSYuval Mintz static struct attn_hw_reg brb_prty1_bb_b0 = { 628ff38577aSYuval Mintz 1, 31, 0x340400, 0x34040c, 0x340408, 0x340404}; 629ff38577aSYuval Mintz 630ff38577aSYuval Mintz static struct attn_hw_reg brb_prty2_bb_b0 = { 631ff38577aSYuval Mintz 2, 14, 0x340410, 0x34041c, 0x340418, 0x340414}; 632ff38577aSYuval Mintz 633ff38577aSYuval Mintz static struct attn_hw_reg *brb_prty_bb_b0_regs[3] = { 634ff38577aSYuval Mintz &brb_prty0_bb_b0, &brb_prty1_bb_b0, &brb_prty2_bb_b0}; 635ff38577aSYuval Mintz 636ff38577aSYuval Mintz static struct attn_hw_reg src_int0_bb_b0 = { 637ff38577aSYuval Mintz 0, 1, 0x2381d8, 0x2381dc, 0x2381e0, 0x2381e4}; 638ff38577aSYuval Mintz 639ff38577aSYuval Mintz static struct attn_hw_reg *src_int_bb_b0_regs[1] = { 640ff38577aSYuval Mintz &src_int0_bb_b0}; 641ff38577aSYuval Mintz 642ff38577aSYuval Mintz static struct attn_hw_reg prs_int0_bb_b0 = { 643ff38577aSYuval Mintz 0, 2, 0x1f0040, 0x1f004c, 0x1f0048, 0x1f0044}; 644ff38577aSYuval Mintz 645ff38577aSYuval Mintz static struct attn_hw_reg *prs_int_bb_b0_regs[1] = { 646ff38577aSYuval Mintz &prs_int0_bb_b0}; 647ff38577aSYuval Mintz 648ff38577aSYuval Mintz static struct attn_hw_reg prs_prty0_bb_b0 = { 649ff38577aSYuval Mintz 0, 2, 0x1f0050, 0x1f005c, 0x1f0058, 0x1f0054}; 650ff38577aSYuval Mintz 651ff38577aSYuval Mintz static struct attn_hw_reg prs_prty1_bb_b0 = { 652ff38577aSYuval Mintz 1, 31, 0x1f0204, 0x1f0210, 0x1f020c, 0x1f0208}; 653ff38577aSYuval Mintz 654ff38577aSYuval Mintz static struct attn_hw_reg prs_prty2_bb_b0 = { 655ff38577aSYuval Mintz 2, 5, 0x1f0214, 0x1f0220, 0x1f021c, 0x1f0218}; 656ff38577aSYuval Mintz 657ff38577aSYuval Mintz static struct attn_hw_reg *prs_prty_bb_b0_regs[3] = { 658ff38577aSYuval Mintz &prs_prty0_bb_b0, &prs_prty1_bb_b0, &prs_prty2_bb_b0}; 659ff38577aSYuval Mintz 660ff38577aSYuval Mintz static struct attn_hw_reg tsdm_int0_bb_b0 = { 661ff38577aSYuval Mintz 0, 26, 0xfb0040, 0xfb004c, 0xfb0048, 0xfb0044}; 662ff38577aSYuval Mintz 663ff38577aSYuval Mintz static struct attn_hw_reg *tsdm_int_bb_b0_regs[1] = { 664ff38577aSYuval Mintz &tsdm_int0_bb_b0}; 665ff38577aSYuval Mintz 666ff38577aSYuval Mintz static struct attn_hw_reg tsdm_prty1_bb_b0 = { 667ff38577aSYuval Mintz 0, 10, 0xfb0200, 0xfb020c, 0xfb0208, 0xfb0204}; 668ff38577aSYuval Mintz 669ff38577aSYuval Mintz static struct attn_hw_reg *tsdm_prty_bb_b0_regs[1] = { 670ff38577aSYuval Mintz &tsdm_prty1_bb_b0}; 671ff38577aSYuval Mintz 672ff38577aSYuval Mintz static struct attn_hw_reg msdm_int0_bb_b0 = { 673ff38577aSYuval Mintz 0, 26, 0xfc0040, 0xfc004c, 0xfc0048, 0xfc0044}; 674ff38577aSYuval Mintz 675ff38577aSYuval Mintz static struct attn_hw_reg *msdm_int_bb_b0_regs[1] = { 676ff38577aSYuval Mintz &msdm_int0_bb_b0}; 677ff38577aSYuval Mintz 678ff38577aSYuval Mintz static struct attn_hw_reg msdm_prty1_bb_b0 = { 679ff38577aSYuval Mintz 0, 11, 0xfc0200, 0xfc020c, 0xfc0208, 0xfc0204}; 680ff38577aSYuval Mintz 681ff38577aSYuval Mintz static struct attn_hw_reg *msdm_prty_bb_b0_regs[1] = { 682ff38577aSYuval Mintz &msdm_prty1_bb_b0}; 683ff38577aSYuval Mintz 684ff38577aSYuval Mintz static struct attn_hw_reg usdm_int0_bb_b0 = { 685ff38577aSYuval Mintz 0, 26, 0xfd0040, 0xfd004c, 0xfd0048, 0xfd0044}; 686ff38577aSYuval Mintz 687ff38577aSYuval Mintz static struct attn_hw_reg *usdm_int_bb_b0_regs[1] = { 688ff38577aSYuval Mintz &usdm_int0_bb_b0}; 689ff38577aSYuval Mintz 690ff38577aSYuval Mintz static struct attn_hw_reg usdm_prty1_bb_b0 = { 691ff38577aSYuval Mintz 0, 10, 0xfd0200, 0xfd020c, 0xfd0208, 0xfd0204}; 692ff38577aSYuval Mintz 693ff38577aSYuval Mintz static struct attn_hw_reg *usdm_prty_bb_b0_regs[1] = { 694ff38577aSYuval Mintz &usdm_prty1_bb_b0}; 695ff38577aSYuval Mintz 696ff38577aSYuval Mintz static struct attn_hw_reg xsdm_int0_bb_b0 = { 697ff38577aSYuval Mintz 0, 26, 0xf80040, 0xf8004c, 0xf80048, 0xf80044}; 698ff38577aSYuval Mintz 699ff38577aSYuval Mintz static struct attn_hw_reg *xsdm_int_bb_b0_regs[1] = { 700ff38577aSYuval Mintz &xsdm_int0_bb_b0}; 701ff38577aSYuval Mintz 702ff38577aSYuval Mintz static struct attn_hw_reg xsdm_prty1_bb_b0 = { 703ff38577aSYuval Mintz 0, 10, 0xf80200, 0xf8020c, 0xf80208, 0xf80204}; 704ff38577aSYuval Mintz 705ff38577aSYuval Mintz static struct attn_hw_reg *xsdm_prty_bb_b0_regs[1] = { 706ff38577aSYuval Mintz &xsdm_prty1_bb_b0}; 707ff38577aSYuval Mintz 708ff38577aSYuval Mintz static struct attn_hw_reg ysdm_int0_bb_b0 = { 709ff38577aSYuval Mintz 0, 26, 0xf90040, 0xf9004c, 0xf90048, 0xf90044}; 710ff38577aSYuval Mintz 711ff38577aSYuval Mintz static struct attn_hw_reg *ysdm_int_bb_b0_regs[1] = { 712ff38577aSYuval Mintz &ysdm_int0_bb_b0}; 713ff38577aSYuval Mintz 714ff38577aSYuval Mintz static struct attn_hw_reg ysdm_prty1_bb_b0 = { 715ff38577aSYuval Mintz 0, 9, 0xf90200, 0xf9020c, 0xf90208, 0xf90204}; 716ff38577aSYuval Mintz 717ff38577aSYuval Mintz static struct attn_hw_reg *ysdm_prty_bb_b0_regs[1] = { 718ff38577aSYuval Mintz &ysdm_prty1_bb_b0}; 719ff38577aSYuval Mintz 720ff38577aSYuval Mintz static struct attn_hw_reg psdm_int0_bb_b0 = { 721ff38577aSYuval Mintz 0, 26, 0xfa0040, 0xfa004c, 0xfa0048, 0xfa0044}; 722ff38577aSYuval Mintz 723ff38577aSYuval Mintz static struct attn_hw_reg *psdm_int_bb_b0_regs[1] = { 724ff38577aSYuval Mintz &psdm_int0_bb_b0}; 725ff38577aSYuval Mintz 726ff38577aSYuval Mintz static struct attn_hw_reg psdm_prty1_bb_b0 = { 727ff38577aSYuval Mintz 0, 9, 0xfa0200, 0xfa020c, 0xfa0208, 0xfa0204}; 728ff38577aSYuval Mintz 729ff38577aSYuval Mintz static struct attn_hw_reg *psdm_prty_bb_b0_regs[1] = { 730ff38577aSYuval Mintz &psdm_prty1_bb_b0}; 731ff38577aSYuval Mintz 732ff38577aSYuval Mintz static struct attn_hw_reg tsem_int0_bb_b0 = { 733ff38577aSYuval Mintz 0, 32, 0x1700040, 0x170004c, 0x1700048, 0x1700044}; 734ff38577aSYuval Mintz 735ff38577aSYuval Mintz static struct attn_hw_reg tsem_int1_bb_b0 = { 736ff38577aSYuval Mintz 1, 13, 0x1700050, 0x170005c, 0x1700058, 0x1700054}; 737ff38577aSYuval Mintz 738ff38577aSYuval Mintz static struct attn_hw_reg tsem_fast_memory_int0_bb_b0 = { 739ff38577aSYuval Mintz 2, 1, 0x1740040, 0x174004c, 0x1740048, 0x1740044}; 740ff38577aSYuval Mintz 741ff38577aSYuval Mintz static struct attn_hw_reg *tsem_int_bb_b0_regs[3] = { 742ff38577aSYuval Mintz &tsem_int0_bb_b0, &tsem_int1_bb_b0, &tsem_fast_memory_int0_bb_b0}; 743ff38577aSYuval Mintz 744ff38577aSYuval Mintz static struct attn_hw_reg tsem_prty0_bb_b0 = { 745ff38577aSYuval Mintz 0, 3, 0x17000c8, 0x17000d4, 0x17000d0, 0x17000cc}; 746ff38577aSYuval Mintz 747ff38577aSYuval Mintz static struct attn_hw_reg tsem_prty1_bb_b0 = { 748ff38577aSYuval Mintz 1, 6, 0x1700200, 0x170020c, 0x1700208, 0x1700204}; 749ff38577aSYuval Mintz 750ff38577aSYuval Mintz static struct attn_hw_reg tsem_fast_memory_vfc_config_prty1_bb_b0 = { 751ff38577aSYuval Mintz 2, 6, 0x174a200, 0x174a20c, 0x174a208, 0x174a204}; 752ff38577aSYuval Mintz 753ff38577aSYuval Mintz static struct attn_hw_reg *tsem_prty_bb_b0_regs[3] = { 754ff38577aSYuval Mintz &tsem_prty0_bb_b0, &tsem_prty1_bb_b0, 755ff38577aSYuval Mintz &tsem_fast_memory_vfc_config_prty1_bb_b0}; 756ff38577aSYuval Mintz 757ff38577aSYuval Mintz static struct attn_hw_reg msem_int0_bb_b0 = { 758ff38577aSYuval Mintz 0, 32, 0x1800040, 0x180004c, 0x1800048, 0x1800044}; 759ff38577aSYuval Mintz 760ff38577aSYuval Mintz static struct attn_hw_reg msem_int1_bb_b0 = { 761ff38577aSYuval Mintz 1, 13, 0x1800050, 0x180005c, 0x1800058, 0x1800054}; 762ff38577aSYuval Mintz 763ff38577aSYuval Mintz static struct attn_hw_reg msem_fast_memory_int0_bb_b0 = { 764ff38577aSYuval Mintz 2, 1, 0x1840040, 0x184004c, 0x1840048, 0x1840044}; 765ff38577aSYuval Mintz 766ff38577aSYuval Mintz static struct attn_hw_reg *msem_int_bb_b0_regs[3] = { 767ff38577aSYuval Mintz &msem_int0_bb_b0, &msem_int1_bb_b0, &msem_fast_memory_int0_bb_b0}; 768ff38577aSYuval Mintz 769ff38577aSYuval Mintz static struct attn_hw_reg msem_prty0_bb_b0 = { 770ff38577aSYuval Mintz 0, 3, 0x18000c8, 0x18000d4, 0x18000d0, 0x18000cc}; 771ff38577aSYuval Mintz 772ff38577aSYuval Mintz static struct attn_hw_reg msem_prty1_bb_b0 = { 773ff38577aSYuval Mintz 1, 6, 0x1800200, 0x180020c, 0x1800208, 0x1800204}; 774ff38577aSYuval Mintz 775ff38577aSYuval Mintz static struct attn_hw_reg *msem_prty_bb_b0_regs[2] = { 776ff38577aSYuval Mintz &msem_prty0_bb_b0, &msem_prty1_bb_b0}; 777ff38577aSYuval Mintz 778ff38577aSYuval Mintz static struct attn_hw_reg usem_int0_bb_b0 = { 779ff38577aSYuval Mintz 0, 32, 0x1900040, 0x190004c, 0x1900048, 0x1900044}; 780ff38577aSYuval Mintz 781ff38577aSYuval Mintz static struct attn_hw_reg usem_int1_bb_b0 = { 782ff38577aSYuval Mintz 1, 13, 0x1900050, 0x190005c, 0x1900058, 0x1900054}; 783ff38577aSYuval Mintz 784ff38577aSYuval Mintz static struct attn_hw_reg usem_fast_memory_int0_bb_b0 = { 785ff38577aSYuval Mintz 2, 1, 0x1940040, 0x194004c, 0x1940048, 0x1940044}; 786ff38577aSYuval Mintz 787ff38577aSYuval Mintz static struct attn_hw_reg *usem_int_bb_b0_regs[3] = { 788ff38577aSYuval Mintz &usem_int0_bb_b0, &usem_int1_bb_b0, &usem_fast_memory_int0_bb_b0}; 789ff38577aSYuval Mintz 790ff38577aSYuval Mintz static struct attn_hw_reg usem_prty0_bb_b0 = { 791ff38577aSYuval Mintz 0, 3, 0x19000c8, 0x19000d4, 0x19000d0, 0x19000cc}; 792ff38577aSYuval Mintz 793ff38577aSYuval Mintz static struct attn_hw_reg usem_prty1_bb_b0 = { 794ff38577aSYuval Mintz 1, 6, 0x1900200, 0x190020c, 0x1900208, 0x1900204}; 795ff38577aSYuval Mintz 796ff38577aSYuval Mintz static struct attn_hw_reg *usem_prty_bb_b0_regs[2] = { 797ff38577aSYuval Mintz &usem_prty0_bb_b0, &usem_prty1_bb_b0}; 798ff38577aSYuval Mintz 799ff38577aSYuval Mintz static struct attn_hw_reg xsem_int0_bb_b0 = { 800ff38577aSYuval Mintz 0, 32, 0x1400040, 0x140004c, 0x1400048, 0x1400044}; 801ff38577aSYuval Mintz 802ff38577aSYuval Mintz static struct attn_hw_reg xsem_int1_bb_b0 = { 803ff38577aSYuval Mintz 1, 13, 0x1400050, 0x140005c, 0x1400058, 0x1400054}; 804ff38577aSYuval Mintz 805ff38577aSYuval Mintz static struct attn_hw_reg xsem_fast_memory_int0_bb_b0 = { 806ff38577aSYuval Mintz 2, 1, 0x1440040, 0x144004c, 0x1440048, 0x1440044}; 807ff38577aSYuval Mintz 808ff38577aSYuval Mintz static struct attn_hw_reg *xsem_int_bb_b0_regs[3] = { 809ff38577aSYuval Mintz &xsem_int0_bb_b0, &xsem_int1_bb_b0, &xsem_fast_memory_int0_bb_b0}; 810ff38577aSYuval Mintz 811ff38577aSYuval Mintz static struct attn_hw_reg xsem_prty0_bb_b0 = { 812ff38577aSYuval Mintz 0, 3, 0x14000c8, 0x14000d4, 0x14000d0, 0x14000cc}; 813ff38577aSYuval Mintz 814ff38577aSYuval Mintz static struct attn_hw_reg xsem_prty1_bb_b0 = { 815ff38577aSYuval Mintz 1, 7, 0x1400200, 0x140020c, 0x1400208, 0x1400204}; 816ff38577aSYuval Mintz 817ff38577aSYuval Mintz static struct attn_hw_reg *xsem_prty_bb_b0_regs[2] = { 818ff38577aSYuval Mintz &xsem_prty0_bb_b0, &xsem_prty1_bb_b0}; 819ff38577aSYuval Mintz 820ff38577aSYuval Mintz static struct attn_hw_reg ysem_int0_bb_b0 = { 821ff38577aSYuval Mintz 0, 32, 0x1500040, 0x150004c, 0x1500048, 0x1500044}; 822ff38577aSYuval Mintz 823ff38577aSYuval Mintz static struct attn_hw_reg ysem_int1_bb_b0 = { 824ff38577aSYuval Mintz 1, 13, 0x1500050, 0x150005c, 0x1500058, 0x1500054}; 825ff38577aSYuval Mintz 826ff38577aSYuval Mintz static struct attn_hw_reg ysem_fast_memory_int0_bb_b0 = { 827ff38577aSYuval Mintz 2, 1, 0x1540040, 0x154004c, 0x1540048, 0x1540044}; 828ff38577aSYuval Mintz 829ff38577aSYuval Mintz static struct attn_hw_reg *ysem_int_bb_b0_regs[3] = { 830ff38577aSYuval Mintz &ysem_int0_bb_b0, &ysem_int1_bb_b0, &ysem_fast_memory_int0_bb_b0}; 831ff38577aSYuval Mintz 832ff38577aSYuval Mintz static struct attn_hw_reg ysem_prty0_bb_b0 = { 833ff38577aSYuval Mintz 0, 3, 0x15000c8, 0x15000d4, 0x15000d0, 0x15000cc}; 834ff38577aSYuval Mintz 835ff38577aSYuval Mintz static struct attn_hw_reg ysem_prty1_bb_b0 = { 836ff38577aSYuval Mintz 1, 7, 0x1500200, 0x150020c, 0x1500208, 0x1500204}; 837ff38577aSYuval Mintz 838ff38577aSYuval Mintz static struct attn_hw_reg *ysem_prty_bb_b0_regs[2] = { 839ff38577aSYuval Mintz &ysem_prty0_bb_b0, &ysem_prty1_bb_b0}; 840ff38577aSYuval Mintz 841ff38577aSYuval Mintz static struct attn_hw_reg psem_int0_bb_b0 = { 842ff38577aSYuval Mintz 0, 32, 0x1600040, 0x160004c, 0x1600048, 0x1600044}; 843ff38577aSYuval Mintz 844ff38577aSYuval Mintz static struct attn_hw_reg psem_int1_bb_b0 = { 845ff38577aSYuval Mintz 1, 13, 0x1600050, 0x160005c, 0x1600058, 0x1600054}; 846ff38577aSYuval Mintz 847ff38577aSYuval Mintz static struct attn_hw_reg psem_fast_memory_int0_bb_b0 = { 848ff38577aSYuval Mintz 2, 1, 0x1640040, 0x164004c, 0x1640048, 0x1640044}; 849ff38577aSYuval Mintz 850ff38577aSYuval Mintz static struct attn_hw_reg *psem_int_bb_b0_regs[3] = { 851ff38577aSYuval Mintz &psem_int0_bb_b0, &psem_int1_bb_b0, &psem_fast_memory_int0_bb_b0}; 852ff38577aSYuval Mintz 853ff38577aSYuval Mintz static struct attn_hw_reg psem_prty0_bb_b0 = { 854ff38577aSYuval Mintz 0, 3, 0x16000c8, 0x16000d4, 0x16000d0, 0x16000cc}; 855ff38577aSYuval Mintz 856ff38577aSYuval Mintz static struct attn_hw_reg psem_prty1_bb_b0 = { 857ff38577aSYuval Mintz 1, 6, 0x1600200, 0x160020c, 0x1600208, 0x1600204}; 858ff38577aSYuval Mintz 859ff38577aSYuval Mintz static struct attn_hw_reg psem_fast_memory_vfc_config_prty1_bb_b0 = { 860ff38577aSYuval Mintz 2, 6, 0x164a200, 0x164a20c, 0x164a208, 0x164a204}; 861ff38577aSYuval Mintz 862ff38577aSYuval Mintz static struct attn_hw_reg *psem_prty_bb_b0_regs[3] = { 863ff38577aSYuval Mintz &psem_prty0_bb_b0, &psem_prty1_bb_b0, 864ff38577aSYuval Mintz &psem_fast_memory_vfc_config_prty1_bb_b0}; 865ff38577aSYuval Mintz 866ff38577aSYuval Mintz static struct attn_hw_reg rss_int0_bb_b0 = { 867ff38577aSYuval Mintz 0, 12, 0x238980, 0x23898c, 0x238988, 0x238984}; 868ff38577aSYuval Mintz 869ff38577aSYuval Mintz static struct attn_hw_reg *rss_int_bb_b0_regs[1] = { 870ff38577aSYuval Mintz &rss_int0_bb_b0}; 871ff38577aSYuval Mintz 872ff38577aSYuval Mintz static struct attn_hw_reg rss_prty1_bb_b0 = { 873ff38577aSYuval Mintz 0, 4, 0x238a00, 0x238a0c, 0x238a08, 0x238a04}; 874ff38577aSYuval Mintz 875ff38577aSYuval Mintz static struct attn_hw_reg *rss_prty_bb_b0_regs[1] = { 876ff38577aSYuval Mintz &rss_prty1_bb_b0}; 877ff38577aSYuval Mintz 878ff38577aSYuval Mintz static struct attn_hw_reg tmld_int0_bb_b0 = { 879ff38577aSYuval Mintz 0, 6, 0x4d0180, 0x4d018c, 0x4d0188, 0x4d0184}; 880ff38577aSYuval Mintz 881ff38577aSYuval Mintz static struct attn_hw_reg *tmld_int_bb_b0_regs[1] = { 882ff38577aSYuval Mintz &tmld_int0_bb_b0}; 883ff38577aSYuval Mintz 884ff38577aSYuval Mintz static struct attn_hw_reg tmld_prty1_bb_b0 = { 885ff38577aSYuval Mintz 0, 8, 0x4d0200, 0x4d020c, 0x4d0208, 0x4d0204}; 886ff38577aSYuval Mintz 887ff38577aSYuval Mintz static struct attn_hw_reg *tmld_prty_bb_b0_regs[1] = { 888ff38577aSYuval Mintz &tmld_prty1_bb_b0}; 889ff38577aSYuval Mintz 890ff38577aSYuval Mintz static struct attn_hw_reg muld_int0_bb_b0 = { 891ff38577aSYuval Mintz 0, 6, 0x4e0180, 0x4e018c, 0x4e0188, 0x4e0184}; 892ff38577aSYuval Mintz 893ff38577aSYuval Mintz static struct attn_hw_reg *muld_int_bb_b0_regs[1] = { 894ff38577aSYuval Mintz &muld_int0_bb_b0}; 895ff38577aSYuval Mintz 896ff38577aSYuval Mintz static struct attn_hw_reg muld_prty1_bb_b0 = { 897ff38577aSYuval Mintz 0, 10, 0x4e0200, 0x4e020c, 0x4e0208, 0x4e0204}; 898ff38577aSYuval Mintz 899ff38577aSYuval Mintz static struct attn_hw_reg *muld_prty_bb_b0_regs[1] = { 900ff38577aSYuval Mintz &muld_prty1_bb_b0}; 901ff38577aSYuval Mintz 902ff38577aSYuval Mintz static struct attn_hw_reg yuld_int0_bb_b0 = { 903ff38577aSYuval Mintz 0, 6, 0x4c8180, 0x4c818c, 0x4c8188, 0x4c8184}; 904ff38577aSYuval Mintz 905ff38577aSYuval Mintz static struct attn_hw_reg *yuld_int_bb_b0_regs[1] = { 906ff38577aSYuval Mintz &yuld_int0_bb_b0}; 907ff38577aSYuval Mintz 908ff38577aSYuval Mintz static struct attn_hw_reg yuld_prty1_bb_b0 = { 909ff38577aSYuval Mintz 0, 6, 0x4c8200, 0x4c820c, 0x4c8208, 0x4c8204}; 910ff38577aSYuval Mintz 911ff38577aSYuval Mintz static struct attn_hw_reg *yuld_prty_bb_b0_regs[1] = { 912ff38577aSYuval Mintz &yuld_prty1_bb_b0}; 913ff38577aSYuval Mintz 914ff38577aSYuval Mintz static struct attn_hw_reg xyld_int0_bb_b0 = { 915ff38577aSYuval Mintz 0, 6, 0x4c0180, 0x4c018c, 0x4c0188, 0x4c0184}; 916ff38577aSYuval Mintz 917ff38577aSYuval Mintz static struct attn_hw_reg *xyld_int_bb_b0_regs[1] = { 918ff38577aSYuval Mintz &xyld_int0_bb_b0}; 919ff38577aSYuval Mintz 920ff38577aSYuval Mintz static struct attn_hw_reg xyld_prty1_bb_b0 = { 921ff38577aSYuval Mintz 0, 9, 0x4c0200, 0x4c020c, 0x4c0208, 0x4c0204}; 922ff38577aSYuval Mintz 923ff38577aSYuval Mintz static struct attn_hw_reg *xyld_prty_bb_b0_regs[1] = { 924ff38577aSYuval Mintz &xyld_prty1_bb_b0}; 925ff38577aSYuval Mintz 926ff38577aSYuval Mintz static struct attn_hw_reg prm_int0_bb_b0 = { 927ff38577aSYuval Mintz 0, 11, 0x230040, 0x23004c, 0x230048, 0x230044}; 928ff38577aSYuval Mintz 929ff38577aSYuval Mintz static struct attn_hw_reg *prm_int_bb_b0_regs[1] = { 930ff38577aSYuval Mintz &prm_int0_bb_b0}; 931ff38577aSYuval Mintz 932ff38577aSYuval Mintz static struct attn_hw_reg prm_prty0_bb_b0 = { 933ff38577aSYuval Mintz 0, 1, 0x230050, 0x23005c, 0x230058, 0x230054}; 934ff38577aSYuval Mintz 935ff38577aSYuval Mintz static struct attn_hw_reg prm_prty1_bb_b0 = { 936ff38577aSYuval Mintz 1, 24, 0x230200, 0x23020c, 0x230208, 0x230204}; 937ff38577aSYuval Mintz 938ff38577aSYuval Mintz static struct attn_hw_reg *prm_prty_bb_b0_regs[2] = { 939ff38577aSYuval Mintz &prm_prty0_bb_b0, &prm_prty1_bb_b0}; 940ff38577aSYuval Mintz 941ff38577aSYuval Mintz static struct attn_hw_reg pbf_pb1_int0_bb_b0 = { 942ff38577aSYuval Mintz 0, 9, 0xda0040, 0xda004c, 0xda0048, 0xda0044}; 943ff38577aSYuval Mintz 944ff38577aSYuval Mintz static struct attn_hw_reg *pbf_pb1_int_bb_b0_regs[1] = { 945ff38577aSYuval Mintz &pbf_pb1_int0_bb_b0}; 946ff38577aSYuval Mintz 947ff38577aSYuval Mintz static struct attn_hw_reg pbf_pb1_prty0_bb_b0 = { 948ff38577aSYuval Mintz 0, 1, 0xda0050, 0xda005c, 0xda0058, 0xda0054}; 949ff38577aSYuval Mintz 950ff38577aSYuval Mintz static struct attn_hw_reg *pbf_pb1_prty_bb_b0_regs[1] = { 951ff38577aSYuval Mintz &pbf_pb1_prty0_bb_b0}; 952ff38577aSYuval Mintz 953ff38577aSYuval Mintz static struct attn_hw_reg pbf_pb2_int0_bb_b0 = { 954ff38577aSYuval Mintz 0, 9, 0xda4040, 0xda404c, 0xda4048, 0xda4044}; 955ff38577aSYuval Mintz 956ff38577aSYuval Mintz static struct attn_hw_reg *pbf_pb2_int_bb_b0_regs[1] = { 957ff38577aSYuval Mintz &pbf_pb2_int0_bb_b0}; 958ff38577aSYuval Mintz 959ff38577aSYuval Mintz static struct attn_hw_reg pbf_pb2_prty0_bb_b0 = { 960ff38577aSYuval Mintz 0, 1, 0xda4050, 0xda405c, 0xda4058, 0xda4054}; 961ff38577aSYuval Mintz 962ff38577aSYuval Mintz static struct attn_hw_reg *pbf_pb2_prty_bb_b0_regs[1] = { 963ff38577aSYuval Mintz &pbf_pb2_prty0_bb_b0}; 964ff38577aSYuval Mintz 965ff38577aSYuval Mintz static struct attn_hw_reg rpb_int0_bb_b0 = { 966ff38577aSYuval Mintz 0, 9, 0x23c040, 0x23c04c, 0x23c048, 0x23c044}; 967ff38577aSYuval Mintz 968ff38577aSYuval Mintz static struct attn_hw_reg *rpb_int_bb_b0_regs[1] = { 969ff38577aSYuval Mintz &rpb_int0_bb_b0}; 970ff38577aSYuval Mintz 971ff38577aSYuval Mintz static struct attn_hw_reg rpb_prty0_bb_b0 = { 972ff38577aSYuval Mintz 0, 1, 0x23c050, 0x23c05c, 0x23c058, 0x23c054}; 973ff38577aSYuval Mintz 974ff38577aSYuval Mintz static struct attn_hw_reg *rpb_prty_bb_b0_regs[1] = { 975ff38577aSYuval Mintz &rpb_prty0_bb_b0}; 976ff38577aSYuval Mintz 977ff38577aSYuval Mintz static struct attn_hw_reg btb_int0_bb_b0 = { 978ff38577aSYuval Mintz 0, 16, 0xdb00c0, 0xdb00cc, 0xdb00c8, 0xdb00c4}; 979ff38577aSYuval Mintz 980ff38577aSYuval Mintz static struct attn_hw_reg btb_int1_bb_b0 = { 981ff38577aSYuval Mintz 1, 16, 0xdb00d8, 0xdb00e4, 0xdb00e0, 0xdb00dc}; 982ff38577aSYuval Mintz 983ff38577aSYuval Mintz static struct attn_hw_reg btb_int2_bb_b0 = { 984ff38577aSYuval Mintz 2, 4, 0xdb00f0, 0xdb00fc, 0xdb00f8, 0xdb00f4}; 985ff38577aSYuval Mintz 986ff38577aSYuval Mintz static struct attn_hw_reg btb_int3_bb_b0 = { 987ff38577aSYuval Mintz 3, 32, 0xdb0108, 0xdb0114, 0xdb0110, 0xdb010c}; 988ff38577aSYuval Mintz 989ff38577aSYuval Mintz static struct attn_hw_reg btb_int4_bb_b0 = { 990ff38577aSYuval Mintz 4, 23, 0xdb0120, 0xdb012c, 0xdb0128, 0xdb0124}; 991ff38577aSYuval Mintz 992ff38577aSYuval Mintz static struct attn_hw_reg btb_int5_bb_b0 = { 993ff38577aSYuval Mintz 5, 32, 0xdb0138, 0xdb0144, 0xdb0140, 0xdb013c}; 994ff38577aSYuval Mintz 995ff38577aSYuval Mintz static struct attn_hw_reg btb_int6_bb_b0 = { 996ff38577aSYuval Mintz 6, 1, 0xdb0150, 0xdb015c, 0xdb0158, 0xdb0154}; 997ff38577aSYuval Mintz 998ff38577aSYuval Mintz static struct attn_hw_reg btb_int8_bb_b0 = { 999ff38577aSYuval Mintz 7, 1, 0xdb0184, 0xdb0190, 0xdb018c, 0xdb0188}; 1000ff38577aSYuval Mintz 1001ff38577aSYuval Mintz static struct attn_hw_reg btb_int9_bb_b0 = { 1002ff38577aSYuval Mintz 8, 1, 0xdb019c, 0xdb01a8, 0xdb01a4, 0xdb01a0}; 1003ff38577aSYuval Mintz 1004ff38577aSYuval Mintz static struct attn_hw_reg btb_int10_bb_b0 = { 1005ff38577aSYuval Mintz 9, 1, 0xdb01b4, 0xdb01c0, 0xdb01bc, 0xdb01b8}; 1006ff38577aSYuval Mintz 1007ff38577aSYuval Mintz static struct attn_hw_reg btb_int11_bb_b0 = { 1008ff38577aSYuval Mintz 10, 2, 0xdb01cc, 0xdb01d8, 0xdb01d4, 0xdb01d0}; 1009ff38577aSYuval Mintz 1010ff38577aSYuval Mintz static struct attn_hw_reg *btb_int_bb_b0_regs[11] = { 1011ff38577aSYuval Mintz &btb_int0_bb_b0, &btb_int1_bb_b0, &btb_int2_bb_b0, &btb_int3_bb_b0, 1012ff38577aSYuval Mintz &btb_int4_bb_b0, &btb_int5_bb_b0, &btb_int6_bb_b0, &btb_int8_bb_b0, 1013ff38577aSYuval Mintz &btb_int9_bb_b0, &btb_int10_bb_b0, &btb_int11_bb_b0}; 1014ff38577aSYuval Mintz 1015ff38577aSYuval Mintz static struct attn_hw_reg btb_prty0_bb_b0 = { 1016ff38577aSYuval Mintz 0, 5, 0xdb01dc, 0xdb01e8, 0xdb01e4, 0xdb01e0}; 1017ff38577aSYuval Mintz 1018ff38577aSYuval Mintz static struct attn_hw_reg btb_prty1_bb_b0 = { 1019ff38577aSYuval Mintz 1, 23, 0xdb0400, 0xdb040c, 0xdb0408, 0xdb0404}; 1020ff38577aSYuval Mintz 1021ff38577aSYuval Mintz static struct attn_hw_reg *btb_prty_bb_b0_regs[2] = { 1022ff38577aSYuval Mintz &btb_prty0_bb_b0, &btb_prty1_bb_b0}; 1023ff38577aSYuval Mintz 1024ff38577aSYuval Mintz static struct attn_hw_reg pbf_int0_bb_b0 = { 1025ff38577aSYuval Mintz 0, 1, 0xd80180, 0xd8018c, 0xd80188, 0xd80184}; 1026ff38577aSYuval Mintz 1027ff38577aSYuval Mintz static struct attn_hw_reg *pbf_int_bb_b0_regs[1] = { 1028ff38577aSYuval Mintz &pbf_int0_bb_b0}; 1029ff38577aSYuval Mintz 1030ff38577aSYuval Mintz static struct attn_hw_reg pbf_prty0_bb_b0 = { 1031ff38577aSYuval Mintz 0, 1, 0xd80190, 0xd8019c, 0xd80198, 0xd80194}; 1032ff38577aSYuval Mintz 1033ff38577aSYuval Mintz static struct attn_hw_reg pbf_prty1_bb_b0 = { 1034ff38577aSYuval Mintz 1, 31, 0xd80200, 0xd8020c, 0xd80208, 0xd80204}; 1035ff38577aSYuval Mintz 1036ff38577aSYuval Mintz static struct attn_hw_reg pbf_prty2_bb_b0 = { 1037ff38577aSYuval Mintz 2, 27, 0xd80210, 0xd8021c, 0xd80218, 0xd80214}; 1038ff38577aSYuval Mintz 1039ff38577aSYuval Mintz static struct attn_hw_reg *pbf_prty_bb_b0_regs[3] = { 1040ff38577aSYuval Mintz &pbf_prty0_bb_b0, &pbf_prty1_bb_b0, &pbf_prty2_bb_b0}; 1041ff38577aSYuval Mintz 1042ff38577aSYuval Mintz static struct attn_hw_reg rdif_int0_bb_b0 = { 1043ff38577aSYuval Mintz 0, 8, 0x300180, 0x30018c, 0x300188, 0x300184}; 1044ff38577aSYuval Mintz 1045ff38577aSYuval Mintz static struct attn_hw_reg *rdif_int_bb_b0_regs[1] = { 1046ff38577aSYuval Mintz &rdif_int0_bb_b0}; 1047ff38577aSYuval Mintz 1048ff38577aSYuval Mintz static struct attn_hw_reg rdif_prty0_bb_b0 = { 1049ff38577aSYuval Mintz 0, 1, 0x300190, 0x30019c, 0x300198, 0x300194}; 1050ff38577aSYuval Mintz 1051ff38577aSYuval Mintz static struct attn_hw_reg *rdif_prty_bb_b0_regs[1] = { 1052ff38577aSYuval Mintz &rdif_prty0_bb_b0}; 1053ff38577aSYuval Mintz 1054ff38577aSYuval Mintz static struct attn_hw_reg tdif_int0_bb_b0 = { 1055ff38577aSYuval Mintz 0, 8, 0x310180, 0x31018c, 0x310188, 0x310184}; 1056ff38577aSYuval Mintz 1057ff38577aSYuval Mintz static struct attn_hw_reg *tdif_int_bb_b0_regs[1] = { 1058ff38577aSYuval Mintz &tdif_int0_bb_b0}; 1059ff38577aSYuval Mintz 1060ff38577aSYuval Mintz static struct attn_hw_reg tdif_prty0_bb_b0 = { 1061ff38577aSYuval Mintz 0, 1, 0x310190, 0x31019c, 0x310198, 0x310194}; 1062ff38577aSYuval Mintz 1063ff38577aSYuval Mintz static struct attn_hw_reg tdif_prty1_bb_b0 = { 1064ff38577aSYuval Mintz 1, 11, 0x310200, 0x31020c, 0x310208, 0x310204}; 1065ff38577aSYuval Mintz 1066ff38577aSYuval Mintz static struct attn_hw_reg *tdif_prty_bb_b0_regs[2] = { 1067ff38577aSYuval Mintz &tdif_prty0_bb_b0, &tdif_prty1_bb_b0}; 1068ff38577aSYuval Mintz 1069ff38577aSYuval Mintz static struct attn_hw_reg cdu_int0_bb_b0 = { 1070ff38577aSYuval Mintz 0, 8, 0x5801c0, 0x5801c4, 0x5801c8, 0x5801cc}; 1071ff38577aSYuval Mintz 1072ff38577aSYuval Mintz static struct attn_hw_reg *cdu_int_bb_b0_regs[1] = { 1073ff38577aSYuval Mintz &cdu_int0_bb_b0}; 1074ff38577aSYuval Mintz 1075ff38577aSYuval Mintz static struct attn_hw_reg cdu_prty1_bb_b0 = { 1076ff38577aSYuval Mintz 0, 5, 0x580200, 0x58020c, 0x580208, 0x580204}; 1077ff38577aSYuval Mintz 1078ff38577aSYuval Mintz static struct attn_hw_reg *cdu_prty_bb_b0_regs[1] = { 1079ff38577aSYuval Mintz &cdu_prty1_bb_b0}; 1080ff38577aSYuval Mintz 1081ff38577aSYuval Mintz static struct attn_hw_reg ccfc_int0_bb_b0 = { 1082ff38577aSYuval Mintz 0, 2, 0x2e0180, 0x2e018c, 0x2e0188, 0x2e0184}; 1083ff38577aSYuval Mintz 1084ff38577aSYuval Mintz static struct attn_hw_reg *ccfc_int_bb_b0_regs[1] = { 1085ff38577aSYuval Mintz &ccfc_int0_bb_b0}; 1086ff38577aSYuval Mintz 1087ff38577aSYuval Mintz static struct attn_hw_reg ccfc_prty1_bb_b0 = { 1088ff38577aSYuval Mintz 0, 2, 0x2e0200, 0x2e020c, 0x2e0208, 0x2e0204}; 1089ff38577aSYuval Mintz 1090ff38577aSYuval Mintz static struct attn_hw_reg ccfc_prty0_bb_b0 = { 1091ff38577aSYuval Mintz 1, 6, 0x2e05e4, 0x2e05f0, 0x2e05ec, 0x2e05e8}; 1092ff38577aSYuval Mintz 1093ff38577aSYuval Mintz static struct attn_hw_reg *ccfc_prty_bb_b0_regs[2] = { 1094ff38577aSYuval Mintz &ccfc_prty1_bb_b0, &ccfc_prty0_bb_b0}; 1095ff38577aSYuval Mintz 1096ff38577aSYuval Mintz static struct attn_hw_reg tcfc_int0_bb_b0 = { 1097ff38577aSYuval Mintz 0, 2, 0x2d0180, 0x2d018c, 0x2d0188, 0x2d0184}; 1098ff38577aSYuval Mintz 1099ff38577aSYuval Mintz static struct attn_hw_reg *tcfc_int_bb_b0_regs[1] = { 1100ff38577aSYuval Mintz &tcfc_int0_bb_b0}; 1101ff38577aSYuval Mintz 1102ff38577aSYuval Mintz static struct attn_hw_reg tcfc_prty1_bb_b0 = { 1103ff38577aSYuval Mintz 0, 2, 0x2d0200, 0x2d020c, 0x2d0208, 0x2d0204}; 1104ff38577aSYuval Mintz 1105ff38577aSYuval Mintz static struct attn_hw_reg tcfc_prty0_bb_b0 = { 1106ff38577aSYuval Mintz 1, 6, 0x2d05e4, 0x2d05f0, 0x2d05ec, 0x2d05e8}; 1107ff38577aSYuval Mintz 1108ff38577aSYuval Mintz static struct attn_hw_reg *tcfc_prty_bb_b0_regs[2] = { 1109ff38577aSYuval Mintz &tcfc_prty1_bb_b0, &tcfc_prty0_bb_b0}; 1110ff38577aSYuval Mintz 1111ff38577aSYuval Mintz static struct attn_hw_reg igu_int0_bb_b0 = { 1112ff38577aSYuval Mintz 0, 11, 0x180180, 0x18018c, 0x180188, 0x180184}; 1113ff38577aSYuval Mintz 1114ff38577aSYuval Mintz static struct attn_hw_reg *igu_int_bb_b0_regs[1] = { 1115ff38577aSYuval Mintz &igu_int0_bb_b0}; 1116ff38577aSYuval Mintz 1117ff38577aSYuval Mintz static struct attn_hw_reg igu_prty0_bb_b0 = { 1118ff38577aSYuval Mintz 0, 1, 0x180190, 0x18019c, 0x180198, 0x180194}; 1119ff38577aSYuval Mintz 1120ff38577aSYuval Mintz static struct attn_hw_reg igu_prty1_bb_b0 = { 1121ff38577aSYuval Mintz 1, 31, 0x180200, 0x18020c, 0x180208, 0x180204}; 1122ff38577aSYuval Mintz 1123ff38577aSYuval Mintz static struct attn_hw_reg igu_prty2_bb_b0 = { 1124ff38577aSYuval Mintz 2, 1, 0x180210, 0x18021c, 0x180218, 0x180214}; 1125ff38577aSYuval Mintz 1126ff38577aSYuval Mintz static struct attn_hw_reg *igu_prty_bb_b0_regs[3] = { 1127ff38577aSYuval Mintz &igu_prty0_bb_b0, &igu_prty1_bb_b0, &igu_prty2_bb_b0}; 1128ff38577aSYuval Mintz 1129ff38577aSYuval Mintz static struct attn_hw_reg cau_int0_bb_b0 = { 1130ff38577aSYuval Mintz 0, 11, 0x1c00d4, 0x1c00d8, 0x1c00dc, 0x1c00e0}; 1131ff38577aSYuval Mintz 1132ff38577aSYuval Mintz static struct attn_hw_reg *cau_int_bb_b0_regs[1] = { 1133ff38577aSYuval Mintz &cau_int0_bb_b0}; 1134ff38577aSYuval Mintz 1135ff38577aSYuval Mintz static struct attn_hw_reg cau_prty1_bb_b0 = { 1136ff38577aSYuval Mintz 0, 13, 0x1c0200, 0x1c020c, 0x1c0208, 0x1c0204}; 1137ff38577aSYuval Mintz 1138ff38577aSYuval Mintz static struct attn_hw_reg *cau_prty_bb_b0_regs[1] = { 1139ff38577aSYuval Mintz &cau_prty1_bb_b0}; 1140ff38577aSYuval Mintz 1141ff38577aSYuval Mintz static struct attn_hw_reg dbg_int0_bb_b0 = { 1142ff38577aSYuval Mintz 0, 1, 0x10180, 0x1018c, 0x10188, 0x10184}; 1143ff38577aSYuval Mintz 1144ff38577aSYuval Mintz static struct attn_hw_reg *dbg_int_bb_b0_regs[1] = { 1145ff38577aSYuval Mintz &dbg_int0_bb_b0}; 1146ff38577aSYuval Mintz 1147ff38577aSYuval Mintz static struct attn_hw_reg dbg_prty1_bb_b0 = { 1148ff38577aSYuval Mintz 0, 1, 0x10200, 0x1020c, 0x10208, 0x10204}; 1149ff38577aSYuval Mintz 1150ff38577aSYuval Mintz static struct attn_hw_reg *dbg_prty_bb_b0_regs[1] = { 1151ff38577aSYuval Mintz &dbg_prty1_bb_b0}; 1152ff38577aSYuval Mintz 1153ff38577aSYuval Mintz static struct attn_hw_reg nig_int0_bb_b0 = { 1154ff38577aSYuval Mintz 0, 12, 0x500040, 0x50004c, 0x500048, 0x500044}; 1155ff38577aSYuval Mintz 1156ff38577aSYuval Mintz static struct attn_hw_reg nig_int1_bb_b0 = { 1157ff38577aSYuval Mintz 1, 32, 0x500050, 0x50005c, 0x500058, 0x500054}; 1158ff38577aSYuval Mintz 1159ff38577aSYuval Mintz static struct attn_hw_reg nig_int2_bb_b0 = { 1160ff38577aSYuval Mintz 2, 20, 0x500060, 0x50006c, 0x500068, 0x500064}; 1161ff38577aSYuval Mintz 1162ff38577aSYuval Mintz static struct attn_hw_reg nig_int3_bb_b0 = { 1163ff38577aSYuval Mintz 3, 18, 0x500070, 0x50007c, 0x500078, 0x500074}; 1164ff38577aSYuval Mintz 1165ff38577aSYuval Mintz static struct attn_hw_reg nig_int4_bb_b0 = { 1166ff38577aSYuval Mintz 4, 20, 0x500080, 0x50008c, 0x500088, 0x500084}; 1167ff38577aSYuval Mintz 1168ff38577aSYuval Mintz static struct attn_hw_reg nig_int5_bb_b0 = { 1169ff38577aSYuval Mintz 5, 18, 0x500090, 0x50009c, 0x500098, 0x500094}; 1170ff38577aSYuval Mintz 1171ff38577aSYuval Mintz static struct attn_hw_reg *nig_int_bb_b0_regs[6] = { 1172ff38577aSYuval Mintz &nig_int0_bb_b0, &nig_int1_bb_b0, &nig_int2_bb_b0, &nig_int3_bb_b0, 1173ff38577aSYuval Mintz &nig_int4_bb_b0, &nig_int5_bb_b0}; 1174ff38577aSYuval Mintz 1175ff38577aSYuval Mintz static struct attn_hw_reg nig_prty0_bb_b0 = { 1176ff38577aSYuval Mintz 0, 1, 0x5000a0, 0x5000ac, 0x5000a8, 0x5000a4}; 1177ff38577aSYuval Mintz 1178ff38577aSYuval Mintz static struct attn_hw_reg nig_prty1_bb_b0 = { 1179ff38577aSYuval Mintz 1, 31, 0x500200, 0x50020c, 0x500208, 0x500204}; 1180ff38577aSYuval Mintz 1181ff38577aSYuval Mintz static struct attn_hw_reg nig_prty2_bb_b0 = { 1182ff38577aSYuval Mintz 2, 31, 0x500210, 0x50021c, 0x500218, 0x500214}; 1183ff38577aSYuval Mintz 1184ff38577aSYuval Mintz static struct attn_hw_reg nig_prty3_bb_b0 = { 1185ff38577aSYuval Mintz 3, 31, 0x500220, 0x50022c, 0x500228, 0x500224}; 1186ff38577aSYuval Mintz 1187ff38577aSYuval Mintz static struct attn_hw_reg nig_prty4_bb_b0 = { 1188ff38577aSYuval Mintz 4, 17, 0x500230, 0x50023c, 0x500238, 0x500234}; 1189ff38577aSYuval Mintz 1190ff38577aSYuval Mintz static struct attn_hw_reg *nig_prty_bb_b0_regs[5] = { 1191ff38577aSYuval Mintz &nig_prty0_bb_b0, &nig_prty1_bb_b0, &nig_prty2_bb_b0, 1192ff38577aSYuval Mintz &nig_prty3_bb_b0, &nig_prty4_bb_b0}; 1193ff38577aSYuval Mintz 1194ff38577aSYuval Mintz static struct attn_hw_reg ipc_int0_bb_b0 = { 1195ff38577aSYuval Mintz 0, 13, 0x2050c, 0x20518, 0x20514, 0x20510}; 1196ff38577aSYuval Mintz 1197ff38577aSYuval Mintz static struct attn_hw_reg *ipc_int_bb_b0_regs[1] = { 1198ff38577aSYuval Mintz &ipc_int0_bb_b0}; 1199ff38577aSYuval Mintz 1200ff38577aSYuval Mintz static struct attn_hw_reg ipc_prty0_bb_b0 = { 1201ff38577aSYuval Mintz 0, 1, 0x2051c, 0x20528, 0x20524, 0x20520}; 1202ff38577aSYuval Mintz 1203ff38577aSYuval Mintz static struct attn_hw_reg *ipc_prty_bb_b0_regs[1] = { 1204ff38577aSYuval Mintz &ipc_prty0_bb_b0}; 1205ff38577aSYuval Mintz 1206ff38577aSYuval Mintz static struct attn_hw_block attn_blocks[] = { 1207ff38577aSYuval Mintz {"grc", {{1, 1, grc_int_bb_b0_regs, grc_prty_bb_b0_regs} } }, 1208ff38577aSYuval Mintz {"miscs", {{2, 1, miscs_int_bb_b0_regs, miscs_prty_bb_b0_regs} } }, 1209ff38577aSYuval Mintz {"misc", {{1, 0, misc_int_bb_b0_regs, NULL} } }, 1210ff38577aSYuval Mintz {"dbu", {{0, 0, NULL, NULL} } }, 1211ff38577aSYuval Mintz {"pglue_b", {{1, 2, pglue_b_int_bb_b0_regs, 1212ff38577aSYuval Mintz pglue_b_prty_bb_b0_regs} } }, 1213ff38577aSYuval Mintz {"cnig", {{1, 1, cnig_int_bb_b0_regs, cnig_prty_bb_b0_regs} } }, 1214ff38577aSYuval Mintz {"cpmu", {{1, 0, cpmu_int_bb_b0_regs, NULL} } }, 1215ff38577aSYuval Mintz {"ncsi", {{1, 1, ncsi_int_bb_b0_regs, ncsi_prty_bb_b0_regs} } }, 1216ff38577aSYuval Mintz {"opte", {{0, 2, NULL, opte_prty_bb_b0_regs} } }, 1217ff38577aSYuval Mintz {"bmb", {{12, 3, bmb_int_bb_b0_regs, bmb_prty_bb_b0_regs} } }, 1218ff38577aSYuval Mintz {"pcie", {{0, 1, NULL, pcie_prty_bb_b0_regs} } }, 1219ff38577aSYuval Mintz {"mcp", {{0, 0, NULL, NULL} } }, 1220ff38577aSYuval Mintz {"mcp2", {{0, 2, NULL, mcp2_prty_bb_b0_regs} } }, 1221ff38577aSYuval Mintz {"pswhst", {{1, 2, pswhst_int_bb_b0_regs, pswhst_prty_bb_b0_regs} } }, 1222ff38577aSYuval Mintz {"pswhst2", {{1, 1, pswhst2_int_bb_b0_regs, 1223ff38577aSYuval Mintz pswhst2_prty_bb_b0_regs} } }, 1224ff38577aSYuval Mintz {"pswrd", {{1, 1, pswrd_int_bb_b0_regs, pswrd_prty_bb_b0_regs} } }, 1225ff38577aSYuval Mintz {"pswrd2", {{1, 3, pswrd2_int_bb_b0_regs, pswrd2_prty_bb_b0_regs} } }, 1226ff38577aSYuval Mintz {"pswwr", {{1, 1, pswwr_int_bb_b0_regs, pswwr_prty_bb_b0_regs} } }, 1227ff38577aSYuval Mintz {"pswwr2", {{1, 5, pswwr2_int_bb_b0_regs, pswwr2_prty_bb_b0_regs} } }, 1228ff38577aSYuval Mintz {"pswrq", {{1, 1, pswrq_int_bb_b0_regs, pswrq_prty_bb_b0_regs} } }, 1229ff38577aSYuval Mintz {"pswrq2", {{1, 1, pswrq2_int_bb_b0_regs, pswrq2_prty_bb_b0_regs} } }, 1230ff38577aSYuval Mintz {"pglcs", {{1, 0, pglcs_int_bb_b0_regs, NULL} } }, 1231ff38577aSYuval Mintz {"dmae", {{1, 1, dmae_int_bb_b0_regs, dmae_prty_bb_b0_regs} } }, 1232ff38577aSYuval Mintz {"ptu", {{1, 1, ptu_int_bb_b0_regs, ptu_prty_bb_b0_regs} } }, 1233ff38577aSYuval Mintz {"tcm", {{3, 2, tcm_int_bb_b0_regs, tcm_prty_bb_b0_regs} } }, 1234ff38577aSYuval Mintz {"mcm", {{3, 2, mcm_int_bb_b0_regs, mcm_prty_bb_b0_regs} } }, 1235ff38577aSYuval Mintz {"ucm", {{3, 2, ucm_int_bb_b0_regs, ucm_prty_bb_b0_regs} } }, 1236ff38577aSYuval Mintz {"xcm", {{3, 2, xcm_int_bb_b0_regs, xcm_prty_bb_b0_regs} } }, 1237ff38577aSYuval Mintz {"ycm", {{3, 2, ycm_int_bb_b0_regs, ycm_prty_bb_b0_regs} } }, 1238ff38577aSYuval Mintz {"pcm", {{3, 1, pcm_int_bb_b0_regs, pcm_prty_bb_b0_regs} } }, 1239ff38577aSYuval Mintz {"qm", {{1, 4, qm_int_bb_b0_regs, qm_prty_bb_b0_regs} } }, 1240ff38577aSYuval Mintz {"tm", {{2, 1, tm_int_bb_b0_regs, tm_prty_bb_b0_regs} } }, 1241ff38577aSYuval Mintz {"dorq", {{1, 2, dorq_int_bb_b0_regs, dorq_prty_bb_b0_regs} } }, 1242ff38577aSYuval Mintz {"brb", {{12, 3, brb_int_bb_b0_regs, brb_prty_bb_b0_regs} } }, 1243ff38577aSYuval Mintz {"src", {{1, 0, src_int_bb_b0_regs, NULL} } }, 1244ff38577aSYuval Mintz {"prs", {{1, 3, prs_int_bb_b0_regs, prs_prty_bb_b0_regs} } }, 1245ff38577aSYuval Mintz {"tsdm", {{1, 1, tsdm_int_bb_b0_regs, tsdm_prty_bb_b0_regs} } }, 1246ff38577aSYuval Mintz {"msdm", {{1, 1, msdm_int_bb_b0_regs, msdm_prty_bb_b0_regs} } }, 1247ff38577aSYuval Mintz {"usdm", {{1, 1, usdm_int_bb_b0_regs, usdm_prty_bb_b0_regs} } }, 1248ff38577aSYuval Mintz {"xsdm", {{1, 1, xsdm_int_bb_b0_regs, xsdm_prty_bb_b0_regs} } }, 1249ff38577aSYuval Mintz {"ysdm", {{1, 1, ysdm_int_bb_b0_regs, ysdm_prty_bb_b0_regs} } }, 1250ff38577aSYuval Mintz {"psdm", {{1, 1, psdm_int_bb_b0_regs, psdm_prty_bb_b0_regs} } }, 1251ff38577aSYuval Mintz {"tsem", {{3, 3, tsem_int_bb_b0_regs, tsem_prty_bb_b0_regs} } }, 1252ff38577aSYuval Mintz {"msem", {{3, 2, msem_int_bb_b0_regs, msem_prty_bb_b0_regs} } }, 1253ff38577aSYuval Mintz {"usem", {{3, 2, usem_int_bb_b0_regs, usem_prty_bb_b0_regs} } }, 1254ff38577aSYuval Mintz {"xsem", {{3, 2, xsem_int_bb_b0_regs, xsem_prty_bb_b0_regs} } }, 1255ff38577aSYuval Mintz {"ysem", {{3, 2, ysem_int_bb_b0_regs, ysem_prty_bb_b0_regs} } }, 1256ff38577aSYuval Mintz {"psem", {{3, 3, psem_int_bb_b0_regs, psem_prty_bb_b0_regs} } }, 1257ff38577aSYuval Mintz {"rss", {{1, 1, rss_int_bb_b0_regs, rss_prty_bb_b0_regs} } }, 1258ff38577aSYuval Mintz {"tmld", {{1, 1, tmld_int_bb_b0_regs, tmld_prty_bb_b0_regs} } }, 1259ff38577aSYuval Mintz {"muld", {{1, 1, muld_int_bb_b0_regs, muld_prty_bb_b0_regs} } }, 1260ff38577aSYuval Mintz {"yuld", {{1, 1, yuld_int_bb_b0_regs, yuld_prty_bb_b0_regs} } }, 1261ff38577aSYuval Mintz {"xyld", {{1, 1, xyld_int_bb_b0_regs, xyld_prty_bb_b0_regs} } }, 1262ff38577aSYuval Mintz {"prm", {{1, 2, prm_int_bb_b0_regs, prm_prty_bb_b0_regs} } }, 1263ff38577aSYuval Mintz {"pbf_pb1", {{1, 1, pbf_pb1_int_bb_b0_regs, 1264ff38577aSYuval Mintz pbf_pb1_prty_bb_b0_regs} } }, 1265ff38577aSYuval Mintz {"pbf_pb2", {{1, 1, pbf_pb2_int_bb_b0_regs, 1266ff38577aSYuval Mintz pbf_pb2_prty_bb_b0_regs} } }, 1267ff38577aSYuval Mintz {"rpb", { {1, 1, rpb_int_bb_b0_regs, rpb_prty_bb_b0_regs} } }, 1268ff38577aSYuval Mintz {"btb", { {11, 2, btb_int_bb_b0_regs, btb_prty_bb_b0_regs} } }, 1269ff38577aSYuval Mintz {"pbf", { {1, 3, pbf_int_bb_b0_regs, pbf_prty_bb_b0_regs} } }, 1270ff38577aSYuval Mintz {"rdif", { {1, 1, rdif_int_bb_b0_regs, rdif_prty_bb_b0_regs} } }, 1271ff38577aSYuval Mintz {"tdif", { {1, 2, tdif_int_bb_b0_regs, tdif_prty_bb_b0_regs} } }, 1272ff38577aSYuval Mintz {"cdu", { {1, 1, cdu_int_bb_b0_regs, cdu_prty_bb_b0_regs} } }, 1273ff38577aSYuval Mintz {"ccfc", { {1, 2, ccfc_int_bb_b0_regs, ccfc_prty_bb_b0_regs} } }, 1274ff38577aSYuval Mintz {"tcfc", { {1, 2, tcfc_int_bb_b0_regs, tcfc_prty_bb_b0_regs} } }, 1275ff38577aSYuval Mintz {"igu", { {1, 3, igu_int_bb_b0_regs, igu_prty_bb_b0_regs} } }, 1276ff38577aSYuval Mintz {"cau", { {1, 1, cau_int_bb_b0_regs, cau_prty_bb_b0_regs} } }, 1277ff38577aSYuval Mintz {"umac", { {0, 0, NULL, NULL} } }, 1278ff38577aSYuval Mintz {"xmac", { {0, 0, NULL, NULL} } }, 1279ff38577aSYuval Mintz {"dbg", { {1, 1, dbg_int_bb_b0_regs, dbg_prty_bb_b0_regs} } }, 1280ff38577aSYuval Mintz {"nig", { {6, 5, nig_int_bb_b0_regs, nig_prty_bb_b0_regs} } }, 1281ff38577aSYuval Mintz {"wol", { {0, 0, NULL, NULL} } }, 1282ff38577aSYuval Mintz {"bmbn", { {0, 0, NULL, NULL} } }, 1283ff38577aSYuval Mintz {"ipc", { {1, 1, ipc_int_bb_b0_regs, ipc_prty_bb_b0_regs} } }, 1284ff38577aSYuval Mintz {"nwm", { {0, 0, NULL, NULL} } }, 1285ff38577aSYuval Mintz {"nws", { {0, 0, NULL, NULL} } }, 1286ff38577aSYuval Mintz {"ms", { {0, 0, NULL, NULL} } }, 1287ff38577aSYuval Mintz {"phy_pcie", { {0, 0, NULL, NULL} } }, 1288ff38577aSYuval Mintz {"misc_aeu", { {0, 0, NULL, NULL} } }, 1289ff38577aSYuval Mintz {"bar0_map", { {0, 0, NULL, NULL} } },}; 1290ff38577aSYuval Mintz 1291b4149dc7SYuval Mintz /* Specific HW attention callbacks */ 1292b4149dc7SYuval Mintz static int qed_mcp_attn_cb(struct qed_hwfn *p_hwfn) 1293b4149dc7SYuval Mintz { 1294b4149dc7SYuval Mintz u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE); 1295b4149dc7SYuval Mintz 1296b4149dc7SYuval Mintz /* This might occur on certain instances; Log it once then mask it */ 1297b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, "MCP_REG_CPU_STATE: %08x - Masking...\n", 1298b4149dc7SYuval Mintz tmp); 1299b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, 1300b4149dc7SYuval Mintz 0xffffffff); 1301b4149dc7SYuval Mintz 1302b4149dc7SYuval Mintz return 0; 1303b4149dc7SYuval Mintz } 1304b4149dc7SYuval Mintz 1305b4149dc7SYuval Mintz #define QED_PSWHST_ATTENTION_INCORRECT_ACCESS (0x1) 1306b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_WR_MASK (0x1) 1307b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_WR_SHIFT (0) 1308b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_CLIENT_MASK (0xf) 1309b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT (1) 1310b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK (0x1) 1311b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT (5) 1312b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_ID_MASK (0xff) 1313b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT (6) 1314b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_PF_ID_MASK (0xf) 1315b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT (14) 1316b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK (0xff) 1317b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT (18) 1318b4149dc7SYuval Mintz static int qed_pswhst_attn_cb(struct qed_hwfn *p_hwfn) 1319b4149dc7SYuval Mintz { 1320b4149dc7SYuval Mintz u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1321b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_VALID); 1322b4149dc7SYuval Mintz 1323b4149dc7SYuval Mintz if (tmp & QED_PSWHST_ATTENTION_INCORRECT_ACCESS) { 1324b4149dc7SYuval Mintz u32 addr, data, length; 1325b4149dc7SYuval Mintz 1326b4149dc7SYuval Mintz addr = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1327b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_ADDRESS); 1328b4149dc7SYuval Mintz data = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1329b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_DATA); 1330b4149dc7SYuval Mintz length = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1331b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_LENGTH); 1332b4149dc7SYuval Mintz 1333b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, 1334b4149dc7SYuval Mintz "Incorrect access to %08x of length %08x - PF [%02x] VF [%04x] [valid %02x] client [%02x] write [%02x] Byte-Enable [%04x] [%08x]\n", 1335b4149dc7SYuval Mintz addr, length, 1336b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_PF_ID), 1337b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_VF_ID), 1338b4149dc7SYuval Mintz (u8) GET_FIELD(data, 1339b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_VF_VALID), 1340b4149dc7SYuval Mintz (u8) GET_FIELD(data, 1341b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_CLIENT), 1342b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_WR), 1343b4149dc7SYuval Mintz (u8) GET_FIELD(data, 1344b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_BYTE_EN), 1345b4149dc7SYuval Mintz data); 1346b4149dc7SYuval Mintz } 1347b4149dc7SYuval Mintz 1348b4149dc7SYuval Mintz return 0; 1349b4149dc7SYuval Mintz } 1350b4149dc7SYuval Mintz 1351b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VALID_BIT (1 << 0) 1352b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_ADDRESS_MASK (0x7fffff) 1353b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_ADDRESS_SHIFT (0) 1354b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_RDWR_BIT (1 << 23) 1355b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_MASTER_MASK (0xf) 1356b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_MASTER_SHIFT (24) 1357b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PF_MASK (0xf) 1358b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PF_SHIFT (0) 1359b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VF_MASK (0xff) 1360b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VF_SHIFT (4) 1361b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_MASK (0x3) 1362b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_SHIFT (14) 1363b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_VF (0) 1364b4149dc7SYuval Mintz static const char *attn_master_to_str(u8 master) 1365b4149dc7SYuval Mintz { 1366b4149dc7SYuval Mintz switch (master) { 1367b4149dc7SYuval Mintz case 1: return "PXP"; 1368b4149dc7SYuval Mintz case 2: return "MCP"; 1369b4149dc7SYuval Mintz case 3: return "MSDM"; 1370b4149dc7SYuval Mintz case 4: return "PSDM"; 1371b4149dc7SYuval Mintz case 5: return "YSDM"; 1372b4149dc7SYuval Mintz case 6: return "USDM"; 1373b4149dc7SYuval Mintz case 7: return "TSDM"; 1374b4149dc7SYuval Mintz case 8: return "XSDM"; 1375b4149dc7SYuval Mintz case 9: return "DBU"; 1376b4149dc7SYuval Mintz case 10: return "DMAE"; 1377b4149dc7SYuval Mintz default: 1378b4149dc7SYuval Mintz return "Unkown"; 1379b4149dc7SYuval Mintz } 1380b4149dc7SYuval Mintz } 1381b4149dc7SYuval Mintz 1382b4149dc7SYuval Mintz static int qed_grc_attn_cb(struct qed_hwfn *p_hwfn) 1383b4149dc7SYuval Mintz { 1384b4149dc7SYuval Mintz u32 tmp, tmp2; 1385b4149dc7SYuval Mintz 1386b4149dc7SYuval Mintz /* We've already cleared the timeout interrupt register, so we learn 1387b4149dc7SYuval Mintz * of interrupts via the validity register 1388b4149dc7SYuval Mintz */ 1389b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1390b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_VALID); 1391b4149dc7SYuval Mintz if (!(tmp & QED_GRC_ATTENTION_VALID_BIT)) 1392b4149dc7SYuval Mintz goto out; 1393b4149dc7SYuval Mintz 1394b4149dc7SYuval Mintz /* Read the GRC timeout information */ 1395b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1396b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0); 1397b4149dc7SYuval Mintz tmp2 = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1398b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1); 1399b4149dc7SYuval Mintz 1400b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, 1401b4149dc7SYuval Mintz "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n", 1402b4149dc7SYuval Mintz tmp2, tmp, 1403b4149dc7SYuval Mintz (tmp & QED_GRC_ATTENTION_RDWR_BIT) ? "Write to" : "Read from", 1404b4149dc7SYuval Mintz GET_FIELD(tmp, QED_GRC_ATTENTION_ADDRESS) << 2, 1405b4149dc7SYuval Mintz attn_master_to_str(GET_FIELD(tmp, QED_GRC_ATTENTION_MASTER)), 1406b4149dc7SYuval Mintz GET_FIELD(tmp2, QED_GRC_ATTENTION_PF), 1407b4149dc7SYuval Mintz (GET_FIELD(tmp2, QED_GRC_ATTENTION_PRIV) == 1408b4149dc7SYuval Mintz QED_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Ireelevant)", 1409b4149dc7SYuval Mintz GET_FIELD(tmp2, QED_GRC_ATTENTION_VF)); 1410b4149dc7SYuval Mintz 1411b4149dc7SYuval Mintz out: 1412b4149dc7SYuval Mintz /* Regardles of anything else, clean the validity bit */ 1413b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 1414b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0); 1415b4149dc7SYuval Mintz return 0; 1416b4149dc7SYuval Mintz } 1417b4149dc7SYuval Mintz 1418b4149dc7SYuval Mintz #define PGLUE_ATTENTION_VALID (1 << 29) 1419b4149dc7SYuval Mintz #define PGLUE_ATTENTION_RD_VALID (1 << 26) 1420b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf) 1421b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20) 1422b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VF_VALID_MASK (0x1) 1423b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VF_VALID_SHIFT (19) 1424b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff) 1425b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24) 1426b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_MASK (0x1) 1427b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_SHIFT (21) 1428b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_BME_MASK (0x1) 1429b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_BME_SHIFT (22) 1430b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_FID_EN_MASK (0x1) 1431b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_FID_EN_SHIFT (23) 1432b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ICPL_VALID (1 << 23) 1433b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ZLR_VALID (1 << 25) 1434b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ILT_VALID (1 << 23) 1435b4149dc7SYuval Mintz static int qed_pglub_rbc_attn_cb(struct qed_hwfn *p_hwfn) 1436b4149dc7SYuval Mintz { 1437b4149dc7SYuval Mintz u32 tmp; 1438b4149dc7SYuval Mintz 1439b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1440b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_DETAILS2); 1441b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_VALID) { 1442b4149dc7SYuval Mintz u32 addr_lo, addr_hi, details; 1443b4149dc7SYuval Mintz 1444b4149dc7SYuval Mintz addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1445b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_ADD_31_0); 1446b4149dc7SYuval Mintz addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1447b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_ADD_63_32); 1448b4149dc7SYuval Mintz details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1449b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_DETAILS); 1450b4149dc7SYuval Mintz 1451b4149dc7SYuval Mintz DP_INFO(p_hwfn, 1452b4149dc7SYuval Mintz "Illegal write by chip to [%08x:%08x] blocked.\n" 1453b4149dc7SYuval Mintz "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 1454b4149dc7SYuval Mintz "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 1455b4149dc7SYuval Mintz addr_hi, addr_lo, details, 1456b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 1457b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 1458b4149dc7SYuval Mintz GET_FIELD(details, 1459b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0, 1460b4149dc7SYuval Mintz tmp, 1461b4149dc7SYuval Mintz GET_FIELD(tmp, 1462b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0, 1463b4149dc7SYuval Mintz GET_FIELD(tmp, 1464b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0, 1465b4149dc7SYuval Mintz GET_FIELD(tmp, 1466b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0); 1467b4149dc7SYuval Mintz } 1468b4149dc7SYuval Mintz 1469b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1470b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_DETAILS2); 1471b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_RD_VALID) { 1472b4149dc7SYuval Mintz u32 addr_lo, addr_hi, details; 1473b4149dc7SYuval Mintz 1474b4149dc7SYuval Mintz addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1475b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_ADD_31_0); 1476b4149dc7SYuval Mintz addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1477b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_ADD_63_32); 1478b4149dc7SYuval Mintz details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1479b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_DETAILS); 1480b4149dc7SYuval Mintz 1481b4149dc7SYuval Mintz DP_INFO(p_hwfn, 1482b4149dc7SYuval Mintz "Illegal read by chip from [%08x:%08x] blocked.\n" 1483b4149dc7SYuval Mintz " Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 1484b4149dc7SYuval Mintz " Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 1485b4149dc7SYuval Mintz addr_hi, addr_lo, details, 1486b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 1487b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 1488b4149dc7SYuval Mintz GET_FIELD(details, 1489b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0, 1490b4149dc7SYuval Mintz tmp, 1491b4149dc7SYuval Mintz GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 1492b4149dc7SYuval Mintz : 0, 1493b4149dc7SYuval Mintz GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0, 1494b4149dc7SYuval Mintz GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 1495b4149dc7SYuval Mintz : 0); 1496b4149dc7SYuval Mintz } 1497b4149dc7SYuval Mintz 1498b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1499b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL); 1500b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ICPL_VALID) 1501b4149dc7SYuval Mintz DP_INFO(p_hwfn, "ICPL eror - %08x\n", tmp); 1502b4149dc7SYuval Mintz 1503b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1504b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS); 1505b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ZLR_VALID) { 1506b4149dc7SYuval Mintz u32 addr_hi, addr_lo; 1507b4149dc7SYuval Mintz 1508b4149dc7SYuval Mintz addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1509b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0); 1510b4149dc7SYuval Mintz addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1511b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32); 1512b4149dc7SYuval Mintz 1513b4149dc7SYuval Mintz DP_INFO(p_hwfn, "ZLR eror - %08x [Address %08x:%08x]\n", 1514b4149dc7SYuval Mintz tmp, addr_hi, addr_lo); 1515b4149dc7SYuval Mintz } 1516b4149dc7SYuval Mintz 1517b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1518b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_DETAILS2); 1519b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ILT_VALID) { 1520b4149dc7SYuval Mintz u32 addr_hi, addr_lo, details; 1521b4149dc7SYuval Mintz 1522b4149dc7SYuval Mintz addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1523b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_ADD_31_0); 1524b4149dc7SYuval Mintz addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1525b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_ADD_63_32); 1526b4149dc7SYuval Mintz details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1527b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_DETAILS); 1528b4149dc7SYuval Mintz 1529b4149dc7SYuval Mintz DP_INFO(p_hwfn, 1530b4149dc7SYuval Mintz "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n", 1531b4149dc7SYuval Mintz details, tmp, addr_hi, addr_lo); 1532b4149dc7SYuval Mintz } 1533b4149dc7SYuval Mintz 1534b4149dc7SYuval Mintz /* Clear the indications */ 1535b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 1536b4149dc7SYuval Mintz PGLUE_B_REG_LATCHED_ERRORS_CLR, (1 << 2)); 1537b4149dc7SYuval Mintz 1538b4149dc7SYuval Mintz return 0; 1539b4149dc7SYuval Mintz } 1540b4149dc7SYuval Mintz 1541b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_REASON_MASK (0xfffff) 1542b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_OPAQUE_MASK (0xffff) 1543b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_SIZE_MASK (0x7f) 1544b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_SIZE_SHIFT (16) 1545b4149dc7SYuval Mintz static int qed_dorq_attn_cb(struct qed_hwfn *p_hwfn) 1546b4149dc7SYuval Mintz { 1547b4149dc7SYuval Mintz u32 reason; 1548b4149dc7SYuval Mintz 1549b4149dc7SYuval Mintz reason = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, DORQ_REG_DB_DROP_REASON) & 1550b4149dc7SYuval Mintz QED_DORQ_ATTENTION_REASON_MASK; 1551b4149dc7SYuval Mintz if (reason) { 1552b4149dc7SYuval Mintz u32 details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1553b4149dc7SYuval Mintz DORQ_REG_DB_DROP_DETAILS); 1554b4149dc7SYuval Mintz 1555b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, 1556b4149dc7SYuval Mintz "DORQ db_drop: adress 0x%08x Opaque FID 0x%04x Size [bytes] 0x%08x Reason: 0x%08x\n", 1557b4149dc7SYuval Mintz qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1558b4149dc7SYuval Mintz DORQ_REG_DB_DROP_DETAILS_ADDRESS), 1559b4149dc7SYuval Mintz (u16)(details & QED_DORQ_ATTENTION_OPAQUE_MASK), 1560b4149dc7SYuval Mintz GET_FIELD(details, QED_DORQ_ATTENTION_SIZE) * 4, 1561b4149dc7SYuval Mintz reason); 1562b4149dc7SYuval Mintz } 1563b4149dc7SYuval Mintz 1564b4149dc7SYuval Mintz return -EINVAL; 1565b4149dc7SYuval Mintz } 1566b4149dc7SYuval Mintz 15670d956e8aSYuval Mintz /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */ 15680d956e8aSYuval Mintz static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = { 15690d956e8aSYuval Mintz { 15700d956e8aSYuval Mintz { /* After Invert 1 */ 15710d956e8aSYuval Mintz {"GPIO0 function%d", 1572b4149dc7SYuval Mintz (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 15730d956e8aSYuval Mintz } 15740d956e8aSYuval Mintz }, 15750d956e8aSYuval Mintz 15760d956e8aSYuval Mintz { 15770d956e8aSYuval Mintz { /* After Invert 2 */ 1578b4149dc7SYuval Mintz {"PGLUE config_space", ATTENTION_SINGLE, 1579b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1580b4149dc7SYuval Mintz {"PGLUE misc_flr", ATTENTION_SINGLE, 1581b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1582b4149dc7SYuval Mintz {"PGLUE B RBC", ATTENTION_PAR_INT, 1583b4149dc7SYuval Mintz qed_pglub_rbc_attn_cb, BLOCK_PGLUE_B}, 1584b4149dc7SYuval Mintz {"PGLUE misc_mctp", ATTENTION_SINGLE, 1585b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1586b4149dc7SYuval Mintz {"Flash event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 1587b4149dc7SYuval Mintz {"SMB event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 1588b4149dc7SYuval Mintz {"Main Power", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 15890d956e8aSYuval Mintz {"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) | 1590ff38577aSYuval Mintz (1 << ATTENTION_OFFSET_SHIFT), 1591b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 15920d956e8aSYuval Mintz {"PCIE glue/PXP VPD %d", 1593b4149dc7SYuval Mintz (16 << ATTENTION_LENGTH_SHIFT), NULL, BLOCK_PGLCS}, 15940d956e8aSYuval Mintz } 15950d956e8aSYuval Mintz }, 15960d956e8aSYuval Mintz 15970d956e8aSYuval Mintz { 15980d956e8aSYuval Mintz { /* After Invert 3 */ 15990d956e8aSYuval Mintz {"General Attention %d", 1600b4149dc7SYuval Mintz (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 16010d956e8aSYuval Mintz } 16020d956e8aSYuval Mintz }, 16030d956e8aSYuval Mintz 16040d956e8aSYuval Mintz { 16050d956e8aSYuval Mintz { /* After Invert 4 */ 1606ff38577aSYuval Mintz {"General Attention 32", ATTENTION_SINGLE, 1607b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 16080d956e8aSYuval Mintz {"General Attention %d", 16090d956e8aSYuval Mintz (2 << ATTENTION_LENGTH_SHIFT) | 1610b4149dc7SYuval Mintz (33 << ATTENTION_OFFSET_SHIFT), NULL, MAX_BLOCK_ID}, 1611ff38577aSYuval Mintz {"General Attention 35", ATTENTION_SINGLE, 1612b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1613ff38577aSYuval Mintz {"CNIG port %d", (4 << ATTENTION_LENGTH_SHIFT), 1614b4149dc7SYuval Mintz NULL, BLOCK_CNIG}, 1615b4149dc7SYuval Mintz {"MCP CPU", ATTENTION_SINGLE, 1616b4149dc7SYuval Mintz qed_mcp_attn_cb, MAX_BLOCK_ID}, 1617b4149dc7SYuval Mintz {"MCP Watchdog timer", ATTENTION_SINGLE, 1618b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1619b4149dc7SYuval Mintz {"MCP M2P", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 1620ff38577aSYuval Mintz {"AVS stop status ready", ATTENTION_SINGLE, 1621b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1622b4149dc7SYuval Mintz {"MSTAT", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 1623b4149dc7SYuval Mintz {"MSTAT per-path", ATTENTION_PAR_INT, 1624b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1625ff38577aSYuval Mintz {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), 1626b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1627b4149dc7SYuval Mintz {"NIG", ATTENTION_PAR_INT, NULL, BLOCK_NIG}, 1628b4149dc7SYuval Mintz {"BMB/OPTE/MCP", ATTENTION_PAR_INT, NULL, BLOCK_BMB}, 1629b4149dc7SYuval Mintz {"BTB", ATTENTION_PAR_INT, NULL, BLOCK_BTB}, 1630b4149dc7SYuval Mintz {"BRB", ATTENTION_PAR_INT, NULL, BLOCK_BRB}, 1631b4149dc7SYuval Mintz {"PRS", ATTENTION_PAR_INT, NULL, BLOCK_PRS}, 16320d956e8aSYuval Mintz } 16330d956e8aSYuval Mintz }, 16340d956e8aSYuval Mintz 16350d956e8aSYuval Mintz { 16360d956e8aSYuval Mintz { /* After Invert 5 */ 1637b4149dc7SYuval Mintz {"SRC", ATTENTION_PAR_INT, NULL, BLOCK_SRC}, 1638b4149dc7SYuval Mintz {"PB Client1", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB1}, 1639b4149dc7SYuval Mintz {"PB Client2", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB2}, 1640b4149dc7SYuval Mintz {"RPB", ATTENTION_PAR_INT, NULL, BLOCK_RPB}, 1641b4149dc7SYuval Mintz {"PBF", ATTENTION_PAR_INT, NULL, BLOCK_PBF}, 1642b4149dc7SYuval Mintz {"QM", ATTENTION_PAR_INT, NULL, BLOCK_QM}, 1643b4149dc7SYuval Mintz {"TM", ATTENTION_PAR_INT, NULL, BLOCK_TM}, 1644b4149dc7SYuval Mintz {"MCM", ATTENTION_PAR_INT, NULL, BLOCK_MCM}, 1645b4149dc7SYuval Mintz {"MSDM", ATTENTION_PAR_INT, NULL, BLOCK_MSDM}, 1646b4149dc7SYuval Mintz {"MSEM", ATTENTION_PAR_INT, NULL, BLOCK_MSEM}, 1647b4149dc7SYuval Mintz {"PCM", ATTENTION_PAR_INT, NULL, BLOCK_PCM}, 1648b4149dc7SYuval Mintz {"PSDM", ATTENTION_PAR_INT, NULL, BLOCK_PSDM}, 1649b4149dc7SYuval Mintz {"PSEM", ATTENTION_PAR_INT, NULL, BLOCK_PSEM}, 1650b4149dc7SYuval Mintz {"TCM", ATTENTION_PAR_INT, NULL, BLOCK_TCM}, 1651b4149dc7SYuval Mintz {"TSDM", ATTENTION_PAR_INT, NULL, BLOCK_TSDM}, 1652b4149dc7SYuval Mintz {"TSEM", ATTENTION_PAR_INT, NULL, BLOCK_TSEM}, 16530d956e8aSYuval Mintz } 16540d956e8aSYuval Mintz }, 16550d956e8aSYuval Mintz 16560d956e8aSYuval Mintz { 16570d956e8aSYuval Mintz { /* After Invert 6 */ 1658b4149dc7SYuval Mintz {"UCM", ATTENTION_PAR_INT, NULL, BLOCK_UCM}, 1659b4149dc7SYuval Mintz {"USDM", ATTENTION_PAR_INT, NULL, BLOCK_USDM}, 1660b4149dc7SYuval Mintz {"USEM", ATTENTION_PAR_INT, NULL, BLOCK_USEM}, 1661b4149dc7SYuval Mintz {"XCM", ATTENTION_PAR_INT, NULL, BLOCK_XCM}, 1662b4149dc7SYuval Mintz {"XSDM", ATTENTION_PAR_INT, NULL, BLOCK_XSDM}, 1663b4149dc7SYuval Mintz {"XSEM", ATTENTION_PAR_INT, NULL, BLOCK_XSEM}, 1664b4149dc7SYuval Mintz {"YCM", ATTENTION_PAR_INT, NULL, BLOCK_YCM}, 1665b4149dc7SYuval Mintz {"YSDM", ATTENTION_PAR_INT, NULL, BLOCK_YSDM}, 1666b4149dc7SYuval Mintz {"YSEM", ATTENTION_PAR_INT, NULL, BLOCK_YSEM}, 1667b4149dc7SYuval Mintz {"XYLD", ATTENTION_PAR_INT, NULL, BLOCK_XYLD}, 1668b4149dc7SYuval Mintz {"TMLD", ATTENTION_PAR_INT, NULL, BLOCK_TMLD}, 1669b4149dc7SYuval Mintz {"MYLD", ATTENTION_PAR_INT, NULL, BLOCK_MULD}, 1670b4149dc7SYuval Mintz {"YULD", ATTENTION_PAR_INT, NULL, BLOCK_YULD}, 1671b4149dc7SYuval Mintz {"DORQ", ATTENTION_PAR_INT, 1672b4149dc7SYuval Mintz qed_dorq_attn_cb, BLOCK_DORQ}, 1673b4149dc7SYuval Mintz {"DBG", ATTENTION_PAR_INT, NULL, BLOCK_DBG}, 1674b4149dc7SYuval Mintz {"IPC", ATTENTION_PAR_INT, NULL, BLOCK_IPC}, 16750d956e8aSYuval Mintz } 16760d956e8aSYuval Mintz }, 16770d956e8aSYuval Mintz 16780d956e8aSYuval Mintz { 16790d956e8aSYuval Mintz { /* After Invert 7 */ 1680b4149dc7SYuval Mintz {"CCFC", ATTENTION_PAR_INT, NULL, BLOCK_CCFC}, 1681b4149dc7SYuval Mintz {"CDU", ATTENTION_PAR_INT, NULL, BLOCK_CDU}, 1682b4149dc7SYuval Mintz {"DMAE", ATTENTION_PAR_INT, NULL, BLOCK_DMAE}, 1683b4149dc7SYuval Mintz {"IGU", ATTENTION_PAR_INT, NULL, BLOCK_IGU}, 1684b4149dc7SYuval Mintz {"ATC", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 1685b4149dc7SYuval Mintz {"CAU", ATTENTION_PAR_INT, NULL, BLOCK_CAU}, 1686b4149dc7SYuval Mintz {"PTU", ATTENTION_PAR_INT, NULL, BLOCK_PTU}, 1687b4149dc7SYuval Mintz {"PRM", ATTENTION_PAR_INT, NULL, BLOCK_PRM}, 1688b4149dc7SYuval Mintz {"TCFC", ATTENTION_PAR_INT, NULL, BLOCK_TCFC}, 1689b4149dc7SYuval Mintz {"RDIF", ATTENTION_PAR_INT, NULL, BLOCK_RDIF}, 1690b4149dc7SYuval Mintz {"TDIF", ATTENTION_PAR_INT, NULL, BLOCK_TDIF}, 1691b4149dc7SYuval Mintz {"RSS", ATTENTION_PAR_INT, NULL, BLOCK_RSS}, 1692b4149dc7SYuval Mintz {"MISC", ATTENTION_PAR_INT, NULL, BLOCK_MISC}, 1693b4149dc7SYuval Mintz {"MISCS", ATTENTION_PAR_INT, NULL, BLOCK_MISCS}, 1694b4149dc7SYuval Mintz {"PCIE", ATTENTION_PAR, NULL, BLOCK_PCIE}, 1695b4149dc7SYuval Mintz {"Vaux PCI core", ATTENTION_SINGLE, NULL, BLOCK_PGLCS}, 1696b4149dc7SYuval Mintz {"PSWRQ", ATTENTION_PAR_INT, NULL, BLOCK_PSWRQ}, 16970d956e8aSYuval Mintz } 16980d956e8aSYuval Mintz }, 16990d956e8aSYuval Mintz 17000d956e8aSYuval Mintz { 17010d956e8aSYuval Mintz { /* After Invert 8 */ 1702b4149dc7SYuval Mintz {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, 1703b4149dc7SYuval Mintz NULL, BLOCK_PSWRQ2}, 1704b4149dc7SYuval Mintz {"PSWWR", ATTENTION_PAR_INT, NULL, BLOCK_PSWWR}, 1705b4149dc7SYuval Mintz {"PSWWR (pci_clk)", ATTENTION_PAR_INT, 1706b4149dc7SYuval Mintz NULL, BLOCK_PSWWR2}, 1707b4149dc7SYuval Mintz {"PSWRD", ATTENTION_PAR_INT, NULL, BLOCK_PSWRD}, 1708b4149dc7SYuval Mintz {"PSWRD (pci_clk)", ATTENTION_PAR_INT, 1709b4149dc7SYuval Mintz NULL, BLOCK_PSWRD2}, 1710b4149dc7SYuval Mintz {"PSWHST", ATTENTION_PAR_INT, 1711b4149dc7SYuval Mintz qed_pswhst_attn_cb, BLOCK_PSWHST}, 1712b4149dc7SYuval Mintz {"PSWHST (pci_clk)", ATTENTION_PAR_INT, 1713b4149dc7SYuval Mintz NULL, BLOCK_PSWHST2}, 1714b4149dc7SYuval Mintz {"GRC", ATTENTION_PAR_INT, 1715b4149dc7SYuval Mintz qed_grc_attn_cb, BLOCK_GRC}, 1716b4149dc7SYuval Mintz {"CPMU", ATTENTION_PAR_INT, NULL, BLOCK_CPMU}, 1717b4149dc7SYuval Mintz {"NCSI", ATTENTION_PAR_INT, NULL, BLOCK_NCSI}, 1718b4149dc7SYuval Mintz {"MSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 1719b4149dc7SYuval Mintz {"PSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 1720b4149dc7SYuval Mintz {"TSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 1721b4149dc7SYuval Mintz {"USEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 1722b4149dc7SYuval Mintz {"XSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 1723b4149dc7SYuval Mintz {"YSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 1724b4149dc7SYuval Mintz {"pxp_misc_mps", ATTENTION_PAR, NULL, BLOCK_PGLCS}, 1725ff38577aSYuval Mintz {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, 1726b4149dc7SYuval Mintz NULL, BLOCK_PGLCS}, 1727b4149dc7SYuval Mintz {"PERST_B assertion", ATTENTION_SINGLE, 1728b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1729ff38577aSYuval Mintz {"PERST_B deassertion", ATTENTION_SINGLE, 1730b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1731ff38577aSYuval Mintz {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), 1732b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 17330d956e8aSYuval Mintz } 17340d956e8aSYuval Mintz }, 17350d956e8aSYuval Mintz 17360d956e8aSYuval Mintz { 17370d956e8aSYuval Mintz { /* After Invert 9 */ 1738b4149dc7SYuval Mintz {"MCP Latched memory", ATTENTION_PAR, 1739b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1740ff38577aSYuval Mintz {"MCP Latched scratchpad cache", ATTENTION_SINGLE, 1741b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1742b4149dc7SYuval Mintz {"MCP Latched ump_tx", ATTENTION_PAR, 1743b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1744ff38577aSYuval Mintz {"MCP Latched scratchpad", ATTENTION_PAR, 1745b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1746ff38577aSYuval Mintz {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT), 1747b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 17480d956e8aSYuval Mintz } 17490d956e8aSYuval Mintz }, 17500d956e8aSYuval Mintz }; 17510d956e8aSYuval Mintz 1752cc875c2eSYuval Mintz #define ATTN_STATE_BITS (0xfff) 1753cc875c2eSYuval Mintz #define ATTN_BITS_MASKABLE (0x3ff) 1754cc875c2eSYuval Mintz struct qed_sb_attn_info { 1755cc875c2eSYuval Mintz /* Virtual & Physical address of the SB */ 1756cc875c2eSYuval Mintz struct atten_status_block *sb_attn; 1757cc875c2eSYuval Mintz dma_addr_t sb_phys; 1758cc875c2eSYuval Mintz 1759cc875c2eSYuval Mintz /* Last seen running index */ 1760cc875c2eSYuval Mintz u16 index; 1761cc875c2eSYuval Mintz 17620d956e8aSYuval Mintz /* A mask of the AEU bits resulting in a parity error */ 17630d956e8aSYuval Mintz u32 parity_mask[NUM_ATTN_REGS]; 17640d956e8aSYuval Mintz 17650d956e8aSYuval Mintz /* A pointer to the attention description structure */ 17660d956e8aSYuval Mintz struct aeu_invert_reg *p_aeu_desc; 17670d956e8aSYuval Mintz 1768cc875c2eSYuval Mintz /* Previously asserted attentions, which are still unasserted */ 1769cc875c2eSYuval Mintz u16 known_attn; 1770cc875c2eSYuval Mintz 1771cc875c2eSYuval Mintz /* Cleanup address for the link's general hw attention */ 1772cc875c2eSYuval Mintz u32 mfw_attn_addr; 1773cc875c2eSYuval Mintz }; 1774cc875c2eSYuval Mintz 1775cc875c2eSYuval Mintz static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn, 1776cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb_desc) 1777cc875c2eSYuval Mintz { 1778cc875c2eSYuval Mintz u16 rc = 0; 1779cc875c2eSYuval Mintz u16 index; 1780cc875c2eSYuval Mintz 1781cc875c2eSYuval Mintz /* Make certain HW write took affect */ 1782cc875c2eSYuval Mintz mmiowb(); 1783cc875c2eSYuval Mintz 1784cc875c2eSYuval Mintz index = le16_to_cpu(p_sb_desc->sb_attn->sb_index); 1785cc875c2eSYuval Mintz if (p_sb_desc->index != index) { 1786cc875c2eSYuval Mintz p_sb_desc->index = index; 1787cc875c2eSYuval Mintz rc = QED_SB_ATT_IDX; 1788cc875c2eSYuval Mintz } 1789cc875c2eSYuval Mintz 1790cc875c2eSYuval Mintz /* Make certain we got a consistent view with HW */ 1791cc875c2eSYuval Mintz mmiowb(); 1792cc875c2eSYuval Mintz 1793cc875c2eSYuval Mintz return rc; 1794cc875c2eSYuval Mintz } 1795cc875c2eSYuval Mintz 1796cc875c2eSYuval Mintz /** 1797cc875c2eSYuval Mintz * @brief qed_int_assertion - handles asserted attention bits 1798cc875c2eSYuval Mintz * 1799cc875c2eSYuval Mintz * @param p_hwfn 1800cc875c2eSYuval Mintz * @param asserted_bits newly asserted bits 1801cc875c2eSYuval Mintz * @return int 1802cc875c2eSYuval Mintz */ 1803cc875c2eSYuval Mintz static int qed_int_assertion(struct qed_hwfn *p_hwfn, 1804cc875c2eSYuval Mintz u16 asserted_bits) 1805cc875c2eSYuval Mintz { 1806cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 1807cc875c2eSYuval Mintz u32 igu_mask; 1808cc875c2eSYuval Mintz 1809cc875c2eSYuval Mintz /* Mask the source of the attention in the IGU */ 1810cc875c2eSYuval Mintz igu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1811cc875c2eSYuval Mintz IGU_REG_ATTENTION_ENABLE); 1812cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n", 1813cc875c2eSYuval Mintz igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE)); 1814cc875c2eSYuval Mintz igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE); 1815cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask); 1816cc875c2eSYuval Mintz 1817cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1818cc875c2eSYuval Mintz "inner known ATTN state: 0x%04x --> 0x%04x\n", 1819cc875c2eSYuval Mintz sb_attn_sw->known_attn, 1820cc875c2eSYuval Mintz sb_attn_sw->known_attn | asserted_bits); 1821cc875c2eSYuval Mintz sb_attn_sw->known_attn |= asserted_bits; 1822cc875c2eSYuval Mintz 1823cc875c2eSYuval Mintz /* Handle MCP events */ 1824cc875c2eSYuval Mintz if (asserted_bits & 0x100) { 1825cc875c2eSYuval Mintz qed_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt); 1826cc875c2eSYuval Mintz /* Clean the MCP attention */ 1827cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 1828cc875c2eSYuval Mintz sb_attn_sw->mfw_attn_addr, 0); 1829cc875c2eSYuval Mintz } 1830cc875c2eSYuval Mintz 1831cc875c2eSYuval Mintz DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 1832cc875c2eSYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 1833cc875c2eSYuval Mintz ((IGU_CMD_ATTN_BIT_SET_UPPER - 1834cc875c2eSYuval Mintz IGU_CMD_INT_ACK_BASE) << 3), 1835cc875c2eSYuval Mintz (u32)asserted_bits); 1836cc875c2eSYuval Mintz 1837cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "set cmd IGU: 0x%04x\n", 1838cc875c2eSYuval Mintz asserted_bits); 1839cc875c2eSYuval Mintz 1840cc875c2eSYuval Mintz return 0; 1841cc875c2eSYuval Mintz } 1842cc875c2eSYuval Mintz 1843ff38577aSYuval Mintz static void qed_int_deassertion_print_bit(struct qed_hwfn *p_hwfn, 1844ff38577aSYuval Mintz struct attn_hw_reg *p_reg_desc, 1845ff38577aSYuval Mintz struct attn_hw_block *p_block, 1846ff38577aSYuval Mintz enum qed_attention_type type, 1847ff38577aSYuval Mintz u32 val, u32 mask) 1848ff38577aSYuval Mintz { 1849ff38577aSYuval Mintz int j; 1850ff38577aSYuval Mintz 1851ff38577aSYuval Mintz for (j = 0; j < p_reg_desc->num_of_bits; j++) { 1852ff38577aSYuval Mintz if (!(val & (1 << j))) 1853ff38577aSYuval Mintz continue; 1854ff38577aSYuval Mintz 1855ff38577aSYuval Mintz DP_NOTICE(p_hwfn, 1856ff38577aSYuval Mintz "%s (%s): reg %d [0x%08x], bit %d [%s]\n", 1857ff38577aSYuval Mintz p_block->name, 1858ff38577aSYuval Mintz type == QED_ATTN_TYPE_ATTN ? "Interrupt" : 1859ff38577aSYuval Mintz "Parity", 1860ff38577aSYuval Mintz p_reg_desc->reg_idx, p_reg_desc->sts_addr, 1861ff38577aSYuval Mintz j, (mask & (1 << j)) ? " [MASKED]" : ""); 1862ff38577aSYuval Mintz } 1863ff38577aSYuval Mintz } 1864ff38577aSYuval Mintz 1865cc875c2eSYuval Mintz /** 18660d956e8aSYuval Mintz * @brief qed_int_deassertion_aeu_bit - handles the effects of a single 18670d956e8aSYuval Mintz * cause of the attention 18680d956e8aSYuval Mintz * 18690d956e8aSYuval Mintz * @param p_hwfn 18700d956e8aSYuval Mintz * @param p_aeu - descriptor of an AEU bit which caused the attention 18710d956e8aSYuval Mintz * @param aeu_en_reg - register offset of the AEU enable reg. which configured 18720d956e8aSYuval Mintz * this bit to this group. 18730d956e8aSYuval Mintz * @param bit_index - index of this bit in the aeu_en_reg 18740d956e8aSYuval Mintz * 18750d956e8aSYuval Mintz * @return int 18760d956e8aSYuval Mintz */ 18770d956e8aSYuval Mintz static int 18780d956e8aSYuval Mintz qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn, 18790d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_aeu, 18800d956e8aSYuval Mintz u32 aeu_en_reg, 18810d956e8aSYuval Mintz u32 bitmask) 18820d956e8aSYuval Mintz { 18830d956e8aSYuval Mintz int rc = -EINVAL; 1884b4149dc7SYuval Mintz u32 val; 18850d956e8aSYuval Mintz 18860d956e8aSYuval Mintz DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n", 18870d956e8aSYuval Mintz p_aeu->bit_name, bitmask); 18880d956e8aSYuval Mintz 1889b4149dc7SYuval Mintz /* Call callback before clearing the interrupt status */ 1890b4149dc7SYuval Mintz if (p_aeu->cb) { 1891b4149dc7SYuval Mintz DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n", 1892b4149dc7SYuval Mintz p_aeu->bit_name); 1893b4149dc7SYuval Mintz rc = p_aeu->cb(p_hwfn); 1894b4149dc7SYuval Mintz } 1895b4149dc7SYuval Mintz 1896ff38577aSYuval Mintz /* Handle HW block interrupt registers */ 1897ff38577aSYuval Mintz if (p_aeu->block_index != MAX_BLOCK_ID) { 1898ff38577aSYuval Mintz struct attn_hw_block *p_block; 1899b4149dc7SYuval Mintz u32 mask; 1900ff38577aSYuval Mintz int i; 1901ff38577aSYuval Mintz 1902ff38577aSYuval Mintz p_block = &attn_blocks[p_aeu->block_index]; 1903ff38577aSYuval Mintz 1904ff38577aSYuval Mintz /* Handle each interrupt register */ 1905ff38577aSYuval Mintz for (i = 0; i < p_block->chip_regs[0].num_of_int_regs; i++) { 1906ff38577aSYuval Mintz struct attn_hw_reg *p_reg_desc; 1907ff38577aSYuval Mintz u32 sts_addr; 1908ff38577aSYuval Mintz 1909ff38577aSYuval Mintz p_reg_desc = p_block->chip_regs[0].int_regs[i]; 1910b4149dc7SYuval Mintz 1911b4149dc7SYuval Mintz /* In case of fatal attention, don't clear the status 1912b4149dc7SYuval Mintz * so it would appear in following idle check. 1913b4149dc7SYuval Mintz */ 1914b4149dc7SYuval Mintz if (rc == 0) 1915b4149dc7SYuval Mintz sts_addr = p_reg_desc->sts_clr_addr; 1916b4149dc7SYuval Mintz else 1917ff38577aSYuval Mintz sts_addr = p_reg_desc->sts_addr; 1918ff38577aSYuval Mintz 1919ff38577aSYuval Mintz val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, sts_addr); 1920ff38577aSYuval Mintz mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1921ff38577aSYuval Mintz p_reg_desc->mask_addr); 1922ff38577aSYuval Mintz qed_int_deassertion_print_bit(p_hwfn, p_reg_desc, 1923ff38577aSYuval Mintz p_block, 1924ff38577aSYuval Mintz QED_ATTN_TYPE_ATTN, 1925ff38577aSYuval Mintz val, mask); 1926ff38577aSYuval Mintz } 1927ff38577aSYuval Mintz } 1928ff38577aSYuval Mintz 1929b4149dc7SYuval Mintz /* If the attention is benign, no need to prevent it */ 1930b4149dc7SYuval Mintz if (!rc) 1931b4149dc7SYuval Mintz goto out; 1932b4149dc7SYuval Mintz 19330d956e8aSYuval Mintz /* Prevent this Attention from being asserted in the future */ 19340d956e8aSYuval Mintz val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 1935b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & ~bitmask)); 19360d956e8aSYuval Mintz DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n", 19370d956e8aSYuval Mintz p_aeu->bit_name); 19380d956e8aSYuval Mintz 1939b4149dc7SYuval Mintz out: 19400d956e8aSYuval Mintz return rc; 19410d956e8aSYuval Mintz } 19420d956e8aSYuval Mintz 1943ff38577aSYuval Mintz static void qed_int_parity_print(struct qed_hwfn *p_hwfn, 1944ff38577aSYuval Mintz struct aeu_invert_reg_bit *p_aeu, 1945ff38577aSYuval Mintz struct attn_hw_block *p_block, 1946ff38577aSYuval Mintz u8 bit_index) 1947ff38577aSYuval Mintz { 1948ff38577aSYuval Mintz int i; 1949ff38577aSYuval Mintz 1950ff38577aSYuval Mintz for (i = 0; i < p_block->chip_regs[0].num_of_prty_regs; i++) { 1951ff38577aSYuval Mintz struct attn_hw_reg *p_reg_desc; 1952ff38577aSYuval Mintz u32 val, mask; 1953ff38577aSYuval Mintz 1954ff38577aSYuval Mintz p_reg_desc = p_block->chip_regs[0].prty_regs[i]; 1955ff38577aSYuval Mintz 1956ff38577aSYuval Mintz val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1957ff38577aSYuval Mintz p_reg_desc->sts_clr_addr); 1958ff38577aSYuval Mintz mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1959ff38577aSYuval Mintz p_reg_desc->mask_addr); 1960ff38577aSYuval Mintz qed_int_deassertion_print_bit(p_hwfn, p_reg_desc, 1961ff38577aSYuval Mintz p_block, 1962ff38577aSYuval Mintz QED_ATTN_TYPE_PARITY, 1963ff38577aSYuval Mintz val, mask); 1964ff38577aSYuval Mintz } 1965ff38577aSYuval Mintz } 1966ff38577aSYuval Mintz 1967ff38577aSYuval Mintz /** 1968ff38577aSYuval Mintz * @brief qed_int_deassertion_parity - handle a single parity AEU source 1969ff38577aSYuval Mintz * 1970ff38577aSYuval Mintz * @param p_hwfn 1971ff38577aSYuval Mintz * @param p_aeu - descriptor of an AEU bit which caused the parity 1972ff38577aSYuval Mintz * @param bit_index 1973ff38577aSYuval Mintz */ 1974ff38577aSYuval Mintz static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn, 1975ff38577aSYuval Mintz struct aeu_invert_reg_bit *p_aeu, 1976ff38577aSYuval Mintz u8 bit_index) 1977ff38577aSYuval Mintz { 1978ff38577aSYuval Mintz u32 block_id = p_aeu->block_index; 1979ff38577aSYuval Mintz 1980ff38577aSYuval Mintz DP_INFO(p_hwfn->cdev, "%s[%d] parity attention is set\n", 1981ff38577aSYuval Mintz p_aeu->bit_name, bit_index); 1982ff38577aSYuval Mintz 1983ff38577aSYuval Mintz if (block_id != MAX_BLOCK_ID) { 1984ff38577aSYuval Mintz qed_int_parity_print(p_hwfn, p_aeu, &attn_blocks[block_id], 1985ff38577aSYuval Mintz bit_index); 1986ff38577aSYuval Mintz 1987ff38577aSYuval Mintz /* In BB, there's a single parity bit for several blocks */ 1988ff38577aSYuval Mintz if (block_id == BLOCK_BTB) { 1989ff38577aSYuval Mintz qed_int_parity_print(p_hwfn, p_aeu, 1990ff38577aSYuval Mintz &attn_blocks[BLOCK_OPTE], 1991ff38577aSYuval Mintz bit_index); 1992ff38577aSYuval Mintz qed_int_parity_print(p_hwfn, p_aeu, 1993ff38577aSYuval Mintz &attn_blocks[BLOCK_MCP], 1994ff38577aSYuval Mintz bit_index); 1995ff38577aSYuval Mintz } 1996ff38577aSYuval Mintz } 1997ff38577aSYuval Mintz } 1998ff38577aSYuval Mintz 19990d956e8aSYuval Mintz /** 2000cc875c2eSYuval Mintz * @brief - handles deassertion of previously asserted attentions. 2001cc875c2eSYuval Mintz * 2002cc875c2eSYuval Mintz * @param p_hwfn 2003cc875c2eSYuval Mintz * @param deasserted_bits - newly deasserted bits 2004cc875c2eSYuval Mintz * @return int 2005cc875c2eSYuval Mintz * 2006cc875c2eSYuval Mintz */ 2007cc875c2eSYuval Mintz static int qed_int_deassertion(struct qed_hwfn *p_hwfn, 2008cc875c2eSYuval Mintz u16 deasserted_bits) 2009cc875c2eSYuval Mintz { 2010cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 20110d956e8aSYuval Mintz u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask; 20120d956e8aSYuval Mintz u8 i, j, k, bit_idx; 20130d956e8aSYuval Mintz int rc = 0; 2014cc875c2eSYuval Mintz 20150d956e8aSYuval Mintz /* Read the attention registers in the AEU */ 20160d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 20170d956e8aSYuval Mintz aeu_inv_arr[i] = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 20180d956e8aSYuval Mintz MISC_REG_AEU_AFTER_INVERT_1_IGU + 20190d956e8aSYuval Mintz i * 0x4); 20200d956e8aSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 20210d956e8aSYuval Mintz "Deasserted bits [%d]: %08x\n", 20220d956e8aSYuval Mintz i, aeu_inv_arr[i]); 20230d956e8aSYuval Mintz } 20240d956e8aSYuval Mintz 20250d956e8aSYuval Mintz /* Find parity attentions first */ 20260d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 20270d956e8aSYuval Mintz struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i]; 20280d956e8aSYuval Mintz u32 en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 20290d956e8aSYuval Mintz MISC_REG_AEU_ENABLE1_IGU_OUT_0 + 20300d956e8aSYuval Mintz i * sizeof(u32)); 20310d956e8aSYuval Mintz u32 parities; 20320d956e8aSYuval Mintz 20330d956e8aSYuval Mintz /* Skip register in which no parity bit is currently set */ 20340d956e8aSYuval Mintz parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en; 20350d956e8aSYuval Mintz if (!parities) 20360d956e8aSYuval Mintz continue; 20370d956e8aSYuval Mintz 20380d956e8aSYuval Mintz for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 20390d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j]; 20400d956e8aSYuval Mintz 20410d956e8aSYuval Mintz if ((p_bit->flags & ATTENTION_PARITY) && 2042ff38577aSYuval Mintz !!(parities & (1 << bit_idx))) 2043ff38577aSYuval Mintz qed_int_deassertion_parity(p_hwfn, p_bit, 2044ff38577aSYuval Mintz bit_idx); 20450d956e8aSYuval Mintz 20460d956e8aSYuval Mintz bit_idx += ATTENTION_LENGTH(p_bit->flags); 20470d956e8aSYuval Mintz } 20480d956e8aSYuval Mintz } 20490d956e8aSYuval Mintz 20500d956e8aSYuval Mintz /* Find non-parity cause for attention and act */ 20510d956e8aSYuval Mintz for (k = 0; k < MAX_ATTN_GRPS; k++) { 20520d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_aeu; 20530d956e8aSYuval Mintz 20540d956e8aSYuval Mintz /* Handle only groups whose attention is currently deasserted */ 20550d956e8aSYuval Mintz if (!(deasserted_bits & (1 << k))) 20560d956e8aSYuval Mintz continue; 20570d956e8aSYuval Mintz 20580d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 20590d956e8aSYuval Mintz u32 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + 20600d956e8aSYuval Mintz i * sizeof(u32) + 20610d956e8aSYuval Mintz k * sizeof(u32) * NUM_ATTN_REGS; 20620d956e8aSYuval Mintz u32 en, bits; 20630d956e8aSYuval Mintz 20640d956e8aSYuval Mintz en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 20650d956e8aSYuval Mintz bits = aeu_inv_arr[i] & en; 20660d956e8aSYuval Mintz 20670d956e8aSYuval Mintz /* Skip if no bit from this group is currently set */ 20680d956e8aSYuval Mintz if (!bits) 20690d956e8aSYuval Mintz continue; 20700d956e8aSYuval Mintz 20710d956e8aSYuval Mintz /* Find all set bits from current register which belong 20720d956e8aSYuval Mintz * to current group, making them responsible for the 20730d956e8aSYuval Mintz * previous assertion. 20740d956e8aSYuval Mintz */ 20750d956e8aSYuval Mintz for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 20760d956e8aSYuval Mintz u8 bit, bit_len; 20770d956e8aSYuval Mintz u32 bitmask; 20780d956e8aSYuval Mintz 20790d956e8aSYuval Mintz p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j]; 20800d956e8aSYuval Mintz 20810d956e8aSYuval Mintz /* No need to handle parity-only bits */ 20820d956e8aSYuval Mintz if (p_aeu->flags == ATTENTION_PAR) 20830d956e8aSYuval Mintz continue; 20840d956e8aSYuval Mintz 20850d956e8aSYuval Mintz bit = bit_idx; 20860d956e8aSYuval Mintz bit_len = ATTENTION_LENGTH(p_aeu->flags); 20870d956e8aSYuval Mintz if (p_aeu->flags & ATTENTION_PAR_INT) { 20880d956e8aSYuval Mintz /* Skip Parity */ 20890d956e8aSYuval Mintz bit++; 20900d956e8aSYuval Mintz bit_len--; 20910d956e8aSYuval Mintz } 20920d956e8aSYuval Mintz 20930d956e8aSYuval Mintz bitmask = bits & (((1 << bit_len) - 1) << bit); 20940d956e8aSYuval Mintz if (bitmask) { 20950d956e8aSYuval Mintz /* Handle source of the attention */ 20960d956e8aSYuval Mintz qed_int_deassertion_aeu_bit(p_hwfn, 20970d956e8aSYuval Mintz p_aeu, 20980d956e8aSYuval Mintz aeu_en, 20990d956e8aSYuval Mintz bitmask); 21000d956e8aSYuval Mintz } 21010d956e8aSYuval Mintz 21020d956e8aSYuval Mintz bit_idx += ATTENTION_LENGTH(p_aeu->flags); 21030d956e8aSYuval Mintz } 21040d956e8aSYuval Mintz } 21050d956e8aSYuval Mintz } 2106cc875c2eSYuval Mintz 2107cc875c2eSYuval Mintz /* Clear IGU indication for the deasserted bits */ 2108cc875c2eSYuval Mintz DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 2109cc875c2eSYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 2110cc875c2eSYuval Mintz ((IGU_CMD_ATTN_BIT_CLR_UPPER - 2111cc875c2eSYuval Mintz IGU_CMD_INT_ACK_BASE) << 3), 2112cc875c2eSYuval Mintz ~((u32)deasserted_bits)); 2113cc875c2eSYuval Mintz 2114cc875c2eSYuval Mintz /* Unmask deasserted attentions in IGU */ 2115cc875c2eSYuval Mintz aeu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 2116cc875c2eSYuval Mintz IGU_REG_ATTENTION_ENABLE); 2117cc875c2eSYuval Mintz aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE); 2118cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask); 2119cc875c2eSYuval Mintz 2120cc875c2eSYuval Mintz /* Clear deassertion from inner state */ 2121cc875c2eSYuval Mintz sb_attn_sw->known_attn &= ~deasserted_bits; 2122cc875c2eSYuval Mintz 21230d956e8aSYuval Mintz return rc; 2124cc875c2eSYuval Mintz } 2125cc875c2eSYuval Mintz 2126cc875c2eSYuval Mintz static int qed_int_attentions(struct qed_hwfn *p_hwfn) 2127cc875c2eSYuval Mintz { 2128cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn; 2129cc875c2eSYuval Mintz struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn; 2130cc875c2eSYuval Mintz u32 attn_bits = 0, attn_acks = 0; 2131cc875c2eSYuval Mintz u16 asserted_bits, deasserted_bits; 2132cc875c2eSYuval Mintz __le16 index; 2133cc875c2eSYuval Mintz int rc = 0; 2134cc875c2eSYuval Mintz 2135cc875c2eSYuval Mintz /* Read current attention bits/acks - safeguard against attentions 2136cc875c2eSYuval Mintz * by guaranting work on a synchronized timeframe 2137cc875c2eSYuval Mintz */ 2138cc875c2eSYuval Mintz do { 2139cc875c2eSYuval Mintz index = p_sb_attn->sb_index; 2140cc875c2eSYuval Mintz attn_bits = le32_to_cpu(p_sb_attn->atten_bits); 2141cc875c2eSYuval Mintz attn_acks = le32_to_cpu(p_sb_attn->atten_ack); 2142cc875c2eSYuval Mintz } while (index != p_sb_attn->sb_index); 2143cc875c2eSYuval Mintz p_sb_attn->sb_index = index; 2144cc875c2eSYuval Mintz 2145cc875c2eSYuval Mintz /* Attention / Deassertion are meaningful (and in correct state) 2146cc875c2eSYuval Mintz * only when they differ and consistent with known state - deassertion 2147cc875c2eSYuval Mintz * when previous attention & current ack, and assertion when current 2148cc875c2eSYuval Mintz * attention with no previous attention 2149cc875c2eSYuval Mintz */ 2150cc875c2eSYuval Mintz asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) & 2151cc875c2eSYuval Mintz ~p_sb_attn_sw->known_attn; 2152cc875c2eSYuval Mintz deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) & 2153cc875c2eSYuval Mintz p_sb_attn_sw->known_attn; 2154cc875c2eSYuval Mintz 2155cc875c2eSYuval Mintz if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100)) { 2156cc875c2eSYuval Mintz DP_INFO(p_hwfn, 2157cc875c2eSYuval Mintz "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n", 2158cc875c2eSYuval Mintz index, attn_bits, attn_acks, asserted_bits, 2159cc875c2eSYuval Mintz deasserted_bits, p_sb_attn_sw->known_attn); 2160cc875c2eSYuval Mintz } else if (asserted_bits == 0x100) { 2161cc875c2eSYuval Mintz DP_INFO(p_hwfn, 2162cc875c2eSYuval Mintz "MFW indication via attention\n"); 2163cc875c2eSYuval Mintz } else { 2164cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2165cc875c2eSYuval Mintz "MFW indication [deassertion]\n"); 2166cc875c2eSYuval Mintz } 2167cc875c2eSYuval Mintz 2168cc875c2eSYuval Mintz if (asserted_bits) { 2169cc875c2eSYuval Mintz rc = qed_int_assertion(p_hwfn, asserted_bits); 2170cc875c2eSYuval Mintz if (rc) 2171cc875c2eSYuval Mintz return rc; 2172cc875c2eSYuval Mintz } 2173cc875c2eSYuval Mintz 2174cc875c2eSYuval Mintz if (deasserted_bits) { 2175cc875c2eSYuval Mintz rc = qed_int_deassertion(p_hwfn, deasserted_bits); 2176cc875c2eSYuval Mintz if (rc) 2177cc875c2eSYuval Mintz return rc; 2178cc875c2eSYuval Mintz } 2179cc875c2eSYuval Mintz 2180cc875c2eSYuval Mintz return rc; 2181cc875c2eSYuval Mintz } 2182cc875c2eSYuval Mintz 2183cc875c2eSYuval Mintz static void qed_sb_ack_attn(struct qed_hwfn *p_hwfn, 2184cc875c2eSYuval Mintz void __iomem *igu_addr, 2185cc875c2eSYuval Mintz u32 ack_cons) 2186cc875c2eSYuval Mintz { 2187cc875c2eSYuval Mintz struct igu_prod_cons_update igu_ack = { 0 }; 2188cc875c2eSYuval Mintz 2189cc875c2eSYuval Mintz igu_ack.sb_id_and_flags = 2190cc875c2eSYuval Mintz ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 2191cc875c2eSYuval Mintz (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 2192cc875c2eSYuval Mintz (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 2193cc875c2eSYuval Mintz (IGU_SEG_ACCESS_ATTN << 2194cc875c2eSYuval Mintz IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 2195cc875c2eSYuval Mintz 2196cc875c2eSYuval Mintz DIRECT_REG_WR(igu_addr, igu_ack.sb_id_and_flags); 2197cc875c2eSYuval Mintz 2198cc875c2eSYuval Mintz /* Both segments (interrupts & acks) are written to same place address; 2199cc875c2eSYuval Mintz * Need to guarantee all commands will be received (in-order) by HW. 2200cc875c2eSYuval Mintz */ 2201cc875c2eSYuval Mintz mmiowb(); 2202cc875c2eSYuval Mintz barrier(); 2203cc875c2eSYuval Mintz } 2204cc875c2eSYuval Mintz 2205fe56b9e6SYuval Mintz void qed_int_sp_dpc(unsigned long hwfn_cookie) 2206fe56b9e6SYuval Mintz { 2207fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = (struct qed_hwfn *)hwfn_cookie; 2208fe56b9e6SYuval Mintz struct qed_pi_info *pi_info = NULL; 2209cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn; 2210fe56b9e6SYuval Mintz struct qed_sb_info *sb_info; 2211fe56b9e6SYuval Mintz int arr_size; 2212fe56b9e6SYuval Mintz u16 rc = 0; 2213fe56b9e6SYuval Mintz 2214fe56b9e6SYuval Mintz if (!p_hwfn->p_sp_sb) { 2215fe56b9e6SYuval Mintz DP_ERR(p_hwfn->cdev, "DPC called - no p_sp_sb\n"); 2216fe56b9e6SYuval Mintz return; 2217fe56b9e6SYuval Mintz } 2218fe56b9e6SYuval Mintz 2219fe56b9e6SYuval Mintz sb_info = &p_hwfn->p_sp_sb->sb_info; 2220fe56b9e6SYuval Mintz arr_size = ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr); 2221fe56b9e6SYuval Mintz if (!sb_info) { 2222fe56b9e6SYuval Mintz DP_ERR(p_hwfn->cdev, 2223fe56b9e6SYuval Mintz "Status block is NULL - cannot ack interrupts\n"); 2224fe56b9e6SYuval Mintz return; 2225fe56b9e6SYuval Mintz } 2226fe56b9e6SYuval Mintz 2227cc875c2eSYuval Mintz if (!p_hwfn->p_sb_attn) { 2228cc875c2eSYuval Mintz DP_ERR(p_hwfn->cdev, "DPC called - no p_sb_attn"); 2229cc875c2eSYuval Mintz return; 2230cc875c2eSYuval Mintz } 2231cc875c2eSYuval Mintz sb_attn = p_hwfn->p_sb_attn; 2232cc875c2eSYuval Mintz 2233fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "DPC Called! (hwfn %p %d)\n", 2234fe56b9e6SYuval Mintz p_hwfn, p_hwfn->my_id); 2235fe56b9e6SYuval Mintz 2236fe56b9e6SYuval Mintz /* Disable ack for def status block. Required both for msix + 2237fe56b9e6SYuval Mintz * inta in non-mask mode, in inta does no harm. 2238fe56b9e6SYuval Mintz */ 2239fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_DISABLE, 0); 2240fe56b9e6SYuval Mintz 2241fe56b9e6SYuval Mintz /* Gather Interrupts/Attentions information */ 2242fe56b9e6SYuval Mintz if (!sb_info->sb_virt) { 2243fe56b9e6SYuval Mintz DP_ERR( 2244fe56b9e6SYuval Mintz p_hwfn->cdev, 2245fe56b9e6SYuval Mintz "Interrupt Status block is NULL - cannot check for new interrupts!\n"); 2246fe56b9e6SYuval Mintz } else { 2247fe56b9e6SYuval Mintz u32 tmp_index = sb_info->sb_ack; 2248fe56b9e6SYuval Mintz 2249fe56b9e6SYuval Mintz rc = qed_sb_update_sb_idx(sb_info); 2250fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 2251fe56b9e6SYuval Mintz "Interrupt indices: 0x%08x --> 0x%08x\n", 2252fe56b9e6SYuval Mintz tmp_index, sb_info->sb_ack); 2253fe56b9e6SYuval Mintz } 2254fe56b9e6SYuval Mintz 2255cc875c2eSYuval Mintz if (!sb_attn || !sb_attn->sb_attn) { 2256cc875c2eSYuval Mintz DP_ERR( 2257cc875c2eSYuval Mintz p_hwfn->cdev, 2258cc875c2eSYuval Mintz "Attentions Status block is NULL - cannot check for new attentions!\n"); 2259cc875c2eSYuval Mintz } else { 2260cc875c2eSYuval Mintz u16 tmp_index = sb_attn->index; 2261cc875c2eSYuval Mintz 2262cc875c2eSYuval Mintz rc |= qed_attn_update_idx(p_hwfn, sb_attn); 2263cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 2264cc875c2eSYuval Mintz "Attention indices: 0x%08x --> 0x%08x\n", 2265cc875c2eSYuval Mintz tmp_index, sb_attn->index); 2266cc875c2eSYuval Mintz } 2267cc875c2eSYuval Mintz 2268fe56b9e6SYuval Mintz /* Check if we expect interrupts at this time. if not just ack them */ 2269fe56b9e6SYuval Mintz if (!(rc & QED_SB_EVENT_MASK)) { 2270fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 2271fe56b9e6SYuval Mintz return; 2272fe56b9e6SYuval Mintz } 2273fe56b9e6SYuval Mintz 2274fe56b9e6SYuval Mintz /* Check the validity of the DPC ptt. If not ack interrupts and fail */ 2275fe56b9e6SYuval Mintz if (!p_hwfn->p_dpc_ptt) { 2276fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn->cdev, "Failed to allocate PTT\n"); 2277fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 2278fe56b9e6SYuval Mintz return; 2279fe56b9e6SYuval Mintz } 2280fe56b9e6SYuval Mintz 2281cc875c2eSYuval Mintz if (rc & QED_SB_ATT_IDX) 2282cc875c2eSYuval Mintz qed_int_attentions(p_hwfn); 2283cc875c2eSYuval Mintz 2284fe56b9e6SYuval Mintz if (rc & QED_SB_IDX) { 2285fe56b9e6SYuval Mintz int pi; 2286fe56b9e6SYuval Mintz 2287fe56b9e6SYuval Mintz /* Look for a free index */ 2288fe56b9e6SYuval Mintz for (pi = 0; pi < arr_size; pi++) { 2289fe56b9e6SYuval Mintz pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi]; 2290fe56b9e6SYuval Mintz if (pi_info->comp_cb) 2291fe56b9e6SYuval Mintz pi_info->comp_cb(p_hwfn, pi_info->cookie); 2292fe56b9e6SYuval Mintz } 2293fe56b9e6SYuval Mintz } 2294fe56b9e6SYuval Mintz 2295cc875c2eSYuval Mintz if (sb_attn && (rc & QED_SB_ATT_IDX)) 2296cc875c2eSYuval Mintz /* This should be done before the interrupts are enabled, 2297cc875c2eSYuval Mintz * since otherwise a new attention will be generated. 2298cc875c2eSYuval Mintz */ 2299cc875c2eSYuval Mintz qed_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index); 2300cc875c2eSYuval Mintz 2301fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 2302fe56b9e6SYuval Mintz } 2303fe56b9e6SYuval Mintz 2304cc875c2eSYuval Mintz static void qed_int_sb_attn_free(struct qed_hwfn *p_hwfn) 2305cc875c2eSYuval Mintz { 2306cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb = p_hwfn->p_sb_attn; 2307cc875c2eSYuval Mintz 23084ac801b7SYuval Mintz if (!p_sb) 23094ac801b7SYuval Mintz return; 23104ac801b7SYuval Mintz 2311cc875c2eSYuval Mintz if (p_sb->sb_attn) 23124ac801b7SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 2313cc875c2eSYuval Mintz SB_ATTN_ALIGNED_SIZE(p_hwfn), 2314cc875c2eSYuval Mintz p_sb->sb_attn, 2315cc875c2eSYuval Mintz p_sb->sb_phys); 2316cc875c2eSYuval Mintz kfree(p_sb); 2317cc875c2eSYuval Mintz } 2318cc875c2eSYuval Mintz 2319cc875c2eSYuval Mintz static void qed_int_sb_attn_setup(struct qed_hwfn *p_hwfn, 2320cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 2321cc875c2eSYuval Mintz { 2322cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 2323cc875c2eSYuval Mintz 2324cc875c2eSYuval Mintz memset(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn)); 2325cc875c2eSYuval Mintz 2326cc875c2eSYuval Mintz sb_info->index = 0; 2327cc875c2eSYuval Mintz sb_info->known_attn = 0; 2328cc875c2eSYuval Mintz 2329cc875c2eSYuval Mintz /* Configure Attention Status Block in IGU */ 2330cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L, 2331cc875c2eSYuval Mintz lower_32_bits(p_hwfn->p_sb_attn->sb_phys)); 2332cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H, 2333cc875c2eSYuval Mintz upper_32_bits(p_hwfn->p_sb_attn->sb_phys)); 2334cc875c2eSYuval Mintz } 2335cc875c2eSYuval Mintz 2336cc875c2eSYuval Mintz static void qed_int_sb_attn_init(struct qed_hwfn *p_hwfn, 2337cc875c2eSYuval Mintz struct qed_ptt *p_ptt, 2338cc875c2eSYuval Mintz void *sb_virt_addr, 2339cc875c2eSYuval Mintz dma_addr_t sb_phy_addr) 2340cc875c2eSYuval Mintz { 2341cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 23420d956e8aSYuval Mintz int i, j, k; 2343cc875c2eSYuval Mintz 2344cc875c2eSYuval Mintz sb_info->sb_attn = sb_virt_addr; 2345cc875c2eSYuval Mintz sb_info->sb_phys = sb_phy_addr; 2346cc875c2eSYuval Mintz 23470d956e8aSYuval Mintz /* Set the pointer to the AEU descriptors */ 23480d956e8aSYuval Mintz sb_info->p_aeu_desc = aeu_descs; 23490d956e8aSYuval Mintz 23500d956e8aSYuval Mintz /* Calculate Parity Masks */ 23510d956e8aSYuval Mintz memset(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS); 23520d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 23530d956e8aSYuval Mintz /* j is array index, k is bit index */ 23540d956e8aSYuval Mintz for (j = 0, k = 0; k < 32; j++) { 23550d956e8aSYuval Mintz unsigned int flags = aeu_descs[i].bits[j].flags; 23560d956e8aSYuval Mintz 23570d956e8aSYuval Mintz if (flags & ATTENTION_PARITY) 23580d956e8aSYuval Mintz sb_info->parity_mask[i] |= 1 << k; 23590d956e8aSYuval Mintz 23600d956e8aSYuval Mintz k += ATTENTION_LENGTH(flags); 23610d956e8aSYuval Mintz } 23620d956e8aSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 23630d956e8aSYuval Mintz "Attn Mask [Reg %d]: 0x%08x\n", 23640d956e8aSYuval Mintz i, sb_info->parity_mask[i]); 23650d956e8aSYuval Mintz } 23660d956e8aSYuval Mintz 2367cc875c2eSYuval Mintz /* Set the address of cleanup for the mcp attention */ 2368cc875c2eSYuval Mintz sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) + 2369cc875c2eSYuval Mintz MISC_REG_AEU_GENERAL_ATTN_0; 2370cc875c2eSYuval Mintz 2371cc875c2eSYuval Mintz qed_int_sb_attn_setup(p_hwfn, p_ptt); 2372cc875c2eSYuval Mintz } 2373cc875c2eSYuval Mintz 2374cc875c2eSYuval Mintz static int qed_int_sb_attn_alloc(struct qed_hwfn *p_hwfn, 2375cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 2376cc875c2eSYuval Mintz { 2377cc875c2eSYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 2378cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb; 2379cc875c2eSYuval Mintz void *p_virt; 2380cc875c2eSYuval Mintz dma_addr_t p_phys = 0; 2381cc875c2eSYuval Mintz 2382cc875c2eSYuval Mintz /* SB struct */ 238360fffb3bSYuval Mintz p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 2384cc875c2eSYuval Mintz if (!p_sb) { 2385cc875c2eSYuval Mintz DP_NOTICE(cdev, "Failed to allocate `struct qed_sb_attn_info'\n"); 2386cc875c2eSYuval Mintz return -ENOMEM; 2387cc875c2eSYuval Mintz } 2388cc875c2eSYuval Mintz 2389cc875c2eSYuval Mintz /* SB ring */ 2390cc875c2eSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 2391cc875c2eSYuval Mintz SB_ATTN_ALIGNED_SIZE(p_hwfn), 2392cc875c2eSYuval Mintz &p_phys, GFP_KERNEL); 2393cc875c2eSYuval Mintz 2394cc875c2eSYuval Mintz if (!p_virt) { 2395cc875c2eSYuval Mintz DP_NOTICE(cdev, "Failed to allocate status block (attentions)\n"); 2396cc875c2eSYuval Mintz kfree(p_sb); 2397cc875c2eSYuval Mintz return -ENOMEM; 2398cc875c2eSYuval Mintz } 2399cc875c2eSYuval Mintz 2400cc875c2eSYuval Mintz /* Attention setup */ 2401cc875c2eSYuval Mintz p_hwfn->p_sb_attn = p_sb; 2402cc875c2eSYuval Mintz qed_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys); 2403cc875c2eSYuval Mintz 2404cc875c2eSYuval Mintz return 0; 2405cc875c2eSYuval Mintz } 2406cc875c2eSYuval Mintz 2407fe56b9e6SYuval Mintz /* coalescing timeout = timeset << (timer_res + 1) */ 2408fe56b9e6SYuval Mintz #define QED_CAU_DEF_RX_USECS 24 2409fe56b9e6SYuval Mintz #define QED_CAU_DEF_TX_USECS 48 2410fe56b9e6SYuval Mintz 2411fe56b9e6SYuval Mintz void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn, 2412fe56b9e6SYuval Mintz struct cau_sb_entry *p_sb_entry, 2413fe56b9e6SYuval Mintz u8 pf_id, 2414fe56b9e6SYuval Mintz u16 vf_number, 2415fe56b9e6SYuval Mintz u8 vf_valid) 2416fe56b9e6SYuval Mintz { 24174ac801b7SYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 2418fe56b9e6SYuval Mintz u32 cau_state; 2419fe56b9e6SYuval Mintz 2420fe56b9e6SYuval Mintz memset(p_sb_entry, 0, sizeof(*p_sb_entry)); 2421fe56b9e6SYuval Mintz 2422fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id); 2423fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number); 2424fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid); 2425fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F); 2426fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F); 2427fe56b9e6SYuval Mintz 2428fe56b9e6SYuval Mintz /* setting the time resultion to a fixed value ( = 1) */ 2429fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, 2430fe56b9e6SYuval Mintz QED_CAU_DEF_RX_TIMER_RES); 2431fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, 2432fe56b9e6SYuval Mintz QED_CAU_DEF_TX_TIMER_RES); 2433fe56b9e6SYuval Mintz 2434fe56b9e6SYuval Mintz cau_state = CAU_HC_DISABLE_STATE; 2435fe56b9e6SYuval Mintz 24364ac801b7SYuval Mintz if (cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 2437fe56b9e6SYuval Mintz cau_state = CAU_HC_ENABLE_STATE; 24384ac801b7SYuval Mintz if (!cdev->rx_coalesce_usecs) 24394ac801b7SYuval Mintz cdev->rx_coalesce_usecs = QED_CAU_DEF_RX_USECS; 24404ac801b7SYuval Mintz if (!cdev->tx_coalesce_usecs) 24414ac801b7SYuval Mintz cdev->tx_coalesce_usecs = QED_CAU_DEF_TX_USECS; 2442fe56b9e6SYuval Mintz } 2443fe56b9e6SYuval Mintz 2444fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state); 2445fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state); 2446fe56b9e6SYuval Mintz } 2447fe56b9e6SYuval Mintz 2448fe56b9e6SYuval Mintz void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn, 2449fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2450fe56b9e6SYuval Mintz dma_addr_t sb_phys, 2451fe56b9e6SYuval Mintz u16 igu_sb_id, 2452fe56b9e6SYuval Mintz u16 vf_number, 2453fe56b9e6SYuval Mintz u8 vf_valid) 2454fe56b9e6SYuval Mintz { 2455fe56b9e6SYuval Mintz struct cau_sb_entry sb_entry; 2456fe56b9e6SYuval Mintz 2457fe56b9e6SYuval Mintz qed_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id, 2458fe56b9e6SYuval Mintz vf_number, vf_valid); 2459fe56b9e6SYuval Mintz 2460fe56b9e6SYuval Mintz if (p_hwfn->hw_init_done) { 24610a0c5d3bSYuval Mintz /* Wide-bus, initialize via DMAE */ 24620a0c5d3bSYuval Mintz u64 phys_addr = (u64)sb_phys; 2463fe56b9e6SYuval Mintz 24640a0c5d3bSYuval Mintz qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&phys_addr, 24650a0c5d3bSYuval Mintz CAU_REG_SB_ADDR_MEMORY + 24660a0c5d3bSYuval Mintz igu_sb_id * sizeof(u64), 2, 0); 24670a0c5d3bSYuval Mintz qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&sb_entry, 24680a0c5d3bSYuval Mintz CAU_REG_SB_VAR_MEMORY + 24690a0c5d3bSYuval Mintz igu_sb_id * sizeof(u64), 2, 0); 2470fe56b9e6SYuval Mintz } else { 2471fe56b9e6SYuval Mintz /* Initialize Status Block Address */ 2472fe56b9e6SYuval Mintz STORE_RT_REG_AGG(p_hwfn, 2473fe56b9e6SYuval Mintz CAU_REG_SB_ADDR_MEMORY_RT_OFFSET + 2474fe56b9e6SYuval Mintz igu_sb_id * 2, 2475fe56b9e6SYuval Mintz sb_phys); 2476fe56b9e6SYuval Mintz 2477fe56b9e6SYuval Mintz STORE_RT_REG_AGG(p_hwfn, 2478fe56b9e6SYuval Mintz CAU_REG_SB_VAR_MEMORY_RT_OFFSET + 2479fe56b9e6SYuval Mintz igu_sb_id * 2, 2480fe56b9e6SYuval Mintz sb_entry); 2481fe56b9e6SYuval Mintz } 2482fe56b9e6SYuval Mintz 2483fe56b9e6SYuval Mintz /* Configure pi coalescing if set */ 2484fe56b9e6SYuval Mintz if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 2485fe56b9e6SYuval Mintz u8 timeset = p_hwfn->cdev->rx_coalesce_usecs >> 2486fe56b9e6SYuval Mintz (QED_CAU_DEF_RX_TIMER_RES + 1); 2487fe56b9e6SYuval Mintz u8 num_tc = 1, i; 2488fe56b9e6SYuval Mintz 2489fe56b9e6SYuval Mintz qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI, 2490fe56b9e6SYuval Mintz QED_COAL_RX_STATE_MACHINE, 2491fe56b9e6SYuval Mintz timeset); 2492fe56b9e6SYuval Mintz 2493fe56b9e6SYuval Mintz timeset = p_hwfn->cdev->tx_coalesce_usecs >> 2494fe56b9e6SYuval Mintz (QED_CAU_DEF_TX_TIMER_RES + 1); 2495fe56b9e6SYuval Mintz 2496fe56b9e6SYuval Mintz for (i = 0; i < num_tc; i++) { 2497fe56b9e6SYuval Mintz qed_int_cau_conf_pi(p_hwfn, p_ptt, 2498fe56b9e6SYuval Mintz igu_sb_id, TX_PI(i), 2499fe56b9e6SYuval Mintz QED_COAL_TX_STATE_MACHINE, 2500fe56b9e6SYuval Mintz timeset); 2501fe56b9e6SYuval Mintz } 2502fe56b9e6SYuval Mintz } 2503fe56b9e6SYuval Mintz } 2504fe56b9e6SYuval Mintz 2505fe56b9e6SYuval Mintz void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn, 2506fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2507fe56b9e6SYuval Mintz u16 igu_sb_id, 2508fe56b9e6SYuval Mintz u32 pi_index, 2509fe56b9e6SYuval Mintz enum qed_coalescing_fsm coalescing_fsm, 2510fe56b9e6SYuval Mintz u8 timeset) 2511fe56b9e6SYuval Mintz { 2512fe56b9e6SYuval Mintz struct cau_pi_entry pi_entry; 2513fe56b9e6SYuval Mintz u32 sb_offset; 2514fe56b9e6SYuval Mintz u32 pi_offset; 2515fe56b9e6SYuval Mintz 2516fe56b9e6SYuval Mintz sb_offset = igu_sb_id * PIS_PER_SB; 2517fe56b9e6SYuval Mintz memset(&pi_entry, 0, sizeof(struct cau_pi_entry)); 2518fe56b9e6SYuval Mintz 2519fe56b9e6SYuval Mintz SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset); 2520fe56b9e6SYuval Mintz if (coalescing_fsm == QED_COAL_RX_STATE_MACHINE) 2521fe56b9e6SYuval Mintz SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0); 2522fe56b9e6SYuval Mintz else 2523fe56b9e6SYuval Mintz SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1); 2524fe56b9e6SYuval Mintz 2525fe56b9e6SYuval Mintz pi_offset = sb_offset + pi_index; 2526fe56b9e6SYuval Mintz if (p_hwfn->hw_init_done) { 2527fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 2528fe56b9e6SYuval Mintz CAU_REG_PI_MEMORY + pi_offset * sizeof(u32), 2529fe56b9e6SYuval Mintz *((u32 *)&(pi_entry))); 2530fe56b9e6SYuval Mintz } else { 2531fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, 2532fe56b9e6SYuval Mintz CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset, 2533fe56b9e6SYuval Mintz *((u32 *)&(pi_entry))); 2534fe56b9e6SYuval Mintz } 2535fe56b9e6SYuval Mintz } 2536fe56b9e6SYuval Mintz 2537fe56b9e6SYuval Mintz void qed_int_sb_setup(struct qed_hwfn *p_hwfn, 2538fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2539fe56b9e6SYuval Mintz struct qed_sb_info *sb_info) 2540fe56b9e6SYuval Mintz { 2541fe56b9e6SYuval Mintz /* zero status block and ack counter */ 2542fe56b9e6SYuval Mintz sb_info->sb_ack = 0; 2543fe56b9e6SYuval Mintz memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 2544fe56b9e6SYuval Mintz 2545fe56b9e6SYuval Mintz qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys, 2546fe56b9e6SYuval Mintz sb_info->igu_sb_id, 0, 0); 2547fe56b9e6SYuval Mintz } 2548fe56b9e6SYuval Mintz 2549fe56b9e6SYuval Mintz /** 2550fe56b9e6SYuval Mintz * @brief qed_get_igu_sb_id - given a sw sb_id return the 2551fe56b9e6SYuval Mintz * igu_sb_id 2552fe56b9e6SYuval Mintz * 2553fe56b9e6SYuval Mintz * @param p_hwfn 2554fe56b9e6SYuval Mintz * @param sb_id 2555fe56b9e6SYuval Mintz * 2556fe56b9e6SYuval Mintz * @return u16 2557fe56b9e6SYuval Mintz */ 2558fe56b9e6SYuval Mintz static u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, 2559fe56b9e6SYuval Mintz u16 sb_id) 2560fe56b9e6SYuval Mintz { 2561fe56b9e6SYuval Mintz u16 igu_sb_id; 2562fe56b9e6SYuval Mintz 2563fe56b9e6SYuval Mintz /* Assuming continuous set of IGU SBs dedicated for given PF */ 2564fe56b9e6SYuval Mintz if (sb_id == QED_SP_SB_ID) 2565fe56b9e6SYuval Mintz igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id; 2566fe56b9e6SYuval Mintz else 2567fe56b9e6SYuval Mintz igu_sb_id = sb_id + p_hwfn->hw_info.p_igu_info->igu_base_sb; 2568fe56b9e6SYuval Mintz 2569fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "SB [%s] index is 0x%04x\n", 2570fe56b9e6SYuval Mintz (sb_id == QED_SP_SB_ID) ? "DSB" : "non-DSB", igu_sb_id); 2571fe56b9e6SYuval Mintz 2572fe56b9e6SYuval Mintz return igu_sb_id; 2573fe56b9e6SYuval Mintz } 2574fe56b9e6SYuval Mintz 2575fe56b9e6SYuval Mintz int qed_int_sb_init(struct qed_hwfn *p_hwfn, 2576fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2577fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 2578fe56b9e6SYuval Mintz void *sb_virt_addr, 2579fe56b9e6SYuval Mintz dma_addr_t sb_phy_addr, 2580fe56b9e6SYuval Mintz u16 sb_id) 2581fe56b9e6SYuval Mintz { 2582fe56b9e6SYuval Mintz sb_info->sb_virt = sb_virt_addr; 2583fe56b9e6SYuval Mintz sb_info->sb_phys = sb_phy_addr; 2584fe56b9e6SYuval Mintz 2585fe56b9e6SYuval Mintz sb_info->igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id); 2586fe56b9e6SYuval Mintz 2587fe56b9e6SYuval Mintz if (sb_id != QED_SP_SB_ID) { 2588fe56b9e6SYuval Mintz p_hwfn->sbs_info[sb_id] = sb_info; 2589fe56b9e6SYuval Mintz p_hwfn->num_sbs++; 2590fe56b9e6SYuval Mintz } 2591fe56b9e6SYuval Mintz 2592fe56b9e6SYuval Mintz sb_info->cdev = p_hwfn->cdev; 2593fe56b9e6SYuval Mintz 2594fe56b9e6SYuval Mintz /* The igu address will hold the absolute address that needs to be 2595fe56b9e6SYuval Mintz * written to for a specific status block 2596fe56b9e6SYuval Mintz */ 2597fe56b9e6SYuval Mintz sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 2598fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 2599fe56b9e6SYuval Mintz (sb_info->igu_sb_id << 3); 2600fe56b9e6SYuval Mintz 2601fe56b9e6SYuval Mintz sb_info->flags |= QED_SB_INFO_INIT; 2602fe56b9e6SYuval Mintz 2603fe56b9e6SYuval Mintz qed_int_sb_setup(p_hwfn, p_ptt, sb_info); 2604fe56b9e6SYuval Mintz 2605fe56b9e6SYuval Mintz return 0; 2606fe56b9e6SYuval Mintz } 2607fe56b9e6SYuval Mintz 2608fe56b9e6SYuval Mintz int qed_int_sb_release(struct qed_hwfn *p_hwfn, 2609fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 2610fe56b9e6SYuval Mintz u16 sb_id) 2611fe56b9e6SYuval Mintz { 2612fe56b9e6SYuval Mintz if (sb_id == QED_SP_SB_ID) { 2613fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Do Not free sp sb using this function"); 2614fe56b9e6SYuval Mintz return -EINVAL; 2615fe56b9e6SYuval Mintz } 2616fe56b9e6SYuval Mintz 2617fe56b9e6SYuval Mintz /* zero status block and ack counter */ 2618fe56b9e6SYuval Mintz sb_info->sb_ack = 0; 2619fe56b9e6SYuval Mintz memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 2620fe56b9e6SYuval Mintz 26214ac801b7SYuval Mintz if (p_hwfn->sbs_info[sb_id] != NULL) { 2622fe56b9e6SYuval Mintz p_hwfn->sbs_info[sb_id] = NULL; 2623fe56b9e6SYuval Mintz p_hwfn->num_sbs--; 26244ac801b7SYuval Mintz } 2625fe56b9e6SYuval Mintz 2626fe56b9e6SYuval Mintz return 0; 2627fe56b9e6SYuval Mintz } 2628fe56b9e6SYuval Mintz 2629fe56b9e6SYuval Mintz static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn) 2630fe56b9e6SYuval Mintz { 2631fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb; 2632fe56b9e6SYuval Mintz 26334ac801b7SYuval Mintz if (!p_sb) 26344ac801b7SYuval Mintz return; 26354ac801b7SYuval Mintz 2636fe56b9e6SYuval Mintz if (p_sb->sb_info.sb_virt) 2637fe56b9e6SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 2638fe56b9e6SYuval Mintz SB_ALIGNED_SIZE(p_hwfn), 2639fe56b9e6SYuval Mintz p_sb->sb_info.sb_virt, 2640fe56b9e6SYuval Mintz p_sb->sb_info.sb_phys); 2641fe56b9e6SYuval Mintz kfree(p_sb); 2642fe56b9e6SYuval Mintz } 2643fe56b9e6SYuval Mintz 2644fe56b9e6SYuval Mintz static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn, 2645fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 2646fe56b9e6SYuval Mintz { 2647fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sb; 2648fe56b9e6SYuval Mintz dma_addr_t p_phys = 0; 2649fe56b9e6SYuval Mintz void *p_virt; 2650fe56b9e6SYuval Mintz 2651fe56b9e6SYuval Mintz /* SB struct */ 265260fffb3bSYuval Mintz p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 2653fe56b9e6SYuval Mintz if (!p_sb) { 2654fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed to allocate `struct qed_sb_info'\n"); 2655fe56b9e6SYuval Mintz return -ENOMEM; 2656fe56b9e6SYuval Mintz } 2657fe56b9e6SYuval Mintz 2658fe56b9e6SYuval Mintz /* SB ring */ 2659fe56b9e6SYuval Mintz p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 2660fe56b9e6SYuval Mintz SB_ALIGNED_SIZE(p_hwfn), 2661fe56b9e6SYuval Mintz &p_phys, GFP_KERNEL); 2662fe56b9e6SYuval Mintz if (!p_virt) { 2663fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed to allocate status block\n"); 2664fe56b9e6SYuval Mintz kfree(p_sb); 2665fe56b9e6SYuval Mintz return -ENOMEM; 2666fe56b9e6SYuval Mintz } 2667fe56b9e6SYuval Mintz 2668fe56b9e6SYuval Mintz /* Status Block setup */ 2669fe56b9e6SYuval Mintz p_hwfn->p_sp_sb = p_sb; 2670fe56b9e6SYuval Mintz qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt, 2671fe56b9e6SYuval Mintz p_phys, QED_SP_SB_ID); 2672fe56b9e6SYuval Mintz 2673fe56b9e6SYuval Mintz memset(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr)); 2674fe56b9e6SYuval Mintz 2675fe56b9e6SYuval Mintz return 0; 2676fe56b9e6SYuval Mintz } 2677fe56b9e6SYuval Mintz 2678fe56b9e6SYuval Mintz int qed_int_register_cb(struct qed_hwfn *p_hwfn, 2679fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb, 2680fe56b9e6SYuval Mintz void *cookie, 2681fe56b9e6SYuval Mintz u8 *sb_idx, 2682fe56b9e6SYuval Mintz __le16 **p_fw_cons) 2683fe56b9e6SYuval Mintz { 2684fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 26854ac801b7SYuval Mintz int rc = -ENOMEM; 2686fe56b9e6SYuval Mintz u8 pi; 2687fe56b9e6SYuval Mintz 2688fe56b9e6SYuval Mintz /* Look for a free index */ 2689fe56b9e6SYuval Mintz for (pi = 0; pi < ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) { 26904ac801b7SYuval Mintz if (p_sp_sb->pi_info_arr[pi].comp_cb) 26914ac801b7SYuval Mintz continue; 26924ac801b7SYuval Mintz 2693fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb; 2694fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].cookie = cookie; 2695fe56b9e6SYuval Mintz *sb_idx = pi; 2696fe56b9e6SYuval Mintz *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi]; 26974ac801b7SYuval Mintz rc = 0; 2698fe56b9e6SYuval Mintz break; 2699fe56b9e6SYuval Mintz } 2700fe56b9e6SYuval Mintz 27014ac801b7SYuval Mintz return rc; 2702fe56b9e6SYuval Mintz } 2703fe56b9e6SYuval Mintz 2704fe56b9e6SYuval Mintz int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi) 2705fe56b9e6SYuval Mintz { 2706fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 2707fe56b9e6SYuval Mintz 27084ac801b7SYuval Mintz if (p_sp_sb->pi_info_arr[pi].comp_cb == NULL) 27094ac801b7SYuval Mintz return -ENOMEM; 27104ac801b7SYuval Mintz 2711fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].comp_cb = NULL; 2712fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].cookie = NULL; 2713fe56b9e6SYuval Mintz 27144ac801b7SYuval Mintz return 0; 2715fe56b9e6SYuval Mintz } 2716fe56b9e6SYuval Mintz 2717fe56b9e6SYuval Mintz u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn) 2718fe56b9e6SYuval Mintz { 2719fe56b9e6SYuval Mintz return p_hwfn->p_sp_sb->sb_info.igu_sb_id; 2720fe56b9e6SYuval Mintz } 2721fe56b9e6SYuval Mintz 2722fe56b9e6SYuval Mintz void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn, 2723fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2724fe56b9e6SYuval Mintz enum qed_int_mode int_mode) 2725fe56b9e6SYuval Mintz { 2726cc875c2eSYuval Mintz u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN; 2727fe56b9e6SYuval Mintz 2728fe56b9e6SYuval Mintz p_hwfn->cdev->int_mode = int_mode; 2729fe56b9e6SYuval Mintz switch (p_hwfn->cdev->int_mode) { 2730fe56b9e6SYuval Mintz case QED_INT_MODE_INTA: 2731fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN; 2732fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 2733fe56b9e6SYuval Mintz break; 2734fe56b9e6SYuval Mintz 2735fe56b9e6SYuval Mintz case QED_INT_MODE_MSI: 2736fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 2737fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 2738fe56b9e6SYuval Mintz break; 2739fe56b9e6SYuval Mintz 2740fe56b9e6SYuval Mintz case QED_INT_MODE_MSIX: 2741fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 2742fe56b9e6SYuval Mintz break; 2743fe56b9e6SYuval Mintz case QED_INT_MODE_POLL: 2744fe56b9e6SYuval Mintz break; 2745fe56b9e6SYuval Mintz } 2746fe56b9e6SYuval Mintz 2747fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf); 2748fe56b9e6SYuval Mintz } 2749fe56b9e6SYuval Mintz 27508f16bc97SSudarsana Kalluru int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2751fe56b9e6SYuval Mintz enum qed_int_mode int_mode) 2752fe56b9e6SYuval Mintz { 27530d956e8aSYuval Mintz int rc; 2754fe56b9e6SYuval Mintz 27550d956e8aSYuval Mintz /* Configure AEU signal change to produce attentions */ 27560d956e8aSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0); 2757cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff); 2758cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff); 27590d956e8aSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff); 2760cc875c2eSYuval Mintz 2761fe56b9e6SYuval Mintz /* Flush the writes to IGU */ 2762fe56b9e6SYuval Mintz mmiowb(); 2763cc875c2eSYuval Mintz 2764cc875c2eSYuval Mintz /* Unmask AEU signals toward IGU */ 2765cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff); 27668f16bc97SSudarsana Kalluru if ((int_mode != QED_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) { 27678f16bc97SSudarsana Kalluru rc = qed_slowpath_irq_req(p_hwfn); 27688f16bc97SSudarsana Kalluru if (rc != 0) { 27698f16bc97SSudarsana Kalluru DP_NOTICE(p_hwfn, "Slowpath IRQ request failed\n"); 27708f16bc97SSudarsana Kalluru return -EINVAL; 27718f16bc97SSudarsana Kalluru } 27728f16bc97SSudarsana Kalluru p_hwfn->b_int_requested = true; 27738f16bc97SSudarsana Kalluru } 27748f16bc97SSudarsana Kalluru /* Enable interrupt Generation */ 27758f16bc97SSudarsana Kalluru qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode); 27768f16bc97SSudarsana Kalluru p_hwfn->b_int_enabled = 1; 27778f16bc97SSudarsana Kalluru 27788f16bc97SSudarsana Kalluru return rc; 2779fe56b9e6SYuval Mintz } 2780fe56b9e6SYuval Mintz 2781fe56b9e6SYuval Mintz void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, 2782fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 2783fe56b9e6SYuval Mintz { 2784fe56b9e6SYuval Mintz p_hwfn->b_int_enabled = 0; 2785fe56b9e6SYuval Mintz 2786fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0); 2787fe56b9e6SYuval Mintz } 2788fe56b9e6SYuval Mintz 2789fe56b9e6SYuval Mintz #define IGU_CLEANUP_SLEEP_LENGTH (1000) 2790fe56b9e6SYuval Mintz void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn, 2791fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2792fe56b9e6SYuval Mintz u32 sb_id, 2793fe56b9e6SYuval Mintz bool cleanup_set, 2794fe56b9e6SYuval Mintz u16 opaque_fid 2795fe56b9e6SYuval Mintz ) 2796fe56b9e6SYuval Mintz { 2797fe56b9e6SYuval Mintz u32 pxp_addr = IGU_CMD_INT_ACK_BASE + sb_id; 2798fe56b9e6SYuval Mintz u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH; 2799fe56b9e6SYuval Mintz u32 data = 0; 2800fe56b9e6SYuval Mintz u32 cmd_ctrl = 0; 2801fe56b9e6SYuval Mintz u32 val = 0; 2802fe56b9e6SYuval Mintz u32 sb_bit = 0; 2803fe56b9e6SYuval Mintz u32 sb_bit_addr = 0; 2804fe56b9e6SYuval Mintz 2805fe56b9e6SYuval Mintz /* Set the data field */ 2806fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0); 2807fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, 0); 2808fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET); 2809fe56b9e6SYuval Mintz 2810fe56b9e6SYuval Mintz /* Set the control register */ 2811fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr); 2812fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid); 2813fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR); 2814fe56b9e6SYuval Mintz 2815fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data); 2816fe56b9e6SYuval Mintz 2817fe56b9e6SYuval Mintz barrier(); 2818fe56b9e6SYuval Mintz 2819fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl); 2820fe56b9e6SYuval Mintz 2821fe56b9e6SYuval Mintz /* Flush the write to IGU */ 2822fe56b9e6SYuval Mintz mmiowb(); 2823fe56b9e6SYuval Mintz 2824fe56b9e6SYuval Mintz /* calculate where to read the status bit from */ 2825fe56b9e6SYuval Mintz sb_bit = 1 << (sb_id % 32); 2826fe56b9e6SYuval Mintz sb_bit_addr = sb_id / 32 * sizeof(u32); 2827fe56b9e6SYuval Mintz 2828fe56b9e6SYuval Mintz sb_bit_addr += IGU_REG_CLEANUP_STATUS_0; 2829fe56b9e6SYuval Mintz 2830fe56b9e6SYuval Mintz /* Now wait for the command to complete */ 2831fe56b9e6SYuval Mintz do { 2832fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, sb_bit_addr); 2833fe56b9e6SYuval Mintz 2834fe56b9e6SYuval Mintz if ((val & sb_bit) == (cleanup_set ? sb_bit : 0)) 2835fe56b9e6SYuval Mintz break; 2836fe56b9e6SYuval Mintz 2837fe56b9e6SYuval Mintz usleep_range(5000, 10000); 2838fe56b9e6SYuval Mintz } while (--sleep_cnt); 2839fe56b9e6SYuval Mintz 2840fe56b9e6SYuval Mintz if (!sleep_cnt) 2841fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 2842fe56b9e6SYuval Mintz "Timeout waiting for clear status 0x%08x [for sb %d]\n", 2843fe56b9e6SYuval Mintz val, sb_id); 2844fe56b9e6SYuval Mintz } 2845fe56b9e6SYuval Mintz 2846fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn, 2847fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2848fe56b9e6SYuval Mintz u32 sb_id, 2849fe56b9e6SYuval Mintz u16 opaque, 2850fe56b9e6SYuval Mintz bool b_set) 2851fe56b9e6SYuval Mintz { 2852fe56b9e6SYuval Mintz int pi; 2853fe56b9e6SYuval Mintz 2854fe56b9e6SYuval Mintz /* Set */ 2855fe56b9e6SYuval Mintz if (b_set) 2856fe56b9e6SYuval Mintz qed_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 1, opaque); 2857fe56b9e6SYuval Mintz 2858fe56b9e6SYuval Mintz /* Clear */ 2859fe56b9e6SYuval Mintz qed_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 0, opaque); 2860fe56b9e6SYuval Mintz 2861fe56b9e6SYuval Mintz /* Clear the CAU for the SB */ 2862fe56b9e6SYuval Mintz for (pi = 0; pi < 12; pi++) 2863fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 2864fe56b9e6SYuval Mintz CAU_REG_PI_MEMORY + (sb_id * 12 + pi) * 4, 0); 2865fe56b9e6SYuval Mintz } 2866fe56b9e6SYuval Mintz 2867fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn, 2868fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2869fe56b9e6SYuval Mintz bool b_set, 2870fe56b9e6SYuval Mintz bool b_slowpath) 2871fe56b9e6SYuval Mintz { 2872fe56b9e6SYuval Mintz u32 igu_base_sb = p_hwfn->hw_info.p_igu_info->igu_base_sb; 2873fe56b9e6SYuval Mintz u32 igu_sb_cnt = p_hwfn->hw_info.p_igu_info->igu_sb_cnt; 2874fe56b9e6SYuval Mintz u32 sb_id = 0; 2875fe56b9e6SYuval Mintz u32 val = 0; 2876fe56b9e6SYuval Mintz 2877fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION); 2878fe56b9e6SYuval Mintz val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN; 2879fe56b9e6SYuval Mintz val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN; 2880fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val); 2881fe56b9e6SYuval Mintz 2882fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2883fe56b9e6SYuval Mintz "IGU cleaning SBs [%d,...,%d]\n", 2884fe56b9e6SYuval Mintz igu_base_sb, igu_base_sb + igu_sb_cnt - 1); 2885fe56b9e6SYuval Mintz 2886fe56b9e6SYuval Mintz for (sb_id = igu_base_sb; sb_id < igu_base_sb + igu_sb_cnt; sb_id++) 2887fe56b9e6SYuval Mintz qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id, 2888fe56b9e6SYuval Mintz p_hwfn->hw_info.opaque_fid, 2889fe56b9e6SYuval Mintz b_set); 2890fe56b9e6SYuval Mintz 2891fe56b9e6SYuval Mintz if (b_slowpath) { 2892fe56b9e6SYuval Mintz sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id; 2893fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2894fe56b9e6SYuval Mintz "IGU cleaning slowpath SB [%d]\n", sb_id); 2895fe56b9e6SYuval Mintz qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id, 2896fe56b9e6SYuval Mintz p_hwfn->hw_info.opaque_fid, 2897fe56b9e6SYuval Mintz b_set); 2898fe56b9e6SYuval Mintz } 2899fe56b9e6SYuval Mintz } 2900fe56b9e6SYuval Mintz 29014ac801b7SYuval Mintz static u32 qed_int_igu_read_cam_block(struct qed_hwfn *p_hwfn, 29024ac801b7SYuval Mintz struct qed_ptt *p_ptt, 29034ac801b7SYuval Mintz u16 sb_id) 29044ac801b7SYuval Mintz { 29054ac801b7SYuval Mintz u32 val = qed_rd(p_hwfn, p_ptt, 29064ac801b7SYuval Mintz IGU_REG_MAPPING_MEMORY + 29074ac801b7SYuval Mintz sizeof(u32) * sb_id); 29084ac801b7SYuval Mintz struct qed_igu_block *p_block; 29094ac801b7SYuval Mintz 29104ac801b7SYuval Mintz p_block = &p_hwfn->hw_info.p_igu_info->igu_map.igu_blocks[sb_id]; 29114ac801b7SYuval Mintz 29124ac801b7SYuval Mintz /* stop scanning when hit first invalid PF entry */ 29134ac801b7SYuval Mintz if (!GET_FIELD(val, IGU_MAPPING_LINE_VALID) && 29144ac801b7SYuval Mintz GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID)) 29154ac801b7SYuval Mintz goto out; 29164ac801b7SYuval Mintz 29174ac801b7SYuval Mintz /* Fill the block information */ 29184ac801b7SYuval Mintz p_block->status = QED_IGU_STATUS_VALID; 29194ac801b7SYuval Mintz p_block->function_id = GET_FIELD(val, 29204ac801b7SYuval Mintz IGU_MAPPING_LINE_FUNCTION_NUMBER); 29214ac801b7SYuval Mintz p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID); 29224ac801b7SYuval Mintz p_block->vector_number = GET_FIELD(val, 29234ac801b7SYuval Mintz IGU_MAPPING_LINE_VECTOR_NUMBER); 29244ac801b7SYuval Mintz 29254ac801b7SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 29264ac801b7SYuval Mintz "IGU_BLOCK: [SB 0x%04x, Value in CAM 0x%08x] func_id = %d is_pf = %d vector_num = 0x%x\n", 29274ac801b7SYuval Mintz sb_id, val, p_block->function_id, 29284ac801b7SYuval Mintz p_block->is_pf, p_block->vector_number); 29294ac801b7SYuval Mintz 29304ac801b7SYuval Mintz out: 29314ac801b7SYuval Mintz return val; 29324ac801b7SYuval Mintz } 29334ac801b7SYuval Mintz 2934fe56b9e6SYuval Mintz int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, 2935fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 2936fe56b9e6SYuval Mintz { 2937fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 2938fe56b9e6SYuval Mintz struct qed_igu_block *blk; 2939fe56b9e6SYuval Mintz u32 val; 2940fe56b9e6SYuval Mintz u16 sb_id; 2941fe56b9e6SYuval Mintz u16 prev_sb_id = 0xFF; 2942fe56b9e6SYuval Mintz 294360fffb3bSYuval Mintz p_hwfn->hw_info.p_igu_info = kzalloc(sizeof(*p_igu_info), GFP_KERNEL); 2944fe56b9e6SYuval Mintz 2945fe56b9e6SYuval Mintz if (!p_hwfn->hw_info.p_igu_info) 2946fe56b9e6SYuval Mintz return -ENOMEM; 2947fe56b9e6SYuval Mintz 2948fe56b9e6SYuval Mintz p_igu_info = p_hwfn->hw_info.p_igu_info; 2949fe56b9e6SYuval Mintz 2950fe56b9e6SYuval Mintz /* Initialize base sb / sb cnt for PFs */ 2951fe56b9e6SYuval Mintz p_igu_info->igu_base_sb = 0xffff; 2952fe56b9e6SYuval Mintz p_igu_info->igu_sb_cnt = 0; 2953fe56b9e6SYuval Mintz p_igu_info->igu_dsb_id = 0xffff; 2954fe56b9e6SYuval Mintz p_igu_info->igu_base_sb_iov = 0xffff; 2955fe56b9e6SYuval Mintz 2956fe56b9e6SYuval Mintz for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); 2957fe56b9e6SYuval Mintz sb_id++) { 2958fe56b9e6SYuval Mintz blk = &p_igu_info->igu_map.igu_blocks[sb_id]; 2959fe56b9e6SYuval Mintz 29604ac801b7SYuval Mintz val = qed_int_igu_read_cam_block(p_hwfn, p_ptt, sb_id); 2961fe56b9e6SYuval Mintz 2962fe56b9e6SYuval Mintz /* stop scanning when hit first invalid PF entry */ 2963fe56b9e6SYuval Mintz if (!GET_FIELD(val, IGU_MAPPING_LINE_VALID) && 2964fe56b9e6SYuval Mintz GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID)) 2965fe56b9e6SYuval Mintz break; 2966fe56b9e6SYuval Mintz 2967fe56b9e6SYuval Mintz if (blk->is_pf) { 2968fe56b9e6SYuval Mintz if (blk->function_id == p_hwfn->rel_pf_id) { 2969fe56b9e6SYuval Mintz blk->status |= QED_IGU_STATUS_PF; 2970fe56b9e6SYuval Mintz 2971fe56b9e6SYuval Mintz if (blk->vector_number == 0) { 2972fe56b9e6SYuval Mintz if (p_igu_info->igu_dsb_id == 0xffff) 2973fe56b9e6SYuval Mintz p_igu_info->igu_dsb_id = sb_id; 2974fe56b9e6SYuval Mintz } else { 2975fe56b9e6SYuval Mintz if (p_igu_info->igu_base_sb == 2976fe56b9e6SYuval Mintz 0xffff) { 2977fe56b9e6SYuval Mintz p_igu_info->igu_base_sb = sb_id; 2978fe56b9e6SYuval Mintz } else if (prev_sb_id != sb_id - 1) { 2979fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn->cdev, 2980fe56b9e6SYuval Mintz "consecutive igu vectors for HWFN %x broken", 2981fe56b9e6SYuval Mintz p_hwfn->rel_pf_id); 2982fe56b9e6SYuval Mintz break; 2983fe56b9e6SYuval Mintz } 2984fe56b9e6SYuval Mintz prev_sb_id = sb_id; 2985fe56b9e6SYuval Mintz /* we don't count the default */ 2986fe56b9e6SYuval Mintz (p_igu_info->igu_sb_cnt)++; 2987fe56b9e6SYuval Mintz } 2988fe56b9e6SYuval Mintz } 2989fe56b9e6SYuval Mintz } 2990fe56b9e6SYuval Mintz } 2991fe56b9e6SYuval Mintz 2992fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2993fe56b9e6SYuval Mintz "IGU igu_base_sb=0x%x igu_sb_cnt=%d igu_dsb_id=0x%x\n", 2994fe56b9e6SYuval Mintz p_igu_info->igu_base_sb, 2995fe56b9e6SYuval Mintz p_igu_info->igu_sb_cnt, 2996fe56b9e6SYuval Mintz p_igu_info->igu_dsb_id); 2997fe56b9e6SYuval Mintz 2998fe56b9e6SYuval Mintz if (p_igu_info->igu_base_sb == 0xffff || 2999fe56b9e6SYuval Mintz p_igu_info->igu_dsb_id == 0xffff || 3000fe56b9e6SYuval Mintz p_igu_info->igu_sb_cnt == 0) { 3001fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 3002fe56b9e6SYuval Mintz "IGU CAM returned invalid values igu_base_sb=0x%x igu_sb_cnt=%d igu_dsb_id=0x%x\n", 3003fe56b9e6SYuval Mintz p_igu_info->igu_base_sb, 3004fe56b9e6SYuval Mintz p_igu_info->igu_sb_cnt, 3005fe56b9e6SYuval Mintz p_igu_info->igu_dsb_id); 3006fe56b9e6SYuval Mintz return -EINVAL; 3007fe56b9e6SYuval Mintz } 3008fe56b9e6SYuval Mintz 3009fe56b9e6SYuval Mintz return 0; 3010fe56b9e6SYuval Mintz } 3011fe56b9e6SYuval Mintz 3012fe56b9e6SYuval Mintz /** 3013fe56b9e6SYuval Mintz * @brief Initialize igu runtime registers 3014fe56b9e6SYuval Mintz * 3015fe56b9e6SYuval Mintz * @param p_hwfn 3016fe56b9e6SYuval Mintz */ 3017fe56b9e6SYuval Mintz void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn) 3018fe56b9e6SYuval Mintz { 3019fe56b9e6SYuval Mintz u32 igu_pf_conf = 0; 3020fe56b9e6SYuval Mintz 3021fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_FUNC_EN; 3022fe56b9e6SYuval Mintz 3023fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf); 3024fe56b9e6SYuval Mintz } 3025fe56b9e6SYuval Mintz 3026fe56b9e6SYuval Mintz u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn) 3027fe56b9e6SYuval Mintz { 3028fe56b9e6SYuval Mintz u64 intr_status = 0; 3029fe56b9e6SYuval Mintz u32 intr_status_lo = 0; 3030fe56b9e6SYuval Mintz u32 intr_status_hi = 0; 3031fe56b9e6SYuval Mintz u32 lsb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - 3032fe56b9e6SYuval Mintz IGU_CMD_INT_ACK_BASE; 3033fe56b9e6SYuval Mintz u32 msb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - 3034fe56b9e6SYuval Mintz IGU_CMD_INT_ACK_BASE; 3035fe56b9e6SYuval Mintz 3036fe56b9e6SYuval Mintz intr_status_lo = REG_RD(p_hwfn, 3037fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 3038fe56b9e6SYuval Mintz lsb_igu_cmd_addr * 8); 3039fe56b9e6SYuval Mintz intr_status_hi = REG_RD(p_hwfn, 3040fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 3041fe56b9e6SYuval Mintz msb_igu_cmd_addr * 8); 3042fe56b9e6SYuval Mintz intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo; 3043fe56b9e6SYuval Mintz 3044fe56b9e6SYuval Mintz return intr_status; 3045fe56b9e6SYuval Mintz } 3046fe56b9e6SYuval Mintz 3047fe56b9e6SYuval Mintz static void qed_int_sp_dpc_setup(struct qed_hwfn *p_hwfn) 3048fe56b9e6SYuval Mintz { 3049fe56b9e6SYuval Mintz tasklet_init(p_hwfn->sp_dpc, 3050fe56b9e6SYuval Mintz qed_int_sp_dpc, (unsigned long)p_hwfn); 3051fe56b9e6SYuval Mintz p_hwfn->b_sp_dpc_enabled = true; 3052fe56b9e6SYuval Mintz } 3053fe56b9e6SYuval Mintz 3054fe56b9e6SYuval Mintz static int qed_int_sp_dpc_alloc(struct qed_hwfn *p_hwfn) 3055fe56b9e6SYuval Mintz { 305660fffb3bSYuval Mintz p_hwfn->sp_dpc = kmalloc(sizeof(*p_hwfn->sp_dpc), GFP_KERNEL); 3057fe56b9e6SYuval Mintz if (!p_hwfn->sp_dpc) 3058fe56b9e6SYuval Mintz return -ENOMEM; 3059fe56b9e6SYuval Mintz 3060fe56b9e6SYuval Mintz return 0; 3061fe56b9e6SYuval Mintz } 3062fe56b9e6SYuval Mintz 3063fe56b9e6SYuval Mintz static void qed_int_sp_dpc_free(struct qed_hwfn *p_hwfn) 3064fe56b9e6SYuval Mintz { 3065fe56b9e6SYuval Mintz kfree(p_hwfn->sp_dpc); 3066fe56b9e6SYuval Mintz } 3067fe56b9e6SYuval Mintz 3068fe56b9e6SYuval Mintz int qed_int_alloc(struct qed_hwfn *p_hwfn, 3069fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 3070fe56b9e6SYuval Mintz { 3071fe56b9e6SYuval Mintz int rc = 0; 3072fe56b9e6SYuval Mintz 3073fe56b9e6SYuval Mintz rc = qed_int_sp_dpc_alloc(p_hwfn); 3074fe56b9e6SYuval Mintz if (rc) { 3075fe56b9e6SYuval Mintz DP_ERR(p_hwfn->cdev, "Failed to allocate sp dpc mem\n"); 3076fe56b9e6SYuval Mintz return rc; 3077fe56b9e6SYuval Mintz } 3078fe56b9e6SYuval Mintz rc = qed_int_sp_sb_alloc(p_hwfn, p_ptt); 3079fe56b9e6SYuval Mintz if (rc) { 3080fe56b9e6SYuval Mintz DP_ERR(p_hwfn->cdev, "Failed to allocate sp sb mem\n"); 3081fe56b9e6SYuval Mintz return rc; 3082fe56b9e6SYuval Mintz } 3083cc875c2eSYuval Mintz rc = qed_int_sb_attn_alloc(p_hwfn, p_ptt); 3084cc875c2eSYuval Mintz if (rc) { 3085cc875c2eSYuval Mintz DP_ERR(p_hwfn->cdev, "Failed to allocate sb attn mem\n"); 3086cc875c2eSYuval Mintz return rc; 3087cc875c2eSYuval Mintz } 3088fe56b9e6SYuval Mintz return rc; 3089fe56b9e6SYuval Mintz } 3090fe56b9e6SYuval Mintz 3091fe56b9e6SYuval Mintz void qed_int_free(struct qed_hwfn *p_hwfn) 3092fe56b9e6SYuval Mintz { 3093fe56b9e6SYuval Mintz qed_int_sp_sb_free(p_hwfn); 3094cc875c2eSYuval Mintz qed_int_sb_attn_free(p_hwfn); 3095fe56b9e6SYuval Mintz qed_int_sp_dpc_free(p_hwfn); 3096fe56b9e6SYuval Mintz } 3097fe56b9e6SYuval Mintz 3098fe56b9e6SYuval Mintz void qed_int_setup(struct qed_hwfn *p_hwfn, 3099fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 3100fe56b9e6SYuval Mintz { 31010d956e8aSYuval Mintz qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info); 31020d956e8aSYuval Mintz qed_int_sb_attn_setup(p_hwfn, p_ptt); 3103fe56b9e6SYuval Mintz qed_int_sp_dpc_setup(p_hwfn); 3104fe56b9e6SYuval Mintz } 3105fe56b9e6SYuval Mintz 31064ac801b7SYuval Mintz void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn, 31074ac801b7SYuval Mintz struct qed_sb_cnt_info *p_sb_cnt_info) 3108fe56b9e6SYuval Mintz { 3109fe56b9e6SYuval Mintz struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info; 3110fe56b9e6SYuval Mintz 31114ac801b7SYuval Mintz if (!info || !p_sb_cnt_info) 31124ac801b7SYuval Mintz return; 3113fe56b9e6SYuval Mintz 31144ac801b7SYuval Mintz p_sb_cnt_info->sb_cnt = info->igu_sb_cnt; 31154ac801b7SYuval Mintz p_sb_cnt_info->sb_iov_cnt = info->igu_sb_cnt_iov; 31164ac801b7SYuval Mintz p_sb_cnt_info->sb_free_blk = info->free_blks; 3117fe56b9e6SYuval Mintz } 31188f16bc97SSudarsana Kalluru 31198f16bc97SSudarsana Kalluru void qed_int_disable_post_isr_release(struct qed_dev *cdev) 31208f16bc97SSudarsana Kalluru { 31218f16bc97SSudarsana Kalluru int i; 31228f16bc97SSudarsana Kalluru 31238f16bc97SSudarsana Kalluru for_each_hwfn(cdev, i) 31248f16bc97SSudarsana Kalluru cdev->hwfns[i].b_int_requested = false; 31258f16bc97SSudarsana Kalluru } 3126