1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #include <linux/types.h> 34fe56b9e6SYuval Mintz #include <asm/byteorder.h> 35fe56b9e6SYuval Mintz #include <linux/io.h> 36fe56b9e6SYuval Mintz #include <linux/bitops.h> 37fe56b9e6SYuval Mintz #include <linux/delay.h> 38fe56b9e6SYuval Mintz #include <linux/dma-mapping.h> 39fe56b9e6SYuval Mintz #include <linux/errno.h> 40fe56b9e6SYuval Mintz #include <linux/interrupt.h> 41fe56b9e6SYuval Mintz #include <linux/kernel.h> 42fe56b9e6SYuval Mintz #include <linux/pci.h> 43fe56b9e6SYuval Mintz #include <linux/slab.h> 44fe56b9e6SYuval Mintz #include <linux/string.h> 45fe56b9e6SYuval Mintz #include "qed.h" 46fe56b9e6SYuval Mintz #include "qed_hsi.h" 47fe56b9e6SYuval Mintz #include "qed_hw.h" 48fe56b9e6SYuval Mintz #include "qed_init_ops.h" 49fe56b9e6SYuval Mintz #include "qed_int.h" 50fe56b9e6SYuval Mintz #include "qed_mcp.h" 51fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 52fe56b9e6SYuval Mintz #include "qed_sp.h" 531408cc1fSYuval Mintz #include "qed_sriov.h" 541408cc1fSYuval Mintz #include "qed_vf.h" 55fe56b9e6SYuval Mintz 56fe56b9e6SYuval Mintz struct qed_pi_info { 57fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb; 58fe56b9e6SYuval Mintz void *cookie; 59fe56b9e6SYuval Mintz }; 60fe56b9e6SYuval Mintz 61fe56b9e6SYuval Mintz struct qed_sb_sp_info { 62fe56b9e6SYuval Mintz struct qed_sb_info sb_info; 63fe56b9e6SYuval Mintz 64fe56b9e6SYuval Mintz /* per protocol index data */ 65fe56b9e6SYuval Mintz struct qed_pi_info pi_info_arr[PIS_PER_SB]; 66fe56b9e6SYuval Mintz }; 67fe56b9e6SYuval Mintz 68ff38577aSYuval Mintz enum qed_attention_type { 69ff38577aSYuval Mintz QED_ATTN_TYPE_ATTN, 70ff38577aSYuval Mintz QED_ATTN_TYPE_PARITY, 71ff38577aSYuval Mintz }; 72ff38577aSYuval Mintz 73cc875c2eSYuval Mintz #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \ 74cc875c2eSYuval Mintz ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn) 75cc875c2eSYuval Mintz 760d956e8aSYuval Mintz struct aeu_invert_reg_bit { 770d956e8aSYuval Mintz char bit_name[30]; 780d956e8aSYuval Mintz 790d956e8aSYuval Mintz #define ATTENTION_PARITY (1 << 0) 800d956e8aSYuval Mintz 810d956e8aSYuval Mintz #define ATTENTION_LENGTH_MASK (0x00000ff0) 820d956e8aSYuval Mintz #define ATTENTION_LENGTH_SHIFT (4) 830d956e8aSYuval Mintz #define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \ 840d956e8aSYuval Mintz ATTENTION_LENGTH_SHIFT) 850d956e8aSYuval Mintz #define ATTENTION_SINGLE (1 << ATTENTION_LENGTH_SHIFT) 860d956e8aSYuval Mintz #define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY) 870d956e8aSYuval Mintz #define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \ 880d956e8aSYuval Mintz ATTENTION_PARITY) 890d956e8aSYuval Mintz 900d956e8aSYuval Mintz /* Multiple bits start with this offset */ 910d956e8aSYuval Mintz #define ATTENTION_OFFSET_MASK (0x000ff000) 920d956e8aSYuval Mintz #define ATTENTION_OFFSET_SHIFT (12) 930d956e8aSYuval Mintz unsigned int flags; 94ff38577aSYuval Mintz 95b4149dc7SYuval Mintz /* Callback to call if attention will be triggered */ 96b4149dc7SYuval Mintz int (*cb)(struct qed_hwfn *p_hwfn); 97b4149dc7SYuval Mintz 98ff38577aSYuval Mintz enum block_id block_index; 990d956e8aSYuval Mintz }; 1000d956e8aSYuval Mintz 1010d956e8aSYuval Mintz struct aeu_invert_reg { 1020d956e8aSYuval Mintz struct aeu_invert_reg_bit bits[32]; 1030d956e8aSYuval Mintz }; 1040d956e8aSYuval Mintz 1050d956e8aSYuval Mintz #define MAX_ATTN_GRPS (8) 1060d956e8aSYuval Mintz #define NUM_ATTN_REGS (9) 1070d956e8aSYuval Mintz 108ff38577aSYuval Mintz /* HW Attention register */ 109ff38577aSYuval Mintz struct attn_hw_reg { 110ff38577aSYuval Mintz u16 reg_idx; /* Index of this register in its block */ 111ff38577aSYuval Mintz u16 num_of_bits; /* number of valid attention bits */ 112ff38577aSYuval Mintz u32 sts_addr; /* Address of the STS register */ 113ff38577aSYuval Mintz u32 sts_clr_addr; /* Address of the STS_CLR register */ 114ff38577aSYuval Mintz u32 sts_wr_addr; /* Address of the STS_WR register */ 115ff38577aSYuval Mintz u32 mask_addr; /* Address of the MASK register */ 116ff38577aSYuval Mintz }; 117ff38577aSYuval Mintz 118ff38577aSYuval Mintz /* HW block attention registers */ 119ff38577aSYuval Mintz struct attn_hw_regs { 120ff38577aSYuval Mintz u16 num_of_int_regs; /* Number of interrupt regs */ 121ff38577aSYuval Mintz u16 num_of_prty_regs; /* Number of parity regs */ 122ff38577aSYuval Mintz struct attn_hw_reg **int_regs; /* interrupt regs */ 123ff38577aSYuval Mintz struct attn_hw_reg **prty_regs; /* parity regs */ 124ff38577aSYuval Mintz }; 125ff38577aSYuval Mintz 126ff38577aSYuval Mintz /* HW block attention registers */ 127ff38577aSYuval Mintz struct attn_hw_block { 128ff38577aSYuval Mintz const char *name; /* Block name */ 129ff38577aSYuval Mintz struct attn_hw_regs chip_regs[1]; 130ff38577aSYuval Mintz }; 131ff38577aSYuval Mintz 132ff38577aSYuval Mintz static struct attn_hw_reg grc_int0_bb_b0 = { 133ff38577aSYuval Mintz 0, 4, 0x50180, 0x5018c, 0x50188, 0x50184}; 134ff38577aSYuval Mintz 135ff38577aSYuval Mintz static struct attn_hw_reg *grc_int_bb_b0_regs[1] = { 136ff38577aSYuval Mintz &grc_int0_bb_b0}; 137ff38577aSYuval Mintz 138ff38577aSYuval Mintz static struct attn_hw_reg grc_prty1_bb_b0 = { 139ff38577aSYuval Mintz 0, 2, 0x50200, 0x5020c, 0x50208, 0x50204}; 140ff38577aSYuval Mintz 141ff38577aSYuval Mintz static struct attn_hw_reg *grc_prty_bb_b0_regs[1] = { 142ff38577aSYuval Mintz &grc_prty1_bb_b0}; 143ff38577aSYuval Mintz 144ff38577aSYuval Mintz static struct attn_hw_reg miscs_int0_bb_b0 = { 145ff38577aSYuval Mintz 0, 3, 0x9180, 0x918c, 0x9188, 0x9184}; 146ff38577aSYuval Mintz 147ff38577aSYuval Mintz static struct attn_hw_reg miscs_int1_bb_b0 = { 148ff38577aSYuval Mintz 1, 11, 0x9190, 0x919c, 0x9198, 0x9194}; 149ff38577aSYuval Mintz 150ff38577aSYuval Mintz static struct attn_hw_reg *miscs_int_bb_b0_regs[2] = { 151ff38577aSYuval Mintz &miscs_int0_bb_b0, &miscs_int1_bb_b0}; 152ff38577aSYuval Mintz 153ff38577aSYuval Mintz static struct attn_hw_reg miscs_prty0_bb_b0 = { 154ff38577aSYuval Mintz 0, 1, 0x91a0, 0x91ac, 0x91a8, 0x91a4}; 155ff38577aSYuval Mintz 156ff38577aSYuval Mintz static struct attn_hw_reg *miscs_prty_bb_b0_regs[1] = { 157ff38577aSYuval Mintz &miscs_prty0_bb_b0}; 158ff38577aSYuval Mintz 159ff38577aSYuval Mintz static struct attn_hw_reg misc_int0_bb_b0 = { 160ff38577aSYuval Mintz 0, 1, 0x8180, 0x818c, 0x8188, 0x8184}; 161ff38577aSYuval Mintz 162ff38577aSYuval Mintz static struct attn_hw_reg *misc_int_bb_b0_regs[1] = { 163ff38577aSYuval Mintz &misc_int0_bb_b0}; 164ff38577aSYuval Mintz 165ff38577aSYuval Mintz static struct attn_hw_reg pglue_b_int0_bb_b0 = { 166ff38577aSYuval Mintz 0, 23, 0x2a8180, 0x2a818c, 0x2a8188, 0x2a8184}; 167ff38577aSYuval Mintz 168ff38577aSYuval Mintz static struct attn_hw_reg *pglue_b_int_bb_b0_regs[1] = { 169ff38577aSYuval Mintz &pglue_b_int0_bb_b0}; 170ff38577aSYuval Mintz 171ff38577aSYuval Mintz static struct attn_hw_reg pglue_b_prty0_bb_b0 = { 172ff38577aSYuval Mintz 0, 1, 0x2a8190, 0x2a819c, 0x2a8198, 0x2a8194}; 173ff38577aSYuval Mintz 174ff38577aSYuval Mintz static struct attn_hw_reg pglue_b_prty1_bb_b0 = { 175ff38577aSYuval Mintz 1, 22, 0x2a8200, 0x2a820c, 0x2a8208, 0x2a8204}; 176ff38577aSYuval Mintz 177ff38577aSYuval Mintz static struct attn_hw_reg *pglue_b_prty_bb_b0_regs[2] = { 178ff38577aSYuval Mintz &pglue_b_prty0_bb_b0, &pglue_b_prty1_bb_b0}; 179ff38577aSYuval Mintz 180ff38577aSYuval Mintz static struct attn_hw_reg cnig_int0_bb_b0 = { 181ff38577aSYuval Mintz 0, 6, 0x2182e8, 0x2182f4, 0x2182f0, 0x2182ec}; 182ff38577aSYuval Mintz 183ff38577aSYuval Mintz static struct attn_hw_reg *cnig_int_bb_b0_regs[1] = { 184ff38577aSYuval Mintz &cnig_int0_bb_b0}; 185ff38577aSYuval Mintz 186ff38577aSYuval Mintz static struct attn_hw_reg cnig_prty0_bb_b0 = { 187ff38577aSYuval Mintz 0, 2, 0x218348, 0x218354, 0x218350, 0x21834c}; 188ff38577aSYuval Mintz 189ff38577aSYuval Mintz static struct attn_hw_reg *cnig_prty_bb_b0_regs[1] = { 190ff38577aSYuval Mintz &cnig_prty0_bb_b0}; 191ff38577aSYuval Mintz 192ff38577aSYuval Mintz static struct attn_hw_reg cpmu_int0_bb_b0 = { 193ff38577aSYuval Mintz 0, 1, 0x303e0, 0x303ec, 0x303e8, 0x303e4}; 194ff38577aSYuval Mintz 195ff38577aSYuval Mintz static struct attn_hw_reg *cpmu_int_bb_b0_regs[1] = { 196ff38577aSYuval Mintz &cpmu_int0_bb_b0}; 197ff38577aSYuval Mintz 198ff38577aSYuval Mintz static struct attn_hw_reg ncsi_int0_bb_b0 = { 199ff38577aSYuval Mintz 0, 1, 0x404cc, 0x404d8, 0x404d4, 0x404d0}; 200ff38577aSYuval Mintz 201ff38577aSYuval Mintz static struct attn_hw_reg *ncsi_int_bb_b0_regs[1] = { 202ff38577aSYuval Mintz &ncsi_int0_bb_b0}; 203ff38577aSYuval Mintz 204ff38577aSYuval Mintz static struct attn_hw_reg ncsi_prty1_bb_b0 = { 205ff38577aSYuval Mintz 0, 1, 0x40000, 0x4000c, 0x40008, 0x40004}; 206ff38577aSYuval Mintz 207ff38577aSYuval Mintz static struct attn_hw_reg *ncsi_prty_bb_b0_regs[1] = { 208ff38577aSYuval Mintz &ncsi_prty1_bb_b0}; 209ff38577aSYuval Mintz 210ff38577aSYuval Mintz static struct attn_hw_reg opte_prty1_bb_b0 = { 211ff38577aSYuval Mintz 0, 11, 0x53000, 0x5300c, 0x53008, 0x53004}; 212ff38577aSYuval Mintz 213ff38577aSYuval Mintz static struct attn_hw_reg opte_prty0_bb_b0 = { 214ff38577aSYuval Mintz 1, 1, 0x53208, 0x53214, 0x53210, 0x5320c}; 215ff38577aSYuval Mintz 216ff38577aSYuval Mintz static struct attn_hw_reg *opte_prty_bb_b0_regs[2] = { 217ff38577aSYuval Mintz &opte_prty1_bb_b0, &opte_prty0_bb_b0}; 218ff38577aSYuval Mintz 219ff38577aSYuval Mintz static struct attn_hw_reg bmb_int0_bb_b0 = { 220ff38577aSYuval Mintz 0, 16, 0x5400c0, 0x5400cc, 0x5400c8, 0x5400c4}; 221ff38577aSYuval Mintz 222ff38577aSYuval Mintz static struct attn_hw_reg bmb_int1_bb_b0 = { 223ff38577aSYuval Mintz 1, 28, 0x5400d8, 0x5400e4, 0x5400e0, 0x5400dc}; 224ff38577aSYuval Mintz 225ff38577aSYuval Mintz static struct attn_hw_reg bmb_int2_bb_b0 = { 226ff38577aSYuval Mintz 2, 26, 0x5400f0, 0x5400fc, 0x5400f8, 0x5400f4}; 227ff38577aSYuval Mintz 228ff38577aSYuval Mintz static struct attn_hw_reg bmb_int3_bb_b0 = { 229ff38577aSYuval Mintz 3, 31, 0x540108, 0x540114, 0x540110, 0x54010c}; 230ff38577aSYuval Mintz 231ff38577aSYuval Mintz static struct attn_hw_reg bmb_int4_bb_b0 = { 232ff38577aSYuval Mintz 4, 27, 0x540120, 0x54012c, 0x540128, 0x540124}; 233ff38577aSYuval Mintz 234ff38577aSYuval Mintz static struct attn_hw_reg bmb_int5_bb_b0 = { 235ff38577aSYuval Mintz 5, 29, 0x540138, 0x540144, 0x540140, 0x54013c}; 236ff38577aSYuval Mintz 237ff38577aSYuval Mintz static struct attn_hw_reg bmb_int6_bb_b0 = { 238ff38577aSYuval Mintz 6, 30, 0x540150, 0x54015c, 0x540158, 0x540154}; 239ff38577aSYuval Mintz 240ff38577aSYuval Mintz static struct attn_hw_reg bmb_int7_bb_b0 = { 241ff38577aSYuval Mintz 7, 32, 0x540168, 0x540174, 0x540170, 0x54016c}; 242ff38577aSYuval Mintz 243ff38577aSYuval Mintz static struct attn_hw_reg bmb_int8_bb_b0 = { 244ff38577aSYuval Mintz 8, 32, 0x540184, 0x540190, 0x54018c, 0x540188}; 245ff38577aSYuval Mintz 246ff38577aSYuval Mintz static struct attn_hw_reg bmb_int9_bb_b0 = { 247ff38577aSYuval Mintz 9, 32, 0x54019c, 0x5401a8, 0x5401a4, 0x5401a0}; 248ff38577aSYuval Mintz 249ff38577aSYuval Mintz static struct attn_hw_reg bmb_int10_bb_b0 = { 250ff38577aSYuval Mintz 10, 3, 0x5401b4, 0x5401c0, 0x5401bc, 0x5401b8}; 251ff38577aSYuval Mintz 252ff38577aSYuval Mintz static struct attn_hw_reg bmb_int11_bb_b0 = { 253ff38577aSYuval Mintz 11, 4, 0x5401cc, 0x5401d8, 0x5401d4, 0x5401d0}; 254ff38577aSYuval Mintz 255ff38577aSYuval Mintz static struct attn_hw_reg *bmb_int_bb_b0_regs[12] = { 256ff38577aSYuval Mintz &bmb_int0_bb_b0, &bmb_int1_bb_b0, &bmb_int2_bb_b0, &bmb_int3_bb_b0, 257ff38577aSYuval Mintz &bmb_int4_bb_b0, &bmb_int5_bb_b0, &bmb_int6_bb_b0, &bmb_int7_bb_b0, 258ff38577aSYuval Mintz &bmb_int8_bb_b0, &bmb_int9_bb_b0, &bmb_int10_bb_b0, &bmb_int11_bb_b0}; 259ff38577aSYuval Mintz 260ff38577aSYuval Mintz static struct attn_hw_reg bmb_prty0_bb_b0 = { 261ff38577aSYuval Mintz 0, 5, 0x5401dc, 0x5401e8, 0x5401e4, 0x5401e0}; 262ff38577aSYuval Mintz 263ff38577aSYuval Mintz static struct attn_hw_reg bmb_prty1_bb_b0 = { 264ff38577aSYuval Mintz 1, 31, 0x540400, 0x54040c, 0x540408, 0x540404}; 265ff38577aSYuval Mintz 266ff38577aSYuval Mintz static struct attn_hw_reg bmb_prty2_bb_b0 = { 267ff38577aSYuval Mintz 2, 15, 0x540410, 0x54041c, 0x540418, 0x540414}; 268ff38577aSYuval Mintz 269ff38577aSYuval Mintz static struct attn_hw_reg *bmb_prty_bb_b0_regs[3] = { 270ff38577aSYuval Mintz &bmb_prty0_bb_b0, &bmb_prty1_bb_b0, &bmb_prty2_bb_b0}; 271ff38577aSYuval Mintz 272ff38577aSYuval Mintz static struct attn_hw_reg pcie_prty1_bb_b0 = { 273ff38577aSYuval Mintz 0, 17, 0x54000, 0x5400c, 0x54008, 0x54004}; 274ff38577aSYuval Mintz 275ff38577aSYuval Mintz static struct attn_hw_reg *pcie_prty_bb_b0_regs[1] = { 276ff38577aSYuval Mintz &pcie_prty1_bb_b0}; 277ff38577aSYuval Mintz 278ff38577aSYuval Mintz static struct attn_hw_reg mcp2_prty0_bb_b0 = { 279ff38577aSYuval Mintz 0, 1, 0x52040, 0x5204c, 0x52048, 0x52044}; 280ff38577aSYuval Mintz 281ff38577aSYuval Mintz static struct attn_hw_reg mcp2_prty1_bb_b0 = { 282ff38577aSYuval Mintz 1, 12, 0x52204, 0x52210, 0x5220c, 0x52208}; 283ff38577aSYuval Mintz 284ff38577aSYuval Mintz static struct attn_hw_reg *mcp2_prty_bb_b0_regs[2] = { 285ff38577aSYuval Mintz &mcp2_prty0_bb_b0, &mcp2_prty1_bb_b0}; 286ff38577aSYuval Mintz 287ff38577aSYuval Mintz static struct attn_hw_reg pswhst_int0_bb_b0 = { 288ff38577aSYuval Mintz 0, 18, 0x2a0180, 0x2a018c, 0x2a0188, 0x2a0184}; 289ff38577aSYuval Mintz 290ff38577aSYuval Mintz static struct attn_hw_reg *pswhst_int_bb_b0_regs[1] = { 291ff38577aSYuval Mintz &pswhst_int0_bb_b0}; 292ff38577aSYuval Mintz 293ff38577aSYuval Mintz static struct attn_hw_reg pswhst_prty0_bb_b0 = { 294ff38577aSYuval Mintz 0, 1, 0x2a0190, 0x2a019c, 0x2a0198, 0x2a0194}; 295ff38577aSYuval Mintz 296ff38577aSYuval Mintz static struct attn_hw_reg pswhst_prty1_bb_b0 = { 297ff38577aSYuval Mintz 1, 17, 0x2a0200, 0x2a020c, 0x2a0208, 0x2a0204}; 298ff38577aSYuval Mintz 299ff38577aSYuval Mintz static struct attn_hw_reg *pswhst_prty_bb_b0_regs[2] = { 300ff38577aSYuval Mintz &pswhst_prty0_bb_b0, &pswhst_prty1_bb_b0}; 301ff38577aSYuval Mintz 302ff38577aSYuval Mintz static struct attn_hw_reg pswhst2_int0_bb_b0 = { 303ff38577aSYuval Mintz 0, 5, 0x29e180, 0x29e18c, 0x29e188, 0x29e184}; 304ff38577aSYuval Mintz 305ff38577aSYuval Mintz static struct attn_hw_reg *pswhst2_int_bb_b0_regs[1] = { 306ff38577aSYuval Mintz &pswhst2_int0_bb_b0}; 307ff38577aSYuval Mintz 308ff38577aSYuval Mintz static struct attn_hw_reg pswhst2_prty0_bb_b0 = { 309ff38577aSYuval Mintz 0, 1, 0x29e190, 0x29e19c, 0x29e198, 0x29e194}; 310ff38577aSYuval Mintz 311ff38577aSYuval Mintz static struct attn_hw_reg *pswhst2_prty_bb_b0_regs[1] = { 312ff38577aSYuval Mintz &pswhst2_prty0_bb_b0}; 313ff38577aSYuval Mintz 314ff38577aSYuval Mintz static struct attn_hw_reg pswrd_int0_bb_b0 = { 315ff38577aSYuval Mintz 0, 3, 0x29c180, 0x29c18c, 0x29c188, 0x29c184}; 316ff38577aSYuval Mintz 317ff38577aSYuval Mintz static struct attn_hw_reg *pswrd_int_bb_b0_regs[1] = { 318ff38577aSYuval Mintz &pswrd_int0_bb_b0}; 319ff38577aSYuval Mintz 320ff38577aSYuval Mintz static struct attn_hw_reg pswrd_prty0_bb_b0 = { 321ff38577aSYuval Mintz 0, 1, 0x29c190, 0x29c19c, 0x29c198, 0x29c194}; 322ff38577aSYuval Mintz 323ff38577aSYuval Mintz static struct attn_hw_reg *pswrd_prty_bb_b0_regs[1] = { 324ff38577aSYuval Mintz &pswrd_prty0_bb_b0}; 325ff38577aSYuval Mintz 326ff38577aSYuval Mintz static struct attn_hw_reg pswrd2_int0_bb_b0 = { 327ff38577aSYuval Mintz 0, 5, 0x29d180, 0x29d18c, 0x29d188, 0x29d184}; 328ff38577aSYuval Mintz 329ff38577aSYuval Mintz static struct attn_hw_reg *pswrd2_int_bb_b0_regs[1] = { 330ff38577aSYuval Mintz &pswrd2_int0_bb_b0}; 331ff38577aSYuval Mintz 332ff38577aSYuval Mintz static struct attn_hw_reg pswrd2_prty0_bb_b0 = { 333ff38577aSYuval Mintz 0, 1, 0x29d190, 0x29d19c, 0x29d198, 0x29d194}; 334ff38577aSYuval Mintz 335ff38577aSYuval Mintz static struct attn_hw_reg pswrd2_prty1_bb_b0 = { 336ff38577aSYuval Mintz 1, 31, 0x29d200, 0x29d20c, 0x29d208, 0x29d204}; 337ff38577aSYuval Mintz 338ff38577aSYuval Mintz static struct attn_hw_reg pswrd2_prty2_bb_b0 = { 339ff38577aSYuval Mintz 2, 3, 0x29d210, 0x29d21c, 0x29d218, 0x29d214}; 340ff38577aSYuval Mintz 341ff38577aSYuval Mintz static struct attn_hw_reg *pswrd2_prty_bb_b0_regs[3] = { 342ff38577aSYuval Mintz &pswrd2_prty0_bb_b0, &pswrd2_prty1_bb_b0, &pswrd2_prty2_bb_b0}; 343ff38577aSYuval Mintz 344ff38577aSYuval Mintz static struct attn_hw_reg pswwr_int0_bb_b0 = { 345ff38577aSYuval Mintz 0, 16, 0x29a180, 0x29a18c, 0x29a188, 0x29a184}; 346ff38577aSYuval Mintz 347ff38577aSYuval Mintz static struct attn_hw_reg *pswwr_int_bb_b0_regs[1] = { 348ff38577aSYuval Mintz &pswwr_int0_bb_b0}; 349ff38577aSYuval Mintz 350ff38577aSYuval Mintz static struct attn_hw_reg pswwr_prty0_bb_b0 = { 351ff38577aSYuval Mintz 0, 1, 0x29a190, 0x29a19c, 0x29a198, 0x29a194}; 352ff38577aSYuval Mintz 353ff38577aSYuval Mintz static struct attn_hw_reg *pswwr_prty_bb_b0_regs[1] = { 354ff38577aSYuval Mintz &pswwr_prty0_bb_b0}; 355ff38577aSYuval Mintz 356ff38577aSYuval Mintz static struct attn_hw_reg pswwr2_int0_bb_b0 = { 357ff38577aSYuval Mintz 0, 19, 0x29b180, 0x29b18c, 0x29b188, 0x29b184}; 358ff38577aSYuval Mintz 359ff38577aSYuval Mintz static struct attn_hw_reg *pswwr2_int_bb_b0_regs[1] = { 360ff38577aSYuval Mintz &pswwr2_int0_bb_b0}; 361ff38577aSYuval Mintz 362ff38577aSYuval Mintz static struct attn_hw_reg pswwr2_prty0_bb_b0 = { 363ff38577aSYuval Mintz 0, 1, 0x29b190, 0x29b19c, 0x29b198, 0x29b194}; 364ff38577aSYuval Mintz 365ff38577aSYuval Mintz static struct attn_hw_reg pswwr2_prty1_bb_b0 = { 366ff38577aSYuval Mintz 1, 31, 0x29b200, 0x29b20c, 0x29b208, 0x29b204}; 367ff38577aSYuval Mintz 368ff38577aSYuval Mintz static struct attn_hw_reg pswwr2_prty2_bb_b0 = { 369ff38577aSYuval Mintz 2, 31, 0x29b210, 0x29b21c, 0x29b218, 0x29b214}; 370ff38577aSYuval Mintz 371ff38577aSYuval Mintz static struct attn_hw_reg pswwr2_prty3_bb_b0 = { 372ff38577aSYuval Mintz 3, 31, 0x29b220, 0x29b22c, 0x29b228, 0x29b224}; 373ff38577aSYuval Mintz 374ff38577aSYuval Mintz static struct attn_hw_reg pswwr2_prty4_bb_b0 = { 375ff38577aSYuval Mintz 4, 20, 0x29b230, 0x29b23c, 0x29b238, 0x29b234}; 376ff38577aSYuval Mintz 377ff38577aSYuval Mintz static struct attn_hw_reg *pswwr2_prty_bb_b0_regs[5] = { 378ff38577aSYuval Mintz &pswwr2_prty0_bb_b0, &pswwr2_prty1_bb_b0, &pswwr2_prty2_bb_b0, 379ff38577aSYuval Mintz &pswwr2_prty3_bb_b0, &pswwr2_prty4_bb_b0}; 380ff38577aSYuval Mintz 381ff38577aSYuval Mintz static struct attn_hw_reg pswrq_int0_bb_b0 = { 382ff38577aSYuval Mintz 0, 21, 0x280180, 0x28018c, 0x280188, 0x280184}; 383ff38577aSYuval Mintz 384ff38577aSYuval Mintz static struct attn_hw_reg *pswrq_int_bb_b0_regs[1] = { 385ff38577aSYuval Mintz &pswrq_int0_bb_b0}; 386ff38577aSYuval Mintz 387ff38577aSYuval Mintz static struct attn_hw_reg pswrq_prty0_bb_b0 = { 388ff38577aSYuval Mintz 0, 1, 0x280190, 0x28019c, 0x280198, 0x280194}; 389ff38577aSYuval Mintz 390ff38577aSYuval Mintz static struct attn_hw_reg *pswrq_prty_bb_b0_regs[1] = { 391ff38577aSYuval Mintz &pswrq_prty0_bb_b0}; 392ff38577aSYuval Mintz 393ff38577aSYuval Mintz static struct attn_hw_reg pswrq2_int0_bb_b0 = { 394ff38577aSYuval Mintz 0, 15, 0x240180, 0x24018c, 0x240188, 0x240184}; 395ff38577aSYuval Mintz 396ff38577aSYuval Mintz static struct attn_hw_reg *pswrq2_int_bb_b0_regs[1] = { 397ff38577aSYuval Mintz &pswrq2_int0_bb_b0}; 398ff38577aSYuval Mintz 399ff38577aSYuval Mintz static struct attn_hw_reg pswrq2_prty1_bb_b0 = { 400ff38577aSYuval Mintz 0, 9, 0x240200, 0x24020c, 0x240208, 0x240204}; 401ff38577aSYuval Mintz 402ff38577aSYuval Mintz static struct attn_hw_reg *pswrq2_prty_bb_b0_regs[1] = { 403ff38577aSYuval Mintz &pswrq2_prty1_bb_b0}; 404ff38577aSYuval Mintz 405ff38577aSYuval Mintz static struct attn_hw_reg pglcs_int0_bb_b0 = { 406ff38577aSYuval Mintz 0, 1, 0x1d00, 0x1d0c, 0x1d08, 0x1d04}; 407ff38577aSYuval Mintz 408ff38577aSYuval Mintz static struct attn_hw_reg *pglcs_int_bb_b0_regs[1] = { 409ff38577aSYuval Mintz &pglcs_int0_bb_b0}; 410ff38577aSYuval Mintz 411ff38577aSYuval Mintz static struct attn_hw_reg dmae_int0_bb_b0 = { 412ff38577aSYuval Mintz 0, 2, 0xc180, 0xc18c, 0xc188, 0xc184}; 413ff38577aSYuval Mintz 414ff38577aSYuval Mintz static struct attn_hw_reg *dmae_int_bb_b0_regs[1] = { 415ff38577aSYuval Mintz &dmae_int0_bb_b0}; 416ff38577aSYuval Mintz 417ff38577aSYuval Mintz static struct attn_hw_reg dmae_prty1_bb_b0 = { 418ff38577aSYuval Mintz 0, 3, 0xc200, 0xc20c, 0xc208, 0xc204}; 419ff38577aSYuval Mintz 420ff38577aSYuval Mintz static struct attn_hw_reg *dmae_prty_bb_b0_regs[1] = { 421ff38577aSYuval Mintz &dmae_prty1_bb_b0}; 422ff38577aSYuval Mintz 423ff38577aSYuval Mintz static struct attn_hw_reg ptu_int0_bb_b0 = { 424ff38577aSYuval Mintz 0, 8, 0x560180, 0x56018c, 0x560188, 0x560184}; 425ff38577aSYuval Mintz 426ff38577aSYuval Mintz static struct attn_hw_reg *ptu_int_bb_b0_regs[1] = { 427ff38577aSYuval Mintz &ptu_int0_bb_b0}; 428ff38577aSYuval Mintz 429ff38577aSYuval Mintz static struct attn_hw_reg ptu_prty1_bb_b0 = { 430ff38577aSYuval Mintz 0, 18, 0x560200, 0x56020c, 0x560208, 0x560204}; 431ff38577aSYuval Mintz 432ff38577aSYuval Mintz static struct attn_hw_reg *ptu_prty_bb_b0_regs[1] = { 433ff38577aSYuval Mintz &ptu_prty1_bb_b0}; 434ff38577aSYuval Mintz 435ff38577aSYuval Mintz static struct attn_hw_reg tcm_int0_bb_b0 = { 436ff38577aSYuval Mintz 0, 8, 0x1180180, 0x118018c, 0x1180188, 0x1180184}; 437ff38577aSYuval Mintz 438ff38577aSYuval Mintz static struct attn_hw_reg tcm_int1_bb_b0 = { 439ff38577aSYuval Mintz 1, 32, 0x1180190, 0x118019c, 0x1180198, 0x1180194}; 440ff38577aSYuval Mintz 441ff38577aSYuval Mintz static struct attn_hw_reg tcm_int2_bb_b0 = { 442ff38577aSYuval Mintz 2, 1, 0x11801a0, 0x11801ac, 0x11801a8, 0x11801a4}; 443ff38577aSYuval Mintz 444ff38577aSYuval Mintz static struct attn_hw_reg *tcm_int_bb_b0_regs[3] = { 445ff38577aSYuval Mintz &tcm_int0_bb_b0, &tcm_int1_bb_b0, &tcm_int2_bb_b0}; 446ff38577aSYuval Mintz 447ff38577aSYuval Mintz static struct attn_hw_reg tcm_prty1_bb_b0 = { 448ff38577aSYuval Mintz 0, 31, 0x1180200, 0x118020c, 0x1180208, 0x1180204}; 449ff38577aSYuval Mintz 450ff38577aSYuval Mintz static struct attn_hw_reg tcm_prty2_bb_b0 = { 451ff38577aSYuval Mintz 1, 2, 0x1180210, 0x118021c, 0x1180218, 0x1180214}; 452ff38577aSYuval Mintz 453ff38577aSYuval Mintz static struct attn_hw_reg *tcm_prty_bb_b0_regs[2] = { 454ff38577aSYuval Mintz &tcm_prty1_bb_b0, &tcm_prty2_bb_b0}; 455ff38577aSYuval Mintz 456ff38577aSYuval Mintz static struct attn_hw_reg mcm_int0_bb_b0 = { 457ff38577aSYuval Mintz 0, 14, 0x1200180, 0x120018c, 0x1200188, 0x1200184}; 458ff38577aSYuval Mintz 459ff38577aSYuval Mintz static struct attn_hw_reg mcm_int1_bb_b0 = { 460ff38577aSYuval Mintz 1, 26, 0x1200190, 0x120019c, 0x1200198, 0x1200194}; 461ff38577aSYuval Mintz 462ff38577aSYuval Mintz static struct attn_hw_reg mcm_int2_bb_b0 = { 463ff38577aSYuval Mintz 2, 1, 0x12001a0, 0x12001ac, 0x12001a8, 0x12001a4}; 464ff38577aSYuval Mintz 465ff38577aSYuval Mintz static struct attn_hw_reg *mcm_int_bb_b0_regs[3] = { 466ff38577aSYuval Mintz &mcm_int0_bb_b0, &mcm_int1_bb_b0, &mcm_int2_bb_b0}; 467ff38577aSYuval Mintz 468ff38577aSYuval Mintz static struct attn_hw_reg mcm_prty1_bb_b0 = { 469ff38577aSYuval Mintz 0, 31, 0x1200200, 0x120020c, 0x1200208, 0x1200204}; 470ff38577aSYuval Mintz 471ff38577aSYuval Mintz static struct attn_hw_reg mcm_prty2_bb_b0 = { 472ff38577aSYuval Mintz 1, 4, 0x1200210, 0x120021c, 0x1200218, 0x1200214}; 473ff38577aSYuval Mintz 474ff38577aSYuval Mintz static struct attn_hw_reg *mcm_prty_bb_b0_regs[2] = { 475ff38577aSYuval Mintz &mcm_prty1_bb_b0, &mcm_prty2_bb_b0}; 476ff38577aSYuval Mintz 477ff38577aSYuval Mintz static struct attn_hw_reg ucm_int0_bb_b0 = { 478ff38577aSYuval Mintz 0, 17, 0x1280180, 0x128018c, 0x1280188, 0x1280184}; 479ff38577aSYuval Mintz 480ff38577aSYuval Mintz static struct attn_hw_reg ucm_int1_bb_b0 = { 481ff38577aSYuval Mintz 1, 29, 0x1280190, 0x128019c, 0x1280198, 0x1280194}; 482ff38577aSYuval Mintz 483ff38577aSYuval Mintz static struct attn_hw_reg ucm_int2_bb_b0 = { 484ff38577aSYuval Mintz 2, 1, 0x12801a0, 0x12801ac, 0x12801a8, 0x12801a4}; 485ff38577aSYuval Mintz 486ff38577aSYuval Mintz static struct attn_hw_reg *ucm_int_bb_b0_regs[3] = { 487ff38577aSYuval Mintz &ucm_int0_bb_b0, &ucm_int1_bb_b0, &ucm_int2_bb_b0}; 488ff38577aSYuval Mintz 489ff38577aSYuval Mintz static struct attn_hw_reg ucm_prty1_bb_b0 = { 490ff38577aSYuval Mintz 0, 31, 0x1280200, 0x128020c, 0x1280208, 0x1280204}; 491ff38577aSYuval Mintz 492ff38577aSYuval Mintz static struct attn_hw_reg ucm_prty2_bb_b0 = { 493ff38577aSYuval Mintz 1, 7, 0x1280210, 0x128021c, 0x1280218, 0x1280214}; 494ff38577aSYuval Mintz 495ff38577aSYuval Mintz static struct attn_hw_reg *ucm_prty_bb_b0_regs[2] = { 496ff38577aSYuval Mintz &ucm_prty1_bb_b0, &ucm_prty2_bb_b0}; 497ff38577aSYuval Mintz 498ff38577aSYuval Mintz static struct attn_hw_reg xcm_int0_bb_b0 = { 499ff38577aSYuval Mintz 0, 16, 0x1000180, 0x100018c, 0x1000188, 0x1000184}; 500ff38577aSYuval Mintz 501ff38577aSYuval Mintz static struct attn_hw_reg xcm_int1_bb_b0 = { 502ff38577aSYuval Mintz 1, 25, 0x1000190, 0x100019c, 0x1000198, 0x1000194}; 503ff38577aSYuval Mintz 504ff38577aSYuval Mintz static struct attn_hw_reg xcm_int2_bb_b0 = { 505ff38577aSYuval Mintz 2, 8, 0x10001a0, 0x10001ac, 0x10001a8, 0x10001a4}; 506ff38577aSYuval Mintz 507ff38577aSYuval Mintz static struct attn_hw_reg *xcm_int_bb_b0_regs[3] = { 508ff38577aSYuval Mintz &xcm_int0_bb_b0, &xcm_int1_bb_b0, &xcm_int2_bb_b0}; 509ff38577aSYuval Mintz 510ff38577aSYuval Mintz static struct attn_hw_reg xcm_prty1_bb_b0 = { 511ff38577aSYuval Mintz 0, 31, 0x1000200, 0x100020c, 0x1000208, 0x1000204}; 512ff38577aSYuval Mintz 513ff38577aSYuval Mintz static struct attn_hw_reg xcm_prty2_bb_b0 = { 514ff38577aSYuval Mintz 1, 11, 0x1000210, 0x100021c, 0x1000218, 0x1000214}; 515ff38577aSYuval Mintz 516ff38577aSYuval Mintz static struct attn_hw_reg *xcm_prty_bb_b0_regs[2] = { 517ff38577aSYuval Mintz &xcm_prty1_bb_b0, &xcm_prty2_bb_b0}; 518ff38577aSYuval Mintz 519ff38577aSYuval Mintz static struct attn_hw_reg ycm_int0_bb_b0 = { 520ff38577aSYuval Mintz 0, 13, 0x1080180, 0x108018c, 0x1080188, 0x1080184}; 521ff38577aSYuval Mintz 522ff38577aSYuval Mintz static struct attn_hw_reg ycm_int1_bb_b0 = { 523ff38577aSYuval Mintz 1, 23, 0x1080190, 0x108019c, 0x1080198, 0x1080194}; 524ff38577aSYuval Mintz 525ff38577aSYuval Mintz static struct attn_hw_reg ycm_int2_bb_b0 = { 526ff38577aSYuval Mintz 2, 1, 0x10801a0, 0x10801ac, 0x10801a8, 0x10801a4}; 527ff38577aSYuval Mintz 528ff38577aSYuval Mintz static struct attn_hw_reg *ycm_int_bb_b0_regs[3] = { 529ff38577aSYuval Mintz &ycm_int0_bb_b0, &ycm_int1_bb_b0, &ycm_int2_bb_b0}; 530ff38577aSYuval Mintz 531ff38577aSYuval Mintz static struct attn_hw_reg ycm_prty1_bb_b0 = { 532ff38577aSYuval Mintz 0, 31, 0x1080200, 0x108020c, 0x1080208, 0x1080204}; 533ff38577aSYuval Mintz 534ff38577aSYuval Mintz static struct attn_hw_reg ycm_prty2_bb_b0 = { 535ff38577aSYuval Mintz 1, 3, 0x1080210, 0x108021c, 0x1080218, 0x1080214}; 536ff38577aSYuval Mintz 537ff38577aSYuval Mintz static struct attn_hw_reg *ycm_prty_bb_b0_regs[2] = { 538ff38577aSYuval Mintz &ycm_prty1_bb_b0, &ycm_prty2_bb_b0}; 539ff38577aSYuval Mintz 540ff38577aSYuval Mintz static struct attn_hw_reg pcm_int0_bb_b0 = { 541ff38577aSYuval Mintz 0, 5, 0x1100180, 0x110018c, 0x1100188, 0x1100184}; 542ff38577aSYuval Mintz 543ff38577aSYuval Mintz static struct attn_hw_reg pcm_int1_bb_b0 = { 544ff38577aSYuval Mintz 1, 14, 0x1100190, 0x110019c, 0x1100198, 0x1100194}; 545ff38577aSYuval Mintz 546ff38577aSYuval Mintz static struct attn_hw_reg pcm_int2_bb_b0 = { 547ff38577aSYuval Mintz 2, 1, 0x11001a0, 0x11001ac, 0x11001a8, 0x11001a4}; 548ff38577aSYuval Mintz 549ff38577aSYuval Mintz static struct attn_hw_reg *pcm_int_bb_b0_regs[3] = { 550ff38577aSYuval Mintz &pcm_int0_bb_b0, &pcm_int1_bb_b0, &pcm_int2_bb_b0}; 551ff38577aSYuval Mintz 552ff38577aSYuval Mintz static struct attn_hw_reg pcm_prty1_bb_b0 = { 553ff38577aSYuval Mintz 0, 11, 0x1100200, 0x110020c, 0x1100208, 0x1100204}; 554ff38577aSYuval Mintz 555ff38577aSYuval Mintz static struct attn_hw_reg *pcm_prty_bb_b0_regs[1] = { 556ff38577aSYuval Mintz &pcm_prty1_bb_b0}; 557ff38577aSYuval Mintz 558ff38577aSYuval Mintz static struct attn_hw_reg qm_int0_bb_b0 = { 559ff38577aSYuval Mintz 0, 22, 0x2f0180, 0x2f018c, 0x2f0188, 0x2f0184}; 560ff38577aSYuval Mintz 561ff38577aSYuval Mintz static struct attn_hw_reg *qm_int_bb_b0_regs[1] = { 562ff38577aSYuval Mintz &qm_int0_bb_b0}; 563ff38577aSYuval Mintz 564ff38577aSYuval Mintz static struct attn_hw_reg qm_prty0_bb_b0 = { 565ff38577aSYuval Mintz 0, 11, 0x2f0190, 0x2f019c, 0x2f0198, 0x2f0194}; 566ff38577aSYuval Mintz 567ff38577aSYuval Mintz static struct attn_hw_reg qm_prty1_bb_b0 = { 568ff38577aSYuval Mintz 1, 31, 0x2f0200, 0x2f020c, 0x2f0208, 0x2f0204}; 569ff38577aSYuval Mintz 570ff38577aSYuval Mintz static struct attn_hw_reg qm_prty2_bb_b0 = { 571ff38577aSYuval Mintz 2, 31, 0x2f0210, 0x2f021c, 0x2f0218, 0x2f0214}; 572ff38577aSYuval Mintz 573ff38577aSYuval Mintz static struct attn_hw_reg qm_prty3_bb_b0 = { 574ff38577aSYuval Mintz 3, 11, 0x2f0220, 0x2f022c, 0x2f0228, 0x2f0224}; 575ff38577aSYuval Mintz 576ff38577aSYuval Mintz static struct attn_hw_reg *qm_prty_bb_b0_regs[4] = { 577ff38577aSYuval Mintz &qm_prty0_bb_b0, &qm_prty1_bb_b0, &qm_prty2_bb_b0, &qm_prty3_bb_b0}; 578ff38577aSYuval Mintz 579ff38577aSYuval Mintz static struct attn_hw_reg tm_int0_bb_b0 = { 580ff38577aSYuval Mintz 0, 32, 0x2c0180, 0x2c018c, 0x2c0188, 0x2c0184}; 581ff38577aSYuval Mintz 582ff38577aSYuval Mintz static struct attn_hw_reg tm_int1_bb_b0 = { 583ff38577aSYuval Mintz 1, 11, 0x2c0190, 0x2c019c, 0x2c0198, 0x2c0194}; 584ff38577aSYuval Mintz 585ff38577aSYuval Mintz static struct attn_hw_reg *tm_int_bb_b0_regs[2] = { 586ff38577aSYuval Mintz &tm_int0_bb_b0, &tm_int1_bb_b0}; 587ff38577aSYuval Mintz 588ff38577aSYuval Mintz static struct attn_hw_reg tm_prty1_bb_b0 = { 589ff38577aSYuval Mintz 0, 17, 0x2c0200, 0x2c020c, 0x2c0208, 0x2c0204}; 590ff38577aSYuval Mintz 591ff38577aSYuval Mintz static struct attn_hw_reg *tm_prty_bb_b0_regs[1] = { 592ff38577aSYuval Mintz &tm_prty1_bb_b0}; 593ff38577aSYuval Mintz 594ff38577aSYuval Mintz static struct attn_hw_reg dorq_int0_bb_b0 = { 595ff38577aSYuval Mintz 0, 9, 0x100180, 0x10018c, 0x100188, 0x100184}; 596ff38577aSYuval Mintz 597ff38577aSYuval Mintz static struct attn_hw_reg *dorq_int_bb_b0_regs[1] = { 598ff38577aSYuval Mintz &dorq_int0_bb_b0}; 599ff38577aSYuval Mintz 600ff38577aSYuval Mintz static struct attn_hw_reg dorq_prty0_bb_b0 = { 601ff38577aSYuval Mintz 0, 1, 0x100190, 0x10019c, 0x100198, 0x100194}; 602ff38577aSYuval Mintz 603ff38577aSYuval Mintz static struct attn_hw_reg dorq_prty1_bb_b0 = { 604ff38577aSYuval Mintz 1, 6, 0x100200, 0x10020c, 0x100208, 0x100204}; 605ff38577aSYuval Mintz 606ff38577aSYuval Mintz static struct attn_hw_reg *dorq_prty_bb_b0_regs[2] = { 607ff38577aSYuval Mintz &dorq_prty0_bb_b0, &dorq_prty1_bb_b0}; 608ff38577aSYuval Mintz 609ff38577aSYuval Mintz static struct attn_hw_reg brb_int0_bb_b0 = { 610ff38577aSYuval Mintz 0, 32, 0x3400c0, 0x3400cc, 0x3400c8, 0x3400c4}; 611ff38577aSYuval Mintz 612ff38577aSYuval Mintz static struct attn_hw_reg brb_int1_bb_b0 = { 613ff38577aSYuval Mintz 1, 30, 0x3400d8, 0x3400e4, 0x3400e0, 0x3400dc}; 614ff38577aSYuval Mintz 615ff38577aSYuval Mintz static struct attn_hw_reg brb_int2_bb_b0 = { 616ff38577aSYuval Mintz 2, 28, 0x3400f0, 0x3400fc, 0x3400f8, 0x3400f4}; 617ff38577aSYuval Mintz 618ff38577aSYuval Mintz static struct attn_hw_reg brb_int3_bb_b0 = { 619ff38577aSYuval Mintz 3, 31, 0x340108, 0x340114, 0x340110, 0x34010c}; 620ff38577aSYuval Mintz 621ff38577aSYuval Mintz static struct attn_hw_reg brb_int4_bb_b0 = { 622ff38577aSYuval Mintz 4, 27, 0x340120, 0x34012c, 0x340128, 0x340124}; 623ff38577aSYuval Mintz 624ff38577aSYuval Mintz static struct attn_hw_reg brb_int5_bb_b0 = { 625ff38577aSYuval Mintz 5, 1, 0x340138, 0x340144, 0x340140, 0x34013c}; 626ff38577aSYuval Mintz 627ff38577aSYuval Mintz static struct attn_hw_reg brb_int6_bb_b0 = { 628ff38577aSYuval Mintz 6, 8, 0x340150, 0x34015c, 0x340158, 0x340154}; 629ff38577aSYuval Mintz 630ff38577aSYuval Mintz static struct attn_hw_reg brb_int7_bb_b0 = { 631ff38577aSYuval Mintz 7, 32, 0x340168, 0x340174, 0x340170, 0x34016c}; 632ff38577aSYuval Mintz 633ff38577aSYuval Mintz static struct attn_hw_reg brb_int8_bb_b0 = { 634ff38577aSYuval Mintz 8, 17, 0x340184, 0x340190, 0x34018c, 0x340188}; 635ff38577aSYuval Mintz 636ff38577aSYuval Mintz static struct attn_hw_reg brb_int9_bb_b0 = { 637ff38577aSYuval Mintz 9, 1, 0x34019c, 0x3401a8, 0x3401a4, 0x3401a0}; 638ff38577aSYuval Mintz 639ff38577aSYuval Mintz static struct attn_hw_reg brb_int10_bb_b0 = { 640ff38577aSYuval Mintz 10, 14, 0x3401b4, 0x3401c0, 0x3401bc, 0x3401b8}; 641ff38577aSYuval Mintz 642ff38577aSYuval Mintz static struct attn_hw_reg brb_int11_bb_b0 = { 643ff38577aSYuval Mintz 11, 8, 0x3401cc, 0x3401d8, 0x3401d4, 0x3401d0}; 644ff38577aSYuval Mintz 645ff38577aSYuval Mintz static struct attn_hw_reg *brb_int_bb_b0_regs[12] = { 646ff38577aSYuval Mintz &brb_int0_bb_b0, &brb_int1_bb_b0, &brb_int2_bb_b0, &brb_int3_bb_b0, 647ff38577aSYuval Mintz &brb_int4_bb_b0, &brb_int5_bb_b0, &brb_int6_bb_b0, &brb_int7_bb_b0, 648ff38577aSYuval Mintz &brb_int8_bb_b0, &brb_int9_bb_b0, &brb_int10_bb_b0, &brb_int11_bb_b0}; 649ff38577aSYuval Mintz 650ff38577aSYuval Mintz static struct attn_hw_reg brb_prty0_bb_b0 = { 651ff38577aSYuval Mintz 0, 5, 0x3401dc, 0x3401e8, 0x3401e4, 0x3401e0}; 652ff38577aSYuval Mintz 653ff38577aSYuval Mintz static struct attn_hw_reg brb_prty1_bb_b0 = { 654ff38577aSYuval Mintz 1, 31, 0x340400, 0x34040c, 0x340408, 0x340404}; 655ff38577aSYuval Mintz 656ff38577aSYuval Mintz static struct attn_hw_reg brb_prty2_bb_b0 = { 657ff38577aSYuval Mintz 2, 14, 0x340410, 0x34041c, 0x340418, 0x340414}; 658ff38577aSYuval Mintz 659ff38577aSYuval Mintz static struct attn_hw_reg *brb_prty_bb_b0_regs[3] = { 660ff38577aSYuval Mintz &brb_prty0_bb_b0, &brb_prty1_bb_b0, &brb_prty2_bb_b0}; 661ff38577aSYuval Mintz 662ff38577aSYuval Mintz static struct attn_hw_reg src_int0_bb_b0 = { 663ff38577aSYuval Mintz 0, 1, 0x2381d8, 0x2381dc, 0x2381e0, 0x2381e4}; 664ff38577aSYuval Mintz 665ff38577aSYuval Mintz static struct attn_hw_reg *src_int_bb_b0_regs[1] = { 666ff38577aSYuval Mintz &src_int0_bb_b0}; 667ff38577aSYuval Mintz 668ff38577aSYuval Mintz static struct attn_hw_reg prs_int0_bb_b0 = { 669ff38577aSYuval Mintz 0, 2, 0x1f0040, 0x1f004c, 0x1f0048, 0x1f0044}; 670ff38577aSYuval Mintz 671ff38577aSYuval Mintz static struct attn_hw_reg *prs_int_bb_b0_regs[1] = { 672ff38577aSYuval Mintz &prs_int0_bb_b0}; 673ff38577aSYuval Mintz 674ff38577aSYuval Mintz static struct attn_hw_reg prs_prty0_bb_b0 = { 675ff38577aSYuval Mintz 0, 2, 0x1f0050, 0x1f005c, 0x1f0058, 0x1f0054}; 676ff38577aSYuval Mintz 677ff38577aSYuval Mintz static struct attn_hw_reg prs_prty1_bb_b0 = { 678ff38577aSYuval Mintz 1, 31, 0x1f0204, 0x1f0210, 0x1f020c, 0x1f0208}; 679ff38577aSYuval Mintz 680ff38577aSYuval Mintz static struct attn_hw_reg prs_prty2_bb_b0 = { 681ff38577aSYuval Mintz 2, 5, 0x1f0214, 0x1f0220, 0x1f021c, 0x1f0218}; 682ff38577aSYuval Mintz 683ff38577aSYuval Mintz static struct attn_hw_reg *prs_prty_bb_b0_regs[3] = { 684ff38577aSYuval Mintz &prs_prty0_bb_b0, &prs_prty1_bb_b0, &prs_prty2_bb_b0}; 685ff38577aSYuval Mintz 686ff38577aSYuval Mintz static struct attn_hw_reg tsdm_int0_bb_b0 = { 687ff38577aSYuval Mintz 0, 26, 0xfb0040, 0xfb004c, 0xfb0048, 0xfb0044}; 688ff38577aSYuval Mintz 689ff38577aSYuval Mintz static struct attn_hw_reg *tsdm_int_bb_b0_regs[1] = { 690ff38577aSYuval Mintz &tsdm_int0_bb_b0}; 691ff38577aSYuval Mintz 692ff38577aSYuval Mintz static struct attn_hw_reg tsdm_prty1_bb_b0 = { 693ff38577aSYuval Mintz 0, 10, 0xfb0200, 0xfb020c, 0xfb0208, 0xfb0204}; 694ff38577aSYuval Mintz 695ff38577aSYuval Mintz static struct attn_hw_reg *tsdm_prty_bb_b0_regs[1] = { 696ff38577aSYuval Mintz &tsdm_prty1_bb_b0}; 697ff38577aSYuval Mintz 698ff38577aSYuval Mintz static struct attn_hw_reg msdm_int0_bb_b0 = { 699ff38577aSYuval Mintz 0, 26, 0xfc0040, 0xfc004c, 0xfc0048, 0xfc0044}; 700ff38577aSYuval Mintz 701ff38577aSYuval Mintz static struct attn_hw_reg *msdm_int_bb_b0_regs[1] = { 702ff38577aSYuval Mintz &msdm_int0_bb_b0}; 703ff38577aSYuval Mintz 704ff38577aSYuval Mintz static struct attn_hw_reg msdm_prty1_bb_b0 = { 705ff38577aSYuval Mintz 0, 11, 0xfc0200, 0xfc020c, 0xfc0208, 0xfc0204}; 706ff38577aSYuval Mintz 707ff38577aSYuval Mintz static struct attn_hw_reg *msdm_prty_bb_b0_regs[1] = { 708ff38577aSYuval Mintz &msdm_prty1_bb_b0}; 709ff38577aSYuval Mintz 710ff38577aSYuval Mintz static struct attn_hw_reg usdm_int0_bb_b0 = { 711ff38577aSYuval Mintz 0, 26, 0xfd0040, 0xfd004c, 0xfd0048, 0xfd0044}; 712ff38577aSYuval Mintz 713ff38577aSYuval Mintz static struct attn_hw_reg *usdm_int_bb_b0_regs[1] = { 714ff38577aSYuval Mintz &usdm_int0_bb_b0}; 715ff38577aSYuval Mintz 716ff38577aSYuval Mintz static struct attn_hw_reg usdm_prty1_bb_b0 = { 717ff38577aSYuval Mintz 0, 10, 0xfd0200, 0xfd020c, 0xfd0208, 0xfd0204}; 718ff38577aSYuval Mintz 719ff38577aSYuval Mintz static struct attn_hw_reg *usdm_prty_bb_b0_regs[1] = { 720ff38577aSYuval Mintz &usdm_prty1_bb_b0}; 721ff38577aSYuval Mintz 722ff38577aSYuval Mintz static struct attn_hw_reg xsdm_int0_bb_b0 = { 723ff38577aSYuval Mintz 0, 26, 0xf80040, 0xf8004c, 0xf80048, 0xf80044}; 724ff38577aSYuval Mintz 725ff38577aSYuval Mintz static struct attn_hw_reg *xsdm_int_bb_b0_regs[1] = { 726ff38577aSYuval Mintz &xsdm_int0_bb_b0}; 727ff38577aSYuval Mintz 728ff38577aSYuval Mintz static struct attn_hw_reg xsdm_prty1_bb_b0 = { 729ff38577aSYuval Mintz 0, 10, 0xf80200, 0xf8020c, 0xf80208, 0xf80204}; 730ff38577aSYuval Mintz 731ff38577aSYuval Mintz static struct attn_hw_reg *xsdm_prty_bb_b0_regs[1] = { 732ff38577aSYuval Mintz &xsdm_prty1_bb_b0}; 733ff38577aSYuval Mintz 734ff38577aSYuval Mintz static struct attn_hw_reg ysdm_int0_bb_b0 = { 735ff38577aSYuval Mintz 0, 26, 0xf90040, 0xf9004c, 0xf90048, 0xf90044}; 736ff38577aSYuval Mintz 737ff38577aSYuval Mintz static struct attn_hw_reg *ysdm_int_bb_b0_regs[1] = { 738ff38577aSYuval Mintz &ysdm_int0_bb_b0}; 739ff38577aSYuval Mintz 740ff38577aSYuval Mintz static struct attn_hw_reg ysdm_prty1_bb_b0 = { 741ff38577aSYuval Mintz 0, 9, 0xf90200, 0xf9020c, 0xf90208, 0xf90204}; 742ff38577aSYuval Mintz 743ff38577aSYuval Mintz static struct attn_hw_reg *ysdm_prty_bb_b0_regs[1] = { 744ff38577aSYuval Mintz &ysdm_prty1_bb_b0}; 745ff38577aSYuval Mintz 746ff38577aSYuval Mintz static struct attn_hw_reg psdm_int0_bb_b0 = { 747ff38577aSYuval Mintz 0, 26, 0xfa0040, 0xfa004c, 0xfa0048, 0xfa0044}; 748ff38577aSYuval Mintz 749ff38577aSYuval Mintz static struct attn_hw_reg *psdm_int_bb_b0_regs[1] = { 750ff38577aSYuval Mintz &psdm_int0_bb_b0}; 751ff38577aSYuval Mintz 752ff38577aSYuval Mintz static struct attn_hw_reg psdm_prty1_bb_b0 = { 753ff38577aSYuval Mintz 0, 9, 0xfa0200, 0xfa020c, 0xfa0208, 0xfa0204}; 754ff38577aSYuval Mintz 755ff38577aSYuval Mintz static struct attn_hw_reg *psdm_prty_bb_b0_regs[1] = { 756ff38577aSYuval Mintz &psdm_prty1_bb_b0}; 757ff38577aSYuval Mintz 758ff38577aSYuval Mintz static struct attn_hw_reg tsem_int0_bb_b0 = { 759ff38577aSYuval Mintz 0, 32, 0x1700040, 0x170004c, 0x1700048, 0x1700044}; 760ff38577aSYuval Mintz 761ff38577aSYuval Mintz static struct attn_hw_reg tsem_int1_bb_b0 = { 762ff38577aSYuval Mintz 1, 13, 0x1700050, 0x170005c, 0x1700058, 0x1700054}; 763ff38577aSYuval Mintz 764ff38577aSYuval Mintz static struct attn_hw_reg tsem_fast_memory_int0_bb_b0 = { 765ff38577aSYuval Mintz 2, 1, 0x1740040, 0x174004c, 0x1740048, 0x1740044}; 766ff38577aSYuval Mintz 767ff38577aSYuval Mintz static struct attn_hw_reg *tsem_int_bb_b0_regs[3] = { 768ff38577aSYuval Mintz &tsem_int0_bb_b0, &tsem_int1_bb_b0, &tsem_fast_memory_int0_bb_b0}; 769ff38577aSYuval Mintz 770ff38577aSYuval Mintz static struct attn_hw_reg tsem_prty0_bb_b0 = { 771ff38577aSYuval Mintz 0, 3, 0x17000c8, 0x17000d4, 0x17000d0, 0x17000cc}; 772ff38577aSYuval Mintz 773ff38577aSYuval Mintz static struct attn_hw_reg tsem_prty1_bb_b0 = { 774ff38577aSYuval Mintz 1, 6, 0x1700200, 0x170020c, 0x1700208, 0x1700204}; 775ff38577aSYuval Mintz 776ff38577aSYuval Mintz static struct attn_hw_reg tsem_fast_memory_vfc_config_prty1_bb_b0 = { 777ff38577aSYuval Mintz 2, 6, 0x174a200, 0x174a20c, 0x174a208, 0x174a204}; 778ff38577aSYuval Mintz 779ff38577aSYuval Mintz static struct attn_hw_reg *tsem_prty_bb_b0_regs[3] = { 780ff38577aSYuval Mintz &tsem_prty0_bb_b0, &tsem_prty1_bb_b0, 781ff38577aSYuval Mintz &tsem_fast_memory_vfc_config_prty1_bb_b0}; 782ff38577aSYuval Mintz 783ff38577aSYuval Mintz static struct attn_hw_reg msem_int0_bb_b0 = { 784ff38577aSYuval Mintz 0, 32, 0x1800040, 0x180004c, 0x1800048, 0x1800044}; 785ff38577aSYuval Mintz 786ff38577aSYuval Mintz static struct attn_hw_reg msem_int1_bb_b0 = { 787ff38577aSYuval Mintz 1, 13, 0x1800050, 0x180005c, 0x1800058, 0x1800054}; 788ff38577aSYuval Mintz 789ff38577aSYuval Mintz static struct attn_hw_reg msem_fast_memory_int0_bb_b0 = { 790ff38577aSYuval Mintz 2, 1, 0x1840040, 0x184004c, 0x1840048, 0x1840044}; 791ff38577aSYuval Mintz 792ff38577aSYuval Mintz static struct attn_hw_reg *msem_int_bb_b0_regs[3] = { 793ff38577aSYuval Mintz &msem_int0_bb_b0, &msem_int1_bb_b0, &msem_fast_memory_int0_bb_b0}; 794ff38577aSYuval Mintz 795ff38577aSYuval Mintz static struct attn_hw_reg msem_prty0_bb_b0 = { 796ff38577aSYuval Mintz 0, 3, 0x18000c8, 0x18000d4, 0x18000d0, 0x18000cc}; 797ff38577aSYuval Mintz 798ff38577aSYuval Mintz static struct attn_hw_reg msem_prty1_bb_b0 = { 799ff38577aSYuval Mintz 1, 6, 0x1800200, 0x180020c, 0x1800208, 0x1800204}; 800ff38577aSYuval Mintz 801ff38577aSYuval Mintz static struct attn_hw_reg *msem_prty_bb_b0_regs[2] = { 802ff38577aSYuval Mintz &msem_prty0_bb_b0, &msem_prty1_bb_b0}; 803ff38577aSYuval Mintz 804ff38577aSYuval Mintz static struct attn_hw_reg usem_int0_bb_b0 = { 805ff38577aSYuval Mintz 0, 32, 0x1900040, 0x190004c, 0x1900048, 0x1900044}; 806ff38577aSYuval Mintz 807ff38577aSYuval Mintz static struct attn_hw_reg usem_int1_bb_b0 = { 808ff38577aSYuval Mintz 1, 13, 0x1900050, 0x190005c, 0x1900058, 0x1900054}; 809ff38577aSYuval Mintz 810ff38577aSYuval Mintz static struct attn_hw_reg usem_fast_memory_int0_bb_b0 = { 811ff38577aSYuval Mintz 2, 1, 0x1940040, 0x194004c, 0x1940048, 0x1940044}; 812ff38577aSYuval Mintz 813ff38577aSYuval Mintz static struct attn_hw_reg *usem_int_bb_b0_regs[3] = { 814ff38577aSYuval Mintz &usem_int0_bb_b0, &usem_int1_bb_b0, &usem_fast_memory_int0_bb_b0}; 815ff38577aSYuval Mintz 816ff38577aSYuval Mintz static struct attn_hw_reg usem_prty0_bb_b0 = { 817ff38577aSYuval Mintz 0, 3, 0x19000c8, 0x19000d4, 0x19000d0, 0x19000cc}; 818ff38577aSYuval Mintz 819ff38577aSYuval Mintz static struct attn_hw_reg usem_prty1_bb_b0 = { 820ff38577aSYuval Mintz 1, 6, 0x1900200, 0x190020c, 0x1900208, 0x1900204}; 821ff38577aSYuval Mintz 822ff38577aSYuval Mintz static struct attn_hw_reg *usem_prty_bb_b0_regs[2] = { 823ff38577aSYuval Mintz &usem_prty0_bb_b0, &usem_prty1_bb_b0}; 824ff38577aSYuval Mintz 825ff38577aSYuval Mintz static struct attn_hw_reg xsem_int0_bb_b0 = { 826ff38577aSYuval Mintz 0, 32, 0x1400040, 0x140004c, 0x1400048, 0x1400044}; 827ff38577aSYuval Mintz 828ff38577aSYuval Mintz static struct attn_hw_reg xsem_int1_bb_b0 = { 829ff38577aSYuval Mintz 1, 13, 0x1400050, 0x140005c, 0x1400058, 0x1400054}; 830ff38577aSYuval Mintz 831ff38577aSYuval Mintz static struct attn_hw_reg xsem_fast_memory_int0_bb_b0 = { 832ff38577aSYuval Mintz 2, 1, 0x1440040, 0x144004c, 0x1440048, 0x1440044}; 833ff38577aSYuval Mintz 834ff38577aSYuval Mintz static struct attn_hw_reg *xsem_int_bb_b0_regs[3] = { 835ff38577aSYuval Mintz &xsem_int0_bb_b0, &xsem_int1_bb_b0, &xsem_fast_memory_int0_bb_b0}; 836ff38577aSYuval Mintz 837ff38577aSYuval Mintz static struct attn_hw_reg xsem_prty0_bb_b0 = { 838ff38577aSYuval Mintz 0, 3, 0x14000c8, 0x14000d4, 0x14000d0, 0x14000cc}; 839ff38577aSYuval Mintz 840ff38577aSYuval Mintz static struct attn_hw_reg xsem_prty1_bb_b0 = { 841ff38577aSYuval Mintz 1, 7, 0x1400200, 0x140020c, 0x1400208, 0x1400204}; 842ff38577aSYuval Mintz 843ff38577aSYuval Mintz static struct attn_hw_reg *xsem_prty_bb_b0_regs[2] = { 844ff38577aSYuval Mintz &xsem_prty0_bb_b0, &xsem_prty1_bb_b0}; 845ff38577aSYuval Mintz 846ff38577aSYuval Mintz static struct attn_hw_reg ysem_int0_bb_b0 = { 847ff38577aSYuval Mintz 0, 32, 0x1500040, 0x150004c, 0x1500048, 0x1500044}; 848ff38577aSYuval Mintz 849ff38577aSYuval Mintz static struct attn_hw_reg ysem_int1_bb_b0 = { 850ff38577aSYuval Mintz 1, 13, 0x1500050, 0x150005c, 0x1500058, 0x1500054}; 851ff38577aSYuval Mintz 852ff38577aSYuval Mintz static struct attn_hw_reg ysem_fast_memory_int0_bb_b0 = { 853ff38577aSYuval Mintz 2, 1, 0x1540040, 0x154004c, 0x1540048, 0x1540044}; 854ff38577aSYuval Mintz 855ff38577aSYuval Mintz static struct attn_hw_reg *ysem_int_bb_b0_regs[3] = { 856ff38577aSYuval Mintz &ysem_int0_bb_b0, &ysem_int1_bb_b0, &ysem_fast_memory_int0_bb_b0}; 857ff38577aSYuval Mintz 858ff38577aSYuval Mintz static struct attn_hw_reg ysem_prty0_bb_b0 = { 859ff38577aSYuval Mintz 0, 3, 0x15000c8, 0x15000d4, 0x15000d0, 0x15000cc}; 860ff38577aSYuval Mintz 861ff38577aSYuval Mintz static struct attn_hw_reg ysem_prty1_bb_b0 = { 862ff38577aSYuval Mintz 1, 7, 0x1500200, 0x150020c, 0x1500208, 0x1500204}; 863ff38577aSYuval Mintz 864ff38577aSYuval Mintz static struct attn_hw_reg *ysem_prty_bb_b0_regs[2] = { 865ff38577aSYuval Mintz &ysem_prty0_bb_b0, &ysem_prty1_bb_b0}; 866ff38577aSYuval Mintz 867ff38577aSYuval Mintz static struct attn_hw_reg psem_int0_bb_b0 = { 868ff38577aSYuval Mintz 0, 32, 0x1600040, 0x160004c, 0x1600048, 0x1600044}; 869ff38577aSYuval Mintz 870ff38577aSYuval Mintz static struct attn_hw_reg psem_int1_bb_b0 = { 871ff38577aSYuval Mintz 1, 13, 0x1600050, 0x160005c, 0x1600058, 0x1600054}; 872ff38577aSYuval Mintz 873ff38577aSYuval Mintz static struct attn_hw_reg psem_fast_memory_int0_bb_b0 = { 874ff38577aSYuval Mintz 2, 1, 0x1640040, 0x164004c, 0x1640048, 0x1640044}; 875ff38577aSYuval Mintz 876ff38577aSYuval Mintz static struct attn_hw_reg *psem_int_bb_b0_regs[3] = { 877ff38577aSYuval Mintz &psem_int0_bb_b0, &psem_int1_bb_b0, &psem_fast_memory_int0_bb_b0}; 878ff38577aSYuval Mintz 879ff38577aSYuval Mintz static struct attn_hw_reg psem_prty0_bb_b0 = { 880ff38577aSYuval Mintz 0, 3, 0x16000c8, 0x16000d4, 0x16000d0, 0x16000cc}; 881ff38577aSYuval Mintz 882ff38577aSYuval Mintz static struct attn_hw_reg psem_prty1_bb_b0 = { 883ff38577aSYuval Mintz 1, 6, 0x1600200, 0x160020c, 0x1600208, 0x1600204}; 884ff38577aSYuval Mintz 885ff38577aSYuval Mintz static struct attn_hw_reg psem_fast_memory_vfc_config_prty1_bb_b0 = { 886ff38577aSYuval Mintz 2, 6, 0x164a200, 0x164a20c, 0x164a208, 0x164a204}; 887ff38577aSYuval Mintz 888ff38577aSYuval Mintz static struct attn_hw_reg *psem_prty_bb_b0_regs[3] = { 889ff38577aSYuval Mintz &psem_prty0_bb_b0, &psem_prty1_bb_b0, 890ff38577aSYuval Mintz &psem_fast_memory_vfc_config_prty1_bb_b0}; 891ff38577aSYuval Mintz 892ff38577aSYuval Mintz static struct attn_hw_reg rss_int0_bb_b0 = { 893ff38577aSYuval Mintz 0, 12, 0x238980, 0x23898c, 0x238988, 0x238984}; 894ff38577aSYuval Mintz 895ff38577aSYuval Mintz static struct attn_hw_reg *rss_int_bb_b0_regs[1] = { 896ff38577aSYuval Mintz &rss_int0_bb_b0}; 897ff38577aSYuval Mintz 898ff38577aSYuval Mintz static struct attn_hw_reg rss_prty1_bb_b0 = { 899ff38577aSYuval Mintz 0, 4, 0x238a00, 0x238a0c, 0x238a08, 0x238a04}; 900ff38577aSYuval Mintz 901ff38577aSYuval Mintz static struct attn_hw_reg *rss_prty_bb_b0_regs[1] = { 902ff38577aSYuval Mintz &rss_prty1_bb_b0}; 903ff38577aSYuval Mintz 904ff38577aSYuval Mintz static struct attn_hw_reg tmld_int0_bb_b0 = { 905ff38577aSYuval Mintz 0, 6, 0x4d0180, 0x4d018c, 0x4d0188, 0x4d0184}; 906ff38577aSYuval Mintz 907ff38577aSYuval Mintz static struct attn_hw_reg *tmld_int_bb_b0_regs[1] = { 908ff38577aSYuval Mintz &tmld_int0_bb_b0}; 909ff38577aSYuval Mintz 910ff38577aSYuval Mintz static struct attn_hw_reg tmld_prty1_bb_b0 = { 911ff38577aSYuval Mintz 0, 8, 0x4d0200, 0x4d020c, 0x4d0208, 0x4d0204}; 912ff38577aSYuval Mintz 913ff38577aSYuval Mintz static struct attn_hw_reg *tmld_prty_bb_b0_regs[1] = { 914ff38577aSYuval Mintz &tmld_prty1_bb_b0}; 915ff38577aSYuval Mintz 916ff38577aSYuval Mintz static struct attn_hw_reg muld_int0_bb_b0 = { 917ff38577aSYuval Mintz 0, 6, 0x4e0180, 0x4e018c, 0x4e0188, 0x4e0184}; 918ff38577aSYuval Mintz 919ff38577aSYuval Mintz static struct attn_hw_reg *muld_int_bb_b0_regs[1] = { 920ff38577aSYuval Mintz &muld_int0_bb_b0}; 921ff38577aSYuval Mintz 922ff38577aSYuval Mintz static struct attn_hw_reg muld_prty1_bb_b0 = { 923ff38577aSYuval Mintz 0, 10, 0x4e0200, 0x4e020c, 0x4e0208, 0x4e0204}; 924ff38577aSYuval Mintz 925ff38577aSYuval Mintz static struct attn_hw_reg *muld_prty_bb_b0_regs[1] = { 926ff38577aSYuval Mintz &muld_prty1_bb_b0}; 927ff38577aSYuval Mintz 928ff38577aSYuval Mintz static struct attn_hw_reg yuld_int0_bb_b0 = { 929ff38577aSYuval Mintz 0, 6, 0x4c8180, 0x4c818c, 0x4c8188, 0x4c8184}; 930ff38577aSYuval Mintz 931ff38577aSYuval Mintz static struct attn_hw_reg *yuld_int_bb_b0_regs[1] = { 932ff38577aSYuval Mintz &yuld_int0_bb_b0}; 933ff38577aSYuval Mintz 934ff38577aSYuval Mintz static struct attn_hw_reg yuld_prty1_bb_b0 = { 935ff38577aSYuval Mintz 0, 6, 0x4c8200, 0x4c820c, 0x4c8208, 0x4c8204}; 936ff38577aSYuval Mintz 937ff38577aSYuval Mintz static struct attn_hw_reg *yuld_prty_bb_b0_regs[1] = { 938ff38577aSYuval Mintz &yuld_prty1_bb_b0}; 939ff38577aSYuval Mintz 940ff38577aSYuval Mintz static struct attn_hw_reg xyld_int0_bb_b0 = { 941ff38577aSYuval Mintz 0, 6, 0x4c0180, 0x4c018c, 0x4c0188, 0x4c0184}; 942ff38577aSYuval Mintz 943ff38577aSYuval Mintz static struct attn_hw_reg *xyld_int_bb_b0_regs[1] = { 944ff38577aSYuval Mintz &xyld_int0_bb_b0}; 945ff38577aSYuval Mintz 946ff38577aSYuval Mintz static struct attn_hw_reg xyld_prty1_bb_b0 = { 947ff38577aSYuval Mintz 0, 9, 0x4c0200, 0x4c020c, 0x4c0208, 0x4c0204}; 948ff38577aSYuval Mintz 949ff38577aSYuval Mintz static struct attn_hw_reg *xyld_prty_bb_b0_regs[1] = { 950ff38577aSYuval Mintz &xyld_prty1_bb_b0}; 951ff38577aSYuval Mintz 952ff38577aSYuval Mintz static struct attn_hw_reg prm_int0_bb_b0 = { 953ff38577aSYuval Mintz 0, 11, 0x230040, 0x23004c, 0x230048, 0x230044}; 954ff38577aSYuval Mintz 955ff38577aSYuval Mintz static struct attn_hw_reg *prm_int_bb_b0_regs[1] = { 956ff38577aSYuval Mintz &prm_int0_bb_b0}; 957ff38577aSYuval Mintz 958ff38577aSYuval Mintz static struct attn_hw_reg prm_prty0_bb_b0 = { 959ff38577aSYuval Mintz 0, 1, 0x230050, 0x23005c, 0x230058, 0x230054}; 960ff38577aSYuval Mintz 961ff38577aSYuval Mintz static struct attn_hw_reg prm_prty1_bb_b0 = { 962ff38577aSYuval Mintz 1, 24, 0x230200, 0x23020c, 0x230208, 0x230204}; 963ff38577aSYuval Mintz 964ff38577aSYuval Mintz static struct attn_hw_reg *prm_prty_bb_b0_regs[2] = { 965ff38577aSYuval Mintz &prm_prty0_bb_b0, &prm_prty1_bb_b0}; 966ff38577aSYuval Mintz 967ff38577aSYuval Mintz static struct attn_hw_reg pbf_pb1_int0_bb_b0 = { 968ff38577aSYuval Mintz 0, 9, 0xda0040, 0xda004c, 0xda0048, 0xda0044}; 969ff38577aSYuval Mintz 970ff38577aSYuval Mintz static struct attn_hw_reg *pbf_pb1_int_bb_b0_regs[1] = { 971ff38577aSYuval Mintz &pbf_pb1_int0_bb_b0}; 972ff38577aSYuval Mintz 973ff38577aSYuval Mintz static struct attn_hw_reg pbf_pb1_prty0_bb_b0 = { 974ff38577aSYuval Mintz 0, 1, 0xda0050, 0xda005c, 0xda0058, 0xda0054}; 975ff38577aSYuval Mintz 976ff38577aSYuval Mintz static struct attn_hw_reg *pbf_pb1_prty_bb_b0_regs[1] = { 977ff38577aSYuval Mintz &pbf_pb1_prty0_bb_b0}; 978ff38577aSYuval Mintz 979ff38577aSYuval Mintz static struct attn_hw_reg pbf_pb2_int0_bb_b0 = { 980ff38577aSYuval Mintz 0, 9, 0xda4040, 0xda404c, 0xda4048, 0xda4044}; 981ff38577aSYuval Mintz 982ff38577aSYuval Mintz static struct attn_hw_reg *pbf_pb2_int_bb_b0_regs[1] = { 983ff38577aSYuval Mintz &pbf_pb2_int0_bb_b0}; 984ff38577aSYuval Mintz 985ff38577aSYuval Mintz static struct attn_hw_reg pbf_pb2_prty0_bb_b0 = { 986ff38577aSYuval Mintz 0, 1, 0xda4050, 0xda405c, 0xda4058, 0xda4054}; 987ff38577aSYuval Mintz 988ff38577aSYuval Mintz static struct attn_hw_reg *pbf_pb2_prty_bb_b0_regs[1] = { 989ff38577aSYuval Mintz &pbf_pb2_prty0_bb_b0}; 990ff38577aSYuval Mintz 991ff38577aSYuval Mintz static struct attn_hw_reg rpb_int0_bb_b0 = { 992ff38577aSYuval Mintz 0, 9, 0x23c040, 0x23c04c, 0x23c048, 0x23c044}; 993ff38577aSYuval Mintz 994ff38577aSYuval Mintz static struct attn_hw_reg *rpb_int_bb_b0_regs[1] = { 995ff38577aSYuval Mintz &rpb_int0_bb_b0}; 996ff38577aSYuval Mintz 997ff38577aSYuval Mintz static struct attn_hw_reg rpb_prty0_bb_b0 = { 998ff38577aSYuval Mintz 0, 1, 0x23c050, 0x23c05c, 0x23c058, 0x23c054}; 999ff38577aSYuval Mintz 1000ff38577aSYuval Mintz static struct attn_hw_reg *rpb_prty_bb_b0_regs[1] = { 1001ff38577aSYuval Mintz &rpb_prty0_bb_b0}; 1002ff38577aSYuval Mintz 1003ff38577aSYuval Mintz static struct attn_hw_reg btb_int0_bb_b0 = { 1004ff38577aSYuval Mintz 0, 16, 0xdb00c0, 0xdb00cc, 0xdb00c8, 0xdb00c4}; 1005ff38577aSYuval Mintz 1006ff38577aSYuval Mintz static struct attn_hw_reg btb_int1_bb_b0 = { 1007ff38577aSYuval Mintz 1, 16, 0xdb00d8, 0xdb00e4, 0xdb00e0, 0xdb00dc}; 1008ff38577aSYuval Mintz 1009ff38577aSYuval Mintz static struct attn_hw_reg btb_int2_bb_b0 = { 1010ff38577aSYuval Mintz 2, 4, 0xdb00f0, 0xdb00fc, 0xdb00f8, 0xdb00f4}; 1011ff38577aSYuval Mintz 1012ff38577aSYuval Mintz static struct attn_hw_reg btb_int3_bb_b0 = { 1013ff38577aSYuval Mintz 3, 32, 0xdb0108, 0xdb0114, 0xdb0110, 0xdb010c}; 1014ff38577aSYuval Mintz 1015ff38577aSYuval Mintz static struct attn_hw_reg btb_int4_bb_b0 = { 1016ff38577aSYuval Mintz 4, 23, 0xdb0120, 0xdb012c, 0xdb0128, 0xdb0124}; 1017ff38577aSYuval Mintz 1018ff38577aSYuval Mintz static struct attn_hw_reg btb_int5_bb_b0 = { 1019ff38577aSYuval Mintz 5, 32, 0xdb0138, 0xdb0144, 0xdb0140, 0xdb013c}; 1020ff38577aSYuval Mintz 1021ff38577aSYuval Mintz static struct attn_hw_reg btb_int6_bb_b0 = { 1022ff38577aSYuval Mintz 6, 1, 0xdb0150, 0xdb015c, 0xdb0158, 0xdb0154}; 1023ff38577aSYuval Mintz 1024ff38577aSYuval Mintz static struct attn_hw_reg btb_int8_bb_b0 = { 1025ff38577aSYuval Mintz 7, 1, 0xdb0184, 0xdb0190, 0xdb018c, 0xdb0188}; 1026ff38577aSYuval Mintz 1027ff38577aSYuval Mintz static struct attn_hw_reg btb_int9_bb_b0 = { 1028ff38577aSYuval Mintz 8, 1, 0xdb019c, 0xdb01a8, 0xdb01a4, 0xdb01a0}; 1029ff38577aSYuval Mintz 1030ff38577aSYuval Mintz static struct attn_hw_reg btb_int10_bb_b0 = { 1031ff38577aSYuval Mintz 9, 1, 0xdb01b4, 0xdb01c0, 0xdb01bc, 0xdb01b8}; 1032ff38577aSYuval Mintz 1033ff38577aSYuval Mintz static struct attn_hw_reg btb_int11_bb_b0 = { 1034ff38577aSYuval Mintz 10, 2, 0xdb01cc, 0xdb01d8, 0xdb01d4, 0xdb01d0}; 1035ff38577aSYuval Mintz 1036ff38577aSYuval Mintz static struct attn_hw_reg *btb_int_bb_b0_regs[11] = { 1037ff38577aSYuval Mintz &btb_int0_bb_b0, &btb_int1_bb_b0, &btb_int2_bb_b0, &btb_int3_bb_b0, 1038ff38577aSYuval Mintz &btb_int4_bb_b0, &btb_int5_bb_b0, &btb_int6_bb_b0, &btb_int8_bb_b0, 1039ff38577aSYuval Mintz &btb_int9_bb_b0, &btb_int10_bb_b0, &btb_int11_bb_b0}; 1040ff38577aSYuval Mintz 1041ff38577aSYuval Mintz static struct attn_hw_reg btb_prty0_bb_b0 = { 1042ff38577aSYuval Mintz 0, 5, 0xdb01dc, 0xdb01e8, 0xdb01e4, 0xdb01e0}; 1043ff38577aSYuval Mintz 1044ff38577aSYuval Mintz static struct attn_hw_reg btb_prty1_bb_b0 = { 1045ff38577aSYuval Mintz 1, 23, 0xdb0400, 0xdb040c, 0xdb0408, 0xdb0404}; 1046ff38577aSYuval Mintz 1047ff38577aSYuval Mintz static struct attn_hw_reg *btb_prty_bb_b0_regs[2] = { 1048ff38577aSYuval Mintz &btb_prty0_bb_b0, &btb_prty1_bb_b0}; 1049ff38577aSYuval Mintz 1050ff38577aSYuval Mintz static struct attn_hw_reg pbf_int0_bb_b0 = { 1051ff38577aSYuval Mintz 0, 1, 0xd80180, 0xd8018c, 0xd80188, 0xd80184}; 1052ff38577aSYuval Mintz 1053ff38577aSYuval Mintz static struct attn_hw_reg *pbf_int_bb_b0_regs[1] = { 1054ff38577aSYuval Mintz &pbf_int0_bb_b0}; 1055ff38577aSYuval Mintz 1056ff38577aSYuval Mintz static struct attn_hw_reg pbf_prty0_bb_b0 = { 1057ff38577aSYuval Mintz 0, 1, 0xd80190, 0xd8019c, 0xd80198, 0xd80194}; 1058ff38577aSYuval Mintz 1059ff38577aSYuval Mintz static struct attn_hw_reg pbf_prty1_bb_b0 = { 1060ff38577aSYuval Mintz 1, 31, 0xd80200, 0xd8020c, 0xd80208, 0xd80204}; 1061ff38577aSYuval Mintz 1062ff38577aSYuval Mintz static struct attn_hw_reg pbf_prty2_bb_b0 = { 1063ff38577aSYuval Mintz 2, 27, 0xd80210, 0xd8021c, 0xd80218, 0xd80214}; 1064ff38577aSYuval Mintz 1065ff38577aSYuval Mintz static struct attn_hw_reg *pbf_prty_bb_b0_regs[3] = { 1066ff38577aSYuval Mintz &pbf_prty0_bb_b0, &pbf_prty1_bb_b0, &pbf_prty2_bb_b0}; 1067ff38577aSYuval Mintz 1068ff38577aSYuval Mintz static struct attn_hw_reg rdif_int0_bb_b0 = { 1069ff38577aSYuval Mintz 0, 8, 0x300180, 0x30018c, 0x300188, 0x300184}; 1070ff38577aSYuval Mintz 1071ff38577aSYuval Mintz static struct attn_hw_reg *rdif_int_bb_b0_regs[1] = { 1072ff38577aSYuval Mintz &rdif_int0_bb_b0}; 1073ff38577aSYuval Mintz 1074ff38577aSYuval Mintz static struct attn_hw_reg rdif_prty0_bb_b0 = { 1075ff38577aSYuval Mintz 0, 1, 0x300190, 0x30019c, 0x300198, 0x300194}; 1076ff38577aSYuval Mintz 1077ff38577aSYuval Mintz static struct attn_hw_reg *rdif_prty_bb_b0_regs[1] = { 1078ff38577aSYuval Mintz &rdif_prty0_bb_b0}; 1079ff38577aSYuval Mintz 1080ff38577aSYuval Mintz static struct attn_hw_reg tdif_int0_bb_b0 = { 1081ff38577aSYuval Mintz 0, 8, 0x310180, 0x31018c, 0x310188, 0x310184}; 1082ff38577aSYuval Mintz 1083ff38577aSYuval Mintz static struct attn_hw_reg *tdif_int_bb_b0_regs[1] = { 1084ff38577aSYuval Mintz &tdif_int0_bb_b0}; 1085ff38577aSYuval Mintz 1086ff38577aSYuval Mintz static struct attn_hw_reg tdif_prty0_bb_b0 = { 1087ff38577aSYuval Mintz 0, 1, 0x310190, 0x31019c, 0x310198, 0x310194}; 1088ff38577aSYuval Mintz 1089ff38577aSYuval Mintz static struct attn_hw_reg tdif_prty1_bb_b0 = { 1090ff38577aSYuval Mintz 1, 11, 0x310200, 0x31020c, 0x310208, 0x310204}; 1091ff38577aSYuval Mintz 1092ff38577aSYuval Mintz static struct attn_hw_reg *tdif_prty_bb_b0_regs[2] = { 1093ff38577aSYuval Mintz &tdif_prty0_bb_b0, &tdif_prty1_bb_b0}; 1094ff38577aSYuval Mintz 1095ff38577aSYuval Mintz static struct attn_hw_reg cdu_int0_bb_b0 = { 1096ff38577aSYuval Mintz 0, 8, 0x5801c0, 0x5801c4, 0x5801c8, 0x5801cc}; 1097ff38577aSYuval Mintz 1098ff38577aSYuval Mintz static struct attn_hw_reg *cdu_int_bb_b0_regs[1] = { 1099ff38577aSYuval Mintz &cdu_int0_bb_b0}; 1100ff38577aSYuval Mintz 1101ff38577aSYuval Mintz static struct attn_hw_reg cdu_prty1_bb_b0 = { 1102ff38577aSYuval Mintz 0, 5, 0x580200, 0x58020c, 0x580208, 0x580204}; 1103ff38577aSYuval Mintz 1104ff38577aSYuval Mintz static struct attn_hw_reg *cdu_prty_bb_b0_regs[1] = { 1105ff38577aSYuval Mintz &cdu_prty1_bb_b0}; 1106ff38577aSYuval Mintz 1107ff38577aSYuval Mintz static struct attn_hw_reg ccfc_int0_bb_b0 = { 1108ff38577aSYuval Mintz 0, 2, 0x2e0180, 0x2e018c, 0x2e0188, 0x2e0184}; 1109ff38577aSYuval Mintz 1110ff38577aSYuval Mintz static struct attn_hw_reg *ccfc_int_bb_b0_regs[1] = { 1111ff38577aSYuval Mintz &ccfc_int0_bb_b0}; 1112ff38577aSYuval Mintz 1113ff38577aSYuval Mintz static struct attn_hw_reg ccfc_prty1_bb_b0 = { 1114ff38577aSYuval Mintz 0, 2, 0x2e0200, 0x2e020c, 0x2e0208, 0x2e0204}; 1115ff38577aSYuval Mintz 1116ff38577aSYuval Mintz static struct attn_hw_reg ccfc_prty0_bb_b0 = { 1117ff38577aSYuval Mintz 1, 6, 0x2e05e4, 0x2e05f0, 0x2e05ec, 0x2e05e8}; 1118ff38577aSYuval Mintz 1119ff38577aSYuval Mintz static struct attn_hw_reg *ccfc_prty_bb_b0_regs[2] = { 1120ff38577aSYuval Mintz &ccfc_prty1_bb_b0, &ccfc_prty0_bb_b0}; 1121ff38577aSYuval Mintz 1122ff38577aSYuval Mintz static struct attn_hw_reg tcfc_int0_bb_b0 = { 1123ff38577aSYuval Mintz 0, 2, 0x2d0180, 0x2d018c, 0x2d0188, 0x2d0184}; 1124ff38577aSYuval Mintz 1125ff38577aSYuval Mintz static struct attn_hw_reg *tcfc_int_bb_b0_regs[1] = { 1126ff38577aSYuval Mintz &tcfc_int0_bb_b0}; 1127ff38577aSYuval Mintz 1128ff38577aSYuval Mintz static struct attn_hw_reg tcfc_prty1_bb_b0 = { 1129ff38577aSYuval Mintz 0, 2, 0x2d0200, 0x2d020c, 0x2d0208, 0x2d0204}; 1130ff38577aSYuval Mintz 1131ff38577aSYuval Mintz static struct attn_hw_reg tcfc_prty0_bb_b0 = { 1132ff38577aSYuval Mintz 1, 6, 0x2d05e4, 0x2d05f0, 0x2d05ec, 0x2d05e8}; 1133ff38577aSYuval Mintz 1134ff38577aSYuval Mintz static struct attn_hw_reg *tcfc_prty_bb_b0_regs[2] = { 1135ff38577aSYuval Mintz &tcfc_prty1_bb_b0, &tcfc_prty0_bb_b0}; 1136ff38577aSYuval Mintz 1137ff38577aSYuval Mintz static struct attn_hw_reg igu_int0_bb_b0 = { 1138ff38577aSYuval Mintz 0, 11, 0x180180, 0x18018c, 0x180188, 0x180184}; 1139ff38577aSYuval Mintz 1140ff38577aSYuval Mintz static struct attn_hw_reg *igu_int_bb_b0_regs[1] = { 1141ff38577aSYuval Mintz &igu_int0_bb_b0}; 1142ff38577aSYuval Mintz 1143ff38577aSYuval Mintz static struct attn_hw_reg igu_prty0_bb_b0 = { 1144ff38577aSYuval Mintz 0, 1, 0x180190, 0x18019c, 0x180198, 0x180194}; 1145ff38577aSYuval Mintz 1146ff38577aSYuval Mintz static struct attn_hw_reg igu_prty1_bb_b0 = { 1147ff38577aSYuval Mintz 1, 31, 0x180200, 0x18020c, 0x180208, 0x180204}; 1148ff38577aSYuval Mintz 1149ff38577aSYuval Mintz static struct attn_hw_reg igu_prty2_bb_b0 = { 1150ff38577aSYuval Mintz 2, 1, 0x180210, 0x18021c, 0x180218, 0x180214}; 1151ff38577aSYuval Mintz 1152ff38577aSYuval Mintz static struct attn_hw_reg *igu_prty_bb_b0_regs[3] = { 1153ff38577aSYuval Mintz &igu_prty0_bb_b0, &igu_prty1_bb_b0, &igu_prty2_bb_b0}; 1154ff38577aSYuval Mintz 1155ff38577aSYuval Mintz static struct attn_hw_reg cau_int0_bb_b0 = { 1156ff38577aSYuval Mintz 0, 11, 0x1c00d4, 0x1c00d8, 0x1c00dc, 0x1c00e0}; 1157ff38577aSYuval Mintz 1158ff38577aSYuval Mintz static struct attn_hw_reg *cau_int_bb_b0_regs[1] = { 1159ff38577aSYuval Mintz &cau_int0_bb_b0}; 1160ff38577aSYuval Mintz 1161ff38577aSYuval Mintz static struct attn_hw_reg cau_prty1_bb_b0 = { 1162ff38577aSYuval Mintz 0, 13, 0x1c0200, 0x1c020c, 0x1c0208, 0x1c0204}; 1163ff38577aSYuval Mintz 1164ff38577aSYuval Mintz static struct attn_hw_reg *cau_prty_bb_b0_regs[1] = { 1165ff38577aSYuval Mintz &cau_prty1_bb_b0}; 1166ff38577aSYuval Mintz 1167ff38577aSYuval Mintz static struct attn_hw_reg dbg_int0_bb_b0 = { 1168ff38577aSYuval Mintz 0, 1, 0x10180, 0x1018c, 0x10188, 0x10184}; 1169ff38577aSYuval Mintz 1170ff38577aSYuval Mintz static struct attn_hw_reg *dbg_int_bb_b0_regs[1] = { 1171ff38577aSYuval Mintz &dbg_int0_bb_b0}; 1172ff38577aSYuval Mintz 1173ff38577aSYuval Mintz static struct attn_hw_reg dbg_prty1_bb_b0 = { 1174ff38577aSYuval Mintz 0, 1, 0x10200, 0x1020c, 0x10208, 0x10204}; 1175ff38577aSYuval Mintz 1176ff38577aSYuval Mintz static struct attn_hw_reg *dbg_prty_bb_b0_regs[1] = { 1177ff38577aSYuval Mintz &dbg_prty1_bb_b0}; 1178ff38577aSYuval Mintz 1179ff38577aSYuval Mintz static struct attn_hw_reg nig_int0_bb_b0 = { 1180ff38577aSYuval Mintz 0, 12, 0x500040, 0x50004c, 0x500048, 0x500044}; 1181ff38577aSYuval Mintz 1182ff38577aSYuval Mintz static struct attn_hw_reg nig_int1_bb_b0 = { 1183ff38577aSYuval Mintz 1, 32, 0x500050, 0x50005c, 0x500058, 0x500054}; 1184ff38577aSYuval Mintz 1185ff38577aSYuval Mintz static struct attn_hw_reg nig_int2_bb_b0 = { 1186ff38577aSYuval Mintz 2, 20, 0x500060, 0x50006c, 0x500068, 0x500064}; 1187ff38577aSYuval Mintz 1188ff38577aSYuval Mintz static struct attn_hw_reg nig_int3_bb_b0 = { 1189ff38577aSYuval Mintz 3, 18, 0x500070, 0x50007c, 0x500078, 0x500074}; 1190ff38577aSYuval Mintz 1191ff38577aSYuval Mintz static struct attn_hw_reg nig_int4_bb_b0 = { 1192ff38577aSYuval Mintz 4, 20, 0x500080, 0x50008c, 0x500088, 0x500084}; 1193ff38577aSYuval Mintz 1194ff38577aSYuval Mintz static struct attn_hw_reg nig_int5_bb_b0 = { 1195ff38577aSYuval Mintz 5, 18, 0x500090, 0x50009c, 0x500098, 0x500094}; 1196ff38577aSYuval Mintz 1197ff38577aSYuval Mintz static struct attn_hw_reg *nig_int_bb_b0_regs[6] = { 1198ff38577aSYuval Mintz &nig_int0_bb_b0, &nig_int1_bb_b0, &nig_int2_bb_b0, &nig_int3_bb_b0, 1199ff38577aSYuval Mintz &nig_int4_bb_b0, &nig_int5_bb_b0}; 1200ff38577aSYuval Mintz 1201ff38577aSYuval Mintz static struct attn_hw_reg nig_prty0_bb_b0 = { 1202ff38577aSYuval Mintz 0, 1, 0x5000a0, 0x5000ac, 0x5000a8, 0x5000a4}; 1203ff38577aSYuval Mintz 1204ff38577aSYuval Mintz static struct attn_hw_reg nig_prty1_bb_b0 = { 1205ff38577aSYuval Mintz 1, 31, 0x500200, 0x50020c, 0x500208, 0x500204}; 1206ff38577aSYuval Mintz 1207ff38577aSYuval Mintz static struct attn_hw_reg nig_prty2_bb_b0 = { 1208ff38577aSYuval Mintz 2, 31, 0x500210, 0x50021c, 0x500218, 0x500214}; 1209ff38577aSYuval Mintz 1210ff38577aSYuval Mintz static struct attn_hw_reg nig_prty3_bb_b0 = { 1211ff38577aSYuval Mintz 3, 31, 0x500220, 0x50022c, 0x500228, 0x500224}; 1212ff38577aSYuval Mintz 1213ff38577aSYuval Mintz static struct attn_hw_reg nig_prty4_bb_b0 = { 1214ff38577aSYuval Mintz 4, 17, 0x500230, 0x50023c, 0x500238, 0x500234}; 1215ff38577aSYuval Mintz 1216ff38577aSYuval Mintz static struct attn_hw_reg *nig_prty_bb_b0_regs[5] = { 1217ff38577aSYuval Mintz &nig_prty0_bb_b0, &nig_prty1_bb_b0, &nig_prty2_bb_b0, 1218ff38577aSYuval Mintz &nig_prty3_bb_b0, &nig_prty4_bb_b0}; 1219ff38577aSYuval Mintz 1220ff38577aSYuval Mintz static struct attn_hw_reg ipc_int0_bb_b0 = { 1221ff38577aSYuval Mintz 0, 13, 0x2050c, 0x20518, 0x20514, 0x20510}; 1222ff38577aSYuval Mintz 1223ff38577aSYuval Mintz static struct attn_hw_reg *ipc_int_bb_b0_regs[1] = { 1224ff38577aSYuval Mintz &ipc_int0_bb_b0}; 1225ff38577aSYuval Mintz 1226ff38577aSYuval Mintz static struct attn_hw_reg ipc_prty0_bb_b0 = { 1227ff38577aSYuval Mintz 0, 1, 0x2051c, 0x20528, 0x20524, 0x20520}; 1228ff38577aSYuval Mintz 1229ff38577aSYuval Mintz static struct attn_hw_reg *ipc_prty_bb_b0_regs[1] = { 1230ff38577aSYuval Mintz &ipc_prty0_bb_b0}; 1231ff38577aSYuval Mintz 1232ff38577aSYuval Mintz static struct attn_hw_block attn_blocks[] = { 1233ff38577aSYuval Mintz {"grc", {{1, 1, grc_int_bb_b0_regs, grc_prty_bb_b0_regs} } }, 1234ff38577aSYuval Mintz {"miscs", {{2, 1, miscs_int_bb_b0_regs, miscs_prty_bb_b0_regs} } }, 1235ff38577aSYuval Mintz {"misc", {{1, 0, misc_int_bb_b0_regs, NULL} } }, 1236ff38577aSYuval Mintz {"dbu", {{0, 0, NULL, NULL} } }, 1237ff38577aSYuval Mintz {"pglue_b", {{1, 2, pglue_b_int_bb_b0_regs, 1238ff38577aSYuval Mintz pglue_b_prty_bb_b0_regs} } }, 1239ff38577aSYuval Mintz {"cnig", {{1, 1, cnig_int_bb_b0_regs, cnig_prty_bb_b0_regs} } }, 1240ff38577aSYuval Mintz {"cpmu", {{1, 0, cpmu_int_bb_b0_regs, NULL} } }, 1241ff38577aSYuval Mintz {"ncsi", {{1, 1, ncsi_int_bb_b0_regs, ncsi_prty_bb_b0_regs} } }, 1242ff38577aSYuval Mintz {"opte", {{0, 2, NULL, opte_prty_bb_b0_regs} } }, 1243ff38577aSYuval Mintz {"bmb", {{12, 3, bmb_int_bb_b0_regs, bmb_prty_bb_b0_regs} } }, 1244ff38577aSYuval Mintz {"pcie", {{0, 1, NULL, pcie_prty_bb_b0_regs} } }, 1245ff38577aSYuval Mintz {"mcp", {{0, 0, NULL, NULL} } }, 1246ff38577aSYuval Mintz {"mcp2", {{0, 2, NULL, mcp2_prty_bb_b0_regs} } }, 1247ff38577aSYuval Mintz {"pswhst", {{1, 2, pswhst_int_bb_b0_regs, pswhst_prty_bb_b0_regs} } }, 1248ff38577aSYuval Mintz {"pswhst2", {{1, 1, pswhst2_int_bb_b0_regs, 1249ff38577aSYuval Mintz pswhst2_prty_bb_b0_regs} } }, 1250ff38577aSYuval Mintz {"pswrd", {{1, 1, pswrd_int_bb_b0_regs, pswrd_prty_bb_b0_regs} } }, 1251ff38577aSYuval Mintz {"pswrd2", {{1, 3, pswrd2_int_bb_b0_regs, pswrd2_prty_bb_b0_regs} } }, 1252ff38577aSYuval Mintz {"pswwr", {{1, 1, pswwr_int_bb_b0_regs, pswwr_prty_bb_b0_regs} } }, 1253ff38577aSYuval Mintz {"pswwr2", {{1, 5, pswwr2_int_bb_b0_regs, pswwr2_prty_bb_b0_regs} } }, 1254ff38577aSYuval Mintz {"pswrq", {{1, 1, pswrq_int_bb_b0_regs, pswrq_prty_bb_b0_regs} } }, 1255ff38577aSYuval Mintz {"pswrq2", {{1, 1, pswrq2_int_bb_b0_regs, pswrq2_prty_bb_b0_regs} } }, 1256ff38577aSYuval Mintz {"pglcs", {{1, 0, pglcs_int_bb_b0_regs, NULL} } }, 1257ff38577aSYuval Mintz {"dmae", {{1, 1, dmae_int_bb_b0_regs, dmae_prty_bb_b0_regs} } }, 1258ff38577aSYuval Mintz {"ptu", {{1, 1, ptu_int_bb_b0_regs, ptu_prty_bb_b0_regs} } }, 1259ff38577aSYuval Mintz {"tcm", {{3, 2, tcm_int_bb_b0_regs, tcm_prty_bb_b0_regs} } }, 1260ff38577aSYuval Mintz {"mcm", {{3, 2, mcm_int_bb_b0_regs, mcm_prty_bb_b0_regs} } }, 1261ff38577aSYuval Mintz {"ucm", {{3, 2, ucm_int_bb_b0_regs, ucm_prty_bb_b0_regs} } }, 1262ff38577aSYuval Mintz {"xcm", {{3, 2, xcm_int_bb_b0_regs, xcm_prty_bb_b0_regs} } }, 1263ff38577aSYuval Mintz {"ycm", {{3, 2, ycm_int_bb_b0_regs, ycm_prty_bb_b0_regs} } }, 1264ff38577aSYuval Mintz {"pcm", {{3, 1, pcm_int_bb_b0_regs, pcm_prty_bb_b0_regs} } }, 1265ff38577aSYuval Mintz {"qm", {{1, 4, qm_int_bb_b0_regs, qm_prty_bb_b0_regs} } }, 1266ff38577aSYuval Mintz {"tm", {{2, 1, tm_int_bb_b0_regs, tm_prty_bb_b0_regs} } }, 1267ff38577aSYuval Mintz {"dorq", {{1, 2, dorq_int_bb_b0_regs, dorq_prty_bb_b0_regs} } }, 1268ff38577aSYuval Mintz {"brb", {{12, 3, brb_int_bb_b0_regs, brb_prty_bb_b0_regs} } }, 1269ff38577aSYuval Mintz {"src", {{1, 0, src_int_bb_b0_regs, NULL} } }, 1270ff38577aSYuval Mintz {"prs", {{1, 3, prs_int_bb_b0_regs, prs_prty_bb_b0_regs} } }, 1271ff38577aSYuval Mintz {"tsdm", {{1, 1, tsdm_int_bb_b0_regs, tsdm_prty_bb_b0_regs} } }, 1272ff38577aSYuval Mintz {"msdm", {{1, 1, msdm_int_bb_b0_regs, msdm_prty_bb_b0_regs} } }, 1273ff38577aSYuval Mintz {"usdm", {{1, 1, usdm_int_bb_b0_regs, usdm_prty_bb_b0_regs} } }, 1274ff38577aSYuval Mintz {"xsdm", {{1, 1, xsdm_int_bb_b0_regs, xsdm_prty_bb_b0_regs} } }, 1275ff38577aSYuval Mintz {"ysdm", {{1, 1, ysdm_int_bb_b0_regs, ysdm_prty_bb_b0_regs} } }, 1276ff38577aSYuval Mintz {"psdm", {{1, 1, psdm_int_bb_b0_regs, psdm_prty_bb_b0_regs} } }, 1277ff38577aSYuval Mintz {"tsem", {{3, 3, tsem_int_bb_b0_regs, tsem_prty_bb_b0_regs} } }, 1278ff38577aSYuval Mintz {"msem", {{3, 2, msem_int_bb_b0_regs, msem_prty_bb_b0_regs} } }, 1279ff38577aSYuval Mintz {"usem", {{3, 2, usem_int_bb_b0_regs, usem_prty_bb_b0_regs} } }, 1280ff38577aSYuval Mintz {"xsem", {{3, 2, xsem_int_bb_b0_regs, xsem_prty_bb_b0_regs} } }, 1281ff38577aSYuval Mintz {"ysem", {{3, 2, ysem_int_bb_b0_regs, ysem_prty_bb_b0_regs} } }, 1282ff38577aSYuval Mintz {"psem", {{3, 3, psem_int_bb_b0_regs, psem_prty_bb_b0_regs} } }, 1283ff38577aSYuval Mintz {"rss", {{1, 1, rss_int_bb_b0_regs, rss_prty_bb_b0_regs} } }, 1284ff38577aSYuval Mintz {"tmld", {{1, 1, tmld_int_bb_b0_regs, tmld_prty_bb_b0_regs} } }, 1285ff38577aSYuval Mintz {"muld", {{1, 1, muld_int_bb_b0_regs, muld_prty_bb_b0_regs} } }, 1286ff38577aSYuval Mintz {"yuld", {{1, 1, yuld_int_bb_b0_regs, yuld_prty_bb_b0_regs} } }, 1287ff38577aSYuval Mintz {"xyld", {{1, 1, xyld_int_bb_b0_regs, xyld_prty_bb_b0_regs} } }, 1288ff38577aSYuval Mintz {"prm", {{1, 2, prm_int_bb_b0_regs, prm_prty_bb_b0_regs} } }, 1289ff38577aSYuval Mintz {"pbf_pb1", {{1, 1, pbf_pb1_int_bb_b0_regs, 1290ff38577aSYuval Mintz pbf_pb1_prty_bb_b0_regs} } }, 1291ff38577aSYuval Mintz {"pbf_pb2", {{1, 1, pbf_pb2_int_bb_b0_regs, 1292ff38577aSYuval Mintz pbf_pb2_prty_bb_b0_regs} } }, 1293ff38577aSYuval Mintz {"rpb", { {1, 1, rpb_int_bb_b0_regs, rpb_prty_bb_b0_regs} } }, 1294ff38577aSYuval Mintz {"btb", { {11, 2, btb_int_bb_b0_regs, btb_prty_bb_b0_regs} } }, 1295ff38577aSYuval Mintz {"pbf", { {1, 3, pbf_int_bb_b0_regs, pbf_prty_bb_b0_regs} } }, 1296ff38577aSYuval Mintz {"rdif", { {1, 1, rdif_int_bb_b0_regs, rdif_prty_bb_b0_regs} } }, 1297ff38577aSYuval Mintz {"tdif", { {1, 2, tdif_int_bb_b0_regs, tdif_prty_bb_b0_regs} } }, 1298ff38577aSYuval Mintz {"cdu", { {1, 1, cdu_int_bb_b0_regs, cdu_prty_bb_b0_regs} } }, 1299ff38577aSYuval Mintz {"ccfc", { {1, 2, ccfc_int_bb_b0_regs, ccfc_prty_bb_b0_regs} } }, 1300ff38577aSYuval Mintz {"tcfc", { {1, 2, tcfc_int_bb_b0_regs, tcfc_prty_bb_b0_regs} } }, 1301ff38577aSYuval Mintz {"igu", { {1, 3, igu_int_bb_b0_regs, igu_prty_bb_b0_regs} } }, 1302ff38577aSYuval Mintz {"cau", { {1, 1, cau_int_bb_b0_regs, cau_prty_bb_b0_regs} } }, 1303ff38577aSYuval Mintz {"umac", { {0, 0, NULL, NULL} } }, 1304ff38577aSYuval Mintz {"xmac", { {0, 0, NULL, NULL} } }, 1305ff38577aSYuval Mintz {"dbg", { {1, 1, dbg_int_bb_b0_regs, dbg_prty_bb_b0_regs} } }, 1306ff38577aSYuval Mintz {"nig", { {6, 5, nig_int_bb_b0_regs, nig_prty_bb_b0_regs} } }, 1307ff38577aSYuval Mintz {"wol", { {0, 0, NULL, NULL} } }, 1308ff38577aSYuval Mintz {"bmbn", { {0, 0, NULL, NULL} } }, 1309ff38577aSYuval Mintz {"ipc", { {1, 1, ipc_int_bb_b0_regs, ipc_prty_bb_b0_regs} } }, 1310ff38577aSYuval Mintz {"nwm", { {0, 0, NULL, NULL} } }, 1311ff38577aSYuval Mintz {"nws", { {0, 0, NULL, NULL} } }, 1312ff38577aSYuval Mintz {"ms", { {0, 0, NULL, NULL} } }, 1313ff38577aSYuval Mintz {"phy_pcie", { {0, 0, NULL, NULL} } }, 1314ff38577aSYuval Mintz {"misc_aeu", { {0, 0, NULL, NULL} } }, 1315ff38577aSYuval Mintz {"bar0_map", { {0, 0, NULL, NULL} } },}; 1316ff38577aSYuval Mintz 1317b4149dc7SYuval Mintz /* Specific HW attention callbacks */ 1318b4149dc7SYuval Mintz static int qed_mcp_attn_cb(struct qed_hwfn *p_hwfn) 1319b4149dc7SYuval Mintz { 1320b4149dc7SYuval Mintz u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE); 1321b4149dc7SYuval Mintz 1322b4149dc7SYuval Mintz /* This might occur on certain instances; Log it once then mask it */ 1323b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, "MCP_REG_CPU_STATE: %08x - Masking...\n", 1324b4149dc7SYuval Mintz tmp); 1325b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, 1326b4149dc7SYuval Mintz 0xffffffff); 1327b4149dc7SYuval Mintz 1328b4149dc7SYuval Mintz return 0; 1329b4149dc7SYuval Mintz } 1330b4149dc7SYuval Mintz 1331b4149dc7SYuval Mintz #define QED_PSWHST_ATTENTION_INCORRECT_ACCESS (0x1) 1332b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_WR_MASK (0x1) 1333b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_WR_SHIFT (0) 1334b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_CLIENT_MASK (0xf) 1335b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT (1) 1336b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK (0x1) 1337b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT (5) 1338b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_ID_MASK (0xff) 1339b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT (6) 1340b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_PF_ID_MASK (0xf) 1341b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT (14) 1342b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK (0xff) 1343b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT (18) 1344b4149dc7SYuval Mintz static int qed_pswhst_attn_cb(struct qed_hwfn *p_hwfn) 1345b4149dc7SYuval Mintz { 1346b4149dc7SYuval Mintz u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1347b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_VALID); 1348b4149dc7SYuval Mintz 1349b4149dc7SYuval Mintz if (tmp & QED_PSWHST_ATTENTION_INCORRECT_ACCESS) { 1350b4149dc7SYuval Mintz u32 addr, data, length; 1351b4149dc7SYuval Mintz 1352b4149dc7SYuval Mintz addr = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1353b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_ADDRESS); 1354b4149dc7SYuval Mintz data = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1355b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_DATA); 1356b4149dc7SYuval Mintz length = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1357b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_LENGTH); 1358b4149dc7SYuval Mintz 1359b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, 1360b4149dc7SYuval Mintz "Incorrect access to %08x of length %08x - PF [%02x] VF [%04x] [valid %02x] client [%02x] write [%02x] Byte-Enable [%04x] [%08x]\n", 1361b4149dc7SYuval Mintz addr, length, 1362b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_PF_ID), 1363b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_VF_ID), 1364b4149dc7SYuval Mintz (u8) GET_FIELD(data, 1365b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_VF_VALID), 1366b4149dc7SYuval Mintz (u8) GET_FIELD(data, 1367b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_CLIENT), 1368b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_WR), 1369b4149dc7SYuval Mintz (u8) GET_FIELD(data, 1370b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_BYTE_EN), 1371b4149dc7SYuval Mintz data); 1372b4149dc7SYuval Mintz } 1373b4149dc7SYuval Mintz 1374b4149dc7SYuval Mintz return 0; 1375b4149dc7SYuval Mintz } 1376b4149dc7SYuval Mintz 1377b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VALID_BIT (1 << 0) 1378b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_ADDRESS_MASK (0x7fffff) 1379b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_ADDRESS_SHIFT (0) 1380b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_RDWR_BIT (1 << 23) 1381b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_MASTER_MASK (0xf) 1382b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_MASTER_SHIFT (24) 1383b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PF_MASK (0xf) 1384b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PF_SHIFT (0) 1385b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VF_MASK (0xff) 1386b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VF_SHIFT (4) 1387b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_MASK (0x3) 1388b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_SHIFT (14) 1389b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_VF (0) 1390b4149dc7SYuval Mintz static const char *attn_master_to_str(u8 master) 1391b4149dc7SYuval Mintz { 1392b4149dc7SYuval Mintz switch (master) { 1393b4149dc7SYuval Mintz case 1: return "PXP"; 1394b4149dc7SYuval Mintz case 2: return "MCP"; 1395b4149dc7SYuval Mintz case 3: return "MSDM"; 1396b4149dc7SYuval Mintz case 4: return "PSDM"; 1397b4149dc7SYuval Mintz case 5: return "YSDM"; 1398b4149dc7SYuval Mintz case 6: return "USDM"; 1399b4149dc7SYuval Mintz case 7: return "TSDM"; 1400b4149dc7SYuval Mintz case 8: return "XSDM"; 1401b4149dc7SYuval Mintz case 9: return "DBU"; 1402b4149dc7SYuval Mintz case 10: return "DMAE"; 1403b4149dc7SYuval Mintz default: 14049165dabbSMasanari Iida return "Unknown"; 1405b4149dc7SYuval Mintz } 1406b4149dc7SYuval Mintz } 1407b4149dc7SYuval Mintz 1408b4149dc7SYuval Mintz static int qed_grc_attn_cb(struct qed_hwfn *p_hwfn) 1409b4149dc7SYuval Mintz { 1410b4149dc7SYuval Mintz u32 tmp, tmp2; 1411b4149dc7SYuval Mintz 1412b4149dc7SYuval Mintz /* We've already cleared the timeout interrupt register, so we learn 1413b4149dc7SYuval Mintz * of interrupts via the validity register 1414b4149dc7SYuval Mintz */ 1415b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1416b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_VALID); 1417b4149dc7SYuval Mintz if (!(tmp & QED_GRC_ATTENTION_VALID_BIT)) 1418b4149dc7SYuval Mintz goto out; 1419b4149dc7SYuval Mintz 1420b4149dc7SYuval Mintz /* Read the GRC timeout information */ 1421b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1422b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0); 1423b4149dc7SYuval Mintz tmp2 = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1424b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1); 1425b4149dc7SYuval Mintz 1426b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, 1427b4149dc7SYuval Mintz "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n", 1428b4149dc7SYuval Mintz tmp2, tmp, 1429b4149dc7SYuval Mintz (tmp & QED_GRC_ATTENTION_RDWR_BIT) ? "Write to" : "Read from", 1430b4149dc7SYuval Mintz GET_FIELD(tmp, QED_GRC_ATTENTION_ADDRESS) << 2, 1431b4149dc7SYuval Mintz attn_master_to_str(GET_FIELD(tmp, QED_GRC_ATTENTION_MASTER)), 1432b4149dc7SYuval Mintz GET_FIELD(tmp2, QED_GRC_ATTENTION_PF), 1433b4149dc7SYuval Mintz (GET_FIELD(tmp2, QED_GRC_ATTENTION_PRIV) == 1434b4149dc7SYuval Mintz QED_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Ireelevant)", 1435b4149dc7SYuval Mintz GET_FIELD(tmp2, QED_GRC_ATTENTION_VF)); 1436b4149dc7SYuval Mintz 1437b4149dc7SYuval Mintz out: 1438b4149dc7SYuval Mintz /* Regardles of anything else, clean the validity bit */ 1439b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 1440b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0); 1441b4149dc7SYuval Mintz return 0; 1442b4149dc7SYuval Mintz } 1443b4149dc7SYuval Mintz 1444b4149dc7SYuval Mintz #define PGLUE_ATTENTION_VALID (1 << 29) 1445b4149dc7SYuval Mintz #define PGLUE_ATTENTION_RD_VALID (1 << 26) 1446b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf) 1447b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20) 1448b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VF_VALID_MASK (0x1) 1449b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VF_VALID_SHIFT (19) 1450b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff) 1451b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24) 1452b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_MASK (0x1) 1453b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_SHIFT (21) 1454b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_BME_MASK (0x1) 1455b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_BME_SHIFT (22) 1456b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_FID_EN_MASK (0x1) 1457b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_FID_EN_SHIFT (23) 1458b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ICPL_VALID (1 << 23) 1459b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ZLR_VALID (1 << 25) 1460b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ILT_VALID (1 << 23) 1461b4149dc7SYuval Mintz static int qed_pglub_rbc_attn_cb(struct qed_hwfn *p_hwfn) 1462b4149dc7SYuval Mintz { 1463b4149dc7SYuval Mintz u32 tmp; 1464b4149dc7SYuval Mintz 1465b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1466b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_DETAILS2); 1467b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_VALID) { 1468b4149dc7SYuval Mintz u32 addr_lo, addr_hi, details; 1469b4149dc7SYuval Mintz 1470b4149dc7SYuval Mintz addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1471b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_ADD_31_0); 1472b4149dc7SYuval Mintz addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1473b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_ADD_63_32); 1474b4149dc7SYuval Mintz details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1475b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_DETAILS); 1476b4149dc7SYuval Mintz 1477b4149dc7SYuval Mintz DP_INFO(p_hwfn, 1478b4149dc7SYuval Mintz "Illegal write by chip to [%08x:%08x] blocked.\n" 1479b4149dc7SYuval Mintz "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 1480b4149dc7SYuval Mintz "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 1481b4149dc7SYuval Mintz addr_hi, addr_lo, details, 1482b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 1483b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 1484b4149dc7SYuval Mintz GET_FIELD(details, 1485b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0, 1486b4149dc7SYuval Mintz tmp, 1487b4149dc7SYuval Mintz GET_FIELD(tmp, 1488b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0, 1489b4149dc7SYuval Mintz GET_FIELD(tmp, 1490b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0, 1491b4149dc7SYuval Mintz GET_FIELD(tmp, 1492b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0); 1493b4149dc7SYuval Mintz } 1494b4149dc7SYuval Mintz 1495b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1496b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_DETAILS2); 1497b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_RD_VALID) { 1498b4149dc7SYuval Mintz u32 addr_lo, addr_hi, details; 1499b4149dc7SYuval Mintz 1500b4149dc7SYuval Mintz addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1501b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_ADD_31_0); 1502b4149dc7SYuval Mintz addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1503b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_ADD_63_32); 1504b4149dc7SYuval Mintz details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1505b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_DETAILS); 1506b4149dc7SYuval Mintz 1507b4149dc7SYuval Mintz DP_INFO(p_hwfn, 1508b4149dc7SYuval Mintz "Illegal read by chip from [%08x:%08x] blocked.\n" 1509b4149dc7SYuval Mintz " Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 1510b4149dc7SYuval Mintz " Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 1511b4149dc7SYuval Mintz addr_hi, addr_lo, details, 1512b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 1513b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 1514b4149dc7SYuval Mintz GET_FIELD(details, 1515b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0, 1516b4149dc7SYuval Mintz tmp, 1517b4149dc7SYuval Mintz GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 1518b4149dc7SYuval Mintz : 0, 1519b4149dc7SYuval Mintz GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0, 1520b4149dc7SYuval Mintz GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 1521b4149dc7SYuval Mintz : 0); 1522b4149dc7SYuval Mintz } 1523b4149dc7SYuval Mintz 1524b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1525b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL); 1526b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ICPL_VALID) 1527b4149dc7SYuval Mintz DP_INFO(p_hwfn, "ICPL eror - %08x\n", tmp); 1528b4149dc7SYuval Mintz 1529b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1530b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS); 1531b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ZLR_VALID) { 1532b4149dc7SYuval Mintz u32 addr_hi, addr_lo; 1533b4149dc7SYuval Mintz 1534b4149dc7SYuval Mintz addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1535b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0); 1536b4149dc7SYuval Mintz addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1537b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32); 1538b4149dc7SYuval Mintz 1539b4149dc7SYuval Mintz DP_INFO(p_hwfn, "ZLR eror - %08x [Address %08x:%08x]\n", 1540b4149dc7SYuval Mintz tmp, addr_hi, addr_lo); 1541b4149dc7SYuval Mintz } 1542b4149dc7SYuval Mintz 1543b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1544b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_DETAILS2); 1545b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ILT_VALID) { 1546b4149dc7SYuval Mintz u32 addr_hi, addr_lo, details; 1547b4149dc7SYuval Mintz 1548b4149dc7SYuval Mintz addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1549b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_ADD_31_0); 1550b4149dc7SYuval Mintz addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1551b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_ADD_63_32); 1552b4149dc7SYuval Mintz details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1553b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_DETAILS); 1554b4149dc7SYuval Mintz 1555b4149dc7SYuval Mintz DP_INFO(p_hwfn, 1556b4149dc7SYuval Mintz "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n", 1557b4149dc7SYuval Mintz details, tmp, addr_hi, addr_lo); 1558b4149dc7SYuval Mintz } 1559b4149dc7SYuval Mintz 1560b4149dc7SYuval Mintz /* Clear the indications */ 1561b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 1562b4149dc7SYuval Mintz PGLUE_B_REG_LATCHED_ERRORS_CLR, (1 << 2)); 1563b4149dc7SYuval Mintz 1564b4149dc7SYuval Mintz return 0; 1565b4149dc7SYuval Mintz } 1566b4149dc7SYuval Mintz 1567b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_REASON_MASK (0xfffff) 1568b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_OPAQUE_MASK (0xffff) 1569b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_SIZE_MASK (0x7f) 1570b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_SIZE_SHIFT (16) 1571b4149dc7SYuval Mintz static int qed_dorq_attn_cb(struct qed_hwfn *p_hwfn) 1572b4149dc7SYuval Mintz { 1573b4149dc7SYuval Mintz u32 reason; 1574b4149dc7SYuval Mintz 1575b4149dc7SYuval Mintz reason = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, DORQ_REG_DB_DROP_REASON) & 1576b4149dc7SYuval Mintz QED_DORQ_ATTENTION_REASON_MASK; 1577b4149dc7SYuval Mintz if (reason) { 1578b4149dc7SYuval Mintz u32 details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1579b4149dc7SYuval Mintz DORQ_REG_DB_DROP_DETAILS); 1580b4149dc7SYuval Mintz 1581b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, 15829165dabbSMasanari Iida "DORQ db_drop: address 0x%08x Opaque FID 0x%04x Size [bytes] 0x%08x Reason: 0x%08x\n", 1583b4149dc7SYuval Mintz qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1584b4149dc7SYuval Mintz DORQ_REG_DB_DROP_DETAILS_ADDRESS), 1585b4149dc7SYuval Mintz (u16)(details & QED_DORQ_ATTENTION_OPAQUE_MASK), 1586b4149dc7SYuval Mintz GET_FIELD(details, QED_DORQ_ATTENTION_SIZE) * 4, 1587b4149dc7SYuval Mintz reason); 1588b4149dc7SYuval Mintz } 1589b4149dc7SYuval Mintz 1590b4149dc7SYuval Mintz return -EINVAL; 1591b4149dc7SYuval Mintz } 1592b4149dc7SYuval Mintz 15930d956e8aSYuval Mintz /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */ 15940d956e8aSYuval Mintz static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = { 15950d956e8aSYuval Mintz { 15960d956e8aSYuval Mintz { /* After Invert 1 */ 15970d956e8aSYuval Mintz {"GPIO0 function%d", 1598b4149dc7SYuval Mintz (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 15990d956e8aSYuval Mintz } 16000d956e8aSYuval Mintz }, 16010d956e8aSYuval Mintz 16020d956e8aSYuval Mintz { 16030d956e8aSYuval Mintz { /* After Invert 2 */ 1604b4149dc7SYuval Mintz {"PGLUE config_space", ATTENTION_SINGLE, 1605b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1606b4149dc7SYuval Mintz {"PGLUE misc_flr", ATTENTION_SINGLE, 1607b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1608b4149dc7SYuval Mintz {"PGLUE B RBC", ATTENTION_PAR_INT, 1609b4149dc7SYuval Mintz qed_pglub_rbc_attn_cb, BLOCK_PGLUE_B}, 1610b4149dc7SYuval Mintz {"PGLUE misc_mctp", ATTENTION_SINGLE, 1611b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1612b4149dc7SYuval Mintz {"Flash event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 1613b4149dc7SYuval Mintz {"SMB event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 1614b4149dc7SYuval Mintz {"Main Power", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 16150d956e8aSYuval Mintz {"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) | 1616ff38577aSYuval Mintz (1 << ATTENTION_OFFSET_SHIFT), 1617b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 16180d956e8aSYuval Mintz {"PCIE glue/PXP VPD %d", 1619b4149dc7SYuval Mintz (16 << ATTENTION_LENGTH_SHIFT), NULL, BLOCK_PGLCS}, 16200d956e8aSYuval Mintz } 16210d956e8aSYuval Mintz }, 16220d956e8aSYuval Mintz 16230d956e8aSYuval Mintz { 16240d956e8aSYuval Mintz { /* After Invert 3 */ 16250d956e8aSYuval Mintz {"General Attention %d", 1626b4149dc7SYuval Mintz (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 16270d956e8aSYuval Mintz } 16280d956e8aSYuval Mintz }, 16290d956e8aSYuval Mintz 16300d956e8aSYuval Mintz { 16310d956e8aSYuval Mintz { /* After Invert 4 */ 1632ff38577aSYuval Mintz {"General Attention 32", ATTENTION_SINGLE, 1633b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 16340d956e8aSYuval Mintz {"General Attention %d", 16350d956e8aSYuval Mintz (2 << ATTENTION_LENGTH_SHIFT) | 1636b4149dc7SYuval Mintz (33 << ATTENTION_OFFSET_SHIFT), NULL, MAX_BLOCK_ID}, 1637ff38577aSYuval Mintz {"General Attention 35", ATTENTION_SINGLE, 1638b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1639ff38577aSYuval Mintz {"CNIG port %d", (4 << ATTENTION_LENGTH_SHIFT), 1640b4149dc7SYuval Mintz NULL, BLOCK_CNIG}, 1641b4149dc7SYuval Mintz {"MCP CPU", ATTENTION_SINGLE, 1642b4149dc7SYuval Mintz qed_mcp_attn_cb, MAX_BLOCK_ID}, 1643b4149dc7SYuval Mintz {"MCP Watchdog timer", ATTENTION_SINGLE, 1644b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1645b4149dc7SYuval Mintz {"MCP M2P", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 1646ff38577aSYuval Mintz {"AVS stop status ready", ATTENTION_SINGLE, 1647b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1648b4149dc7SYuval Mintz {"MSTAT", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 1649b4149dc7SYuval Mintz {"MSTAT per-path", ATTENTION_PAR_INT, 1650b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1651ff38577aSYuval Mintz {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), 1652b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1653b4149dc7SYuval Mintz {"NIG", ATTENTION_PAR_INT, NULL, BLOCK_NIG}, 1654b4149dc7SYuval Mintz {"BMB/OPTE/MCP", ATTENTION_PAR_INT, NULL, BLOCK_BMB}, 1655b4149dc7SYuval Mintz {"BTB", ATTENTION_PAR_INT, NULL, BLOCK_BTB}, 1656b4149dc7SYuval Mintz {"BRB", ATTENTION_PAR_INT, NULL, BLOCK_BRB}, 1657b4149dc7SYuval Mintz {"PRS", ATTENTION_PAR_INT, NULL, BLOCK_PRS}, 16580d956e8aSYuval Mintz } 16590d956e8aSYuval Mintz }, 16600d956e8aSYuval Mintz 16610d956e8aSYuval Mintz { 16620d956e8aSYuval Mintz { /* After Invert 5 */ 1663b4149dc7SYuval Mintz {"SRC", ATTENTION_PAR_INT, NULL, BLOCK_SRC}, 1664b4149dc7SYuval Mintz {"PB Client1", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB1}, 1665b4149dc7SYuval Mintz {"PB Client2", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB2}, 1666b4149dc7SYuval Mintz {"RPB", ATTENTION_PAR_INT, NULL, BLOCK_RPB}, 1667b4149dc7SYuval Mintz {"PBF", ATTENTION_PAR_INT, NULL, BLOCK_PBF}, 1668b4149dc7SYuval Mintz {"QM", ATTENTION_PAR_INT, NULL, BLOCK_QM}, 1669b4149dc7SYuval Mintz {"TM", ATTENTION_PAR_INT, NULL, BLOCK_TM}, 1670b4149dc7SYuval Mintz {"MCM", ATTENTION_PAR_INT, NULL, BLOCK_MCM}, 1671b4149dc7SYuval Mintz {"MSDM", ATTENTION_PAR_INT, NULL, BLOCK_MSDM}, 1672b4149dc7SYuval Mintz {"MSEM", ATTENTION_PAR_INT, NULL, BLOCK_MSEM}, 1673b4149dc7SYuval Mintz {"PCM", ATTENTION_PAR_INT, NULL, BLOCK_PCM}, 1674b4149dc7SYuval Mintz {"PSDM", ATTENTION_PAR_INT, NULL, BLOCK_PSDM}, 1675b4149dc7SYuval Mintz {"PSEM", ATTENTION_PAR_INT, NULL, BLOCK_PSEM}, 1676b4149dc7SYuval Mintz {"TCM", ATTENTION_PAR_INT, NULL, BLOCK_TCM}, 1677b4149dc7SYuval Mintz {"TSDM", ATTENTION_PAR_INT, NULL, BLOCK_TSDM}, 1678b4149dc7SYuval Mintz {"TSEM", ATTENTION_PAR_INT, NULL, BLOCK_TSEM}, 16790d956e8aSYuval Mintz } 16800d956e8aSYuval Mintz }, 16810d956e8aSYuval Mintz 16820d956e8aSYuval Mintz { 16830d956e8aSYuval Mintz { /* After Invert 6 */ 1684b4149dc7SYuval Mintz {"UCM", ATTENTION_PAR_INT, NULL, BLOCK_UCM}, 1685b4149dc7SYuval Mintz {"USDM", ATTENTION_PAR_INT, NULL, BLOCK_USDM}, 1686b4149dc7SYuval Mintz {"USEM", ATTENTION_PAR_INT, NULL, BLOCK_USEM}, 1687b4149dc7SYuval Mintz {"XCM", ATTENTION_PAR_INT, NULL, BLOCK_XCM}, 1688b4149dc7SYuval Mintz {"XSDM", ATTENTION_PAR_INT, NULL, BLOCK_XSDM}, 1689b4149dc7SYuval Mintz {"XSEM", ATTENTION_PAR_INT, NULL, BLOCK_XSEM}, 1690b4149dc7SYuval Mintz {"YCM", ATTENTION_PAR_INT, NULL, BLOCK_YCM}, 1691b4149dc7SYuval Mintz {"YSDM", ATTENTION_PAR_INT, NULL, BLOCK_YSDM}, 1692b4149dc7SYuval Mintz {"YSEM", ATTENTION_PAR_INT, NULL, BLOCK_YSEM}, 1693b4149dc7SYuval Mintz {"XYLD", ATTENTION_PAR_INT, NULL, BLOCK_XYLD}, 1694b4149dc7SYuval Mintz {"TMLD", ATTENTION_PAR_INT, NULL, BLOCK_TMLD}, 1695b4149dc7SYuval Mintz {"MYLD", ATTENTION_PAR_INT, NULL, BLOCK_MULD}, 1696b4149dc7SYuval Mintz {"YULD", ATTENTION_PAR_INT, NULL, BLOCK_YULD}, 1697b4149dc7SYuval Mintz {"DORQ", ATTENTION_PAR_INT, 1698b4149dc7SYuval Mintz qed_dorq_attn_cb, BLOCK_DORQ}, 1699b4149dc7SYuval Mintz {"DBG", ATTENTION_PAR_INT, NULL, BLOCK_DBG}, 1700b4149dc7SYuval Mintz {"IPC", ATTENTION_PAR_INT, NULL, BLOCK_IPC}, 17010d956e8aSYuval Mintz } 17020d956e8aSYuval Mintz }, 17030d956e8aSYuval Mintz 17040d956e8aSYuval Mintz { 17050d956e8aSYuval Mintz { /* After Invert 7 */ 1706b4149dc7SYuval Mintz {"CCFC", ATTENTION_PAR_INT, NULL, BLOCK_CCFC}, 1707b4149dc7SYuval Mintz {"CDU", ATTENTION_PAR_INT, NULL, BLOCK_CDU}, 1708b4149dc7SYuval Mintz {"DMAE", ATTENTION_PAR_INT, NULL, BLOCK_DMAE}, 1709b4149dc7SYuval Mintz {"IGU", ATTENTION_PAR_INT, NULL, BLOCK_IGU}, 1710b4149dc7SYuval Mintz {"ATC", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 1711b4149dc7SYuval Mintz {"CAU", ATTENTION_PAR_INT, NULL, BLOCK_CAU}, 1712b4149dc7SYuval Mintz {"PTU", ATTENTION_PAR_INT, NULL, BLOCK_PTU}, 1713b4149dc7SYuval Mintz {"PRM", ATTENTION_PAR_INT, NULL, BLOCK_PRM}, 1714b4149dc7SYuval Mintz {"TCFC", ATTENTION_PAR_INT, NULL, BLOCK_TCFC}, 1715b4149dc7SYuval Mintz {"RDIF", ATTENTION_PAR_INT, NULL, BLOCK_RDIF}, 1716b4149dc7SYuval Mintz {"TDIF", ATTENTION_PAR_INT, NULL, BLOCK_TDIF}, 1717b4149dc7SYuval Mintz {"RSS", ATTENTION_PAR_INT, NULL, BLOCK_RSS}, 1718b4149dc7SYuval Mintz {"MISC", ATTENTION_PAR_INT, NULL, BLOCK_MISC}, 1719b4149dc7SYuval Mintz {"MISCS", ATTENTION_PAR_INT, NULL, BLOCK_MISCS}, 1720b4149dc7SYuval Mintz {"PCIE", ATTENTION_PAR, NULL, BLOCK_PCIE}, 1721b4149dc7SYuval Mintz {"Vaux PCI core", ATTENTION_SINGLE, NULL, BLOCK_PGLCS}, 1722b4149dc7SYuval Mintz {"PSWRQ", ATTENTION_PAR_INT, NULL, BLOCK_PSWRQ}, 17230d956e8aSYuval Mintz } 17240d956e8aSYuval Mintz }, 17250d956e8aSYuval Mintz 17260d956e8aSYuval Mintz { 17270d956e8aSYuval Mintz { /* After Invert 8 */ 1728b4149dc7SYuval Mintz {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, 1729b4149dc7SYuval Mintz NULL, BLOCK_PSWRQ2}, 1730b4149dc7SYuval Mintz {"PSWWR", ATTENTION_PAR_INT, NULL, BLOCK_PSWWR}, 1731b4149dc7SYuval Mintz {"PSWWR (pci_clk)", ATTENTION_PAR_INT, 1732b4149dc7SYuval Mintz NULL, BLOCK_PSWWR2}, 1733b4149dc7SYuval Mintz {"PSWRD", ATTENTION_PAR_INT, NULL, BLOCK_PSWRD}, 1734b4149dc7SYuval Mintz {"PSWRD (pci_clk)", ATTENTION_PAR_INT, 1735b4149dc7SYuval Mintz NULL, BLOCK_PSWRD2}, 1736b4149dc7SYuval Mintz {"PSWHST", ATTENTION_PAR_INT, 1737b4149dc7SYuval Mintz qed_pswhst_attn_cb, BLOCK_PSWHST}, 1738b4149dc7SYuval Mintz {"PSWHST (pci_clk)", ATTENTION_PAR_INT, 1739b4149dc7SYuval Mintz NULL, BLOCK_PSWHST2}, 1740b4149dc7SYuval Mintz {"GRC", ATTENTION_PAR_INT, 1741b4149dc7SYuval Mintz qed_grc_attn_cb, BLOCK_GRC}, 1742b4149dc7SYuval Mintz {"CPMU", ATTENTION_PAR_INT, NULL, BLOCK_CPMU}, 1743b4149dc7SYuval Mintz {"NCSI", ATTENTION_PAR_INT, NULL, BLOCK_NCSI}, 1744b4149dc7SYuval Mintz {"MSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 1745b4149dc7SYuval Mintz {"PSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 1746b4149dc7SYuval Mintz {"TSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 1747b4149dc7SYuval Mintz {"USEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 1748b4149dc7SYuval Mintz {"XSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 1749b4149dc7SYuval Mintz {"YSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 1750b4149dc7SYuval Mintz {"pxp_misc_mps", ATTENTION_PAR, NULL, BLOCK_PGLCS}, 1751ff38577aSYuval Mintz {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, 1752b4149dc7SYuval Mintz NULL, BLOCK_PGLCS}, 1753b4149dc7SYuval Mintz {"PERST_B assertion", ATTENTION_SINGLE, 1754b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1755ff38577aSYuval Mintz {"PERST_B deassertion", ATTENTION_SINGLE, 1756b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1757ff38577aSYuval Mintz {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), 1758b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 17590d956e8aSYuval Mintz } 17600d956e8aSYuval Mintz }, 17610d956e8aSYuval Mintz 17620d956e8aSYuval Mintz { 17630d956e8aSYuval Mintz { /* After Invert 9 */ 1764b4149dc7SYuval Mintz {"MCP Latched memory", ATTENTION_PAR, 1765b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1766ff38577aSYuval Mintz {"MCP Latched scratchpad cache", ATTENTION_SINGLE, 1767b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1768b4149dc7SYuval Mintz {"MCP Latched ump_tx", ATTENTION_PAR, 1769b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1770ff38577aSYuval Mintz {"MCP Latched scratchpad", ATTENTION_PAR, 1771b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 1772ff38577aSYuval Mintz {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT), 1773b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 17740d956e8aSYuval Mintz } 17750d956e8aSYuval Mintz }, 17760d956e8aSYuval Mintz }; 17770d956e8aSYuval Mintz 1778cc875c2eSYuval Mintz #define ATTN_STATE_BITS (0xfff) 1779cc875c2eSYuval Mintz #define ATTN_BITS_MASKABLE (0x3ff) 1780cc875c2eSYuval Mintz struct qed_sb_attn_info { 1781cc875c2eSYuval Mintz /* Virtual & Physical address of the SB */ 1782cc875c2eSYuval Mintz struct atten_status_block *sb_attn; 1783cc875c2eSYuval Mintz dma_addr_t sb_phys; 1784cc875c2eSYuval Mintz 1785cc875c2eSYuval Mintz /* Last seen running index */ 1786cc875c2eSYuval Mintz u16 index; 1787cc875c2eSYuval Mintz 17880d956e8aSYuval Mintz /* A mask of the AEU bits resulting in a parity error */ 17890d956e8aSYuval Mintz u32 parity_mask[NUM_ATTN_REGS]; 17900d956e8aSYuval Mintz 17910d956e8aSYuval Mintz /* A pointer to the attention description structure */ 17920d956e8aSYuval Mintz struct aeu_invert_reg *p_aeu_desc; 17930d956e8aSYuval Mintz 1794cc875c2eSYuval Mintz /* Previously asserted attentions, which are still unasserted */ 1795cc875c2eSYuval Mintz u16 known_attn; 1796cc875c2eSYuval Mintz 1797cc875c2eSYuval Mintz /* Cleanup address for the link's general hw attention */ 1798cc875c2eSYuval Mintz u32 mfw_attn_addr; 1799cc875c2eSYuval Mintz }; 1800cc875c2eSYuval Mintz 1801cc875c2eSYuval Mintz static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn, 1802cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb_desc) 1803cc875c2eSYuval Mintz { 18041a635e48SYuval Mintz u16 rc = 0, index; 1805cc875c2eSYuval Mintz 1806cc875c2eSYuval Mintz /* Make certain HW write took affect */ 1807cc875c2eSYuval Mintz mmiowb(); 1808cc875c2eSYuval Mintz 1809cc875c2eSYuval Mintz index = le16_to_cpu(p_sb_desc->sb_attn->sb_index); 1810cc875c2eSYuval Mintz if (p_sb_desc->index != index) { 1811cc875c2eSYuval Mintz p_sb_desc->index = index; 1812cc875c2eSYuval Mintz rc = QED_SB_ATT_IDX; 1813cc875c2eSYuval Mintz } 1814cc875c2eSYuval Mintz 1815cc875c2eSYuval Mintz /* Make certain we got a consistent view with HW */ 1816cc875c2eSYuval Mintz mmiowb(); 1817cc875c2eSYuval Mintz 1818cc875c2eSYuval Mintz return rc; 1819cc875c2eSYuval Mintz } 1820cc875c2eSYuval Mintz 1821cc875c2eSYuval Mintz /** 1822cc875c2eSYuval Mintz * @brief qed_int_assertion - handles asserted attention bits 1823cc875c2eSYuval Mintz * 1824cc875c2eSYuval Mintz * @param p_hwfn 1825cc875c2eSYuval Mintz * @param asserted_bits newly asserted bits 1826cc875c2eSYuval Mintz * @return int 1827cc875c2eSYuval Mintz */ 18281a635e48SYuval Mintz static int qed_int_assertion(struct qed_hwfn *p_hwfn, u16 asserted_bits) 1829cc875c2eSYuval Mintz { 1830cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 1831cc875c2eSYuval Mintz u32 igu_mask; 1832cc875c2eSYuval Mintz 1833cc875c2eSYuval Mintz /* Mask the source of the attention in the IGU */ 18341a635e48SYuval Mintz igu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); 1835cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n", 1836cc875c2eSYuval Mintz igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE)); 1837cc875c2eSYuval Mintz igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE); 1838cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask); 1839cc875c2eSYuval Mintz 1840cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1841cc875c2eSYuval Mintz "inner known ATTN state: 0x%04x --> 0x%04x\n", 1842cc875c2eSYuval Mintz sb_attn_sw->known_attn, 1843cc875c2eSYuval Mintz sb_attn_sw->known_attn | asserted_bits); 1844cc875c2eSYuval Mintz sb_attn_sw->known_attn |= asserted_bits; 1845cc875c2eSYuval Mintz 1846cc875c2eSYuval Mintz /* Handle MCP events */ 1847cc875c2eSYuval Mintz if (asserted_bits & 0x100) { 1848cc875c2eSYuval Mintz qed_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt); 1849cc875c2eSYuval Mintz /* Clean the MCP attention */ 1850cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 1851cc875c2eSYuval Mintz sb_attn_sw->mfw_attn_addr, 0); 1852cc875c2eSYuval Mintz } 1853cc875c2eSYuval Mintz 1854cc875c2eSYuval Mintz DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 1855cc875c2eSYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 1856cc875c2eSYuval Mintz ((IGU_CMD_ATTN_BIT_SET_UPPER - 1857cc875c2eSYuval Mintz IGU_CMD_INT_ACK_BASE) << 3), 1858cc875c2eSYuval Mintz (u32)asserted_bits); 1859cc875c2eSYuval Mintz 1860cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "set cmd IGU: 0x%04x\n", 1861cc875c2eSYuval Mintz asserted_bits); 1862cc875c2eSYuval Mintz 1863cc875c2eSYuval Mintz return 0; 1864cc875c2eSYuval Mintz } 1865cc875c2eSYuval Mintz 1866ff38577aSYuval Mintz static void qed_int_deassertion_print_bit(struct qed_hwfn *p_hwfn, 1867ff38577aSYuval Mintz struct attn_hw_reg *p_reg_desc, 1868ff38577aSYuval Mintz struct attn_hw_block *p_block, 1869ff38577aSYuval Mintz enum qed_attention_type type, 1870ff38577aSYuval Mintz u32 val, u32 mask) 1871ff38577aSYuval Mintz { 1872ff38577aSYuval Mintz int j; 1873ff38577aSYuval Mintz 1874ff38577aSYuval Mintz for (j = 0; j < p_reg_desc->num_of_bits; j++) { 1875ff38577aSYuval Mintz if (!(val & (1 << j))) 1876ff38577aSYuval Mintz continue; 1877ff38577aSYuval Mintz 1878ff38577aSYuval Mintz DP_NOTICE(p_hwfn, 1879ff38577aSYuval Mintz "%s (%s): reg %d [0x%08x], bit %d [%s]\n", 1880ff38577aSYuval Mintz p_block->name, 1881ff38577aSYuval Mintz type == QED_ATTN_TYPE_ATTN ? "Interrupt" : 1882ff38577aSYuval Mintz "Parity", 1883ff38577aSYuval Mintz p_reg_desc->reg_idx, p_reg_desc->sts_addr, 1884ff38577aSYuval Mintz j, (mask & (1 << j)) ? " [MASKED]" : ""); 1885ff38577aSYuval Mintz } 1886ff38577aSYuval Mintz } 1887ff38577aSYuval Mintz 1888cc875c2eSYuval Mintz /** 18890d956e8aSYuval Mintz * @brief qed_int_deassertion_aeu_bit - handles the effects of a single 18900d956e8aSYuval Mintz * cause of the attention 18910d956e8aSYuval Mintz * 18920d956e8aSYuval Mintz * @param p_hwfn 18930d956e8aSYuval Mintz * @param p_aeu - descriptor of an AEU bit which caused the attention 18940d956e8aSYuval Mintz * @param aeu_en_reg - register offset of the AEU enable reg. which configured 18950d956e8aSYuval Mintz * this bit to this group. 18960d956e8aSYuval Mintz * @param bit_index - index of this bit in the aeu_en_reg 18970d956e8aSYuval Mintz * 18980d956e8aSYuval Mintz * @return int 18990d956e8aSYuval Mintz */ 19000d956e8aSYuval Mintz static int 19010d956e8aSYuval Mintz qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn, 19020d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_aeu, 19030d956e8aSYuval Mintz u32 aeu_en_reg, 19040d956e8aSYuval Mintz u32 bitmask) 19050d956e8aSYuval Mintz { 19060d956e8aSYuval Mintz int rc = -EINVAL; 1907b4149dc7SYuval Mintz u32 val; 19080d956e8aSYuval Mintz 19090d956e8aSYuval Mintz DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n", 19100d956e8aSYuval Mintz p_aeu->bit_name, bitmask); 19110d956e8aSYuval Mintz 1912b4149dc7SYuval Mintz /* Call callback before clearing the interrupt status */ 1913b4149dc7SYuval Mintz if (p_aeu->cb) { 1914b4149dc7SYuval Mintz DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n", 1915b4149dc7SYuval Mintz p_aeu->bit_name); 1916b4149dc7SYuval Mintz rc = p_aeu->cb(p_hwfn); 1917b4149dc7SYuval Mintz } 1918b4149dc7SYuval Mintz 1919ff38577aSYuval Mintz /* Handle HW block interrupt registers */ 1920ff38577aSYuval Mintz if (p_aeu->block_index != MAX_BLOCK_ID) { 1921ff38577aSYuval Mintz struct attn_hw_block *p_block; 1922b4149dc7SYuval Mintz u32 mask; 1923ff38577aSYuval Mintz int i; 1924ff38577aSYuval Mintz 1925ff38577aSYuval Mintz p_block = &attn_blocks[p_aeu->block_index]; 1926ff38577aSYuval Mintz 1927ff38577aSYuval Mintz /* Handle each interrupt register */ 1928ff38577aSYuval Mintz for (i = 0; i < p_block->chip_regs[0].num_of_int_regs; i++) { 1929ff38577aSYuval Mintz struct attn_hw_reg *p_reg_desc; 1930ff38577aSYuval Mintz u32 sts_addr; 1931ff38577aSYuval Mintz 1932ff38577aSYuval Mintz p_reg_desc = p_block->chip_regs[0].int_regs[i]; 1933b4149dc7SYuval Mintz 1934b4149dc7SYuval Mintz /* In case of fatal attention, don't clear the status 1935b4149dc7SYuval Mintz * so it would appear in following idle check. 1936b4149dc7SYuval Mintz */ 1937b4149dc7SYuval Mintz if (rc == 0) 1938b4149dc7SYuval Mintz sts_addr = p_reg_desc->sts_clr_addr; 1939b4149dc7SYuval Mintz else 1940ff38577aSYuval Mintz sts_addr = p_reg_desc->sts_addr; 1941ff38577aSYuval Mintz 1942ff38577aSYuval Mintz val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, sts_addr); 1943ff38577aSYuval Mintz mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1944ff38577aSYuval Mintz p_reg_desc->mask_addr); 1945ff38577aSYuval Mintz qed_int_deassertion_print_bit(p_hwfn, p_reg_desc, 1946ff38577aSYuval Mintz p_block, 1947ff38577aSYuval Mintz QED_ATTN_TYPE_ATTN, 1948ff38577aSYuval Mintz val, mask); 1949ff38577aSYuval Mintz } 1950ff38577aSYuval Mintz } 1951ff38577aSYuval Mintz 1952b4149dc7SYuval Mintz /* If the attention is benign, no need to prevent it */ 1953b4149dc7SYuval Mintz if (!rc) 1954b4149dc7SYuval Mintz goto out; 1955b4149dc7SYuval Mintz 19560d956e8aSYuval Mintz /* Prevent this Attention from being asserted in the future */ 19570d956e8aSYuval Mintz val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 1958b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & ~bitmask)); 19590d956e8aSYuval Mintz DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n", 19600d956e8aSYuval Mintz p_aeu->bit_name); 19610d956e8aSYuval Mintz 1962b4149dc7SYuval Mintz out: 19630d956e8aSYuval Mintz return rc; 19640d956e8aSYuval Mintz } 19650d956e8aSYuval Mintz 1966ff38577aSYuval Mintz static void qed_int_parity_print(struct qed_hwfn *p_hwfn, 1967ff38577aSYuval Mintz struct aeu_invert_reg_bit *p_aeu, 1968ff38577aSYuval Mintz struct attn_hw_block *p_block, 1969ff38577aSYuval Mintz u8 bit_index) 1970ff38577aSYuval Mintz { 1971ff38577aSYuval Mintz int i; 1972ff38577aSYuval Mintz 1973ff38577aSYuval Mintz for (i = 0; i < p_block->chip_regs[0].num_of_prty_regs; i++) { 1974ff38577aSYuval Mintz struct attn_hw_reg *p_reg_desc; 1975ff38577aSYuval Mintz u32 val, mask; 1976ff38577aSYuval Mintz 1977ff38577aSYuval Mintz p_reg_desc = p_block->chip_regs[0].prty_regs[i]; 1978ff38577aSYuval Mintz 1979ff38577aSYuval Mintz val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1980ff38577aSYuval Mintz p_reg_desc->sts_clr_addr); 1981ff38577aSYuval Mintz mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 1982ff38577aSYuval Mintz p_reg_desc->mask_addr); 1983ff38577aSYuval Mintz qed_int_deassertion_print_bit(p_hwfn, p_reg_desc, 1984ff38577aSYuval Mintz p_block, 1985ff38577aSYuval Mintz QED_ATTN_TYPE_PARITY, 1986ff38577aSYuval Mintz val, mask); 1987ff38577aSYuval Mintz } 1988ff38577aSYuval Mintz } 1989ff38577aSYuval Mintz 1990ff38577aSYuval Mintz /** 1991ff38577aSYuval Mintz * @brief qed_int_deassertion_parity - handle a single parity AEU source 1992ff38577aSYuval Mintz * 1993ff38577aSYuval Mintz * @param p_hwfn 1994ff38577aSYuval Mintz * @param p_aeu - descriptor of an AEU bit which caused the parity 1995ff38577aSYuval Mintz * @param bit_index 1996ff38577aSYuval Mintz */ 1997ff38577aSYuval Mintz static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn, 1998ff38577aSYuval Mintz struct aeu_invert_reg_bit *p_aeu, 1999ff38577aSYuval Mintz u8 bit_index) 2000ff38577aSYuval Mintz { 2001ff38577aSYuval Mintz u32 block_id = p_aeu->block_index; 2002ff38577aSYuval Mintz 2003ff38577aSYuval Mintz DP_INFO(p_hwfn->cdev, "%s[%d] parity attention is set\n", 2004ff38577aSYuval Mintz p_aeu->bit_name, bit_index); 2005ff38577aSYuval Mintz 2006ff38577aSYuval Mintz if (block_id != MAX_BLOCK_ID) { 2007ff38577aSYuval Mintz qed_int_parity_print(p_hwfn, p_aeu, &attn_blocks[block_id], 2008ff38577aSYuval Mintz bit_index); 2009ff38577aSYuval Mintz 2010ff38577aSYuval Mintz /* In BB, there's a single parity bit for several blocks */ 2011ff38577aSYuval Mintz if (block_id == BLOCK_BTB) { 2012ff38577aSYuval Mintz qed_int_parity_print(p_hwfn, p_aeu, 2013ff38577aSYuval Mintz &attn_blocks[BLOCK_OPTE], 2014ff38577aSYuval Mintz bit_index); 2015ff38577aSYuval Mintz qed_int_parity_print(p_hwfn, p_aeu, 2016ff38577aSYuval Mintz &attn_blocks[BLOCK_MCP], 2017ff38577aSYuval Mintz bit_index); 2018ff38577aSYuval Mintz } 2019ff38577aSYuval Mintz } 2020ff38577aSYuval Mintz } 2021ff38577aSYuval Mintz 20220d956e8aSYuval Mintz /** 2023cc875c2eSYuval Mintz * @brief - handles deassertion of previously asserted attentions. 2024cc875c2eSYuval Mintz * 2025cc875c2eSYuval Mintz * @param p_hwfn 2026cc875c2eSYuval Mintz * @param deasserted_bits - newly deasserted bits 2027cc875c2eSYuval Mintz * @return int 2028cc875c2eSYuval Mintz * 2029cc875c2eSYuval Mintz */ 2030cc875c2eSYuval Mintz static int qed_int_deassertion(struct qed_hwfn *p_hwfn, 2031cc875c2eSYuval Mintz u16 deasserted_bits) 2032cc875c2eSYuval Mintz { 2033cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 20340d956e8aSYuval Mintz u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask; 20350d956e8aSYuval Mintz u8 i, j, k, bit_idx; 20360d956e8aSYuval Mintz int rc = 0; 2037cc875c2eSYuval Mintz 20380d956e8aSYuval Mintz /* Read the attention registers in the AEU */ 20390d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 20400d956e8aSYuval Mintz aeu_inv_arr[i] = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 20410d956e8aSYuval Mintz MISC_REG_AEU_AFTER_INVERT_1_IGU + 20420d956e8aSYuval Mintz i * 0x4); 20430d956e8aSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 20440d956e8aSYuval Mintz "Deasserted bits [%d]: %08x\n", 20450d956e8aSYuval Mintz i, aeu_inv_arr[i]); 20460d956e8aSYuval Mintz } 20470d956e8aSYuval Mintz 20480d956e8aSYuval Mintz /* Find parity attentions first */ 20490d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 20500d956e8aSYuval Mintz struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i]; 20510d956e8aSYuval Mintz u32 en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 20520d956e8aSYuval Mintz MISC_REG_AEU_ENABLE1_IGU_OUT_0 + 20530d956e8aSYuval Mintz i * sizeof(u32)); 20540d956e8aSYuval Mintz u32 parities; 20550d956e8aSYuval Mintz 20560d956e8aSYuval Mintz /* Skip register in which no parity bit is currently set */ 20570d956e8aSYuval Mintz parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en; 20580d956e8aSYuval Mintz if (!parities) 20590d956e8aSYuval Mintz continue; 20600d956e8aSYuval Mintz 20610d956e8aSYuval Mintz for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 20620d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j]; 20630d956e8aSYuval Mintz 20640d956e8aSYuval Mintz if ((p_bit->flags & ATTENTION_PARITY) && 20651a635e48SYuval Mintz !!(parities & BIT(bit_idx))) 2066ff38577aSYuval Mintz qed_int_deassertion_parity(p_hwfn, p_bit, 2067ff38577aSYuval Mintz bit_idx); 20680d956e8aSYuval Mintz 20690d956e8aSYuval Mintz bit_idx += ATTENTION_LENGTH(p_bit->flags); 20700d956e8aSYuval Mintz } 20710d956e8aSYuval Mintz } 20720d956e8aSYuval Mintz 20730d956e8aSYuval Mintz /* Find non-parity cause for attention and act */ 20740d956e8aSYuval Mintz for (k = 0; k < MAX_ATTN_GRPS; k++) { 20750d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_aeu; 20760d956e8aSYuval Mintz 20770d956e8aSYuval Mintz /* Handle only groups whose attention is currently deasserted */ 20780d956e8aSYuval Mintz if (!(deasserted_bits & (1 << k))) 20790d956e8aSYuval Mintz continue; 20800d956e8aSYuval Mintz 20810d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 20820d956e8aSYuval Mintz u32 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + 20830d956e8aSYuval Mintz i * sizeof(u32) + 20840d956e8aSYuval Mintz k * sizeof(u32) * NUM_ATTN_REGS; 20850d956e8aSYuval Mintz u32 en, bits; 20860d956e8aSYuval Mintz 20870d956e8aSYuval Mintz en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 20880d956e8aSYuval Mintz bits = aeu_inv_arr[i] & en; 20890d956e8aSYuval Mintz 20900d956e8aSYuval Mintz /* Skip if no bit from this group is currently set */ 20910d956e8aSYuval Mintz if (!bits) 20920d956e8aSYuval Mintz continue; 20930d956e8aSYuval Mintz 20940d956e8aSYuval Mintz /* Find all set bits from current register which belong 20950d956e8aSYuval Mintz * to current group, making them responsible for the 20960d956e8aSYuval Mintz * previous assertion. 20970d956e8aSYuval Mintz */ 20980d956e8aSYuval Mintz for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 20990d956e8aSYuval Mintz u8 bit, bit_len; 21000d956e8aSYuval Mintz u32 bitmask; 21010d956e8aSYuval Mintz 21020d956e8aSYuval Mintz p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j]; 21030d956e8aSYuval Mintz 21040d956e8aSYuval Mintz /* No need to handle parity-only bits */ 21050d956e8aSYuval Mintz if (p_aeu->flags == ATTENTION_PAR) 21060d956e8aSYuval Mintz continue; 21070d956e8aSYuval Mintz 21080d956e8aSYuval Mintz bit = bit_idx; 21090d956e8aSYuval Mintz bit_len = ATTENTION_LENGTH(p_aeu->flags); 21100d956e8aSYuval Mintz if (p_aeu->flags & ATTENTION_PAR_INT) { 21110d956e8aSYuval Mintz /* Skip Parity */ 21120d956e8aSYuval Mintz bit++; 21130d956e8aSYuval Mintz bit_len--; 21140d956e8aSYuval Mintz } 21150d956e8aSYuval Mintz 21160d956e8aSYuval Mintz bitmask = bits & (((1 << bit_len) - 1) << bit); 21170d956e8aSYuval Mintz if (bitmask) { 21180d956e8aSYuval Mintz /* Handle source of the attention */ 21190d956e8aSYuval Mintz qed_int_deassertion_aeu_bit(p_hwfn, 21200d956e8aSYuval Mintz p_aeu, 21210d956e8aSYuval Mintz aeu_en, 21220d956e8aSYuval Mintz bitmask); 21230d956e8aSYuval Mintz } 21240d956e8aSYuval Mintz 21250d956e8aSYuval Mintz bit_idx += ATTENTION_LENGTH(p_aeu->flags); 21260d956e8aSYuval Mintz } 21270d956e8aSYuval Mintz } 21280d956e8aSYuval Mintz } 2129cc875c2eSYuval Mintz 2130cc875c2eSYuval Mintz /* Clear IGU indication for the deasserted bits */ 2131cc875c2eSYuval Mintz DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 2132cc875c2eSYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 2133cc875c2eSYuval Mintz ((IGU_CMD_ATTN_BIT_CLR_UPPER - 2134cc875c2eSYuval Mintz IGU_CMD_INT_ACK_BASE) << 3), 2135cc875c2eSYuval Mintz ~((u32)deasserted_bits)); 2136cc875c2eSYuval Mintz 2137cc875c2eSYuval Mintz /* Unmask deasserted attentions in IGU */ 21381a635e48SYuval Mintz aeu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); 2139cc875c2eSYuval Mintz aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE); 2140cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask); 2141cc875c2eSYuval Mintz 2142cc875c2eSYuval Mintz /* Clear deassertion from inner state */ 2143cc875c2eSYuval Mintz sb_attn_sw->known_attn &= ~deasserted_bits; 2144cc875c2eSYuval Mintz 21450d956e8aSYuval Mintz return rc; 2146cc875c2eSYuval Mintz } 2147cc875c2eSYuval Mintz 2148cc875c2eSYuval Mintz static int qed_int_attentions(struct qed_hwfn *p_hwfn) 2149cc875c2eSYuval Mintz { 2150cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn; 2151cc875c2eSYuval Mintz struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn; 2152cc875c2eSYuval Mintz u32 attn_bits = 0, attn_acks = 0; 2153cc875c2eSYuval Mintz u16 asserted_bits, deasserted_bits; 2154cc875c2eSYuval Mintz __le16 index; 2155cc875c2eSYuval Mintz int rc = 0; 2156cc875c2eSYuval Mintz 2157cc875c2eSYuval Mintz /* Read current attention bits/acks - safeguard against attentions 2158cc875c2eSYuval Mintz * by guaranting work on a synchronized timeframe 2159cc875c2eSYuval Mintz */ 2160cc875c2eSYuval Mintz do { 2161cc875c2eSYuval Mintz index = p_sb_attn->sb_index; 2162cc875c2eSYuval Mintz attn_bits = le32_to_cpu(p_sb_attn->atten_bits); 2163cc875c2eSYuval Mintz attn_acks = le32_to_cpu(p_sb_attn->atten_ack); 2164cc875c2eSYuval Mintz } while (index != p_sb_attn->sb_index); 2165cc875c2eSYuval Mintz p_sb_attn->sb_index = index; 2166cc875c2eSYuval Mintz 2167cc875c2eSYuval Mintz /* Attention / Deassertion are meaningful (and in correct state) 2168cc875c2eSYuval Mintz * only when they differ and consistent with known state - deassertion 2169cc875c2eSYuval Mintz * when previous attention & current ack, and assertion when current 2170cc875c2eSYuval Mintz * attention with no previous attention 2171cc875c2eSYuval Mintz */ 2172cc875c2eSYuval Mintz asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) & 2173cc875c2eSYuval Mintz ~p_sb_attn_sw->known_attn; 2174cc875c2eSYuval Mintz deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) & 2175cc875c2eSYuval Mintz p_sb_attn_sw->known_attn; 2176cc875c2eSYuval Mintz 2177cc875c2eSYuval Mintz if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100)) { 2178cc875c2eSYuval Mintz DP_INFO(p_hwfn, 2179cc875c2eSYuval Mintz "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n", 2180cc875c2eSYuval Mintz index, attn_bits, attn_acks, asserted_bits, 2181cc875c2eSYuval Mintz deasserted_bits, p_sb_attn_sw->known_attn); 2182cc875c2eSYuval Mintz } else if (asserted_bits == 0x100) { 21831a635e48SYuval Mintz DP_INFO(p_hwfn, "MFW indication via attention\n"); 2184cc875c2eSYuval Mintz } else { 2185cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2186cc875c2eSYuval Mintz "MFW indication [deassertion]\n"); 2187cc875c2eSYuval Mintz } 2188cc875c2eSYuval Mintz 2189cc875c2eSYuval Mintz if (asserted_bits) { 2190cc875c2eSYuval Mintz rc = qed_int_assertion(p_hwfn, asserted_bits); 2191cc875c2eSYuval Mintz if (rc) 2192cc875c2eSYuval Mintz return rc; 2193cc875c2eSYuval Mintz } 2194cc875c2eSYuval Mintz 21951a635e48SYuval Mintz if (deasserted_bits) 2196cc875c2eSYuval Mintz rc = qed_int_deassertion(p_hwfn, deasserted_bits); 2197cc875c2eSYuval Mintz 2198cc875c2eSYuval Mintz return rc; 2199cc875c2eSYuval Mintz } 2200cc875c2eSYuval Mintz 2201cc875c2eSYuval Mintz static void qed_sb_ack_attn(struct qed_hwfn *p_hwfn, 22021a635e48SYuval Mintz void __iomem *igu_addr, u32 ack_cons) 2203cc875c2eSYuval Mintz { 2204cc875c2eSYuval Mintz struct igu_prod_cons_update igu_ack = { 0 }; 2205cc875c2eSYuval Mintz 2206cc875c2eSYuval Mintz igu_ack.sb_id_and_flags = 2207cc875c2eSYuval Mintz ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 2208cc875c2eSYuval Mintz (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 2209cc875c2eSYuval Mintz (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 2210cc875c2eSYuval Mintz (IGU_SEG_ACCESS_ATTN << 2211cc875c2eSYuval Mintz IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 2212cc875c2eSYuval Mintz 2213cc875c2eSYuval Mintz DIRECT_REG_WR(igu_addr, igu_ack.sb_id_and_flags); 2214cc875c2eSYuval Mintz 2215cc875c2eSYuval Mintz /* Both segments (interrupts & acks) are written to same place address; 2216cc875c2eSYuval Mintz * Need to guarantee all commands will be received (in-order) by HW. 2217cc875c2eSYuval Mintz */ 2218cc875c2eSYuval Mintz mmiowb(); 2219cc875c2eSYuval Mintz barrier(); 2220cc875c2eSYuval Mintz } 2221cc875c2eSYuval Mintz 2222fe56b9e6SYuval Mintz void qed_int_sp_dpc(unsigned long hwfn_cookie) 2223fe56b9e6SYuval Mintz { 2224fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = (struct qed_hwfn *)hwfn_cookie; 2225fe56b9e6SYuval Mintz struct qed_pi_info *pi_info = NULL; 2226cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn; 2227fe56b9e6SYuval Mintz struct qed_sb_info *sb_info; 2228fe56b9e6SYuval Mintz int arr_size; 2229fe56b9e6SYuval Mintz u16 rc = 0; 2230fe56b9e6SYuval Mintz 2231fe56b9e6SYuval Mintz if (!p_hwfn->p_sp_sb) { 2232fe56b9e6SYuval Mintz DP_ERR(p_hwfn->cdev, "DPC called - no p_sp_sb\n"); 2233fe56b9e6SYuval Mintz return; 2234fe56b9e6SYuval Mintz } 2235fe56b9e6SYuval Mintz 2236fe56b9e6SYuval Mintz sb_info = &p_hwfn->p_sp_sb->sb_info; 2237fe56b9e6SYuval Mintz arr_size = ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr); 2238fe56b9e6SYuval Mintz if (!sb_info) { 2239fe56b9e6SYuval Mintz DP_ERR(p_hwfn->cdev, 2240fe56b9e6SYuval Mintz "Status block is NULL - cannot ack interrupts\n"); 2241fe56b9e6SYuval Mintz return; 2242fe56b9e6SYuval Mintz } 2243fe56b9e6SYuval Mintz 2244cc875c2eSYuval Mintz if (!p_hwfn->p_sb_attn) { 2245cc875c2eSYuval Mintz DP_ERR(p_hwfn->cdev, "DPC called - no p_sb_attn"); 2246cc875c2eSYuval Mintz return; 2247cc875c2eSYuval Mintz } 2248cc875c2eSYuval Mintz sb_attn = p_hwfn->p_sb_attn; 2249cc875c2eSYuval Mintz 2250fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "DPC Called! (hwfn %p %d)\n", 2251fe56b9e6SYuval Mintz p_hwfn, p_hwfn->my_id); 2252fe56b9e6SYuval Mintz 2253fe56b9e6SYuval Mintz /* Disable ack for def status block. Required both for msix + 2254fe56b9e6SYuval Mintz * inta in non-mask mode, in inta does no harm. 2255fe56b9e6SYuval Mintz */ 2256fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_DISABLE, 0); 2257fe56b9e6SYuval Mintz 2258fe56b9e6SYuval Mintz /* Gather Interrupts/Attentions information */ 2259fe56b9e6SYuval Mintz if (!sb_info->sb_virt) { 22601a635e48SYuval Mintz DP_ERR(p_hwfn->cdev, 2261fe56b9e6SYuval Mintz "Interrupt Status block is NULL - cannot check for new interrupts!\n"); 2262fe56b9e6SYuval Mintz } else { 2263fe56b9e6SYuval Mintz u32 tmp_index = sb_info->sb_ack; 2264fe56b9e6SYuval Mintz 2265fe56b9e6SYuval Mintz rc = qed_sb_update_sb_idx(sb_info); 2266fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 2267fe56b9e6SYuval Mintz "Interrupt indices: 0x%08x --> 0x%08x\n", 2268fe56b9e6SYuval Mintz tmp_index, sb_info->sb_ack); 2269fe56b9e6SYuval Mintz } 2270fe56b9e6SYuval Mintz 2271cc875c2eSYuval Mintz if (!sb_attn || !sb_attn->sb_attn) { 22721a635e48SYuval Mintz DP_ERR(p_hwfn->cdev, 2273cc875c2eSYuval Mintz "Attentions Status block is NULL - cannot check for new attentions!\n"); 2274cc875c2eSYuval Mintz } else { 2275cc875c2eSYuval Mintz u16 tmp_index = sb_attn->index; 2276cc875c2eSYuval Mintz 2277cc875c2eSYuval Mintz rc |= qed_attn_update_idx(p_hwfn, sb_attn); 2278cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 2279cc875c2eSYuval Mintz "Attention indices: 0x%08x --> 0x%08x\n", 2280cc875c2eSYuval Mintz tmp_index, sb_attn->index); 2281cc875c2eSYuval Mintz } 2282cc875c2eSYuval Mintz 2283fe56b9e6SYuval Mintz /* Check if we expect interrupts at this time. if not just ack them */ 2284fe56b9e6SYuval Mintz if (!(rc & QED_SB_EVENT_MASK)) { 2285fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 2286fe56b9e6SYuval Mintz return; 2287fe56b9e6SYuval Mintz } 2288fe56b9e6SYuval Mintz 2289fe56b9e6SYuval Mintz /* Check the validity of the DPC ptt. If not ack interrupts and fail */ 2290fe56b9e6SYuval Mintz if (!p_hwfn->p_dpc_ptt) { 2291fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn->cdev, "Failed to allocate PTT\n"); 2292fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 2293fe56b9e6SYuval Mintz return; 2294fe56b9e6SYuval Mintz } 2295fe56b9e6SYuval Mintz 2296cc875c2eSYuval Mintz if (rc & QED_SB_ATT_IDX) 2297cc875c2eSYuval Mintz qed_int_attentions(p_hwfn); 2298cc875c2eSYuval Mintz 2299fe56b9e6SYuval Mintz if (rc & QED_SB_IDX) { 2300fe56b9e6SYuval Mintz int pi; 2301fe56b9e6SYuval Mintz 2302fe56b9e6SYuval Mintz /* Look for a free index */ 2303fe56b9e6SYuval Mintz for (pi = 0; pi < arr_size; pi++) { 2304fe56b9e6SYuval Mintz pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi]; 2305fe56b9e6SYuval Mintz if (pi_info->comp_cb) 2306fe56b9e6SYuval Mintz pi_info->comp_cb(p_hwfn, pi_info->cookie); 2307fe56b9e6SYuval Mintz } 2308fe56b9e6SYuval Mintz } 2309fe56b9e6SYuval Mintz 2310cc875c2eSYuval Mintz if (sb_attn && (rc & QED_SB_ATT_IDX)) 2311cc875c2eSYuval Mintz /* This should be done before the interrupts are enabled, 2312cc875c2eSYuval Mintz * since otherwise a new attention will be generated. 2313cc875c2eSYuval Mintz */ 2314cc875c2eSYuval Mintz qed_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index); 2315cc875c2eSYuval Mintz 2316fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 2317fe56b9e6SYuval Mintz } 2318fe56b9e6SYuval Mintz 2319cc875c2eSYuval Mintz static void qed_int_sb_attn_free(struct qed_hwfn *p_hwfn) 2320cc875c2eSYuval Mintz { 2321cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb = p_hwfn->p_sb_attn; 2322cc875c2eSYuval Mintz 23234ac801b7SYuval Mintz if (!p_sb) 23244ac801b7SYuval Mintz return; 23254ac801b7SYuval Mintz 2326cc875c2eSYuval Mintz if (p_sb->sb_attn) 23274ac801b7SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 2328cc875c2eSYuval Mintz SB_ATTN_ALIGNED_SIZE(p_hwfn), 23291a635e48SYuval Mintz p_sb->sb_attn, p_sb->sb_phys); 2330cc875c2eSYuval Mintz kfree(p_sb); 2331cc875c2eSYuval Mintz } 2332cc875c2eSYuval Mintz 2333cc875c2eSYuval Mintz static void qed_int_sb_attn_setup(struct qed_hwfn *p_hwfn, 2334cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 2335cc875c2eSYuval Mintz { 2336cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 2337cc875c2eSYuval Mintz 2338cc875c2eSYuval Mintz memset(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn)); 2339cc875c2eSYuval Mintz 2340cc875c2eSYuval Mintz sb_info->index = 0; 2341cc875c2eSYuval Mintz sb_info->known_attn = 0; 2342cc875c2eSYuval Mintz 2343cc875c2eSYuval Mintz /* Configure Attention Status Block in IGU */ 2344cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L, 2345cc875c2eSYuval Mintz lower_32_bits(p_hwfn->p_sb_attn->sb_phys)); 2346cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H, 2347cc875c2eSYuval Mintz upper_32_bits(p_hwfn->p_sb_attn->sb_phys)); 2348cc875c2eSYuval Mintz } 2349cc875c2eSYuval Mintz 2350cc875c2eSYuval Mintz static void qed_int_sb_attn_init(struct qed_hwfn *p_hwfn, 2351cc875c2eSYuval Mintz struct qed_ptt *p_ptt, 23521a635e48SYuval Mintz void *sb_virt_addr, dma_addr_t sb_phy_addr) 2353cc875c2eSYuval Mintz { 2354cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 23550d956e8aSYuval Mintz int i, j, k; 2356cc875c2eSYuval Mintz 2357cc875c2eSYuval Mintz sb_info->sb_attn = sb_virt_addr; 2358cc875c2eSYuval Mintz sb_info->sb_phys = sb_phy_addr; 2359cc875c2eSYuval Mintz 23600d956e8aSYuval Mintz /* Set the pointer to the AEU descriptors */ 23610d956e8aSYuval Mintz sb_info->p_aeu_desc = aeu_descs; 23620d956e8aSYuval Mintz 23630d956e8aSYuval Mintz /* Calculate Parity Masks */ 23640d956e8aSYuval Mintz memset(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS); 23650d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 23660d956e8aSYuval Mintz /* j is array index, k is bit index */ 23670d956e8aSYuval Mintz for (j = 0, k = 0; k < 32; j++) { 23680d956e8aSYuval Mintz unsigned int flags = aeu_descs[i].bits[j].flags; 23690d956e8aSYuval Mintz 23700d956e8aSYuval Mintz if (flags & ATTENTION_PARITY) 23710d956e8aSYuval Mintz sb_info->parity_mask[i] |= 1 << k; 23720d956e8aSYuval Mintz 23730d956e8aSYuval Mintz k += ATTENTION_LENGTH(flags); 23740d956e8aSYuval Mintz } 23750d956e8aSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 23760d956e8aSYuval Mintz "Attn Mask [Reg %d]: 0x%08x\n", 23770d956e8aSYuval Mintz i, sb_info->parity_mask[i]); 23780d956e8aSYuval Mintz } 23790d956e8aSYuval Mintz 2380cc875c2eSYuval Mintz /* Set the address of cleanup for the mcp attention */ 2381cc875c2eSYuval Mintz sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) + 2382cc875c2eSYuval Mintz MISC_REG_AEU_GENERAL_ATTN_0; 2383cc875c2eSYuval Mintz 2384cc875c2eSYuval Mintz qed_int_sb_attn_setup(p_hwfn, p_ptt); 2385cc875c2eSYuval Mintz } 2386cc875c2eSYuval Mintz 2387cc875c2eSYuval Mintz static int qed_int_sb_attn_alloc(struct qed_hwfn *p_hwfn, 2388cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 2389cc875c2eSYuval Mintz { 2390cc875c2eSYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 2391cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb; 2392cc875c2eSYuval Mintz dma_addr_t p_phys = 0; 23931a635e48SYuval Mintz void *p_virt; 2394cc875c2eSYuval Mintz 2395cc875c2eSYuval Mintz /* SB struct */ 239660fffb3bSYuval Mintz p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 23972591c280SJoe Perches if (!p_sb) 2398cc875c2eSYuval Mintz return -ENOMEM; 2399cc875c2eSYuval Mintz 2400cc875c2eSYuval Mintz /* SB ring */ 2401cc875c2eSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 2402cc875c2eSYuval Mintz SB_ATTN_ALIGNED_SIZE(p_hwfn), 2403cc875c2eSYuval Mintz &p_phys, GFP_KERNEL); 2404cc875c2eSYuval Mintz 2405cc875c2eSYuval Mintz if (!p_virt) { 2406cc875c2eSYuval Mintz kfree(p_sb); 2407cc875c2eSYuval Mintz return -ENOMEM; 2408cc875c2eSYuval Mintz } 2409cc875c2eSYuval Mintz 2410cc875c2eSYuval Mintz /* Attention setup */ 2411cc875c2eSYuval Mintz p_hwfn->p_sb_attn = p_sb; 2412cc875c2eSYuval Mintz qed_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys); 2413cc875c2eSYuval Mintz 2414cc875c2eSYuval Mintz return 0; 2415cc875c2eSYuval Mintz } 2416cc875c2eSYuval Mintz 2417fe56b9e6SYuval Mintz /* coalescing timeout = timeset << (timer_res + 1) */ 2418fe56b9e6SYuval Mintz #define QED_CAU_DEF_RX_USECS 24 2419fe56b9e6SYuval Mintz #define QED_CAU_DEF_TX_USECS 48 2420fe56b9e6SYuval Mintz 2421fe56b9e6SYuval Mintz void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn, 2422fe56b9e6SYuval Mintz struct cau_sb_entry *p_sb_entry, 24231a635e48SYuval Mintz u8 pf_id, u16 vf_number, u8 vf_valid) 2424fe56b9e6SYuval Mintz { 24254ac801b7SYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 2426fe56b9e6SYuval Mintz u32 cau_state; 2427722003acSSudarsana Reddy Kalluru u8 timer_res; 2428fe56b9e6SYuval Mintz 2429fe56b9e6SYuval Mintz memset(p_sb_entry, 0, sizeof(*p_sb_entry)); 2430fe56b9e6SYuval Mintz 2431fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id); 2432fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number); 2433fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid); 2434fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F); 2435fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F); 2436fe56b9e6SYuval Mintz 2437fe56b9e6SYuval Mintz cau_state = CAU_HC_DISABLE_STATE; 2438fe56b9e6SYuval Mintz 24394ac801b7SYuval Mintz if (cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 2440fe56b9e6SYuval Mintz cau_state = CAU_HC_ENABLE_STATE; 24414ac801b7SYuval Mintz if (!cdev->rx_coalesce_usecs) 24424ac801b7SYuval Mintz cdev->rx_coalesce_usecs = QED_CAU_DEF_RX_USECS; 24434ac801b7SYuval Mintz if (!cdev->tx_coalesce_usecs) 24444ac801b7SYuval Mintz cdev->tx_coalesce_usecs = QED_CAU_DEF_TX_USECS; 2445fe56b9e6SYuval Mintz } 2446fe56b9e6SYuval Mintz 2447722003acSSudarsana Reddy Kalluru /* Coalesce = (timeset << timer-res), timeset is 7bit wide */ 2448722003acSSudarsana Reddy Kalluru if (cdev->rx_coalesce_usecs <= 0x7F) 2449722003acSSudarsana Reddy Kalluru timer_res = 0; 2450722003acSSudarsana Reddy Kalluru else if (cdev->rx_coalesce_usecs <= 0xFF) 2451722003acSSudarsana Reddy Kalluru timer_res = 1; 2452722003acSSudarsana Reddy Kalluru else 2453722003acSSudarsana Reddy Kalluru timer_res = 2; 2454722003acSSudarsana Reddy Kalluru SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 2455722003acSSudarsana Reddy Kalluru 2456722003acSSudarsana Reddy Kalluru if (cdev->tx_coalesce_usecs <= 0x7F) 2457722003acSSudarsana Reddy Kalluru timer_res = 0; 2458722003acSSudarsana Reddy Kalluru else if (cdev->tx_coalesce_usecs <= 0xFF) 2459722003acSSudarsana Reddy Kalluru timer_res = 1; 2460722003acSSudarsana Reddy Kalluru else 2461722003acSSudarsana Reddy Kalluru timer_res = 2; 2462722003acSSudarsana Reddy Kalluru SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 2463722003acSSudarsana Reddy Kalluru 2464fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state); 2465fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state); 2466fe56b9e6SYuval Mintz } 2467fe56b9e6SYuval Mintz 2468fe56b9e6SYuval Mintz void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn, 2469fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2470fe56b9e6SYuval Mintz dma_addr_t sb_phys, 24711a635e48SYuval Mintz u16 igu_sb_id, u16 vf_number, u8 vf_valid) 2472fe56b9e6SYuval Mintz { 2473fe56b9e6SYuval Mintz struct cau_sb_entry sb_entry; 2474fe56b9e6SYuval Mintz 2475fe56b9e6SYuval Mintz qed_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id, 2476fe56b9e6SYuval Mintz vf_number, vf_valid); 2477fe56b9e6SYuval Mintz 2478fe56b9e6SYuval Mintz if (p_hwfn->hw_init_done) { 24790a0c5d3bSYuval Mintz /* Wide-bus, initialize via DMAE */ 24800a0c5d3bSYuval Mintz u64 phys_addr = (u64)sb_phys; 2481fe56b9e6SYuval Mintz 24820a0c5d3bSYuval Mintz qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&phys_addr, 24830a0c5d3bSYuval Mintz CAU_REG_SB_ADDR_MEMORY + 24840a0c5d3bSYuval Mintz igu_sb_id * sizeof(u64), 2, 0); 24850a0c5d3bSYuval Mintz qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&sb_entry, 24860a0c5d3bSYuval Mintz CAU_REG_SB_VAR_MEMORY + 24870a0c5d3bSYuval Mintz igu_sb_id * sizeof(u64), 2, 0); 2488fe56b9e6SYuval Mintz } else { 2489fe56b9e6SYuval Mintz /* Initialize Status Block Address */ 2490fe56b9e6SYuval Mintz STORE_RT_REG_AGG(p_hwfn, 2491fe56b9e6SYuval Mintz CAU_REG_SB_ADDR_MEMORY_RT_OFFSET + 2492fe56b9e6SYuval Mintz igu_sb_id * 2, 2493fe56b9e6SYuval Mintz sb_phys); 2494fe56b9e6SYuval Mintz 2495fe56b9e6SYuval Mintz STORE_RT_REG_AGG(p_hwfn, 2496fe56b9e6SYuval Mintz CAU_REG_SB_VAR_MEMORY_RT_OFFSET + 2497fe56b9e6SYuval Mintz igu_sb_id * 2, 2498fe56b9e6SYuval Mintz sb_entry); 2499fe56b9e6SYuval Mintz } 2500fe56b9e6SYuval Mintz 2501fe56b9e6SYuval Mintz /* Configure pi coalescing if set */ 2502fe56b9e6SYuval Mintz if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 2503b5a9ee7cSAriel Elior u8 num_tc = p_hwfn->hw_info.num_hw_tc; 2504722003acSSudarsana Reddy Kalluru u8 timeset, timer_res; 2505b5a9ee7cSAriel Elior u8 i; 2506fe56b9e6SYuval Mintz 2507722003acSSudarsana Reddy Kalluru /* timeset = (coalesce >> timer-res), timeset is 7bit wide */ 2508722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->rx_coalesce_usecs <= 0x7F) 2509722003acSSudarsana Reddy Kalluru timer_res = 0; 2510722003acSSudarsana Reddy Kalluru else if (p_hwfn->cdev->rx_coalesce_usecs <= 0xFF) 2511722003acSSudarsana Reddy Kalluru timer_res = 1; 2512722003acSSudarsana Reddy Kalluru else 2513722003acSSudarsana Reddy Kalluru timer_res = 2; 2514722003acSSudarsana Reddy Kalluru timeset = (u8)(p_hwfn->cdev->rx_coalesce_usecs >> timer_res); 2515fe56b9e6SYuval Mintz qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI, 25161a635e48SYuval Mintz QED_COAL_RX_STATE_MACHINE, timeset); 2517fe56b9e6SYuval Mintz 2518722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->tx_coalesce_usecs <= 0x7F) 2519722003acSSudarsana Reddy Kalluru timer_res = 0; 2520722003acSSudarsana Reddy Kalluru else if (p_hwfn->cdev->tx_coalesce_usecs <= 0xFF) 2521722003acSSudarsana Reddy Kalluru timer_res = 1; 2522722003acSSudarsana Reddy Kalluru else 2523722003acSSudarsana Reddy Kalluru timer_res = 2; 2524722003acSSudarsana Reddy Kalluru timeset = (u8)(p_hwfn->cdev->tx_coalesce_usecs >> timer_res); 2525fe56b9e6SYuval Mintz for (i = 0; i < num_tc; i++) { 2526fe56b9e6SYuval Mintz qed_int_cau_conf_pi(p_hwfn, p_ptt, 2527fe56b9e6SYuval Mintz igu_sb_id, TX_PI(i), 2528fe56b9e6SYuval Mintz QED_COAL_TX_STATE_MACHINE, 2529fe56b9e6SYuval Mintz timeset); 2530fe56b9e6SYuval Mintz } 2531fe56b9e6SYuval Mintz } 2532fe56b9e6SYuval Mintz } 2533fe56b9e6SYuval Mintz 2534fe56b9e6SYuval Mintz void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn, 2535fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2536fe56b9e6SYuval Mintz u16 igu_sb_id, 2537fe56b9e6SYuval Mintz u32 pi_index, 2538fe56b9e6SYuval Mintz enum qed_coalescing_fsm coalescing_fsm, 2539fe56b9e6SYuval Mintz u8 timeset) 2540fe56b9e6SYuval Mintz { 2541fe56b9e6SYuval Mintz struct cau_pi_entry pi_entry; 25421a635e48SYuval Mintz u32 sb_offset, pi_offset; 2543fe56b9e6SYuval Mintz 25441408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 25451408cc1fSYuval Mintz return; 25461408cc1fSYuval Mintz 2547fe56b9e6SYuval Mintz sb_offset = igu_sb_id * PIS_PER_SB; 2548fe56b9e6SYuval Mintz memset(&pi_entry, 0, sizeof(struct cau_pi_entry)); 2549fe56b9e6SYuval Mintz 2550fe56b9e6SYuval Mintz SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset); 2551fe56b9e6SYuval Mintz if (coalescing_fsm == QED_COAL_RX_STATE_MACHINE) 2552fe56b9e6SYuval Mintz SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0); 2553fe56b9e6SYuval Mintz else 2554fe56b9e6SYuval Mintz SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1); 2555fe56b9e6SYuval Mintz 2556fe56b9e6SYuval Mintz pi_offset = sb_offset + pi_index; 2557fe56b9e6SYuval Mintz if (p_hwfn->hw_init_done) { 2558fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 2559fe56b9e6SYuval Mintz CAU_REG_PI_MEMORY + pi_offset * sizeof(u32), 2560fe56b9e6SYuval Mintz *((u32 *)&(pi_entry))); 2561fe56b9e6SYuval Mintz } else { 2562fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, 2563fe56b9e6SYuval Mintz CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset, 2564fe56b9e6SYuval Mintz *((u32 *)&(pi_entry))); 2565fe56b9e6SYuval Mintz } 2566fe56b9e6SYuval Mintz } 2567fe56b9e6SYuval Mintz 2568fe56b9e6SYuval Mintz void qed_int_sb_setup(struct qed_hwfn *p_hwfn, 25691a635e48SYuval Mintz struct qed_ptt *p_ptt, struct qed_sb_info *sb_info) 2570fe56b9e6SYuval Mintz { 2571fe56b9e6SYuval Mintz /* zero status block and ack counter */ 2572fe56b9e6SYuval Mintz sb_info->sb_ack = 0; 2573fe56b9e6SYuval Mintz memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 2574fe56b9e6SYuval Mintz 25751408cc1fSYuval Mintz if (IS_PF(p_hwfn->cdev)) 2576fe56b9e6SYuval Mintz qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys, 2577fe56b9e6SYuval Mintz sb_info->igu_sb_id, 0, 0); 2578fe56b9e6SYuval Mintz } 2579fe56b9e6SYuval Mintz 2580fe56b9e6SYuval Mintz /** 2581fe56b9e6SYuval Mintz * @brief qed_get_igu_sb_id - given a sw sb_id return the 2582fe56b9e6SYuval Mintz * igu_sb_id 2583fe56b9e6SYuval Mintz * 2584fe56b9e6SYuval Mintz * @param p_hwfn 2585fe56b9e6SYuval Mintz * @param sb_id 2586fe56b9e6SYuval Mintz * 2587fe56b9e6SYuval Mintz * @return u16 2588fe56b9e6SYuval Mintz */ 25891a635e48SYuval Mintz static u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id) 2590fe56b9e6SYuval Mintz { 2591fe56b9e6SYuval Mintz u16 igu_sb_id; 2592fe56b9e6SYuval Mintz 2593fe56b9e6SYuval Mintz /* Assuming continuous set of IGU SBs dedicated for given PF */ 2594fe56b9e6SYuval Mintz if (sb_id == QED_SP_SB_ID) 2595fe56b9e6SYuval Mintz igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id; 25961408cc1fSYuval Mintz else if (IS_PF(p_hwfn->cdev)) 2597fe56b9e6SYuval Mintz igu_sb_id = sb_id + p_hwfn->hw_info.p_igu_info->igu_base_sb; 25981408cc1fSYuval Mintz else 25991408cc1fSYuval Mintz igu_sb_id = qed_vf_get_igu_sb_id(p_hwfn, sb_id); 2600fe56b9e6SYuval Mintz 2601525ef5c0SYuval Mintz if (sb_id == QED_SP_SB_ID) 2602525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2603525ef5c0SYuval Mintz "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id); 2604525ef5c0SYuval Mintz else 2605525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2606525ef5c0SYuval Mintz "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id); 2607fe56b9e6SYuval Mintz 2608fe56b9e6SYuval Mintz return igu_sb_id; 2609fe56b9e6SYuval Mintz } 2610fe56b9e6SYuval Mintz 2611fe56b9e6SYuval Mintz int qed_int_sb_init(struct qed_hwfn *p_hwfn, 2612fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2613fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 26141a635e48SYuval Mintz void *sb_virt_addr, dma_addr_t sb_phy_addr, u16 sb_id) 2615fe56b9e6SYuval Mintz { 2616fe56b9e6SYuval Mintz sb_info->sb_virt = sb_virt_addr; 2617fe56b9e6SYuval Mintz sb_info->sb_phys = sb_phy_addr; 2618fe56b9e6SYuval Mintz 2619fe56b9e6SYuval Mintz sb_info->igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id); 2620fe56b9e6SYuval Mintz 2621fe56b9e6SYuval Mintz if (sb_id != QED_SP_SB_ID) { 2622fe56b9e6SYuval Mintz p_hwfn->sbs_info[sb_id] = sb_info; 2623fe56b9e6SYuval Mintz p_hwfn->num_sbs++; 2624fe56b9e6SYuval Mintz } 2625fe56b9e6SYuval Mintz 2626fe56b9e6SYuval Mintz sb_info->cdev = p_hwfn->cdev; 2627fe56b9e6SYuval Mintz 2628fe56b9e6SYuval Mintz /* The igu address will hold the absolute address that needs to be 2629fe56b9e6SYuval Mintz * written to for a specific status block 2630fe56b9e6SYuval Mintz */ 26311408cc1fSYuval Mintz if (IS_PF(p_hwfn->cdev)) { 2632fe56b9e6SYuval Mintz sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 2633fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 2634fe56b9e6SYuval Mintz (sb_info->igu_sb_id << 3); 26351408cc1fSYuval Mintz } else { 26361408cc1fSYuval Mintz sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 26371408cc1fSYuval Mintz PXP_VF_BAR0_START_IGU + 26381408cc1fSYuval Mintz ((IGU_CMD_INT_ACK_BASE + 26391408cc1fSYuval Mintz sb_info->igu_sb_id) << 3); 26401408cc1fSYuval Mintz } 2641fe56b9e6SYuval Mintz 2642fe56b9e6SYuval Mintz sb_info->flags |= QED_SB_INFO_INIT; 2643fe56b9e6SYuval Mintz 2644fe56b9e6SYuval Mintz qed_int_sb_setup(p_hwfn, p_ptt, sb_info); 2645fe56b9e6SYuval Mintz 2646fe56b9e6SYuval Mintz return 0; 2647fe56b9e6SYuval Mintz } 2648fe56b9e6SYuval Mintz 2649fe56b9e6SYuval Mintz int qed_int_sb_release(struct qed_hwfn *p_hwfn, 26501a635e48SYuval Mintz struct qed_sb_info *sb_info, u16 sb_id) 2651fe56b9e6SYuval Mintz { 2652fe56b9e6SYuval Mintz if (sb_id == QED_SP_SB_ID) { 2653fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Do Not free sp sb using this function"); 2654fe56b9e6SYuval Mintz return -EINVAL; 2655fe56b9e6SYuval Mintz } 2656fe56b9e6SYuval Mintz 2657fe56b9e6SYuval Mintz /* zero status block and ack counter */ 2658fe56b9e6SYuval Mintz sb_info->sb_ack = 0; 2659fe56b9e6SYuval Mintz memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 2660fe56b9e6SYuval Mintz 26614ac801b7SYuval Mintz if (p_hwfn->sbs_info[sb_id] != NULL) { 2662fe56b9e6SYuval Mintz p_hwfn->sbs_info[sb_id] = NULL; 2663fe56b9e6SYuval Mintz p_hwfn->num_sbs--; 26644ac801b7SYuval Mintz } 2665fe56b9e6SYuval Mintz 2666fe56b9e6SYuval Mintz return 0; 2667fe56b9e6SYuval Mintz } 2668fe56b9e6SYuval Mintz 2669fe56b9e6SYuval Mintz static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn) 2670fe56b9e6SYuval Mintz { 2671fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb; 2672fe56b9e6SYuval Mintz 26734ac801b7SYuval Mintz if (!p_sb) 26744ac801b7SYuval Mintz return; 26754ac801b7SYuval Mintz 2676fe56b9e6SYuval Mintz if (p_sb->sb_info.sb_virt) 2677fe56b9e6SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 2678fe56b9e6SYuval Mintz SB_ALIGNED_SIZE(p_hwfn), 2679fe56b9e6SYuval Mintz p_sb->sb_info.sb_virt, 2680fe56b9e6SYuval Mintz p_sb->sb_info.sb_phys); 2681fe56b9e6SYuval Mintz kfree(p_sb); 2682fe56b9e6SYuval Mintz } 2683fe56b9e6SYuval Mintz 26841a635e48SYuval Mintz static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2685fe56b9e6SYuval Mintz { 2686fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sb; 2687fe56b9e6SYuval Mintz dma_addr_t p_phys = 0; 2688fe56b9e6SYuval Mintz void *p_virt; 2689fe56b9e6SYuval Mintz 2690fe56b9e6SYuval Mintz /* SB struct */ 269160fffb3bSYuval Mintz p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 26922591c280SJoe Perches if (!p_sb) 2693fe56b9e6SYuval Mintz return -ENOMEM; 2694fe56b9e6SYuval Mintz 2695fe56b9e6SYuval Mintz /* SB ring */ 2696fe56b9e6SYuval Mintz p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 2697fe56b9e6SYuval Mintz SB_ALIGNED_SIZE(p_hwfn), 2698fe56b9e6SYuval Mintz &p_phys, GFP_KERNEL); 2699fe56b9e6SYuval Mintz if (!p_virt) { 2700fe56b9e6SYuval Mintz kfree(p_sb); 2701fe56b9e6SYuval Mintz return -ENOMEM; 2702fe56b9e6SYuval Mintz } 2703fe56b9e6SYuval Mintz 2704fe56b9e6SYuval Mintz /* Status Block setup */ 2705fe56b9e6SYuval Mintz p_hwfn->p_sp_sb = p_sb; 2706fe56b9e6SYuval Mintz qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt, 2707fe56b9e6SYuval Mintz p_phys, QED_SP_SB_ID); 2708fe56b9e6SYuval Mintz 2709fe56b9e6SYuval Mintz memset(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr)); 2710fe56b9e6SYuval Mintz 2711fe56b9e6SYuval Mintz return 0; 2712fe56b9e6SYuval Mintz } 2713fe56b9e6SYuval Mintz 2714fe56b9e6SYuval Mintz int qed_int_register_cb(struct qed_hwfn *p_hwfn, 2715fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb, 27161a635e48SYuval Mintz void *cookie, u8 *sb_idx, __le16 **p_fw_cons) 2717fe56b9e6SYuval Mintz { 2718fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 27194ac801b7SYuval Mintz int rc = -ENOMEM; 2720fe56b9e6SYuval Mintz u8 pi; 2721fe56b9e6SYuval Mintz 2722fe56b9e6SYuval Mintz /* Look for a free index */ 2723fe56b9e6SYuval Mintz for (pi = 0; pi < ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) { 27244ac801b7SYuval Mintz if (p_sp_sb->pi_info_arr[pi].comp_cb) 27254ac801b7SYuval Mintz continue; 27264ac801b7SYuval Mintz 2727fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb; 2728fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].cookie = cookie; 2729fe56b9e6SYuval Mintz *sb_idx = pi; 2730fe56b9e6SYuval Mintz *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi]; 27314ac801b7SYuval Mintz rc = 0; 2732fe56b9e6SYuval Mintz break; 2733fe56b9e6SYuval Mintz } 2734fe56b9e6SYuval Mintz 27354ac801b7SYuval Mintz return rc; 2736fe56b9e6SYuval Mintz } 2737fe56b9e6SYuval Mintz 2738fe56b9e6SYuval Mintz int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi) 2739fe56b9e6SYuval Mintz { 2740fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 2741fe56b9e6SYuval Mintz 27424ac801b7SYuval Mintz if (p_sp_sb->pi_info_arr[pi].comp_cb == NULL) 27434ac801b7SYuval Mintz return -ENOMEM; 27444ac801b7SYuval Mintz 2745fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].comp_cb = NULL; 2746fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].cookie = NULL; 2747fe56b9e6SYuval Mintz 27484ac801b7SYuval Mintz return 0; 2749fe56b9e6SYuval Mintz } 2750fe56b9e6SYuval Mintz 2751fe56b9e6SYuval Mintz u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn) 2752fe56b9e6SYuval Mintz { 2753fe56b9e6SYuval Mintz return p_hwfn->p_sp_sb->sb_info.igu_sb_id; 2754fe56b9e6SYuval Mintz } 2755fe56b9e6SYuval Mintz 2756fe56b9e6SYuval Mintz void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn, 27571a635e48SYuval Mintz struct qed_ptt *p_ptt, enum qed_int_mode int_mode) 2758fe56b9e6SYuval Mintz { 2759cc875c2eSYuval Mintz u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN; 2760fe56b9e6SYuval Mintz 2761fe56b9e6SYuval Mintz p_hwfn->cdev->int_mode = int_mode; 2762fe56b9e6SYuval Mintz switch (p_hwfn->cdev->int_mode) { 2763fe56b9e6SYuval Mintz case QED_INT_MODE_INTA: 2764fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN; 2765fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 2766fe56b9e6SYuval Mintz break; 2767fe56b9e6SYuval Mintz 2768fe56b9e6SYuval Mintz case QED_INT_MODE_MSI: 2769fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 2770fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 2771fe56b9e6SYuval Mintz break; 2772fe56b9e6SYuval Mintz 2773fe56b9e6SYuval Mintz case QED_INT_MODE_MSIX: 2774fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 2775fe56b9e6SYuval Mintz break; 2776fe56b9e6SYuval Mintz case QED_INT_MODE_POLL: 2777fe56b9e6SYuval Mintz break; 2778fe56b9e6SYuval Mintz } 2779fe56b9e6SYuval Mintz 2780fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf); 2781fe56b9e6SYuval Mintz } 2782fe56b9e6SYuval Mintz 27838f16bc97SSudarsana Kalluru int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2784fe56b9e6SYuval Mintz enum qed_int_mode int_mode) 2785fe56b9e6SYuval Mintz { 2786fea24857SColin Ian King int rc = 0; 2787fe56b9e6SYuval Mintz 27880d956e8aSYuval Mintz /* Configure AEU signal change to produce attentions */ 27890d956e8aSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0); 2790cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff); 2791cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff); 27920d956e8aSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff); 2793cc875c2eSYuval Mintz 2794fe56b9e6SYuval Mintz /* Flush the writes to IGU */ 2795fe56b9e6SYuval Mintz mmiowb(); 2796cc875c2eSYuval Mintz 2797cc875c2eSYuval Mintz /* Unmask AEU signals toward IGU */ 2798cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff); 27998f16bc97SSudarsana Kalluru if ((int_mode != QED_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) { 28008f16bc97SSudarsana Kalluru rc = qed_slowpath_irq_req(p_hwfn); 28011a635e48SYuval Mintz if (rc) { 28028f16bc97SSudarsana Kalluru DP_NOTICE(p_hwfn, "Slowpath IRQ request failed\n"); 28038f16bc97SSudarsana Kalluru return -EINVAL; 28048f16bc97SSudarsana Kalluru } 28058f16bc97SSudarsana Kalluru p_hwfn->b_int_requested = true; 28068f16bc97SSudarsana Kalluru } 28078f16bc97SSudarsana Kalluru /* Enable interrupt Generation */ 28088f16bc97SSudarsana Kalluru qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode); 28098f16bc97SSudarsana Kalluru p_hwfn->b_int_enabled = 1; 28108f16bc97SSudarsana Kalluru 28118f16bc97SSudarsana Kalluru return rc; 2812fe56b9e6SYuval Mintz } 2813fe56b9e6SYuval Mintz 28141a635e48SYuval Mintz void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2815fe56b9e6SYuval Mintz { 2816fe56b9e6SYuval Mintz p_hwfn->b_int_enabled = 0; 2817fe56b9e6SYuval Mintz 28181408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 28191408cc1fSYuval Mintz return; 28201408cc1fSYuval Mintz 2821fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0); 2822fe56b9e6SYuval Mintz } 2823fe56b9e6SYuval Mintz 2824fe56b9e6SYuval Mintz #define IGU_CLEANUP_SLEEP_LENGTH (1000) 2825b2b897ebSYuval Mintz static void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn, 2826fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2827b2b897ebSYuval Mintz u32 sb_id, bool cleanup_set, u16 opaque_fid) 2828fe56b9e6SYuval Mintz { 2829b2b897ebSYuval Mintz u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0; 2830fe56b9e6SYuval Mintz u32 pxp_addr = IGU_CMD_INT_ACK_BASE + sb_id; 2831fe56b9e6SYuval Mintz u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH; 2832fe56b9e6SYuval Mintz 2833fe56b9e6SYuval Mintz /* Set the data field */ 2834fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0); 2835fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, 0); 2836fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET); 2837fe56b9e6SYuval Mintz 2838fe56b9e6SYuval Mintz /* Set the control register */ 2839fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr); 2840fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid); 2841fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR); 2842fe56b9e6SYuval Mintz 2843fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data); 2844fe56b9e6SYuval Mintz 2845fe56b9e6SYuval Mintz barrier(); 2846fe56b9e6SYuval Mintz 2847fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl); 2848fe56b9e6SYuval Mintz 2849fe56b9e6SYuval Mintz /* Flush the write to IGU */ 2850fe56b9e6SYuval Mintz mmiowb(); 2851fe56b9e6SYuval Mintz 2852fe56b9e6SYuval Mintz /* calculate where to read the status bit from */ 2853fe56b9e6SYuval Mintz sb_bit = 1 << (sb_id % 32); 2854fe56b9e6SYuval Mintz sb_bit_addr = sb_id / 32 * sizeof(u32); 2855fe56b9e6SYuval Mintz 2856fe56b9e6SYuval Mintz sb_bit_addr += IGU_REG_CLEANUP_STATUS_0; 2857fe56b9e6SYuval Mintz 2858fe56b9e6SYuval Mintz /* Now wait for the command to complete */ 2859fe56b9e6SYuval Mintz do { 2860fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, sb_bit_addr); 2861fe56b9e6SYuval Mintz 2862fe56b9e6SYuval Mintz if ((val & sb_bit) == (cleanup_set ? sb_bit : 0)) 2863fe56b9e6SYuval Mintz break; 2864fe56b9e6SYuval Mintz 2865fe56b9e6SYuval Mintz usleep_range(5000, 10000); 2866fe56b9e6SYuval Mintz } while (--sleep_cnt); 2867fe56b9e6SYuval Mintz 2868fe56b9e6SYuval Mintz if (!sleep_cnt) 2869fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 2870fe56b9e6SYuval Mintz "Timeout waiting for clear status 0x%08x [for sb %d]\n", 2871fe56b9e6SYuval Mintz val, sb_id); 2872fe56b9e6SYuval Mintz } 2873fe56b9e6SYuval Mintz 2874fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn, 2875fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2876b2b897ebSYuval Mintz u32 sb_id, u16 opaque, bool b_set) 2877fe56b9e6SYuval Mintz { 2878b2b897ebSYuval Mintz int pi, i; 2879fe56b9e6SYuval Mintz 2880fe56b9e6SYuval Mintz /* Set */ 2881fe56b9e6SYuval Mintz if (b_set) 2882fe56b9e6SYuval Mintz qed_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 1, opaque); 2883fe56b9e6SYuval Mintz 2884fe56b9e6SYuval Mintz /* Clear */ 2885fe56b9e6SYuval Mintz qed_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 0, opaque); 2886fe56b9e6SYuval Mintz 2887b2b897ebSYuval Mintz /* Wait for the IGU SB to cleanup */ 2888b2b897ebSYuval Mintz for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) { 2889b2b897ebSYuval Mintz u32 val; 2890b2b897ebSYuval Mintz 2891b2b897ebSYuval Mintz val = qed_rd(p_hwfn, p_ptt, 2892b2b897ebSYuval Mintz IGU_REG_WRITE_DONE_PENDING + ((sb_id / 32) * 4)); 2893b2b897ebSYuval Mintz if (val & (1 << (sb_id % 32))) 2894b2b897ebSYuval Mintz usleep_range(10, 20); 2895b2b897ebSYuval Mintz else 2896b2b897ebSYuval Mintz break; 2897b2b897ebSYuval Mintz } 2898b2b897ebSYuval Mintz if (i == IGU_CLEANUP_SLEEP_LENGTH) 2899b2b897ebSYuval Mintz DP_NOTICE(p_hwfn, 2900b2b897ebSYuval Mintz "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n", 2901b2b897ebSYuval Mintz sb_id); 2902b2b897ebSYuval Mintz 2903fe56b9e6SYuval Mintz /* Clear the CAU for the SB */ 2904fe56b9e6SYuval Mintz for (pi = 0; pi < 12; pi++) 2905fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 2906fe56b9e6SYuval Mintz CAU_REG_PI_MEMORY + (sb_id * 12 + pi) * 4, 0); 2907fe56b9e6SYuval Mintz } 2908fe56b9e6SYuval Mintz 2909fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn, 2910fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2911b2b897ebSYuval Mintz bool b_set, bool b_slowpath) 2912fe56b9e6SYuval Mintz { 2913fe56b9e6SYuval Mintz u32 igu_base_sb = p_hwfn->hw_info.p_igu_info->igu_base_sb; 2914fe56b9e6SYuval Mintz u32 igu_sb_cnt = p_hwfn->hw_info.p_igu_info->igu_sb_cnt; 2915b2b897ebSYuval Mintz u32 sb_id = 0, val = 0; 2916fe56b9e6SYuval Mintz 2917fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION); 2918fe56b9e6SYuval Mintz val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN; 2919fe56b9e6SYuval Mintz val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN; 2920fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val); 2921fe56b9e6SYuval Mintz 2922fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2923fe56b9e6SYuval Mintz "IGU cleaning SBs [%d,...,%d]\n", 2924fe56b9e6SYuval Mintz igu_base_sb, igu_base_sb + igu_sb_cnt - 1); 2925fe56b9e6SYuval Mintz 2926fe56b9e6SYuval Mintz for (sb_id = igu_base_sb; sb_id < igu_base_sb + igu_sb_cnt; sb_id++) 2927fe56b9e6SYuval Mintz qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id, 2928fe56b9e6SYuval Mintz p_hwfn->hw_info.opaque_fid, 2929fe56b9e6SYuval Mintz b_set); 2930fe56b9e6SYuval Mintz 2931b2b897ebSYuval Mintz if (!b_slowpath) 2932b2b897ebSYuval Mintz return; 2933b2b897ebSYuval Mintz 2934fe56b9e6SYuval Mintz sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id; 2935fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2936fe56b9e6SYuval Mintz "IGU cleaning slowpath SB [%d]\n", sb_id); 2937fe56b9e6SYuval Mintz qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id, 2938b2b897ebSYuval Mintz p_hwfn->hw_info.opaque_fid, b_set); 2939fe56b9e6SYuval Mintz } 2940fe56b9e6SYuval Mintz 29414ac801b7SYuval Mintz static u32 qed_int_igu_read_cam_block(struct qed_hwfn *p_hwfn, 29421a635e48SYuval Mintz struct qed_ptt *p_ptt, u16 sb_id) 29434ac801b7SYuval Mintz { 29444ac801b7SYuval Mintz u32 val = qed_rd(p_hwfn, p_ptt, 29451a635e48SYuval Mintz IGU_REG_MAPPING_MEMORY + sizeof(u32) * sb_id); 29464ac801b7SYuval Mintz struct qed_igu_block *p_block; 29474ac801b7SYuval Mintz 29484ac801b7SYuval Mintz p_block = &p_hwfn->hw_info.p_igu_info->igu_map.igu_blocks[sb_id]; 29494ac801b7SYuval Mintz 29504ac801b7SYuval Mintz /* stop scanning when hit first invalid PF entry */ 29514ac801b7SYuval Mintz if (!GET_FIELD(val, IGU_MAPPING_LINE_VALID) && 29524ac801b7SYuval Mintz GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID)) 29534ac801b7SYuval Mintz goto out; 29544ac801b7SYuval Mintz 29554ac801b7SYuval Mintz /* Fill the block information */ 29564ac801b7SYuval Mintz p_block->status = QED_IGU_STATUS_VALID; 29574ac801b7SYuval Mintz p_block->function_id = GET_FIELD(val, 29584ac801b7SYuval Mintz IGU_MAPPING_LINE_FUNCTION_NUMBER); 29594ac801b7SYuval Mintz p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID); 29604ac801b7SYuval Mintz p_block->vector_number = GET_FIELD(val, 29614ac801b7SYuval Mintz IGU_MAPPING_LINE_VECTOR_NUMBER); 29624ac801b7SYuval Mintz 29634ac801b7SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 29644ac801b7SYuval Mintz "IGU_BLOCK: [SB 0x%04x, Value in CAM 0x%08x] func_id = %d is_pf = %d vector_num = 0x%x\n", 29654ac801b7SYuval Mintz sb_id, val, p_block->function_id, 29664ac801b7SYuval Mintz p_block->is_pf, p_block->vector_number); 29674ac801b7SYuval Mintz 29684ac801b7SYuval Mintz out: 29694ac801b7SYuval Mintz return val; 29704ac801b7SYuval Mintz } 29714ac801b7SYuval Mintz 29721a635e48SYuval Mintz int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2973fe56b9e6SYuval Mintz { 2974fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 29751408cc1fSYuval Mintz u32 val, min_vf = 0, max_vf = 0; 29761408cc1fSYuval Mintz u16 sb_id, last_iov_sb_id = 0; 2977fe56b9e6SYuval Mintz struct qed_igu_block *blk; 2978fe56b9e6SYuval Mintz u16 prev_sb_id = 0xFF; 2979fe56b9e6SYuval Mintz 298060fffb3bSYuval Mintz p_hwfn->hw_info.p_igu_info = kzalloc(sizeof(*p_igu_info), GFP_KERNEL); 2981fe56b9e6SYuval Mintz if (!p_hwfn->hw_info.p_igu_info) 2982fe56b9e6SYuval Mintz return -ENOMEM; 2983fe56b9e6SYuval Mintz 2984fe56b9e6SYuval Mintz p_igu_info = p_hwfn->hw_info.p_igu_info; 2985fe56b9e6SYuval Mintz 29861408cc1fSYuval Mintz /* Initialize base sb / sb cnt for PFs and VFs */ 2987fe56b9e6SYuval Mintz p_igu_info->igu_base_sb = 0xffff; 2988fe56b9e6SYuval Mintz p_igu_info->igu_sb_cnt = 0; 2989fe56b9e6SYuval Mintz p_igu_info->igu_dsb_id = 0xffff; 2990fe56b9e6SYuval Mintz p_igu_info->igu_base_sb_iov = 0xffff; 2991fe56b9e6SYuval Mintz 29921408cc1fSYuval Mintz if (p_hwfn->cdev->p_iov_info) { 29931408cc1fSYuval Mintz struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info; 29941408cc1fSYuval Mintz 29951408cc1fSYuval Mintz min_vf = p_iov->first_vf_in_pf; 29961408cc1fSYuval Mintz max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs; 29971408cc1fSYuval Mintz } 29981408cc1fSYuval Mintz 2999fe56b9e6SYuval Mintz for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); 3000fe56b9e6SYuval Mintz sb_id++) { 3001fe56b9e6SYuval Mintz blk = &p_igu_info->igu_map.igu_blocks[sb_id]; 3002fe56b9e6SYuval Mintz 30034ac801b7SYuval Mintz val = qed_int_igu_read_cam_block(p_hwfn, p_ptt, sb_id); 3004fe56b9e6SYuval Mintz 3005fe56b9e6SYuval Mintz /* stop scanning when hit first invalid PF entry */ 3006fe56b9e6SYuval Mintz if (!GET_FIELD(val, IGU_MAPPING_LINE_VALID) && 3007fe56b9e6SYuval Mintz GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID)) 3008fe56b9e6SYuval Mintz break; 3009fe56b9e6SYuval Mintz 3010fe56b9e6SYuval Mintz if (blk->is_pf) { 3011fe56b9e6SYuval Mintz if (blk->function_id == p_hwfn->rel_pf_id) { 3012fe56b9e6SYuval Mintz blk->status |= QED_IGU_STATUS_PF; 3013fe56b9e6SYuval Mintz 3014fe56b9e6SYuval Mintz if (blk->vector_number == 0) { 3015fe56b9e6SYuval Mintz if (p_igu_info->igu_dsb_id == 0xffff) 3016fe56b9e6SYuval Mintz p_igu_info->igu_dsb_id = sb_id; 3017fe56b9e6SYuval Mintz } else { 3018fe56b9e6SYuval Mintz if (p_igu_info->igu_base_sb == 3019fe56b9e6SYuval Mintz 0xffff) { 3020fe56b9e6SYuval Mintz p_igu_info->igu_base_sb = sb_id; 3021fe56b9e6SYuval Mintz } else if (prev_sb_id != sb_id - 1) { 3022fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn->cdev, 3023fe56b9e6SYuval Mintz "consecutive igu vectors for HWFN %x broken", 3024fe56b9e6SYuval Mintz p_hwfn->rel_pf_id); 3025fe56b9e6SYuval Mintz break; 3026fe56b9e6SYuval Mintz } 3027fe56b9e6SYuval Mintz prev_sb_id = sb_id; 3028fe56b9e6SYuval Mintz /* we don't count the default */ 3029fe56b9e6SYuval Mintz (p_igu_info->igu_sb_cnt)++; 3030fe56b9e6SYuval Mintz } 3031fe56b9e6SYuval Mintz } 30321408cc1fSYuval Mintz } else { 30331408cc1fSYuval Mintz if ((blk->function_id >= min_vf) && 30341408cc1fSYuval Mintz (blk->function_id < max_vf)) { 30351408cc1fSYuval Mintz /* Available for VFs of this PF */ 30361408cc1fSYuval Mintz if (p_igu_info->igu_base_sb_iov == 0xffff) { 30371408cc1fSYuval Mintz p_igu_info->igu_base_sb_iov = sb_id; 30381408cc1fSYuval Mintz } else if (last_iov_sb_id != sb_id - 1) { 30391408cc1fSYuval Mintz if (!val) { 30401408cc1fSYuval Mintz DP_VERBOSE(p_hwfn->cdev, 30411408cc1fSYuval Mintz NETIF_MSG_INTR, 30421408cc1fSYuval Mintz "First uninitialized IGU CAM entry at index 0x%04x\n", 30431408cc1fSYuval Mintz sb_id); 30441408cc1fSYuval Mintz } else { 30451408cc1fSYuval Mintz DP_NOTICE(p_hwfn->cdev, 30461408cc1fSYuval Mintz "Consecutive igu vectors for HWFN %x vfs is broken [jumps from %04x to %04x]\n", 30471408cc1fSYuval Mintz p_hwfn->rel_pf_id, 30481408cc1fSYuval Mintz last_iov_sb_id, 30491408cc1fSYuval Mintz sb_id); } 30501408cc1fSYuval Mintz break; 30511408cc1fSYuval Mintz } 30521408cc1fSYuval Mintz blk->status |= QED_IGU_STATUS_FREE; 30531408cc1fSYuval Mintz p_hwfn->hw_info.p_igu_info->free_blks++; 30541408cc1fSYuval Mintz last_iov_sb_id = sb_id; 3055fe56b9e6SYuval Mintz } 3056fe56b9e6SYuval Mintz } 30571408cc1fSYuval Mintz } 30585a1f965aSMintz, Yuval 30595a1f965aSMintz, Yuval /* There's a possibility the igu_sb_cnt_iov doesn't properly reflect 30605a1f965aSMintz, Yuval * the number of VF SBs [especially for first VF on engine, as we can't 30618ac1ed79SJoe Perches * differentiate between empty entries and its entries]. 30625a1f965aSMintz, Yuval * Since we don't really support more SBs than VFs today, prevent any 30635a1f965aSMintz, Yuval * such configuration by sanitizing the number of SBs to equal the 30645a1f965aSMintz, Yuval * number of VFs. 30655a1f965aSMintz, Yuval */ 30665a1f965aSMintz, Yuval if (IS_PF_SRIOV(p_hwfn)) { 30675a1f965aSMintz, Yuval u16 total_vfs = p_hwfn->cdev->p_iov_info->total_vfs; 30685a1f965aSMintz, Yuval 30695a1f965aSMintz, Yuval if (total_vfs < p_igu_info->free_blks) { 30705a1f965aSMintz, Yuval DP_VERBOSE(p_hwfn, 30715a1f965aSMintz, Yuval (NETIF_MSG_INTR | QED_MSG_IOV), 30725a1f965aSMintz, Yuval "Limiting number of SBs for IOV - %04x --> %04x\n", 30735a1f965aSMintz, Yuval p_igu_info->free_blks, 30745a1f965aSMintz, Yuval p_hwfn->cdev->p_iov_info->total_vfs); 30755a1f965aSMintz, Yuval p_igu_info->free_blks = total_vfs; 30765a1f965aSMintz, Yuval } else if (total_vfs > p_igu_info->free_blks) { 30775a1f965aSMintz, Yuval DP_NOTICE(p_hwfn, 30785a1f965aSMintz, Yuval "IGU has only %04x SBs for VFs while the device has %04x VFs\n", 30795a1f965aSMintz, Yuval p_igu_info->free_blks, total_vfs); 30805a1f965aSMintz, Yuval return -EINVAL; 30815a1f965aSMintz, Yuval } 30825a1f965aSMintz, Yuval } 30831408cc1fSYuval Mintz p_igu_info->igu_sb_cnt_iov = p_igu_info->free_blks; 3084fe56b9e6SYuval Mintz 30851408cc1fSYuval Mintz DP_VERBOSE( 30861408cc1fSYuval Mintz p_hwfn, 30871408cc1fSYuval Mintz NETIF_MSG_INTR, 30881408cc1fSYuval Mintz "IGU igu_base_sb=0x%x [IOV 0x%x] igu_sb_cnt=%d [IOV 0x%x] igu_dsb_id=0x%x\n", 3089fe56b9e6SYuval Mintz p_igu_info->igu_base_sb, 30901408cc1fSYuval Mintz p_igu_info->igu_base_sb_iov, 3091fe56b9e6SYuval Mintz p_igu_info->igu_sb_cnt, 30921408cc1fSYuval Mintz p_igu_info->igu_sb_cnt_iov, 3093fe56b9e6SYuval Mintz p_igu_info->igu_dsb_id); 3094fe56b9e6SYuval Mintz 3095fe56b9e6SYuval Mintz if (p_igu_info->igu_base_sb == 0xffff || 3096fe56b9e6SYuval Mintz p_igu_info->igu_dsb_id == 0xffff || 3097fe56b9e6SYuval Mintz p_igu_info->igu_sb_cnt == 0) { 3098fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 3099fe56b9e6SYuval Mintz "IGU CAM returned invalid values igu_base_sb=0x%x igu_sb_cnt=%d igu_dsb_id=0x%x\n", 3100fe56b9e6SYuval Mintz p_igu_info->igu_base_sb, 3101fe56b9e6SYuval Mintz p_igu_info->igu_sb_cnt, 3102fe56b9e6SYuval Mintz p_igu_info->igu_dsb_id); 3103fe56b9e6SYuval Mintz return -EINVAL; 3104fe56b9e6SYuval Mintz } 3105fe56b9e6SYuval Mintz 3106fe56b9e6SYuval Mintz return 0; 3107fe56b9e6SYuval Mintz } 3108fe56b9e6SYuval Mintz 3109fe56b9e6SYuval Mintz /** 3110fe56b9e6SYuval Mintz * @brief Initialize igu runtime registers 3111fe56b9e6SYuval Mintz * 3112fe56b9e6SYuval Mintz * @param p_hwfn 3113fe56b9e6SYuval Mintz */ 3114fe56b9e6SYuval Mintz void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn) 3115fe56b9e6SYuval Mintz { 31161a635e48SYuval Mintz u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN; 3117fe56b9e6SYuval Mintz 3118fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf); 3119fe56b9e6SYuval Mintz } 3120fe56b9e6SYuval Mintz 3121fe56b9e6SYuval Mintz u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn) 3122fe56b9e6SYuval Mintz { 3123fe56b9e6SYuval Mintz u32 lsb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - 3124fe56b9e6SYuval Mintz IGU_CMD_INT_ACK_BASE; 3125fe56b9e6SYuval Mintz u32 msb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - 3126fe56b9e6SYuval Mintz IGU_CMD_INT_ACK_BASE; 31271a635e48SYuval Mintz u32 intr_status_hi = 0, intr_status_lo = 0; 31281a635e48SYuval Mintz u64 intr_status = 0; 3129fe56b9e6SYuval Mintz 3130fe56b9e6SYuval Mintz intr_status_lo = REG_RD(p_hwfn, 3131fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 3132fe56b9e6SYuval Mintz lsb_igu_cmd_addr * 8); 3133fe56b9e6SYuval Mintz intr_status_hi = REG_RD(p_hwfn, 3134fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 3135fe56b9e6SYuval Mintz msb_igu_cmd_addr * 8); 3136fe56b9e6SYuval Mintz intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo; 3137fe56b9e6SYuval Mintz 3138fe56b9e6SYuval Mintz return intr_status; 3139fe56b9e6SYuval Mintz } 3140fe56b9e6SYuval Mintz 3141fe56b9e6SYuval Mintz static void qed_int_sp_dpc_setup(struct qed_hwfn *p_hwfn) 3142fe56b9e6SYuval Mintz { 3143fe56b9e6SYuval Mintz tasklet_init(p_hwfn->sp_dpc, 3144fe56b9e6SYuval Mintz qed_int_sp_dpc, (unsigned long)p_hwfn); 3145fe56b9e6SYuval Mintz p_hwfn->b_sp_dpc_enabled = true; 3146fe56b9e6SYuval Mintz } 3147fe56b9e6SYuval Mintz 3148fe56b9e6SYuval Mintz static int qed_int_sp_dpc_alloc(struct qed_hwfn *p_hwfn) 3149fe56b9e6SYuval Mintz { 315060fffb3bSYuval Mintz p_hwfn->sp_dpc = kmalloc(sizeof(*p_hwfn->sp_dpc), GFP_KERNEL); 3151fe56b9e6SYuval Mintz if (!p_hwfn->sp_dpc) 3152fe56b9e6SYuval Mintz return -ENOMEM; 3153fe56b9e6SYuval Mintz 3154fe56b9e6SYuval Mintz return 0; 3155fe56b9e6SYuval Mintz } 3156fe56b9e6SYuval Mintz 3157fe56b9e6SYuval Mintz static void qed_int_sp_dpc_free(struct qed_hwfn *p_hwfn) 3158fe56b9e6SYuval Mintz { 3159fe56b9e6SYuval Mintz kfree(p_hwfn->sp_dpc); 3160fe56b9e6SYuval Mintz } 3161fe56b9e6SYuval Mintz 31621a635e48SYuval Mintz int qed_int_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3163fe56b9e6SYuval Mintz { 3164fe56b9e6SYuval Mintz int rc = 0; 3165fe56b9e6SYuval Mintz 3166fe56b9e6SYuval Mintz rc = qed_int_sp_dpc_alloc(p_hwfn); 316783aeb933SYuval Mintz if (rc) 31682591c280SJoe Perches return rc; 31692591c280SJoe Perches 31702591c280SJoe Perches rc = qed_int_sp_sb_alloc(p_hwfn, p_ptt); 31712591c280SJoe Perches if (rc) 31722591c280SJoe Perches return rc; 31732591c280SJoe Perches 31742591c280SJoe Perches rc = qed_int_sb_attn_alloc(p_hwfn, p_ptt); 317583aeb933SYuval Mintz 3176fe56b9e6SYuval Mintz return rc; 3177fe56b9e6SYuval Mintz } 3178fe56b9e6SYuval Mintz 3179fe56b9e6SYuval Mintz void qed_int_free(struct qed_hwfn *p_hwfn) 3180fe56b9e6SYuval Mintz { 3181fe56b9e6SYuval Mintz qed_int_sp_sb_free(p_hwfn); 3182cc875c2eSYuval Mintz qed_int_sb_attn_free(p_hwfn); 3183fe56b9e6SYuval Mintz qed_int_sp_dpc_free(p_hwfn); 3184fe56b9e6SYuval Mintz } 3185fe56b9e6SYuval Mintz 31861a635e48SYuval Mintz void qed_int_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3187fe56b9e6SYuval Mintz { 31880d956e8aSYuval Mintz qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info); 31890d956e8aSYuval Mintz qed_int_sb_attn_setup(p_hwfn, p_ptt); 3190fe56b9e6SYuval Mintz qed_int_sp_dpc_setup(p_hwfn); 3191fe56b9e6SYuval Mintz } 3192fe56b9e6SYuval Mintz 31934ac801b7SYuval Mintz void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn, 31944ac801b7SYuval Mintz struct qed_sb_cnt_info *p_sb_cnt_info) 3195fe56b9e6SYuval Mintz { 3196fe56b9e6SYuval Mintz struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info; 3197fe56b9e6SYuval Mintz 31984ac801b7SYuval Mintz if (!info || !p_sb_cnt_info) 31994ac801b7SYuval Mintz return; 3200fe56b9e6SYuval Mintz 32014ac801b7SYuval Mintz p_sb_cnt_info->sb_cnt = info->igu_sb_cnt; 32024ac801b7SYuval Mintz p_sb_cnt_info->sb_iov_cnt = info->igu_sb_cnt_iov; 32034ac801b7SYuval Mintz p_sb_cnt_info->sb_free_blk = info->free_blks; 3204fe56b9e6SYuval Mintz } 32058f16bc97SSudarsana Kalluru 32061408cc1fSYuval Mintz u16 qed_int_queue_id_from_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id) 32071408cc1fSYuval Mintz { 32081408cc1fSYuval Mintz struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info; 32091408cc1fSYuval Mintz 32101408cc1fSYuval Mintz /* Determine origin of SB id */ 32111408cc1fSYuval Mintz if ((sb_id >= p_info->igu_base_sb) && 32121408cc1fSYuval Mintz (sb_id < p_info->igu_base_sb + p_info->igu_sb_cnt)) { 32131408cc1fSYuval Mintz return sb_id - p_info->igu_base_sb; 32141408cc1fSYuval Mintz } else if ((sb_id >= p_info->igu_base_sb_iov) && 32151408cc1fSYuval Mintz (sb_id < p_info->igu_base_sb_iov + p_info->igu_sb_cnt_iov)) { 32165a1f965aSMintz, Yuval /* We want the first VF queue to be adjacent to the 32175a1f965aSMintz, Yuval * last PF queue. Since L2 queues can be partial to 32185a1f965aSMintz, Yuval * SBs, we'll use the feature instead. 32195a1f965aSMintz, Yuval */ 32205a1f965aSMintz, Yuval return sb_id - p_info->igu_base_sb_iov + 32215a1f965aSMintz, Yuval FEAT_NUM(p_hwfn, QED_PF_L2_QUE); 32221408cc1fSYuval Mintz } else { 32231408cc1fSYuval Mintz DP_NOTICE(p_hwfn, "SB %d not in range for function\n", sb_id); 32241408cc1fSYuval Mintz return 0; 32251408cc1fSYuval Mintz } 32261408cc1fSYuval Mintz } 32271408cc1fSYuval Mintz 32288f16bc97SSudarsana Kalluru void qed_int_disable_post_isr_release(struct qed_dev *cdev) 32298f16bc97SSudarsana Kalluru { 32308f16bc97SSudarsana Kalluru int i; 32318f16bc97SSudarsana Kalluru 32328f16bc97SSudarsana Kalluru for_each_hwfn(cdev, i) 32338f16bc97SSudarsana Kalluru cdev->hwfns[i].b_int_requested = false; 32348f16bc97SSudarsana Kalluru } 3235722003acSSudarsana Reddy Kalluru 3236722003acSSudarsana Reddy Kalluru int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 3237722003acSSudarsana Reddy Kalluru u8 timer_res, u16 sb_id, bool tx) 3238722003acSSudarsana Reddy Kalluru { 3239722003acSSudarsana Reddy Kalluru struct cau_sb_entry sb_entry; 3240722003acSSudarsana Reddy Kalluru int rc; 3241722003acSSudarsana Reddy Kalluru 3242722003acSSudarsana Reddy Kalluru if (!p_hwfn->hw_init_done) { 3243722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "hardware not initialized yet\n"); 3244722003acSSudarsana Reddy Kalluru return -EINVAL; 3245722003acSSudarsana Reddy Kalluru } 3246722003acSSudarsana Reddy Kalluru 3247722003acSSudarsana Reddy Kalluru rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY + 3248722003acSSudarsana Reddy Kalluru sb_id * sizeof(u64), 3249722003acSSudarsana Reddy Kalluru (u64)(uintptr_t)&sb_entry, 2, 0); 3250722003acSSudarsana Reddy Kalluru if (rc) { 3251722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc); 3252722003acSSudarsana Reddy Kalluru return rc; 3253722003acSSudarsana Reddy Kalluru } 3254722003acSSudarsana Reddy Kalluru 3255722003acSSudarsana Reddy Kalluru if (tx) 3256722003acSSudarsana Reddy Kalluru SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 3257722003acSSudarsana Reddy Kalluru else 3258722003acSSudarsana Reddy Kalluru SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 3259722003acSSudarsana Reddy Kalluru 3260722003acSSudarsana Reddy Kalluru rc = qed_dmae_host2grc(p_hwfn, p_ptt, 3261722003acSSudarsana Reddy Kalluru (u64)(uintptr_t)&sb_entry, 3262722003acSSudarsana Reddy Kalluru CAU_REG_SB_VAR_MEMORY + 3263722003acSSudarsana Reddy Kalluru sb_id * sizeof(u64), 2, 0); 3264722003acSSudarsana Reddy Kalluru if (rc) { 3265722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc); 3266722003acSSudarsana Reddy Kalluru return rc; 3267722003acSSudarsana Reddy Kalluru } 3268722003acSSudarsana Reddy Kalluru 3269722003acSSudarsana Reddy Kalluru return rc; 3270722003acSSudarsana Reddy Kalluru } 3271