1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #include <linux/types.h> 34fe56b9e6SYuval Mintz #include <asm/byteorder.h> 35fe56b9e6SYuval Mintz #include <linux/io.h> 36fe56b9e6SYuval Mintz #include <linux/bitops.h> 37fe56b9e6SYuval Mintz #include <linux/delay.h> 38fe56b9e6SYuval Mintz #include <linux/dma-mapping.h> 39fe56b9e6SYuval Mintz #include <linux/errno.h> 40fe56b9e6SYuval Mintz #include <linux/interrupt.h> 41fe56b9e6SYuval Mintz #include <linux/kernel.h> 42fe56b9e6SYuval Mintz #include <linux/pci.h> 43fe56b9e6SYuval Mintz #include <linux/slab.h> 44fe56b9e6SYuval Mintz #include <linux/string.h> 45fe56b9e6SYuval Mintz #include "qed.h" 46fe56b9e6SYuval Mintz #include "qed_hsi.h" 47fe56b9e6SYuval Mintz #include "qed_hw.h" 48fe56b9e6SYuval Mintz #include "qed_init_ops.h" 49fe56b9e6SYuval Mintz #include "qed_int.h" 50fe56b9e6SYuval Mintz #include "qed_mcp.h" 51fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 52fe56b9e6SYuval Mintz #include "qed_sp.h" 531408cc1fSYuval Mintz #include "qed_sriov.h" 541408cc1fSYuval Mintz #include "qed_vf.h" 55fe56b9e6SYuval Mintz 56fe56b9e6SYuval Mintz struct qed_pi_info { 57fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb; 58fe56b9e6SYuval Mintz void *cookie; 59fe56b9e6SYuval Mintz }; 60fe56b9e6SYuval Mintz 61fe56b9e6SYuval Mintz struct qed_sb_sp_info { 62fe56b9e6SYuval Mintz struct qed_sb_info sb_info; 63fe56b9e6SYuval Mintz 64fe56b9e6SYuval Mintz /* per protocol index data */ 6521dd79e8STomer Tayar struct qed_pi_info pi_info_arr[PIS_PER_SB_E4]; 66fe56b9e6SYuval Mintz }; 67fe56b9e6SYuval Mintz 68ff38577aSYuval Mintz enum qed_attention_type { 69ff38577aSYuval Mintz QED_ATTN_TYPE_ATTN, 70ff38577aSYuval Mintz QED_ATTN_TYPE_PARITY, 71ff38577aSYuval Mintz }; 72ff38577aSYuval Mintz 73cc875c2eSYuval Mintz #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \ 74cc875c2eSYuval Mintz ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn) 75cc875c2eSYuval Mintz 760d956e8aSYuval Mintz struct aeu_invert_reg_bit { 770d956e8aSYuval Mintz char bit_name[30]; 780d956e8aSYuval Mintz 790d956e8aSYuval Mintz #define ATTENTION_PARITY (1 << 0) 800d956e8aSYuval Mintz 810d956e8aSYuval Mintz #define ATTENTION_LENGTH_MASK (0x00000ff0) 820d956e8aSYuval Mintz #define ATTENTION_LENGTH_SHIFT (4) 830d956e8aSYuval Mintz #define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \ 840d956e8aSYuval Mintz ATTENTION_LENGTH_SHIFT) 85a2e7699eSTomer Tayar #define ATTENTION_SINGLE BIT(ATTENTION_LENGTH_SHIFT) 860d956e8aSYuval Mintz #define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY) 870d956e8aSYuval Mintz #define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \ 880d956e8aSYuval Mintz ATTENTION_PARITY) 890d956e8aSYuval Mintz 900d956e8aSYuval Mintz /* Multiple bits start with this offset */ 910d956e8aSYuval Mintz #define ATTENTION_OFFSET_MASK (0x000ff000) 920d956e8aSYuval Mintz #define ATTENTION_OFFSET_SHIFT (12) 93ba36f718SMintz, Yuval 94ba36f718SMintz, Yuval #define ATTENTION_BB_MASK (0x00700000) 95ba36f718SMintz, Yuval #define ATTENTION_BB_SHIFT (20) 96ba36f718SMintz, Yuval #define ATTENTION_BB(value) (value << ATTENTION_BB_SHIFT) 97ba36f718SMintz, Yuval #define ATTENTION_BB_DIFFERENT BIT(23) 98ba36f718SMintz, Yuval 990d956e8aSYuval Mintz unsigned int flags; 100ff38577aSYuval Mintz 101b4149dc7SYuval Mintz /* Callback to call if attention will be triggered */ 102b4149dc7SYuval Mintz int (*cb)(struct qed_hwfn *p_hwfn); 103b4149dc7SYuval Mintz 104ff38577aSYuval Mintz enum block_id block_index; 1050d956e8aSYuval Mintz }; 1060d956e8aSYuval Mintz 1070d956e8aSYuval Mintz struct aeu_invert_reg { 1080d956e8aSYuval Mintz struct aeu_invert_reg_bit bits[32]; 1090d956e8aSYuval Mintz }; 1100d956e8aSYuval Mintz 1110d956e8aSYuval Mintz #define MAX_ATTN_GRPS (8) 1120d956e8aSYuval Mintz #define NUM_ATTN_REGS (9) 1130d956e8aSYuval Mintz 114b4149dc7SYuval Mintz /* Specific HW attention callbacks */ 115b4149dc7SYuval Mintz static int qed_mcp_attn_cb(struct qed_hwfn *p_hwfn) 116b4149dc7SYuval Mintz { 117b4149dc7SYuval Mintz u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE); 118b4149dc7SYuval Mintz 119b4149dc7SYuval Mintz /* This might occur on certain instances; Log it once then mask it */ 120b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, "MCP_REG_CPU_STATE: %08x - Masking...\n", 121b4149dc7SYuval Mintz tmp); 122b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, 123b4149dc7SYuval Mintz 0xffffffff); 124b4149dc7SYuval Mintz 125b4149dc7SYuval Mintz return 0; 126b4149dc7SYuval Mintz } 127b4149dc7SYuval Mintz 128b4149dc7SYuval Mintz #define QED_PSWHST_ATTENTION_INCORRECT_ACCESS (0x1) 129b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_WR_MASK (0x1) 130b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_WR_SHIFT (0) 131b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_CLIENT_MASK (0xf) 132b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT (1) 133b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK (0x1) 134b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT (5) 135b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_ID_MASK (0xff) 136b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT (6) 137b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_PF_ID_MASK (0xf) 138b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT (14) 139b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK (0xff) 140b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT (18) 141b4149dc7SYuval Mintz static int qed_pswhst_attn_cb(struct qed_hwfn *p_hwfn) 142b4149dc7SYuval Mintz { 143b4149dc7SYuval Mintz u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 144b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_VALID); 145b4149dc7SYuval Mintz 146b4149dc7SYuval Mintz if (tmp & QED_PSWHST_ATTENTION_INCORRECT_ACCESS) { 147b4149dc7SYuval Mintz u32 addr, data, length; 148b4149dc7SYuval Mintz 149b4149dc7SYuval Mintz addr = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 150b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_ADDRESS); 151b4149dc7SYuval Mintz data = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 152b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_DATA); 153b4149dc7SYuval Mintz length = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 154b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_LENGTH); 155b4149dc7SYuval Mintz 156b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, 157b4149dc7SYuval Mintz "Incorrect access to %08x of length %08x - PF [%02x] VF [%04x] [valid %02x] client [%02x] write [%02x] Byte-Enable [%04x] [%08x]\n", 158b4149dc7SYuval Mintz addr, length, 159b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_PF_ID), 160b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_VF_ID), 161b4149dc7SYuval Mintz (u8) GET_FIELD(data, 162b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_VF_VALID), 163b4149dc7SYuval Mintz (u8) GET_FIELD(data, 164b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_CLIENT), 165b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_WR), 166b4149dc7SYuval Mintz (u8) GET_FIELD(data, 167b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_BYTE_EN), 168b4149dc7SYuval Mintz data); 169b4149dc7SYuval Mintz } 170b4149dc7SYuval Mintz 171b4149dc7SYuval Mintz return 0; 172b4149dc7SYuval Mintz } 173b4149dc7SYuval Mintz 174b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VALID_BIT (1 << 0) 175b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_ADDRESS_MASK (0x7fffff) 176b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_ADDRESS_SHIFT (0) 177b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_RDWR_BIT (1 << 23) 178b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_MASTER_MASK (0xf) 179b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_MASTER_SHIFT (24) 180b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PF_MASK (0xf) 181b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PF_SHIFT (0) 182b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VF_MASK (0xff) 183b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VF_SHIFT (4) 184b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_MASK (0x3) 185b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_SHIFT (14) 186b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_VF (0) 187b4149dc7SYuval Mintz static const char *attn_master_to_str(u8 master) 188b4149dc7SYuval Mintz { 189b4149dc7SYuval Mintz switch (master) { 190b4149dc7SYuval Mintz case 1: return "PXP"; 191b4149dc7SYuval Mintz case 2: return "MCP"; 192b4149dc7SYuval Mintz case 3: return "MSDM"; 193b4149dc7SYuval Mintz case 4: return "PSDM"; 194b4149dc7SYuval Mintz case 5: return "YSDM"; 195b4149dc7SYuval Mintz case 6: return "USDM"; 196b4149dc7SYuval Mintz case 7: return "TSDM"; 197b4149dc7SYuval Mintz case 8: return "XSDM"; 198b4149dc7SYuval Mintz case 9: return "DBU"; 199b4149dc7SYuval Mintz case 10: return "DMAE"; 200b4149dc7SYuval Mintz default: 2019165dabbSMasanari Iida return "Unknown"; 202b4149dc7SYuval Mintz } 203b4149dc7SYuval Mintz } 204b4149dc7SYuval Mintz 205b4149dc7SYuval Mintz static int qed_grc_attn_cb(struct qed_hwfn *p_hwfn) 206b4149dc7SYuval Mintz { 207b4149dc7SYuval Mintz u32 tmp, tmp2; 208b4149dc7SYuval Mintz 209b4149dc7SYuval Mintz /* We've already cleared the timeout interrupt register, so we learn 210b4149dc7SYuval Mintz * of interrupts via the validity register 211b4149dc7SYuval Mintz */ 212b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 213b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_VALID); 214b4149dc7SYuval Mintz if (!(tmp & QED_GRC_ATTENTION_VALID_BIT)) 215b4149dc7SYuval Mintz goto out; 216b4149dc7SYuval Mintz 217b4149dc7SYuval Mintz /* Read the GRC timeout information */ 218b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 219b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0); 220b4149dc7SYuval Mintz tmp2 = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 221b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1); 222b4149dc7SYuval Mintz 223b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, 224b4149dc7SYuval Mintz "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n", 225b4149dc7SYuval Mintz tmp2, tmp, 226b4149dc7SYuval Mintz (tmp & QED_GRC_ATTENTION_RDWR_BIT) ? "Write to" : "Read from", 227b4149dc7SYuval Mintz GET_FIELD(tmp, QED_GRC_ATTENTION_ADDRESS) << 2, 228b4149dc7SYuval Mintz attn_master_to_str(GET_FIELD(tmp, QED_GRC_ATTENTION_MASTER)), 229b4149dc7SYuval Mintz GET_FIELD(tmp2, QED_GRC_ATTENTION_PF), 230b4149dc7SYuval Mintz (GET_FIELD(tmp2, QED_GRC_ATTENTION_PRIV) == 231fbe1222cSColin Ian King QED_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Irrelevant)", 232b4149dc7SYuval Mintz GET_FIELD(tmp2, QED_GRC_ATTENTION_VF)); 233b4149dc7SYuval Mintz 234b4149dc7SYuval Mintz out: 235b4149dc7SYuval Mintz /* Regardles of anything else, clean the validity bit */ 236b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 237b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0); 238b4149dc7SYuval Mintz return 0; 239b4149dc7SYuval Mintz } 240b4149dc7SYuval Mintz 241b4149dc7SYuval Mintz #define PGLUE_ATTENTION_VALID (1 << 29) 242b4149dc7SYuval Mintz #define PGLUE_ATTENTION_RD_VALID (1 << 26) 243b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf) 244b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20) 245b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VF_VALID_MASK (0x1) 246b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VF_VALID_SHIFT (19) 247b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff) 248b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24) 249b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_MASK (0x1) 250b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_SHIFT (21) 251b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_BME_MASK (0x1) 252b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_BME_SHIFT (22) 253b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_FID_EN_MASK (0x1) 254b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_FID_EN_SHIFT (23) 255b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ICPL_VALID (1 << 23) 256b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ZLR_VALID (1 << 25) 257b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ILT_VALID (1 << 23) 258666db486STomer Tayar 259666db486STomer Tayar int qed_pglueb_rbc_attn_handler(struct qed_hwfn *p_hwfn, 260666db486STomer Tayar struct qed_ptt *p_ptt) 261b4149dc7SYuval Mintz { 262b4149dc7SYuval Mintz u32 tmp; 263b4149dc7SYuval Mintz 264666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS2); 265b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_VALID) { 266b4149dc7SYuval Mintz u32 addr_lo, addr_hi, details; 267b4149dc7SYuval Mintz 268666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 269b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_ADD_31_0); 270666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 271b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_ADD_63_32); 272666db486STomer Tayar details = qed_rd(p_hwfn, p_ptt, 273b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_DETAILS); 274b4149dc7SYuval Mintz 275666db486STomer Tayar DP_NOTICE(p_hwfn, 276b4149dc7SYuval Mintz "Illegal write by chip to [%08x:%08x] blocked.\n" 277b4149dc7SYuval Mintz "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 278b4149dc7SYuval Mintz "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 279b4149dc7SYuval Mintz addr_hi, addr_lo, details, 280b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 281b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 282b4149dc7SYuval Mintz GET_FIELD(details, 283b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0, 284b4149dc7SYuval Mintz tmp, 285b4149dc7SYuval Mintz GET_FIELD(tmp, 286b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0, 287b4149dc7SYuval Mintz GET_FIELD(tmp, 288b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0, 289b4149dc7SYuval Mintz GET_FIELD(tmp, 290b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0); 291b4149dc7SYuval Mintz } 292b4149dc7SYuval Mintz 293666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_RD_DETAILS2); 294b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_RD_VALID) { 295b4149dc7SYuval Mintz u32 addr_lo, addr_hi, details; 296b4149dc7SYuval Mintz 297666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 298b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_ADD_31_0); 299666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 300b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_ADD_63_32); 301666db486STomer Tayar details = qed_rd(p_hwfn, p_ptt, 302b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_DETAILS); 303b4149dc7SYuval Mintz 304666db486STomer Tayar DP_NOTICE(p_hwfn, 305b4149dc7SYuval Mintz "Illegal read by chip from [%08x:%08x] blocked.\n" 306b4149dc7SYuval Mintz "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 307b4149dc7SYuval Mintz "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 308b4149dc7SYuval Mintz addr_hi, addr_lo, details, 309b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 310b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 311b4149dc7SYuval Mintz GET_FIELD(details, 312b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0, 313b4149dc7SYuval Mintz tmp, 314666db486STomer Tayar GET_FIELD(tmp, 315666db486STomer Tayar PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0, 316666db486STomer Tayar GET_FIELD(tmp, 317666db486STomer Tayar PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0, 318666db486STomer Tayar GET_FIELD(tmp, 319666db486STomer Tayar PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0); 320b4149dc7SYuval Mintz } 321b4149dc7SYuval Mintz 322666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL); 323b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ICPL_VALID) 324666db486STomer Tayar DP_NOTICE(p_hwfn, "ICPL error - %08x\n", tmp); 325b4149dc7SYuval Mintz 326666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS); 327b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ZLR_VALID) { 328b4149dc7SYuval Mintz u32 addr_hi, addr_lo; 329b4149dc7SYuval Mintz 330666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 331b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0); 332666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 333b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32); 334b4149dc7SYuval Mintz 335666db486STomer Tayar DP_NOTICE(p_hwfn, "ZLR error - %08x [Address %08x:%08x]\n", 336b4149dc7SYuval Mintz tmp, addr_hi, addr_lo); 337b4149dc7SYuval Mintz } 338b4149dc7SYuval Mintz 339666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_VF_ILT_ERR_DETAILS2); 340b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ILT_VALID) { 341b4149dc7SYuval Mintz u32 addr_hi, addr_lo, details; 342b4149dc7SYuval Mintz 343666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 344b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_ADD_31_0); 345666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 346b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_ADD_63_32); 347666db486STomer Tayar details = qed_rd(p_hwfn, p_ptt, 348b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_DETAILS); 349b4149dc7SYuval Mintz 350666db486STomer Tayar DP_NOTICE(p_hwfn, 351b4149dc7SYuval Mintz "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n", 352b4149dc7SYuval Mintz details, tmp, addr_hi, addr_lo); 353b4149dc7SYuval Mintz } 354b4149dc7SYuval Mintz 355b4149dc7SYuval Mintz /* Clear the indications */ 356666db486STomer Tayar qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_LATCHED_ERRORS_CLR, BIT(2)); 357b4149dc7SYuval Mintz 358b4149dc7SYuval Mintz return 0; 359b4149dc7SYuval Mintz } 360b4149dc7SYuval Mintz 361666db486STomer Tayar static int qed_pglueb_rbc_attn_cb(struct qed_hwfn *p_hwfn) 362666db486STomer Tayar { 363666db486STomer Tayar return qed_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_dpc_ptt); 364666db486STomer Tayar } 365666db486STomer Tayar 366b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_REASON_MASK (0xfffff) 367b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_OPAQUE_MASK (0xffff) 368a1b469b8SAriel Elior #define QED_DORQ_ATTENTION_OPAQUE_SHIFT (0x0) 369b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_SIZE_MASK (0x7f) 370b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_SIZE_SHIFT (16) 371a1b469b8SAriel Elior 372a1b469b8SAriel Elior #define QED_DB_REC_COUNT 1000 373a1b469b8SAriel Elior #define QED_DB_REC_INTERVAL 100 374a1b469b8SAriel Elior 375a1b469b8SAriel Elior static int qed_db_rec_flush_queue(struct qed_hwfn *p_hwfn, 376a1b469b8SAriel Elior struct qed_ptt *p_ptt) 377a1b469b8SAriel Elior { 378a1b469b8SAriel Elior u32 count = QED_DB_REC_COUNT; 379a1b469b8SAriel Elior u32 usage = 1; 380a1b469b8SAriel Elior 3810d72c2acSDenis Bolotin /* Flush any pending (e)dpms as they may never arrive */ 3820d72c2acSDenis Bolotin qed_wr(p_hwfn, p_ptt, DORQ_REG_DPM_FORCE_ABORT, 0x1); 3830d72c2acSDenis Bolotin 384a1b469b8SAriel Elior /* wait for usage to zero or count to run out. This is necessary since 385a1b469b8SAriel Elior * EDPM doorbell transactions can take multiple 64b cycles, and as such 386a1b469b8SAriel Elior * can "split" over the pci. Possibly, the doorbell drop can happen with 387a1b469b8SAriel Elior * half an EDPM in the queue and other half dropped. Another EDPM 388a1b469b8SAriel Elior * doorbell to the same address (from doorbell recovery mechanism or 389a1b469b8SAriel Elior * from the doorbelling entity) could have first half dropped and second 390a1b469b8SAriel Elior * half interpreted as continuation of the first. To prevent such 391a1b469b8SAriel Elior * malformed doorbells from reaching the device, flush the queue before 392a1b469b8SAriel Elior * releasing the overflow sticky indication. 393a1b469b8SAriel Elior */ 394a1b469b8SAriel Elior while (count-- && usage) { 395a1b469b8SAriel Elior usage = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_USAGE_CNT); 396a1b469b8SAriel Elior udelay(QED_DB_REC_INTERVAL); 397a1b469b8SAriel Elior } 398a1b469b8SAriel Elior 399a1b469b8SAriel Elior /* should have been depleted by now */ 400a1b469b8SAriel Elior if (usage) { 401a1b469b8SAriel Elior DP_NOTICE(p_hwfn->cdev, 402a1b469b8SAriel Elior "DB recovery: doorbell usage failed to zero after %d usec. usage was %x\n", 403a1b469b8SAriel Elior QED_DB_REC_INTERVAL * QED_DB_REC_COUNT, usage); 404a1b469b8SAriel Elior return -EBUSY; 405a1b469b8SAriel Elior } 406a1b469b8SAriel Elior 407a1b469b8SAriel Elior return 0; 408a1b469b8SAriel Elior } 409a1b469b8SAriel Elior 410a1b469b8SAriel Elior int qed_db_rec_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 411a1b469b8SAriel Elior { 4120d72c2acSDenis Bolotin u32 attn_ovfl, cur_ovfl; 413a1b469b8SAriel Elior int rc; 414a1b469b8SAriel Elior 4150d72c2acSDenis Bolotin attn_ovfl = test_and_clear_bit(QED_OVERFLOW_BIT, 4160d72c2acSDenis Bolotin &p_hwfn->db_recovery_info.overflow); 4170d72c2acSDenis Bolotin cur_ovfl = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY); 4180d72c2acSDenis Bolotin if (!cur_ovfl && !attn_ovfl) 419a1b469b8SAriel Elior return 0; 420a1b469b8SAriel Elior 4210d72c2acSDenis Bolotin DP_NOTICE(p_hwfn, "PF Overflow sticky: attn %u current %u\n", 4220d72c2acSDenis Bolotin attn_ovfl, cur_ovfl); 4230d72c2acSDenis Bolotin 4240d72c2acSDenis Bolotin if (cur_ovfl && !p_hwfn->db_bar_no_edpm) { 425a1b469b8SAriel Elior rc = qed_db_rec_flush_queue(p_hwfn, p_ptt); 426a1b469b8SAriel Elior if (rc) 427a1b469b8SAriel Elior return rc; 428a1b469b8SAriel Elior } 429a1b469b8SAriel Elior 430a1b469b8SAriel Elior /* Release overflow sticky indication (stop silently dropping everything) */ 431a1b469b8SAriel Elior qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0); 432a1b469b8SAriel Elior 433a1b469b8SAriel Elior /* Repeat all last doorbells (doorbell drop recovery) */ 4349ac6bb14SDenis Bolotin qed_db_recovery_execute(p_hwfn); 435a1b469b8SAriel Elior 436a1b469b8SAriel Elior return 0; 437a1b469b8SAriel Elior } 438a1b469b8SAriel Elior 4390d72c2acSDenis Bolotin static void qed_dorq_attn_overflow(struct qed_hwfn *p_hwfn) 4400d72c2acSDenis Bolotin { 4410d72c2acSDenis Bolotin struct qed_ptt *p_ptt = p_hwfn->p_dpc_ptt; 4420d72c2acSDenis Bolotin u32 overflow; 4430d72c2acSDenis Bolotin int rc; 4440d72c2acSDenis Bolotin 4450d72c2acSDenis Bolotin overflow = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY); 4460d72c2acSDenis Bolotin if (!overflow) 4470d72c2acSDenis Bolotin goto out; 4480d72c2acSDenis Bolotin 4490d72c2acSDenis Bolotin /* Run PF doorbell recovery in next periodic handler */ 4500d72c2acSDenis Bolotin set_bit(QED_OVERFLOW_BIT, &p_hwfn->db_recovery_info.overflow); 4510d72c2acSDenis Bolotin 4520d72c2acSDenis Bolotin if (!p_hwfn->db_bar_no_edpm) { 4530d72c2acSDenis Bolotin rc = qed_db_rec_flush_queue(p_hwfn, p_ptt); 4540d72c2acSDenis Bolotin if (rc) 4550d72c2acSDenis Bolotin goto out; 4560d72c2acSDenis Bolotin } 4570d72c2acSDenis Bolotin 4580d72c2acSDenis Bolotin qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0); 4590d72c2acSDenis Bolotin out: 4600d72c2acSDenis Bolotin /* Schedule the handler even if overflow was not detected */ 4610d72c2acSDenis Bolotin qed_periodic_db_rec_start(p_hwfn); 4620d72c2acSDenis Bolotin } 4630d72c2acSDenis Bolotin 4640d72c2acSDenis Bolotin static int qed_dorq_attn_int_sts(struct qed_hwfn *p_hwfn) 465b4149dc7SYuval Mintz { 466a1b469b8SAriel Elior u32 int_sts, first_drop_reason, details, address, all_drops_reason; 467a1b469b8SAriel Elior struct qed_ptt *p_ptt = p_hwfn->p_dpc_ptt; 468a1b469b8SAriel Elior 469a1b469b8SAriel Elior /* int_sts may be zero since all PFs were interrupted for doorbell 470a1b469b8SAriel Elior * overflow but another one already handled it. Can abort here. If 471a1b469b8SAriel Elior * This PF also requires overflow recovery we will be interrupted again. 472a1b469b8SAriel Elior * The masked almost full indication may also be set. Ignoring. 473a1b469b8SAriel Elior */ 474d4476b8aSDenis Bolotin int_sts = qed_rd(p_hwfn, p_ptt, DORQ_REG_INT_STS); 475a1b469b8SAriel Elior if (!(int_sts & ~DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) 476a1b469b8SAriel Elior return 0; 477a1b469b8SAriel Elior 478d4476b8aSDenis Bolotin DP_NOTICE(p_hwfn->cdev, "DORQ attention. int_sts was %x\n", int_sts); 479d4476b8aSDenis Bolotin 480a1b469b8SAriel Elior /* check if db_drop or overflow happened */ 481a1b469b8SAriel Elior if (int_sts & (DORQ_REG_INT_STS_DB_DROP | 482a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR)) { 483a1b469b8SAriel Elior /* Obtain data about db drop/overflow */ 484a1b469b8SAriel Elior first_drop_reason = qed_rd(p_hwfn, p_ptt, 485a1b469b8SAriel Elior DORQ_REG_DB_DROP_REASON) & 486b4149dc7SYuval Mintz QED_DORQ_ATTENTION_REASON_MASK; 487a1b469b8SAriel Elior details = qed_rd(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS); 488a1b469b8SAriel Elior address = qed_rd(p_hwfn, p_ptt, 489a1b469b8SAriel Elior DORQ_REG_DB_DROP_DETAILS_ADDRESS); 490a1b469b8SAriel Elior all_drops_reason = qed_rd(p_hwfn, p_ptt, 491a1b469b8SAriel Elior DORQ_REG_DB_DROP_DETAILS_REASON); 492b4149dc7SYuval Mintz 493a1b469b8SAriel Elior /* Log info */ 494a1b469b8SAriel Elior DP_NOTICE(p_hwfn->cdev, 495a1b469b8SAriel Elior "Doorbell drop occurred\n" 496a1b469b8SAriel Elior "Address\t\t0x%08x\t(second BAR address)\n" 497a1b469b8SAriel Elior "FID\t\t0x%04x\t\t(Opaque FID)\n" 498a1b469b8SAriel Elior "Size\t\t0x%04x\t\t(in bytes)\n" 499a1b469b8SAriel Elior "1st drop reason\t0x%08x\t(details on first drop since last handling)\n" 500a1b469b8SAriel Elior "Sticky reasons\t0x%08x\t(all drop reasons since last handling)\n", 501a1b469b8SAriel Elior address, 502a1b469b8SAriel Elior GET_FIELD(details, QED_DORQ_ATTENTION_OPAQUE), 503b4149dc7SYuval Mintz GET_FIELD(details, QED_DORQ_ATTENTION_SIZE) * 4, 504a1b469b8SAriel Elior first_drop_reason, all_drops_reason); 505a1b469b8SAriel Elior 506a1b469b8SAriel Elior /* Clear the doorbell drop details and prepare for next drop */ 507a1b469b8SAriel Elior qed_wr(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS_REL, 0); 508a1b469b8SAriel Elior 509a1b469b8SAriel Elior /* Mark interrupt as handled (note: even if drop was due to a different 510a1b469b8SAriel Elior * reason than overflow we mark as handled) 511a1b469b8SAriel Elior */ 512a1b469b8SAriel Elior qed_wr(p_hwfn, 513a1b469b8SAriel Elior p_ptt, 514a1b469b8SAriel Elior DORQ_REG_INT_STS_WR, 515a1b469b8SAriel Elior DORQ_REG_INT_STS_DB_DROP | 516a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR); 517a1b469b8SAriel Elior 518a1b469b8SAriel Elior /* If there are no indications other than drop indications, success */ 519a1b469b8SAriel Elior if ((int_sts & ~(DORQ_REG_INT_STS_DB_DROP | 520a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR | 521a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) == 0) 522a1b469b8SAriel Elior return 0; 523b4149dc7SYuval Mintz } 524b4149dc7SYuval Mintz 525a1b469b8SAriel Elior /* Some other indication was present - non recoverable */ 526a1b469b8SAriel Elior DP_INFO(p_hwfn, "DORQ fatal attention\n"); 527a1b469b8SAriel Elior 528b4149dc7SYuval Mintz return -EINVAL; 529b4149dc7SYuval Mintz } 530b4149dc7SYuval Mintz 5310d72c2acSDenis Bolotin static int qed_dorq_attn_cb(struct qed_hwfn *p_hwfn) 5320d72c2acSDenis Bolotin { 5330d72c2acSDenis Bolotin p_hwfn->db_recovery_info.dorq_attn = true; 5340d72c2acSDenis Bolotin qed_dorq_attn_overflow(p_hwfn); 5350d72c2acSDenis Bolotin 5360d72c2acSDenis Bolotin return qed_dorq_attn_int_sts(p_hwfn); 5370d72c2acSDenis Bolotin } 5380d72c2acSDenis Bolotin 539d4476b8aSDenis Bolotin static void qed_dorq_attn_handler(struct qed_hwfn *p_hwfn) 540d4476b8aSDenis Bolotin { 541d4476b8aSDenis Bolotin if (p_hwfn->db_recovery_info.dorq_attn) 542d4476b8aSDenis Bolotin goto out; 543d4476b8aSDenis Bolotin 544d4476b8aSDenis Bolotin /* Call DORQ callback if the attention was missed */ 545d4476b8aSDenis Bolotin qed_dorq_attn_cb(p_hwfn); 546d4476b8aSDenis Bolotin out: 547d4476b8aSDenis Bolotin p_hwfn->db_recovery_info.dorq_attn = false; 548d4476b8aSDenis Bolotin } 549d4476b8aSDenis Bolotin 550ba36f718SMintz, Yuval /* Instead of major changes to the data-structure, we have a some 'special' 551ba36f718SMintz, Yuval * identifiers for sources that changed meaning between adapters. 552ba36f718SMintz, Yuval */ 553ba36f718SMintz, Yuval enum aeu_invert_reg_special_type { 554ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_0, 555ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_1, 556ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_2, 557ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_3, 558ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_MAX, 559ba36f718SMintz, Yuval }; 560ba36f718SMintz, Yuval 561ba36f718SMintz, Yuval static struct aeu_invert_reg_bit 562ba36f718SMintz, Yuval aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = { 563ba36f718SMintz, Yuval {"CNIG port 0", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 564ba36f718SMintz, Yuval {"CNIG port 1", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 565ba36f718SMintz, Yuval {"CNIG port 2", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 566ba36f718SMintz, Yuval {"CNIG port 3", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 567ba36f718SMintz, Yuval }; 568ba36f718SMintz, Yuval 5690d956e8aSYuval Mintz /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */ 5700d956e8aSYuval Mintz static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = { 5710d956e8aSYuval Mintz { 5720d956e8aSYuval Mintz { /* After Invert 1 */ 5730d956e8aSYuval Mintz {"GPIO0 function%d", 574b4149dc7SYuval Mintz (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 5750d956e8aSYuval Mintz } 5760d956e8aSYuval Mintz }, 5770d956e8aSYuval Mintz 5780d956e8aSYuval Mintz { 5790d956e8aSYuval Mintz { /* After Invert 2 */ 580b4149dc7SYuval Mintz {"PGLUE config_space", ATTENTION_SINGLE, 581b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 582b4149dc7SYuval Mintz {"PGLUE misc_flr", ATTENTION_SINGLE, 583b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 584b4149dc7SYuval Mintz {"PGLUE B RBC", ATTENTION_PAR_INT, 585666db486STomer Tayar qed_pglueb_rbc_attn_cb, BLOCK_PGLUE_B}, 586b4149dc7SYuval Mintz {"PGLUE misc_mctp", ATTENTION_SINGLE, 587b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 588b4149dc7SYuval Mintz {"Flash event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 589b4149dc7SYuval Mintz {"SMB event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 590b4149dc7SYuval Mintz {"Main Power", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 5910d956e8aSYuval Mintz {"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) | 592ff38577aSYuval Mintz (1 << ATTENTION_OFFSET_SHIFT), 593b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 5940d956e8aSYuval Mintz {"PCIE glue/PXP VPD %d", 595b4149dc7SYuval Mintz (16 << ATTENTION_LENGTH_SHIFT), NULL, BLOCK_PGLCS}, 5960d956e8aSYuval Mintz } 5970d956e8aSYuval Mintz }, 5980d956e8aSYuval Mintz 5990d956e8aSYuval Mintz { 6000d956e8aSYuval Mintz { /* After Invert 3 */ 6010d956e8aSYuval Mintz {"General Attention %d", 602b4149dc7SYuval Mintz (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 6030d956e8aSYuval Mintz } 6040d956e8aSYuval Mintz }, 6050d956e8aSYuval Mintz 6060d956e8aSYuval Mintz { 6070d956e8aSYuval Mintz { /* After Invert 4 */ 608ff38577aSYuval Mintz {"General Attention 32", ATTENTION_SINGLE, 609b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 6100d956e8aSYuval Mintz {"General Attention %d", 6110d956e8aSYuval Mintz (2 << ATTENTION_LENGTH_SHIFT) | 612b4149dc7SYuval Mintz (33 << ATTENTION_OFFSET_SHIFT), NULL, MAX_BLOCK_ID}, 613ff38577aSYuval Mintz {"General Attention 35", ATTENTION_SINGLE, 614b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 615ba36f718SMintz, Yuval {"NWS Parity", 616ba36f718SMintz, Yuval ATTENTION_PAR | ATTENTION_BB_DIFFERENT | 617ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_0), 618ba36f718SMintz, Yuval NULL, BLOCK_NWS}, 619ba36f718SMintz, Yuval {"NWS Interrupt", 620ba36f718SMintz, Yuval ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT | 621ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_1), 622ba36f718SMintz, Yuval NULL, BLOCK_NWS}, 623ba36f718SMintz, Yuval {"NWM Parity", 624ba36f718SMintz, Yuval ATTENTION_PAR | ATTENTION_BB_DIFFERENT | 625ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_2), 626ba36f718SMintz, Yuval NULL, BLOCK_NWM}, 627ba36f718SMintz, Yuval {"NWM Interrupt", 628ba36f718SMintz, Yuval ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT | 629ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_3), 630ba36f718SMintz, Yuval NULL, BLOCK_NWM}, 631b4149dc7SYuval Mintz {"MCP CPU", ATTENTION_SINGLE, 632b4149dc7SYuval Mintz qed_mcp_attn_cb, MAX_BLOCK_ID}, 633b4149dc7SYuval Mintz {"MCP Watchdog timer", ATTENTION_SINGLE, 634b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 635b4149dc7SYuval Mintz {"MCP M2P", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 636ff38577aSYuval Mintz {"AVS stop status ready", ATTENTION_SINGLE, 637b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 638b4149dc7SYuval Mintz {"MSTAT", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 639b4149dc7SYuval Mintz {"MSTAT per-path", ATTENTION_PAR_INT, 640b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 641ff38577aSYuval Mintz {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), 642b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 643b4149dc7SYuval Mintz {"NIG", ATTENTION_PAR_INT, NULL, BLOCK_NIG}, 644b4149dc7SYuval Mintz {"BMB/OPTE/MCP", ATTENTION_PAR_INT, NULL, BLOCK_BMB}, 645b4149dc7SYuval Mintz {"BTB", ATTENTION_PAR_INT, NULL, BLOCK_BTB}, 646b4149dc7SYuval Mintz {"BRB", ATTENTION_PAR_INT, NULL, BLOCK_BRB}, 647b4149dc7SYuval Mintz {"PRS", ATTENTION_PAR_INT, NULL, BLOCK_PRS}, 6480d956e8aSYuval Mintz } 6490d956e8aSYuval Mintz }, 6500d956e8aSYuval Mintz 6510d956e8aSYuval Mintz { 6520d956e8aSYuval Mintz { /* After Invert 5 */ 653b4149dc7SYuval Mintz {"SRC", ATTENTION_PAR_INT, NULL, BLOCK_SRC}, 654b4149dc7SYuval Mintz {"PB Client1", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB1}, 655b4149dc7SYuval Mintz {"PB Client2", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB2}, 656b4149dc7SYuval Mintz {"RPB", ATTENTION_PAR_INT, NULL, BLOCK_RPB}, 657b4149dc7SYuval Mintz {"PBF", ATTENTION_PAR_INT, NULL, BLOCK_PBF}, 658b4149dc7SYuval Mintz {"QM", ATTENTION_PAR_INT, NULL, BLOCK_QM}, 659b4149dc7SYuval Mintz {"TM", ATTENTION_PAR_INT, NULL, BLOCK_TM}, 660b4149dc7SYuval Mintz {"MCM", ATTENTION_PAR_INT, NULL, BLOCK_MCM}, 661b4149dc7SYuval Mintz {"MSDM", ATTENTION_PAR_INT, NULL, BLOCK_MSDM}, 662b4149dc7SYuval Mintz {"MSEM", ATTENTION_PAR_INT, NULL, BLOCK_MSEM}, 663b4149dc7SYuval Mintz {"PCM", ATTENTION_PAR_INT, NULL, BLOCK_PCM}, 664b4149dc7SYuval Mintz {"PSDM", ATTENTION_PAR_INT, NULL, BLOCK_PSDM}, 665b4149dc7SYuval Mintz {"PSEM", ATTENTION_PAR_INT, NULL, BLOCK_PSEM}, 666b4149dc7SYuval Mintz {"TCM", ATTENTION_PAR_INT, NULL, BLOCK_TCM}, 667b4149dc7SYuval Mintz {"TSDM", ATTENTION_PAR_INT, NULL, BLOCK_TSDM}, 668b4149dc7SYuval Mintz {"TSEM", ATTENTION_PAR_INT, NULL, BLOCK_TSEM}, 6690d956e8aSYuval Mintz } 6700d956e8aSYuval Mintz }, 6710d956e8aSYuval Mintz 6720d956e8aSYuval Mintz { 6730d956e8aSYuval Mintz { /* After Invert 6 */ 674b4149dc7SYuval Mintz {"UCM", ATTENTION_PAR_INT, NULL, BLOCK_UCM}, 675b4149dc7SYuval Mintz {"USDM", ATTENTION_PAR_INT, NULL, BLOCK_USDM}, 676b4149dc7SYuval Mintz {"USEM", ATTENTION_PAR_INT, NULL, BLOCK_USEM}, 677b4149dc7SYuval Mintz {"XCM", ATTENTION_PAR_INT, NULL, BLOCK_XCM}, 678b4149dc7SYuval Mintz {"XSDM", ATTENTION_PAR_INT, NULL, BLOCK_XSDM}, 679b4149dc7SYuval Mintz {"XSEM", ATTENTION_PAR_INT, NULL, BLOCK_XSEM}, 680b4149dc7SYuval Mintz {"YCM", ATTENTION_PAR_INT, NULL, BLOCK_YCM}, 681b4149dc7SYuval Mintz {"YSDM", ATTENTION_PAR_INT, NULL, BLOCK_YSDM}, 682b4149dc7SYuval Mintz {"YSEM", ATTENTION_PAR_INT, NULL, BLOCK_YSEM}, 683b4149dc7SYuval Mintz {"XYLD", ATTENTION_PAR_INT, NULL, BLOCK_XYLD}, 684b4149dc7SYuval Mintz {"TMLD", ATTENTION_PAR_INT, NULL, BLOCK_TMLD}, 685b4149dc7SYuval Mintz {"MYLD", ATTENTION_PAR_INT, NULL, BLOCK_MULD}, 686b4149dc7SYuval Mintz {"YULD", ATTENTION_PAR_INT, NULL, BLOCK_YULD}, 687b4149dc7SYuval Mintz {"DORQ", ATTENTION_PAR_INT, 688b4149dc7SYuval Mintz qed_dorq_attn_cb, BLOCK_DORQ}, 689b4149dc7SYuval Mintz {"DBG", ATTENTION_PAR_INT, NULL, BLOCK_DBG}, 690b4149dc7SYuval Mintz {"IPC", ATTENTION_PAR_INT, NULL, BLOCK_IPC}, 6910d956e8aSYuval Mintz } 6920d956e8aSYuval Mintz }, 6930d956e8aSYuval Mintz 6940d956e8aSYuval Mintz { 6950d956e8aSYuval Mintz { /* After Invert 7 */ 696b4149dc7SYuval Mintz {"CCFC", ATTENTION_PAR_INT, NULL, BLOCK_CCFC}, 697b4149dc7SYuval Mintz {"CDU", ATTENTION_PAR_INT, NULL, BLOCK_CDU}, 698b4149dc7SYuval Mintz {"DMAE", ATTENTION_PAR_INT, NULL, BLOCK_DMAE}, 699b4149dc7SYuval Mintz {"IGU", ATTENTION_PAR_INT, NULL, BLOCK_IGU}, 700b4149dc7SYuval Mintz {"ATC", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 701b4149dc7SYuval Mintz {"CAU", ATTENTION_PAR_INT, NULL, BLOCK_CAU}, 702b4149dc7SYuval Mintz {"PTU", ATTENTION_PAR_INT, NULL, BLOCK_PTU}, 703b4149dc7SYuval Mintz {"PRM", ATTENTION_PAR_INT, NULL, BLOCK_PRM}, 704b4149dc7SYuval Mintz {"TCFC", ATTENTION_PAR_INT, NULL, BLOCK_TCFC}, 705b4149dc7SYuval Mintz {"RDIF", ATTENTION_PAR_INT, NULL, BLOCK_RDIF}, 706b4149dc7SYuval Mintz {"TDIF", ATTENTION_PAR_INT, NULL, BLOCK_TDIF}, 707b4149dc7SYuval Mintz {"RSS", ATTENTION_PAR_INT, NULL, BLOCK_RSS}, 708b4149dc7SYuval Mintz {"MISC", ATTENTION_PAR_INT, NULL, BLOCK_MISC}, 709b4149dc7SYuval Mintz {"MISCS", ATTENTION_PAR_INT, NULL, BLOCK_MISCS}, 710b4149dc7SYuval Mintz {"PCIE", ATTENTION_PAR, NULL, BLOCK_PCIE}, 711b4149dc7SYuval Mintz {"Vaux PCI core", ATTENTION_SINGLE, NULL, BLOCK_PGLCS}, 712b4149dc7SYuval Mintz {"PSWRQ", ATTENTION_PAR_INT, NULL, BLOCK_PSWRQ}, 7130d956e8aSYuval Mintz } 7140d956e8aSYuval Mintz }, 7150d956e8aSYuval Mintz 7160d956e8aSYuval Mintz { 7170d956e8aSYuval Mintz { /* After Invert 8 */ 718b4149dc7SYuval Mintz {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, 719b4149dc7SYuval Mintz NULL, BLOCK_PSWRQ2}, 720b4149dc7SYuval Mintz {"PSWWR", ATTENTION_PAR_INT, NULL, BLOCK_PSWWR}, 721b4149dc7SYuval Mintz {"PSWWR (pci_clk)", ATTENTION_PAR_INT, 722b4149dc7SYuval Mintz NULL, BLOCK_PSWWR2}, 723b4149dc7SYuval Mintz {"PSWRD", ATTENTION_PAR_INT, NULL, BLOCK_PSWRD}, 724b4149dc7SYuval Mintz {"PSWRD (pci_clk)", ATTENTION_PAR_INT, 725b4149dc7SYuval Mintz NULL, BLOCK_PSWRD2}, 726b4149dc7SYuval Mintz {"PSWHST", ATTENTION_PAR_INT, 727b4149dc7SYuval Mintz qed_pswhst_attn_cb, BLOCK_PSWHST}, 728b4149dc7SYuval Mintz {"PSWHST (pci_clk)", ATTENTION_PAR_INT, 729b4149dc7SYuval Mintz NULL, BLOCK_PSWHST2}, 730b4149dc7SYuval Mintz {"GRC", ATTENTION_PAR_INT, 731b4149dc7SYuval Mintz qed_grc_attn_cb, BLOCK_GRC}, 732b4149dc7SYuval Mintz {"CPMU", ATTENTION_PAR_INT, NULL, BLOCK_CPMU}, 733b4149dc7SYuval Mintz {"NCSI", ATTENTION_PAR_INT, NULL, BLOCK_NCSI}, 734b4149dc7SYuval Mintz {"MSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 735b4149dc7SYuval Mintz {"PSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 736b4149dc7SYuval Mintz {"TSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 737b4149dc7SYuval Mintz {"USEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 738b4149dc7SYuval Mintz {"XSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 739b4149dc7SYuval Mintz {"YSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 740b4149dc7SYuval Mintz {"pxp_misc_mps", ATTENTION_PAR, NULL, BLOCK_PGLCS}, 741ff38577aSYuval Mintz {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, 742b4149dc7SYuval Mintz NULL, BLOCK_PGLCS}, 743b4149dc7SYuval Mintz {"PERST_B assertion", ATTENTION_SINGLE, 744b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 745ff38577aSYuval Mintz {"PERST_B deassertion", ATTENTION_SINGLE, 746b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 747ff38577aSYuval Mintz {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), 748b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 7490d956e8aSYuval Mintz } 7500d956e8aSYuval Mintz }, 7510d956e8aSYuval Mintz 7520d956e8aSYuval Mintz { 7530d956e8aSYuval Mintz { /* After Invert 9 */ 754b4149dc7SYuval Mintz {"MCP Latched memory", ATTENTION_PAR, 755b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 756ff38577aSYuval Mintz {"MCP Latched scratchpad cache", ATTENTION_SINGLE, 757b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 758b4149dc7SYuval Mintz {"MCP Latched ump_tx", ATTENTION_PAR, 759b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 760ff38577aSYuval Mintz {"MCP Latched scratchpad", ATTENTION_PAR, 761b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 762ff38577aSYuval Mintz {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT), 763b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 7640d956e8aSYuval Mintz } 7650d956e8aSYuval Mintz }, 7660d956e8aSYuval Mintz }; 7670d956e8aSYuval Mintz 768ba36f718SMintz, Yuval static struct aeu_invert_reg_bit * 769ba36f718SMintz, Yuval qed_int_aeu_translate(struct qed_hwfn *p_hwfn, 770ba36f718SMintz, Yuval struct aeu_invert_reg_bit *p_bit) 771ba36f718SMintz, Yuval { 772ba36f718SMintz, Yuval if (!QED_IS_BB(p_hwfn->cdev)) 773ba36f718SMintz, Yuval return p_bit; 774ba36f718SMintz, Yuval 775ba36f718SMintz, Yuval if (!(p_bit->flags & ATTENTION_BB_DIFFERENT)) 776ba36f718SMintz, Yuval return p_bit; 777ba36f718SMintz, Yuval 778ba36f718SMintz, Yuval return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >> 779ba36f718SMintz, Yuval ATTENTION_BB_SHIFT]; 780ba36f718SMintz, Yuval } 781ba36f718SMintz, Yuval 782ba36f718SMintz, Yuval static bool qed_int_is_parity_flag(struct qed_hwfn *p_hwfn, 783ba36f718SMintz, Yuval struct aeu_invert_reg_bit *p_bit) 784ba36f718SMintz, Yuval { 785ba36f718SMintz, Yuval return !!(qed_int_aeu_translate(p_hwfn, p_bit)->flags & 786ba36f718SMintz, Yuval ATTENTION_PARITY); 787ba36f718SMintz, Yuval } 788ba36f718SMintz, Yuval 789cc875c2eSYuval Mintz #define ATTN_STATE_BITS (0xfff) 790cc875c2eSYuval Mintz #define ATTN_BITS_MASKABLE (0x3ff) 791cc875c2eSYuval Mintz struct qed_sb_attn_info { 792cc875c2eSYuval Mintz /* Virtual & Physical address of the SB */ 793cc875c2eSYuval Mintz struct atten_status_block *sb_attn; 794cc875c2eSYuval Mintz dma_addr_t sb_phys; 795cc875c2eSYuval Mintz 796cc875c2eSYuval Mintz /* Last seen running index */ 797cc875c2eSYuval Mintz u16 index; 798cc875c2eSYuval Mintz 7990d956e8aSYuval Mintz /* A mask of the AEU bits resulting in a parity error */ 8000d956e8aSYuval Mintz u32 parity_mask[NUM_ATTN_REGS]; 8010d956e8aSYuval Mintz 8020d956e8aSYuval Mintz /* A pointer to the attention description structure */ 8030d956e8aSYuval Mintz struct aeu_invert_reg *p_aeu_desc; 8040d956e8aSYuval Mintz 805cc875c2eSYuval Mintz /* Previously asserted attentions, which are still unasserted */ 806cc875c2eSYuval Mintz u16 known_attn; 807cc875c2eSYuval Mintz 808cc875c2eSYuval Mintz /* Cleanup address for the link's general hw attention */ 809cc875c2eSYuval Mintz u32 mfw_attn_addr; 810cc875c2eSYuval Mintz }; 811cc875c2eSYuval Mintz 812cc875c2eSYuval Mintz static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn, 813cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb_desc) 814cc875c2eSYuval Mintz { 8151a635e48SYuval Mintz u16 rc = 0, index; 816cc875c2eSYuval Mintz 817cc875c2eSYuval Mintz index = le16_to_cpu(p_sb_desc->sb_attn->sb_index); 818cc875c2eSYuval Mintz if (p_sb_desc->index != index) { 819cc875c2eSYuval Mintz p_sb_desc->index = index; 820cc875c2eSYuval Mintz rc = QED_SB_ATT_IDX; 821cc875c2eSYuval Mintz } 822cc875c2eSYuval Mintz 823cc875c2eSYuval Mintz return rc; 824cc875c2eSYuval Mintz } 825cc875c2eSYuval Mintz 826cc875c2eSYuval Mintz /** 827cc875c2eSYuval Mintz * @brief qed_int_assertion - handles asserted attention bits 828cc875c2eSYuval Mintz * 829cc875c2eSYuval Mintz * @param p_hwfn 830cc875c2eSYuval Mintz * @param asserted_bits newly asserted bits 831cc875c2eSYuval Mintz * @return int 832cc875c2eSYuval Mintz */ 8331a635e48SYuval Mintz static int qed_int_assertion(struct qed_hwfn *p_hwfn, u16 asserted_bits) 834cc875c2eSYuval Mintz { 835cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 836cc875c2eSYuval Mintz u32 igu_mask; 837cc875c2eSYuval Mintz 838cc875c2eSYuval Mintz /* Mask the source of the attention in the IGU */ 8391a635e48SYuval Mintz igu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); 840cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n", 841cc875c2eSYuval Mintz igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE)); 842cc875c2eSYuval Mintz igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE); 843cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask); 844cc875c2eSYuval Mintz 845cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 846cc875c2eSYuval Mintz "inner known ATTN state: 0x%04x --> 0x%04x\n", 847cc875c2eSYuval Mintz sb_attn_sw->known_attn, 848cc875c2eSYuval Mintz sb_attn_sw->known_attn | asserted_bits); 849cc875c2eSYuval Mintz sb_attn_sw->known_attn |= asserted_bits; 850cc875c2eSYuval Mintz 851cc875c2eSYuval Mintz /* Handle MCP events */ 852cc875c2eSYuval Mintz if (asserted_bits & 0x100) { 853cc875c2eSYuval Mintz qed_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt); 854cc875c2eSYuval Mintz /* Clean the MCP attention */ 855cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 856cc875c2eSYuval Mintz sb_attn_sw->mfw_attn_addr, 0); 857cc875c2eSYuval Mintz } 858cc875c2eSYuval Mintz 859cc875c2eSYuval Mintz DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 860cc875c2eSYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 861cc875c2eSYuval Mintz ((IGU_CMD_ATTN_BIT_SET_UPPER - 862cc875c2eSYuval Mintz IGU_CMD_INT_ACK_BASE) << 3), 863cc875c2eSYuval Mintz (u32)asserted_bits); 864cc875c2eSYuval Mintz 865cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "set cmd IGU: 0x%04x\n", 866cc875c2eSYuval Mintz asserted_bits); 867cc875c2eSYuval Mintz 868cc875c2eSYuval Mintz return 0; 869cc875c2eSYuval Mintz } 870cc875c2eSYuval Mintz 8710ebbd1c8SMintz, Yuval static void qed_int_attn_print(struct qed_hwfn *p_hwfn, 8720ebbd1c8SMintz, Yuval enum block_id id, 8730ebbd1c8SMintz, Yuval enum dbg_attn_type type, bool b_clear) 874ff38577aSYuval Mintz { 8750ebbd1c8SMintz, Yuval struct dbg_attn_block_result attn_results; 8760ebbd1c8SMintz, Yuval enum dbg_status status; 877ff38577aSYuval Mintz 8780ebbd1c8SMintz, Yuval memset(&attn_results, 0, sizeof(attn_results)); 879ff38577aSYuval Mintz 8800ebbd1c8SMintz, Yuval status = qed_dbg_read_attn(p_hwfn, p_hwfn->p_dpc_ptt, id, type, 8810ebbd1c8SMintz, Yuval b_clear, &attn_results); 8820ebbd1c8SMintz, Yuval if (status != DBG_STATUS_OK) 883ff38577aSYuval Mintz DP_NOTICE(p_hwfn, 8840ebbd1c8SMintz, Yuval "Failed to parse attention information [status: %s]\n", 8850ebbd1c8SMintz, Yuval qed_dbg_get_status_str(status)); 8860ebbd1c8SMintz, Yuval else 8870ebbd1c8SMintz, Yuval qed_dbg_parse_attn(p_hwfn, &attn_results); 888ff38577aSYuval Mintz } 889ff38577aSYuval Mintz 890cc875c2eSYuval Mintz /** 8910d956e8aSYuval Mintz * @brief qed_int_deassertion_aeu_bit - handles the effects of a single 8920d956e8aSYuval Mintz * cause of the attention 8930d956e8aSYuval Mintz * 8940d956e8aSYuval Mintz * @param p_hwfn 8950d956e8aSYuval Mintz * @param p_aeu - descriptor of an AEU bit which caused the attention 8960d956e8aSYuval Mintz * @param aeu_en_reg - register offset of the AEU enable reg. which configured 8970d956e8aSYuval Mintz * this bit to this group. 8980d956e8aSYuval Mintz * @param bit_index - index of this bit in the aeu_en_reg 8990d956e8aSYuval Mintz * 9000d956e8aSYuval Mintz * @return int 9010d956e8aSYuval Mintz */ 9020d956e8aSYuval Mintz static int 9030d956e8aSYuval Mintz qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn, 9040d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_aeu, 9050d956e8aSYuval Mintz u32 aeu_en_reg, 9066010179dSMintz, Yuval const char *p_bit_name, u32 bitmask) 9070d956e8aSYuval Mintz { 9080ebbd1c8SMintz, Yuval bool b_fatal = false; 9090d956e8aSYuval Mintz int rc = -EINVAL; 910b4149dc7SYuval Mintz u32 val; 9110d956e8aSYuval Mintz 9120d956e8aSYuval Mintz DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n", 9136010179dSMintz, Yuval p_bit_name, bitmask); 9140d956e8aSYuval Mintz 915b4149dc7SYuval Mintz /* Call callback before clearing the interrupt status */ 916b4149dc7SYuval Mintz if (p_aeu->cb) { 917b4149dc7SYuval Mintz DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n", 9186010179dSMintz, Yuval p_bit_name); 919b4149dc7SYuval Mintz rc = p_aeu->cb(p_hwfn); 920b4149dc7SYuval Mintz } 921b4149dc7SYuval Mintz 9220ebbd1c8SMintz, Yuval if (rc) 9230ebbd1c8SMintz, Yuval b_fatal = true; 924ff38577aSYuval Mintz 9250ebbd1c8SMintz, Yuval /* Print HW block interrupt registers */ 9260ebbd1c8SMintz, Yuval if (p_aeu->block_index != MAX_BLOCK_ID) 9270ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, p_aeu->block_index, 9280ebbd1c8SMintz, Yuval ATTN_TYPE_INTERRUPT, !b_fatal); 929ff38577aSYuval Mintz 930ff38577aSYuval Mintz 931b4149dc7SYuval Mintz /* If the attention is benign, no need to prevent it */ 932b4149dc7SYuval Mintz if (!rc) 933b4149dc7SYuval Mintz goto out; 934b4149dc7SYuval Mintz 9350d956e8aSYuval Mintz /* Prevent this Attention from being asserted in the future */ 9360d956e8aSYuval Mintz val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 937b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & ~bitmask)); 9380d956e8aSYuval Mintz DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n", 9396010179dSMintz, Yuval p_bit_name); 9400d956e8aSYuval Mintz 941b4149dc7SYuval Mintz out: 9420d956e8aSYuval Mintz return rc; 9430d956e8aSYuval Mintz } 9440d956e8aSYuval Mintz 945ff38577aSYuval Mintz /** 946ff38577aSYuval Mintz * @brief qed_int_deassertion_parity - handle a single parity AEU source 947ff38577aSYuval Mintz * 948ff38577aSYuval Mintz * @param p_hwfn 949ff38577aSYuval Mintz * @param p_aeu - descriptor of an AEU bit which caused the parity 9509790c35eSMintz, Yuval * @param aeu_en_reg - address of the AEU enable register 951ff38577aSYuval Mintz * @param bit_index 952ff38577aSYuval Mintz */ 953ff38577aSYuval Mintz static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn, 954ff38577aSYuval Mintz struct aeu_invert_reg_bit *p_aeu, 9559790c35eSMintz, Yuval u32 aeu_en_reg, u8 bit_index) 956ff38577aSYuval Mintz { 9579790c35eSMintz, Yuval u32 block_id = p_aeu->block_index, mask, val; 958ff38577aSYuval Mintz 9599790c35eSMintz, Yuval DP_NOTICE(p_hwfn->cdev, 9609790c35eSMintz, Yuval "%s parity attention is set [address 0x%08x, bit %d]\n", 9619790c35eSMintz, Yuval p_aeu->bit_name, aeu_en_reg, bit_index); 962ff38577aSYuval Mintz 963ff38577aSYuval Mintz if (block_id != MAX_BLOCK_ID) { 9640ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, block_id, ATTN_TYPE_PARITY, false); 965ff38577aSYuval Mintz 966ff38577aSYuval Mintz /* In BB, there's a single parity bit for several blocks */ 967ff38577aSYuval Mintz if (block_id == BLOCK_BTB) { 9680ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, BLOCK_OPTE, 9690ebbd1c8SMintz, Yuval ATTN_TYPE_PARITY, false); 9700ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, BLOCK_MCP, 9710ebbd1c8SMintz, Yuval ATTN_TYPE_PARITY, false); 972ff38577aSYuval Mintz } 973ff38577aSYuval Mintz } 9749790c35eSMintz, Yuval 9759790c35eSMintz, Yuval /* Prevent this parity error from being re-asserted */ 9769790c35eSMintz, Yuval mask = ~BIT(bit_index); 9779790c35eSMintz, Yuval val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 9789790c35eSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask); 9799790c35eSMintz, Yuval DP_INFO(p_hwfn, "`%s' - Disabled future parity errors\n", 9809790c35eSMintz, Yuval p_aeu->bit_name); 981ff38577aSYuval Mintz } 982ff38577aSYuval Mintz 9830d956e8aSYuval Mintz /** 984cc875c2eSYuval Mintz * @brief - handles deassertion of previously asserted attentions. 985cc875c2eSYuval Mintz * 986cc875c2eSYuval Mintz * @param p_hwfn 987cc875c2eSYuval Mintz * @param deasserted_bits - newly deasserted bits 988cc875c2eSYuval Mintz * @return int 989cc875c2eSYuval Mintz * 990cc875c2eSYuval Mintz */ 991cc875c2eSYuval Mintz static int qed_int_deassertion(struct qed_hwfn *p_hwfn, 992cc875c2eSYuval Mintz u16 deasserted_bits) 993cc875c2eSYuval Mintz { 994cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 9959790c35eSMintz, Yuval u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask, aeu_en, en; 9960d956e8aSYuval Mintz u8 i, j, k, bit_idx; 9970d956e8aSYuval Mintz int rc = 0; 998cc875c2eSYuval Mintz 9990d956e8aSYuval Mintz /* Read the attention registers in the AEU */ 10000d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 10010d956e8aSYuval Mintz aeu_inv_arr[i] = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 10020d956e8aSYuval Mintz MISC_REG_AEU_AFTER_INVERT_1_IGU + 10030d956e8aSYuval Mintz i * 0x4); 10040d956e8aSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 10050d956e8aSYuval Mintz "Deasserted bits [%d]: %08x\n", 10060d956e8aSYuval Mintz i, aeu_inv_arr[i]); 10070d956e8aSYuval Mintz } 10080d956e8aSYuval Mintz 10090d956e8aSYuval Mintz /* Find parity attentions first */ 10100d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 10110d956e8aSYuval Mintz struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i]; 10120d956e8aSYuval Mintz u32 parities; 10130d956e8aSYuval Mintz 10149790c35eSMintz, Yuval aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + i * sizeof(u32); 10159790c35eSMintz, Yuval en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 10169790c35eSMintz, Yuval 10170d956e8aSYuval Mintz /* Skip register in which no parity bit is currently set */ 10180d956e8aSYuval Mintz parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en; 10190d956e8aSYuval Mintz if (!parities) 10200d956e8aSYuval Mintz continue; 10210d956e8aSYuval Mintz 10220d956e8aSYuval Mintz for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 10230d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j]; 10240d956e8aSYuval Mintz 1025ba36f718SMintz, Yuval if (qed_int_is_parity_flag(p_hwfn, p_bit) && 10261a635e48SYuval Mintz !!(parities & BIT(bit_idx))) 1027ff38577aSYuval Mintz qed_int_deassertion_parity(p_hwfn, p_bit, 10289790c35eSMintz, Yuval aeu_en, bit_idx); 10290d956e8aSYuval Mintz 10300d956e8aSYuval Mintz bit_idx += ATTENTION_LENGTH(p_bit->flags); 10310d956e8aSYuval Mintz } 10320d956e8aSYuval Mintz } 10330d956e8aSYuval Mintz 10340d956e8aSYuval Mintz /* Find non-parity cause for attention and act */ 10350d956e8aSYuval Mintz for (k = 0; k < MAX_ATTN_GRPS; k++) { 10360d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_aeu; 10370d956e8aSYuval Mintz 10380d956e8aSYuval Mintz /* Handle only groups whose attention is currently deasserted */ 10390d956e8aSYuval Mintz if (!(deasserted_bits & (1 << k))) 10400d956e8aSYuval Mintz continue; 10410d956e8aSYuval Mintz 10420d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 10439790c35eSMintz, Yuval u32 bits; 10449790c35eSMintz, Yuval 10459790c35eSMintz, Yuval aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + 10460d956e8aSYuval Mintz i * sizeof(u32) + 10470d956e8aSYuval Mintz k * sizeof(u32) * NUM_ATTN_REGS; 10480d956e8aSYuval Mintz 10490d956e8aSYuval Mintz en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 10500d956e8aSYuval Mintz bits = aeu_inv_arr[i] & en; 10510d956e8aSYuval Mintz 10520d956e8aSYuval Mintz /* Skip if no bit from this group is currently set */ 10530d956e8aSYuval Mintz if (!bits) 10540d956e8aSYuval Mintz continue; 10550d956e8aSYuval Mintz 10560d956e8aSYuval Mintz /* Find all set bits from current register which belong 10570d956e8aSYuval Mintz * to current group, making them responsible for the 10580d956e8aSYuval Mintz * previous assertion. 10590d956e8aSYuval Mintz */ 10600d956e8aSYuval Mintz for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 10616010179dSMintz, Yuval long unsigned int bitmask; 10620d956e8aSYuval Mintz u8 bit, bit_len; 10630d956e8aSYuval Mintz 10640d956e8aSYuval Mintz p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j]; 1065ba36f718SMintz, Yuval p_aeu = qed_int_aeu_translate(p_hwfn, p_aeu); 10660d956e8aSYuval Mintz 10670d956e8aSYuval Mintz bit = bit_idx; 10680d956e8aSYuval Mintz bit_len = ATTENTION_LENGTH(p_aeu->flags); 1069ba36f718SMintz, Yuval if (qed_int_is_parity_flag(p_hwfn, p_aeu)) { 10700d956e8aSYuval Mintz /* Skip Parity */ 10710d956e8aSYuval Mintz bit++; 10720d956e8aSYuval Mintz bit_len--; 10730d956e8aSYuval Mintz } 10740d956e8aSYuval Mintz 10750d956e8aSYuval Mintz bitmask = bits & (((1 << bit_len) - 1) << bit); 10766010179dSMintz, Yuval bitmask >>= bit; 10776010179dSMintz, Yuval 10780d956e8aSYuval Mintz if (bitmask) { 10796010179dSMintz, Yuval u32 flags = p_aeu->flags; 10806010179dSMintz, Yuval char bit_name[30]; 10816010179dSMintz, Yuval u8 num; 10826010179dSMintz, Yuval 10836010179dSMintz, Yuval num = (u8)find_first_bit(&bitmask, 10846010179dSMintz, Yuval bit_len); 10856010179dSMintz, Yuval 10866010179dSMintz, Yuval /* Some bits represent more than a 10876010179dSMintz, Yuval * a single interrupt. Correctly print 10886010179dSMintz, Yuval * their name. 10896010179dSMintz, Yuval */ 10906010179dSMintz, Yuval if (ATTENTION_LENGTH(flags) > 2 || 10916010179dSMintz, Yuval ((flags & ATTENTION_PAR_INT) && 10926010179dSMintz, Yuval ATTENTION_LENGTH(flags) > 1)) 10936010179dSMintz, Yuval snprintf(bit_name, 30, 10946010179dSMintz, Yuval p_aeu->bit_name, num); 10956010179dSMintz, Yuval else 10966010179dSMintz, Yuval strncpy(bit_name, 10976010179dSMintz, Yuval p_aeu->bit_name, 30); 10986010179dSMintz, Yuval 10996010179dSMintz, Yuval /* We now need to pass bitmask in its 11006010179dSMintz, Yuval * correct position. 11016010179dSMintz, Yuval */ 11026010179dSMintz, Yuval bitmask <<= bit; 11036010179dSMintz, Yuval 11040d956e8aSYuval Mintz /* Handle source of the attention */ 11050d956e8aSYuval Mintz qed_int_deassertion_aeu_bit(p_hwfn, 11060d956e8aSYuval Mintz p_aeu, 11070d956e8aSYuval Mintz aeu_en, 11086010179dSMintz, Yuval bit_name, 11090d956e8aSYuval Mintz bitmask); 11100d956e8aSYuval Mintz } 11110d956e8aSYuval Mintz 11120d956e8aSYuval Mintz bit_idx += ATTENTION_LENGTH(p_aeu->flags); 11130d956e8aSYuval Mintz } 11140d956e8aSYuval Mintz } 11150d956e8aSYuval Mintz } 1116cc875c2eSYuval Mintz 1117d4476b8aSDenis Bolotin /* Handle missed DORQ attention */ 1118d4476b8aSDenis Bolotin qed_dorq_attn_handler(p_hwfn); 1119d4476b8aSDenis Bolotin 1120cc875c2eSYuval Mintz /* Clear IGU indication for the deasserted bits */ 1121cc875c2eSYuval Mintz DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 1122cc875c2eSYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 1123cc875c2eSYuval Mintz ((IGU_CMD_ATTN_BIT_CLR_UPPER - 1124cc875c2eSYuval Mintz IGU_CMD_INT_ACK_BASE) << 3), 1125cc875c2eSYuval Mintz ~((u32)deasserted_bits)); 1126cc875c2eSYuval Mintz 1127cc875c2eSYuval Mintz /* Unmask deasserted attentions in IGU */ 11281a635e48SYuval Mintz aeu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); 1129cc875c2eSYuval Mintz aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE); 1130cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask); 1131cc875c2eSYuval Mintz 1132cc875c2eSYuval Mintz /* Clear deassertion from inner state */ 1133cc875c2eSYuval Mintz sb_attn_sw->known_attn &= ~deasserted_bits; 1134cc875c2eSYuval Mintz 11350d956e8aSYuval Mintz return rc; 1136cc875c2eSYuval Mintz } 1137cc875c2eSYuval Mintz 1138cc875c2eSYuval Mintz static int qed_int_attentions(struct qed_hwfn *p_hwfn) 1139cc875c2eSYuval Mintz { 1140cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn; 1141cc875c2eSYuval Mintz struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn; 1142cc875c2eSYuval Mintz u32 attn_bits = 0, attn_acks = 0; 1143cc875c2eSYuval Mintz u16 asserted_bits, deasserted_bits; 1144cc875c2eSYuval Mintz __le16 index; 1145cc875c2eSYuval Mintz int rc = 0; 1146cc875c2eSYuval Mintz 1147cc875c2eSYuval Mintz /* Read current attention bits/acks - safeguard against attentions 1148cc875c2eSYuval Mintz * by guaranting work on a synchronized timeframe 1149cc875c2eSYuval Mintz */ 1150cc875c2eSYuval Mintz do { 1151cc875c2eSYuval Mintz index = p_sb_attn->sb_index; 1152ed4eac20SDenis Bolotin /* finish reading index before the loop condition */ 1153ed4eac20SDenis Bolotin dma_rmb(); 1154cc875c2eSYuval Mintz attn_bits = le32_to_cpu(p_sb_attn->atten_bits); 1155cc875c2eSYuval Mintz attn_acks = le32_to_cpu(p_sb_attn->atten_ack); 1156cc875c2eSYuval Mintz } while (index != p_sb_attn->sb_index); 1157cc875c2eSYuval Mintz p_sb_attn->sb_index = index; 1158cc875c2eSYuval Mintz 1159cc875c2eSYuval Mintz /* Attention / Deassertion are meaningful (and in correct state) 1160cc875c2eSYuval Mintz * only when they differ and consistent with known state - deassertion 1161cc875c2eSYuval Mintz * when previous attention & current ack, and assertion when current 1162cc875c2eSYuval Mintz * attention with no previous attention 1163cc875c2eSYuval Mintz */ 1164cc875c2eSYuval Mintz asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) & 1165cc875c2eSYuval Mintz ~p_sb_attn_sw->known_attn; 1166cc875c2eSYuval Mintz deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) & 1167cc875c2eSYuval Mintz p_sb_attn_sw->known_attn; 1168cc875c2eSYuval Mintz 1169cc875c2eSYuval Mintz if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100)) { 1170cc875c2eSYuval Mintz DP_INFO(p_hwfn, 1171cc875c2eSYuval Mintz "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n", 1172cc875c2eSYuval Mintz index, attn_bits, attn_acks, asserted_bits, 1173cc875c2eSYuval Mintz deasserted_bits, p_sb_attn_sw->known_attn); 1174cc875c2eSYuval Mintz } else if (asserted_bits == 0x100) { 11751a635e48SYuval Mintz DP_INFO(p_hwfn, "MFW indication via attention\n"); 1176cc875c2eSYuval Mintz } else { 1177cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1178cc875c2eSYuval Mintz "MFW indication [deassertion]\n"); 1179cc875c2eSYuval Mintz } 1180cc875c2eSYuval Mintz 1181cc875c2eSYuval Mintz if (asserted_bits) { 1182cc875c2eSYuval Mintz rc = qed_int_assertion(p_hwfn, asserted_bits); 1183cc875c2eSYuval Mintz if (rc) 1184cc875c2eSYuval Mintz return rc; 1185cc875c2eSYuval Mintz } 1186cc875c2eSYuval Mintz 11871a635e48SYuval Mintz if (deasserted_bits) 1188cc875c2eSYuval Mintz rc = qed_int_deassertion(p_hwfn, deasserted_bits); 1189cc875c2eSYuval Mintz 1190cc875c2eSYuval Mintz return rc; 1191cc875c2eSYuval Mintz } 1192cc875c2eSYuval Mintz 1193cc875c2eSYuval Mintz static void qed_sb_ack_attn(struct qed_hwfn *p_hwfn, 11941a635e48SYuval Mintz void __iomem *igu_addr, u32 ack_cons) 1195cc875c2eSYuval Mintz { 1196cc875c2eSYuval Mintz struct igu_prod_cons_update igu_ack = { 0 }; 1197cc875c2eSYuval Mintz 1198cc875c2eSYuval Mintz igu_ack.sb_id_and_flags = 1199cc875c2eSYuval Mintz ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 1200cc875c2eSYuval Mintz (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 1201cc875c2eSYuval Mintz (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 1202cc875c2eSYuval Mintz (IGU_SEG_ACCESS_ATTN << 1203cc875c2eSYuval Mintz IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 1204cc875c2eSYuval Mintz 1205cc875c2eSYuval Mintz DIRECT_REG_WR(igu_addr, igu_ack.sb_id_and_flags); 1206cc875c2eSYuval Mintz 1207cc875c2eSYuval Mintz /* Both segments (interrupts & acks) are written to same place address; 1208cc875c2eSYuval Mintz * Need to guarantee all commands will be received (in-order) by HW. 1209cc875c2eSYuval Mintz */ 1210cc875c2eSYuval Mintz barrier(); 1211cc875c2eSYuval Mintz } 1212cc875c2eSYuval Mintz 1213fe56b9e6SYuval Mintz void qed_int_sp_dpc(unsigned long hwfn_cookie) 1214fe56b9e6SYuval Mintz { 1215fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = (struct qed_hwfn *)hwfn_cookie; 1216fe56b9e6SYuval Mintz struct qed_pi_info *pi_info = NULL; 1217cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn; 1218fe56b9e6SYuval Mintz struct qed_sb_info *sb_info; 1219fe56b9e6SYuval Mintz int arr_size; 1220fe56b9e6SYuval Mintz u16 rc = 0; 1221fe56b9e6SYuval Mintz 1222fe56b9e6SYuval Mintz if (!p_hwfn->p_sp_sb) { 1223fe56b9e6SYuval Mintz DP_ERR(p_hwfn->cdev, "DPC called - no p_sp_sb\n"); 1224fe56b9e6SYuval Mintz return; 1225fe56b9e6SYuval Mintz } 1226fe56b9e6SYuval Mintz 1227fe56b9e6SYuval Mintz sb_info = &p_hwfn->p_sp_sb->sb_info; 1228fe56b9e6SYuval Mintz arr_size = ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr); 1229fe56b9e6SYuval Mintz if (!sb_info) { 1230fe56b9e6SYuval Mintz DP_ERR(p_hwfn->cdev, 1231fe56b9e6SYuval Mintz "Status block is NULL - cannot ack interrupts\n"); 1232fe56b9e6SYuval Mintz return; 1233fe56b9e6SYuval Mintz } 1234fe56b9e6SYuval Mintz 1235cc875c2eSYuval Mintz if (!p_hwfn->p_sb_attn) { 1236cc875c2eSYuval Mintz DP_ERR(p_hwfn->cdev, "DPC called - no p_sb_attn"); 1237cc875c2eSYuval Mintz return; 1238cc875c2eSYuval Mintz } 1239cc875c2eSYuval Mintz sb_attn = p_hwfn->p_sb_attn; 1240cc875c2eSYuval Mintz 1241fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "DPC Called! (hwfn %p %d)\n", 1242fe56b9e6SYuval Mintz p_hwfn, p_hwfn->my_id); 1243fe56b9e6SYuval Mintz 1244fe56b9e6SYuval Mintz /* Disable ack for def status block. Required both for msix + 1245fe56b9e6SYuval Mintz * inta in non-mask mode, in inta does no harm. 1246fe56b9e6SYuval Mintz */ 1247fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_DISABLE, 0); 1248fe56b9e6SYuval Mintz 1249fe56b9e6SYuval Mintz /* Gather Interrupts/Attentions information */ 1250fe56b9e6SYuval Mintz if (!sb_info->sb_virt) { 12511a635e48SYuval Mintz DP_ERR(p_hwfn->cdev, 1252fe56b9e6SYuval Mintz "Interrupt Status block is NULL - cannot check for new interrupts!\n"); 1253fe56b9e6SYuval Mintz } else { 1254fe56b9e6SYuval Mintz u32 tmp_index = sb_info->sb_ack; 1255fe56b9e6SYuval Mintz 1256fe56b9e6SYuval Mintz rc = qed_sb_update_sb_idx(sb_info); 1257fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 1258fe56b9e6SYuval Mintz "Interrupt indices: 0x%08x --> 0x%08x\n", 1259fe56b9e6SYuval Mintz tmp_index, sb_info->sb_ack); 1260fe56b9e6SYuval Mintz } 1261fe56b9e6SYuval Mintz 1262cc875c2eSYuval Mintz if (!sb_attn || !sb_attn->sb_attn) { 12631a635e48SYuval Mintz DP_ERR(p_hwfn->cdev, 1264cc875c2eSYuval Mintz "Attentions Status block is NULL - cannot check for new attentions!\n"); 1265cc875c2eSYuval Mintz } else { 1266cc875c2eSYuval Mintz u16 tmp_index = sb_attn->index; 1267cc875c2eSYuval Mintz 1268cc875c2eSYuval Mintz rc |= qed_attn_update_idx(p_hwfn, sb_attn); 1269cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 1270cc875c2eSYuval Mintz "Attention indices: 0x%08x --> 0x%08x\n", 1271cc875c2eSYuval Mintz tmp_index, sb_attn->index); 1272cc875c2eSYuval Mintz } 1273cc875c2eSYuval Mintz 1274fe56b9e6SYuval Mintz /* Check if we expect interrupts at this time. if not just ack them */ 1275fe56b9e6SYuval Mintz if (!(rc & QED_SB_EVENT_MASK)) { 1276fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1277fe56b9e6SYuval Mintz return; 1278fe56b9e6SYuval Mintz } 1279fe56b9e6SYuval Mintz 1280fe56b9e6SYuval Mintz /* Check the validity of the DPC ptt. If not ack interrupts and fail */ 1281fe56b9e6SYuval Mintz if (!p_hwfn->p_dpc_ptt) { 1282fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn->cdev, "Failed to allocate PTT\n"); 1283fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1284fe56b9e6SYuval Mintz return; 1285fe56b9e6SYuval Mintz } 1286fe56b9e6SYuval Mintz 1287cc875c2eSYuval Mintz if (rc & QED_SB_ATT_IDX) 1288cc875c2eSYuval Mintz qed_int_attentions(p_hwfn); 1289cc875c2eSYuval Mintz 1290fe56b9e6SYuval Mintz if (rc & QED_SB_IDX) { 1291fe56b9e6SYuval Mintz int pi; 1292fe56b9e6SYuval Mintz 1293fe56b9e6SYuval Mintz /* Look for a free index */ 1294fe56b9e6SYuval Mintz for (pi = 0; pi < arr_size; pi++) { 1295fe56b9e6SYuval Mintz pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi]; 1296fe56b9e6SYuval Mintz if (pi_info->comp_cb) 1297fe56b9e6SYuval Mintz pi_info->comp_cb(p_hwfn, pi_info->cookie); 1298fe56b9e6SYuval Mintz } 1299fe56b9e6SYuval Mintz } 1300fe56b9e6SYuval Mintz 1301cc875c2eSYuval Mintz if (sb_attn && (rc & QED_SB_ATT_IDX)) 1302cc875c2eSYuval Mintz /* This should be done before the interrupts are enabled, 1303cc875c2eSYuval Mintz * since otherwise a new attention will be generated. 1304cc875c2eSYuval Mintz */ 1305cc875c2eSYuval Mintz qed_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index); 1306cc875c2eSYuval Mintz 1307fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1308fe56b9e6SYuval Mintz } 1309fe56b9e6SYuval Mintz 1310cc875c2eSYuval Mintz static void qed_int_sb_attn_free(struct qed_hwfn *p_hwfn) 1311cc875c2eSYuval Mintz { 1312cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb = p_hwfn->p_sb_attn; 1313cc875c2eSYuval Mintz 13144ac801b7SYuval Mintz if (!p_sb) 13154ac801b7SYuval Mintz return; 13164ac801b7SYuval Mintz 1317cc875c2eSYuval Mintz if (p_sb->sb_attn) 13184ac801b7SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1319cc875c2eSYuval Mintz SB_ATTN_ALIGNED_SIZE(p_hwfn), 13201a635e48SYuval Mintz p_sb->sb_attn, p_sb->sb_phys); 1321cc875c2eSYuval Mintz kfree(p_sb); 13223587cb87STomer Tayar p_hwfn->p_sb_attn = NULL; 1323cc875c2eSYuval Mintz } 1324cc875c2eSYuval Mintz 1325cc875c2eSYuval Mintz static void qed_int_sb_attn_setup(struct qed_hwfn *p_hwfn, 1326cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1327cc875c2eSYuval Mintz { 1328cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 1329cc875c2eSYuval Mintz 1330cc875c2eSYuval Mintz memset(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn)); 1331cc875c2eSYuval Mintz 1332cc875c2eSYuval Mintz sb_info->index = 0; 1333cc875c2eSYuval Mintz sb_info->known_attn = 0; 1334cc875c2eSYuval Mintz 1335cc875c2eSYuval Mintz /* Configure Attention Status Block in IGU */ 1336cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L, 1337cc875c2eSYuval Mintz lower_32_bits(p_hwfn->p_sb_attn->sb_phys)); 1338cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H, 1339cc875c2eSYuval Mintz upper_32_bits(p_hwfn->p_sb_attn->sb_phys)); 1340cc875c2eSYuval Mintz } 1341cc875c2eSYuval Mintz 1342cc875c2eSYuval Mintz static void qed_int_sb_attn_init(struct qed_hwfn *p_hwfn, 1343cc875c2eSYuval Mintz struct qed_ptt *p_ptt, 13441a635e48SYuval Mintz void *sb_virt_addr, dma_addr_t sb_phy_addr) 1345cc875c2eSYuval Mintz { 1346cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 13470d956e8aSYuval Mintz int i, j, k; 1348cc875c2eSYuval Mintz 1349cc875c2eSYuval Mintz sb_info->sb_attn = sb_virt_addr; 1350cc875c2eSYuval Mintz sb_info->sb_phys = sb_phy_addr; 1351cc875c2eSYuval Mintz 13520d956e8aSYuval Mintz /* Set the pointer to the AEU descriptors */ 13530d956e8aSYuval Mintz sb_info->p_aeu_desc = aeu_descs; 13540d956e8aSYuval Mintz 13550d956e8aSYuval Mintz /* Calculate Parity Masks */ 13560d956e8aSYuval Mintz memset(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS); 13570d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 13580d956e8aSYuval Mintz /* j is array index, k is bit index */ 13590d956e8aSYuval Mintz for (j = 0, k = 0; k < 32; j++) { 1360ba36f718SMintz, Yuval struct aeu_invert_reg_bit *p_aeu; 13610d956e8aSYuval Mintz 1362ba36f718SMintz, Yuval p_aeu = &aeu_descs[i].bits[j]; 1363ba36f718SMintz, Yuval if (qed_int_is_parity_flag(p_hwfn, p_aeu)) 13640d956e8aSYuval Mintz sb_info->parity_mask[i] |= 1 << k; 13650d956e8aSYuval Mintz 1366ba36f718SMintz, Yuval k += ATTENTION_LENGTH(p_aeu->flags); 13670d956e8aSYuval Mintz } 13680d956e8aSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 13690d956e8aSYuval Mintz "Attn Mask [Reg %d]: 0x%08x\n", 13700d956e8aSYuval Mintz i, sb_info->parity_mask[i]); 13710d956e8aSYuval Mintz } 13720d956e8aSYuval Mintz 1373cc875c2eSYuval Mintz /* Set the address of cleanup for the mcp attention */ 1374cc875c2eSYuval Mintz sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) + 1375cc875c2eSYuval Mintz MISC_REG_AEU_GENERAL_ATTN_0; 1376cc875c2eSYuval Mintz 1377cc875c2eSYuval Mintz qed_int_sb_attn_setup(p_hwfn, p_ptt); 1378cc875c2eSYuval Mintz } 1379cc875c2eSYuval Mintz 1380cc875c2eSYuval Mintz static int qed_int_sb_attn_alloc(struct qed_hwfn *p_hwfn, 1381cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1382cc875c2eSYuval Mintz { 1383cc875c2eSYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 1384cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb; 1385cc875c2eSYuval Mintz dma_addr_t p_phys = 0; 13861a635e48SYuval Mintz void *p_virt; 1387cc875c2eSYuval Mintz 1388cc875c2eSYuval Mintz /* SB struct */ 138960fffb3bSYuval Mintz p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 13902591c280SJoe Perches if (!p_sb) 1391cc875c2eSYuval Mintz return -ENOMEM; 1392cc875c2eSYuval Mintz 1393cc875c2eSYuval Mintz /* SB ring */ 1394cc875c2eSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 1395cc875c2eSYuval Mintz SB_ATTN_ALIGNED_SIZE(p_hwfn), 1396cc875c2eSYuval Mintz &p_phys, GFP_KERNEL); 1397cc875c2eSYuval Mintz 1398cc875c2eSYuval Mintz if (!p_virt) { 1399cc875c2eSYuval Mintz kfree(p_sb); 1400cc875c2eSYuval Mintz return -ENOMEM; 1401cc875c2eSYuval Mintz } 1402cc875c2eSYuval Mintz 1403cc875c2eSYuval Mintz /* Attention setup */ 1404cc875c2eSYuval Mintz p_hwfn->p_sb_attn = p_sb; 1405cc875c2eSYuval Mintz qed_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys); 1406cc875c2eSYuval Mintz 1407cc875c2eSYuval Mintz return 0; 1408cc875c2eSYuval Mintz } 1409cc875c2eSYuval Mintz 1410fe56b9e6SYuval Mintz /* coalescing timeout = timeset << (timer_res + 1) */ 1411fe56b9e6SYuval Mintz #define QED_CAU_DEF_RX_USECS 24 1412fe56b9e6SYuval Mintz #define QED_CAU_DEF_TX_USECS 48 1413fe56b9e6SYuval Mintz 1414fe56b9e6SYuval Mintz void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn, 1415fe56b9e6SYuval Mintz struct cau_sb_entry *p_sb_entry, 14161a635e48SYuval Mintz u8 pf_id, u16 vf_number, u8 vf_valid) 1417fe56b9e6SYuval Mintz { 14184ac801b7SYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 1419fe56b9e6SYuval Mintz u32 cau_state; 1420722003acSSudarsana Reddy Kalluru u8 timer_res; 1421fe56b9e6SYuval Mintz 1422fe56b9e6SYuval Mintz memset(p_sb_entry, 0, sizeof(*p_sb_entry)); 1423fe56b9e6SYuval Mintz 1424fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id); 1425fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number); 1426fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid); 1427fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F); 1428fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F); 1429fe56b9e6SYuval Mintz 1430fe56b9e6SYuval Mintz cau_state = CAU_HC_DISABLE_STATE; 1431fe56b9e6SYuval Mintz 14324ac801b7SYuval Mintz if (cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 1433fe56b9e6SYuval Mintz cau_state = CAU_HC_ENABLE_STATE; 14344ac801b7SYuval Mintz if (!cdev->rx_coalesce_usecs) 14354ac801b7SYuval Mintz cdev->rx_coalesce_usecs = QED_CAU_DEF_RX_USECS; 14364ac801b7SYuval Mintz if (!cdev->tx_coalesce_usecs) 14374ac801b7SYuval Mintz cdev->tx_coalesce_usecs = QED_CAU_DEF_TX_USECS; 1438fe56b9e6SYuval Mintz } 1439fe56b9e6SYuval Mintz 1440722003acSSudarsana Reddy Kalluru /* Coalesce = (timeset << timer-res), timeset is 7bit wide */ 1441722003acSSudarsana Reddy Kalluru if (cdev->rx_coalesce_usecs <= 0x7F) 1442722003acSSudarsana Reddy Kalluru timer_res = 0; 1443722003acSSudarsana Reddy Kalluru else if (cdev->rx_coalesce_usecs <= 0xFF) 1444722003acSSudarsana Reddy Kalluru timer_res = 1; 1445722003acSSudarsana Reddy Kalluru else 1446722003acSSudarsana Reddy Kalluru timer_res = 2; 1447722003acSSudarsana Reddy Kalluru SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 1448722003acSSudarsana Reddy Kalluru 1449722003acSSudarsana Reddy Kalluru if (cdev->tx_coalesce_usecs <= 0x7F) 1450722003acSSudarsana Reddy Kalluru timer_res = 0; 1451722003acSSudarsana Reddy Kalluru else if (cdev->tx_coalesce_usecs <= 0xFF) 1452722003acSSudarsana Reddy Kalluru timer_res = 1; 1453722003acSSudarsana Reddy Kalluru else 1454722003acSSudarsana Reddy Kalluru timer_res = 2; 1455722003acSSudarsana Reddy Kalluru SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 1456722003acSSudarsana Reddy Kalluru 1457fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state); 1458fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state); 1459fe56b9e6SYuval Mintz } 1460fe56b9e6SYuval Mintz 14618befd73cSMintz, Yuval static void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn, 14628befd73cSMintz, Yuval struct qed_ptt *p_ptt, 14638befd73cSMintz, Yuval u16 igu_sb_id, 14648befd73cSMintz, Yuval u32 pi_index, 14658befd73cSMintz, Yuval enum qed_coalescing_fsm coalescing_fsm, 14668befd73cSMintz, Yuval u8 timeset) 14678befd73cSMintz, Yuval { 14688befd73cSMintz, Yuval struct cau_pi_entry pi_entry; 14698befd73cSMintz, Yuval u32 sb_offset, pi_offset; 14708befd73cSMintz, Yuval 14718befd73cSMintz, Yuval if (IS_VF(p_hwfn->cdev)) 14728befd73cSMintz, Yuval return; 14738befd73cSMintz, Yuval 147421dd79e8STomer Tayar sb_offset = igu_sb_id * PIS_PER_SB_E4; 14758befd73cSMintz, Yuval memset(&pi_entry, 0, sizeof(struct cau_pi_entry)); 14768befd73cSMintz, Yuval 14778befd73cSMintz, Yuval SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset); 14788befd73cSMintz, Yuval if (coalescing_fsm == QED_COAL_RX_STATE_MACHINE) 14798befd73cSMintz, Yuval SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0); 14808befd73cSMintz, Yuval else 14818befd73cSMintz, Yuval SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1); 14828befd73cSMintz, Yuval 14838befd73cSMintz, Yuval pi_offset = sb_offset + pi_index; 14848befd73cSMintz, Yuval if (p_hwfn->hw_init_done) { 14858befd73cSMintz, Yuval qed_wr(p_hwfn, p_ptt, 14868befd73cSMintz, Yuval CAU_REG_PI_MEMORY + pi_offset * sizeof(u32), 14878befd73cSMintz, Yuval *((u32 *)&(pi_entry))); 14888befd73cSMintz, Yuval } else { 14898befd73cSMintz, Yuval STORE_RT_REG(p_hwfn, 14908befd73cSMintz, Yuval CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset, 14918befd73cSMintz, Yuval *((u32 *)&(pi_entry))); 14928befd73cSMintz, Yuval } 14938befd73cSMintz, Yuval } 14948befd73cSMintz, Yuval 1495fe56b9e6SYuval Mintz void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn, 1496fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1497fe56b9e6SYuval Mintz dma_addr_t sb_phys, 14981a635e48SYuval Mintz u16 igu_sb_id, u16 vf_number, u8 vf_valid) 1499fe56b9e6SYuval Mintz { 1500fe56b9e6SYuval Mintz struct cau_sb_entry sb_entry; 1501fe56b9e6SYuval Mintz 1502fe56b9e6SYuval Mintz qed_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id, 1503fe56b9e6SYuval Mintz vf_number, vf_valid); 1504fe56b9e6SYuval Mintz 1505fe56b9e6SYuval Mintz if (p_hwfn->hw_init_done) { 15060a0c5d3bSYuval Mintz /* Wide-bus, initialize via DMAE */ 15070a0c5d3bSYuval Mintz u64 phys_addr = (u64)sb_phys; 1508fe56b9e6SYuval Mintz 15090a0c5d3bSYuval Mintz qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&phys_addr, 15100a0c5d3bSYuval Mintz CAU_REG_SB_ADDR_MEMORY + 151183bf76e3SMichal Kalderon igu_sb_id * sizeof(u64), 2, NULL); 15120a0c5d3bSYuval Mintz qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&sb_entry, 15130a0c5d3bSYuval Mintz CAU_REG_SB_VAR_MEMORY + 151483bf76e3SMichal Kalderon igu_sb_id * sizeof(u64), 2, NULL); 1515fe56b9e6SYuval Mintz } else { 1516fe56b9e6SYuval Mintz /* Initialize Status Block Address */ 1517fe56b9e6SYuval Mintz STORE_RT_REG_AGG(p_hwfn, 1518fe56b9e6SYuval Mintz CAU_REG_SB_ADDR_MEMORY_RT_OFFSET + 1519fe56b9e6SYuval Mintz igu_sb_id * 2, 1520fe56b9e6SYuval Mintz sb_phys); 1521fe56b9e6SYuval Mintz 1522fe56b9e6SYuval Mintz STORE_RT_REG_AGG(p_hwfn, 1523fe56b9e6SYuval Mintz CAU_REG_SB_VAR_MEMORY_RT_OFFSET + 1524fe56b9e6SYuval Mintz igu_sb_id * 2, 1525fe56b9e6SYuval Mintz sb_entry); 1526fe56b9e6SYuval Mintz } 1527fe56b9e6SYuval Mintz 1528fe56b9e6SYuval Mintz /* Configure pi coalescing if set */ 1529fe56b9e6SYuval Mintz if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 1530b5a9ee7cSAriel Elior u8 num_tc = p_hwfn->hw_info.num_hw_tc; 1531722003acSSudarsana Reddy Kalluru u8 timeset, timer_res; 1532b5a9ee7cSAriel Elior u8 i; 1533fe56b9e6SYuval Mintz 1534722003acSSudarsana Reddy Kalluru /* timeset = (coalesce >> timer-res), timeset is 7bit wide */ 1535722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->rx_coalesce_usecs <= 0x7F) 1536722003acSSudarsana Reddy Kalluru timer_res = 0; 1537722003acSSudarsana Reddy Kalluru else if (p_hwfn->cdev->rx_coalesce_usecs <= 0xFF) 1538722003acSSudarsana Reddy Kalluru timer_res = 1; 1539722003acSSudarsana Reddy Kalluru else 1540722003acSSudarsana Reddy Kalluru timer_res = 2; 1541722003acSSudarsana Reddy Kalluru timeset = (u8)(p_hwfn->cdev->rx_coalesce_usecs >> timer_res); 1542fe56b9e6SYuval Mintz qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI, 15431a635e48SYuval Mintz QED_COAL_RX_STATE_MACHINE, timeset); 1544fe56b9e6SYuval Mintz 1545722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->tx_coalesce_usecs <= 0x7F) 1546722003acSSudarsana Reddy Kalluru timer_res = 0; 1547722003acSSudarsana Reddy Kalluru else if (p_hwfn->cdev->tx_coalesce_usecs <= 0xFF) 1548722003acSSudarsana Reddy Kalluru timer_res = 1; 1549722003acSSudarsana Reddy Kalluru else 1550722003acSSudarsana Reddy Kalluru timer_res = 2; 1551722003acSSudarsana Reddy Kalluru timeset = (u8)(p_hwfn->cdev->tx_coalesce_usecs >> timer_res); 1552fe56b9e6SYuval Mintz for (i = 0; i < num_tc; i++) { 1553fe56b9e6SYuval Mintz qed_int_cau_conf_pi(p_hwfn, p_ptt, 1554fe56b9e6SYuval Mintz igu_sb_id, TX_PI(i), 1555fe56b9e6SYuval Mintz QED_COAL_TX_STATE_MACHINE, 1556fe56b9e6SYuval Mintz timeset); 1557fe56b9e6SYuval Mintz } 1558fe56b9e6SYuval Mintz } 1559fe56b9e6SYuval Mintz } 1560fe56b9e6SYuval Mintz 1561fe56b9e6SYuval Mintz void qed_int_sb_setup(struct qed_hwfn *p_hwfn, 15621a635e48SYuval Mintz struct qed_ptt *p_ptt, struct qed_sb_info *sb_info) 1563fe56b9e6SYuval Mintz { 1564fe56b9e6SYuval Mintz /* zero status block and ack counter */ 1565fe56b9e6SYuval Mintz sb_info->sb_ack = 0; 1566fe56b9e6SYuval Mintz memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 1567fe56b9e6SYuval Mintz 15681408cc1fSYuval Mintz if (IS_PF(p_hwfn->cdev)) 1569fe56b9e6SYuval Mintz qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys, 1570fe56b9e6SYuval Mintz sb_info->igu_sb_id, 0, 0); 1571fe56b9e6SYuval Mintz } 1572fe56b9e6SYuval Mintz 157309b6b147SMintz, Yuval struct qed_igu_block *qed_get_igu_free_sb(struct qed_hwfn *p_hwfn, bool b_is_pf) 157409b6b147SMintz, Yuval { 157509b6b147SMintz, Yuval struct qed_igu_block *p_block; 157609b6b147SMintz, Yuval u16 igu_id; 157709b6b147SMintz, Yuval 157809b6b147SMintz, Yuval for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); 157909b6b147SMintz, Yuval igu_id++) { 158009b6b147SMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id]; 158109b6b147SMintz, Yuval 158209b6b147SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID) || 158309b6b147SMintz, Yuval !(p_block->status & QED_IGU_STATUS_FREE)) 158409b6b147SMintz, Yuval continue; 158509b6b147SMintz, Yuval 158609b6b147SMintz, Yuval if (!!(p_block->status & QED_IGU_STATUS_PF) == b_is_pf) 158709b6b147SMintz, Yuval return p_block; 158809b6b147SMintz, Yuval } 158909b6b147SMintz, Yuval 159009b6b147SMintz, Yuval return NULL; 159109b6b147SMintz, Yuval } 159209b6b147SMintz, Yuval 1593a333f7f3SMintz, Yuval static u16 qed_get_pf_igu_sb_id(struct qed_hwfn *p_hwfn, u16 vector_id) 1594a333f7f3SMintz, Yuval { 1595a333f7f3SMintz, Yuval struct qed_igu_block *p_block; 1596a333f7f3SMintz, Yuval u16 igu_id; 1597a333f7f3SMintz, Yuval 1598a333f7f3SMintz, Yuval for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); 1599a333f7f3SMintz, Yuval igu_id++) { 1600a333f7f3SMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id]; 1601a333f7f3SMintz, Yuval 1602a333f7f3SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID) || 1603a333f7f3SMintz, Yuval !p_block->is_pf || 1604a333f7f3SMintz, Yuval p_block->vector_number != vector_id) 1605a333f7f3SMintz, Yuval continue; 1606a333f7f3SMintz, Yuval 1607a333f7f3SMintz, Yuval return igu_id; 1608a333f7f3SMintz, Yuval } 1609a333f7f3SMintz, Yuval 1610a333f7f3SMintz, Yuval return QED_SB_INVALID_IDX; 1611a333f7f3SMintz, Yuval } 1612a333f7f3SMintz, Yuval 161350a20714SMintz, Yuval u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id) 1614fe56b9e6SYuval Mintz { 1615fe56b9e6SYuval Mintz u16 igu_sb_id; 1616fe56b9e6SYuval Mintz 1617fe56b9e6SYuval Mintz /* Assuming continuous set of IGU SBs dedicated for given PF */ 1618fe56b9e6SYuval Mintz if (sb_id == QED_SP_SB_ID) 1619fe56b9e6SYuval Mintz igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id; 16201408cc1fSYuval Mintz else if (IS_PF(p_hwfn->cdev)) 1621a333f7f3SMintz, Yuval igu_sb_id = qed_get_pf_igu_sb_id(p_hwfn, sb_id + 1); 16221408cc1fSYuval Mintz else 16231408cc1fSYuval Mintz igu_sb_id = qed_vf_get_igu_sb_id(p_hwfn, sb_id); 1624fe56b9e6SYuval Mintz 1625525ef5c0SYuval Mintz if (sb_id == QED_SP_SB_ID) 1626525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1627525ef5c0SYuval Mintz "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id); 1628525ef5c0SYuval Mintz else 1629525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1630525ef5c0SYuval Mintz "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id); 1631fe56b9e6SYuval Mintz 1632fe56b9e6SYuval Mintz return igu_sb_id; 1633fe56b9e6SYuval Mintz } 1634fe56b9e6SYuval Mintz 1635fe56b9e6SYuval Mintz int qed_int_sb_init(struct qed_hwfn *p_hwfn, 1636fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1637fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 16381a635e48SYuval Mintz void *sb_virt_addr, dma_addr_t sb_phy_addr, u16 sb_id) 1639fe56b9e6SYuval Mintz { 1640fe56b9e6SYuval Mintz sb_info->sb_virt = sb_virt_addr; 1641fe56b9e6SYuval Mintz sb_info->sb_phys = sb_phy_addr; 1642fe56b9e6SYuval Mintz 1643fe56b9e6SYuval Mintz sb_info->igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id); 1644fe56b9e6SYuval Mintz 1645fe56b9e6SYuval Mintz if (sb_id != QED_SP_SB_ID) { 164650a20714SMintz, Yuval if (IS_PF(p_hwfn->cdev)) { 164750a20714SMintz, Yuval struct qed_igu_info *p_info; 164850a20714SMintz, Yuval struct qed_igu_block *p_block; 164950a20714SMintz, Yuval 165050a20714SMintz, Yuval p_info = p_hwfn->hw_info.p_igu_info; 165150a20714SMintz, Yuval p_block = &p_info->entry[sb_info->igu_sb_id]; 165250a20714SMintz, Yuval 165350a20714SMintz, Yuval p_block->sb_info = sb_info; 165450a20714SMintz, Yuval p_block->status &= ~QED_IGU_STATUS_FREE; 165550a20714SMintz, Yuval p_info->usage.free_cnt--; 165650a20714SMintz, Yuval } else { 165750a20714SMintz, Yuval qed_vf_set_sb_info(p_hwfn, sb_id, sb_info); 165850a20714SMintz, Yuval } 1659fe56b9e6SYuval Mintz } 1660fe56b9e6SYuval Mintz 1661fe56b9e6SYuval Mintz sb_info->cdev = p_hwfn->cdev; 1662fe56b9e6SYuval Mintz 1663fe56b9e6SYuval Mintz /* The igu address will hold the absolute address that needs to be 1664fe56b9e6SYuval Mintz * written to for a specific status block 1665fe56b9e6SYuval Mintz */ 16661408cc1fSYuval Mintz if (IS_PF(p_hwfn->cdev)) { 1667fe56b9e6SYuval Mintz sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 1668fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 1669fe56b9e6SYuval Mintz (sb_info->igu_sb_id << 3); 16701408cc1fSYuval Mintz } else { 16711408cc1fSYuval Mintz sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 16721408cc1fSYuval Mintz PXP_VF_BAR0_START_IGU + 16731408cc1fSYuval Mintz ((IGU_CMD_INT_ACK_BASE + 16741408cc1fSYuval Mintz sb_info->igu_sb_id) << 3); 16751408cc1fSYuval Mintz } 1676fe56b9e6SYuval Mintz 1677fe56b9e6SYuval Mintz sb_info->flags |= QED_SB_INFO_INIT; 1678fe56b9e6SYuval Mintz 1679fe56b9e6SYuval Mintz qed_int_sb_setup(p_hwfn, p_ptt, sb_info); 1680fe56b9e6SYuval Mintz 1681fe56b9e6SYuval Mintz return 0; 1682fe56b9e6SYuval Mintz } 1683fe56b9e6SYuval Mintz 1684fe56b9e6SYuval Mintz int qed_int_sb_release(struct qed_hwfn *p_hwfn, 16851a635e48SYuval Mintz struct qed_sb_info *sb_info, u16 sb_id) 1686fe56b9e6SYuval Mintz { 168750a20714SMintz, Yuval struct qed_igu_block *p_block; 168850a20714SMintz, Yuval struct qed_igu_info *p_info; 168950a20714SMintz, Yuval 169050a20714SMintz, Yuval if (!sb_info) 169150a20714SMintz, Yuval return 0; 1692fe56b9e6SYuval Mintz 1693fe56b9e6SYuval Mintz /* zero status block and ack counter */ 1694fe56b9e6SYuval Mintz sb_info->sb_ack = 0; 1695fe56b9e6SYuval Mintz memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 1696fe56b9e6SYuval Mintz 169750a20714SMintz, Yuval if (IS_VF(p_hwfn->cdev)) { 169850a20714SMintz, Yuval qed_vf_set_sb_info(p_hwfn, sb_id, NULL); 169950a20714SMintz, Yuval return 0; 17004ac801b7SYuval Mintz } 1701fe56b9e6SYuval Mintz 170250a20714SMintz, Yuval p_info = p_hwfn->hw_info.p_igu_info; 170350a20714SMintz, Yuval p_block = &p_info->entry[sb_info->igu_sb_id]; 170450a20714SMintz, Yuval 170550a20714SMintz, Yuval /* Vector 0 is reserved to Default SB */ 170650a20714SMintz, Yuval if (!p_block->vector_number) { 170750a20714SMintz, Yuval DP_ERR(p_hwfn, "Do Not free sp sb using this function"); 170850a20714SMintz, Yuval return -EINVAL; 170950a20714SMintz, Yuval } 171050a20714SMintz, Yuval 171150a20714SMintz, Yuval /* Lose reference to client's SB info, and fix counters */ 171250a20714SMintz, Yuval p_block->sb_info = NULL; 171350a20714SMintz, Yuval p_block->status |= QED_IGU_STATUS_FREE; 171450a20714SMintz, Yuval p_info->usage.free_cnt++; 171550a20714SMintz, Yuval 1716fe56b9e6SYuval Mintz return 0; 1717fe56b9e6SYuval Mintz } 1718fe56b9e6SYuval Mintz 1719fe56b9e6SYuval Mintz static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn) 1720fe56b9e6SYuval Mintz { 1721fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb; 1722fe56b9e6SYuval Mintz 17234ac801b7SYuval Mintz if (!p_sb) 17244ac801b7SYuval Mintz return; 17254ac801b7SYuval Mintz 1726fe56b9e6SYuval Mintz if (p_sb->sb_info.sb_virt) 1727fe56b9e6SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1728fe56b9e6SYuval Mintz SB_ALIGNED_SIZE(p_hwfn), 1729fe56b9e6SYuval Mintz p_sb->sb_info.sb_virt, 1730fe56b9e6SYuval Mintz p_sb->sb_info.sb_phys); 1731fe56b9e6SYuval Mintz kfree(p_sb); 17323587cb87STomer Tayar p_hwfn->p_sp_sb = NULL; 1733fe56b9e6SYuval Mintz } 1734fe56b9e6SYuval Mintz 17351a635e48SYuval Mintz static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1736fe56b9e6SYuval Mintz { 1737fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sb; 1738fe56b9e6SYuval Mintz dma_addr_t p_phys = 0; 1739fe56b9e6SYuval Mintz void *p_virt; 1740fe56b9e6SYuval Mintz 1741fe56b9e6SYuval Mintz /* SB struct */ 174260fffb3bSYuval Mintz p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 17432591c280SJoe Perches if (!p_sb) 1744fe56b9e6SYuval Mintz return -ENOMEM; 1745fe56b9e6SYuval Mintz 1746fe56b9e6SYuval Mintz /* SB ring */ 1747fe56b9e6SYuval Mintz p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1748fe56b9e6SYuval Mintz SB_ALIGNED_SIZE(p_hwfn), 1749fe56b9e6SYuval Mintz &p_phys, GFP_KERNEL); 1750fe56b9e6SYuval Mintz if (!p_virt) { 1751fe56b9e6SYuval Mintz kfree(p_sb); 1752fe56b9e6SYuval Mintz return -ENOMEM; 1753fe56b9e6SYuval Mintz } 1754fe56b9e6SYuval Mintz 1755fe56b9e6SYuval Mintz /* Status Block setup */ 1756fe56b9e6SYuval Mintz p_hwfn->p_sp_sb = p_sb; 1757fe56b9e6SYuval Mintz qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt, 1758fe56b9e6SYuval Mintz p_phys, QED_SP_SB_ID); 1759fe56b9e6SYuval Mintz 1760fe56b9e6SYuval Mintz memset(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr)); 1761fe56b9e6SYuval Mintz 1762fe56b9e6SYuval Mintz return 0; 1763fe56b9e6SYuval Mintz } 1764fe56b9e6SYuval Mintz 1765fe56b9e6SYuval Mintz int qed_int_register_cb(struct qed_hwfn *p_hwfn, 1766fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb, 17671a635e48SYuval Mintz void *cookie, u8 *sb_idx, __le16 **p_fw_cons) 1768fe56b9e6SYuval Mintz { 1769fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 17704ac801b7SYuval Mintz int rc = -ENOMEM; 1771fe56b9e6SYuval Mintz u8 pi; 1772fe56b9e6SYuval Mintz 1773fe56b9e6SYuval Mintz /* Look for a free index */ 1774fe56b9e6SYuval Mintz for (pi = 0; pi < ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) { 17754ac801b7SYuval Mintz if (p_sp_sb->pi_info_arr[pi].comp_cb) 17764ac801b7SYuval Mintz continue; 17774ac801b7SYuval Mintz 1778fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb; 1779fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].cookie = cookie; 1780fe56b9e6SYuval Mintz *sb_idx = pi; 1781fe56b9e6SYuval Mintz *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi]; 17824ac801b7SYuval Mintz rc = 0; 1783fe56b9e6SYuval Mintz break; 1784fe56b9e6SYuval Mintz } 1785fe56b9e6SYuval Mintz 17864ac801b7SYuval Mintz return rc; 1787fe56b9e6SYuval Mintz } 1788fe56b9e6SYuval Mintz 1789fe56b9e6SYuval Mintz int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi) 1790fe56b9e6SYuval Mintz { 1791fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 1792fe56b9e6SYuval Mintz 17934ac801b7SYuval Mintz if (p_sp_sb->pi_info_arr[pi].comp_cb == NULL) 17944ac801b7SYuval Mintz return -ENOMEM; 17954ac801b7SYuval Mintz 1796fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].comp_cb = NULL; 1797fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].cookie = NULL; 1798fe56b9e6SYuval Mintz 17994ac801b7SYuval Mintz return 0; 1800fe56b9e6SYuval Mintz } 1801fe56b9e6SYuval Mintz 1802fe56b9e6SYuval Mintz u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn) 1803fe56b9e6SYuval Mintz { 1804fe56b9e6SYuval Mintz return p_hwfn->p_sp_sb->sb_info.igu_sb_id; 1805fe56b9e6SYuval Mintz } 1806fe56b9e6SYuval Mintz 1807fe56b9e6SYuval Mintz void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn, 18081a635e48SYuval Mintz struct qed_ptt *p_ptt, enum qed_int_mode int_mode) 1809fe56b9e6SYuval Mintz { 1810cc875c2eSYuval Mintz u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN; 1811fe56b9e6SYuval Mintz 1812fe56b9e6SYuval Mintz p_hwfn->cdev->int_mode = int_mode; 1813fe56b9e6SYuval Mintz switch (p_hwfn->cdev->int_mode) { 1814fe56b9e6SYuval Mintz case QED_INT_MODE_INTA: 1815fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN; 1816fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 1817fe56b9e6SYuval Mintz break; 1818fe56b9e6SYuval Mintz 1819fe56b9e6SYuval Mintz case QED_INT_MODE_MSI: 1820fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 1821fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 1822fe56b9e6SYuval Mintz break; 1823fe56b9e6SYuval Mintz 1824fe56b9e6SYuval Mintz case QED_INT_MODE_MSIX: 1825fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 1826fe56b9e6SYuval Mintz break; 1827fe56b9e6SYuval Mintz case QED_INT_MODE_POLL: 1828fe56b9e6SYuval Mintz break; 1829fe56b9e6SYuval Mintz } 1830fe56b9e6SYuval Mintz 1831fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf); 1832fe56b9e6SYuval Mintz } 1833fe56b9e6SYuval Mintz 1834979cead3SMintz, Yuval static void qed_int_igu_enable_attn(struct qed_hwfn *p_hwfn, 1835979cead3SMintz, Yuval struct qed_ptt *p_ptt) 1836fe56b9e6SYuval Mintz { 1837fe56b9e6SYuval Mintz 18380d956e8aSYuval Mintz /* Configure AEU signal change to produce attentions */ 18390d956e8aSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0); 1840cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff); 1841cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff); 18420d956e8aSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff); 1843cc875c2eSYuval Mintz 1844cc875c2eSYuval Mintz /* Unmask AEU signals toward IGU */ 1845cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff); 1846979cead3SMintz, Yuval } 1847979cead3SMintz, Yuval 1848979cead3SMintz, Yuval int 1849979cead3SMintz, Yuval qed_int_igu_enable(struct qed_hwfn *p_hwfn, 1850979cead3SMintz, Yuval struct qed_ptt *p_ptt, enum qed_int_mode int_mode) 1851979cead3SMintz, Yuval { 1852979cead3SMintz, Yuval int rc = 0; 1853979cead3SMintz, Yuval 1854979cead3SMintz, Yuval qed_int_igu_enable_attn(p_hwfn, p_ptt); 1855979cead3SMintz, Yuval 18568f16bc97SSudarsana Kalluru if ((int_mode != QED_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) { 18578f16bc97SSudarsana Kalluru rc = qed_slowpath_irq_req(p_hwfn); 18581a635e48SYuval Mintz if (rc) { 18598f16bc97SSudarsana Kalluru DP_NOTICE(p_hwfn, "Slowpath IRQ request failed\n"); 18608f16bc97SSudarsana Kalluru return -EINVAL; 18618f16bc97SSudarsana Kalluru } 18628f16bc97SSudarsana Kalluru p_hwfn->b_int_requested = true; 18638f16bc97SSudarsana Kalluru } 18648f16bc97SSudarsana Kalluru /* Enable interrupt Generation */ 18658f16bc97SSudarsana Kalluru qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode); 18668f16bc97SSudarsana Kalluru p_hwfn->b_int_enabled = 1; 18678f16bc97SSudarsana Kalluru 18688f16bc97SSudarsana Kalluru return rc; 1869fe56b9e6SYuval Mintz } 1870fe56b9e6SYuval Mintz 18711a635e48SYuval Mintz void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1872fe56b9e6SYuval Mintz { 1873fe56b9e6SYuval Mintz p_hwfn->b_int_enabled = 0; 1874fe56b9e6SYuval Mintz 18751408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 18761408cc1fSYuval Mintz return; 18771408cc1fSYuval Mintz 1878fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0); 1879fe56b9e6SYuval Mintz } 1880fe56b9e6SYuval Mintz 1881fe56b9e6SYuval Mintz #define IGU_CLEANUP_SLEEP_LENGTH (1000) 1882b2b897ebSYuval Mintz static void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn, 1883fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1884d031548eSMintz, Yuval u16 igu_sb_id, 1885d031548eSMintz, Yuval bool cleanup_set, u16 opaque_fid) 1886fe56b9e6SYuval Mintz { 1887b2b897ebSYuval Mintz u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0; 1888d031548eSMintz, Yuval u32 pxp_addr = IGU_CMD_INT_ACK_BASE + igu_sb_id; 1889fe56b9e6SYuval Mintz u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH; 1890fe56b9e6SYuval Mintz 1891fe56b9e6SYuval Mintz /* Set the data field */ 1892fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0); 1893fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, 0); 1894fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET); 1895fe56b9e6SYuval Mintz 1896fe56b9e6SYuval Mintz /* Set the control register */ 1897fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr); 1898fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid); 1899fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR); 1900fe56b9e6SYuval Mintz 1901fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data); 1902fe56b9e6SYuval Mintz 1903fe56b9e6SYuval Mintz barrier(); 1904fe56b9e6SYuval Mintz 1905fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl); 1906fe56b9e6SYuval Mintz 1907fe56b9e6SYuval Mintz /* calculate where to read the status bit from */ 1908d031548eSMintz, Yuval sb_bit = 1 << (igu_sb_id % 32); 1909d031548eSMintz, Yuval sb_bit_addr = igu_sb_id / 32 * sizeof(u32); 1910fe56b9e6SYuval Mintz 1911fe56b9e6SYuval Mintz sb_bit_addr += IGU_REG_CLEANUP_STATUS_0; 1912fe56b9e6SYuval Mintz 1913fe56b9e6SYuval Mintz /* Now wait for the command to complete */ 1914fe56b9e6SYuval Mintz do { 1915fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, sb_bit_addr); 1916fe56b9e6SYuval Mintz 1917fe56b9e6SYuval Mintz if ((val & sb_bit) == (cleanup_set ? sb_bit : 0)) 1918fe56b9e6SYuval Mintz break; 1919fe56b9e6SYuval Mintz 1920fe56b9e6SYuval Mintz usleep_range(5000, 10000); 1921fe56b9e6SYuval Mintz } while (--sleep_cnt); 1922fe56b9e6SYuval Mintz 1923fe56b9e6SYuval Mintz if (!sleep_cnt) 1924fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 1925fe56b9e6SYuval Mintz "Timeout waiting for clear status 0x%08x [for sb %d]\n", 1926d031548eSMintz, Yuval val, igu_sb_id); 1927fe56b9e6SYuval Mintz } 1928fe56b9e6SYuval Mintz 1929fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn, 1930fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1931d031548eSMintz, Yuval u16 igu_sb_id, u16 opaque, bool b_set) 1932fe56b9e6SYuval Mintz { 19331ac72433SMintz, Yuval struct qed_igu_block *p_block; 1934b2b897ebSYuval Mintz int pi, i; 1935fe56b9e6SYuval Mintz 19361ac72433SMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id]; 19371ac72433SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 19381ac72433SMintz, Yuval "Cleaning SB [%04x]: func_id= %d is_pf = %d vector_num = 0x%0x\n", 19391ac72433SMintz, Yuval igu_sb_id, 19401ac72433SMintz, Yuval p_block->function_id, 19411ac72433SMintz, Yuval p_block->is_pf, p_block->vector_number); 19421ac72433SMintz, Yuval 1943fe56b9e6SYuval Mintz /* Set */ 1944fe56b9e6SYuval Mintz if (b_set) 1945d031548eSMintz, Yuval qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 1, opaque); 1946fe56b9e6SYuval Mintz 1947fe56b9e6SYuval Mintz /* Clear */ 1948d031548eSMintz, Yuval qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 0, opaque); 1949fe56b9e6SYuval Mintz 1950b2b897ebSYuval Mintz /* Wait for the IGU SB to cleanup */ 1951b2b897ebSYuval Mintz for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) { 1952b2b897ebSYuval Mintz u32 val; 1953b2b897ebSYuval Mintz 1954b2b897ebSYuval Mintz val = qed_rd(p_hwfn, p_ptt, 1955d031548eSMintz, Yuval IGU_REG_WRITE_DONE_PENDING + 1956d031548eSMintz, Yuval ((igu_sb_id / 32) * 4)); 1957d031548eSMintz, Yuval if (val & BIT((igu_sb_id % 32))) 1958b2b897ebSYuval Mintz usleep_range(10, 20); 1959b2b897ebSYuval Mintz else 1960b2b897ebSYuval Mintz break; 1961b2b897ebSYuval Mintz } 1962b2b897ebSYuval Mintz if (i == IGU_CLEANUP_SLEEP_LENGTH) 1963b2b897ebSYuval Mintz DP_NOTICE(p_hwfn, 1964b2b897ebSYuval Mintz "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n", 1965d031548eSMintz, Yuval igu_sb_id); 1966b2b897ebSYuval Mintz 1967fe56b9e6SYuval Mintz /* Clear the CAU for the SB */ 1968fe56b9e6SYuval Mintz for (pi = 0; pi < 12; pi++) 1969fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 1970d031548eSMintz, Yuval CAU_REG_PI_MEMORY + (igu_sb_id * 12 + pi) * 4, 0); 1971fe56b9e6SYuval Mintz } 1972fe56b9e6SYuval Mintz 1973fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn, 1974fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1975b2b897ebSYuval Mintz bool b_set, bool b_slowpath) 1976fe56b9e6SYuval Mintz { 19771ac72433SMintz, Yuval struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info; 19781ac72433SMintz, Yuval struct qed_igu_block *p_block; 19791ac72433SMintz, Yuval u16 igu_sb_id = 0; 19801ac72433SMintz, Yuval u32 val = 0; 1981fe56b9e6SYuval Mintz 1982fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION); 1983fe56b9e6SYuval Mintz val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN; 1984fe56b9e6SYuval Mintz val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN; 1985fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val); 1986fe56b9e6SYuval Mintz 19871ac72433SMintz, Yuval for (igu_sb_id = 0; 19881ac72433SMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 19891ac72433SMintz, Yuval p_block = &p_info->entry[igu_sb_id]; 1990fe56b9e6SYuval Mintz 19911ac72433SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID) || 19921ac72433SMintz, Yuval !p_block->is_pf || 19931ac72433SMintz, Yuval (p_block->status & QED_IGU_STATUS_DSB)) 19941ac72433SMintz, Yuval continue; 19951ac72433SMintz, Yuval 1996d031548eSMintz, Yuval qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, igu_sb_id, 1997fe56b9e6SYuval Mintz p_hwfn->hw_info.opaque_fid, 1998fe56b9e6SYuval Mintz b_set); 19991ac72433SMintz, Yuval } 2000fe56b9e6SYuval Mintz 20011ac72433SMintz, Yuval if (b_slowpath) 20021ac72433SMintz, Yuval qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, 20031ac72433SMintz, Yuval p_info->igu_dsb_id, 20041ac72433SMintz, Yuval p_hwfn->hw_info.opaque_fid, 20051ac72433SMintz, Yuval b_set); 2006fe56b9e6SYuval Mintz } 2007fe56b9e6SYuval Mintz 2008ebbdcc66SMintz, Yuval int qed_int_igu_reset_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2009ebbdcc66SMintz, Yuval { 2010ebbdcc66SMintz, Yuval struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info; 2011ebbdcc66SMintz, Yuval struct qed_igu_block *p_block; 2012ebbdcc66SMintz, Yuval int pf_sbs, vf_sbs; 2013ebbdcc66SMintz, Yuval u16 igu_sb_id; 2014ebbdcc66SMintz, Yuval u32 val, rval; 2015ebbdcc66SMintz, Yuval 2016ebbdcc66SMintz, Yuval if (!RESC_NUM(p_hwfn, QED_SB)) { 2017ebbdcc66SMintz, Yuval p_info->b_allow_pf_vf_change = false; 2018ebbdcc66SMintz, Yuval } else { 2019ebbdcc66SMintz, Yuval /* Use the numbers the MFW have provided - 2020ebbdcc66SMintz, Yuval * don't forget MFW accounts for the default SB as well. 2021ebbdcc66SMintz, Yuval */ 2022ebbdcc66SMintz, Yuval p_info->b_allow_pf_vf_change = true; 2023ebbdcc66SMintz, Yuval 2024ebbdcc66SMintz, Yuval if (p_info->usage.cnt != RESC_NUM(p_hwfn, QED_SB) - 1) { 2025ebbdcc66SMintz, Yuval DP_INFO(p_hwfn, 2026ebbdcc66SMintz, Yuval "MFW notifies of 0x%04x PF SBs; IGU indicates of only 0x%04x\n", 2027ebbdcc66SMintz, Yuval RESC_NUM(p_hwfn, QED_SB) - 1, 2028ebbdcc66SMintz, Yuval p_info->usage.cnt); 2029ebbdcc66SMintz, Yuval p_info->usage.cnt = RESC_NUM(p_hwfn, QED_SB) - 1; 2030ebbdcc66SMintz, Yuval } 2031ebbdcc66SMintz, Yuval 2032ebbdcc66SMintz, Yuval if (IS_PF_SRIOV(p_hwfn)) { 2033ebbdcc66SMintz, Yuval u16 vfs = p_hwfn->cdev->p_iov_info->total_vfs; 2034ebbdcc66SMintz, Yuval 2035ebbdcc66SMintz, Yuval if (vfs != p_info->usage.iov_cnt) 2036ebbdcc66SMintz, Yuval DP_VERBOSE(p_hwfn, 2037ebbdcc66SMintz, Yuval NETIF_MSG_INTR, 2038ebbdcc66SMintz, Yuval "0x%04x VF SBs in IGU CAM != PCI configuration 0x%04x\n", 2039ebbdcc66SMintz, Yuval p_info->usage.iov_cnt, vfs); 2040ebbdcc66SMintz, Yuval 2041ebbdcc66SMintz, Yuval /* At this point we know how many SBs we have totally 2042ebbdcc66SMintz, Yuval * in IGU + number of PF SBs. So we can validate that 2043ebbdcc66SMintz, Yuval * we'd have sufficient for VF. 2044ebbdcc66SMintz, Yuval */ 2045ebbdcc66SMintz, Yuval if (vfs > p_info->usage.free_cnt + 2046ebbdcc66SMintz, Yuval p_info->usage.free_cnt_iov - p_info->usage.cnt) { 2047ebbdcc66SMintz, Yuval DP_NOTICE(p_hwfn, 2048ebbdcc66SMintz, Yuval "Not enough SBs for VFs - 0x%04x SBs, from which %04x PFs and %04x are required\n", 2049ebbdcc66SMintz, Yuval p_info->usage.free_cnt + 2050ebbdcc66SMintz, Yuval p_info->usage.free_cnt_iov, 2051ebbdcc66SMintz, Yuval p_info->usage.cnt, vfs); 2052ebbdcc66SMintz, Yuval return -EINVAL; 2053ebbdcc66SMintz, Yuval } 2054ebbdcc66SMintz, Yuval 2055ebbdcc66SMintz, Yuval /* Currently cap the number of VFs SBs by the 2056ebbdcc66SMintz, Yuval * number of VFs. 2057ebbdcc66SMintz, Yuval */ 2058ebbdcc66SMintz, Yuval p_info->usage.iov_cnt = vfs; 2059ebbdcc66SMintz, Yuval } 2060ebbdcc66SMintz, Yuval } 2061ebbdcc66SMintz, Yuval 2062ebbdcc66SMintz, Yuval /* Mark all SBs as free, now in the right PF/VFs division */ 2063ebbdcc66SMintz, Yuval p_info->usage.free_cnt = p_info->usage.cnt; 2064ebbdcc66SMintz, Yuval p_info->usage.free_cnt_iov = p_info->usage.iov_cnt; 2065ebbdcc66SMintz, Yuval p_info->usage.orig = p_info->usage.cnt; 2066ebbdcc66SMintz, Yuval p_info->usage.iov_orig = p_info->usage.iov_cnt; 2067ebbdcc66SMintz, Yuval 2068ebbdcc66SMintz, Yuval /* We now proceed to re-configure the IGU cam to reflect the initial 2069ebbdcc66SMintz, Yuval * configuration. We can start with the Default SB. 2070ebbdcc66SMintz, Yuval */ 2071ebbdcc66SMintz, Yuval pf_sbs = p_info->usage.cnt; 2072ebbdcc66SMintz, Yuval vf_sbs = p_info->usage.iov_cnt; 2073ebbdcc66SMintz, Yuval 2074ebbdcc66SMintz, Yuval for (igu_sb_id = p_info->igu_dsb_id; 2075ebbdcc66SMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 2076ebbdcc66SMintz, Yuval p_block = &p_info->entry[igu_sb_id]; 2077ebbdcc66SMintz, Yuval val = 0; 2078ebbdcc66SMintz, Yuval 2079ebbdcc66SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID)) 2080ebbdcc66SMintz, Yuval continue; 2081ebbdcc66SMintz, Yuval 2082ebbdcc66SMintz, Yuval if (p_block->status & QED_IGU_STATUS_DSB) { 2083ebbdcc66SMintz, Yuval p_block->function_id = p_hwfn->rel_pf_id; 2084ebbdcc66SMintz, Yuval p_block->is_pf = 1; 2085ebbdcc66SMintz, Yuval p_block->vector_number = 0; 2086ebbdcc66SMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2087ebbdcc66SMintz, Yuval QED_IGU_STATUS_PF | 2088ebbdcc66SMintz, Yuval QED_IGU_STATUS_DSB; 2089ebbdcc66SMintz, Yuval } else if (pf_sbs) { 2090ebbdcc66SMintz, Yuval pf_sbs--; 2091ebbdcc66SMintz, Yuval p_block->function_id = p_hwfn->rel_pf_id; 2092ebbdcc66SMintz, Yuval p_block->is_pf = 1; 2093ebbdcc66SMintz, Yuval p_block->vector_number = p_info->usage.cnt - pf_sbs; 2094ebbdcc66SMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2095ebbdcc66SMintz, Yuval QED_IGU_STATUS_PF | 2096ebbdcc66SMintz, Yuval QED_IGU_STATUS_FREE; 2097ebbdcc66SMintz, Yuval } else if (vf_sbs) { 2098ebbdcc66SMintz, Yuval p_block->function_id = 2099ebbdcc66SMintz, Yuval p_hwfn->cdev->p_iov_info->first_vf_in_pf + 2100ebbdcc66SMintz, Yuval p_info->usage.iov_cnt - vf_sbs; 2101ebbdcc66SMintz, Yuval p_block->is_pf = 0; 2102ebbdcc66SMintz, Yuval p_block->vector_number = 0; 2103ebbdcc66SMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2104ebbdcc66SMintz, Yuval QED_IGU_STATUS_FREE; 2105ebbdcc66SMintz, Yuval vf_sbs--; 2106ebbdcc66SMintz, Yuval } else { 2107ebbdcc66SMintz, Yuval p_block->function_id = 0; 2108ebbdcc66SMintz, Yuval p_block->is_pf = 0; 2109ebbdcc66SMintz, Yuval p_block->vector_number = 0; 2110ebbdcc66SMintz, Yuval } 2111ebbdcc66SMintz, Yuval 2112ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER, 2113ebbdcc66SMintz, Yuval p_block->function_id); 2114ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf); 2115ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER, 2116ebbdcc66SMintz, Yuval p_block->vector_number); 2117ebbdcc66SMintz, Yuval 2118ebbdcc66SMintz, Yuval /* VF entries would be enabled when VF is initializaed */ 2119ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf); 2120ebbdcc66SMintz, Yuval 2121ebbdcc66SMintz, Yuval rval = qed_rd(p_hwfn, p_ptt, 2122ebbdcc66SMintz, Yuval IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id); 2123ebbdcc66SMintz, Yuval 2124ebbdcc66SMintz, Yuval if (rval != val) { 2125ebbdcc66SMintz, Yuval qed_wr(p_hwfn, p_ptt, 2126ebbdcc66SMintz, Yuval IGU_REG_MAPPING_MEMORY + 2127ebbdcc66SMintz, Yuval sizeof(u32) * igu_sb_id, val); 2128ebbdcc66SMintz, Yuval 2129ebbdcc66SMintz, Yuval DP_VERBOSE(p_hwfn, 2130ebbdcc66SMintz, Yuval NETIF_MSG_INTR, 2131ebbdcc66SMintz, Yuval "IGU reset: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x [%08x -> %08x]\n", 2132ebbdcc66SMintz, Yuval igu_sb_id, 2133ebbdcc66SMintz, Yuval p_block->function_id, 2134ebbdcc66SMintz, Yuval p_block->is_pf, 2135ebbdcc66SMintz, Yuval p_block->vector_number, rval, val); 2136ebbdcc66SMintz, Yuval } 2137ebbdcc66SMintz, Yuval } 2138ebbdcc66SMintz, Yuval 2139ebbdcc66SMintz, Yuval return 0; 2140ebbdcc66SMintz, Yuval } 2141ebbdcc66SMintz, Yuval 2142d749dd0dSMintz, Yuval static void qed_int_igu_read_cam_block(struct qed_hwfn *p_hwfn, 2143d749dd0dSMintz, Yuval struct qed_ptt *p_ptt, u16 igu_sb_id) 21444ac801b7SYuval Mintz { 21454ac801b7SYuval Mintz u32 val = qed_rd(p_hwfn, p_ptt, 2146d749dd0dSMintz, Yuval IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id); 21474ac801b7SYuval Mintz struct qed_igu_block *p_block; 21484ac801b7SYuval Mintz 2149d749dd0dSMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id]; 21504ac801b7SYuval Mintz 21514ac801b7SYuval Mintz /* Fill the block information */ 2152d749dd0dSMintz, Yuval p_block->function_id = GET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER); 21534ac801b7SYuval Mintz p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID); 2154d749dd0dSMintz, Yuval p_block->vector_number = GET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER); 21551ac72433SMintz, Yuval p_block->igu_sb_id = igu_sb_id; 21564ac801b7SYuval Mintz } 21574ac801b7SYuval Mintz 21581a635e48SYuval Mintz int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2159fe56b9e6SYuval Mintz { 2160fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 2161d749dd0dSMintz, Yuval struct qed_igu_block *p_block; 2162d749dd0dSMintz, Yuval u32 min_vf = 0, max_vf = 0; 2163d749dd0dSMintz, Yuval u16 igu_sb_id; 2164fe56b9e6SYuval Mintz 216560fffb3bSYuval Mintz p_hwfn->hw_info.p_igu_info = kzalloc(sizeof(*p_igu_info), GFP_KERNEL); 2166fe56b9e6SYuval Mintz if (!p_hwfn->hw_info.p_igu_info) 2167fe56b9e6SYuval Mintz return -ENOMEM; 2168fe56b9e6SYuval Mintz 2169fe56b9e6SYuval Mintz p_igu_info = p_hwfn->hw_info.p_igu_info; 2170fe56b9e6SYuval Mintz 2171d749dd0dSMintz, Yuval /* Distinguish between existent and non-existent default SB */ 2172d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id = QED_SB_INVALID_IDX; 2173d749dd0dSMintz, Yuval 2174d749dd0dSMintz, Yuval /* Find the range of VF ids whose SB belong to this PF */ 21751408cc1fSYuval Mintz if (p_hwfn->cdev->p_iov_info) { 21761408cc1fSYuval Mintz struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info; 21771408cc1fSYuval Mintz 21781408cc1fSYuval Mintz min_vf = p_iov->first_vf_in_pf; 21791408cc1fSYuval Mintz max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs; 21801408cc1fSYuval Mintz } 21811408cc1fSYuval Mintz 2182d749dd0dSMintz, Yuval for (igu_sb_id = 0; 2183d749dd0dSMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 2184d749dd0dSMintz, Yuval /* Read current entry; Notice it might not belong to this PF */ 2185d749dd0dSMintz, Yuval qed_int_igu_read_cam_block(p_hwfn, p_ptt, igu_sb_id); 2186d749dd0dSMintz, Yuval p_block = &p_igu_info->entry[igu_sb_id]; 2187fe56b9e6SYuval Mintz 2188d749dd0dSMintz, Yuval if ((p_block->is_pf) && 2189d749dd0dSMintz, Yuval (p_block->function_id == p_hwfn->rel_pf_id)) { 2190d749dd0dSMintz, Yuval p_block->status = QED_IGU_STATUS_PF | 2191d749dd0dSMintz, Yuval QED_IGU_STATUS_VALID | 2192d749dd0dSMintz, Yuval QED_IGU_STATUS_FREE; 2193fe56b9e6SYuval Mintz 21941ac72433SMintz, Yuval if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX) 2195726fdbe9SMintz, Yuval p_igu_info->usage.cnt++; 2196d749dd0dSMintz, Yuval } else if (!(p_block->is_pf) && 2197d749dd0dSMintz, Yuval (p_block->function_id >= min_vf) && 2198d749dd0dSMintz, Yuval (p_block->function_id < max_vf)) { 21991408cc1fSYuval Mintz /* Available for VFs of this PF */ 2200d749dd0dSMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2201d749dd0dSMintz, Yuval QED_IGU_STATUS_FREE; 2202d749dd0dSMintz, Yuval 22031ac72433SMintz, Yuval if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX) 2204726fdbe9SMintz, Yuval p_igu_info->usage.iov_cnt++; 22051408cc1fSYuval Mintz } 22065a1f965aSMintz, Yuval 2207d749dd0dSMintz, Yuval /* Mark the First entry belonging to the PF or its VFs 2208ebbdcc66SMintz, Yuval * as the default SB [we'll reset IGU prior to first usage]. 22095a1f965aSMintz, Yuval */ 2210d749dd0dSMintz, Yuval if ((p_block->status & QED_IGU_STATUS_VALID) && 2211d749dd0dSMintz, Yuval (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX)) { 2212d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id = igu_sb_id; 2213d749dd0dSMintz, Yuval p_block->status |= QED_IGU_STATUS_DSB; 2214d749dd0dSMintz, Yuval } 22155a1f965aSMintz, Yuval 2216d749dd0dSMintz, Yuval /* limit number of prints by having each PF print only its 2217d749dd0dSMintz, Yuval * entries with the exception of PF0 which would print 2218d749dd0dSMintz, Yuval * everything. 2219d749dd0dSMintz, Yuval */ 2220d749dd0dSMintz, Yuval if ((p_block->status & QED_IGU_STATUS_VALID) || 2221d749dd0dSMintz, Yuval (p_hwfn->abs_pf_id == 0)) { 2222d749dd0dSMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2223d749dd0dSMintz, Yuval "IGU_BLOCK: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n", 2224d749dd0dSMintz, Yuval igu_sb_id, p_block->function_id, 2225d749dd0dSMintz, Yuval p_block->is_pf, p_block->vector_number); 2226d749dd0dSMintz, Yuval } 2227d749dd0dSMintz, Yuval } 2228d749dd0dSMintz, Yuval 2229d749dd0dSMintz, Yuval if (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX) { 22305a1f965aSMintz, Yuval DP_NOTICE(p_hwfn, 2231d749dd0dSMintz, Yuval "IGU CAM returned invalid values igu_dsb_id=0x%x\n", 2232d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id); 22335a1f965aSMintz, Yuval return -EINVAL; 22345a1f965aSMintz, Yuval } 2235d749dd0dSMintz, Yuval 2236d749dd0dSMintz, Yuval /* All non default SB are considered free at this point */ 2237726fdbe9SMintz, Yuval p_igu_info->usage.free_cnt = p_igu_info->usage.cnt; 2238726fdbe9SMintz, Yuval p_igu_info->usage.free_cnt_iov = p_igu_info->usage.iov_cnt; 2239fe56b9e6SYuval Mintz 2240d749dd0dSMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2241ebbdcc66SMintz, Yuval "igu_dsb_id=0x%x, num Free SBs - PF: %04x VF: %04x [might change after resource allocation]\n", 2242d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id, 2243726fdbe9SMintz, Yuval p_igu_info->usage.cnt, p_igu_info->usage.iov_cnt); 2244fe56b9e6SYuval Mintz 2245fe56b9e6SYuval Mintz return 0; 2246fe56b9e6SYuval Mintz } 2247fe56b9e6SYuval Mintz 2248fe56b9e6SYuval Mintz /** 2249fe56b9e6SYuval Mintz * @brief Initialize igu runtime registers 2250fe56b9e6SYuval Mintz * 2251fe56b9e6SYuval Mintz * @param p_hwfn 2252fe56b9e6SYuval Mintz */ 2253fe56b9e6SYuval Mintz void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn) 2254fe56b9e6SYuval Mintz { 22551a635e48SYuval Mintz u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN; 2256fe56b9e6SYuval Mintz 2257fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf); 2258fe56b9e6SYuval Mintz } 2259fe56b9e6SYuval Mintz 2260fe56b9e6SYuval Mintz u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn) 2261fe56b9e6SYuval Mintz { 2262fe56b9e6SYuval Mintz u32 lsb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - 2263fe56b9e6SYuval Mintz IGU_CMD_INT_ACK_BASE; 2264fe56b9e6SYuval Mintz u32 msb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - 2265fe56b9e6SYuval Mintz IGU_CMD_INT_ACK_BASE; 22661a635e48SYuval Mintz u32 intr_status_hi = 0, intr_status_lo = 0; 22671a635e48SYuval Mintz u64 intr_status = 0; 2268fe56b9e6SYuval Mintz 2269fe56b9e6SYuval Mintz intr_status_lo = REG_RD(p_hwfn, 2270fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 2271fe56b9e6SYuval Mintz lsb_igu_cmd_addr * 8); 2272fe56b9e6SYuval Mintz intr_status_hi = REG_RD(p_hwfn, 2273fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 2274fe56b9e6SYuval Mintz msb_igu_cmd_addr * 8); 2275fe56b9e6SYuval Mintz intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo; 2276fe56b9e6SYuval Mintz 2277fe56b9e6SYuval Mintz return intr_status; 2278fe56b9e6SYuval Mintz } 2279fe56b9e6SYuval Mintz 2280fe56b9e6SYuval Mintz static void qed_int_sp_dpc_setup(struct qed_hwfn *p_hwfn) 2281fe56b9e6SYuval Mintz { 2282fe56b9e6SYuval Mintz tasklet_init(p_hwfn->sp_dpc, 2283fe56b9e6SYuval Mintz qed_int_sp_dpc, (unsigned long)p_hwfn); 2284fe56b9e6SYuval Mintz p_hwfn->b_sp_dpc_enabled = true; 2285fe56b9e6SYuval Mintz } 2286fe56b9e6SYuval Mintz 2287fe56b9e6SYuval Mintz static int qed_int_sp_dpc_alloc(struct qed_hwfn *p_hwfn) 2288fe56b9e6SYuval Mintz { 228960fffb3bSYuval Mintz p_hwfn->sp_dpc = kmalloc(sizeof(*p_hwfn->sp_dpc), GFP_KERNEL); 2290fe56b9e6SYuval Mintz if (!p_hwfn->sp_dpc) 2291fe56b9e6SYuval Mintz return -ENOMEM; 2292fe56b9e6SYuval Mintz 2293fe56b9e6SYuval Mintz return 0; 2294fe56b9e6SYuval Mintz } 2295fe56b9e6SYuval Mintz 2296fe56b9e6SYuval Mintz static void qed_int_sp_dpc_free(struct qed_hwfn *p_hwfn) 2297fe56b9e6SYuval Mintz { 2298fe56b9e6SYuval Mintz kfree(p_hwfn->sp_dpc); 22993587cb87STomer Tayar p_hwfn->sp_dpc = NULL; 2300fe56b9e6SYuval Mintz } 2301fe56b9e6SYuval Mintz 23021a635e48SYuval Mintz int qed_int_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2303fe56b9e6SYuval Mintz { 2304fe56b9e6SYuval Mintz int rc = 0; 2305fe56b9e6SYuval Mintz 2306fe56b9e6SYuval Mintz rc = qed_int_sp_dpc_alloc(p_hwfn); 230783aeb933SYuval Mintz if (rc) 23082591c280SJoe Perches return rc; 23092591c280SJoe Perches 23102591c280SJoe Perches rc = qed_int_sp_sb_alloc(p_hwfn, p_ptt); 23112591c280SJoe Perches if (rc) 23122591c280SJoe Perches return rc; 23132591c280SJoe Perches 23142591c280SJoe Perches rc = qed_int_sb_attn_alloc(p_hwfn, p_ptt); 231583aeb933SYuval Mintz 2316fe56b9e6SYuval Mintz return rc; 2317fe56b9e6SYuval Mintz } 2318fe56b9e6SYuval Mintz 2319fe56b9e6SYuval Mintz void qed_int_free(struct qed_hwfn *p_hwfn) 2320fe56b9e6SYuval Mintz { 2321fe56b9e6SYuval Mintz qed_int_sp_sb_free(p_hwfn); 2322cc875c2eSYuval Mintz qed_int_sb_attn_free(p_hwfn); 2323fe56b9e6SYuval Mintz qed_int_sp_dpc_free(p_hwfn); 2324fe56b9e6SYuval Mintz } 2325fe56b9e6SYuval Mintz 23261a635e48SYuval Mintz void qed_int_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2327fe56b9e6SYuval Mintz { 23280d956e8aSYuval Mintz qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info); 23290d956e8aSYuval Mintz qed_int_sb_attn_setup(p_hwfn, p_ptt); 2330fe56b9e6SYuval Mintz qed_int_sp_dpc_setup(p_hwfn); 2331fe56b9e6SYuval Mintz } 2332fe56b9e6SYuval Mintz 23334ac801b7SYuval Mintz void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn, 23344ac801b7SYuval Mintz struct qed_sb_cnt_info *p_sb_cnt_info) 2335fe56b9e6SYuval Mintz { 2336fe56b9e6SYuval Mintz struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info; 2337fe56b9e6SYuval Mintz 23384ac801b7SYuval Mintz if (!info || !p_sb_cnt_info) 23394ac801b7SYuval Mintz return; 2340fe56b9e6SYuval Mintz 2341726fdbe9SMintz, Yuval memcpy(p_sb_cnt_info, &info->usage, sizeof(*p_sb_cnt_info)); 2342fe56b9e6SYuval Mintz } 23438f16bc97SSudarsana Kalluru 23448f16bc97SSudarsana Kalluru void qed_int_disable_post_isr_release(struct qed_dev *cdev) 23458f16bc97SSudarsana Kalluru { 23468f16bc97SSudarsana Kalluru int i; 23478f16bc97SSudarsana Kalluru 23488f16bc97SSudarsana Kalluru for_each_hwfn(cdev, i) 23498f16bc97SSudarsana Kalluru cdev->hwfns[i].b_int_requested = false; 23508f16bc97SSudarsana Kalluru } 2351722003acSSudarsana Reddy Kalluru 2352722003acSSudarsana Reddy Kalluru int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2353722003acSSudarsana Reddy Kalluru u8 timer_res, u16 sb_id, bool tx) 2354722003acSSudarsana Reddy Kalluru { 2355722003acSSudarsana Reddy Kalluru struct cau_sb_entry sb_entry; 2356722003acSSudarsana Reddy Kalluru int rc; 2357722003acSSudarsana Reddy Kalluru 2358722003acSSudarsana Reddy Kalluru if (!p_hwfn->hw_init_done) { 2359722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "hardware not initialized yet\n"); 2360722003acSSudarsana Reddy Kalluru return -EINVAL; 2361722003acSSudarsana Reddy Kalluru } 2362722003acSSudarsana Reddy Kalluru 2363722003acSSudarsana Reddy Kalluru rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY + 2364722003acSSudarsana Reddy Kalluru sb_id * sizeof(u64), 236583bf76e3SMichal Kalderon (u64)(uintptr_t)&sb_entry, 2, NULL); 2366722003acSSudarsana Reddy Kalluru if (rc) { 2367722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc); 2368722003acSSudarsana Reddy Kalluru return rc; 2369722003acSSudarsana Reddy Kalluru } 2370722003acSSudarsana Reddy Kalluru 2371722003acSSudarsana Reddy Kalluru if (tx) 2372722003acSSudarsana Reddy Kalluru SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 2373722003acSSudarsana Reddy Kalluru else 2374722003acSSudarsana Reddy Kalluru SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 2375722003acSSudarsana Reddy Kalluru 2376722003acSSudarsana Reddy Kalluru rc = qed_dmae_host2grc(p_hwfn, p_ptt, 2377722003acSSudarsana Reddy Kalluru (u64)(uintptr_t)&sb_entry, 2378722003acSSudarsana Reddy Kalluru CAU_REG_SB_VAR_MEMORY + 237983bf76e3SMichal Kalderon sb_id * sizeof(u64), 2, NULL); 2380722003acSSudarsana Reddy Kalluru if (rc) { 2381722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc); 2382722003acSSudarsana Reddy Kalluru return rc; 2383722003acSSudarsana Reddy Kalluru } 2384722003acSSudarsana Reddy Kalluru 2385722003acSSudarsana Reddy Kalluru return rc; 2386722003acSSudarsana Reddy Kalluru } 2387