11f4d4ed6SAlexander Lobakin // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 3e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 4663eacd8SAlexander Lobakin * Copyright (c) 2019-2020 Marvell International Ltd. 5fe56b9e6SYuval Mintz */ 6fe56b9e6SYuval Mintz 7fe56b9e6SYuval Mintz #include <linux/types.h> 8fe56b9e6SYuval Mintz #include <asm/byteorder.h> 9fe56b9e6SYuval Mintz #include <linux/io.h> 10fe56b9e6SYuval Mintz #include <linux/bitops.h> 11fe56b9e6SYuval Mintz #include <linux/delay.h> 12fe56b9e6SYuval Mintz #include <linux/dma-mapping.h> 13fe56b9e6SYuval Mintz #include <linux/errno.h> 14fe56b9e6SYuval Mintz #include <linux/interrupt.h> 15fe56b9e6SYuval Mintz #include <linux/kernel.h> 16fe56b9e6SYuval Mintz #include <linux/pci.h> 17fe56b9e6SYuval Mintz #include <linux/slab.h> 18fe56b9e6SYuval Mintz #include <linux/string.h> 19fe56b9e6SYuval Mintz #include "qed.h" 20fe56b9e6SYuval Mintz #include "qed_hsi.h" 21fe56b9e6SYuval Mintz #include "qed_hw.h" 22fe56b9e6SYuval Mintz #include "qed_init_ops.h" 23fe56b9e6SYuval Mintz #include "qed_int.h" 24fe56b9e6SYuval Mintz #include "qed_mcp.h" 25fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 26fe56b9e6SYuval Mintz #include "qed_sp.h" 271408cc1fSYuval Mintz #include "qed_sriov.h" 281408cc1fSYuval Mintz #include "qed_vf.h" 29fe56b9e6SYuval Mintz 30fe56b9e6SYuval Mintz struct qed_pi_info { 31fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb; 32fe56b9e6SYuval Mintz void *cookie; 33fe56b9e6SYuval Mintz }; 34fe56b9e6SYuval Mintz 35fe56b9e6SYuval Mintz struct qed_sb_sp_info { 36fe56b9e6SYuval Mintz struct qed_sb_info sb_info; 37fe56b9e6SYuval Mintz 38fe56b9e6SYuval Mintz /* per protocol index data */ 3921dd79e8STomer Tayar struct qed_pi_info pi_info_arr[PIS_PER_SB_E4]; 40fe56b9e6SYuval Mintz }; 41fe56b9e6SYuval Mintz 42ff38577aSYuval Mintz enum qed_attention_type { 43ff38577aSYuval Mintz QED_ATTN_TYPE_ATTN, 44ff38577aSYuval Mintz QED_ATTN_TYPE_PARITY, 45ff38577aSYuval Mintz }; 46ff38577aSYuval Mintz 47cc875c2eSYuval Mintz #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \ 48cc875c2eSYuval Mintz ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn) 49cc875c2eSYuval Mintz 500d956e8aSYuval Mintz struct aeu_invert_reg_bit { 510d956e8aSYuval Mintz char bit_name[30]; 520d956e8aSYuval Mintz 530d956e8aSYuval Mintz #define ATTENTION_PARITY (1 << 0) 540d956e8aSYuval Mintz 550d956e8aSYuval Mintz #define ATTENTION_LENGTH_MASK (0x00000ff0) 560d956e8aSYuval Mintz #define ATTENTION_LENGTH_SHIFT (4) 570d956e8aSYuval Mintz #define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \ 580d956e8aSYuval Mintz ATTENTION_LENGTH_SHIFT) 59a2e7699eSTomer Tayar #define ATTENTION_SINGLE BIT(ATTENTION_LENGTH_SHIFT) 600d956e8aSYuval Mintz #define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY) 610d956e8aSYuval Mintz #define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \ 620d956e8aSYuval Mintz ATTENTION_PARITY) 630d956e8aSYuval Mintz 640d956e8aSYuval Mintz /* Multiple bits start with this offset */ 650d956e8aSYuval Mintz #define ATTENTION_OFFSET_MASK (0x000ff000) 660d956e8aSYuval Mintz #define ATTENTION_OFFSET_SHIFT (12) 67ba36f718SMintz, Yuval 68ba36f718SMintz, Yuval #define ATTENTION_BB_MASK (0x00700000) 69ba36f718SMintz, Yuval #define ATTENTION_BB_SHIFT (20) 70ba36f718SMintz, Yuval #define ATTENTION_BB(value) (value << ATTENTION_BB_SHIFT) 71ba36f718SMintz, Yuval #define ATTENTION_BB_DIFFERENT BIT(23) 72ba36f718SMintz, Yuval 73936c7ba4SIgor Russkikh #define ATTENTION_CLEAR_ENABLE BIT(28) 740d956e8aSYuval Mintz unsigned int flags; 75ff38577aSYuval Mintz 76b4149dc7SYuval Mintz /* Callback to call if attention will be triggered */ 77b4149dc7SYuval Mintz int (*cb)(struct qed_hwfn *p_hwfn); 78b4149dc7SYuval Mintz 79ff38577aSYuval Mintz enum block_id block_index; 800d956e8aSYuval Mintz }; 810d956e8aSYuval Mintz 820d956e8aSYuval Mintz struct aeu_invert_reg { 830d956e8aSYuval Mintz struct aeu_invert_reg_bit bits[32]; 840d956e8aSYuval Mintz }; 850d956e8aSYuval Mintz 860d956e8aSYuval Mintz #define MAX_ATTN_GRPS (8) 870d956e8aSYuval Mintz #define NUM_ATTN_REGS (9) 880d956e8aSYuval Mintz 89b4149dc7SYuval Mintz /* Specific HW attention callbacks */ 90b4149dc7SYuval Mintz static int qed_mcp_attn_cb(struct qed_hwfn *p_hwfn) 91b4149dc7SYuval Mintz { 92b4149dc7SYuval Mintz u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE); 93b4149dc7SYuval Mintz 94b4149dc7SYuval Mintz /* This might occur on certain instances; Log it once then mask it */ 95b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, "MCP_REG_CPU_STATE: %08x - Masking...\n", 96b4149dc7SYuval Mintz tmp); 97b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, 98b4149dc7SYuval Mintz 0xffffffff); 99b4149dc7SYuval Mintz 100b4149dc7SYuval Mintz return 0; 101b4149dc7SYuval Mintz } 102b4149dc7SYuval Mintz 103b4149dc7SYuval Mintz #define QED_PSWHST_ATTENTION_INCORRECT_ACCESS (0x1) 104b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_WR_MASK (0x1) 105b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_WR_SHIFT (0) 106b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_CLIENT_MASK (0xf) 107b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT (1) 108b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK (0x1) 109b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT (5) 110b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_ID_MASK (0xff) 111b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT (6) 112b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_PF_ID_MASK (0xf) 113b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT (14) 114b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK (0xff) 115b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT (18) 116b4149dc7SYuval Mintz static int qed_pswhst_attn_cb(struct qed_hwfn *p_hwfn) 117b4149dc7SYuval Mintz { 118b4149dc7SYuval Mintz u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 119b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_VALID); 120b4149dc7SYuval Mintz 121b4149dc7SYuval Mintz if (tmp & QED_PSWHST_ATTENTION_INCORRECT_ACCESS) { 122b4149dc7SYuval Mintz u32 addr, data, length; 123b4149dc7SYuval Mintz 124b4149dc7SYuval Mintz addr = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 125b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_ADDRESS); 126b4149dc7SYuval Mintz data = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 127b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_DATA); 128b4149dc7SYuval Mintz length = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 129b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_LENGTH); 130b4149dc7SYuval Mintz 131b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, 132b4149dc7SYuval Mintz "Incorrect access to %08x of length %08x - PF [%02x] VF [%04x] [valid %02x] client [%02x] write [%02x] Byte-Enable [%04x] [%08x]\n", 133b4149dc7SYuval Mintz addr, length, 134b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_PF_ID), 135b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_VF_ID), 136b4149dc7SYuval Mintz (u8) GET_FIELD(data, 137b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_VF_VALID), 138b4149dc7SYuval Mintz (u8) GET_FIELD(data, 139b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_CLIENT), 140b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_WR), 141b4149dc7SYuval Mintz (u8) GET_FIELD(data, 142b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_BYTE_EN), 143b4149dc7SYuval Mintz data); 144b4149dc7SYuval Mintz } 145b4149dc7SYuval Mintz 146b4149dc7SYuval Mintz return 0; 147b4149dc7SYuval Mintz } 148b4149dc7SYuval Mintz 149b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VALID_BIT (1 << 0) 150b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_ADDRESS_MASK (0x7fffff) 151b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_ADDRESS_SHIFT (0) 152b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_RDWR_BIT (1 << 23) 153b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_MASTER_MASK (0xf) 154b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_MASTER_SHIFT (24) 155b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PF_MASK (0xf) 156b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PF_SHIFT (0) 157b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VF_MASK (0xff) 158b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VF_SHIFT (4) 159b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_MASK (0x3) 160b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_SHIFT (14) 161b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_VF (0) 162b4149dc7SYuval Mintz static const char *attn_master_to_str(u8 master) 163b4149dc7SYuval Mintz { 164b4149dc7SYuval Mintz switch (master) { 165b4149dc7SYuval Mintz case 1: return "PXP"; 166b4149dc7SYuval Mintz case 2: return "MCP"; 167b4149dc7SYuval Mintz case 3: return "MSDM"; 168b4149dc7SYuval Mintz case 4: return "PSDM"; 169b4149dc7SYuval Mintz case 5: return "YSDM"; 170b4149dc7SYuval Mintz case 6: return "USDM"; 171b4149dc7SYuval Mintz case 7: return "TSDM"; 172b4149dc7SYuval Mintz case 8: return "XSDM"; 173b4149dc7SYuval Mintz case 9: return "DBU"; 174b4149dc7SYuval Mintz case 10: return "DMAE"; 175b4149dc7SYuval Mintz default: 1769165dabbSMasanari Iida return "Unknown"; 177b4149dc7SYuval Mintz } 178b4149dc7SYuval Mintz } 179b4149dc7SYuval Mintz 180b4149dc7SYuval Mintz static int qed_grc_attn_cb(struct qed_hwfn *p_hwfn) 181b4149dc7SYuval Mintz { 182b4149dc7SYuval Mintz u32 tmp, tmp2; 183b4149dc7SYuval Mintz 184b4149dc7SYuval Mintz /* We've already cleared the timeout interrupt register, so we learn 185b4149dc7SYuval Mintz * of interrupts via the validity register 186b4149dc7SYuval Mintz */ 187b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 188b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_VALID); 189b4149dc7SYuval Mintz if (!(tmp & QED_GRC_ATTENTION_VALID_BIT)) 190b4149dc7SYuval Mintz goto out; 191b4149dc7SYuval Mintz 192b4149dc7SYuval Mintz /* Read the GRC timeout information */ 193b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 194b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0); 195b4149dc7SYuval Mintz tmp2 = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 196b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1); 197b4149dc7SYuval Mintz 198b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, 199b4149dc7SYuval Mintz "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n", 200b4149dc7SYuval Mintz tmp2, tmp, 201b4149dc7SYuval Mintz (tmp & QED_GRC_ATTENTION_RDWR_BIT) ? "Write to" : "Read from", 202b4149dc7SYuval Mintz GET_FIELD(tmp, QED_GRC_ATTENTION_ADDRESS) << 2, 203b4149dc7SYuval Mintz attn_master_to_str(GET_FIELD(tmp, QED_GRC_ATTENTION_MASTER)), 204b4149dc7SYuval Mintz GET_FIELD(tmp2, QED_GRC_ATTENTION_PF), 205b4149dc7SYuval Mintz (GET_FIELD(tmp2, QED_GRC_ATTENTION_PRIV) == 206fbe1222cSColin Ian King QED_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Irrelevant)", 207b4149dc7SYuval Mintz GET_FIELD(tmp2, QED_GRC_ATTENTION_VF)); 208b4149dc7SYuval Mintz 209b4149dc7SYuval Mintz out: 210b4149dc7SYuval Mintz /* Regardles of anything else, clean the validity bit */ 211b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 212b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0); 213b4149dc7SYuval Mintz return 0; 214b4149dc7SYuval Mintz } 215b4149dc7SYuval Mintz 216b4149dc7SYuval Mintz #define PGLUE_ATTENTION_VALID (1 << 29) 217b4149dc7SYuval Mintz #define PGLUE_ATTENTION_RD_VALID (1 << 26) 218b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf) 219b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20) 220b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VF_VALID_MASK (0x1) 221b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VF_VALID_SHIFT (19) 222b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff) 223b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24) 224b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_MASK (0x1) 225b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_SHIFT (21) 226b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_BME_MASK (0x1) 227b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_BME_SHIFT (22) 228b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_FID_EN_MASK (0x1) 229b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_FID_EN_SHIFT (23) 230b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ICPL_VALID (1 << 23) 231b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ZLR_VALID (1 << 25) 232b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ILT_VALID (1 << 23) 233666db486STomer Tayar 234666db486STomer Tayar int qed_pglueb_rbc_attn_handler(struct qed_hwfn *p_hwfn, 235666db486STomer Tayar struct qed_ptt *p_ptt) 236b4149dc7SYuval Mintz { 237b4149dc7SYuval Mintz u32 tmp; 238b4149dc7SYuval Mintz 239666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS2); 240b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_VALID) { 241b4149dc7SYuval Mintz u32 addr_lo, addr_hi, details; 242b4149dc7SYuval Mintz 243666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 244b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_ADD_31_0); 245666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 246b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_ADD_63_32); 247666db486STomer Tayar details = qed_rd(p_hwfn, p_ptt, 248b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_DETAILS); 249b4149dc7SYuval Mintz 250666db486STomer Tayar DP_NOTICE(p_hwfn, 251b4149dc7SYuval Mintz "Illegal write by chip to [%08x:%08x] blocked.\n" 252b4149dc7SYuval Mintz "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 253b4149dc7SYuval Mintz "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 254b4149dc7SYuval Mintz addr_hi, addr_lo, details, 255b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 256b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 257b4149dc7SYuval Mintz GET_FIELD(details, 258b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0, 259b4149dc7SYuval Mintz tmp, 260b4149dc7SYuval Mintz GET_FIELD(tmp, 261b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0, 262b4149dc7SYuval Mintz GET_FIELD(tmp, 263b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0, 264b4149dc7SYuval Mintz GET_FIELD(tmp, 265b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0); 266b4149dc7SYuval Mintz } 267b4149dc7SYuval Mintz 268666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_RD_DETAILS2); 269b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_RD_VALID) { 270b4149dc7SYuval Mintz u32 addr_lo, addr_hi, details; 271b4149dc7SYuval Mintz 272666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 273b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_ADD_31_0); 274666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 275b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_ADD_63_32); 276666db486STomer Tayar details = qed_rd(p_hwfn, p_ptt, 277b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_DETAILS); 278b4149dc7SYuval Mintz 279666db486STomer Tayar DP_NOTICE(p_hwfn, 280b4149dc7SYuval Mintz "Illegal read by chip from [%08x:%08x] blocked.\n" 281b4149dc7SYuval Mintz "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 282b4149dc7SYuval Mintz "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 283b4149dc7SYuval Mintz addr_hi, addr_lo, details, 284b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 285b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 286b4149dc7SYuval Mintz GET_FIELD(details, 287b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0, 288b4149dc7SYuval Mintz tmp, 289666db486STomer Tayar GET_FIELD(tmp, 290666db486STomer Tayar PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0, 291666db486STomer Tayar GET_FIELD(tmp, 292666db486STomer Tayar PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0, 293666db486STomer Tayar GET_FIELD(tmp, 294666db486STomer Tayar PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0); 295b4149dc7SYuval Mintz } 296b4149dc7SYuval Mintz 297666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL); 298b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ICPL_VALID) 299666db486STomer Tayar DP_NOTICE(p_hwfn, "ICPL error - %08x\n", tmp); 300b4149dc7SYuval Mintz 301666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS); 302b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ZLR_VALID) { 303b4149dc7SYuval Mintz u32 addr_hi, addr_lo; 304b4149dc7SYuval Mintz 305666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 306b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0); 307666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 308b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32); 309b4149dc7SYuval Mintz 310666db486STomer Tayar DP_NOTICE(p_hwfn, "ZLR error - %08x [Address %08x:%08x]\n", 311b4149dc7SYuval Mintz tmp, addr_hi, addr_lo); 312b4149dc7SYuval Mintz } 313b4149dc7SYuval Mintz 314666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_VF_ILT_ERR_DETAILS2); 315b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ILT_VALID) { 316b4149dc7SYuval Mintz u32 addr_hi, addr_lo, details; 317b4149dc7SYuval Mintz 318666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 319b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_ADD_31_0); 320666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 321b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_ADD_63_32); 322666db486STomer Tayar details = qed_rd(p_hwfn, p_ptt, 323b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_DETAILS); 324b4149dc7SYuval Mintz 325666db486STomer Tayar DP_NOTICE(p_hwfn, 326b4149dc7SYuval Mintz "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n", 327b4149dc7SYuval Mintz details, tmp, addr_hi, addr_lo); 328b4149dc7SYuval Mintz } 329b4149dc7SYuval Mintz 330b4149dc7SYuval Mintz /* Clear the indications */ 331666db486STomer Tayar qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_LATCHED_ERRORS_CLR, BIT(2)); 332b4149dc7SYuval Mintz 333b4149dc7SYuval Mintz return 0; 334b4149dc7SYuval Mintz } 335b4149dc7SYuval Mintz 336666db486STomer Tayar static int qed_pglueb_rbc_attn_cb(struct qed_hwfn *p_hwfn) 337666db486STomer Tayar { 338666db486STomer Tayar return qed_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_dpc_ptt); 339666db486STomer Tayar } 340666db486STomer Tayar 3412ec276d5SIgor Russkikh static int qed_fw_assertion(struct qed_hwfn *p_hwfn) 3422ec276d5SIgor Russkikh { 3432ec276d5SIgor Russkikh qed_hw_err_notify(p_hwfn, p_hwfn->p_dpc_ptt, QED_HW_ERR_FW_ASSERT, 3442ec276d5SIgor Russkikh "FW assertion!\n"); 3452ec276d5SIgor Russkikh 3462ec276d5SIgor Russkikh return -EINVAL; 3472ec276d5SIgor Russkikh } 3482ec276d5SIgor Russkikh 349936c7ba4SIgor Russkikh static int qed_general_attention_35(struct qed_hwfn *p_hwfn) 350936c7ba4SIgor Russkikh { 351936c7ba4SIgor Russkikh DP_INFO(p_hwfn, "General attention 35!\n"); 352936c7ba4SIgor Russkikh 353936c7ba4SIgor Russkikh return 0; 354936c7ba4SIgor Russkikh } 355936c7ba4SIgor Russkikh 356b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_REASON_MASK (0xfffff) 357b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_OPAQUE_MASK (0xffff) 358a1b469b8SAriel Elior #define QED_DORQ_ATTENTION_OPAQUE_SHIFT (0x0) 359b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_SIZE_MASK (0x7f) 360b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_SIZE_SHIFT (16) 361a1b469b8SAriel Elior 362a1b469b8SAriel Elior #define QED_DB_REC_COUNT 1000 363a1b469b8SAriel Elior #define QED_DB_REC_INTERVAL 100 364a1b469b8SAriel Elior 365a1b469b8SAriel Elior static int qed_db_rec_flush_queue(struct qed_hwfn *p_hwfn, 366a1b469b8SAriel Elior struct qed_ptt *p_ptt) 367a1b469b8SAriel Elior { 368a1b469b8SAriel Elior u32 count = QED_DB_REC_COUNT; 369a1b469b8SAriel Elior u32 usage = 1; 370a1b469b8SAriel Elior 3710d72c2acSDenis Bolotin /* Flush any pending (e)dpms as they may never arrive */ 3720d72c2acSDenis Bolotin qed_wr(p_hwfn, p_ptt, DORQ_REG_DPM_FORCE_ABORT, 0x1); 3730d72c2acSDenis Bolotin 374a1b469b8SAriel Elior /* wait for usage to zero or count to run out. This is necessary since 375a1b469b8SAriel Elior * EDPM doorbell transactions can take multiple 64b cycles, and as such 376a1b469b8SAriel Elior * can "split" over the pci. Possibly, the doorbell drop can happen with 377a1b469b8SAriel Elior * half an EDPM in the queue and other half dropped. Another EDPM 378a1b469b8SAriel Elior * doorbell to the same address (from doorbell recovery mechanism or 379a1b469b8SAriel Elior * from the doorbelling entity) could have first half dropped and second 380a1b469b8SAriel Elior * half interpreted as continuation of the first. To prevent such 381a1b469b8SAriel Elior * malformed doorbells from reaching the device, flush the queue before 382a1b469b8SAriel Elior * releasing the overflow sticky indication. 383a1b469b8SAriel Elior */ 384a1b469b8SAriel Elior while (count-- && usage) { 385a1b469b8SAriel Elior usage = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_USAGE_CNT); 386a1b469b8SAriel Elior udelay(QED_DB_REC_INTERVAL); 387a1b469b8SAriel Elior } 388a1b469b8SAriel Elior 389a1b469b8SAriel Elior /* should have been depleted by now */ 390a1b469b8SAriel Elior if (usage) { 391a1b469b8SAriel Elior DP_NOTICE(p_hwfn->cdev, 392a1b469b8SAriel Elior "DB recovery: doorbell usage failed to zero after %d usec. usage was %x\n", 393a1b469b8SAriel Elior QED_DB_REC_INTERVAL * QED_DB_REC_COUNT, usage); 394a1b469b8SAriel Elior return -EBUSY; 395a1b469b8SAriel Elior } 396a1b469b8SAriel Elior 397a1b469b8SAriel Elior return 0; 398a1b469b8SAriel Elior } 399a1b469b8SAriel Elior 400a1b469b8SAriel Elior int qed_db_rec_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 401a1b469b8SAriel Elior { 4020d72c2acSDenis Bolotin u32 attn_ovfl, cur_ovfl; 403a1b469b8SAriel Elior int rc; 404a1b469b8SAriel Elior 4050d72c2acSDenis Bolotin attn_ovfl = test_and_clear_bit(QED_OVERFLOW_BIT, 4060d72c2acSDenis Bolotin &p_hwfn->db_recovery_info.overflow); 4070d72c2acSDenis Bolotin cur_ovfl = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY); 4080d72c2acSDenis Bolotin if (!cur_ovfl && !attn_ovfl) 409a1b469b8SAriel Elior return 0; 410a1b469b8SAriel Elior 4110d72c2acSDenis Bolotin DP_NOTICE(p_hwfn, "PF Overflow sticky: attn %u current %u\n", 4120d72c2acSDenis Bolotin attn_ovfl, cur_ovfl); 4130d72c2acSDenis Bolotin 4140d72c2acSDenis Bolotin if (cur_ovfl && !p_hwfn->db_bar_no_edpm) { 415a1b469b8SAriel Elior rc = qed_db_rec_flush_queue(p_hwfn, p_ptt); 416a1b469b8SAriel Elior if (rc) 417a1b469b8SAriel Elior return rc; 418a1b469b8SAriel Elior } 419a1b469b8SAriel Elior 420a1b469b8SAriel Elior /* Release overflow sticky indication (stop silently dropping everything) */ 421a1b469b8SAriel Elior qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0); 422a1b469b8SAriel Elior 423a1b469b8SAriel Elior /* Repeat all last doorbells (doorbell drop recovery) */ 4249ac6bb14SDenis Bolotin qed_db_recovery_execute(p_hwfn); 425a1b469b8SAriel Elior 426a1b469b8SAriel Elior return 0; 427a1b469b8SAriel Elior } 428a1b469b8SAriel Elior 4290d72c2acSDenis Bolotin static void qed_dorq_attn_overflow(struct qed_hwfn *p_hwfn) 4300d72c2acSDenis Bolotin { 4310d72c2acSDenis Bolotin struct qed_ptt *p_ptt = p_hwfn->p_dpc_ptt; 4320d72c2acSDenis Bolotin u32 overflow; 4330d72c2acSDenis Bolotin int rc; 4340d72c2acSDenis Bolotin 4350d72c2acSDenis Bolotin overflow = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY); 4360d72c2acSDenis Bolotin if (!overflow) 4370d72c2acSDenis Bolotin goto out; 4380d72c2acSDenis Bolotin 4390d72c2acSDenis Bolotin /* Run PF doorbell recovery in next periodic handler */ 4400d72c2acSDenis Bolotin set_bit(QED_OVERFLOW_BIT, &p_hwfn->db_recovery_info.overflow); 4410d72c2acSDenis Bolotin 4420d72c2acSDenis Bolotin if (!p_hwfn->db_bar_no_edpm) { 4430d72c2acSDenis Bolotin rc = qed_db_rec_flush_queue(p_hwfn, p_ptt); 4440d72c2acSDenis Bolotin if (rc) 4450d72c2acSDenis Bolotin goto out; 4460d72c2acSDenis Bolotin } 4470d72c2acSDenis Bolotin 4480d72c2acSDenis Bolotin qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0); 4490d72c2acSDenis Bolotin out: 4500d72c2acSDenis Bolotin /* Schedule the handler even if overflow was not detected */ 4510d72c2acSDenis Bolotin qed_periodic_db_rec_start(p_hwfn); 4520d72c2acSDenis Bolotin } 4530d72c2acSDenis Bolotin 4540d72c2acSDenis Bolotin static int qed_dorq_attn_int_sts(struct qed_hwfn *p_hwfn) 455b4149dc7SYuval Mintz { 456a1b469b8SAriel Elior u32 int_sts, first_drop_reason, details, address, all_drops_reason; 457a1b469b8SAriel Elior struct qed_ptt *p_ptt = p_hwfn->p_dpc_ptt; 458a1b469b8SAriel Elior 459a1b469b8SAriel Elior /* int_sts may be zero since all PFs were interrupted for doorbell 460a1b469b8SAriel Elior * overflow but another one already handled it. Can abort here. If 461a1b469b8SAriel Elior * This PF also requires overflow recovery we will be interrupted again. 462a1b469b8SAriel Elior * The masked almost full indication may also be set. Ignoring. 463a1b469b8SAriel Elior */ 464d4476b8aSDenis Bolotin int_sts = qed_rd(p_hwfn, p_ptt, DORQ_REG_INT_STS); 465a1b469b8SAriel Elior if (!(int_sts & ~DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) 466a1b469b8SAriel Elior return 0; 467a1b469b8SAriel Elior 468d4476b8aSDenis Bolotin DP_NOTICE(p_hwfn->cdev, "DORQ attention. int_sts was %x\n", int_sts); 469d4476b8aSDenis Bolotin 470a1b469b8SAriel Elior /* check if db_drop or overflow happened */ 471a1b469b8SAriel Elior if (int_sts & (DORQ_REG_INT_STS_DB_DROP | 472a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR)) { 473a1b469b8SAriel Elior /* Obtain data about db drop/overflow */ 474a1b469b8SAriel Elior first_drop_reason = qed_rd(p_hwfn, p_ptt, 475a1b469b8SAriel Elior DORQ_REG_DB_DROP_REASON) & 476b4149dc7SYuval Mintz QED_DORQ_ATTENTION_REASON_MASK; 477a1b469b8SAriel Elior details = qed_rd(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS); 478a1b469b8SAriel Elior address = qed_rd(p_hwfn, p_ptt, 479a1b469b8SAriel Elior DORQ_REG_DB_DROP_DETAILS_ADDRESS); 480a1b469b8SAriel Elior all_drops_reason = qed_rd(p_hwfn, p_ptt, 481a1b469b8SAriel Elior DORQ_REG_DB_DROP_DETAILS_REASON); 482b4149dc7SYuval Mintz 483a1b469b8SAriel Elior /* Log info */ 484a1b469b8SAriel Elior DP_NOTICE(p_hwfn->cdev, 485a1b469b8SAriel Elior "Doorbell drop occurred\n" 486a1b469b8SAriel Elior "Address\t\t0x%08x\t(second BAR address)\n" 487a1b469b8SAriel Elior "FID\t\t0x%04x\t\t(Opaque FID)\n" 488a1b469b8SAriel Elior "Size\t\t0x%04x\t\t(in bytes)\n" 489a1b469b8SAriel Elior "1st drop reason\t0x%08x\t(details on first drop since last handling)\n" 490a1b469b8SAriel Elior "Sticky reasons\t0x%08x\t(all drop reasons since last handling)\n", 491a1b469b8SAriel Elior address, 492a1b469b8SAriel Elior GET_FIELD(details, QED_DORQ_ATTENTION_OPAQUE), 493b4149dc7SYuval Mintz GET_FIELD(details, QED_DORQ_ATTENTION_SIZE) * 4, 494a1b469b8SAriel Elior first_drop_reason, all_drops_reason); 495a1b469b8SAriel Elior 496a1b469b8SAriel Elior /* Clear the doorbell drop details and prepare for next drop */ 497a1b469b8SAriel Elior qed_wr(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS_REL, 0); 498a1b469b8SAriel Elior 499a1b469b8SAriel Elior /* Mark interrupt as handled (note: even if drop was due to a different 500a1b469b8SAriel Elior * reason than overflow we mark as handled) 501a1b469b8SAriel Elior */ 502a1b469b8SAriel Elior qed_wr(p_hwfn, 503a1b469b8SAriel Elior p_ptt, 504a1b469b8SAriel Elior DORQ_REG_INT_STS_WR, 505a1b469b8SAriel Elior DORQ_REG_INT_STS_DB_DROP | 506a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR); 507a1b469b8SAriel Elior 508a1b469b8SAriel Elior /* If there are no indications other than drop indications, success */ 509a1b469b8SAriel Elior if ((int_sts & ~(DORQ_REG_INT_STS_DB_DROP | 510a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR | 511a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) == 0) 512a1b469b8SAriel Elior return 0; 513b4149dc7SYuval Mintz } 514b4149dc7SYuval Mintz 515a1b469b8SAriel Elior /* Some other indication was present - non recoverable */ 516a1b469b8SAriel Elior DP_INFO(p_hwfn, "DORQ fatal attention\n"); 517a1b469b8SAriel Elior 518b4149dc7SYuval Mintz return -EINVAL; 519b4149dc7SYuval Mintz } 520b4149dc7SYuval Mintz 5210d72c2acSDenis Bolotin static int qed_dorq_attn_cb(struct qed_hwfn *p_hwfn) 5220d72c2acSDenis Bolotin { 5230d72c2acSDenis Bolotin p_hwfn->db_recovery_info.dorq_attn = true; 5240d72c2acSDenis Bolotin qed_dorq_attn_overflow(p_hwfn); 5250d72c2acSDenis Bolotin 5260d72c2acSDenis Bolotin return qed_dorq_attn_int_sts(p_hwfn); 5270d72c2acSDenis Bolotin } 5280d72c2acSDenis Bolotin 529d4476b8aSDenis Bolotin static void qed_dorq_attn_handler(struct qed_hwfn *p_hwfn) 530d4476b8aSDenis Bolotin { 531d4476b8aSDenis Bolotin if (p_hwfn->db_recovery_info.dorq_attn) 532d4476b8aSDenis Bolotin goto out; 533d4476b8aSDenis Bolotin 534d4476b8aSDenis Bolotin /* Call DORQ callback if the attention was missed */ 535d4476b8aSDenis Bolotin qed_dorq_attn_cb(p_hwfn); 536d4476b8aSDenis Bolotin out: 537d4476b8aSDenis Bolotin p_hwfn->db_recovery_info.dorq_attn = false; 538d4476b8aSDenis Bolotin } 539d4476b8aSDenis Bolotin 540ba36f718SMintz, Yuval /* Instead of major changes to the data-structure, we have a some 'special' 541ba36f718SMintz, Yuval * identifiers for sources that changed meaning between adapters. 542ba36f718SMintz, Yuval */ 543ba36f718SMintz, Yuval enum aeu_invert_reg_special_type { 544ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_0, 545ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_1, 546ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_2, 547ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_3, 548ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_MAX, 549ba36f718SMintz, Yuval }; 550ba36f718SMintz, Yuval 551ba36f718SMintz, Yuval static struct aeu_invert_reg_bit 552ba36f718SMintz, Yuval aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = { 553ba36f718SMintz, Yuval {"CNIG port 0", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 554ba36f718SMintz, Yuval {"CNIG port 1", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 555ba36f718SMintz, Yuval {"CNIG port 2", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 556ba36f718SMintz, Yuval {"CNIG port 3", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 557ba36f718SMintz, Yuval }; 558ba36f718SMintz, Yuval 5590d956e8aSYuval Mintz /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */ 5600d956e8aSYuval Mintz static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = { 5610d956e8aSYuval Mintz { 5620d956e8aSYuval Mintz { /* After Invert 1 */ 5630d956e8aSYuval Mintz {"GPIO0 function%d", 564b4149dc7SYuval Mintz (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 5650d956e8aSYuval Mintz } 5660d956e8aSYuval Mintz }, 5670d956e8aSYuval Mintz 5680d956e8aSYuval Mintz { 5690d956e8aSYuval Mintz { /* After Invert 2 */ 570b4149dc7SYuval Mintz {"PGLUE config_space", ATTENTION_SINGLE, 571b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 572b4149dc7SYuval Mintz {"PGLUE misc_flr", ATTENTION_SINGLE, 573b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 574b4149dc7SYuval Mintz {"PGLUE B RBC", ATTENTION_PAR_INT, 575666db486STomer Tayar qed_pglueb_rbc_attn_cb, BLOCK_PGLUE_B}, 576b4149dc7SYuval Mintz {"PGLUE misc_mctp", ATTENTION_SINGLE, 577b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 578b4149dc7SYuval Mintz {"Flash event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 579b4149dc7SYuval Mintz {"SMB event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 580b4149dc7SYuval Mintz {"Main Power", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 5810d956e8aSYuval Mintz {"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) | 582ff38577aSYuval Mintz (1 << ATTENTION_OFFSET_SHIFT), 583b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 5840d956e8aSYuval Mintz {"PCIE glue/PXP VPD %d", 585b4149dc7SYuval Mintz (16 << ATTENTION_LENGTH_SHIFT), NULL, BLOCK_PGLCS}, 5860d956e8aSYuval Mintz } 5870d956e8aSYuval Mintz }, 5880d956e8aSYuval Mintz 5890d956e8aSYuval Mintz { 5900d956e8aSYuval Mintz { /* After Invert 3 */ 5910d956e8aSYuval Mintz {"General Attention %d", 592b4149dc7SYuval Mintz (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 5930d956e8aSYuval Mintz } 5940d956e8aSYuval Mintz }, 5950d956e8aSYuval Mintz 5960d956e8aSYuval Mintz { 5970d956e8aSYuval Mintz { /* After Invert 4 */ 598936c7ba4SIgor Russkikh {"General Attention 32", ATTENTION_SINGLE | 599936c7ba4SIgor Russkikh ATTENTION_CLEAR_ENABLE, qed_fw_assertion, 6002ec276d5SIgor Russkikh MAX_BLOCK_ID}, 6010d956e8aSYuval Mintz {"General Attention %d", 6020d956e8aSYuval Mintz (2 << ATTENTION_LENGTH_SHIFT) | 603b4149dc7SYuval Mintz (33 << ATTENTION_OFFSET_SHIFT), NULL, MAX_BLOCK_ID}, 604936c7ba4SIgor Russkikh {"General Attention 35", ATTENTION_SINGLE | 605936c7ba4SIgor Russkikh ATTENTION_CLEAR_ENABLE, qed_general_attention_35, 606936c7ba4SIgor Russkikh MAX_BLOCK_ID}, 607ba36f718SMintz, Yuval {"NWS Parity", 608ba36f718SMintz, Yuval ATTENTION_PAR | ATTENTION_BB_DIFFERENT | 609ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_0), 610ba36f718SMintz, Yuval NULL, BLOCK_NWS}, 611ba36f718SMintz, Yuval {"NWS Interrupt", 612ba36f718SMintz, Yuval ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT | 613ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_1), 614ba36f718SMintz, Yuval NULL, BLOCK_NWS}, 615ba36f718SMintz, Yuval {"NWM Parity", 616ba36f718SMintz, Yuval ATTENTION_PAR | ATTENTION_BB_DIFFERENT | 617ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_2), 618ba36f718SMintz, Yuval NULL, BLOCK_NWM}, 619ba36f718SMintz, Yuval {"NWM Interrupt", 620ba36f718SMintz, Yuval ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT | 621ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_3), 622ba36f718SMintz, Yuval NULL, BLOCK_NWM}, 623b4149dc7SYuval Mintz {"MCP CPU", ATTENTION_SINGLE, 624b4149dc7SYuval Mintz qed_mcp_attn_cb, MAX_BLOCK_ID}, 625b4149dc7SYuval Mintz {"MCP Watchdog timer", ATTENTION_SINGLE, 626b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 627b4149dc7SYuval Mintz {"MCP M2P", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 628ff38577aSYuval Mintz {"AVS stop status ready", ATTENTION_SINGLE, 629b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 630b4149dc7SYuval Mintz {"MSTAT", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 631b4149dc7SYuval Mintz {"MSTAT per-path", ATTENTION_PAR_INT, 632b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 633ff38577aSYuval Mintz {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), 634b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 635b4149dc7SYuval Mintz {"NIG", ATTENTION_PAR_INT, NULL, BLOCK_NIG}, 636b4149dc7SYuval Mintz {"BMB/OPTE/MCP", ATTENTION_PAR_INT, NULL, BLOCK_BMB}, 637b4149dc7SYuval Mintz {"BTB", ATTENTION_PAR_INT, NULL, BLOCK_BTB}, 638b4149dc7SYuval Mintz {"BRB", ATTENTION_PAR_INT, NULL, BLOCK_BRB}, 639b4149dc7SYuval Mintz {"PRS", ATTENTION_PAR_INT, NULL, BLOCK_PRS}, 6400d956e8aSYuval Mintz } 6410d956e8aSYuval Mintz }, 6420d956e8aSYuval Mintz 6430d956e8aSYuval Mintz { 6440d956e8aSYuval Mintz { /* After Invert 5 */ 645b4149dc7SYuval Mintz {"SRC", ATTENTION_PAR_INT, NULL, BLOCK_SRC}, 646b4149dc7SYuval Mintz {"PB Client1", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB1}, 647b4149dc7SYuval Mintz {"PB Client2", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB2}, 648b4149dc7SYuval Mintz {"RPB", ATTENTION_PAR_INT, NULL, BLOCK_RPB}, 649b4149dc7SYuval Mintz {"PBF", ATTENTION_PAR_INT, NULL, BLOCK_PBF}, 650b4149dc7SYuval Mintz {"QM", ATTENTION_PAR_INT, NULL, BLOCK_QM}, 651b4149dc7SYuval Mintz {"TM", ATTENTION_PAR_INT, NULL, BLOCK_TM}, 652b4149dc7SYuval Mintz {"MCM", ATTENTION_PAR_INT, NULL, BLOCK_MCM}, 653b4149dc7SYuval Mintz {"MSDM", ATTENTION_PAR_INT, NULL, BLOCK_MSDM}, 654b4149dc7SYuval Mintz {"MSEM", ATTENTION_PAR_INT, NULL, BLOCK_MSEM}, 655b4149dc7SYuval Mintz {"PCM", ATTENTION_PAR_INT, NULL, BLOCK_PCM}, 656b4149dc7SYuval Mintz {"PSDM", ATTENTION_PAR_INT, NULL, BLOCK_PSDM}, 657b4149dc7SYuval Mintz {"PSEM", ATTENTION_PAR_INT, NULL, BLOCK_PSEM}, 658b4149dc7SYuval Mintz {"TCM", ATTENTION_PAR_INT, NULL, BLOCK_TCM}, 659b4149dc7SYuval Mintz {"TSDM", ATTENTION_PAR_INT, NULL, BLOCK_TSDM}, 660b4149dc7SYuval Mintz {"TSEM", ATTENTION_PAR_INT, NULL, BLOCK_TSEM}, 6610d956e8aSYuval Mintz } 6620d956e8aSYuval Mintz }, 6630d956e8aSYuval Mintz 6640d956e8aSYuval Mintz { 6650d956e8aSYuval Mintz { /* After Invert 6 */ 666b4149dc7SYuval Mintz {"UCM", ATTENTION_PAR_INT, NULL, BLOCK_UCM}, 667b4149dc7SYuval Mintz {"USDM", ATTENTION_PAR_INT, NULL, BLOCK_USDM}, 668b4149dc7SYuval Mintz {"USEM", ATTENTION_PAR_INT, NULL, BLOCK_USEM}, 669b4149dc7SYuval Mintz {"XCM", ATTENTION_PAR_INT, NULL, BLOCK_XCM}, 670b4149dc7SYuval Mintz {"XSDM", ATTENTION_PAR_INT, NULL, BLOCK_XSDM}, 671b4149dc7SYuval Mintz {"XSEM", ATTENTION_PAR_INT, NULL, BLOCK_XSEM}, 672b4149dc7SYuval Mintz {"YCM", ATTENTION_PAR_INT, NULL, BLOCK_YCM}, 673b4149dc7SYuval Mintz {"YSDM", ATTENTION_PAR_INT, NULL, BLOCK_YSDM}, 674b4149dc7SYuval Mintz {"YSEM", ATTENTION_PAR_INT, NULL, BLOCK_YSEM}, 675b4149dc7SYuval Mintz {"XYLD", ATTENTION_PAR_INT, NULL, BLOCK_XYLD}, 676b4149dc7SYuval Mintz {"TMLD", ATTENTION_PAR_INT, NULL, BLOCK_TMLD}, 677b4149dc7SYuval Mintz {"MYLD", ATTENTION_PAR_INT, NULL, BLOCK_MULD}, 678b4149dc7SYuval Mintz {"YULD", ATTENTION_PAR_INT, NULL, BLOCK_YULD}, 679b4149dc7SYuval Mintz {"DORQ", ATTENTION_PAR_INT, 680b4149dc7SYuval Mintz qed_dorq_attn_cb, BLOCK_DORQ}, 681b4149dc7SYuval Mintz {"DBG", ATTENTION_PAR_INT, NULL, BLOCK_DBG}, 682b4149dc7SYuval Mintz {"IPC", ATTENTION_PAR_INT, NULL, BLOCK_IPC}, 6830d956e8aSYuval Mintz } 6840d956e8aSYuval Mintz }, 6850d956e8aSYuval Mintz 6860d956e8aSYuval Mintz { 6870d956e8aSYuval Mintz { /* After Invert 7 */ 688b4149dc7SYuval Mintz {"CCFC", ATTENTION_PAR_INT, NULL, BLOCK_CCFC}, 689b4149dc7SYuval Mintz {"CDU", ATTENTION_PAR_INT, NULL, BLOCK_CDU}, 690b4149dc7SYuval Mintz {"DMAE", ATTENTION_PAR_INT, NULL, BLOCK_DMAE}, 691b4149dc7SYuval Mintz {"IGU", ATTENTION_PAR_INT, NULL, BLOCK_IGU}, 692b4149dc7SYuval Mintz {"ATC", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 693b4149dc7SYuval Mintz {"CAU", ATTENTION_PAR_INT, NULL, BLOCK_CAU}, 694b4149dc7SYuval Mintz {"PTU", ATTENTION_PAR_INT, NULL, BLOCK_PTU}, 695b4149dc7SYuval Mintz {"PRM", ATTENTION_PAR_INT, NULL, BLOCK_PRM}, 696b4149dc7SYuval Mintz {"TCFC", ATTENTION_PAR_INT, NULL, BLOCK_TCFC}, 697b4149dc7SYuval Mintz {"RDIF", ATTENTION_PAR_INT, NULL, BLOCK_RDIF}, 698b4149dc7SYuval Mintz {"TDIF", ATTENTION_PAR_INT, NULL, BLOCK_TDIF}, 699b4149dc7SYuval Mintz {"RSS", ATTENTION_PAR_INT, NULL, BLOCK_RSS}, 700b4149dc7SYuval Mintz {"MISC", ATTENTION_PAR_INT, NULL, BLOCK_MISC}, 701b4149dc7SYuval Mintz {"MISCS", ATTENTION_PAR_INT, NULL, BLOCK_MISCS}, 702b4149dc7SYuval Mintz {"PCIE", ATTENTION_PAR, NULL, BLOCK_PCIE}, 703b4149dc7SYuval Mintz {"Vaux PCI core", ATTENTION_SINGLE, NULL, BLOCK_PGLCS}, 704b4149dc7SYuval Mintz {"PSWRQ", ATTENTION_PAR_INT, NULL, BLOCK_PSWRQ}, 7050d956e8aSYuval Mintz } 7060d956e8aSYuval Mintz }, 7070d956e8aSYuval Mintz 7080d956e8aSYuval Mintz { 7090d956e8aSYuval Mintz { /* After Invert 8 */ 710b4149dc7SYuval Mintz {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, 711b4149dc7SYuval Mintz NULL, BLOCK_PSWRQ2}, 712b4149dc7SYuval Mintz {"PSWWR", ATTENTION_PAR_INT, NULL, BLOCK_PSWWR}, 713b4149dc7SYuval Mintz {"PSWWR (pci_clk)", ATTENTION_PAR_INT, 714b4149dc7SYuval Mintz NULL, BLOCK_PSWWR2}, 715b4149dc7SYuval Mintz {"PSWRD", ATTENTION_PAR_INT, NULL, BLOCK_PSWRD}, 716b4149dc7SYuval Mintz {"PSWRD (pci_clk)", ATTENTION_PAR_INT, 717b4149dc7SYuval Mintz NULL, BLOCK_PSWRD2}, 718b4149dc7SYuval Mintz {"PSWHST", ATTENTION_PAR_INT, 719b4149dc7SYuval Mintz qed_pswhst_attn_cb, BLOCK_PSWHST}, 720b4149dc7SYuval Mintz {"PSWHST (pci_clk)", ATTENTION_PAR_INT, 721b4149dc7SYuval Mintz NULL, BLOCK_PSWHST2}, 722b4149dc7SYuval Mintz {"GRC", ATTENTION_PAR_INT, 723b4149dc7SYuval Mintz qed_grc_attn_cb, BLOCK_GRC}, 724b4149dc7SYuval Mintz {"CPMU", ATTENTION_PAR_INT, NULL, BLOCK_CPMU}, 725b4149dc7SYuval Mintz {"NCSI", ATTENTION_PAR_INT, NULL, BLOCK_NCSI}, 726b4149dc7SYuval Mintz {"MSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 727b4149dc7SYuval Mintz {"PSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 728b4149dc7SYuval Mintz {"TSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 729b4149dc7SYuval Mintz {"USEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 730b4149dc7SYuval Mintz {"XSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 731b4149dc7SYuval Mintz {"YSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 732b4149dc7SYuval Mintz {"pxp_misc_mps", ATTENTION_PAR, NULL, BLOCK_PGLCS}, 733ff38577aSYuval Mintz {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, 734b4149dc7SYuval Mintz NULL, BLOCK_PGLCS}, 735b4149dc7SYuval Mintz {"PERST_B assertion", ATTENTION_SINGLE, 736b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 737ff38577aSYuval Mintz {"PERST_B deassertion", ATTENTION_SINGLE, 738b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 739ff38577aSYuval Mintz {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), 740b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 7410d956e8aSYuval Mintz } 7420d956e8aSYuval Mintz }, 7430d956e8aSYuval Mintz 7440d956e8aSYuval Mintz { 7450d956e8aSYuval Mintz { /* After Invert 9 */ 746b4149dc7SYuval Mintz {"MCP Latched memory", ATTENTION_PAR, 747b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 748ff38577aSYuval Mintz {"MCP Latched scratchpad cache", ATTENTION_SINGLE, 749b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 750b4149dc7SYuval Mintz {"MCP Latched ump_tx", ATTENTION_PAR, 751b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 752ff38577aSYuval Mintz {"MCP Latched scratchpad", ATTENTION_PAR, 753b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 754ff38577aSYuval Mintz {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT), 755b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 7560d956e8aSYuval Mintz } 7570d956e8aSYuval Mintz }, 7580d956e8aSYuval Mintz }; 7590d956e8aSYuval Mintz 760ba36f718SMintz, Yuval static struct aeu_invert_reg_bit * 761ba36f718SMintz, Yuval qed_int_aeu_translate(struct qed_hwfn *p_hwfn, 762ba36f718SMintz, Yuval struct aeu_invert_reg_bit *p_bit) 763ba36f718SMintz, Yuval { 764ba36f718SMintz, Yuval if (!QED_IS_BB(p_hwfn->cdev)) 765ba36f718SMintz, Yuval return p_bit; 766ba36f718SMintz, Yuval 767ba36f718SMintz, Yuval if (!(p_bit->flags & ATTENTION_BB_DIFFERENT)) 768ba36f718SMintz, Yuval return p_bit; 769ba36f718SMintz, Yuval 770ba36f718SMintz, Yuval return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >> 771ba36f718SMintz, Yuval ATTENTION_BB_SHIFT]; 772ba36f718SMintz, Yuval } 773ba36f718SMintz, Yuval 774ba36f718SMintz, Yuval static bool qed_int_is_parity_flag(struct qed_hwfn *p_hwfn, 775ba36f718SMintz, Yuval struct aeu_invert_reg_bit *p_bit) 776ba36f718SMintz, Yuval { 777ba36f718SMintz, Yuval return !!(qed_int_aeu_translate(p_hwfn, p_bit)->flags & 778ba36f718SMintz, Yuval ATTENTION_PARITY); 779ba36f718SMintz, Yuval } 780ba36f718SMintz, Yuval 781cc875c2eSYuval Mintz #define ATTN_STATE_BITS (0xfff) 782cc875c2eSYuval Mintz #define ATTN_BITS_MASKABLE (0x3ff) 783cc875c2eSYuval Mintz struct qed_sb_attn_info { 784cc875c2eSYuval Mintz /* Virtual & Physical address of the SB */ 785cc875c2eSYuval Mintz struct atten_status_block *sb_attn; 786cc875c2eSYuval Mintz dma_addr_t sb_phys; 787cc875c2eSYuval Mintz 788cc875c2eSYuval Mintz /* Last seen running index */ 789cc875c2eSYuval Mintz u16 index; 790cc875c2eSYuval Mintz 7910d956e8aSYuval Mintz /* A mask of the AEU bits resulting in a parity error */ 7920d956e8aSYuval Mintz u32 parity_mask[NUM_ATTN_REGS]; 7930d956e8aSYuval Mintz 7940d956e8aSYuval Mintz /* A pointer to the attention description structure */ 7950d956e8aSYuval Mintz struct aeu_invert_reg *p_aeu_desc; 7960d956e8aSYuval Mintz 797cc875c2eSYuval Mintz /* Previously asserted attentions, which are still unasserted */ 798cc875c2eSYuval Mintz u16 known_attn; 799cc875c2eSYuval Mintz 800cc875c2eSYuval Mintz /* Cleanup address for the link's general hw attention */ 801cc875c2eSYuval Mintz u32 mfw_attn_addr; 802cc875c2eSYuval Mintz }; 803cc875c2eSYuval Mintz 804cc875c2eSYuval Mintz static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn, 805cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb_desc) 806cc875c2eSYuval Mintz { 8071a635e48SYuval Mintz u16 rc = 0, index; 808cc875c2eSYuval Mintz 809cc875c2eSYuval Mintz index = le16_to_cpu(p_sb_desc->sb_attn->sb_index); 810cc875c2eSYuval Mintz if (p_sb_desc->index != index) { 811cc875c2eSYuval Mintz p_sb_desc->index = index; 812cc875c2eSYuval Mintz rc = QED_SB_ATT_IDX; 813cc875c2eSYuval Mintz } 814cc875c2eSYuval Mintz 815cc875c2eSYuval Mintz return rc; 816cc875c2eSYuval Mintz } 817cc875c2eSYuval Mintz 818cc875c2eSYuval Mintz /** 819cc875c2eSYuval Mintz * @brief qed_int_assertion - handles asserted attention bits 820cc875c2eSYuval Mintz * 821cc875c2eSYuval Mintz * @param p_hwfn 822cc875c2eSYuval Mintz * @param asserted_bits newly asserted bits 823cc875c2eSYuval Mintz * @return int 824cc875c2eSYuval Mintz */ 8251a635e48SYuval Mintz static int qed_int_assertion(struct qed_hwfn *p_hwfn, u16 asserted_bits) 826cc875c2eSYuval Mintz { 827cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 828cc875c2eSYuval Mintz u32 igu_mask; 829cc875c2eSYuval Mintz 830cc875c2eSYuval Mintz /* Mask the source of the attention in the IGU */ 8311a635e48SYuval Mintz igu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); 832cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n", 833cc875c2eSYuval Mintz igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE)); 834cc875c2eSYuval Mintz igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE); 835cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask); 836cc875c2eSYuval Mintz 837cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 838cc875c2eSYuval Mintz "inner known ATTN state: 0x%04x --> 0x%04x\n", 839cc875c2eSYuval Mintz sb_attn_sw->known_attn, 840cc875c2eSYuval Mintz sb_attn_sw->known_attn | asserted_bits); 841cc875c2eSYuval Mintz sb_attn_sw->known_attn |= asserted_bits; 842cc875c2eSYuval Mintz 843cc875c2eSYuval Mintz /* Handle MCP events */ 844cc875c2eSYuval Mintz if (asserted_bits & 0x100) { 845cc875c2eSYuval Mintz qed_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt); 846cc875c2eSYuval Mintz /* Clean the MCP attention */ 847cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 848cc875c2eSYuval Mintz sb_attn_sw->mfw_attn_addr, 0); 849cc875c2eSYuval Mintz } 850cc875c2eSYuval Mintz 851cc875c2eSYuval Mintz DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 852cc875c2eSYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 853cc875c2eSYuval Mintz ((IGU_CMD_ATTN_BIT_SET_UPPER - 854cc875c2eSYuval Mintz IGU_CMD_INT_ACK_BASE) << 3), 855cc875c2eSYuval Mintz (u32)asserted_bits); 856cc875c2eSYuval Mintz 857cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "set cmd IGU: 0x%04x\n", 858cc875c2eSYuval Mintz asserted_bits); 859cc875c2eSYuval Mintz 860cc875c2eSYuval Mintz return 0; 861cc875c2eSYuval Mintz } 862cc875c2eSYuval Mintz 8630ebbd1c8SMintz, Yuval static void qed_int_attn_print(struct qed_hwfn *p_hwfn, 8640ebbd1c8SMintz, Yuval enum block_id id, 8650ebbd1c8SMintz, Yuval enum dbg_attn_type type, bool b_clear) 866ff38577aSYuval Mintz { 8670ebbd1c8SMintz, Yuval struct dbg_attn_block_result attn_results; 8680ebbd1c8SMintz, Yuval enum dbg_status status; 869ff38577aSYuval Mintz 8700ebbd1c8SMintz, Yuval memset(&attn_results, 0, sizeof(attn_results)); 871ff38577aSYuval Mintz 8720ebbd1c8SMintz, Yuval status = qed_dbg_read_attn(p_hwfn, p_hwfn->p_dpc_ptt, id, type, 8730ebbd1c8SMintz, Yuval b_clear, &attn_results); 8740ebbd1c8SMintz, Yuval if (status != DBG_STATUS_OK) 875ff38577aSYuval Mintz DP_NOTICE(p_hwfn, 8760ebbd1c8SMintz, Yuval "Failed to parse attention information [status: %s]\n", 8770ebbd1c8SMintz, Yuval qed_dbg_get_status_str(status)); 8780ebbd1c8SMintz, Yuval else 8790ebbd1c8SMintz, Yuval qed_dbg_parse_attn(p_hwfn, &attn_results); 880ff38577aSYuval Mintz } 881ff38577aSYuval Mintz 882cc875c2eSYuval Mintz /** 8830d956e8aSYuval Mintz * @brief qed_int_deassertion_aeu_bit - handles the effects of a single 8840d956e8aSYuval Mintz * cause of the attention 8850d956e8aSYuval Mintz * 8860d956e8aSYuval Mintz * @param p_hwfn 8870d956e8aSYuval Mintz * @param p_aeu - descriptor of an AEU bit which caused the attention 8880d956e8aSYuval Mintz * @param aeu_en_reg - register offset of the AEU enable reg. which configured 8890d956e8aSYuval Mintz * this bit to this group. 8900d956e8aSYuval Mintz * @param bit_index - index of this bit in the aeu_en_reg 8910d956e8aSYuval Mintz * 8920d956e8aSYuval Mintz * @return int 8930d956e8aSYuval Mintz */ 8940d956e8aSYuval Mintz static int 8950d956e8aSYuval Mintz qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn, 8960d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_aeu, 8970d956e8aSYuval Mintz u32 aeu_en_reg, 8986010179dSMintz, Yuval const char *p_bit_name, u32 bitmask) 8990d956e8aSYuval Mintz { 9000ebbd1c8SMintz, Yuval bool b_fatal = false; 9010d956e8aSYuval Mintz int rc = -EINVAL; 902b4149dc7SYuval Mintz u32 val; 9030d956e8aSYuval Mintz 9040d956e8aSYuval Mintz DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n", 9056010179dSMintz, Yuval p_bit_name, bitmask); 9060d956e8aSYuval Mintz 907b4149dc7SYuval Mintz /* Call callback before clearing the interrupt status */ 908b4149dc7SYuval Mintz if (p_aeu->cb) { 909b4149dc7SYuval Mintz DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n", 9106010179dSMintz, Yuval p_bit_name); 911b4149dc7SYuval Mintz rc = p_aeu->cb(p_hwfn); 912b4149dc7SYuval Mintz } 913b4149dc7SYuval Mintz 9140ebbd1c8SMintz, Yuval if (rc) 9150ebbd1c8SMintz, Yuval b_fatal = true; 916ff38577aSYuval Mintz 9170ebbd1c8SMintz, Yuval /* Print HW block interrupt registers */ 9180ebbd1c8SMintz, Yuval if (p_aeu->block_index != MAX_BLOCK_ID) 9190ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, p_aeu->block_index, 9200ebbd1c8SMintz, Yuval ATTN_TYPE_INTERRUPT, !b_fatal); 921ff38577aSYuval Mintz 9222ec276d5SIgor Russkikh /* Reach assertion if attention is fatal */ 9232ec276d5SIgor Russkikh if (b_fatal) 9242ec276d5SIgor Russkikh qed_hw_err_notify(p_hwfn, p_hwfn->p_dpc_ptt, QED_HW_ERR_HW_ATTN, 9252ec276d5SIgor Russkikh "`%s': Fatal attention\n", 9262ec276d5SIgor Russkikh p_bit_name); 9272ec276d5SIgor Russkikh else /* If the attention is benign, no need to prevent it */ 928b4149dc7SYuval Mintz goto out; 929b4149dc7SYuval Mintz 9300d956e8aSYuval Mintz /* Prevent this Attention from being asserted in the future */ 9310d956e8aSYuval Mintz val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 932b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & ~bitmask)); 9330d956e8aSYuval Mintz DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n", 9346010179dSMintz, Yuval p_bit_name); 9350d956e8aSYuval Mintz 936b4149dc7SYuval Mintz out: 9370d956e8aSYuval Mintz return rc; 9380d956e8aSYuval Mintz } 9390d956e8aSYuval Mintz 940ff38577aSYuval Mintz /** 941ff38577aSYuval Mintz * @brief qed_int_deassertion_parity - handle a single parity AEU source 942ff38577aSYuval Mintz * 943ff38577aSYuval Mintz * @param p_hwfn 944ff38577aSYuval Mintz * @param p_aeu - descriptor of an AEU bit which caused the parity 9459790c35eSMintz, Yuval * @param aeu_en_reg - address of the AEU enable register 946ff38577aSYuval Mintz * @param bit_index 947ff38577aSYuval Mintz */ 948ff38577aSYuval Mintz static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn, 949ff38577aSYuval Mintz struct aeu_invert_reg_bit *p_aeu, 9509790c35eSMintz, Yuval u32 aeu_en_reg, u8 bit_index) 951ff38577aSYuval Mintz { 9529790c35eSMintz, Yuval u32 block_id = p_aeu->block_index, mask, val; 953ff38577aSYuval Mintz 9549790c35eSMintz, Yuval DP_NOTICE(p_hwfn->cdev, 9559790c35eSMintz, Yuval "%s parity attention is set [address 0x%08x, bit %d]\n", 9569790c35eSMintz, Yuval p_aeu->bit_name, aeu_en_reg, bit_index); 957ff38577aSYuval Mintz 958ff38577aSYuval Mintz if (block_id != MAX_BLOCK_ID) { 9590ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, block_id, ATTN_TYPE_PARITY, false); 960ff38577aSYuval Mintz 961ff38577aSYuval Mintz /* In BB, there's a single parity bit for several blocks */ 962ff38577aSYuval Mintz if (block_id == BLOCK_BTB) { 9630ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, BLOCK_OPTE, 9640ebbd1c8SMintz, Yuval ATTN_TYPE_PARITY, false); 9650ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, BLOCK_MCP, 9660ebbd1c8SMintz, Yuval ATTN_TYPE_PARITY, false); 967ff38577aSYuval Mintz } 968ff38577aSYuval Mintz } 9699790c35eSMintz, Yuval 9709790c35eSMintz, Yuval /* Prevent this parity error from being re-asserted */ 9719790c35eSMintz, Yuval mask = ~BIT(bit_index); 9729790c35eSMintz, Yuval val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 9739790c35eSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask); 9749790c35eSMintz, Yuval DP_INFO(p_hwfn, "`%s' - Disabled future parity errors\n", 9759790c35eSMintz, Yuval p_aeu->bit_name); 976ff38577aSYuval Mintz } 977ff38577aSYuval Mintz 9780d956e8aSYuval Mintz /** 979cc875c2eSYuval Mintz * @brief - handles deassertion of previously asserted attentions. 980cc875c2eSYuval Mintz * 981cc875c2eSYuval Mintz * @param p_hwfn 982cc875c2eSYuval Mintz * @param deasserted_bits - newly deasserted bits 983cc875c2eSYuval Mintz * @return int 984cc875c2eSYuval Mintz * 985cc875c2eSYuval Mintz */ 986cc875c2eSYuval Mintz static int qed_int_deassertion(struct qed_hwfn *p_hwfn, 987cc875c2eSYuval Mintz u16 deasserted_bits) 988cc875c2eSYuval Mintz { 989cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 9909790c35eSMintz, Yuval u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask, aeu_en, en; 9910d956e8aSYuval Mintz u8 i, j, k, bit_idx; 9920d956e8aSYuval Mintz int rc = 0; 993cc875c2eSYuval Mintz 9940d956e8aSYuval Mintz /* Read the attention registers in the AEU */ 9950d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 9960d956e8aSYuval Mintz aeu_inv_arr[i] = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 9970d956e8aSYuval Mintz MISC_REG_AEU_AFTER_INVERT_1_IGU + 9980d956e8aSYuval Mintz i * 0x4); 9990d956e8aSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 10000d956e8aSYuval Mintz "Deasserted bits [%d]: %08x\n", 10010d956e8aSYuval Mintz i, aeu_inv_arr[i]); 10020d956e8aSYuval Mintz } 10030d956e8aSYuval Mintz 10040d956e8aSYuval Mintz /* Find parity attentions first */ 10050d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 10060d956e8aSYuval Mintz struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i]; 10070d956e8aSYuval Mintz u32 parities; 10080d956e8aSYuval Mintz 10099790c35eSMintz, Yuval aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + i * sizeof(u32); 10109790c35eSMintz, Yuval en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 10119790c35eSMintz, Yuval 10120d956e8aSYuval Mintz /* Skip register in which no parity bit is currently set */ 10130d956e8aSYuval Mintz parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en; 10140d956e8aSYuval Mintz if (!parities) 10150d956e8aSYuval Mintz continue; 10160d956e8aSYuval Mintz 10170d956e8aSYuval Mintz for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 10180d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j]; 10190d956e8aSYuval Mintz 1020ba36f718SMintz, Yuval if (qed_int_is_parity_flag(p_hwfn, p_bit) && 10211a635e48SYuval Mintz !!(parities & BIT(bit_idx))) 1022ff38577aSYuval Mintz qed_int_deassertion_parity(p_hwfn, p_bit, 10239790c35eSMintz, Yuval aeu_en, bit_idx); 10240d956e8aSYuval Mintz 10250d956e8aSYuval Mintz bit_idx += ATTENTION_LENGTH(p_bit->flags); 10260d956e8aSYuval Mintz } 10270d956e8aSYuval Mintz } 10280d956e8aSYuval Mintz 10290d956e8aSYuval Mintz /* Find non-parity cause for attention and act */ 10300d956e8aSYuval Mintz for (k = 0; k < MAX_ATTN_GRPS; k++) { 10310d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_aeu; 10320d956e8aSYuval Mintz 10330d956e8aSYuval Mintz /* Handle only groups whose attention is currently deasserted */ 10340d956e8aSYuval Mintz if (!(deasserted_bits & (1 << k))) 10350d956e8aSYuval Mintz continue; 10360d956e8aSYuval Mintz 10370d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 10389790c35eSMintz, Yuval u32 bits; 10399790c35eSMintz, Yuval 10409790c35eSMintz, Yuval aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + 10410d956e8aSYuval Mintz i * sizeof(u32) + 10420d956e8aSYuval Mintz k * sizeof(u32) * NUM_ATTN_REGS; 10430d956e8aSYuval Mintz 10440d956e8aSYuval Mintz en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 10450d956e8aSYuval Mintz bits = aeu_inv_arr[i] & en; 10460d956e8aSYuval Mintz 10470d956e8aSYuval Mintz /* Skip if no bit from this group is currently set */ 10480d956e8aSYuval Mintz if (!bits) 10490d956e8aSYuval Mintz continue; 10500d956e8aSYuval Mintz 10510d956e8aSYuval Mintz /* Find all set bits from current register which belong 10520d956e8aSYuval Mintz * to current group, making them responsible for the 10530d956e8aSYuval Mintz * previous assertion. 10540d956e8aSYuval Mintz */ 10550d956e8aSYuval Mintz for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 10566010179dSMintz, Yuval long unsigned int bitmask; 10570d956e8aSYuval Mintz u8 bit, bit_len; 10580d956e8aSYuval Mintz 10590d956e8aSYuval Mintz p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j]; 1060ba36f718SMintz, Yuval p_aeu = qed_int_aeu_translate(p_hwfn, p_aeu); 10610d956e8aSYuval Mintz 10620d956e8aSYuval Mintz bit = bit_idx; 10630d956e8aSYuval Mintz bit_len = ATTENTION_LENGTH(p_aeu->flags); 1064ba36f718SMintz, Yuval if (qed_int_is_parity_flag(p_hwfn, p_aeu)) { 10650d956e8aSYuval Mintz /* Skip Parity */ 10660d956e8aSYuval Mintz bit++; 10670d956e8aSYuval Mintz bit_len--; 10680d956e8aSYuval Mintz } 10690d956e8aSYuval Mintz 10700d956e8aSYuval Mintz bitmask = bits & (((1 << bit_len) - 1) << bit); 10716010179dSMintz, Yuval bitmask >>= bit; 10726010179dSMintz, Yuval 10730d956e8aSYuval Mintz if (bitmask) { 10746010179dSMintz, Yuval u32 flags = p_aeu->flags; 10756010179dSMintz, Yuval char bit_name[30]; 10766010179dSMintz, Yuval u8 num; 10776010179dSMintz, Yuval 10786010179dSMintz, Yuval num = (u8)find_first_bit(&bitmask, 10796010179dSMintz, Yuval bit_len); 10806010179dSMintz, Yuval 10816010179dSMintz, Yuval /* Some bits represent more than a 10826010179dSMintz, Yuval * a single interrupt. Correctly print 10836010179dSMintz, Yuval * their name. 10846010179dSMintz, Yuval */ 10856010179dSMintz, Yuval if (ATTENTION_LENGTH(flags) > 2 || 10866010179dSMintz, Yuval ((flags & ATTENTION_PAR_INT) && 10876010179dSMintz, Yuval ATTENTION_LENGTH(flags) > 1)) 10886010179dSMintz, Yuval snprintf(bit_name, 30, 10896010179dSMintz, Yuval p_aeu->bit_name, num); 10906010179dSMintz, Yuval else 10913690c8c9SWang Xiayang strlcpy(bit_name, 10926010179dSMintz, Yuval p_aeu->bit_name, 30); 10936010179dSMintz, Yuval 10946010179dSMintz, Yuval /* We now need to pass bitmask in its 10956010179dSMintz, Yuval * correct position. 10966010179dSMintz, Yuval */ 10976010179dSMintz, Yuval bitmask <<= bit; 10986010179dSMintz, Yuval 10990d956e8aSYuval Mintz /* Handle source of the attention */ 11000d956e8aSYuval Mintz qed_int_deassertion_aeu_bit(p_hwfn, 11010d956e8aSYuval Mintz p_aeu, 11020d956e8aSYuval Mintz aeu_en, 11036010179dSMintz, Yuval bit_name, 11040d956e8aSYuval Mintz bitmask); 11050d956e8aSYuval Mintz } 11060d956e8aSYuval Mintz 11070d956e8aSYuval Mintz bit_idx += ATTENTION_LENGTH(p_aeu->flags); 11080d956e8aSYuval Mintz } 11090d956e8aSYuval Mintz } 11100d956e8aSYuval Mintz } 1111cc875c2eSYuval Mintz 1112d4476b8aSDenis Bolotin /* Handle missed DORQ attention */ 1113d4476b8aSDenis Bolotin qed_dorq_attn_handler(p_hwfn); 1114d4476b8aSDenis Bolotin 1115cc875c2eSYuval Mintz /* Clear IGU indication for the deasserted bits */ 1116cc875c2eSYuval Mintz DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 1117cc875c2eSYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 1118cc875c2eSYuval Mintz ((IGU_CMD_ATTN_BIT_CLR_UPPER - 1119cc875c2eSYuval Mintz IGU_CMD_INT_ACK_BASE) << 3), 1120cc875c2eSYuval Mintz ~((u32)deasserted_bits)); 1121cc875c2eSYuval Mintz 1122cc875c2eSYuval Mintz /* Unmask deasserted attentions in IGU */ 11231a635e48SYuval Mintz aeu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); 1124cc875c2eSYuval Mintz aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE); 1125cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask); 1126cc875c2eSYuval Mintz 1127cc875c2eSYuval Mintz /* Clear deassertion from inner state */ 1128cc875c2eSYuval Mintz sb_attn_sw->known_attn &= ~deasserted_bits; 1129cc875c2eSYuval Mintz 11300d956e8aSYuval Mintz return rc; 1131cc875c2eSYuval Mintz } 1132cc875c2eSYuval Mintz 1133cc875c2eSYuval Mintz static int qed_int_attentions(struct qed_hwfn *p_hwfn) 1134cc875c2eSYuval Mintz { 1135cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn; 1136cc875c2eSYuval Mintz struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn; 1137cc875c2eSYuval Mintz u32 attn_bits = 0, attn_acks = 0; 1138cc875c2eSYuval Mintz u16 asserted_bits, deasserted_bits; 1139cc875c2eSYuval Mintz __le16 index; 1140cc875c2eSYuval Mintz int rc = 0; 1141cc875c2eSYuval Mintz 1142cc875c2eSYuval Mintz /* Read current attention bits/acks - safeguard against attentions 1143cc875c2eSYuval Mintz * by guaranting work on a synchronized timeframe 1144cc875c2eSYuval Mintz */ 1145cc875c2eSYuval Mintz do { 1146cc875c2eSYuval Mintz index = p_sb_attn->sb_index; 1147ed4eac20SDenis Bolotin /* finish reading index before the loop condition */ 1148ed4eac20SDenis Bolotin dma_rmb(); 1149cc875c2eSYuval Mintz attn_bits = le32_to_cpu(p_sb_attn->atten_bits); 1150cc875c2eSYuval Mintz attn_acks = le32_to_cpu(p_sb_attn->atten_ack); 1151cc875c2eSYuval Mintz } while (index != p_sb_attn->sb_index); 1152cc875c2eSYuval Mintz p_sb_attn->sb_index = index; 1153cc875c2eSYuval Mintz 1154cc875c2eSYuval Mintz /* Attention / Deassertion are meaningful (and in correct state) 1155cc875c2eSYuval Mintz * only when they differ and consistent with known state - deassertion 1156cc875c2eSYuval Mintz * when previous attention & current ack, and assertion when current 1157cc875c2eSYuval Mintz * attention with no previous attention 1158cc875c2eSYuval Mintz */ 1159cc875c2eSYuval Mintz asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) & 1160cc875c2eSYuval Mintz ~p_sb_attn_sw->known_attn; 1161cc875c2eSYuval Mintz deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) & 1162cc875c2eSYuval Mintz p_sb_attn_sw->known_attn; 1163cc875c2eSYuval Mintz 1164cc875c2eSYuval Mintz if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100)) { 1165cc875c2eSYuval Mintz DP_INFO(p_hwfn, 1166cc875c2eSYuval Mintz "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n", 1167cc875c2eSYuval Mintz index, attn_bits, attn_acks, asserted_bits, 1168cc875c2eSYuval Mintz deasserted_bits, p_sb_attn_sw->known_attn); 1169cc875c2eSYuval Mintz } else if (asserted_bits == 0x100) { 11701a635e48SYuval Mintz DP_INFO(p_hwfn, "MFW indication via attention\n"); 1171cc875c2eSYuval Mintz } else { 1172cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1173cc875c2eSYuval Mintz "MFW indication [deassertion]\n"); 1174cc875c2eSYuval Mintz } 1175cc875c2eSYuval Mintz 1176cc875c2eSYuval Mintz if (asserted_bits) { 1177cc875c2eSYuval Mintz rc = qed_int_assertion(p_hwfn, asserted_bits); 1178cc875c2eSYuval Mintz if (rc) 1179cc875c2eSYuval Mintz return rc; 1180cc875c2eSYuval Mintz } 1181cc875c2eSYuval Mintz 11821a635e48SYuval Mintz if (deasserted_bits) 1183cc875c2eSYuval Mintz rc = qed_int_deassertion(p_hwfn, deasserted_bits); 1184cc875c2eSYuval Mintz 1185cc875c2eSYuval Mintz return rc; 1186cc875c2eSYuval Mintz } 1187cc875c2eSYuval Mintz 1188cc875c2eSYuval Mintz static void qed_sb_ack_attn(struct qed_hwfn *p_hwfn, 11891a635e48SYuval Mintz void __iomem *igu_addr, u32 ack_cons) 1190cc875c2eSYuval Mintz { 1191cc875c2eSYuval Mintz struct igu_prod_cons_update igu_ack = { 0 }; 1192cc875c2eSYuval Mintz 1193cc875c2eSYuval Mintz igu_ack.sb_id_and_flags = 1194cc875c2eSYuval Mintz ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 1195cc875c2eSYuval Mintz (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 1196cc875c2eSYuval Mintz (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 1197cc875c2eSYuval Mintz (IGU_SEG_ACCESS_ATTN << 1198cc875c2eSYuval Mintz IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 1199cc875c2eSYuval Mintz 1200cc875c2eSYuval Mintz DIRECT_REG_WR(igu_addr, igu_ack.sb_id_and_flags); 1201cc875c2eSYuval Mintz 1202cc875c2eSYuval Mintz /* Both segments (interrupts & acks) are written to same place address; 1203cc875c2eSYuval Mintz * Need to guarantee all commands will be received (in-order) by HW. 1204cc875c2eSYuval Mintz */ 1205cc875c2eSYuval Mintz barrier(); 1206cc875c2eSYuval Mintz } 1207cc875c2eSYuval Mintz 1208fe56b9e6SYuval Mintz void qed_int_sp_dpc(unsigned long hwfn_cookie) 1209fe56b9e6SYuval Mintz { 1210fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = (struct qed_hwfn *)hwfn_cookie; 1211fe56b9e6SYuval Mintz struct qed_pi_info *pi_info = NULL; 1212cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn; 1213fe56b9e6SYuval Mintz struct qed_sb_info *sb_info; 1214fe56b9e6SYuval Mintz int arr_size; 1215fe56b9e6SYuval Mintz u16 rc = 0; 1216fe56b9e6SYuval Mintz 1217fe56b9e6SYuval Mintz if (!p_hwfn->p_sp_sb) { 1218fe56b9e6SYuval Mintz DP_ERR(p_hwfn->cdev, "DPC called - no p_sp_sb\n"); 1219fe56b9e6SYuval Mintz return; 1220fe56b9e6SYuval Mintz } 1221fe56b9e6SYuval Mintz 1222fe56b9e6SYuval Mintz sb_info = &p_hwfn->p_sp_sb->sb_info; 1223fe56b9e6SYuval Mintz arr_size = ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr); 1224fe56b9e6SYuval Mintz if (!sb_info) { 1225fe56b9e6SYuval Mintz DP_ERR(p_hwfn->cdev, 1226fe56b9e6SYuval Mintz "Status block is NULL - cannot ack interrupts\n"); 1227fe56b9e6SYuval Mintz return; 1228fe56b9e6SYuval Mintz } 1229fe56b9e6SYuval Mintz 1230cc875c2eSYuval Mintz if (!p_hwfn->p_sb_attn) { 1231cc875c2eSYuval Mintz DP_ERR(p_hwfn->cdev, "DPC called - no p_sb_attn"); 1232cc875c2eSYuval Mintz return; 1233cc875c2eSYuval Mintz } 1234cc875c2eSYuval Mintz sb_attn = p_hwfn->p_sb_attn; 1235cc875c2eSYuval Mintz 1236fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "DPC Called! (hwfn %p %d)\n", 1237fe56b9e6SYuval Mintz p_hwfn, p_hwfn->my_id); 1238fe56b9e6SYuval Mintz 1239fe56b9e6SYuval Mintz /* Disable ack for def status block. Required both for msix + 1240fe56b9e6SYuval Mintz * inta in non-mask mode, in inta does no harm. 1241fe56b9e6SYuval Mintz */ 1242fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_DISABLE, 0); 1243fe56b9e6SYuval Mintz 1244fe56b9e6SYuval Mintz /* Gather Interrupts/Attentions information */ 1245fe56b9e6SYuval Mintz if (!sb_info->sb_virt) { 12461a635e48SYuval Mintz DP_ERR(p_hwfn->cdev, 1247fe56b9e6SYuval Mintz "Interrupt Status block is NULL - cannot check for new interrupts!\n"); 1248fe56b9e6SYuval Mintz } else { 1249fe56b9e6SYuval Mintz u32 tmp_index = sb_info->sb_ack; 1250fe56b9e6SYuval Mintz 1251fe56b9e6SYuval Mintz rc = qed_sb_update_sb_idx(sb_info); 1252fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 1253fe56b9e6SYuval Mintz "Interrupt indices: 0x%08x --> 0x%08x\n", 1254fe56b9e6SYuval Mintz tmp_index, sb_info->sb_ack); 1255fe56b9e6SYuval Mintz } 1256fe56b9e6SYuval Mintz 1257cc875c2eSYuval Mintz if (!sb_attn || !sb_attn->sb_attn) { 12581a635e48SYuval Mintz DP_ERR(p_hwfn->cdev, 1259cc875c2eSYuval Mintz "Attentions Status block is NULL - cannot check for new attentions!\n"); 1260cc875c2eSYuval Mintz } else { 1261cc875c2eSYuval Mintz u16 tmp_index = sb_attn->index; 1262cc875c2eSYuval Mintz 1263cc875c2eSYuval Mintz rc |= qed_attn_update_idx(p_hwfn, sb_attn); 1264cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 1265cc875c2eSYuval Mintz "Attention indices: 0x%08x --> 0x%08x\n", 1266cc875c2eSYuval Mintz tmp_index, sb_attn->index); 1267cc875c2eSYuval Mintz } 1268cc875c2eSYuval Mintz 1269fe56b9e6SYuval Mintz /* Check if we expect interrupts at this time. if not just ack them */ 1270fe56b9e6SYuval Mintz if (!(rc & QED_SB_EVENT_MASK)) { 1271fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1272fe56b9e6SYuval Mintz return; 1273fe56b9e6SYuval Mintz } 1274fe56b9e6SYuval Mintz 1275fe56b9e6SYuval Mintz /* Check the validity of the DPC ptt. If not ack interrupts and fail */ 1276fe56b9e6SYuval Mintz if (!p_hwfn->p_dpc_ptt) { 1277fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn->cdev, "Failed to allocate PTT\n"); 1278fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1279fe56b9e6SYuval Mintz return; 1280fe56b9e6SYuval Mintz } 1281fe56b9e6SYuval Mintz 1282cc875c2eSYuval Mintz if (rc & QED_SB_ATT_IDX) 1283cc875c2eSYuval Mintz qed_int_attentions(p_hwfn); 1284cc875c2eSYuval Mintz 1285fe56b9e6SYuval Mintz if (rc & QED_SB_IDX) { 1286fe56b9e6SYuval Mintz int pi; 1287fe56b9e6SYuval Mintz 1288fe56b9e6SYuval Mintz /* Look for a free index */ 1289fe56b9e6SYuval Mintz for (pi = 0; pi < arr_size; pi++) { 1290fe56b9e6SYuval Mintz pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi]; 1291fe56b9e6SYuval Mintz if (pi_info->comp_cb) 1292fe56b9e6SYuval Mintz pi_info->comp_cb(p_hwfn, pi_info->cookie); 1293fe56b9e6SYuval Mintz } 1294fe56b9e6SYuval Mintz } 1295fe56b9e6SYuval Mintz 1296cc875c2eSYuval Mintz if (sb_attn && (rc & QED_SB_ATT_IDX)) 1297cc875c2eSYuval Mintz /* This should be done before the interrupts are enabled, 1298cc875c2eSYuval Mintz * since otherwise a new attention will be generated. 1299cc875c2eSYuval Mintz */ 1300cc875c2eSYuval Mintz qed_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index); 1301cc875c2eSYuval Mintz 1302fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1303fe56b9e6SYuval Mintz } 1304fe56b9e6SYuval Mintz 1305cc875c2eSYuval Mintz static void qed_int_sb_attn_free(struct qed_hwfn *p_hwfn) 1306cc875c2eSYuval Mintz { 1307cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb = p_hwfn->p_sb_attn; 1308cc875c2eSYuval Mintz 13094ac801b7SYuval Mintz if (!p_sb) 13104ac801b7SYuval Mintz return; 13114ac801b7SYuval Mintz 1312cc875c2eSYuval Mintz if (p_sb->sb_attn) 13134ac801b7SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1314cc875c2eSYuval Mintz SB_ATTN_ALIGNED_SIZE(p_hwfn), 13151a635e48SYuval Mintz p_sb->sb_attn, p_sb->sb_phys); 1316cc875c2eSYuval Mintz kfree(p_sb); 13173587cb87STomer Tayar p_hwfn->p_sb_attn = NULL; 1318cc875c2eSYuval Mintz } 1319cc875c2eSYuval Mintz 1320cc875c2eSYuval Mintz static void qed_int_sb_attn_setup(struct qed_hwfn *p_hwfn, 1321cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1322cc875c2eSYuval Mintz { 1323cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 1324cc875c2eSYuval Mintz 1325cc875c2eSYuval Mintz memset(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn)); 1326cc875c2eSYuval Mintz 1327cc875c2eSYuval Mintz sb_info->index = 0; 1328cc875c2eSYuval Mintz sb_info->known_attn = 0; 1329cc875c2eSYuval Mintz 1330cc875c2eSYuval Mintz /* Configure Attention Status Block in IGU */ 1331cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L, 1332cc875c2eSYuval Mintz lower_32_bits(p_hwfn->p_sb_attn->sb_phys)); 1333cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H, 1334cc875c2eSYuval Mintz upper_32_bits(p_hwfn->p_sb_attn->sb_phys)); 1335cc875c2eSYuval Mintz } 1336cc875c2eSYuval Mintz 1337cc875c2eSYuval Mintz static void qed_int_sb_attn_init(struct qed_hwfn *p_hwfn, 1338cc875c2eSYuval Mintz struct qed_ptt *p_ptt, 13391a635e48SYuval Mintz void *sb_virt_addr, dma_addr_t sb_phy_addr) 1340cc875c2eSYuval Mintz { 1341cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 13420d956e8aSYuval Mintz int i, j, k; 1343cc875c2eSYuval Mintz 1344cc875c2eSYuval Mintz sb_info->sb_attn = sb_virt_addr; 1345cc875c2eSYuval Mintz sb_info->sb_phys = sb_phy_addr; 1346cc875c2eSYuval Mintz 13470d956e8aSYuval Mintz /* Set the pointer to the AEU descriptors */ 13480d956e8aSYuval Mintz sb_info->p_aeu_desc = aeu_descs; 13490d956e8aSYuval Mintz 13500d956e8aSYuval Mintz /* Calculate Parity Masks */ 13510d956e8aSYuval Mintz memset(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS); 13520d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 13530d956e8aSYuval Mintz /* j is array index, k is bit index */ 13540d956e8aSYuval Mintz for (j = 0, k = 0; k < 32; j++) { 1355ba36f718SMintz, Yuval struct aeu_invert_reg_bit *p_aeu; 13560d956e8aSYuval Mintz 1357ba36f718SMintz, Yuval p_aeu = &aeu_descs[i].bits[j]; 1358ba36f718SMintz, Yuval if (qed_int_is_parity_flag(p_hwfn, p_aeu)) 13590d956e8aSYuval Mintz sb_info->parity_mask[i] |= 1 << k; 13600d956e8aSYuval Mintz 1361ba36f718SMintz, Yuval k += ATTENTION_LENGTH(p_aeu->flags); 13620d956e8aSYuval Mintz } 13630d956e8aSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 13640d956e8aSYuval Mintz "Attn Mask [Reg %d]: 0x%08x\n", 13650d956e8aSYuval Mintz i, sb_info->parity_mask[i]); 13660d956e8aSYuval Mintz } 13670d956e8aSYuval Mintz 1368cc875c2eSYuval Mintz /* Set the address of cleanup for the mcp attention */ 1369cc875c2eSYuval Mintz sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) + 1370cc875c2eSYuval Mintz MISC_REG_AEU_GENERAL_ATTN_0; 1371cc875c2eSYuval Mintz 1372cc875c2eSYuval Mintz qed_int_sb_attn_setup(p_hwfn, p_ptt); 1373cc875c2eSYuval Mintz } 1374cc875c2eSYuval Mintz 1375cc875c2eSYuval Mintz static int qed_int_sb_attn_alloc(struct qed_hwfn *p_hwfn, 1376cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1377cc875c2eSYuval Mintz { 1378cc875c2eSYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 1379cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb; 1380cc875c2eSYuval Mintz dma_addr_t p_phys = 0; 13811a635e48SYuval Mintz void *p_virt; 1382cc875c2eSYuval Mintz 1383cc875c2eSYuval Mintz /* SB struct */ 138460fffb3bSYuval Mintz p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 13852591c280SJoe Perches if (!p_sb) 1386cc875c2eSYuval Mintz return -ENOMEM; 1387cc875c2eSYuval Mintz 1388cc875c2eSYuval Mintz /* SB ring */ 1389cc875c2eSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 1390cc875c2eSYuval Mintz SB_ATTN_ALIGNED_SIZE(p_hwfn), 1391cc875c2eSYuval Mintz &p_phys, GFP_KERNEL); 1392cc875c2eSYuval Mintz 1393cc875c2eSYuval Mintz if (!p_virt) { 1394cc875c2eSYuval Mintz kfree(p_sb); 1395cc875c2eSYuval Mintz return -ENOMEM; 1396cc875c2eSYuval Mintz } 1397cc875c2eSYuval Mintz 1398cc875c2eSYuval Mintz /* Attention setup */ 1399cc875c2eSYuval Mintz p_hwfn->p_sb_attn = p_sb; 1400cc875c2eSYuval Mintz qed_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys); 1401cc875c2eSYuval Mintz 1402cc875c2eSYuval Mintz return 0; 1403cc875c2eSYuval Mintz } 1404cc875c2eSYuval Mintz 1405fe56b9e6SYuval Mintz /* coalescing timeout = timeset << (timer_res + 1) */ 1406fe56b9e6SYuval Mintz #define QED_CAU_DEF_RX_USECS 24 1407fe56b9e6SYuval Mintz #define QED_CAU_DEF_TX_USECS 48 1408fe56b9e6SYuval Mintz 1409fe56b9e6SYuval Mintz void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn, 1410fe56b9e6SYuval Mintz struct cau_sb_entry *p_sb_entry, 14111a635e48SYuval Mintz u8 pf_id, u16 vf_number, u8 vf_valid) 1412fe56b9e6SYuval Mintz { 14134ac801b7SYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 1414fe56b9e6SYuval Mintz u32 cau_state; 1415722003acSSudarsana Reddy Kalluru u8 timer_res; 1416fe56b9e6SYuval Mintz 1417fe56b9e6SYuval Mintz memset(p_sb_entry, 0, sizeof(*p_sb_entry)); 1418fe56b9e6SYuval Mintz 1419fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id); 1420fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number); 1421fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid); 1422fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F); 1423fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F); 1424fe56b9e6SYuval Mintz 1425fe56b9e6SYuval Mintz cau_state = CAU_HC_DISABLE_STATE; 1426fe56b9e6SYuval Mintz 14274ac801b7SYuval Mintz if (cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 1428fe56b9e6SYuval Mintz cau_state = CAU_HC_ENABLE_STATE; 14294ac801b7SYuval Mintz if (!cdev->rx_coalesce_usecs) 14304ac801b7SYuval Mintz cdev->rx_coalesce_usecs = QED_CAU_DEF_RX_USECS; 14314ac801b7SYuval Mintz if (!cdev->tx_coalesce_usecs) 14324ac801b7SYuval Mintz cdev->tx_coalesce_usecs = QED_CAU_DEF_TX_USECS; 1433fe56b9e6SYuval Mintz } 1434fe56b9e6SYuval Mintz 1435722003acSSudarsana Reddy Kalluru /* Coalesce = (timeset << timer-res), timeset is 7bit wide */ 1436722003acSSudarsana Reddy Kalluru if (cdev->rx_coalesce_usecs <= 0x7F) 1437722003acSSudarsana Reddy Kalluru timer_res = 0; 1438722003acSSudarsana Reddy Kalluru else if (cdev->rx_coalesce_usecs <= 0xFF) 1439722003acSSudarsana Reddy Kalluru timer_res = 1; 1440722003acSSudarsana Reddy Kalluru else 1441722003acSSudarsana Reddy Kalluru timer_res = 2; 1442722003acSSudarsana Reddy Kalluru SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 1443722003acSSudarsana Reddy Kalluru 1444722003acSSudarsana Reddy Kalluru if (cdev->tx_coalesce_usecs <= 0x7F) 1445722003acSSudarsana Reddy Kalluru timer_res = 0; 1446722003acSSudarsana Reddy Kalluru else if (cdev->tx_coalesce_usecs <= 0xFF) 1447722003acSSudarsana Reddy Kalluru timer_res = 1; 1448722003acSSudarsana Reddy Kalluru else 1449722003acSSudarsana Reddy Kalluru timer_res = 2; 1450722003acSSudarsana Reddy Kalluru SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 1451722003acSSudarsana Reddy Kalluru 1452fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state); 1453fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state); 1454fe56b9e6SYuval Mintz } 1455fe56b9e6SYuval Mintz 14568befd73cSMintz, Yuval static void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn, 14578befd73cSMintz, Yuval struct qed_ptt *p_ptt, 14588befd73cSMintz, Yuval u16 igu_sb_id, 14598befd73cSMintz, Yuval u32 pi_index, 14608befd73cSMintz, Yuval enum qed_coalescing_fsm coalescing_fsm, 14618befd73cSMintz, Yuval u8 timeset) 14628befd73cSMintz, Yuval { 14638befd73cSMintz, Yuval struct cau_pi_entry pi_entry; 14648befd73cSMintz, Yuval u32 sb_offset, pi_offset; 14658befd73cSMintz, Yuval 14668befd73cSMintz, Yuval if (IS_VF(p_hwfn->cdev)) 14678befd73cSMintz, Yuval return; 14688befd73cSMintz, Yuval 146921dd79e8STomer Tayar sb_offset = igu_sb_id * PIS_PER_SB_E4; 14708befd73cSMintz, Yuval memset(&pi_entry, 0, sizeof(struct cau_pi_entry)); 14718befd73cSMintz, Yuval 14728befd73cSMintz, Yuval SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset); 14738befd73cSMintz, Yuval if (coalescing_fsm == QED_COAL_RX_STATE_MACHINE) 14748befd73cSMintz, Yuval SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0); 14758befd73cSMintz, Yuval else 14768befd73cSMintz, Yuval SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1); 14778befd73cSMintz, Yuval 14788befd73cSMintz, Yuval pi_offset = sb_offset + pi_index; 14798befd73cSMintz, Yuval if (p_hwfn->hw_init_done) { 14808befd73cSMintz, Yuval qed_wr(p_hwfn, p_ptt, 14818befd73cSMintz, Yuval CAU_REG_PI_MEMORY + pi_offset * sizeof(u32), 14828befd73cSMintz, Yuval *((u32 *)&(pi_entry))); 14838befd73cSMintz, Yuval } else { 14848befd73cSMintz, Yuval STORE_RT_REG(p_hwfn, 14858befd73cSMintz, Yuval CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset, 14868befd73cSMintz, Yuval *((u32 *)&(pi_entry))); 14878befd73cSMintz, Yuval } 14888befd73cSMintz, Yuval } 14898befd73cSMintz, Yuval 1490fe56b9e6SYuval Mintz void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn, 1491fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1492fe56b9e6SYuval Mintz dma_addr_t sb_phys, 14931a635e48SYuval Mintz u16 igu_sb_id, u16 vf_number, u8 vf_valid) 1494fe56b9e6SYuval Mintz { 1495fe56b9e6SYuval Mintz struct cau_sb_entry sb_entry; 1496fe56b9e6SYuval Mintz 1497fe56b9e6SYuval Mintz qed_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id, 1498fe56b9e6SYuval Mintz vf_number, vf_valid); 1499fe56b9e6SYuval Mintz 1500fe56b9e6SYuval Mintz if (p_hwfn->hw_init_done) { 15010a0c5d3bSYuval Mintz /* Wide-bus, initialize via DMAE */ 15020a0c5d3bSYuval Mintz u64 phys_addr = (u64)sb_phys; 1503fe56b9e6SYuval Mintz 15040a0c5d3bSYuval Mintz qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&phys_addr, 15050a0c5d3bSYuval Mintz CAU_REG_SB_ADDR_MEMORY + 150683bf76e3SMichal Kalderon igu_sb_id * sizeof(u64), 2, NULL); 15070a0c5d3bSYuval Mintz qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&sb_entry, 15080a0c5d3bSYuval Mintz CAU_REG_SB_VAR_MEMORY + 150983bf76e3SMichal Kalderon igu_sb_id * sizeof(u64), 2, NULL); 1510fe56b9e6SYuval Mintz } else { 1511fe56b9e6SYuval Mintz /* Initialize Status Block Address */ 1512fe56b9e6SYuval Mintz STORE_RT_REG_AGG(p_hwfn, 1513fe56b9e6SYuval Mintz CAU_REG_SB_ADDR_MEMORY_RT_OFFSET + 1514fe56b9e6SYuval Mintz igu_sb_id * 2, 1515fe56b9e6SYuval Mintz sb_phys); 1516fe56b9e6SYuval Mintz 1517fe56b9e6SYuval Mintz STORE_RT_REG_AGG(p_hwfn, 1518fe56b9e6SYuval Mintz CAU_REG_SB_VAR_MEMORY_RT_OFFSET + 1519fe56b9e6SYuval Mintz igu_sb_id * 2, 1520fe56b9e6SYuval Mintz sb_entry); 1521fe56b9e6SYuval Mintz } 1522fe56b9e6SYuval Mintz 1523fe56b9e6SYuval Mintz /* Configure pi coalescing if set */ 1524fe56b9e6SYuval Mintz if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 1525b5a9ee7cSAriel Elior u8 num_tc = p_hwfn->hw_info.num_hw_tc; 1526722003acSSudarsana Reddy Kalluru u8 timeset, timer_res; 1527b5a9ee7cSAriel Elior u8 i; 1528fe56b9e6SYuval Mintz 1529722003acSSudarsana Reddy Kalluru /* timeset = (coalesce >> timer-res), timeset is 7bit wide */ 1530722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->rx_coalesce_usecs <= 0x7F) 1531722003acSSudarsana Reddy Kalluru timer_res = 0; 1532722003acSSudarsana Reddy Kalluru else if (p_hwfn->cdev->rx_coalesce_usecs <= 0xFF) 1533722003acSSudarsana Reddy Kalluru timer_res = 1; 1534722003acSSudarsana Reddy Kalluru else 1535722003acSSudarsana Reddy Kalluru timer_res = 2; 1536722003acSSudarsana Reddy Kalluru timeset = (u8)(p_hwfn->cdev->rx_coalesce_usecs >> timer_res); 1537fe56b9e6SYuval Mintz qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI, 15381a635e48SYuval Mintz QED_COAL_RX_STATE_MACHINE, timeset); 1539fe56b9e6SYuval Mintz 1540722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->tx_coalesce_usecs <= 0x7F) 1541722003acSSudarsana Reddy Kalluru timer_res = 0; 1542722003acSSudarsana Reddy Kalluru else if (p_hwfn->cdev->tx_coalesce_usecs <= 0xFF) 1543722003acSSudarsana Reddy Kalluru timer_res = 1; 1544722003acSSudarsana Reddy Kalluru else 1545722003acSSudarsana Reddy Kalluru timer_res = 2; 1546722003acSSudarsana Reddy Kalluru timeset = (u8)(p_hwfn->cdev->tx_coalesce_usecs >> timer_res); 1547fe56b9e6SYuval Mintz for (i = 0; i < num_tc; i++) { 1548fe56b9e6SYuval Mintz qed_int_cau_conf_pi(p_hwfn, p_ptt, 1549fe56b9e6SYuval Mintz igu_sb_id, TX_PI(i), 1550fe56b9e6SYuval Mintz QED_COAL_TX_STATE_MACHINE, 1551fe56b9e6SYuval Mintz timeset); 1552fe56b9e6SYuval Mintz } 1553fe56b9e6SYuval Mintz } 1554fe56b9e6SYuval Mintz } 1555fe56b9e6SYuval Mintz 1556fe56b9e6SYuval Mintz void qed_int_sb_setup(struct qed_hwfn *p_hwfn, 15571a635e48SYuval Mintz struct qed_ptt *p_ptt, struct qed_sb_info *sb_info) 1558fe56b9e6SYuval Mintz { 1559fe56b9e6SYuval Mintz /* zero status block and ack counter */ 1560fe56b9e6SYuval Mintz sb_info->sb_ack = 0; 1561fe56b9e6SYuval Mintz memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 1562fe56b9e6SYuval Mintz 15631408cc1fSYuval Mintz if (IS_PF(p_hwfn->cdev)) 1564fe56b9e6SYuval Mintz qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys, 1565fe56b9e6SYuval Mintz sb_info->igu_sb_id, 0, 0); 1566fe56b9e6SYuval Mintz } 1567fe56b9e6SYuval Mintz 156809b6b147SMintz, Yuval struct qed_igu_block *qed_get_igu_free_sb(struct qed_hwfn *p_hwfn, bool b_is_pf) 156909b6b147SMintz, Yuval { 157009b6b147SMintz, Yuval struct qed_igu_block *p_block; 157109b6b147SMintz, Yuval u16 igu_id; 157209b6b147SMintz, Yuval 157309b6b147SMintz, Yuval for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); 157409b6b147SMintz, Yuval igu_id++) { 157509b6b147SMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id]; 157609b6b147SMintz, Yuval 157709b6b147SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID) || 157809b6b147SMintz, Yuval !(p_block->status & QED_IGU_STATUS_FREE)) 157909b6b147SMintz, Yuval continue; 158009b6b147SMintz, Yuval 158109b6b147SMintz, Yuval if (!!(p_block->status & QED_IGU_STATUS_PF) == b_is_pf) 158209b6b147SMintz, Yuval return p_block; 158309b6b147SMintz, Yuval } 158409b6b147SMintz, Yuval 158509b6b147SMintz, Yuval return NULL; 158609b6b147SMintz, Yuval } 158709b6b147SMintz, Yuval 1588a333f7f3SMintz, Yuval static u16 qed_get_pf_igu_sb_id(struct qed_hwfn *p_hwfn, u16 vector_id) 1589a333f7f3SMintz, Yuval { 1590a333f7f3SMintz, Yuval struct qed_igu_block *p_block; 1591a333f7f3SMintz, Yuval u16 igu_id; 1592a333f7f3SMintz, Yuval 1593a333f7f3SMintz, Yuval for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); 1594a333f7f3SMintz, Yuval igu_id++) { 1595a333f7f3SMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id]; 1596a333f7f3SMintz, Yuval 1597a333f7f3SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID) || 1598a333f7f3SMintz, Yuval !p_block->is_pf || 1599a333f7f3SMintz, Yuval p_block->vector_number != vector_id) 1600a333f7f3SMintz, Yuval continue; 1601a333f7f3SMintz, Yuval 1602a333f7f3SMintz, Yuval return igu_id; 1603a333f7f3SMintz, Yuval } 1604a333f7f3SMintz, Yuval 1605a333f7f3SMintz, Yuval return QED_SB_INVALID_IDX; 1606a333f7f3SMintz, Yuval } 1607a333f7f3SMintz, Yuval 160850a20714SMintz, Yuval u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id) 1609fe56b9e6SYuval Mintz { 1610fe56b9e6SYuval Mintz u16 igu_sb_id; 1611fe56b9e6SYuval Mintz 1612fe56b9e6SYuval Mintz /* Assuming continuous set of IGU SBs dedicated for given PF */ 1613fe56b9e6SYuval Mintz if (sb_id == QED_SP_SB_ID) 1614fe56b9e6SYuval Mintz igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id; 16151408cc1fSYuval Mintz else if (IS_PF(p_hwfn->cdev)) 1616a333f7f3SMintz, Yuval igu_sb_id = qed_get_pf_igu_sb_id(p_hwfn, sb_id + 1); 16171408cc1fSYuval Mintz else 16181408cc1fSYuval Mintz igu_sb_id = qed_vf_get_igu_sb_id(p_hwfn, sb_id); 1619fe56b9e6SYuval Mintz 1620525ef5c0SYuval Mintz if (sb_id == QED_SP_SB_ID) 1621525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1622525ef5c0SYuval Mintz "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id); 1623525ef5c0SYuval Mintz else 1624525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1625525ef5c0SYuval Mintz "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id); 1626fe56b9e6SYuval Mintz 1627fe56b9e6SYuval Mintz return igu_sb_id; 1628fe56b9e6SYuval Mintz } 1629fe56b9e6SYuval Mintz 1630fe56b9e6SYuval Mintz int qed_int_sb_init(struct qed_hwfn *p_hwfn, 1631fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1632fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 16331a635e48SYuval Mintz void *sb_virt_addr, dma_addr_t sb_phy_addr, u16 sb_id) 1634fe56b9e6SYuval Mintz { 1635fe56b9e6SYuval Mintz sb_info->sb_virt = sb_virt_addr; 1636fe56b9e6SYuval Mintz sb_info->sb_phys = sb_phy_addr; 1637fe56b9e6SYuval Mintz 1638fe56b9e6SYuval Mintz sb_info->igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id); 1639fe56b9e6SYuval Mintz 1640fe56b9e6SYuval Mintz if (sb_id != QED_SP_SB_ID) { 164150a20714SMintz, Yuval if (IS_PF(p_hwfn->cdev)) { 164250a20714SMintz, Yuval struct qed_igu_info *p_info; 164350a20714SMintz, Yuval struct qed_igu_block *p_block; 164450a20714SMintz, Yuval 164550a20714SMintz, Yuval p_info = p_hwfn->hw_info.p_igu_info; 164650a20714SMintz, Yuval p_block = &p_info->entry[sb_info->igu_sb_id]; 164750a20714SMintz, Yuval 164850a20714SMintz, Yuval p_block->sb_info = sb_info; 164950a20714SMintz, Yuval p_block->status &= ~QED_IGU_STATUS_FREE; 165050a20714SMintz, Yuval p_info->usage.free_cnt--; 165150a20714SMintz, Yuval } else { 165250a20714SMintz, Yuval qed_vf_set_sb_info(p_hwfn, sb_id, sb_info); 165350a20714SMintz, Yuval } 1654fe56b9e6SYuval Mintz } 1655fe56b9e6SYuval Mintz 1656fe56b9e6SYuval Mintz sb_info->cdev = p_hwfn->cdev; 1657fe56b9e6SYuval Mintz 1658fe56b9e6SYuval Mintz /* The igu address will hold the absolute address that needs to be 1659fe56b9e6SYuval Mintz * written to for a specific status block 1660fe56b9e6SYuval Mintz */ 16611408cc1fSYuval Mintz if (IS_PF(p_hwfn->cdev)) { 1662fe56b9e6SYuval Mintz sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 1663fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 1664fe56b9e6SYuval Mintz (sb_info->igu_sb_id << 3); 16651408cc1fSYuval Mintz } else { 16661408cc1fSYuval Mintz sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 16671408cc1fSYuval Mintz PXP_VF_BAR0_START_IGU + 16681408cc1fSYuval Mintz ((IGU_CMD_INT_ACK_BASE + 16691408cc1fSYuval Mintz sb_info->igu_sb_id) << 3); 16701408cc1fSYuval Mintz } 1671fe56b9e6SYuval Mintz 1672fe56b9e6SYuval Mintz sb_info->flags |= QED_SB_INFO_INIT; 1673fe56b9e6SYuval Mintz 1674fe56b9e6SYuval Mintz qed_int_sb_setup(p_hwfn, p_ptt, sb_info); 1675fe56b9e6SYuval Mintz 1676fe56b9e6SYuval Mintz return 0; 1677fe56b9e6SYuval Mintz } 1678fe56b9e6SYuval Mintz 1679fe56b9e6SYuval Mintz int qed_int_sb_release(struct qed_hwfn *p_hwfn, 16801a635e48SYuval Mintz struct qed_sb_info *sb_info, u16 sb_id) 1681fe56b9e6SYuval Mintz { 168250a20714SMintz, Yuval struct qed_igu_block *p_block; 168350a20714SMintz, Yuval struct qed_igu_info *p_info; 168450a20714SMintz, Yuval 168550a20714SMintz, Yuval if (!sb_info) 168650a20714SMintz, Yuval return 0; 1687fe56b9e6SYuval Mintz 1688fe56b9e6SYuval Mintz /* zero status block and ack counter */ 1689fe56b9e6SYuval Mintz sb_info->sb_ack = 0; 1690fe56b9e6SYuval Mintz memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 1691fe56b9e6SYuval Mintz 169250a20714SMintz, Yuval if (IS_VF(p_hwfn->cdev)) { 169350a20714SMintz, Yuval qed_vf_set_sb_info(p_hwfn, sb_id, NULL); 169450a20714SMintz, Yuval return 0; 16954ac801b7SYuval Mintz } 1696fe56b9e6SYuval Mintz 169750a20714SMintz, Yuval p_info = p_hwfn->hw_info.p_igu_info; 169850a20714SMintz, Yuval p_block = &p_info->entry[sb_info->igu_sb_id]; 169950a20714SMintz, Yuval 170050a20714SMintz, Yuval /* Vector 0 is reserved to Default SB */ 170150a20714SMintz, Yuval if (!p_block->vector_number) { 170250a20714SMintz, Yuval DP_ERR(p_hwfn, "Do Not free sp sb using this function"); 170350a20714SMintz, Yuval return -EINVAL; 170450a20714SMintz, Yuval } 170550a20714SMintz, Yuval 170650a20714SMintz, Yuval /* Lose reference to client's SB info, and fix counters */ 170750a20714SMintz, Yuval p_block->sb_info = NULL; 170850a20714SMintz, Yuval p_block->status |= QED_IGU_STATUS_FREE; 170950a20714SMintz, Yuval p_info->usage.free_cnt++; 171050a20714SMintz, Yuval 1711fe56b9e6SYuval Mintz return 0; 1712fe56b9e6SYuval Mintz } 1713fe56b9e6SYuval Mintz 1714fe56b9e6SYuval Mintz static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn) 1715fe56b9e6SYuval Mintz { 1716fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb; 1717fe56b9e6SYuval Mintz 17184ac801b7SYuval Mintz if (!p_sb) 17194ac801b7SYuval Mintz return; 17204ac801b7SYuval Mintz 1721fe56b9e6SYuval Mintz if (p_sb->sb_info.sb_virt) 1722fe56b9e6SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1723fe56b9e6SYuval Mintz SB_ALIGNED_SIZE(p_hwfn), 1724fe56b9e6SYuval Mintz p_sb->sb_info.sb_virt, 1725fe56b9e6SYuval Mintz p_sb->sb_info.sb_phys); 1726fe56b9e6SYuval Mintz kfree(p_sb); 17273587cb87STomer Tayar p_hwfn->p_sp_sb = NULL; 1728fe56b9e6SYuval Mintz } 1729fe56b9e6SYuval Mintz 17301a635e48SYuval Mintz static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1731fe56b9e6SYuval Mintz { 1732fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sb; 1733fe56b9e6SYuval Mintz dma_addr_t p_phys = 0; 1734fe56b9e6SYuval Mintz void *p_virt; 1735fe56b9e6SYuval Mintz 1736fe56b9e6SYuval Mintz /* SB struct */ 173760fffb3bSYuval Mintz p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 17382591c280SJoe Perches if (!p_sb) 1739fe56b9e6SYuval Mintz return -ENOMEM; 1740fe56b9e6SYuval Mintz 1741fe56b9e6SYuval Mintz /* SB ring */ 1742fe56b9e6SYuval Mintz p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1743fe56b9e6SYuval Mintz SB_ALIGNED_SIZE(p_hwfn), 1744fe56b9e6SYuval Mintz &p_phys, GFP_KERNEL); 1745fe56b9e6SYuval Mintz if (!p_virt) { 1746fe56b9e6SYuval Mintz kfree(p_sb); 1747fe56b9e6SYuval Mintz return -ENOMEM; 1748fe56b9e6SYuval Mintz } 1749fe56b9e6SYuval Mintz 1750fe56b9e6SYuval Mintz /* Status Block setup */ 1751fe56b9e6SYuval Mintz p_hwfn->p_sp_sb = p_sb; 1752fe56b9e6SYuval Mintz qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt, 1753fe56b9e6SYuval Mintz p_phys, QED_SP_SB_ID); 1754fe56b9e6SYuval Mintz 1755fe56b9e6SYuval Mintz memset(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr)); 1756fe56b9e6SYuval Mintz 1757fe56b9e6SYuval Mintz return 0; 1758fe56b9e6SYuval Mintz } 1759fe56b9e6SYuval Mintz 1760fe56b9e6SYuval Mintz int qed_int_register_cb(struct qed_hwfn *p_hwfn, 1761fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb, 17621a635e48SYuval Mintz void *cookie, u8 *sb_idx, __le16 **p_fw_cons) 1763fe56b9e6SYuval Mintz { 1764fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 17654ac801b7SYuval Mintz int rc = -ENOMEM; 1766fe56b9e6SYuval Mintz u8 pi; 1767fe56b9e6SYuval Mintz 1768fe56b9e6SYuval Mintz /* Look for a free index */ 1769fe56b9e6SYuval Mintz for (pi = 0; pi < ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) { 17704ac801b7SYuval Mintz if (p_sp_sb->pi_info_arr[pi].comp_cb) 17714ac801b7SYuval Mintz continue; 17724ac801b7SYuval Mintz 1773fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb; 1774fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].cookie = cookie; 1775fe56b9e6SYuval Mintz *sb_idx = pi; 1776fe56b9e6SYuval Mintz *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi]; 17774ac801b7SYuval Mintz rc = 0; 1778fe56b9e6SYuval Mintz break; 1779fe56b9e6SYuval Mintz } 1780fe56b9e6SYuval Mintz 17814ac801b7SYuval Mintz return rc; 1782fe56b9e6SYuval Mintz } 1783fe56b9e6SYuval Mintz 1784fe56b9e6SYuval Mintz int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi) 1785fe56b9e6SYuval Mintz { 1786fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 1787fe56b9e6SYuval Mintz 17884ac801b7SYuval Mintz if (p_sp_sb->pi_info_arr[pi].comp_cb == NULL) 17894ac801b7SYuval Mintz return -ENOMEM; 17904ac801b7SYuval Mintz 1791fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].comp_cb = NULL; 1792fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].cookie = NULL; 1793fe56b9e6SYuval Mintz 17944ac801b7SYuval Mintz return 0; 1795fe56b9e6SYuval Mintz } 1796fe56b9e6SYuval Mintz 1797fe56b9e6SYuval Mintz u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn) 1798fe56b9e6SYuval Mintz { 1799fe56b9e6SYuval Mintz return p_hwfn->p_sp_sb->sb_info.igu_sb_id; 1800fe56b9e6SYuval Mintz } 1801fe56b9e6SYuval Mintz 1802fe56b9e6SYuval Mintz void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn, 18031a635e48SYuval Mintz struct qed_ptt *p_ptt, enum qed_int_mode int_mode) 1804fe56b9e6SYuval Mintz { 1805cc875c2eSYuval Mintz u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN; 1806fe56b9e6SYuval Mintz 1807fe56b9e6SYuval Mintz p_hwfn->cdev->int_mode = int_mode; 1808fe56b9e6SYuval Mintz switch (p_hwfn->cdev->int_mode) { 1809fe56b9e6SYuval Mintz case QED_INT_MODE_INTA: 1810fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN; 1811fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 1812fe56b9e6SYuval Mintz break; 1813fe56b9e6SYuval Mintz 1814fe56b9e6SYuval Mintz case QED_INT_MODE_MSI: 1815fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 1816fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 1817fe56b9e6SYuval Mintz break; 1818fe56b9e6SYuval Mintz 1819fe56b9e6SYuval Mintz case QED_INT_MODE_MSIX: 1820fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 1821fe56b9e6SYuval Mintz break; 1822fe56b9e6SYuval Mintz case QED_INT_MODE_POLL: 1823fe56b9e6SYuval Mintz break; 1824fe56b9e6SYuval Mintz } 1825fe56b9e6SYuval Mintz 1826fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf); 1827fe56b9e6SYuval Mintz } 1828fe56b9e6SYuval Mintz 1829979cead3SMintz, Yuval static void qed_int_igu_enable_attn(struct qed_hwfn *p_hwfn, 1830979cead3SMintz, Yuval struct qed_ptt *p_ptt) 1831fe56b9e6SYuval Mintz { 1832fe56b9e6SYuval Mintz 18330d956e8aSYuval Mintz /* Configure AEU signal change to produce attentions */ 18340d956e8aSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0); 1835cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff); 1836cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff); 18370d956e8aSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff); 1838cc875c2eSYuval Mintz 1839cc875c2eSYuval Mintz /* Unmask AEU signals toward IGU */ 1840cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff); 1841979cead3SMintz, Yuval } 1842979cead3SMintz, Yuval 1843979cead3SMintz, Yuval int 1844979cead3SMintz, Yuval qed_int_igu_enable(struct qed_hwfn *p_hwfn, 1845979cead3SMintz, Yuval struct qed_ptt *p_ptt, enum qed_int_mode int_mode) 1846979cead3SMintz, Yuval { 1847979cead3SMintz, Yuval int rc = 0; 1848979cead3SMintz, Yuval 1849979cead3SMintz, Yuval qed_int_igu_enable_attn(p_hwfn, p_ptt); 1850979cead3SMintz, Yuval 18518f16bc97SSudarsana Kalluru if ((int_mode != QED_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) { 18528f16bc97SSudarsana Kalluru rc = qed_slowpath_irq_req(p_hwfn); 18531a635e48SYuval Mintz if (rc) { 18548f16bc97SSudarsana Kalluru DP_NOTICE(p_hwfn, "Slowpath IRQ request failed\n"); 18558f16bc97SSudarsana Kalluru return -EINVAL; 18568f16bc97SSudarsana Kalluru } 18578f16bc97SSudarsana Kalluru p_hwfn->b_int_requested = true; 18588f16bc97SSudarsana Kalluru } 18598f16bc97SSudarsana Kalluru /* Enable interrupt Generation */ 18608f16bc97SSudarsana Kalluru qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode); 18618f16bc97SSudarsana Kalluru p_hwfn->b_int_enabled = 1; 18628f16bc97SSudarsana Kalluru 18638f16bc97SSudarsana Kalluru return rc; 1864fe56b9e6SYuval Mintz } 1865fe56b9e6SYuval Mintz 18661a635e48SYuval Mintz void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1867fe56b9e6SYuval Mintz { 1868fe56b9e6SYuval Mintz p_hwfn->b_int_enabled = 0; 1869fe56b9e6SYuval Mintz 18701408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 18711408cc1fSYuval Mintz return; 18721408cc1fSYuval Mintz 1873fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0); 1874fe56b9e6SYuval Mintz } 1875fe56b9e6SYuval Mintz 1876fe56b9e6SYuval Mintz #define IGU_CLEANUP_SLEEP_LENGTH (1000) 1877b2b897ebSYuval Mintz static void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn, 1878fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1879d031548eSMintz, Yuval u16 igu_sb_id, 1880d031548eSMintz, Yuval bool cleanup_set, u16 opaque_fid) 1881fe56b9e6SYuval Mintz { 1882b2b897ebSYuval Mintz u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0; 1883d031548eSMintz, Yuval u32 pxp_addr = IGU_CMD_INT_ACK_BASE + igu_sb_id; 1884fe56b9e6SYuval Mintz u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH; 1885fe56b9e6SYuval Mintz 1886fe56b9e6SYuval Mintz /* Set the data field */ 1887fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0); 1888fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, 0); 1889fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET); 1890fe56b9e6SYuval Mintz 1891fe56b9e6SYuval Mintz /* Set the control register */ 1892fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr); 1893fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid); 1894fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR); 1895fe56b9e6SYuval Mintz 1896fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data); 1897fe56b9e6SYuval Mintz 1898fe56b9e6SYuval Mintz barrier(); 1899fe56b9e6SYuval Mintz 1900fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl); 1901fe56b9e6SYuval Mintz 1902fe56b9e6SYuval Mintz /* calculate where to read the status bit from */ 1903d031548eSMintz, Yuval sb_bit = 1 << (igu_sb_id % 32); 1904d031548eSMintz, Yuval sb_bit_addr = igu_sb_id / 32 * sizeof(u32); 1905fe56b9e6SYuval Mintz 1906fe56b9e6SYuval Mintz sb_bit_addr += IGU_REG_CLEANUP_STATUS_0; 1907fe56b9e6SYuval Mintz 1908fe56b9e6SYuval Mintz /* Now wait for the command to complete */ 1909fe56b9e6SYuval Mintz do { 1910fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, sb_bit_addr); 1911fe56b9e6SYuval Mintz 1912fe56b9e6SYuval Mintz if ((val & sb_bit) == (cleanup_set ? sb_bit : 0)) 1913fe56b9e6SYuval Mintz break; 1914fe56b9e6SYuval Mintz 1915fe56b9e6SYuval Mintz usleep_range(5000, 10000); 1916fe56b9e6SYuval Mintz } while (--sleep_cnt); 1917fe56b9e6SYuval Mintz 1918fe56b9e6SYuval Mintz if (!sleep_cnt) 1919fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 1920fe56b9e6SYuval Mintz "Timeout waiting for clear status 0x%08x [for sb %d]\n", 1921d031548eSMintz, Yuval val, igu_sb_id); 1922fe56b9e6SYuval Mintz } 1923fe56b9e6SYuval Mintz 1924fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn, 1925fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1926d031548eSMintz, Yuval u16 igu_sb_id, u16 opaque, bool b_set) 1927fe56b9e6SYuval Mintz { 19281ac72433SMintz, Yuval struct qed_igu_block *p_block; 1929b2b897ebSYuval Mintz int pi, i; 1930fe56b9e6SYuval Mintz 19311ac72433SMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id]; 19321ac72433SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 19331ac72433SMintz, Yuval "Cleaning SB [%04x]: func_id= %d is_pf = %d vector_num = 0x%0x\n", 19341ac72433SMintz, Yuval igu_sb_id, 19351ac72433SMintz, Yuval p_block->function_id, 19361ac72433SMintz, Yuval p_block->is_pf, p_block->vector_number); 19371ac72433SMintz, Yuval 1938fe56b9e6SYuval Mintz /* Set */ 1939fe56b9e6SYuval Mintz if (b_set) 1940d031548eSMintz, Yuval qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 1, opaque); 1941fe56b9e6SYuval Mintz 1942fe56b9e6SYuval Mintz /* Clear */ 1943d031548eSMintz, Yuval qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 0, opaque); 1944fe56b9e6SYuval Mintz 1945b2b897ebSYuval Mintz /* Wait for the IGU SB to cleanup */ 1946b2b897ebSYuval Mintz for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) { 1947b2b897ebSYuval Mintz u32 val; 1948b2b897ebSYuval Mintz 1949b2b897ebSYuval Mintz val = qed_rd(p_hwfn, p_ptt, 1950d031548eSMintz, Yuval IGU_REG_WRITE_DONE_PENDING + 1951d031548eSMintz, Yuval ((igu_sb_id / 32) * 4)); 1952d031548eSMintz, Yuval if (val & BIT((igu_sb_id % 32))) 1953b2b897ebSYuval Mintz usleep_range(10, 20); 1954b2b897ebSYuval Mintz else 1955b2b897ebSYuval Mintz break; 1956b2b897ebSYuval Mintz } 1957b2b897ebSYuval Mintz if (i == IGU_CLEANUP_SLEEP_LENGTH) 1958b2b897ebSYuval Mintz DP_NOTICE(p_hwfn, 1959b2b897ebSYuval Mintz "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n", 1960d031548eSMintz, Yuval igu_sb_id); 1961b2b897ebSYuval Mintz 1962fe56b9e6SYuval Mintz /* Clear the CAU for the SB */ 1963fe56b9e6SYuval Mintz for (pi = 0; pi < 12; pi++) 1964fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 1965d031548eSMintz, Yuval CAU_REG_PI_MEMORY + (igu_sb_id * 12 + pi) * 4, 0); 1966fe56b9e6SYuval Mintz } 1967fe56b9e6SYuval Mintz 1968fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn, 1969fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1970b2b897ebSYuval Mintz bool b_set, bool b_slowpath) 1971fe56b9e6SYuval Mintz { 19721ac72433SMintz, Yuval struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info; 19731ac72433SMintz, Yuval struct qed_igu_block *p_block; 19741ac72433SMintz, Yuval u16 igu_sb_id = 0; 19751ac72433SMintz, Yuval u32 val = 0; 1976fe56b9e6SYuval Mintz 1977fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION); 1978fe56b9e6SYuval Mintz val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN; 1979fe56b9e6SYuval Mintz val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN; 1980fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val); 1981fe56b9e6SYuval Mintz 19821ac72433SMintz, Yuval for (igu_sb_id = 0; 19831ac72433SMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 19841ac72433SMintz, Yuval p_block = &p_info->entry[igu_sb_id]; 1985fe56b9e6SYuval Mintz 19861ac72433SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID) || 19871ac72433SMintz, Yuval !p_block->is_pf || 19881ac72433SMintz, Yuval (p_block->status & QED_IGU_STATUS_DSB)) 19891ac72433SMintz, Yuval continue; 19901ac72433SMintz, Yuval 1991d031548eSMintz, Yuval qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, igu_sb_id, 1992fe56b9e6SYuval Mintz p_hwfn->hw_info.opaque_fid, 1993fe56b9e6SYuval Mintz b_set); 19941ac72433SMintz, Yuval } 1995fe56b9e6SYuval Mintz 19961ac72433SMintz, Yuval if (b_slowpath) 19971ac72433SMintz, Yuval qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, 19981ac72433SMintz, Yuval p_info->igu_dsb_id, 19991ac72433SMintz, Yuval p_hwfn->hw_info.opaque_fid, 20001ac72433SMintz, Yuval b_set); 2001fe56b9e6SYuval Mintz } 2002fe56b9e6SYuval Mintz 2003ebbdcc66SMintz, Yuval int qed_int_igu_reset_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2004ebbdcc66SMintz, Yuval { 2005ebbdcc66SMintz, Yuval struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info; 2006ebbdcc66SMintz, Yuval struct qed_igu_block *p_block; 2007ebbdcc66SMintz, Yuval int pf_sbs, vf_sbs; 2008ebbdcc66SMintz, Yuval u16 igu_sb_id; 2009ebbdcc66SMintz, Yuval u32 val, rval; 2010ebbdcc66SMintz, Yuval 2011ebbdcc66SMintz, Yuval if (!RESC_NUM(p_hwfn, QED_SB)) { 2012ebbdcc66SMintz, Yuval p_info->b_allow_pf_vf_change = false; 2013ebbdcc66SMintz, Yuval } else { 2014ebbdcc66SMintz, Yuval /* Use the numbers the MFW have provided - 2015ebbdcc66SMintz, Yuval * don't forget MFW accounts for the default SB as well. 2016ebbdcc66SMintz, Yuval */ 2017ebbdcc66SMintz, Yuval p_info->b_allow_pf_vf_change = true; 2018ebbdcc66SMintz, Yuval 2019ebbdcc66SMintz, Yuval if (p_info->usage.cnt != RESC_NUM(p_hwfn, QED_SB) - 1) { 2020ebbdcc66SMintz, Yuval DP_INFO(p_hwfn, 2021ebbdcc66SMintz, Yuval "MFW notifies of 0x%04x PF SBs; IGU indicates of only 0x%04x\n", 2022ebbdcc66SMintz, Yuval RESC_NUM(p_hwfn, QED_SB) - 1, 2023ebbdcc66SMintz, Yuval p_info->usage.cnt); 2024ebbdcc66SMintz, Yuval p_info->usage.cnt = RESC_NUM(p_hwfn, QED_SB) - 1; 2025ebbdcc66SMintz, Yuval } 2026ebbdcc66SMintz, Yuval 2027ebbdcc66SMintz, Yuval if (IS_PF_SRIOV(p_hwfn)) { 2028ebbdcc66SMintz, Yuval u16 vfs = p_hwfn->cdev->p_iov_info->total_vfs; 2029ebbdcc66SMintz, Yuval 2030ebbdcc66SMintz, Yuval if (vfs != p_info->usage.iov_cnt) 2031ebbdcc66SMintz, Yuval DP_VERBOSE(p_hwfn, 2032ebbdcc66SMintz, Yuval NETIF_MSG_INTR, 2033ebbdcc66SMintz, Yuval "0x%04x VF SBs in IGU CAM != PCI configuration 0x%04x\n", 2034ebbdcc66SMintz, Yuval p_info->usage.iov_cnt, vfs); 2035ebbdcc66SMintz, Yuval 2036ebbdcc66SMintz, Yuval /* At this point we know how many SBs we have totally 2037ebbdcc66SMintz, Yuval * in IGU + number of PF SBs. So we can validate that 2038ebbdcc66SMintz, Yuval * we'd have sufficient for VF. 2039ebbdcc66SMintz, Yuval */ 2040ebbdcc66SMintz, Yuval if (vfs > p_info->usage.free_cnt + 2041ebbdcc66SMintz, Yuval p_info->usage.free_cnt_iov - p_info->usage.cnt) { 2042ebbdcc66SMintz, Yuval DP_NOTICE(p_hwfn, 2043ebbdcc66SMintz, Yuval "Not enough SBs for VFs - 0x%04x SBs, from which %04x PFs and %04x are required\n", 2044ebbdcc66SMintz, Yuval p_info->usage.free_cnt + 2045ebbdcc66SMintz, Yuval p_info->usage.free_cnt_iov, 2046ebbdcc66SMintz, Yuval p_info->usage.cnt, vfs); 2047ebbdcc66SMintz, Yuval return -EINVAL; 2048ebbdcc66SMintz, Yuval } 2049ebbdcc66SMintz, Yuval 2050ebbdcc66SMintz, Yuval /* Currently cap the number of VFs SBs by the 2051ebbdcc66SMintz, Yuval * number of VFs. 2052ebbdcc66SMintz, Yuval */ 2053ebbdcc66SMintz, Yuval p_info->usage.iov_cnt = vfs; 2054ebbdcc66SMintz, Yuval } 2055ebbdcc66SMintz, Yuval } 2056ebbdcc66SMintz, Yuval 2057ebbdcc66SMintz, Yuval /* Mark all SBs as free, now in the right PF/VFs division */ 2058ebbdcc66SMintz, Yuval p_info->usage.free_cnt = p_info->usage.cnt; 2059ebbdcc66SMintz, Yuval p_info->usage.free_cnt_iov = p_info->usage.iov_cnt; 2060ebbdcc66SMintz, Yuval p_info->usage.orig = p_info->usage.cnt; 2061ebbdcc66SMintz, Yuval p_info->usage.iov_orig = p_info->usage.iov_cnt; 2062ebbdcc66SMintz, Yuval 2063ebbdcc66SMintz, Yuval /* We now proceed to re-configure the IGU cam to reflect the initial 2064ebbdcc66SMintz, Yuval * configuration. We can start with the Default SB. 2065ebbdcc66SMintz, Yuval */ 2066ebbdcc66SMintz, Yuval pf_sbs = p_info->usage.cnt; 2067ebbdcc66SMintz, Yuval vf_sbs = p_info->usage.iov_cnt; 2068ebbdcc66SMintz, Yuval 2069ebbdcc66SMintz, Yuval for (igu_sb_id = p_info->igu_dsb_id; 2070ebbdcc66SMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 2071ebbdcc66SMintz, Yuval p_block = &p_info->entry[igu_sb_id]; 2072ebbdcc66SMintz, Yuval val = 0; 2073ebbdcc66SMintz, Yuval 2074ebbdcc66SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID)) 2075ebbdcc66SMintz, Yuval continue; 2076ebbdcc66SMintz, Yuval 2077ebbdcc66SMintz, Yuval if (p_block->status & QED_IGU_STATUS_DSB) { 2078ebbdcc66SMintz, Yuval p_block->function_id = p_hwfn->rel_pf_id; 2079ebbdcc66SMintz, Yuval p_block->is_pf = 1; 2080ebbdcc66SMintz, Yuval p_block->vector_number = 0; 2081ebbdcc66SMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2082ebbdcc66SMintz, Yuval QED_IGU_STATUS_PF | 2083ebbdcc66SMintz, Yuval QED_IGU_STATUS_DSB; 2084ebbdcc66SMintz, Yuval } else if (pf_sbs) { 2085ebbdcc66SMintz, Yuval pf_sbs--; 2086ebbdcc66SMintz, Yuval p_block->function_id = p_hwfn->rel_pf_id; 2087ebbdcc66SMintz, Yuval p_block->is_pf = 1; 2088ebbdcc66SMintz, Yuval p_block->vector_number = p_info->usage.cnt - pf_sbs; 2089ebbdcc66SMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2090ebbdcc66SMintz, Yuval QED_IGU_STATUS_PF | 2091ebbdcc66SMintz, Yuval QED_IGU_STATUS_FREE; 2092ebbdcc66SMintz, Yuval } else if (vf_sbs) { 2093ebbdcc66SMintz, Yuval p_block->function_id = 2094ebbdcc66SMintz, Yuval p_hwfn->cdev->p_iov_info->first_vf_in_pf + 2095ebbdcc66SMintz, Yuval p_info->usage.iov_cnt - vf_sbs; 2096ebbdcc66SMintz, Yuval p_block->is_pf = 0; 2097ebbdcc66SMintz, Yuval p_block->vector_number = 0; 2098ebbdcc66SMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2099ebbdcc66SMintz, Yuval QED_IGU_STATUS_FREE; 2100ebbdcc66SMintz, Yuval vf_sbs--; 2101ebbdcc66SMintz, Yuval } else { 2102ebbdcc66SMintz, Yuval p_block->function_id = 0; 2103ebbdcc66SMintz, Yuval p_block->is_pf = 0; 2104ebbdcc66SMintz, Yuval p_block->vector_number = 0; 2105ebbdcc66SMintz, Yuval } 2106ebbdcc66SMintz, Yuval 2107ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER, 2108ebbdcc66SMintz, Yuval p_block->function_id); 2109ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf); 2110ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER, 2111ebbdcc66SMintz, Yuval p_block->vector_number); 2112ebbdcc66SMintz, Yuval 2113ebbdcc66SMintz, Yuval /* VF entries would be enabled when VF is initializaed */ 2114ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf); 2115ebbdcc66SMintz, Yuval 2116ebbdcc66SMintz, Yuval rval = qed_rd(p_hwfn, p_ptt, 2117ebbdcc66SMintz, Yuval IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id); 2118ebbdcc66SMintz, Yuval 2119ebbdcc66SMintz, Yuval if (rval != val) { 2120ebbdcc66SMintz, Yuval qed_wr(p_hwfn, p_ptt, 2121ebbdcc66SMintz, Yuval IGU_REG_MAPPING_MEMORY + 2122ebbdcc66SMintz, Yuval sizeof(u32) * igu_sb_id, val); 2123ebbdcc66SMintz, Yuval 2124ebbdcc66SMintz, Yuval DP_VERBOSE(p_hwfn, 2125ebbdcc66SMintz, Yuval NETIF_MSG_INTR, 2126ebbdcc66SMintz, Yuval "IGU reset: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x [%08x -> %08x]\n", 2127ebbdcc66SMintz, Yuval igu_sb_id, 2128ebbdcc66SMintz, Yuval p_block->function_id, 2129ebbdcc66SMintz, Yuval p_block->is_pf, 2130ebbdcc66SMintz, Yuval p_block->vector_number, rval, val); 2131ebbdcc66SMintz, Yuval } 2132ebbdcc66SMintz, Yuval } 2133ebbdcc66SMintz, Yuval 2134ebbdcc66SMintz, Yuval return 0; 2135ebbdcc66SMintz, Yuval } 2136ebbdcc66SMintz, Yuval 2137d749dd0dSMintz, Yuval static void qed_int_igu_read_cam_block(struct qed_hwfn *p_hwfn, 2138d749dd0dSMintz, Yuval struct qed_ptt *p_ptt, u16 igu_sb_id) 21394ac801b7SYuval Mintz { 21404ac801b7SYuval Mintz u32 val = qed_rd(p_hwfn, p_ptt, 2141d749dd0dSMintz, Yuval IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id); 21424ac801b7SYuval Mintz struct qed_igu_block *p_block; 21434ac801b7SYuval Mintz 2144d749dd0dSMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id]; 21454ac801b7SYuval Mintz 21464ac801b7SYuval Mintz /* Fill the block information */ 2147d749dd0dSMintz, Yuval p_block->function_id = GET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER); 21484ac801b7SYuval Mintz p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID); 2149d749dd0dSMintz, Yuval p_block->vector_number = GET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER); 21501ac72433SMintz, Yuval p_block->igu_sb_id = igu_sb_id; 21514ac801b7SYuval Mintz } 21524ac801b7SYuval Mintz 21531a635e48SYuval Mintz int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2154fe56b9e6SYuval Mintz { 2155fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 2156d749dd0dSMintz, Yuval struct qed_igu_block *p_block; 2157d749dd0dSMintz, Yuval u32 min_vf = 0, max_vf = 0; 2158d749dd0dSMintz, Yuval u16 igu_sb_id; 2159fe56b9e6SYuval Mintz 216060fffb3bSYuval Mintz p_hwfn->hw_info.p_igu_info = kzalloc(sizeof(*p_igu_info), GFP_KERNEL); 2161fe56b9e6SYuval Mintz if (!p_hwfn->hw_info.p_igu_info) 2162fe56b9e6SYuval Mintz return -ENOMEM; 2163fe56b9e6SYuval Mintz 2164fe56b9e6SYuval Mintz p_igu_info = p_hwfn->hw_info.p_igu_info; 2165fe56b9e6SYuval Mintz 2166d749dd0dSMintz, Yuval /* Distinguish between existent and non-existent default SB */ 2167d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id = QED_SB_INVALID_IDX; 2168d749dd0dSMintz, Yuval 2169d749dd0dSMintz, Yuval /* Find the range of VF ids whose SB belong to this PF */ 21701408cc1fSYuval Mintz if (p_hwfn->cdev->p_iov_info) { 21711408cc1fSYuval Mintz struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info; 21721408cc1fSYuval Mintz 21731408cc1fSYuval Mintz min_vf = p_iov->first_vf_in_pf; 21741408cc1fSYuval Mintz max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs; 21751408cc1fSYuval Mintz } 21761408cc1fSYuval Mintz 2177d749dd0dSMintz, Yuval for (igu_sb_id = 0; 2178d749dd0dSMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 2179d749dd0dSMintz, Yuval /* Read current entry; Notice it might not belong to this PF */ 2180d749dd0dSMintz, Yuval qed_int_igu_read_cam_block(p_hwfn, p_ptt, igu_sb_id); 2181d749dd0dSMintz, Yuval p_block = &p_igu_info->entry[igu_sb_id]; 2182fe56b9e6SYuval Mintz 2183d749dd0dSMintz, Yuval if ((p_block->is_pf) && 2184d749dd0dSMintz, Yuval (p_block->function_id == p_hwfn->rel_pf_id)) { 2185d749dd0dSMintz, Yuval p_block->status = QED_IGU_STATUS_PF | 2186d749dd0dSMintz, Yuval QED_IGU_STATUS_VALID | 2187d749dd0dSMintz, Yuval QED_IGU_STATUS_FREE; 2188fe56b9e6SYuval Mintz 21891ac72433SMintz, Yuval if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX) 2190726fdbe9SMintz, Yuval p_igu_info->usage.cnt++; 2191d749dd0dSMintz, Yuval } else if (!(p_block->is_pf) && 2192d749dd0dSMintz, Yuval (p_block->function_id >= min_vf) && 2193d749dd0dSMintz, Yuval (p_block->function_id < max_vf)) { 21941408cc1fSYuval Mintz /* Available for VFs of this PF */ 2195d749dd0dSMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2196d749dd0dSMintz, Yuval QED_IGU_STATUS_FREE; 2197d749dd0dSMintz, Yuval 21981ac72433SMintz, Yuval if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX) 2199726fdbe9SMintz, Yuval p_igu_info->usage.iov_cnt++; 22001408cc1fSYuval Mintz } 22015a1f965aSMintz, Yuval 2202d749dd0dSMintz, Yuval /* Mark the First entry belonging to the PF or its VFs 2203ebbdcc66SMintz, Yuval * as the default SB [we'll reset IGU prior to first usage]. 22045a1f965aSMintz, Yuval */ 2205d749dd0dSMintz, Yuval if ((p_block->status & QED_IGU_STATUS_VALID) && 2206d749dd0dSMintz, Yuval (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX)) { 2207d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id = igu_sb_id; 2208d749dd0dSMintz, Yuval p_block->status |= QED_IGU_STATUS_DSB; 2209d749dd0dSMintz, Yuval } 22105a1f965aSMintz, Yuval 2211d749dd0dSMintz, Yuval /* limit number of prints by having each PF print only its 2212d749dd0dSMintz, Yuval * entries with the exception of PF0 which would print 2213d749dd0dSMintz, Yuval * everything. 2214d749dd0dSMintz, Yuval */ 2215d749dd0dSMintz, Yuval if ((p_block->status & QED_IGU_STATUS_VALID) || 2216d749dd0dSMintz, Yuval (p_hwfn->abs_pf_id == 0)) { 2217d749dd0dSMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2218d749dd0dSMintz, Yuval "IGU_BLOCK: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n", 2219d749dd0dSMintz, Yuval igu_sb_id, p_block->function_id, 2220d749dd0dSMintz, Yuval p_block->is_pf, p_block->vector_number); 2221d749dd0dSMintz, Yuval } 2222d749dd0dSMintz, Yuval } 2223d749dd0dSMintz, Yuval 2224d749dd0dSMintz, Yuval if (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX) { 22255a1f965aSMintz, Yuval DP_NOTICE(p_hwfn, 2226d749dd0dSMintz, Yuval "IGU CAM returned invalid values igu_dsb_id=0x%x\n", 2227d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id); 22285a1f965aSMintz, Yuval return -EINVAL; 22295a1f965aSMintz, Yuval } 2230d749dd0dSMintz, Yuval 2231d749dd0dSMintz, Yuval /* All non default SB are considered free at this point */ 2232726fdbe9SMintz, Yuval p_igu_info->usage.free_cnt = p_igu_info->usage.cnt; 2233726fdbe9SMintz, Yuval p_igu_info->usage.free_cnt_iov = p_igu_info->usage.iov_cnt; 2234fe56b9e6SYuval Mintz 2235d749dd0dSMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2236ebbdcc66SMintz, Yuval "igu_dsb_id=0x%x, num Free SBs - PF: %04x VF: %04x [might change after resource allocation]\n", 2237d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id, 2238726fdbe9SMintz, Yuval p_igu_info->usage.cnt, p_igu_info->usage.iov_cnt); 2239fe56b9e6SYuval Mintz 2240fe56b9e6SYuval Mintz return 0; 2241fe56b9e6SYuval Mintz } 2242fe56b9e6SYuval Mintz 2243fe56b9e6SYuval Mintz /** 2244fe56b9e6SYuval Mintz * @brief Initialize igu runtime registers 2245fe56b9e6SYuval Mintz * 2246fe56b9e6SYuval Mintz * @param p_hwfn 2247fe56b9e6SYuval Mintz */ 2248fe56b9e6SYuval Mintz void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn) 2249fe56b9e6SYuval Mintz { 22501a635e48SYuval Mintz u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN; 2251fe56b9e6SYuval Mintz 2252fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf); 2253fe56b9e6SYuval Mintz } 2254fe56b9e6SYuval Mintz 2255fe56b9e6SYuval Mintz u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn) 2256fe56b9e6SYuval Mintz { 2257fe56b9e6SYuval Mintz u32 lsb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - 2258fe56b9e6SYuval Mintz IGU_CMD_INT_ACK_BASE; 2259fe56b9e6SYuval Mintz u32 msb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - 2260fe56b9e6SYuval Mintz IGU_CMD_INT_ACK_BASE; 22611a635e48SYuval Mintz u32 intr_status_hi = 0, intr_status_lo = 0; 22621a635e48SYuval Mintz u64 intr_status = 0; 2263fe56b9e6SYuval Mintz 2264fe56b9e6SYuval Mintz intr_status_lo = REG_RD(p_hwfn, 2265fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 2266fe56b9e6SYuval Mintz lsb_igu_cmd_addr * 8); 2267fe56b9e6SYuval Mintz intr_status_hi = REG_RD(p_hwfn, 2268fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 2269fe56b9e6SYuval Mintz msb_igu_cmd_addr * 8); 2270fe56b9e6SYuval Mintz intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo; 2271fe56b9e6SYuval Mintz 2272fe56b9e6SYuval Mintz return intr_status; 2273fe56b9e6SYuval Mintz } 2274fe56b9e6SYuval Mintz 2275fe56b9e6SYuval Mintz static void qed_int_sp_dpc_setup(struct qed_hwfn *p_hwfn) 2276fe56b9e6SYuval Mintz { 2277fe56b9e6SYuval Mintz tasklet_init(p_hwfn->sp_dpc, 2278fe56b9e6SYuval Mintz qed_int_sp_dpc, (unsigned long)p_hwfn); 2279fe56b9e6SYuval Mintz p_hwfn->b_sp_dpc_enabled = true; 2280fe56b9e6SYuval Mintz } 2281fe56b9e6SYuval Mintz 2282fe56b9e6SYuval Mintz static int qed_int_sp_dpc_alloc(struct qed_hwfn *p_hwfn) 2283fe56b9e6SYuval Mintz { 228460fffb3bSYuval Mintz p_hwfn->sp_dpc = kmalloc(sizeof(*p_hwfn->sp_dpc), GFP_KERNEL); 2285fe56b9e6SYuval Mintz if (!p_hwfn->sp_dpc) 2286fe56b9e6SYuval Mintz return -ENOMEM; 2287fe56b9e6SYuval Mintz 2288fe56b9e6SYuval Mintz return 0; 2289fe56b9e6SYuval Mintz } 2290fe56b9e6SYuval Mintz 2291fe56b9e6SYuval Mintz static void qed_int_sp_dpc_free(struct qed_hwfn *p_hwfn) 2292fe56b9e6SYuval Mintz { 2293fe56b9e6SYuval Mintz kfree(p_hwfn->sp_dpc); 22943587cb87STomer Tayar p_hwfn->sp_dpc = NULL; 2295fe56b9e6SYuval Mintz } 2296fe56b9e6SYuval Mintz 22971a635e48SYuval Mintz int qed_int_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2298fe56b9e6SYuval Mintz { 2299fe56b9e6SYuval Mintz int rc = 0; 2300fe56b9e6SYuval Mintz 2301fe56b9e6SYuval Mintz rc = qed_int_sp_dpc_alloc(p_hwfn); 230283aeb933SYuval Mintz if (rc) 23032591c280SJoe Perches return rc; 23042591c280SJoe Perches 23052591c280SJoe Perches rc = qed_int_sp_sb_alloc(p_hwfn, p_ptt); 23062591c280SJoe Perches if (rc) 23072591c280SJoe Perches return rc; 23082591c280SJoe Perches 23092591c280SJoe Perches rc = qed_int_sb_attn_alloc(p_hwfn, p_ptt); 231083aeb933SYuval Mintz 2311fe56b9e6SYuval Mintz return rc; 2312fe56b9e6SYuval Mintz } 2313fe56b9e6SYuval Mintz 2314fe56b9e6SYuval Mintz void qed_int_free(struct qed_hwfn *p_hwfn) 2315fe56b9e6SYuval Mintz { 2316fe56b9e6SYuval Mintz qed_int_sp_sb_free(p_hwfn); 2317cc875c2eSYuval Mintz qed_int_sb_attn_free(p_hwfn); 2318fe56b9e6SYuval Mintz qed_int_sp_dpc_free(p_hwfn); 2319fe56b9e6SYuval Mintz } 2320fe56b9e6SYuval Mintz 23211a635e48SYuval Mintz void qed_int_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2322fe56b9e6SYuval Mintz { 23230d956e8aSYuval Mintz qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info); 23240d956e8aSYuval Mintz qed_int_sb_attn_setup(p_hwfn, p_ptt); 2325fe56b9e6SYuval Mintz qed_int_sp_dpc_setup(p_hwfn); 2326fe56b9e6SYuval Mintz } 2327fe56b9e6SYuval Mintz 23284ac801b7SYuval Mintz void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn, 23294ac801b7SYuval Mintz struct qed_sb_cnt_info *p_sb_cnt_info) 2330fe56b9e6SYuval Mintz { 2331fe56b9e6SYuval Mintz struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info; 2332fe56b9e6SYuval Mintz 23334ac801b7SYuval Mintz if (!info || !p_sb_cnt_info) 23344ac801b7SYuval Mintz return; 2335fe56b9e6SYuval Mintz 2336726fdbe9SMintz, Yuval memcpy(p_sb_cnt_info, &info->usage, sizeof(*p_sb_cnt_info)); 2337fe56b9e6SYuval Mintz } 23388f16bc97SSudarsana Kalluru 23398f16bc97SSudarsana Kalluru void qed_int_disable_post_isr_release(struct qed_dev *cdev) 23408f16bc97SSudarsana Kalluru { 23418f16bc97SSudarsana Kalluru int i; 23428f16bc97SSudarsana Kalluru 23438f16bc97SSudarsana Kalluru for_each_hwfn(cdev, i) 23448f16bc97SSudarsana Kalluru cdev->hwfns[i].b_int_requested = false; 23458f16bc97SSudarsana Kalluru } 2346722003acSSudarsana Reddy Kalluru 2347936c7ba4SIgor Russkikh void qed_int_attn_clr_enable(struct qed_dev *cdev, bool clr_enable) 2348936c7ba4SIgor Russkikh { 2349936c7ba4SIgor Russkikh cdev->attn_clr_en = clr_enable; 2350936c7ba4SIgor Russkikh } 2351936c7ba4SIgor Russkikh 2352722003acSSudarsana Reddy Kalluru int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2353722003acSSudarsana Reddy Kalluru u8 timer_res, u16 sb_id, bool tx) 2354722003acSSudarsana Reddy Kalluru { 2355722003acSSudarsana Reddy Kalluru struct cau_sb_entry sb_entry; 2356722003acSSudarsana Reddy Kalluru int rc; 2357722003acSSudarsana Reddy Kalluru 2358722003acSSudarsana Reddy Kalluru if (!p_hwfn->hw_init_done) { 2359722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "hardware not initialized yet\n"); 2360722003acSSudarsana Reddy Kalluru return -EINVAL; 2361722003acSSudarsana Reddy Kalluru } 2362722003acSSudarsana Reddy Kalluru 2363722003acSSudarsana Reddy Kalluru rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY + 2364722003acSSudarsana Reddy Kalluru sb_id * sizeof(u64), 236583bf76e3SMichal Kalderon (u64)(uintptr_t)&sb_entry, 2, NULL); 2366722003acSSudarsana Reddy Kalluru if (rc) { 2367722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc); 2368722003acSSudarsana Reddy Kalluru return rc; 2369722003acSSudarsana Reddy Kalluru } 2370722003acSSudarsana Reddy Kalluru 2371722003acSSudarsana Reddy Kalluru if (tx) 2372722003acSSudarsana Reddy Kalluru SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 2373722003acSSudarsana Reddy Kalluru else 2374722003acSSudarsana Reddy Kalluru SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 2375722003acSSudarsana Reddy Kalluru 2376722003acSSudarsana Reddy Kalluru rc = qed_dmae_host2grc(p_hwfn, p_ptt, 2377722003acSSudarsana Reddy Kalluru (u64)(uintptr_t)&sb_entry, 2378722003acSSudarsana Reddy Kalluru CAU_REG_SB_VAR_MEMORY + 237983bf76e3SMichal Kalderon sb_id * sizeof(u64), 2, NULL); 2380722003acSSudarsana Reddy Kalluru if (rc) { 2381722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc); 2382722003acSSudarsana Reddy Kalluru return rc; 2383722003acSSudarsana Reddy Kalluru } 2384722003acSSudarsana Reddy Kalluru 2385722003acSSudarsana Reddy Kalluru return rc; 2386722003acSSudarsana Reddy Kalluru } 2387