11f4d4ed6SAlexander Lobakin // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 3e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 4fe56b9e6SYuval Mintz */ 5fe56b9e6SYuval Mintz 6fe56b9e6SYuval Mintz #include <linux/types.h> 7fe56b9e6SYuval Mintz #include <asm/byteorder.h> 8fe56b9e6SYuval Mintz #include <linux/io.h> 9fe56b9e6SYuval Mintz #include <linux/bitops.h> 10fe56b9e6SYuval Mintz #include <linux/delay.h> 11fe56b9e6SYuval Mintz #include <linux/dma-mapping.h> 12fe56b9e6SYuval Mintz #include <linux/errno.h> 13fe56b9e6SYuval Mintz #include <linux/interrupt.h> 14fe56b9e6SYuval Mintz #include <linux/kernel.h> 15fe56b9e6SYuval Mintz #include <linux/pci.h> 16fe56b9e6SYuval Mintz #include <linux/slab.h> 17fe56b9e6SYuval Mintz #include <linux/string.h> 18fe56b9e6SYuval Mintz #include "qed.h" 19fe56b9e6SYuval Mintz #include "qed_hsi.h" 20fe56b9e6SYuval Mintz #include "qed_hw.h" 21fe56b9e6SYuval Mintz #include "qed_init_ops.h" 22fe56b9e6SYuval Mintz #include "qed_int.h" 23fe56b9e6SYuval Mintz #include "qed_mcp.h" 24fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 25fe56b9e6SYuval Mintz #include "qed_sp.h" 261408cc1fSYuval Mintz #include "qed_sriov.h" 271408cc1fSYuval Mintz #include "qed_vf.h" 28fe56b9e6SYuval Mintz 29fe56b9e6SYuval Mintz struct qed_pi_info { 30fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb; 31fe56b9e6SYuval Mintz void *cookie; 32fe56b9e6SYuval Mintz }; 33fe56b9e6SYuval Mintz 34fe56b9e6SYuval Mintz struct qed_sb_sp_info { 35fe56b9e6SYuval Mintz struct qed_sb_info sb_info; 36fe56b9e6SYuval Mintz 37fe56b9e6SYuval Mintz /* per protocol index data */ 3821dd79e8STomer Tayar struct qed_pi_info pi_info_arr[PIS_PER_SB_E4]; 39fe56b9e6SYuval Mintz }; 40fe56b9e6SYuval Mintz 41ff38577aSYuval Mintz enum qed_attention_type { 42ff38577aSYuval Mintz QED_ATTN_TYPE_ATTN, 43ff38577aSYuval Mintz QED_ATTN_TYPE_PARITY, 44ff38577aSYuval Mintz }; 45ff38577aSYuval Mintz 46cc875c2eSYuval Mintz #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \ 47cc875c2eSYuval Mintz ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn) 48cc875c2eSYuval Mintz 490d956e8aSYuval Mintz struct aeu_invert_reg_bit { 500d956e8aSYuval Mintz char bit_name[30]; 510d956e8aSYuval Mintz 520d956e8aSYuval Mintz #define ATTENTION_PARITY (1 << 0) 530d956e8aSYuval Mintz 540d956e8aSYuval Mintz #define ATTENTION_LENGTH_MASK (0x00000ff0) 550d956e8aSYuval Mintz #define ATTENTION_LENGTH_SHIFT (4) 560d956e8aSYuval Mintz #define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \ 570d956e8aSYuval Mintz ATTENTION_LENGTH_SHIFT) 58a2e7699eSTomer Tayar #define ATTENTION_SINGLE BIT(ATTENTION_LENGTH_SHIFT) 590d956e8aSYuval Mintz #define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY) 600d956e8aSYuval Mintz #define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \ 610d956e8aSYuval Mintz ATTENTION_PARITY) 620d956e8aSYuval Mintz 630d956e8aSYuval Mintz /* Multiple bits start with this offset */ 640d956e8aSYuval Mintz #define ATTENTION_OFFSET_MASK (0x000ff000) 650d956e8aSYuval Mintz #define ATTENTION_OFFSET_SHIFT (12) 66ba36f718SMintz, Yuval 67ba36f718SMintz, Yuval #define ATTENTION_BB_MASK (0x00700000) 68ba36f718SMintz, Yuval #define ATTENTION_BB_SHIFT (20) 69ba36f718SMintz, Yuval #define ATTENTION_BB(value) (value << ATTENTION_BB_SHIFT) 70ba36f718SMintz, Yuval #define ATTENTION_BB_DIFFERENT BIT(23) 71ba36f718SMintz, Yuval 72936c7ba4SIgor Russkikh #define ATTENTION_CLEAR_ENABLE BIT(28) 730d956e8aSYuval Mintz unsigned int flags; 74ff38577aSYuval Mintz 75b4149dc7SYuval Mintz /* Callback to call if attention will be triggered */ 76b4149dc7SYuval Mintz int (*cb)(struct qed_hwfn *p_hwfn); 77b4149dc7SYuval Mintz 78ff38577aSYuval Mintz enum block_id block_index; 790d956e8aSYuval Mintz }; 800d956e8aSYuval Mintz 810d956e8aSYuval Mintz struct aeu_invert_reg { 820d956e8aSYuval Mintz struct aeu_invert_reg_bit bits[32]; 830d956e8aSYuval Mintz }; 840d956e8aSYuval Mintz 850d956e8aSYuval Mintz #define MAX_ATTN_GRPS (8) 860d956e8aSYuval Mintz #define NUM_ATTN_REGS (9) 870d956e8aSYuval Mintz 88b4149dc7SYuval Mintz /* Specific HW attention callbacks */ 89b4149dc7SYuval Mintz static int qed_mcp_attn_cb(struct qed_hwfn *p_hwfn) 90b4149dc7SYuval Mintz { 91b4149dc7SYuval Mintz u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE); 92b4149dc7SYuval Mintz 93b4149dc7SYuval Mintz /* This might occur on certain instances; Log it once then mask it */ 94b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, "MCP_REG_CPU_STATE: %08x - Masking...\n", 95b4149dc7SYuval Mintz tmp); 96b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, 97b4149dc7SYuval Mintz 0xffffffff); 98b4149dc7SYuval Mintz 99b4149dc7SYuval Mintz return 0; 100b4149dc7SYuval Mintz } 101b4149dc7SYuval Mintz 102b4149dc7SYuval Mintz #define QED_PSWHST_ATTENTION_INCORRECT_ACCESS (0x1) 103b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_WR_MASK (0x1) 104b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_WR_SHIFT (0) 105b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_CLIENT_MASK (0xf) 106b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT (1) 107b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK (0x1) 108b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT (5) 109b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_ID_MASK (0xff) 110b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT (6) 111b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_PF_ID_MASK (0xf) 112b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT (14) 113b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK (0xff) 114b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT (18) 115b4149dc7SYuval Mintz static int qed_pswhst_attn_cb(struct qed_hwfn *p_hwfn) 116b4149dc7SYuval Mintz { 117b4149dc7SYuval Mintz u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 118b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_VALID); 119b4149dc7SYuval Mintz 120b4149dc7SYuval Mintz if (tmp & QED_PSWHST_ATTENTION_INCORRECT_ACCESS) { 121b4149dc7SYuval Mintz u32 addr, data, length; 122b4149dc7SYuval Mintz 123b4149dc7SYuval Mintz addr = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 124b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_ADDRESS); 125b4149dc7SYuval Mintz data = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 126b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_DATA); 127b4149dc7SYuval Mintz length = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 128b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_LENGTH); 129b4149dc7SYuval Mintz 130b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, 131b4149dc7SYuval Mintz "Incorrect access to %08x of length %08x - PF [%02x] VF [%04x] [valid %02x] client [%02x] write [%02x] Byte-Enable [%04x] [%08x]\n", 132b4149dc7SYuval Mintz addr, length, 133b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_PF_ID), 134b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_VF_ID), 135b4149dc7SYuval Mintz (u8) GET_FIELD(data, 136b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_VF_VALID), 137b4149dc7SYuval Mintz (u8) GET_FIELD(data, 138b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_CLIENT), 139b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_WR), 140b4149dc7SYuval Mintz (u8) GET_FIELD(data, 141b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_BYTE_EN), 142b4149dc7SYuval Mintz data); 143b4149dc7SYuval Mintz } 144b4149dc7SYuval Mintz 145b4149dc7SYuval Mintz return 0; 146b4149dc7SYuval Mintz } 147b4149dc7SYuval Mintz 148b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VALID_BIT (1 << 0) 149b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_ADDRESS_MASK (0x7fffff) 150b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_ADDRESS_SHIFT (0) 151b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_RDWR_BIT (1 << 23) 152b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_MASTER_MASK (0xf) 153b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_MASTER_SHIFT (24) 154b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PF_MASK (0xf) 155b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PF_SHIFT (0) 156b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VF_MASK (0xff) 157b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VF_SHIFT (4) 158b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_MASK (0x3) 159b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_SHIFT (14) 160b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_VF (0) 161b4149dc7SYuval Mintz static const char *attn_master_to_str(u8 master) 162b4149dc7SYuval Mintz { 163b4149dc7SYuval Mintz switch (master) { 164b4149dc7SYuval Mintz case 1: return "PXP"; 165b4149dc7SYuval Mintz case 2: return "MCP"; 166b4149dc7SYuval Mintz case 3: return "MSDM"; 167b4149dc7SYuval Mintz case 4: return "PSDM"; 168b4149dc7SYuval Mintz case 5: return "YSDM"; 169b4149dc7SYuval Mintz case 6: return "USDM"; 170b4149dc7SYuval Mintz case 7: return "TSDM"; 171b4149dc7SYuval Mintz case 8: return "XSDM"; 172b4149dc7SYuval Mintz case 9: return "DBU"; 173b4149dc7SYuval Mintz case 10: return "DMAE"; 174b4149dc7SYuval Mintz default: 1759165dabbSMasanari Iida return "Unknown"; 176b4149dc7SYuval Mintz } 177b4149dc7SYuval Mintz } 178b4149dc7SYuval Mintz 179b4149dc7SYuval Mintz static int qed_grc_attn_cb(struct qed_hwfn *p_hwfn) 180b4149dc7SYuval Mintz { 181b4149dc7SYuval Mintz u32 tmp, tmp2; 182b4149dc7SYuval Mintz 183b4149dc7SYuval Mintz /* We've already cleared the timeout interrupt register, so we learn 184b4149dc7SYuval Mintz * of interrupts via the validity register 185b4149dc7SYuval Mintz */ 186b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 187b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_VALID); 188b4149dc7SYuval Mintz if (!(tmp & QED_GRC_ATTENTION_VALID_BIT)) 189b4149dc7SYuval Mintz goto out; 190b4149dc7SYuval Mintz 191b4149dc7SYuval Mintz /* Read the GRC timeout information */ 192b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 193b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0); 194b4149dc7SYuval Mintz tmp2 = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 195b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1); 196b4149dc7SYuval Mintz 197b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, 198b4149dc7SYuval Mintz "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n", 199b4149dc7SYuval Mintz tmp2, tmp, 200b4149dc7SYuval Mintz (tmp & QED_GRC_ATTENTION_RDWR_BIT) ? "Write to" : "Read from", 201b4149dc7SYuval Mintz GET_FIELD(tmp, QED_GRC_ATTENTION_ADDRESS) << 2, 202b4149dc7SYuval Mintz attn_master_to_str(GET_FIELD(tmp, QED_GRC_ATTENTION_MASTER)), 203b4149dc7SYuval Mintz GET_FIELD(tmp2, QED_GRC_ATTENTION_PF), 204b4149dc7SYuval Mintz (GET_FIELD(tmp2, QED_GRC_ATTENTION_PRIV) == 205fbe1222cSColin Ian King QED_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Irrelevant)", 206b4149dc7SYuval Mintz GET_FIELD(tmp2, QED_GRC_ATTENTION_VF)); 207b4149dc7SYuval Mintz 208b4149dc7SYuval Mintz out: 209b4149dc7SYuval Mintz /* Regardles of anything else, clean the validity bit */ 210b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 211b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0); 212b4149dc7SYuval Mintz return 0; 213b4149dc7SYuval Mintz } 214b4149dc7SYuval Mintz 215b4149dc7SYuval Mintz #define PGLUE_ATTENTION_VALID (1 << 29) 216b4149dc7SYuval Mintz #define PGLUE_ATTENTION_RD_VALID (1 << 26) 217b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf) 218b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20) 219b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VF_VALID_MASK (0x1) 220b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VF_VALID_SHIFT (19) 221b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff) 222b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24) 223b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_MASK (0x1) 224b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_SHIFT (21) 225b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_BME_MASK (0x1) 226b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_BME_SHIFT (22) 227b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_FID_EN_MASK (0x1) 228b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_FID_EN_SHIFT (23) 229b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ICPL_VALID (1 << 23) 230b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ZLR_VALID (1 << 25) 231b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ILT_VALID (1 << 23) 232666db486STomer Tayar 233666db486STomer Tayar int qed_pglueb_rbc_attn_handler(struct qed_hwfn *p_hwfn, 234666db486STomer Tayar struct qed_ptt *p_ptt) 235b4149dc7SYuval Mintz { 236b4149dc7SYuval Mintz u32 tmp; 237b4149dc7SYuval Mintz 238666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS2); 239b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_VALID) { 240b4149dc7SYuval Mintz u32 addr_lo, addr_hi, details; 241b4149dc7SYuval Mintz 242666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 243b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_ADD_31_0); 244666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 245b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_ADD_63_32); 246666db486STomer Tayar details = qed_rd(p_hwfn, p_ptt, 247b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_DETAILS); 248b4149dc7SYuval Mintz 249666db486STomer Tayar DP_NOTICE(p_hwfn, 250b4149dc7SYuval Mintz "Illegal write by chip to [%08x:%08x] blocked.\n" 251b4149dc7SYuval Mintz "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 252b4149dc7SYuval Mintz "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 253b4149dc7SYuval Mintz addr_hi, addr_lo, details, 254b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 255b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 256b4149dc7SYuval Mintz GET_FIELD(details, 257b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0, 258b4149dc7SYuval Mintz tmp, 259b4149dc7SYuval Mintz GET_FIELD(tmp, 260b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0, 261b4149dc7SYuval Mintz GET_FIELD(tmp, 262b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0, 263b4149dc7SYuval Mintz GET_FIELD(tmp, 264b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0); 265b4149dc7SYuval Mintz } 266b4149dc7SYuval Mintz 267666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_RD_DETAILS2); 268b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_RD_VALID) { 269b4149dc7SYuval Mintz u32 addr_lo, addr_hi, details; 270b4149dc7SYuval Mintz 271666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 272b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_ADD_31_0); 273666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 274b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_ADD_63_32); 275666db486STomer Tayar details = qed_rd(p_hwfn, p_ptt, 276b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_DETAILS); 277b4149dc7SYuval Mintz 278666db486STomer Tayar DP_NOTICE(p_hwfn, 279b4149dc7SYuval Mintz "Illegal read by chip from [%08x:%08x] blocked.\n" 280b4149dc7SYuval Mintz "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 281b4149dc7SYuval Mintz "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 282b4149dc7SYuval Mintz addr_hi, addr_lo, details, 283b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 284b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 285b4149dc7SYuval Mintz GET_FIELD(details, 286b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0, 287b4149dc7SYuval Mintz tmp, 288666db486STomer Tayar GET_FIELD(tmp, 289666db486STomer Tayar PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0, 290666db486STomer Tayar GET_FIELD(tmp, 291666db486STomer Tayar PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0, 292666db486STomer Tayar GET_FIELD(tmp, 293666db486STomer Tayar PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0); 294b4149dc7SYuval Mintz } 295b4149dc7SYuval Mintz 296666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL); 297b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ICPL_VALID) 298666db486STomer Tayar DP_NOTICE(p_hwfn, "ICPL error - %08x\n", tmp); 299b4149dc7SYuval Mintz 300666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS); 301b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ZLR_VALID) { 302b4149dc7SYuval Mintz u32 addr_hi, addr_lo; 303b4149dc7SYuval Mintz 304666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 305b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0); 306666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 307b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32); 308b4149dc7SYuval Mintz 309666db486STomer Tayar DP_NOTICE(p_hwfn, "ZLR error - %08x [Address %08x:%08x]\n", 310b4149dc7SYuval Mintz tmp, addr_hi, addr_lo); 311b4149dc7SYuval Mintz } 312b4149dc7SYuval Mintz 313666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_VF_ILT_ERR_DETAILS2); 314b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ILT_VALID) { 315b4149dc7SYuval Mintz u32 addr_hi, addr_lo, details; 316b4149dc7SYuval Mintz 317666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 318b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_ADD_31_0); 319666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 320b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_ADD_63_32); 321666db486STomer Tayar details = qed_rd(p_hwfn, p_ptt, 322b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_DETAILS); 323b4149dc7SYuval Mintz 324666db486STomer Tayar DP_NOTICE(p_hwfn, 325b4149dc7SYuval Mintz "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n", 326b4149dc7SYuval Mintz details, tmp, addr_hi, addr_lo); 327b4149dc7SYuval Mintz } 328b4149dc7SYuval Mintz 329b4149dc7SYuval Mintz /* Clear the indications */ 330666db486STomer Tayar qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_LATCHED_ERRORS_CLR, BIT(2)); 331b4149dc7SYuval Mintz 332b4149dc7SYuval Mintz return 0; 333b4149dc7SYuval Mintz } 334b4149dc7SYuval Mintz 335666db486STomer Tayar static int qed_pglueb_rbc_attn_cb(struct qed_hwfn *p_hwfn) 336666db486STomer Tayar { 337666db486STomer Tayar return qed_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_dpc_ptt); 338666db486STomer Tayar } 339666db486STomer Tayar 3402ec276d5SIgor Russkikh static int qed_fw_assertion(struct qed_hwfn *p_hwfn) 3412ec276d5SIgor Russkikh { 3422ec276d5SIgor Russkikh qed_hw_err_notify(p_hwfn, p_hwfn->p_dpc_ptt, QED_HW_ERR_FW_ASSERT, 3432ec276d5SIgor Russkikh "FW assertion!\n"); 3442ec276d5SIgor Russkikh 3452ec276d5SIgor Russkikh return -EINVAL; 3462ec276d5SIgor Russkikh } 3472ec276d5SIgor Russkikh 348936c7ba4SIgor Russkikh static int qed_general_attention_35(struct qed_hwfn *p_hwfn) 349936c7ba4SIgor Russkikh { 350936c7ba4SIgor Russkikh DP_INFO(p_hwfn, "General attention 35!\n"); 351936c7ba4SIgor Russkikh 352936c7ba4SIgor Russkikh return 0; 353936c7ba4SIgor Russkikh } 354936c7ba4SIgor Russkikh 355b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_REASON_MASK (0xfffff) 356b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_OPAQUE_MASK (0xffff) 357a1b469b8SAriel Elior #define QED_DORQ_ATTENTION_OPAQUE_SHIFT (0x0) 358b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_SIZE_MASK (0x7f) 359b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_SIZE_SHIFT (16) 360a1b469b8SAriel Elior 361a1b469b8SAriel Elior #define QED_DB_REC_COUNT 1000 362a1b469b8SAriel Elior #define QED_DB_REC_INTERVAL 100 363a1b469b8SAriel Elior 364a1b469b8SAriel Elior static int qed_db_rec_flush_queue(struct qed_hwfn *p_hwfn, 365a1b469b8SAriel Elior struct qed_ptt *p_ptt) 366a1b469b8SAriel Elior { 367a1b469b8SAriel Elior u32 count = QED_DB_REC_COUNT; 368a1b469b8SAriel Elior u32 usage = 1; 369a1b469b8SAriel Elior 3700d72c2acSDenis Bolotin /* Flush any pending (e)dpms as they may never arrive */ 3710d72c2acSDenis Bolotin qed_wr(p_hwfn, p_ptt, DORQ_REG_DPM_FORCE_ABORT, 0x1); 3720d72c2acSDenis Bolotin 373a1b469b8SAriel Elior /* wait for usage to zero or count to run out. This is necessary since 374a1b469b8SAriel Elior * EDPM doorbell transactions can take multiple 64b cycles, and as such 375a1b469b8SAriel Elior * can "split" over the pci. Possibly, the doorbell drop can happen with 376a1b469b8SAriel Elior * half an EDPM in the queue and other half dropped. Another EDPM 377a1b469b8SAriel Elior * doorbell to the same address (from doorbell recovery mechanism or 378a1b469b8SAriel Elior * from the doorbelling entity) could have first half dropped and second 379a1b469b8SAriel Elior * half interpreted as continuation of the first. To prevent such 380a1b469b8SAriel Elior * malformed doorbells from reaching the device, flush the queue before 381a1b469b8SAriel Elior * releasing the overflow sticky indication. 382a1b469b8SAriel Elior */ 383a1b469b8SAriel Elior while (count-- && usage) { 384a1b469b8SAriel Elior usage = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_USAGE_CNT); 385a1b469b8SAriel Elior udelay(QED_DB_REC_INTERVAL); 386a1b469b8SAriel Elior } 387a1b469b8SAriel Elior 388a1b469b8SAriel Elior /* should have been depleted by now */ 389a1b469b8SAriel Elior if (usage) { 390a1b469b8SAriel Elior DP_NOTICE(p_hwfn->cdev, 391a1b469b8SAriel Elior "DB recovery: doorbell usage failed to zero after %d usec. usage was %x\n", 392a1b469b8SAriel Elior QED_DB_REC_INTERVAL * QED_DB_REC_COUNT, usage); 393a1b469b8SAriel Elior return -EBUSY; 394a1b469b8SAriel Elior } 395a1b469b8SAriel Elior 396a1b469b8SAriel Elior return 0; 397a1b469b8SAriel Elior } 398a1b469b8SAriel Elior 399a1b469b8SAriel Elior int qed_db_rec_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 400a1b469b8SAriel Elior { 4010d72c2acSDenis Bolotin u32 attn_ovfl, cur_ovfl; 402a1b469b8SAriel Elior int rc; 403a1b469b8SAriel Elior 4040d72c2acSDenis Bolotin attn_ovfl = test_and_clear_bit(QED_OVERFLOW_BIT, 4050d72c2acSDenis Bolotin &p_hwfn->db_recovery_info.overflow); 4060d72c2acSDenis Bolotin cur_ovfl = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY); 4070d72c2acSDenis Bolotin if (!cur_ovfl && !attn_ovfl) 408a1b469b8SAriel Elior return 0; 409a1b469b8SAriel Elior 4100d72c2acSDenis Bolotin DP_NOTICE(p_hwfn, "PF Overflow sticky: attn %u current %u\n", 4110d72c2acSDenis Bolotin attn_ovfl, cur_ovfl); 4120d72c2acSDenis Bolotin 4130d72c2acSDenis Bolotin if (cur_ovfl && !p_hwfn->db_bar_no_edpm) { 414a1b469b8SAriel Elior rc = qed_db_rec_flush_queue(p_hwfn, p_ptt); 415a1b469b8SAriel Elior if (rc) 416a1b469b8SAriel Elior return rc; 417a1b469b8SAriel Elior } 418a1b469b8SAriel Elior 419a1b469b8SAriel Elior /* Release overflow sticky indication (stop silently dropping everything) */ 420a1b469b8SAriel Elior qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0); 421a1b469b8SAriel Elior 422a1b469b8SAriel Elior /* Repeat all last doorbells (doorbell drop recovery) */ 4239ac6bb14SDenis Bolotin qed_db_recovery_execute(p_hwfn); 424a1b469b8SAriel Elior 425a1b469b8SAriel Elior return 0; 426a1b469b8SAriel Elior } 427a1b469b8SAriel Elior 4280d72c2acSDenis Bolotin static void qed_dorq_attn_overflow(struct qed_hwfn *p_hwfn) 4290d72c2acSDenis Bolotin { 4300d72c2acSDenis Bolotin struct qed_ptt *p_ptt = p_hwfn->p_dpc_ptt; 4310d72c2acSDenis Bolotin u32 overflow; 4320d72c2acSDenis Bolotin int rc; 4330d72c2acSDenis Bolotin 4340d72c2acSDenis Bolotin overflow = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY); 4350d72c2acSDenis Bolotin if (!overflow) 4360d72c2acSDenis Bolotin goto out; 4370d72c2acSDenis Bolotin 4380d72c2acSDenis Bolotin /* Run PF doorbell recovery in next periodic handler */ 4390d72c2acSDenis Bolotin set_bit(QED_OVERFLOW_BIT, &p_hwfn->db_recovery_info.overflow); 4400d72c2acSDenis Bolotin 4410d72c2acSDenis Bolotin if (!p_hwfn->db_bar_no_edpm) { 4420d72c2acSDenis Bolotin rc = qed_db_rec_flush_queue(p_hwfn, p_ptt); 4430d72c2acSDenis Bolotin if (rc) 4440d72c2acSDenis Bolotin goto out; 4450d72c2acSDenis Bolotin } 4460d72c2acSDenis Bolotin 4470d72c2acSDenis Bolotin qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0); 4480d72c2acSDenis Bolotin out: 4490d72c2acSDenis Bolotin /* Schedule the handler even if overflow was not detected */ 4500d72c2acSDenis Bolotin qed_periodic_db_rec_start(p_hwfn); 4510d72c2acSDenis Bolotin } 4520d72c2acSDenis Bolotin 4530d72c2acSDenis Bolotin static int qed_dorq_attn_int_sts(struct qed_hwfn *p_hwfn) 454b4149dc7SYuval Mintz { 455a1b469b8SAriel Elior u32 int_sts, first_drop_reason, details, address, all_drops_reason; 456a1b469b8SAriel Elior struct qed_ptt *p_ptt = p_hwfn->p_dpc_ptt; 457a1b469b8SAriel Elior 458a1b469b8SAriel Elior /* int_sts may be zero since all PFs were interrupted for doorbell 459a1b469b8SAriel Elior * overflow but another one already handled it. Can abort here. If 460a1b469b8SAriel Elior * This PF also requires overflow recovery we will be interrupted again. 461a1b469b8SAriel Elior * The masked almost full indication may also be set. Ignoring. 462a1b469b8SAriel Elior */ 463d4476b8aSDenis Bolotin int_sts = qed_rd(p_hwfn, p_ptt, DORQ_REG_INT_STS); 464a1b469b8SAriel Elior if (!(int_sts & ~DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) 465a1b469b8SAriel Elior return 0; 466a1b469b8SAriel Elior 467d4476b8aSDenis Bolotin DP_NOTICE(p_hwfn->cdev, "DORQ attention. int_sts was %x\n", int_sts); 468d4476b8aSDenis Bolotin 469a1b469b8SAriel Elior /* check if db_drop or overflow happened */ 470a1b469b8SAriel Elior if (int_sts & (DORQ_REG_INT_STS_DB_DROP | 471a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR)) { 472a1b469b8SAriel Elior /* Obtain data about db drop/overflow */ 473a1b469b8SAriel Elior first_drop_reason = qed_rd(p_hwfn, p_ptt, 474a1b469b8SAriel Elior DORQ_REG_DB_DROP_REASON) & 475b4149dc7SYuval Mintz QED_DORQ_ATTENTION_REASON_MASK; 476a1b469b8SAriel Elior details = qed_rd(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS); 477a1b469b8SAriel Elior address = qed_rd(p_hwfn, p_ptt, 478a1b469b8SAriel Elior DORQ_REG_DB_DROP_DETAILS_ADDRESS); 479a1b469b8SAriel Elior all_drops_reason = qed_rd(p_hwfn, p_ptt, 480a1b469b8SAriel Elior DORQ_REG_DB_DROP_DETAILS_REASON); 481b4149dc7SYuval Mintz 482a1b469b8SAriel Elior /* Log info */ 483a1b469b8SAriel Elior DP_NOTICE(p_hwfn->cdev, 484a1b469b8SAriel Elior "Doorbell drop occurred\n" 485a1b469b8SAriel Elior "Address\t\t0x%08x\t(second BAR address)\n" 486a1b469b8SAriel Elior "FID\t\t0x%04x\t\t(Opaque FID)\n" 487a1b469b8SAriel Elior "Size\t\t0x%04x\t\t(in bytes)\n" 488a1b469b8SAriel Elior "1st drop reason\t0x%08x\t(details on first drop since last handling)\n" 489a1b469b8SAriel Elior "Sticky reasons\t0x%08x\t(all drop reasons since last handling)\n", 490a1b469b8SAriel Elior address, 491a1b469b8SAriel Elior GET_FIELD(details, QED_DORQ_ATTENTION_OPAQUE), 492b4149dc7SYuval Mintz GET_FIELD(details, QED_DORQ_ATTENTION_SIZE) * 4, 493a1b469b8SAriel Elior first_drop_reason, all_drops_reason); 494a1b469b8SAriel Elior 495a1b469b8SAriel Elior /* Clear the doorbell drop details and prepare for next drop */ 496a1b469b8SAriel Elior qed_wr(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS_REL, 0); 497a1b469b8SAriel Elior 498a1b469b8SAriel Elior /* Mark interrupt as handled (note: even if drop was due to a different 499a1b469b8SAriel Elior * reason than overflow we mark as handled) 500a1b469b8SAriel Elior */ 501a1b469b8SAriel Elior qed_wr(p_hwfn, 502a1b469b8SAriel Elior p_ptt, 503a1b469b8SAriel Elior DORQ_REG_INT_STS_WR, 504a1b469b8SAriel Elior DORQ_REG_INT_STS_DB_DROP | 505a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR); 506a1b469b8SAriel Elior 507a1b469b8SAriel Elior /* If there are no indications other than drop indications, success */ 508a1b469b8SAriel Elior if ((int_sts & ~(DORQ_REG_INT_STS_DB_DROP | 509a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR | 510a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) == 0) 511a1b469b8SAriel Elior return 0; 512b4149dc7SYuval Mintz } 513b4149dc7SYuval Mintz 514a1b469b8SAriel Elior /* Some other indication was present - non recoverable */ 515a1b469b8SAriel Elior DP_INFO(p_hwfn, "DORQ fatal attention\n"); 516a1b469b8SAriel Elior 517b4149dc7SYuval Mintz return -EINVAL; 518b4149dc7SYuval Mintz } 519b4149dc7SYuval Mintz 5200d72c2acSDenis Bolotin static int qed_dorq_attn_cb(struct qed_hwfn *p_hwfn) 5210d72c2acSDenis Bolotin { 5220d72c2acSDenis Bolotin p_hwfn->db_recovery_info.dorq_attn = true; 5230d72c2acSDenis Bolotin qed_dorq_attn_overflow(p_hwfn); 5240d72c2acSDenis Bolotin 5250d72c2acSDenis Bolotin return qed_dorq_attn_int_sts(p_hwfn); 5260d72c2acSDenis Bolotin } 5270d72c2acSDenis Bolotin 528d4476b8aSDenis Bolotin static void qed_dorq_attn_handler(struct qed_hwfn *p_hwfn) 529d4476b8aSDenis Bolotin { 530d4476b8aSDenis Bolotin if (p_hwfn->db_recovery_info.dorq_attn) 531d4476b8aSDenis Bolotin goto out; 532d4476b8aSDenis Bolotin 533d4476b8aSDenis Bolotin /* Call DORQ callback if the attention was missed */ 534d4476b8aSDenis Bolotin qed_dorq_attn_cb(p_hwfn); 535d4476b8aSDenis Bolotin out: 536d4476b8aSDenis Bolotin p_hwfn->db_recovery_info.dorq_attn = false; 537d4476b8aSDenis Bolotin } 538d4476b8aSDenis Bolotin 539ba36f718SMintz, Yuval /* Instead of major changes to the data-structure, we have a some 'special' 540ba36f718SMintz, Yuval * identifiers for sources that changed meaning between adapters. 541ba36f718SMintz, Yuval */ 542ba36f718SMintz, Yuval enum aeu_invert_reg_special_type { 543ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_0, 544ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_1, 545ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_2, 546ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_3, 547ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_MAX, 548ba36f718SMintz, Yuval }; 549ba36f718SMintz, Yuval 550ba36f718SMintz, Yuval static struct aeu_invert_reg_bit 551ba36f718SMintz, Yuval aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = { 552ba36f718SMintz, Yuval {"CNIG port 0", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 553ba36f718SMintz, Yuval {"CNIG port 1", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 554ba36f718SMintz, Yuval {"CNIG port 2", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 555ba36f718SMintz, Yuval {"CNIG port 3", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 556ba36f718SMintz, Yuval }; 557ba36f718SMintz, Yuval 5580d956e8aSYuval Mintz /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */ 5590d956e8aSYuval Mintz static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = { 5600d956e8aSYuval Mintz { 5610d956e8aSYuval Mintz { /* After Invert 1 */ 5620d956e8aSYuval Mintz {"GPIO0 function%d", 563b4149dc7SYuval Mintz (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 5640d956e8aSYuval Mintz } 5650d956e8aSYuval Mintz }, 5660d956e8aSYuval Mintz 5670d956e8aSYuval Mintz { 5680d956e8aSYuval Mintz { /* After Invert 2 */ 569b4149dc7SYuval Mintz {"PGLUE config_space", ATTENTION_SINGLE, 570b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 571b4149dc7SYuval Mintz {"PGLUE misc_flr", ATTENTION_SINGLE, 572b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 573b4149dc7SYuval Mintz {"PGLUE B RBC", ATTENTION_PAR_INT, 574666db486STomer Tayar qed_pglueb_rbc_attn_cb, BLOCK_PGLUE_B}, 575b4149dc7SYuval Mintz {"PGLUE misc_mctp", ATTENTION_SINGLE, 576b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 577b4149dc7SYuval Mintz {"Flash event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 578b4149dc7SYuval Mintz {"SMB event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 579b4149dc7SYuval Mintz {"Main Power", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 5800d956e8aSYuval Mintz {"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) | 581ff38577aSYuval Mintz (1 << ATTENTION_OFFSET_SHIFT), 582b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 5830d956e8aSYuval Mintz {"PCIE glue/PXP VPD %d", 584b4149dc7SYuval Mintz (16 << ATTENTION_LENGTH_SHIFT), NULL, BLOCK_PGLCS}, 5850d956e8aSYuval Mintz } 5860d956e8aSYuval Mintz }, 5870d956e8aSYuval Mintz 5880d956e8aSYuval Mintz { 5890d956e8aSYuval Mintz { /* After Invert 3 */ 5900d956e8aSYuval Mintz {"General Attention %d", 591b4149dc7SYuval Mintz (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 5920d956e8aSYuval Mintz } 5930d956e8aSYuval Mintz }, 5940d956e8aSYuval Mintz 5950d956e8aSYuval Mintz { 5960d956e8aSYuval Mintz { /* After Invert 4 */ 597936c7ba4SIgor Russkikh {"General Attention 32", ATTENTION_SINGLE | 598936c7ba4SIgor Russkikh ATTENTION_CLEAR_ENABLE, qed_fw_assertion, 5992ec276d5SIgor Russkikh MAX_BLOCK_ID}, 6000d956e8aSYuval Mintz {"General Attention %d", 6010d956e8aSYuval Mintz (2 << ATTENTION_LENGTH_SHIFT) | 602b4149dc7SYuval Mintz (33 << ATTENTION_OFFSET_SHIFT), NULL, MAX_BLOCK_ID}, 603936c7ba4SIgor Russkikh {"General Attention 35", ATTENTION_SINGLE | 604936c7ba4SIgor Russkikh ATTENTION_CLEAR_ENABLE, qed_general_attention_35, 605936c7ba4SIgor Russkikh MAX_BLOCK_ID}, 606ba36f718SMintz, Yuval {"NWS Parity", 607ba36f718SMintz, Yuval ATTENTION_PAR | ATTENTION_BB_DIFFERENT | 608ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_0), 609ba36f718SMintz, Yuval NULL, BLOCK_NWS}, 610ba36f718SMintz, Yuval {"NWS Interrupt", 611ba36f718SMintz, Yuval ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT | 612ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_1), 613ba36f718SMintz, Yuval NULL, BLOCK_NWS}, 614ba36f718SMintz, Yuval {"NWM Parity", 615ba36f718SMintz, Yuval ATTENTION_PAR | ATTENTION_BB_DIFFERENT | 616ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_2), 617ba36f718SMintz, Yuval NULL, BLOCK_NWM}, 618ba36f718SMintz, Yuval {"NWM Interrupt", 619ba36f718SMintz, Yuval ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT | 620ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_3), 621ba36f718SMintz, Yuval NULL, BLOCK_NWM}, 622b4149dc7SYuval Mintz {"MCP CPU", ATTENTION_SINGLE, 623b4149dc7SYuval Mintz qed_mcp_attn_cb, MAX_BLOCK_ID}, 624b4149dc7SYuval Mintz {"MCP Watchdog timer", ATTENTION_SINGLE, 625b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 626b4149dc7SYuval Mintz {"MCP M2P", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 627ff38577aSYuval Mintz {"AVS stop status ready", ATTENTION_SINGLE, 628b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 629b4149dc7SYuval Mintz {"MSTAT", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 630b4149dc7SYuval Mintz {"MSTAT per-path", ATTENTION_PAR_INT, 631b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 632ff38577aSYuval Mintz {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), 633b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 634b4149dc7SYuval Mintz {"NIG", ATTENTION_PAR_INT, NULL, BLOCK_NIG}, 635b4149dc7SYuval Mintz {"BMB/OPTE/MCP", ATTENTION_PAR_INT, NULL, BLOCK_BMB}, 636b4149dc7SYuval Mintz {"BTB", ATTENTION_PAR_INT, NULL, BLOCK_BTB}, 637b4149dc7SYuval Mintz {"BRB", ATTENTION_PAR_INT, NULL, BLOCK_BRB}, 638b4149dc7SYuval Mintz {"PRS", ATTENTION_PAR_INT, NULL, BLOCK_PRS}, 6390d956e8aSYuval Mintz } 6400d956e8aSYuval Mintz }, 6410d956e8aSYuval Mintz 6420d956e8aSYuval Mintz { 6430d956e8aSYuval Mintz { /* After Invert 5 */ 644b4149dc7SYuval Mintz {"SRC", ATTENTION_PAR_INT, NULL, BLOCK_SRC}, 645b4149dc7SYuval Mintz {"PB Client1", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB1}, 646b4149dc7SYuval Mintz {"PB Client2", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB2}, 647b4149dc7SYuval Mintz {"RPB", ATTENTION_PAR_INT, NULL, BLOCK_RPB}, 648b4149dc7SYuval Mintz {"PBF", ATTENTION_PAR_INT, NULL, BLOCK_PBF}, 649b4149dc7SYuval Mintz {"QM", ATTENTION_PAR_INT, NULL, BLOCK_QM}, 650b4149dc7SYuval Mintz {"TM", ATTENTION_PAR_INT, NULL, BLOCK_TM}, 651b4149dc7SYuval Mintz {"MCM", ATTENTION_PAR_INT, NULL, BLOCK_MCM}, 652b4149dc7SYuval Mintz {"MSDM", ATTENTION_PAR_INT, NULL, BLOCK_MSDM}, 653b4149dc7SYuval Mintz {"MSEM", ATTENTION_PAR_INT, NULL, BLOCK_MSEM}, 654b4149dc7SYuval Mintz {"PCM", ATTENTION_PAR_INT, NULL, BLOCK_PCM}, 655b4149dc7SYuval Mintz {"PSDM", ATTENTION_PAR_INT, NULL, BLOCK_PSDM}, 656b4149dc7SYuval Mintz {"PSEM", ATTENTION_PAR_INT, NULL, BLOCK_PSEM}, 657b4149dc7SYuval Mintz {"TCM", ATTENTION_PAR_INT, NULL, BLOCK_TCM}, 658b4149dc7SYuval Mintz {"TSDM", ATTENTION_PAR_INT, NULL, BLOCK_TSDM}, 659b4149dc7SYuval Mintz {"TSEM", ATTENTION_PAR_INT, NULL, BLOCK_TSEM}, 6600d956e8aSYuval Mintz } 6610d956e8aSYuval Mintz }, 6620d956e8aSYuval Mintz 6630d956e8aSYuval Mintz { 6640d956e8aSYuval Mintz { /* After Invert 6 */ 665b4149dc7SYuval Mintz {"UCM", ATTENTION_PAR_INT, NULL, BLOCK_UCM}, 666b4149dc7SYuval Mintz {"USDM", ATTENTION_PAR_INT, NULL, BLOCK_USDM}, 667b4149dc7SYuval Mintz {"USEM", ATTENTION_PAR_INT, NULL, BLOCK_USEM}, 668b4149dc7SYuval Mintz {"XCM", ATTENTION_PAR_INT, NULL, BLOCK_XCM}, 669b4149dc7SYuval Mintz {"XSDM", ATTENTION_PAR_INT, NULL, BLOCK_XSDM}, 670b4149dc7SYuval Mintz {"XSEM", ATTENTION_PAR_INT, NULL, BLOCK_XSEM}, 671b4149dc7SYuval Mintz {"YCM", ATTENTION_PAR_INT, NULL, BLOCK_YCM}, 672b4149dc7SYuval Mintz {"YSDM", ATTENTION_PAR_INT, NULL, BLOCK_YSDM}, 673b4149dc7SYuval Mintz {"YSEM", ATTENTION_PAR_INT, NULL, BLOCK_YSEM}, 674b4149dc7SYuval Mintz {"XYLD", ATTENTION_PAR_INT, NULL, BLOCK_XYLD}, 675b4149dc7SYuval Mintz {"TMLD", ATTENTION_PAR_INT, NULL, BLOCK_TMLD}, 676b4149dc7SYuval Mintz {"MYLD", ATTENTION_PAR_INT, NULL, BLOCK_MULD}, 677b4149dc7SYuval Mintz {"YULD", ATTENTION_PAR_INT, NULL, BLOCK_YULD}, 678b4149dc7SYuval Mintz {"DORQ", ATTENTION_PAR_INT, 679b4149dc7SYuval Mintz qed_dorq_attn_cb, BLOCK_DORQ}, 680b4149dc7SYuval Mintz {"DBG", ATTENTION_PAR_INT, NULL, BLOCK_DBG}, 681b4149dc7SYuval Mintz {"IPC", ATTENTION_PAR_INT, NULL, BLOCK_IPC}, 6820d956e8aSYuval Mintz } 6830d956e8aSYuval Mintz }, 6840d956e8aSYuval Mintz 6850d956e8aSYuval Mintz { 6860d956e8aSYuval Mintz { /* After Invert 7 */ 687b4149dc7SYuval Mintz {"CCFC", ATTENTION_PAR_INT, NULL, BLOCK_CCFC}, 688b4149dc7SYuval Mintz {"CDU", ATTENTION_PAR_INT, NULL, BLOCK_CDU}, 689b4149dc7SYuval Mintz {"DMAE", ATTENTION_PAR_INT, NULL, BLOCK_DMAE}, 690b4149dc7SYuval Mintz {"IGU", ATTENTION_PAR_INT, NULL, BLOCK_IGU}, 691b4149dc7SYuval Mintz {"ATC", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 692b4149dc7SYuval Mintz {"CAU", ATTENTION_PAR_INT, NULL, BLOCK_CAU}, 693b4149dc7SYuval Mintz {"PTU", ATTENTION_PAR_INT, NULL, BLOCK_PTU}, 694b4149dc7SYuval Mintz {"PRM", ATTENTION_PAR_INT, NULL, BLOCK_PRM}, 695b4149dc7SYuval Mintz {"TCFC", ATTENTION_PAR_INT, NULL, BLOCK_TCFC}, 696b4149dc7SYuval Mintz {"RDIF", ATTENTION_PAR_INT, NULL, BLOCK_RDIF}, 697b4149dc7SYuval Mintz {"TDIF", ATTENTION_PAR_INT, NULL, BLOCK_TDIF}, 698b4149dc7SYuval Mintz {"RSS", ATTENTION_PAR_INT, NULL, BLOCK_RSS}, 699b4149dc7SYuval Mintz {"MISC", ATTENTION_PAR_INT, NULL, BLOCK_MISC}, 700b4149dc7SYuval Mintz {"MISCS", ATTENTION_PAR_INT, NULL, BLOCK_MISCS}, 701b4149dc7SYuval Mintz {"PCIE", ATTENTION_PAR, NULL, BLOCK_PCIE}, 702b4149dc7SYuval Mintz {"Vaux PCI core", ATTENTION_SINGLE, NULL, BLOCK_PGLCS}, 703b4149dc7SYuval Mintz {"PSWRQ", ATTENTION_PAR_INT, NULL, BLOCK_PSWRQ}, 7040d956e8aSYuval Mintz } 7050d956e8aSYuval Mintz }, 7060d956e8aSYuval Mintz 7070d956e8aSYuval Mintz { 7080d956e8aSYuval Mintz { /* After Invert 8 */ 709b4149dc7SYuval Mintz {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, 710b4149dc7SYuval Mintz NULL, BLOCK_PSWRQ2}, 711b4149dc7SYuval Mintz {"PSWWR", ATTENTION_PAR_INT, NULL, BLOCK_PSWWR}, 712b4149dc7SYuval Mintz {"PSWWR (pci_clk)", ATTENTION_PAR_INT, 713b4149dc7SYuval Mintz NULL, BLOCK_PSWWR2}, 714b4149dc7SYuval Mintz {"PSWRD", ATTENTION_PAR_INT, NULL, BLOCK_PSWRD}, 715b4149dc7SYuval Mintz {"PSWRD (pci_clk)", ATTENTION_PAR_INT, 716b4149dc7SYuval Mintz NULL, BLOCK_PSWRD2}, 717b4149dc7SYuval Mintz {"PSWHST", ATTENTION_PAR_INT, 718b4149dc7SYuval Mintz qed_pswhst_attn_cb, BLOCK_PSWHST}, 719b4149dc7SYuval Mintz {"PSWHST (pci_clk)", ATTENTION_PAR_INT, 720b4149dc7SYuval Mintz NULL, BLOCK_PSWHST2}, 721b4149dc7SYuval Mintz {"GRC", ATTENTION_PAR_INT, 722b4149dc7SYuval Mintz qed_grc_attn_cb, BLOCK_GRC}, 723b4149dc7SYuval Mintz {"CPMU", ATTENTION_PAR_INT, NULL, BLOCK_CPMU}, 724b4149dc7SYuval Mintz {"NCSI", ATTENTION_PAR_INT, NULL, BLOCK_NCSI}, 725b4149dc7SYuval Mintz {"MSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 726b4149dc7SYuval Mintz {"PSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 727b4149dc7SYuval Mintz {"TSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 728b4149dc7SYuval Mintz {"USEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 729b4149dc7SYuval Mintz {"XSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 730b4149dc7SYuval Mintz {"YSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 731b4149dc7SYuval Mintz {"pxp_misc_mps", ATTENTION_PAR, NULL, BLOCK_PGLCS}, 732ff38577aSYuval Mintz {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, 733b4149dc7SYuval Mintz NULL, BLOCK_PGLCS}, 734b4149dc7SYuval Mintz {"PERST_B assertion", ATTENTION_SINGLE, 735b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 736ff38577aSYuval Mintz {"PERST_B deassertion", ATTENTION_SINGLE, 737b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 738ff38577aSYuval Mintz {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), 739b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 7400d956e8aSYuval Mintz } 7410d956e8aSYuval Mintz }, 7420d956e8aSYuval Mintz 7430d956e8aSYuval Mintz { 7440d956e8aSYuval Mintz { /* After Invert 9 */ 745b4149dc7SYuval Mintz {"MCP Latched memory", ATTENTION_PAR, 746b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 747ff38577aSYuval Mintz {"MCP Latched scratchpad cache", ATTENTION_SINGLE, 748b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 749b4149dc7SYuval Mintz {"MCP Latched ump_tx", ATTENTION_PAR, 750b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 751ff38577aSYuval Mintz {"MCP Latched scratchpad", ATTENTION_PAR, 752b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 753ff38577aSYuval Mintz {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT), 754b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 7550d956e8aSYuval Mintz } 7560d956e8aSYuval Mintz }, 7570d956e8aSYuval Mintz }; 7580d956e8aSYuval Mintz 759ba36f718SMintz, Yuval static struct aeu_invert_reg_bit * 760ba36f718SMintz, Yuval qed_int_aeu_translate(struct qed_hwfn *p_hwfn, 761ba36f718SMintz, Yuval struct aeu_invert_reg_bit *p_bit) 762ba36f718SMintz, Yuval { 763ba36f718SMintz, Yuval if (!QED_IS_BB(p_hwfn->cdev)) 764ba36f718SMintz, Yuval return p_bit; 765ba36f718SMintz, Yuval 766ba36f718SMintz, Yuval if (!(p_bit->flags & ATTENTION_BB_DIFFERENT)) 767ba36f718SMintz, Yuval return p_bit; 768ba36f718SMintz, Yuval 769ba36f718SMintz, Yuval return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >> 770ba36f718SMintz, Yuval ATTENTION_BB_SHIFT]; 771ba36f718SMintz, Yuval } 772ba36f718SMintz, Yuval 773ba36f718SMintz, Yuval static bool qed_int_is_parity_flag(struct qed_hwfn *p_hwfn, 774ba36f718SMintz, Yuval struct aeu_invert_reg_bit *p_bit) 775ba36f718SMintz, Yuval { 776ba36f718SMintz, Yuval return !!(qed_int_aeu_translate(p_hwfn, p_bit)->flags & 777ba36f718SMintz, Yuval ATTENTION_PARITY); 778ba36f718SMintz, Yuval } 779ba36f718SMintz, Yuval 780cc875c2eSYuval Mintz #define ATTN_STATE_BITS (0xfff) 781cc875c2eSYuval Mintz #define ATTN_BITS_MASKABLE (0x3ff) 782cc875c2eSYuval Mintz struct qed_sb_attn_info { 783cc875c2eSYuval Mintz /* Virtual & Physical address of the SB */ 784cc875c2eSYuval Mintz struct atten_status_block *sb_attn; 785cc875c2eSYuval Mintz dma_addr_t sb_phys; 786cc875c2eSYuval Mintz 787cc875c2eSYuval Mintz /* Last seen running index */ 788cc875c2eSYuval Mintz u16 index; 789cc875c2eSYuval Mintz 7900d956e8aSYuval Mintz /* A mask of the AEU bits resulting in a parity error */ 7910d956e8aSYuval Mintz u32 parity_mask[NUM_ATTN_REGS]; 7920d956e8aSYuval Mintz 7930d956e8aSYuval Mintz /* A pointer to the attention description structure */ 7940d956e8aSYuval Mintz struct aeu_invert_reg *p_aeu_desc; 7950d956e8aSYuval Mintz 796cc875c2eSYuval Mintz /* Previously asserted attentions, which are still unasserted */ 797cc875c2eSYuval Mintz u16 known_attn; 798cc875c2eSYuval Mintz 799cc875c2eSYuval Mintz /* Cleanup address for the link's general hw attention */ 800cc875c2eSYuval Mintz u32 mfw_attn_addr; 801cc875c2eSYuval Mintz }; 802cc875c2eSYuval Mintz 803cc875c2eSYuval Mintz static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn, 804cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb_desc) 805cc875c2eSYuval Mintz { 8061a635e48SYuval Mintz u16 rc = 0, index; 807cc875c2eSYuval Mintz 808cc875c2eSYuval Mintz index = le16_to_cpu(p_sb_desc->sb_attn->sb_index); 809cc875c2eSYuval Mintz if (p_sb_desc->index != index) { 810cc875c2eSYuval Mintz p_sb_desc->index = index; 811cc875c2eSYuval Mintz rc = QED_SB_ATT_IDX; 812cc875c2eSYuval Mintz } 813cc875c2eSYuval Mintz 814cc875c2eSYuval Mintz return rc; 815cc875c2eSYuval Mintz } 816cc875c2eSYuval Mintz 817cc875c2eSYuval Mintz /** 818cc875c2eSYuval Mintz * @brief qed_int_assertion - handles asserted attention bits 819cc875c2eSYuval Mintz * 820cc875c2eSYuval Mintz * @param p_hwfn 821cc875c2eSYuval Mintz * @param asserted_bits newly asserted bits 822cc875c2eSYuval Mintz * @return int 823cc875c2eSYuval Mintz */ 8241a635e48SYuval Mintz static int qed_int_assertion(struct qed_hwfn *p_hwfn, u16 asserted_bits) 825cc875c2eSYuval Mintz { 826cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 827cc875c2eSYuval Mintz u32 igu_mask; 828cc875c2eSYuval Mintz 829cc875c2eSYuval Mintz /* Mask the source of the attention in the IGU */ 8301a635e48SYuval Mintz igu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); 831cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n", 832cc875c2eSYuval Mintz igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE)); 833cc875c2eSYuval Mintz igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE); 834cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask); 835cc875c2eSYuval Mintz 836cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 837cc875c2eSYuval Mintz "inner known ATTN state: 0x%04x --> 0x%04x\n", 838cc875c2eSYuval Mintz sb_attn_sw->known_attn, 839cc875c2eSYuval Mintz sb_attn_sw->known_attn | asserted_bits); 840cc875c2eSYuval Mintz sb_attn_sw->known_attn |= asserted_bits; 841cc875c2eSYuval Mintz 842cc875c2eSYuval Mintz /* Handle MCP events */ 843cc875c2eSYuval Mintz if (asserted_bits & 0x100) { 844cc875c2eSYuval Mintz qed_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt); 845cc875c2eSYuval Mintz /* Clean the MCP attention */ 846cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 847cc875c2eSYuval Mintz sb_attn_sw->mfw_attn_addr, 0); 848cc875c2eSYuval Mintz } 849cc875c2eSYuval Mintz 850cc875c2eSYuval Mintz DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 851cc875c2eSYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 852cc875c2eSYuval Mintz ((IGU_CMD_ATTN_BIT_SET_UPPER - 853cc875c2eSYuval Mintz IGU_CMD_INT_ACK_BASE) << 3), 854cc875c2eSYuval Mintz (u32)asserted_bits); 855cc875c2eSYuval Mintz 856cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "set cmd IGU: 0x%04x\n", 857cc875c2eSYuval Mintz asserted_bits); 858cc875c2eSYuval Mintz 859cc875c2eSYuval Mintz return 0; 860cc875c2eSYuval Mintz } 861cc875c2eSYuval Mintz 8620ebbd1c8SMintz, Yuval static void qed_int_attn_print(struct qed_hwfn *p_hwfn, 8630ebbd1c8SMintz, Yuval enum block_id id, 8640ebbd1c8SMintz, Yuval enum dbg_attn_type type, bool b_clear) 865ff38577aSYuval Mintz { 8660ebbd1c8SMintz, Yuval struct dbg_attn_block_result attn_results; 8670ebbd1c8SMintz, Yuval enum dbg_status status; 868ff38577aSYuval Mintz 8690ebbd1c8SMintz, Yuval memset(&attn_results, 0, sizeof(attn_results)); 870ff38577aSYuval Mintz 8710ebbd1c8SMintz, Yuval status = qed_dbg_read_attn(p_hwfn, p_hwfn->p_dpc_ptt, id, type, 8720ebbd1c8SMintz, Yuval b_clear, &attn_results); 8730ebbd1c8SMintz, Yuval if (status != DBG_STATUS_OK) 874ff38577aSYuval Mintz DP_NOTICE(p_hwfn, 8750ebbd1c8SMintz, Yuval "Failed to parse attention information [status: %s]\n", 8760ebbd1c8SMintz, Yuval qed_dbg_get_status_str(status)); 8770ebbd1c8SMintz, Yuval else 8780ebbd1c8SMintz, Yuval qed_dbg_parse_attn(p_hwfn, &attn_results); 879ff38577aSYuval Mintz } 880ff38577aSYuval Mintz 881cc875c2eSYuval Mintz /** 8820d956e8aSYuval Mintz * @brief qed_int_deassertion_aeu_bit - handles the effects of a single 8830d956e8aSYuval Mintz * cause of the attention 8840d956e8aSYuval Mintz * 8850d956e8aSYuval Mintz * @param p_hwfn 8860d956e8aSYuval Mintz * @param p_aeu - descriptor of an AEU bit which caused the attention 8870d956e8aSYuval Mintz * @param aeu_en_reg - register offset of the AEU enable reg. which configured 8880d956e8aSYuval Mintz * this bit to this group. 8890d956e8aSYuval Mintz * @param bit_index - index of this bit in the aeu_en_reg 8900d956e8aSYuval Mintz * 8910d956e8aSYuval Mintz * @return int 8920d956e8aSYuval Mintz */ 8930d956e8aSYuval Mintz static int 8940d956e8aSYuval Mintz qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn, 8950d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_aeu, 8960d956e8aSYuval Mintz u32 aeu_en_reg, 8976010179dSMintz, Yuval const char *p_bit_name, u32 bitmask) 8980d956e8aSYuval Mintz { 8990ebbd1c8SMintz, Yuval bool b_fatal = false; 9000d956e8aSYuval Mintz int rc = -EINVAL; 901b4149dc7SYuval Mintz u32 val; 9020d956e8aSYuval Mintz 9030d956e8aSYuval Mintz DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n", 9046010179dSMintz, Yuval p_bit_name, bitmask); 9050d956e8aSYuval Mintz 906b4149dc7SYuval Mintz /* Call callback before clearing the interrupt status */ 907b4149dc7SYuval Mintz if (p_aeu->cb) { 908b4149dc7SYuval Mintz DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n", 9096010179dSMintz, Yuval p_bit_name); 910b4149dc7SYuval Mintz rc = p_aeu->cb(p_hwfn); 911b4149dc7SYuval Mintz } 912b4149dc7SYuval Mintz 9130ebbd1c8SMintz, Yuval if (rc) 9140ebbd1c8SMintz, Yuval b_fatal = true; 915ff38577aSYuval Mintz 9160ebbd1c8SMintz, Yuval /* Print HW block interrupt registers */ 9170ebbd1c8SMintz, Yuval if (p_aeu->block_index != MAX_BLOCK_ID) 9180ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, p_aeu->block_index, 9190ebbd1c8SMintz, Yuval ATTN_TYPE_INTERRUPT, !b_fatal); 920ff38577aSYuval Mintz 9212ec276d5SIgor Russkikh /* Reach assertion if attention is fatal */ 9222ec276d5SIgor Russkikh if (b_fatal) 9232ec276d5SIgor Russkikh qed_hw_err_notify(p_hwfn, p_hwfn->p_dpc_ptt, QED_HW_ERR_HW_ATTN, 9242ec276d5SIgor Russkikh "`%s': Fatal attention\n", 9252ec276d5SIgor Russkikh p_bit_name); 9262ec276d5SIgor Russkikh else /* If the attention is benign, no need to prevent it */ 927b4149dc7SYuval Mintz goto out; 928b4149dc7SYuval Mintz 9290d956e8aSYuval Mintz /* Prevent this Attention from being asserted in the future */ 9300d956e8aSYuval Mintz val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 931b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & ~bitmask)); 9320d956e8aSYuval Mintz DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n", 9336010179dSMintz, Yuval p_bit_name); 9340d956e8aSYuval Mintz 935b4149dc7SYuval Mintz out: 9360d956e8aSYuval Mintz return rc; 9370d956e8aSYuval Mintz } 9380d956e8aSYuval Mintz 939ff38577aSYuval Mintz /** 940ff38577aSYuval Mintz * @brief qed_int_deassertion_parity - handle a single parity AEU source 941ff38577aSYuval Mintz * 942ff38577aSYuval Mintz * @param p_hwfn 943ff38577aSYuval Mintz * @param p_aeu - descriptor of an AEU bit which caused the parity 9449790c35eSMintz, Yuval * @param aeu_en_reg - address of the AEU enable register 945ff38577aSYuval Mintz * @param bit_index 946ff38577aSYuval Mintz */ 947ff38577aSYuval Mintz static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn, 948ff38577aSYuval Mintz struct aeu_invert_reg_bit *p_aeu, 9499790c35eSMintz, Yuval u32 aeu_en_reg, u8 bit_index) 950ff38577aSYuval Mintz { 9519790c35eSMintz, Yuval u32 block_id = p_aeu->block_index, mask, val; 952ff38577aSYuval Mintz 9539790c35eSMintz, Yuval DP_NOTICE(p_hwfn->cdev, 9549790c35eSMintz, Yuval "%s parity attention is set [address 0x%08x, bit %d]\n", 9559790c35eSMintz, Yuval p_aeu->bit_name, aeu_en_reg, bit_index); 956ff38577aSYuval Mintz 957ff38577aSYuval Mintz if (block_id != MAX_BLOCK_ID) { 9580ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, block_id, ATTN_TYPE_PARITY, false); 959ff38577aSYuval Mintz 960ff38577aSYuval Mintz /* In BB, there's a single parity bit for several blocks */ 961ff38577aSYuval Mintz if (block_id == BLOCK_BTB) { 9620ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, BLOCK_OPTE, 9630ebbd1c8SMintz, Yuval ATTN_TYPE_PARITY, false); 9640ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, BLOCK_MCP, 9650ebbd1c8SMintz, Yuval ATTN_TYPE_PARITY, false); 966ff38577aSYuval Mintz } 967ff38577aSYuval Mintz } 9689790c35eSMintz, Yuval 9699790c35eSMintz, Yuval /* Prevent this parity error from being re-asserted */ 9709790c35eSMintz, Yuval mask = ~BIT(bit_index); 9719790c35eSMintz, Yuval val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 9729790c35eSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask); 9739790c35eSMintz, Yuval DP_INFO(p_hwfn, "`%s' - Disabled future parity errors\n", 9749790c35eSMintz, Yuval p_aeu->bit_name); 975ff38577aSYuval Mintz } 976ff38577aSYuval Mintz 9770d956e8aSYuval Mintz /** 978cc875c2eSYuval Mintz * @brief - handles deassertion of previously asserted attentions. 979cc875c2eSYuval Mintz * 980cc875c2eSYuval Mintz * @param p_hwfn 981cc875c2eSYuval Mintz * @param deasserted_bits - newly deasserted bits 982cc875c2eSYuval Mintz * @return int 983cc875c2eSYuval Mintz * 984cc875c2eSYuval Mintz */ 985cc875c2eSYuval Mintz static int qed_int_deassertion(struct qed_hwfn *p_hwfn, 986cc875c2eSYuval Mintz u16 deasserted_bits) 987cc875c2eSYuval Mintz { 988cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 9899790c35eSMintz, Yuval u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask, aeu_en, en; 9900d956e8aSYuval Mintz u8 i, j, k, bit_idx; 9910d956e8aSYuval Mintz int rc = 0; 992cc875c2eSYuval Mintz 9930d956e8aSYuval Mintz /* Read the attention registers in the AEU */ 9940d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 9950d956e8aSYuval Mintz aeu_inv_arr[i] = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 9960d956e8aSYuval Mintz MISC_REG_AEU_AFTER_INVERT_1_IGU + 9970d956e8aSYuval Mintz i * 0x4); 9980d956e8aSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 9990d956e8aSYuval Mintz "Deasserted bits [%d]: %08x\n", 10000d956e8aSYuval Mintz i, aeu_inv_arr[i]); 10010d956e8aSYuval Mintz } 10020d956e8aSYuval Mintz 10030d956e8aSYuval Mintz /* Find parity attentions first */ 10040d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 10050d956e8aSYuval Mintz struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i]; 10060d956e8aSYuval Mintz u32 parities; 10070d956e8aSYuval Mintz 10089790c35eSMintz, Yuval aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + i * sizeof(u32); 10099790c35eSMintz, Yuval en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 10109790c35eSMintz, Yuval 10110d956e8aSYuval Mintz /* Skip register in which no parity bit is currently set */ 10120d956e8aSYuval Mintz parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en; 10130d956e8aSYuval Mintz if (!parities) 10140d956e8aSYuval Mintz continue; 10150d956e8aSYuval Mintz 10160d956e8aSYuval Mintz for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 10170d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j]; 10180d956e8aSYuval Mintz 1019ba36f718SMintz, Yuval if (qed_int_is_parity_flag(p_hwfn, p_bit) && 10201a635e48SYuval Mintz !!(parities & BIT(bit_idx))) 1021ff38577aSYuval Mintz qed_int_deassertion_parity(p_hwfn, p_bit, 10229790c35eSMintz, Yuval aeu_en, bit_idx); 10230d956e8aSYuval Mintz 10240d956e8aSYuval Mintz bit_idx += ATTENTION_LENGTH(p_bit->flags); 10250d956e8aSYuval Mintz } 10260d956e8aSYuval Mintz } 10270d956e8aSYuval Mintz 10280d956e8aSYuval Mintz /* Find non-parity cause for attention and act */ 10290d956e8aSYuval Mintz for (k = 0; k < MAX_ATTN_GRPS; k++) { 10300d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_aeu; 10310d956e8aSYuval Mintz 10320d956e8aSYuval Mintz /* Handle only groups whose attention is currently deasserted */ 10330d956e8aSYuval Mintz if (!(deasserted_bits & (1 << k))) 10340d956e8aSYuval Mintz continue; 10350d956e8aSYuval Mintz 10360d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 10379790c35eSMintz, Yuval u32 bits; 10389790c35eSMintz, Yuval 10399790c35eSMintz, Yuval aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + 10400d956e8aSYuval Mintz i * sizeof(u32) + 10410d956e8aSYuval Mintz k * sizeof(u32) * NUM_ATTN_REGS; 10420d956e8aSYuval Mintz 10430d956e8aSYuval Mintz en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 10440d956e8aSYuval Mintz bits = aeu_inv_arr[i] & en; 10450d956e8aSYuval Mintz 10460d956e8aSYuval Mintz /* Skip if no bit from this group is currently set */ 10470d956e8aSYuval Mintz if (!bits) 10480d956e8aSYuval Mintz continue; 10490d956e8aSYuval Mintz 10500d956e8aSYuval Mintz /* Find all set bits from current register which belong 10510d956e8aSYuval Mintz * to current group, making them responsible for the 10520d956e8aSYuval Mintz * previous assertion. 10530d956e8aSYuval Mintz */ 10540d956e8aSYuval Mintz for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 10556010179dSMintz, Yuval long unsigned int bitmask; 10560d956e8aSYuval Mintz u8 bit, bit_len; 10570d956e8aSYuval Mintz 10580d956e8aSYuval Mintz p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j]; 1059ba36f718SMintz, Yuval p_aeu = qed_int_aeu_translate(p_hwfn, p_aeu); 10600d956e8aSYuval Mintz 10610d956e8aSYuval Mintz bit = bit_idx; 10620d956e8aSYuval Mintz bit_len = ATTENTION_LENGTH(p_aeu->flags); 1063ba36f718SMintz, Yuval if (qed_int_is_parity_flag(p_hwfn, p_aeu)) { 10640d956e8aSYuval Mintz /* Skip Parity */ 10650d956e8aSYuval Mintz bit++; 10660d956e8aSYuval Mintz bit_len--; 10670d956e8aSYuval Mintz } 10680d956e8aSYuval Mintz 10690d956e8aSYuval Mintz bitmask = bits & (((1 << bit_len) - 1) << bit); 10706010179dSMintz, Yuval bitmask >>= bit; 10716010179dSMintz, Yuval 10720d956e8aSYuval Mintz if (bitmask) { 10736010179dSMintz, Yuval u32 flags = p_aeu->flags; 10746010179dSMintz, Yuval char bit_name[30]; 10756010179dSMintz, Yuval u8 num; 10766010179dSMintz, Yuval 10776010179dSMintz, Yuval num = (u8)find_first_bit(&bitmask, 10786010179dSMintz, Yuval bit_len); 10796010179dSMintz, Yuval 10806010179dSMintz, Yuval /* Some bits represent more than a 10816010179dSMintz, Yuval * a single interrupt. Correctly print 10826010179dSMintz, Yuval * their name. 10836010179dSMintz, Yuval */ 10846010179dSMintz, Yuval if (ATTENTION_LENGTH(flags) > 2 || 10856010179dSMintz, Yuval ((flags & ATTENTION_PAR_INT) && 10866010179dSMintz, Yuval ATTENTION_LENGTH(flags) > 1)) 10876010179dSMintz, Yuval snprintf(bit_name, 30, 10886010179dSMintz, Yuval p_aeu->bit_name, num); 10896010179dSMintz, Yuval else 10903690c8c9SWang Xiayang strlcpy(bit_name, 10916010179dSMintz, Yuval p_aeu->bit_name, 30); 10926010179dSMintz, Yuval 10936010179dSMintz, Yuval /* We now need to pass bitmask in its 10946010179dSMintz, Yuval * correct position. 10956010179dSMintz, Yuval */ 10966010179dSMintz, Yuval bitmask <<= bit; 10976010179dSMintz, Yuval 10980d956e8aSYuval Mintz /* Handle source of the attention */ 10990d956e8aSYuval Mintz qed_int_deassertion_aeu_bit(p_hwfn, 11000d956e8aSYuval Mintz p_aeu, 11010d956e8aSYuval Mintz aeu_en, 11026010179dSMintz, Yuval bit_name, 11030d956e8aSYuval Mintz bitmask); 11040d956e8aSYuval Mintz } 11050d956e8aSYuval Mintz 11060d956e8aSYuval Mintz bit_idx += ATTENTION_LENGTH(p_aeu->flags); 11070d956e8aSYuval Mintz } 11080d956e8aSYuval Mintz } 11090d956e8aSYuval Mintz } 1110cc875c2eSYuval Mintz 1111d4476b8aSDenis Bolotin /* Handle missed DORQ attention */ 1112d4476b8aSDenis Bolotin qed_dorq_attn_handler(p_hwfn); 1113d4476b8aSDenis Bolotin 1114cc875c2eSYuval Mintz /* Clear IGU indication for the deasserted bits */ 1115cc875c2eSYuval Mintz DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 1116cc875c2eSYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 1117cc875c2eSYuval Mintz ((IGU_CMD_ATTN_BIT_CLR_UPPER - 1118cc875c2eSYuval Mintz IGU_CMD_INT_ACK_BASE) << 3), 1119cc875c2eSYuval Mintz ~((u32)deasserted_bits)); 1120cc875c2eSYuval Mintz 1121cc875c2eSYuval Mintz /* Unmask deasserted attentions in IGU */ 11221a635e48SYuval Mintz aeu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); 1123cc875c2eSYuval Mintz aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE); 1124cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask); 1125cc875c2eSYuval Mintz 1126cc875c2eSYuval Mintz /* Clear deassertion from inner state */ 1127cc875c2eSYuval Mintz sb_attn_sw->known_attn &= ~deasserted_bits; 1128cc875c2eSYuval Mintz 11290d956e8aSYuval Mintz return rc; 1130cc875c2eSYuval Mintz } 1131cc875c2eSYuval Mintz 1132cc875c2eSYuval Mintz static int qed_int_attentions(struct qed_hwfn *p_hwfn) 1133cc875c2eSYuval Mintz { 1134cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn; 1135cc875c2eSYuval Mintz struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn; 1136cc875c2eSYuval Mintz u32 attn_bits = 0, attn_acks = 0; 1137cc875c2eSYuval Mintz u16 asserted_bits, deasserted_bits; 1138cc875c2eSYuval Mintz __le16 index; 1139cc875c2eSYuval Mintz int rc = 0; 1140cc875c2eSYuval Mintz 1141cc875c2eSYuval Mintz /* Read current attention bits/acks - safeguard against attentions 1142cc875c2eSYuval Mintz * by guaranting work on a synchronized timeframe 1143cc875c2eSYuval Mintz */ 1144cc875c2eSYuval Mintz do { 1145cc875c2eSYuval Mintz index = p_sb_attn->sb_index; 1146ed4eac20SDenis Bolotin /* finish reading index before the loop condition */ 1147ed4eac20SDenis Bolotin dma_rmb(); 1148cc875c2eSYuval Mintz attn_bits = le32_to_cpu(p_sb_attn->atten_bits); 1149cc875c2eSYuval Mintz attn_acks = le32_to_cpu(p_sb_attn->atten_ack); 1150cc875c2eSYuval Mintz } while (index != p_sb_attn->sb_index); 1151cc875c2eSYuval Mintz p_sb_attn->sb_index = index; 1152cc875c2eSYuval Mintz 1153cc875c2eSYuval Mintz /* Attention / Deassertion are meaningful (and in correct state) 1154cc875c2eSYuval Mintz * only when they differ and consistent with known state - deassertion 1155cc875c2eSYuval Mintz * when previous attention & current ack, and assertion when current 1156cc875c2eSYuval Mintz * attention with no previous attention 1157cc875c2eSYuval Mintz */ 1158cc875c2eSYuval Mintz asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) & 1159cc875c2eSYuval Mintz ~p_sb_attn_sw->known_attn; 1160cc875c2eSYuval Mintz deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) & 1161cc875c2eSYuval Mintz p_sb_attn_sw->known_attn; 1162cc875c2eSYuval Mintz 1163cc875c2eSYuval Mintz if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100)) { 1164cc875c2eSYuval Mintz DP_INFO(p_hwfn, 1165cc875c2eSYuval Mintz "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n", 1166cc875c2eSYuval Mintz index, attn_bits, attn_acks, asserted_bits, 1167cc875c2eSYuval Mintz deasserted_bits, p_sb_attn_sw->known_attn); 1168cc875c2eSYuval Mintz } else if (asserted_bits == 0x100) { 11691a635e48SYuval Mintz DP_INFO(p_hwfn, "MFW indication via attention\n"); 1170cc875c2eSYuval Mintz } else { 1171cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1172cc875c2eSYuval Mintz "MFW indication [deassertion]\n"); 1173cc875c2eSYuval Mintz } 1174cc875c2eSYuval Mintz 1175cc875c2eSYuval Mintz if (asserted_bits) { 1176cc875c2eSYuval Mintz rc = qed_int_assertion(p_hwfn, asserted_bits); 1177cc875c2eSYuval Mintz if (rc) 1178cc875c2eSYuval Mintz return rc; 1179cc875c2eSYuval Mintz } 1180cc875c2eSYuval Mintz 11811a635e48SYuval Mintz if (deasserted_bits) 1182cc875c2eSYuval Mintz rc = qed_int_deassertion(p_hwfn, deasserted_bits); 1183cc875c2eSYuval Mintz 1184cc875c2eSYuval Mintz return rc; 1185cc875c2eSYuval Mintz } 1186cc875c2eSYuval Mintz 1187cc875c2eSYuval Mintz static void qed_sb_ack_attn(struct qed_hwfn *p_hwfn, 11881a635e48SYuval Mintz void __iomem *igu_addr, u32 ack_cons) 1189cc875c2eSYuval Mintz { 1190cc875c2eSYuval Mintz struct igu_prod_cons_update igu_ack = { 0 }; 1191cc875c2eSYuval Mintz 1192cc875c2eSYuval Mintz igu_ack.sb_id_and_flags = 1193cc875c2eSYuval Mintz ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 1194cc875c2eSYuval Mintz (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 1195cc875c2eSYuval Mintz (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 1196cc875c2eSYuval Mintz (IGU_SEG_ACCESS_ATTN << 1197cc875c2eSYuval Mintz IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 1198cc875c2eSYuval Mintz 1199cc875c2eSYuval Mintz DIRECT_REG_WR(igu_addr, igu_ack.sb_id_and_flags); 1200cc875c2eSYuval Mintz 1201cc875c2eSYuval Mintz /* Both segments (interrupts & acks) are written to same place address; 1202cc875c2eSYuval Mintz * Need to guarantee all commands will be received (in-order) by HW. 1203cc875c2eSYuval Mintz */ 1204cc875c2eSYuval Mintz barrier(); 1205cc875c2eSYuval Mintz } 1206cc875c2eSYuval Mintz 1207fe56b9e6SYuval Mintz void qed_int_sp_dpc(unsigned long hwfn_cookie) 1208fe56b9e6SYuval Mintz { 1209fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = (struct qed_hwfn *)hwfn_cookie; 1210fe56b9e6SYuval Mintz struct qed_pi_info *pi_info = NULL; 1211cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn; 1212fe56b9e6SYuval Mintz struct qed_sb_info *sb_info; 1213fe56b9e6SYuval Mintz int arr_size; 1214fe56b9e6SYuval Mintz u16 rc = 0; 1215fe56b9e6SYuval Mintz 1216fe56b9e6SYuval Mintz if (!p_hwfn->p_sp_sb) { 1217fe56b9e6SYuval Mintz DP_ERR(p_hwfn->cdev, "DPC called - no p_sp_sb\n"); 1218fe56b9e6SYuval Mintz return; 1219fe56b9e6SYuval Mintz } 1220fe56b9e6SYuval Mintz 1221fe56b9e6SYuval Mintz sb_info = &p_hwfn->p_sp_sb->sb_info; 1222fe56b9e6SYuval Mintz arr_size = ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr); 1223fe56b9e6SYuval Mintz if (!sb_info) { 1224fe56b9e6SYuval Mintz DP_ERR(p_hwfn->cdev, 1225fe56b9e6SYuval Mintz "Status block is NULL - cannot ack interrupts\n"); 1226fe56b9e6SYuval Mintz return; 1227fe56b9e6SYuval Mintz } 1228fe56b9e6SYuval Mintz 1229cc875c2eSYuval Mintz if (!p_hwfn->p_sb_attn) { 1230cc875c2eSYuval Mintz DP_ERR(p_hwfn->cdev, "DPC called - no p_sb_attn"); 1231cc875c2eSYuval Mintz return; 1232cc875c2eSYuval Mintz } 1233cc875c2eSYuval Mintz sb_attn = p_hwfn->p_sb_attn; 1234cc875c2eSYuval Mintz 1235fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "DPC Called! (hwfn %p %d)\n", 1236fe56b9e6SYuval Mintz p_hwfn, p_hwfn->my_id); 1237fe56b9e6SYuval Mintz 1238fe56b9e6SYuval Mintz /* Disable ack for def status block. Required both for msix + 1239fe56b9e6SYuval Mintz * inta in non-mask mode, in inta does no harm. 1240fe56b9e6SYuval Mintz */ 1241fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_DISABLE, 0); 1242fe56b9e6SYuval Mintz 1243fe56b9e6SYuval Mintz /* Gather Interrupts/Attentions information */ 1244fe56b9e6SYuval Mintz if (!sb_info->sb_virt) { 12451a635e48SYuval Mintz DP_ERR(p_hwfn->cdev, 1246fe56b9e6SYuval Mintz "Interrupt Status block is NULL - cannot check for new interrupts!\n"); 1247fe56b9e6SYuval Mintz } else { 1248fe56b9e6SYuval Mintz u32 tmp_index = sb_info->sb_ack; 1249fe56b9e6SYuval Mintz 1250fe56b9e6SYuval Mintz rc = qed_sb_update_sb_idx(sb_info); 1251fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 1252fe56b9e6SYuval Mintz "Interrupt indices: 0x%08x --> 0x%08x\n", 1253fe56b9e6SYuval Mintz tmp_index, sb_info->sb_ack); 1254fe56b9e6SYuval Mintz } 1255fe56b9e6SYuval Mintz 1256cc875c2eSYuval Mintz if (!sb_attn || !sb_attn->sb_attn) { 12571a635e48SYuval Mintz DP_ERR(p_hwfn->cdev, 1258cc875c2eSYuval Mintz "Attentions Status block is NULL - cannot check for new attentions!\n"); 1259cc875c2eSYuval Mintz } else { 1260cc875c2eSYuval Mintz u16 tmp_index = sb_attn->index; 1261cc875c2eSYuval Mintz 1262cc875c2eSYuval Mintz rc |= qed_attn_update_idx(p_hwfn, sb_attn); 1263cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 1264cc875c2eSYuval Mintz "Attention indices: 0x%08x --> 0x%08x\n", 1265cc875c2eSYuval Mintz tmp_index, sb_attn->index); 1266cc875c2eSYuval Mintz } 1267cc875c2eSYuval Mintz 1268fe56b9e6SYuval Mintz /* Check if we expect interrupts at this time. if not just ack them */ 1269fe56b9e6SYuval Mintz if (!(rc & QED_SB_EVENT_MASK)) { 1270fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1271fe56b9e6SYuval Mintz return; 1272fe56b9e6SYuval Mintz } 1273fe56b9e6SYuval Mintz 1274fe56b9e6SYuval Mintz /* Check the validity of the DPC ptt. If not ack interrupts and fail */ 1275fe56b9e6SYuval Mintz if (!p_hwfn->p_dpc_ptt) { 1276fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn->cdev, "Failed to allocate PTT\n"); 1277fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1278fe56b9e6SYuval Mintz return; 1279fe56b9e6SYuval Mintz } 1280fe56b9e6SYuval Mintz 1281cc875c2eSYuval Mintz if (rc & QED_SB_ATT_IDX) 1282cc875c2eSYuval Mintz qed_int_attentions(p_hwfn); 1283cc875c2eSYuval Mintz 1284fe56b9e6SYuval Mintz if (rc & QED_SB_IDX) { 1285fe56b9e6SYuval Mintz int pi; 1286fe56b9e6SYuval Mintz 1287fe56b9e6SYuval Mintz /* Look for a free index */ 1288fe56b9e6SYuval Mintz for (pi = 0; pi < arr_size; pi++) { 1289fe56b9e6SYuval Mintz pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi]; 1290fe56b9e6SYuval Mintz if (pi_info->comp_cb) 1291fe56b9e6SYuval Mintz pi_info->comp_cb(p_hwfn, pi_info->cookie); 1292fe56b9e6SYuval Mintz } 1293fe56b9e6SYuval Mintz } 1294fe56b9e6SYuval Mintz 1295cc875c2eSYuval Mintz if (sb_attn && (rc & QED_SB_ATT_IDX)) 1296cc875c2eSYuval Mintz /* This should be done before the interrupts are enabled, 1297cc875c2eSYuval Mintz * since otherwise a new attention will be generated. 1298cc875c2eSYuval Mintz */ 1299cc875c2eSYuval Mintz qed_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index); 1300cc875c2eSYuval Mintz 1301fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1302fe56b9e6SYuval Mintz } 1303fe56b9e6SYuval Mintz 1304cc875c2eSYuval Mintz static void qed_int_sb_attn_free(struct qed_hwfn *p_hwfn) 1305cc875c2eSYuval Mintz { 1306cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb = p_hwfn->p_sb_attn; 1307cc875c2eSYuval Mintz 13084ac801b7SYuval Mintz if (!p_sb) 13094ac801b7SYuval Mintz return; 13104ac801b7SYuval Mintz 1311cc875c2eSYuval Mintz if (p_sb->sb_attn) 13124ac801b7SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1313cc875c2eSYuval Mintz SB_ATTN_ALIGNED_SIZE(p_hwfn), 13141a635e48SYuval Mintz p_sb->sb_attn, p_sb->sb_phys); 1315cc875c2eSYuval Mintz kfree(p_sb); 13163587cb87STomer Tayar p_hwfn->p_sb_attn = NULL; 1317cc875c2eSYuval Mintz } 1318cc875c2eSYuval Mintz 1319cc875c2eSYuval Mintz static void qed_int_sb_attn_setup(struct qed_hwfn *p_hwfn, 1320cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1321cc875c2eSYuval Mintz { 1322cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 1323cc875c2eSYuval Mintz 1324cc875c2eSYuval Mintz memset(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn)); 1325cc875c2eSYuval Mintz 1326cc875c2eSYuval Mintz sb_info->index = 0; 1327cc875c2eSYuval Mintz sb_info->known_attn = 0; 1328cc875c2eSYuval Mintz 1329cc875c2eSYuval Mintz /* Configure Attention Status Block in IGU */ 1330cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L, 1331cc875c2eSYuval Mintz lower_32_bits(p_hwfn->p_sb_attn->sb_phys)); 1332cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H, 1333cc875c2eSYuval Mintz upper_32_bits(p_hwfn->p_sb_attn->sb_phys)); 1334cc875c2eSYuval Mintz } 1335cc875c2eSYuval Mintz 1336cc875c2eSYuval Mintz static void qed_int_sb_attn_init(struct qed_hwfn *p_hwfn, 1337cc875c2eSYuval Mintz struct qed_ptt *p_ptt, 13381a635e48SYuval Mintz void *sb_virt_addr, dma_addr_t sb_phy_addr) 1339cc875c2eSYuval Mintz { 1340cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 13410d956e8aSYuval Mintz int i, j, k; 1342cc875c2eSYuval Mintz 1343cc875c2eSYuval Mintz sb_info->sb_attn = sb_virt_addr; 1344cc875c2eSYuval Mintz sb_info->sb_phys = sb_phy_addr; 1345cc875c2eSYuval Mintz 13460d956e8aSYuval Mintz /* Set the pointer to the AEU descriptors */ 13470d956e8aSYuval Mintz sb_info->p_aeu_desc = aeu_descs; 13480d956e8aSYuval Mintz 13490d956e8aSYuval Mintz /* Calculate Parity Masks */ 13500d956e8aSYuval Mintz memset(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS); 13510d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 13520d956e8aSYuval Mintz /* j is array index, k is bit index */ 13530d956e8aSYuval Mintz for (j = 0, k = 0; k < 32; j++) { 1354ba36f718SMintz, Yuval struct aeu_invert_reg_bit *p_aeu; 13550d956e8aSYuval Mintz 1356ba36f718SMintz, Yuval p_aeu = &aeu_descs[i].bits[j]; 1357ba36f718SMintz, Yuval if (qed_int_is_parity_flag(p_hwfn, p_aeu)) 13580d956e8aSYuval Mintz sb_info->parity_mask[i] |= 1 << k; 13590d956e8aSYuval Mintz 1360ba36f718SMintz, Yuval k += ATTENTION_LENGTH(p_aeu->flags); 13610d956e8aSYuval Mintz } 13620d956e8aSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 13630d956e8aSYuval Mintz "Attn Mask [Reg %d]: 0x%08x\n", 13640d956e8aSYuval Mintz i, sb_info->parity_mask[i]); 13650d956e8aSYuval Mintz } 13660d956e8aSYuval Mintz 1367cc875c2eSYuval Mintz /* Set the address of cleanup for the mcp attention */ 1368cc875c2eSYuval Mintz sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) + 1369cc875c2eSYuval Mintz MISC_REG_AEU_GENERAL_ATTN_0; 1370cc875c2eSYuval Mintz 1371cc875c2eSYuval Mintz qed_int_sb_attn_setup(p_hwfn, p_ptt); 1372cc875c2eSYuval Mintz } 1373cc875c2eSYuval Mintz 1374cc875c2eSYuval Mintz static int qed_int_sb_attn_alloc(struct qed_hwfn *p_hwfn, 1375cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1376cc875c2eSYuval Mintz { 1377cc875c2eSYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 1378cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb; 1379cc875c2eSYuval Mintz dma_addr_t p_phys = 0; 13801a635e48SYuval Mintz void *p_virt; 1381cc875c2eSYuval Mintz 1382cc875c2eSYuval Mintz /* SB struct */ 138360fffb3bSYuval Mintz p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 13842591c280SJoe Perches if (!p_sb) 1385cc875c2eSYuval Mintz return -ENOMEM; 1386cc875c2eSYuval Mintz 1387cc875c2eSYuval Mintz /* SB ring */ 1388cc875c2eSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 1389cc875c2eSYuval Mintz SB_ATTN_ALIGNED_SIZE(p_hwfn), 1390cc875c2eSYuval Mintz &p_phys, GFP_KERNEL); 1391cc875c2eSYuval Mintz 1392cc875c2eSYuval Mintz if (!p_virt) { 1393cc875c2eSYuval Mintz kfree(p_sb); 1394cc875c2eSYuval Mintz return -ENOMEM; 1395cc875c2eSYuval Mintz } 1396cc875c2eSYuval Mintz 1397cc875c2eSYuval Mintz /* Attention setup */ 1398cc875c2eSYuval Mintz p_hwfn->p_sb_attn = p_sb; 1399cc875c2eSYuval Mintz qed_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys); 1400cc875c2eSYuval Mintz 1401cc875c2eSYuval Mintz return 0; 1402cc875c2eSYuval Mintz } 1403cc875c2eSYuval Mintz 1404fe56b9e6SYuval Mintz /* coalescing timeout = timeset << (timer_res + 1) */ 1405fe56b9e6SYuval Mintz #define QED_CAU_DEF_RX_USECS 24 1406fe56b9e6SYuval Mintz #define QED_CAU_DEF_TX_USECS 48 1407fe56b9e6SYuval Mintz 1408fe56b9e6SYuval Mintz void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn, 1409fe56b9e6SYuval Mintz struct cau_sb_entry *p_sb_entry, 14101a635e48SYuval Mintz u8 pf_id, u16 vf_number, u8 vf_valid) 1411fe56b9e6SYuval Mintz { 14124ac801b7SYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 1413fe56b9e6SYuval Mintz u32 cau_state; 1414722003acSSudarsana Reddy Kalluru u8 timer_res; 1415fe56b9e6SYuval Mintz 1416fe56b9e6SYuval Mintz memset(p_sb_entry, 0, sizeof(*p_sb_entry)); 1417fe56b9e6SYuval Mintz 1418fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id); 1419fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number); 1420fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid); 1421fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F); 1422fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F); 1423fe56b9e6SYuval Mintz 1424fe56b9e6SYuval Mintz cau_state = CAU_HC_DISABLE_STATE; 1425fe56b9e6SYuval Mintz 14264ac801b7SYuval Mintz if (cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 1427fe56b9e6SYuval Mintz cau_state = CAU_HC_ENABLE_STATE; 14284ac801b7SYuval Mintz if (!cdev->rx_coalesce_usecs) 14294ac801b7SYuval Mintz cdev->rx_coalesce_usecs = QED_CAU_DEF_RX_USECS; 14304ac801b7SYuval Mintz if (!cdev->tx_coalesce_usecs) 14314ac801b7SYuval Mintz cdev->tx_coalesce_usecs = QED_CAU_DEF_TX_USECS; 1432fe56b9e6SYuval Mintz } 1433fe56b9e6SYuval Mintz 1434722003acSSudarsana Reddy Kalluru /* Coalesce = (timeset << timer-res), timeset is 7bit wide */ 1435722003acSSudarsana Reddy Kalluru if (cdev->rx_coalesce_usecs <= 0x7F) 1436722003acSSudarsana Reddy Kalluru timer_res = 0; 1437722003acSSudarsana Reddy Kalluru else if (cdev->rx_coalesce_usecs <= 0xFF) 1438722003acSSudarsana Reddy Kalluru timer_res = 1; 1439722003acSSudarsana Reddy Kalluru else 1440722003acSSudarsana Reddy Kalluru timer_res = 2; 1441722003acSSudarsana Reddy Kalluru SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 1442722003acSSudarsana Reddy Kalluru 1443722003acSSudarsana Reddy Kalluru if (cdev->tx_coalesce_usecs <= 0x7F) 1444722003acSSudarsana Reddy Kalluru timer_res = 0; 1445722003acSSudarsana Reddy Kalluru else if (cdev->tx_coalesce_usecs <= 0xFF) 1446722003acSSudarsana Reddy Kalluru timer_res = 1; 1447722003acSSudarsana Reddy Kalluru else 1448722003acSSudarsana Reddy Kalluru timer_res = 2; 1449722003acSSudarsana Reddy Kalluru SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 1450722003acSSudarsana Reddy Kalluru 1451fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state); 1452fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state); 1453fe56b9e6SYuval Mintz } 1454fe56b9e6SYuval Mintz 14558befd73cSMintz, Yuval static void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn, 14568befd73cSMintz, Yuval struct qed_ptt *p_ptt, 14578befd73cSMintz, Yuval u16 igu_sb_id, 14588befd73cSMintz, Yuval u32 pi_index, 14598befd73cSMintz, Yuval enum qed_coalescing_fsm coalescing_fsm, 14608befd73cSMintz, Yuval u8 timeset) 14618befd73cSMintz, Yuval { 14628befd73cSMintz, Yuval struct cau_pi_entry pi_entry; 14638befd73cSMintz, Yuval u32 sb_offset, pi_offset; 14648befd73cSMintz, Yuval 14658befd73cSMintz, Yuval if (IS_VF(p_hwfn->cdev)) 14668befd73cSMintz, Yuval return; 14678befd73cSMintz, Yuval 146821dd79e8STomer Tayar sb_offset = igu_sb_id * PIS_PER_SB_E4; 14698befd73cSMintz, Yuval memset(&pi_entry, 0, sizeof(struct cau_pi_entry)); 14708befd73cSMintz, Yuval 14718befd73cSMintz, Yuval SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset); 14728befd73cSMintz, Yuval if (coalescing_fsm == QED_COAL_RX_STATE_MACHINE) 14738befd73cSMintz, Yuval SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0); 14748befd73cSMintz, Yuval else 14758befd73cSMintz, Yuval SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1); 14768befd73cSMintz, Yuval 14778befd73cSMintz, Yuval pi_offset = sb_offset + pi_index; 14788befd73cSMintz, Yuval if (p_hwfn->hw_init_done) { 14798befd73cSMintz, Yuval qed_wr(p_hwfn, p_ptt, 14808befd73cSMintz, Yuval CAU_REG_PI_MEMORY + pi_offset * sizeof(u32), 14818befd73cSMintz, Yuval *((u32 *)&(pi_entry))); 14828befd73cSMintz, Yuval } else { 14838befd73cSMintz, Yuval STORE_RT_REG(p_hwfn, 14848befd73cSMintz, Yuval CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset, 14858befd73cSMintz, Yuval *((u32 *)&(pi_entry))); 14868befd73cSMintz, Yuval } 14878befd73cSMintz, Yuval } 14888befd73cSMintz, Yuval 1489fe56b9e6SYuval Mintz void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn, 1490fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1491fe56b9e6SYuval Mintz dma_addr_t sb_phys, 14921a635e48SYuval Mintz u16 igu_sb_id, u16 vf_number, u8 vf_valid) 1493fe56b9e6SYuval Mintz { 1494fe56b9e6SYuval Mintz struct cau_sb_entry sb_entry; 1495fe56b9e6SYuval Mintz 1496fe56b9e6SYuval Mintz qed_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id, 1497fe56b9e6SYuval Mintz vf_number, vf_valid); 1498fe56b9e6SYuval Mintz 1499fe56b9e6SYuval Mintz if (p_hwfn->hw_init_done) { 15000a0c5d3bSYuval Mintz /* Wide-bus, initialize via DMAE */ 15010a0c5d3bSYuval Mintz u64 phys_addr = (u64)sb_phys; 1502fe56b9e6SYuval Mintz 15030a0c5d3bSYuval Mintz qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&phys_addr, 15040a0c5d3bSYuval Mintz CAU_REG_SB_ADDR_MEMORY + 150583bf76e3SMichal Kalderon igu_sb_id * sizeof(u64), 2, NULL); 15060a0c5d3bSYuval Mintz qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&sb_entry, 15070a0c5d3bSYuval Mintz CAU_REG_SB_VAR_MEMORY + 150883bf76e3SMichal Kalderon igu_sb_id * sizeof(u64), 2, NULL); 1509fe56b9e6SYuval Mintz } else { 1510fe56b9e6SYuval Mintz /* Initialize Status Block Address */ 1511fe56b9e6SYuval Mintz STORE_RT_REG_AGG(p_hwfn, 1512fe56b9e6SYuval Mintz CAU_REG_SB_ADDR_MEMORY_RT_OFFSET + 1513fe56b9e6SYuval Mintz igu_sb_id * 2, 1514fe56b9e6SYuval Mintz sb_phys); 1515fe56b9e6SYuval Mintz 1516fe56b9e6SYuval Mintz STORE_RT_REG_AGG(p_hwfn, 1517fe56b9e6SYuval Mintz CAU_REG_SB_VAR_MEMORY_RT_OFFSET + 1518fe56b9e6SYuval Mintz igu_sb_id * 2, 1519fe56b9e6SYuval Mintz sb_entry); 1520fe56b9e6SYuval Mintz } 1521fe56b9e6SYuval Mintz 1522fe56b9e6SYuval Mintz /* Configure pi coalescing if set */ 1523fe56b9e6SYuval Mintz if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 1524b5a9ee7cSAriel Elior u8 num_tc = p_hwfn->hw_info.num_hw_tc; 1525722003acSSudarsana Reddy Kalluru u8 timeset, timer_res; 1526b5a9ee7cSAriel Elior u8 i; 1527fe56b9e6SYuval Mintz 1528722003acSSudarsana Reddy Kalluru /* timeset = (coalesce >> timer-res), timeset is 7bit wide */ 1529722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->rx_coalesce_usecs <= 0x7F) 1530722003acSSudarsana Reddy Kalluru timer_res = 0; 1531722003acSSudarsana Reddy Kalluru else if (p_hwfn->cdev->rx_coalesce_usecs <= 0xFF) 1532722003acSSudarsana Reddy Kalluru timer_res = 1; 1533722003acSSudarsana Reddy Kalluru else 1534722003acSSudarsana Reddy Kalluru timer_res = 2; 1535722003acSSudarsana Reddy Kalluru timeset = (u8)(p_hwfn->cdev->rx_coalesce_usecs >> timer_res); 1536fe56b9e6SYuval Mintz qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI, 15371a635e48SYuval Mintz QED_COAL_RX_STATE_MACHINE, timeset); 1538fe56b9e6SYuval Mintz 1539722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->tx_coalesce_usecs <= 0x7F) 1540722003acSSudarsana Reddy Kalluru timer_res = 0; 1541722003acSSudarsana Reddy Kalluru else if (p_hwfn->cdev->tx_coalesce_usecs <= 0xFF) 1542722003acSSudarsana Reddy Kalluru timer_res = 1; 1543722003acSSudarsana Reddy Kalluru else 1544722003acSSudarsana Reddy Kalluru timer_res = 2; 1545722003acSSudarsana Reddy Kalluru timeset = (u8)(p_hwfn->cdev->tx_coalesce_usecs >> timer_res); 1546fe56b9e6SYuval Mintz for (i = 0; i < num_tc; i++) { 1547fe56b9e6SYuval Mintz qed_int_cau_conf_pi(p_hwfn, p_ptt, 1548fe56b9e6SYuval Mintz igu_sb_id, TX_PI(i), 1549fe56b9e6SYuval Mintz QED_COAL_TX_STATE_MACHINE, 1550fe56b9e6SYuval Mintz timeset); 1551fe56b9e6SYuval Mintz } 1552fe56b9e6SYuval Mintz } 1553fe56b9e6SYuval Mintz } 1554fe56b9e6SYuval Mintz 1555fe56b9e6SYuval Mintz void qed_int_sb_setup(struct qed_hwfn *p_hwfn, 15561a635e48SYuval Mintz struct qed_ptt *p_ptt, struct qed_sb_info *sb_info) 1557fe56b9e6SYuval Mintz { 1558fe56b9e6SYuval Mintz /* zero status block and ack counter */ 1559fe56b9e6SYuval Mintz sb_info->sb_ack = 0; 1560fe56b9e6SYuval Mintz memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 1561fe56b9e6SYuval Mintz 15621408cc1fSYuval Mintz if (IS_PF(p_hwfn->cdev)) 1563fe56b9e6SYuval Mintz qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys, 1564fe56b9e6SYuval Mintz sb_info->igu_sb_id, 0, 0); 1565fe56b9e6SYuval Mintz } 1566fe56b9e6SYuval Mintz 156709b6b147SMintz, Yuval struct qed_igu_block *qed_get_igu_free_sb(struct qed_hwfn *p_hwfn, bool b_is_pf) 156809b6b147SMintz, Yuval { 156909b6b147SMintz, Yuval struct qed_igu_block *p_block; 157009b6b147SMintz, Yuval u16 igu_id; 157109b6b147SMintz, Yuval 157209b6b147SMintz, Yuval for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); 157309b6b147SMintz, Yuval igu_id++) { 157409b6b147SMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id]; 157509b6b147SMintz, Yuval 157609b6b147SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID) || 157709b6b147SMintz, Yuval !(p_block->status & QED_IGU_STATUS_FREE)) 157809b6b147SMintz, Yuval continue; 157909b6b147SMintz, Yuval 158009b6b147SMintz, Yuval if (!!(p_block->status & QED_IGU_STATUS_PF) == b_is_pf) 158109b6b147SMintz, Yuval return p_block; 158209b6b147SMintz, Yuval } 158309b6b147SMintz, Yuval 158409b6b147SMintz, Yuval return NULL; 158509b6b147SMintz, Yuval } 158609b6b147SMintz, Yuval 1587a333f7f3SMintz, Yuval static u16 qed_get_pf_igu_sb_id(struct qed_hwfn *p_hwfn, u16 vector_id) 1588a333f7f3SMintz, Yuval { 1589a333f7f3SMintz, Yuval struct qed_igu_block *p_block; 1590a333f7f3SMintz, Yuval u16 igu_id; 1591a333f7f3SMintz, Yuval 1592a333f7f3SMintz, Yuval for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); 1593a333f7f3SMintz, Yuval igu_id++) { 1594a333f7f3SMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id]; 1595a333f7f3SMintz, Yuval 1596a333f7f3SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID) || 1597a333f7f3SMintz, Yuval !p_block->is_pf || 1598a333f7f3SMintz, Yuval p_block->vector_number != vector_id) 1599a333f7f3SMintz, Yuval continue; 1600a333f7f3SMintz, Yuval 1601a333f7f3SMintz, Yuval return igu_id; 1602a333f7f3SMintz, Yuval } 1603a333f7f3SMintz, Yuval 1604a333f7f3SMintz, Yuval return QED_SB_INVALID_IDX; 1605a333f7f3SMintz, Yuval } 1606a333f7f3SMintz, Yuval 160750a20714SMintz, Yuval u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id) 1608fe56b9e6SYuval Mintz { 1609fe56b9e6SYuval Mintz u16 igu_sb_id; 1610fe56b9e6SYuval Mintz 1611fe56b9e6SYuval Mintz /* Assuming continuous set of IGU SBs dedicated for given PF */ 1612fe56b9e6SYuval Mintz if (sb_id == QED_SP_SB_ID) 1613fe56b9e6SYuval Mintz igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id; 16141408cc1fSYuval Mintz else if (IS_PF(p_hwfn->cdev)) 1615a333f7f3SMintz, Yuval igu_sb_id = qed_get_pf_igu_sb_id(p_hwfn, sb_id + 1); 16161408cc1fSYuval Mintz else 16171408cc1fSYuval Mintz igu_sb_id = qed_vf_get_igu_sb_id(p_hwfn, sb_id); 1618fe56b9e6SYuval Mintz 1619525ef5c0SYuval Mintz if (sb_id == QED_SP_SB_ID) 1620525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1621525ef5c0SYuval Mintz "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id); 1622525ef5c0SYuval Mintz else 1623525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1624525ef5c0SYuval Mintz "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id); 1625fe56b9e6SYuval Mintz 1626fe56b9e6SYuval Mintz return igu_sb_id; 1627fe56b9e6SYuval Mintz } 1628fe56b9e6SYuval Mintz 1629fe56b9e6SYuval Mintz int qed_int_sb_init(struct qed_hwfn *p_hwfn, 1630fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1631fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 16321a635e48SYuval Mintz void *sb_virt_addr, dma_addr_t sb_phy_addr, u16 sb_id) 1633fe56b9e6SYuval Mintz { 1634fe56b9e6SYuval Mintz sb_info->sb_virt = sb_virt_addr; 1635fe56b9e6SYuval Mintz sb_info->sb_phys = sb_phy_addr; 1636fe56b9e6SYuval Mintz 1637fe56b9e6SYuval Mintz sb_info->igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id); 1638fe56b9e6SYuval Mintz 1639fe56b9e6SYuval Mintz if (sb_id != QED_SP_SB_ID) { 164050a20714SMintz, Yuval if (IS_PF(p_hwfn->cdev)) { 164150a20714SMintz, Yuval struct qed_igu_info *p_info; 164250a20714SMintz, Yuval struct qed_igu_block *p_block; 164350a20714SMintz, Yuval 164450a20714SMintz, Yuval p_info = p_hwfn->hw_info.p_igu_info; 164550a20714SMintz, Yuval p_block = &p_info->entry[sb_info->igu_sb_id]; 164650a20714SMintz, Yuval 164750a20714SMintz, Yuval p_block->sb_info = sb_info; 164850a20714SMintz, Yuval p_block->status &= ~QED_IGU_STATUS_FREE; 164950a20714SMintz, Yuval p_info->usage.free_cnt--; 165050a20714SMintz, Yuval } else { 165150a20714SMintz, Yuval qed_vf_set_sb_info(p_hwfn, sb_id, sb_info); 165250a20714SMintz, Yuval } 1653fe56b9e6SYuval Mintz } 1654fe56b9e6SYuval Mintz 1655fe56b9e6SYuval Mintz sb_info->cdev = p_hwfn->cdev; 1656fe56b9e6SYuval Mintz 1657fe56b9e6SYuval Mintz /* The igu address will hold the absolute address that needs to be 1658fe56b9e6SYuval Mintz * written to for a specific status block 1659fe56b9e6SYuval Mintz */ 16601408cc1fSYuval Mintz if (IS_PF(p_hwfn->cdev)) { 1661fe56b9e6SYuval Mintz sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 1662fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 1663fe56b9e6SYuval Mintz (sb_info->igu_sb_id << 3); 16641408cc1fSYuval Mintz } else { 16651408cc1fSYuval Mintz sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 16661408cc1fSYuval Mintz PXP_VF_BAR0_START_IGU + 16671408cc1fSYuval Mintz ((IGU_CMD_INT_ACK_BASE + 16681408cc1fSYuval Mintz sb_info->igu_sb_id) << 3); 16691408cc1fSYuval Mintz } 1670fe56b9e6SYuval Mintz 1671fe56b9e6SYuval Mintz sb_info->flags |= QED_SB_INFO_INIT; 1672fe56b9e6SYuval Mintz 1673fe56b9e6SYuval Mintz qed_int_sb_setup(p_hwfn, p_ptt, sb_info); 1674fe56b9e6SYuval Mintz 1675fe56b9e6SYuval Mintz return 0; 1676fe56b9e6SYuval Mintz } 1677fe56b9e6SYuval Mintz 1678fe56b9e6SYuval Mintz int qed_int_sb_release(struct qed_hwfn *p_hwfn, 16791a635e48SYuval Mintz struct qed_sb_info *sb_info, u16 sb_id) 1680fe56b9e6SYuval Mintz { 168150a20714SMintz, Yuval struct qed_igu_block *p_block; 168250a20714SMintz, Yuval struct qed_igu_info *p_info; 168350a20714SMintz, Yuval 168450a20714SMintz, Yuval if (!sb_info) 168550a20714SMintz, Yuval return 0; 1686fe56b9e6SYuval Mintz 1687fe56b9e6SYuval Mintz /* zero status block and ack counter */ 1688fe56b9e6SYuval Mintz sb_info->sb_ack = 0; 1689fe56b9e6SYuval Mintz memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 1690fe56b9e6SYuval Mintz 169150a20714SMintz, Yuval if (IS_VF(p_hwfn->cdev)) { 169250a20714SMintz, Yuval qed_vf_set_sb_info(p_hwfn, sb_id, NULL); 169350a20714SMintz, Yuval return 0; 16944ac801b7SYuval Mintz } 1695fe56b9e6SYuval Mintz 169650a20714SMintz, Yuval p_info = p_hwfn->hw_info.p_igu_info; 169750a20714SMintz, Yuval p_block = &p_info->entry[sb_info->igu_sb_id]; 169850a20714SMintz, Yuval 169950a20714SMintz, Yuval /* Vector 0 is reserved to Default SB */ 170050a20714SMintz, Yuval if (!p_block->vector_number) { 170150a20714SMintz, Yuval DP_ERR(p_hwfn, "Do Not free sp sb using this function"); 170250a20714SMintz, Yuval return -EINVAL; 170350a20714SMintz, Yuval } 170450a20714SMintz, Yuval 170550a20714SMintz, Yuval /* Lose reference to client's SB info, and fix counters */ 170650a20714SMintz, Yuval p_block->sb_info = NULL; 170750a20714SMintz, Yuval p_block->status |= QED_IGU_STATUS_FREE; 170850a20714SMintz, Yuval p_info->usage.free_cnt++; 170950a20714SMintz, Yuval 1710fe56b9e6SYuval Mintz return 0; 1711fe56b9e6SYuval Mintz } 1712fe56b9e6SYuval Mintz 1713fe56b9e6SYuval Mintz static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn) 1714fe56b9e6SYuval Mintz { 1715fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb; 1716fe56b9e6SYuval Mintz 17174ac801b7SYuval Mintz if (!p_sb) 17184ac801b7SYuval Mintz return; 17194ac801b7SYuval Mintz 1720fe56b9e6SYuval Mintz if (p_sb->sb_info.sb_virt) 1721fe56b9e6SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1722fe56b9e6SYuval Mintz SB_ALIGNED_SIZE(p_hwfn), 1723fe56b9e6SYuval Mintz p_sb->sb_info.sb_virt, 1724fe56b9e6SYuval Mintz p_sb->sb_info.sb_phys); 1725fe56b9e6SYuval Mintz kfree(p_sb); 17263587cb87STomer Tayar p_hwfn->p_sp_sb = NULL; 1727fe56b9e6SYuval Mintz } 1728fe56b9e6SYuval Mintz 17291a635e48SYuval Mintz static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1730fe56b9e6SYuval Mintz { 1731fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sb; 1732fe56b9e6SYuval Mintz dma_addr_t p_phys = 0; 1733fe56b9e6SYuval Mintz void *p_virt; 1734fe56b9e6SYuval Mintz 1735fe56b9e6SYuval Mintz /* SB struct */ 173660fffb3bSYuval Mintz p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 17372591c280SJoe Perches if (!p_sb) 1738fe56b9e6SYuval Mintz return -ENOMEM; 1739fe56b9e6SYuval Mintz 1740fe56b9e6SYuval Mintz /* SB ring */ 1741fe56b9e6SYuval Mintz p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1742fe56b9e6SYuval Mintz SB_ALIGNED_SIZE(p_hwfn), 1743fe56b9e6SYuval Mintz &p_phys, GFP_KERNEL); 1744fe56b9e6SYuval Mintz if (!p_virt) { 1745fe56b9e6SYuval Mintz kfree(p_sb); 1746fe56b9e6SYuval Mintz return -ENOMEM; 1747fe56b9e6SYuval Mintz } 1748fe56b9e6SYuval Mintz 1749fe56b9e6SYuval Mintz /* Status Block setup */ 1750fe56b9e6SYuval Mintz p_hwfn->p_sp_sb = p_sb; 1751fe56b9e6SYuval Mintz qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt, 1752fe56b9e6SYuval Mintz p_phys, QED_SP_SB_ID); 1753fe56b9e6SYuval Mintz 1754fe56b9e6SYuval Mintz memset(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr)); 1755fe56b9e6SYuval Mintz 1756fe56b9e6SYuval Mintz return 0; 1757fe56b9e6SYuval Mintz } 1758fe56b9e6SYuval Mintz 1759fe56b9e6SYuval Mintz int qed_int_register_cb(struct qed_hwfn *p_hwfn, 1760fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb, 17611a635e48SYuval Mintz void *cookie, u8 *sb_idx, __le16 **p_fw_cons) 1762fe56b9e6SYuval Mintz { 1763fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 17644ac801b7SYuval Mintz int rc = -ENOMEM; 1765fe56b9e6SYuval Mintz u8 pi; 1766fe56b9e6SYuval Mintz 1767fe56b9e6SYuval Mintz /* Look for a free index */ 1768fe56b9e6SYuval Mintz for (pi = 0; pi < ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) { 17694ac801b7SYuval Mintz if (p_sp_sb->pi_info_arr[pi].comp_cb) 17704ac801b7SYuval Mintz continue; 17714ac801b7SYuval Mintz 1772fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb; 1773fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].cookie = cookie; 1774fe56b9e6SYuval Mintz *sb_idx = pi; 1775fe56b9e6SYuval Mintz *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi]; 17764ac801b7SYuval Mintz rc = 0; 1777fe56b9e6SYuval Mintz break; 1778fe56b9e6SYuval Mintz } 1779fe56b9e6SYuval Mintz 17804ac801b7SYuval Mintz return rc; 1781fe56b9e6SYuval Mintz } 1782fe56b9e6SYuval Mintz 1783fe56b9e6SYuval Mintz int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi) 1784fe56b9e6SYuval Mintz { 1785fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 1786fe56b9e6SYuval Mintz 17874ac801b7SYuval Mintz if (p_sp_sb->pi_info_arr[pi].comp_cb == NULL) 17884ac801b7SYuval Mintz return -ENOMEM; 17894ac801b7SYuval Mintz 1790fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].comp_cb = NULL; 1791fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].cookie = NULL; 1792fe56b9e6SYuval Mintz 17934ac801b7SYuval Mintz return 0; 1794fe56b9e6SYuval Mintz } 1795fe56b9e6SYuval Mintz 1796fe56b9e6SYuval Mintz u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn) 1797fe56b9e6SYuval Mintz { 1798fe56b9e6SYuval Mintz return p_hwfn->p_sp_sb->sb_info.igu_sb_id; 1799fe56b9e6SYuval Mintz } 1800fe56b9e6SYuval Mintz 1801fe56b9e6SYuval Mintz void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn, 18021a635e48SYuval Mintz struct qed_ptt *p_ptt, enum qed_int_mode int_mode) 1803fe56b9e6SYuval Mintz { 1804cc875c2eSYuval Mintz u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN; 1805fe56b9e6SYuval Mintz 1806fe56b9e6SYuval Mintz p_hwfn->cdev->int_mode = int_mode; 1807fe56b9e6SYuval Mintz switch (p_hwfn->cdev->int_mode) { 1808fe56b9e6SYuval Mintz case QED_INT_MODE_INTA: 1809fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN; 1810fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 1811fe56b9e6SYuval Mintz break; 1812fe56b9e6SYuval Mintz 1813fe56b9e6SYuval Mintz case QED_INT_MODE_MSI: 1814fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 1815fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 1816fe56b9e6SYuval Mintz break; 1817fe56b9e6SYuval Mintz 1818fe56b9e6SYuval Mintz case QED_INT_MODE_MSIX: 1819fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 1820fe56b9e6SYuval Mintz break; 1821fe56b9e6SYuval Mintz case QED_INT_MODE_POLL: 1822fe56b9e6SYuval Mintz break; 1823fe56b9e6SYuval Mintz } 1824fe56b9e6SYuval Mintz 1825fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf); 1826fe56b9e6SYuval Mintz } 1827fe56b9e6SYuval Mintz 1828979cead3SMintz, Yuval static void qed_int_igu_enable_attn(struct qed_hwfn *p_hwfn, 1829979cead3SMintz, Yuval struct qed_ptt *p_ptt) 1830fe56b9e6SYuval Mintz { 1831fe56b9e6SYuval Mintz 18320d956e8aSYuval Mintz /* Configure AEU signal change to produce attentions */ 18330d956e8aSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0); 1834cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff); 1835cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff); 18360d956e8aSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff); 1837cc875c2eSYuval Mintz 1838cc875c2eSYuval Mintz /* Unmask AEU signals toward IGU */ 1839cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff); 1840979cead3SMintz, Yuval } 1841979cead3SMintz, Yuval 1842979cead3SMintz, Yuval int 1843979cead3SMintz, Yuval qed_int_igu_enable(struct qed_hwfn *p_hwfn, 1844979cead3SMintz, Yuval struct qed_ptt *p_ptt, enum qed_int_mode int_mode) 1845979cead3SMintz, Yuval { 1846979cead3SMintz, Yuval int rc = 0; 1847979cead3SMintz, Yuval 1848979cead3SMintz, Yuval qed_int_igu_enable_attn(p_hwfn, p_ptt); 1849979cead3SMintz, Yuval 18508f16bc97SSudarsana Kalluru if ((int_mode != QED_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) { 18518f16bc97SSudarsana Kalluru rc = qed_slowpath_irq_req(p_hwfn); 18521a635e48SYuval Mintz if (rc) { 18538f16bc97SSudarsana Kalluru DP_NOTICE(p_hwfn, "Slowpath IRQ request failed\n"); 18548f16bc97SSudarsana Kalluru return -EINVAL; 18558f16bc97SSudarsana Kalluru } 18568f16bc97SSudarsana Kalluru p_hwfn->b_int_requested = true; 18578f16bc97SSudarsana Kalluru } 18588f16bc97SSudarsana Kalluru /* Enable interrupt Generation */ 18598f16bc97SSudarsana Kalluru qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode); 18608f16bc97SSudarsana Kalluru p_hwfn->b_int_enabled = 1; 18618f16bc97SSudarsana Kalluru 18628f16bc97SSudarsana Kalluru return rc; 1863fe56b9e6SYuval Mintz } 1864fe56b9e6SYuval Mintz 18651a635e48SYuval Mintz void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1866fe56b9e6SYuval Mintz { 1867fe56b9e6SYuval Mintz p_hwfn->b_int_enabled = 0; 1868fe56b9e6SYuval Mintz 18691408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 18701408cc1fSYuval Mintz return; 18711408cc1fSYuval Mintz 1872fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0); 1873fe56b9e6SYuval Mintz } 1874fe56b9e6SYuval Mintz 1875fe56b9e6SYuval Mintz #define IGU_CLEANUP_SLEEP_LENGTH (1000) 1876b2b897ebSYuval Mintz static void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn, 1877fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1878d031548eSMintz, Yuval u16 igu_sb_id, 1879d031548eSMintz, Yuval bool cleanup_set, u16 opaque_fid) 1880fe56b9e6SYuval Mintz { 1881b2b897ebSYuval Mintz u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0; 1882d031548eSMintz, Yuval u32 pxp_addr = IGU_CMD_INT_ACK_BASE + igu_sb_id; 1883fe56b9e6SYuval Mintz u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH; 1884fe56b9e6SYuval Mintz 1885fe56b9e6SYuval Mintz /* Set the data field */ 1886fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0); 1887fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, 0); 1888fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET); 1889fe56b9e6SYuval Mintz 1890fe56b9e6SYuval Mintz /* Set the control register */ 1891fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr); 1892fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid); 1893fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR); 1894fe56b9e6SYuval Mintz 1895fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data); 1896fe56b9e6SYuval Mintz 1897fe56b9e6SYuval Mintz barrier(); 1898fe56b9e6SYuval Mintz 1899fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl); 1900fe56b9e6SYuval Mintz 1901fe56b9e6SYuval Mintz /* calculate where to read the status bit from */ 1902d031548eSMintz, Yuval sb_bit = 1 << (igu_sb_id % 32); 1903d031548eSMintz, Yuval sb_bit_addr = igu_sb_id / 32 * sizeof(u32); 1904fe56b9e6SYuval Mintz 1905fe56b9e6SYuval Mintz sb_bit_addr += IGU_REG_CLEANUP_STATUS_0; 1906fe56b9e6SYuval Mintz 1907fe56b9e6SYuval Mintz /* Now wait for the command to complete */ 1908fe56b9e6SYuval Mintz do { 1909fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, sb_bit_addr); 1910fe56b9e6SYuval Mintz 1911fe56b9e6SYuval Mintz if ((val & sb_bit) == (cleanup_set ? sb_bit : 0)) 1912fe56b9e6SYuval Mintz break; 1913fe56b9e6SYuval Mintz 1914fe56b9e6SYuval Mintz usleep_range(5000, 10000); 1915fe56b9e6SYuval Mintz } while (--sleep_cnt); 1916fe56b9e6SYuval Mintz 1917fe56b9e6SYuval Mintz if (!sleep_cnt) 1918fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 1919fe56b9e6SYuval Mintz "Timeout waiting for clear status 0x%08x [for sb %d]\n", 1920d031548eSMintz, Yuval val, igu_sb_id); 1921fe56b9e6SYuval Mintz } 1922fe56b9e6SYuval Mintz 1923fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn, 1924fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1925d031548eSMintz, Yuval u16 igu_sb_id, u16 opaque, bool b_set) 1926fe56b9e6SYuval Mintz { 19271ac72433SMintz, Yuval struct qed_igu_block *p_block; 1928b2b897ebSYuval Mintz int pi, i; 1929fe56b9e6SYuval Mintz 19301ac72433SMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id]; 19311ac72433SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 19321ac72433SMintz, Yuval "Cleaning SB [%04x]: func_id= %d is_pf = %d vector_num = 0x%0x\n", 19331ac72433SMintz, Yuval igu_sb_id, 19341ac72433SMintz, Yuval p_block->function_id, 19351ac72433SMintz, Yuval p_block->is_pf, p_block->vector_number); 19361ac72433SMintz, Yuval 1937fe56b9e6SYuval Mintz /* Set */ 1938fe56b9e6SYuval Mintz if (b_set) 1939d031548eSMintz, Yuval qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 1, opaque); 1940fe56b9e6SYuval Mintz 1941fe56b9e6SYuval Mintz /* Clear */ 1942d031548eSMintz, Yuval qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 0, opaque); 1943fe56b9e6SYuval Mintz 1944b2b897ebSYuval Mintz /* Wait for the IGU SB to cleanup */ 1945b2b897ebSYuval Mintz for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) { 1946b2b897ebSYuval Mintz u32 val; 1947b2b897ebSYuval Mintz 1948b2b897ebSYuval Mintz val = qed_rd(p_hwfn, p_ptt, 1949d031548eSMintz, Yuval IGU_REG_WRITE_DONE_PENDING + 1950d031548eSMintz, Yuval ((igu_sb_id / 32) * 4)); 1951d031548eSMintz, Yuval if (val & BIT((igu_sb_id % 32))) 1952b2b897ebSYuval Mintz usleep_range(10, 20); 1953b2b897ebSYuval Mintz else 1954b2b897ebSYuval Mintz break; 1955b2b897ebSYuval Mintz } 1956b2b897ebSYuval Mintz if (i == IGU_CLEANUP_SLEEP_LENGTH) 1957b2b897ebSYuval Mintz DP_NOTICE(p_hwfn, 1958b2b897ebSYuval Mintz "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n", 1959d031548eSMintz, Yuval igu_sb_id); 1960b2b897ebSYuval Mintz 1961fe56b9e6SYuval Mintz /* Clear the CAU for the SB */ 1962fe56b9e6SYuval Mintz for (pi = 0; pi < 12; pi++) 1963fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 1964d031548eSMintz, Yuval CAU_REG_PI_MEMORY + (igu_sb_id * 12 + pi) * 4, 0); 1965fe56b9e6SYuval Mintz } 1966fe56b9e6SYuval Mintz 1967fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn, 1968fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1969b2b897ebSYuval Mintz bool b_set, bool b_slowpath) 1970fe56b9e6SYuval Mintz { 19711ac72433SMintz, Yuval struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info; 19721ac72433SMintz, Yuval struct qed_igu_block *p_block; 19731ac72433SMintz, Yuval u16 igu_sb_id = 0; 19741ac72433SMintz, Yuval u32 val = 0; 1975fe56b9e6SYuval Mintz 1976fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION); 1977fe56b9e6SYuval Mintz val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN; 1978fe56b9e6SYuval Mintz val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN; 1979fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val); 1980fe56b9e6SYuval Mintz 19811ac72433SMintz, Yuval for (igu_sb_id = 0; 19821ac72433SMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 19831ac72433SMintz, Yuval p_block = &p_info->entry[igu_sb_id]; 1984fe56b9e6SYuval Mintz 19851ac72433SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID) || 19861ac72433SMintz, Yuval !p_block->is_pf || 19871ac72433SMintz, Yuval (p_block->status & QED_IGU_STATUS_DSB)) 19881ac72433SMintz, Yuval continue; 19891ac72433SMintz, Yuval 1990d031548eSMintz, Yuval qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, igu_sb_id, 1991fe56b9e6SYuval Mintz p_hwfn->hw_info.opaque_fid, 1992fe56b9e6SYuval Mintz b_set); 19931ac72433SMintz, Yuval } 1994fe56b9e6SYuval Mintz 19951ac72433SMintz, Yuval if (b_slowpath) 19961ac72433SMintz, Yuval qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, 19971ac72433SMintz, Yuval p_info->igu_dsb_id, 19981ac72433SMintz, Yuval p_hwfn->hw_info.opaque_fid, 19991ac72433SMintz, Yuval b_set); 2000fe56b9e6SYuval Mintz } 2001fe56b9e6SYuval Mintz 2002ebbdcc66SMintz, Yuval int qed_int_igu_reset_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2003ebbdcc66SMintz, Yuval { 2004ebbdcc66SMintz, Yuval struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info; 2005ebbdcc66SMintz, Yuval struct qed_igu_block *p_block; 2006ebbdcc66SMintz, Yuval int pf_sbs, vf_sbs; 2007ebbdcc66SMintz, Yuval u16 igu_sb_id; 2008ebbdcc66SMintz, Yuval u32 val, rval; 2009ebbdcc66SMintz, Yuval 2010ebbdcc66SMintz, Yuval if (!RESC_NUM(p_hwfn, QED_SB)) { 2011ebbdcc66SMintz, Yuval p_info->b_allow_pf_vf_change = false; 2012ebbdcc66SMintz, Yuval } else { 2013ebbdcc66SMintz, Yuval /* Use the numbers the MFW have provided - 2014ebbdcc66SMintz, Yuval * don't forget MFW accounts for the default SB as well. 2015ebbdcc66SMintz, Yuval */ 2016ebbdcc66SMintz, Yuval p_info->b_allow_pf_vf_change = true; 2017ebbdcc66SMintz, Yuval 2018ebbdcc66SMintz, Yuval if (p_info->usage.cnt != RESC_NUM(p_hwfn, QED_SB) - 1) { 2019ebbdcc66SMintz, Yuval DP_INFO(p_hwfn, 2020ebbdcc66SMintz, Yuval "MFW notifies of 0x%04x PF SBs; IGU indicates of only 0x%04x\n", 2021ebbdcc66SMintz, Yuval RESC_NUM(p_hwfn, QED_SB) - 1, 2022ebbdcc66SMintz, Yuval p_info->usage.cnt); 2023ebbdcc66SMintz, Yuval p_info->usage.cnt = RESC_NUM(p_hwfn, QED_SB) - 1; 2024ebbdcc66SMintz, Yuval } 2025ebbdcc66SMintz, Yuval 2026ebbdcc66SMintz, Yuval if (IS_PF_SRIOV(p_hwfn)) { 2027ebbdcc66SMintz, Yuval u16 vfs = p_hwfn->cdev->p_iov_info->total_vfs; 2028ebbdcc66SMintz, Yuval 2029ebbdcc66SMintz, Yuval if (vfs != p_info->usage.iov_cnt) 2030ebbdcc66SMintz, Yuval DP_VERBOSE(p_hwfn, 2031ebbdcc66SMintz, Yuval NETIF_MSG_INTR, 2032ebbdcc66SMintz, Yuval "0x%04x VF SBs in IGU CAM != PCI configuration 0x%04x\n", 2033ebbdcc66SMintz, Yuval p_info->usage.iov_cnt, vfs); 2034ebbdcc66SMintz, Yuval 2035ebbdcc66SMintz, Yuval /* At this point we know how many SBs we have totally 2036ebbdcc66SMintz, Yuval * in IGU + number of PF SBs. So we can validate that 2037ebbdcc66SMintz, Yuval * we'd have sufficient for VF. 2038ebbdcc66SMintz, Yuval */ 2039ebbdcc66SMintz, Yuval if (vfs > p_info->usage.free_cnt + 2040ebbdcc66SMintz, Yuval p_info->usage.free_cnt_iov - p_info->usage.cnt) { 2041ebbdcc66SMintz, Yuval DP_NOTICE(p_hwfn, 2042ebbdcc66SMintz, Yuval "Not enough SBs for VFs - 0x%04x SBs, from which %04x PFs and %04x are required\n", 2043ebbdcc66SMintz, Yuval p_info->usage.free_cnt + 2044ebbdcc66SMintz, Yuval p_info->usage.free_cnt_iov, 2045ebbdcc66SMintz, Yuval p_info->usage.cnt, vfs); 2046ebbdcc66SMintz, Yuval return -EINVAL; 2047ebbdcc66SMintz, Yuval } 2048ebbdcc66SMintz, Yuval 2049ebbdcc66SMintz, Yuval /* Currently cap the number of VFs SBs by the 2050ebbdcc66SMintz, Yuval * number of VFs. 2051ebbdcc66SMintz, Yuval */ 2052ebbdcc66SMintz, Yuval p_info->usage.iov_cnt = vfs; 2053ebbdcc66SMintz, Yuval } 2054ebbdcc66SMintz, Yuval } 2055ebbdcc66SMintz, Yuval 2056ebbdcc66SMintz, Yuval /* Mark all SBs as free, now in the right PF/VFs division */ 2057ebbdcc66SMintz, Yuval p_info->usage.free_cnt = p_info->usage.cnt; 2058ebbdcc66SMintz, Yuval p_info->usage.free_cnt_iov = p_info->usage.iov_cnt; 2059ebbdcc66SMintz, Yuval p_info->usage.orig = p_info->usage.cnt; 2060ebbdcc66SMintz, Yuval p_info->usage.iov_orig = p_info->usage.iov_cnt; 2061ebbdcc66SMintz, Yuval 2062ebbdcc66SMintz, Yuval /* We now proceed to re-configure the IGU cam to reflect the initial 2063ebbdcc66SMintz, Yuval * configuration. We can start with the Default SB. 2064ebbdcc66SMintz, Yuval */ 2065ebbdcc66SMintz, Yuval pf_sbs = p_info->usage.cnt; 2066ebbdcc66SMintz, Yuval vf_sbs = p_info->usage.iov_cnt; 2067ebbdcc66SMintz, Yuval 2068ebbdcc66SMintz, Yuval for (igu_sb_id = p_info->igu_dsb_id; 2069ebbdcc66SMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 2070ebbdcc66SMintz, Yuval p_block = &p_info->entry[igu_sb_id]; 2071ebbdcc66SMintz, Yuval val = 0; 2072ebbdcc66SMintz, Yuval 2073ebbdcc66SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID)) 2074ebbdcc66SMintz, Yuval continue; 2075ebbdcc66SMintz, Yuval 2076ebbdcc66SMintz, Yuval if (p_block->status & QED_IGU_STATUS_DSB) { 2077ebbdcc66SMintz, Yuval p_block->function_id = p_hwfn->rel_pf_id; 2078ebbdcc66SMintz, Yuval p_block->is_pf = 1; 2079ebbdcc66SMintz, Yuval p_block->vector_number = 0; 2080ebbdcc66SMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2081ebbdcc66SMintz, Yuval QED_IGU_STATUS_PF | 2082ebbdcc66SMintz, Yuval QED_IGU_STATUS_DSB; 2083ebbdcc66SMintz, Yuval } else if (pf_sbs) { 2084ebbdcc66SMintz, Yuval pf_sbs--; 2085ebbdcc66SMintz, Yuval p_block->function_id = p_hwfn->rel_pf_id; 2086ebbdcc66SMintz, Yuval p_block->is_pf = 1; 2087ebbdcc66SMintz, Yuval p_block->vector_number = p_info->usage.cnt - pf_sbs; 2088ebbdcc66SMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2089ebbdcc66SMintz, Yuval QED_IGU_STATUS_PF | 2090ebbdcc66SMintz, Yuval QED_IGU_STATUS_FREE; 2091ebbdcc66SMintz, Yuval } else if (vf_sbs) { 2092ebbdcc66SMintz, Yuval p_block->function_id = 2093ebbdcc66SMintz, Yuval p_hwfn->cdev->p_iov_info->first_vf_in_pf + 2094ebbdcc66SMintz, Yuval p_info->usage.iov_cnt - vf_sbs; 2095ebbdcc66SMintz, Yuval p_block->is_pf = 0; 2096ebbdcc66SMintz, Yuval p_block->vector_number = 0; 2097ebbdcc66SMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2098ebbdcc66SMintz, Yuval QED_IGU_STATUS_FREE; 2099ebbdcc66SMintz, Yuval vf_sbs--; 2100ebbdcc66SMintz, Yuval } else { 2101ebbdcc66SMintz, Yuval p_block->function_id = 0; 2102ebbdcc66SMintz, Yuval p_block->is_pf = 0; 2103ebbdcc66SMintz, Yuval p_block->vector_number = 0; 2104ebbdcc66SMintz, Yuval } 2105ebbdcc66SMintz, Yuval 2106ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER, 2107ebbdcc66SMintz, Yuval p_block->function_id); 2108ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf); 2109ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER, 2110ebbdcc66SMintz, Yuval p_block->vector_number); 2111ebbdcc66SMintz, Yuval 2112ebbdcc66SMintz, Yuval /* VF entries would be enabled when VF is initializaed */ 2113ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf); 2114ebbdcc66SMintz, Yuval 2115ebbdcc66SMintz, Yuval rval = qed_rd(p_hwfn, p_ptt, 2116ebbdcc66SMintz, Yuval IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id); 2117ebbdcc66SMintz, Yuval 2118ebbdcc66SMintz, Yuval if (rval != val) { 2119ebbdcc66SMintz, Yuval qed_wr(p_hwfn, p_ptt, 2120ebbdcc66SMintz, Yuval IGU_REG_MAPPING_MEMORY + 2121ebbdcc66SMintz, Yuval sizeof(u32) * igu_sb_id, val); 2122ebbdcc66SMintz, Yuval 2123ebbdcc66SMintz, Yuval DP_VERBOSE(p_hwfn, 2124ebbdcc66SMintz, Yuval NETIF_MSG_INTR, 2125ebbdcc66SMintz, Yuval "IGU reset: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x [%08x -> %08x]\n", 2126ebbdcc66SMintz, Yuval igu_sb_id, 2127ebbdcc66SMintz, Yuval p_block->function_id, 2128ebbdcc66SMintz, Yuval p_block->is_pf, 2129ebbdcc66SMintz, Yuval p_block->vector_number, rval, val); 2130ebbdcc66SMintz, Yuval } 2131ebbdcc66SMintz, Yuval } 2132ebbdcc66SMintz, Yuval 2133ebbdcc66SMintz, Yuval return 0; 2134ebbdcc66SMintz, Yuval } 2135ebbdcc66SMintz, Yuval 2136d749dd0dSMintz, Yuval static void qed_int_igu_read_cam_block(struct qed_hwfn *p_hwfn, 2137d749dd0dSMintz, Yuval struct qed_ptt *p_ptt, u16 igu_sb_id) 21384ac801b7SYuval Mintz { 21394ac801b7SYuval Mintz u32 val = qed_rd(p_hwfn, p_ptt, 2140d749dd0dSMintz, Yuval IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id); 21414ac801b7SYuval Mintz struct qed_igu_block *p_block; 21424ac801b7SYuval Mintz 2143d749dd0dSMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id]; 21444ac801b7SYuval Mintz 21454ac801b7SYuval Mintz /* Fill the block information */ 2146d749dd0dSMintz, Yuval p_block->function_id = GET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER); 21474ac801b7SYuval Mintz p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID); 2148d749dd0dSMintz, Yuval p_block->vector_number = GET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER); 21491ac72433SMintz, Yuval p_block->igu_sb_id = igu_sb_id; 21504ac801b7SYuval Mintz } 21514ac801b7SYuval Mintz 21521a635e48SYuval Mintz int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2153fe56b9e6SYuval Mintz { 2154fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 2155d749dd0dSMintz, Yuval struct qed_igu_block *p_block; 2156d749dd0dSMintz, Yuval u32 min_vf = 0, max_vf = 0; 2157d749dd0dSMintz, Yuval u16 igu_sb_id; 2158fe56b9e6SYuval Mintz 215960fffb3bSYuval Mintz p_hwfn->hw_info.p_igu_info = kzalloc(sizeof(*p_igu_info), GFP_KERNEL); 2160fe56b9e6SYuval Mintz if (!p_hwfn->hw_info.p_igu_info) 2161fe56b9e6SYuval Mintz return -ENOMEM; 2162fe56b9e6SYuval Mintz 2163fe56b9e6SYuval Mintz p_igu_info = p_hwfn->hw_info.p_igu_info; 2164fe56b9e6SYuval Mintz 2165d749dd0dSMintz, Yuval /* Distinguish between existent and non-existent default SB */ 2166d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id = QED_SB_INVALID_IDX; 2167d749dd0dSMintz, Yuval 2168d749dd0dSMintz, Yuval /* Find the range of VF ids whose SB belong to this PF */ 21691408cc1fSYuval Mintz if (p_hwfn->cdev->p_iov_info) { 21701408cc1fSYuval Mintz struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info; 21711408cc1fSYuval Mintz 21721408cc1fSYuval Mintz min_vf = p_iov->first_vf_in_pf; 21731408cc1fSYuval Mintz max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs; 21741408cc1fSYuval Mintz } 21751408cc1fSYuval Mintz 2176d749dd0dSMintz, Yuval for (igu_sb_id = 0; 2177d749dd0dSMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 2178d749dd0dSMintz, Yuval /* Read current entry; Notice it might not belong to this PF */ 2179d749dd0dSMintz, Yuval qed_int_igu_read_cam_block(p_hwfn, p_ptt, igu_sb_id); 2180d749dd0dSMintz, Yuval p_block = &p_igu_info->entry[igu_sb_id]; 2181fe56b9e6SYuval Mintz 2182d749dd0dSMintz, Yuval if ((p_block->is_pf) && 2183d749dd0dSMintz, Yuval (p_block->function_id == p_hwfn->rel_pf_id)) { 2184d749dd0dSMintz, Yuval p_block->status = QED_IGU_STATUS_PF | 2185d749dd0dSMintz, Yuval QED_IGU_STATUS_VALID | 2186d749dd0dSMintz, Yuval QED_IGU_STATUS_FREE; 2187fe56b9e6SYuval Mintz 21881ac72433SMintz, Yuval if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX) 2189726fdbe9SMintz, Yuval p_igu_info->usage.cnt++; 2190d749dd0dSMintz, Yuval } else if (!(p_block->is_pf) && 2191d749dd0dSMintz, Yuval (p_block->function_id >= min_vf) && 2192d749dd0dSMintz, Yuval (p_block->function_id < max_vf)) { 21931408cc1fSYuval Mintz /* Available for VFs of this PF */ 2194d749dd0dSMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2195d749dd0dSMintz, Yuval QED_IGU_STATUS_FREE; 2196d749dd0dSMintz, Yuval 21971ac72433SMintz, Yuval if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX) 2198726fdbe9SMintz, Yuval p_igu_info->usage.iov_cnt++; 21991408cc1fSYuval Mintz } 22005a1f965aSMintz, Yuval 2201d749dd0dSMintz, Yuval /* Mark the First entry belonging to the PF or its VFs 2202ebbdcc66SMintz, Yuval * as the default SB [we'll reset IGU prior to first usage]. 22035a1f965aSMintz, Yuval */ 2204d749dd0dSMintz, Yuval if ((p_block->status & QED_IGU_STATUS_VALID) && 2205d749dd0dSMintz, Yuval (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX)) { 2206d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id = igu_sb_id; 2207d749dd0dSMintz, Yuval p_block->status |= QED_IGU_STATUS_DSB; 2208d749dd0dSMintz, Yuval } 22095a1f965aSMintz, Yuval 2210d749dd0dSMintz, Yuval /* limit number of prints by having each PF print only its 2211d749dd0dSMintz, Yuval * entries with the exception of PF0 which would print 2212d749dd0dSMintz, Yuval * everything. 2213d749dd0dSMintz, Yuval */ 2214d749dd0dSMintz, Yuval if ((p_block->status & QED_IGU_STATUS_VALID) || 2215d749dd0dSMintz, Yuval (p_hwfn->abs_pf_id == 0)) { 2216d749dd0dSMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2217d749dd0dSMintz, Yuval "IGU_BLOCK: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n", 2218d749dd0dSMintz, Yuval igu_sb_id, p_block->function_id, 2219d749dd0dSMintz, Yuval p_block->is_pf, p_block->vector_number); 2220d749dd0dSMintz, Yuval } 2221d749dd0dSMintz, Yuval } 2222d749dd0dSMintz, Yuval 2223d749dd0dSMintz, Yuval if (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX) { 22245a1f965aSMintz, Yuval DP_NOTICE(p_hwfn, 2225d749dd0dSMintz, Yuval "IGU CAM returned invalid values igu_dsb_id=0x%x\n", 2226d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id); 22275a1f965aSMintz, Yuval return -EINVAL; 22285a1f965aSMintz, Yuval } 2229d749dd0dSMintz, Yuval 2230d749dd0dSMintz, Yuval /* All non default SB are considered free at this point */ 2231726fdbe9SMintz, Yuval p_igu_info->usage.free_cnt = p_igu_info->usage.cnt; 2232726fdbe9SMintz, Yuval p_igu_info->usage.free_cnt_iov = p_igu_info->usage.iov_cnt; 2233fe56b9e6SYuval Mintz 2234d749dd0dSMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2235ebbdcc66SMintz, Yuval "igu_dsb_id=0x%x, num Free SBs - PF: %04x VF: %04x [might change after resource allocation]\n", 2236d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id, 2237726fdbe9SMintz, Yuval p_igu_info->usage.cnt, p_igu_info->usage.iov_cnt); 2238fe56b9e6SYuval Mintz 2239fe56b9e6SYuval Mintz return 0; 2240fe56b9e6SYuval Mintz } 2241fe56b9e6SYuval Mintz 2242fe56b9e6SYuval Mintz /** 2243fe56b9e6SYuval Mintz * @brief Initialize igu runtime registers 2244fe56b9e6SYuval Mintz * 2245fe56b9e6SYuval Mintz * @param p_hwfn 2246fe56b9e6SYuval Mintz */ 2247fe56b9e6SYuval Mintz void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn) 2248fe56b9e6SYuval Mintz { 22491a635e48SYuval Mintz u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN; 2250fe56b9e6SYuval Mintz 2251fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf); 2252fe56b9e6SYuval Mintz } 2253fe56b9e6SYuval Mintz 2254fe56b9e6SYuval Mintz u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn) 2255fe56b9e6SYuval Mintz { 2256fe56b9e6SYuval Mintz u32 lsb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - 2257fe56b9e6SYuval Mintz IGU_CMD_INT_ACK_BASE; 2258fe56b9e6SYuval Mintz u32 msb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - 2259fe56b9e6SYuval Mintz IGU_CMD_INT_ACK_BASE; 22601a635e48SYuval Mintz u32 intr_status_hi = 0, intr_status_lo = 0; 22611a635e48SYuval Mintz u64 intr_status = 0; 2262fe56b9e6SYuval Mintz 2263fe56b9e6SYuval Mintz intr_status_lo = REG_RD(p_hwfn, 2264fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 2265fe56b9e6SYuval Mintz lsb_igu_cmd_addr * 8); 2266fe56b9e6SYuval Mintz intr_status_hi = REG_RD(p_hwfn, 2267fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 2268fe56b9e6SYuval Mintz msb_igu_cmd_addr * 8); 2269fe56b9e6SYuval Mintz intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo; 2270fe56b9e6SYuval Mintz 2271fe56b9e6SYuval Mintz return intr_status; 2272fe56b9e6SYuval Mintz } 2273fe56b9e6SYuval Mintz 2274fe56b9e6SYuval Mintz static void qed_int_sp_dpc_setup(struct qed_hwfn *p_hwfn) 2275fe56b9e6SYuval Mintz { 2276fe56b9e6SYuval Mintz tasklet_init(p_hwfn->sp_dpc, 2277fe56b9e6SYuval Mintz qed_int_sp_dpc, (unsigned long)p_hwfn); 2278fe56b9e6SYuval Mintz p_hwfn->b_sp_dpc_enabled = true; 2279fe56b9e6SYuval Mintz } 2280fe56b9e6SYuval Mintz 2281fe56b9e6SYuval Mintz static int qed_int_sp_dpc_alloc(struct qed_hwfn *p_hwfn) 2282fe56b9e6SYuval Mintz { 228360fffb3bSYuval Mintz p_hwfn->sp_dpc = kmalloc(sizeof(*p_hwfn->sp_dpc), GFP_KERNEL); 2284fe56b9e6SYuval Mintz if (!p_hwfn->sp_dpc) 2285fe56b9e6SYuval Mintz return -ENOMEM; 2286fe56b9e6SYuval Mintz 2287fe56b9e6SYuval Mintz return 0; 2288fe56b9e6SYuval Mintz } 2289fe56b9e6SYuval Mintz 2290fe56b9e6SYuval Mintz static void qed_int_sp_dpc_free(struct qed_hwfn *p_hwfn) 2291fe56b9e6SYuval Mintz { 2292fe56b9e6SYuval Mintz kfree(p_hwfn->sp_dpc); 22933587cb87STomer Tayar p_hwfn->sp_dpc = NULL; 2294fe56b9e6SYuval Mintz } 2295fe56b9e6SYuval Mintz 22961a635e48SYuval Mintz int qed_int_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2297fe56b9e6SYuval Mintz { 2298fe56b9e6SYuval Mintz int rc = 0; 2299fe56b9e6SYuval Mintz 2300fe56b9e6SYuval Mintz rc = qed_int_sp_dpc_alloc(p_hwfn); 230183aeb933SYuval Mintz if (rc) 23022591c280SJoe Perches return rc; 23032591c280SJoe Perches 23042591c280SJoe Perches rc = qed_int_sp_sb_alloc(p_hwfn, p_ptt); 23052591c280SJoe Perches if (rc) 23062591c280SJoe Perches return rc; 23072591c280SJoe Perches 23082591c280SJoe Perches rc = qed_int_sb_attn_alloc(p_hwfn, p_ptt); 230983aeb933SYuval Mintz 2310fe56b9e6SYuval Mintz return rc; 2311fe56b9e6SYuval Mintz } 2312fe56b9e6SYuval Mintz 2313fe56b9e6SYuval Mintz void qed_int_free(struct qed_hwfn *p_hwfn) 2314fe56b9e6SYuval Mintz { 2315fe56b9e6SYuval Mintz qed_int_sp_sb_free(p_hwfn); 2316cc875c2eSYuval Mintz qed_int_sb_attn_free(p_hwfn); 2317fe56b9e6SYuval Mintz qed_int_sp_dpc_free(p_hwfn); 2318fe56b9e6SYuval Mintz } 2319fe56b9e6SYuval Mintz 23201a635e48SYuval Mintz void qed_int_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2321fe56b9e6SYuval Mintz { 23220d956e8aSYuval Mintz qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info); 23230d956e8aSYuval Mintz qed_int_sb_attn_setup(p_hwfn, p_ptt); 2324fe56b9e6SYuval Mintz qed_int_sp_dpc_setup(p_hwfn); 2325fe56b9e6SYuval Mintz } 2326fe56b9e6SYuval Mintz 23274ac801b7SYuval Mintz void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn, 23284ac801b7SYuval Mintz struct qed_sb_cnt_info *p_sb_cnt_info) 2329fe56b9e6SYuval Mintz { 2330fe56b9e6SYuval Mintz struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info; 2331fe56b9e6SYuval Mintz 23324ac801b7SYuval Mintz if (!info || !p_sb_cnt_info) 23334ac801b7SYuval Mintz return; 2334fe56b9e6SYuval Mintz 2335726fdbe9SMintz, Yuval memcpy(p_sb_cnt_info, &info->usage, sizeof(*p_sb_cnt_info)); 2336fe56b9e6SYuval Mintz } 23378f16bc97SSudarsana Kalluru 23388f16bc97SSudarsana Kalluru void qed_int_disable_post_isr_release(struct qed_dev *cdev) 23398f16bc97SSudarsana Kalluru { 23408f16bc97SSudarsana Kalluru int i; 23418f16bc97SSudarsana Kalluru 23428f16bc97SSudarsana Kalluru for_each_hwfn(cdev, i) 23438f16bc97SSudarsana Kalluru cdev->hwfns[i].b_int_requested = false; 23448f16bc97SSudarsana Kalluru } 2345722003acSSudarsana Reddy Kalluru 2346936c7ba4SIgor Russkikh void qed_int_attn_clr_enable(struct qed_dev *cdev, bool clr_enable) 2347936c7ba4SIgor Russkikh { 2348936c7ba4SIgor Russkikh cdev->attn_clr_en = clr_enable; 2349936c7ba4SIgor Russkikh } 2350936c7ba4SIgor Russkikh 2351722003acSSudarsana Reddy Kalluru int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2352722003acSSudarsana Reddy Kalluru u8 timer_res, u16 sb_id, bool tx) 2353722003acSSudarsana Reddy Kalluru { 2354722003acSSudarsana Reddy Kalluru struct cau_sb_entry sb_entry; 2355722003acSSudarsana Reddy Kalluru int rc; 2356722003acSSudarsana Reddy Kalluru 2357722003acSSudarsana Reddy Kalluru if (!p_hwfn->hw_init_done) { 2358722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "hardware not initialized yet\n"); 2359722003acSSudarsana Reddy Kalluru return -EINVAL; 2360722003acSSudarsana Reddy Kalluru } 2361722003acSSudarsana Reddy Kalluru 2362722003acSSudarsana Reddy Kalluru rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY + 2363722003acSSudarsana Reddy Kalluru sb_id * sizeof(u64), 236483bf76e3SMichal Kalderon (u64)(uintptr_t)&sb_entry, 2, NULL); 2365722003acSSudarsana Reddy Kalluru if (rc) { 2366722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc); 2367722003acSSudarsana Reddy Kalluru return rc; 2368722003acSSudarsana Reddy Kalluru } 2369722003acSSudarsana Reddy Kalluru 2370722003acSSudarsana Reddy Kalluru if (tx) 2371722003acSSudarsana Reddy Kalluru SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 2372722003acSSudarsana Reddy Kalluru else 2373722003acSSudarsana Reddy Kalluru SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 2374722003acSSudarsana Reddy Kalluru 2375722003acSSudarsana Reddy Kalluru rc = qed_dmae_host2grc(p_hwfn, p_ptt, 2376722003acSSudarsana Reddy Kalluru (u64)(uintptr_t)&sb_entry, 2377722003acSSudarsana Reddy Kalluru CAU_REG_SB_VAR_MEMORY + 237883bf76e3SMichal Kalderon sb_id * sizeof(u64), 2, NULL); 2379722003acSSudarsana Reddy Kalluru if (rc) { 2380722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc); 2381722003acSSudarsana Reddy Kalluru return rc; 2382722003acSSudarsana Reddy Kalluru } 2383722003acSSudarsana Reddy Kalluru 2384722003acSSudarsana Reddy Kalluru return rc; 2385722003acSSudarsana Reddy Kalluru } 2386