1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #include <linux/types.h> 34fe56b9e6SYuval Mintz #include <asm/byteorder.h> 35fe56b9e6SYuval Mintz #include <linux/io.h> 36fe56b9e6SYuval Mintz #include <linux/bitops.h> 37fe56b9e6SYuval Mintz #include <linux/delay.h> 38fe56b9e6SYuval Mintz #include <linux/dma-mapping.h> 39fe56b9e6SYuval Mintz #include <linux/errno.h> 40fe56b9e6SYuval Mintz #include <linux/interrupt.h> 41fe56b9e6SYuval Mintz #include <linux/kernel.h> 42fe56b9e6SYuval Mintz #include <linux/pci.h> 43fe56b9e6SYuval Mintz #include <linux/slab.h> 44fe56b9e6SYuval Mintz #include <linux/string.h> 45fe56b9e6SYuval Mintz #include "qed.h" 46fe56b9e6SYuval Mintz #include "qed_hsi.h" 47fe56b9e6SYuval Mintz #include "qed_hw.h" 48fe56b9e6SYuval Mintz #include "qed_init_ops.h" 49fe56b9e6SYuval Mintz #include "qed_int.h" 50fe56b9e6SYuval Mintz #include "qed_mcp.h" 51fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 52fe56b9e6SYuval Mintz #include "qed_sp.h" 531408cc1fSYuval Mintz #include "qed_sriov.h" 541408cc1fSYuval Mintz #include "qed_vf.h" 55fe56b9e6SYuval Mintz 56fe56b9e6SYuval Mintz struct qed_pi_info { 57fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb; 58fe56b9e6SYuval Mintz void *cookie; 59fe56b9e6SYuval Mintz }; 60fe56b9e6SYuval Mintz 61fe56b9e6SYuval Mintz struct qed_sb_sp_info { 62fe56b9e6SYuval Mintz struct qed_sb_info sb_info; 63fe56b9e6SYuval Mintz 64fe56b9e6SYuval Mintz /* per protocol index data */ 65fe56b9e6SYuval Mintz struct qed_pi_info pi_info_arr[PIS_PER_SB]; 66fe56b9e6SYuval Mintz }; 67fe56b9e6SYuval Mintz 68ff38577aSYuval Mintz enum qed_attention_type { 69ff38577aSYuval Mintz QED_ATTN_TYPE_ATTN, 70ff38577aSYuval Mintz QED_ATTN_TYPE_PARITY, 71ff38577aSYuval Mintz }; 72ff38577aSYuval Mintz 73cc875c2eSYuval Mintz #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \ 74cc875c2eSYuval Mintz ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn) 75cc875c2eSYuval Mintz 760d956e8aSYuval Mintz struct aeu_invert_reg_bit { 770d956e8aSYuval Mintz char bit_name[30]; 780d956e8aSYuval Mintz 790d956e8aSYuval Mintz #define ATTENTION_PARITY (1 << 0) 800d956e8aSYuval Mintz 810d956e8aSYuval Mintz #define ATTENTION_LENGTH_MASK (0x00000ff0) 820d956e8aSYuval Mintz #define ATTENTION_LENGTH_SHIFT (4) 830d956e8aSYuval Mintz #define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \ 840d956e8aSYuval Mintz ATTENTION_LENGTH_SHIFT) 850d956e8aSYuval Mintz #define ATTENTION_SINGLE (1 << ATTENTION_LENGTH_SHIFT) 860d956e8aSYuval Mintz #define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY) 870d956e8aSYuval Mintz #define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \ 880d956e8aSYuval Mintz ATTENTION_PARITY) 890d956e8aSYuval Mintz 900d956e8aSYuval Mintz /* Multiple bits start with this offset */ 910d956e8aSYuval Mintz #define ATTENTION_OFFSET_MASK (0x000ff000) 920d956e8aSYuval Mintz #define ATTENTION_OFFSET_SHIFT (12) 930d956e8aSYuval Mintz unsigned int flags; 94ff38577aSYuval Mintz 95b4149dc7SYuval Mintz /* Callback to call if attention will be triggered */ 96b4149dc7SYuval Mintz int (*cb)(struct qed_hwfn *p_hwfn); 97b4149dc7SYuval Mintz 98ff38577aSYuval Mintz enum block_id block_index; 990d956e8aSYuval Mintz }; 1000d956e8aSYuval Mintz 1010d956e8aSYuval Mintz struct aeu_invert_reg { 1020d956e8aSYuval Mintz struct aeu_invert_reg_bit bits[32]; 1030d956e8aSYuval Mintz }; 1040d956e8aSYuval Mintz 1050d956e8aSYuval Mintz #define MAX_ATTN_GRPS (8) 1060d956e8aSYuval Mintz #define NUM_ATTN_REGS (9) 1070d956e8aSYuval Mintz 108b4149dc7SYuval Mintz /* Specific HW attention callbacks */ 109b4149dc7SYuval Mintz static int qed_mcp_attn_cb(struct qed_hwfn *p_hwfn) 110b4149dc7SYuval Mintz { 111b4149dc7SYuval Mintz u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE); 112b4149dc7SYuval Mintz 113b4149dc7SYuval Mintz /* This might occur on certain instances; Log it once then mask it */ 114b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, "MCP_REG_CPU_STATE: %08x - Masking...\n", 115b4149dc7SYuval Mintz tmp); 116b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, 117b4149dc7SYuval Mintz 0xffffffff); 118b4149dc7SYuval Mintz 119b4149dc7SYuval Mintz return 0; 120b4149dc7SYuval Mintz } 121b4149dc7SYuval Mintz 122b4149dc7SYuval Mintz #define QED_PSWHST_ATTENTION_INCORRECT_ACCESS (0x1) 123b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_WR_MASK (0x1) 124b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_WR_SHIFT (0) 125b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_CLIENT_MASK (0xf) 126b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT (1) 127b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK (0x1) 128b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT (5) 129b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_ID_MASK (0xff) 130b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT (6) 131b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_PF_ID_MASK (0xf) 132b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT (14) 133b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK (0xff) 134b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT (18) 135b4149dc7SYuval Mintz static int qed_pswhst_attn_cb(struct qed_hwfn *p_hwfn) 136b4149dc7SYuval Mintz { 137b4149dc7SYuval Mintz u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 138b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_VALID); 139b4149dc7SYuval Mintz 140b4149dc7SYuval Mintz if (tmp & QED_PSWHST_ATTENTION_INCORRECT_ACCESS) { 141b4149dc7SYuval Mintz u32 addr, data, length; 142b4149dc7SYuval Mintz 143b4149dc7SYuval Mintz addr = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 144b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_ADDRESS); 145b4149dc7SYuval Mintz data = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 146b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_DATA); 147b4149dc7SYuval Mintz length = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 148b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_LENGTH); 149b4149dc7SYuval Mintz 150b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, 151b4149dc7SYuval Mintz "Incorrect access to %08x of length %08x - PF [%02x] VF [%04x] [valid %02x] client [%02x] write [%02x] Byte-Enable [%04x] [%08x]\n", 152b4149dc7SYuval Mintz addr, length, 153b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_PF_ID), 154b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_VF_ID), 155b4149dc7SYuval Mintz (u8) GET_FIELD(data, 156b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_VF_VALID), 157b4149dc7SYuval Mintz (u8) GET_FIELD(data, 158b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_CLIENT), 159b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_WR), 160b4149dc7SYuval Mintz (u8) GET_FIELD(data, 161b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_BYTE_EN), 162b4149dc7SYuval Mintz data); 163b4149dc7SYuval Mintz } 164b4149dc7SYuval Mintz 165b4149dc7SYuval Mintz return 0; 166b4149dc7SYuval Mintz } 167b4149dc7SYuval Mintz 168b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VALID_BIT (1 << 0) 169b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_ADDRESS_MASK (0x7fffff) 170b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_ADDRESS_SHIFT (0) 171b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_RDWR_BIT (1 << 23) 172b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_MASTER_MASK (0xf) 173b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_MASTER_SHIFT (24) 174b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PF_MASK (0xf) 175b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PF_SHIFT (0) 176b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VF_MASK (0xff) 177b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VF_SHIFT (4) 178b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_MASK (0x3) 179b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_SHIFT (14) 180b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_VF (0) 181b4149dc7SYuval Mintz static const char *attn_master_to_str(u8 master) 182b4149dc7SYuval Mintz { 183b4149dc7SYuval Mintz switch (master) { 184b4149dc7SYuval Mintz case 1: return "PXP"; 185b4149dc7SYuval Mintz case 2: return "MCP"; 186b4149dc7SYuval Mintz case 3: return "MSDM"; 187b4149dc7SYuval Mintz case 4: return "PSDM"; 188b4149dc7SYuval Mintz case 5: return "YSDM"; 189b4149dc7SYuval Mintz case 6: return "USDM"; 190b4149dc7SYuval Mintz case 7: return "TSDM"; 191b4149dc7SYuval Mintz case 8: return "XSDM"; 192b4149dc7SYuval Mintz case 9: return "DBU"; 193b4149dc7SYuval Mintz case 10: return "DMAE"; 194b4149dc7SYuval Mintz default: 1959165dabbSMasanari Iida return "Unknown"; 196b4149dc7SYuval Mintz } 197b4149dc7SYuval Mintz } 198b4149dc7SYuval Mintz 199b4149dc7SYuval Mintz static int qed_grc_attn_cb(struct qed_hwfn *p_hwfn) 200b4149dc7SYuval Mintz { 201b4149dc7SYuval Mintz u32 tmp, tmp2; 202b4149dc7SYuval Mintz 203b4149dc7SYuval Mintz /* We've already cleared the timeout interrupt register, so we learn 204b4149dc7SYuval Mintz * of interrupts via the validity register 205b4149dc7SYuval Mintz */ 206b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 207b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_VALID); 208b4149dc7SYuval Mintz if (!(tmp & QED_GRC_ATTENTION_VALID_BIT)) 209b4149dc7SYuval Mintz goto out; 210b4149dc7SYuval Mintz 211b4149dc7SYuval Mintz /* Read the GRC timeout information */ 212b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 213b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0); 214b4149dc7SYuval Mintz tmp2 = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 215b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1); 216b4149dc7SYuval Mintz 217b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, 218b4149dc7SYuval Mintz "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n", 219b4149dc7SYuval Mintz tmp2, tmp, 220b4149dc7SYuval Mintz (tmp & QED_GRC_ATTENTION_RDWR_BIT) ? "Write to" : "Read from", 221b4149dc7SYuval Mintz GET_FIELD(tmp, QED_GRC_ATTENTION_ADDRESS) << 2, 222b4149dc7SYuval Mintz attn_master_to_str(GET_FIELD(tmp, QED_GRC_ATTENTION_MASTER)), 223b4149dc7SYuval Mintz GET_FIELD(tmp2, QED_GRC_ATTENTION_PF), 224b4149dc7SYuval Mintz (GET_FIELD(tmp2, QED_GRC_ATTENTION_PRIV) == 225b4149dc7SYuval Mintz QED_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Ireelevant)", 226b4149dc7SYuval Mintz GET_FIELD(tmp2, QED_GRC_ATTENTION_VF)); 227b4149dc7SYuval Mintz 228b4149dc7SYuval Mintz out: 229b4149dc7SYuval Mintz /* Regardles of anything else, clean the validity bit */ 230b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 231b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0); 232b4149dc7SYuval Mintz return 0; 233b4149dc7SYuval Mintz } 234b4149dc7SYuval Mintz 235b4149dc7SYuval Mintz #define PGLUE_ATTENTION_VALID (1 << 29) 236b4149dc7SYuval Mintz #define PGLUE_ATTENTION_RD_VALID (1 << 26) 237b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf) 238b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20) 239b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VF_VALID_MASK (0x1) 240b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VF_VALID_SHIFT (19) 241b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff) 242b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24) 243b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_MASK (0x1) 244b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_SHIFT (21) 245b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_BME_MASK (0x1) 246b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_BME_SHIFT (22) 247b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_FID_EN_MASK (0x1) 248b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_FID_EN_SHIFT (23) 249b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ICPL_VALID (1 << 23) 250b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ZLR_VALID (1 << 25) 251b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ILT_VALID (1 << 23) 252b4149dc7SYuval Mintz static int qed_pglub_rbc_attn_cb(struct qed_hwfn *p_hwfn) 253b4149dc7SYuval Mintz { 254b4149dc7SYuval Mintz u32 tmp; 255b4149dc7SYuval Mintz 256b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 257b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_DETAILS2); 258b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_VALID) { 259b4149dc7SYuval Mintz u32 addr_lo, addr_hi, details; 260b4149dc7SYuval Mintz 261b4149dc7SYuval Mintz addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 262b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_ADD_31_0); 263b4149dc7SYuval Mintz addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 264b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_ADD_63_32); 265b4149dc7SYuval Mintz details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 266b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_DETAILS); 267b4149dc7SYuval Mintz 268b4149dc7SYuval Mintz DP_INFO(p_hwfn, 269b4149dc7SYuval Mintz "Illegal write by chip to [%08x:%08x] blocked.\n" 270b4149dc7SYuval Mintz "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 271b4149dc7SYuval Mintz "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 272b4149dc7SYuval Mintz addr_hi, addr_lo, details, 273b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 274b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 275b4149dc7SYuval Mintz GET_FIELD(details, 276b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0, 277b4149dc7SYuval Mintz tmp, 278b4149dc7SYuval Mintz GET_FIELD(tmp, 279b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0, 280b4149dc7SYuval Mintz GET_FIELD(tmp, 281b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0, 282b4149dc7SYuval Mintz GET_FIELD(tmp, 283b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0); 284b4149dc7SYuval Mintz } 285b4149dc7SYuval Mintz 286b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 287b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_DETAILS2); 288b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_RD_VALID) { 289b4149dc7SYuval Mintz u32 addr_lo, addr_hi, details; 290b4149dc7SYuval Mintz 291b4149dc7SYuval Mintz addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 292b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_ADD_31_0); 293b4149dc7SYuval Mintz addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 294b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_ADD_63_32); 295b4149dc7SYuval Mintz details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 296b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_DETAILS); 297b4149dc7SYuval Mintz 298b4149dc7SYuval Mintz DP_INFO(p_hwfn, 299b4149dc7SYuval Mintz "Illegal read by chip from [%08x:%08x] blocked.\n" 300b4149dc7SYuval Mintz " Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 301b4149dc7SYuval Mintz " Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 302b4149dc7SYuval Mintz addr_hi, addr_lo, details, 303b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 304b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 305b4149dc7SYuval Mintz GET_FIELD(details, 306b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0, 307b4149dc7SYuval Mintz tmp, 308b4149dc7SYuval Mintz GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 309b4149dc7SYuval Mintz : 0, 310b4149dc7SYuval Mintz GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0, 311b4149dc7SYuval Mintz GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 312b4149dc7SYuval Mintz : 0); 313b4149dc7SYuval Mintz } 314b4149dc7SYuval Mintz 315b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 316b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL); 317b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ICPL_VALID) 318b4149dc7SYuval Mintz DP_INFO(p_hwfn, "ICPL eror - %08x\n", tmp); 319b4149dc7SYuval Mintz 320b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 321b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS); 322b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ZLR_VALID) { 323b4149dc7SYuval Mintz u32 addr_hi, addr_lo; 324b4149dc7SYuval Mintz 325b4149dc7SYuval Mintz addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 326b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0); 327b4149dc7SYuval Mintz addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 328b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32); 329b4149dc7SYuval Mintz 330b4149dc7SYuval Mintz DP_INFO(p_hwfn, "ZLR eror - %08x [Address %08x:%08x]\n", 331b4149dc7SYuval Mintz tmp, addr_hi, addr_lo); 332b4149dc7SYuval Mintz } 333b4149dc7SYuval Mintz 334b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 335b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_DETAILS2); 336b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ILT_VALID) { 337b4149dc7SYuval Mintz u32 addr_hi, addr_lo, details; 338b4149dc7SYuval Mintz 339b4149dc7SYuval Mintz addr_lo = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 340b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_ADD_31_0); 341b4149dc7SYuval Mintz addr_hi = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 342b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_ADD_63_32); 343b4149dc7SYuval Mintz details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 344b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_DETAILS); 345b4149dc7SYuval Mintz 346b4149dc7SYuval Mintz DP_INFO(p_hwfn, 347b4149dc7SYuval Mintz "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n", 348b4149dc7SYuval Mintz details, tmp, addr_hi, addr_lo); 349b4149dc7SYuval Mintz } 350b4149dc7SYuval Mintz 351b4149dc7SYuval Mintz /* Clear the indications */ 352b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 353b4149dc7SYuval Mintz PGLUE_B_REG_LATCHED_ERRORS_CLR, (1 << 2)); 354b4149dc7SYuval Mintz 355b4149dc7SYuval Mintz return 0; 356b4149dc7SYuval Mintz } 357b4149dc7SYuval Mintz 358b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_REASON_MASK (0xfffff) 359b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_OPAQUE_MASK (0xffff) 360b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_SIZE_MASK (0x7f) 361b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_SIZE_SHIFT (16) 362b4149dc7SYuval Mintz static int qed_dorq_attn_cb(struct qed_hwfn *p_hwfn) 363b4149dc7SYuval Mintz { 364b4149dc7SYuval Mintz u32 reason; 365b4149dc7SYuval Mintz 366b4149dc7SYuval Mintz reason = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, DORQ_REG_DB_DROP_REASON) & 367b4149dc7SYuval Mintz QED_DORQ_ATTENTION_REASON_MASK; 368b4149dc7SYuval Mintz if (reason) { 369b4149dc7SYuval Mintz u32 details = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 370b4149dc7SYuval Mintz DORQ_REG_DB_DROP_DETAILS); 371b4149dc7SYuval Mintz 372b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, 3739165dabbSMasanari Iida "DORQ db_drop: address 0x%08x Opaque FID 0x%04x Size [bytes] 0x%08x Reason: 0x%08x\n", 374b4149dc7SYuval Mintz qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 375b4149dc7SYuval Mintz DORQ_REG_DB_DROP_DETAILS_ADDRESS), 376b4149dc7SYuval Mintz (u16)(details & QED_DORQ_ATTENTION_OPAQUE_MASK), 377b4149dc7SYuval Mintz GET_FIELD(details, QED_DORQ_ATTENTION_SIZE) * 4, 378b4149dc7SYuval Mintz reason); 379b4149dc7SYuval Mintz } 380b4149dc7SYuval Mintz 381b4149dc7SYuval Mintz return -EINVAL; 382b4149dc7SYuval Mintz } 383b4149dc7SYuval Mintz 3840d956e8aSYuval Mintz /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */ 3850d956e8aSYuval Mintz static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = { 3860d956e8aSYuval Mintz { 3870d956e8aSYuval Mintz { /* After Invert 1 */ 3880d956e8aSYuval Mintz {"GPIO0 function%d", 389b4149dc7SYuval Mintz (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 3900d956e8aSYuval Mintz } 3910d956e8aSYuval Mintz }, 3920d956e8aSYuval Mintz 3930d956e8aSYuval Mintz { 3940d956e8aSYuval Mintz { /* After Invert 2 */ 395b4149dc7SYuval Mintz {"PGLUE config_space", ATTENTION_SINGLE, 396b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 397b4149dc7SYuval Mintz {"PGLUE misc_flr", ATTENTION_SINGLE, 398b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 399b4149dc7SYuval Mintz {"PGLUE B RBC", ATTENTION_PAR_INT, 400b4149dc7SYuval Mintz qed_pglub_rbc_attn_cb, BLOCK_PGLUE_B}, 401b4149dc7SYuval Mintz {"PGLUE misc_mctp", ATTENTION_SINGLE, 402b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 403b4149dc7SYuval Mintz {"Flash event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 404b4149dc7SYuval Mintz {"SMB event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 405b4149dc7SYuval Mintz {"Main Power", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 4060d956e8aSYuval Mintz {"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) | 407ff38577aSYuval Mintz (1 << ATTENTION_OFFSET_SHIFT), 408b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 4090d956e8aSYuval Mintz {"PCIE glue/PXP VPD %d", 410b4149dc7SYuval Mintz (16 << ATTENTION_LENGTH_SHIFT), NULL, BLOCK_PGLCS}, 4110d956e8aSYuval Mintz } 4120d956e8aSYuval Mintz }, 4130d956e8aSYuval Mintz 4140d956e8aSYuval Mintz { 4150d956e8aSYuval Mintz { /* After Invert 3 */ 4160d956e8aSYuval Mintz {"General Attention %d", 417b4149dc7SYuval Mintz (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 4180d956e8aSYuval Mintz } 4190d956e8aSYuval Mintz }, 4200d956e8aSYuval Mintz 4210d956e8aSYuval Mintz { 4220d956e8aSYuval Mintz { /* After Invert 4 */ 423ff38577aSYuval Mintz {"General Attention 32", ATTENTION_SINGLE, 424b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 4250d956e8aSYuval Mintz {"General Attention %d", 4260d956e8aSYuval Mintz (2 << ATTENTION_LENGTH_SHIFT) | 427b4149dc7SYuval Mintz (33 << ATTENTION_OFFSET_SHIFT), NULL, MAX_BLOCK_ID}, 428ff38577aSYuval Mintz {"General Attention 35", ATTENTION_SINGLE, 429b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 430ff38577aSYuval Mintz {"CNIG port %d", (4 << ATTENTION_LENGTH_SHIFT), 431b4149dc7SYuval Mintz NULL, BLOCK_CNIG}, 432b4149dc7SYuval Mintz {"MCP CPU", ATTENTION_SINGLE, 433b4149dc7SYuval Mintz qed_mcp_attn_cb, MAX_BLOCK_ID}, 434b4149dc7SYuval Mintz {"MCP Watchdog timer", ATTENTION_SINGLE, 435b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 436b4149dc7SYuval Mintz {"MCP M2P", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 437ff38577aSYuval Mintz {"AVS stop status ready", ATTENTION_SINGLE, 438b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 439b4149dc7SYuval Mintz {"MSTAT", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 440b4149dc7SYuval Mintz {"MSTAT per-path", ATTENTION_PAR_INT, 441b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 442ff38577aSYuval Mintz {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), 443b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 444b4149dc7SYuval Mintz {"NIG", ATTENTION_PAR_INT, NULL, BLOCK_NIG}, 445b4149dc7SYuval Mintz {"BMB/OPTE/MCP", ATTENTION_PAR_INT, NULL, BLOCK_BMB}, 446b4149dc7SYuval Mintz {"BTB", ATTENTION_PAR_INT, NULL, BLOCK_BTB}, 447b4149dc7SYuval Mintz {"BRB", ATTENTION_PAR_INT, NULL, BLOCK_BRB}, 448b4149dc7SYuval Mintz {"PRS", ATTENTION_PAR_INT, NULL, BLOCK_PRS}, 4490d956e8aSYuval Mintz } 4500d956e8aSYuval Mintz }, 4510d956e8aSYuval Mintz 4520d956e8aSYuval Mintz { 4530d956e8aSYuval Mintz { /* After Invert 5 */ 454b4149dc7SYuval Mintz {"SRC", ATTENTION_PAR_INT, NULL, BLOCK_SRC}, 455b4149dc7SYuval Mintz {"PB Client1", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB1}, 456b4149dc7SYuval Mintz {"PB Client2", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB2}, 457b4149dc7SYuval Mintz {"RPB", ATTENTION_PAR_INT, NULL, BLOCK_RPB}, 458b4149dc7SYuval Mintz {"PBF", ATTENTION_PAR_INT, NULL, BLOCK_PBF}, 459b4149dc7SYuval Mintz {"QM", ATTENTION_PAR_INT, NULL, BLOCK_QM}, 460b4149dc7SYuval Mintz {"TM", ATTENTION_PAR_INT, NULL, BLOCK_TM}, 461b4149dc7SYuval Mintz {"MCM", ATTENTION_PAR_INT, NULL, BLOCK_MCM}, 462b4149dc7SYuval Mintz {"MSDM", ATTENTION_PAR_INT, NULL, BLOCK_MSDM}, 463b4149dc7SYuval Mintz {"MSEM", ATTENTION_PAR_INT, NULL, BLOCK_MSEM}, 464b4149dc7SYuval Mintz {"PCM", ATTENTION_PAR_INT, NULL, BLOCK_PCM}, 465b4149dc7SYuval Mintz {"PSDM", ATTENTION_PAR_INT, NULL, BLOCK_PSDM}, 466b4149dc7SYuval Mintz {"PSEM", ATTENTION_PAR_INT, NULL, BLOCK_PSEM}, 467b4149dc7SYuval Mintz {"TCM", ATTENTION_PAR_INT, NULL, BLOCK_TCM}, 468b4149dc7SYuval Mintz {"TSDM", ATTENTION_PAR_INT, NULL, BLOCK_TSDM}, 469b4149dc7SYuval Mintz {"TSEM", ATTENTION_PAR_INT, NULL, BLOCK_TSEM}, 4700d956e8aSYuval Mintz } 4710d956e8aSYuval Mintz }, 4720d956e8aSYuval Mintz 4730d956e8aSYuval Mintz { 4740d956e8aSYuval Mintz { /* After Invert 6 */ 475b4149dc7SYuval Mintz {"UCM", ATTENTION_PAR_INT, NULL, BLOCK_UCM}, 476b4149dc7SYuval Mintz {"USDM", ATTENTION_PAR_INT, NULL, BLOCK_USDM}, 477b4149dc7SYuval Mintz {"USEM", ATTENTION_PAR_INT, NULL, BLOCK_USEM}, 478b4149dc7SYuval Mintz {"XCM", ATTENTION_PAR_INT, NULL, BLOCK_XCM}, 479b4149dc7SYuval Mintz {"XSDM", ATTENTION_PAR_INT, NULL, BLOCK_XSDM}, 480b4149dc7SYuval Mintz {"XSEM", ATTENTION_PAR_INT, NULL, BLOCK_XSEM}, 481b4149dc7SYuval Mintz {"YCM", ATTENTION_PAR_INT, NULL, BLOCK_YCM}, 482b4149dc7SYuval Mintz {"YSDM", ATTENTION_PAR_INT, NULL, BLOCK_YSDM}, 483b4149dc7SYuval Mintz {"YSEM", ATTENTION_PAR_INT, NULL, BLOCK_YSEM}, 484b4149dc7SYuval Mintz {"XYLD", ATTENTION_PAR_INT, NULL, BLOCK_XYLD}, 485b4149dc7SYuval Mintz {"TMLD", ATTENTION_PAR_INT, NULL, BLOCK_TMLD}, 486b4149dc7SYuval Mintz {"MYLD", ATTENTION_PAR_INT, NULL, BLOCK_MULD}, 487b4149dc7SYuval Mintz {"YULD", ATTENTION_PAR_INT, NULL, BLOCK_YULD}, 488b4149dc7SYuval Mintz {"DORQ", ATTENTION_PAR_INT, 489b4149dc7SYuval Mintz qed_dorq_attn_cb, BLOCK_DORQ}, 490b4149dc7SYuval Mintz {"DBG", ATTENTION_PAR_INT, NULL, BLOCK_DBG}, 491b4149dc7SYuval Mintz {"IPC", ATTENTION_PAR_INT, NULL, BLOCK_IPC}, 4920d956e8aSYuval Mintz } 4930d956e8aSYuval Mintz }, 4940d956e8aSYuval Mintz 4950d956e8aSYuval Mintz { 4960d956e8aSYuval Mintz { /* After Invert 7 */ 497b4149dc7SYuval Mintz {"CCFC", ATTENTION_PAR_INT, NULL, BLOCK_CCFC}, 498b4149dc7SYuval Mintz {"CDU", ATTENTION_PAR_INT, NULL, BLOCK_CDU}, 499b4149dc7SYuval Mintz {"DMAE", ATTENTION_PAR_INT, NULL, BLOCK_DMAE}, 500b4149dc7SYuval Mintz {"IGU", ATTENTION_PAR_INT, NULL, BLOCK_IGU}, 501b4149dc7SYuval Mintz {"ATC", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 502b4149dc7SYuval Mintz {"CAU", ATTENTION_PAR_INT, NULL, BLOCK_CAU}, 503b4149dc7SYuval Mintz {"PTU", ATTENTION_PAR_INT, NULL, BLOCK_PTU}, 504b4149dc7SYuval Mintz {"PRM", ATTENTION_PAR_INT, NULL, BLOCK_PRM}, 505b4149dc7SYuval Mintz {"TCFC", ATTENTION_PAR_INT, NULL, BLOCK_TCFC}, 506b4149dc7SYuval Mintz {"RDIF", ATTENTION_PAR_INT, NULL, BLOCK_RDIF}, 507b4149dc7SYuval Mintz {"TDIF", ATTENTION_PAR_INT, NULL, BLOCK_TDIF}, 508b4149dc7SYuval Mintz {"RSS", ATTENTION_PAR_INT, NULL, BLOCK_RSS}, 509b4149dc7SYuval Mintz {"MISC", ATTENTION_PAR_INT, NULL, BLOCK_MISC}, 510b4149dc7SYuval Mintz {"MISCS", ATTENTION_PAR_INT, NULL, BLOCK_MISCS}, 511b4149dc7SYuval Mintz {"PCIE", ATTENTION_PAR, NULL, BLOCK_PCIE}, 512b4149dc7SYuval Mintz {"Vaux PCI core", ATTENTION_SINGLE, NULL, BLOCK_PGLCS}, 513b4149dc7SYuval Mintz {"PSWRQ", ATTENTION_PAR_INT, NULL, BLOCK_PSWRQ}, 5140d956e8aSYuval Mintz } 5150d956e8aSYuval Mintz }, 5160d956e8aSYuval Mintz 5170d956e8aSYuval Mintz { 5180d956e8aSYuval Mintz { /* After Invert 8 */ 519b4149dc7SYuval Mintz {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, 520b4149dc7SYuval Mintz NULL, BLOCK_PSWRQ2}, 521b4149dc7SYuval Mintz {"PSWWR", ATTENTION_PAR_INT, NULL, BLOCK_PSWWR}, 522b4149dc7SYuval Mintz {"PSWWR (pci_clk)", ATTENTION_PAR_INT, 523b4149dc7SYuval Mintz NULL, BLOCK_PSWWR2}, 524b4149dc7SYuval Mintz {"PSWRD", ATTENTION_PAR_INT, NULL, BLOCK_PSWRD}, 525b4149dc7SYuval Mintz {"PSWRD (pci_clk)", ATTENTION_PAR_INT, 526b4149dc7SYuval Mintz NULL, BLOCK_PSWRD2}, 527b4149dc7SYuval Mintz {"PSWHST", ATTENTION_PAR_INT, 528b4149dc7SYuval Mintz qed_pswhst_attn_cb, BLOCK_PSWHST}, 529b4149dc7SYuval Mintz {"PSWHST (pci_clk)", ATTENTION_PAR_INT, 530b4149dc7SYuval Mintz NULL, BLOCK_PSWHST2}, 531b4149dc7SYuval Mintz {"GRC", ATTENTION_PAR_INT, 532b4149dc7SYuval Mintz qed_grc_attn_cb, BLOCK_GRC}, 533b4149dc7SYuval Mintz {"CPMU", ATTENTION_PAR_INT, NULL, BLOCK_CPMU}, 534b4149dc7SYuval Mintz {"NCSI", ATTENTION_PAR_INT, NULL, BLOCK_NCSI}, 535b4149dc7SYuval Mintz {"MSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 536b4149dc7SYuval Mintz {"PSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 537b4149dc7SYuval Mintz {"TSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 538b4149dc7SYuval Mintz {"USEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 539b4149dc7SYuval Mintz {"XSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 540b4149dc7SYuval Mintz {"YSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 541b4149dc7SYuval Mintz {"pxp_misc_mps", ATTENTION_PAR, NULL, BLOCK_PGLCS}, 542ff38577aSYuval Mintz {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, 543b4149dc7SYuval Mintz NULL, BLOCK_PGLCS}, 544b4149dc7SYuval Mintz {"PERST_B assertion", ATTENTION_SINGLE, 545b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 546ff38577aSYuval Mintz {"PERST_B deassertion", ATTENTION_SINGLE, 547b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 548ff38577aSYuval Mintz {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), 549b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 5500d956e8aSYuval Mintz } 5510d956e8aSYuval Mintz }, 5520d956e8aSYuval Mintz 5530d956e8aSYuval Mintz { 5540d956e8aSYuval Mintz { /* After Invert 9 */ 555b4149dc7SYuval Mintz {"MCP Latched memory", ATTENTION_PAR, 556b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 557ff38577aSYuval Mintz {"MCP Latched scratchpad cache", ATTENTION_SINGLE, 558b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 559b4149dc7SYuval Mintz {"MCP Latched ump_tx", ATTENTION_PAR, 560b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 561ff38577aSYuval Mintz {"MCP Latched scratchpad", ATTENTION_PAR, 562b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 563ff38577aSYuval Mintz {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT), 564b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 5650d956e8aSYuval Mintz } 5660d956e8aSYuval Mintz }, 5670d956e8aSYuval Mintz }; 5680d956e8aSYuval Mintz 569cc875c2eSYuval Mintz #define ATTN_STATE_BITS (0xfff) 570cc875c2eSYuval Mintz #define ATTN_BITS_MASKABLE (0x3ff) 571cc875c2eSYuval Mintz struct qed_sb_attn_info { 572cc875c2eSYuval Mintz /* Virtual & Physical address of the SB */ 573cc875c2eSYuval Mintz struct atten_status_block *sb_attn; 574cc875c2eSYuval Mintz dma_addr_t sb_phys; 575cc875c2eSYuval Mintz 576cc875c2eSYuval Mintz /* Last seen running index */ 577cc875c2eSYuval Mintz u16 index; 578cc875c2eSYuval Mintz 5790d956e8aSYuval Mintz /* A mask of the AEU bits resulting in a parity error */ 5800d956e8aSYuval Mintz u32 parity_mask[NUM_ATTN_REGS]; 5810d956e8aSYuval Mintz 5820d956e8aSYuval Mintz /* A pointer to the attention description structure */ 5830d956e8aSYuval Mintz struct aeu_invert_reg *p_aeu_desc; 5840d956e8aSYuval Mintz 585cc875c2eSYuval Mintz /* Previously asserted attentions, which are still unasserted */ 586cc875c2eSYuval Mintz u16 known_attn; 587cc875c2eSYuval Mintz 588cc875c2eSYuval Mintz /* Cleanup address for the link's general hw attention */ 589cc875c2eSYuval Mintz u32 mfw_attn_addr; 590cc875c2eSYuval Mintz }; 591cc875c2eSYuval Mintz 592cc875c2eSYuval Mintz static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn, 593cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb_desc) 594cc875c2eSYuval Mintz { 5951a635e48SYuval Mintz u16 rc = 0, index; 596cc875c2eSYuval Mintz 597cc875c2eSYuval Mintz /* Make certain HW write took affect */ 598cc875c2eSYuval Mintz mmiowb(); 599cc875c2eSYuval Mintz 600cc875c2eSYuval Mintz index = le16_to_cpu(p_sb_desc->sb_attn->sb_index); 601cc875c2eSYuval Mintz if (p_sb_desc->index != index) { 602cc875c2eSYuval Mintz p_sb_desc->index = index; 603cc875c2eSYuval Mintz rc = QED_SB_ATT_IDX; 604cc875c2eSYuval Mintz } 605cc875c2eSYuval Mintz 606cc875c2eSYuval Mintz /* Make certain we got a consistent view with HW */ 607cc875c2eSYuval Mintz mmiowb(); 608cc875c2eSYuval Mintz 609cc875c2eSYuval Mintz return rc; 610cc875c2eSYuval Mintz } 611cc875c2eSYuval Mintz 612cc875c2eSYuval Mintz /** 613cc875c2eSYuval Mintz * @brief qed_int_assertion - handles asserted attention bits 614cc875c2eSYuval Mintz * 615cc875c2eSYuval Mintz * @param p_hwfn 616cc875c2eSYuval Mintz * @param asserted_bits newly asserted bits 617cc875c2eSYuval Mintz * @return int 618cc875c2eSYuval Mintz */ 6191a635e48SYuval Mintz static int qed_int_assertion(struct qed_hwfn *p_hwfn, u16 asserted_bits) 620cc875c2eSYuval Mintz { 621cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 622cc875c2eSYuval Mintz u32 igu_mask; 623cc875c2eSYuval Mintz 624cc875c2eSYuval Mintz /* Mask the source of the attention in the IGU */ 6251a635e48SYuval Mintz igu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); 626cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n", 627cc875c2eSYuval Mintz igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE)); 628cc875c2eSYuval Mintz igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE); 629cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask); 630cc875c2eSYuval Mintz 631cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 632cc875c2eSYuval Mintz "inner known ATTN state: 0x%04x --> 0x%04x\n", 633cc875c2eSYuval Mintz sb_attn_sw->known_attn, 634cc875c2eSYuval Mintz sb_attn_sw->known_attn | asserted_bits); 635cc875c2eSYuval Mintz sb_attn_sw->known_attn |= asserted_bits; 636cc875c2eSYuval Mintz 637cc875c2eSYuval Mintz /* Handle MCP events */ 638cc875c2eSYuval Mintz if (asserted_bits & 0x100) { 639cc875c2eSYuval Mintz qed_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt); 640cc875c2eSYuval Mintz /* Clean the MCP attention */ 641cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 642cc875c2eSYuval Mintz sb_attn_sw->mfw_attn_addr, 0); 643cc875c2eSYuval Mintz } 644cc875c2eSYuval Mintz 645cc875c2eSYuval Mintz DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 646cc875c2eSYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 647cc875c2eSYuval Mintz ((IGU_CMD_ATTN_BIT_SET_UPPER - 648cc875c2eSYuval Mintz IGU_CMD_INT_ACK_BASE) << 3), 649cc875c2eSYuval Mintz (u32)asserted_bits); 650cc875c2eSYuval Mintz 651cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "set cmd IGU: 0x%04x\n", 652cc875c2eSYuval Mintz asserted_bits); 653cc875c2eSYuval Mintz 654cc875c2eSYuval Mintz return 0; 655cc875c2eSYuval Mintz } 656cc875c2eSYuval Mintz 6570ebbd1c8SMintz, Yuval static void qed_int_attn_print(struct qed_hwfn *p_hwfn, 6580ebbd1c8SMintz, Yuval enum block_id id, 6590ebbd1c8SMintz, Yuval enum dbg_attn_type type, bool b_clear) 660ff38577aSYuval Mintz { 6610ebbd1c8SMintz, Yuval struct dbg_attn_block_result attn_results; 6620ebbd1c8SMintz, Yuval enum dbg_status status; 663ff38577aSYuval Mintz 6640ebbd1c8SMintz, Yuval memset(&attn_results, 0, sizeof(attn_results)); 665ff38577aSYuval Mintz 6660ebbd1c8SMintz, Yuval status = qed_dbg_read_attn(p_hwfn, p_hwfn->p_dpc_ptt, id, type, 6670ebbd1c8SMintz, Yuval b_clear, &attn_results); 6680ebbd1c8SMintz, Yuval if (status != DBG_STATUS_OK) 669ff38577aSYuval Mintz DP_NOTICE(p_hwfn, 6700ebbd1c8SMintz, Yuval "Failed to parse attention information [status: %s]\n", 6710ebbd1c8SMintz, Yuval qed_dbg_get_status_str(status)); 6720ebbd1c8SMintz, Yuval else 6730ebbd1c8SMintz, Yuval qed_dbg_parse_attn(p_hwfn, &attn_results); 674ff38577aSYuval Mintz } 675ff38577aSYuval Mintz 676cc875c2eSYuval Mintz /** 6770d956e8aSYuval Mintz * @brief qed_int_deassertion_aeu_bit - handles the effects of a single 6780d956e8aSYuval Mintz * cause of the attention 6790d956e8aSYuval Mintz * 6800d956e8aSYuval Mintz * @param p_hwfn 6810d956e8aSYuval Mintz * @param p_aeu - descriptor of an AEU bit which caused the attention 6820d956e8aSYuval Mintz * @param aeu_en_reg - register offset of the AEU enable reg. which configured 6830d956e8aSYuval Mintz * this bit to this group. 6840d956e8aSYuval Mintz * @param bit_index - index of this bit in the aeu_en_reg 6850d956e8aSYuval Mintz * 6860d956e8aSYuval Mintz * @return int 6870d956e8aSYuval Mintz */ 6880d956e8aSYuval Mintz static int 6890d956e8aSYuval Mintz qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn, 6900d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_aeu, 6910d956e8aSYuval Mintz u32 aeu_en_reg, 6920d956e8aSYuval Mintz u32 bitmask) 6930d956e8aSYuval Mintz { 6940ebbd1c8SMintz, Yuval bool b_fatal = false; 6950d956e8aSYuval Mintz int rc = -EINVAL; 696b4149dc7SYuval Mintz u32 val; 6970d956e8aSYuval Mintz 6980d956e8aSYuval Mintz DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n", 6990d956e8aSYuval Mintz p_aeu->bit_name, bitmask); 7000d956e8aSYuval Mintz 701b4149dc7SYuval Mintz /* Call callback before clearing the interrupt status */ 702b4149dc7SYuval Mintz if (p_aeu->cb) { 703b4149dc7SYuval Mintz DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n", 704b4149dc7SYuval Mintz p_aeu->bit_name); 705b4149dc7SYuval Mintz rc = p_aeu->cb(p_hwfn); 706b4149dc7SYuval Mintz } 707b4149dc7SYuval Mintz 7080ebbd1c8SMintz, Yuval if (rc) 7090ebbd1c8SMintz, Yuval b_fatal = true; 710ff38577aSYuval Mintz 7110ebbd1c8SMintz, Yuval /* Print HW block interrupt registers */ 7120ebbd1c8SMintz, Yuval if (p_aeu->block_index != MAX_BLOCK_ID) 7130ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, p_aeu->block_index, 7140ebbd1c8SMintz, Yuval ATTN_TYPE_INTERRUPT, !b_fatal); 715ff38577aSYuval Mintz 716ff38577aSYuval Mintz 717b4149dc7SYuval Mintz /* If the attention is benign, no need to prevent it */ 718b4149dc7SYuval Mintz if (!rc) 719b4149dc7SYuval Mintz goto out; 720b4149dc7SYuval Mintz 7210d956e8aSYuval Mintz /* Prevent this Attention from being asserted in the future */ 7220d956e8aSYuval Mintz val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 723b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & ~bitmask)); 7240d956e8aSYuval Mintz DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n", 7250d956e8aSYuval Mintz p_aeu->bit_name); 7260d956e8aSYuval Mintz 727b4149dc7SYuval Mintz out: 7280d956e8aSYuval Mintz return rc; 7290d956e8aSYuval Mintz } 7300d956e8aSYuval Mintz 731ff38577aSYuval Mintz /** 732ff38577aSYuval Mintz * @brief qed_int_deassertion_parity - handle a single parity AEU source 733ff38577aSYuval Mintz * 734ff38577aSYuval Mintz * @param p_hwfn 735ff38577aSYuval Mintz * @param p_aeu - descriptor of an AEU bit which caused the parity 736ff38577aSYuval Mintz * @param bit_index 737ff38577aSYuval Mintz */ 738ff38577aSYuval Mintz static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn, 739ff38577aSYuval Mintz struct aeu_invert_reg_bit *p_aeu, 740ff38577aSYuval Mintz u8 bit_index) 741ff38577aSYuval Mintz { 742ff38577aSYuval Mintz u32 block_id = p_aeu->block_index; 743ff38577aSYuval Mintz 744ff38577aSYuval Mintz DP_INFO(p_hwfn->cdev, "%s[%d] parity attention is set\n", 745ff38577aSYuval Mintz p_aeu->bit_name, bit_index); 746ff38577aSYuval Mintz 747ff38577aSYuval Mintz if (block_id != MAX_BLOCK_ID) { 7480ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, block_id, ATTN_TYPE_PARITY, false); 749ff38577aSYuval Mintz 750ff38577aSYuval Mintz /* In BB, there's a single parity bit for several blocks */ 751ff38577aSYuval Mintz if (block_id == BLOCK_BTB) { 7520ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, BLOCK_OPTE, 7530ebbd1c8SMintz, Yuval ATTN_TYPE_PARITY, false); 7540ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, BLOCK_MCP, 7550ebbd1c8SMintz, Yuval ATTN_TYPE_PARITY, false); 756ff38577aSYuval Mintz } 757ff38577aSYuval Mintz } 758ff38577aSYuval Mintz } 759ff38577aSYuval Mintz 7600d956e8aSYuval Mintz /** 761cc875c2eSYuval Mintz * @brief - handles deassertion of previously asserted attentions. 762cc875c2eSYuval Mintz * 763cc875c2eSYuval Mintz * @param p_hwfn 764cc875c2eSYuval Mintz * @param deasserted_bits - newly deasserted bits 765cc875c2eSYuval Mintz * @return int 766cc875c2eSYuval Mintz * 767cc875c2eSYuval Mintz */ 768cc875c2eSYuval Mintz static int qed_int_deassertion(struct qed_hwfn *p_hwfn, 769cc875c2eSYuval Mintz u16 deasserted_bits) 770cc875c2eSYuval Mintz { 771cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 7720d956e8aSYuval Mintz u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask; 7730d956e8aSYuval Mintz u8 i, j, k, bit_idx; 7740d956e8aSYuval Mintz int rc = 0; 775cc875c2eSYuval Mintz 7760d956e8aSYuval Mintz /* Read the attention registers in the AEU */ 7770d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 7780d956e8aSYuval Mintz aeu_inv_arr[i] = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 7790d956e8aSYuval Mintz MISC_REG_AEU_AFTER_INVERT_1_IGU + 7800d956e8aSYuval Mintz i * 0x4); 7810d956e8aSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 7820d956e8aSYuval Mintz "Deasserted bits [%d]: %08x\n", 7830d956e8aSYuval Mintz i, aeu_inv_arr[i]); 7840d956e8aSYuval Mintz } 7850d956e8aSYuval Mintz 7860d956e8aSYuval Mintz /* Find parity attentions first */ 7870d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 7880d956e8aSYuval Mintz struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i]; 7890d956e8aSYuval Mintz u32 en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 7900d956e8aSYuval Mintz MISC_REG_AEU_ENABLE1_IGU_OUT_0 + 7910d956e8aSYuval Mintz i * sizeof(u32)); 7920d956e8aSYuval Mintz u32 parities; 7930d956e8aSYuval Mintz 7940d956e8aSYuval Mintz /* Skip register in which no parity bit is currently set */ 7950d956e8aSYuval Mintz parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en; 7960d956e8aSYuval Mintz if (!parities) 7970d956e8aSYuval Mintz continue; 7980d956e8aSYuval Mintz 7990d956e8aSYuval Mintz for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 8000d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j]; 8010d956e8aSYuval Mintz 8020d956e8aSYuval Mintz if ((p_bit->flags & ATTENTION_PARITY) && 8031a635e48SYuval Mintz !!(parities & BIT(bit_idx))) 804ff38577aSYuval Mintz qed_int_deassertion_parity(p_hwfn, p_bit, 805ff38577aSYuval Mintz bit_idx); 8060d956e8aSYuval Mintz 8070d956e8aSYuval Mintz bit_idx += ATTENTION_LENGTH(p_bit->flags); 8080d956e8aSYuval Mintz } 8090d956e8aSYuval Mintz } 8100d956e8aSYuval Mintz 8110d956e8aSYuval Mintz /* Find non-parity cause for attention and act */ 8120d956e8aSYuval Mintz for (k = 0; k < MAX_ATTN_GRPS; k++) { 8130d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_aeu; 8140d956e8aSYuval Mintz 8150d956e8aSYuval Mintz /* Handle only groups whose attention is currently deasserted */ 8160d956e8aSYuval Mintz if (!(deasserted_bits & (1 << k))) 8170d956e8aSYuval Mintz continue; 8180d956e8aSYuval Mintz 8190d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 8200d956e8aSYuval Mintz u32 aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + 8210d956e8aSYuval Mintz i * sizeof(u32) + 8220d956e8aSYuval Mintz k * sizeof(u32) * NUM_ATTN_REGS; 8230d956e8aSYuval Mintz u32 en, bits; 8240d956e8aSYuval Mintz 8250d956e8aSYuval Mintz en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 8260d956e8aSYuval Mintz bits = aeu_inv_arr[i] & en; 8270d956e8aSYuval Mintz 8280d956e8aSYuval Mintz /* Skip if no bit from this group is currently set */ 8290d956e8aSYuval Mintz if (!bits) 8300d956e8aSYuval Mintz continue; 8310d956e8aSYuval Mintz 8320d956e8aSYuval Mintz /* Find all set bits from current register which belong 8330d956e8aSYuval Mintz * to current group, making them responsible for the 8340d956e8aSYuval Mintz * previous assertion. 8350d956e8aSYuval Mintz */ 8360d956e8aSYuval Mintz for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 8370d956e8aSYuval Mintz u8 bit, bit_len; 8380d956e8aSYuval Mintz u32 bitmask; 8390d956e8aSYuval Mintz 8400d956e8aSYuval Mintz p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j]; 8410d956e8aSYuval Mintz 8420d956e8aSYuval Mintz /* No need to handle parity-only bits */ 8430d956e8aSYuval Mintz if (p_aeu->flags == ATTENTION_PAR) 8440d956e8aSYuval Mintz continue; 8450d956e8aSYuval Mintz 8460d956e8aSYuval Mintz bit = bit_idx; 8470d956e8aSYuval Mintz bit_len = ATTENTION_LENGTH(p_aeu->flags); 8480d956e8aSYuval Mintz if (p_aeu->flags & ATTENTION_PAR_INT) { 8490d956e8aSYuval Mintz /* Skip Parity */ 8500d956e8aSYuval Mintz bit++; 8510d956e8aSYuval Mintz bit_len--; 8520d956e8aSYuval Mintz } 8530d956e8aSYuval Mintz 8540d956e8aSYuval Mintz bitmask = bits & (((1 << bit_len) - 1) << bit); 8550d956e8aSYuval Mintz if (bitmask) { 8560d956e8aSYuval Mintz /* Handle source of the attention */ 8570d956e8aSYuval Mintz qed_int_deassertion_aeu_bit(p_hwfn, 8580d956e8aSYuval Mintz p_aeu, 8590d956e8aSYuval Mintz aeu_en, 8600d956e8aSYuval Mintz bitmask); 8610d956e8aSYuval Mintz } 8620d956e8aSYuval Mintz 8630d956e8aSYuval Mintz bit_idx += ATTENTION_LENGTH(p_aeu->flags); 8640d956e8aSYuval Mintz } 8650d956e8aSYuval Mintz } 8660d956e8aSYuval Mintz } 867cc875c2eSYuval Mintz 868cc875c2eSYuval Mintz /* Clear IGU indication for the deasserted bits */ 869cc875c2eSYuval Mintz DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 870cc875c2eSYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 871cc875c2eSYuval Mintz ((IGU_CMD_ATTN_BIT_CLR_UPPER - 872cc875c2eSYuval Mintz IGU_CMD_INT_ACK_BASE) << 3), 873cc875c2eSYuval Mintz ~((u32)deasserted_bits)); 874cc875c2eSYuval Mintz 875cc875c2eSYuval Mintz /* Unmask deasserted attentions in IGU */ 8761a635e48SYuval Mintz aeu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); 877cc875c2eSYuval Mintz aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE); 878cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask); 879cc875c2eSYuval Mintz 880cc875c2eSYuval Mintz /* Clear deassertion from inner state */ 881cc875c2eSYuval Mintz sb_attn_sw->known_attn &= ~deasserted_bits; 882cc875c2eSYuval Mintz 8830d956e8aSYuval Mintz return rc; 884cc875c2eSYuval Mintz } 885cc875c2eSYuval Mintz 886cc875c2eSYuval Mintz static int qed_int_attentions(struct qed_hwfn *p_hwfn) 887cc875c2eSYuval Mintz { 888cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn; 889cc875c2eSYuval Mintz struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn; 890cc875c2eSYuval Mintz u32 attn_bits = 0, attn_acks = 0; 891cc875c2eSYuval Mintz u16 asserted_bits, deasserted_bits; 892cc875c2eSYuval Mintz __le16 index; 893cc875c2eSYuval Mintz int rc = 0; 894cc875c2eSYuval Mintz 895cc875c2eSYuval Mintz /* Read current attention bits/acks - safeguard against attentions 896cc875c2eSYuval Mintz * by guaranting work on a synchronized timeframe 897cc875c2eSYuval Mintz */ 898cc875c2eSYuval Mintz do { 899cc875c2eSYuval Mintz index = p_sb_attn->sb_index; 900cc875c2eSYuval Mintz attn_bits = le32_to_cpu(p_sb_attn->atten_bits); 901cc875c2eSYuval Mintz attn_acks = le32_to_cpu(p_sb_attn->atten_ack); 902cc875c2eSYuval Mintz } while (index != p_sb_attn->sb_index); 903cc875c2eSYuval Mintz p_sb_attn->sb_index = index; 904cc875c2eSYuval Mintz 905cc875c2eSYuval Mintz /* Attention / Deassertion are meaningful (and in correct state) 906cc875c2eSYuval Mintz * only when they differ and consistent with known state - deassertion 907cc875c2eSYuval Mintz * when previous attention & current ack, and assertion when current 908cc875c2eSYuval Mintz * attention with no previous attention 909cc875c2eSYuval Mintz */ 910cc875c2eSYuval Mintz asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) & 911cc875c2eSYuval Mintz ~p_sb_attn_sw->known_attn; 912cc875c2eSYuval Mintz deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) & 913cc875c2eSYuval Mintz p_sb_attn_sw->known_attn; 914cc875c2eSYuval Mintz 915cc875c2eSYuval Mintz if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100)) { 916cc875c2eSYuval Mintz DP_INFO(p_hwfn, 917cc875c2eSYuval Mintz "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n", 918cc875c2eSYuval Mintz index, attn_bits, attn_acks, asserted_bits, 919cc875c2eSYuval Mintz deasserted_bits, p_sb_attn_sw->known_attn); 920cc875c2eSYuval Mintz } else if (asserted_bits == 0x100) { 9211a635e48SYuval Mintz DP_INFO(p_hwfn, "MFW indication via attention\n"); 922cc875c2eSYuval Mintz } else { 923cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 924cc875c2eSYuval Mintz "MFW indication [deassertion]\n"); 925cc875c2eSYuval Mintz } 926cc875c2eSYuval Mintz 927cc875c2eSYuval Mintz if (asserted_bits) { 928cc875c2eSYuval Mintz rc = qed_int_assertion(p_hwfn, asserted_bits); 929cc875c2eSYuval Mintz if (rc) 930cc875c2eSYuval Mintz return rc; 931cc875c2eSYuval Mintz } 932cc875c2eSYuval Mintz 9331a635e48SYuval Mintz if (deasserted_bits) 934cc875c2eSYuval Mintz rc = qed_int_deassertion(p_hwfn, deasserted_bits); 935cc875c2eSYuval Mintz 936cc875c2eSYuval Mintz return rc; 937cc875c2eSYuval Mintz } 938cc875c2eSYuval Mintz 939cc875c2eSYuval Mintz static void qed_sb_ack_attn(struct qed_hwfn *p_hwfn, 9401a635e48SYuval Mintz void __iomem *igu_addr, u32 ack_cons) 941cc875c2eSYuval Mintz { 942cc875c2eSYuval Mintz struct igu_prod_cons_update igu_ack = { 0 }; 943cc875c2eSYuval Mintz 944cc875c2eSYuval Mintz igu_ack.sb_id_and_flags = 945cc875c2eSYuval Mintz ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 946cc875c2eSYuval Mintz (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 947cc875c2eSYuval Mintz (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 948cc875c2eSYuval Mintz (IGU_SEG_ACCESS_ATTN << 949cc875c2eSYuval Mintz IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 950cc875c2eSYuval Mintz 951cc875c2eSYuval Mintz DIRECT_REG_WR(igu_addr, igu_ack.sb_id_and_flags); 952cc875c2eSYuval Mintz 953cc875c2eSYuval Mintz /* Both segments (interrupts & acks) are written to same place address; 954cc875c2eSYuval Mintz * Need to guarantee all commands will be received (in-order) by HW. 955cc875c2eSYuval Mintz */ 956cc875c2eSYuval Mintz mmiowb(); 957cc875c2eSYuval Mintz barrier(); 958cc875c2eSYuval Mintz } 959cc875c2eSYuval Mintz 960fe56b9e6SYuval Mintz void qed_int_sp_dpc(unsigned long hwfn_cookie) 961fe56b9e6SYuval Mintz { 962fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = (struct qed_hwfn *)hwfn_cookie; 963fe56b9e6SYuval Mintz struct qed_pi_info *pi_info = NULL; 964cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn; 965fe56b9e6SYuval Mintz struct qed_sb_info *sb_info; 966fe56b9e6SYuval Mintz int arr_size; 967fe56b9e6SYuval Mintz u16 rc = 0; 968fe56b9e6SYuval Mintz 969fe56b9e6SYuval Mintz if (!p_hwfn->p_sp_sb) { 970fe56b9e6SYuval Mintz DP_ERR(p_hwfn->cdev, "DPC called - no p_sp_sb\n"); 971fe56b9e6SYuval Mintz return; 972fe56b9e6SYuval Mintz } 973fe56b9e6SYuval Mintz 974fe56b9e6SYuval Mintz sb_info = &p_hwfn->p_sp_sb->sb_info; 975fe56b9e6SYuval Mintz arr_size = ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr); 976fe56b9e6SYuval Mintz if (!sb_info) { 977fe56b9e6SYuval Mintz DP_ERR(p_hwfn->cdev, 978fe56b9e6SYuval Mintz "Status block is NULL - cannot ack interrupts\n"); 979fe56b9e6SYuval Mintz return; 980fe56b9e6SYuval Mintz } 981fe56b9e6SYuval Mintz 982cc875c2eSYuval Mintz if (!p_hwfn->p_sb_attn) { 983cc875c2eSYuval Mintz DP_ERR(p_hwfn->cdev, "DPC called - no p_sb_attn"); 984cc875c2eSYuval Mintz return; 985cc875c2eSYuval Mintz } 986cc875c2eSYuval Mintz sb_attn = p_hwfn->p_sb_attn; 987cc875c2eSYuval Mintz 988fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "DPC Called! (hwfn %p %d)\n", 989fe56b9e6SYuval Mintz p_hwfn, p_hwfn->my_id); 990fe56b9e6SYuval Mintz 991fe56b9e6SYuval Mintz /* Disable ack for def status block. Required both for msix + 992fe56b9e6SYuval Mintz * inta in non-mask mode, in inta does no harm. 993fe56b9e6SYuval Mintz */ 994fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_DISABLE, 0); 995fe56b9e6SYuval Mintz 996fe56b9e6SYuval Mintz /* Gather Interrupts/Attentions information */ 997fe56b9e6SYuval Mintz if (!sb_info->sb_virt) { 9981a635e48SYuval Mintz DP_ERR(p_hwfn->cdev, 999fe56b9e6SYuval Mintz "Interrupt Status block is NULL - cannot check for new interrupts!\n"); 1000fe56b9e6SYuval Mintz } else { 1001fe56b9e6SYuval Mintz u32 tmp_index = sb_info->sb_ack; 1002fe56b9e6SYuval Mintz 1003fe56b9e6SYuval Mintz rc = qed_sb_update_sb_idx(sb_info); 1004fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 1005fe56b9e6SYuval Mintz "Interrupt indices: 0x%08x --> 0x%08x\n", 1006fe56b9e6SYuval Mintz tmp_index, sb_info->sb_ack); 1007fe56b9e6SYuval Mintz } 1008fe56b9e6SYuval Mintz 1009cc875c2eSYuval Mintz if (!sb_attn || !sb_attn->sb_attn) { 10101a635e48SYuval Mintz DP_ERR(p_hwfn->cdev, 1011cc875c2eSYuval Mintz "Attentions Status block is NULL - cannot check for new attentions!\n"); 1012cc875c2eSYuval Mintz } else { 1013cc875c2eSYuval Mintz u16 tmp_index = sb_attn->index; 1014cc875c2eSYuval Mintz 1015cc875c2eSYuval Mintz rc |= qed_attn_update_idx(p_hwfn, sb_attn); 1016cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 1017cc875c2eSYuval Mintz "Attention indices: 0x%08x --> 0x%08x\n", 1018cc875c2eSYuval Mintz tmp_index, sb_attn->index); 1019cc875c2eSYuval Mintz } 1020cc875c2eSYuval Mintz 1021fe56b9e6SYuval Mintz /* Check if we expect interrupts at this time. if not just ack them */ 1022fe56b9e6SYuval Mintz if (!(rc & QED_SB_EVENT_MASK)) { 1023fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1024fe56b9e6SYuval Mintz return; 1025fe56b9e6SYuval Mintz } 1026fe56b9e6SYuval Mintz 1027fe56b9e6SYuval Mintz /* Check the validity of the DPC ptt. If not ack interrupts and fail */ 1028fe56b9e6SYuval Mintz if (!p_hwfn->p_dpc_ptt) { 1029fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn->cdev, "Failed to allocate PTT\n"); 1030fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1031fe56b9e6SYuval Mintz return; 1032fe56b9e6SYuval Mintz } 1033fe56b9e6SYuval Mintz 1034cc875c2eSYuval Mintz if (rc & QED_SB_ATT_IDX) 1035cc875c2eSYuval Mintz qed_int_attentions(p_hwfn); 1036cc875c2eSYuval Mintz 1037fe56b9e6SYuval Mintz if (rc & QED_SB_IDX) { 1038fe56b9e6SYuval Mintz int pi; 1039fe56b9e6SYuval Mintz 1040fe56b9e6SYuval Mintz /* Look for a free index */ 1041fe56b9e6SYuval Mintz for (pi = 0; pi < arr_size; pi++) { 1042fe56b9e6SYuval Mintz pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi]; 1043fe56b9e6SYuval Mintz if (pi_info->comp_cb) 1044fe56b9e6SYuval Mintz pi_info->comp_cb(p_hwfn, pi_info->cookie); 1045fe56b9e6SYuval Mintz } 1046fe56b9e6SYuval Mintz } 1047fe56b9e6SYuval Mintz 1048cc875c2eSYuval Mintz if (sb_attn && (rc & QED_SB_ATT_IDX)) 1049cc875c2eSYuval Mintz /* This should be done before the interrupts are enabled, 1050cc875c2eSYuval Mintz * since otherwise a new attention will be generated. 1051cc875c2eSYuval Mintz */ 1052cc875c2eSYuval Mintz qed_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index); 1053cc875c2eSYuval Mintz 1054fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1055fe56b9e6SYuval Mintz } 1056fe56b9e6SYuval Mintz 1057cc875c2eSYuval Mintz static void qed_int_sb_attn_free(struct qed_hwfn *p_hwfn) 1058cc875c2eSYuval Mintz { 1059cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb = p_hwfn->p_sb_attn; 1060cc875c2eSYuval Mintz 10614ac801b7SYuval Mintz if (!p_sb) 10624ac801b7SYuval Mintz return; 10634ac801b7SYuval Mintz 1064cc875c2eSYuval Mintz if (p_sb->sb_attn) 10654ac801b7SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1066cc875c2eSYuval Mintz SB_ATTN_ALIGNED_SIZE(p_hwfn), 10671a635e48SYuval Mintz p_sb->sb_attn, p_sb->sb_phys); 1068cc875c2eSYuval Mintz kfree(p_sb); 10693587cb87STomer Tayar p_hwfn->p_sb_attn = NULL; 1070cc875c2eSYuval Mintz } 1071cc875c2eSYuval Mintz 1072cc875c2eSYuval Mintz static void qed_int_sb_attn_setup(struct qed_hwfn *p_hwfn, 1073cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1074cc875c2eSYuval Mintz { 1075cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 1076cc875c2eSYuval Mintz 1077cc875c2eSYuval Mintz memset(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn)); 1078cc875c2eSYuval Mintz 1079cc875c2eSYuval Mintz sb_info->index = 0; 1080cc875c2eSYuval Mintz sb_info->known_attn = 0; 1081cc875c2eSYuval Mintz 1082cc875c2eSYuval Mintz /* Configure Attention Status Block in IGU */ 1083cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L, 1084cc875c2eSYuval Mintz lower_32_bits(p_hwfn->p_sb_attn->sb_phys)); 1085cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H, 1086cc875c2eSYuval Mintz upper_32_bits(p_hwfn->p_sb_attn->sb_phys)); 1087cc875c2eSYuval Mintz } 1088cc875c2eSYuval Mintz 1089cc875c2eSYuval Mintz static void qed_int_sb_attn_init(struct qed_hwfn *p_hwfn, 1090cc875c2eSYuval Mintz struct qed_ptt *p_ptt, 10911a635e48SYuval Mintz void *sb_virt_addr, dma_addr_t sb_phy_addr) 1092cc875c2eSYuval Mintz { 1093cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 10940d956e8aSYuval Mintz int i, j, k; 1095cc875c2eSYuval Mintz 1096cc875c2eSYuval Mintz sb_info->sb_attn = sb_virt_addr; 1097cc875c2eSYuval Mintz sb_info->sb_phys = sb_phy_addr; 1098cc875c2eSYuval Mintz 10990d956e8aSYuval Mintz /* Set the pointer to the AEU descriptors */ 11000d956e8aSYuval Mintz sb_info->p_aeu_desc = aeu_descs; 11010d956e8aSYuval Mintz 11020d956e8aSYuval Mintz /* Calculate Parity Masks */ 11030d956e8aSYuval Mintz memset(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS); 11040d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 11050d956e8aSYuval Mintz /* j is array index, k is bit index */ 11060d956e8aSYuval Mintz for (j = 0, k = 0; k < 32; j++) { 11070d956e8aSYuval Mintz unsigned int flags = aeu_descs[i].bits[j].flags; 11080d956e8aSYuval Mintz 11090d956e8aSYuval Mintz if (flags & ATTENTION_PARITY) 11100d956e8aSYuval Mintz sb_info->parity_mask[i] |= 1 << k; 11110d956e8aSYuval Mintz 11120d956e8aSYuval Mintz k += ATTENTION_LENGTH(flags); 11130d956e8aSYuval Mintz } 11140d956e8aSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 11150d956e8aSYuval Mintz "Attn Mask [Reg %d]: 0x%08x\n", 11160d956e8aSYuval Mintz i, sb_info->parity_mask[i]); 11170d956e8aSYuval Mintz } 11180d956e8aSYuval Mintz 1119cc875c2eSYuval Mintz /* Set the address of cleanup for the mcp attention */ 1120cc875c2eSYuval Mintz sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) + 1121cc875c2eSYuval Mintz MISC_REG_AEU_GENERAL_ATTN_0; 1122cc875c2eSYuval Mintz 1123cc875c2eSYuval Mintz qed_int_sb_attn_setup(p_hwfn, p_ptt); 1124cc875c2eSYuval Mintz } 1125cc875c2eSYuval Mintz 1126cc875c2eSYuval Mintz static int qed_int_sb_attn_alloc(struct qed_hwfn *p_hwfn, 1127cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1128cc875c2eSYuval Mintz { 1129cc875c2eSYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 1130cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb; 1131cc875c2eSYuval Mintz dma_addr_t p_phys = 0; 11321a635e48SYuval Mintz void *p_virt; 1133cc875c2eSYuval Mintz 1134cc875c2eSYuval Mintz /* SB struct */ 113560fffb3bSYuval Mintz p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 11362591c280SJoe Perches if (!p_sb) 1137cc875c2eSYuval Mintz return -ENOMEM; 1138cc875c2eSYuval Mintz 1139cc875c2eSYuval Mintz /* SB ring */ 1140cc875c2eSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 1141cc875c2eSYuval Mintz SB_ATTN_ALIGNED_SIZE(p_hwfn), 1142cc875c2eSYuval Mintz &p_phys, GFP_KERNEL); 1143cc875c2eSYuval Mintz 1144cc875c2eSYuval Mintz if (!p_virt) { 1145cc875c2eSYuval Mintz kfree(p_sb); 1146cc875c2eSYuval Mintz return -ENOMEM; 1147cc875c2eSYuval Mintz } 1148cc875c2eSYuval Mintz 1149cc875c2eSYuval Mintz /* Attention setup */ 1150cc875c2eSYuval Mintz p_hwfn->p_sb_attn = p_sb; 1151cc875c2eSYuval Mintz qed_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys); 1152cc875c2eSYuval Mintz 1153cc875c2eSYuval Mintz return 0; 1154cc875c2eSYuval Mintz } 1155cc875c2eSYuval Mintz 1156fe56b9e6SYuval Mintz /* coalescing timeout = timeset << (timer_res + 1) */ 1157fe56b9e6SYuval Mintz #define QED_CAU_DEF_RX_USECS 24 1158fe56b9e6SYuval Mintz #define QED_CAU_DEF_TX_USECS 48 1159fe56b9e6SYuval Mintz 1160fe56b9e6SYuval Mintz void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn, 1161fe56b9e6SYuval Mintz struct cau_sb_entry *p_sb_entry, 11621a635e48SYuval Mintz u8 pf_id, u16 vf_number, u8 vf_valid) 1163fe56b9e6SYuval Mintz { 11644ac801b7SYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 1165fe56b9e6SYuval Mintz u32 cau_state; 1166722003acSSudarsana Reddy Kalluru u8 timer_res; 1167fe56b9e6SYuval Mintz 1168fe56b9e6SYuval Mintz memset(p_sb_entry, 0, sizeof(*p_sb_entry)); 1169fe56b9e6SYuval Mintz 1170fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id); 1171fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number); 1172fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid); 1173fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F); 1174fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F); 1175fe56b9e6SYuval Mintz 1176fe56b9e6SYuval Mintz cau_state = CAU_HC_DISABLE_STATE; 1177fe56b9e6SYuval Mintz 11784ac801b7SYuval Mintz if (cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 1179fe56b9e6SYuval Mintz cau_state = CAU_HC_ENABLE_STATE; 11804ac801b7SYuval Mintz if (!cdev->rx_coalesce_usecs) 11814ac801b7SYuval Mintz cdev->rx_coalesce_usecs = QED_CAU_DEF_RX_USECS; 11824ac801b7SYuval Mintz if (!cdev->tx_coalesce_usecs) 11834ac801b7SYuval Mintz cdev->tx_coalesce_usecs = QED_CAU_DEF_TX_USECS; 1184fe56b9e6SYuval Mintz } 1185fe56b9e6SYuval Mintz 1186722003acSSudarsana Reddy Kalluru /* Coalesce = (timeset << timer-res), timeset is 7bit wide */ 1187722003acSSudarsana Reddy Kalluru if (cdev->rx_coalesce_usecs <= 0x7F) 1188722003acSSudarsana Reddy Kalluru timer_res = 0; 1189722003acSSudarsana Reddy Kalluru else if (cdev->rx_coalesce_usecs <= 0xFF) 1190722003acSSudarsana Reddy Kalluru timer_res = 1; 1191722003acSSudarsana Reddy Kalluru else 1192722003acSSudarsana Reddy Kalluru timer_res = 2; 1193722003acSSudarsana Reddy Kalluru SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 1194722003acSSudarsana Reddy Kalluru 1195722003acSSudarsana Reddy Kalluru if (cdev->tx_coalesce_usecs <= 0x7F) 1196722003acSSudarsana Reddy Kalluru timer_res = 0; 1197722003acSSudarsana Reddy Kalluru else if (cdev->tx_coalesce_usecs <= 0xFF) 1198722003acSSudarsana Reddy Kalluru timer_res = 1; 1199722003acSSudarsana Reddy Kalluru else 1200722003acSSudarsana Reddy Kalluru timer_res = 2; 1201722003acSSudarsana Reddy Kalluru SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 1202722003acSSudarsana Reddy Kalluru 1203fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state); 1204fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state); 1205fe56b9e6SYuval Mintz } 1206fe56b9e6SYuval Mintz 1207fe56b9e6SYuval Mintz void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn, 1208fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1209fe56b9e6SYuval Mintz dma_addr_t sb_phys, 12101a635e48SYuval Mintz u16 igu_sb_id, u16 vf_number, u8 vf_valid) 1211fe56b9e6SYuval Mintz { 1212fe56b9e6SYuval Mintz struct cau_sb_entry sb_entry; 1213fe56b9e6SYuval Mintz 1214fe56b9e6SYuval Mintz qed_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id, 1215fe56b9e6SYuval Mintz vf_number, vf_valid); 1216fe56b9e6SYuval Mintz 1217fe56b9e6SYuval Mintz if (p_hwfn->hw_init_done) { 12180a0c5d3bSYuval Mintz /* Wide-bus, initialize via DMAE */ 12190a0c5d3bSYuval Mintz u64 phys_addr = (u64)sb_phys; 1220fe56b9e6SYuval Mintz 12210a0c5d3bSYuval Mintz qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&phys_addr, 12220a0c5d3bSYuval Mintz CAU_REG_SB_ADDR_MEMORY + 12230a0c5d3bSYuval Mintz igu_sb_id * sizeof(u64), 2, 0); 12240a0c5d3bSYuval Mintz qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&sb_entry, 12250a0c5d3bSYuval Mintz CAU_REG_SB_VAR_MEMORY + 12260a0c5d3bSYuval Mintz igu_sb_id * sizeof(u64), 2, 0); 1227fe56b9e6SYuval Mintz } else { 1228fe56b9e6SYuval Mintz /* Initialize Status Block Address */ 1229fe56b9e6SYuval Mintz STORE_RT_REG_AGG(p_hwfn, 1230fe56b9e6SYuval Mintz CAU_REG_SB_ADDR_MEMORY_RT_OFFSET + 1231fe56b9e6SYuval Mintz igu_sb_id * 2, 1232fe56b9e6SYuval Mintz sb_phys); 1233fe56b9e6SYuval Mintz 1234fe56b9e6SYuval Mintz STORE_RT_REG_AGG(p_hwfn, 1235fe56b9e6SYuval Mintz CAU_REG_SB_VAR_MEMORY_RT_OFFSET + 1236fe56b9e6SYuval Mintz igu_sb_id * 2, 1237fe56b9e6SYuval Mintz sb_entry); 1238fe56b9e6SYuval Mintz } 1239fe56b9e6SYuval Mintz 1240fe56b9e6SYuval Mintz /* Configure pi coalescing if set */ 1241fe56b9e6SYuval Mintz if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 1242b5a9ee7cSAriel Elior u8 num_tc = p_hwfn->hw_info.num_hw_tc; 1243722003acSSudarsana Reddy Kalluru u8 timeset, timer_res; 1244b5a9ee7cSAriel Elior u8 i; 1245fe56b9e6SYuval Mintz 1246722003acSSudarsana Reddy Kalluru /* timeset = (coalesce >> timer-res), timeset is 7bit wide */ 1247722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->rx_coalesce_usecs <= 0x7F) 1248722003acSSudarsana Reddy Kalluru timer_res = 0; 1249722003acSSudarsana Reddy Kalluru else if (p_hwfn->cdev->rx_coalesce_usecs <= 0xFF) 1250722003acSSudarsana Reddy Kalluru timer_res = 1; 1251722003acSSudarsana Reddy Kalluru else 1252722003acSSudarsana Reddy Kalluru timer_res = 2; 1253722003acSSudarsana Reddy Kalluru timeset = (u8)(p_hwfn->cdev->rx_coalesce_usecs >> timer_res); 1254fe56b9e6SYuval Mintz qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI, 12551a635e48SYuval Mintz QED_COAL_RX_STATE_MACHINE, timeset); 1256fe56b9e6SYuval Mintz 1257722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->tx_coalesce_usecs <= 0x7F) 1258722003acSSudarsana Reddy Kalluru timer_res = 0; 1259722003acSSudarsana Reddy Kalluru else if (p_hwfn->cdev->tx_coalesce_usecs <= 0xFF) 1260722003acSSudarsana Reddy Kalluru timer_res = 1; 1261722003acSSudarsana Reddy Kalluru else 1262722003acSSudarsana Reddy Kalluru timer_res = 2; 1263722003acSSudarsana Reddy Kalluru timeset = (u8)(p_hwfn->cdev->tx_coalesce_usecs >> timer_res); 1264fe56b9e6SYuval Mintz for (i = 0; i < num_tc; i++) { 1265fe56b9e6SYuval Mintz qed_int_cau_conf_pi(p_hwfn, p_ptt, 1266fe56b9e6SYuval Mintz igu_sb_id, TX_PI(i), 1267fe56b9e6SYuval Mintz QED_COAL_TX_STATE_MACHINE, 1268fe56b9e6SYuval Mintz timeset); 1269fe56b9e6SYuval Mintz } 1270fe56b9e6SYuval Mintz } 1271fe56b9e6SYuval Mintz } 1272fe56b9e6SYuval Mintz 1273fe56b9e6SYuval Mintz void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn, 1274fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1275fe56b9e6SYuval Mintz u16 igu_sb_id, 1276fe56b9e6SYuval Mintz u32 pi_index, 1277fe56b9e6SYuval Mintz enum qed_coalescing_fsm coalescing_fsm, 1278fe56b9e6SYuval Mintz u8 timeset) 1279fe56b9e6SYuval Mintz { 1280fe56b9e6SYuval Mintz struct cau_pi_entry pi_entry; 12811a635e48SYuval Mintz u32 sb_offset, pi_offset; 1282fe56b9e6SYuval Mintz 12831408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 12841408cc1fSYuval Mintz return; 12851408cc1fSYuval Mintz 1286fe56b9e6SYuval Mintz sb_offset = igu_sb_id * PIS_PER_SB; 1287fe56b9e6SYuval Mintz memset(&pi_entry, 0, sizeof(struct cau_pi_entry)); 1288fe56b9e6SYuval Mintz 1289fe56b9e6SYuval Mintz SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset); 1290fe56b9e6SYuval Mintz if (coalescing_fsm == QED_COAL_RX_STATE_MACHINE) 1291fe56b9e6SYuval Mintz SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0); 1292fe56b9e6SYuval Mintz else 1293fe56b9e6SYuval Mintz SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1); 1294fe56b9e6SYuval Mintz 1295fe56b9e6SYuval Mintz pi_offset = sb_offset + pi_index; 1296fe56b9e6SYuval Mintz if (p_hwfn->hw_init_done) { 1297fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 1298fe56b9e6SYuval Mintz CAU_REG_PI_MEMORY + pi_offset * sizeof(u32), 1299fe56b9e6SYuval Mintz *((u32 *)&(pi_entry))); 1300fe56b9e6SYuval Mintz } else { 1301fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, 1302fe56b9e6SYuval Mintz CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset, 1303fe56b9e6SYuval Mintz *((u32 *)&(pi_entry))); 1304fe56b9e6SYuval Mintz } 1305fe56b9e6SYuval Mintz } 1306fe56b9e6SYuval Mintz 1307fe56b9e6SYuval Mintz void qed_int_sb_setup(struct qed_hwfn *p_hwfn, 13081a635e48SYuval Mintz struct qed_ptt *p_ptt, struct qed_sb_info *sb_info) 1309fe56b9e6SYuval Mintz { 1310fe56b9e6SYuval Mintz /* zero status block and ack counter */ 1311fe56b9e6SYuval Mintz sb_info->sb_ack = 0; 1312fe56b9e6SYuval Mintz memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 1313fe56b9e6SYuval Mintz 13141408cc1fSYuval Mintz if (IS_PF(p_hwfn->cdev)) 1315fe56b9e6SYuval Mintz qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys, 1316fe56b9e6SYuval Mintz sb_info->igu_sb_id, 0, 0); 1317fe56b9e6SYuval Mintz } 1318fe56b9e6SYuval Mintz 1319fe56b9e6SYuval Mintz /** 1320fe56b9e6SYuval Mintz * @brief qed_get_igu_sb_id - given a sw sb_id return the 1321fe56b9e6SYuval Mintz * igu_sb_id 1322fe56b9e6SYuval Mintz * 1323fe56b9e6SYuval Mintz * @param p_hwfn 1324fe56b9e6SYuval Mintz * @param sb_id 1325fe56b9e6SYuval Mintz * 1326fe56b9e6SYuval Mintz * @return u16 1327fe56b9e6SYuval Mintz */ 13281a635e48SYuval Mintz static u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id) 1329fe56b9e6SYuval Mintz { 1330fe56b9e6SYuval Mintz u16 igu_sb_id; 1331fe56b9e6SYuval Mintz 1332fe56b9e6SYuval Mintz /* Assuming continuous set of IGU SBs dedicated for given PF */ 1333fe56b9e6SYuval Mintz if (sb_id == QED_SP_SB_ID) 1334fe56b9e6SYuval Mintz igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id; 13351408cc1fSYuval Mintz else if (IS_PF(p_hwfn->cdev)) 1336fe56b9e6SYuval Mintz igu_sb_id = sb_id + p_hwfn->hw_info.p_igu_info->igu_base_sb; 13371408cc1fSYuval Mintz else 13381408cc1fSYuval Mintz igu_sb_id = qed_vf_get_igu_sb_id(p_hwfn, sb_id); 1339fe56b9e6SYuval Mintz 1340525ef5c0SYuval Mintz if (sb_id == QED_SP_SB_ID) 1341525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1342525ef5c0SYuval Mintz "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id); 1343525ef5c0SYuval Mintz else 1344525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1345525ef5c0SYuval Mintz "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id); 1346fe56b9e6SYuval Mintz 1347fe56b9e6SYuval Mintz return igu_sb_id; 1348fe56b9e6SYuval Mintz } 1349fe56b9e6SYuval Mintz 1350fe56b9e6SYuval Mintz int qed_int_sb_init(struct qed_hwfn *p_hwfn, 1351fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1352fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 13531a635e48SYuval Mintz void *sb_virt_addr, dma_addr_t sb_phy_addr, u16 sb_id) 1354fe56b9e6SYuval Mintz { 1355fe56b9e6SYuval Mintz sb_info->sb_virt = sb_virt_addr; 1356fe56b9e6SYuval Mintz sb_info->sb_phys = sb_phy_addr; 1357fe56b9e6SYuval Mintz 1358fe56b9e6SYuval Mintz sb_info->igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id); 1359fe56b9e6SYuval Mintz 1360fe56b9e6SYuval Mintz if (sb_id != QED_SP_SB_ID) { 1361fe56b9e6SYuval Mintz p_hwfn->sbs_info[sb_id] = sb_info; 1362fe56b9e6SYuval Mintz p_hwfn->num_sbs++; 1363fe56b9e6SYuval Mintz } 1364fe56b9e6SYuval Mintz 1365fe56b9e6SYuval Mintz sb_info->cdev = p_hwfn->cdev; 1366fe56b9e6SYuval Mintz 1367fe56b9e6SYuval Mintz /* The igu address will hold the absolute address that needs to be 1368fe56b9e6SYuval Mintz * written to for a specific status block 1369fe56b9e6SYuval Mintz */ 13701408cc1fSYuval Mintz if (IS_PF(p_hwfn->cdev)) { 1371fe56b9e6SYuval Mintz sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 1372fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 1373fe56b9e6SYuval Mintz (sb_info->igu_sb_id << 3); 13741408cc1fSYuval Mintz } else { 13751408cc1fSYuval Mintz sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 13761408cc1fSYuval Mintz PXP_VF_BAR0_START_IGU + 13771408cc1fSYuval Mintz ((IGU_CMD_INT_ACK_BASE + 13781408cc1fSYuval Mintz sb_info->igu_sb_id) << 3); 13791408cc1fSYuval Mintz } 1380fe56b9e6SYuval Mintz 1381fe56b9e6SYuval Mintz sb_info->flags |= QED_SB_INFO_INIT; 1382fe56b9e6SYuval Mintz 1383fe56b9e6SYuval Mintz qed_int_sb_setup(p_hwfn, p_ptt, sb_info); 1384fe56b9e6SYuval Mintz 1385fe56b9e6SYuval Mintz return 0; 1386fe56b9e6SYuval Mintz } 1387fe56b9e6SYuval Mintz 1388fe56b9e6SYuval Mintz int qed_int_sb_release(struct qed_hwfn *p_hwfn, 13891a635e48SYuval Mintz struct qed_sb_info *sb_info, u16 sb_id) 1390fe56b9e6SYuval Mintz { 1391fe56b9e6SYuval Mintz if (sb_id == QED_SP_SB_ID) { 1392fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Do Not free sp sb using this function"); 1393fe56b9e6SYuval Mintz return -EINVAL; 1394fe56b9e6SYuval Mintz } 1395fe56b9e6SYuval Mintz 1396fe56b9e6SYuval Mintz /* zero status block and ack counter */ 1397fe56b9e6SYuval Mintz sb_info->sb_ack = 0; 1398fe56b9e6SYuval Mintz memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 1399fe56b9e6SYuval Mintz 14004ac801b7SYuval Mintz if (p_hwfn->sbs_info[sb_id] != NULL) { 1401fe56b9e6SYuval Mintz p_hwfn->sbs_info[sb_id] = NULL; 1402fe56b9e6SYuval Mintz p_hwfn->num_sbs--; 14034ac801b7SYuval Mintz } 1404fe56b9e6SYuval Mintz 1405fe56b9e6SYuval Mintz return 0; 1406fe56b9e6SYuval Mintz } 1407fe56b9e6SYuval Mintz 1408fe56b9e6SYuval Mintz static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn) 1409fe56b9e6SYuval Mintz { 1410fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb; 1411fe56b9e6SYuval Mintz 14124ac801b7SYuval Mintz if (!p_sb) 14134ac801b7SYuval Mintz return; 14144ac801b7SYuval Mintz 1415fe56b9e6SYuval Mintz if (p_sb->sb_info.sb_virt) 1416fe56b9e6SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1417fe56b9e6SYuval Mintz SB_ALIGNED_SIZE(p_hwfn), 1418fe56b9e6SYuval Mintz p_sb->sb_info.sb_virt, 1419fe56b9e6SYuval Mintz p_sb->sb_info.sb_phys); 1420fe56b9e6SYuval Mintz kfree(p_sb); 14213587cb87STomer Tayar p_hwfn->p_sp_sb = NULL; 1422fe56b9e6SYuval Mintz } 1423fe56b9e6SYuval Mintz 14241a635e48SYuval Mintz static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1425fe56b9e6SYuval Mintz { 1426fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sb; 1427fe56b9e6SYuval Mintz dma_addr_t p_phys = 0; 1428fe56b9e6SYuval Mintz void *p_virt; 1429fe56b9e6SYuval Mintz 1430fe56b9e6SYuval Mintz /* SB struct */ 143160fffb3bSYuval Mintz p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 14322591c280SJoe Perches if (!p_sb) 1433fe56b9e6SYuval Mintz return -ENOMEM; 1434fe56b9e6SYuval Mintz 1435fe56b9e6SYuval Mintz /* SB ring */ 1436fe56b9e6SYuval Mintz p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1437fe56b9e6SYuval Mintz SB_ALIGNED_SIZE(p_hwfn), 1438fe56b9e6SYuval Mintz &p_phys, GFP_KERNEL); 1439fe56b9e6SYuval Mintz if (!p_virt) { 1440fe56b9e6SYuval Mintz kfree(p_sb); 1441fe56b9e6SYuval Mintz return -ENOMEM; 1442fe56b9e6SYuval Mintz } 1443fe56b9e6SYuval Mintz 1444fe56b9e6SYuval Mintz /* Status Block setup */ 1445fe56b9e6SYuval Mintz p_hwfn->p_sp_sb = p_sb; 1446fe56b9e6SYuval Mintz qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt, 1447fe56b9e6SYuval Mintz p_phys, QED_SP_SB_ID); 1448fe56b9e6SYuval Mintz 1449fe56b9e6SYuval Mintz memset(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr)); 1450fe56b9e6SYuval Mintz 1451fe56b9e6SYuval Mintz return 0; 1452fe56b9e6SYuval Mintz } 1453fe56b9e6SYuval Mintz 1454fe56b9e6SYuval Mintz int qed_int_register_cb(struct qed_hwfn *p_hwfn, 1455fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb, 14561a635e48SYuval Mintz void *cookie, u8 *sb_idx, __le16 **p_fw_cons) 1457fe56b9e6SYuval Mintz { 1458fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 14594ac801b7SYuval Mintz int rc = -ENOMEM; 1460fe56b9e6SYuval Mintz u8 pi; 1461fe56b9e6SYuval Mintz 1462fe56b9e6SYuval Mintz /* Look for a free index */ 1463fe56b9e6SYuval Mintz for (pi = 0; pi < ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) { 14644ac801b7SYuval Mintz if (p_sp_sb->pi_info_arr[pi].comp_cb) 14654ac801b7SYuval Mintz continue; 14664ac801b7SYuval Mintz 1467fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb; 1468fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].cookie = cookie; 1469fe56b9e6SYuval Mintz *sb_idx = pi; 1470fe56b9e6SYuval Mintz *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi]; 14714ac801b7SYuval Mintz rc = 0; 1472fe56b9e6SYuval Mintz break; 1473fe56b9e6SYuval Mintz } 1474fe56b9e6SYuval Mintz 14754ac801b7SYuval Mintz return rc; 1476fe56b9e6SYuval Mintz } 1477fe56b9e6SYuval Mintz 1478fe56b9e6SYuval Mintz int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi) 1479fe56b9e6SYuval Mintz { 1480fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 1481fe56b9e6SYuval Mintz 14824ac801b7SYuval Mintz if (p_sp_sb->pi_info_arr[pi].comp_cb == NULL) 14834ac801b7SYuval Mintz return -ENOMEM; 14844ac801b7SYuval Mintz 1485fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].comp_cb = NULL; 1486fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].cookie = NULL; 1487fe56b9e6SYuval Mintz 14884ac801b7SYuval Mintz return 0; 1489fe56b9e6SYuval Mintz } 1490fe56b9e6SYuval Mintz 1491fe56b9e6SYuval Mintz u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn) 1492fe56b9e6SYuval Mintz { 1493fe56b9e6SYuval Mintz return p_hwfn->p_sp_sb->sb_info.igu_sb_id; 1494fe56b9e6SYuval Mintz } 1495fe56b9e6SYuval Mintz 1496fe56b9e6SYuval Mintz void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn, 14971a635e48SYuval Mintz struct qed_ptt *p_ptt, enum qed_int_mode int_mode) 1498fe56b9e6SYuval Mintz { 1499cc875c2eSYuval Mintz u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN; 1500fe56b9e6SYuval Mintz 1501fe56b9e6SYuval Mintz p_hwfn->cdev->int_mode = int_mode; 1502fe56b9e6SYuval Mintz switch (p_hwfn->cdev->int_mode) { 1503fe56b9e6SYuval Mintz case QED_INT_MODE_INTA: 1504fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN; 1505fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 1506fe56b9e6SYuval Mintz break; 1507fe56b9e6SYuval Mintz 1508fe56b9e6SYuval Mintz case QED_INT_MODE_MSI: 1509fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 1510fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 1511fe56b9e6SYuval Mintz break; 1512fe56b9e6SYuval Mintz 1513fe56b9e6SYuval Mintz case QED_INT_MODE_MSIX: 1514fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 1515fe56b9e6SYuval Mintz break; 1516fe56b9e6SYuval Mintz case QED_INT_MODE_POLL: 1517fe56b9e6SYuval Mintz break; 1518fe56b9e6SYuval Mintz } 1519fe56b9e6SYuval Mintz 1520fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf); 1521fe56b9e6SYuval Mintz } 1522fe56b9e6SYuval Mintz 15238f16bc97SSudarsana Kalluru int qed_int_igu_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 1524fe56b9e6SYuval Mintz enum qed_int_mode int_mode) 1525fe56b9e6SYuval Mintz { 1526fea24857SColin Ian King int rc = 0; 1527fe56b9e6SYuval Mintz 15280d956e8aSYuval Mintz /* Configure AEU signal change to produce attentions */ 15290d956e8aSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0); 1530cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff); 1531cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff); 15320d956e8aSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff); 1533cc875c2eSYuval Mintz 1534fe56b9e6SYuval Mintz /* Flush the writes to IGU */ 1535fe56b9e6SYuval Mintz mmiowb(); 1536cc875c2eSYuval Mintz 1537cc875c2eSYuval Mintz /* Unmask AEU signals toward IGU */ 1538cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff); 15398f16bc97SSudarsana Kalluru if ((int_mode != QED_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) { 15408f16bc97SSudarsana Kalluru rc = qed_slowpath_irq_req(p_hwfn); 15411a635e48SYuval Mintz if (rc) { 15428f16bc97SSudarsana Kalluru DP_NOTICE(p_hwfn, "Slowpath IRQ request failed\n"); 15438f16bc97SSudarsana Kalluru return -EINVAL; 15448f16bc97SSudarsana Kalluru } 15458f16bc97SSudarsana Kalluru p_hwfn->b_int_requested = true; 15468f16bc97SSudarsana Kalluru } 15478f16bc97SSudarsana Kalluru /* Enable interrupt Generation */ 15488f16bc97SSudarsana Kalluru qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode); 15498f16bc97SSudarsana Kalluru p_hwfn->b_int_enabled = 1; 15508f16bc97SSudarsana Kalluru 15518f16bc97SSudarsana Kalluru return rc; 1552fe56b9e6SYuval Mintz } 1553fe56b9e6SYuval Mintz 15541a635e48SYuval Mintz void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1555fe56b9e6SYuval Mintz { 1556fe56b9e6SYuval Mintz p_hwfn->b_int_enabled = 0; 1557fe56b9e6SYuval Mintz 15581408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 15591408cc1fSYuval Mintz return; 15601408cc1fSYuval Mintz 1561fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0); 1562fe56b9e6SYuval Mintz } 1563fe56b9e6SYuval Mintz 1564fe56b9e6SYuval Mintz #define IGU_CLEANUP_SLEEP_LENGTH (1000) 1565b2b897ebSYuval Mintz static void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn, 1566fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1567b2b897ebSYuval Mintz u32 sb_id, bool cleanup_set, u16 opaque_fid) 1568fe56b9e6SYuval Mintz { 1569b2b897ebSYuval Mintz u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0; 1570fe56b9e6SYuval Mintz u32 pxp_addr = IGU_CMD_INT_ACK_BASE + sb_id; 1571fe56b9e6SYuval Mintz u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH; 1572fe56b9e6SYuval Mintz 1573fe56b9e6SYuval Mintz /* Set the data field */ 1574fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0); 1575fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, 0); 1576fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET); 1577fe56b9e6SYuval Mintz 1578fe56b9e6SYuval Mintz /* Set the control register */ 1579fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr); 1580fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid); 1581fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR); 1582fe56b9e6SYuval Mintz 1583fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data); 1584fe56b9e6SYuval Mintz 1585fe56b9e6SYuval Mintz barrier(); 1586fe56b9e6SYuval Mintz 1587fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl); 1588fe56b9e6SYuval Mintz 1589fe56b9e6SYuval Mintz /* Flush the write to IGU */ 1590fe56b9e6SYuval Mintz mmiowb(); 1591fe56b9e6SYuval Mintz 1592fe56b9e6SYuval Mintz /* calculate where to read the status bit from */ 1593fe56b9e6SYuval Mintz sb_bit = 1 << (sb_id % 32); 1594fe56b9e6SYuval Mintz sb_bit_addr = sb_id / 32 * sizeof(u32); 1595fe56b9e6SYuval Mintz 1596fe56b9e6SYuval Mintz sb_bit_addr += IGU_REG_CLEANUP_STATUS_0; 1597fe56b9e6SYuval Mintz 1598fe56b9e6SYuval Mintz /* Now wait for the command to complete */ 1599fe56b9e6SYuval Mintz do { 1600fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, sb_bit_addr); 1601fe56b9e6SYuval Mintz 1602fe56b9e6SYuval Mintz if ((val & sb_bit) == (cleanup_set ? sb_bit : 0)) 1603fe56b9e6SYuval Mintz break; 1604fe56b9e6SYuval Mintz 1605fe56b9e6SYuval Mintz usleep_range(5000, 10000); 1606fe56b9e6SYuval Mintz } while (--sleep_cnt); 1607fe56b9e6SYuval Mintz 1608fe56b9e6SYuval Mintz if (!sleep_cnt) 1609fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 1610fe56b9e6SYuval Mintz "Timeout waiting for clear status 0x%08x [for sb %d]\n", 1611fe56b9e6SYuval Mintz val, sb_id); 1612fe56b9e6SYuval Mintz } 1613fe56b9e6SYuval Mintz 1614fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn, 1615fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1616b2b897ebSYuval Mintz u32 sb_id, u16 opaque, bool b_set) 1617fe56b9e6SYuval Mintz { 1618b2b897ebSYuval Mintz int pi, i; 1619fe56b9e6SYuval Mintz 1620fe56b9e6SYuval Mintz /* Set */ 1621fe56b9e6SYuval Mintz if (b_set) 1622fe56b9e6SYuval Mintz qed_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 1, opaque); 1623fe56b9e6SYuval Mintz 1624fe56b9e6SYuval Mintz /* Clear */ 1625fe56b9e6SYuval Mintz qed_int_igu_cleanup_sb(p_hwfn, p_ptt, sb_id, 0, opaque); 1626fe56b9e6SYuval Mintz 1627b2b897ebSYuval Mintz /* Wait for the IGU SB to cleanup */ 1628b2b897ebSYuval Mintz for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) { 1629b2b897ebSYuval Mintz u32 val; 1630b2b897ebSYuval Mintz 1631b2b897ebSYuval Mintz val = qed_rd(p_hwfn, p_ptt, 1632b2b897ebSYuval Mintz IGU_REG_WRITE_DONE_PENDING + ((sb_id / 32) * 4)); 1633b2b897ebSYuval Mintz if (val & (1 << (sb_id % 32))) 1634b2b897ebSYuval Mintz usleep_range(10, 20); 1635b2b897ebSYuval Mintz else 1636b2b897ebSYuval Mintz break; 1637b2b897ebSYuval Mintz } 1638b2b897ebSYuval Mintz if (i == IGU_CLEANUP_SLEEP_LENGTH) 1639b2b897ebSYuval Mintz DP_NOTICE(p_hwfn, 1640b2b897ebSYuval Mintz "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n", 1641b2b897ebSYuval Mintz sb_id); 1642b2b897ebSYuval Mintz 1643fe56b9e6SYuval Mintz /* Clear the CAU for the SB */ 1644fe56b9e6SYuval Mintz for (pi = 0; pi < 12; pi++) 1645fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 1646fe56b9e6SYuval Mintz CAU_REG_PI_MEMORY + (sb_id * 12 + pi) * 4, 0); 1647fe56b9e6SYuval Mintz } 1648fe56b9e6SYuval Mintz 1649fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn, 1650fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1651b2b897ebSYuval Mintz bool b_set, bool b_slowpath) 1652fe56b9e6SYuval Mintz { 1653fe56b9e6SYuval Mintz u32 igu_base_sb = p_hwfn->hw_info.p_igu_info->igu_base_sb; 1654fe56b9e6SYuval Mintz u32 igu_sb_cnt = p_hwfn->hw_info.p_igu_info->igu_sb_cnt; 1655b2b897ebSYuval Mintz u32 sb_id = 0, val = 0; 1656fe56b9e6SYuval Mintz 1657fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION); 1658fe56b9e6SYuval Mintz val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN; 1659fe56b9e6SYuval Mintz val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN; 1660fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val); 1661fe56b9e6SYuval Mintz 1662fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1663fe56b9e6SYuval Mintz "IGU cleaning SBs [%d,...,%d]\n", 1664fe56b9e6SYuval Mintz igu_base_sb, igu_base_sb + igu_sb_cnt - 1); 1665fe56b9e6SYuval Mintz 1666fe56b9e6SYuval Mintz for (sb_id = igu_base_sb; sb_id < igu_base_sb + igu_sb_cnt; sb_id++) 1667fe56b9e6SYuval Mintz qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id, 1668fe56b9e6SYuval Mintz p_hwfn->hw_info.opaque_fid, 1669fe56b9e6SYuval Mintz b_set); 1670fe56b9e6SYuval Mintz 1671b2b897ebSYuval Mintz if (!b_slowpath) 1672b2b897ebSYuval Mintz return; 1673b2b897ebSYuval Mintz 1674fe56b9e6SYuval Mintz sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id; 1675fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1676fe56b9e6SYuval Mintz "IGU cleaning slowpath SB [%d]\n", sb_id); 1677fe56b9e6SYuval Mintz qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, sb_id, 1678b2b897ebSYuval Mintz p_hwfn->hw_info.opaque_fid, b_set); 1679fe56b9e6SYuval Mintz } 1680fe56b9e6SYuval Mintz 16814ac801b7SYuval Mintz static u32 qed_int_igu_read_cam_block(struct qed_hwfn *p_hwfn, 16821a635e48SYuval Mintz struct qed_ptt *p_ptt, u16 sb_id) 16834ac801b7SYuval Mintz { 16844ac801b7SYuval Mintz u32 val = qed_rd(p_hwfn, p_ptt, 16851a635e48SYuval Mintz IGU_REG_MAPPING_MEMORY + sizeof(u32) * sb_id); 16864ac801b7SYuval Mintz struct qed_igu_block *p_block; 16874ac801b7SYuval Mintz 16884ac801b7SYuval Mintz p_block = &p_hwfn->hw_info.p_igu_info->igu_map.igu_blocks[sb_id]; 16894ac801b7SYuval Mintz 16904ac801b7SYuval Mintz /* stop scanning when hit first invalid PF entry */ 16914ac801b7SYuval Mintz if (!GET_FIELD(val, IGU_MAPPING_LINE_VALID) && 16924ac801b7SYuval Mintz GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID)) 16934ac801b7SYuval Mintz goto out; 16944ac801b7SYuval Mintz 16954ac801b7SYuval Mintz /* Fill the block information */ 16964ac801b7SYuval Mintz p_block->status = QED_IGU_STATUS_VALID; 16974ac801b7SYuval Mintz p_block->function_id = GET_FIELD(val, 16984ac801b7SYuval Mintz IGU_MAPPING_LINE_FUNCTION_NUMBER); 16994ac801b7SYuval Mintz p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID); 17004ac801b7SYuval Mintz p_block->vector_number = GET_FIELD(val, 17014ac801b7SYuval Mintz IGU_MAPPING_LINE_VECTOR_NUMBER); 17024ac801b7SYuval Mintz 17034ac801b7SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 17044ac801b7SYuval Mintz "IGU_BLOCK: [SB 0x%04x, Value in CAM 0x%08x] func_id = %d is_pf = %d vector_num = 0x%x\n", 17054ac801b7SYuval Mintz sb_id, val, p_block->function_id, 17064ac801b7SYuval Mintz p_block->is_pf, p_block->vector_number); 17074ac801b7SYuval Mintz 17084ac801b7SYuval Mintz out: 17094ac801b7SYuval Mintz return val; 17104ac801b7SYuval Mintz } 17114ac801b7SYuval Mintz 17121a635e48SYuval Mintz int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1713fe56b9e6SYuval Mintz { 1714fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 17151408cc1fSYuval Mintz u32 val, min_vf = 0, max_vf = 0; 17161408cc1fSYuval Mintz u16 sb_id, last_iov_sb_id = 0; 1717fe56b9e6SYuval Mintz struct qed_igu_block *blk; 1718fe56b9e6SYuval Mintz u16 prev_sb_id = 0xFF; 1719fe56b9e6SYuval Mintz 172060fffb3bSYuval Mintz p_hwfn->hw_info.p_igu_info = kzalloc(sizeof(*p_igu_info), GFP_KERNEL); 1721fe56b9e6SYuval Mintz if (!p_hwfn->hw_info.p_igu_info) 1722fe56b9e6SYuval Mintz return -ENOMEM; 1723fe56b9e6SYuval Mintz 1724fe56b9e6SYuval Mintz p_igu_info = p_hwfn->hw_info.p_igu_info; 1725fe56b9e6SYuval Mintz 17261408cc1fSYuval Mintz /* Initialize base sb / sb cnt for PFs and VFs */ 1727fe56b9e6SYuval Mintz p_igu_info->igu_base_sb = 0xffff; 1728fe56b9e6SYuval Mintz p_igu_info->igu_sb_cnt = 0; 1729fe56b9e6SYuval Mintz p_igu_info->igu_dsb_id = 0xffff; 1730fe56b9e6SYuval Mintz p_igu_info->igu_base_sb_iov = 0xffff; 1731fe56b9e6SYuval Mintz 17321408cc1fSYuval Mintz if (p_hwfn->cdev->p_iov_info) { 17331408cc1fSYuval Mintz struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info; 17341408cc1fSYuval Mintz 17351408cc1fSYuval Mintz min_vf = p_iov->first_vf_in_pf; 17361408cc1fSYuval Mintz max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs; 17371408cc1fSYuval Mintz } 17381408cc1fSYuval Mintz 1739fe56b9e6SYuval Mintz for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); 1740fe56b9e6SYuval Mintz sb_id++) { 1741fe56b9e6SYuval Mintz blk = &p_igu_info->igu_map.igu_blocks[sb_id]; 1742fe56b9e6SYuval Mintz 17434ac801b7SYuval Mintz val = qed_int_igu_read_cam_block(p_hwfn, p_ptt, sb_id); 1744fe56b9e6SYuval Mintz 1745fe56b9e6SYuval Mintz /* stop scanning when hit first invalid PF entry */ 1746fe56b9e6SYuval Mintz if (!GET_FIELD(val, IGU_MAPPING_LINE_VALID) && 1747fe56b9e6SYuval Mintz GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID)) 1748fe56b9e6SYuval Mintz break; 1749fe56b9e6SYuval Mintz 1750fe56b9e6SYuval Mintz if (blk->is_pf) { 1751fe56b9e6SYuval Mintz if (blk->function_id == p_hwfn->rel_pf_id) { 1752fe56b9e6SYuval Mintz blk->status |= QED_IGU_STATUS_PF; 1753fe56b9e6SYuval Mintz 1754fe56b9e6SYuval Mintz if (blk->vector_number == 0) { 1755fe56b9e6SYuval Mintz if (p_igu_info->igu_dsb_id == 0xffff) 1756fe56b9e6SYuval Mintz p_igu_info->igu_dsb_id = sb_id; 1757fe56b9e6SYuval Mintz } else { 1758fe56b9e6SYuval Mintz if (p_igu_info->igu_base_sb == 1759fe56b9e6SYuval Mintz 0xffff) { 1760fe56b9e6SYuval Mintz p_igu_info->igu_base_sb = sb_id; 1761fe56b9e6SYuval Mintz } else if (prev_sb_id != sb_id - 1) { 1762fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn->cdev, 1763fe56b9e6SYuval Mintz "consecutive igu vectors for HWFN %x broken", 1764fe56b9e6SYuval Mintz p_hwfn->rel_pf_id); 1765fe56b9e6SYuval Mintz break; 1766fe56b9e6SYuval Mintz } 1767fe56b9e6SYuval Mintz prev_sb_id = sb_id; 1768fe56b9e6SYuval Mintz /* we don't count the default */ 1769fe56b9e6SYuval Mintz (p_igu_info->igu_sb_cnt)++; 1770fe56b9e6SYuval Mintz } 1771fe56b9e6SYuval Mintz } 17721408cc1fSYuval Mintz } else { 17731408cc1fSYuval Mintz if ((blk->function_id >= min_vf) && 17741408cc1fSYuval Mintz (blk->function_id < max_vf)) { 17751408cc1fSYuval Mintz /* Available for VFs of this PF */ 17761408cc1fSYuval Mintz if (p_igu_info->igu_base_sb_iov == 0xffff) { 17771408cc1fSYuval Mintz p_igu_info->igu_base_sb_iov = sb_id; 17781408cc1fSYuval Mintz } else if (last_iov_sb_id != sb_id - 1) { 17791408cc1fSYuval Mintz if (!val) { 17801408cc1fSYuval Mintz DP_VERBOSE(p_hwfn->cdev, 17811408cc1fSYuval Mintz NETIF_MSG_INTR, 17821408cc1fSYuval Mintz "First uninitialized IGU CAM entry at index 0x%04x\n", 17831408cc1fSYuval Mintz sb_id); 17841408cc1fSYuval Mintz } else { 17851408cc1fSYuval Mintz DP_NOTICE(p_hwfn->cdev, 17861408cc1fSYuval Mintz "Consecutive igu vectors for HWFN %x vfs is broken [jumps from %04x to %04x]\n", 17871408cc1fSYuval Mintz p_hwfn->rel_pf_id, 17881408cc1fSYuval Mintz last_iov_sb_id, 17891408cc1fSYuval Mintz sb_id); } 17901408cc1fSYuval Mintz break; 17911408cc1fSYuval Mintz } 17921408cc1fSYuval Mintz blk->status |= QED_IGU_STATUS_FREE; 17931408cc1fSYuval Mintz p_hwfn->hw_info.p_igu_info->free_blks++; 17941408cc1fSYuval Mintz last_iov_sb_id = sb_id; 1795fe56b9e6SYuval Mintz } 1796fe56b9e6SYuval Mintz } 17971408cc1fSYuval Mintz } 17985a1f965aSMintz, Yuval 17995a1f965aSMintz, Yuval /* There's a possibility the igu_sb_cnt_iov doesn't properly reflect 18005a1f965aSMintz, Yuval * the number of VF SBs [especially for first VF on engine, as we can't 18018ac1ed79SJoe Perches * differentiate between empty entries and its entries]. 18025a1f965aSMintz, Yuval * Since we don't really support more SBs than VFs today, prevent any 18035a1f965aSMintz, Yuval * such configuration by sanitizing the number of SBs to equal the 18045a1f965aSMintz, Yuval * number of VFs. 18055a1f965aSMintz, Yuval */ 18065a1f965aSMintz, Yuval if (IS_PF_SRIOV(p_hwfn)) { 18075a1f965aSMintz, Yuval u16 total_vfs = p_hwfn->cdev->p_iov_info->total_vfs; 18085a1f965aSMintz, Yuval 18095a1f965aSMintz, Yuval if (total_vfs < p_igu_info->free_blks) { 18105a1f965aSMintz, Yuval DP_VERBOSE(p_hwfn, 18115a1f965aSMintz, Yuval (NETIF_MSG_INTR | QED_MSG_IOV), 18125a1f965aSMintz, Yuval "Limiting number of SBs for IOV - %04x --> %04x\n", 18135a1f965aSMintz, Yuval p_igu_info->free_blks, 18145a1f965aSMintz, Yuval p_hwfn->cdev->p_iov_info->total_vfs); 18155a1f965aSMintz, Yuval p_igu_info->free_blks = total_vfs; 18165a1f965aSMintz, Yuval } else if (total_vfs > p_igu_info->free_blks) { 18175a1f965aSMintz, Yuval DP_NOTICE(p_hwfn, 18185a1f965aSMintz, Yuval "IGU has only %04x SBs for VFs while the device has %04x VFs\n", 18195a1f965aSMintz, Yuval p_igu_info->free_blks, total_vfs); 18205a1f965aSMintz, Yuval return -EINVAL; 18215a1f965aSMintz, Yuval } 18225a1f965aSMintz, Yuval } 18231408cc1fSYuval Mintz p_igu_info->igu_sb_cnt_iov = p_igu_info->free_blks; 1824fe56b9e6SYuval Mintz 18251408cc1fSYuval Mintz DP_VERBOSE( 18261408cc1fSYuval Mintz p_hwfn, 18271408cc1fSYuval Mintz NETIF_MSG_INTR, 18281408cc1fSYuval Mintz "IGU igu_base_sb=0x%x [IOV 0x%x] igu_sb_cnt=%d [IOV 0x%x] igu_dsb_id=0x%x\n", 1829fe56b9e6SYuval Mintz p_igu_info->igu_base_sb, 18301408cc1fSYuval Mintz p_igu_info->igu_base_sb_iov, 1831fe56b9e6SYuval Mintz p_igu_info->igu_sb_cnt, 18321408cc1fSYuval Mintz p_igu_info->igu_sb_cnt_iov, 1833fe56b9e6SYuval Mintz p_igu_info->igu_dsb_id); 1834fe56b9e6SYuval Mintz 1835fe56b9e6SYuval Mintz if (p_igu_info->igu_base_sb == 0xffff || 1836fe56b9e6SYuval Mintz p_igu_info->igu_dsb_id == 0xffff || 1837fe56b9e6SYuval Mintz p_igu_info->igu_sb_cnt == 0) { 1838fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 1839fe56b9e6SYuval Mintz "IGU CAM returned invalid values igu_base_sb=0x%x igu_sb_cnt=%d igu_dsb_id=0x%x\n", 1840fe56b9e6SYuval Mintz p_igu_info->igu_base_sb, 1841fe56b9e6SYuval Mintz p_igu_info->igu_sb_cnt, 1842fe56b9e6SYuval Mintz p_igu_info->igu_dsb_id); 1843fe56b9e6SYuval Mintz return -EINVAL; 1844fe56b9e6SYuval Mintz } 1845fe56b9e6SYuval Mintz 1846fe56b9e6SYuval Mintz return 0; 1847fe56b9e6SYuval Mintz } 1848fe56b9e6SYuval Mintz 1849fe56b9e6SYuval Mintz /** 1850fe56b9e6SYuval Mintz * @brief Initialize igu runtime registers 1851fe56b9e6SYuval Mintz * 1852fe56b9e6SYuval Mintz * @param p_hwfn 1853fe56b9e6SYuval Mintz */ 1854fe56b9e6SYuval Mintz void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn) 1855fe56b9e6SYuval Mintz { 18561a635e48SYuval Mintz u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN; 1857fe56b9e6SYuval Mintz 1858fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf); 1859fe56b9e6SYuval Mintz } 1860fe56b9e6SYuval Mintz 1861fe56b9e6SYuval Mintz u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn) 1862fe56b9e6SYuval Mintz { 1863fe56b9e6SYuval Mintz u32 lsb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - 1864fe56b9e6SYuval Mintz IGU_CMD_INT_ACK_BASE; 1865fe56b9e6SYuval Mintz u32 msb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - 1866fe56b9e6SYuval Mintz IGU_CMD_INT_ACK_BASE; 18671a635e48SYuval Mintz u32 intr_status_hi = 0, intr_status_lo = 0; 18681a635e48SYuval Mintz u64 intr_status = 0; 1869fe56b9e6SYuval Mintz 1870fe56b9e6SYuval Mintz intr_status_lo = REG_RD(p_hwfn, 1871fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 1872fe56b9e6SYuval Mintz lsb_igu_cmd_addr * 8); 1873fe56b9e6SYuval Mintz intr_status_hi = REG_RD(p_hwfn, 1874fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 1875fe56b9e6SYuval Mintz msb_igu_cmd_addr * 8); 1876fe56b9e6SYuval Mintz intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo; 1877fe56b9e6SYuval Mintz 1878fe56b9e6SYuval Mintz return intr_status; 1879fe56b9e6SYuval Mintz } 1880fe56b9e6SYuval Mintz 1881fe56b9e6SYuval Mintz static void qed_int_sp_dpc_setup(struct qed_hwfn *p_hwfn) 1882fe56b9e6SYuval Mintz { 1883fe56b9e6SYuval Mintz tasklet_init(p_hwfn->sp_dpc, 1884fe56b9e6SYuval Mintz qed_int_sp_dpc, (unsigned long)p_hwfn); 1885fe56b9e6SYuval Mintz p_hwfn->b_sp_dpc_enabled = true; 1886fe56b9e6SYuval Mintz } 1887fe56b9e6SYuval Mintz 1888fe56b9e6SYuval Mintz static int qed_int_sp_dpc_alloc(struct qed_hwfn *p_hwfn) 1889fe56b9e6SYuval Mintz { 189060fffb3bSYuval Mintz p_hwfn->sp_dpc = kmalloc(sizeof(*p_hwfn->sp_dpc), GFP_KERNEL); 1891fe56b9e6SYuval Mintz if (!p_hwfn->sp_dpc) 1892fe56b9e6SYuval Mintz return -ENOMEM; 1893fe56b9e6SYuval Mintz 1894fe56b9e6SYuval Mintz return 0; 1895fe56b9e6SYuval Mintz } 1896fe56b9e6SYuval Mintz 1897fe56b9e6SYuval Mintz static void qed_int_sp_dpc_free(struct qed_hwfn *p_hwfn) 1898fe56b9e6SYuval Mintz { 1899fe56b9e6SYuval Mintz kfree(p_hwfn->sp_dpc); 19003587cb87STomer Tayar p_hwfn->sp_dpc = NULL; 1901fe56b9e6SYuval Mintz } 1902fe56b9e6SYuval Mintz 19031a635e48SYuval Mintz int qed_int_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1904fe56b9e6SYuval Mintz { 1905fe56b9e6SYuval Mintz int rc = 0; 1906fe56b9e6SYuval Mintz 1907fe56b9e6SYuval Mintz rc = qed_int_sp_dpc_alloc(p_hwfn); 190883aeb933SYuval Mintz if (rc) 19092591c280SJoe Perches return rc; 19102591c280SJoe Perches 19112591c280SJoe Perches rc = qed_int_sp_sb_alloc(p_hwfn, p_ptt); 19122591c280SJoe Perches if (rc) 19132591c280SJoe Perches return rc; 19142591c280SJoe Perches 19152591c280SJoe Perches rc = qed_int_sb_attn_alloc(p_hwfn, p_ptt); 191683aeb933SYuval Mintz 1917fe56b9e6SYuval Mintz return rc; 1918fe56b9e6SYuval Mintz } 1919fe56b9e6SYuval Mintz 1920fe56b9e6SYuval Mintz void qed_int_free(struct qed_hwfn *p_hwfn) 1921fe56b9e6SYuval Mintz { 1922fe56b9e6SYuval Mintz qed_int_sp_sb_free(p_hwfn); 1923cc875c2eSYuval Mintz qed_int_sb_attn_free(p_hwfn); 1924fe56b9e6SYuval Mintz qed_int_sp_dpc_free(p_hwfn); 1925fe56b9e6SYuval Mintz } 1926fe56b9e6SYuval Mintz 19271a635e48SYuval Mintz void qed_int_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1928fe56b9e6SYuval Mintz { 19290d956e8aSYuval Mintz qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info); 19300d956e8aSYuval Mintz qed_int_sb_attn_setup(p_hwfn, p_ptt); 1931fe56b9e6SYuval Mintz qed_int_sp_dpc_setup(p_hwfn); 1932fe56b9e6SYuval Mintz } 1933fe56b9e6SYuval Mintz 19344ac801b7SYuval Mintz void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn, 19354ac801b7SYuval Mintz struct qed_sb_cnt_info *p_sb_cnt_info) 1936fe56b9e6SYuval Mintz { 1937fe56b9e6SYuval Mintz struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info; 1938fe56b9e6SYuval Mintz 19394ac801b7SYuval Mintz if (!info || !p_sb_cnt_info) 19404ac801b7SYuval Mintz return; 1941fe56b9e6SYuval Mintz 19424ac801b7SYuval Mintz p_sb_cnt_info->sb_cnt = info->igu_sb_cnt; 19434ac801b7SYuval Mintz p_sb_cnt_info->sb_iov_cnt = info->igu_sb_cnt_iov; 19444ac801b7SYuval Mintz p_sb_cnt_info->sb_free_blk = info->free_blks; 1945fe56b9e6SYuval Mintz } 19468f16bc97SSudarsana Kalluru 19471408cc1fSYuval Mintz u16 qed_int_queue_id_from_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id) 19481408cc1fSYuval Mintz { 19491408cc1fSYuval Mintz struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info; 19501408cc1fSYuval Mintz 19511408cc1fSYuval Mintz /* Determine origin of SB id */ 19521408cc1fSYuval Mintz if ((sb_id >= p_info->igu_base_sb) && 19531408cc1fSYuval Mintz (sb_id < p_info->igu_base_sb + p_info->igu_sb_cnt)) { 19541408cc1fSYuval Mintz return sb_id - p_info->igu_base_sb; 19551408cc1fSYuval Mintz } else if ((sb_id >= p_info->igu_base_sb_iov) && 19561408cc1fSYuval Mintz (sb_id < p_info->igu_base_sb_iov + p_info->igu_sb_cnt_iov)) { 19575a1f965aSMintz, Yuval /* We want the first VF queue to be adjacent to the 19585a1f965aSMintz, Yuval * last PF queue. Since L2 queues can be partial to 19595a1f965aSMintz, Yuval * SBs, we'll use the feature instead. 19605a1f965aSMintz, Yuval */ 19615a1f965aSMintz, Yuval return sb_id - p_info->igu_base_sb_iov + 19625a1f965aSMintz, Yuval FEAT_NUM(p_hwfn, QED_PF_L2_QUE); 19631408cc1fSYuval Mintz } else { 19641408cc1fSYuval Mintz DP_NOTICE(p_hwfn, "SB %d not in range for function\n", sb_id); 19651408cc1fSYuval Mintz return 0; 19661408cc1fSYuval Mintz } 19671408cc1fSYuval Mintz } 19681408cc1fSYuval Mintz 19698f16bc97SSudarsana Kalluru void qed_int_disable_post_isr_release(struct qed_dev *cdev) 19708f16bc97SSudarsana Kalluru { 19718f16bc97SSudarsana Kalluru int i; 19728f16bc97SSudarsana Kalluru 19738f16bc97SSudarsana Kalluru for_each_hwfn(cdev, i) 19748f16bc97SSudarsana Kalluru cdev->hwfns[i].b_int_requested = false; 19758f16bc97SSudarsana Kalluru } 1976722003acSSudarsana Reddy Kalluru 1977722003acSSudarsana Reddy Kalluru int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 1978722003acSSudarsana Reddy Kalluru u8 timer_res, u16 sb_id, bool tx) 1979722003acSSudarsana Reddy Kalluru { 1980722003acSSudarsana Reddy Kalluru struct cau_sb_entry sb_entry; 1981722003acSSudarsana Reddy Kalluru int rc; 1982722003acSSudarsana Reddy Kalluru 1983722003acSSudarsana Reddy Kalluru if (!p_hwfn->hw_init_done) { 1984722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "hardware not initialized yet\n"); 1985722003acSSudarsana Reddy Kalluru return -EINVAL; 1986722003acSSudarsana Reddy Kalluru } 1987722003acSSudarsana Reddy Kalluru 1988722003acSSudarsana Reddy Kalluru rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY + 1989722003acSSudarsana Reddy Kalluru sb_id * sizeof(u64), 1990722003acSSudarsana Reddy Kalluru (u64)(uintptr_t)&sb_entry, 2, 0); 1991722003acSSudarsana Reddy Kalluru if (rc) { 1992722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc); 1993722003acSSudarsana Reddy Kalluru return rc; 1994722003acSSudarsana Reddy Kalluru } 1995722003acSSudarsana Reddy Kalluru 1996722003acSSudarsana Reddy Kalluru if (tx) 1997722003acSSudarsana Reddy Kalluru SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 1998722003acSSudarsana Reddy Kalluru else 1999722003acSSudarsana Reddy Kalluru SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 2000722003acSSudarsana Reddy Kalluru 2001722003acSSudarsana Reddy Kalluru rc = qed_dmae_host2grc(p_hwfn, p_ptt, 2002722003acSSudarsana Reddy Kalluru (u64)(uintptr_t)&sb_entry, 2003722003acSSudarsana Reddy Kalluru CAU_REG_SB_VAR_MEMORY + 2004722003acSSudarsana Reddy Kalluru sb_id * sizeof(u64), 2, 0); 2005722003acSSudarsana Reddy Kalluru if (rc) { 2006722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc); 2007722003acSSudarsana Reddy Kalluru return rc; 2008722003acSSudarsana Reddy Kalluru } 2009722003acSSudarsana Reddy Kalluru 2010722003acSSudarsana Reddy Kalluru return rc; 2011722003acSSudarsana Reddy Kalluru } 2012