1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #include <linux/types.h> 34fe56b9e6SYuval Mintz #include <asm/byteorder.h> 35fe56b9e6SYuval Mintz #include <linux/io.h> 36fe56b9e6SYuval Mintz #include <linux/bitops.h> 37fe56b9e6SYuval Mintz #include <linux/delay.h> 38fe56b9e6SYuval Mintz #include <linux/dma-mapping.h> 39fe56b9e6SYuval Mintz #include <linux/errno.h> 40fe56b9e6SYuval Mintz #include <linux/interrupt.h> 41fe56b9e6SYuval Mintz #include <linux/kernel.h> 42fe56b9e6SYuval Mintz #include <linux/pci.h> 43fe56b9e6SYuval Mintz #include <linux/slab.h> 44fe56b9e6SYuval Mintz #include <linux/string.h> 45fe56b9e6SYuval Mintz #include "qed.h" 46fe56b9e6SYuval Mintz #include "qed_hsi.h" 47fe56b9e6SYuval Mintz #include "qed_hw.h" 48fe56b9e6SYuval Mintz #include "qed_init_ops.h" 49fe56b9e6SYuval Mintz #include "qed_int.h" 50fe56b9e6SYuval Mintz #include "qed_mcp.h" 51fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 52fe56b9e6SYuval Mintz #include "qed_sp.h" 531408cc1fSYuval Mintz #include "qed_sriov.h" 541408cc1fSYuval Mintz #include "qed_vf.h" 55fe56b9e6SYuval Mintz 56fe56b9e6SYuval Mintz struct qed_pi_info { 57fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb; 58fe56b9e6SYuval Mintz void *cookie; 59fe56b9e6SYuval Mintz }; 60fe56b9e6SYuval Mintz 61fe56b9e6SYuval Mintz struct qed_sb_sp_info { 62fe56b9e6SYuval Mintz struct qed_sb_info sb_info; 63fe56b9e6SYuval Mintz 64fe56b9e6SYuval Mintz /* per protocol index data */ 6521dd79e8STomer Tayar struct qed_pi_info pi_info_arr[PIS_PER_SB_E4]; 66fe56b9e6SYuval Mintz }; 67fe56b9e6SYuval Mintz 68ff38577aSYuval Mintz enum qed_attention_type { 69ff38577aSYuval Mintz QED_ATTN_TYPE_ATTN, 70ff38577aSYuval Mintz QED_ATTN_TYPE_PARITY, 71ff38577aSYuval Mintz }; 72ff38577aSYuval Mintz 73cc875c2eSYuval Mintz #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \ 74cc875c2eSYuval Mintz ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn) 75cc875c2eSYuval Mintz 760d956e8aSYuval Mintz struct aeu_invert_reg_bit { 770d956e8aSYuval Mintz char bit_name[30]; 780d956e8aSYuval Mintz 790d956e8aSYuval Mintz #define ATTENTION_PARITY (1 << 0) 800d956e8aSYuval Mintz 810d956e8aSYuval Mintz #define ATTENTION_LENGTH_MASK (0x00000ff0) 820d956e8aSYuval Mintz #define ATTENTION_LENGTH_SHIFT (4) 830d956e8aSYuval Mintz #define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \ 840d956e8aSYuval Mintz ATTENTION_LENGTH_SHIFT) 85a2e7699eSTomer Tayar #define ATTENTION_SINGLE BIT(ATTENTION_LENGTH_SHIFT) 860d956e8aSYuval Mintz #define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY) 870d956e8aSYuval Mintz #define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \ 880d956e8aSYuval Mintz ATTENTION_PARITY) 890d956e8aSYuval Mintz 900d956e8aSYuval Mintz /* Multiple bits start with this offset */ 910d956e8aSYuval Mintz #define ATTENTION_OFFSET_MASK (0x000ff000) 920d956e8aSYuval Mintz #define ATTENTION_OFFSET_SHIFT (12) 93ba36f718SMintz, Yuval 94ba36f718SMintz, Yuval #define ATTENTION_BB_MASK (0x00700000) 95ba36f718SMintz, Yuval #define ATTENTION_BB_SHIFT (20) 96ba36f718SMintz, Yuval #define ATTENTION_BB(value) (value << ATTENTION_BB_SHIFT) 97ba36f718SMintz, Yuval #define ATTENTION_BB_DIFFERENT BIT(23) 98ba36f718SMintz, Yuval 990d956e8aSYuval Mintz unsigned int flags; 100ff38577aSYuval Mintz 101b4149dc7SYuval Mintz /* Callback to call if attention will be triggered */ 102b4149dc7SYuval Mintz int (*cb)(struct qed_hwfn *p_hwfn); 103b4149dc7SYuval Mintz 104ff38577aSYuval Mintz enum block_id block_index; 1050d956e8aSYuval Mintz }; 1060d956e8aSYuval Mintz 1070d956e8aSYuval Mintz struct aeu_invert_reg { 1080d956e8aSYuval Mintz struct aeu_invert_reg_bit bits[32]; 1090d956e8aSYuval Mintz }; 1100d956e8aSYuval Mintz 1110d956e8aSYuval Mintz #define MAX_ATTN_GRPS (8) 1120d956e8aSYuval Mintz #define NUM_ATTN_REGS (9) 1130d956e8aSYuval Mintz 114b4149dc7SYuval Mintz /* Specific HW attention callbacks */ 115b4149dc7SYuval Mintz static int qed_mcp_attn_cb(struct qed_hwfn *p_hwfn) 116b4149dc7SYuval Mintz { 117b4149dc7SYuval Mintz u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE); 118b4149dc7SYuval Mintz 119b4149dc7SYuval Mintz /* This might occur on certain instances; Log it once then mask it */ 120b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, "MCP_REG_CPU_STATE: %08x - Masking...\n", 121b4149dc7SYuval Mintz tmp); 122b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK, 123b4149dc7SYuval Mintz 0xffffffff); 124b4149dc7SYuval Mintz 125b4149dc7SYuval Mintz return 0; 126b4149dc7SYuval Mintz } 127b4149dc7SYuval Mintz 128b4149dc7SYuval Mintz #define QED_PSWHST_ATTENTION_INCORRECT_ACCESS (0x1) 129b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_WR_MASK (0x1) 130b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_WR_SHIFT (0) 131b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_CLIENT_MASK (0xf) 132b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT (1) 133b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK (0x1) 134b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT (5) 135b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_ID_MASK (0xff) 136b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT (6) 137b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_PF_ID_MASK (0xf) 138b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT (14) 139b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK (0xff) 140b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT (18) 141b4149dc7SYuval Mintz static int qed_pswhst_attn_cb(struct qed_hwfn *p_hwfn) 142b4149dc7SYuval Mintz { 143b4149dc7SYuval Mintz u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 144b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_VALID); 145b4149dc7SYuval Mintz 146b4149dc7SYuval Mintz if (tmp & QED_PSWHST_ATTENTION_INCORRECT_ACCESS) { 147b4149dc7SYuval Mintz u32 addr, data, length; 148b4149dc7SYuval Mintz 149b4149dc7SYuval Mintz addr = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 150b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_ADDRESS); 151b4149dc7SYuval Mintz data = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 152b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_DATA); 153b4149dc7SYuval Mintz length = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 154b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_LENGTH); 155b4149dc7SYuval Mintz 156b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, 157b4149dc7SYuval Mintz "Incorrect access to %08x of length %08x - PF [%02x] VF [%04x] [valid %02x] client [%02x] write [%02x] Byte-Enable [%04x] [%08x]\n", 158b4149dc7SYuval Mintz addr, length, 159b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_PF_ID), 160b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_VF_ID), 161b4149dc7SYuval Mintz (u8) GET_FIELD(data, 162b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_VF_VALID), 163b4149dc7SYuval Mintz (u8) GET_FIELD(data, 164b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_CLIENT), 165b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_WR), 166b4149dc7SYuval Mintz (u8) GET_FIELD(data, 167b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_BYTE_EN), 168b4149dc7SYuval Mintz data); 169b4149dc7SYuval Mintz } 170b4149dc7SYuval Mintz 171b4149dc7SYuval Mintz return 0; 172b4149dc7SYuval Mintz } 173b4149dc7SYuval Mintz 174b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VALID_BIT (1 << 0) 175b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_ADDRESS_MASK (0x7fffff) 176b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_ADDRESS_SHIFT (0) 177b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_RDWR_BIT (1 << 23) 178b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_MASTER_MASK (0xf) 179b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_MASTER_SHIFT (24) 180b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PF_MASK (0xf) 181b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PF_SHIFT (0) 182b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VF_MASK (0xff) 183b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VF_SHIFT (4) 184b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_MASK (0x3) 185b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_SHIFT (14) 186b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_VF (0) 187b4149dc7SYuval Mintz static const char *attn_master_to_str(u8 master) 188b4149dc7SYuval Mintz { 189b4149dc7SYuval Mintz switch (master) { 190b4149dc7SYuval Mintz case 1: return "PXP"; 191b4149dc7SYuval Mintz case 2: return "MCP"; 192b4149dc7SYuval Mintz case 3: return "MSDM"; 193b4149dc7SYuval Mintz case 4: return "PSDM"; 194b4149dc7SYuval Mintz case 5: return "YSDM"; 195b4149dc7SYuval Mintz case 6: return "USDM"; 196b4149dc7SYuval Mintz case 7: return "TSDM"; 197b4149dc7SYuval Mintz case 8: return "XSDM"; 198b4149dc7SYuval Mintz case 9: return "DBU"; 199b4149dc7SYuval Mintz case 10: return "DMAE"; 200b4149dc7SYuval Mintz default: 2019165dabbSMasanari Iida return "Unknown"; 202b4149dc7SYuval Mintz } 203b4149dc7SYuval Mintz } 204b4149dc7SYuval Mintz 205b4149dc7SYuval Mintz static int qed_grc_attn_cb(struct qed_hwfn *p_hwfn) 206b4149dc7SYuval Mintz { 207b4149dc7SYuval Mintz u32 tmp, tmp2; 208b4149dc7SYuval Mintz 209b4149dc7SYuval Mintz /* We've already cleared the timeout interrupt register, so we learn 210b4149dc7SYuval Mintz * of interrupts via the validity register 211b4149dc7SYuval Mintz */ 212b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 213b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_VALID); 214b4149dc7SYuval Mintz if (!(tmp & QED_GRC_ATTENTION_VALID_BIT)) 215b4149dc7SYuval Mintz goto out; 216b4149dc7SYuval Mintz 217b4149dc7SYuval Mintz /* Read the GRC timeout information */ 218b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 219b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0); 220b4149dc7SYuval Mintz tmp2 = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 221b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1); 222b4149dc7SYuval Mintz 223b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, 224b4149dc7SYuval Mintz "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n", 225b4149dc7SYuval Mintz tmp2, tmp, 226b4149dc7SYuval Mintz (tmp & QED_GRC_ATTENTION_RDWR_BIT) ? "Write to" : "Read from", 227b4149dc7SYuval Mintz GET_FIELD(tmp, QED_GRC_ATTENTION_ADDRESS) << 2, 228b4149dc7SYuval Mintz attn_master_to_str(GET_FIELD(tmp, QED_GRC_ATTENTION_MASTER)), 229b4149dc7SYuval Mintz GET_FIELD(tmp2, QED_GRC_ATTENTION_PF), 230b4149dc7SYuval Mintz (GET_FIELD(tmp2, QED_GRC_ATTENTION_PRIV) == 231fbe1222cSColin Ian King QED_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Irrelevant)", 232b4149dc7SYuval Mintz GET_FIELD(tmp2, QED_GRC_ATTENTION_VF)); 233b4149dc7SYuval Mintz 234b4149dc7SYuval Mintz out: 235b4149dc7SYuval Mintz /* Regardles of anything else, clean the validity bit */ 236b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 237b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0); 238b4149dc7SYuval Mintz return 0; 239b4149dc7SYuval Mintz } 240b4149dc7SYuval Mintz 241b4149dc7SYuval Mintz #define PGLUE_ATTENTION_VALID (1 << 29) 242b4149dc7SYuval Mintz #define PGLUE_ATTENTION_RD_VALID (1 << 26) 243b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf) 244b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20) 245b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VF_VALID_MASK (0x1) 246b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VF_VALID_SHIFT (19) 247b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff) 248b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24) 249b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_MASK (0x1) 250b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_SHIFT (21) 251b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_BME_MASK (0x1) 252b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_BME_SHIFT (22) 253b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_FID_EN_MASK (0x1) 254b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_FID_EN_SHIFT (23) 255b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ICPL_VALID (1 << 23) 256b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ZLR_VALID (1 << 25) 257b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ILT_VALID (1 << 23) 258666db486STomer Tayar 259666db486STomer Tayar int qed_pglueb_rbc_attn_handler(struct qed_hwfn *p_hwfn, 260666db486STomer Tayar struct qed_ptt *p_ptt) 261b4149dc7SYuval Mintz { 262b4149dc7SYuval Mintz u32 tmp; 263b4149dc7SYuval Mintz 264666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS2); 265b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_VALID) { 266b4149dc7SYuval Mintz u32 addr_lo, addr_hi, details; 267b4149dc7SYuval Mintz 268666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 269b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_ADD_31_0); 270666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 271b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_ADD_63_32); 272666db486STomer Tayar details = qed_rd(p_hwfn, p_ptt, 273b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_DETAILS); 274b4149dc7SYuval Mintz 275666db486STomer Tayar DP_NOTICE(p_hwfn, 276b4149dc7SYuval Mintz "Illegal write by chip to [%08x:%08x] blocked.\n" 277b4149dc7SYuval Mintz "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 278b4149dc7SYuval Mintz "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 279b4149dc7SYuval Mintz addr_hi, addr_lo, details, 280b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 281b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 282b4149dc7SYuval Mintz GET_FIELD(details, 283b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0, 284b4149dc7SYuval Mintz tmp, 285b4149dc7SYuval Mintz GET_FIELD(tmp, 286b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0, 287b4149dc7SYuval Mintz GET_FIELD(tmp, 288b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0, 289b4149dc7SYuval Mintz GET_FIELD(tmp, 290b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0); 291b4149dc7SYuval Mintz } 292b4149dc7SYuval Mintz 293666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_RD_DETAILS2); 294b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_RD_VALID) { 295b4149dc7SYuval Mintz u32 addr_lo, addr_hi, details; 296b4149dc7SYuval Mintz 297666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 298b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_ADD_31_0); 299666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 300b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_ADD_63_32); 301666db486STomer Tayar details = qed_rd(p_hwfn, p_ptt, 302b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_DETAILS); 303b4149dc7SYuval Mintz 304666db486STomer Tayar DP_NOTICE(p_hwfn, 305b4149dc7SYuval Mintz "Illegal read by chip from [%08x:%08x] blocked.\n" 306b4149dc7SYuval Mintz "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n" 307b4149dc7SYuval Mintz "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n", 308b4149dc7SYuval Mintz addr_hi, addr_lo, details, 309b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID), 310b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID), 311b4149dc7SYuval Mintz GET_FIELD(details, 312b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0, 313b4149dc7SYuval Mintz tmp, 314666db486STomer Tayar GET_FIELD(tmp, 315666db486STomer Tayar PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0, 316666db486STomer Tayar GET_FIELD(tmp, 317666db486STomer Tayar PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0, 318666db486STomer Tayar GET_FIELD(tmp, 319666db486STomer Tayar PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0); 320b4149dc7SYuval Mintz } 321b4149dc7SYuval Mintz 322666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL); 323b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ICPL_VALID) 324666db486STomer Tayar DP_NOTICE(p_hwfn, "ICPL error - %08x\n", tmp); 325b4149dc7SYuval Mintz 326666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS); 327b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ZLR_VALID) { 328b4149dc7SYuval Mintz u32 addr_hi, addr_lo; 329b4149dc7SYuval Mintz 330666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 331b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0); 332666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 333b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32); 334b4149dc7SYuval Mintz 335666db486STomer Tayar DP_NOTICE(p_hwfn, "ZLR error - %08x [Address %08x:%08x]\n", 336b4149dc7SYuval Mintz tmp, addr_hi, addr_lo); 337b4149dc7SYuval Mintz } 338b4149dc7SYuval Mintz 339666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_VF_ILT_ERR_DETAILS2); 340b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ILT_VALID) { 341b4149dc7SYuval Mintz u32 addr_hi, addr_lo, details; 342b4149dc7SYuval Mintz 343666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt, 344b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_ADD_31_0); 345666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt, 346b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_ADD_63_32); 347666db486STomer Tayar details = qed_rd(p_hwfn, p_ptt, 348b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_DETAILS); 349b4149dc7SYuval Mintz 350666db486STomer Tayar DP_NOTICE(p_hwfn, 351b4149dc7SYuval Mintz "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n", 352b4149dc7SYuval Mintz details, tmp, addr_hi, addr_lo); 353b4149dc7SYuval Mintz } 354b4149dc7SYuval Mintz 355b4149dc7SYuval Mintz /* Clear the indications */ 356666db486STomer Tayar qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_LATCHED_ERRORS_CLR, BIT(2)); 357b4149dc7SYuval Mintz 358b4149dc7SYuval Mintz return 0; 359b4149dc7SYuval Mintz } 360b4149dc7SYuval Mintz 361666db486STomer Tayar static int qed_pglueb_rbc_attn_cb(struct qed_hwfn *p_hwfn) 362666db486STomer Tayar { 363666db486STomer Tayar return qed_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_dpc_ptt); 364666db486STomer Tayar } 365666db486STomer Tayar 366b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_REASON_MASK (0xfffff) 367b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_OPAQUE_MASK (0xffff) 368a1b469b8SAriel Elior #define QED_DORQ_ATTENTION_OPAQUE_SHIFT (0x0) 369b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_SIZE_MASK (0x7f) 370b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_SIZE_SHIFT (16) 371a1b469b8SAriel Elior 372a1b469b8SAriel Elior #define QED_DB_REC_COUNT 1000 373a1b469b8SAriel Elior #define QED_DB_REC_INTERVAL 100 374a1b469b8SAriel Elior 375a1b469b8SAriel Elior static int qed_db_rec_flush_queue(struct qed_hwfn *p_hwfn, 376a1b469b8SAriel Elior struct qed_ptt *p_ptt) 377a1b469b8SAriel Elior { 378a1b469b8SAriel Elior u32 count = QED_DB_REC_COUNT; 379a1b469b8SAriel Elior u32 usage = 1; 380a1b469b8SAriel Elior 3810d72c2acSDenis Bolotin /* Flush any pending (e)dpms as they may never arrive */ 3820d72c2acSDenis Bolotin qed_wr(p_hwfn, p_ptt, DORQ_REG_DPM_FORCE_ABORT, 0x1); 3830d72c2acSDenis Bolotin 384a1b469b8SAriel Elior /* wait for usage to zero or count to run out. This is necessary since 385a1b469b8SAriel Elior * EDPM doorbell transactions can take multiple 64b cycles, and as such 386a1b469b8SAriel Elior * can "split" over the pci. Possibly, the doorbell drop can happen with 387a1b469b8SAriel Elior * half an EDPM in the queue and other half dropped. Another EDPM 388a1b469b8SAriel Elior * doorbell to the same address (from doorbell recovery mechanism or 389a1b469b8SAriel Elior * from the doorbelling entity) could have first half dropped and second 390a1b469b8SAriel Elior * half interpreted as continuation of the first. To prevent such 391a1b469b8SAriel Elior * malformed doorbells from reaching the device, flush the queue before 392a1b469b8SAriel Elior * releasing the overflow sticky indication. 393a1b469b8SAriel Elior */ 394a1b469b8SAriel Elior while (count-- && usage) { 395a1b469b8SAriel Elior usage = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_USAGE_CNT); 396a1b469b8SAriel Elior udelay(QED_DB_REC_INTERVAL); 397a1b469b8SAriel Elior } 398a1b469b8SAriel Elior 399a1b469b8SAriel Elior /* should have been depleted by now */ 400a1b469b8SAriel Elior if (usage) { 401a1b469b8SAriel Elior DP_NOTICE(p_hwfn->cdev, 402a1b469b8SAriel Elior "DB recovery: doorbell usage failed to zero after %d usec. usage was %x\n", 403a1b469b8SAriel Elior QED_DB_REC_INTERVAL * QED_DB_REC_COUNT, usage); 404a1b469b8SAriel Elior return -EBUSY; 405a1b469b8SAriel Elior } 406a1b469b8SAriel Elior 407a1b469b8SAriel Elior return 0; 408a1b469b8SAriel Elior } 409a1b469b8SAriel Elior 410a1b469b8SAriel Elior int qed_db_rec_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 411a1b469b8SAriel Elior { 4120d72c2acSDenis Bolotin u32 attn_ovfl, cur_ovfl; 413a1b469b8SAriel Elior int rc; 414a1b469b8SAriel Elior 4150d72c2acSDenis Bolotin attn_ovfl = test_and_clear_bit(QED_OVERFLOW_BIT, 4160d72c2acSDenis Bolotin &p_hwfn->db_recovery_info.overflow); 4170d72c2acSDenis Bolotin cur_ovfl = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY); 4180d72c2acSDenis Bolotin if (!cur_ovfl && !attn_ovfl) 419a1b469b8SAriel Elior return 0; 420a1b469b8SAriel Elior 4210d72c2acSDenis Bolotin DP_NOTICE(p_hwfn, "PF Overflow sticky: attn %u current %u\n", 4220d72c2acSDenis Bolotin attn_ovfl, cur_ovfl); 4230d72c2acSDenis Bolotin 4240d72c2acSDenis Bolotin if (cur_ovfl && !p_hwfn->db_bar_no_edpm) { 425a1b469b8SAriel Elior rc = qed_db_rec_flush_queue(p_hwfn, p_ptt); 426a1b469b8SAriel Elior if (rc) 427a1b469b8SAriel Elior return rc; 428a1b469b8SAriel Elior } 429a1b469b8SAriel Elior 430a1b469b8SAriel Elior /* Release overflow sticky indication (stop silently dropping everything) */ 431a1b469b8SAriel Elior qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0); 432a1b469b8SAriel Elior 433a1b469b8SAriel Elior /* Repeat all last doorbells (doorbell drop recovery) */ 4349ac6bb14SDenis Bolotin qed_db_recovery_execute(p_hwfn); 435a1b469b8SAriel Elior 436a1b469b8SAriel Elior return 0; 437a1b469b8SAriel Elior } 438a1b469b8SAriel Elior 4390d72c2acSDenis Bolotin static void qed_dorq_attn_overflow(struct qed_hwfn *p_hwfn) 4400d72c2acSDenis Bolotin { 4410d72c2acSDenis Bolotin struct qed_ptt *p_ptt = p_hwfn->p_dpc_ptt; 4420d72c2acSDenis Bolotin u32 overflow; 4430d72c2acSDenis Bolotin int rc; 4440d72c2acSDenis Bolotin 4450d72c2acSDenis Bolotin overflow = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY); 4460d72c2acSDenis Bolotin if (!overflow) 4470d72c2acSDenis Bolotin goto out; 4480d72c2acSDenis Bolotin 4490d72c2acSDenis Bolotin /* Run PF doorbell recovery in next periodic handler */ 4500d72c2acSDenis Bolotin set_bit(QED_OVERFLOW_BIT, &p_hwfn->db_recovery_info.overflow); 4510d72c2acSDenis Bolotin 4520d72c2acSDenis Bolotin if (!p_hwfn->db_bar_no_edpm) { 4530d72c2acSDenis Bolotin rc = qed_db_rec_flush_queue(p_hwfn, p_ptt); 4540d72c2acSDenis Bolotin if (rc) 4550d72c2acSDenis Bolotin goto out; 4560d72c2acSDenis Bolotin } 4570d72c2acSDenis Bolotin 4580d72c2acSDenis Bolotin qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0); 4590d72c2acSDenis Bolotin out: 4600d72c2acSDenis Bolotin /* Schedule the handler even if overflow was not detected */ 4610d72c2acSDenis Bolotin qed_periodic_db_rec_start(p_hwfn); 4620d72c2acSDenis Bolotin } 4630d72c2acSDenis Bolotin 4640d72c2acSDenis Bolotin static int qed_dorq_attn_int_sts(struct qed_hwfn *p_hwfn) 465b4149dc7SYuval Mintz { 466a1b469b8SAriel Elior u32 int_sts, first_drop_reason, details, address, all_drops_reason; 467a1b469b8SAriel Elior struct qed_ptt *p_ptt = p_hwfn->p_dpc_ptt; 468a1b469b8SAriel Elior 469a1b469b8SAriel Elior /* int_sts may be zero since all PFs were interrupted for doorbell 470a1b469b8SAriel Elior * overflow but another one already handled it. Can abort here. If 471a1b469b8SAriel Elior * This PF also requires overflow recovery we will be interrupted again. 472a1b469b8SAriel Elior * The masked almost full indication may also be set. Ignoring. 473a1b469b8SAriel Elior */ 474d4476b8aSDenis Bolotin int_sts = qed_rd(p_hwfn, p_ptt, DORQ_REG_INT_STS); 475a1b469b8SAriel Elior if (!(int_sts & ~DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) 476a1b469b8SAriel Elior return 0; 477a1b469b8SAriel Elior 478d4476b8aSDenis Bolotin DP_NOTICE(p_hwfn->cdev, "DORQ attention. int_sts was %x\n", int_sts); 479d4476b8aSDenis Bolotin 480a1b469b8SAriel Elior /* check if db_drop or overflow happened */ 481a1b469b8SAriel Elior if (int_sts & (DORQ_REG_INT_STS_DB_DROP | 482a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR)) { 483a1b469b8SAriel Elior /* Obtain data about db drop/overflow */ 484a1b469b8SAriel Elior first_drop_reason = qed_rd(p_hwfn, p_ptt, 485a1b469b8SAriel Elior DORQ_REG_DB_DROP_REASON) & 486b4149dc7SYuval Mintz QED_DORQ_ATTENTION_REASON_MASK; 487a1b469b8SAriel Elior details = qed_rd(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS); 488a1b469b8SAriel Elior address = qed_rd(p_hwfn, p_ptt, 489a1b469b8SAriel Elior DORQ_REG_DB_DROP_DETAILS_ADDRESS); 490a1b469b8SAriel Elior all_drops_reason = qed_rd(p_hwfn, p_ptt, 491a1b469b8SAriel Elior DORQ_REG_DB_DROP_DETAILS_REASON); 492b4149dc7SYuval Mintz 493a1b469b8SAriel Elior /* Log info */ 494a1b469b8SAriel Elior DP_NOTICE(p_hwfn->cdev, 495a1b469b8SAriel Elior "Doorbell drop occurred\n" 496a1b469b8SAriel Elior "Address\t\t0x%08x\t(second BAR address)\n" 497a1b469b8SAriel Elior "FID\t\t0x%04x\t\t(Opaque FID)\n" 498a1b469b8SAriel Elior "Size\t\t0x%04x\t\t(in bytes)\n" 499a1b469b8SAriel Elior "1st drop reason\t0x%08x\t(details on first drop since last handling)\n" 500a1b469b8SAriel Elior "Sticky reasons\t0x%08x\t(all drop reasons since last handling)\n", 501a1b469b8SAriel Elior address, 502a1b469b8SAriel Elior GET_FIELD(details, QED_DORQ_ATTENTION_OPAQUE), 503b4149dc7SYuval Mintz GET_FIELD(details, QED_DORQ_ATTENTION_SIZE) * 4, 504a1b469b8SAriel Elior first_drop_reason, all_drops_reason); 505a1b469b8SAriel Elior 506a1b469b8SAriel Elior /* Clear the doorbell drop details and prepare for next drop */ 507a1b469b8SAriel Elior qed_wr(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS_REL, 0); 508a1b469b8SAriel Elior 509a1b469b8SAriel Elior /* Mark interrupt as handled (note: even if drop was due to a different 510a1b469b8SAriel Elior * reason than overflow we mark as handled) 511a1b469b8SAriel Elior */ 512a1b469b8SAriel Elior qed_wr(p_hwfn, 513a1b469b8SAriel Elior p_ptt, 514a1b469b8SAriel Elior DORQ_REG_INT_STS_WR, 515a1b469b8SAriel Elior DORQ_REG_INT_STS_DB_DROP | 516a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR); 517a1b469b8SAriel Elior 518a1b469b8SAriel Elior /* If there are no indications other than drop indications, success */ 519a1b469b8SAriel Elior if ((int_sts & ~(DORQ_REG_INT_STS_DB_DROP | 520a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR | 521a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) == 0) 522a1b469b8SAriel Elior return 0; 523b4149dc7SYuval Mintz } 524b4149dc7SYuval Mintz 525a1b469b8SAriel Elior /* Some other indication was present - non recoverable */ 526a1b469b8SAriel Elior DP_INFO(p_hwfn, "DORQ fatal attention\n"); 527a1b469b8SAriel Elior 528b4149dc7SYuval Mintz return -EINVAL; 529b4149dc7SYuval Mintz } 530b4149dc7SYuval Mintz 5310d72c2acSDenis Bolotin static int qed_dorq_attn_cb(struct qed_hwfn *p_hwfn) 5320d72c2acSDenis Bolotin { 5330d72c2acSDenis Bolotin p_hwfn->db_recovery_info.dorq_attn = true; 5340d72c2acSDenis Bolotin qed_dorq_attn_overflow(p_hwfn); 5350d72c2acSDenis Bolotin 5360d72c2acSDenis Bolotin return qed_dorq_attn_int_sts(p_hwfn); 5370d72c2acSDenis Bolotin } 5380d72c2acSDenis Bolotin 539d4476b8aSDenis Bolotin static void qed_dorq_attn_handler(struct qed_hwfn *p_hwfn) 540d4476b8aSDenis Bolotin { 541d4476b8aSDenis Bolotin if (p_hwfn->db_recovery_info.dorq_attn) 542d4476b8aSDenis Bolotin goto out; 543d4476b8aSDenis Bolotin 544d4476b8aSDenis Bolotin /* Call DORQ callback if the attention was missed */ 545d4476b8aSDenis Bolotin qed_dorq_attn_cb(p_hwfn); 546d4476b8aSDenis Bolotin out: 547d4476b8aSDenis Bolotin p_hwfn->db_recovery_info.dorq_attn = false; 548d4476b8aSDenis Bolotin } 549d4476b8aSDenis Bolotin 550ba36f718SMintz, Yuval /* Instead of major changes to the data-structure, we have a some 'special' 551ba36f718SMintz, Yuval * identifiers for sources that changed meaning between adapters. 552ba36f718SMintz, Yuval */ 553ba36f718SMintz, Yuval enum aeu_invert_reg_special_type { 554ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_0, 555ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_1, 556ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_2, 557ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_3, 558ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_MAX, 559ba36f718SMintz, Yuval }; 560ba36f718SMintz, Yuval 561ba36f718SMintz, Yuval static struct aeu_invert_reg_bit 562ba36f718SMintz, Yuval aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = { 563ba36f718SMintz, Yuval {"CNIG port 0", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 564ba36f718SMintz, Yuval {"CNIG port 1", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 565ba36f718SMintz, Yuval {"CNIG port 2", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 566ba36f718SMintz, Yuval {"CNIG port 3", ATTENTION_SINGLE, NULL, BLOCK_CNIG}, 567ba36f718SMintz, Yuval }; 568ba36f718SMintz, Yuval 5690d956e8aSYuval Mintz /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */ 5700d956e8aSYuval Mintz static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = { 5710d956e8aSYuval Mintz { 5720d956e8aSYuval Mintz { /* After Invert 1 */ 5730d956e8aSYuval Mintz {"GPIO0 function%d", 574b4149dc7SYuval Mintz (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 5750d956e8aSYuval Mintz } 5760d956e8aSYuval Mintz }, 5770d956e8aSYuval Mintz 5780d956e8aSYuval Mintz { 5790d956e8aSYuval Mintz { /* After Invert 2 */ 580b4149dc7SYuval Mintz {"PGLUE config_space", ATTENTION_SINGLE, 581b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 582b4149dc7SYuval Mintz {"PGLUE misc_flr", ATTENTION_SINGLE, 583b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 584b4149dc7SYuval Mintz {"PGLUE B RBC", ATTENTION_PAR_INT, 585666db486STomer Tayar qed_pglueb_rbc_attn_cb, BLOCK_PGLUE_B}, 586b4149dc7SYuval Mintz {"PGLUE misc_mctp", ATTENTION_SINGLE, 587b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 588b4149dc7SYuval Mintz {"Flash event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 589b4149dc7SYuval Mintz {"SMB event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 590b4149dc7SYuval Mintz {"Main Power", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 5910d956e8aSYuval Mintz {"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) | 592ff38577aSYuval Mintz (1 << ATTENTION_OFFSET_SHIFT), 593b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 5940d956e8aSYuval Mintz {"PCIE glue/PXP VPD %d", 595b4149dc7SYuval Mintz (16 << ATTENTION_LENGTH_SHIFT), NULL, BLOCK_PGLCS}, 5960d956e8aSYuval Mintz } 5970d956e8aSYuval Mintz }, 5980d956e8aSYuval Mintz 5990d956e8aSYuval Mintz { 6000d956e8aSYuval Mintz { /* After Invert 3 */ 6010d956e8aSYuval Mintz {"General Attention %d", 602b4149dc7SYuval Mintz (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID}, 6030d956e8aSYuval Mintz } 6040d956e8aSYuval Mintz }, 6050d956e8aSYuval Mintz 6060d956e8aSYuval Mintz { 6070d956e8aSYuval Mintz { /* After Invert 4 */ 608ff38577aSYuval Mintz {"General Attention 32", ATTENTION_SINGLE, 609b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 6100d956e8aSYuval Mintz {"General Attention %d", 6110d956e8aSYuval Mintz (2 << ATTENTION_LENGTH_SHIFT) | 612b4149dc7SYuval Mintz (33 << ATTENTION_OFFSET_SHIFT), NULL, MAX_BLOCK_ID}, 613ff38577aSYuval Mintz {"General Attention 35", ATTENTION_SINGLE, 614b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 615ba36f718SMintz, Yuval {"NWS Parity", 616ba36f718SMintz, Yuval ATTENTION_PAR | ATTENTION_BB_DIFFERENT | 617ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_0), 618ba36f718SMintz, Yuval NULL, BLOCK_NWS}, 619ba36f718SMintz, Yuval {"NWS Interrupt", 620ba36f718SMintz, Yuval ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT | 621ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_1), 622ba36f718SMintz, Yuval NULL, BLOCK_NWS}, 623ba36f718SMintz, Yuval {"NWM Parity", 624ba36f718SMintz, Yuval ATTENTION_PAR | ATTENTION_BB_DIFFERENT | 625ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_2), 626ba36f718SMintz, Yuval NULL, BLOCK_NWM}, 627ba36f718SMintz, Yuval {"NWM Interrupt", 628ba36f718SMintz, Yuval ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT | 629ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_3), 630ba36f718SMintz, Yuval NULL, BLOCK_NWM}, 631b4149dc7SYuval Mintz {"MCP CPU", ATTENTION_SINGLE, 632b4149dc7SYuval Mintz qed_mcp_attn_cb, MAX_BLOCK_ID}, 633b4149dc7SYuval Mintz {"MCP Watchdog timer", ATTENTION_SINGLE, 634b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 635b4149dc7SYuval Mintz {"MCP M2P", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID}, 636ff38577aSYuval Mintz {"AVS stop status ready", ATTENTION_SINGLE, 637b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 638b4149dc7SYuval Mintz {"MSTAT", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 639b4149dc7SYuval Mintz {"MSTAT per-path", ATTENTION_PAR_INT, 640b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 641ff38577aSYuval Mintz {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT), 642b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 643b4149dc7SYuval Mintz {"NIG", ATTENTION_PAR_INT, NULL, BLOCK_NIG}, 644b4149dc7SYuval Mintz {"BMB/OPTE/MCP", ATTENTION_PAR_INT, NULL, BLOCK_BMB}, 645b4149dc7SYuval Mintz {"BTB", ATTENTION_PAR_INT, NULL, BLOCK_BTB}, 646b4149dc7SYuval Mintz {"BRB", ATTENTION_PAR_INT, NULL, BLOCK_BRB}, 647b4149dc7SYuval Mintz {"PRS", ATTENTION_PAR_INT, NULL, BLOCK_PRS}, 6480d956e8aSYuval Mintz } 6490d956e8aSYuval Mintz }, 6500d956e8aSYuval Mintz 6510d956e8aSYuval Mintz { 6520d956e8aSYuval Mintz { /* After Invert 5 */ 653b4149dc7SYuval Mintz {"SRC", ATTENTION_PAR_INT, NULL, BLOCK_SRC}, 654b4149dc7SYuval Mintz {"PB Client1", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB1}, 655b4149dc7SYuval Mintz {"PB Client2", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB2}, 656b4149dc7SYuval Mintz {"RPB", ATTENTION_PAR_INT, NULL, BLOCK_RPB}, 657b4149dc7SYuval Mintz {"PBF", ATTENTION_PAR_INT, NULL, BLOCK_PBF}, 658b4149dc7SYuval Mintz {"QM", ATTENTION_PAR_INT, NULL, BLOCK_QM}, 659b4149dc7SYuval Mintz {"TM", ATTENTION_PAR_INT, NULL, BLOCK_TM}, 660b4149dc7SYuval Mintz {"MCM", ATTENTION_PAR_INT, NULL, BLOCK_MCM}, 661b4149dc7SYuval Mintz {"MSDM", ATTENTION_PAR_INT, NULL, BLOCK_MSDM}, 662b4149dc7SYuval Mintz {"MSEM", ATTENTION_PAR_INT, NULL, BLOCK_MSEM}, 663b4149dc7SYuval Mintz {"PCM", ATTENTION_PAR_INT, NULL, BLOCK_PCM}, 664b4149dc7SYuval Mintz {"PSDM", ATTENTION_PAR_INT, NULL, BLOCK_PSDM}, 665b4149dc7SYuval Mintz {"PSEM", ATTENTION_PAR_INT, NULL, BLOCK_PSEM}, 666b4149dc7SYuval Mintz {"TCM", ATTENTION_PAR_INT, NULL, BLOCK_TCM}, 667b4149dc7SYuval Mintz {"TSDM", ATTENTION_PAR_INT, NULL, BLOCK_TSDM}, 668b4149dc7SYuval Mintz {"TSEM", ATTENTION_PAR_INT, NULL, BLOCK_TSEM}, 6690d956e8aSYuval Mintz } 6700d956e8aSYuval Mintz }, 6710d956e8aSYuval Mintz 6720d956e8aSYuval Mintz { 6730d956e8aSYuval Mintz { /* After Invert 6 */ 674b4149dc7SYuval Mintz {"UCM", ATTENTION_PAR_INT, NULL, BLOCK_UCM}, 675b4149dc7SYuval Mintz {"USDM", ATTENTION_PAR_INT, NULL, BLOCK_USDM}, 676b4149dc7SYuval Mintz {"USEM", ATTENTION_PAR_INT, NULL, BLOCK_USEM}, 677b4149dc7SYuval Mintz {"XCM", ATTENTION_PAR_INT, NULL, BLOCK_XCM}, 678b4149dc7SYuval Mintz {"XSDM", ATTENTION_PAR_INT, NULL, BLOCK_XSDM}, 679b4149dc7SYuval Mintz {"XSEM", ATTENTION_PAR_INT, NULL, BLOCK_XSEM}, 680b4149dc7SYuval Mintz {"YCM", ATTENTION_PAR_INT, NULL, BLOCK_YCM}, 681b4149dc7SYuval Mintz {"YSDM", ATTENTION_PAR_INT, NULL, BLOCK_YSDM}, 682b4149dc7SYuval Mintz {"YSEM", ATTENTION_PAR_INT, NULL, BLOCK_YSEM}, 683b4149dc7SYuval Mintz {"XYLD", ATTENTION_PAR_INT, NULL, BLOCK_XYLD}, 684b4149dc7SYuval Mintz {"TMLD", ATTENTION_PAR_INT, NULL, BLOCK_TMLD}, 685b4149dc7SYuval Mintz {"MYLD", ATTENTION_PAR_INT, NULL, BLOCK_MULD}, 686b4149dc7SYuval Mintz {"YULD", ATTENTION_PAR_INT, NULL, BLOCK_YULD}, 687b4149dc7SYuval Mintz {"DORQ", ATTENTION_PAR_INT, 688b4149dc7SYuval Mintz qed_dorq_attn_cb, BLOCK_DORQ}, 689b4149dc7SYuval Mintz {"DBG", ATTENTION_PAR_INT, NULL, BLOCK_DBG}, 690b4149dc7SYuval Mintz {"IPC", ATTENTION_PAR_INT, NULL, BLOCK_IPC}, 6910d956e8aSYuval Mintz } 6920d956e8aSYuval Mintz }, 6930d956e8aSYuval Mintz 6940d956e8aSYuval Mintz { 6950d956e8aSYuval Mintz { /* After Invert 7 */ 696b4149dc7SYuval Mintz {"CCFC", ATTENTION_PAR_INT, NULL, BLOCK_CCFC}, 697b4149dc7SYuval Mintz {"CDU", ATTENTION_PAR_INT, NULL, BLOCK_CDU}, 698b4149dc7SYuval Mintz {"DMAE", ATTENTION_PAR_INT, NULL, BLOCK_DMAE}, 699b4149dc7SYuval Mintz {"IGU", ATTENTION_PAR_INT, NULL, BLOCK_IGU}, 700b4149dc7SYuval Mintz {"ATC", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID}, 701b4149dc7SYuval Mintz {"CAU", ATTENTION_PAR_INT, NULL, BLOCK_CAU}, 702b4149dc7SYuval Mintz {"PTU", ATTENTION_PAR_INT, NULL, BLOCK_PTU}, 703b4149dc7SYuval Mintz {"PRM", ATTENTION_PAR_INT, NULL, BLOCK_PRM}, 704b4149dc7SYuval Mintz {"TCFC", ATTENTION_PAR_INT, NULL, BLOCK_TCFC}, 705b4149dc7SYuval Mintz {"RDIF", ATTENTION_PAR_INT, NULL, BLOCK_RDIF}, 706b4149dc7SYuval Mintz {"TDIF", ATTENTION_PAR_INT, NULL, BLOCK_TDIF}, 707b4149dc7SYuval Mintz {"RSS", ATTENTION_PAR_INT, NULL, BLOCK_RSS}, 708b4149dc7SYuval Mintz {"MISC", ATTENTION_PAR_INT, NULL, BLOCK_MISC}, 709b4149dc7SYuval Mintz {"MISCS", ATTENTION_PAR_INT, NULL, BLOCK_MISCS}, 710b4149dc7SYuval Mintz {"PCIE", ATTENTION_PAR, NULL, BLOCK_PCIE}, 711b4149dc7SYuval Mintz {"Vaux PCI core", ATTENTION_SINGLE, NULL, BLOCK_PGLCS}, 712b4149dc7SYuval Mintz {"PSWRQ", ATTENTION_PAR_INT, NULL, BLOCK_PSWRQ}, 7130d956e8aSYuval Mintz } 7140d956e8aSYuval Mintz }, 7150d956e8aSYuval Mintz 7160d956e8aSYuval Mintz { 7170d956e8aSYuval Mintz { /* After Invert 8 */ 718b4149dc7SYuval Mintz {"PSWRQ (pci_clk)", ATTENTION_PAR_INT, 719b4149dc7SYuval Mintz NULL, BLOCK_PSWRQ2}, 720b4149dc7SYuval Mintz {"PSWWR", ATTENTION_PAR_INT, NULL, BLOCK_PSWWR}, 721b4149dc7SYuval Mintz {"PSWWR (pci_clk)", ATTENTION_PAR_INT, 722b4149dc7SYuval Mintz NULL, BLOCK_PSWWR2}, 723b4149dc7SYuval Mintz {"PSWRD", ATTENTION_PAR_INT, NULL, BLOCK_PSWRD}, 724b4149dc7SYuval Mintz {"PSWRD (pci_clk)", ATTENTION_PAR_INT, 725b4149dc7SYuval Mintz NULL, BLOCK_PSWRD2}, 726b4149dc7SYuval Mintz {"PSWHST", ATTENTION_PAR_INT, 727b4149dc7SYuval Mintz qed_pswhst_attn_cb, BLOCK_PSWHST}, 728b4149dc7SYuval Mintz {"PSWHST (pci_clk)", ATTENTION_PAR_INT, 729b4149dc7SYuval Mintz NULL, BLOCK_PSWHST2}, 730b4149dc7SYuval Mintz {"GRC", ATTENTION_PAR_INT, 731b4149dc7SYuval Mintz qed_grc_attn_cb, BLOCK_GRC}, 732b4149dc7SYuval Mintz {"CPMU", ATTENTION_PAR_INT, NULL, BLOCK_CPMU}, 733b4149dc7SYuval Mintz {"NCSI", ATTENTION_PAR_INT, NULL, BLOCK_NCSI}, 734b4149dc7SYuval Mintz {"MSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 735b4149dc7SYuval Mintz {"PSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 736b4149dc7SYuval Mintz {"TSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 737b4149dc7SYuval Mintz {"USEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 738b4149dc7SYuval Mintz {"XSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 739b4149dc7SYuval Mintz {"YSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID}, 740b4149dc7SYuval Mintz {"pxp_misc_mps", ATTENTION_PAR, NULL, BLOCK_PGLCS}, 741ff38577aSYuval Mintz {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE, 742b4149dc7SYuval Mintz NULL, BLOCK_PGLCS}, 743b4149dc7SYuval Mintz {"PERST_B assertion", ATTENTION_SINGLE, 744b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 745ff38577aSYuval Mintz {"PERST_B deassertion", ATTENTION_SINGLE, 746b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 747ff38577aSYuval Mintz {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT), 748b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 7490d956e8aSYuval Mintz } 7500d956e8aSYuval Mintz }, 7510d956e8aSYuval Mintz 7520d956e8aSYuval Mintz { 7530d956e8aSYuval Mintz { /* After Invert 9 */ 754b4149dc7SYuval Mintz {"MCP Latched memory", ATTENTION_PAR, 755b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 756ff38577aSYuval Mintz {"MCP Latched scratchpad cache", ATTENTION_SINGLE, 757b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 758b4149dc7SYuval Mintz {"MCP Latched ump_tx", ATTENTION_PAR, 759b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 760ff38577aSYuval Mintz {"MCP Latched scratchpad", ATTENTION_PAR, 761b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 762ff38577aSYuval Mintz {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT), 763b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID}, 7640d956e8aSYuval Mintz } 7650d956e8aSYuval Mintz }, 7660d956e8aSYuval Mintz }; 7670d956e8aSYuval Mintz 768ba36f718SMintz, Yuval static struct aeu_invert_reg_bit * 769ba36f718SMintz, Yuval qed_int_aeu_translate(struct qed_hwfn *p_hwfn, 770ba36f718SMintz, Yuval struct aeu_invert_reg_bit *p_bit) 771ba36f718SMintz, Yuval { 772ba36f718SMintz, Yuval if (!QED_IS_BB(p_hwfn->cdev)) 773ba36f718SMintz, Yuval return p_bit; 774ba36f718SMintz, Yuval 775ba36f718SMintz, Yuval if (!(p_bit->flags & ATTENTION_BB_DIFFERENT)) 776ba36f718SMintz, Yuval return p_bit; 777ba36f718SMintz, Yuval 778ba36f718SMintz, Yuval return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >> 779ba36f718SMintz, Yuval ATTENTION_BB_SHIFT]; 780ba36f718SMintz, Yuval } 781ba36f718SMintz, Yuval 782ba36f718SMintz, Yuval static bool qed_int_is_parity_flag(struct qed_hwfn *p_hwfn, 783ba36f718SMintz, Yuval struct aeu_invert_reg_bit *p_bit) 784ba36f718SMintz, Yuval { 785ba36f718SMintz, Yuval return !!(qed_int_aeu_translate(p_hwfn, p_bit)->flags & 786ba36f718SMintz, Yuval ATTENTION_PARITY); 787ba36f718SMintz, Yuval } 788ba36f718SMintz, Yuval 789cc875c2eSYuval Mintz #define ATTN_STATE_BITS (0xfff) 790cc875c2eSYuval Mintz #define ATTN_BITS_MASKABLE (0x3ff) 791cc875c2eSYuval Mintz struct qed_sb_attn_info { 792cc875c2eSYuval Mintz /* Virtual & Physical address of the SB */ 793cc875c2eSYuval Mintz struct atten_status_block *sb_attn; 794cc875c2eSYuval Mintz dma_addr_t sb_phys; 795cc875c2eSYuval Mintz 796cc875c2eSYuval Mintz /* Last seen running index */ 797cc875c2eSYuval Mintz u16 index; 798cc875c2eSYuval Mintz 7990d956e8aSYuval Mintz /* A mask of the AEU bits resulting in a parity error */ 8000d956e8aSYuval Mintz u32 parity_mask[NUM_ATTN_REGS]; 8010d956e8aSYuval Mintz 8020d956e8aSYuval Mintz /* A pointer to the attention description structure */ 8030d956e8aSYuval Mintz struct aeu_invert_reg *p_aeu_desc; 8040d956e8aSYuval Mintz 805cc875c2eSYuval Mintz /* Previously asserted attentions, which are still unasserted */ 806cc875c2eSYuval Mintz u16 known_attn; 807cc875c2eSYuval Mintz 808cc875c2eSYuval Mintz /* Cleanup address for the link's general hw attention */ 809cc875c2eSYuval Mintz u32 mfw_attn_addr; 810cc875c2eSYuval Mintz }; 811cc875c2eSYuval Mintz 812cc875c2eSYuval Mintz static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn, 813cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb_desc) 814cc875c2eSYuval Mintz { 8151a635e48SYuval Mintz u16 rc = 0, index; 816cc875c2eSYuval Mintz 817cc875c2eSYuval Mintz /* Make certain HW write took affect */ 818cc875c2eSYuval Mintz mmiowb(); 819cc875c2eSYuval Mintz 820cc875c2eSYuval Mintz index = le16_to_cpu(p_sb_desc->sb_attn->sb_index); 821cc875c2eSYuval Mintz if (p_sb_desc->index != index) { 822cc875c2eSYuval Mintz p_sb_desc->index = index; 823cc875c2eSYuval Mintz rc = QED_SB_ATT_IDX; 824cc875c2eSYuval Mintz } 825cc875c2eSYuval Mintz 826cc875c2eSYuval Mintz /* Make certain we got a consistent view with HW */ 827cc875c2eSYuval Mintz mmiowb(); 828cc875c2eSYuval Mintz 829cc875c2eSYuval Mintz return rc; 830cc875c2eSYuval Mintz } 831cc875c2eSYuval Mintz 832cc875c2eSYuval Mintz /** 833cc875c2eSYuval Mintz * @brief qed_int_assertion - handles asserted attention bits 834cc875c2eSYuval Mintz * 835cc875c2eSYuval Mintz * @param p_hwfn 836cc875c2eSYuval Mintz * @param asserted_bits newly asserted bits 837cc875c2eSYuval Mintz * @return int 838cc875c2eSYuval Mintz */ 8391a635e48SYuval Mintz static int qed_int_assertion(struct qed_hwfn *p_hwfn, u16 asserted_bits) 840cc875c2eSYuval Mintz { 841cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 842cc875c2eSYuval Mintz u32 igu_mask; 843cc875c2eSYuval Mintz 844cc875c2eSYuval Mintz /* Mask the source of the attention in the IGU */ 8451a635e48SYuval Mintz igu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); 846cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n", 847cc875c2eSYuval Mintz igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE)); 848cc875c2eSYuval Mintz igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE); 849cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask); 850cc875c2eSYuval Mintz 851cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 852cc875c2eSYuval Mintz "inner known ATTN state: 0x%04x --> 0x%04x\n", 853cc875c2eSYuval Mintz sb_attn_sw->known_attn, 854cc875c2eSYuval Mintz sb_attn_sw->known_attn | asserted_bits); 855cc875c2eSYuval Mintz sb_attn_sw->known_attn |= asserted_bits; 856cc875c2eSYuval Mintz 857cc875c2eSYuval Mintz /* Handle MCP events */ 858cc875c2eSYuval Mintz if (asserted_bits & 0x100) { 859cc875c2eSYuval Mintz qed_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt); 860cc875c2eSYuval Mintz /* Clean the MCP attention */ 861cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, 862cc875c2eSYuval Mintz sb_attn_sw->mfw_attn_addr, 0); 863cc875c2eSYuval Mintz } 864cc875c2eSYuval Mintz 865cc875c2eSYuval Mintz DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 866cc875c2eSYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 867cc875c2eSYuval Mintz ((IGU_CMD_ATTN_BIT_SET_UPPER - 868cc875c2eSYuval Mintz IGU_CMD_INT_ACK_BASE) << 3), 869cc875c2eSYuval Mintz (u32)asserted_bits); 870cc875c2eSYuval Mintz 871cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "set cmd IGU: 0x%04x\n", 872cc875c2eSYuval Mintz asserted_bits); 873cc875c2eSYuval Mintz 874cc875c2eSYuval Mintz return 0; 875cc875c2eSYuval Mintz } 876cc875c2eSYuval Mintz 8770ebbd1c8SMintz, Yuval static void qed_int_attn_print(struct qed_hwfn *p_hwfn, 8780ebbd1c8SMintz, Yuval enum block_id id, 8790ebbd1c8SMintz, Yuval enum dbg_attn_type type, bool b_clear) 880ff38577aSYuval Mintz { 8810ebbd1c8SMintz, Yuval struct dbg_attn_block_result attn_results; 8820ebbd1c8SMintz, Yuval enum dbg_status status; 883ff38577aSYuval Mintz 8840ebbd1c8SMintz, Yuval memset(&attn_results, 0, sizeof(attn_results)); 885ff38577aSYuval Mintz 8860ebbd1c8SMintz, Yuval status = qed_dbg_read_attn(p_hwfn, p_hwfn->p_dpc_ptt, id, type, 8870ebbd1c8SMintz, Yuval b_clear, &attn_results); 8880ebbd1c8SMintz, Yuval if (status != DBG_STATUS_OK) 889ff38577aSYuval Mintz DP_NOTICE(p_hwfn, 8900ebbd1c8SMintz, Yuval "Failed to parse attention information [status: %s]\n", 8910ebbd1c8SMintz, Yuval qed_dbg_get_status_str(status)); 8920ebbd1c8SMintz, Yuval else 8930ebbd1c8SMintz, Yuval qed_dbg_parse_attn(p_hwfn, &attn_results); 894ff38577aSYuval Mintz } 895ff38577aSYuval Mintz 896cc875c2eSYuval Mintz /** 8970d956e8aSYuval Mintz * @brief qed_int_deassertion_aeu_bit - handles the effects of a single 8980d956e8aSYuval Mintz * cause of the attention 8990d956e8aSYuval Mintz * 9000d956e8aSYuval Mintz * @param p_hwfn 9010d956e8aSYuval Mintz * @param p_aeu - descriptor of an AEU bit which caused the attention 9020d956e8aSYuval Mintz * @param aeu_en_reg - register offset of the AEU enable reg. which configured 9030d956e8aSYuval Mintz * this bit to this group. 9040d956e8aSYuval Mintz * @param bit_index - index of this bit in the aeu_en_reg 9050d956e8aSYuval Mintz * 9060d956e8aSYuval Mintz * @return int 9070d956e8aSYuval Mintz */ 9080d956e8aSYuval Mintz static int 9090d956e8aSYuval Mintz qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn, 9100d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_aeu, 9110d956e8aSYuval Mintz u32 aeu_en_reg, 9126010179dSMintz, Yuval const char *p_bit_name, u32 bitmask) 9130d956e8aSYuval Mintz { 9140ebbd1c8SMintz, Yuval bool b_fatal = false; 9150d956e8aSYuval Mintz int rc = -EINVAL; 916b4149dc7SYuval Mintz u32 val; 9170d956e8aSYuval Mintz 9180d956e8aSYuval Mintz DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n", 9196010179dSMintz, Yuval p_bit_name, bitmask); 9200d956e8aSYuval Mintz 921b4149dc7SYuval Mintz /* Call callback before clearing the interrupt status */ 922b4149dc7SYuval Mintz if (p_aeu->cb) { 923b4149dc7SYuval Mintz DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n", 9246010179dSMintz, Yuval p_bit_name); 925b4149dc7SYuval Mintz rc = p_aeu->cb(p_hwfn); 926b4149dc7SYuval Mintz } 927b4149dc7SYuval Mintz 9280ebbd1c8SMintz, Yuval if (rc) 9290ebbd1c8SMintz, Yuval b_fatal = true; 930ff38577aSYuval Mintz 9310ebbd1c8SMintz, Yuval /* Print HW block interrupt registers */ 9320ebbd1c8SMintz, Yuval if (p_aeu->block_index != MAX_BLOCK_ID) 9330ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, p_aeu->block_index, 9340ebbd1c8SMintz, Yuval ATTN_TYPE_INTERRUPT, !b_fatal); 935ff38577aSYuval Mintz 936ff38577aSYuval Mintz 937b4149dc7SYuval Mintz /* If the attention is benign, no need to prevent it */ 938b4149dc7SYuval Mintz if (!rc) 939b4149dc7SYuval Mintz goto out; 940b4149dc7SYuval Mintz 9410d956e8aSYuval Mintz /* Prevent this Attention from being asserted in the future */ 9420d956e8aSYuval Mintz val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 943b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & ~bitmask)); 9440d956e8aSYuval Mintz DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n", 9456010179dSMintz, Yuval p_bit_name); 9460d956e8aSYuval Mintz 947b4149dc7SYuval Mintz out: 9480d956e8aSYuval Mintz return rc; 9490d956e8aSYuval Mintz } 9500d956e8aSYuval Mintz 951ff38577aSYuval Mintz /** 952ff38577aSYuval Mintz * @brief qed_int_deassertion_parity - handle a single parity AEU source 953ff38577aSYuval Mintz * 954ff38577aSYuval Mintz * @param p_hwfn 955ff38577aSYuval Mintz * @param p_aeu - descriptor of an AEU bit which caused the parity 9569790c35eSMintz, Yuval * @param aeu_en_reg - address of the AEU enable register 957ff38577aSYuval Mintz * @param bit_index 958ff38577aSYuval Mintz */ 959ff38577aSYuval Mintz static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn, 960ff38577aSYuval Mintz struct aeu_invert_reg_bit *p_aeu, 9619790c35eSMintz, Yuval u32 aeu_en_reg, u8 bit_index) 962ff38577aSYuval Mintz { 9639790c35eSMintz, Yuval u32 block_id = p_aeu->block_index, mask, val; 964ff38577aSYuval Mintz 9659790c35eSMintz, Yuval DP_NOTICE(p_hwfn->cdev, 9669790c35eSMintz, Yuval "%s parity attention is set [address 0x%08x, bit %d]\n", 9679790c35eSMintz, Yuval p_aeu->bit_name, aeu_en_reg, bit_index); 968ff38577aSYuval Mintz 969ff38577aSYuval Mintz if (block_id != MAX_BLOCK_ID) { 9700ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, block_id, ATTN_TYPE_PARITY, false); 971ff38577aSYuval Mintz 972ff38577aSYuval Mintz /* In BB, there's a single parity bit for several blocks */ 973ff38577aSYuval Mintz if (block_id == BLOCK_BTB) { 9740ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, BLOCK_OPTE, 9750ebbd1c8SMintz, Yuval ATTN_TYPE_PARITY, false); 9760ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, BLOCK_MCP, 9770ebbd1c8SMintz, Yuval ATTN_TYPE_PARITY, false); 978ff38577aSYuval Mintz } 979ff38577aSYuval Mintz } 9809790c35eSMintz, Yuval 9819790c35eSMintz, Yuval /* Prevent this parity error from being re-asserted */ 9829790c35eSMintz, Yuval mask = ~BIT(bit_index); 9839790c35eSMintz, Yuval val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg); 9849790c35eSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask); 9859790c35eSMintz, Yuval DP_INFO(p_hwfn, "`%s' - Disabled future parity errors\n", 9869790c35eSMintz, Yuval p_aeu->bit_name); 987ff38577aSYuval Mintz } 988ff38577aSYuval Mintz 9890d956e8aSYuval Mintz /** 990cc875c2eSYuval Mintz * @brief - handles deassertion of previously asserted attentions. 991cc875c2eSYuval Mintz * 992cc875c2eSYuval Mintz * @param p_hwfn 993cc875c2eSYuval Mintz * @param deasserted_bits - newly deasserted bits 994cc875c2eSYuval Mintz * @return int 995cc875c2eSYuval Mintz * 996cc875c2eSYuval Mintz */ 997cc875c2eSYuval Mintz static int qed_int_deassertion(struct qed_hwfn *p_hwfn, 998cc875c2eSYuval Mintz u16 deasserted_bits) 999cc875c2eSYuval Mintz { 1000cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn; 10019790c35eSMintz, Yuval u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask, aeu_en, en; 10020d956e8aSYuval Mintz u8 i, j, k, bit_idx; 10030d956e8aSYuval Mintz int rc = 0; 1004cc875c2eSYuval Mintz 10050d956e8aSYuval Mintz /* Read the attention registers in the AEU */ 10060d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 10070d956e8aSYuval Mintz aeu_inv_arr[i] = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, 10080d956e8aSYuval Mintz MISC_REG_AEU_AFTER_INVERT_1_IGU + 10090d956e8aSYuval Mintz i * 0x4); 10100d956e8aSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 10110d956e8aSYuval Mintz "Deasserted bits [%d]: %08x\n", 10120d956e8aSYuval Mintz i, aeu_inv_arr[i]); 10130d956e8aSYuval Mintz } 10140d956e8aSYuval Mintz 10150d956e8aSYuval Mintz /* Find parity attentions first */ 10160d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 10170d956e8aSYuval Mintz struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i]; 10180d956e8aSYuval Mintz u32 parities; 10190d956e8aSYuval Mintz 10209790c35eSMintz, Yuval aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + i * sizeof(u32); 10219790c35eSMintz, Yuval en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 10229790c35eSMintz, Yuval 10230d956e8aSYuval Mintz /* Skip register in which no parity bit is currently set */ 10240d956e8aSYuval Mintz parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en; 10250d956e8aSYuval Mintz if (!parities) 10260d956e8aSYuval Mintz continue; 10270d956e8aSYuval Mintz 10280d956e8aSYuval Mintz for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 10290d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j]; 10300d956e8aSYuval Mintz 1031ba36f718SMintz, Yuval if (qed_int_is_parity_flag(p_hwfn, p_bit) && 10321a635e48SYuval Mintz !!(parities & BIT(bit_idx))) 1033ff38577aSYuval Mintz qed_int_deassertion_parity(p_hwfn, p_bit, 10349790c35eSMintz, Yuval aeu_en, bit_idx); 10350d956e8aSYuval Mintz 10360d956e8aSYuval Mintz bit_idx += ATTENTION_LENGTH(p_bit->flags); 10370d956e8aSYuval Mintz } 10380d956e8aSYuval Mintz } 10390d956e8aSYuval Mintz 10400d956e8aSYuval Mintz /* Find non-parity cause for attention and act */ 10410d956e8aSYuval Mintz for (k = 0; k < MAX_ATTN_GRPS; k++) { 10420d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_aeu; 10430d956e8aSYuval Mintz 10440d956e8aSYuval Mintz /* Handle only groups whose attention is currently deasserted */ 10450d956e8aSYuval Mintz if (!(deasserted_bits & (1 << k))) 10460d956e8aSYuval Mintz continue; 10470d956e8aSYuval Mintz 10480d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 10499790c35eSMintz, Yuval u32 bits; 10509790c35eSMintz, Yuval 10519790c35eSMintz, Yuval aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + 10520d956e8aSYuval Mintz i * sizeof(u32) + 10530d956e8aSYuval Mintz k * sizeof(u32) * NUM_ATTN_REGS; 10540d956e8aSYuval Mintz 10550d956e8aSYuval Mintz en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en); 10560d956e8aSYuval Mintz bits = aeu_inv_arr[i] & en; 10570d956e8aSYuval Mintz 10580d956e8aSYuval Mintz /* Skip if no bit from this group is currently set */ 10590d956e8aSYuval Mintz if (!bits) 10600d956e8aSYuval Mintz continue; 10610d956e8aSYuval Mintz 10620d956e8aSYuval Mintz /* Find all set bits from current register which belong 10630d956e8aSYuval Mintz * to current group, making them responsible for the 10640d956e8aSYuval Mintz * previous assertion. 10650d956e8aSYuval Mintz */ 10660d956e8aSYuval Mintz for (j = 0, bit_idx = 0; bit_idx < 32; j++) { 10676010179dSMintz, Yuval long unsigned int bitmask; 10680d956e8aSYuval Mintz u8 bit, bit_len; 10690d956e8aSYuval Mintz 10700d956e8aSYuval Mintz p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j]; 1071ba36f718SMintz, Yuval p_aeu = qed_int_aeu_translate(p_hwfn, p_aeu); 10720d956e8aSYuval Mintz 10730d956e8aSYuval Mintz bit = bit_idx; 10740d956e8aSYuval Mintz bit_len = ATTENTION_LENGTH(p_aeu->flags); 1075ba36f718SMintz, Yuval if (qed_int_is_parity_flag(p_hwfn, p_aeu)) { 10760d956e8aSYuval Mintz /* Skip Parity */ 10770d956e8aSYuval Mintz bit++; 10780d956e8aSYuval Mintz bit_len--; 10790d956e8aSYuval Mintz } 10800d956e8aSYuval Mintz 10810d956e8aSYuval Mintz bitmask = bits & (((1 << bit_len) - 1) << bit); 10826010179dSMintz, Yuval bitmask >>= bit; 10836010179dSMintz, Yuval 10840d956e8aSYuval Mintz if (bitmask) { 10856010179dSMintz, Yuval u32 flags = p_aeu->flags; 10866010179dSMintz, Yuval char bit_name[30]; 10876010179dSMintz, Yuval u8 num; 10886010179dSMintz, Yuval 10896010179dSMintz, Yuval num = (u8)find_first_bit(&bitmask, 10906010179dSMintz, Yuval bit_len); 10916010179dSMintz, Yuval 10926010179dSMintz, Yuval /* Some bits represent more than a 10936010179dSMintz, Yuval * a single interrupt. Correctly print 10946010179dSMintz, Yuval * their name. 10956010179dSMintz, Yuval */ 10966010179dSMintz, Yuval if (ATTENTION_LENGTH(flags) > 2 || 10976010179dSMintz, Yuval ((flags & ATTENTION_PAR_INT) && 10986010179dSMintz, Yuval ATTENTION_LENGTH(flags) > 1)) 10996010179dSMintz, Yuval snprintf(bit_name, 30, 11006010179dSMintz, Yuval p_aeu->bit_name, num); 11016010179dSMintz, Yuval else 11026010179dSMintz, Yuval strncpy(bit_name, 11036010179dSMintz, Yuval p_aeu->bit_name, 30); 11046010179dSMintz, Yuval 11056010179dSMintz, Yuval /* We now need to pass bitmask in its 11066010179dSMintz, Yuval * correct position. 11076010179dSMintz, Yuval */ 11086010179dSMintz, Yuval bitmask <<= bit; 11096010179dSMintz, Yuval 11100d956e8aSYuval Mintz /* Handle source of the attention */ 11110d956e8aSYuval Mintz qed_int_deassertion_aeu_bit(p_hwfn, 11120d956e8aSYuval Mintz p_aeu, 11130d956e8aSYuval Mintz aeu_en, 11146010179dSMintz, Yuval bit_name, 11150d956e8aSYuval Mintz bitmask); 11160d956e8aSYuval Mintz } 11170d956e8aSYuval Mintz 11180d956e8aSYuval Mintz bit_idx += ATTENTION_LENGTH(p_aeu->flags); 11190d956e8aSYuval Mintz } 11200d956e8aSYuval Mintz } 11210d956e8aSYuval Mintz } 1122cc875c2eSYuval Mintz 1123d4476b8aSDenis Bolotin /* Handle missed DORQ attention */ 1124d4476b8aSDenis Bolotin qed_dorq_attn_handler(p_hwfn); 1125d4476b8aSDenis Bolotin 1126cc875c2eSYuval Mintz /* Clear IGU indication for the deasserted bits */ 1127cc875c2eSYuval Mintz DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview + 1128cc875c2eSYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 1129cc875c2eSYuval Mintz ((IGU_CMD_ATTN_BIT_CLR_UPPER - 1130cc875c2eSYuval Mintz IGU_CMD_INT_ACK_BASE) << 3), 1131cc875c2eSYuval Mintz ~((u32)deasserted_bits)); 1132cc875c2eSYuval Mintz 1133cc875c2eSYuval Mintz /* Unmask deasserted attentions in IGU */ 11341a635e48SYuval Mintz aeu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE); 1135cc875c2eSYuval Mintz aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE); 1136cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask); 1137cc875c2eSYuval Mintz 1138cc875c2eSYuval Mintz /* Clear deassertion from inner state */ 1139cc875c2eSYuval Mintz sb_attn_sw->known_attn &= ~deasserted_bits; 1140cc875c2eSYuval Mintz 11410d956e8aSYuval Mintz return rc; 1142cc875c2eSYuval Mintz } 1143cc875c2eSYuval Mintz 1144cc875c2eSYuval Mintz static int qed_int_attentions(struct qed_hwfn *p_hwfn) 1145cc875c2eSYuval Mintz { 1146cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn; 1147cc875c2eSYuval Mintz struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn; 1148cc875c2eSYuval Mintz u32 attn_bits = 0, attn_acks = 0; 1149cc875c2eSYuval Mintz u16 asserted_bits, deasserted_bits; 1150cc875c2eSYuval Mintz __le16 index; 1151cc875c2eSYuval Mintz int rc = 0; 1152cc875c2eSYuval Mintz 1153cc875c2eSYuval Mintz /* Read current attention bits/acks - safeguard against attentions 1154cc875c2eSYuval Mintz * by guaranting work on a synchronized timeframe 1155cc875c2eSYuval Mintz */ 1156cc875c2eSYuval Mintz do { 1157cc875c2eSYuval Mintz index = p_sb_attn->sb_index; 1158ed4eac20SDenis Bolotin /* finish reading index before the loop condition */ 1159ed4eac20SDenis Bolotin dma_rmb(); 1160cc875c2eSYuval Mintz attn_bits = le32_to_cpu(p_sb_attn->atten_bits); 1161cc875c2eSYuval Mintz attn_acks = le32_to_cpu(p_sb_attn->atten_ack); 1162cc875c2eSYuval Mintz } while (index != p_sb_attn->sb_index); 1163cc875c2eSYuval Mintz p_sb_attn->sb_index = index; 1164cc875c2eSYuval Mintz 1165cc875c2eSYuval Mintz /* Attention / Deassertion are meaningful (and in correct state) 1166cc875c2eSYuval Mintz * only when they differ and consistent with known state - deassertion 1167cc875c2eSYuval Mintz * when previous attention & current ack, and assertion when current 1168cc875c2eSYuval Mintz * attention with no previous attention 1169cc875c2eSYuval Mintz */ 1170cc875c2eSYuval Mintz asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) & 1171cc875c2eSYuval Mintz ~p_sb_attn_sw->known_attn; 1172cc875c2eSYuval Mintz deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) & 1173cc875c2eSYuval Mintz p_sb_attn_sw->known_attn; 1174cc875c2eSYuval Mintz 1175cc875c2eSYuval Mintz if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100)) { 1176cc875c2eSYuval Mintz DP_INFO(p_hwfn, 1177cc875c2eSYuval Mintz "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n", 1178cc875c2eSYuval Mintz index, attn_bits, attn_acks, asserted_bits, 1179cc875c2eSYuval Mintz deasserted_bits, p_sb_attn_sw->known_attn); 1180cc875c2eSYuval Mintz } else if (asserted_bits == 0x100) { 11811a635e48SYuval Mintz DP_INFO(p_hwfn, "MFW indication via attention\n"); 1182cc875c2eSYuval Mintz } else { 1183cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1184cc875c2eSYuval Mintz "MFW indication [deassertion]\n"); 1185cc875c2eSYuval Mintz } 1186cc875c2eSYuval Mintz 1187cc875c2eSYuval Mintz if (asserted_bits) { 1188cc875c2eSYuval Mintz rc = qed_int_assertion(p_hwfn, asserted_bits); 1189cc875c2eSYuval Mintz if (rc) 1190cc875c2eSYuval Mintz return rc; 1191cc875c2eSYuval Mintz } 1192cc875c2eSYuval Mintz 11931a635e48SYuval Mintz if (deasserted_bits) 1194cc875c2eSYuval Mintz rc = qed_int_deassertion(p_hwfn, deasserted_bits); 1195cc875c2eSYuval Mintz 1196cc875c2eSYuval Mintz return rc; 1197cc875c2eSYuval Mintz } 1198cc875c2eSYuval Mintz 1199cc875c2eSYuval Mintz static void qed_sb_ack_attn(struct qed_hwfn *p_hwfn, 12001a635e48SYuval Mintz void __iomem *igu_addr, u32 ack_cons) 1201cc875c2eSYuval Mintz { 1202cc875c2eSYuval Mintz struct igu_prod_cons_update igu_ack = { 0 }; 1203cc875c2eSYuval Mintz 1204cc875c2eSYuval Mintz igu_ack.sb_id_and_flags = 1205cc875c2eSYuval Mintz ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) | 1206cc875c2eSYuval Mintz (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) | 1207cc875c2eSYuval Mintz (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) | 1208cc875c2eSYuval Mintz (IGU_SEG_ACCESS_ATTN << 1209cc875c2eSYuval Mintz IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT)); 1210cc875c2eSYuval Mintz 1211cc875c2eSYuval Mintz DIRECT_REG_WR(igu_addr, igu_ack.sb_id_and_flags); 1212cc875c2eSYuval Mintz 1213cc875c2eSYuval Mintz /* Both segments (interrupts & acks) are written to same place address; 1214cc875c2eSYuval Mintz * Need to guarantee all commands will be received (in-order) by HW. 1215cc875c2eSYuval Mintz */ 1216cc875c2eSYuval Mintz mmiowb(); 1217cc875c2eSYuval Mintz barrier(); 1218cc875c2eSYuval Mintz } 1219cc875c2eSYuval Mintz 1220fe56b9e6SYuval Mintz void qed_int_sp_dpc(unsigned long hwfn_cookie) 1221fe56b9e6SYuval Mintz { 1222fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = (struct qed_hwfn *)hwfn_cookie; 1223fe56b9e6SYuval Mintz struct qed_pi_info *pi_info = NULL; 1224cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn; 1225fe56b9e6SYuval Mintz struct qed_sb_info *sb_info; 1226fe56b9e6SYuval Mintz int arr_size; 1227fe56b9e6SYuval Mintz u16 rc = 0; 1228fe56b9e6SYuval Mintz 1229fe56b9e6SYuval Mintz if (!p_hwfn->p_sp_sb) { 1230fe56b9e6SYuval Mintz DP_ERR(p_hwfn->cdev, "DPC called - no p_sp_sb\n"); 1231fe56b9e6SYuval Mintz return; 1232fe56b9e6SYuval Mintz } 1233fe56b9e6SYuval Mintz 1234fe56b9e6SYuval Mintz sb_info = &p_hwfn->p_sp_sb->sb_info; 1235fe56b9e6SYuval Mintz arr_size = ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr); 1236fe56b9e6SYuval Mintz if (!sb_info) { 1237fe56b9e6SYuval Mintz DP_ERR(p_hwfn->cdev, 1238fe56b9e6SYuval Mintz "Status block is NULL - cannot ack interrupts\n"); 1239fe56b9e6SYuval Mintz return; 1240fe56b9e6SYuval Mintz } 1241fe56b9e6SYuval Mintz 1242cc875c2eSYuval Mintz if (!p_hwfn->p_sb_attn) { 1243cc875c2eSYuval Mintz DP_ERR(p_hwfn->cdev, "DPC called - no p_sb_attn"); 1244cc875c2eSYuval Mintz return; 1245cc875c2eSYuval Mintz } 1246cc875c2eSYuval Mintz sb_attn = p_hwfn->p_sb_attn; 1247cc875c2eSYuval Mintz 1248fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "DPC Called! (hwfn %p %d)\n", 1249fe56b9e6SYuval Mintz p_hwfn, p_hwfn->my_id); 1250fe56b9e6SYuval Mintz 1251fe56b9e6SYuval Mintz /* Disable ack for def status block. Required both for msix + 1252fe56b9e6SYuval Mintz * inta in non-mask mode, in inta does no harm. 1253fe56b9e6SYuval Mintz */ 1254fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_DISABLE, 0); 1255fe56b9e6SYuval Mintz 1256fe56b9e6SYuval Mintz /* Gather Interrupts/Attentions information */ 1257fe56b9e6SYuval Mintz if (!sb_info->sb_virt) { 12581a635e48SYuval Mintz DP_ERR(p_hwfn->cdev, 1259fe56b9e6SYuval Mintz "Interrupt Status block is NULL - cannot check for new interrupts!\n"); 1260fe56b9e6SYuval Mintz } else { 1261fe56b9e6SYuval Mintz u32 tmp_index = sb_info->sb_ack; 1262fe56b9e6SYuval Mintz 1263fe56b9e6SYuval Mintz rc = qed_sb_update_sb_idx(sb_info); 1264fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 1265fe56b9e6SYuval Mintz "Interrupt indices: 0x%08x --> 0x%08x\n", 1266fe56b9e6SYuval Mintz tmp_index, sb_info->sb_ack); 1267fe56b9e6SYuval Mintz } 1268fe56b9e6SYuval Mintz 1269cc875c2eSYuval Mintz if (!sb_attn || !sb_attn->sb_attn) { 12701a635e48SYuval Mintz DP_ERR(p_hwfn->cdev, 1271cc875c2eSYuval Mintz "Attentions Status block is NULL - cannot check for new attentions!\n"); 1272cc875c2eSYuval Mintz } else { 1273cc875c2eSYuval Mintz u16 tmp_index = sb_attn->index; 1274cc875c2eSYuval Mintz 1275cc875c2eSYuval Mintz rc |= qed_attn_update_idx(p_hwfn, sb_attn); 1276cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR, 1277cc875c2eSYuval Mintz "Attention indices: 0x%08x --> 0x%08x\n", 1278cc875c2eSYuval Mintz tmp_index, sb_attn->index); 1279cc875c2eSYuval Mintz } 1280cc875c2eSYuval Mintz 1281fe56b9e6SYuval Mintz /* Check if we expect interrupts at this time. if not just ack them */ 1282fe56b9e6SYuval Mintz if (!(rc & QED_SB_EVENT_MASK)) { 1283fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1284fe56b9e6SYuval Mintz return; 1285fe56b9e6SYuval Mintz } 1286fe56b9e6SYuval Mintz 1287fe56b9e6SYuval Mintz /* Check the validity of the DPC ptt. If not ack interrupts and fail */ 1288fe56b9e6SYuval Mintz if (!p_hwfn->p_dpc_ptt) { 1289fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn->cdev, "Failed to allocate PTT\n"); 1290fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1291fe56b9e6SYuval Mintz return; 1292fe56b9e6SYuval Mintz } 1293fe56b9e6SYuval Mintz 1294cc875c2eSYuval Mintz if (rc & QED_SB_ATT_IDX) 1295cc875c2eSYuval Mintz qed_int_attentions(p_hwfn); 1296cc875c2eSYuval Mintz 1297fe56b9e6SYuval Mintz if (rc & QED_SB_IDX) { 1298fe56b9e6SYuval Mintz int pi; 1299fe56b9e6SYuval Mintz 1300fe56b9e6SYuval Mintz /* Look for a free index */ 1301fe56b9e6SYuval Mintz for (pi = 0; pi < arr_size; pi++) { 1302fe56b9e6SYuval Mintz pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi]; 1303fe56b9e6SYuval Mintz if (pi_info->comp_cb) 1304fe56b9e6SYuval Mintz pi_info->comp_cb(p_hwfn, pi_info->cookie); 1305fe56b9e6SYuval Mintz } 1306fe56b9e6SYuval Mintz } 1307fe56b9e6SYuval Mintz 1308cc875c2eSYuval Mintz if (sb_attn && (rc & QED_SB_ATT_IDX)) 1309cc875c2eSYuval Mintz /* This should be done before the interrupts are enabled, 1310cc875c2eSYuval Mintz * since otherwise a new attention will be generated. 1311cc875c2eSYuval Mintz */ 1312cc875c2eSYuval Mintz qed_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index); 1313cc875c2eSYuval Mintz 1314fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1); 1315fe56b9e6SYuval Mintz } 1316fe56b9e6SYuval Mintz 1317cc875c2eSYuval Mintz static void qed_int_sb_attn_free(struct qed_hwfn *p_hwfn) 1318cc875c2eSYuval Mintz { 1319cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb = p_hwfn->p_sb_attn; 1320cc875c2eSYuval Mintz 13214ac801b7SYuval Mintz if (!p_sb) 13224ac801b7SYuval Mintz return; 13234ac801b7SYuval Mintz 1324cc875c2eSYuval Mintz if (p_sb->sb_attn) 13254ac801b7SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1326cc875c2eSYuval Mintz SB_ATTN_ALIGNED_SIZE(p_hwfn), 13271a635e48SYuval Mintz p_sb->sb_attn, p_sb->sb_phys); 1328cc875c2eSYuval Mintz kfree(p_sb); 13293587cb87STomer Tayar p_hwfn->p_sb_attn = NULL; 1330cc875c2eSYuval Mintz } 1331cc875c2eSYuval Mintz 1332cc875c2eSYuval Mintz static void qed_int_sb_attn_setup(struct qed_hwfn *p_hwfn, 1333cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1334cc875c2eSYuval Mintz { 1335cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 1336cc875c2eSYuval Mintz 1337cc875c2eSYuval Mintz memset(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn)); 1338cc875c2eSYuval Mintz 1339cc875c2eSYuval Mintz sb_info->index = 0; 1340cc875c2eSYuval Mintz sb_info->known_attn = 0; 1341cc875c2eSYuval Mintz 1342cc875c2eSYuval Mintz /* Configure Attention Status Block in IGU */ 1343cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L, 1344cc875c2eSYuval Mintz lower_32_bits(p_hwfn->p_sb_attn->sb_phys)); 1345cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H, 1346cc875c2eSYuval Mintz upper_32_bits(p_hwfn->p_sb_attn->sb_phys)); 1347cc875c2eSYuval Mintz } 1348cc875c2eSYuval Mintz 1349cc875c2eSYuval Mintz static void qed_int_sb_attn_init(struct qed_hwfn *p_hwfn, 1350cc875c2eSYuval Mintz struct qed_ptt *p_ptt, 13511a635e48SYuval Mintz void *sb_virt_addr, dma_addr_t sb_phy_addr) 1352cc875c2eSYuval Mintz { 1353cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn; 13540d956e8aSYuval Mintz int i, j, k; 1355cc875c2eSYuval Mintz 1356cc875c2eSYuval Mintz sb_info->sb_attn = sb_virt_addr; 1357cc875c2eSYuval Mintz sb_info->sb_phys = sb_phy_addr; 1358cc875c2eSYuval Mintz 13590d956e8aSYuval Mintz /* Set the pointer to the AEU descriptors */ 13600d956e8aSYuval Mintz sb_info->p_aeu_desc = aeu_descs; 13610d956e8aSYuval Mintz 13620d956e8aSYuval Mintz /* Calculate Parity Masks */ 13630d956e8aSYuval Mintz memset(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS); 13640d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) { 13650d956e8aSYuval Mintz /* j is array index, k is bit index */ 13660d956e8aSYuval Mintz for (j = 0, k = 0; k < 32; j++) { 1367ba36f718SMintz, Yuval struct aeu_invert_reg_bit *p_aeu; 13680d956e8aSYuval Mintz 1369ba36f718SMintz, Yuval p_aeu = &aeu_descs[i].bits[j]; 1370ba36f718SMintz, Yuval if (qed_int_is_parity_flag(p_hwfn, p_aeu)) 13710d956e8aSYuval Mintz sb_info->parity_mask[i] |= 1 << k; 13720d956e8aSYuval Mintz 1373ba36f718SMintz, Yuval k += ATTENTION_LENGTH(p_aeu->flags); 13740d956e8aSYuval Mintz } 13750d956e8aSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 13760d956e8aSYuval Mintz "Attn Mask [Reg %d]: 0x%08x\n", 13770d956e8aSYuval Mintz i, sb_info->parity_mask[i]); 13780d956e8aSYuval Mintz } 13790d956e8aSYuval Mintz 1380cc875c2eSYuval Mintz /* Set the address of cleanup for the mcp attention */ 1381cc875c2eSYuval Mintz sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) + 1382cc875c2eSYuval Mintz MISC_REG_AEU_GENERAL_ATTN_0; 1383cc875c2eSYuval Mintz 1384cc875c2eSYuval Mintz qed_int_sb_attn_setup(p_hwfn, p_ptt); 1385cc875c2eSYuval Mintz } 1386cc875c2eSYuval Mintz 1387cc875c2eSYuval Mintz static int qed_int_sb_attn_alloc(struct qed_hwfn *p_hwfn, 1388cc875c2eSYuval Mintz struct qed_ptt *p_ptt) 1389cc875c2eSYuval Mintz { 1390cc875c2eSYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 1391cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb; 1392cc875c2eSYuval Mintz dma_addr_t p_phys = 0; 13931a635e48SYuval Mintz void *p_virt; 1394cc875c2eSYuval Mintz 1395cc875c2eSYuval Mintz /* SB struct */ 139660fffb3bSYuval Mintz p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 13972591c280SJoe Perches if (!p_sb) 1398cc875c2eSYuval Mintz return -ENOMEM; 1399cc875c2eSYuval Mintz 1400cc875c2eSYuval Mintz /* SB ring */ 1401cc875c2eSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 1402cc875c2eSYuval Mintz SB_ATTN_ALIGNED_SIZE(p_hwfn), 1403cc875c2eSYuval Mintz &p_phys, GFP_KERNEL); 1404cc875c2eSYuval Mintz 1405cc875c2eSYuval Mintz if (!p_virt) { 1406cc875c2eSYuval Mintz kfree(p_sb); 1407cc875c2eSYuval Mintz return -ENOMEM; 1408cc875c2eSYuval Mintz } 1409cc875c2eSYuval Mintz 1410cc875c2eSYuval Mintz /* Attention setup */ 1411cc875c2eSYuval Mintz p_hwfn->p_sb_attn = p_sb; 1412cc875c2eSYuval Mintz qed_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys); 1413cc875c2eSYuval Mintz 1414cc875c2eSYuval Mintz return 0; 1415cc875c2eSYuval Mintz } 1416cc875c2eSYuval Mintz 1417fe56b9e6SYuval Mintz /* coalescing timeout = timeset << (timer_res + 1) */ 1418fe56b9e6SYuval Mintz #define QED_CAU_DEF_RX_USECS 24 1419fe56b9e6SYuval Mintz #define QED_CAU_DEF_TX_USECS 48 1420fe56b9e6SYuval Mintz 1421fe56b9e6SYuval Mintz void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn, 1422fe56b9e6SYuval Mintz struct cau_sb_entry *p_sb_entry, 14231a635e48SYuval Mintz u8 pf_id, u16 vf_number, u8 vf_valid) 1424fe56b9e6SYuval Mintz { 14254ac801b7SYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 1426fe56b9e6SYuval Mintz u32 cau_state; 1427722003acSSudarsana Reddy Kalluru u8 timer_res; 1428fe56b9e6SYuval Mintz 1429fe56b9e6SYuval Mintz memset(p_sb_entry, 0, sizeof(*p_sb_entry)); 1430fe56b9e6SYuval Mintz 1431fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_PF_NUMBER, pf_id); 1432fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_NUMBER, vf_number); 1433fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_VF_VALID, vf_valid); 1434fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F); 1435fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F); 1436fe56b9e6SYuval Mintz 1437fe56b9e6SYuval Mintz cau_state = CAU_HC_DISABLE_STATE; 1438fe56b9e6SYuval Mintz 14394ac801b7SYuval Mintz if (cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 1440fe56b9e6SYuval Mintz cau_state = CAU_HC_ENABLE_STATE; 14414ac801b7SYuval Mintz if (!cdev->rx_coalesce_usecs) 14424ac801b7SYuval Mintz cdev->rx_coalesce_usecs = QED_CAU_DEF_RX_USECS; 14434ac801b7SYuval Mintz if (!cdev->tx_coalesce_usecs) 14444ac801b7SYuval Mintz cdev->tx_coalesce_usecs = QED_CAU_DEF_TX_USECS; 1445fe56b9e6SYuval Mintz } 1446fe56b9e6SYuval Mintz 1447722003acSSudarsana Reddy Kalluru /* Coalesce = (timeset << timer-res), timeset is 7bit wide */ 1448722003acSSudarsana Reddy Kalluru if (cdev->rx_coalesce_usecs <= 0x7F) 1449722003acSSudarsana Reddy Kalluru timer_res = 0; 1450722003acSSudarsana Reddy Kalluru else if (cdev->rx_coalesce_usecs <= 0xFF) 1451722003acSSudarsana Reddy Kalluru timer_res = 1; 1452722003acSSudarsana Reddy Kalluru else 1453722003acSSudarsana Reddy Kalluru timer_res = 2; 1454722003acSSudarsana Reddy Kalluru SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 1455722003acSSudarsana Reddy Kalluru 1456722003acSSudarsana Reddy Kalluru if (cdev->tx_coalesce_usecs <= 0x7F) 1457722003acSSudarsana Reddy Kalluru timer_res = 0; 1458722003acSSudarsana Reddy Kalluru else if (cdev->tx_coalesce_usecs <= 0xFF) 1459722003acSSudarsana Reddy Kalluru timer_res = 1; 1460722003acSSudarsana Reddy Kalluru else 1461722003acSSudarsana Reddy Kalluru timer_res = 2; 1462722003acSSudarsana Reddy Kalluru SET_FIELD(p_sb_entry->params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 1463722003acSSudarsana Reddy Kalluru 1464fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE0, cau_state); 1465fe56b9e6SYuval Mintz SET_FIELD(p_sb_entry->data, CAU_SB_ENTRY_STATE1, cau_state); 1466fe56b9e6SYuval Mintz } 1467fe56b9e6SYuval Mintz 14688befd73cSMintz, Yuval static void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn, 14698befd73cSMintz, Yuval struct qed_ptt *p_ptt, 14708befd73cSMintz, Yuval u16 igu_sb_id, 14718befd73cSMintz, Yuval u32 pi_index, 14728befd73cSMintz, Yuval enum qed_coalescing_fsm coalescing_fsm, 14738befd73cSMintz, Yuval u8 timeset) 14748befd73cSMintz, Yuval { 14758befd73cSMintz, Yuval struct cau_pi_entry pi_entry; 14768befd73cSMintz, Yuval u32 sb_offset, pi_offset; 14778befd73cSMintz, Yuval 14788befd73cSMintz, Yuval if (IS_VF(p_hwfn->cdev)) 14798befd73cSMintz, Yuval return; 14808befd73cSMintz, Yuval 148121dd79e8STomer Tayar sb_offset = igu_sb_id * PIS_PER_SB_E4; 14828befd73cSMintz, Yuval memset(&pi_entry, 0, sizeof(struct cau_pi_entry)); 14838befd73cSMintz, Yuval 14848befd73cSMintz, Yuval SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_PI_TIMESET, timeset); 14858befd73cSMintz, Yuval if (coalescing_fsm == QED_COAL_RX_STATE_MACHINE) 14868befd73cSMintz, Yuval SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 0); 14878befd73cSMintz, Yuval else 14888befd73cSMintz, Yuval SET_FIELD(pi_entry.prod, CAU_PI_ENTRY_FSM_SEL, 1); 14898befd73cSMintz, Yuval 14908befd73cSMintz, Yuval pi_offset = sb_offset + pi_index; 14918befd73cSMintz, Yuval if (p_hwfn->hw_init_done) { 14928befd73cSMintz, Yuval qed_wr(p_hwfn, p_ptt, 14938befd73cSMintz, Yuval CAU_REG_PI_MEMORY + pi_offset * sizeof(u32), 14948befd73cSMintz, Yuval *((u32 *)&(pi_entry))); 14958befd73cSMintz, Yuval } else { 14968befd73cSMintz, Yuval STORE_RT_REG(p_hwfn, 14978befd73cSMintz, Yuval CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset, 14988befd73cSMintz, Yuval *((u32 *)&(pi_entry))); 14998befd73cSMintz, Yuval } 15008befd73cSMintz, Yuval } 15018befd73cSMintz, Yuval 1502fe56b9e6SYuval Mintz void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn, 1503fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1504fe56b9e6SYuval Mintz dma_addr_t sb_phys, 15051a635e48SYuval Mintz u16 igu_sb_id, u16 vf_number, u8 vf_valid) 1506fe56b9e6SYuval Mintz { 1507fe56b9e6SYuval Mintz struct cau_sb_entry sb_entry; 1508fe56b9e6SYuval Mintz 1509fe56b9e6SYuval Mintz qed_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id, 1510fe56b9e6SYuval Mintz vf_number, vf_valid); 1511fe56b9e6SYuval Mintz 1512fe56b9e6SYuval Mintz if (p_hwfn->hw_init_done) { 15130a0c5d3bSYuval Mintz /* Wide-bus, initialize via DMAE */ 15140a0c5d3bSYuval Mintz u64 phys_addr = (u64)sb_phys; 1515fe56b9e6SYuval Mintz 15160a0c5d3bSYuval Mintz qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&phys_addr, 15170a0c5d3bSYuval Mintz CAU_REG_SB_ADDR_MEMORY + 15180a0c5d3bSYuval Mintz igu_sb_id * sizeof(u64), 2, 0); 15190a0c5d3bSYuval Mintz qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&sb_entry, 15200a0c5d3bSYuval Mintz CAU_REG_SB_VAR_MEMORY + 15210a0c5d3bSYuval Mintz igu_sb_id * sizeof(u64), 2, 0); 1522fe56b9e6SYuval Mintz } else { 1523fe56b9e6SYuval Mintz /* Initialize Status Block Address */ 1524fe56b9e6SYuval Mintz STORE_RT_REG_AGG(p_hwfn, 1525fe56b9e6SYuval Mintz CAU_REG_SB_ADDR_MEMORY_RT_OFFSET + 1526fe56b9e6SYuval Mintz igu_sb_id * 2, 1527fe56b9e6SYuval Mintz sb_phys); 1528fe56b9e6SYuval Mintz 1529fe56b9e6SYuval Mintz STORE_RT_REG_AGG(p_hwfn, 1530fe56b9e6SYuval Mintz CAU_REG_SB_VAR_MEMORY_RT_OFFSET + 1531fe56b9e6SYuval Mintz igu_sb_id * 2, 1532fe56b9e6SYuval Mintz sb_entry); 1533fe56b9e6SYuval Mintz } 1534fe56b9e6SYuval Mintz 1535fe56b9e6SYuval Mintz /* Configure pi coalescing if set */ 1536fe56b9e6SYuval Mintz if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) { 1537b5a9ee7cSAriel Elior u8 num_tc = p_hwfn->hw_info.num_hw_tc; 1538722003acSSudarsana Reddy Kalluru u8 timeset, timer_res; 1539b5a9ee7cSAriel Elior u8 i; 1540fe56b9e6SYuval Mintz 1541722003acSSudarsana Reddy Kalluru /* timeset = (coalesce >> timer-res), timeset is 7bit wide */ 1542722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->rx_coalesce_usecs <= 0x7F) 1543722003acSSudarsana Reddy Kalluru timer_res = 0; 1544722003acSSudarsana Reddy Kalluru else if (p_hwfn->cdev->rx_coalesce_usecs <= 0xFF) 1545722003acSSudarsana Reddy Kalluru timer_res = 1; 1546722003acSSudarsana Reddy Kalluru else 1547722003acSSudarsana Reddy Kalluru timer_res = 2; 1548722003acSSudarsana Reddy Kalluru timeset = (u8)(p_hwfn->cdev->rx_coalesce_usecs >> timer_res); 1549fe56b9e6SYuval Mintz qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI, 15501a635e48SYuval Mintz QED_COAL_RX_STATE_MACHINE, timeset); 1551fe56b9e6SYuval Mintz 1552722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->tx_coalesce_usecs <= 0x7F) 1553722003acSSudarsana Reddy Kalluru timer_res = 0; 1554722003acSSudarsana Reddy Kalluru else if (p_hwfn->cdev->tx_coalesce_usecs <= 0xFF) 1555722003acSSudarsana Reddy Kalluru timer_res = 1; 1556722003acSSudarsana Reddy Kalluru else 1557722003acSSudarsana Reddy Kalluru timer_res = 2; 1558722003acSSudarsana Reddy Kalluru timeset = (u8)(p_hwfn->cdev->tx_coalesce_usecs >> timer_res); 1559fe56b9e6SYuval Mintz for (i = 0; i < num_tc; i++) { 1560fe56b9e6SYuval Mintz qed_int_cau_conf_pi(p_hwfn, p_ptt, 1561fe56b9e6SYuval Mintz igu_sb_id, TX_PI(i), 1562fe56b9e6SYuval Mintz QED_COAL_TX_STATE_MACHINE, 1563fe56b9e6SYuval Mintz timeset); 1564fe56b9e6SYuval Mintz } 1565fe56b9e6SYuval Mintz } 1566fe56b9e6SYuval Mintz } 1567fe56b9e6SYuval Mintz 1568fe56b9e6SYuval Mintz void qed_int_sb_setup(struct qed_hwfn *p_hwfn, 15691a635e48SYuval Mintz struct qed_ptt *p_ptt, struct qed_sb_info *sb_info) 1570fe56b9e6SYuval Mintz { 1571fe56b9e6SYuval Mintz /* zero status block and ack counter */ 1572fe56b9e6SYuval Mintz sb_info->sb_ack = 0; 1573fe56b9e6SYuval Mintz memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 1574fe56b9e6SYuval Mintz 15751408cc1fSYuval Mintz if (IS_PF(p_hwfn->cdev)) 1576fe56b9e6SYuval Mintz qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys, 1577fe56b9e6SYuval Mintz sb_info->igu_sb_id, 0, 0); 1578fe56b9e6SYuval Mintz } 1579fe56b9e6SYuval Mintz 158009b6b147SMintz, Yuval struct qed_igu_block *qed_get_igu_free_sb(struct qed_hwfn *p_hwfn, bool b_is_pf) 158109b6b147SMintz, Yuval { 158209b6b147SMintz, Yuval struct qed_igu_block *p_block; 158309b6b147SMintz, Yuval u16 igu_id; 158409b6b147SMintz, Yuval 158509b6b147SMintz, Yuval for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); 158609b6b147SMintz, Yuval igu_id++) { 158709b6b147SMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id]; 158809b6b147SMintz, Yuval 158909b6b147SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID) || 159009b6b147SMintz, Yuval !(p_block->status & QED_IGU_STATUS_FREE)) 159109b6b147SMintz, Yuval continue; 159209b6b147SMintz, Yuval 159309b6b147SMintz, Yuval if (!!(p_block->status & QED_IGU_STATUS_PF) == b_is_pf) 159409b6b147SMintz, Yuval return p_block; 159509b6b147SMintz, Yuval } 159609b6b147SMintz, Yuval 159709b6b147SMintz, Yuval return NULL; 159809b6b147SMintz, Yuval } 159909b6b147SMintz, Yuval 1600a333f7f3SMintz, Yuval static u16 qed_get_pf_igu_sb_id(struct qed_hwfn *p_hwfn, u16 vector_id) 1601a333f7f3SMintz, Yuval { 1602a333f7f3SMintz, Yuval struct qed_igu_block *p_block; 1603a333f7f3SMintz, Yuval u16 igu_id; 1604a333f7f3SMintz, Yuval 1605a333f7f3SMintz, Yuval for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); 1606a333f7f3SMintz, Yuval igu_id++) { 1607a333f7f3SMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id]; 1608a333f7f3SMintz, Yuval 1609a333f7f3SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID) || 1610a333f7f3SMintz, Yuval !p_block->is_pf || 1611a333f7f3SMintz, Yuval p_block->vector_number != vector_id) 1612a333f7f3SMintz, Yuval continue; 1613a333f7f3SMintz, Yuval 1614a333f7f3SMintz, Yuval return igu_id; 1615a333f7f3SMintz, Yuval } 1616a333f7f3SMintz, Yuval 1617a333f7f3SMintz, Yuval return QED_SB_INVALID_IDX; 1618a333f7f3SMintz, Yuval } 1619a333f7f3SMintz, Yuval 162050a20714SMintz, Yuval u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id) 1621fe56b9e6SYuval Mintz { 1622fe56b9e6SYuval Mintz u16 igu_sb_id; 1623fe56b9e6SYuval Mintz 1624fe56b9e6SYuval Mintz /* Assuming continuous set of IGU SBs dedicated for given PF */ 1625fe56b9e6SYuval Mintz if (sb_id == QED_SP_SB_ID) 1626fe56b9e6SYuval Mintz igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id; 16271408cc1fSYuval Mintz else if (IS_PF(p_hwfn->cdev)) 1628a333f7f3SMintz, Yuval igu_sb_id = qed_get_pf_igu_sb_id(p_hwfn, sb_id + 1); 16291408cc1fSYuval Mintz else 16301408cc1fSYuval Mintz igu_sb_id = qed_vf_get_igu_sb_id(p_hwfn, sb_id); 1631fe56b9e6SYuval Mintz 1632525ef5c0SYuval Mintz if (sb_id == QED_SP_SB_ID) 1633525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1634525ef5c0SYuval Mintz "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id); 1635525ef5c0SYuval Mintz else 1636525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 1637525ef5c0SYuval Mintz "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id); 1638fe56b9e6SYuval Mintz 1639fe56b9e6SYuval Mintz return igu_sb_id; 1640fe56b9e6SYuval Mintz } 1641fe56b9e6SYuval Mintz 1642fe56b9e6SYuval Mintz int qed_int_sb_init(struct qed_hwfn *p_hwfn, 1643fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1644fe56b9e6SYuval Mintz struct qed_sb_info *sb_info, 16451a635e48SYuval Mintz void *sb_virt_addr, dma_addr_t sb_phy_addr, u16 sb_id) 1646fe56b9e6SYuval Mintz { 1647fe56b9e6SYuval Mintz sb_info->sb_virt = sb_virt_addr; 1648fe56b9e6SYuval Mintz sb_info->sb_phys = sb_phy_addr; 1649fe56b9e6SYuval Mintz 1650fe56b9e6SYuval Mintz sb_info->igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id); 1651fe56b9e6SYuval Mintz 1652fe56b9e6SYuval Mintz if (sb_id != QED_SP_SB_ID) { 165350a20714SMintz, Yuval if (IS_PF(p_hwfn->cdev)) { 165450a20714SMintz, Yuval struct qed_igu_info *p_info; 165550a20714SMintz, Yuval struct qed_igu_block *p_block; 165650a20714SMintz, Yuval 165750a20714SMintz, Yuval p_info = p_hwfn->hw_info.p_igu_info; 165850a20714SMintz, Yuval p_block = &p_info->entry[sb_info->igu_sb_id]; 165950a20714SMintz, Yuval 166050a20714SMintz, Yuval p_block->sb_info = sb_info; 166150a20714SMintz, Yuval p_block->status &= ~QED_IGU_STATUS_FREE; 166250a20714SMintz, Yuval p_info->usage.free_cnt--; 166350a20714SMintz, Yuval } else { 166450a20714SMintz, Yuval qed_vf_set_sb_info(p_hwfn, sb_id, sb_info); 166550a20714SMintz, Yuval } 1666fe56b9e6SYuval Mintz } 1667fe56b9e6SYuval Mintz 1668fe56b9e6SYuval Mintz sb_info->cdev = p_hwfn->cdev; 1669fe56b9e6SYuval Mintz 1670fe56b9e6SYuval Mintz /* The igu address will hold the absolute address that needs to be 1671fe56b9e6SYuval Mintz * written to for a specific status block 1672fe56b9e6SYuval Mintz */ 16731408cc1fSYuval Mintz if (IS_PF(p_hwfn->cdev)) { 1674fe56b9e6SYuval Mintz sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 1675fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 1676fe56b9e6SYuval Mintz (sb_info->igu_sb_id << 3); 16771408cc1fSYuval Mintz } else { 16781408cc1fSYuval Mintz sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview + 16791408cc1fSYuval Mintz PXP_VF_BAR0_START_IGU + 16801408cc1fSYuval Mintz ((IGU_CMD_INT_ACK_BASE + 16811408cc1fSYuval Mintz sb_info->igu_sb_id) << 3); 16821408cc1fSYuval Mintz } 1683fe56b9e6SYuval Mintz 1684fe56b9e6SYuval Mintz sb_info->flags |= QED_SB_INFO_INIT; 1685fe56b9e6SYuval Mintz 1686fe56b9e6SYuval Mintz qed_int_sb_setup(p_hwfn, p_ptt, sb_info); 1687fe56b9e6SYuval Mintz 1688fe56b9e6SYuval Mintz return 0; 1689fe56b9e6SYuval Mintz } 1690fe56b9e6SYuval Mintz 1691fe56b9e6SYuval Mintz int qed_int_sb_release(struct qed_hwfn *p_hwfn, 16921a635e48SYuval Mintz struct qed_sb_info *sb_info, u16 sb_id) 1693fe56b9e6SYuval Mintz { 169450a20714SMintz, Yuval struct qed_igu_block *p_block; 169550a20714SMintz, Yuval struct qed_igu_info *p_info; 169650a20714SMintz, Yuval 169750a20714SMintz, Yuval if (!sb_info) 169850a20714SMintz, Yuval return 0; 1699fe56b9e6SYuval Mintz 1700fe56b9e6SYuval Mintz /* zero status block and ack counter */ 1701fe56b9e6SYuval Mintz sb_info->sb_ack = 0; 1702fe56b9e6SYuval Mintz memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt)); 1703fe56b9e6SYuval Mintz 170450a20714SMintz, Yuval if (IS_VF(p_hwfn->cdev)) { 170550a20714SMintz, Yuval qed_vf_set_sb_info(p_hwfn, sb_id, NULL); 170650a20714SMintz, Yuval return 0; 17074ac801b7SYuval Mintz } 1708fe56b9e6SYuval Mintz 170950a20714SMintz, Yuval p_info = p_hwfn->hw_info.p_igu_info; 171050a20714SMintz, Yuval p_block = &p_info->entry[sb_info->igu_sb_id]; 171150a20714SMintz, Yuval 171250a20714SMintz, Yuval /* Vector 0 is reserved to Default SB */ 171350a20714SMintz, Yuval if (!p_block->vector_number) { 171450a20714SMintz, Yuval DP_ERR(p_hwfn, "Do Not free sp sb using this function"); 171550a20714SMintz, Yuval return -EINVAL; 171650a20714SMintz, Yuval } 171750a20714SMintz, Yuval 171850a20714SMintz, Yuval /* Lose reference to client's SB info, and fix counters */ 171950a20714SMintz, Yuval p_block->sb_info = NULL; 172050a20714SMintz, Yuval p_block->status |= QED_IGU_STATUS_FREE; 172150a20714SMintz, Yuval p_info->usage.free_cnt++; 172250a20714SMintz, Yuval 1723fe56b9e6SYuval Mintz return 0; 1724fe56b9e6SYuval Mintz } 1725fe56b9e6SYuval Mintz 1726fe56b9e6SYuval Mintz static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn) 1727fe56b9e6SYuval Mintz { 1728fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb; 1729fe56b9e6SYuval Mintz 17304ac801b7SYuval Mintz if (!p_sb) 17314ac801b7SYuval Mintz return; 17324ac801b7SYuval Mintz 1733fe56b9e6SYuval Mintz if (p_sb->sb_info.sb_virt) 1734fe56b9e6SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1735fe56b9e6SYuval Mintz SB_ALIGNED_SIZE(p_hwfn), 1736fe56b9e6SYuval Mintz p_sb->sb_info.sb_virt, 1737fe56b9e6SYuval Mintz p_sb->sb_info.sb_phys); 1738fe56b9e6SYuval Mintz kfree(p_sb); 17393587cb87STomer Tayar p_hwfn->p_sp_sb = NULL; 1740fe56b9e6SYuval Mintz } 1741fe56b9e6SYuval Mintz 17421a635e48SYuval Mintz static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1743fe56b9e6SYuval Mintz { 1744fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sb; 1745fe56b9e6SYuval Mintz dma_addr_t p_phys = 0; 1746fe56b9e6SYuval Mintz void *p_virt; 1747fe56b9e6SYuval Mintz 1748fe56b9e6SYuval Mintz /* SB struct */ 174960fffb3bSYuval Mintz p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL); 17502591c280SJoe Perches if (!p_sb) 1751fe56b9e6SYuval Mintz return -ENOMEM; 1752fe56b9e6SYuval Mintz 1753fe56b9e6SYuval Mintz /* SB ring */ 1754fe56b9e6SYuval Mintz p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1755fe56b9e6SYuval Mintz SB_ALIGNED_SIZE(p_hwfn), 1756fe56b9e6SYuval Mintz &p_phys, GFP_KERNEL); 1757fe56b9e6SYuval Mintz if (!p_virt) { 1758fe56b9e6SYuval Mintz kfree(p_sb); 1759fe56b9e6SYuval Mintz return -ENOMEM; 1760fe56b9e6SYuval Mintz } 1761fe56b9e6SYuval Mintz 1762fe56b9e6SYuval Mintz /* Status Block setup */ 1763fe56b9e6SYuval Mintz p_hwfn->p_sp_sb = p_sb; 1764fe56b9e6SYuval Mintz qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt, 1765fe56b9e6SYuval Mintz p_phys, QED_SP_SB_ID); 1766fe56b9e6SYuval Mintz 1767fe56b9e6SYuval Mintz memset(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr)); 1768fe56b9e6SYuval Mintz 1769fe56b9e6SYuval Mintz return 0; 1770fe56b9e6SYuval Mintz } 1771fe56b9e6SYuval Mintz 1772fe56b9e6SYuval Mintz int qed_int_register_cb(struct qed_hwfn *p_hwfn, 1773fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb, 17741a635e48SYuval Mintz void *cookie, u8 *sb_idx, __le16 **p_fw_cons) 1775fe56b9e6SYuval Mintz { 1776fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 17774ac801b7SYuval Mintz int rc = -ENOMEM; 1778fe56b9e6SYuval Mintz u8 pi; 1779fe56b9e6SYuval Mintz 1780fe56b9e6SYuval Mintz /* Look for a free index */ 1781fe56b9e6SYuval Mintz for (pi = 0; pi < ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) { 17824ac801b7SYuval Mintz if (p_sp_sb->pi_info_arr[pi].comp_cb) 17834ac801b7SYuval Mintz continue; 17844ac801b7SYuval Mintz 1785fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb; 1786fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].cookie = cookie; 1787fe56b9e6SYuval Mintz *sb_idx = pi; 1788fe56b9e6SYuval Mintz *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi]; 17894ac801b7SYuval Mintz rc = 0; 1790fe56b9e6SYuval Mintz break; 1791fe56b9e6SYuval Mintz } 1792fe56b9e6SYuval Mintz 17934ac801b7SYuval Mintz return rc; 1794fe56b9e6SYuval Mintz } 1795fe56b9e6SYuval Mintz 1796fe56b9e6SYuval Mintz int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi) 1797fe56b9e6SYuval Mintz { 1798fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb; 1799fe56b9e6SYuval Mintz 18004ac801b7SYuval Mintz if (p_sp_sb->pi_info_arr[pi].comp_cb == NULL) 18014ac801b7SYuval Mintz return -ENOMEM; 18024ac801b7SYuval Mintz 1803fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].comp_cb = NULL; 1804fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].cookie = NULL; 1805fe56b9e6SYuval Mintz 18064ac801b7SYuval Mintz return 0; 1807fe56b9e6SYuval Mintz } 1808fe56b9e6SYuval Mintz 1809fe56b9e6SYuval Mintz u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn) 1810fe56b9e6SYuval Mintz { 1811fe56b9e6SYuval Mintz return p_hwfn->p_sp_sb->sb_info.igu_sb_id; 1812fe56b9e6SYuval Mintz } 1813fe56b9e6SYuval Mintz 1814fe56b9e6SYuval Mintz void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn, 18151a635e48SYuval Mintz struct qed_ptt *p_ptt, enum qed_int_mode int_mode) 1816fe56b9e6SYuval Mintz { 1817cc875c2eSYuval Mintz u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN; 1818fe56b9e6SYuval Mintz 1819fe56b9e6SYuval Mintz p_hwfn->cdev->int_mode = int_mode; 1820fe56b9e6SYuval Mintz switch (p_hwfn->cdev->int_mode) { 1821fe56b9e6SYuval Mintz case QED_INT_MODE_INTA: 1822fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN; 1823fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 1824fe56b9e6SYuval Mintz break; 1825fe56b9e6SYuval Mintz 1826fe56b9e6SYuval Mintz case QED_INT_MODE_MSI: 1827fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 1828fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 1829fe56b9e6SYuval Mintz break; 1830fe56b9e6SYuval Mintz 1831fe56b9e6SYuval Mintz case QED_INT_MODE_MSIX: 1832fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN; 1833fe56b9e6SYuval Mintz break; 1834fe56b9e6SYuval Mintz case QED_INT_MODE_POLL: 1835fe56b9e6SYuval Mintz break; 1836fe56b9e6SYuval Mintz } 1837fe56b9e6SYuval Mintz 1838fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf); 1839fe56b9e6SYuval Mintz } 1840fe56b9e6SYuval Mintz 1841979cead3SMintz, Yuval static void qed_int_igu_enable_attn(struct qed_hwfn *p_hwfn, 1842979cead3SMintz, Yuval struct qed_ptt *p_ptt) 1843fe56b9e6SYuval Mintz { 1844fe56b9e6SYuval Mintz 18450d956e8aSYuval Mintz /* Configure AEU signal change to produce attentions */ 18460d956e8aSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0); 1847cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff); 1848cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff); 18490d956e8aSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff); 1850cc875c2eSYuval Mintz 1851fe56b9e6SYuval Mintz /* Flush the writes to IGU */ 1852fe56b9e6SYuval Mintz mmiowb(); 1853cc875c2eSYuval Mintz 1854cc875c2eSYuval Mintz /* Unmask AEU signals toward IGU */ 1855cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff); 1856979cead3SMintz, Yuval } 1857979cead3SMintz, Yuval 1858979cead3SMintz, Yuval int 1859979cead3SMintz, Yuval qed_int_igu_enable(struct qed_hwfn *p_hwfn, 1860979cead3SMintz, Yuval struct qed_ptt *p_ptt, enum qed_int_mode int_mode) 1861979cead3SMintz, Yuval { 1862979cead3SMintz, Yuval int rc = 0; 1863979cead3SMintz, Yuval 1864979cead3SMintz, Yuval qed_int_igu_enable_attn(p_hwfn, p_ptt); 1865979cead3SMintz, Yuval 18668f16bc97SSudarsana Kalluru if ((int_mode != QED_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) { 18678f16bc97SSudarsana Kalluru rc = qed_slowpath_irq_req(p_hwfn); 18681a635e48SYuval Mintz if (rc) { 18698f16bc97SSudarsana Kalluru DP_NOTICE(p_hwfn, "Slowpath IRQ request failed\n"); 18708f16bc97SSudarsana Kalluru return -EINVAL; 18718f16bc97SSudarsana Kalluru } 18728f16bc97SSudarsana Kalluru p_hwfn->b_int_requested = true; 18738f16bc97SSudarsana Kalluru } 18748f16bc97SSudarsana Kalluru /* Enable interrupt Generation */ 18758f16bc97SSudarsana Kalluru qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode); 18768f16bc97SSudarsana Kalluru p_hwfn->b_int_enabled = 1; 18778f16bc97SSudarsana Kalluru 18788f16bc97SSudarsana Kalluru return rc; 1879fe56b9e6SYuval Mintz } 1880fe56b9e6SYuval Mintz 18811a635e48SYuval Mintz void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1882fe56b9e6SYuval Mintz { 1883fe56b9e6SYuval Mintz p_hwfn->b_int_enabled = 0; 1884fe56b9e6SYuval Mintz 18851408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 18861408cc1fSYuval Mintz return; 18871408cc1fSYuval Mintz 1888fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0); 1889fe56b9e6SYuval Mintz } 1890fe56b9e6SYuval Mintz 1891fe56b9e6SYuval Mintz #define IGU_CLEANUP_SLEEP_LENGTH (1000) 1892b2b897ebSYuval Mintz static void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn, 1893fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1894d031548eSMintz, Yuval u16 igu_sb_id, 1895d031548eSMintz, Yuval bool cleanup_set, u16 opaque_fid) 1896fe56b9e6SYuval Mintz { 1897b2b897ebSYuval Mintz u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0; 1898d031548eSMintz, Yuval u32 pxp_addr = IGU_CMD_INT_ACK_BASE + igu_sb_id; 1899fe56b9e6SYuval Mintz u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH; 1900fe56b9e6SYuval Mintz 1901fe56b9e6SYuval Mintz /* Set the data field */ 1902fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0); 1903fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, 0); 1904fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET); 1905fe56b9e6SYuval Mintz 1906fe56b9e6SYuval Mintz /* Set the control register */ 1907fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr); 1908fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid); 1909fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR); 1910fe56b9e6SYuval Mintz 1911fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data); 1912fe56b9e6SYuval Mintz 1913fe56b9e6SYuval Mintz barrier(); 1914fe56b9e6SYuval Mintz 1915fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl); 1916fe56b9e6SYuval Mintz 1917fe56b9e6SYuval Mintz /* Flush the write to IGU */ 1918fe56b9e6SYuval Mintz mmiowb(); 1919fe56b9e6SYuval Mintz 1920fe56b9e6SYuval Mintz /* calculate where to read the status bit from */ 1921d031548eSMintz, Yuval sb_bit = 1 << (igu_sb_id % 32); 1922d031548eSMintz, Yuval sb_bit_addr = igu_sb_id / 32 * sizeof(u32); 1923fe56b9e6SYuval Mintz 1924fe56b9e6SYuval Mintz sb_bit_addr += IGU_REG_CLEANUP_STATUS_0; 1925fe56b9e6SYuval Mintz 1926fe56b9e6SYuval Mintz /* Now wait for the command to complete */ 1927fe56b9e6SYuval Mintz do { 1928fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, sb_bit_addr); 1929fe56b9e6SYuval Mintz 1930fe56b9e6SYuval Mintz if ((val & sb_bit) == (cleanup_set ? sb_bit : 0)) 1931fe56b9e6SYuval Mintz break; 1932fe56b9e6SYuval Mintz 1933fe56b9e6SYuval Mintz usleep_range(5000, 10000); 1934fe56b9e6SYuval Mintz } while (--sleep_cnt); 1935fe56b9e6SYuval Mintz 1936fe56b9e6SYuval Mintz if (!sleep_cnt) 1937fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 1938fe56b9e6SYuval Mintz "Timeout waiting for clear status 0x%08x [for sb %d]\n", 1939d031548eSMintz, Yuval val, igu_sb_id); 1940fe56b9e6SYuval Mintz } 1941fe56b9e6SYuval Mintz 1942fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn, 1943fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1944d031548eSMintz, Yuval u16 igu_sb_id, u16 opaque, bool b_set) 1945fe56b9e6SYuval Mintz { 19461ac72433SMintz, Yuval struct qed_igu_block *p_block; 1947b2b897ebSYuval Mintz int pi, i; 1948fe56b9e6SYuval Mintz 19491ac72433SMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id]; 19501ac72433SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 19511ac72433SMintz, Yuval "Cleaning SB [%04x]: func_id= %d is_pf = %d vector_num = 0x%0x\n", 19521ac72433SMintz, Yuval igu_sb_id, 19531ac72433SMintz, Yuval p_block->function_id, 19541ac72433SMintz, Yuval p_block->is_pf, p_block->vector_number); 19551ac72433SMintz, Yuval 1956fe56b9e6SYuval Mintz /* Set */ 1957fe56b9e6SYuval Mintz if (b_set) 1958d031548eSMintz, Yuval qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 1, opaque); 1959fe56b9e6SYuval Mintz 1960fe56b9e6SYuval Mintz /* Clear */ 1961d031548eSMintz, Yuval qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 0, opaque); 1962fe56b9e6SYuval Mintz 1963b2b897ebSYuval Mintz /* Wait for the IGU SB to cleanup */ 1964b2b897ebSYuval Mintz for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) { 1965b2b897ebSYuval Mintz u32 val; 1966b2b897ebSYuval Mintz 1967b2b897ebSYuval Mintz val = qed_rd(p_hwfn, p_ptt, 1968d031548eSMintz, Yuval IGU_REG_WRITE_DONE_PENDING + 1969d031548eSMintz, Yuval ((igu_sb_id / 32) * 4)); 1970d031548eSMintz, Yuval if (val & BIT((igu_sb_id % 32))) 1971b2b897ebSYuval Mintz usleep_range(10, 20); 1972b2b897ebSYuval Mintz else 1973b2b897ebSYuval Mintz break; 1974b2b897ebSYuval Mintz } 1975b2b897ebSYuval Mintz if (i == IGU_CLEANUP_SLEEP_LENGTH) 1976b2b897ebSYuval Mintz DP_NOTICE(p_hwfn, 1977b2b897ebSYuval Mintz "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n", 1978d031548eSMintz, Yuval igu_sb_id); 1979b2b897ebSYuval Mintz 1980fe56b9e6SYuval Mintz /* Clear the CAU for the SB */ 1981fe56b9e6SYuval Mintz for (pi = 0; pi < 12; pi++) 1982fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 1983d031548eSMintz, Yuval CAU_REG_PI_MEMORY + (igu_sb_id * 12 + pi) * 4, 0); 1984fe56b9e6SYuval Mintz } 1985fe56b9e6SYuval Mintz 1986fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn, 1987fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1988b2b897ebSYuval Mintz bool b_set, bool b_slowpath) 1989fe56b9e6SYuval Mintz { 19901ac72433SMintz, Yuval struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info; 19911ac72433SMintz, Yuval struct qed_igu_block *p_block; 19921ac72433SMintz, Yuval u16 igu_sb_id = 0; 19931ac72433SMintz, Yuval u32 val = 0; 1994fe56b9e6SYuval Mintz 1995fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION); 1996fe56b9e6SYuval Mintz val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN; 1997fe56b9e6SYuval Mintz val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN; 1998fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val); 1999fe56b9e6SYuval Mintz 20001ac72433SMintz, Yuval for (igu_sb_id = 0; 20011ac72433SMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 20021ac72433SMintz, Yuval p_block = &p_info->entry[igu_sb_id]; 2003fe56b9e6SYuval Mintz 20041ac72433SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID) || 20051ac72433SMintz, Yuval !p_block->is_pf || 20061ac72433SMintz, Yuval (p_block->status & QED_IGU_STATUS_DSB)) 20071ac72433SMintz, Yuval continue; 20081ac72433SMintz, Yuval 2009d031548eSMintz, Yuval qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, igu_sb_id, 2010fe56b9e6SYuval Mintz p_hwfn->hw_info.opaque_fid, 2011fe56b9e6SYuval Mintz b_set); 20121ac72433SMintz, Yuval } 2013fe56b9e6SYuval Mintz 20141ac72433SMintz, Yuval if (b_slowpath) 20151ac72433SMintz, Yuval qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, 20161ac72433SMintz, Yuval p_info->igu_dsb_id, 20171ac72433SMintz, Yuval p_hwfn->hw_info.opaque_fid, 20181ac72433SMintz, Yuval b_set); 2019fe56b9e6SYuval Mintz } 2020fe56b9e6SYuval Mintz 2021ebbdcc66SMintz, Yuval int qed_int_igu_reset_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2022ebbdcc66SMintz, Yuval { 2023ebbdcc66SMintz, Yuval struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info; 2024ebbdcc66SMintz, Yuval struct qed_igu_block *p_block; 2025ebbdcc66SMintz, Yuval int pf_sbs, vf_sbs; 2026ebbdcc66SMintz, Yuval u16 igu_sb_id; 2027ebbdcc66SMintz, Yuval u32 val, rval; 2028ebbdcc66SMintz, Yuval 2029ebbdcc66SMintz, Yuval if (!RESC_NUM(p_hwfn, QED_SB)) { 2030ebbdcc66SMintz, Yuval p_info->b_allow_pf_vf_change = false; 2031ebbdcc66SMintz, Yuval } else { 2032ebbdcc66SMintz, Yuval /* Use the numbers the MFW have provided - 2033ebbdcc66SMintz, Yuval * don't forget MFW accounts for the default SB as well. 2034ebbdcc66SMintz, Yuval */ 2035ebbdcc66SMintz, Yuval p_info->b_allow_pf_vf_change = true; 2036ebbdcc66SMintz, Yuval 2037ebbdcc66SMintz, Yuval if (p_info->usage.cnt != RESC_NUM(p_hwfn, QED_SB) - 1) { 2038ebbdcc66SMintz, Yuval DP_INFO(p_hwfn, 2039ebbdcc66SMintz, Yuval "MFW notifies of 0x%04x PF SBs; IGU indicates of only 0x%04x\n", 2040ebbdcc66SMintz, Yuval RESC_NUM(p_hwfn, QED_SB) - 1, 2041ebbdcc66SMintz, Yuval p_info->usage.cnt); 2042ebbdcc66SMintz, Yuval p_info->usage.cnt = RESC_NUM(p_hwfn, QED_SB) - 1; 2043ebbdcc66SMintz, Yuval } 2044ebbdcc66SMintz, Yuval 2045ebbdcc66SMintz, Yuval if (IS_PF_SRIOV(p_hwfn)) { 2046ebbdcc66SMintz, Yuval u16 vfs = p_hwfn->cdev->p_iov_info->total_vfs; 2047ebbdcc66SMintz, Yuval 2048ebbdcc66SMintz, Yuval if (vfs != p_info->usage.iov_cnt) 2049ebbdcc66SMintz, Yuval DP_VERBOSE(p_hwfn, 2050ebbdcc66SMintz, Yuval NETIF_MSG_INTR, 2051ebbdcc66SMintz, Yuval "0x%04x VF SBs in IGU CAM != PCI configuration 0x%04x\n", 2052ebbdcc66SMintz, Yuval p_info->usage.iov_cnt, vfs); 2053ebbdcc66SMintz, Yuval 2054ebbdcc66SMintz, Yuval /* At this point we know how many SBs we have totally 2055ebbdcc66SMintz, Yuval * in IGU + number of PF SBs. So we can validate that 2056ebbdcc66SMintz, Yuval * we'd have sufficient for VF. 2057ebbdcc66SMintz, Yuval */ 2058ebbdcc66SMintz, Yuval if (vfs > p_info->usage.free_cnt + 2059ebbdcc66SMintz, Yuval p_info->usage.free_cnt_iov - p_info->usage.cnt) { 2060ebbdcc66SMintz, Yuval DP_NOTICE(p_hwfn, 2061ebbdcc66SMintz, Yuval "Not enough SBs for VFs - 0x%04x SBs, from which %04x PFs and %04x are required\n", 2062ebbdcc66SMintz, Yuval p_info->usage.free_cnt + 2063ebbdcc66SMintz, Yuval p_info->usage.free_cnt_iov, 2064ebbdcc66SMintz, Yuval p_info->usage.cnt, vfs); 2065ebbdcc66SMintz, Yuval return -EINVAL; 2066ebbdcc66SMintz, Yuval } 2067ebbdcc66SMintz, Yuval 2068ebbdcc66SMintz, Yuval /* Currently cap the number of VFs SBs by the 2069ebbdcc66SMintz, Yuval * number of VFs. 2070ebbdcc66SMintz, Yuval */ 2071ebbdcc66SMintz, Yuval p_info->usage.iov_cnt = vfs; 2072ebbdcc66SMintz, Yuval } 2073ebbdcc66SMintz, Yuval } 2074ebbdcc66SMintz, Yuval 2075ebbdcc66SMintz, Yuval /* Mark all SBs as free, now in the right PF/VFs division */ 2076ebbdcc66SMintz, Yuval p_info->usage.free_cnt = p_info->usage.cnt; 2077ebbdcc66SMintz, Yuval p_info->usage.free_cnt_iov = p_info->usage.iov_cnt; 2078ebbdcc66SMintz, Yuval p_info->usage.orig = p_info->usage.cnt; 2079ebbdcc66SMintz, Yuval p_info->usage.iov_orig = p_info->usage.iov_cnt; 2080ebbdcc66SMintz, Yuval 2081ebbdcc66SMintz, Yuval /* We now proceed to re-configure the IGU cam to reflect the initial 2082ebbdcc66SMintz, Yuval * configuration. We can start with the Default SB. 2083ebbdcc66SMintz, Yuval */ 2084ebbdcc66SMintz, Yuval pf_sbs = p_info->usage.cnt; 2085ebbdcc66SMintz, Yuval vf_sbs = p_info->usage.iov_cnt; 2086ebbdcc66SMintz, Yuval 2087ebbdcc66SMintz, Yuval for (igu_sb_id = p_info->igu_dsb_id; 2088ebbdcc66SMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 2089ebbdcc66SMintz, Yuval p_block = &p_info->entry[igu_sb_id]; 2090ebbdcc66SMintz, Yuval val = 0; 2091ebbdcc66SMintz, Yuval 2092ebbdcc66SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID)) 2093ebbdcc66SMintz, Yuval continue; 2094ebbdcc66SMintz, Yuval 2095ebbdcc66SMintz, Yuval if (p_block->status & QED_IGU_STATUS_DSB) { 2096ebbdcc66SMintz, Yuval p_block->function_id = p_hwfn->rel_pf_id; 2097ebbdcc66SMintz, Yuval p_block->is_pf = 1; 2098ebbdcc66SMintz, Yuval p_block->vector_number = 0; 2099ebbdcc66SMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2100ebbdcc66SMintz, Yuval QED_IGU_STATUS_PF | 2101ebbdcc66SMintz, Yuval QED_IGU_STATUS_DSB; 2102ebbdcc66SMintz, Yuval } else if (pf_sbs) { 2103ebbdcc66SMintz, Yuval pf_sbs--; 2104ebbdcc66SMintz, Yuval p_block->function_id = p_hwfn->rel_pf_id; 2105ebbdcc66SMintz, Yuval p_block->is_pf = 1; 2106ebbdcc66SMintz, Yuval p_block->vector_number = p_info->usage.cnt - pf_sbs; 2107ebbdcc66SMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2108ebbdcc66SMintz, Yuval QED_IGU_STATUS_PF | 2109ebbdcc66SMintz, Yuval QED_IGU_STATUS_FREE; 2110ebbdcc66SMintz, Yuval } else if (vf_sbs) { 2111ebbdcc66SMintz, Yuval p_block->function_id = 2112ebbdcc66SMintz, Yuval p_hwfn->cdev->p_iov_info->first_vf_in_pf + 2113ebbdcc66SMintz, Yuval p_info->usage.iov_cnt - vf_sbs; 2114ebbdcc66SMintz, Yuval p_block->is_pf = 0; 2115ebbdcc66SMintz, Yuval p_block->vector_number = 0; 2116ebbdcc66SMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2117ebbdcc66SMintz, Yuval QED_IGU_STATUS_FREE; 2118ebbdcc66SMintz, Yuval vf_sbs--; 2119ebbdcc66SMintz, Yuval } else { 2120ebbdcc66SMintz, Yuval p_block->function_id = 0; 2121ebbdcc66SMintz, Yuval p_block->is_pf = 0; 2122ebbdcc66SMintz, Yuval p_block->vector_number = 0; 2123ebbdcc66SMintz, Yuval } 2124ebbdcc66SMintz, Yuval 2125ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER, 2126ebbdcc66SMintz, Yuval p_block->function_id); 2127ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf); 2128ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER, 2129ebbdcc66SMintz, Yuval p_block->vector_number); 2130ebbdcc66SMintz, Yuval 2131ebbdcc66SMintz, Yuval /* VF entries would be enabled when VF is initializaed */ 2132ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf); 2133ebbdcc66SMintz, Yuval 2134ebbdcc66SMintz, Yuval rval = qed_rd(p_hwfn, p_ptt, 2135ebbdcc66SMintz, Yuval IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id); 2136ebbdcc66SMintz, Yuval 2137ebbdcc66SMintz, Yuval if (rval != val) { 2138ebbdcc66SMintz, Yuval qed_wr(p_hwfn, p_ptt, 2139ebbdcc66SMintz, Yuval IGU_REG_MAPPING_MEMORY + 2140ebbdcc66SMintz, Yuval sizeof(u32) * igu_sb_id, val); 2141ebbdcc66SMintz, Yuval 2142ebbdcc66SMintz, Yuval DP_VERBOSE(p_hwfn, 2143ebbdcc66SMintz, Yuval NETIF_MSG_INTR, 2144ebbdcc66SMintz, Yuval "IGU reset: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x [%08x -> %08x]\n", 2145ebbdcc66SMintz, Yuval igu_sb_id, 2146ebbdcc66SMintz, Yuval p_block->function_id, 2147ebbdcc66SMintz, Yuval p_block->is_pf, 2148ebbdcc66SMintz, Yuval p_block->vector_number, rval, val); 2149ebbdcc66SMintz, Yuval } 2150ebbdcc66SMintz, Yuval } 2151ebbdcc66SMintz, Yuval 2152ebbdcc66SMintz, Yuval return 0; 2153ebbdcc66SMintz, Yuval } 2154ebbdcc66SMintz, Yuval 2155d749dd0dSMintz, Yuval static void qed_int_igu_read_cam_block(struct qed_hwfn *p_hwfn, 2156d749dd0dSMintz, Yuval struct qed_ptt *p_ptt, u16 igu_sb_id) 21574ac801b7SYuval Mintz { 21584ac801b7SYuval Mintz u32 val = qed_rd(p_hwfn, p_ptt, 2159d749dd0dSMintz, Yuval IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id); 21604ac801b7SYuval Mintz struct qed_igu_block *p_block; 21614ac801b7SYuval Mintz 2162d749dd0dSMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id]; 21634ac801b7SYuval Mintz 21644ac801b7SYuval Mintz /* Fill the block information */ 2165d749dd0dSMintz, Yuval p_block->function_id = GET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER); 21664ac801b7SYuval Mintz p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID); 2167d749dd0dSMintz, Yuval p_block->vector_number = GET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER); 21681ac72433SMintz, Yuval p_block->igu_sb_id = igu_sb_id; 21694ac801b7SYuval Mintz } 21704ac801b7SYuval Mintz 21711a635e48SYuval Mintz int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2172fe56b9e6SYuval Mintz { 2173fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 2174d749dd0dSMintz, Yuval struct qed_igu_block *p_block; 2175d749dd0dSMintz, Yuval u32 min_vf = 0, max_vf = 0; 2176d749dd0dSMintz, Yuval u16 igu_sb_id; 2177fe56b9e6SYuval Mintz 217860fffb3bSYuval Mintz p_hwfn->hw_info.p_igu_info = kzalloc(sizeof(*p_igu_info), GFP_KERNEL); 2179fe56b9e6SYuval Mintz if (!p_hwfn->hw_info.p_igu_info) 2180fe56b9e6SYuval Mintz return -ENOMEM; 2181fe56b9e6SYuval Mintz 2182fe56b9e6SYuval Mintz p_igu_info = p_hwfn->hw_info.p_igu_info; 2183fe56b9e6SYuval Mintz 2184d749dd0dSMintz, Yuval /* Distinguish between existent and non-existent default SB */ 2185d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id = QED_SB_INVALID_IDX; 2186d749dd0dSMintz, Yuval 2187d749dd0dSMintz, Yuval /* Find the range of VF ids whose SB belong to this PF */ 21881408cc1fSYuval Mintz if (p_hwfn->cdev->p_iov_info) { 21891408cc1fSYuval Mintz struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info; 21901408cc1fSYuval Mintz 21911408cc1fSYuval Mintz min_vf = p_iov->first_vf_in_pf; 21921408cc1fSYuval Mintz max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs; 21931408cc1fSYuval Mintz } 21941408cc1fSYuval Mintz 2195d749dd0dSMintz, Yuval for (igu_sb_id = 0; 2196d749dd0dSMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) { 2197d749dd0dSMintz, Yuval /* Read current entry; Notice it might not belong to this PF */ 2198d749dd0dSMintz, Yuval qed_int_igu_read_cam_block(p_hwfn, p_ptt, igu_sb_id); 2199d749dd0dSMintz, Yuval p_block = &p_igu_info->entry[igu_sb_id]; 2200fe56b9e6SYuval Mintz 2201d749dd0dSMintz, Yuval if ((p_block->is_pf) && 2202d749dd0dSMintz, Yuval (p_block->function_id == p_hwfn->rel_pf_id)) { 2203d749dd0dSMintz, Yuval p_block->status = QED_IGU_STATUS_PF | 2204d749dd0dSMintz, Yuval QED_IGU_STATUS_VALID | 2205d749dd0dSMintz, Yuval QED_IGU_STATUS_FREE; 2206fe56b9e6SYuval Mintz 22071ac72433SMintz, Yuval if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX) 2208726fdbe9SMintz, Yuval p_igu_info->usage.cnt++; 2209d749dd0dSMintz, Yuval } else if (!(p_block->is_pf) && 2210d749dd0dSMintz, Yuval (p_block->function_id >= min_vf) && 2211d749dd0dSMintz, Yuval (p_block->function_id < max_vf)) { 22121408cc1fSYuval Mintz /* Available for VFs of this PF */ 2213d749dd0dSMintz, Yuval p_block->status = QED_IGU_STATUS_VALID | 2214d749dd0dSMintz, Yuval QED_IGU_STATUS_FREE; 2215d749dd0dSMintz, Yuval 22161ac72433SMintz, Yuval if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX) 2217726fdbe9SMintz, Yuval p_igu_info->usage.iov_cnt++; 22181408cc1fSYuval Mintz } 22195a1f965aSMintz, Yuval 2220d749dd0dSMintz, Yuval /* Mark the First entry belonging to the PF or its VFs 2221ebbdcc66SMintz, Yuval * as the default SB [we'll reset IGU prior to first usage]. 22225a1f965aSMintz, Yuval */ 2223d749dd0dSMintz, Yuval if ((p_block->status & QED_IGU_STATUS_VALID) && 2224d749dd0dSMintz, Yuval (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX)) { 2225d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id = igu_sb_id; 2226d749dd0dSMintz, Yuval p_block->status |= QED_IGU_STATUS_DSB; 2227d749dd0dSMintz, Yuval } 22285a1f965aSMintz, Yuval 2229d749dd0dSMintz, Yuval /* limit number of prints by having each PF print only its 2230d749dd0dSMintz, Yuval * entries with the exception of PF0 which would print 2231d749dd0dSMintz, Yuval * everything. 2232d749dd0dSMintz, Yuval */ 2233d749dd0dSMintz, Yuval if ((p_block->status & QED_IGU_STATUS_VALID) || 2234d749dd0dSMintz, Yuval (p_hwfn->abs_pf_id == 0)) { 2235d749dd0dSMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2236d749dd0dSMintz, Yuval "IGU_BLOCK: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n", 2237d749dd0dSMintz, Yuval igu_sb_id, p_block->function_id, 2238d749dd0dSMintz, Yuval p_block->is_pf, p_block->vector_number); 2239d749dd0dSMintz, Yuval } 2240d749dd0dSMintz, Yuval } 2241d749dd0dSMintz, Yuval 2242d749dd0dSMintz, Yuval if (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX) { 22435a1f965aSMintz, Yuval DP_NOTICE(p_hwfn, 2244d749dd0dSMintz, Yuval "IGU CAM returned invalid values igu_dsb_id=0x%x\n", 2245d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id); 22465a1f965aSMintz, Yuval return -EINVAL; 22475a1f965aSMintz, Yuval } 2248d749dd0dSMintz, Yuval 2249d749dd0dSMintz, Yuval /* All non default SB are considered free at this point */ 2250726fdbe9SMintz, Yuval p_igu_info->usage.free_cnt = p_igu_info->usage.cnt; 2251726fdbe9SMintz, Yuval p_igu_info->usage.free_cnt_iov = p_igu_info->usage.iov_cnt; 2252fe56b9e6SYuval Mintz 2253d749dd0dSMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, 2254ebbdcc66SMintz, Yuval "igu_dsb_id=0x%x, num Free SBs - PF: %04x VF: %04x [might change after resource allocation]\n", 2255d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id, 2256726fdbe9SMintz, Yuval p_igu_info->usage.cnt, p_igu_info->usage.iov_cnt); 2257fe56b9e6SYuval Mintz 2258fe56b9e6SYuval Mintz return 0; 2259fe56b9e6SYuval Mintz } 2260fe56b9e6SYuval Mintz 2261fe56b9e6SYuval Mintz /** 2262fe56b9e6SYuval Mintz * @brief Initialize igu runtime registers 2263fe56b9e6SYuval Mintz * 2264fe56b9e6SYuval Mintz * @param p_hwfn 2265fe56b9e6SYuval Mintz */ 2266fe56b9e6SYuval Mintz void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn) 2267fe56b9e6SYuval Mintz { 22681a635e48SYuval Mintz u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN; 2269fe56b9e6SYuval Mintz 2270fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf); 2271fe56b9e6SYuval Mintz } 2272fe56b9e6SYuval Mintz 2273fe56b9e6SYuval Mintz u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn) 2274fe56b9e6SYuval Mintz { 2275fe56b9e6SYuval Mintz u32 lsb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_LSB_UPPER - 2276fe56b9e6SYuval Mintz IGU_CMD_INT_ACK_BASE; 2277fe56b9e6SYuval Mintz u32 msb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_MSB_UPPER - 2278fe56b9e6SYuval Mintz IGU_CMD_INT_ACK_BASE; 22791a635e48SYuval Mintz u32 intr_status_hi = 0, intr_status_lo = 0; 22801a635e48SYuval Mintz u64 intr_status = 0; 2281fe56b9e6SYuval Mintz 2282fe56b9e6SYuval Mintz intr_status_lo = REG_RD(p_hwfn, 2283fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 2284fe56b9e6SYuval Mintz lsb_igu_cmd_addr * 8); 2285fe56b9e6SYuval Mintz intr_status_hi = REG_RD(p_hwfn, 2286fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD + 2287fe56b9e6SYuval Mintz msb_igu_cmd_addr * 8); 2288fe56b9e6SYuval Mintz intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo; 2289fe56b9e6SYuval Mintz 2290fe56b9e6SYuval Mintz return intr_status; 2291fe56b9e6SYuval Mintz } 2292fe56b9e6SYuval Mintz 2293fe56b9e6SYuval Mintz static void qed_int_sp_dpc_setup(struct qed_hwfn *p_hwfn) 2294fe56b9e6SYuval Mintz { 2295fe56b9e6SYuval Mintz tasklet_init(p_hwfn->sp_dpc, 2296fe56b9e6SYuval Mintz qed_int_sp_dpc, (unsigned long)p_hwfn); 2297fe56b9e6SYuval Mintz p_hwfn->b_sp_dpc_enabled = true; 2298fe56b9e6SYuval Mintz } 2299fe56b9e6SYuval Mintz 2300fe56b9e6SYuval Mintz static int qed_int_sp_dpc_alloc(struct qed_hwfn *p_hwfn) 2301fe56b9e6SYuval Mintz { 230260fffb3bSYuval Mintz p_hwfn->sp_dpc = kmalloc(sizeof(*p_hwfn->sp_dpc), GFP_KERNEL); 2303fe56b9e6SYuval Mintz if (!p_hwfn->sp_dpc) 2304fe56b9e6SYuval Mintz return -ENOMEM; 2305fe56b9e6SYuval Mintz 2306fe56b9e6SYuval Mintz return 0; 2307fe56b9e6SYuval Mintz } 2308fe56b9e6SYuval Mintz 2309fe56b9e6SYuval Mintz static void qed_int_sp_dpc_free(struct qed_hwfn *p_hwfn) 2310fe56b9e6SYuval Mintz { 2311fe56b9e6SYuval Mintz kfree(p_hwfn->sp_dpc); 23123587cb87STomer Tayar p_hwfn->sp_dpc = NULL; 2313fe56b9e6SYuval Mintz } 2314fe56b9e6SYuval Mintz 23151a635e48SYuval Mintz int qed_int_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2316fe56b9e6SYuval Mintz { 2317fe56b9e6SYuval Mintz int rc = 0; 2318fe56b9e6SYuval Mintz 2319fe56b9e6SYuval Mintz rc = qed_int_sp_dpc_alloc(p_hwfn); 232083aeb933SYuval Mintz if (rc) 23212591c280SJoe Perches return rc; 23222591c280SJoe Perches 23232591c280SJoe Perches rc = qed_int_sp_sb_alloc(p_hwfn, p_ptt); 23242591c280SJoe Perches if (rc) 23252591c280SJoe Perches return rc; 23262591c280SJoe Perches 23272591c280SJoe Perches rc = qed_int_sb_attn_alloc(p_hwfn, p_ptt); 232883aeb933SYuval Mintz 2329fe56b9e6SYuval Mintz return rc; 2330fe56b9e6SYuval Mintz } 2331fe56b9e6SYuval Mintz 2332fe56b9e6SYuval Mintz void qed_int_free(struct qed_hwfn *p_hwfn) 2333fe56b9e6SYuval Mintz { 2334fe56b9e6SYuval Mintz qed_int_sp_sb_free(p_hwfn); 2335cc875c2eSYuval Mintz qed_int_sb_attn_free(p_hwfn); 2336fe56b9e6SYuval Mintz qed_int_sp_dpc_free(p_hwfn); 2337fe56b9e6SYuval Mintz } 2338fe56b9e6SYuval Mintz 23391a635e48SYuval Mintz void qed_int_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2340fe56b9e6SYuval Mintz { 23410d956e8aSYuval Mintz qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info); 23420d956e8aSYuval Mintz qed_int_sb_attn_setup(p_hwfn, p_ptt); 2343fe56b9e6SYuval Mintz qed_int_sp_dpc_setup(p_hwfn); 2344fe56b9e6SYuval Mintz } 2345fe56b9e6SYuval Mintz 23464ac801b7SYuval Mintz void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn, 23474ac801b7SYuval Mintz struct qed_sb_cnt_info *p_sb_cnt_info) 2348fe56b9e6SYuval Mintz { 2349fe56b9e6SYuval Mintz struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info; 2350fe56b9e6SYuval Mintz 23514ac801b7SYuval Mintz if (!info || !p_sb_cnt_info) 23524ac801b7SYuval Mintz return; 2353fe56b9e6SYuval Mintz 2354726fdbe9SMintz, Yuval memcpy(p_sb_cnt_info, &info->usage, sizeof(*p_sb_cnt_info)); 2355fe56b9e6SYuval Mintz } 23568f16bc97SSudarsana Kalluru 23578f16bc97SSudarsana Kalluru void qed_int_disable_post_isr_release(struct qed_dev *cdev) 23588f16bc97SSudarsana Kalluru { 23598f16bc97SSudarsana Kalluru int i; 23608f16bc97SSudarsana Kalluru 23618f16bc97SSudarsana Kalluru for_each_hwfn(cdev, i) 23628f16bc97SSudarsana Kalluru cdev->hwfns[i].b_int_requested = false; 23638f16bc97SSudarsana Kalluru } 2364722003acSSudarsana Reddy Kalluru 2365722003acSSudarsana Reddy Kalluru int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2366722003acSSudarsana Reddy Kalluru u8 timer_res, u16 sb_id, bool tx) 2367722003acSSudarsana Reddy Kalluru { 2368722003acSSudarsana Reddy Kalluru struct cau_sb_entry sb_entry; 2369722003acSSudarsana Reddy Kalluru int rc; 2370722003acSSudarsana Reddy Kalluru 2371722003acSSudarsana Reddy Kalluru if (!p_hwfn->hw_init_done) { 2372722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "hardware not initialized yet\n"); 2373722003acSSudarsana Reddy Kalluru return -EINVAL; 2374722003acSSudarsana Reddy Kalluru } 2375722003acSSudarsana Reddy Kalluru 2376722003acSSudarsana Reddy Kalluru rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY + 2377722003acSSudarsana Reddy Kalluru sb_id * sizeof(u64), 2378722003acSSudarsana Reddy Kalluru (u64)(uintptr_t)&sb_entry, 2, 0); 2379722003acSSudarsana Reddy Kalluru if (rc) { 2380722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc); 2381722003acSSudarsana Reddy Kalluru return rc; 2382722003acSSudarsana Reddy Kalluru } 2383722003acSSudarsana Reddy Kalluru 2384722003acSSudarsana Reddy Kalluru if (tx) 2385722003acSSudarsana Reddy Kalluru SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES1, timer_res); 2386722003acSSudarsana Reddy Kalluru else 2387722003acSSudarsana Reddy Kalluru SET_FIELD(sb_entry.params, CAU_SB_ENTRY_TIMER_RES0, timer_res); 2388722003acSSudarsana Reddy Kalluru 2389722003acSSudarsana Reddy Kalluru rc = qed_dmae_host2grc(p_hwfn, p_ptt, 2390722003acSSudarsana Reddy Kalluru (u64)(uintptr_t)&sb_entry, 2391722003acSSudarsana Reddy Kalluru CAU_REG_SB_VAR_MEMORY + 2392722003acSSudarsana Reddy Kalluru sb_id * sizeof(u64), 2, 0); 2393722003acSSudarsana Reddy Kalluru if (rc) { 2394722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc); 2395722003acSSudarsana Reddy Kalluru return rc; 2396722003acSSudarsana Reddy Kalluru } 2397722003acSSudarsana Reddy Kalluru 2398722003acSSudarsana Reddy Kalluru return rc; 2399722003acSSudarsana Reddy Kalluru } 2400