11f4d4ed6SAlexander Lobakin // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2fe56b9e6SYuval Mintz /* QLogic qed NIC Driver
3e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation
4663eacd8SAlexander Lobakin * Copyright (c) 2019-2020 Marvell International Ltd.
5fe56b9e6SYuval Mintz */
6fe56b9e6SYuval Mintz
7fe56b9e6SYuval Mintz #include <linux/types.h>
8fe56b9e6SYuval Mintz #include <asm/byteorder.h>
9fe56b9e6SYuval Mintz #include <linux/io.h>
10fe56b9e6SYuval Mintz #include <linux/bitops.h>
11fe56b9e6SYuval Mintz #include <linux/delay.h>
12fe56b9e6SYuval Mintz #include <linux/dma-mapping.h>
13fe56b9e6SYuval Mintz #include <linux/errno.h>
14fe56b9e6SYuval Mintz #include <linux/interrupt.h>
15fe56b9e6SYuval Mintz #include <linux/kernel.h>
16fe56b9e6SYuval Mintz #include <linux/pci.h>
17fe56b9e6SYuval Mintz #include <linux/slab.h>
18fe56b9e6SYuval Mintz #include <linux/string.h>
19fe56b9e6SYuval Mintz #include "qed.h"
20fe56b9e6SYuval Mintz #include "qed_hsi.h"
21fe56b9e6SYuval Mintz #include "qed_hw.h"
22fe56b9e6SYuval Mintz #include "qed_init_ops.h"
23fe56b9e6SYuval Mintz #include "qed_int.h"
24fe56b9e6SYuval Mintz #include "qed_mcp.h"
25fe56b9e6SYuval Mintz #include "qed_reg_addr.h"
26fe56b9e6SYuval Mintz #include "qed_sp.h"
271408cc1fSYuval Mintz #include "qed_sriov.h"
281408cc1fSYuval Mintz #include "qed_vf.h"
29fe56b9e6SYuval Mintz
30fe56b9e6SYuval Mintz struct qed_pi_info {
31fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb;
32fe56b9e6SYuval Mintz void *cookie;
33fe56b9e6SYuval Mintz };
34fe56b9e6SYuval Mintz
35fe56b9e6SYuval Mintz struct qed_sb_sp_info {
36fe56b9e6SYuval Mintz struct qed_sb_info sb_info;
37fe56b9e6SYuval Mintz
38fe56b9e6SYuval Mintz /* per protocol index data */
39fb09a1edSShai Malin struct qed_pi_info pi_info_arr[PIS_PER_SB];
40fe56b9e6SYuval Mintz };
41fe56b9e6SYuval Mintz
42ff38577aSYuval Mintz enum qed_attention_type {
43ff38577aSYuval Mintz QED_ATTN_TYPE_ATTN,
44ff38577aSYuval Mintz QED_ATTN_TYPE_PARITY,
45ff38577aSYuval Mintz };
46ff38577aSYuval Mintz
47cc875c2eSYuval Mintz #define SB_ATTN_ALIGNED_SIZE(p_hwfn) \
48cc875c2eSYuval Mintz ALIGNED_TYPE_SIZE(struct atten_status_block, p_hwfn)
49cc875c2eSYuval Mintz
500d956e8aSYuval Mintz struct aeu_invert_reg_bit {
510d956e8aSYuval Mintz char bit_name[30];
520d956e8aSYuval Mintz
530d956e8aSYuval Mintz #define ATTENTION_PARITY (1 << 0)
540d956e8aSYuval Mintz
550d956e8aSYuval Mintz #define ATTENTION_LENGTH_MASK (0x00000ff0)
560d956e8aSYuval Mintz #define ATTENTION_LENGTH_SHIFT (4)
570d956e8aSYuval Mintz #define ATTENTION_LENGTH(flags) (((flags) & ATTENTION_LENGTH_MASK) >> \
580d956e8aSYuval Mintz ATTENTION_LENGTH_SHIFT)
59a2e7699eSTomer Tayar #define ATTENTION_SINGLE BIT(ATTENTION_LENGTH_SHIFT)
600d956e8aSYuval Mintz #define ATTENTION_PAR (ATTENTION_SINGLE | ATTENTION_PARITY)
610d956e8aSYuval Mintz #define ATTENTION_PAR_INT ((2 << ATTENTION_LENGTH_SHIFT) | \
620d956e8aSYuval Mintz ATTENTION_PARITY)
630d956e8aSYuval Mintz
640d956e8aSYuval Mintz /* Multiple bits start with this offset */
650d956e8aSYuval Mintz #define ATTENTION_OFFSET_MASK (0x000ff000)
660d956e8aSYuval Mintz #define ATTENTION_OFFSET_SHIFT (12)
67ba36f718SMintz, Yuval
68ba36f718SMintz, Yuval #define ATTENTION_BB_MASK (0x00700000)
69ba36f718SMintz, Yuval #define ATTENTION_BB_SHIFT (20)
70ba36f718SMintz, Yuval #define ATTENTION_BB(value) (value << ATTENTION_BB_SHIFT)
71ba36f718SMintz, Yuval #define ATTENTION_BB_DIFFERENT BIT(23)
72ba36f718SMintz, Yuval
73936c7ba4SIgor Russkikh #define ATTENTION_CLEAR_ENABLE BIT(28)
740d956e8aSYuval Mintz unsigned int flags;
75ff38577aSYuval Mintz
76b4149dc7SYuval Mintz /* Callback to call if attention will be triggered */
77b4149dc7SYuval Mintz int (*cb)(struct qed_hwfn *p_hwfn);
78b4149dc7SYuval Mintz
79ff38577aSYuval Mintz enum block_id block_index;
800d956e8aSYuval Mintz };
810d956e8aSYuval Mintz
820d956e8aSYuval Mintz struct aeu_invert_reg {
830d956e8aSYuval Mintz struct aeu_invert_reg_bit bits[32];
840d956e8aSYuval Mintz };
850d956e8aSYuval Mintz
860d956e8aSYuval Mintz #define MAX_ATTN_GRPS (8)
870d956e8aSYuval Mintz #define NUM_ATTN_REGS (9)
880d956e8aSYuval Mintz
89b4149dc7SYuval Mintz /* Specific HW attention callbacks */
qed_mcp_attn_cb(struct qed_hwfn * p_hwfn)90b4149dc7SYuval Mintz static int qed_mcp_attn_cb(struct qed_hwfn *p_hwfn)
91b4149dc7SYuval Mintz {
92b4149dc7SYuval Mintz u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_STATE);
93b4149dc7SYuval Mintz
94b4149dc7SYuval Mintz /* This might occur on certain instances; Log it once then mask it */
95b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev, "MCP_REG_CPU_STATE: %08x - Masking...\n",
96b4149dc7SYuval Mintz tmp);
97b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MCP_REG_CPU_EVENT_MASK,
98b4149dc7SYuval Mintz 0xffffffff);
99b4149dc7SYuval Mintz
100b4149dc7SYuval Mintz return 0;
101b4149dc7SYuval Mintz }
102b4149dc7SYuval Mintz
103b4149dc7SYuval Mintz #define QED_PSWHST_ATTENTION_INCORRECT_ACCESS (0x1)
104b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_WR_MASK (0x1)
105b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_WR_SHIFT (0)
106b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_CLIENT_MASK (0xf)
107b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_CLIENT_SHIFT (1)
108b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_VALID_MASK (0x1)
109b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_VALID_SHIFT (5)
110b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_ID_MASK (0xff)
111b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_VF_ID_SHIFT (6)
112b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_PF_ID_MASK (0xf)
113b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_PF_ID_SHIFT (14)
114b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_MASK (0xff)
115b4149dc7SYuval Mintz #define ATTENTION_INCORRECT_ACCESS_BYTE_EN_SHIFT (18)
qed_pswhst_attn_cb(struct qed_hwfn * p_hwfn)116b4149dc7SYuval Mintz static int qed_pswhst_attn_cb(struct qed_hwfn *p_hwfn)
117b4149dc7SYuval Mintz {
118b4149dc7SYuval Mintz u32 tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
119b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_VALID);
120b4149dc7SYuval Mintz
121b4149dc7SYuval Mintz if (tmp & QED_PSWHST_ATTENTION_INCORRECT_ACCESS) {
122b4149dc7SYuval Mintz u32 addr, data, length;
123b4149dc7SYuval Mintz
124b4149dc7SYuval Mintz addr = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
125b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_ADDRESS);
126b4149dc7SYuval Mintz data = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
127b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_DATA);
128b4149dc7SYuval Mintz length = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
129b4149dc7SYuval Mintz PSWHST_REG_INCORRECT_ACCESS_LENGTH);
130b4149dc7SYuval Mintz
131b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev,
132b4149dc7SYuval Mintz "Incorrect access to %08x of length %08x - PF [%02x] VF [%04x] [valid %02x] client [%02x] write [%02x] Byte-Enable [%04x] [%08x]\n",
133b4149dc7SYuval Mintz addr, length,
134b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_PF_ID),
135b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_VF_ID),
136b4149dc7SYuval Mintz (u8) GET_FIELD(data,
137b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_VF_VALID),
138b4149dc7SYuval Mintz (u8) GET_FIELD(data,
139b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_CLIENT),
140b4149dc7SYuval Mintz (u8) GET_FIELD(data, ATTENTION_INCORRECT_ACCESS_WR),
141b4149dc7SYuval Mintz (u8) GET_FIELD(data,
142b4149dc7SYuval Mintz ATTENTION_INCORRECT_ACCESS_BYTE_EN),
143b4149dc7SYuval Mintz data);
144b4149dc7SYuval Mintz }
145b4149dc7SYuval Mintz
146b4149dc7SYuval Mintz return 0;
147b4149dc7SYuval Mintz }
148b4149dc7SYuval Mintz
149b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VALID_BIT (1 << 0)
150b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_ADDRESS_MASK (0x7fffff)
151b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_ADDRESS_SHIFT (0)
152b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_RDWR_BIT (1 << 23)
153b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_MASTER_MASK (0xf)
154b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_MASTER_SHIFT (24)
155b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PF_MASK (0xf)
156b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PF_SHIFT (0)
157b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VF_MASK (0xff)
158b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_VF_SHIFT (4)
159b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_MASK (0x3)
160b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_SHIFT (14)
161b4149dc7SYuval Mintz #define QED_GRC_ATTENTION_PRIV_VF (0)
attn_master_to_str(u8 master)162b4149dc7SYuval Mintz static const char *attn_master_to_str(u8 master)
163b4149dc7SYuval Mintz {
164b4149dc7SYuval Mintz switch (master) {
165b4149dc7SYuval Mintz case 1: return "PXP";
166b4149dc7SYuval Mintz case 2: return "MCP";
167b4149dc7SYuval Mintz case 3: return "MSDM";
168b4149dc7SYuval Mintz case 4: return "PSDM";
169b4149dc7SYuval Mintz case 5: return "YSDM";
170b4149dc7SYuval Mintz case 6: return "USDM";
171b4149dc7SYuval Mintz case 7: return "TSDM";
172b4149dc7SYuval Mintz case 8: return "XSDM";
173b4149dc7SYuval Mintz case 9: return "DBU";
174b4149dc7SYuval Mintz case 10: return "DMAE";
175b4149dc7SYuval Mintz default:
1769165dabbSMasanari Iida return "Unknown";
177b4149dc7SYuval Mintz }
178b4149dc7SYuval Mintz }
179b4149dc7SYuval Mintz
qed_grc_attn_cb(struct qed_hwfn * p_hwfn)180b4149dc7SYuval Mintz static int qed_grc_attn_cb(struct qed_hwfn *p_hwfn)
181b4149dc7SYuval Mintz {
182b4149dc7SYuval Mintz u32 tmp, tmp2;
183b4149dc7SYuval Mintz
184b4149dc7SYuval Mintz /* We've already cleared the timeout interrupt register, so we learn
185b4149dc7SYuval Mintz * of interrupts via the validity register
186b4149dc7SYuval Mintz */
187b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
188b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_VALID);
189b4149dc7SYuval Mintz if (!(tmp & QED_GRC_ATTENTION_VALID_BIT))
190b4149dc7SYuval Mintz goto out;
191b4149dc7SYuval Mintz
192b4149dc7SYuval Mintz /* Read the GRC timeout information */
193b4149dc7SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
194b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0);
195b4149dc7SYuval Mintz tmp2 = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
196b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_1);
197b4149dc7SYuval Mintz
198b4149dc7SYuval Mintz DP_INFO(p_hwfn->cdev,
199b4149dc7SYuval Mintz "GRC timeout [%08x:%08x] - %s Address [%08x] [Master %s] [PF: %02x %s %02x]\n",
200b4149dc7SYuval Mintz tmp2, tmp,
201b4149dc7SYuval Mintz (tmp & QED_GRC_ATTENTION_RDWR_BIT) ? "Write to" : "Read from",
202b4149dc7SYuval Mintz GET_FIELD(tmp, QED_GRC_ATTENTION_ADDRESS) << 2,
203b4149dc7SYuval Mintz attn_master_to_str(GET_FIELD(tmp, QED_GRC_ATTENTION_MASTER)),
204b4149dc7SYuval Mintz GET_FIELD(tmp2, QED_GRC_ATTENTION_PF),
205b4149dc7SYuval Mintz (GET_FIELD(tmp2, QED_GRC_ATTENTION_PRIV) ==
206fbe1222cSColin Ian King QED_GRC_ATTENTION_PRIV_VF) ? "VF" : "(Irrelevant)",
207b4149dc7SYuval Mintz GET_FIELD(tmp2, QED_GRC_ATTENTION_VF));
208b4149dc7SYuval Mintz
209b4149dc7SYuval Mintz out:
210b4149dc7SYuval Mintz /* Regardles of anything else, clean the validity bit */
211b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt,
212b4149dc7SYuval Mintz GRC_REG_TIMEOUT_ATTN_ACCESS_VALID, 0);
213b4149dc7SYuval Mintz return 0;
214b4149dc7SYuval Mintz }
215b4149dc7SYuval Mintz
216b4149dc7SYuval Mintz #define PGLUE_ATTENTION_VALID (1 << 29)
217b4149dc7SYuval Mintz #define PGLUE_ATTENTION_RD_VALID (1 << 26)
218b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_PFID_MASK (0xf)
219b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_PFID_SHIFT (20)
220b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VF_VALID_MASK (0x1)
221b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VF_VALID_SHIFT (19)
222b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VFID_MASK (0xff)
223b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS_VFID_SHIFT (24)
224b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_MASK (0x1)
225b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_WAS_ERR_SHIFT (21)
226b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_BME_MASK (0x1)
227b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_BME_SHIFT (22)
228b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_FID_EN_MASK (0x1)
229b4149dc7SYuval Mintz #define PGLUE_ATTENTION_DETAILS2_FID_EN_SHIFT (23)
230b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ICPL_VALID (1 << 23)
231b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ZLR_VALID (1 << 25)
232b4149dc7SYuval Mintz #define PGLUE_ATTENTION_ILT_VALID (1 << 23)
233666db486STomer Tayar
qed_pglueb_rbc_attn_handler(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,bool hw_init)234eb61c2d6SAlexander Lobakin int qed_pglueb_rbc_attn_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
235eb61c2d6SAlexander Lobakin bool hw_init)
236b4149dc7SYuval Mintz {
237eb61c2d6SAlexander Lobakin char msg[256];
238b4149dc7SYuval Mintz u32 tmp;
239b4149dc7SYuval Mintz
240666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS2);
241b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_VALID) {
242b4149dc7SYuval Mintz u32 addr_lo, addr_hi, details;
243b4149dc7SYuval Mintz
244666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt,
245b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_ADD_31_0);
246666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt,
247b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_ADD_63_32);
248666db486STomer Tayar details = qed_rd(p_hwfn, p_ptt,
249b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_WR_DETAILS);
250b4149dc7SYuval Mintz
251eb61c2d6SAlexander Lobakin snprintf(msg, sizeof(msg),
252b4149dc7SYuval Mintz "Illegal write by chip to [%08x:%08x] blocked.\n"
253b4149dc7SYuval Mintz "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n"
254eb61c2d6SAlexander Lobakin "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]",
255b4149dc7SYuval Mintz addr_hi, addr_lo, details,
256b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID),
257b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID),
258eb61c2d6SAlexander Lobakin !!GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VF_VALID),
259b4149dc7SYuval Mintz tmp,
260eb61c2d6SAlexander Lobakin !!GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_WAS_ERR),
261eb61c2d6SAlexander Lobakin !!GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_BME),
262eb61c2d6SAlexander Lobakin !!GET_FIELD(tmp, PGLUE_ATTENTION_DETAILS2_FID_EN));
263eb61c2d6SAlexander Lobakin
264eb61c2d6SAlexander Lobakin if (hw_init)
265eb61c2d6SAlexander Lobakin DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "%s\n", msg);
266eb61c2d6SAlexander Lobakin else
267eb61c2d6SAlexander Lobakin DP_NOTICE(p_hwfn, "%s\n", msg);
268b4149dc7SYuval Mintz }
269b4149dc7SYuval Mintz
270666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_RD_DETAILS2);
271b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_RD_VALID) {
272b4149dc7SYuval Mintz u32 addr_lo, addr_hi, details;
273b4149dc7SYuval Mintz
274666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt,
275b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_ADD_31_0);
276666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt,
277b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_ADD_63_32);
278666db486STomer Tayar details = qed_rd(p_hwfn, p_ptt,
279b4149dc7SYuval Mintz PGLUE_B_REG_TX_ERR_RD_DETAILS);
280b4149dc7SYuval Mintz
281666db486STomer Tayar DP_NOTICE(p_hwfn,
282b4149dc7SYuval Mintz "Illegal read by chip from [%08x:%08x] blocked.\n"
283b4149dc7SYuval Mintz "Details: %08x [PFID %02x, VFID %02x, VF_VALID %02x]\n"
284b4149dc7SYuval Mintz "Details2 %08x [Was_error %02x BME deassert %02x FID_enable deassert %02x]\n",
285b4149dc7SYuval Mintz addr_hi, addr_lo, details,
286b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_PFID),
287b4149dc7SYuval Mintz (u8)GET_FIELD(details, PGLUE_ATTENTION_DETAILS_VFID),
288b4149dc7SYuval Mintz GET_FIELD(details,
289b4149dc7SYuval Mintz PGLUE_ATTENTION_DETAILS_VF_VALID) ? 1 : 0,
290b4149dc7SYuval Mintz tmp,
291666db486STomer Tayar GET_FIELD(tmp,
292666db486STomer Tayar PGLUE_ATTENTION_DETAILS2_WAS_ERR) ? 1 : 0,
293666db486STomer Tayar GET_FIELD(tmp,
294666db486STomer Tayar PGLUE_ATTENTION_DETAILS2_BME) ? 1 : 0,
295666db486STomer Tayar GET_FIELD(tmp,
296666db486STomer Tayar PGLUE_ATTENTION_DETAILS2_FID_EN) ? 1 : 0);
297b4149dc7SYuval Mintz }
298b4149dc7SYuval Mintz
299666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_TX_ERR_WR_DETAILS_ICPL);
300eb61c2d6SAlexander Lobakin if (tmp & PGLUE_ATTENTION_ICPL_VALID) {
301eb61c2d6SAlexander Lobakin snprintf(msg, sizeof(msg), "ICPL error - %08x", tmp);
302eb61c2d6SAlexander Lobakin
303eb61c2d6SAlexander Lobakin if (hw_init)
304eb61c2d6SAlexander Lobakin DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "%s\n", msg);
305eb61c2d6SAlexander Lobakin else
306eb61c2d6SAlexander Lobakin DP_NOTICE(p_hwfn, "%s\n", msg);
307eb61c2d6SAlexander Lobakin }
308b4149dc7SYuval Mintz
309666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_ZLR_ERR_DETAILS);
310b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ZLR_VALID) {
311b4149dc7SYuval Mintz u32 addr_hi, addr_lo;
312b4149dc7SYuval Mintz
313666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt,
314b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_ADD_31_0);
315666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt,
316b4149dc7SYuval Mintz PGLUE_B_REG_MASTER_ZLR_ERR_ADD_63_32);
317b4149dc7SYuval Mintz
318666db486STomer Tayar DP_NOTICE(p_hwfn, "ZLR error - %08x [Address %08x:%08x]\n",
319b4149dc7SYuval Mintz tmp, addr_hi, addr_lo);
320b4149dc7SYuval Mintz }
321b4149dc7SYuval Mintz
322666db486STomer Tayar tmp = qed_rd(p_hwfn, p_ptt, PGLUE_B_REG_VF_ILT_ERR_DETAILS2);
323b4149dc7SYuval Mintz if (tmp & PGLUE_ATTENTION_ILT_VALID) {
324b4149dc7SYuval Mintz u32 addr_hi, addr_lo, details;
325b4149dc7SYuval Mintz
326666db486STomer Tayar addr_lo = qed_rd(p_hwfn, p_ptt,
327b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_ADD_31_0);
328666db486STomer Tayar addr_hi = qed_rd(p_hwfn, p_ptt,
329b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_ADD_63_32);
330666db486STomer Tayar details = qed_rd(p_hwfn, p_ptt,
331b4149dc7SYuval Mintz PGLUE_B_REG_VF_ILT_ERR_DETAILS);
332b4149dc7SYuval Mintz
333666db486STomer Tayar DP_NOTICE(p_hwfn,
334b4149dc7SYuval Mintz "ILT error - Details %08x Details2 %08x [Address %08x:%08x]\n",
335b4149dc7SYuval Mintz details, tmp, addr_hi, addr_lo);
336b4149dc7SYuval Mintz }
337b4149dc7SYuval Mintz
338b4149dc7SYuval Mintz /* Clear the indications */
339666db486STomer Tayar qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_LATCHED_ERRORS_CLR, BIT(2));
340b4149dc7SYuval Mintz
341b4149dc7SYuval Mintz return 0;
342b4149dc7SYuval Mintz }
343b4149dc7SYuval Mintz
qed_pglueb_rbc_attn_cb(struct qed_hwfn * p_hwfn)344666db486STomer Tayar static int qed_pglueb_rbc_attn_cb(struct qed_hwfn *p_hwfn)
345666db486STomer Tayar {
346eb61c2d6SAlexander Lobakin return qed_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_dpc_ptt, false);
347666db486STomer Tayar }
348666db486STomer Tayar
qed_fw_assertion(struct qed_hwfn * p_hwfn)3492ec276d5SIgor Russkikh static int qed_fw_assertion(struct qed_hwfn *p_hwfn)
3502ec276d5SIgor Russkikh {
3512ec276d5SIgor Russkikh qed_hw_err_notify(p_hwfn, p_hwfn->p_dpc_ptt, QED_HW_ERR_FW_ASSERT,
3522ec276d5SIgor Russkikh "FW assertion!\n");
3532ec276d5SIgor Russkikh
354755f9053SAlok Prasad /* Clear assert indications */
355755f9053SAlok Prasad qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MISC_REG_AEU_GENERAL_ATTN_32, 0);
356755f9053SAlok Prasad
3572ec276d5SIgor Russkikh return -EINVAL;
3582ec276d5SIgor Russkikh }
3592ec276d5SIgor Russkikh
qed_general_attention_35(struct qed_hwfn * p_hwfn)360936c7ba4SIgor Russkikh static int qed_general_attention_35(struct qed_hwfn *p_hwfn)
361936c7ba4SIgor Russkikh {
362936c7ba4SIgor Russkikh DP_INFO(p_hwfn, "General attention 35!\n");
363936c7ba4SIgor Russkikh
364936c7ba4SIgor Russkikh return 0;
365936c7ba4SIgor Russkikh }
366936c7ba4SIgor Russkikh
367b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_REASON_MASK (0xfffff)
368b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_OPAQUE_MASK (0xffff)
369a1b469b8SAriel Elior #define QED_DORQ_ATTENTION_OPAQUE_SHIFT (0x0)
370b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_SIZE_MASK (0x7f)
371b4149dc7SYuval Mintz #define QED_DORQ_ATTENTION_SIZE_SHIFT (16)
372a1b469b8SAriel Elior
373a1b469b8SAriel Elior #define QED_DB_REC_COUNT 1000
374a1b469b8SAriel Elior #define QED_DB_REC_INTERVAL 100
375a1b469b8SAriel Elior
qed_db_rec_flush_queue(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt)376a1b469b8SAriel Elior static int qed_db_rec_flush_queue(struct qed_hwfn *p_hwfn,
377a1b469b8SAriel Elior struct qed_ptt *p_ptt)
378a1b469b8SAriel Elior {
379a1b469b8SAriel Elior u32 count = QED_DB_REC_COUNT;
380a1b469b8SAriel Elior u32 usage = 1;
381a1b469b8SAriel Elior
3820d72c2acSDenis Bolotin /* Flush any pending (e)dpms as they may never arrive */
3830d72c2acSDenis Bolotin qed_wr(p_hwfn, p_ptt, DORQ_REG_DPM_FORCE_ABORT, 0x1);
3840d72c2acSDenis Bolotin
385a1b469b8SAriel Elior /* wait for usage to zero or count to run out. This is necessary since
386a1b469b8SAriel Elior * EDPM doorbell transactions can take multiple 64b cycles, and as such
387a1b469b8SAriel Elior * can "split" over the pci. Possibly, the doorbell drop can happen with
388a1b469b8SAriel Elior * half an EDPM in the queue and other half dropped. Another EDPM
389a1b469b8SAriel Elior * doorbell to the same address (from doorbell recovery mechanism or
390a1b469b8SAriel Elior * from the doorbelling entity) could have first half dropped and second
391a1b469b8SAriel Elior * half interpreted as continuation of the first. To prevent such
392a1b469b8SAriel Elior * malformed doorbells from reaching the device, flush the queue before
393a1b469b8SAriel Elior * releasing the overflow sticky indication.
394a1b469b8SAriel Elior */
395a1b469b8SAriel Elior while (count-- && usage) {
396a1b469b8SAriel Elior usage = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_USAGE_CNT);
397a1b469b8SAriel Elior udelay(QED_DB_REC_INTERVAL);
398a1b469b8SAriel Elior }
399a1b469b8SAriel Elior
400a1b469b8SAriel Elior /* should have been depleted by now */
401a1b469b8SAriel Elior if (usage) {
402a1b469b8SAriel Elior DP_NOTICE(p_hwfn->cdev,
403a1b469b8SAriel Elior "DB recovery: doorbell usage failed to zero after %d usec. usage was %x\n",
404a1b469b8SAriel Elior QED_DB_REC_INTERVAL * QED_DB_REC_COUNT, usage);
405a1b469b8SAriel Elior return -EBUSY;
406a1b469b8SAriel Elior }
407a1b469b8SAriel Elior
408a1b469b8SAriel Elior return 0;
409a1b469b8SAriel Elior }
410a1b469b8SAriel Elior
qed_db_rec_handler(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt)411a1b469b8SAriel Elior int qed_db_rec_handler(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
412a1b469b8SAriel Elior {
4130d72c2acSDenis Bolotin u32 attn_ovfl, cur_ovfl;
414a1b469b8SAriel Elior int rc;
415a1b469b8SAriel Elior
4160d72c2acSDenis Bolotin attn_ovfl = test_and_clear_bit(QED_OVERFLOW_BIT,
4170d72c2acSDenis Bolotin &p_hwfn->db_recovery_info.overflow);
4180d72c2acSDenis Bolotin cur_ovfl = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY);
4190d72c2acSDenis Bolotin if (!cur_ovfl && !attn_ovfl)
420a1b469b8SAriel Elior return 0;
421a1b469b8SAriel Elior
4220d72c2acSDenis Bolotin DP_NOTICE(p_hwfn, "PF Overflow sticky: attn %u current %u\n",
4230d72c2acSDenis Bolotin attn_ovfl, cur_ovfl);
4240d72c2acSDenis Bolotin
4250d72c2acSDenis Bolotin if (cur_ovfl && !p_hwfn->db_bar_no_edpm) {
426a1b469b8SAriel Elior rc = qed_db_rec_flush_queue(p_hwfn, p_ptt);
427a1b469b8SAriel Elior if (rc)
428a1b469b8SAriel Elior return rc;
429a1b469b8SAriel Elior }
430a1b469b8SAriel Elior
431a1b469b8SAriel Elior /* Release overflow sticky indication (stop silently dropping everything) */
432a1b469b8SAriel Elior qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0);
433a1b469b8SAriel Elior
434a1b469b8SAriel Elior /* Repeat all last doorbells (doorbell drop recovery) */
4359ac6bb14SDenis Bolotin qed_db_recovery_execute(p_hwfn);
436a1b469b8SAriel Elior
437a1b469b8SAriel Elior return 0;
438a1b469b8SAriel Elior }
439a1b469b8SAriel Elior
qed_dorq_attn_overflow(struct qed_hwfn * p_hwfn)4400d72c2acSDenis Bolotin static void qed_dorq_attn_overflow(struct qed_hwfn *p_hwfn)
4410d72c2acSDenis Bolotin {
4420d72c2acSDenis Bolotin struct qed_ptt *p_ptt = p_hwfn->p_dpc_ptt;
4430d72c2acSDenis Bolotin u32 overflow;
4440d72c2acSDenis Bolotin int rc;
4450d72c2acSDenis Bolotin
4460d72c2acSDenis Bolotin overflow = qed_rd(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY);
4470d72c2acSDenis Bolotin if (!overflow)
4480d72c2acSDenis Bolotin goto out;
4490d72c2acSDenis Bolotin
4500d72c2acSDenis Bolotin /* Run PF doorbell recovery in next periodic handler */
4510d72c2acSDenis Bolotin set_bit(QED_OVERFLOW_BIT, &p_hwfn->db_recovery_info.overflow);
4520d72c2acSDenis Bolotin
4530d72c2acSDenis Bolotin if (!p_hwfn->db_bar_no_edpm) {
4540d72c2acSDenis Bolotin rc = qed_db_rec_flush_queue(p_hwfn, p_ptt);
4550d72c2acSDenis Bolotin if (rc)
4560d72c2acSDenis Bolotin goto out;
4570d72c2acSDenis Bolotin }
4580d72c2acSDenis Bolotin
4590d72c2acSDenis Bolotin qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_OVFL_STICKY, 0x0);
4600d72c2acSDenis Bolotin out:
4610d72c2acSDenis Bolotin /* Schedule the handler even if overflow was not detected */
4620d72c2acSDenis Bolotin qed_periodic_db_rec_start(p_hwfn);
4630d72c2acSDenis Bolotin }
4640d72c2acSDenis Bolotin
qed_dorq_attn_int_sts(struct qed_hwfn * p_hwfn)4650d72c2acSDenis Bolotin static int qed_dorq_attn_int_sts(struct qed_hwfn *p_hwfn)
466b4149dc7SYuval Mintz {
467a1b469b8SAriel Elior u32 int_sts, first_drop_reason, details, address, all_drops_reason;
468a1b469b8SAriel Elior struct qed_ptt *p_ptt = p_hwfn->p_dpc_ptt;
469a1b469b8SAriel Elior
470cdc1d868SShai Malin int_sts = qed_rd(p_hwfn, p_ptt, DORQ_REG_INT_STS);
471cdc1d868SShai Malin if (int_sts == 0xdeadbeaf) {
472cdc1d868SShai Malin DP_NOTICE(p_hwfn->cdev,
473cdc1d868SShai Malin "DORQ is being reset, skipping int_sts handler\n");
474cdc1d868SShai Malin
475cdc1d868SShai Malin return 0;
476cdc1d868SShai Malin }
477cdc1d868SShai Malin
478a1b469b8SAriel Elior /* int_sts may be zero since all PFs were interrupted for doorbell
479a1b469b8SAriel Elior * overflow but another one already handled it. Can abort here. If
480a1b469b8SAriel Elior * This PF also requires overflow recovery we will be interrupted again.
481a1b469b8SAriel Elior * The masked almost full indication may also be set. Ignoring.
482a1b469b8SAriel Elior */
483a1b469b8SAriel Elior if (!(int_sts & ~DORQ_REG_INT_STS_DORQ_FIFO_AFULL))
484a1b469b8SAriel Elior return 0;
485a1b469b8SAriel Elior
486d4476b8aSDenis Bolotin DP_NOTICE(p_hwfn->cdev, "DORQ attention. int_sts was %x\n", int_sts);
487d4476b8aSDenis Bolotin
488a1b469b8SAriel Elior /* check if db_drop or overflow happened */
489a1b469b8SAriel Elior if (int_sts & (DORQ_REG_INT_STS_DB_DROP |
490a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR)) {
491a1b469b8SAriel Elior /* Obtain data about db drop/overflow */
492a1b469b8SAriel Elior first_drop_reason = qed_rd(p_hwfn, p_ptt,
493a1b469b8SAriel Elior DORQ_REG_DB_DROP_REASON) &
494b4149dc7SYuval Mintz QED_DORQ_ATTENTION_REASON_MASK;
495a1b469b8SAriel Elior details = qed_rd(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS);
496a1b469b8SAriel Elior address = qed_rd(p_hwfn, p_ptt,
497a1b469b8SAriel Elior DORQ_REG_DB_DROP_DETAILS_ADDRESS);
498a1b469b8SAriel Elior all_drops_reason = qed_rd(p_hwfn, p_ptt,
499a1b469b8SAriel Elior DORQ_REG_DB_DROP_DETAILS_REASON);
500b4149dc7SYuval Mintz
501a1b469b8SAriel Elior /* Log info */
502a1b469b8SAriel Elior DP_NOTICE(p_hwfn->cdev,
503a1b469b8SAriel Elior "Doorbell drop occurred\n"
504a1b469b8SAriel Elior "Address\t\t0x%08x\t(second BAR address)\n"
505a1b469b8SAriel Elior "FID\t\t0x%04x\t\t(Opaque FID)\n"
506a1b469b8SAriel Elior "Size\t\t0x%04x\t\t(in bytes)\n"
507a1b469b8SAriel Elior "1st drop reason\t0x%08x\t(details on first drop since last handling)\n"
508a1b469b8SAriel Elior "Sticky reasons\t0x%08x\t(all drop reasons since last handling)\n",
509a1b469b8SAriel Elior address,
510a1b469b8SAriel Elior GET_FIELD(details, QED_DORQ_ATTENTION_OPAQUE),
511b4149dc7SYuval Mintz GET_FIELD(details, QED_DORQ_ATTENTION_SIZE) * 4,
512a1b469b8SAriel Elior first_drop_reason, all_drops_reason);
513a1b469b8SAriel Elior
514a1b469b8SAriel Elior /* Clear the doorbell drop details and prepare for next drop */
515a1b469b8SAriel Elior qed_wr(p_hwfn, p_ptt, DORQ_REG_DB_DROP_DETAILS_REL, 0);
516a1b469b8SAriel Elior
517a1b469b8SAriel Elior /* Mark interrupt as handled (note: even if drop was due to a different
518a1b469b8SAriel Elior * reason than overflow we mark as handled)
519a1b469b8SAriel Elior */
520a1b469b8SAriel Elior qed_wr(p_hwfn,
521a1b469b8SAriel Elior p_ptt,
522a1b469b8SAriel Elior DORQ_REG_INT_STS_WR,
523a1b469b8SAriel Elior DORQ_REG_INT_STS_DB_DROP |
524a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR);
525a1b469b8SAriel Elior
526a1b469b8SAriel Elior /* If there are no indications other than drop indications, success */
527a1b469b8SAriel Elior if ((int_sts & ~(DORQ_REG_INT_STS_DB_DROP |
528a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR |
529a1b469b8SAriel Elior DORQ_REG_INT_STS_DORQ_FIFO_AFULL)) == 0)
530a1b469b8SAriel Elior return 0;
531b4149dc7SYuval Mintz }
532b4149dc7SYuval Mintz
533a1b469b8SAriel Elior /* Some other indication was present - non recoverable */
534a1b469b8SAriel Elior DP_INFO(p_hwfn, "DORQ fatal attention\n");
535a1b469b8SAriel Elior
536b4149dc7SYuval Mintz return -EINVAL;
537b4149dc7SYuval Mintz }
538b4149dc7SYuval Mintz
qed_dorq_attn_cb(struct qed_hwfn * p_hwfn)5390d72c2acSDenis Bolotin static int qed_dorq_attn_cb(struct qed_hwfn *p_hwfn)
5400d72c2acSDenis Bolotin {
541cdc1d868SShai Malin if (p_hwfn->cdev->recov_in_prog)
542cdc1d868SShai Malin return 0;
543cdc1d868SShai Malin
5440d72c2acSDenis Bolotin p_hwfn->db_recovery_info.dorq_attn = true;
5450d72c2acSDenis Bolotin qed_dorq_attn_overflow(p_hwfn);
5460d72c2acSDenis Bolotin
5470d72c2acSDenis Bolotin return qed_dorq_attn_int_sts(p_hwfn);
5480d72c2acSDenis Bolotin }
5490d72c2acSDenis Bolotin
qed_dorq_attn_handler(struct qed_hwfn * p_hwfn)550d4476b8aSDenis Bolotin static void qed_dorq_attn_handler(struct qed_hwfn *p_hwfn)
551d4476b8aSDenis Bolotin {
552d4476b8aSDenis Bolotin if (p_hwfn->db_recovery_info.dorq_attn)
553d4476b8aSDenis Bolotin goto out;
554d4476b8aSDenis Bolotin
555d4476b8aSDenis Bolotin /* Call DORQ callback if the attention was missed */
556d4476b8aSDenis Bolotin qed_dorq_attn_cb(p_hwfn);
557d4476b8aSDenis Bolotin out:
558d4476b8aSDenis Bolotin p_hwfn->db_recovery_info.dorq_attn = false;
559d4476b8aSDenis Bolotin }
560d4476b8aSDenis Bolotin
561ba36f718SMintz, Yuval /* Instead of major changes to the data-structure, we have a some 'special'
562ba36f718SMintz, Yuval * identifiers for sources that changed meaning between adapters.
563ba36f718SMintz, Yuval */
564ba36f718SMintz, Yuval enum aeu_invert_reg_special_type {
565ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_0,
566ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_1,
567ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_2,
568ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_CNIG_3,
569ba36f718SMintz, Yuval AEU_INVERT_REG_SPECIAL_MAX,
570ba36f718SMintz, Yuval };
571ba36f718SMintz, Yuval
572ba36f718SMintz, Yuval static struct aeu_invert_reg_bit
573ba36f718SMintz, Yuval aeu_descs_special[AEU_INVERT_REG_SPECIAL_MAX] = {
574ba36f718SMintz, Yuval {"CNIG port 0", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
575ba36f718SMintz, Yuval {"CNIG port 1", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
576ba36f718SMintz, Yuval {"CNIG port 2", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
577ba36f718SMintz, Yuval {"CNIG port 3", ATTENTION_SINGLE, NULL, BLOCK_CNIG},
578ba36f718SMintz, Yuval };
579ba36f718SMintz, Yuval
5800d956e8aSYuval Mintz /* Notice aeu_invert_reg must be defined in the same order of bits as HW; */
5810d956e8aSYuval Mintz static struct aeu_invert_reg aeu_descs[NUM_ATTN_REGS] = {
5820d956e8aSYuval Mintz {
5830d956e8aSYuval Mintz { /* After Invert 1 */
5840d956e8aSYuval Mintz {"GPIO0 function%d",
585b4149dc7SYuval Mintz (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID},
5860d956e8aSYuval Mintz }
5870d956e8aSYuval Mintz },
5880d956e8aSYuval Mintz
5890d956e8aSYuval Mintz {
5900d956e8aSYuval Mintz { /* After Invert 2 */
591b4149dc7SYuval Mintz {"PGLUE config_space", ATTENTION_SINGLE,
592b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID},
593b4149dc7SYuval Mintz {"PGLUE misc_flr", ATTENTION_SINGLE,
594b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID},
595b4149dc7SYuval Mintz {"PGLUE B RBC", ATTENTION_PAR_INT,
596666db486STomer Tayar qed_pglueb_rbc_attn_cb, BLOCK_PGLUE_B},
597b4149dc7SYuval Mintz {"PGLUE misc_mctp", ATTENTION_SINGLE,
598b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID},
599b4149dc7SYuval Mintz {"Flash event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
600b4149dc7SYuval Mintz {"SMB event", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
601b4149dc7SYuval Mintz {"Main Power", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
6020d956e8aSYuval Mintz {"SW timers #%d", (8 << ATTENTION_LENGTH_SHIFT) |
603ff38577aSYuval Mintz (1 << ATTENTION_OFFSET_SHIFT),
604b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID},
6050d956e8aSYuval Mintz {"PCIE glue/PXP VPD %d",
606b4149dc7SYuval Mintz (16 << ATTENTION_LENGTH_SHIFT), NULL, BLOCK_PGLCS},
6070d956e8aSYuval Mintz }
6080d956e8aSYuval Mintz },
6090d956e8aSYuval Mintz
6100d956e8aSYuval Mintz {
6110d956e8aSYuval Mintz { /* After Invert 3 */
6120d956e8aSYuval Mintz {"General Attention %d",
613b4149dc7SYuval Mintz (32 << ATTENTION_LENGTH_SHIFT), NULL, MAX_BLOCK_ID},
6140d956e8aSYuval Mintz }
6150d956e8aSYuval Mintz },
6160d956e8aSYuval Mintz
6170d956e8aSYuval Mintz {
6180d956e8aSYuval Mintz { /* After Invert 4 */
619936c7ba4SIgor Russkikh {"General Attention 32", ATTENTION_SINGLE |
620936c7ba4SIgor Russkikh ATTENTION_CLEAR_ENABLE, qed_fw_assertion,
6212ec276d5SIgor Russkikh MAX_BLOCK_ID},
6220d956e8aSYuval Mintz {"General Attention %d",
6230d956e8aSYuval Mintz (2 << ATTENTION_LENGTH_SHIFT) |
624b4149dc7SYuval Mintz (33 << ATTENTION_OFFSET_SHIFT), NULL, MAX_BLOCK_ID},
625936c7ba4SIgor Russkikh {"General Attention 35", ATTENTION_SINGLE |
626936c7ba4SIgor Russkikh ATTENTION_CLEAR_ENABLE, qed_general_attention_35,
627936c7ba4SIgor Russkikh MAX_BLOCK_ID},
628ba36f718SMintz, Yuval {"NWS Parity",
629ba36f718SMintz, Yuval ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
630ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_0),
631ba36f718SMintz, Yuval NULL, BLOCK_NWS},
632ba36f718SMintz, Yuval {"NWS Interrupt",
633ba36f718SMintz, Yuval ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
634ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_1),
635ba36f718SMintz, Yuval NULL, BLOCK_NWS},
636ba36f718SMintz, Yuval {"NWM Parity",
637ba36f718SMintz, Yuval ATTENTION_PAR | ATTENTION_BB_DIFFERENT |
638ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_2),
639ba36f718SMintz, Yuval NULL, BLOCK_NWM},
640ba36f718SMintz, Yuval {"NWM Interrupt",
641ba36f718SMintz, Yuval ATTENTION_SINGLE | ATTENTION_BB_DIFFERENT |
642ba36f718SMintz, Yuval ATTENTION_BB(AEU_INVERT_REG_SPECIAL_CNIG_3),
643ba36f718SMintz, Yuval NULL, BLOCK_NWM},
644b4149dc7SYuval Mintz {"MCP CPU", ATTENTION_SINGLE,
645b4149dc7SYuval Mintz qed_mcp_attn_cb, MAX_BLOCK_ID},
646b4149dc7SYuval Mintz {"MCP Watchdog timer", ATTENTION_SINGLE,
647b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID},
648b4149dc7SYuval Mintz {"MCP M2P", ATTENTION_SINGLE, NULL, MAX_BLOCK_ID},
649ff38577aSYuval Mintz {"AVS stop status ready", ATTENTION_SINGLE,
650b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID},
651b4149dc7SYuval Mintz {"MSTAT", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID},
652b4149dc7SYuval Mintz {"MSTAT per-path", ATTENTION_PAR_INT,
653b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID},
654ff38577aSYuval Mintz {"Reserved %d", (6 << ATTENTION_LENGTH_SHIFT),
655b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID},
656b4149dc7SYuval Mintz {"NIG", ATTENTION_PAR_INT, NULL, BLOCK_NIG},
657b4149dc7SYuval Mintz {"BMB/OPTE/MCP", ATTENTION_PAR_INT, NULL, BLOCK_BMB},
658b4149dc7SYuval Mintz {"BTB", ATTENTION_PAR_INT, NULL, BLOCK_BTB},
659b4149dc7SYuval Mintz {"BRB", ATTENTION_PAR_INT, NULL, BLOCK_BRB},
660b4149dc7SYuval Mintz {"PRS", ATTENTION_PAR_INT, NULL, BLOCK_PRS},
6610d956e8aSYuval Mintz }
6620d956e8aSYuval Mintz },
6630d956e8aSYuval Mintz
6640d956e8aSYuval Mintz {
6650d956e8aSYuval Mintz { /* After Invert 5 */
666b4149dc7SYuval Mintz {"SRC", ATTENTION_PAR_INT, NULL, BLOCK_SRC},
667b4149dc7SYuval Mintz {"PB Client1", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB1},
668b4149dc7SYuval Mintz {"PB Client2", ATTENTION_PAR_INT, NULL, BLOCK_PBF_PB2},
669b4149dc7SYuval Mintz {"RPB", ATTENTION_PAR_INT, NULL, BLOCK_RPB},
670b4149dc7SYuval Mintz {"PBF", ATTENTION_PAR_INT, NULL, BLOCK_PBF},
671b4149dc7SYuval Mintz {"QM", ATTENTION_PAR_INT, NULL, BLOCK_QM},
672b4149dc7SYuval Mintz {"TM", ATTENTION_PAR_INT, NULL, BLOCK_TM},
673b4149dc7SYuval Mintz {"MCM", ATTENTION_PAR_INT, NULL, BLOCK_MCM},
674b4149dc7SYuval Mintz {"MSDM", ATTENTION_PAR_INT, NULL, BLOCK_MSDM},
675b4149dc7SYuval Mintz {"MSEM", ATTENTION_PAR_INT, NULL, BLOCK_MSEM},
676b4149dc7SYuval Mintz {"PCM", ATTENTION_PAR_INT, NULL, BLOCK_PCM},
677b4149dc7SYuval Mintz {"PSDM", ATTENTION_PAR_INT, NULL, BLOCK_PSDM},
678b4149dc7SYuval Mintz {"PSEM", ATTENTION_PAR_INT, NULL, BLOCK_PSEM},
679b4149dc7SYuval Mintz {"TCM", ATTENTION_PAR_INT, NULL, BLOCK_TCM},
680b4149dc7SYuval Mintz {"TSDM", ATTENTION_PAR_INT, NULL, BLOCK_TSDM},
681b4149dc7SYuval Mintz {"TSEM", ATTENTION_PAR_INT, NULL, BLOCK_TSEM},
6820d956e8aSYuval Mintz }
6830d956e8aSYuval Mintz },
6840d956e8aSYuval Mintz
6850d956e8aSYuval Mintz {
6860d956e8aSYuval Mintz { /* After Invert 6 */
687b4149dc7SYuval Mintz {"UCM", ATTENTION_PAR_INT, NULL, BLOCK_UCM},
688b4149dc7SYuval Mintz {"USDM", ATTENTION_PAR_INT, NULL, BLOCK_USDM},
689b4149dc7SYuval Mintz {"USEM", ATTENTION_PAR_INT, NULL, BLOCK_USEM},
690b4149dc7SYuval Mintz {"XCM", ATTENTION_PAR_INT, NULL, BLOCK_XCM},
691b4149dc7SYuval Mintz {"XSDM", ATTENTION_PAR_INT, NULL, BLOCK_XSDM},
692b4149dc7SYuval Mintz {"XSEM", ATTENTION_PAR_INT, NULL, BLOCK_XSEM},
693b4149dc7SYuval Mintz {"YCM", ATTENTION_PAR_INT, NULL, BLOCK_YCM},
694b4149dc7SYuval Mintz {"YSDM", ATTENTION_PAR_INT, NULL, BLOCK_YSDM},
695b4149dc7SYuval Mintz {"YSEM", ATTENTION_PAR_INT, NULL, BLOCK_YSEM},
696b4149dc7SYuval Mintz {"XYLD", ATTENTION_PAR_INT, NULL, BLOCK_XYLD},
697b4149dc7SYuval Mintz {"TMLD", ATTENTION_PAR_INT, NULL, BLOCK_TMLD},
698b4149dc7SYuval Mintz {"MYLD", ATTENTION_PAR_INT, NULL, BLOCK_MULD},
699b4149dc7SYuval Mintz {"YULD", ATTENTION_PAR_INT, NULL, BLOCK_YULD},
700b4149dc7SYuval Mintz {"DORQ", ATTENTION_PAR_INT,
701b4149dc7SYuval Mintz qed_dorq_attn_cb, BLOCK_DORQ},
702b4149dc7SYuval Mintz {"DBG", ATTENTION_PAR_INT, NULL, BLOCK_DBG},
703b4149dc7SYuval Mintz {"IPC", ATTENTION_PAR_INT, NULL, BLOCK_IPC},
7040d956e8aSYuval Mintz }
7050d956e8aSYuval Mintz },
7060d956e8aSYuval Mintz
7070d956e8aSYuval Mintz {
7080d956e8aSYuval Mintz { /* After Invert 7 */
709b4149dc7SYuval Mintz {"CCFC", ATTENTION_PAR_INT, NULL, BLOCK_CCFC},
710b4149dc7SYuval Mintz {"CDU", ATTENTION_PAR_INT, NULL, BLOCK_CDU},
711b4149dc7SYuval Mintz {"DMAE", ATTENTION_PAR_INT, NULL, BLOCK_DMAE},
712b4149dc7SYuval Mintz {"IGU", ATTENTION_PAR_INT, NULL, BLOCK_IGU},
713b4149dc7SYuval Mintz {"ATC", ATTENTION_PAR_INT, NULL, MAX_BLOCK_ID},
714b4149dc7SYuval Mintz {"CAU", ATTENTION_PAR_INT, NULL, BLOCK_CAU},
715b4149dc7SYuval Mintz {"PTU", ATTENTION_PAR_INT, NULL, BLOCK_PTU},
716b4149dc7SYuval Mintz {"PRM", ATTENTION_PAR_INT, NULL, BLOCK_PRM},
717b4149dc7SYuval Mintz {"TCFC", ATTENTION_PAR_INT, NULL, BLOCK_TCFC},
718b4149dc7SYuval Mintz {"RDIF", ATTENTION_PAR_INT, NULL, BLOCK_RDIF},
719b4149dc7SYuval Mintz {"TDIF", ATTENTION_PAR_INT, NULL, BLOCK_TDIF},
720b4149dc7SYuval Mintz {"RSS", ATTENTION_PAR_INT, NULL, BLOCK_RSS},
721b4149dc7SYuval Mintz {"MISC", ATTENTION_PAR_INT, NULL, BLOCK_MISC},
722b4149dc7SYuval Mintz {"MISCS", ATTENTION_PAR_INT, NULL, BLOCK_MISCS},
723b4149dc7SYuval Mintz {"PCIE", ATTENTION_PAR, NULL, BLOCK_PCIE},
724b4149dc7SYuval Mintz {"Vaux PCI core", ATTENTION_SINGLE, NULL, BLOCK_PGLCS},
725b4149dc7SYuval Mintz {"PSWRQ", ATTENTION_PAR_INT, NULL, BLOCK_PSWRQ},
7260d956e8aSYuval Mintz }
7270d956e8aSYuval Mintz },
7280d956e8aSYuval Mintz
7290d956e8aSYuval Mintz {
7300d956e8aSYuval Mintz { /* After Invert 8 */
731b4149dc7SYuval Mintz {"PSWRQ (pci_clk)", ATTENTION_PAR_INT,
732b4149dc7SYuval Mintz NULL, BLOCK_PSWRQ2},
733b4149dc7SYuval Mintz {"PSWWR", ATTENTION_PAR_INT, NULL, BLOCK_PSWWR},
734b4149dc7SYuval Mintz {"PSWWR (pci_clk)", ATTENTION_PAR_INT,
735b4149dc7SYuval Mintz NULL, BLOCK_PSWWR2},
736b4149dc7SYuval Mintz {"PSWRD", ATTENTION_PAR_INT, NULL, BLOCK_PSWRD},
737b4149dc7SYuval Mintz {"PSWRD (pci_clk)", ATTENTION_PAR_INT,
738b4149dc7SYuval Mintz NULL, BLOCK_PSWRD2},
739b4149dc7SYuval Mintz {"PSWHST", ATTENTION_PAR_INT,
740b4149dc7SYuval Mintz qed_pswhst_attn_cb, BLOCK_PSWHST},
741b4149dc7SYuval Mintz {"PSWHST (pci_clk)", ATTENTION_PAR_INT,
742b4149dc7SYuval Mintz NULL, BLOCK_PSWHST2},
743b4149dc7SYuval Mintz {"GRC", ATTENTION_PAR_INT,
744b4149dc7SYuval Mintz qed_grc_attn_cb, BLOCK_GRC},
745b4149dc7SYuval Mintz {"CPMU", ATTENTION_PAR_INT, NULL, BLOCK_CPMU},
746b4149dc7SYuval Mintz {"NCSI", ATTENTION_PAR_INT, NULL, BLOCK_NCSI},
747b4149dc7SYuval Mintz {"MSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
748b4149dc7SYuval Mintz {"PSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
749b4149dc7SYuval Mintz {"TSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
750b4149dc7SYuval Mintz {"USEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
751b4149dc7SYuval Mintz {"XSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
752b4149dc7SYuval Mintz {"YSEM PRAM", ATTENTION_PAR, NULL, MAX_BLOCK_ID},
753b4149dc7SYuval Mintz {"pxp_misc_mps", ATTENTION_PAR, NULL, BLOCK_PGLCS},
754ff38577aSYuval Mintz {"PCIE glue/PXP Exp. ROM", ATTENTION_SINGLE,
755b4149dc7SYuval Mintz NULL, BLOCK_PGLCS},
756b4149dc7SYuval Mintz {"PERST_B assertion", ATTENTION_SINGLE,
757b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID},
758ff38577aSYuval Mintz {"PERST_B deassertion", ATTENTION_SINGLE,
759b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID},
760ff38577aSYuval Mintz {"Reserved %d", (2 << ATTENTION_LENGTH_SHIFT),
761b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID},
7620d956e8aSYuval Mintz }
7630d956e8aSYuval Mintz },
7640d956e8aSYuval Mintz
7650d956e8aSYuval Mintz {
7660d956e8aSYuval Mintz { /* After Invert 9 */
767b4149dc7SYuval Mintz {"MCP Latched memory", ATTENTION_PAR,
768b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID},
769ff38577aSYuval Mintz {"MCP Latched scratchpad cache", ATTENTION_SINGLE,
770b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID},
771b4149dc7SYuval Mintz {"MCP Latched ump_tx", ATTENTION_PAR,
772b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID},
773ff38577aSYuval Mintz {"MCP Latched scratchpad", ATTENTION_PAR,
774b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID},
775ff38577aSYuval Mintz {"Reserved %d", (28 << ATTENTION_LENGTH_SHIFT),
776b4149dc7SYuval Mintz NULL, MAX_BLOCK_ID},
7770d956e8aSYuval Mintz }
7780d956e8aSYuval Mintz },
7790d956e8aSYuval Mintz };
7800d956e8aSYuval Mintz
781ba36f718SMintz, Yuval static struct aeu_invert_reg_bit *
qed_int_aeu_translate(struct qed_hwfn * p_hwfn,struct aeu_invert_reg_bit * p_bit)782ba36f718SMintz, Yuval qed_int_aeu_translate(struct qed_hwfn *p_hwfn,
783ba36f718SMintz, Yuval struct aeu_invert_reg_bit *p_bit)
784ba36f718SMintz, Yuval {
785ba36f718SMintz, Yuval if (!QED_IS_BB(p_hwfn->cdev))
786ba36f718SMintz, Yuval return p_bit;
787ba36f718SMintz, Yuval
788ba36f718SMintz, Yuval if (!(p_bit->flags & ATTENTION_BB_DIFFERENT))
789ba36f718SMintz, Yuval return p_bit;
790ba36f718SMintz, Yuval
791ba36f718SMintz, Yuval return &aeu_descs_special[(p_bit->flags & ATTENTION_BB_MASK) >>
792ba36f718SMintz, Yuval ATTENTION_BB_SHIFT];
793ba36f718SMintz, Yuval }
794ba36f718SMintz, Yuval
qed_int_is_parity_flag(struct qed_hwfn * p_hwfn,struct aeu_invert_reg_bit * p_bit)795ba36f718SMintz, Yuval static bool qed_int_is_parity_flag(struct qed_hwfn *p_hwfn,
796ba36f718SMintz, Yuval struct aeu_invert_reg_bit *p_bit)
797ba36f718SMintz, Yuval {
798ba36f718SMintz, Yuval return !!(qed_int_aeu_translate(p_hwfn, p_bit)->flags &
799ba36f718SMintz, Yuval ATTENTION_PARITY);
800ba36f718SMintz, Yuval }
801ba36f718SMintz, Yuval
802cc875c2eSYuval Mintz #define ATTN_STATE_BITS (0xfff)
803cc875c2eSYuval Mintz #define ATTN_BITS_MASKABLE (0x3ff)
804cc875c2eSYuval Mintz struct qed_sb_attn_info {
805cc875c2eSYuval Mintz /* Virtual & Physical address of the SB */
806cc875c2eSYuval Mintz struct atten_status_block *sb_attn;
807cc875c2eSYuval Mintz dma_addr_t sb_phys;
808cc875c2eSYuval Mintz
809cc875c2eSYuval Mintz /* Last seen running index */
810cc875c2eSYuval Mintz u16 index;
811cc875c2eSYuval Mintz
8120d956e8aSYuval Mintz /* A mask of the AEU bits resulting in a parity error */
8130d956e8aSYuval Mintz u32 parity_mask[NUM_ATTN_REGS];
8140d956e8aSYuval Mintz
8150d956e8aSYuval Mintz /* A pointer to the attention description structure */
8160d956e8aSYuval Mintz struct aeu_invert_reg *p_aeu_desc;
8170d956e8aSYuval Mintz
818cc875c2eSYuval Mintz /* Previously asserted attentions, which are still unasserted */
819cc875c2eSYuval Mintz u16 known_attn;
820cc875c2eSYuval Mintz
821cc875c2eSYuval Mintz /* Cleanup address for the link's general hw attention */
822cc875c2eSYuval Mintz u32 mfw_attn_addr;
823cc875c2eSYuval Mintz };
824cc875c2eSYuval Mintz
qed_attn_update_idx(struct qed_hwfn * p_hwfn,struct qed_sb_attn_info * p_sb_desc)825cc875c2eSYuval Mintz static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn,
826cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb_desc)
827cc875c2eSYuval Mintz {
8281a635e48SYuval Mintz u16 rc = 0, index;
829cc875c2eSYuval Mintz
830cc875c2eSYuval Mintz index = le16_to_cpu(p_sb_desc->sb_attn->sb_index);
831cc875c2eSYuval Mintz if (p_sb_desc->index != index) {
832cc875c2eSYuval Mintz p_sb_desc->index = index;
833cc875c2eSYuval Mintz rc = QED_SB_ATT_IDX;
834cc875c2eSYuval Mintz }
835cc875c2eSYuval Mintz
836cc875c2eSYuval Mintz return rc;
837cc875c2eSYuval Mintz }
838cc875c2eSYuval Mintz
839cc875c2eSYuval Mintz /**
84071e11a3fSAlexander Lobakin * qed_int_assertion() - Handle asserted attention bits.
841cc875c2eSYuval Mintz *
84271e11a3fSAlexander Lobakin * @p_hwfn: HW device data.
84371e11a3fSAlexander Lobakin * @asserted_bits: Newly asserted bits.
84471e11a3fSAlexander Lobakin *
84571e11a3fSAlexander Lobakin * Return: Zero value.
846cc875c2eSYuval Mintz */
qed_int_assertion(struct qed_hwfn * p_hwfn,u16 asserted_bits)8471a635e48SYuval Mintz static int qed_int_assertion(struct qed_hwfn *p_hwfn, u16 asserted_bits)
848cc875c2eSYuval Mintz {
849cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
850cc875c2eSYuval Mintz u32 igu_mask;
851cc875c2eSYuval Mintz
852cc875c2eSYuval Mintz /* Mask the source of the attention in the IGU */
8531a635e48SYuval Mintz igu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE);
854cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "IGU mask: 0x%08x --> 0x%08x\n",
855cc875c2eSYuval Mintz igu_mask, igu_mask & ~(asserted_bits & ATTN_BITS_MASKABLE));
856cc875c2eSYuval Mintz igu_mask &= ~(asserted_bits & ATTN_BITS_MASKABLE);
857cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, igu_mask);
858cc875c2eSYuval Mintz
859cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
860cc875c2eSYuval Mintz "inner known ATTN state: 0x%04x --> 0x%04x\n",
861cc875c2eSYuval Mintz sb_attn_sw->known_attn,
862cc875c2eSYuval Mintz sb_attn_sw->known_attn | asserted_bits);
863cc875c2eSYuval Mintz sb_attn_sw->known_attn |= asserted_bits;
864cc875c2eSYuval Mintz
865cc875c2eSYuval Mintz /* Handle MCP events */
866cc875c2eSYuval Mintz if (asserted_bits & 0x100) {
867cc875c2eSYuval Mintz qed_mcp_handle_events(p_hwfn, p_hwfn->p_dpc_ptt);
868cc875c2eSYuval Mintz /* Clean the MCP attention */
869cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt,
870cc875c2eSYuval Mintz sb_attn_sw->mfw_attn_addr, 0);
871cc875c2eSYuval Mintz }
872cc875c2eSYuval Mintz
873cc875c2eSYuval Mintz DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview +
874cc875c2eSYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD +
875cc875c2eSYuval Mintz ((IGU_CMD_ATTN_BIT_SET_UPPER -
876cc875c2eSYuval Mintz IGU_CMD_INT_ACK_BASE) << 3),
877cc875c2eSYuval Mintz (u32)asserted_bits);
878cc875c2eSYuval Mintz
879cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "set cmd IGU: 0x%04x\n",
880cc875c2eSYuval Mintz asserted_bits);
881cc875c2eSYuval Mintz
882cc875c2eSYuval Mintz return 0;
883cc875c2eSYuval Mintz }
884cc875c2eSYuval Mintz
qed_int_attn_print(struct qed_hwfn * p_hwfn,enum block_id id,enum dbg_attn_type type,bool b_clear)8850ebbd1c8SMintz, Yuval static void qed_int_attn_print(struct qed_hwfn *p_hwfn,
8860ebbd1c8SMintz, Yuval enum block_id id,
8870ebbd1c8SMintz, Yuval enum dbg_attn_type type, bool b_clear)
888ff38577aSYuval Mintz {
8890ebbd1c8SMintz, Yuval struct dbg_attn_block_result attn_results;
8900ebbd1c8SMintz, Yuval enum dbg_status status;
891ff38577aSYuval Mintz
8920ebbd1c8SMintz, Yuval memset(&attn_results, 0, sizeof(attn_results));
893ff38577aSYuval Mintz
8940ebbd1c8SMintz, Yuval status = qed_dbg_read_attn(p_hwfn, p_hwfn->p_dpc_ptt, id, type,
8950ebbd1c8SMintz, Yuval b_clear, &attn_results);
8960ebbd1c8SMintz, Yuval if (status != DBG_STATUS_OK)
897ff38577aSYuval Mintz DP_NOTICE(p_hwfn,
8980ebbd1c8SMintz, Yuval "Failed to parse attention information [status: %s]\n",
8990ebbd1c8SMintz, Yuval qed_dbg_get_status_str(status));
9000ebbd1c8SMintz, Yuval else
9010ebbd1c8SMintz, Yuval qed_dbg_parse_attn(p_hwfn, &attn_results);
902ff38577aSYuval Mintz }
903ff38577aSYuval Mintz
904cc875c2eSYuval Mintz /**
90571e11a3fSAlexander Lobakin * qed_int_deassertion_aeu_bit() - Handles the effects of a single
90671e11a3fSAlexander Lobakin * cause of the attention.
9070d956e8aSYuval Mintz *
90871e11a3fSAlexander Lobakin * @p_hwfn: HW device data.
90971e11a3fSAlexander Lobakin * @p_aeu: Descriptor of an AEU bit which caused the attention.
91071e11a3fSAlexander Lobakin * @aeu_en_reg: Register offset of the AEU enable reg. which configured
9110d956e8aSYuval Mintz * this bit to this group.
91271e11a3fSAlexander Lobakin * @p_bit_name: AEU bit description for logging purposes.
91371e11a3fSAlexander Lobakin * @bitmask: Index of this bit in the aeu_en_reg.
9140d956e8aSYuval Mintz *
91571e11a3fSAlexander Lobakin * Return: Zero on success, negative errno otherwise.
9160d956e8aSYuval Mintz */
9170d956e8aSYuval Mintz static int
qed_int_deassertion_aeu_bit(struct qed_hwfn * p_hwfn,struct aeu_invert_reg_bit * p_aeu,u32 aeu_en_reg,const char * p_bit_name,u32 bitmask)9180d956e8aSYuval Mintz qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn,
9190d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_aeu,
9200d956e8aSYuval Mintz u32 aeu_en_reg,
9216010179dSMintz, Yuval const char *p_bit_name, u32 bitmask)
9220d956e8aSYuval Mintz {
9230ebbd1c8SMintz, Yuval bool b_fatal = false;
9240d956e8aSYuval Mintz int rc = -EINVAL;
925b4149dc7SYuval Mintz u32 val;
9260d956e8aSYuval Mintz
9270d956e8aSYuval Mintz DP_INFO(p_hwfn, "Deasserted attention `%s'[%08x]\n",
9286010179dSMintz, Yuval p_bit_name, bitmask);
9290d956e8aSYuval Mintz
930b4149dc7SYuval Mintz /* Call callback before clearing the interrupt status */
931b4149dc7SYuval Mintz if (p_aeu->cb) {
932b4149dc7SYuval Mintz DP_INFO(p_hwfn, "`%s (attention)': Calling Callback function\n",
9336010179dSMintz, Yuval p_bit_name);
934b4149dc7SYuval Mintz rc = p_aeu->cb(p_hwfn);
935b4149dc7SYuval Mintz }
936b4149dc7SYuval Mintz
9370ebbd1c8SMintz, Yuval if (rc)
9380ebbd1c8SMintz, Yuval b_fatal = true;
939ff38577aSYuval Mintz
9400ebbd1c8SMintz, Yuval /* Print HW block interrupt registers */
9410ebbd1c8SMintz, Yuval if (p_aeu->block_index != MAX_BLOCK_ID)
9420ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, p_aeu->block_index,
9430ebbd1c8SMintz, Yuval ATTN_TYPE_INTERRUPT, !b_fatal);
944ff38577aSYuval Mintz
9452ec276d5SIgor Russkikh /* Reach assertion if attention is fatal */
9462ec276d5SIgor Russkikh if (b_fatal)
9472ec276d5SIgor Russkikh qed_hw_err_notify(p_hwfn, p_hwfn->p_dpc_ptt, QED_HW_ERR_HW_ATTN,
9482ec276d5SIgor Russkikh "`%s': Fatal attention\n",
9492ec276d5SIgor Russkikh p_bit_name);
9502ec276d5SIgor Russkikh else /* If the attention is benign, no need to prevent it */
951b4149dc7SYuval Mintz goto out;
952b4149dc7SYuval Mintz
9530d956e8aSYuval Mintz /* Prevent this Attention from being asserted in the future */
9540d956e8aSYuval Mintz val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
955b4149dc7SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, (val & ~bitmask));
9560d956e8aSYuval Mintz DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n",
9576010179dSMintz, Yuval p_bit_name);
9580d956e8aSYuval Mintz
959755f9053SAlok Prasad /* Re-enable FW aassertion (Gen 32) interrupts */
960755f9053SAlok Prasad val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
961755f9053SAlok Prasad MISC_REG_AEU_ENABLE4_IGU_OUT_0);
962755f9053SAlok Prasad val |= MISC_REG_AEU_ENABLE4_IGU_OUT_0_GENERAL_ATTN32;
963755f9053SAlok Prasad qed_wr(p_hwfn, p_hwfn->p_dpc_ptt,
964755f9053SAlok Prasad MISC_REG_AEU_ENABLE4_IGU_OUT_0, val);
965755f9053SAlok Prasad
966b4149dc7SYuval Mintz out:
9670d956e8aSYuval Mintz return rc;
9680d956e8aSYuval Mintz }
9690d956e8aSYuval Mintz
970ff38577aSYuval Mintz /**
97171e11a3fSAlexander Lobakin * qed_int_deassertion_parity() - Handle a single parity AEU source.
972ff38577aSYuval Mintz *
97371e11a3fSAlexander Lobakin * @p_hwfn: HW device data.
97471e11a3fSAlexander Lobakin * @p_aeu: Descriptor of an AEU bit which caused the parity.
97571e11a3fSAlexander Lobakin * @aeu_en_reg: Address of the AEU enable register.
97671e11a3fSAlexander Lobakin * @bit_index: Index (0-31) of an AEU bit.
977ff38577aSYuval Mintz */
qed_int_deassertion_parity(struct qed_hwfn * p_hwfn,struct aeu_invert_reg_bit * p_aeu,u32 aeu_en_reg,u8 bit_index)978ff38577aSYuval Mintz static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn,
979ff38577aSYuval Mintz struct aeu_invert_reg_bit *p_aeu,
9809790c35eSMintz, Yuval u32 aeu_en_reg, u8 bit_index)
981ff38577aSYuval Mintz {
9829790c35eSMintz, Yuval u32 block_id = p_aeu->block_index, mask, val;
983ff38577aSYuval Mintz
9849790c35eSMintz, Yuval DP_NOTICE(p_hwfn->cdev,
9859790c35eSMintz, Yuval "%s parity attention is set [address 0x%08x, bit %d]\n",
9869790c35eSMintz, Yuval p_aeu->bit_name, aeu_en_reg, bit_index);
987ff38577aSYuval Mintz
988ff38577aSYuval Mintz if (block_id != MAX_BLOCK_ID) {
9890ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, block_id, ATTN_TYPE_PARITY, false);
990ff38577aSYuval Mintz
991ff38577aSYuval Mintz /* In BB, there's a single parity bit for several blocks */
992ff38577aSYuval Mintz if (block_id == BLOCK_BTB) {
9930ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, BLOCK_OPTE,
9940ebbd1c8SMintz, Yuval ATTN_TYPE_PARITY, false);
9950ebbd1c8SMintz, Yuval qed_int_attn_print(p_hwfn, BLOCK_MCP,
9960ebbd1c8SMintz, Yuval ATTN_TYPE_PARITY, false);
997ff38577aSYuval Mintz }
998ff38577aSYuval Mintz }
9999790c35eSMintz, Yuval
10009790c35eSMintz, Yuval /* Prevent this parity error from being re-asserted */
10019790c35eSMintz, Yuval mask = ~BIT(bit_index);
10029790c35eSMintz, Yuval val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg);
10039790c35eSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en_reg, val & mask);
10049790c35eSMintz, Yuval DP_INFO(p_hwfn, "`%s' - Disabled future parity errors\n",
10059790c35eSMintz, Yuval p_aeu->bit_name);
1006ff38577aSYuval Mintz }
1007ff38577aSYuval Mintz
10080d956e8aSYuval Mintz /**
100971e11a3fSAlexander Lobakin * qed_int_deassertion() - Handle deassertion of previously asserted
101071e11a3fSAlexander Lobakin * attentions.
1011cc875c2eSYuval Mintz *
101271e11a3fSAlexander Lobakin * @p_hwfn: HW device data.
101371e11a3fSAlexander Lobakin * @deasserted_bits: newly deasserted bits.
1014cc875c2eSYuval Mintz *
101571e11a3fSAlexander Lobakin * Return: Zero value.
1016cc875c2eSYuval Mintz */
qed_int_deassertion(struct qed_hwfn * p_hwfn,u16 deasserted_bits)1017cc875c2eSYuval Mintz static int qed_int_deassertion(struct qed_hwfn *p_hwfn,
1018cc875c2eSYuval Mintz u16 deasserted_bits)
1019cc875c2eSYuval Mintz {
1020cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn_sw = p_hwfn->p_sb_attn;
10219790c35eSMintz, Yuval u32 aeu_inv_arr[NUM_ATTN_REGS], aeu_mask, aeu_en, en;
10220d956e8aSYuval Mintz u8 i, j, k, bit_idx;
10230d956e8aSYuval Mintz int rc = 0;
1024cc875c2eSYuval Mintz
10250d956e8aSYuval Mintz /* Read the attention registers in the AEU */
10260d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) {
10270d956e8aSYuval Mintz aeu_inv_arr[i] = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
10280d956e8aSYuval Mintz MISC_REG_AEU_AFTER_INVERT_1_IGU +
10290d956e8aSYuval Mintz i * 0x4);
10300d956e8aSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
10310d956e8aSYuval Mintz "Deasserted bits [%d]: %08x\n",
10320d956e8aSYuval Mintz i, aeu_inv_arr[i]);
10330d956e8aSYuval Mintz }
10340d956e8aSYuval Mintz
10350d956e8aSYuval Mintz /* Find parity attentions first */
10360d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) {
10370d956e8aSYuval Mintz struct aeu_invert_reg *p_aeu = &sb_attn_sw->p_aeu_desc[i];
10380d956e8aSYuval Mintz u32 parities;
10390d956e8aSYuval Mintz
10409790c35eSMintz, Yuval aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 + i * sizeof(u32);
10419790c35eSMintz, Yuval en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
10429790c35eSMintz, Yuval
10430d956e8aSYuval Mintz /* Skip register in which no parity bit is currently set */
10440d956e8aSYuval Mintz parities = sb_attn_sw->parity_mask[i] & aeu_inv_arr[i] & en;
10450d956e8aSYuval Mintz if (!parities)
10460d956e8aSYuval Mintz continue;
10470d956e8aSYuval Mintz
10480435a4d0Szhangyue for (j = 0, bit_idx = 0; bit_idx < 32 && j < 32; j++) {
10490d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_bit = &p_aeu->bits[j];
10500d956e8aSYuval Mintz
1051ba36f718SMintz, Yuval if (qed_int_is_parity_flag(p_hwfn, p_bit) &&
10521a635e48SYuval Mintz !!(parities & BIT(bit_idx)))
1053ff38577aSYuval Mintz qed_int_deassertion_parity(p_hwfn, p_bit,
10549790c35eSMintz, Yuval aeu_en, bit_idx);
10550d956e8aSYuval Mintz
10560d956e8aSYuval Mintz bit_idx += ATTENTION_LENGTH(p_bit->flags);
10570d956e8aSYuval Mintz }
10580d956e8aSYuval Mintz }
10590d956e8aSYuval Mintz
10600d956e8aSYuval Mintz /* Find non-parity cause for attention and act */
10610d956e8aSYuval Mintz for (k = 0; k < MAX_ATTN_GRPS; k++) {
10620d956e8aSYuval Mintz struct aeu_invert_reg_bit *p_aeu;
10630d956e8aSYuval Mintz
10640d956e8aSYuval Mintz /* Handle only groups whose attention is currently deasserted */
10650d956e8aSYuval Mintz if (!(deasserted_bits & (1 << k)))
10660d956e8aSYuval Mintz continue;
10670d956e8aSYuval Mintz
10680d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) {
10699790c35eSMintz, Yuval u32 bits;
10709790c35eSMintz, Yuval
10719790c35eSMintz, Yuval aeu_en = MISC_REG_AEU_ENABLE1_IGU_OUT_0 +
10720d956e8aSYuval Mintz i * sizeof(u32) +
10730d956e8aSYuval Mintz k * sizeof(u32) * NUM_ATTN_REGS;
10740d956e8aSYuval Mintz
10750d956e8aSYuval Mintz en = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, aeu_en);
10760d956e8aSYuval Mintz bits = aeu_inv_arr[i] & en;
10770d956e8aSYuval Mintz
10780d956e8aSYuval Mintz /* Skip if no bit from this group is currently set */
10790d956e8aSYuval Mintz if (!bits)
10800d956e8aSYuval Mintz continue;
10810d956e8aSYuval Mintz
10820d956e8aSYuval Mintz /* Find all set bits from current register which belong
10830d956e8aSYuval Mintz * to current group, making them responsible for the
10840d956e8aSYuval Mintz * previous assertion.
10850d956e8aSYuval Mintz */
10860435a4d0Szhangyue for (j = 0, bit_idx = 0; bit_idx < 32 && j < 32; j++) {
10876010179dSMintz, Yuval long unsigned int bitmask;
10880d956e8aSYuval Mintz u8 bit, bit_len;
10890d956e8aSYuval Mintz
10900d956e8aSYuval Mintz p_aeu = &sb_attn_sw->p_aeu_desc[i].bits[j];
1091ba36f718SMintz, Yuval p_aeu = qed_int_aeu_translate(p_hwfn, p_aeu);
10920d956e8aSYuval Mintz
10930d956e8aSYuval Mintz bit = bit_idx;
10940d956e8aSYuval Mintz bit_len = ATTENTION_LENGTH(p_aeu->flags);
1095ba36f718SMintz, Yuval if (qed_int_is_parity_flag(p_hwfn, p_aeu)) {
10960d956e8aSYuval Mintz /* Skip Parity */
10970d956e8aSYuval Mintz bit++;
10980d956e8aSYuval Mintz bit_len--;
10990d956e8aSYuval Mintz }
11000d956e8aSYuval Mintz
11010d956e8aSYuval Mintz bitmask = bits & (((1 << bit_len) - 1) << bit);
11026010179dSMintz, Yuval bitmask >>= bit;
11036010179dSMintz, Yuval
11040d956e8aSYuval Mintz if (bitmask) {
11056010179dSMintz, Yuval u32 flags = p_aeu->flags;
11066010179dSMintz, Yuval char bit_name[30];
11076010179dSMintz, Yuval u8 num;
11086010179dSMintz, Yuval
11096010179dSMintz, Yuval num = (u8)find_first_bit(&bitmask,
11106010179dSMintz, Yuval bit_len);
11116010179dSMintz, Yuval
11126010179dSMintz, Yuval /* Some bits represent more than a
111304740c53SJilin Yuan * single interrupt. Correctly print
11146010179dSMintz, Yuval * their name.
11156010179dSMintz, Yuval */
11166010179dSMintz, Yuval if (ATTENTION_LENGTH(flags) > 2 ||
11176010179dSMintz, Yuval ((flags & ATTENTION_PAR_INT) &&
11186010179dSMintz, Yuval ATTENTION_LENGTH(flags) > 1))
11196010179dSMintz, Yuval snprintf(bit_name, 30,
11206010179dSMintz, Yuval p_aeu->bit_name, num);
11216010179dSMintz, Yuval else
1122*f029c781SWolfram Sang strscpy(bit_name,
11236010179dSMintz, Yuval p_aeu->bit_name, 30);
11246010179dSMintz, Yuval
11256010179dSMintz, Yuval /* We now need to pass bitmask in its
11266010179dSMintz, Yuval * correct position.
11276010179dSMintz, Yuval */
11286010179dSMintz, Yuval bitmask <<= bit;
11296010179dSMintz, Yuval
11300d956e8aSYuval Mintz /* Handle source of the attention */
11310d956e8aSYuval Mintz qed_int_deassertion_aeu_bit(p_hwfn,
11320d956e8aSYuval Mintz p_aeu,
11330d956e8aSYuval Mintz aeu_en,
11346010179dSMintz, Yuval bit_name,
11350d956e8aSYuval Mintz bitmask);
11360d956e8aSYuval Mintz }
11370d956e8aSYuval Mintz
11380d956e8aSYuval Mintz bit_idx += ATTENTION_LENGTH(p_aeu->flags);
11390d956e8aSYuval Mintz }
11400d956e8aSYuval Mintz }
11410d956e8aSYuval Mintz }
1142cc875c2eSYuval Mintz
1143d4476b8aSDenis Bolotin /* Handle missed DORQ attention */
1144d4476b8aSDenis Bolotin qed_dorq_attn_handler(p_hwfn);
1145d4476b8aSDenis Bolotin
1146cc875c2eSYuval Mintz /* Clear IGU indication for the deasserted bits */
1147cc875c2eSYuval Mintz DIRECT_REG_WR((u8 __iomem *)p_hwfn->regview +
1148cc875c2eSYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD +
1149cc875c2eSYuval Mintz ((IGU_CMD_ATTN_BIT_CLR_UPPER -
1150cc875c2eSYuval Mintz IGU_CMD_INT_ACK_BASE) << 3),
1151cc875c2eSYuval Mintz ~((u32)deasserted_bits));
1152cc875c2eSYuval Mintz
1153cc875c2eSYuval Mintz /* Unmask deasserted attentions in IGU */
11541a635e48SYuval Mintz aeu_mask = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE);
1155cc875c2eSYuval Mintz aeu_mask |= (deasserted_bits & ATTN_BITS_MASKABLE);
1156cc875c2eSYuval Mintz qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, IGU_REG_ATTENTION_ENABLE, aeu_mask);
1157cc875c2eSYuval Mintz
1158cc875c2eSYuval Mintz /* Clear deassertion from inner state */
1159cc875c2eSYuval Mintz sb_attn_sw->known_attn &= ~deasserted_bits;
1160cc875c2eSYuval Mintz
11610d956e8aSYuval Mintz return rc;
1162cc875c2eSYuval Mintz }
1163cc875c2eSYuval Mintz
qed_int_attentions(struct qed_hwfn * p_hwfn)1164cc875c2eSYuval Mintz static int qed_int_attentions(struct qed_hwfn *p_hwfn)
1165cc875c2eSYuval Mintz {
1166cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb_attn_sw = p_hwfn->p_sb_attn;
1167cc875c2eSYuval Mintz struct atten_status_block *p_sb_attn = p_sb_attn_sw->sb_attn;
1168cc875c2eSYuval Mintz u32 attn_bits = 0, attn_acks = 0;
1169cc875c2eSYuval Mintz u16 asserted_bits, deasserted_bits;
1170cc875c2eSYuval Mintz __le16 index;
1171cc875c2eSYuval Mintz int rc = 0;
1172cc875c2eSYuval Mintz
1173cc875c2eSYuval Mintz /* Read current attention bits/acks - safeguard against attentions
1174cc875c2eSYuval Mintz * by guaranting work on a synchronized timeframe
1175cc875c2eSYuval Mintz */
1176cc875c2eSYuval Mintz do {
1177cc875c2eSYuval Mintz index = p_sb_attn->sb_index;
1178ed4eac20SDenis Bolotin /* finish reading index before the loop condition */
1179ed4eac20SDenis Bolotin dma_rmb();
1180cc875c2eSYuval Mintz attn_bits = le32_to_cpu(p_sb_attn->atten_bits);
1181cc875c2eSYuval Mintz attn_acks = le32_to_cpu(p_sb_attn->atten_ack);
1182cc875c2eSYuval Mintz } while (index != p_sb_attn->sb_index);
1183cc875c2eSYuval Mintz p_sb_attn->sb_index = index;
1184cc875c2eSYuval Mintz
1185cc875c2eSYuval Mintz /* Attention / Deassertion are meaningful (and in correct state)
1186cc875c2eSYuval Mintz * only when they differ and consistent with known state - deassertion
1187cc875c2eSYuval Mintz * when previous attention & current ack, and assertion when current
1188cc875c2eSYuval Mintz * attention with no previous attention
1189cc875c2eSYuval Mintz */
1190cc875c2eSYuval Mintz asserted_bits = (attn_bits & ~attn_acks & ATTN_STATE_BITS) &
1191cc875c2eSYuval Mintz ~p_sb_attn_sw->known_attn;
1192cc875c2eSYuval Mintz deasserted_bits = (~attn_bits & attn_acks & ATTN_STATE_BITS) &
1193cc875c2eSYuval Mintz p_sb_attn_sw->known_attn;
1194cc875c2eSYuval Mintz
1195cc875c2eSYuval Mintz if ((asserted_bits & ~0x100) || (deasserted_bits & ~0x100)) {
1196cc875c2eSYuval Mintz DP_INFO(p_hwfn,
1197cc875c2eSYuval Mintz "Attention: Index: 0x%04x, Bits: 0x%08x, Acks: 0x%08x, asserted: 0x%04x, De-asserted 0x%04x [Prev. known: 0x%04x]\n",
1198cc875c2eSYuval Mintz index, attn_bits, attn_acks, asserted_bits,
1199cc875c2eSYuval Mintz deasserted_bits, p_sb_attn_sw->known_attn);
1200cc875c2eSYuval Mintz } else if (asserted_bits == 0x100) {
12011d61e218SLaurence Oberman DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
12021d61e218SLaurence Oberman "MFW indication via attention\n");
1203cc875c2eSYuval Mintz } else {
1204cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1205cc875c2eSYuval Mintz "MFW indication [deassertion]\n");
1206cc875c2eSYuval Mintz }
1207cc875c2eSYuval Mintz
1208cc875c2eSYuval Mintz if (asserted_bits) {
1209cc875c2eSYuval Mintz rc = qed_int_assertion(p_hwfn, asserted_bits);
1210cc875c2eSYuval Mintz if (rc)
1211cc875c2eSYuval Mintz return rc;
1212cc875c2eSYuval Mintz }
1213cc875c2eSYuval Mintz
12141a635e48SYuval Mintz if (deasserted_bits)
1215cc875c2eSYuval Mintz rc = qed_int_deassertion(p_hwfn, deasserted_bits);
1216cc875c2eSYuval Mintz
1217cc875c2eSYuval Mintz return rc;
1218cc875c2eSYuval Mintz }
1219cc875c2eSYuval Mintz
qed_sb_ack_attn(struct qed_hwfn * p_hwfn,void __iomem * igu_addr,u32 ack_cons)1220cc875c2eSYuval Mintz static void qed_sb_ack_attn(struct qed_hwfn *p_hwfn,
12211a635e48SYuval Mintz void __iomem *igu_addr, u32 ack_cons)
1222cc875c2eSYuval Mintz {
12235ab90341SAlexander Lobakin u32 igu_ack;
1224cc875c2eSYuval Mintz
12255ab90341SAlexander Lobakin igu_ack = ((ack_cons << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1226cc875c2eSYuval Mintz (1 << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1227cc875c2eSYuval Mintz (IGU_INT_NOP << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1228cc875c2eSYuval Mintz (IGU_SEG_ACCESS_ATTN <<
1229cc875c2eSYuval Mintz IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1230cc875c2eSYuval Mintz
12315ab90341SAlexander Lobakin DIRECT_REG_WR(igu_addr, igu_ack);
1232cc875c2eSYuval Mintz
1233cc875c2eSYuval Mintz /* Both segments (interrupts & acks) are written to same place address;
1234cc875c2eSYuval Mintz * Need to guarantee all commands will be received (in-order) by HW.
1235cc875c2eSYuval Mintz */
1236cc875c2eSYuval Mintz barrier();
1237cc875c2eSYuval Mintz }
1238cc875c2eSYuval Mintz
qed_int_sp_dpc(struct tasklet_struct * t)1239b5f0a3bfSAllen Pais void qed_int_sp_dpc(struct tasklet_struct *t)
1240fe56b9e6SYuval Mintz {
1241b5f0a3bfSAllen Pais struct qed_hwfn *p_hwfn = from_tasklet(p_hwfn, t, sp_dpc);
1242fe56b9e6SYuval Mintz struct qed_pi_info *pi_info = NULL;
1243cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_attn;
1244fe56b9e6SYuval Mintz struct qed_sb_info *sb_info;
1245fe56b9e6SYuval Mintz int arr_size;
1246fe56b9e6SYuval Mintz u16 rc = 0;
1247fe56b9e6SYuval Mintz
1248fe56b9e6SYuval Mintz if (!p_hwfn->p_sp_sb) {
1249fe56b9e6SYuval Mintz DP_ERR(p_hwfn->cdev, "DPC called - no p_sp_sb\n");
1250fe56b9e6SYuval Mintz return;
1251fe56b9e6SYuval Mintz }
1252fe56b9e6SYuval Mintz
1253fe56b9e6SYuval Mintz sb_info = &p_hwfn->p_sp_sb->sb_info;
1254fe56b9e6SYuval Mintz arr_size = ARRAY_SIZE(p_hwfn->p_sp_sb->pi_info_arr);
1255fe56b9e6SYuval Mintz if (!sb_info) {
1256fe56b9e6SYuval Mintz DP_ERR(p_hwfn->cdev,
1257fe56b9e6SYuval Mintz "Status block is NULL - cannot ack interrupts\n");
1258fe56b9e6SYuval Mintz return;
1259fe56b9e6SYuval Mintz }
1260fe56b9e6SYuval Mintz
1261cc875c2eSYuval Mintz if (!p_hwfn->p_sb_attn) {
1262cc875c2eSYuval Mintz DP_ERR(p_hwfn->cdev, "DPC called - no p_sb_attn");
1263cc875c2eSYuval Mintz return;
1264cc875c2eSYuval Mintz }
1265cc875c2eSYuval Mintz sb_attn = p_hwfn->p_sb_attn;
1266cc875c2eSYuval Mintz
1267fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR, "DPC Called! (hwfn %p %d)\n",
1268fe56b9e6SYuval Mintz p_hwfn, p_hwfn->my_id);
1269fe56b9e6SYuval Mintz
1270fe56b9e6SYuval Mintz /* Disable ack for def status block. Required both for msix +
1271fe56b9e6SYuval Mintz * inta in non-mask mode, in inta does no harm.
1272fe56b9e6SYuval Mintz */
1273fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_DISABLE, 0);
1274fe56b9e6SYuval Mintz
1275fe56b9e6SYuval Mintz /* Gather Interrupts/Attentions information */
1276fe56b9e6SYuval Mintz if (!sb_info->sb_virt) {
12771a635e48SYuval Mintz DP_ERR(p_hwfn->cdev,
1278fe56b9e6SYuval Mintz "Interrupt Status block is NULL - cannot check for new interrupts!\n");
1279fe56b9e6SYuval Mintz } else {
1280fe56b9e6SYuval Mintz u32 tmp_index = sb_info->sb_ack;
1281fe56b9e6SYuval Mintz
1282fe56b9e6SYuval Mintz rc = qed_sb_update_sb_idx(sb_info);
1283fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR,
1284fe56b9e6SYuval Mintz "Interrupt indices: 0x%08x --> 0x%08x\n",
1285fe56b9e6SYuval Mintz tmp_index, sb_info->sb_ack);
1286fe56b9e6SYuval Mintz }
1287fe56b9e6SYuval Mintz
1288cc875c2eSYuval Mintz if (!sb_attn || !sb_attn->sb_attn) {
12891a635e48SYuval Mintz DP_ERR(p_hwfn->cdev,
1290cc875c2eSYuval Mintz "Attentions Status block is NULL - cannot check for new attentions!\n");
1291cc875c2eSYuval Mintz } else {
1292cc875c2eSYuval Mintz u16 tmp_index = sb_attn->index;
1293cc875c2eSYuval Mintz
1294cc875c2eSYuval Mintz rc |= qed_attn_update_idx(p_hwfn, sb_attn);
1295cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn->cdev, NETIF_MSG_INTR,
1296cc875c2eSYuval Mintz "Attention indices: 0x%08x --> 0x%08x\n",
1297cc875c2eSYuval Mintz tmp_index, sb_attn->index);
1298cc875c2eSYuval Mintz }
1299cc875c2eSYuval Mintz
1300fe56b9e6SYuval Mintz /* Check if we expect interrupts at this time. if not just ack them */
1301fe56b9e6SYuval Mintz if (!(rc & QED_SB_EVENT_MASK)) {
1302fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1303fe56b9e6SYuval Mintz return;
1304fe56b9e6SYuval Mintz }
1305fe56b9e6SYuval Mintz
1306fe56b9e6SYuval Mintz /* Check the validity of the DPC ptt. If not ack interrupts and fail */
1307fe56b9e6SYuval Mintz if (!p_hwfn->p_dpc_ptt) {
1308fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn->cdev, "Failed to allocate PTT\n");
1309fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1310fe56b9e6SYuval Mintz return;
1311fe56b9e6SYuval Mintz }
1312fe56b9e6SYuval Mintz
1313cc875c2eSYuval Mintz if (rc & QED_SB_ATT_IDX)
1314cc875c2eSYuval Mintz qed_int_attentions(p_hwfn);
1315cc875c2eSYuval Mintz
1316fe56b9e6SYuval Mintz if (rc & QED_SB_IDX) {
1317fe56b9e6SYuval Mintz int pi;
1318fe56b9e6SYuval Mintz
1319fe56b9e6SYuval Mintz /* Look for a free index */
1320fe56b9e6SYuval Mintz for (pi = 0; pi < arr_size; pi++) {
1321fe56b9e6SYuval Mintz pi_info = &p_hwfn->p_sp_sb->pi_info_arr[pi];
1322fe56b9e6SYuval Mintz if (pi_info->comp_cb)
1323fe56b9e6SYuval Mintz pi_info->comp_cb(p_hwfn, pi_info->cookie);
1324fe56b9e6SYuval Mintz }
1325fe56b9e6SYuval Mintz }
1326fe56b9e6SYuval Mintz
1327cc875c2eSYuval Mintz if (sb_attn && (rc & QED_SB_ATT_IDX))
1328cc875c2eSYuval Mintz /* This should be done before the interrupts are enabled,
1329cc875c2eSYuval Mintz * since otherwise a new attention will be generated.
1330cc875c2eSYuval Mintz */
1331cc875c2eSYuval Mintz qed_sb_ack_attn(p_hwfn, sb_info->igu_addr, sb_attn->index);
1332cc875c2eSYuval Mintz
1333fe56b9e6SYuval Mintz qed_sb_ack(sb_info, IGU_INT_ENABLE, 1);
1334fe56b9e6SYuval Mintz }
1335fe56b9e6SYuval Mintz
qed_int_sb_attn_free(struct qed_hwfn * p_hwfn)1336cc875c2eSYuval Mintz static void qed_int_sb_attn_free(struct qed_hwfn *p_hwfn)
1337cc875c2eSYuval Mintz {
1338cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb = p_hwfn->p_sb_attn;
1339cc875c2eSYuval Mintz
13404ac801b7SYuval Mintz if (!p_sb)
13414ac801b7SYuval Mintz return;
13424ac801b7SYuval Mintz
1343cc875c2eSYuval Mintz if (p_sb->sb_attn)
13444ac801b7SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1345cc875c2eSYuval Mintz SB_ATTN_ALIGNED_SIZE(p_hwfn),
13461a635e48SYuval Mintz p_sb->sb_attn, p_sb->sb_phys);
1347cc875c2eSYuval Mintz kfree(p_sb);
13483587cb87STomer Tayar p_hwfn->p_sb_attn = NULL;
1349cc875c2eSYuval Mintz }
1350cc875c2eSYuval Mintz
qed_int_sb_attn_setup(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt)1351cc875c2eSYuval Mintz static void qed_int_sb_attn_setup(struct qed_hwfn *p_hwfn,
1352cc875c2eSYuval Mintz struct qed_ptt *p_ptt)
1353cc875c2eSYuval Mintz {
1354cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
1355cc875c2eSYuval Mintz
1356cc875c2eSYuval Mintz memset(sb_info->sb_attn, 0, sizeof(*sb_info->sb_attn));
1357cc875c2eSYuval Mintz
1358cc875c2eSYuval Mintz sb_info->index = 0;
1359cc875c2eSYuval Mintz sb_info->known_attn = 0;
1360cc875c2eSYuval Mintz
1361cc875c2eSYuval Mintz /* Configure Attention Status Block in IGU */
1362cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_L,
1363cc875c2eSYuval Mintz lower_32_bits(p_hwfn->p_sb_attn->sb_phys));
1364cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTN_MSG_ADDR_H,
1365cc875c2eSYuval Mintz upper_32_bits(p_hwfn->p_sb_attn->sb_phys));
1366cc875c2eSYuval Mintz }
1367cc875c2eSYuval Mintz
qed_int_sb_attn_init(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,void * sb_virt_addr,dma_addr_t sb_phy_addr)1368cc875c2eSYuval Mintz static void qed_int_sb_attn_init(struct qed_hwfn *p_hwfn,
1369cc875c2eSYuval Mintz struct qed_ptt *p_ptt,
13701a635e48SYuval Mintz void *sb_virt_addr, dma_addr_t sb_phy_addr)
1371cc875c2eSYuval Mintz {
1372cc875c2eSYuval Mintz struct qed_sb_attn_info *sb_info = p_hwfn->p_sb_attn;
13730d956e8aSYuval Mintz int i, j, k;
1374cc875c2eSYuval Mintz
1375cc875c2eSYuval Mintz sb_info->sb_attn = sb_virt_addr;
1376cc875c2eSYuval Mintz sb_info->sb_phys = sb_phy_addr;
1377cc875c2eSYuval Mintz
13780d956e8aSYuval Mintz /* Set the pointer to the AEU descriptors */
13790d956e8aSYuval Mintz sb_info->p_aeu_desc = aeu_descs;
13800d956e8aSYuval Mintz
13810d956e8aSYuval Mintz /* Calculate Parity Masks */
13820d956e8aSYuval Mintz memset(sb_info->parity_mask, 0, sizeof(u32) * NUM_ATTN_REGS);
13830d956e8aSYuval Mintz for (i = 0; i < NUM_ATTN_REGS; i++) {
13840d956e8aSYuval Mintz /* j is array index, k is bit index */
13850435a4d0Szhangyue for (j = 0, k = 0; k < 32 && j < 32; j++) {
1386ba36f718SMintz, Yuval struct aeu_invert_reg_bit *p_aeu;
13870d956e8aSYuval Mintz
1388ba36f718SMintz, Yuval p_aeu = &aeu_descs[i].bits[j];
1389ba36f718SMintz, Yuval if (qed_int_is_parity_flag(p_hwfn, p_aeu))
13900d956e8aSYuval Mintz sb_info->parity_mask[i] |= 1 << k;
13910d956e8aSYuval Mintz
1392ba36f718SMintz, Yuval k += ATTENTION_LENGTH(p_aeu->flags);
13930d956e8aSYuval Mintz }
13940d956e8aSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
13950d956e8aSYuval Mintz "Attn Mask [Reg %d]: 0x%08x\n",
13960d956e8aSYuval Mintz i, sb_info->parity_mask[i]);
13970d956e8aSYuval Mintz }
13980d956e8aSYuval Mintz
1399cc875c2eSYuval Mintz /* Set the address of cleanup for the mcp attention */
1400cc875c2eSYuval Mintz sb_info->mfw_attn_addr = (p_hwfn->rel_pf_id << 3) +
1401cc875c2eSYuval Mintz MISC_REG_AEU_GENERAL_ATTN_0;
1402cc875c2eSYuval Mintz
1403cc875c2eSYuval Mintz qed_int_sb_attn_setup(p_hwfn, p_ptt);
1404cc875c2eSYuval Mintz }
1405cc875c2eSYuval Mintz
qed_int_sb_attn_alloc(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt)1406cc875c2eSYuval Mintz static int qed_int_sb_attn_alloc(struct qed_hwfn *p_hwfn,
1407cc875c2eSYuval Mintz struct qed_ptt *p_ptt)
1408cc875c2eSYuval Mintz {
1409cc875c2eSYuval Mintz struct qed_dev *cdev = p_hwfn->cdev;
1410cc875c2eSYuval Mintz struct qed_sb_attn_info *p_sb;
1411cc875c2eSYuval Mintz dma_addr_t p_phys = 0;
14121a635e48SYuval Mintz void *p_virt;
1413cc875c2eSYuval Mintz
1414cc875c2eSYuval Mintz /* SB struct */
141560fffb3bSYuval Mintz p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL);
14162591c280SJoe Perches if (!p_sb)
1417cc875c2eSYuval Mintz return -ENOMEM;
1418cc875c2eSYuval Mintz
1419cc875c2eSYuval Mintz /* SB ring */
1420cc875c2eSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev,
1421cc875c2eSYuval Mintz SB_ATTN_ALIGNED_SIZE(p_hwfn),
1422cc875c2eSYuval Mintz &p_phys, GFP_KERNEL);
1423cc875c2eSYuval Mintz
1424cc875c2eSYuval Mintz if (!p_virt) {
1425cc875c2eSYuval Mintz kfree(p_sb);
1426cc875c2eSYuval Mintz return -ENOMEM;
1427cc875c2eSYuval Mintz }
1428cc875c2eSYuval Mintz
1429cc875c2eSYuval Mintz /* Attention setup */
1430cc875c2eSYuval Mintz p_hwfn->p_sb_attn = p_sb;
1431cc875c2eSYuval Mintz qed_int_sb_attn_init(p_hwfn, p_ptt, p_virt, p_phys);
1432cc875c2eSYuval Mintz
1433cc875c2eSYuval Mintz return 0;
1434cc875c2eSYuval Mintz }
1435cc875c2eSYuval Mintz
1436fe56b9e6SYuval Mintz /* coalescing timeout = timeset << (timer_res + 1) */
1437fe56b9e6SYuval Mintz #define QED_CAU_DEF_RX_USECS 24
1438fe56b9e6SYuval Mintz #define QED_CAU_DEF_TX_USECS 48
1439fe56b9e6SYuval Mintz
qed_init_cau_sb_entry(struct qed_hwfn * p_hwfn,struct cau_sb_entry * p_sb_entry,u8 pf_id,u16 vf_number,u8 vf_valid)1440fe56b9e6SYuval Mintz void qed_init_cau_sb_entry(struct qed_hwfn *p_hwfn,
1441fe56b9e6SYuval Mintz struct cau_sb_entry *p_sb_entry,
14421a635e48SYuval Mintz u8 pf_id, u16 vf_number, u8 vf_valid)
1443fe56b9e6SYuval Mintz {
14444ac801b7SYuval Mintz struct qed_dev *cdev = p_hwfn->cdev;
14455ab90341SAlexander Lobakin u32 cau_state, params = 0, data = 0;
1446722003acSSudarsana Reddy Kalluru u8 timer_res;
1447fe56b9e6SYuval Mintz
1448fe56b9e6SYuval Mintz memset(p_sb_entry, 0, sizeof(*p_sb_entry));
1449fe56b9e6SYuval Mintz
14505ab90341SAlexander Lobakin SET_FIELD(params, CAU_SB_ENTRY_PF_NUMBER, pf_id);
14515ab90341SAlexander Lobakin SET_FIELD(params, CAU_SB_ENTRY_VF_NUMBER, vf_number);
14525ab90341SAlexander Lobakin SET_FIELD(params, CAU_SB_ENTRY_VF_VALID, vf_valid);
14535ab90341SAlexander Lobakin SET_FIELD(params, CAU_SB_ENTRY_SB_TIMESET0, 0x7F);
14545ab90341SAlexander Lobakin SET_FIELD(params, CAU_SB_ENTRY_SB_TIMESET1, 0x7F);
1455fe56b9e6SYuval Mintz
1456fe56b9e6SYuval Mintz cau_state = CAU_HC_DISABLE_STATE;
1457fe56b9e6SYuval Mintz
14584ac801b7SYuval Mintz if (cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) {
1459fe56b9e6SYuval Mintz cau_state = CAU_HC_ENABLE_STATE;
14604ac801b7SYuval Mintz if (!cdev->rx_coalesce_usecs)
14614ac801b7SYuval Mintz cdev->rx_coalesce_usecs = QED_CAU_DEF_RX_USECS;
14624ac801b7SYuval Mintz if (!cdev->tx_coalesce_usecs)
14634ac801b7SYuval Mintz cdev->tx_coalesce_usecs = QED_CAU_DEF_TX_USECS;
1464fe56b9e6SYuval Mintz }
1465fe56b9e6SYuval Mintz
1466722003acSSudarsana Reddy Kalluru /* Coalesce = (timeset << timer-res), timeset is 7bit wide */
1467722003acSSudarsana Reddy Kalluru if (cdev->rx_coalesce_usecs <= 0x7F)
1468722003acSSudarsana Reddy Kalluru timer_res = 0;
1469722003acSSudarsana Reddy Kalluru else if (cdev->rx_coalesce_usecs <= 0xFF)
1470722003acSSudarsana Reddy Kalluru timer_res = 1;
1471722003acSSudarsana Reddy Kalluru else
1472722003acSSudarsana Reddy Kalluru timer_res = 2;
14735ab90341SAlexander Lobakin
14745ab90341SAlexander Lobakin SET_FIELD(params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
1475722003acSSudarsana Reddy Kalluru
1476722003acSSudarsana Reddy Kalluru if (cdev->tx_coalesce_usecs <= 0x7F)
1477722003acSSudarsana Reddy Kalluru timer_res = 0;
1478722003acSSudarsana Reddy Kalluru else if (cdev->tx_coalesce_usecs <= 0xFF)
1479722003acSSudarsana Reddy Kalluru timer_res = 1;
1480722003acSSudarsana Reddy Kalluru else
1481722003acSSudarsana Reddy Kalluru timer_res = 2;
1482722003acSSudarsana Reddy Kalluru
14835ab90341SAlexander Lobakin SET_FIELD(params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
14845ab90341SAlexander Lobakin p_sb_entry->params = cpu_to_le32(params);
14855ab90341SAlexander Lobakin
14865ab90341SAlexander Lobakin SET_FIELD(data, CAU_SB_ENTRY_STATE0, cau_state);
14875ab90341SAlexander Lobakin SET_FIELD(data, CAU_SB_ENTRY_STATE1, cau_state);
14885ab90341SAlexander Lobakin p_sb_entry->data = cpu_to_le32(data);
1489fe56b9e6SYuval Mintz }
1490fe56b9e6SYuval Mintz
qed_int_cau_conf_pi(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,u16 igu_sb_id,u32 pi_index,enum qed_coalescing_fsm coalescing_fsm,u8 timeset)14918befd73cSMintz, Yuval static void qed_int_cau_conf_pi(struct qed_hwfn *p_hwfn,
14928befd73cSMintz, Yuval struct qed_ptt *p_ptt,
14938befd73cSMintz, Yuval u16 igu_sb_id,
14948befd73cSMintz, Yuval u32 pi_index,
14958befd73cSMintz, Yuval enum qed_coalescing_fsm coalescing_fsm,
14968befd73cSMintz, Yuval u8 timeset)
14978befd73cSMintz, Yuval {
14988befd73cSMintz, Yuval u32 sb_offset, pi_offset;
14995ab90341SAlexander Lobakin u32 prod = 0;
15008befd73cSMintz, Yuval
15018befd73cSMintz, Yuval if (IS_VF(p_hwfn->cdev))
15028befd73cSMintz, Yuval return;
15038befd73cSMintz, Yuval
15045ab90341SAlexander Lobakin SET_FIELD(prod, CAU_PI_ENTRY_PI_TIMESET, timeset);
15058befd73cSMintz, Yuval if (coalescing_fsm == QED_COAL_RX_STATE_MACHINE)
15065ab90341SAlexander Lobakin SET_FIELD(prod, CAU_PI_ENTRY_FSM_SEL, 0);
15078befd73cSMintz, Yuval else
15085ab90341SAlexander Lobakin SET_FIELD(prod, CAU_PI_ENTRY_FSM_SEL, 1);
15098befd73cSMintz, Yuval
1510fb09a1edSShai Malin sb_offset = igu_sb_id * PIS_PER_SB;
15118befd73cSMintz, Yuval pi_offset = sb_offset + pi_index;
15125ab90341SAlexander Lobakin
15135ab90341SAlexander Lobakin if (p_hwfn->hw_init_done)
15148befd73cSMintz, Yuval qed_wr(p_hwfn, p_ptt,
15155ab90341SAlexander Lobakin CAU_REG_PI_MEMORY + pi_offset * sizeof(u32), prod);
15165ab90341SAlexander Lobakin else
15175ab90341SAlexander Lobakin STORE_RT_REG(p_hwfn, CAU_REG_PI_MEMORY_RT_OFFSET + pi_offset,
15185ab90341SAlexander Lobakin prod);
15198befd73cSMintz, Yuval }
15208befd73cSMintz, Yuval
qed_int_cau_conf_sb(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,dma_addr_t sb_phys,u16 igu_sb_id,u16 vf_number,u8 vf_valid)1521fe56b9e6SYuval Mintz void qed_int_cau_conf_sb(struct qed_hwfn *p_hwfn,
1522fe56b9e6SYuval Mintz struct qed_ptt *p_ptt,
1523fe56b9e6SYuval Mintz dma_addr_t sb_phys,
15241a635e48SYuval Mintz u16 igu_sb_id, u16 vf_number, u8 vf_valid)
1525fe56b9e6SYuval Mintz {
1526fe56b9e6SYuval Mintz struct cau_sb_entry sb_entry;
1527fe56b9e6SYuval Mintz
1528fe56b9e6SYuval Mintz qed_init_cau_sb_entry(p_hwfn, &sb_entry, p_hwfn->rel_pf_id,
1529fe56b9e6SYuval Mintz vf_number, vf_valid);
1530fe56b9e6SYuval Mintz
1531fe56b9e6SYuval Mintz if (p_hwfn->hw_init_done) {
15320a0c5d3bSYuval Mintz /* Wide-bus, initialize via DMAE */
15330a0c5d3bSYuval Mintz u64 phys_addr = (u64)sb_phys;
1534fe56b9e6SYuval Mintz
15350a0c5d3bSYuval Mintz qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&phys_addr,
15360a0c5d3bSYuval Mintz CAU_REG_SB_ADDR_MEMORY +
153783bf76e3SMichal Kalderon igu_sb_id * sizeof(u64), 2, NULL);
15380a0c5d3bSYuval Mintz qed_dmae_host2grc(p_hwfn, p_ptt, (u64)(uintptr_t)&sb_entry,
15390a0c5d3bSYuval Mintz CAU_REG_SB_VAR_MEMORY +
154083bf76e3SMichal Kalderon igu_sb_id * sizeof(u64), 2, NULL);
1541fe56b9e6SYuval Mintz } else {
1542fe56b9e6SYuval Mintz /* Initialize Status Block Address */
1543fe56b9e6SYuval Mintz STORE_RT_REG_AGG(p_hwfn,
1544fe56b9e6SYuval Mintz CAU_REG_SB_ADDR_MEMORY_RT_OFFSET +
1545fe56b9e6SYuval Mintz igu_sb_id * 2,
1546fe56b9e6SYuval Mintz sb_phys);
1547fe56b9e6SYuval Mintz
1548fe56b9e6SYuval Mintz STORE_RT_REG_AGG(p_hwfn,
1549fe56b9e6SYuval Mintz CAU_REG_SB_VAR_MEMORY_RT_OFFSET +
1550fe56b9e6SYuval Mintz igu_sb_id * 2,
1551fe56b9e6SYuval Mintz sb_entry);
1552fe56b9e6SYuval Mintz }
1553fe56b9e6SYuval Mintz
1554fe56b9e6SYuval Mintz /* Configure pi coalescing if set */
1555fe56b9e6SYuval Mintz if (p_hwfn->cdev->int_coalescing_mode == QED_COAL_MODE_ENABLE) {
1556b5a9ee7cSAriel Elior u8 num_tc = p_hwfn->hw_info.num_hw_tc;
1557722003acSSudarsana Reddy Kalluru u8 timeset, timer_res;
1558b5a9ee7cSAriel Elior u8 i;
1559fe56b9e6SYuval Mintz
1560722003acSSudarsana Reddy Kalluru /* timeset = (coalesce >> timer-res), timeset is 7bit wide */
1561722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->rx_coalesce_usecs <= 0x7F)
1562722003acSSudarsana Reddy Kalluru timer_res = 0;
1563722003acSSudarsana Reddy Kalluru else if (p_hwfn->cdev->rx_coalesce_usecs <= 0xFF)
1564722003acSSudarsana Reddy Kalluru timer_res = 1;
1565722003acSSudarsana Reddy Kalluru else
1566722003acSSudarsana Reddy Kalluru timer_res = 2;
1567722003acSSudarsana Reddy Kalluru timeset = (u8)(p_hwfn->cdev->rx_coalesce_usecs >> timer_res);
1568fe56b9e6SYuval Mintz qed_int_cau_conf_pi(p_hwfn, p_ptt, igu_sb_id, RX_PI,
15691a635e48SYuval Mintz QED_COAL_RX_STATE_MACHINE, timeset);
1570fe56b9e6SYuval Mintz
1571722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->tx_coalesce_usecs <= 0x7F)
1572722003acSSudarsana Reddy Kalluru timer_res = 0;
1573722003acSSudarsana Reddy Kalluru else if (p_hwfn->cdev->tx_coalesce_usecs <= 0xFF)
1574722003acSSudarsana Reddy Kalluru timer_res = 1;
1575722003acSSudarsana Reddy Kalluru else
1576722003acSSudarsana Reddy Kalluru timer_res = 2;
1577722003acSSudarsana Reddy Kalluru timeset = (u8)(p_hwfn->cdev->tx_coalesce_usecs >> timer_res);
1578fe56b9e6SYuval Mintz for (i = 0; i < num_tc; i++) {
1579fe56b9e6SYuval Mintz qed_int_cau_conf_pi(p_hwfn, p_ptt,
1580fe56b9e6SYuval Mintz igu_sb_id, TX_PI(i),
1581fe56b9e6SYuval Mintz QED_COAL_TX_STATE_MACHINE,
1582fe56b9e6SYuval Mintz timeset);
1583fe56b9e6SYuval Mintz }
1584fe56b9e6SYuval Mintz }
1585fe56b9e6SYuval Mintz }
1586fe56b9e6SYuval Mintz
qed_int_sb_setup(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,struct qed_sb_info * sb_info)1587fe56b9e6SYuval Mintz void qed_int_sb_setup(struct qed_hwfn *p_hwfn,
15881a635e48SYuval Mintz struct qed_ptt *p_ptt, struct qed_sb_info *sb_info)
1589fe56b9e6SYuval Mintz {
1590fe56b9e6SYuval Mintz /* zero status block and ack counter */
1591fe56b9e6SYuval Mintz sb_info->sb_ack = 0;
1592fe56b9e6SYuval Mintz memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1593fe56b9e6SYuval Mintz
15941408cc1fSYuval Mintz if (IS_PF(p_hwfn->cdev))
1595fe56b9e6SYuval Mintz qed_int_cau_conf_sb(p_hwfn, p_ptt, sb_info->sb_phys,
1596fe56b9e6SYuval Mintz sb_info->igu_sb_id, 0, 0);
1597fe56b9e6SYuval Mintz }
1598fe56b9e6SYuval Mintz
qed_get_igu_free_sb(struct qed_hwfn * p_hwfn,bool b_is_pf)159909b6b147SMintz, Yuval struct qed_igu_block *qed_get_igu_free_sb(struct qed_hwfn *p_hwfn, bool b_is_pf)
160009b6b147SMintz, Yuval {
160109b6b147SMintz, Yuval struct qed_igu_block *p_block;
160209b6b147SMintz, Yuval u16 igu_id;
160309b6b147SMintz, Yuval
160409b6b147SMintz, Yuval for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev);
160509b6b147SMintz, Yuval igu_id++) {
160609b6b147SMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id];
160709b6b147SMintz, Yuval
160809b6b147SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID) ||
160909b6b147SMintz, Yuval !(p_block->status & QED_IGU_STATUS_FREE))
161009b6b147SMintz, Yuval continue;
161109b6b147SMintz, Yuval
161209b6b147SMintz, Yuval if (!!(p_block->status & QED_IGU_STATUS_PF) == b_is_pf)
161309b6b147SMintz, Yuval return p_block;
161409b6b147SMintz, Yuval }
161509b6b147SMintz, Yuval
161609b6b147SMintz, Yuval return NULL;
161709b6b147SMintz, Yuval }
161809b6b147SMintz, Yuval
qed_get_pf_igu_sb_id(struct qed_hwfn * p_hwfn,u16 vector_id)1619a333f7f3SMintz, Yuval static u16 qed_get_pf_igu_sb_id(struct qed_hwfn *p_hwfn, u16 vector_id)
1620a333f7f3SMintz, Yuval {
1621a333f7f3SMintz, Yuval struct qed_igu_block *p_block;
1622a333f7f3SMintz, Yuval u16 igu_id;
1623a333f7f3SMintz, Yuval
1624a333f7f3SMintz, Yuval for (igu_id = 0; igu_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev);
1625a333f7f3SMintz, Yuval igu_id++) {
1626a333f7f3SMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_id];
1627a333f7f3SMintz, Yuval
1628a333f7f3SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID) ||
1629a333f7f3SMintz, Yuval !p_block->is_pf ||
1630a333f7f3SMintz, Yuval p_block->vector_number != vector_id)
1631a333f7f3SMintz, Yuval continue;
1632a333f7f3SMintz, Yuval
1633a333f7f3SMintz, Yuval return igu_id;
1634a333f7f3SMintz, Yuval }
1635a333f7f3SMintz, Yuval
1636a333f7f3SMintz, Yuval return QED_SB_INVALID_IDX;
1637a333f7f3SMintz, Yuval }
1638a333f7f3SMintz, Yuval
qed_get_igu_sb_id(struct qed_hwfn * p_hwfn,u16 sb_id)163950a20714SMintz, Yuval u16 qed_get_igu_sb_id(struct qed_hwfn *p_hwfn, u16 sb_id)
1640fe56b9e6SYuval Mintz {
1641fe56b9e6SYuval Mintz u16 igu_sb_id;
1642fe56b9e6SYuval Mintz
1643fe56b9e6SYuval Mintz /* Assuming continuous set of IGU SBs dedicated for given PF */
1644fe56b9e6SYuval Mintz if (sb_id == QED_SP_SB_ID)
1645fe56b9e6SYuval Mintz igu_sb_id = p_hwfn->hw_info.p_igu_info->igu_dsb_id;
16461408cc1fSYuval Mintz else if (IS_PF(p_hwfn->cdev))
1647a333f7f3SMintz, Yuval igu_sb_id = qed_get_pf_igu_sb_id(p_hwfn, sb_id + 1);
16481408cc1fSYuval Mintz else
16491408cc1fSYuval Mintz igu_sb_id = qed_vf_get_igu_sb_id(p_hwfn, sb_id);
1650fe56b9e6SYuval Mintz
1651525ef5c0SYuval Mintz if (sb_id == QED_SP_SB_ID)
1652525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1653525ef5c0SYuval Mintz "Slowpath SB index in IGU is 0x%04x\n", igu_sb_id);
1654525ef5c0SYuval Mintz else
1655525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
1656525ef5c0SYuval Mintz "SB [%04x] <--> IGU SB [%04x]\n", sb_id, igu_sb_id);
1657fe56b9e6SYuval Mintz
1658fe56b9e6SYuval Mintz return igu_sb_id;
1659fe56b9e6SYuval Mintz }
1660fe56b9e6SYuval Mintz
qed_int_sb_init(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,struct qed_sb_info * sb_info,void * sb_virt_addr,dma_addr_t sb_phy_addr,u16 sb_id)1661fe56b9e6SYuval Mintz int qed_int_sb_init(struct qed_hwfn *p_hwfn,
1662fe56b9e6SYuval Mintz struct qed_ptt *p_ptt,
1663fe56b9e6SYuval Mintz struct qed_sb_info *sb_info,
16641a635e48SYuval Mintz void *sb_virt_addr, dma_addr_t sb_phy_addr, u16 sb_id)
1665fe56b9e6SYuval Mintz {
1666fe56b9e6SYuval Mintz sb_info->sb_virt = sb_virt_addr;
1667fe56b9e6SYuval Mintz sb_info->sb_phys = sb_phy_addr;
1668fe56b9e6SYuval Mintz
1669fe56b9e6SYuval Mintz sb_info->igu_sb_id = qed_get_igu_sb_id(p_hwfn, sb_id);
1670fe56b9e6SYuval Mintz
1671fe56b9e6SYuval Mintz if (sb_id != QED_SP_SB_ID) {
167250a20714SMintz, Yuval if (IS_PF(p_hwfn->cdev)) {
167350a20714SMintz, Yuval struct qed_igu_info *p_info;
167450a20714SMintz, Yuval struct qed_igu_block *p_block;
167550a20714SMintz, Yuval
167650a20714SMintz, Yuval p_info = p_hwfn->hw_info.p_igu_info;
167750a20714SMintz, Yuval p_block = &p_info->entry[sb_info->igu_sb_id];
167850a20714SMintz, Yuval
167950a20714SMintz, Yuval p_block->sb_info = sb_info;
168050a20714SMintz, Yuval p_block->status &= ~QED_IGU_STATUS_FREE;
168150a20714SMintz, Yuval p_info->usage.free_cnt--;
168250a20714SMintz, Yuval } else {
168350a20714SMintz, Yuval qed_vf_set_sb_info(p_hwfn, sb_id, sb_info);
168450a20714SMintz, Yuval }
1685fe56b9e6SYuval Mintz }
1686fe56b9e6SYuval Mintz
1687fe56b9e6SYuval Mintz sb_info->cdev = p_hwfn->cdev;
1688fe56b9e6SYuval Mintz
1689fe56b9e6SYuval Mintz /* The igu address will hold the absolute address that needs to be
1690fe56b9e6SYuval Mintz * written to for a specific status block
1691fe56b9e6SYuval Mintz */
16921408cc1fSYuval Mintz if (IS_PF(p_hwfn->cdev)) {
1693fe56b9e6SYuval Mintz sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview +
1694fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD +
1695fe56b9e6SYuval Mintz (sb_info->igu_sb_id << 3);
16961408cc1fSYuval Mintz } else {
16971408cc1fSYuval Mintz sb_info->igu_addr = (u8 __iomem *)p_hwfn->regview +
16981408cc1fSYuval Mintz PXP_VF_BAR0_START_IGU +
16991408cc1fSYuval Mintz ((IGU_CMD_INT_ACK_BASE +
17001408cc1fSYuval Mintz sb_info->igu_sb_id) << 3);
17011408cc1fSYuval Mintz }
1702fe56b9e6SYuval Mintz
1703fe56b9e6SYuval Mintz sb_info->flags |= QED_SB_INFO_INIT;
1704fe56b9e6SYuval Mintz
1705fe56b9e6SYuval Mintz qed_int_sb_setup(p_hwfn, p_ptt, sb_info);
1706fe56b9e6SYuval Mintz
1707fe56b9e6SYuval Mintz return 0;
1708fe56b9e6SYuval Mintz }
1709fe56b9e6SYuval Mintz
qed_int_sb_release(struct qed_hwfn * p_hwfn,struct qed_sb_info * sb_info,u16 sb_id)1710fe56b9e6SYuval Mintz int qed_int_sb_release(struct qed_hwfn *p_hwfn,
17111a635e48SYuval Mintz struct qed_sb_info *sb_info, u16 sb_id)
1712fe56b9e6SYuval Mintz {
171350a20714SMintz, Yuval struct qed_igu_block *p_block;
171450a20714SMintz, Yuval struct qed_igu_info *p_info;
171550a20714SMintz, Yuval
171650a20714SMintz, Yuval if (!sb_info)
171750a20714SMintz, Yuval return 0;
1718fe56b9e6SYuval Mintz
1719fe56b9e6SYuval Mintz /* zero status block and ack counter */
1720fe56b9e6SYuval Mintz sb_info->sb_ack = 0;
1721fe56b9e6SYuval Mintz memset(sb_info->sb_virt, 0, sizeof(*sb_info->sb_virt));
1722fe56b9e6SYuval Mintz
172350a20714SMintz, Yuval if (IS_VF(p_hwfn->cdev)) {
172450a20714SMintz, Yuval qed_vf_set_sb_info(p_hwfn, sb_id, NULL);
172550a20714SMintz, Yuval return 0;
17264ac801b7SYuval Mintz }
1727fe56b9e6SYuval Mintz
172850a20714SMintz, Yuval p_info = p_hwfn->hw_info.p_igu_info;
172950a20714SMintz, Yuval p_block = &p_info->entry[sb_info->igu_sb_id];
173050a20714SMintz, Yuval
173150a20714SMintz, Yuval /* Vector 0 is reserved to Default SB */
173250a20714SMintz, Yuval if (!p_block->vector_number) {
173350a20714SMintz, Yuval DP_ERR(p_hwfn, "Do Not free sp sb using this function");
173450a20714SMintz, Yuval return -EINVAL;
173550a20714SMintz, Yuval }
173650a20714SMintz, Yuval
173750a20714SMintz, Yuval /* Lose reference to client's SB info, and fix counters */
173850a20714SMintz, Yuval p_block->sb_info = NULL;
173950a20714SMintz, Yuval p_block->status |= QED_IGU_STATUS_FREE;
174050a20714SMintz, Yuval p_info->usage.free_cnt++;
174150a20714SMintz, Yuval
1742fe56b9e6SYuval Mintz return 0;
1743fe56b9e6SYuval Mintz }
1744fe56b9e6SYuval Mintz
qed_int_sp_sb_free(struct qed_hwfn * p_hwfn)1745fe56b9e6SYuval Mintz static void qed_int_sp_sb_free(struct qed_hwfn *p_hwfn)
1746fe56b9e6SYuval Mintz {
1747fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sb = p_hwfn->p_sp_sb;
1748fe56b9e6SYuval Mintz
17494ac801b7SYuval Mintz if (!p_sb)
17504ac801b7SYuval Mintz return;
17514ac801b7SYuval Mintz
1752fe56b9e6SYuval Mintz if (p_sb->sb_info.sb_virt)
1753fe56b9e6SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev,
1754fe56b9e6SYuval Mintz SB_ALIGNED_SIZE(p_hwfn),
1755fe56b9e6SYuval Mintz p_sb->sb_info.sb_virt,
1756fe56b9e6SYuval Mintz p_sb->sb_info.sb_phys);
1757fe56b9e6SYuval Mintz kfree(p_sb);
17583587cb87STomer Tayar p_hwfn->p_sp_sb = NULL;
1759fe56b9e6SYuval Mintz }
1760fe56b9e6SYuval Mintz
qed_int_sp_sb_alloc(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt)17611a635e48SYuval Mintz static int qed_int_sp_sb_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1762fe56b9e6SYuval Mintz {
1763fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sb;
1764fe56b9e6SYuval Mintz dma_addr_t p_phys = 0;
1765fe56b9e6SYuval Mintz void *p_virt;
1766fe56b9e6SYuval Mintz
1767fe56b9e6SYuval Mintz /* SB struct */
176860fffb3bSYuval Mintz p_sb = kmalloc(sizeof(*p_sb), GFP_KERNEL);
17692591c280SJoe Perches if (!p_sb)
1770fe56b9e6SYuval Mintz return -ENOMEM;
1771fe56b9e6SYuval Mintz
1772fe56b9e6SYuval Mintz /* SB ring */
1773fe56b9e6SYuval Mintz p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev,
1774fe56b9e6SYuval Mintz SB_ALIGNED_SIZE(p_hwfn),
1775fe56b9e6SYuval Mintz &p_phys, GFP_KERNEL);
1776fe56b9e6SYuval Mintz if (!p_virt) {
1777fe56b9e6SYuval Mintz kfree(p_sb);
1778fe56b9e6SYuval Mintz return -ENOMEM;
1779fe56b9e6SYuval Mintz }
1780fe56b9e6SYuval Mintz
1781fe56b9e6SYuval Mintz /* Status Block setup */
1782fe56b9e6SYuval Mintz p_hwfn->p_sp_sb = p_sb;
1783fe56b9e6SYuval Mintz qed_int_sb_init(p_hwfn, p_ptt, &p_sb->sb_info, p_virt,
1784fe56b9e6SYuval Mintz p_phys, QED_SP_SB_ID);
1785fe56b9e6SYuval Mintz
1786fe56b9e6SYuval Mintz memset(p_sb->pi_info_arr, 0, sizeof(p_sb->pi_info_arr));
1787fe56b9e6SYuval Mintz
1788fe56b9e6SYuval Mintz return 0;
1789fe56b9e6SYuval Mintz }
1790fe56b9e6SYuval Mintz
qed_int_register_cb(struct qed_hwfn * p_hwfn,qed_int_comp_cb_t comp_cb,void * cookie,u8 * sb_idx,__le16 ** p_fw_cons)1791fe56b9e6SYuval Mintz int qed_int_register_cb(struct qed_hwfn *p_hwfn,
1792fe56b9e6SYuval Mintz qed_int_comp_cb_t comp_cb,
17931a635e48SYuval Mintz void *cookie, u8 *sb_idx, __le16 **p_fw_cons)
1794fe56b9e6SYuval Mintz {
1795fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
17964ac801b7SYuval Mintz int rc = -ENOMEM;
1797fe56b9e6SYuval Mintz u8 pi;
1798fe56b9e6SYuval Mintz
1799fe56b9e6SYuval Mintz /* Look for a free index */
1800fe56b9e6SYuval Mintz for (pi = 0; pi < ARRAY_SIZE(p_sp_sb->pi_info_arr); pi++) {
18014ac801b7SYuval Mintz if (p_sp_sb->pi_info_arr[pi].comp_cb)
18024ac801b7SYuval Mintz continue;
18034ac801b7SYuval Mintz
1804fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].comp_cb = comp_cb;
1805fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].cookie = cookie;
1806fe56b9e6SYuval Mintz *sb_idx = pi;
1807fe56b9e6SYuval Mintz *p_fw_cons = &p_sp_sb->sb_info.sb_virt->pi_array[pi];
18084ac801b7SYuval Mintz rc = 0;
1809fe56b9e6SYuval Mintz break;
1810fe56b9e6SYuval Mintz }
1811fe56b9e6SYuval Mintz
18124ac801b7SYuval Mintz return rc;
1813fe56b9e6SYuval Mintz }
1814fe56b9e6SYuval Mintz
qed_int_unregister_cb(struct qed_hwfn * p_hwfn,u8 pi)1815fe56b9e6SYuval Mintz int qed_int_unregister_cb(struct qed_hwfn *p_hwfn, u8 pi)
1816fe56b9e6SYuval Mintz {
1817fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb = p_hwfn->p_sp_sb;
1818fe56b9e6SYuval Mintz
18194ac801b7SYuval Mintz if (p_sp_sb->pi_info_arr[pi].comp_cb == NULL)
18204ac801b7SYuval Mintz return -ENOMEM;
18214ac801b7SYuval Mintz
1822fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].comp_cb = NULL;
1823fe56b9e6SYuval Mintz p_sp_sb->pi_info_arr[pi].cookie = NULL;
1824fe56b9e6SYuval Mintz
18254ac801b7SYuval Mintz return 0;
1826fe56b9e6SYuval Mintz }
1827fe56b9e6SYuval Mintz
qed_int_get_sp_sb_id(struct qed_hwfn * p_hwfn)1828fe56b9e6SYuval Mintz u16 qed_int_get_sp_sb_id(struct qed_hwfn *p_hwfn)
1829fe56b9e6SYuval Mintz {
1830fe56b9e6SYuval Mintz return p_hwfn->p_sp_sb->sb_info.igu_sb_id;
1831fe56b9e6SYuval Mintz }
1832fe56b9e6SYuval Mintz
qed_int_igu_enable_int(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,enum qed_int_mode int_mode)1833fe56b9e6SYuval Mintz void qed_int_igu_enable_int(struct qed_hwfn *p_hwfn,
18341a635e48SYuval Mintz struct qed_ptt *p_ptt, enum qed_int_mode int_mode)
1835fe56b9e6SYuval Mintz {
1836cc875c2eSYuval Mintz u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN | IGU_PF_CONF_ATTN_BIT_EN;
1837fe56b9e6SYuval Mintz
1838fe56b9e6SYuval Mintz p_hwfn->cdev->int_mode = int_mode;
1839fe56b9e6SYuval Mintz switch (p_hwfn->cdev->int_mode) {
1840fe56b9e6SYuval Mintz case QED_INT_MODE_INTA:
1841fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_INT_LINE_EN;
1842fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1843fe56b9e6SYuval Mintz break;
1844fe56b9e6SYuval Mintz
1845fe56b9e6SYuval Mintz case QED_INT_MODE_MSI:
1846fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1847fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN;
1848fe56b9e6SYuval Mintz break;
1849fe56b9e6SYuval Mintz
1850fe56b9e6SYuval Mintz case QED_INT_MODE_MSIX:
1851fe56b9e6SYuval Mintz igu_pf_conf |= IGU_PF_CONF_MSI_MSIX_EN;
1852fe56b9e6SYuval Mintz break;
1853fe56b9e6SYuval Mintz case QED_INT_MODE_POLL:
1854fe56b9e6SYuval Mintz break;
1855fe56b9e6SYuval Mintz }
1856fe56b9e6SYuval Mintz
1857fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, igu_pf_conf);
1858fe56b9e6SYuval Mintz }
1859fe56b9e6SYuval Mintz
qed_int_igu_enable_attn(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt)1860979cead3SMintz, Yuval static void qed_int_igu_enable_attn(struct qed_hwfn *p_hwfn,
1861979cead3SMintz, Yuval struct qed_ptt *p_ptt)
1862fe56b9e6SYuval Mintz {
1863fe56b9e6SYuval Mintz
18640d956e8aSYuval Mintz /* Configure AEU signal change to produce attentions */
18650d956e8aSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0);
1866cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0xfff);
1867cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0xfff);
18680d956e8aSYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_ATTENTION_ENABLE, 0xfff);
1869cc875c2eSYuval Mintz
1870cc875c2eSYuval Mintz /* Unmask AEU signals toward IGU */
1871cc875c2eSYuval Mintz qed_wr(p_hwfn, p_ptt, MISC_REG_AEU_MASK_ATTN_IGU, 0xff);
1872979cead3SMintz, Yuval }
1873979cead3SMintz, Yuval
1874979cead3SMintz, Yuval int
qed_int_igu_enable(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,enum qed_int_mode int_mode)1875979cead3SMintz, Yuval qed_int_igu_enable(struct qed_hwfn *p_hwfn,
1876979cead3SMintz, Yuval struct qed_ptt *p_ptt, enum qed_int_mode int_mode)
1877979cead3SMintz, Yuval {
1878979cead3SMintz, Yuval int rc = 0;
1879979cead3SMintz, Yuval
1880979cead3SMintz, Yuval qed_int_igu_enable_attn(p_hwfn, p_ptt);
1881979cead3SMintz, Yuval
18828f16bc97SSudarsana Kalluru if ((int_mode != QED_INT_MODE_INTA) || IS_LEAD_HWFN(p_hwfn)) {
18838f16bc97SSudarsana Kalluru rc = qed_slowpath_irq_req(p_hwfn);
18841a635e48SYuval Mintz if (rc) {
18858f16bc97SSudarsana Kalluru DP_NOTICE(p_hwfn, "Slowpath IRQ request failed\n");
18868f16bc97SSudarsana Kalluru return -EINVAL;
18878f16bc97SSudarsana Kalluru }
18888f16bc97SSudarsana Kalluru p_hwfn->b_int_requested = true;
18898f16bc97SSudarsana Kalluru }
18908f16bc97SSudarsana Kalluru /* Enable interrupt Generation */
18918f16bc97SSudarsana Kalluru qed_int_igu_enable_int(p_hwfn, p_ptt, int_mode);
18928f16bc97SSudarsana Kalluru p_hwfn->b_int_enabled = 1;
18938f16bc97SSudarsana Kalluru
18948f16bc97SSudarsana Kalluru return rc;
1895fe56b9e6SYuval Mintz }
1896fe56b9e6SYuval Mintz
qed_int_igu_disable_int(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt)18971a635e48SYuval Mintz void qed_int_igu_disable_int(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1898fe56b9e6SYuval Mintz {
1899fe56b9e6SYuval Mintz p_hwfn->b_int_enabled = 0;
1900fe56b9e6SYuval Mintz
19011408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev))
19021408cc1fSYuval Mintz return;
19031408cc1fSYuval Mintz
1904fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_PF_CONFIGURATION, 0);
1905fe56b9e6SYuval Mintz }
1906fe56b9e6SYuval Mintz
1907fe56b9e6SYuval Mintz #define IGU_CLEANUP_SLEEP_LENGTH (1000)
qed_int_igu_cleanup_sb(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,u16 igu_sb_id,bool cleanup_set,u16 opaque_fid)1908b2b897ebSYuval Mintz static void qed_int_igu_cleanup_sb(struct qed_hwfn *p_hwfn,
1909fe56b9e6SYuval Mintz struct qed_ptt *p_ptt,
1910d031548eSMintz, Yuval u16 igu_sb_id,
1911d031548eSMintz, Yuval bool cleanup_set, u16 opaque_fid)
1912fe56b9e6SYuval Mintz {
1913b2b897ebSYuval Mintz u32 cmd_ctrl = 0, val = 0, sb_bit = 0, sb_bit_addr = 0, data = 0;
1914d031548eSMintz, Yuval u32 pxp_addr = IGU_CMD_INT_ACK_BASE + igu_sb_id;
1915fe56b9e6SYuval Mintz u32 sleep_cnt = IGU_CLEANUP_SLEEP_LENGTH;
1916fe56b9e6SYuval Mintz
1917fe56b9e6SYuval Mintz /* Set the data field */
1918fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_CLEANUP_SET, cleanup_set ? 1 : 0);
1919fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_CLEANUP_TYPE, 0);
1920fe56b9e6SYuval Mintz SET_FIELD(data, IGU_CLEANUP_COMMAND_TYPE, IGU_COMMAND_TYPE_SET);
1921fe56b9e6SYuval Mintz
1922fe56b9e6SYuval Mintz /* Set the control register */
1923fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_PXP_ADDR, pxp_addr);
1924fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_FID, opaque_fid);
1925fe56b9e6SYuval Mintz SET_FIELD(cmd_ctrl, IGU_CTRL_REG_TYPE, IGU_CTRL_CMD_TYPE_WR);
1926fe56b9e6SYuval Mintz
1927fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_32LSB_DATA, data);
1928fe56b9e6SYuval Mintz
1929fe56b9e6SYuval Mintz barrier();
1930fe56b9e6SYuval Mintz
1931fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl);
1932fe56b9e6SYuval Mintz
1933fe56b9e6SYuval Mintz /* calculate where to read the status bit from */
1934d031548eSMintz, Yuval sb_bit = 1 << (igu_sb_id % 32);
1935d031548eSMintz, Yuval sb_bit_addr = igu_sb_id / 32 * sizeof(u32);
1936fe56b9e6SYuval Mintz
1937fe56b9e6SYuval Mintz sb_bit_addr += IGU_REG_CLEANUP_STATUS_0;
1938fe56b9e6SYuval Mintz
1939fe56b9e6SYuval Mintz /* Now wait for the command to complete */
1940fe56b9e6SYuval Mintz do {
1941fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, sb_bit_addr);
1942fe56b9e6SYuval Mintz
1943fe56b9e6SYuval Mintz if ((val & sb_bit) == (cleanup_set ? sb_bit : 0))
1944fe56b9e6SYuval Mintz break;
1945fe56b9e6SYuval Mintz
1946fe56b9e6SYuval Mintz usleep_range(5000, 10000);
1947fe56b9e6SYuval Mintz } while (--sleep_cnt);
1948fe56b9e6SYuval Mintz
1949fe56b9e6SYuval Mintz if (!sleep_cnt)
1950fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn,
1951fe56b9e6SYuval Mintz "Timeout waiting for clear status 0x%08x [for sb %d]\n",
1952d031548eSMintz, Yuval val, igu_sb_id);
1953fe56b9e6SYuval Mintz }
1954fe56b9e6SYuval Mintz
qed_int_igu_init_pure_rt_single(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,u16 igu_sb_id,u16 opaque,bool b_set)1955fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt_single(struct qed_hwfn *p_hwfn,
1956fe56b9e6SYuval Mintz struct qed_ptt *p_ptt,
1957d031548eSMintz, Yuval u16 igu_sb_id, u16 opaque, bool b_set)
1958fe56b9e6SYuval Mintz {
19591ac72433SMintz, Yuval struct qed_igu_block *p_block;
1960b2b897ebSYuval Mintz int pi, i;
1961fe56b9e6SYuval Mintz
19621ac72433SMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id];
19631ac72433SMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
19641ac72433SMintz, Yuval "Cleaning SB [%04x]: func_id= %d is_pf = %d vector_num = 0x%0x\n",
19651ac72433SMintz, Yuval igu_sb_id,
19661ac72433SMintz, Yuval p_block->function_id,
19671ac72433SMintz, Yuval p_block->is_pf, p_block->vector_number);
19681ac72433SMintz, Yuval
1969fe56b9e6SYuval Mintz /* Set */
1970fe56b9e6SYuval Mintz if (b_set)
1971d031548eSMintz, Yuval qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 1, opaque);
1972fe56b9e6SYuval Mintz
1973fe56b9e6SYuval Mintz /* Clear */
1974d031548eSMintz, Yuval qed_int_igu_cleanup_sb(p_hwfn, p_ptt, igu_sb_id, 0, opaque);
1975fe56b9e6SYuval Mintz
1976b2b897ebSYuval Mintz /* Wait for the IGU SB to cleanup */
1977b2b897ebSYuval Mintz for (i = 0; i < IGU_CLEANUP_SLEEP_LENGTH; i++) {
1978b2b897ebSYuval Mintz u32 val;
1979b2b897ebSYuval Mintz
1980b2b897ebSYuval Mintz val = qed_rd(p_hwfn, p_ptt,
1981d031548eSMintz, Yuval IGU_REG_WRITE_DONE_PENDING +
1982d031548eSMintz, Yuval ((igu_sb_id / 32) * 4));
1983d031548eSMintz, Yuval if (val & BIT((igu_sb_id % 32)))
1984b2b897ebSYuval Mintz usleep_range(10, 20);
1985b2b897ebSYuval Mintz else
1986b2b897ebSYuval Mintz break;
1987b2b897ebSYuval Mintz }
1988b2b897ebSYuval Mintz if (i == IGU_CLEANUP_SLEEP_LENGTH)
1989b2b897ebSYuval Mintz DP_NOTICE(p_hwfn,
1990b2b897ebSYuval Mintz "Failed SB[0x%08x] still appearing in WRITE_DONE_PENDING\n",
1991d031548eSMintz, Yuval igu_sb_id);
1992b2b897ebSYuval Mintz
1993fe56b9e6SYuval Mintz /* Clear the CAU for the SB */
1994fe56b9e6SYuval Mintz for (pi = 0; pi < 12; pi++)
1995fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt,
1996d031548eSMintz, Yuval CAU_REG_PI_MEMORY + (igu_sb_id * 12 + pi) * 4, 0);
1997fe56b9e6SYuval Mintz }
1998fe56b9e6SYuval Mintz
qed_int_igu_init_pure_rt(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,bool b_set,bool b_slowpath)1999fe56b9e6SYuval Mintz void qed_int_igu_init_pure_rt(struct qed_hwfn *p_hwfn,
2000fe56b9e6SYuval Mintz struct qed_ptt *p_ptt,
2001b2b897ebSYuval Mintz bool b_set, bool b_slowpath)
2002fe56b9e6SYuval Mintz {
20031ac72433SMintz, Yuval struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
20041ac72433SMintz, Yuval struct qed_igu_block *p_block;
20051ac72433SMintz, Yuval u16 igu_sb_id = 0;
20061ac72433SMintz, Yuval u32 val = 0;
2007fe56b9e6SYuval Mintz
2008fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION);
2009fe56b9e6SYuval Mintz val |= IGU_REG_BLOCK_CONFIGURATION_VF_CLEANUP_EN;
2010fe56b9e6SYuval Mintz val &= ~IGU_REG_BLOCK_CONFIGURATION_PXP_TPH_INTERFACE_EN;
2011fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_BLOCK_CONFIGURATION, val);
2012fe56b9e6SYuval Mintz
20131ac72433SMintz, Yuval for (igu_sb_id = 0;
20141ac72433SMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) {
20151ac72433SMintz, Yuval p_block = &p_info->entry[igu_sb_id];
2016fe56b9e6SYuval Mintz
20171ac72433SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID) ||
20181ac72433SMintz, Yuval !p_block->is_pf ||
20191ac72433SMintz, Yuval (p_block->status & QED_IGU_STATUS_DSB))
20201ac72433SMintz, Yuval continue;
20211ac72433SMintz, Yuval
2022d031548eSMintz, Yuval qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt, igu_sb_id,
2023fe56b9e6SYuval Mintz p_hwfn->hw_info.opaque_fid,
2024fe56b9e6SYuval Mintz b_set);
20251ac72433SMintz, Yuval }
2026fe56b9e6SYuval Mintz
20271ac72433SMintz, Yuval if (b_slowpath)
20281ac72433SMintz, Yuval qed_int_igu_init_pure_rt_single(p_hwfn, p_ptt,
20291ac72433SMintz, Yuval p_info->igu_dsb_id,
20301ac72433SMintz, Yuval p_hwfn->hw_info.opaque_fid,
20311ac72433SMintz, Yuval b_set);
2032fe56b9e6SYuval Mintz }
2033fe56b9e6SYuval Mintz
qed_int_igu_reset_cam(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt)2034ebbdcc66SMintz, Yuval int qed_int_igu_reset_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2035ebbdcc66SMintz, Yuval {
2036ebbdcc66SMintz, Yuval struct qed_igu_info *p_info = p_hwfn->hw_info.p_igu_info;
2037ebbdcc66SMintz, Yuval struct qed_igu_block *p_block;
2038ebbdcc66SMintz, Yuval int pf_sbs, vf_sbs;
2039ebbdcc66SMintz, Yuval u16 igu_sb_id;
2040ebbdcc66SMintz, Yuval u32 val, rval;
2041ebbdcc66SMintz, Yuval
2042ebbdcc66SMintz, Yuval if (!RESC_NUM(p_hwfn, QED_SB)) {
2043ebbdcc66SMintz, Yuval p_info->b_allow_pf_vf_change = false;
2044ebbdcc66SMintz, Yuval } else {
2045ebbdcc66SMintz, Yuval /* Use the numbers the MFW have provided -
2046ebbdcc66SMintz, Yuval * don't forget MFW accounts for the default SB as well.
2047ebbdcc66SMintz, Yuval */
2048ebbdcc66SMintz, Yuval p_info->b_allow_pf_vf_change = true;
2049ebbdcc66SMintz, Yuval
2050ebbdcc66SMintz, Yuval if (p_info->usage.cnt != RESC_NUM(p_hwfn, QED_SB) - 1) {
2051ebbdcc66SMintz, Yuval DP_INFO(p_hwfn,
2052ebbdcc66SMintz, Yuval "MFW notifies of 0x%04x PF SBs; IGU indicates of only 0x%04x\n",
2053ebbdcc66SMintz, Yuval RESC_NUM(p_hwfn, QED_SB) - 1,
2054ebbdcc66SMintz, Yuval p_info->usage.cnt);
2055ebbdcc66SMintz, Yuval p_info->usage.cnt = RESC_NUM(p_hwfn, QED_SB) - 1;
2056ebbdcc66SMintz, Yuval }
2057ebbdcc66SMintz, Yuval
2058ebbdcc66SMintz, Yuval if (IS_PF_SRIOV(p_hwfn)) {
2059ebbdcc66SMintz, Yuval u16 vfs = p_hwfn->cdev->p_iov_info->total_vfs;
2060ebbdcc66SMintz, Yuval
2061ebbdcc66SMintz, Yuval if (vfs != p_info->usage.iov_cnt)
2062ebbdcc66SMintz, Yuval DP_VERBOSE(p_hwfn,
2063ebbdcc66SMintz, Yuval NETIF_MSG_INTR,
2064ebbdcc66SMintz, Yuval "0x%04x VF SBs in IGU CAM != PCI configuration 0x%04x\n",
2065ebbdcc66SMintz, Yuval p_info->usage.iov_cnt, vfs);
2066ebbdcc66SMintz, Yuval
2067ebbdcc66SMintz, Yuval /* At this point we know how many SBs we have totally
2068ebbdcc66SMintz, Yuval * in IGU + number of PF SBs. So we can validate that
2069ebbdcc66SMintz, Yuval * we'd have sufficient for VF.
2070ebbdcc66SMintz, Yuval */
2071ebbdcc66SMintz, Yuval if (vfs > p_info->usage.free_cnt +
2072ebbdcc66SMintz, Yuval p_info->usage.free_cnt_iov - p_info->usage.cnt) {
2073ebbdcc66SMintz, Yuval DP_NOTICE(p_hwfn,
2074ebbdcc66SMintz, Yuval "Not enough SBs for VFs - 0x%04x SBs, from which %04x PFs and %04x are required\n",
2075ebbdcc66SMintz, Yuval p_info->usage.free_cnt +
2076ebbdcc66SMintz, Yuval p_info->usage.free_cnt_iov,
2077ebbdcc66SMintz, Yuval p_info->usage.cnt, vfs);
2078ebbdcc66SMintz, Yuval return -EINVAL;
2079ebbdcc66SMintz, Yuval }
2080ebbdcc66SMintz, Yuval
2081ebbdcc66SMintz, Yuval /* Currently cap the number of VFs SBs by the
2082ebbdcc66SMintz, Yuval * number of VFs.
2083ebbdcc66SMintz, Yuval */
2084ebbdcc66SMintz, Yuval p_info->usage.iov_cnt = vfs;
2085ebbdcc66SMintz, Yuval }
2086ebbdcc66SMintz, Yuval }
2087ebbdcc66SMintz, Yuval
2088ebbdcc66SMintz, Yuval /* Mark all SBs as free, now in the right PF/VFs division */
2089ebbdcc66SMintz, Yuval p_info->usage.free_cnt = p_info->usage.cnt;
2090ebbdcc66SMintz, Yuval p_info->usage.free_cnt_iov = p_info->usage.iov_cnt;
2091ebbdcc66SMintz, Yuval p_info->usage.orig = p_info->usage.cnt;
2092ebbdcc66SMintz, Yuval p_info->usage.iov_orig = p_info->usage.iov_cnt;
2093ebbdcc66SMintz, Yuval
2094ebbdcc66SMintz, Yuval /* We now proceed to re-configure the IGU cam to reflect the initial
2095ebbdcc66SMintz, Yuval * configuration. We can start with the Default SB.
2096ebbdcc66SMintz, Yuval */
2097ebbdcc66SMintz, Yuval pf_sbs = p_info->usage.cnt;
2098ebbdcc66SMintz, Yuval vf_sbs = p_info->usage.iov_cnt;
2099ebbdcc66SMintz, Yuval
2100ebbdcc66SMintz, Yuval for (igu_sb_id = p_info->igu_dsb_id;
2101ebbdcc66SMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) {
2102ebbdcc66SMintz, Yuval p_block = &p_info->entry[igu_sb_id];
2103ebbdcc66SMintz, Yuval val = 0;
2104ebbdcc66SMintz, Yuval
2105ebbdcc66SMintz, Yuval if (!(p_block->status & QED_IGU_STATUS_VALID))
2106ebbdcc66SMintz, Yuval continue;
2107ebbdcc66SMintz, Yuval
2108ebbdcc66SMintz, Yuval if (p_block->status & QED_IGU_STATUS_DSB) {
2109ebbdcc66SMintz, Yuval p_block->function_id = p_hwfn->rel_pf_id;
2110ebbdcc66SMintz, Yuval p_block->is_pf = 1;
2111ebbdcc66SMintz, Yuval p_block->vector_number = 0;
2112ebbdcc66SMintz, Yuval p_block->status = QED_IGU_STATUS_VALID |
2113ebbdcc66SMintz, Yuval QED_IGU_STATUS_PF |
2114ebbdcc66SMintz, Yuval QED_IGU_STATUS_DSB;
2115ebbdcc66SMintz, Yuval } else if (pf_sbs) {
2116ebbdcc66SMintz, Yuval pf_sbs--;
2117ebbdcc66SMintz, Yuval p_block->function_id = p_hwfn->rel_pf_id;
2118ebbdcc66SMintz, Yuval p_block->is_pf = 1;
2119ebbdcc66SMintz, Yuval p_block->vector_number = p_info->usage.cnt - pf_sbs;
2120ebbdcc66SMintz, Yuval p_block->status = QED_IGU_STATUS_VALID |
2121ebbdcc66SMintz, Yuval QED_IGU_STATUS_PF |
2122ebbdcc66SMintz, Yuval QED_IGU_STATUS_FREE;
2123ebbdcc66SMintz, Yuval } else if (vf_sbs) {
2124ebbdcc66SMintz, Yuval p_block->function_id =
2125ebbdcc66SMintz, Yuval p_hwfn->cdev->p_iov_info->first_vf_in_pf +
2126ebbdcc66SMintz, Yuval p_info->usage.iov_cnt - vf_sbs;
2127ebbdcc66SMintz, Yuval p_block->is_pf = 0;
2128ebbdcc66SMintz, Yuval p_block->vector_number = 0;
2129ebbdcc66SMintz, Yuval p_block->status = QED_IGU_STATUS_VALID |
2130ebbdcc66SMintz, Yuval QED_IGU_STATUS_FREE;
2131ebbdcc66SMintz, Yuval vf_sbs--;
2132ebbdcc66SMintz, Yuval } else {
2133ebbdcc66SMintz, Yuval p_block->function_id = 0;
2134ebbdcc66SMintz, Yuval p_block->is_pf = 0;
2135ebbdcc66SMintz, Yuval p_block->vector_number = 0;
2136ebbdcc66SMintz, Yuval }
2137ebbdcc66SMintz, Yuval
2138ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER,
2139ebbdcc66SMintz, Yuval p_block->function_id);
2140ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_PF_VALID, p_block->is_pf);
2141ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER,
2142ebbdcc66SMintz, Yuval p_block->vector_number);
2143ebbdcc66SMintz, Yuval
2144ebbdcc66SMintz, Yuval /* VF entries would be enabled when VF is initializaed */
2145ebbdcc66SMintz, Yuval SET_FIELD(val, IGU_MAPPING_LINE_VALID, p_block->is_pf);
2146ebbdcc66SMintz, Yuval
2147ebbdcc66SMintz, Yuval rval = qed_rd(p_hwfn, p_ptt,
2148ebbdcc66SMintz, Yuval IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id);
2149ebbdcc66SMintz, Yuval
2150ebbdcc66SMintz, Yuval if (rval != val) {
2151ebbdcc66SMintz, Yuval qed_wr(p_hwfn, p_ptt,
2152ebbdcc66SMintz, Yuval IGU_REG_MAPPING_MEMORY +
2153ebbdcc66SMintz, Yuval sizeof(u32) * igu_sb_id, val);
2154ebbdcc66SMintz, Yuval
2155ebbdcc66SMintz, Yuval DP_VERBOSE(p_hwfn,
2156ebbdcc66SMintz, Yuval NETIF_MSG_INTR,
2157ebbdcc66SMintz, Yuval "IGU reset: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x [%08x -> %08x]\n",
2158ebbdcc66SMintz, Yuval igu_sb_id,
2159ebbdcc66SMintz, Yuval p_block->function_id,
2160ebbdcc66SMintz, Yuval p_block->is_pf,
2161ebbdcc66SMintz, Yuval p_block->vector_number, rval, val);
2162ebbdcc66SMintz, Yuval }
2163ebbdcc66SMintz, Yuval }
2164ebbdcc66SMintz, Yuval
2165ebbdcc66SMintz, Yuval return 0;
2166ebbdcc66SMintz, Yuval }
2167ebbdcc66SMintz, Yuval
qed_int_igu_read_cam_block(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,u16 igu_sb_id)2168d749dd0dSMintz, Yuval static void qed_int_igu_read_cam_block(struct qed_hwfn *p_hwfn,
2169d749dd0dSMintz, Yuval struct qed_ptt *p_ptt, u16 igu_sb_id)
21704ac801b7SYuval Mintz {
21714ac801b7SYuval Mintz u32 val = qed_rd(p_hwfn, p_ptt,
2172d749dd0dSMintz, Yuval IGU_REG_MAPPING_MEMORY + sizeof(u32) * igu_sb_id);
21734ac801b7SYuval Mintz struct qed_igu_block *p_block;
21744ac801b7SYuval Mintz
2175d749dd0dSMintz, Yuval p_block = &p_hwfn->hw_info.p_igu_info->entry[igu_sb_id];
21764ac801b7SYuval Mintz
21774ac801b7SYuval Mintz /* Fill the block information */
2178d749dd0dSMintz, Yuval p_block->function_id = GET_FIELD(val, IGU_MAPPING_LINE_FUNCTION_NUMBER);
21794ac801b7SYuval Mintz p_block->is_pf = GET_FIELD(val, IGU_MAPPING_LINE_PF_VALID);
2180d749dd0dSMintz, Yuval p_block->vector_number = GET_FIELD(val, IGU_MAPPING_LINE_VECTOR_NUMBER);
21811ac72433SMintz, Yuval p_block->igu_sb_id = igu_sb_id;
21824ac801b7SYuval Mintz }
21834ac801b7SYuval Mintz
qed_int_igu_read_cam(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt)21841a635e48SYuval Mintz int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2185fe56b9e6SYuval Mintz {
2186fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info;
2187d749dd0dSMintz, Yuval struct qed_igu_block *p_block;
2188d749dd0dSMintz, Yuval u32 min_vf = 0, max_vf = 0;
2189d749dd0dSMintz, Yuval u16 igu_sb_id;
2190fe56b9e6SYuval Mintz
219160fffb3bSYuval Mintz p_hwfn->hw_info.p_igu_info = kzalloc(sizeof(*p_igu_info), GFP_KERNEL);
2192fe56b9e6SYuval Mintz if (!p_hwfn->hw_info.p_igu_info)
2193fe56b9e6SYuval Mintz return -ENOMEM;
2194fe56b9e6SYuval Mintz
2195fe56b9e6SYuval Mintz p_igu_info = p_hwfn->hw_info.p_igu_info;
2196fe56b9e6SYuval Mintz
2197d749dd0dSMintz, Yuval /* Distinguish between existent and non-existent default SB */
2198d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id = QED_SB_INVALID_IDX;
2199d749dd0dSMintz, Yuval
2200d749dd0dSMintz, Yuval /* Find the range of VF ids whose SB belong to this PF */
22011408cc1fSYuval Mintz if (p_hwfn->cdev->p_iov_info) {
22021408cc1fSYuval Mintz struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info;
22031408cc1fSYuval Mintz
22041408cc1fSYuval Mintz min_vf = p_iov->first_vf_in_pf;
22051408cc1fSYuval Mintz max_vf = p_iov->first_vf_in_pf + p_iov->total_vfs;
22061408cc1fSYuval Mintz }
22071408cc1fSYuval Mintz
2208d749dd0dSMintz, Yuval for (igu_sb_id = 0;
2209d749dd0dSMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(p_hwfn->cdev); igu_sb_id++) {
2210d749dd0dSMintz, Yuval /* Read current entry; Notice it might not belong to this PF */
2211d749dd0dSMintz, Yuval qed_int_igu_read_cam_block(p_hwfn, p_ptt, igu_sb_id);
2212d749dd0dSMintz, Yuval p_block = &p_igu_info->entry[igu_sb_id];
2213fe56b9e6SYuval Mintz
2214d749dd0dSMintz, Yuval if ((p_block->is_pf) &&
2215d749dd0dSMintz, Yuval (p_block->function_id == p_hwfn->rel_pf_id)) {
2216d749dd0dSMintz, Yuval p_block->status = QED_IGU_STATUS_PF |
2217d749dd0dSMintz, Yuval QED_IGU_STATUS_VALID |
2218d749dd0dSMintz, Yuval QED_IGU_STATUS_FREE;
2219fe56b9e6SYuval Mintz
22201ac72433SMintz, Yuval if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX)
2221726fdbe9SMintz, Yuval p_igu_info->usage.cnt++;
2222d749dd0dSMintz, Yuval } else if (!(p_block->is_pf) &&
2223d749dd0dSMintz, Yuval (p_block->function_id >= min_vf) &&
2224d749dd0dSMintz, Yuval (p_block->function_id < max_vf)) {
22251408cc1fSYuval Mintz /* Available for VFs of this PF */
2226d749dd0dSMintz, Yuval p_block->status = QED_IGU_STATUS_VALID |
2227d749dd0dSMintz, Yuval QED_IGU_STATUS_FREE;
2228d749dd0dSMintz, Yuval
22291ac72433SMintz, Yuval if (p_igu_info->igu_dsb_id != QED_SB_INVALID_IDX)
2230726fdbe9SMintz, Yuval p_igu_info->usage.iov_cnt++;
22311408cc1fSYuval Mintz }
22325a1f965aSMintz, Yuval
2233d749dd0dSMintz, Yuval /* Mark the First entry belonging to the PF or its VFs
2234ebbdcc66SMintz, Yuval * as the default SB [we'll reset IGU prior to first usage].
22355a1f965aSMintz, Yuval */
2236d749dd0dSMintz, Yuval if ((p_block->status & QED_IGU_STATUS_VALID) &&
2237d749dd0dSMintz, Yuval (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX)) {
2238d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id = igu_sb_id;
2239d749dd0dSMintz, Yuval p_block->status |= QED_IGU_STATUS_DSB;
2240d749dd0dSMintz, Yuval }
22415a1f965aSMintz, Yuval
2242d749dd0dSMintz, Yuval /* limit number of prints by having each PF print only its
2243d749dd0dSMintz, Yuval * entries with the exception of PF0 which would print
2244d749dd0dSMintz, Yuval * everything.
2245d749dd0dSMintz, Yuval */
2246d749dd0dSMintz, Yuval if ((p_block->status & QED_IGU_STATUS_VALID) ||
2247d749dd0dSMintz, Yuval (p_hwfn->abs_pf_id == 0)) {
2248d749dd0dSMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
2249d749dd0dSMintz, Yuval "IGU_BLOCK: [SB 0x%04x] func_id = %d is_pf = %d vector_num = 0x%x\n",
2250d749dd0dSMintz, Yuval igu_sb_id, p_block->function_id,
2251d749dd0dSMintz, Yuval p_block->is_pf, p_block->vector_number);
2252d749dd0dSMintz, Yuval }
2253d749dd0dSMintz, Yuval }
2254d749dd0dSMintz, Yuval
2255d749dd0dSMintz, Yuval if (p_igu_info->igu_dsb_id == QED_SB_INVALID_IDX) {
22565a1f965aSMintz, Yuval DP_NOTICE(p_hwfn,
2257d749dd0dSMintz, Yuval "IGU CAM returned invalid values igu_dsb_id=0x%x\n",
2258d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id);
22595a1f965aSMintz, Yuval return -EINVAL;
22605a1f965aSMintz, Yuval }
2261d749dd0dSMintz, Yuval
2262d749dd0dSMintz, Yuval /* All non default SB are considered free at this point */
2263726fdbe9SMintz, Yuval p_igu_info->usage.free_cnt = p_igu_info->usage.cnt;
2264726fdbe9SMintz, Yuval p_igu_info->usage.free_cnt_iov = p_igu_info->usage.iov_cnt;
2265fe56b9e6SYuval Mintz
2266d749dd0dSMintz, Yuval DP_VERBOSE(p_hwfn, NETIF_MSG_INTR,
2267ebbdcc66SMintz, Yuval "igu_dsb_id=0x%x, num Free SBs - PF: %04x VF: %04x [might change after resource allocation]\n",
2268d749dd0dSMintz, Yuval p_igu_info->igu_dsb_id,
2269726fdbe9SMintz, Yuval p_igu_info->usage.cnt, p_igu_info->usage.iov_cnt);
2270fe56b9e6SYuval Mintz
2271fe56b9e6SYuval Mintz return 0;
2272fe56b9e6SYuval Mintz }
2273fe56b9e6SYuval Mintz
2274fe56b9e6SYuval Mintz /**
227571e11a3fSAlexander Lobakin * qed_int_igu_init_rt() - Initialize IGU runtime registers.
2276fe56b9e6SYuval Mintz *
227771e11a3fSAlexander Lobakin * @p_hwfn: HW device data.
2278fe56b9e6SYuval Mintz */
qed_int_igu_init_rt(struct qed_hwfn * p_hwfn)2279fe56b9e6SYuval Mintz void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn)
2280fe56b9e6SYuval Mintz {
22811a635e48SYuval Mintz u32 igu_pf_conf = IGU_PF_CONF_FUNC_EN;
2282fe56b9e6SYuval Mintz
2283fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf);
2284fe56b9e6SYuval Mintz }
2285fe56b9e6SYuval Mintz
qed_int_igu_read_sisr_reg(struct qed_hwfn * p_hwfn)2286fe56b9e6SYuval Mintz u64 qed_int_igu_read_sisr_reg(struct qed_hwfn *p_hwfn)
2287fe56b9e6SYuval Mintz {
2288fe56b9e6SYuval Mintz u32 lsb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_LSB_UPPER -
2289fe56b9e6SYuval Mintz IGU_CMD_INT_ACK_BASE;
2290fe56b9e6SYuval Mintz u32 msb_igu_cmd_addr = IGU_REG_SISR_MDPC_WMASK_MSB_UPPER -
2291fe56b9e6SYuval Mintz IGU_CMD_INT_ACK_BASE;
22921a635e48SYuval Mintz u32 intr_status_hi = 0, intr_status_lo = 0;
22931a635e48SYuval Mintz u64 intr_status = 0;
2294fe56b9e6SYuval Mintz
2295fe56b9e6SYuval Mintz intr_status_lo = REG_RD(p_hwfn,
2296fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD +
2297fe56b9e6SYuval Mintz lsb_igu_cmd_addr * 8);
2298fe56b9e6SYuval Mintz intr_status_hi = REG_RD(p_hwfn,
2299fe56b9e6SYuval Mintz GTT_BAR0_MAP_REG_IGU_CMD +
2300fe56b9e6SYuval Mintz msb_igu_cmd_addr * 8);
2301fe56b9e6SYuval Mintz intr_status = ((u64)intr_status_hi << 32) + (u64)intr_status_lo;
2302fe56b9e6SYuval Mintz
2303fe56b9e6SYuval Mintz return intr_status;
2304fe56b9e6SYuval Mintz }
2305fe56b9e6SYuval Mintz
qed_int_sp_dpc_setup(struct qed_hwfn * p_hwfn)2306fe56b9e6SYuval Mintz static void qed_int_sp_dpc_setup(struct qed_hwfn *p_hwfn)
2307fe56b9e6SYuval Mintz {
2308b5f0a3bfSAllen Pais tasklet_setup(&p_hwfn->sp_dpc, qed_int_sp_dpc);
2309fe56b9e6SYuval Mintz p_hwfn->b_sp_dpc_enabled = true;
2310fe56b9e6SYuval Mintz }
2311fe56b9e6SYuval Mintz
qed_int_alloc(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt)23121a635e48SYuval Mintz int qed_int_alloc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2313fe56b9e6SYuval Mintz {
2314fe56b9e6SYuval Mintz int rc = 0;
2315fe56b9e6SYuval Mintz
23162591c280SJoe Perches rc = qed_int_sp_sb_alloc(p_hwfn, p_ptt);
23172591c280SJoe Perches if (rc)
23182591c280SJoe Perches return rc;
23192591c280SJoe Perches
23202591c280SJoe Perches rc = qed_int_sb_attn_alloc(p_hwfn, p_ptt);
232183aeb933SYuval Mintz
2322fe56b9e6SYuval Mintz return rc;
2323fe56b9e6SYuval Mintz }
2324fe56b9e6SYuval Mintz
qed_int_free(struct qed_hwfn * p_hwfn)2325fe56b9e6SYuval Mintz void qed_int_free(struct qed_hwfn *p_hwfn)
2326fe56b9e6SYuval Mintz {
2327fe56b9e6SYuval Mintz qed_int_sp_sb_free(p_hwfn);
2328cc875c2eSYuval Mintz qed_int_sb_attn_free(p_hwfn);
2329fe56b9e6SYuval Mintz }
2330fe56b9e6SYuval Mintz
qed_int_setup(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt)23311a635e48SYuval Mintz void qed_int_setup(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2332fe56b9e6SYuval Mintz {
23330d956e8aSYuval Mintz qed_int_sb_setup(p_hwfn, p_ptt, &p_hwfn->p_sp_sb->sb_info);
23340d956e8aSYuval Mintz qed_int_sb_attn_setup(p_hwfn, p_ptt);
2335fe56b9e6SYuval Mintz qed_int_sp_dpc_setup(p_hwfn);
2336fe56b9e6SYuval Mintz }
2337fe56b9e6SYuval Mintz
qed_int_get_num_sbs(struct qed_hwfn * p_hwfn,struct qed_sb_cnt_info * p_sb_cnt_info)23384ac801b7SYuval Mintz void qed_int_get_num_sbs(struct qed_hwfn *p_hwfn,
23394ac801b7SYuval Mintz struct qed_sb_cnt_info *p_sb_cnt_info)
2340fe56b9e6SYuval Mintz {
2341fe56b9e6SYuval Mintz struct qed_igu_info *info = p_hwfn->hw_info.p_igu_info;
2342fe56b9e6SYuval Mintz
23434ac801b7SYuval Mintz if (!info || !p_sb_cnt_info)
23444ac801b7SYuval Mintz return;
2345fe56b9e6SYuval Mintz
2346726fdbe9SMintz, Yuval memcpy(p_sb_cnt_info, &info->usage, sizeof(*p_sb_cnt_info));
2347fe56b9e6SYuval Mintz }
23488f16bc97SSudarsana Kalluru
qed_int_disable_post_isr_release(struct qed_dev * cdev)23498f16bc97SSudarsana Kalluru void qed_int_disable_post_isr_release(struct qed_dev *cdev)
23508f16bc97SSudarsana Kalluru {
23518f16bc97SSudarsana Kalluru int i;
23528f16bc97SSudarsana Kalluru
23538f16bc97SSudarsana Kalluru for_each_hwfn(cdev, i)
23548f16bc97SSudarsana Kalluru cdev->hwfns[i].b_int_requested = false;
23558f16bc97SSudarsana Kalluru }
2356722003acSSudarsana Reddy Kalluru
qed_int_attn_clr_enable(struct qed_dev * cdev,bool clr_enable)2357936c7ba4SIgor Russkikh void qed_int_attn_clr_enable(struct qed_dev *cdev, bool clr_enable)
2358936c7ba4SIgor Russkikh {
2359936c7ba4SIgor Russkikh cdev->attn_clr_en = clr_enable;
2360936c7ba4SIgor Russkikh }
2361936c7ba4SIgor Russkikh
qed_int_set_timer_res(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,u8 timer_res,u16 sb_id,bool tx)2362722003acSSudarsana Reddy Kalluru int qed_int_set_timer_res(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
2363722003acSSudarsana Reddy Kalluru u8 timer_res, u16 sb_id, bool tx)
2364722003acSSudarsana Reddy Kalluru {
2365722003acSSudarsana Reddy Kalluru struct cau_sb_entry sb_entry;
23665ab90341SAlexander Lobakin u32 params;
2367722003acSSudarsana Reddy Kalluru int rc;
2368722003acSSudarsana Reddy Kalluru
2369722003acSSudarsana Reddy Kalluru if (!p_hwfn->hw_init_done) {
2370722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "hardware not initialized yet\n");
2371722003acSSudarsana Reddy Kalluru return -EINVAL;
2372722003acSSudarsana Reddy Kalluru }
2373722003acSSudarsana Reddy Kalluru
2374722003acSSudarsana Reddy Kalluru rc = qed_dmae_grc2host(p_hwfn, p_ptt, CAU_REG_SB_VAR_MEMORY +
2375722003acSSudarsana Reddy Kalluru sb_id * sizeof(u64),
237683bf76e3SMichal Kalderon (u64)(uintptr_t)&sb_entry, 2, NULL);
2377722003acSSudarsana Reddy Kalluru if (rc) {
2378722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "dmae_grc2host failed %d\n", rc);
2379722003acSSudarsana Reddy Kalluru return rc;
2380722003acSSudarsana Reddy Kalluru }
2381722003acSSudarsana Reddy Kalluru
23825ab90341SAlexander Lobakin params = le32_to_cpu(sb_entry.params);
23835ab90341SAlexander Lobakin
2384722003acSSudarsana Reddy Kalluru if (tx)
23855ab90341SAlexander Lobakin SET_FIELD(params, CAU_SB_ENTRY_TIMER_RES1, timer_res);
2386722003acSSudarsana Reddy Kalluru else
23875ab90341SAlexander Lobakin SET_FIELD(params, CAU_SB_ENTRY_TIMER_RES0, timer_res);
23885ab90341SAlexander Lobakin
23895ab90341SAlexander Lobakin sb_entry.params = cpu_to_le32(params);
2390722003acSSudarsana Reddy Kalluru
2391722003acSSudarsana Reddy Kalluru rc = qed_dmae_host2grc(p_hwfn, p_ptt,
2392722003acSSudarsana Reddy Kalluru (u64)(uintptr_t)&sb_entry,
2393722003acSSudarsana Reddy Kalluru CAU_REG_SB_VAR_MEMORY +
239483bf76e3SMichal Kalderon sb_id * sizeof(u64), 2, NULL);
2395722003acSSudarsana Reddy Kalluru if (rc) {
2396722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "dmae_host2grc failed %d\n", rc);
2397722003acSSudarsana Reddy Kalluru return rc;
2398722003acSSudarsana Reddy Kalluru }
2399722003acSSudarsana Reddy Kalluru
2400722003acSSudarsana Reddy Kalluru return rc;
2401722003acSSudarsana Reddy Kalluru }
24020cc3a801SManish Chopra
qed_int_get_sb_dbg(struct qed_hwfn * p_hwfn,struct qed_ptt * p_ptt,struct qed_sb_info * p_sb,struct qed_sb_info_dbg * p_info)24030cc3a801SManish Chopra int qed_int_get_sb_dbg(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt,
24040cc3a801SManish Chopra struct qed_sb_info *p_sb, struct qed_sb_info_dbg *p_info)
24050cc3a801SManish Chopra {
24060cc3a801SManish Chopra u16 sbid = p_sb->igu_sb_id;
24070cc3a801SManish Chopra u32 i;
24080cc3a801SManish Chopra
24090cc3a801SManish Chopra if (IS_VF(p_hwfn->cdev))
24100cc3a801SManish Chopra return -EINVAL;
24110cc3a801SManish Chopra
24120cc3a801SManish Chopra if (sbid >= NUM_OF_SBS(p_hwfn->cdev))
24130cc3a801SManish Chopra return -EINVAL;
24140cc3a801SManish Chopra
24150cc3a801SManish Chopra p_info->igu_prod = qed_rd(p_hwfn, p_ptt, IGU_REG_PRODUCER_MEMORY + sbid * 4);
24160cc3a801SManish Chopra p_info->igu_cons = qed_rd(p_hwfn, p_ptt, IGU_REG_CONSUMER_MEM + sbid * 4);
24170cc3a801SManish Chopra
24180cc3a801SManish Chopra for (i = 0; i < PIS_PER_SB; i++)
24190cc3a801SManish Chopra p_info->pi[i] = (u16)qed_rd(p_hwfn, p_ptt,
24200cc3a801SManish Chopra CAU_REG_PI_MEMORY + sbid * 4 * PIS_PER_SB + i * 4);
24210cc3a801SManish Chopra
24220cc3a801SManish Chopra return 0;
24230cc3a801SManish Chopra }
2424