1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015 QLogic Corporation 3 * 4 * This software is available under the terms of the GNU General Public License 5 * (GPL) Version 2, available from the file COPYING in the main directory of 6 * this source tree. 7 */ 8 9 #include <linux/types.h> 10 #include <linux/io.h> 11 #include <linux/delay.h> 12 #include <linux/errno.h> 13 #include <linux/kernel.h> 14 #include <linux/slab.h> 15 #include <linux/string.h> 16 #include "qed.h" 17 #include "qed_hsi.h" 18 #include "qed_hw.h" 19 #include "qed_init_ops.h" 20 #include "qed_reg_addr.h" 21 #include "qed_sriov.h" 22 23 #define QED_INIT_MAX_POLL_COUNT 100 24 #define QED_INIT_POLL_PERIOD_US 500 25 26 static u32 pxp_global_win[] = { 27 0, 28 0, 29 0x1c02, /* win 2: addr=0x1c02000, size=4096 bytes */ 30 0x1c80, /* win 3: addr=0x1c80000, size=4096 bytes */ 31 0x1d00, /* win 4: addr=0x1d00000, size=4096 bytes */ 32 0x1d01, /* win 5: addr=0x1d01000, size=4096 bytes */ 33 0x1d80, /* win 6: addr=0x1d80000, size=4096 bytes */ 34 0x1d81, /* win 7: addr=0x1d81000, size=4096 bytes */ 35 0x1d82, /* win 8: addr=0x1d82000, size=4096 bytes */ 36 0x1e00, /* win 9: addr=0x1e00000, size=4096 bytes */ 37 0x1e80, /* win 10: addr=0x1e80000, size=4096 bytes */ 38 0x1f00, /* win 11: addr=0x1f00000, size=4096 bytes */ 39 0, 40 0, 41 0, 42 0, 43 0, 44 0, 45 0, 46 }; 47 48 void qed_init_iro_array(struct qed_dev *cdev) 49 { 50 cdev->iro_arr = iro_arr; 51 } 52 53 /* Runtime configuration helpers */ 54 void qed_init_clear_rt_data(struct qed_hwfn *p_hwfn) 55 { 56 int i; 57 58 for (i = 0; i < RUNTIME_ARRAY_SIZE; i++) 59 p_hwfn->rt_data.b_valid[i] = false; 60 } 61 62 void qed_init_store_rt_reg(struct qed_hwfn *p_hwfn, 63 u32 rt_offset, 64 u32 val) 65 { 66 p_hwfn->rt_data.init_val[rt_offset] = val; 67 p_hwfn->rt_data.b_valid[rt_offset] = true; 68 } 69 70 void qed_init_store_rt_agg(struct qed_hwfn *p_hwfn, 71 u32 rt_offset, u32 *p_val, 72 size_t size) 73 { 74 size_t i; 75 76 for (i = 0; i < size / sizeof(u32); i++) { 77 p_hwfn->rt_data.init_val[rt_offset + i] = p_val[i]; 78 p_hwfn->rt_data.b_valid[rt_offset + i] = true; 79 } 80 } 81 82 static int qed_init_rt(struct qed_hwfn *p_hwfn, 83 struct qed_ptt *p_ptt, 84 u32 addr, 85 u16 rt_offset, 86 u16 size, 87 bool b_must_dmae) 88 { 89 u32 *p_init_val = &p_hwfn->rt_data.init_val[rt_offset]; 90 bool *p_valid = &p_hwfn->rt_data.b_valid[rt_offset]; 91 u16 i, segment; 92 int rc = 0; 93 94 /* Since not all RT entries are initialized, go over the RT and 95 * for each segment of initialized values use DMA. 96 */ 97 for (i = 0; i < size; i++) { 98 if (!p_valid[i]) 99 continue; 100 101 /* In case there isn't any wide-bus configuration here, 102 * simply write the data instead of using dmae. 103 */ 104 if (!b_must_dmae) { 105 qed_wr(p_hwfn, p_ptt, addr + (i << 2), 106 p_init_val[i]); 107 continue; 108 } 109 110 /* Start of a new segment */ 111 for (segment = 1; i + segment < size; segment++) 112 if (!p_valid[i + segment]) 113 break; 114 115 rc = qed_dmae_host2grc(p_hwfn, p_ptt, 116 (uintptr_t)(p_init_val + i), 117 addr + (i << 2), segment, 0); 118 if (rc != 0) 119 return rc; 120 121 /* Jump over the entire segment, including invalid entry */ 122 i += segment; 123 } 124 125 return rc; 126 } 127 128 int qed_init_alloc(struct qed_hwfn *p_hwfn) 129 { 130 struct qed_rt_data *rt_data = &p_hwfn->rt_data; 131 132 if (IS_VF(p_hwfn->cdev)) 133 return 0; 134 135 rt_data->b_valid = kzalloc(sizeof(bool) * RUNTIME_ARRAY_SIZE, 136 GFP_KERNEL); 137 if (!rt_data->b_valid) 138 return -ENOMEM; 139 140 rt_data->init_val = kzalloc(sizeof(u32) * RUNTIME_ARRAY_SIZE, 141 GFP_KERNEL); 142 if (!rt_data->init_val) { 143 kfree(rt_data->b_valid); 144 return -ENOMEM; 145 } 146 147 return 0; 148 } 149 150 void qed_init_free(struct qed_hwfn *p_hwfn) 151 { 152 kfree(p_hwfn->rt_data.init_val); 153 kfree(p_hwfn->rt_data.b_valid); 154 } 155 156 static int qed_init_array_dmae(struct qed_hwfn *p_hwfn, 157 struct qed_ptt *p_ptt, 158 u32 addr, 159 u32 dmae_data_offset, 160 u32 size, 161 const u32 *buf, 162 bool b_must_dmae, 163 bool b_can_dmae) 164 { 165 int rc = 0; 166 167 /* Perform DMAE only for lengthy enough sections or for wide-bus */ 168 if (!b_can_dmae || (!b_must_dmae && (size < 16))) { 169 const u32 *data = buf + dmae_data_offset; 170 u32 i; 171 172 for (i = 0; i < size; i++) 173 qed_wr(p_hwfn, p_ptt, addr + (i << 2), data[i]); 174 } else { 175 rc = qed_dmae_host2grc(p_hwfn, p_ptt, 176 (uintptr_t)(buf + dmae_data_offset), 177 addr, size, 0); 178 } 179 180 return rc; 181 } 182 183 static int qed_init_fill_dmae(struct qed_hwfn *p_hwfn, 184 struct qed_ptt *p_ptt, 185 u32 addr, 186 u32 fill, 187 u32 fill_count) 188 { 189 static u32 zero_buffer[DMAE_MAX_RW_SIZE]; 190 191 memset(zero_buffer, 0, sizeof(u32) * DMAE_MAX_RW_SIZE); 192 193 /* invoke the DMAE virtual/physical buffer API with 194 * 1. DMAE init channel 195 * 2. addr, 196 * 3. p_hwfb->temp_data, 197 * 4. fill_count 198 */ 199 200 return qed_dmae_host2grc(p_hwfn, p_ptt, 201 (uintptr_t)(&zero_buffer[0]), 202 addr, fill_count, 203 QED_DMAE_FLAG_RW_REPL_SRC); 204 } 205 206 static void qed_init_fill(struct qed_hwfn *p_hwfn, 207 struct qed_ptt *p_ptt, 208 u32 addr, 209 u32 fill, 210 u32 fill_count) 211 { 212 u32 i; 213 214 for (i = 0; i < fill_count; i++, addr += sizeof(u32)) 215 qed_wr(p_hwfn, p_ptt, addr, fill); 216 } 217 218 static int qed_init_cmd_array(struct qed_hwfn *p_hwfn, 219 struct qed_ptt *p_ptt, 220 struct init_write_op *cmd, 221 bool b_must_dmae, 222 bool b_can_dmae) 223 { 224 u32 data = le32_to_cpu(cmd->data); 225 u32 addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2; 226 u32 dmae_array_offset = le32_to_cpu(cmd->args.array_offset); 227 u32 offset, output_len, input_len, max_size; 228 struct qed_dev *cdev = p_hwfn->cdev; 229 union init_array_hdr *hdr; 230 const u32 *array_data; 231 int rc = 0; 232 u32 size; 233 234 array_data = cdev->fw_data->arr_data; 235 236 hdr = (union init_array_hdr *)(array_data + 237 dmae_array_offset); 238 data = le32_to_cpu(hdr->raw.data); 239 switch (GET_FIELD(data, INIT_ARRAY_RAW_HDR_TYPE)) { 240 case INIT_ARR_ZIPPED: 241 offset = dmae_array_offset + 1; 242 input_len = GET_FIELD(data, 243 INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE); 244 max_size = MAX_ZIPPED_SIZE * 4; 245 memset(p_hwfn->unzip_buf, 0, max_size); 246 247 output_len = qed_unzip_data(p_hwfn, input_len, 248 (u8 *)&array_data[offset], 249 max_size, (u8 *)p_hwfn->unzip_buf); 250 if (output_len) { 251 rc = qed_init_array_dmae(p_hwfn, p_ptt, addr, 0, 252 output_len, 253 p_hwfn->unzip_buf, 254 b_must_dmae, b_can_dmae); 255 } else { 256 DP_NOTICE(p_hwfn, "Failed to unzip dmae data\n"); 257 rc = -EINVAL; 258 } 259 break; 260 case INIT_ARR_PATTERN: 261 { 262 u32 repeats = GET_FIELD(data, 263 INIT_ARRAY_PATTERN_HDR_REPETITIONS); 264 u32 i; 265 266 size = GET_FIELD(data, INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE); 267 268 for (i = 0; i < repeats; i++, addr += size << 2) { 269 rc = qed_init_array_dmae(p_hwfn, p_ptt, addr, 270 dmae_array_offset + 1, 271 size, array_data, 272 b_must_dmae, b_can_dmae); 273 if (rc) 274 break; 275 } 276 break; 277 } 278 case INIT_ARR_STANDARD: 279 size = GET_FIELD(data, INIT_ARRAY_STANDARD_HDR_SIZE); 280 rc = qed_init_array_dmae(p_hwfn, p_ptt, addr, 281 dmae_array_offset + 1, 282 size, array_data, 283 b_must_dmae, b_can_dmae); 284 break; 285 } 286 287 return rc; 288 } 289 290 /* init_ops write command */ 291 static int qed_init_cmd_wr(struct qed_hwfn *p_hwfn, 292 struct qed_ptt *p_ptt, 293 struct init_write_op *cmd, 294 bool b_can_dmae) 295 { 296 u32 data = le32_to_cpu(cmd->data); 297 u32 addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2; 298 bool b_must_dmae = GET_FIELD(data, INIT_WRITE_OP_WIDE_BUS); 299 union init_write_args *arg = &cmd->args; 300 int rc = 0; 301 302 /* Sanitize */ 303 if (b_must_dmae && !b_can_dmae) { 304 DP_NOTICE(p_hwfn, 305 "Need to write to %08x for Wide-bus but DMAE isn't allowed\n", 306 addr); 307 return -EINVAL; 308 } 309 310 switch (GET_FIELD(data, INIT_WRITE_OP_SOURCE)) { 311 case INIT_SRC_INLINE: 312 qed_wr(p_hwfn, p_ptt, addr, 313 le32_to_cpu(arg->inline_val)); 314 break; 315 case INIT_SRC_ZEROS: 316 if (b_must_dmae || 317 (b_can_dmae && (le32_to_cpu(arg->zeros_count) >= 64))) 318 rc = qed_init_fill_dmae(p_hwfn, p_ptt, addr, 0, 319 le32_to_cpu(arg->zeros_count)); 320 else 321 qed_init_fill(p_hwfn, p_ptt, addr, 0, 322 le32_to_cpu(arg->zeros_count)); 323 break; 324 case INIT_SRC_ARRAY: 325 rc = qed_init_cmd_array(p_hwfn, p_ptt, cmd, 326 b_must_dmae, b_can_dmae); 327 break; 328 case INIT_SRC_RUNTIME: 329 qed_init_rt(p_hwfn, p_ptt, addr, 330 le16_to_cpu(arg->runtime.offset), 331 le16_to_cpu(arg->runtime.size), 332 b_must_dmae); 333 break; 334 } 335 336 return rc; 337 } 338 339 static inline bool comp_eq(u32 val, u32 expected_val) 340 { 341 return val == expected_val; 342 } 343 344 static inline bool comp_and(u32 val, u32 expected_val) 345 { 346 return (val & expected_val) == expected_val; 347 } 348 349 static inline bool comp_or(u32 val, u32 expected_val) 350 { 351 return (val | expected_val) > 0; 352 } 353 354 /* init_ops read/poll commands */ 355 static void qed_init_cmd_rd(struct qed_hwfn *p_hwfn, 356 struct qed_ptt *p_ptt, 357 struct init_read_op *cmd) 358 { 359 bool (*comp_check)(u32 val, u32 expected_val); 360 u32 delay = QED_INIT_POLL_PERIOD_US, val; 361 u32 data, addr, poll; 362 int i; 363 364 data = le32_to_cpu(cmd->op_data); 365 addr = GET_FIELD(data, INIT_READ_OP_ADDRESS) << 2; 366 poll = GET_FIELD(data, INIT_READ_OP_POLL_TYPE); 367 368 369 val = qed_rd(p_hwfn, p_ptt, addr); 370 371 if (poll == INIT_POLL_NONE) 372 return; 373 374 switch (poll) { 375 case INIT_POLL_EQ: 376 comp_check = comp_eq; 377 break; 378 case INIT_POLL_OR: 379 comp_check = comp_or; 380 break; 381 case INIT_POLL_AND: 382 comp_check = comp_and; 383 break; 384 default: 385 DP_ERR(p_hwfn, "Invalid poll comparison type %08x\n", 386 cmd->op_data); 387 return; 388 } 389 390 data = le32_to_cpu(cmd->expected_val); 391 for (i = 0; 392 i < QED_INIT_MAX_POLL_COUNT && !comp_check(val, data); 393 i++) { 394 udelay(delay); 395 val = qed_rd(p_hwfn, p_ptt, addr); 396 } 397 398 if (i == QED_INIT_MAX_POLL_COUNT) { 399 DP_ERR(p_hwfn, 400 "Timeout when polling reg: 0x%08x [ Waiting-for: %08x Got: %08x (comparsion %08x)]\n", 401 addr, le32_to_cpu(cmd->expected_val), 402 val, le32_to_cpu(cmd->op_data)); 403 } 404 } 405 406 /* init_ops callbacks entry point */ 407 static void qed_init_cmd_cb(struct qed_hwfn *p_hwfn, 408 struct qed_ptt *p_ptt, 409 struct init_callback_op *p_cmd) 410 { 411 DP_NOTICE(p_hwfn, "Currently init values have no need of callbacks\n"); 412 } 413 414 static u8 qed_init_cmd_mode_match(struct qed_hwfn *p_hwfn, 415 u16 *offset, 416 int modes) 417 { 418 struct qed_dev *cdev = p_hwfn->cdev; 419 const u8 *modes_tree_buf; 420 u8 arg1, arg2, tree_val; 421 422 modes_tree_buf = cdev->fw_data->modes_tree_buf; 423 tree_val = modes_tree_buf[(*offset)++]; 424 switch (tree_val) { 425 case INIT_MODE_OP_NOT: 426 return qed_init_cmd_mode_match(p_hwfn, offset, modes) ^ 1; 427 case INIT_MODE_OP_OR: 428 arg1 = qed_init_cmd_mode_match(p_hwfn, offset, modes); 429 arg2 = qed_init_cmd_mode_match(p_hwfn, offset, modes); 430 return arg1 | arg2; 431 case INIT_MODE_OP_AND: 432 arg1 = qed_init_cmd_mode_match(p_hwfn, offset, modes); 433 arg2 = qed_init_cmd_mode_match(p_hwfn, offset, modes); 434 return arg1 & arg2; 435 default: 436 tree_val -= MAX_INIT_MODE_OPS; 437 return (modes & (1 << tree_val)) ? 1 : 0; 438 } 439 } 440 441 static u32 qed_init_cmd_mode(struct qed_hwfn *p_hwfn, 442 struct init_if_mode_op *p_cmd, 443 int modes) 444 { 445 u16 offset = le16_to_cpu(p_cmd->modes_buf_offset); 446 447 if (qed_init_cmd_mode_match(p_hwfn, &offset, modes)) 448 return 0; 449 else 450 return GET_FIELD(le32_to_cpu(p_cmd->op_data), 451 INIT_IF_MODE_OP_CMD_OFFSET); 452 } 453 454 static u32 qed_init_cmd_phase(struct qed_hwfn *p_hwfn, 455 struct init_if_phase_op *p_cmd, 456 u32 phase, 457 u32 phase_id) 458 { 459 u32 data = le32_to_cpu(p_cmd->phase_data); 460 u32 op_data = le32_to_cpu(p_cmd->op_data); 461 462 if (!(GET_FIELD(data, INIT_IF_PHASE_OP_PHASE) == phase && 463 (GET_FIELD(data, INIT_IF_PHASE_OP_PHASE_ID) == ANY_PHASE_ID || 464 GET_FIELD(data, INIT_IF_PHASE_OP_PHASE_ID) == phase_id))) 465 return GET_FIELD(op_data, INIT_IF_PHASE_OP_CMD_OFFSET); 466 else 467 return 0; 468 } 469 470 int qed_init_run(struct qed_hwfn *p_hwfn, 471 struct qed_ptt *p_ptt, 472 int phase, 473 int phase_id, 474 int modes) 475 { 476 struct qed_dev *cdev = p_hwfn->cdev; 477 u32 cmd_num, num_init_ops; 478 union init_op *init_ops; 479 bool b_dmae = false; 480 int rc = 0; 481 482 num_init_ops = cdev->fw_data->init_ops_size; 483 init_ops = cdev->fw_data->init_ops; 484 485 p_hwfn->unzip_buf = kzalloc(MAX_ZIPPED_SIZE * 4, GFP_ATOMIC); 486 if (!p_hwfn->unzip_buf) { 487 DP_NOTICE(p_hwfn, "Failed to allocate unzip buffer\n"); 488 return -ENOMEM; 489 } 490 491 for (cmd_num = 0; cmd_num < num_init_ops; cmd_num++) { 492 union init_op *cmd = &init_ops[cmd_num]; 493 u32 data = le32_to_cpu(cmd->raw.op_data); 494 495 switch (GET_FIELD(data, INIT_CALLBACK_OP_OP)) { 496 case INIT_OP_WRITE: 497 rc = qed_init_cmd_wr(p_hwfn, p_ptt, &cmd->write, 498 b_dmae); 499 break; 500 case INIT_OP_READ: 501 qed_init_cmd_rd(p_hwfn, p_ptt, &cmd->read); 502 break; 503 case INIT_OP_IF_MODE: 504 cmd_num += qed_init_cmd_mode(p_hwfn, &cmd->if_mode, 505 modes); 506 break; 507 case INIT_OP_IF_PHASE: 508 cmd_num += qed_init_cmd_phase(p_hwfn, &cmd->if_phase, 509 phase, phase_id); 510 b_dmae = GET_FIELD(data, INIT_IF_PHASE_OP_DMAE_ENABLE); 511 break; 512 case INIT_OP_DELAY: 513 /* qed_init_run is always invoked from 514 * sleep-able context 515 */ 516 udelay(le32_to_cpu(cmd->delay.delay)); 517 break; 518 519 case INIT_OP_CALLBACK: 520 qed_init_cmd_cb(p_hwfn, p_ptt, &cmd->callback); 521 break; 522 } 523 524 if (rc) 525 break; 526 } 527 528 kfree(p_hwfn->unzip_buf); 529 return rc; 530 } 531 532 void qed_gtt_init(struct qed_hwfn *p_hwfn) 533 { 534 u32 gtt_base; 535 u32 i; 536 537 /* Set the global windows */ 538 gtt_base = PXP_PF_WINDOW_ADMIN_START + PXP_PF_WINDOW_ADMIN_GLOBAL_START; 539 540 for (i = 0; i < ARRAY_SIZE(pxp_global_win); i++) 541 if (pxp_global_win[i]) 542 REG_WR(p_hwfn, gtt_base + i * PXP_GLOBAL_ENTRY_SIZE, 543 pxp_global_win[i]); 544 } 545 546 int qed_init_fw_data(struct qed_dev *cdev, 547 const u8 *data) 548 { 549 struct qed_fw_data *fw = cdev->fw_data; 550 struct bin_buffer_hdr *buf_hdr; 551 u32 offset, len; 552 553 if (!data) { 554 DP_NOTICE(cdev, "Invalid fw data\n"); 555 return -EINVAL; 556 } 557 558 buf_hdr = (struct bin_buffer_hdr *)data; 559 560 offset = buf_hdr[BIN_BUF_INIT_CMD].offset; 561 fw->init_ops = (union init_op *)(data + offset); 562 563 offset = buf_hdr[BIN_BUF_INIT_VAL].offset; 564 fw->arr_data = (u32 *)(data + offset); 565 566 offset = buf_hdr[BIN_BUF_INIT_MODE_TREE].offset; 567 fw->modes_tree_buf = (u8 *)(data + offset); 568 len = buf_hdr[BIN_BUF_INIT_CMD].length; 569 fw->init_ops_size = len / sizeof(struct init_raw_op); 570 571 return 0; 572 } 573