1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #include <linux/types.h> 34fe56b9e6SYuval Mintz #include <linux/io.h> 35fe56b9e6SYuval Mintz #include <linux/delay.h> 36fe56b9e6SYuval Mintz #include <linux/errno.h> 37fe56b9e6SYuval Mintz #include <linux/kernel.h> 38fe56b9e6SYuval Mintz #include <linux/slab.h> 39fe56b9e6SYuval Mintz #include <linux/string.h> 40fe56b9e6SYuval Mintz #include "qed.h" 41fe56b9e6SYuval Mintz #include "qed_hsi.h" 42fe56b9e6SYuval Mintz #include "qed_hw.h" 43fe56b9e6SYuval Mintz #include "qed_init_ops.h" 44fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 451408cc1fSYuval Mintz #include "qed_sriov.h" 46fe56b9e6SYuval Mintz 47fe56b9e6SYuval Mintz #define QED_INIT_MAX_POLL_COUNT 100 48fe56b9e6SYuval Mintz #define QED_INIT_POLL_PERIOD_US 500 49fe56b9e6SYuval Mintz 50fe56b9e6SYuval Mintz static u32 pxp_global_win[] = { 51fe56b9e6SYuval Mintz 0, 52fe56b9e6SYuval Mintz 0, 53fe56b9e6SYuval Mintz 0x1c02, /* win 2: addr=0x1c02000, size=4096 bytes */ 54fe56b9e6SYuval Mintz 0x1c80, /* win 3: addr=0x1c80000, size=4096 bytes */ 55fe56b9e6SYuval Mintz 0x1d00, /* win 4: addr=0x1d00000, size=4096 bytes */ 56fe56b9e6SYuval Mintz 0x1d01, /* win 5: addr=0x1d01000, size=4096 bytes */ 57fe56b9e6SYuval Mintz 0x1d80, /* win 6: addr=0x1d80000, size=4096 bytes */ 58fe56b9e6SYuval Mintz 0x1d81, /* win 7: addr=0x1d81000, size=4096 bytes */ 59fe56b9e6SYuval Mintz 0x1d82, /* win 8: addr=0x1d82000, size=4096 bytes */ 60fe56b9e6SYuval Mintz 0x1e00, /* win 9: addr=0x1e00000, size=4096 bytes */ 61fe56b9e6SYuval Mintz 0x1e80, /* win 10: addr=0x1e80000, size=4096 bytes */ 62fe56b9e6SYuval Mintz 0x1f00, /* win 11: addr=0x1f00000, size=4096 bytes */ 63fe56b9e6SYuval Mintz 0, 64fe56b9e6SYuval Mintz 0, 65fe56b9e6SYuval Mintz 0, 66fe56b9e6SYuval Mintz 0, 67fe56b9e6SYuval Mintz 0, 68fe56b9e6SYuval Mintz 0, 69fe56b9e6SYuval Mintz 0, 70fe56b9e6SYuval Mintz }; 71fe56b9e6SYuval Mintz 72fe56b9e6SYuval Mintz void qed_init_iro_array(struct qed_dev *cdev) 73fe56b9e6SYuval Mintz { 74fe56b9e6SYuval Mintz cdev->iro_arr = iro_arr; 75fe56b9e6SYuval Mintz } 76fe56b9e6SYuval Mintz 77fe56b9e6SYuval Mintz /* Runtime configuration helpers */ 78fe56b9e6SYuval Mintz void qed_init_clear_rt_data(struct qed_hwfn *p_hwfn) 79fe56b9e6SYuval Mintz { 80fe56b9e6SYuval Mintz int i; 81fe56b9e6SYuval Mintz 82fe56b9e6SYuval Mintz for (i = 0; i < RUNTIME_ARRAY_SIZE; i++) 83fc48b7a6SYuval Mintz p_hwfn->rt_data.b_valid[i] = false; 84fe56b9e6SYuval Mintz } 85fe56b9e6SYuval Mintz 861a635e48SYuval Mintz void qed_init_store_rt_reg(struct qed_hwfn *p_hwfn, u32 rt_offset, u32 val) 87fe56b9e6SYuval Mintz { 88fc48b7a6SYuval Mintz p_hwfn->rt_data.init_val[rt_offset] = val; 89fc48b7a6SYuval Mintz p_hwfn->rt_data.b_valid[rt_offset] = true; 90fe56b9e6SYuval Mintz } 91fe56b9e6SYuval Mintz 92fe56b9e6SYuval Mintz void qed_init_store_rt_agg(struct qed_hwfn *p_hwfn, 931a635e48SYuval Mintz u32 rt_offset, u32 *p_val, size_t size) 94fe56b9e6SYuval Mintz { 95fe56b9e6SYuval Mintz size_t i; 96fe56b9e6SYuval Mintz 97fe56b9e6SYuval Mintz for (i = 0; i < size / sizeof(u32); i++) { 98fc48b7a6SYuval Mintz p_hwfn->rt_data.init_val[rt_offset + i] = p_val[i]; 99fc48b7a6SYuval Mintz p_hwfn->rt_data.b_valid[rt_offset + i] = true; 100fe56b9e6SYuval Mintz } 101fe56b9e6SYuval Mintz } 102fe56b9e6SYuval Mintz 103fc48b7a6SYuval Mintz static int qed_init_rt(struct qed_hwfn *p_hwfn, 104fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1051a635e48SYuval Mintz u32 addr, u16 rt_offset, u16 size, bool b_must_dmae) 106fe56b9e6SYuval Mintz { 107fc48b7a6SYuval Mintz u32 *p_init_val = &p_hwfn->rt_data.init_val[rt_offset]; 108fc48b7a6SYuval Mintz bool *p_valid = &p_hwfn->rt_data.b_valid[rt_offset]; 109fc48b7a6SYuval Mintz u16 i, segment; 110fc48b7a6SYuval Mintz int rc = 0; 111fe56b9e6SYuval Mintz 112fc48b7a6SYuval Mintz /* Since not all RT entries are initialized, go over the RT and 113fc48b7a6SYuval Mintz * for each segment of initialized values use DMA. 114fc48b7a6SYuval Mintz */ 115fe56b9e6SYuval Mintz for (i = 0; i < size; i++) { 116fc48b7a6SYuval Mintz if (!p_valid[i]) 117fe56b9e6SYuval Mintz continue; 118fc48b7a6SYuval Mintz 119fc48b7a6SYuval Mintz /* In case there isn't any wide-bus configuration here, 120fc48b7a6SYuval Mintz * simply write the data instead of using dmae. 121fc48b7a6SYuval Mintz */ 122fc48b7a6SYuval Mintz if (!b_must_dmae) { 1231a635e48SYuval Mintz qed_wr(p_hwfn, p_ptt, addr + (i << 2), p_init_val[i]); 124fc48b7a6SYuval Mintz continue; 125fe56b9e6SYuval Mintz } 126fc48b7a6SYuval Mintz 127fc48b7a6SYuval Mintz /* Start of a new segment */ 128fc48b7a6SYuval Mintz for (segment = 1; i + segment < size; segment++) 129fc48b7a6SYuval Mintz if (!p_valid[i + segment]) 130fc48b7a6SYuval Mintz break; 131fc48b7a6SYuval Mintz 132fc48b7a6SYuval Mintz rc = qed_dmae_host2grc(p_hwfn, p_ptt, 133fc48b7a6SYuval Mintz (uintptr_t)(p_init_val + i), 134fc48b7a6SYuval Mintz addr + (i << 2), segment, 0); 1351a635e48SYuval Mintz if (rc) 136fc48b7a6SYuval Mintz return rc; 137fc48b7a6SYuval Mintz 138fc48b7a6SYuval Mintz /* Jump over the entire segment, including invalid entry */ 139fc48b7a6SYuval Mintz i += segment; 140fc48b7a6SYuval Mintz } 141fc48b7a6SYuval Mintz 142fc48b7a6SYuval Mintz return rc; 143fe56b9e6SYuval Mintz } 144fe56b9e6SYuval Mintz 145fe56b9e6SYuval Mintz int qed_init_alloc(struct qed_hwfn *p_hwfn) 146fe56b9e6SYuval Mintz { 147fc48b7a6SYuval Mintz struct qed_rt_data *rt_data = &p_hwfn->rt_data; 148fe56b9e6SYuval Mintz 1491408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 1501408cc1fSYuval Mintz return 0; 1511408cc1fSYuval Mintz 1526396bb22SKees Cook rt_data->b_valid = kcalloc(RUNTIME_ARRAY_SIZE, sizeof(bool), 153fc48b7a6SYuval Mintz GFP_KERNEL); 154fc48b7a6SYuval Mintz if (!rt_data->b_valid) 155fe56b9e6SYuval Mintz return -ENOMEM; 156fe56b9e6SYuval Mintz 1576396bb22SKees Cook rt_data->init_val = kcalloc(RUNTIME_ARRAY_SIZE, sizeof(u32), 158fc48b7a6SYuval Mintz GFP_KERNEL); 159fc48b7a6SYuval Mintz if (!rt_data->init_val) { 160fc48b7a6SYuval Mintz kfree(rt_data->b_valid); 1613587cb87STomer Tayar rt_data->b_valid = NULL; 162fc48b7a6SYuval Mintz return -ENOMEM; 163fc48b7a6SYuval Mintz } 164fe56b9e6SYuval Mintz 165fe56b9e6SYuval Mintz return 0; 166fe56b9e6SYuval Mintz } 167fe56b9e6SYuval Mintz 168fe56b9e6SYuval Mintz void qed_init_free(struct qed_hwfn *p_hwfn) 169fe56b9e6SYuval Mintz { 170fc48b7a6SYuval Mintz kfree(p_hwfn->rt_data.init_val); 1713587cb87STomer Tayar p_hwfn->rt_data.init_val = NULL; 172fc48b7a6SYuval Mintz kfree(p_hwfn->rt_data.b_valid); 1733587cb87STomer Tayar p_hwfn->rt_data.b_valid = NULL; 174fe56b9e6SYuval Mintz } 175fe56b9e6SYuval Mintz 176fe56b9e6SYuval Mintz static int qed_init_array_dmae(struct qed_hwfn *p_hwfn, 177fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 178fe56b9e6SYuval Mintz u32 addr, 179fe56b9e6SYuval Mintz u32 dmae_data_offset, 180fe56b9e6SYuval Mintz u32 size, 181fe56b9e6SYuval Mintz const u32 *buf, 182fe56b9e6SYuval Mintz bool b_must_dmae, 183fe56b9e6SYuval Mintz bool b_can_dmae) 184fe56b9e6SYuval Mintz { 185fe56b9e6SYuval Mintz int rc = 0; 186fe56b9e6SYuval Mintz 187fe56b9e6SYuval Mintz /* Perform DMAE only for lengthy enough sections or for wide-bus */ 188fe56b9e6SYuval Mintz if (!b_can_dmae || (!b_must_dmae && (size < 16))) { 189fe56b9e6SYuval Mintz const u32 *data = buf + dmae_data_offset; 190fe56b9e6SYuval Mintz u32 i; 191fe56b9e6SYuval Mintz 192fe56b9e6SYuval Mintz for (i = 0; i < size; i++) 193fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, addr + (i << 2), data[i]); 194fe56b9e6SYuval Mintz } else { 195fe56b9e6SYuval Mintz rc = qed_dmae_host2grc(p_hwfn, p_ptt, 196fe56b9e6SYuval Mintz (uintptr_t)(buf + dmae_data_offset), 197fe56b9e6SYuval Mintz addr, size, 0); 198fe56b9e6SYuval Mintz } 199fe56b9e6SYuval Mintz 200fe56b9e6SYuval Mintz return rc; 201fe56b9e6SYuval Mintz } 202fe56b9e6SYuval Mintz 203fe56b9e6SYuval Mintz static int qed_init_fill_dmae(struct qed_hwfn *p_hwfn, 204fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2051a635e48SYuval Mintz u32 addr, u32 fill, u32 fill_count) 206fe56b9e6SYuval Mintz { 207fe56b9e6SYuval Mintz static u32 zero_buffer[DMAE_MAX_RW_SIZE]; 208fe56b9e6SYuval Mintz 209fe56b9e6SYuval Mintz memset(zero_buffer, 0, sizeof(u32) * DMAE_MAX_RW_SIZE); 210fe56b9e6SYuval Mintz 211fe56b9e6SYuval Mintz /* invoke the DMAE virtual/physical buffer API with 212fe56b9e6SYuval Mintz * 1. DMAE init channel 213fe56b9e6SYuval Mintz * 2. addr, 214fe56b9e6SYuval Mintz * 3. p_hwfb->temp_data, 215fe56b9e6SYuval Mintz * 4. fill_count 216fe56b9e6SYuval Mintz */ 217fe56b9e6SYuval Mintz 218fe56b9e6SYuval Mintz return qed_dmae_host2grc(p_hwfn, p_ptt, 219fe56b9e6SYuval Mintz (uintptr_t)(&zero_buffer[0]), 2201a635e48SYuval Mintz addr, fill_count, QED_DMAE_FLAG_RW_REPL_SRC); 221fe56b9e6SYuval Mintz } 222fe56b9e6SYuval Mintz 223fe56b9e6SYuval Mintz static void qed_init_fill(struct qed_hwfn *p_hwfn, 224fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2251a635e48SYuval Mintz u32 addr, u32 fill, u32 fill_count) 226fe56b9e6SYuval Mintz { 227fe56b9e6SYuval Mintz u32 i; 228fe56b9e6SYuval Mintz 229fe56b9e6SYuval Mintz for (i = 0; i < fill_count; i++, addr += sizeof(u32)) 230fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, addr, fill); 231fe56b9e6SYuval Mintz } 232fe56b9e6SYuval Mintz 233fe56b9e6SYuval Mintz static int qed_init_cmd_array(struct qed_hwfn *p_hwfn, 234fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 235fe56b9e6SYuval Mintz struct init_write_op *cmd, 2361a635e48SYuval Mintz bool b_must_dmae, bool b_can_dmae) 237fe56b9e6SYuval Mintz { 2381a635e48SYuval Mintz u32 dmae_array_offset = le32_to_cpu(cmd->args.array_offset); 239fe56b9e6SYuval Mintz u32 data = le32_to_cpu(cmd->data); 240fe56b9e6SYuval Mintz u32 addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2; 2411a635e48SYuval Mintz 242fe56b9e6SYuval Mintz u32 offset, output_len, input_len, max_size; 243fe56b9e6SYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 244fe56b9e6SYuval Mintz union init_array_hdr *hdr; 245fe56b9e6SYuval Mintz const u32 *array_data; 246fe56b9e6SYuval Mintz int rc = 0; 247fe56b9e6SYuval Mintz u32 size; 248fe56b9e6SYuval Mintz 249fe56b9e6SYuval Mintz array_data = cdev->fw_data->arr_data; 250fe56b9e6SYuval Mintz 2511a635e48SYuval Mintz hdr = (union init_array_hdr *)(array_data + dmae_array_offset); 252fe56b9e6SYuval Mintz data = le32_to_cpu(hdr->raw.data); 253fe56b9e6SYuval Mintz switch (GET_FIELD(data, INIT_ARRAY_RAW_HDR_TYPE)) { 254fe56b9e6SYuval Mintz case INIT_ARR_ZIPPED: 255fe56b9e6SYuval Mintz offset = dmae_array_offset + 1; 256fe56b9e6SYuval Mintz input_len = GET_FIELD(data, 257fe56b9e6SYuval Mintz INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE); 258fe56b9e6SYuval Mintz max_size = MAX_ZIPPED_SIZE * 4; 259fe56b9e6SYuval Mintz memset(p_hwfn->unzip_buf, 0, max_size); 260fe56b9e6SYuval Mintz 261fe56b9e6SYuval Mintz output_len = qed_unzip_data(p_hwfn, input_len, 262fe56b9e6SYuval Mintz (u8 *)&array_data[offset], 263fe56b9e6SYuval Mintz max_size, (u8 *)p_hwfn->unzip_buf); 264fe56b9e6SYuval Mintz if (output_len) { 265fe56b9e6SYuval Mintz rc = qed_init_array_dmae(p_hwfn, p_ptt, addr, 0, 266fe56b9e6SYuval Mintz output_len, 267fe56b9e6SYuval Mintz p_hwfn->unzip_buf, 268fe56b9e6SYuval Mintz b_must_dmae, b_can_dmae); 269fe56b9e6SYuval Mintz } else { 270fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed to unzip dmae data\n"); 271fe56b9e6SYuval Mintz rc = -EINVAL; 272fe56b9e6SYuval Mintz } 273fe56b9e6SYuval Mintz break; 274fe56b9e6SYuval Mintz case INIT_ARR_PATTERN: 275fe56b9e6SYuval Mintz { 276fe56b9e6SYuval Mintz u32 repeats = GET_FIELD(data, 277fe56b9e6SYuval Mintz INIT_ARRAY_PATTERN_HDR_REPETITIONS); 278fe56b9e6SYuval Mintz u32 i; 279fe56b9e6SYuval Mintz 280fe56b9e6SYuval Mintz size = GET_FIELD(data, INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE); 281fe56b9e6SYuval Mintz 282fe56b9e6SYuval Mintz for (i = 0; i < repeats; i++, addr += size << 2) { 283fe56b9e6SYuval Mintz rc = qed_init_array_dmae(p_hwfn, p_ptt, addr, 284fe56b9e6SYuval Mintz dmae_array_offset + 1, 285fe56b9e6SYuval Mintz size, array_data, 286fe56b9e6SYuval Mintz b_must_dmae, b_can_dmae); 287fe56b9e6SYuval Mintz if (rc) 288fe56b9e6SYuval Mintz break; 289fe56b9e6SYuval Mintz } 290fe56b9e6SYuval Mintz break; 291fe56b9e6SYuval Mintz } 292fe56b9e6SYuval Mintz case INIT_ARR_STANDARD: 293fe56b9e6SYuval Mintz size = GET_FIELD(data, INIT_ARRAY_STANDARD_HDR_SIZE); 294fe56b9e6SYuval Mintz rc = qed_init_array_dmae(p_hwfn, p_ptt, addr, 295fe56b9e6SYuval Mintz dmae_array_offset + 1, 296fe56b9e6SYuval Mintz size, array_data, 297fe56b9e6SYuval Mintz b_must_dmae, b_can_dmae); 298fe56b9e6SYuval Mintz break; 299fe56b9e6SYuval Mintz } 300fe56b9e6SYuval Mintz 301fe56b9e6SYuval Mintz return rc; 302fe56b9e6SYuval Mintz } 303fe56b9e6SYuval Mintz 304fe56b9e6SYuval Mintz /* init_ops write command */ 305fe56b9e6SYuval Mintz static int qed_init_cmd_wr(struct qed_hwfn *p_hwfn, 306fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 3071a635e48SYuval Mintz struct init_write_op *p_cmd, bool b_can_dmae) 308fe56b9e6SYuval Mintz { 3091a635e48SYuval Mintz u32 data = le32_to_cpu(p_cmd->data); 310fe56b9e6SYuval Mintz bool b_must_dmae = GET_FIELD(data, INIT_WRITE_OP_WIDE_BUS); 3111a635e48SYuval Mintz u32 addr = GET_FIELD(data, INIT_WRITE_OP_ADDRESS) << 2; 3121a635e48SYuval Mintz union init_write_args *arg = &p_cmd->args; 313fe56b9e6SYuval Mintz int rc = 0; 314fe56b9e6SYuval Mintz 315fe56b9e6SYuval Mintz /* Sanitize */ 316fe56b9e6SYuval Mintz if (b_must_dmae && !b_can_dmae) { 317fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 318fe56b9e6SYuval Mintz "Need to write to %08x for Wide-bus but DMAE isn't allowed\n", 319fe56b9e6SYuval Mintz addr); 320fe56b9e6SYuval Mintz return -EINVAL; 321fe56b9e6SYuval Mintz } 322fe56b9e6SYuval Mintz 323fe56b9e6SYuval Mintz switch (GET_FIELD(data, INIT_WRITE_OP_SOURCE)) { 324fe56b9e6SYuval Mintz case INIT_SRC_INLINE: 32583aeb933SYuval Mintz data = le32_to_cpu(p_cmd->args.inline_val); 32683aeb933SYuval Mintz qed_wr(p_hwfn, p_ptt, addr, data); 327fe56b9e6SYuval Mintz break; 328fe56b9e6SYuval Mintz case INIT_SRC_ZEROS: 32983aeb933SYuval Mintz data = le32_to_cpu(p_cmd->args.zeros_count); 33083aeb933SYuval Mintz if (b_must_dmae || (b_can_dmae && (data >= 64))) 33183aeb933SYuval Mintz rc = qed_init_fill_dmae(p_hwfn, p_ptt, addr, 0, data); 332fe56b9e6SYuval Mintz else 33383aeb933SYuval Mintz qed_init_fill(p_hwfn, p_ptt, addr, 0, data); 334fe56b9e6SYuval Mintz break; 335fe56b9e6SYuval Mintz case INIT_SRC_ARRAY: 3361a635e48SYuval Mintz rc = qed_init_cmd_array(p_hwfn, p_ptt, p_cmd, 337fe56b9e6SYuval Mintz b_must_dmae, b_can_dmae); 338fe56b9e6SYuval Mintz break; 339fe56b9e6SYuval Mintz case INIT_SRC_RUNTIME: 340fe56b9e6SYuval Mintz qed_init_rt(p_hwfn, p_ptt, addr, 341fe56b9e6SYuval Mintz le16_to_cpu(arg->runtime.offset), 342fc48b7a6SYuval Mintz le16_to_cpu(arg->runtime.size), 343fc48b7a6SYuval Mintz b_must_dmae); 344fe56b9e6SYuval Mintz break; 345fe56b9e6SYuval Mintz } 346fe56b9e6SYuval Mintz 347fe56b9e6SYuval Mintz return rc; 348fe56b9e6SYuval Mintz } 349fe56b9e6SYuval Mintz 350fe56b9e6SYuval Mintz static inline bool comp_eq(u32 val, u32 expected_val) 351fe56b9e6SYuval Mintz { 352fe56b9e6SYuval Mintz return val == expected_val; 353fe56b9e6SYuval Mintz } 354fe56b9e6SYuval Mintz 355fe56b9e6SYuval Mintz static inline bool comp_and(u32 val, u32 expected_val) 356fe56b9e6SYuval Mintz { 357fe56b9e6SYuval Mintz return (val & expected_val) == expected_val; 358fe56b9e6SYuval Mintz } 359fe56b9e6SYuval Mintz 360fe56b9e6SYuval Mintz static inline bool comp_or(u32 val, u32 expected_val) 361fe56b9e6SYuval Mintz { 362fe56b9e6SYuval Mintz return (val | expected_val) > 0; 363fe56b9e6SYuval Mintz } 364fe56b9e6SYuval Mintz 365fe56b9e6SYuval Mintz /* init_ops read/poll commands */ 366fe56b9e6SYuval Mintz static void qed_init_cmd_rd(struct qed_hwfn *p_hwfn, 3671a635e48SYuval Mintz struct qed_ptt *p_ptt, struct init_read_op *cmd) 368fe56b9e6SYuval Mintz { 369fc48b7a6SYuval Mintz bool (*comp_check)(u32 val, u32 expected_val); 370fe56b9e6SYuval Mintz u32 delay = QED_INIT_POLL_PERIOD_US, val; 371fc48b7a6SYuval Mintz u32 data, addr, poll; 372fc48b7a6SYuval Mintz int i; 373fc48b7a6SYuval Mintz 374fc48b7a6SYuval Mintz data = le32_to_cpu(cmd->op_data); 375fc48b7a6SYuval Mintz addr = GET_FIELD(data, INIT_READ_OP_ADDRESS) << 2; 376fc48b7a6SYuval Mintz poll = GET_FIELD(data, INIT_READ_OP_POLL_TYPE); 377fc48b7a6SYuval Mintz 378fe56b9e6SYuval Mintz 379fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, addr); 380fe56b9e6SYuval Mintz 381fc48b7a6SYuval Mintz if (poll == INIT_POLL_NONE) 382fc48b7a6SYuval Mintz return; 383fe56b9e6SYuval Mintz 384fc48b7a6SYuval Mintz switch (poll) { 385fc48b7a6SYuval Mintz case INIT_POLL_EQ: 386fe56b9e6SYuval Mintz comp_check = comp_eq; 387fe56b9e6SYuval Mintz break; 388fc48b7a6SYuval Mintz case INIT_POLL_OR: 389fe56b9e6SYuval Mintz comp_check = comp_or; 390fe56b9e6SYuval Mintz break; 391fc48b7a6SYuval Mintz case INIT_POLL_AND: 392fe56b9e6SYuval Mintz comp_check = comp_and; 393fe56b9e6SYuval Mintz break; 394fe56b9e6SYuval Mintz default: 395fe56b9e6SYuval Mintz DP_ERR(p_hwfn, "Invalid poll comparison type %08x\n", 396fc48b7a6SYuval Mintz cmd->op_data); 397fe56b9e6SYuval Mintz return; 398fe56b9e6SYuval Mintz } 399fe56b9e6SYuval Mintz 400fc48b7a6SYuval Mintz data = le32_to_cpu(cmd->expected_val); 401fe56b9e6SYuval Mintz for (i = 0; 402fc48b7a6SYuval Mintz i < QED_INIT_MAX_POLL_COUNT && !comp_check(val, data); 403fe56b9e6SYuval Mintz i++) { 404fe56b9e6SYuval Mintz udelay(delay); 405fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, addr); 406fe56b9e6SYuval Mintz } 407fe56b9e6SYuval Mintz 408fc48b7a6SYuval Mintz if (i == QED_INIT_MAX_POLL_COUNT) { 409fe56b9e6SYuval Mintz DP_ERR(p_hwfn, 410fe56b9e6SYuval Mintz "Timeout when polling reg: 0x%08x [ Waiting-for: %08x Got: %08x (comparsion %08x)]\n", 411fe56b9e6SYuval Mintz addr, le32_to_cpu(cmd->expected_val), 412fc48b7a6SYuval Mintz val, le32_to_cpu(cmd->op_data)); 413fe56b9e6SYuval Mintz } 414fe56b9e6SYuval Mintz } 415fe56b9e6SYuval Mintz 416fe56b9e6SYuval Mintz /* init_ops callbacks entry point */ 417da090917STomer Tayar static int qed_init_cmd_cb(struct qed_hwfn *p_hwfn, 418fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 419fe56b9e6SYuval Mintz struct init_callback_op *p_cmd) 420fe56b9e6SYuval Mintz { 421da090917STomer Tayar int rc; 422da090917STomer Tayar 423da090917STomer Tayar switch (p_cmd->callback_id) { 424da090917STomer Tayar case DMAE_READY_CB: 425da090917STomer Tayar rc = qed_dmae_sanity(p_hwfn, p_ptt, "engine_phase"); 426da090917STomer Tayar break; 427da090917STomer Tayar default: 428da090917STomer Tayar DP_NOTICE(p_hwfn, "Unexpected init op callback ID %d\n", 429da090917STomer Tayar p_cmd->callback_id); 430da090917STomer Tayar return -EINVAL; 431da090917STomer Tayar } 432da090917STomer Tayar 433da090917STomer Tayar return rc; 434fe56b9e6SYuval Mintz } 435fe56b9e6SYuval Mintz 436fe56b9e6SYuval Mintz static u8 qed_init_cmd_mode_match(struct qed_hwfn *p_hwfn, 4371a635e48SYuval Mintz u16 *p_offset, int modes) 438fe56b9e6SYuval Mintz { 439fe56b9e6SYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 440fe56b9e6SYuval Mintz const u8 *modes_tree_buf; 441fe56b9e6SYuval Mintz u8 arg1, arg2, tree_val; 442fe56b9e6SYuval Mintz 443fe56b9e6SYuval Mintz modes_tree_buf = cdev->fw_data->modes_tree_buf; 4441a635e48SYuval Mintz tree_val = modes_tree_buf[(*p_offset)++]; 445fe56b9e6SYuval Mintz switch (tree_val) { 446fe56b9e6SYuval Mintz case INIT_MODE_OP_NOT: 4471a635e48SYuval Mintz return qed_init_cmd_mode_match(p_hwfn, p_offset, modes) ^ 1; 448fe56b9e6SYuval Mintz case INIT_MODE_OP_OR: 4491a635e48SYuval Mintz arg1 = qed_init_cmd_mode_match(p_hwfn, p_offset, modes); 4501a635e48SYuval Mintz arg2 = qed_init_cmd_mode_match(p_hwfn, p_offset, modes); 451fe56b9e6SYuval Mintz return arg1 | arg2; 452fe56b9e6SYuval Mintz case INIT_MODE_OP_AND: 4531a635e48SYuval Mintz arg1 = qed_init_cmd_mode_match(p_hwfn, p_offset, modes); 4541a635e48SYuval Mintz arg2 = qed_init_cmd_mode_match(p_hwfn, p_offset, modes); 455fe56b9e6SYuval Mintz return arg1 & arg2; 456fe56b9e6SYuval Mintz default: 457fe56b9e6SYuval Mintz tree_val -= MAX_INIT_MODE_OPS; 4581a635e48SYuval Mintz return (modes & BIT(tree_val)) ? 1 : 0; 459fe56b9e6SYuval Mintz } 460fe56b9e6SYuval Mintz } 461fe56b9e6SYuval Mintz 462fe56b9e6SYuval Mintz static u32 qed_init_cmd_mode(struct qed_hwfn *p_hwfn, 4631a635e48SYuval Mintz struct init_if_mode_op *p_cmd, int modes) 464fe56b9e6SYuval Mintz { 465fe56b9e6SYuval Mintz u16 offset = le16_to_cpu(p_cmd->modes_buf_offset); 466fe56b9e6SYuval Mintz 467fe56b9e6SYuval Mintz if (qed_init_cmd_mode_match(p_hwfn, &offset, modes)) 468fe56b9e6SYuval Mintz return 0; 469fe56b9e6SYuval Mintz else 470fe56b9e6SYuval Mintz return GET_FIELD(le32_to_cpu(p_cmd->op_data), 471fe56b9e6SYuval Mintz INIT_IF_MODE_OP_CMD_OFFSET); 472fe56b9e6SYuval Mintz } 473fe56b9e6SYuval Mintz 474fe56b9e6SYuval Mintz static u32 qed_init_cmd_phase(struct qed_hwfn *p_hwfn, 475fe56b9e6SYuval Mintz struct init_if_phase_op *p_cmd, 4761a635e48SYuval Mintz u32 phase, u32 phase_id) 477fe56b9e6SYuval Mintz { 478fe56b9e6SYuval Mintz u32 data = le32_to_cpu(p_cmd->phase_data); 479fe56b9e6SYuval Mintz u32 op_data = le32_to_cpu(p_cmd->op_data); 480fe56b9e6SYuval Mintz 481fe56b9e6SYuval Mintz if (!(GET_FIELD(data, INIT_IF_PHASE_OP_PHASE) == phase && 482fe56b9e6SYuval Mintz (GET_FIELD(data, INIT_IF_PHASE_OP_PHASE_ID) == ANY_PHASE_ID || 483fe56b9e6SYuval Mintz GET_FIELD(data, INIT_IF_PHASE_OP_PHASE_ID) == phase_id))) 484fe56b9e6SYuval Mintz return GET_FIELD(op_data, INIT_IF_PHASE_OP_CMD_OFFSET); 485fe56b9e6SYuval Mintz else 486fe56b9e6SYuval Mintz return 0; 487fe56b9e6SYuval Mintz } 488fe56b9e6SYuval Mintz 489fe56b9e6SYuval Mintz int qed_init_run(struct qed_hwfn *p_hwfn, 4901a635e48SYuval Mintz struct qed_ptt *p_ptt, int phase, int phase_id, int modes) 491fe56b9e6SYuval Mintz { 492fe56b9e6SYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 493fe56b9e6SYuval Mintz u32 cmd_num, num_init_ops; 494fe56b9e6SYuval Mintz union init_op *init_ops; 495fe56b9e6SYuval Mintz bool b_dmae = false; 496fe56b9e6SYuval Mintz int rc = 0; 497fe56b9e6SYuval Mintz 498fe56b9e6SYuval Mintz num_init_ops = cdev->fw_data->init_ops_size; 499fe56b9e6SYuval Mintz init_ops = cdev->fw_data->init_ops; 500fe56b9e6SYuval Mintz 501fe56b9e6SYuval Mintz p_hwfn->unzip_buf = kzalloc(MAX_ZIPPED_SIZE * 4, GFP_ATOMIC); 5022591c280SJoe Perches if (!p_hwfn->unzip_buf) 503fe56b9e6SYuval Mintz return -ENOMEM; 504fe56b9e6SYuval Mintz 505fe56b9e6SYuval Mintz for (cmd_num = 0; cmd_num < num_init_ops; cmd_num++) { 506fe56b9e6SYuval Mintz union init_op *cmd = &init_ops[cmd_num]; 507fe56b9e6SYuval Mintz u32 data = le32_to_cpu(cmd->raw.op_data); 508fe56b9e6SYuval Mintz 509fe56b9e6SYuval Mintz switch (GET_FIELD(data, INIT_CALLBACK_OP_OP)) { 510fe56b9e6SYuval Mintz case INIT_OP_WRITE: 511fe56b9e6SYuval Mintz rc = qed_init_cmd_wr(p_hwfn, p_ptt, &cmd->write, 512fe56b9e6SYuval Mintz b_dmae); 513fe56b9e6SYuval Mintz break; 514fe56b9e6SYuval Mintz case INIT_OP_READ: 515fe56b9e6SYuval Mintz qed_init_cmd_rd(p_hwfn, p_ptt, &cmd->read); 516fe56b9e6SYuval Mintz break; 517fe56b9e6SYuval Mintz case INIT_OP_IF_MODE: 518fe56b9e6SYuval Mintz cmd_num += qed_init_cmd_mode(p_hwfn, &cmd->if_mode, 519fe56b9e6SYuval Mintz modes); 520fe56b9e6SYuval Mintz break; 521fe56b9e6SYuval Mintz case INIT_OP_IF_PHASE: 522fe56b9e6SYuval Mintz cmd_num += qed_init_cmd_phase(p_hwfn, &cmd->if_phase, 523fe56b9e6SYuval Mintz phase, phase_id); 524fe56b9e6SYuval Mintz b_dmae = GET_FIELD(data, INIT_IF_PHASE_OP_DMAE_ENABLE); 525fe56b9e6SYuval Mintz break; 526fe56b9e6SYuval Mintz case INIT_OP_DELAY: 527fe56b9e6SYuval Mintz /* qed_init_run is always invoked from 528fe56b9e6SYuval Mintz * sleep-able context 529fe56b9e6SYuval Mintz */ 530fe56b9e6SYuval Mintz udelay(le32_to_cpu(cmd->delay.delay)); 531fe56b9e6SYuval Mintz break; 532fe56b9e6SYuval Mintz 533fe56b9e6SYuval Mintz case INIT_OP_CALLBACK: 534da090917STomer Tayar rc = qed_init_cmd_cb(p_hwfn, p_ptt, &cmd->callback); 535fe56b9e6SYuval Mintz break; 536fe56b9e6SYuval Mintz } 537fe56b9e6SYuval Mintz 538fe56b9e6SYuval Mintz if (rc) 539fe56b9e6SYuval Mintz break; 540fe56b9e6SYuval Mintz } 541fe56b9e6SYuval Mintz 542fe56b9e6SYuval Mintz kfree(p_hwfn->unzip_buf); 5433587cb87STomer Tayar p_hwfn->unzip_buf = NULL; 544fe56b9e6SYuval Mintz return rc; 545fe56b9e6SYuval Mintz } 546fe56b9e6SYuval Mintz 547fe56b9e6SYuval Mintz void qed_gtt_init(struct qed_hwfn *p_hwfn) 548fe56b9e6SYuval Mintz { 549fe56b9e6SYuval Mintz u32 gtt_base; 550fe56b9e6SYuval Mintz u32 i; 551fe56b9e6SYuval Mintz 552fe56b9e6SYuval Mintz /* Set the global windows */ 553fe56b9e6SYuval Mintz gtt_base = PXP_PF_WINDOW_ADMIN_START + PXP_PF_WINDOW_ADMIN_GLOBAL_START; 554fe56b9e6SYuval Mintz 555fe56b9e6SYuval Mintz for (i = 0; i < ARRAY_SIZE(pxp_global_win); i++) 556fe56b9e6SYuval Mintz if (pxp_global_win[i]) 557fe56b9e6SYuval Mintz REG_WR(p_hwfn, gtt_base + i * PXP_GLOBAL_ENTRY_SIZE, 558fe56b9e6SYuval Mintz pxp_global_win[i]); 559fe56b9e6SYuval Mintz } 560fe56b9e6SYuval Mintz 561351a4dedSYuval Mintz int qed_init_fw_data(struct qed_dev *cdev, const u8 *data) 562fe56b9e6SYuval Mintz { 563fe56b9e6SYuval Mintz struct qed_fw_data *fw = cdev->fw_data; 564fe56b9e6SYuval Mintz struct bin_buffer_hdr *buf_hdr; 565fe56b9e6SYuval Mintz u32 offset, len; 566fe56b9e6SYuval Mintz 567fe56b9e6SYuval Mintz if (!data) { 568fe56b9e6SYuval Mintz DP_NOTICE(cdev, "Invalid fw data\n"); 569fe56b9e6SYuval Mintz return -EINVAL; 570fe56b9e6SYuval Mintz } 571fe56b9e6SYuval Mintz 572351a4dedSYuval Mintz /* First Dword contains metadata and should be skipped */ 573be086e7cSMintz, Yuval buf_hdr = (struct bin_buffer_hdr *)data; 574351a4dedSYuval Mintz 57505fafbfbSYuval Mintz offset = buf_hdr[BIN_BUF_INIT_FW_VER_INFO].offset; 576351a4dedSYuval Mintz fw->fw_ver_info = (struct fw_ver_info *)(data + offset); 577fe56b9e6SYuval Mintz 578fe56b9e6SYuval Mintz offset = buf_hdr[BIN_BUF_INIT_CMD].offset; 579fe56b9e6SYuval Mintz fw->init_ops = (union init_op *)(data + offset); 580fe56b9e6SYuval Mintz 581fe56b9e6SYuval Mintz offset = buf_hdr[BIN_BUF_INIT_VAL].offset; 582fe56b9e6SYuval Mintz fw->arr_data = (u32 *)(data + offset); 583fe56b9e6SYuval Mintz 584fe56b9e6SYuval Mintz offset = buf_hdr[BIN_BUF_INIT_MODE_TREE].offset; 585fe56b9e6SYuval Mintz fw->modes_tree_buf = (u8 *)(data + offset); 586fe56b9e6SYuval Mintz len = buf_hdr[BIN_BUF_INIT_CMD].length; 587fe56b9e6SYuval Mintz fw->init_ops_size = len / sizeof(struct init_raw_op); 588fe56b9e6SYuval Mintz 589fe56b9e6SYuval Mintz return 0; 590fe56b9e6SYuval Mintz } 591