11f4d4ed6SAlexander Lobakin // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 3e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 4663eacd8SAlexander Lobakin * Copyright (c) 2019-2020 Marvell International Ltd. 5fe56b9e6SYuval Mintz */ 6fe56b9e6SYuval Mintz 7fe56b9e6SYuval Mintz #include <linux/types.h> 8da090917STomer Tayar #include <linux/crc8.h> 9fe56b9e6SYuval Mintz #include <linux/delay.h> 10fe56b9e6SYuval Mintz #include <linux/kernel.h> 11fe56b9e6SYuval Mintz #include <linux/slab.h> 12fe56b9e6SYuval Mintz #include <linux/string.h> 13fe56b9e6SYuval Mintz #include "qed_hsi.h" 14fe56b9e6SYuval Mintz #include "qed_hw.h" 15fe56b9e6SYuval Mintz #include "qed_init_ops.h" 16fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 17fe56b9e6SYuval Mintz 18da090917STomer Tayar #define CDU_VALIDATION_DEFAULT_CFG 61 19da090917STomer Tayar 20*fb09a1edSShai Malin static u16 con_region_offsets[3][NUM_OF_CONNECTION_TYPES] = { 216aebde8dSMichal Kalderon {400, 336, 352, 368, 304, 384, 416, 352}, /* region 3 offsets */ 226aebde8dSMichal Kalderon {528, 496, 416, 512, 448, 512, 544, 480}, /* region 4 offsets */ 236aebde8dSMichal Kalderon {608, 544, 496, 576, 576, 592, 624, 560} /* region 5 offsets */ 24da090917STomer Tayar }; 25da090917STomer Tayar 26*fb09a1edSShai Malin static u16 task_region_offsets[1][NUM_OF_CONNECTION_TYPES] = { 27da090917STomer Tayar {240, 240, 112, 0, 0, 0, 0, 96} /* region 1 offsets */ 28da090917STomer Tayar }; 29da090917STomer Tayar 307b6859fbSMintz, Yuval /* General constants */ 31fe56b9e6SYuval Mintz #define QM_PQ_MEM_4KB(pq_size) (pq_size ? DIV_ROUND_UP((pq_size + 1) * \ 32fe56b9e6SYuval Mintz QM_PQ_ELEMENT_SIZE, \ 33fe56b9e6SYuval Mintz 0x1000) : 0) 34fe56b9e6SYuval Mintz #define QM_PQ_SIZE_256B(pq_size) (pq_size ? DIV_ROUND_UP(pq_size, \ 35fe56b9e6SYuval Mintz 0x100) - 1 : 0) 36fe56b9e6SYuval Mintz #define QM_INVALID_PQ_ID 0xffff 37a2e7699eSTomer Tayar 3892fae6fbSMichal Kalderon /* Max link speed (in Mbps) */ 3992fae6fbSMichal Kalderon #define QM_MAX_LINK_SPEED 100000 4092fae6fbSMichal Kalderon 417b6859fbSMintz, Yuval /* Feature enable */ 42fe56b9e6SYuval Mintz #define QM_BYPASS_EN 1 43fe56b9e6SYuval Mintz #define QM_BYTE_CRD_EN 1 44a2e7699eSTomer Tayar 457b6859fbSMintz, Yuval /* Other PQ constants */ 46fe56b9e6SYuval Mintz #define QM_OTHER_PQS_PER_PF 4 47a2e7699eSTomer Tayar 48fe56b9e6SYuval Mintz /* WFQ constants */ 49a2e7699eSTomer Tayar 50a2e7699eSTomer Tayar /* Upper bound in MB, 10 * burst size of 1ms in 50Gbps */ 51351a4dedSYuval Mintz #define QM_WFQ_UPPER_BOUND 62500000 52a2e7699eSTomer Tayar 53a2e7699eSTomer Tayar /* Bit of VOQ in WFQ VP PQ map */ 54fe56b9e6SYuval Mintz #define QM_WFQ_VP_PQ_VOQ_SHIFT 0 55a2e7699eSTomer Tayar 56a2e7699eSTomer Tayar /* Bit of PF in WFQ VP PQ map */ 57*fb09a1edSShai Malin #define QM_WFQ_VP_PQ_PF_SHIFT 5 58a2e7699eSTomer Tayar 59a2e7699eSTomer Tayar /* 0x9000 = 4*9*1024 */ 60fe56b9e6SYuval Mintz #define QM_WFQ_INC_VAL(weight) ((weight) * 0x9000) 61a2e7699eSTomer Tayar 62a2e7699eSTomer Tayar /* Max WFQ increment value is 0.7 * upper bound */ 63da090917STomer Tayar #define QM_WFQ_MAX_INC_VAL ((QM_WFQ_UPPER_BOUND * 7) / 10) 64351a4dedSYuval Mintz 65fe56b9e6SYuval Mintz /* RL constants */ 66a2e7699eSTomer Tayar 67a2e7699eSTomer Tayar /* Period in us */ 68a2e7699eSTomer Tayar #define QM_RL_PERIOD 5 69a2e7699eSTomer Tayar 70a2e7699eSTomer Tayar /* Period in 25MHz cycles */ 71fe56b9e6SYuval Mintz #define QM_RL_PERIOD_CLK_25M (25 * QM_RL_PERIOD) 72a2e7699eSTomer Tayar 73a2e7699eSTomer Tayar /* RL increment value - rate is specified in mbps */ 74da090917STomer Tayar #define QM_RL_INC_VAL(rate) ({ \ 75da090917STomer Tayar typeof(rate) __rate = (rate); \ 76da090917STomer Tayar max_t(u32, \ 77da090917STomer Tayar (u32)(((__rate ? __rate : 1000000) * QM_RL_PERIOD * 101) / \ 78da090917STomer Tayar (8 * 100)), \ 79da090917STomer Tayar 1); }) 80a2e7699eSTomer Tayar 81a2e7699eSTomer Tayar /* PF RL Upper bound is set to 10 * burst size of 1ms in 50Gbps */ 82da090917STomer Tayar #define QM_PF_RL_UPPER_BOUND 62500000 83a2e7699eSTomer Tayar 84a2e7699eSTomer Tayar /* Max PF RL increment value is 0.7 * upper bound */ 85da090917STomer Tayar #define QM_PF_RL_MAX_INC_VAL ((QM_PF_RL_UPPER_BOUND * 7) / 10) 86da090917STomer Tayar 87da090917STomer Tayar /* Vport RL Upper bound, link speed is in Mpbs */ 88da090917STomer Tayar #define QM_VP_RL_UPPER_BOUND(speed) ((u32)max_t(u32, \ 89da090917STomer Tayar QM_RL_INC_VAL(speed), \ 90da090917STomer Tayar 9700 + 1000)) 91da090917STomer Tayar 92da090917STomer Tayar /* Max Vport RL increment value is the Vport RL upper bound */ 93da090917STomer Tayar #define QM_VP_RL_MAX_INC_VAL(speed) QM_VP_RL_UPPER_BOUND(speed) 94da090917STomer Tayar 95da090917STomer Tayar /* Vport RL credit threshold in case of QM bypass */ 96da090917STomer Tayar #define QM_VP_RL_BYPASS_THRESH_SPEED (QM_VP_RL_UPPER_BOUND(10000) - 1) 97a2e7699eSTomer Tayar 98fe56b9e6SYuval Mintz /* AFullOprtnstcCrdMask constants */ 99fe56b9e6SYuval Mintz #define QM_OPPOR_LINE_VOQ_DEF 1 100fe56b9e6SYuval Mintz #define QM_OPPOR_FW_STOP_DEF 0 101fe56b9e6SYuval Mintz #define QM_OPPOR_PQ_EMPTY_DEF 1 102a2e7699eSTomer Tayar 103fe56b9e6SYuval Mintz /* Command Queue constants */ 104a2e7699eSTomer Tayar 105a2e7699eSTomer Tayar /* Pure LB CmdQ lines (+spare) */ 106fe56b9e6SYuval Mintz #define PBF_CMDQ_PURE_LB_LINES 150 107a2e7699eSTomer Tayar 108a2e7699eSTomer Tayar #define PBF_CMDQ_LINES_RT_OFFSET(ext_voq) \ 109a2e7699eSTomer Tayar (PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET + \ 110a2e7699eSTomer Tayar (ext_voq) * (PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET - \ 111fe56b9e6SYuval Mintz PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET)) 112a2e7699eSTomer Tayar 113a2e7699eSTomer Tayar #define PBF_BTB_GUARANTEED_RT_OFFSET(ext_voq) \ 114a2e7699eSTomer Tayar (PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET + \ 115a2e7699eSTomer Tayar (ext_voq) * (PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET - \ 116fe56b9e6SYuval Mintz PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET)) 117a2e7699eSTomer Tayar 11892fae6fbSMichal Kalderon /* Returns the VOQ line credit for the specified number of PBF command lines. 11992fae6fbSMichal Kalderon * PBF lines are specified in 256b units. 12092fae6fbSMichal Kalderon */ 121a2e7699eSTomer Tayar #define QM_VOQ_LINE_CRD(pbf_cmd_lines) \ 122a2e7699eSTomer Tayar ((((pbf_cmd_lines) - 4) * 2) | QM_LINE_CRD_REG_SIGN_BIT) 123a2e7699eSTomer Tayar 124fe56b9e6SYuval Mintz /* BTB: blocks constants (block size = 256B) */ 125a2e7699eSTomer Tayar 126a2e7699eSTomer Tayar /* 256B blocks in 9700B packet */ 127fe56b9e6SYuval Mintz #define BTB_JUMBO_PKT_BLOCKS 38 128a2e7699eSTomer Tayar 129a2e7699eSTomer Tayar /* Headroom per-port */ 130fe56b9e6SYuval Mintz #define BTB_HEADROOM_BLOCKS BTB_JUMBO_PKT_BLOCKS 131fe56b9e6SYuval Mintz #define BTB_PURE_LB_FACTOR 10 132a2e7699eSTomer Tayar 133a2e7699eSTomer Tayar /* Factored (hence really 0.7) */ 134fe56b9e6SYuval Mintz #define BTB_PURE_LB_RATIO 7 135a2e7699eSTomer Tayar 136fe56b9e6SYuval Mintz /* QM stop command constants */ 137fe56b9e6SYuval Mintz #define QM_STOP_PQ_MASK_WIDTH 32 1387b6859fbSMintz, Yuval #define QM_STOP_CMD_ADDR 2 139fe56b9e6SYuval Mintz #define QM_STOP_CMD_STRUCT_SIZE 2 140fe56b9e6SYuval Mintz #define QM_STOP_CMD_PAUSE_MASK_OFFSET 0 141fe56b9e6SYuval Mintz #define QM_STOP_CMD_PAUSE_MASK_SHIFT 0 142fe56b9e6SYuval Mintz #define QM_STOP_CMD_PAUSE_MASK_MASK -1 143fe56b9e6SYuval Mintz #define QM_STOP_CMD_GROUP_ID_OFFSET 1 144fe56b9e6SYuval Mintz #define QM_STOP_CMD_GROUP_ID_SHIFT 16 145fe56b9e6SYuval Mintz #define QM_STOP_CMD_GROUP_ID_MASK 15 146fe56b9e6SYuval Mintz #define QM_STOP_CMD_PQ_TYPE_OFFSET 1 147fe56b9e6SYuval Mintz #define QM_STOP_CMD_PQ_TYPE_SHIFT 24 148fe56b9e6SYuval Mintz #define QM_STOP_CMD_PQ_TYPE_MASK 1 149fe56b9e6SYuval Mintz #define QM_STOP_CMD_MAX_POLL_COUNT 100 150fe56b9e6SYuval Mintz #define QM_STOP_CMD_POLL_PERIOD_US 500 1517b6859fbSMintz, Yuval 152fe56b9e6SYuval Mintz /* QM command macros */ 153a2e7699eSTomer Tayar #define QM_CMD_STRUCT_SIZE(cmd) cmd ## _STRUCT_SIZE 154a2e7699eSTomer Tayar #define QM_CMD_SET_FIELD(var, cmd, field, value) \ 155a2e7699eSTomer Tayar SET_FIELD(var[cmd ## _ ## field ## _OFFSET], \ 156fe56b9e6SYuval Mintz cmd ## _ ## field, \ 157fe56b9e6SYuval Mintz value) 158da090917STomer Tayar 159*fb09a1edSShai Malin #define QM_INIT_TX_PQ_MAP(p_hwfn, map, pq_id, vp_pq_id, rl_valid, \ 1601451e467SAlexander Lobakin rl_id, ext_voq, wrr) \ 161da090917STomer Tayar do { \ 1625ab90341SAlexander Lobakin u32 __reg = 0; \ 1631451e467SAlexander Lobakin \ 1645ab90341SAlexander Lobakin BUILD_BUG_ON(sizeof((map).reg) != sizeof(__reg)); \ 1651451e467SAlexander Lobakin \ 166*fb09a1edSShai Malin SET_FIELD(__reg, QM_RF_PQ_MAP_PQ_VALID, 1); \ 167*fb09a1edSShai Malin SET_FIELD(__reg, QM_RF_PQ_MAP_RL_VALID, \ 1681451e467SAlexander Lobakin !!(rl_valid)); \ 169*fb09a1edSShai Malin SET_FIELD(__reg, QM_RF_PQ_MAP_VP_PQ_ID, (vp_pq_id)); \ 170*fb09a1edSShai Malin SET_FIELD(__reg, QM_RF_PQ_MAP_RL_ID, (rl_id)); \ 171*fb09a1edSShai Malin SET_FIELD(__reg, QM_RF_PQ_MAP_VOQ, (ext_voq)); \ 172*fb09a1edSShai Malin SET_FIELD(__reg, QM_RF_PQ_MAP_WRR_WEIGHT_GROUP, \ 1731451e467SAlexander Lobakin (wrr)); \ 1741451e467SAlexander Lobakin \ 1751451e467SAlexander Lobakin STORE_RT_REG((p_hwfn), QM_REG_TXPQMAP_RT_OFFSET + (pq_id), \ 1765ab90341SAlexander Lobakin __reg); \ 1775ab90341SAlexander Lobakin (map).reg = cpu_to_le32(__reg); \ 178da090917STomer Tayar } while (0) 179da090917STomer Tayar 180da090917STomer Tayar #define WRITE_PQ_INFO_TO_RAM 1 181da090917STomer Tayar #define PQ_INFO_ELEMENT(vp, pf, tc, port, rl_valid, rl) \ 182da090917STomer Tayar (((vp) << 0) | ((pf) << 12) | ((tc) << 16) | ((port) << 20) | \ 18392fae6fbSMichal Kalderon ((rl_valid ? 1 : 0) << 22) | (((rl) & 255) << 24) | \ 18492fae6fbSMichal Kalderon (((rl) >> 8) << 9)) 18592fae6fbSMichal Kalderon 186da090917STomer Tayar #define PQ_INFO_RAM_GRC_ADDRESS(pq_id) \ 18792fae6fbSMichal Kalderon XSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + \ 18892fae6fbSMichal Kalderon XSTORM_PQ_INFO_OFFSET(pq_id) 189da090917STomer Tayar 190fe56b9e6SYuval Mintz /******************** INTERNAL IMPLEMENTATION *********************/ 191a2e7699eSTomer Tayar 192da090917STomer Tayar /* Returns the external VOQ number */ 193da090917STomer Tayar static u8 qed_get_ext_voq(struct qed_hwfn *p_hwfn, 194da090917STomer Tayar u8 port_id, u8 tc, u8 max_phys_tcs_per_port) 195da090917STomer Tayar { 196da090917STomer Tayar if (tc == PURE_LB_TC) 197da090917STomer Tayar return NUM_OF_PHYS_TCS * MAX_NUM_PORTS_BB + port_id; 198da090917STomer Tayar else 199da090917STomer Tayar return port_id * max_phys_tcs_per_port + tc; 200da090917STomer Tayar } 201da090917STomer Tayar 202fe56b9e6SYuval Mintz /* Prepare PF RL enable/disable runtime init values */ 203351a4dedSYuval Mintz static void qed_enable_pf_rl(struct qed_hwfn *p_hwfn, bool pf_rl_en) 204fe56b9e6SYuval Mintz { 205fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, QM_REG_RLPFENABLE_RT_OFFSET, pf_rl_en ? 1 : 0); 206fe56b9e6SYuval Mintz if (pf_rl_en) { 207*fb09a1edSShai Malin u8 num_ext_voqs = MAX_NUM_VOQS; 208da090917STomer Tayar u64 voq_bit_mask = ((u64)1 << num_ext_voqs) - 1; 209da090917STomer Tayar 2107b6859fbSMintz, Yuval /* Enable RLs for all VOQs */ 211da090917STomer Tayar STORE_RT_REG(p_hwfn, 212da090917STomer Tayar QM_REG_RLPFVOQENABLE_RT_OFFSET, 213da090917STomer Tayar (u32)voq_bit_mask); 214da090917STomer Tayar 2157b6859fbSMintz, Yuval /* Write RL period */ 216fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, 217351a4dedSYuval Mintz QM_REG_RLPFPERIOD_RT_OFFSET, QM_RL_PERIOD_CLK_25M); 218fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, 219fe56b9e6SYuval Mintz QM_REG_RLPFPERIODTIMER_RT_OFFSET, 220fe56b9e6SYuval Mintz QM_RL_PERIOD_CLK_25M); 2217b6859fbSMintz, Yuval 2227b6859fbSMintz, Yuval /* Set credit threshold for QM bypass flow */ 223fe56b9e6SYuval Mintz if (QM_BYPASS_EN) 224fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, 225fe56b9e6SYuval Mintz QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET, 226da090917STomer Tayar QM_PF_RL_UPPER_BOUND); 227fe56b9e6SYuval Mintz } 228fe56b9e6SYuval Mintz } 229fe56b9e6SYuval Mintz 230fe56b9e6SYuval Mintz /* Prepare PF WFQ enable/disable runtime init values */ 231351a4dedSYuval Mintz static void qed_enable_pf_wfq(struct qed_hwfn *p_hwfn, bool pf_wfq_en) 232fe56b9e6SYuval Mintz { 233fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, QM_REG_WFQPFENABLE_RT_OFFSET, pf_wfq_en ? 1 : 0); 2347b6859fbSMintz, Yuval 2357b6859fbSMintz, Yuval /* Set credit threshold for QM bypass flow */ 236fe56b9e6SYuval Mintz if (pf_wfq_en && QM_BYPASS_EN) 237fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, 238fe56b9e6SYuval Mintz QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET, 239fe56b9e6SYuval Mintz QM_WFQ_UPPER_BOUND); 240fe56b9e6SYuval Mintz } 241fe56b9e6SYuval Mintz 24292fae6fbSMichal Kalderon /* Prepare global RL enable/disable runtime init values */ 24392fae6fbSMichal Kalderon static void qed_enable_global_rl(struct qed_hwfn *p_hwfn, bool global_rl_en) 244fe56b9e6SYuval Mintz { 245fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, QM_REG_RLGLBLENABLE_RT_OFFSET, 24692fae6fbSMichal Kalderon global_rl_en ? 1 : 0); 24792fae6fbSMichal Kalderon if (global_rl_en) { 2487b6859fbSMintz, Yuval /* Write RL period (use timer 0 only) */ 249fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, 250fe56b9e6SYuval Mintz QM_REG_RLGLBLPERIOD_0_RT_OFFSET, 251fe56b9e6SYuval Mintz QM_RL_PERIOD_CLK_25M); 252fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, 253fe56b9e6SYuval Mintz QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET, 254fe56b9e6SYuval Mintz QM_RL_PERIOD_CLK_25M); 2557b6859fbSMintz, Yuval 2567b6859fbSMintz, Yuval /* Set credit threshold for QM bypass flow */ 257fe56b9e6SYuval Mintz if (QM_BYPASS_EN) 258fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, 259fe56b9e6SYuval Mintz QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET, 260da090917STomer Tayar QM_VP_RL_BYPASS_THRESH_SPEED); 261fe56b9e6SYuval Mintz } 262fe56b9e6SYuval Mintz } 263fe56b9e6SYuval Mintz 264fe56b9e6SYuval Mintz /* Prepare VPORT WFQ enable/disable runtime init values */ 265351a4dedSYuval Mintz static void qed_enable_vport_wfq(struct qed_hwfn *p_hwfn, bool vport_wfq_en) 266fe56b9e6SYuval Mintz { 267fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, QM_REG_WFQVPENABLE_RT_OFFSET, 268fe56b9e6SYuval Mintz vport_wfq_en ? 1 : 0); 2697b6859fbSMintz, Yuval 2707b6859fbSMintz, Yuval /* Set credit threshold for QM bypass flow */ 271fe56b9e6SYuval Mintz if (vport_wfq_en && QM_BYPASS_EN) 272fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, 273fe56b9e6SYuval Mintz QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET, 274fe56b9e6SYuval Mintz QM_WFQ_UPPER_BOUND); 275fe56b9e6SYuval Mintz } 276fe56b9e6SYuval Mintz 277fe56b9e6SYuval Mintz /* Prepare runtime init values to allocate PBF command queue lines for 2787b6859fbSMintz, Yuval * the specified VOQ. 279fe56b9e6SYuval Mintz */ 280fe56b9e6SYuval Mintz static void qed_cmdq_lines_voq_rt_init(struct qed_hwfn *p_hwfn, 281da090917STomer Tayar u8 ext_voq, u16 cmdq_lines) 282fe56b9e6SYuval Mintz { 283da090917STomer Tayar u32 qm_line_crd = QM_VOQ_LINE_CRD(cmdq_lines); 284fe56b9e6SYuval Mintz 285da090917STomer Tayar OVERWRITE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(ext_voq), 286fe56b9e6SYuval Mintz (u32)cmdq_lines); 287da090917STomer Tayar STORE_RT_REG(p_hwfn, QM_REG_VOQCRDLINE_RT_OFFSET + ext_voq, 288da090917STomer Tayar qm_line_crd); 289da090917STomer Tayar STORE_RT_REG(p_hwfn, QM_REG_VOQINITCRDLINE_RT_OFFSET + ext_voq, 290fe56b9e6SYuval Mintz qm_line_crd); 291fe56b9e6SYuval Mintz } 292fe56b9e6SYuval Mintz 293fe56b9e6SYuval Mintz /* Prepare runtime init values to allocate PBF command queue lines. */ 294fe56b9e6SYuval Mintz static void qed_cmdq_lines_rt_init( 295fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn, 296fe56b9e6SYuval Mintz u8 max_ports_per_engine, 297fe56b9e6SYuval Mintz u8 max_phys_tcs_per_port, 298fe56b9e6SYuval Mintz struct init_qm_port_params port_params[MAX_NUM_PORTS]) 299fe56b9e6SYuval Mintz { 300da090917STomer Tayar u8 tc, ext_voq, port_id, num_tcs_in_port; 301*fb09a1edSShai Malin u8 num_ext_voqs = MAX_NUM_VOQS; 302fe56b9e6SYuval Mintz 303da090917STomer Tayar /* Clear PBF lines of all VOQs */ 304da090917STomer Tayar for (ext_voq = 0; ext_voq < num_ext_voqs; ext_voq++) 305da090917STomer Tayar STORE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(ext_voq), 0); 306da090917STomer Tayar 307fe56b9e6SYuval Mintz for (port_id = 0; port_id < max_ports_per_engine; port_id++) { 308fe56b9e6SYuval Mintz u16 phys_lines, phys_lines_per_tc; 309fe56b9e6SYuval Mintz 310da090917STomer Tayar if (!port_params[port_id].active) 311da090917STomer Tayar continue; 312da090917STomer Tayar 313da090917STomer Tayar /* Find number of command queue lines to divide between the 31492fae6fbSMichal Kalderon * active physical TCs. 315da090917STomer Tayar */ 316da090917STomer Tayar phys_lines = port_params[port_id].num_pbf_cmd_lines; 317da090917STomer Tayar phys_lines -= PBF_CMDQ_PURE_LB_LINES; 318da090917STomer Tayar 319da090917STomer Tayar /* Find #lines per active physical TC */ 320351a4dedSYuval Mintz num_tcs_in_port = 0; 321da090917STomer Tayar for (tc = 0; tc < max_phys_tcs_per_port; tc++) 322351a4dedSYuval Mintz if (((port_params[port_id].active_phys_tcs >> 323351a4dedSYuval Mintz tc) & 0x1) == 1) 324351a4dedSYuval Mintz num_tcs_in_port++; 325351a4dedSYuval Mintz phys_lines_per_tc = phys_lines / num_tcs_in_port; 326351a4dedSYuval Mintz 327da090917STomer Tayar /* Init registers per active TC */ 328da090917STomer Tayar for (tc = 0; tc < max_phys_tcs_per_port; tc++) { 329da090917STomer Tayar ext_voq = qed_get_ext_voq(p_hwfn, 330da090917STomer Tayar port_id, 331da090917STomer Tayar tc, max_phys_tcs_per_port); 332da090917STomer Tayar if (((port_params[port_id].active_phys_tcs >> 333da090917STomer Tayar tc) & 0x1) == 1) 334da090917STomer Tayar qed_cmdq_lines_voq_rt_init(p_hwfn, 335da090917STomer Tayar ext_voq, 336fe56b9e6SYuval Mintz phys_lines_per_tc); 337fe56b9e6SYuval Mintz } 338351a4dedSYuval Mintz 339da090917STomer Tayar /* Init registers for pure LB TC */ 340da090917STomer Tayar ext_voq = qed_get_ext_voq(p_hwfn, 341da090917STomer Tayar port_id, 342da090917STomer Tayar PURE_LB_TC, max_phys_tcs_per_port); 34392fae6fbSMichal Kalderon qed_cmdq_lines_voq_rt_init(p_hwfn, ext_voq, 34492fae6fbSMichal Kalderon PBF_CMDQ_PURE_LB_LINES); 345fe56b9e6SYuval Mintz } 346fe56b9e6SYuval Mintz } 347fe56b9e6SYuval Mintz 34892fae6fbSMichal Kalderon /* Prepare runtime init values to allocate guaranteed BTB blocks for the 34992fae6fbSMichal Kalderon * specified port. The guaranteed BTB space is divided between the TCs as 35092fae6fbSMichal Kalderon * follows (shared space Is currently not used): 35192fae6fbSMichal Kalderon * 1. Parameters: 35292fae6fbSMichal Kalderon * B - BTB blocks for this port 35392fae6fbSMichal Kalderon * C - Number of physical TCs for this port 35492fae6fbSMichal Kalderon * 2. Calculation: 35592fae6fbSMichal Kalderon * a. 38 blocks (9700B jumbo frame) are allocated for global per port 35692fae6fbSMichal Kalderon * headroom. 35792fae6fbSMichal Kalderon * b. B = B - 38 (remainder after global headroom allocation). 35892fae6fbSMichal Kalderon * c. MAX(38,B/(C+0.7)) blocks are allocated for the pure LB VOQ. 35992fae6fbSMichal Kalderon * d. B = B - MAX(38, B/(C+0.7)) (remainder after pure LB allocation). 36092fae6fbSMichal Kalderon * e. B/C blocks are allocated for each physical TC. 36192fae6fbSMichal Kalderon * Assumptions: 36292fae6fbSMichal Kalderon * - MTU is up to 9700 bytes (38 blocks) 36392fae6fbSMichal Kalderon * - All TCs are considered symmetrical (same rate and packet size) 36492fae6fbSMichal Kalderon * - No optimization for lossy TC (all are considered lossless). Shared space 36592fae6fbSMichal Kalderon * is not enabled and allocated for each TC. 36692fae6fbSMichal Kalderon */ 367fe56b9e6SYuval Mintz static void qed_btb_blocks_rt_init( 368fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn, 369fe56b9e6SYuval Mintz u8 max_ports_per_engine, 370fe56b9e6SYuval Mintz u8 max_phys_tcs_per_port, 371fe56b9e6SYuval Mintz struct init_qm_port_params port_params[MAX_NUM_PORTS]) 372fe56b9e6SYuval Mintz { 373fe56b9e6SYuval Mintz u32 usable_blocks, pure_lb_blocks, phys_blocks; 374da090917STomer Tayar u8 tc, ext_voq, port_id, num_tcs_in_port; 375fe56b9e6SYuval Mintz 376fe56b9e6SYuval Mintz for (port_id = 0; port_id < max_ports_per_engine; port_id++) { 377fe56b9e6SYuval Mintz if (!port_params[port_id].active) 378fe56b9e6SYuval Mintz continue; 379fe56b9e6SYuval Mintz 3807b6859fbSMintz, Yuval /* Subtract headroom blocks */ 381fe56b9e6SYuval Mintz usable_blocks = port_params[port_id].num_btb_blocks - 382fe56b9e6SYuval Mintz BTB_HEADROOM_BLOCKS; 383fe56b9e6SYuval Mintz 384da090917STomer Tayar /* Find blocks per physical TC. Use factor to avoid floating 385da090917STomer Tayar * arithmethic. 386da090917STomer Tayar */ 387351a4dedSYuval Mintz num_tcs_in_port = 0; 388da090917STomer Tayar for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) 389351a4dedSYuval Mintz if (((port_params[port_id].active_phys_tcs >> 390351a4dedSYuval Mintz tc) & 0x1) == 1) 391351a4dedSYuval Mintz num_tcs_in_port++; 392351a4dedSYuval Mintz 393fe56b9e6SYuval Mintz pure_lb_blocks = (usable_blocks * BTB_PURE_LB_FACTOR) / 394351a4dedSYuval Mintz (num_tcs_in_port * BTB_PURE_LB_FACTOR + 395fe56b9e6SYuval Mintz BTB_PURE_LB_RATIO); 396fe56b9e6SYuval Mintz pure_lb_blocks = max_t(u32, BTB_JUMBO_PKT_BLOCKS, 397fe56b9e6SYuval Mintz pure_lb_blocks / BTB_PURE_LB_FACTOR); 398351a4dedSYuval Mintz phys_blocks = (usable_blocks - pure_lb_blocks) / 399351a4dedSYuval Mintz num_tcs_in_port; 400fe56b9e6SYuval Mintz 4017b6859fbSMintz, Yuval /* Init physical TCs */ 402351a4dedSYuval Mintz for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) { 403351a4dedSYuval Mintz if (((port_params[port_id].active_phys_tcs >> 404da090917STomer Tayar tc) & 0x1) == 1) { 405da090917STomer Tayar ext_voq = 406da090917STomer Tayar qed_get_ext_voq(p_hwfn, 407da090917STomer Tayar port_id, 408da090917STomer Tayar tc, 409351a4dedSYuval Mintz max_phys_tcs_per_port); 410da090917STomer Tayar STORE_RT_REG(p_hwfn, 411da090917STomer Tayar PBF_BTB_GUARANTEED_RT_OFFSET 412da090917STomer Tayar (ext_voq), phys_blocks); 413da090917STomer Tayar } 414fe56b9e6SYuval Mintz } 415fe56b9e6SYuval Mintz 4167b6859fbSMintz, Yuval /* Init pure LB TC */ 417da090917STomer Tayar ext_voq = qed_get_ext_voq(p_hwfn, 418da090917STomer Tayar port_id, 419da090917STomer Tayar PURE_LB_TC, max_phys_tcs_per_port); 420da090917STomer Tayar STORE_RT_REG(p_hwfn, PBF_BTB_GUARANTEED_RT_OFFSET(ext_voq), 421fe56b9e6SYuval Mintz pure_lb_blocks); 422fe56b9e6SYuval Mintz } 423fe56b9e6SYuval Mintz } 424fe56b9e6SYuval Mintz 42592fae6fbSMichal Kalderon /* Prepare runtime init values for the specified RL. 42692fae6fbSMichal Kalderon * Set max link speed (100Gbps) per rate limiter. 42792fae6fbSMichal Kalderon * Return -1 on error. 42892fae6fbSMichal Kalderon */ 42992fae6fbSMichal Kalderon static int qed_global_rl_rt_init(struct qed_hwfn *p_hwfn) 43092fae6fbSMichal Kalderon { 43192fae6fbSMichal Kalderon u32 upper_bound = QM_VP_RL_UPPER_BOUND(QM_MAX_LINK_SPEED) | 43292fae6fbSMichal Kalderon (u32)QM_RL_CRD_REG_SIGN_BIT; 43392fae6fbSMichal Kalderon u32 inc_val; 43492fae6fbSMichal Kalderon u16 rl_id; 43592fae6fbSMichal Kalderon 43692fae6fbSMichal Kalderon /* Go over all global RLs */ 43792fae6fbSMichal Kalderon for (rl_id = 0; rl_id < MAX_QM_GLOBAL_RLS; rl_id++) { 43892fae6fbSMichal Kalderon inc_val = QM_RL_INC_VAL(QM_MAX_LINK_SPEED); 43992fae6fbSMichal Kalderon 44092fae6fbSMichal Kalderon STORE_RT_REG(p_hwfn, 44192fae6fbSMichal Kalderon QM_REG_RLGLBLCRD_RT_OFFSET + rl_id, 44292fae6fbSMichal Kalderon (u32)QM_RL_CRD_REG_SIGN_BIT); 44392fae6fbSMichal Kalderon STORE_RT_REG(p_hwfn, 44492fae6fbSMichal Kalderon QM_REG_RLGLBLUPPERBOUND_RT_OFFSET + rl_id, 44592fae6fbSMichal Kalderon upper_bound); 44692fae6fbSMichal Kalderon STORE_RT_REG(p_hwfn, 44792fae6fbSMichal Kalderon QM_REG_RLGLBLINCVAL_RT_OFFSET + rl_id, inc_val); 44892fae6fbSMichal Kalderon } 44992fae6fbSMichal Kalderon 45092fae6fbSMichal Kalderon return 0; 45192fae6fbSMichal Kalderon } 45292fae6fbSMichal Kalderon 453fe56b9e6SYuval Mintz /* Prepare Tx PQ mapping runtime init values for the specified PF */ 454da090917STomer Tayar static void qed_tx_pq_map_rt_init(struct qed_hwfn *p_hwfn, 455fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 456fe56b9e6SYuval Mintz struct qed_qm_pf_rt_init_params *p_params, 457fe56b9e6SYuval Mintz u32 base_mem_addr_4kb) 458fe56b9e6SYuval Mintz { 459fe56b9e6SYuval Mintz u32 tx_pq_vf_mask[MAX_QM_TX_QUEUES / QM_PF_QUEUE_GROUP_SIZE] = { 0 }; 460da090917STomer Tayar struct init_qm_vport_params *vport_params = p_params->vport_params; 461be086e7cSMintz, Yuval u32 num_tx_pq_vf_masks = MAX_QM_TX_QUEUES / QM_PF_QUEUE_GROUP_SIZE; 462da090917STomer Tayar u16 num_pqs, first_pq_group, last_pq_group, i, j, pq_id, pq_group; 463da090917STomer Tayar struct init_qm_pq_params *pq_params = p_params->pq_params; 464da090917STomer Tayar u32 pq_mem_4kb, vport_pq_mem_4kb, mem_addr_4kb; 465da090917STomer Tayar 466da090917STomer Tayar num_pqs = p_params->num_pf_pqs + p_params->num_vf_pqs; 467da090917STomer Tayar 468da090917STomer Tayar first_pq_group = p_params->start_pq / QM_PF_QUEUE_GROUP_SIZE; 469da090917STomer Tayar last_pq_group = (p_params->start_pq + num_pqs - 1) / 470da090917STomer Tayar QM_PF_QUEUE_GROUP_SIZE; 471da090917STomer Tayar 472da090917STomer Tayar pq_mem_4kb = QM_PQ_MEM_4KB(p_params->num_pf_cids); 473da090917STomer Tayar vport_pq_mem_4kb = QM_PQ_MEM_4KB(p_params->num_vf_cids); 474da090917STomer Tayar mem_addr_4kb = base_mem_addr_4kb; 475fe56b9e6SYuval Mintz 4767b6859fbSMintz, Yuval /* Set mapping from PQ group to PF */ 477fe56b9e6SYuval Mintz for (pq_group = first_pq_group; pq_group <= last_pq_group; pq_group++) 478fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, QM_REG_PQTX2PF_0_RT_OFFSET + pq_group, 479fe56b9e6SYuval Mintz (u32)(p_params->pf_id)); 480da090917STomer Tayar 4817b6859fbSMintz, Yuval /* Set PQ sizes */ 482fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_0_RT_OFFSET, 483fe56b9e6SYuval Mintz QM_PQ_SIZE_256B(p_params->num_pf_cids)); 484fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_1_RT_OFFSET, 485fe56b9e6SYuval Mintz QM_PQ_SIZE_256B(p_params->num_vf_cids)); 486fe56b9e6SYuval Mintz 4877b6859fbSMintz, Yuval /* Go over all Tx PQs */ 488fe56b9e6SYuval Mintz for (i = 0, pq_id = p_params->start_pq; i < num_pqs; i++, pq_id++) { 48992fae6fbSMichal Kalderon u16 *p_first_tx_pq_id, vport_id_in_pf; 490*fb09a1edSShai Malin struct qm_rf_pq_map tx_pq_map; 49192fae6fbSMichal Kalderon u8 tc_id = pq_params[i].tc_id; 49292fae6fbSMichal Kalderon bool is_vf_pq; 49392fae6fbSMichal Kalderon u8 ext_voq; 494fe56b9e6SYuval Mintz 495da090917STomer Tayar ext_voq = qed_get_ext_voq(p_hwfn, 49650bc60cbSMichal Kalderon pq_params[i].port_id, 497da090917STomer Tayar tc_id, 498da090917STomer Tayar p_params->max_phys_tcs_per_port); 499da090917STomer Tayar is_vf_pq = (i >= p_params->num_pf_pqs); 500be086e7cSMintz, Yuval 5017b6859fbSMintz, Yuval /* Update first Tx PQ of VPORT/TC */ 502da090917STomer Tayar vport_id_in_pf = pq_params[i].vport_id - p_params->start_vport; 503da090917STomer Tayar p_first_tx_pq_id = 504da090917STomer Tayar &vport_params[vport_id_in_pf].first_tx_pq_id[tc_id]; 505da090917STomer Tayar if (*p_first_tx_pq_id == QM_INVALID_PQ_ID) { 506da090917STomer Tayar u32 map_val = 507da090917STomer Tayar (ext_voq << QM_WFQ_VP_PQ_VOQ_SHIFT) | 508*fb09a1edSShai Malin (p_params->pf_id << QM_WFQ_VP_PQ_PF_SHIFT); 509fe56b9e6SYuval Mintz 5107b6859fbSMintz, Yuval /* Create new VP PQ */ 511da090917STomer Tayar *p_first_tx_pq_id = pq_id; 5127b6859fbSMintz, Yuval 5137b6859fbSMintz, Yuval /* Map VP PQ to VOQ and PF */ 514fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, 515fe56b9e6SYuval Mintz QM_REG_WFQVPMAP_RT_OFFSET + 516da090917STomer Tayar *p_first_tx_pq_id, 517da090917STomer Tayar map_val); 518fe56b9e6SYuval Mintz } 519be086e7cSMintz, Yuval 520da090917STomer Tayar /* Prepare PQ map entry */ 521da090917STomer Tayar QM_INIT_TX_PQ_MAP(p_hwfn, 522da090917STomer Tayar tx_pq_map, 523da090917STomer Tayar pq_id, 524da090917STomer Tayar *p_first_tx_pq_id, 52592fae6fbSMichal Kalderon pq_params[i].rl_valid, 52692fae6fbSMichal Kalderon pq_params[i].rl_id, 527da090917STomer Tayar ext_voq, pq_params[i].wrr_group); 528da090917STomer Tayar 529da090917STomer Tayar /* Set PQ base address */ 530fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, 531fe56b9e6SYuval Mintz QM_REG_BASEADDRTXPQ_RT_OFFSET + pq_id, 532fe56b9e6SYuval Mintz mem_addr_4kb); 5337b6859fbSMintz, Yuval 534da090917STomer Tayar /* Clear PQ pointer table entry (64 bit) */ 535da090917STomer Tayar if (p_params->is_pf_loading) 536da090917STomer Tayar for (j = 0; j < 2; j++) 537da090917STomer Tayar STORE_RT_REG(p_hwfn, 538da090917STomer Tayar QM_REG_PTRTBLTX_RT_OFFSET + 539da090917STomer Tayar (pq_id * 2) + j, 0); 540da090917STomer Tayar 541da090917STomer Tayar /* Write PQ info to RAM */ 542da090917STomer Tayar if (WRITE_PQ_INFO_TO_RAM != 0) { 543da090917STomer Tayar u32 pq_info = 0; 544da090917STomer Tayar 545da090917STomer Tayar pq_info = PQ_INFO_ELEMENT(*p_first_tx_pq_id, 546da090917STomer Tayar p_params->pf_id, 547da090917STomer Tayar tc_id, 54850bc60cbSMichal Kalderon pq_params[i].port_id, 54992fae6fbSMichal Kalderon pq_params[i].rl_valid, 55092fae6fbSMichal Kalderon pq_params[i].rl_id); 551da090917STomer Tayar qed_wr(p_hwfn, p_ptt, PQ_INFO_RAM_GRC_ADDRESS(pq_id), 552da090917STomer Tayar pq_info); 553da090917STomer Tayar } 554da090917STomer Tayar 5557b6859fbSMintz, Yuval /* If VF PQ, add indication to PQ VF mask */ 556fe56b9e6SYuval Mintz if (is_vf_pq) { 557be086e7cSMintz, Yuval tx_pq_vf_mask[pq_id / 558be086e7cSMintz, Yuval QM_PF_QUEUE_GROUP_SIZE] |= 559be086e7cSMintz, Yuval BIT((pq_id % QM_PF_QUEUE_GROUP_SIZE)); 560fe56b9e6SYuval Mintz mem_addr_4kb += vport_pq_mem_4kb; 561fe56b9e6SYuval Mintz } else { 562fe56b9e6SYuval Mintz mem_addr_4kb += pq_mem_4kb; 563fe56b9e6SYuval Mintz } 564fe56b9e6SYuval Mintz } 565fe56b9e6SYuval Mintz 5667b6859fbSMintz, Yuval /* Store Tx PQ VF mask to size select register */ 5677b6859fbSMintz, Yuval for (i = 0; i < num_tx_pq_vf_masks; i++) 5687b6859fbSMintz, Yuval if (tx_pq_vf_mask[i]) 5697b6859fbSMintz, Yuval STORE_RT_REG(p_hwfn, 5707b6859fbSMintz, Yuval QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET + i, 571fe56b9e6SYuval Mintz tx_pq_vf_mask[i]); 572fe56b9e6SYuval Mintz } 573fe56b9e6SYuval Mintz 574fe56b9e6SYuval Mintz /* Prepare Other PQ mapping runtime init values for the specified PF */ 575fe56b9e6SYuval Mintz static void qed_other_pq_map_rt_init(struct qed_hwfn *p_hwfn, 576fe56b9e6SYuval Mintz u8 pf_id, 577da090917STomer Tayar bool is_pf_loading, 578fe56b9e6SYuval Mintz u32 num_pf_cids, 579351a4dedSYuval Mintz u32 num_tids, u32 base_mem_addr_4kb) 580fe56b9e6SYuval Mintz { 5817b6859fbSMintz, Yuval u32 pq_size, pq_mem_4kb, mem_addr_4kb; 582da090917STomer Tayar u16 i, j, pq_id, pq_group; 583fe56b9e6SYuval Mintz 584da090917STomer Tayar /* A single other PQ group is used in each PF, where PQ group i is used 585da090917STomer Tayar * in PF i. 586fe56b9e6SYuval Mintz */ 5877b6859fbSMintz, Yuval pq_group = pf_id; 5887b6859fbSMintz, Yuval pq_size = num_pf_cids + num_tids; 5897b6859fbSMintz, Yuval pq_mem_4kb = QM_PQ_MEM_4KB(pq_size); 5907b6859fbSMintz, Yuval mem_addr_4kb = base_mem_addr_4kb; 591fe56b9e6SYuval Mintz 5927b6859fbSMintz, Yuval /* Map PQ group to PF */ 593fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, QM_REG_PQOTHER2PF_0_RT_OFFSET + pq_group, 594fe56b9e6SYuval Mintz (u32)(pf_id)); 595da090917STomer Tayar 5967b6859fbSMintz, Yuval /* Set PQ sizes */ 597fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_2_RT_OFFSET, 598fe56b9e6SYuval Mintz QM_PQ_SIZE_256B(pq_size)); 5997b6859fbSMintz, Yuval 600fe56b9e6SYuval Mintz for (i = 0, pq_id = pf_id * QM_PF_QUEUE_GROUP_SIZE; 601fe56b9e6SYuval Mintz i < QM_OTHER_PQS_PER_PF; i++, pq_id++) { 602da090917STomer Tayar /* Set PQ base address */ 603fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, 604fe56b9e6SYuval Mintz QM_REG_BASEADDROTHERPQ_RT_OFFSET + pq_id, 605fe56b9e6SYuval Mintz mem_addr_4kb); 606da090917STomer Tayar 607da090917STomer Tayar /* Clear PQ pointer table entry */ 608da090917STomer Tayar if (is_pf_loading) 609da090917STomer Tayar for (j = 0; j < 2; j++) 610da090917STomer Tayar STORE_RT_REG(p_hwfn, 611da090917STomer Tayar QM_REG_PTRTBLOTHER_RT_OFFSET + 612da090917STomer Tayar (pq_id * 2) + j, 0); 613da090917STomer Tayar 614fe56b9e6SYuval Mintz mem_addr_4kb += pq_mem_4kb; 615fe56b9e6SYuval Mintz } 616fe56b9e6SYuval Mintz } 617fe56b9e6SYuval Mintz 618fe56b9e6SYuval Mintz /* Prepare PF WFQ runtime init values for the specified PF. 619fe56b9e6SYuval Mintz * Return -1 on error. 620fe56b9e6SYuval Mintz */ 621fe56b9e6SYuval Mintz static int qed_pf_wfq_rt_init(struct qed_hwfn *p_hwfn, 62250bc60cbSMichal Kalderon 623fe56b9e6SYuval Mintz struct qed_qm_pf_rt_init_params *p_params) 624fe56b9e6SYuval Mintz { 625fe56b9e6SYuval Mintz u16 num_tx_pqs = p_params->num_pf_pqs + p_params->num_vf_pqs; 626da090917STomer Tayar struct init_qm_pq_params *pq_params = p_params->pq_params; 627da090917STomer Tayar u32 inc_val, crd_reg_offset; 628da090917STomer Tayar u8 ext_voq; 629fe56b9e6SYuval Mintz u16 i; 630fe56b9e6SYuval Mintz 631fe56b9e6SYuval Mintz inc_val = QM_WFQ_INC_VAL(p_params->pf_wfq); 632351a4dedSYuval Mintz if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) { 6337b6859fbSMintz, Yuval DP_NOTICE(p_hwfn, "Invalid PF WFQ weight configuration\n"); 634fe56b9e6SYuval Mintz return -1; 635fe56b9e6SYuval Mintz } 636fe56b9e6SYuval Mintz 637fe56b9e6SYuval Mintz for (i = 0; i < num_tx_pqs; i++) { 638da090917STomer Tayar ext_voq = qed_get_ext_voq(p_hwfn, 63950bc60cbSMichal Kalderon pq_params[i].port_id, 640da090917STomer Tayar pq_params[i].tc_id, 641fe56b9e6SYuval Mintz p_params->max_phys_tcs_per_port); 642da090917STomer Tayar crd_reg_offset = 643da090917STomer Tayar (p_params->pf_id < MAX_NUM_PFS_BB ? 644da090917STomer Tayar QM_REG_WFQPFCRD_RT_OFFSET : 645da090917STomer Tayar QM_REG_WFQPFCRD_MSB_RT_OFFSET) + 646da090917STomer Tayar ext_voq * MAX_NUM_PFS_BB + 647da090917STomer Tayar (p_params->pf_id % MAX_NUM_PFS_BB); 648fe56b9e6SYuval Mintz OVERWRITE_RT_REG(p_hwfn, 649da090917STomer Tayar crd_reg_offset, (u32)QM_WFQ_CRD_REG_SIGN_BIT); 650fe56b9e6SYuval Mintz } 651fe56b9e6SYuval Mintz 652351a4dedSYuval Mintz STORE_RT_REG(p_hwfn, 653351a4dedSYuval Mintz QM_REG_WFQPFUPPERBOUND_RT_OFFSET + p_params->pf_id, 654da090917STomer Tayar QM_WFQ_UPPER_BOUND | (u32)QM_WFQ_CRD_REG_SIGN_BIT); 655be086e7cSMintz, Yuval STORE_RT_REG(p_hwfn, QM_REG_WFQPFWEIGHT_RT_OFFSET + p_params->pf_id, 656be086e7cSMintz, Yuval inc_val); 657da090917STomer Tayar 658fe56b9e6SYuval Mintz return 0; 659fe56b9e6SYuval Mintz } 660fe56b9e6SYuval Mintz 661fe56b9e6SYuval Mintz /* Prepare PF RL runtime init values for the specified PF. 662fe56b9e6SYuval Mintz * Return -1 on error. 663fe56b9e6SYuval Mintz */ 664351a4dedSYuval Mintz static int qed_pf_rl_rt_init(struct qed_hwfn *p_hwfn, u8 pf_id, u32 pf_rl) 665fe56b9e6SYuval Mintz { 666fe56b9e6SYuval Mintz u32 inc_val = QM_RL_INC_VAL(pf_rl); 667fe56b9e6SYuval Mintz 668da090917STomer Tayar if (inc_val > QM_PF_RL_MAX_INC_VAL) { 6697b6859fbSMintz, Yuval DP_NOTICE(p_hwfn, "Invalid PF rate limit configuration\n"); 670fe56b9e6SYuval Mintz return -1; 671fe56b9e6SYuval Mintz } 672da090917STomer Tayar 673da090917STomer Tayar STORE_RT_REG(p_hwfn, 674da090917STomer Tayar QM_REG_RLPFCRD_RT_OFFSET + pf_id, 675da090917STomer Tayar (u32)QM_RL_CRD_REG_SIGN_BIT); 676da090917STomer Tayar STORE_RT_REG(p_hwfn, 677da090917STomer Tayar QM_REG_RLPFUPPERBOUND_RT_OFFSET + pf_id, 678da090917STomer Tayar QM_PF_RL_UPPER_BOUND | (u32)QM_RL_CRD_REG_SIGN_BIT); 679fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, QM_REG_RLPFINCVAL_RT_OFFSET + pf_id, inc_val); 680da090917STomer Tayar 681fe56b9e6SYuval Mintz return 0; 682fe56b9e6SYuval Mintz } 683fe56b9e6SYuval Mintz 684fe56b9e6SYuval Mintz /* Prepare VPORT WFQ runtime init values for the specified VPORTs. 685fe56b9e6SYuval Mintz * Return -1 on error. 686fe56b9e6SYuval Mintz */ 687fe56b9e6SYuval Mintz static int qed_vp_wfq_rt_init(struct qed_hwfn *p_hwfn, 68892fae6fbSMichal Kalderon u16 num_vports, 689fe56b9e6SYuval Mintz struct init_qm_vport_params *vport_params) 690fe56b9e6SYuval Mintz { 69192fae6fbSMichal Kalderon u16 vport_pq_id, i; 692fe56b9e6SYuval Mintz u32 inc_val; 69392fae6fbSMichal Kalderon u8 tc; 694fe56b9e6SYuval Mintz 6957b6859fbSMintz, Yuval /* Go over all PF VPORTs */ 696fc48b7a6SYuval Mintz for (i = 0; i < num_vports; i++) { 69792fae6fbSMichal Kalderon if (!vport_params[i].wfq) 698fe56b9e6SYuval Mintz continue; 699fe56b9e6SYuval Mintz 70092fae6fbSMichal Kalderon inc_val = QM_WFQ_INC_VAL(vport_params[i].wfq); 701fe56b9e6SYuval Mintz if (inc_val > QM_WFQ_MAX_INC_VAL) { 702fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 7037b6859fbSMintz, Yuval "Invalid VPORT WFQ weight configuration\n"); 704fe56b9e6SYuval Mintz return -1; 705fe56b9e6SYuval Mintz } 706fe56b9e6SYuval Mintz 707da090917STomer Tayar /* Each VPORT can have several VPORT PQ IDs for various TCs */ 708fe56b9e6SYuval Mintz for (tc = 0; tc < NUM_OF_TCS; tc++) { 709da090917STomer Tayar vport_pq_id = vport_params[i].first_tx_pq_id[tc]; 710fe56b9e6SYuval Mintz if (vport_pq_id != QM_INVALID_PQ_ID) { 711fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, 712fe56b9e6SYuval Mintz QM_REG_WFQVPCRD_RT_OFFSET + 713fe56b9e6SYuval Mintz vport_pq_id, 714da090917STomer Tayar (u32)QM_WFQ_CRD_REG_SIGN_BIT); 715fc48b7a6SYuval Mintz STORE_RT_REG(p_hwfn, 716fc48b7a6SYuval Mintz QM_REG_WFQVPWEIGHT_RT_OFFSET + 717fc48b7a6SYuval Mintz vport_pq_id, inc_val); 718fe56b9e6SYuval Mintz } 719fe56b9e6SYuval Mintz } 720fe56b9e6SYuval Mintz } 721fe56b9e6SYuval Mintz 722fe56b9e6SYuval Mintz return 0; 723fe56b9e6SYuval Mintz } 724fe56b9e6SYuval Mintz 725fe56b9e6SYuval Mintz static bool qed_poll_on_qm_cmd_ready(struct qed_hwfn *p_hwfn, 726fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 727fe56b9e6SYuval Mintz { 728fe56b9e6SYuval Mintz u32 reg_val, i; 729fe56b9e6SYuval Mintz 730da090917STomer Tayar for (i = 0, reg_val = 0; i < QM_STOP_CMD_MAX_POLL_COUNT && !reg_val; 731fe56b9e6SYuval Mintz i++) { 732fe56b9e6SYuval Mintz udelay(QM_STOP_CMD_POLL_PERIOD_US); 733fe56b9e6SYuval Mintz reg_val = qed_rd(p_hwfn, p_ptt, QM_REG_SDMCMDREADY); 734fe56b9e6SYuval Mintz } 735fe56b9e6SYuval Mintz 7367b6859fbSMintz, Yuval /* Check if timeout while waiting for SDM command ready */ 737fe56b9e6SYuval Mintz if (i == QM_STOP_CMD_MAX_POLL_COUNT) { 738fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 739fe56b9e6SYuval Mintz "Timeout when waiting for QM SDM command ready signal\n"); 740fe56b9e6SYuval Mintz return false; 741fe56b9e6SYuval Mintz } 742fe56b9e6SYuval Mintz 743fe56b9e6SYuval Mintz return true; 744fe56b9e6SYuval Mintz } 745fe56b9e6SYuval Mintz 746fe56b9e6SYuval Mintz static bool qed_send_qm_cmd(struct qed_hwfn *p_hwfn, 747fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 748351a4dedSYuval Mintz u32 cmd_addr, u32 cmd_data_lsb, u32 cmd_data_msb) 749fe56b9e6SYuval Mintz { 750fe56b9e6SYuval Mintz if (!qed_poll_on_qm_cmd_ready(p_hwfn, p_ptt)) 751fe56b9e6SYuval Mintz return false; 752fe56b9e6SYuval Mintz 753fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, QM_REG_SDMCMDADDR, cmd_addr); 754fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, QM_REG_SDMCMDDATALSB, cmd_data_lsb); 755fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, QM_REG_SDMCMDDATAMSB, cmd_data_msb); 756fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, QM_REG_SDMCMDGO, 1); 757fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, QM_REG_SDMCMDGO, 0); 758fe56b9e6SYuval Mintz 759fe56b9e6SYuval Mintz return qed_poll_on_qm_cmd_ready(p_hwfn, p_ptt); 760fe56b9e6SYuval Mintz } 761fe56b9e6SYuval Mintz 762fe56b9e6SYuval Mintz /******************** INTERFACE IMPLEMENTATION *********************/ 763da090917STomer Tayar 764da090917STomer Tayar u32 qed_qm_pf_mem_size(u32 num_pf_cids, 765fe56b9e6SYuval Mintz u32 num_vf_cids, 766351a4dedSYuval Mintz u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs) 767fe56b9e6SYuval Mintz { 768fe56b9e6SYuval Mintz return QM_PQ_MEM_4KB(num_pf_cids) * num_pf_pqs + 769fe56b9e6SYuval Mintz QM_PQ_MEM_4KB(num_vf_cids) * num_vf_pqs + 770fe56b9e6SYuval Mintz QM_PQ_MEM_4KB(num_pf_cids + num_tids) * QM_OTHER_PQS_PER_PF; 771fe56b9e6SYuval Mintz } 772fe56b9e6SYuval Mintz 773da090917STomer Tayar int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn, 774fe56b9e6SYuval Mintz struct qed_qm_common_rt_init_params *p_params) 775fe56b9e6SYuval Mintz { 77692fae6fbSMichal Kalderon u32 mask = 0; 777fe56b9e6SYuval Mintz 77892fae6fbSMichal Kalderon /* Init AFullOprtnstcCrdMask */ 77992fae6fbSMichal Kalderon SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_LINEVOQ, 78092fae6fbSMichal Kalderon QM_OPPOR_LINE_VOQ_DEF); 78192fae6fbSMichal Kalderon SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ, QM_BYTE_CRD_EN); 78292fae6fbSMichal Kalderon SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_PFWFQ, p_params->pf_wfq_en); 78392fae6fbSMichal Kalderon SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_VPWFQ, p_params->vport_wfq_en); 78492fae6fbSMichal Kalderon SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_PFRL, p_params->pf_rl_en); 78592fae6fbSMichal Kalderon SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_VPQCNRL, 78692fae6fbSMichal Kalderon p_params->global_rl_en); 78792fae6fbSMichal Kalderon SET_FIELD(mask, QM_RF_OPPORTUNISTIC_MASK_FWPAUSE, QM_OPPOR_FW_STOP_DEF); 78892fae6fbSMichal Kalderon SET_FIELD(mask, 78992fae6fbSMichal Kalderon QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY, QM_OPPOR_PQ_EMPTY_DEF); 790fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET, mask); 791da090917STomer Tayar 792da090917STomer Tayar /* Enable/disable PF RL */ 793fe56b9e6SYuval Mintz qed_enable_pf_rl(p_hwfn, p_params->pf_rl_en); 794da090917STomer Tayar 795da090917STomer Tayar /* Enable/disable PF WFQ */ 796fe56b9e6SYuval Mintz qed_enable_pf_wfq(p_hwfn, p_params->pf_wfq_en); 797da090917STomer Tayar 79892fae6fbSMichal Kalderon /* Enable/disable global RL */ 79992fae6fbSMichal Kalderon qed_enable_global_rl(p_hwfn, p_params->global_rl_en); 800da090917STomer Tayar 801da090917STomer Tayar /* Enable/disable VPORT WFQ */ 802fe56b9e6SYuval Mintz qed_enable_vport_wfq(p_hwfn, p_params->vport_wfq_en); 803da090917STomer Tayar 804da090917STomer Tayar /* Init PBF CMDQ line credit */ 805fe56b9e6SYuval Mintz qed_cmdq_lines_rt_init(p_hwfn, 806fe56b9e6SYuval Mintz p_params->max_ports_per_engine, 807fe56b9e6SYuval Mintz p_params->max_phys_tcs_per_port, 808fe56b9e6SYuval Mintz p_params->port_params); 809da090917STomer Tayar 810da090917STomer Tayar /* Init BTB blocks in PBF */ 811fe56b9e6SYuval Mintz qed_btb_blocks_rt_init(p_hwfn, 812fe56b9e6SYuval Mintz p_params->max_ports_per_engine, 813fe56b9e6SYuval Mintz p_params->max_phys_tcs_per_port, 814fe56b9e6SYuval Mintz p_params->port_params); 815da090917STomer Tayar 81692fae6fbSMichal Kalderon qed_global_rl_rt_init(p_hwfn); 81792fae6fbSMichal Kalderon 818fe56b9e6SYuval Mintz return 0; 819fe56b9e6SYuval Mintz } 820fe56b9e6SYuval Mintz 821fe56b9e6SYuval Mintz int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn, 822fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 823fe56b9e6SYuval Mintz struct qed_qm_pf_rt_init_params *p_params) 824fe56b9e6SYuval Mintz { 825fe56b9e6SYuval Mintz struct init_qm_vport_params *vport_params = p_params->vport_params; 826fe56b9e6SYuval Mintz u32 other_mem_size_4kb = QM_PQ_MEM_4KB(p_params->num_pf_cids + 827fe56b9e6SYuval Mintz p_params->num_tids) * 828fe56b9e6SYuval Mintz QM_OTHER_PQS_PER_PF; 82992fae6fbSMichal Kalderon u16 i; 83092fae6fbSMichal Kalderon u8 tc; 83192fae6fbSMichal Kalderon 832fe56b9e6SYuval Mintz 8337b6859fbSMintz, Yuval /* Clear first Tx PQ ID array for each VPORT */ 834fe56b9e6SYuval Mintz for (i = 0; i < p_params->num_vports; i++) 835fe56b9e6SYuval Mintz for (tc = 0; tc < NUM_OF_TCS; tc++) 836fe56b9e6SYuval Mintz vport_params[i].first_tx_pq_id[tc] = QM_INVALID_PQ_ID; 837fe56b9e6SYuval Mintz 8387b6859fbSMintz, Yuval /* Map Other PQs (if any) */ 839da090917STomer Tayar qed_other_pq_map_rt_init(p_hwfn, 840da090917STomer Tayar p_params->pf_id, 841da090917STomer Tayar p_params->is_pf_loading, p_params->num_pf_cids, 842da090917STomer Tayar p_params->num_tids, 0); 843fe56b9e6SYuval Mintz 8447b6859fbSMintz, Yuval /* Map Tx PQs */ 845fe56b9e6SYuval Mintz qed_tx_pq_map_rt_init(p_hwfn, p_ptt, p_params, other_mem_size_4kb); 846fe56b9e6SYuval Mintz 847da090917STomer Tayar /* Init PF WFQ */ 848fe56b9e6SYuval Mintz if (p_params->pf_wfq) 849fe56b9e6SYuval Mintz if (qed_pf_wfq_rt_init(p_hwfn, p_params)) 850fe56b9e6SYuval Mintz return -1; 851fe56b9e6SYuval Mintz 852da090917STomer Tayar /* Init PF RL */ 853fe56b9e6SYuval Mintz if (qed_pf_rl_rt_init(p_hwfn, p_params->pf_id, p_params->pf_rl)) 854fe56b9e6SYuval Mintz return -1; 855fe56b9e6SYuval Mintz 85692fae6fbSMichal Kalderon /* Init VPORT WFQ */ 857fc48b7a6SYuval Mintz if (qed_vp_wfq_rt_init(p_hwfn, p_params->num_vports, vport_params)) 858fe56b9e6SYuval Mintz return -1; 859fe56b9e6SYuval Mintz 860fe56b9e6SYuval Mintz return 0; 861fe56b9e6SYuval Mintz } 862fe56b9e6SYuval Mintz 863a64b02d5SManish Chopra int qed_init_pf_wfq(struct qed_hwfn *p_hwfn, 864351a4dedSYuval Mintz struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq) 865a64b02d5SManish Chopra { 866a64b02d5SManish Chopra u32 inc_val = QM_WFQ_INC_VAL(pf_wfq); 867a64b02d5SManish Chopra 868a64b02d5SManish Chopra if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) { 8697b6859fbSMintz, Yuval DP_NOTICE(p_hwfn, "Invalid PF WFQ weight configuration\n"); 870a64b02d5SManish Chopra return -1; 871a64b02d5SManish Chopra } 872a64b02d5SManish Chopra 873a64b02d5SManish Chopra qed_wr(p_hwfn, p_ptt, QM_REG_WFQPFWEIGHT + pf_id * 4, inc_val); 874da090917STomer Tayar 875a64b02d5SManish Chopra return 0; 876a64b02d5SManish Chopra } 877a64b02d5SManish Chopra 878fe56b9e6SYuval Mintz int qed_init_pf_rl(struct qed_hwfn *p_hwfn, 879351a4dedSYuval Mintz struct qed_ptt *p_ptt, u8 pf_id, u32 pf_rl) 880fe56b9e6SYuval Mintz { 881fe56b9e6SYuval Mintz u32 inc_val = QM_RL_INC_VAL(pf_rl); 882fe56b9e6SYuval Mintz 883da090917STomer Tayar if (inc_val > QM_PF_RL_MAX_INC_VAL) { 8847b6859fbSMintz, Yuval DP_NOTICE(p_hwfn, "Invalid PF rate limit configuration\n"); 885fe56b9e6SYuval Mintz return -1; 886fe56b9e6SYuval Mintz } 887fe56b9e6SYuval Mintz 888da090917STomer Tayar qed_wr(p_hwfn, 889da090917STomer Tayar p_ptt, QM_REG_RLPFCRD + pf_id * 4, (u32)QM_RL_CRD_REG_SIGN_BIT); 890fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, QM_REG_RLPFINCVAL + pf_id * 4, inc_val); 891fe56b9e6SYuval Mintz 892fe56b9e6SYuval Mintz return 0; 893fe56b9e6SYuval Mintz } 894fe56b9e6SYuval Mintz 895bcd197c8SManish Chopra int qed_init_vport_wfq(struct qed_hwfn *p_hwfn, 896bcd197c8SManish Chopra struct qed_ptt *p_ptt, 89792fae6fbSMichal Kalderon u16 first_tx_pq_id[NUM_OF_TCS], u16 wfq) 898bcd197c8SManish Chopra { 8997b6859fbSMintz, Yuval u16 vport_pq_id; 9007b6859fbSMintz, Yuval u32 inc_val; 901bcd197c8SManish Chopra u8 tc; 902bcd197c8SManish Chopra 90392fae6fbSMichal Kalderon inc_val = QM_WFQ_INC_VAL(wfq); 904bcd197c8SManish Chopra if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) { 90592fae6fbSMichal Kalderon DP_NOTICE(p_hwfn, "Invalid VPORT WFQ configuration.\n"); 906bcd197c8SManish Chopra return -1; 907bcd197c8SManish Chopra } 908bcd197c8SManish Chopra 90992fae6fbSMichal Kalderon /* A VPORT can have several VPORT PQ IDs for various TCs */ 910bcd197c8SManish Chopra for (tc = 0; tc < NUM_OF_TCS; tc++) { 9117b6859fbSMintz, Yuval vport_pq_id = first_tx_pq_id[tc]; 912bcd197c8SManish Chopra if (vport_pq_id != QM_INVALID_PQ_ID) 913da090917STomer Tayar qed_wr(p_hwfn, 914da090917STomer Tayar p_ptt, 915da090917STomer Tayar QM_REG_WFQVPWEIGHT + vport_pq_id * 4, inc_val); 916bcd197c8SManish Chopra } 917bcd197c8SManish Chopra 918bcd197c8SManish Chopra return 0; 919bcd197c8SManish Chopra } 920bcd197c8SManish Chopra 92192fae6fbSMichal Kalderon int qed_init_global_rl(struct qed_hwfn *p_hwfn, 92292fae6fbSMichal Kalderon struct qed_ptt *p_ptt, u16 rl_id, u32 rate_limit) 923fe56b9e6SYuval Mintz { 92492fae6fbSMichal Kalderon u32 inc_val; 925fe56b9e6SYuval Mintz 92692fae6fbSMichal Kalderon inc_val = QM_RL_INC_VAL(rate_limit); 92792fae6fbSMichal Kalderon if (inc_val > QM_VP_RL_MAX_INC_VAL(rate_limit)) { 92892fae6fbSMichal Kalderon DP_NOTICE(p_hwfn, "Invalid rate limit configuration.\n"); 929be086e7cSMintz, Yuval return -1; 930be086e7cSMintz, Yuval } 931be086e7cSMintz, Yuval 93292fae6fbSMichal Kalderon qed_wr(p_hwfn, p_ptt, 93392fae6fbSMichal Kalderon QM_REG_RLGLBLCRD + rl_id * 4, (u32)QM_RL_CRD_REG_SIGN_BIT); 93492fae6fbSMichal Kalderon qed_wr(p_hwfn, p_ptt, QM_REG_RLGLBLINCVAL + rl_id * 4, inc_val); 935fe56b9e6SYuval Mintz 936fe56b9e6SYuval Mintz return 0; 937fe56b9e6SYuval Mintz } 938fe56b9e6SYuval Mintz 939fe56b9e6SYuval Mintz bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn, 940fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 941fe56b9e6SYuval Mintz bool is_release_cmd, 942351a4dedSYuval Mintz bool is_tx_pq, u16 start_pq, u16 num_pqs) 943fe56b9e6SYuval Mintz { 944fe56b9e6SYuval Mintz u32 cmd_arr[QM_CMD_STRUCT_SIZE(QM_STOP_CMD)] = { 0 }; 945da090917STomer Tayar u32 pq_mask = 0, last_pq, pq_id; 946da090917STomer Tayar 947da090917STomer Tayar last_pq = start_pq + num_pqs - 1; 948fe56b9e6SYuval Mintz 9497b6859fbSMintz, Yuval /* Set command's PQ type */ 950fe56b9e6SYuval Mintz QM_CMD_SET_FIELD(cmd_arr, QM_STOP_CMD, PQ_TYPE, is_tx_pq ? 0 : 1); 951fe56b9e6SYuval Mintz 952da090917STomer Tayar /* Go over requested PQs */ 953fe56b9e6SYuval Mintz for (pq_id = start_pq; pq_id <= last_pq; pq_id++) { 9547b6859fbSMintz, Yuval /* Set PQ bit in mask (stop command only) */ 955fe56b9e6SYuval Mintz if (!is_release_cmd) 956da090917STomer Tayar pq_mask |= BIT((pq_id % QM_STOP_PQ_MASK_WIDTH)); 957fe56b9e6SYuval Mintz 9587b6859fbSMintz, Yuval /* If last PQ or end of PQ mask, write command */ 959fe56b9e6SYuval Mintz if ((pq_id == last_pq) || 960fe56b9e6SYuval Mintz (pq_id % QM_STOP_PQ_MASK_WIDTH == 961fe56b9e6SYuval Mintz (QM_STOP_PQ_MASK_WIDTH - 1))) { 962da090917STomer Tayar QM_CMD_SET_FIELD(cmd_arr, 963da090917STomer Tayar QM_STOP_CMD, PAUSE_MASK, pq_mask); 964da090917STomer Tayar QM_CMD_SET_FIELD(cmd_arr, 965da090917STomer Tayar QM_STOP_CMD, 966fe56b9e6SYuval Mintz GROUP_ID, 967fe56b9e6SYuval Mintz pq_id / QM_STOP_PQ_MASK_WIDTH); 968fe56b9e6SYuval Mintz if (!qed_send_qm_cmd(p_hwfn, p_ptt, QM_STOP_CMD_ADDR, 969fe56b9e6SYuval Mintz cmd_arr[0], cmd_arr[1])) 970fe56b9e6SYuval Mintz return false; 971fe56b9e6SYuval Mintz pq_mask = 0; 972fe56b9e6SYuval Mintz } 973fe56b9e6SYuval Mintz } 974fe56b9e6SYuval Mintz 975fe56b9e6SYuval Mintz return true; 976fe56b9e6SYuval Mintz } 977464f6645SManish Chopra 978da090917STomer Tayar #define SET_TUNNEL_TYPE_ENABLE_BIT(var, offset, enable) \ 979da090917STomer Tayar do { \ 980da090917STomer Tayar typeof(var) *__p_var = &(var); \ 981da090917STomer Tayar typeof(offset) __offset = offset; \ 982da090917STomer Tayar *__p_var = (*__p_var & ~BIT(__offset)) | \ 983da090917STomer Tayar ((enable) ? BIT(__offset) : 0); \ 984da090917STomer Tayar } while (0) 98563ddca30SMichal Kalderon 98663ddca30SMichal Kalderon #define PRS_ETH_TUNN_OUTPUT_FORMAT 0xF4DAB910 98763ddca30SMichal Kalderon #define PRS_ETH_OUTPUT_FORMAT 0xFFFF4910 988464f6645SManish Chopra 989804c5702SMichal Kalderon #define ARR_REG_WR(dev, ptt, addr, arr, arr_size) \ 990804c5702SMichal Kalderon do { \ 991804c5702SMichal Kalderon u32 i; \ 992804c5702SMichal Kalderon \ 993804c5702SMichal Kalderon for (i = 0; i < (arr_size); i++) \ 994804c5702SMichal Kalderon qed_wr(dev, ptt, \ 995804c5702SMichal Kalderon ((addr) + (4 * i)), \ 996804c5702SMichal Kalderon ((u32 *)&(arr))[i]); \ 997804c5702SMichal Kalderon } while (0) 998804c5702SMichal Kalderon 999804c5702SMichal Kalderon /** 100071e11a3fSAlexander Lobakin * qed_dmae_to_grc() - Internal function for writing from host to 100171e11a3fSAlexander Lobakin * wide-bus registers (split registers are not supported yet). 1002804c5702SMichal Kalderon * 100371e11a3fSAlexander Lobakin * @p_hwfn: HW device data. 100471e11a3fSAlexander Lobakin * @p_ptt: PTT window used for writing the registers. 100571e11a3fSAlexander Lobakin * @p_data: Pointer to source data. 100671e11a3fSAlexander Lobakin * @addr: Destination register address. 100771e11a3fSAlexander Lobakin * @len_in_dwords: Data length in dwords (u32). 100871e11a3fSAlexander Lobakin * 100971e11a3fSAlexander Lobakin * Return: Length of the written data in dwords (u32) or -1 on invalid 101071e11a3fSAlexander Lobakin * input. 1011804c5702SMichal Kalderon */ 10121451e467SAlexander Lobakin static int qed_dmae_to_grc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 10135ab90341SAlexander Lobakin __le32 *p_data, u32 addr, u32 len_in_dwords) 1014804c5702SMichal Kalderon { 1015804c5702SMichal Kalderon struct qed_dmae_params params = {}; 10165ab90341SAlexander Lobakin u32 *data_cpu; 1017804c5702SMichal Kalderon int rc; 1018804c5702SMichal Kalderon 1019804c5702SMichal Kalderon if (!p_data) 1020804c5702SMichal Kalderon return -1; 1021804c5702SMichal Kalderon 1022804c5702SMichal Kalderon /* Set DMAE params */ 1023804c5702SMichal Kalderon SET_FIELD(params.flags, QED_DMAE_PARAMS_COMPLETION_DST, 1); 1024804c5702SMichal Kalderon 1025804c5702SMichal Kalderon /* Execute DMAE command */ 1026804c5702SMichal Kalderon rc = qed_dmae_host2grc(p_hwfn, p_ptt, 1027804c5702SMichal Kalderon (u64)(uintptr_t)(p_data), 1028804c5702SMichal Kalderon addr, len_in_dwords, ¶ms); 1029804c5702SMichal Kalderon 1030804c5702SMichal Kalderon /* If not read using DMAE, read using GRC */ 1031804c5702SMichal Kalderon if (rc) { 1032804c5702SMichal Kalderon DP_VERBOSE(p_hwfn, 1033804c5702SMichal Kalderon QED_MSG_DEBUG, 1034804c5702SMichal Kalderon "Failed writing to chip using DMAE, using GRC instead\n"); 10355ab90341SAlexander Lobakin 10365ab90341SAlexander Lobakin /* Swap to CPU byteorder and write to registers using GRC */ 10375ab90341SAlexander Lobakin data_cpu = (__force u32 *)p_data; 10385ab90341SAlexander Lobakin le32_to_cpu_array(data_cpu, len_in_dwords); 10395ab90341SAlexander Lobakin 10405ab90341SAlexander Lobakin ARR_REG_WR(p_hwfn, p_ptt, addr, data_cpu, len_in_dwords); 10415ab90341SAlexander Lobakin cpu_to_le32_array(data_cpu, len_in_dwords); 1042804c5702SMichal Kalderon } 1043804c5702SMichal Kalderon 1044804c5702SMichal Kalderon return len_in_dwords; 1045804c5702SMichal Kalderon } 1046804c5702SMichal Kalderon 1047464f6645SManish Chopra void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn, 1048351a4dedSYuval Mintz struct qed_ptt *p_ptt, u16 dest_port) 1049464f6645SManish Chopra { 1050da090917STomer Tayar /* Update PRS register */ 1051464f6645SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_VXLAN_PORT, dest_port); 1052da090917STomer Tayar 1053da090917STomer Tayar /* Update NIG register */ 1054351a4dedSYuval Mintz qed_wr(p_hwfn, p_ptt, NIG_REG_VXLAN_CTRL, dest_port); 1055da090917STomer Tayar 1056da090917STomer Tayar /* Update PBF register */ 1057464f6645SManish Chopra qed_wr(p_hwfn, p_ptt, PBF_REG_VXLAN_PORT, dest_port); 1058464f6645SManish Chopra } 1059464f6645SManish Chopra 1060464f6645SManish Chopra void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn, 1061351a4dedSYuval Mintz struct qed_ptt *p_ptt, bool vxlan_enable) 1062464f6645SManish Chopra { 1063da090917STomer Tayar u32 reg_val; 1064464f6645SManish Chopra u8 shift; 1065464f6645SManish Chopra 1066da090917STomer Tayar /* Update PRS register */ 1067464f6645SManish Chopra reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN); 1068464f6645SManish Chopra shift = PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT; 1069da090917STomer Tayar SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, vxlan_enable); 1070464f6645SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val); 107150bc60cbSMichal Kalderon if (reg_val) { 107250bc60cbSMichal Kalderon reg_val = 107350bc60cbSMichal Kalderon qed_rd(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2); 107450bc60cbSMichal Kalderon 107550bc60cbSMichal Kalderon /* Update output only if tunnel blocks not included. */ 107650bc60cbSMichal Kalderon if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT) 107750bc60cbSMichal Kalderon qed_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, 107850bc60cbSMichal Kalderon (u32)PRS_ETH_TUNN_OUTPUT_FORMAT); 107950bc60cbSMichal Kalderon } 1080464f6645SManish Chopra 1081da090917STomer Tayar /* Update NIG register */ 1082464f6645SManish Chopra reg_val = qed_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE); 1083464f6645SManish Chopra shift = NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT; 1084da090917STomer Tayar SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, vxlan_enable); 1085464f6645SManish Chopra qed_wr(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE, reg_val); 1086464f6645SManish Chopra 1087da090917STomer Tayar /* Update DORQ register */ 1088da090917STomer Tayar qed_wr(p_hwfn, 1089da090917STomer Tayar p_ptt, DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN, vxlan_enable ? 1 : 0); 1090464f6645SManish Chopra } 1091464f6645SManish Chopra 1092da090917STomer Tayar void qed_set_gre_enable(struct qed_hwfn *p_hwfn, 1093da090917STomer Tayar struct qed_ptt *p_ptt, 1094464f6645SManish Chopra bool eth_gre_enable, bool ip_gre_enable) 1095464f6645SManish Chopra { 1096da090917STomer Tayar u32 reg_val; 1097464f6645SManish Chopra u8 shift; 1098464f6645SManish Chopra 1099da090917STomer Tayar /* Update PRS register */ 1100464f6645SManish Chopra reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN); 1101464f6645SManish Chopra shift = PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT; 1102da090917STomer Tayar SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, eth_gre_enable); 1103464f6645SManish Chopra shift = PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT; 1104da090917STomer Tayar SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, ip_gre_enable); 1105464f6645SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val); 110650bc60cbSMichal Kalderon if (reg_val) { 110750bc60cbSMichal Kalderon reg_val = 110850bc60cbSMichal Kalderon qed_rd(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2); 110950bc60cbSMichal Kalderon 111050bc60cbSMichal Kalderon /* Update output only if tunnel blocks not included. */ 111150bc60cbSMichal Kalderon if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT) 111250bc60cbSMichal Kalderon qed_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, 111350bc60cbSMichal Kalderon (u32)PRS_ETH_TUNN_OUTPUT_FORMAT); 111450bc60cbSMichal Kalderon } 1115464f6645SManish Chopra 1116da090917STomer Tayar /* Update NIG register */ 1117464f6645SManish Chopra reg_val = qed_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE); 1118464f6645SManish Chopra shift = NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT; 1119da090917STomer Tayar SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, eth_gre_enable); 1120464f6645SManish Chopra shift = NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT; 1121da090917STomer Tayar SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, ip_gre_enable); 1122464f6645SManish Chopra qed_wr(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE, reg_val); 1123464f6645SManish Chopra 1124da090917STomer Tayar /* Update DORQ registers */ 1125da090917STomer Tayar qed_wr(p_hwfn, 1126da090917STomer Tayar p_ptt, 1127da090917STomer Tayar DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN, eth_gre_enable ? 1 : 0); 1128da090917STomer Tayar qed_wr(p_hwfn, 1129da090917STomer Tayar p_ptt, DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN, ip_gre_enable ? 1 : 0); 1130464f6645SManish Chopra } 1131464f6645SManish Chopra 1132464f6645SManish Chopra void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn, 1133351a4dedSYuval Mintz struct qed_ptt *p_ptt, u16 dest_port) 1134464f6645SManish Chopra { 1135da090917STomer Tayar /* Update PRS register */ 1136464f6645SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_NGE_PORT, dest_port); 1137da090917STomer Tayar 1138da090917STomer Tayar /* Update NIG register */ 1139464f6645SManish Chopra qed_wr(p_hwfn, p_ptt, NIG_REG_NGE_PORT, dest_port); 1140da090917STomer Tayar 1141da090917STomer Tayar /* Update PBF register */ 1142464f6645SManish Chopra qed_wr(p_hwfn, p_ptt, PBF_REG_NGE_PORT, dest_port); 1143464f6645SManish Chopra } 1144464f6645SManish Chopra 1145464f6645SManish Chopra void qed_set_geneve_enable(struct qed_hwfn *p_hwfn, 1146464f6645SManish Chopra struct qed_ptt *p_ptt, 1147351a4dedSYuval Mintz bool eth_geneve_enable, bool ip_geneve_enable) 1148464f6645SManish Chopra { 1149da090917STomer Tayar u32 reg_val; 1150464f6645SManish Chopra u8 shift; 1151464f6645SManish Chopra 1152da090917STomer Tayar /* Update PRS register */ 1153464f6645SManish Chopra reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN); 1154464f6645SManish Chopra shift = PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT; 1155da090917STomer Tayar SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, eth_geneve_enable); 1156464f6645SManish Chopra shift = PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT; 1157da090917STomer Tayar SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, shift, ip_geneve_enable); 1158464f6645SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val); 115950bc60cbSMichal Kalderon if (reg_val) { 116050bc60cbSMichal Kalderon reg_val = 116150bc60cbSMichal Kalderon qed_rd(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2); 116250bc60cbSMichal Kalderon 116350bc60cbSMichal Kalderon /* Update output only if tunnel blocks not included. */ 116450bc60cbSMichal Kalderon if (reg_val == (u32)PRS_ETH_OUTPUT_FORMAT) 116550bc60cbSMichal Kalderon qed_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, 116650bc60cbSMichal Kalderon (u32)PRS_ETH_TUNN_OUTPUT_FORMAT); 116750bc60cbSMichal Kalderon } 1168464f6645SManish Chopra 1169da090917STomer Tayar /* Update NIG register */ 1170464f6645SManish Chopra qed_wr(p_hwfn, p_ptt, NIG_REG_NGE_ETH_ENABLE, 1171464f6645SManish Chopra eth_geneve_enable ? 1 : 0); 1172464f6645SManish Chopra qed_wr(p_hwfn, p_ptt, NIG_REG_NGE_IP_ENABLE, ip_geneve_enable ? 1 : 0); 1173464f6645SManish Chopra 1174da090917STomer Tayar /* EDPM with geneve tunnel not supported in BB */ 1175464f6645SManish Chopra if (QED_IS_BB_B0(p_hwfn->cdev)) 1176464f6645SManish Chopra return; 1177464f6645SManish Chopra 1178da090917STomer Tayar /* Update DORQ registers */ 1179da090917STomer Tayar qed_wr(p_hwfn, 1180da090917STomer Tayar p_ptt, 1181da090917STomer Tayar DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2_E5, 1182464f6645SManish Chopra eth_geneve_enable ? 1 : 0); 1183da090917STomer Tayar qed_wr(p_hwfn, 1184da090917STomer Tayar p_ptt, 1185da090917STomer Tayar DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2_E5, 1186464f6645SManish Chopra ip_geneve_enable ? 1 : 0); 1187464f6645SManish Chopra } 1188d51e4af5SChopra, Manish 118963ddca30SMichal Kalderon #define PRS_ETH_VXLAN_NO_L2_ENABLE_OFFSET 3 119063ddca30SMichal Kalderon #define PRS_ETH_VXLAN_NO_L2_OUTPUT_FORMAT -925189872 119150bc60cbSMichal Kalderon 119250bc60cbSMichal Kalderon void qed_set_vxlan_no_l2_enable(struct qed_hwfn *p_hwfn, 119350bc60cbSMichal Kalderon struct qed_ptt *p_ptt, bool enable) 119450bc60cbSMichal Kalderon { 119550bc60cbSMichal Kalderon u32 reg_val, cfg_mask; 119650bc60cbSMichal Kalderon 119750bc60cbSMichal Kalderon /* read PRS config register */ 119850bc60cbSMichal Kalderon reg_val = qed_rd(p_hwfn, p_ptt, PRS_REG_MSG_INFO); 119950bc60cbSMichal Kalderon 120050bc60cbSMichal Kalderon /* set VXLAN_NO_L2_ENABLE mask */ 120150bc60cbSMichal Kalderon cfg_mask = BIT(PRS_ETH_VXLAN_NO_L2_ENABLE_OFFSET); 120250bc60cbSMichal Kalderon 120350bc60cbSMichal Kalderon if (enable) { 120450bc60cbSMichal Kalderon /* set VXLAN_NO_L2_ENABLE flag */ 120550bc60cbSMichal Kalderon reg_val |= cfg_mask; 120650bc60cbSMichal Kalderon 120750bc60cbSMichal Kalderon /* update PRS FIC register */ 120850bc60cbSMichal Kalderon qed_wr(p_hwfn, 120950bc60cbSMichal Kalderon p_ptt, 121050bc60cbSMichal Kalderon PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, 121150bc60cbSMichal Kalderon (u32)PRS_ETH_VXLAN_NO_L2_OUTPUT_FORMAT); 121250bc60cbSMichal Kalderon } else { 121350bc60cbSMichal Kalderon /* clear VXLAN_NO_L2_ENABLE flag */ 121450bc60cbSMichal Kalderon reg_val &= ~cfg_mask; 121550bc60cbSMichal Kalderon } 121650bc60cbSMichal Kalderon 121750bc60cbSMichal Kalderon /* write PRS config register */ 121850bc60cbSMichal Kalderon qed_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, reg_val); 121950bc60cbSMichal Kalderon } 122050bc60cbSMichal Kalderon 12217b6859fbSMintz, Yuval #define T_ETH_PACKET_ACTION_GFT_EVENTID 23 12227b6859fbSMintz, Yuval #define PARSER_ETH_CONN_GFT_ACTION_CM_HDR 272 1223d51e4af5SChopra, Manish #define T_ETH_PACKET_MATCH_RFS_EVENTID 25 12247b6859fbSMintz, Yuval #define PARSER_ETH_CONN_CM_HDR 0 1225d51e4af5SChopra, Manish #define CAM_LINE_SIZE sizeof(u32) 1226d51e4af5SChopra, Manish #define RAM_LINE_SIZE sizeof(u64) 1227d51e4af5SChopra, Manish #define REG_SIZE sizeof(u32) 1228d51e4af5SChopra, Manish 1229da090917STomer Tayar void qed_gft_disable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 pf_id) 1230d51e4af5SChopra, Manish { 1231804c5702SMichal Kalderon struct regpair ram_line = { }; 1232804c5702SMichal Kalderon 1233da090917STomer Tayar /* Disable gft search for PF */ 1234d51e4af5SChopra, Manish qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_GFT, 0); 1235da090917STomer Tayar 1236da090917STomer Tayar /* Clean ram & cam for next gft session */ 1237da090917STomer Tayar 1238da090917STomer Tayar /* Zero camline */ 12397b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id, 0); 1240da090917STomer Tayar 1241da090917STomer Tayar /* Zero ramline */ 12425ab90341SAlexander Lobakin qed_dmae_to_grc(p_hwfn, p_ptt, &ram_line.lo, 1243804c5702SMichal Kalderon PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * pf_id, 1244804c5702SMichal Kalderon sizeof(ram_line) / REG_SIZE); 1245d51e4af5SChopra, Manish } 1246d51e4af5SChopra, Manish 1247da090917STomer Tayar void qed_gft_config(struct qed_hwfn *p_hwfn, 1248da090917STomer Tayar struct qed_ptt *p_ptt, 1249da090917STomer Tayar u16 pf_id, 1250da090917STomer Tayar bool tcp, 1251da090917STomer Tayar bool udp, 1252da090917STomer Tayar bool ipv4, bool ipv6, enum gft_profile_type profile_type) 1253da090917STomer Tayar { 12545ab90341SAlexander Lobakin struct regpair ram_line; 12555ab90341SAlexander Lobakin u32 search_non_ip_as_gft; 12565ab90341SAlexander Lobakin u32 reg_val, cam_line; 12575ab90341SAlexander Lobakin u32 lo = 0, hi = 0; 1258d51e4af5SChopra, Manish 1259d51e4af5SChopra, Manish if (!ipv6 && !ipv4) 1260d51e4af5SChopra, Manish DP_NOTICE(p_hwfn, 1261da090917STomer Tayar "gft_config: must accept at least on of - ipv4 or ipv6'\n"); 1262d51e4af5SChopra, Manish if (!tcp && !udp) 1263d51e4af5SChopra, Manish DP_NOTICE(p_hwfn, 1264da090917STomer Tayar "gft_config: must accept at least on of - udp or tcp\n"); 1265da090917STomer Tayar if (profile_type >= MAX_GFT_PROFILE_TYPE) 1266da090917STomer Tayar DP_NOTICE(p_hwfn, "gft_config: unsupported gft_profile_type\n"); 1267d51e4af5SChopra, Manish 1268da090917STomer Tayar /* Set RFS event ID to be awakened i Tstorm By Prs */ 1269da090917STomer Tayar reg_val = T_ETH_PACKET_MATCH_RFS_EVENTID << 1270d51e4af5SChopra, Manish PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT; 1271da090917STomer Tayar reg_val |= PARSER_ETH_CONN_CM_HDR << PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT; 1272da090917STomer Tayar qed_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, reg_val); 1273d51e4af5SChopra, Manish 1274da090917STomer Tayar /* Do not load context only cid in PRS on match. */ 1275d51e4af5SChopra, Manish qed_wr(p_hwfn, p_ptt, PRS_REG_LOAD_L2_FILTER, 0); 1276d51e4af5SChopra, Manish 1277da090917STomer Tayar /* Do not use tenant ID exist bit for gft search */ 1278da090917STomer Tayar qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TENANT_ID, 0); 1279d51e4af5SChopra, Manish 1280da090917STomer Tayar /* Set Cam */ 1281da090917STomer Tayar cam_line = 0; 1282da090917STomer Tayar SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_VALID, 1); 1283da090917STomer Tayar 1284da090917STomer Tayar /* Filters are per PF!! */ 1285da090917STomer Tayar SET_FIELD(cam_line, 12867b6859fbSMintz, Yuval GFT_CAM_LINE_MAPPED_PF_ID_MASK, 12877b6859fbSMintz, Yuval GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK); 1288da090917STomer Tayar SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_PF_ID, pf_id); 1289da090917STomer Tayar 1290d51e4af5SChopra, Manish if (!(tcp && udp)) { 1291da090917STomer Tayar SET_FIELD(cam_line, 12927b6859fbSMintz, Yuval GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK, 12937b6859fbSMintz, Yuval GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK); 1294d51e4af5SChopra, Manish if (tcp) 1295da090917STomer Tayar SET_FIELD(cam_line, 1296d51e4af5SChopra, Manish GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE, 1297d51e4af5SChopra, Manish GFT_PROFILE_TCP_PROTOCOL); 1298d51e4af5SChopra, Manish else 1299da090917STomer Tayar SET_FIELD(cam_line, 1300d51e4af5SChopra, Manish GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE, 1301d51e4af5SChopra, Manish GFT_PROFILE_UDP_PROTOCOL); 1302d51e4af5SChopra, Manish } 1303d51e4af5SChopra, Manish 1304d51e4af5SChopra, Manish if (!(ipv4 && ipv6)) { 1305da090917STomer Tayar SET_FIELD(cam_line, GFT_CAM_LINE_MAPPED_IP_VERSION_MASK, 1); 1306d51e4af5SChopra, Manish if (ipv4) 1307da090917STomer Tayar SET_FIELD(cam_line, 1308d51e4af5SChopra, Manish GFT_CAM_LINE_MAPPED_IP_VERSION, 1309d51e4af5SChopra, Manish GFT_PROFILE_IPV4); 1310d51e4af5SChopra, Manish else 1311da090917STomer Tayar SET_FIELD(cam_line, 1312d51e4af5SChopra, Manish GFT_CAM_LINE_MAPPED_IP_VERSION, 1313d51e4af5SChopra, Manish GFT_PROFILE_IPV6); 1314d51e4af5SChopra, Manish } 1315d51e4af5SChopra, Manish 13167b6859fbSMintz, Yuval /* Write characteristics to cam */ 1317d51e4af5SChopra, Manish qed_wr(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id, 1318da090917STomer Tayar cam_line); 1319da090917STomer Tayar cam_line = 1320da090917STomer Tayar qed_rd(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE * pf_id); 1321d51e4af5SChopra, Manish 13227b6859fbSMintz, Yuval /* Write line to RAM - compare to filter 4 tuple */ 1323d51e4af5SChopra, Manish 1324d52c89f1SMichal Kalderon /* Search no IP as GFT */ 1325d52c89f1SMichal Kalderon search_non_ip_as_gft = 0; 1326d52c89f1SMichal Kalderon 132750bc60cbSMichal Kalderon /* Tunnel type */ 13285ab90341SAlexander Lobakin SET_FIELD(lo, GFT_RAM_LINE_TUNNEL_DST_PORT, 1); 13295ab90341SAlexander Lobakin SET_FIELD(lo, GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL, 1); 133050bc60cbSMichal Kalderon 1331da090917STomer Tayar if (profile_type == GFT_PROFILE_TYPE_4_TUPLE) { 13325ab90341SAlexander Lobakin SET_FIELD(hi, GFT_RAM_LINE_DST_IP, 1); 13335ab90341SAlexander Lobakin SET_FIELD(hi, GFT_RAM_LINE_SRC_IP, 1); 13345ab90341SAlexander Lobakin SET_FIELD(hi, GFT_RAM_LINE_OVER_IP_PROTOCOL, 1); 13355ab90341SAlexander Lobakin SET_FIELD(lo, GFT_RAM_LINE_ETHERTYPE, 1); 13365ab90341SAlexander Lobakin SET_FIELD(lo, GFT_RAM_LINE_SRC_PORT, 1); 13375ab90341SAlexander Lobakin SET_FIELD(lo, GFT_RAM_LINE_DST_PORT, 1); 1338da090917STomer Tayar } else if (profile_type == GFT_PROFILE_TYPE_L4_DST_PORT) { 13395ab90341SAlexander Lobakin SET_FIELD(hi, GFT_RAM_LINE_OVER_IP_PROTOCOL, 1); 13405ab90341SAlexander Lobakin SET_FIELD(lo, GFT_RAM_LINE_ETHERTYPE, 1); 13415ab90341SAlexander Lobakin SET_FIELD(lo, GFT_RAM_LINE_DST_PORT, 1); 134250bc60cbSMichal Kalderon } else if (profile_type == GFT_PROFILE_TYPE_IP_DST_ADDR) { 13435ab90341SAlexander Lobakin SET_FIELD(hi, GFT_RAM_LINE_DST_IP, 1); 13445ab90341SAlexander Lobakin SET_FIELD(lo, GFT_RAM_LINE_ETHERTYPE, 1); 134550bc60cbSMichal Kalderon } else if (profile_type == GFT_PROFILE_TYPE_IP_SRC_ADDR) { 13465ab90341SAlexander Lobakin SET_FIELD(hi, GFT_RAM_LINE_SRC_IP, 1); 13475ab90341SAlexander Lobakin SET_FIELD(lo, GFT_RAM_LINE_ETHERTYPE, 1); 134850bc60cbSMichal Kalderon } else if (profile_type == GFT_PROFILE_TYPE_TUNNEL_TYPE) { 13495ab90341SAlexander Lobakin SET_FIELD(lo, GFT_RAM_LINE_TUNNEL_ETHERTYPE, 1); 1350d52c89f1SMichal Kalderon 1351d52c89f1SMichal Kalderon /* Allow tunneled traffic without inner IP */ 1352d52c89f1SMichal Kalderon search_non_ip_as_gft = 1; 1353da090917STomer Tayar } 1354da090917STomer Tayar 13555ab90341SAlexander Lobakin ram_line.lo = cpu_to_le32(lo); 13565ab90341SAlexander Lobakin ram_line.hi = cpu_to_le32(hi); 13575ab90341SAlexander Lobakin 1358da090917STomer Tayar qed_wr(p_hwfn, 1359d52c89f1SMichal Kalderon p_ptt, PRS_REG_SEARCH_NON_IP_AS_GFT, search_non_ip_as_gft); 13605ab90341SAlexander Lobakin qed_dmae_to_grc(p_hwfn, p_ptt, &ram_line.lo, 13617b6859fbSMintz, Yuval PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * pf_id, 1362804c5702SMichal Kalderon sizeof(ram_line) / REG_SIZE); 13637b6859fbSMintz, Yuval 13647b6859fbSMintz, Yuval /* Set default profile so that no filter match will happen */ 13655ab90341SAlexander Lobakin ram_line.lo = cpu_to_le32(0xffffffff); 13665ab90341SAlexander Lobakin ram_line.hi = cpu_to_le32(0x3ff); 13675ab90341SAlexander Lobakin qed_dmae_to_grc(p_hwfn, p_ptt, &ram_line.lo, 1368da090917STomer Tayar PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE * 1369804c5702SMichal Kalderon PRS_GFT_CAM_LINES_NO_MATCH, 1370804c5702SMichal Kalderon sizeof(ram_line) / REG_SIZE); 1371da090917STomer Tayar 1372da090917STomer Tayar /* Enable gft search */ 1373da090917STomer Tayar qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_GFT, 1); 1374da090917STomer Tayar } 1375da090917STomer Tayar 1376da090917STomer Tayar DECLARE_CRC8_TABLE(cdu_crc8_table); 1377da090917STomer Tayar 1378da090917STomer Tayar /* Calculate and return CDU validation byte per connection type/region/cid */ 1379da090917STomer Tayar static u8 qed_calc_cdu_validation_byte(u8 conn_type, u8 region, u32 cid) 1380da090917STomer Tayar { 1381da090917STomer Tayar const u8 validation_cfg = CDU_VALIDATION_DEFAULT_CFG; 1382da090917STomer Tayar u8 crc, validation_byte = 0; 1383da090917STomer Tayar static u8 crc8_table_valid; /* automatically initialized to 0 */ 1384da090917STomer Tayar u32 validation_string = 0; 13855ab90341SAlexander Lobakin __be32 data_to_crc; 1386da090917STomer Tayar 1387da090917STomer Tayar if (!crc8_table_valid) { 1388da090917STomer Tayar crc8_populate_msb(cdu_crc8_table, 0x07); 1389da090917STomer Tayar crc8_table_valid = 1; 1390da090917STomer Tayar } 1391da090917STomer Tayar 1392da090917STomer Tayar /* The CRC is calculated on the String-to-compress: 1393da090917STomer Tayar * [31:8] = {CID[31:20],CID[11:0]} 1394da090917STomer Tayar * [7:4] = Region 1395da090917STomer Tayar * [3:0] = Type 1396da090917STomer Tayar */ 1397da090917STomer Tayar if ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_USE_CID) & 1) 1398da090917STomer Tayar validation_string |= (cid & 0xFFF00000) | ((cid & 0xFFF) << 8); 1399da090917STomer Tayar 1400da090917STomer Tayar if ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_USE_REGION) & 1) 1401da090917STomer Tayar validation_string |= ((region & 0xF) << 4); 1402da090917STomer Tayar 1403da090917STomer Tayar if ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_USE_TYPE) & 1) 1404da090917STomer Tayar validation_string |= (conn_type & 0xF); 1405da090917STomer Tayar 1406da090917STomer Tayar /* Convert to big-endian and calculate CRC8 */ 14075ab90341SAlexander Lobakin data_to_crc = cpu_to_be32(validation_string); 14085ab90341SAlexander Lobakin crc = crc8(cdu_crc8_table, (u8 *)&data_to_crc, sizeof(data_to_crc), 14095ab90341SAlexander Lobakin CRC8_INIT_VALUE); 1410da090917STomer Tayar 1411da090917STomer Tayar /* The validation byte [7:0] is composed: 1412da090917STomer Tayar * for type A validation 1413da090917STomer Tayar * [7] = active configuration bit 1414da090917STomer Tayar * [6:0] = crc[6:0] 1415da090917STomer Tayar * 1416da090917STomer Tayar * for type B validation 1417da090917STomer Tayar * [7] = active configuration bit 1418da090917STomer Tayar * [6:3] = connection_type[3:0] 1419da090917STomer Tayar * [2:0] = crc[2:0] 1420da090917STomer Tayar */ 1421da090917STomer Tayar validation_byte |= 1422da090917STomer Tayar ((validation_cfg >> 1423da090917STomer Tayar CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE) & 1) << 7; 1424da090917STomer Tayar 1425da090917STomer Tayar if ((validation_cfg >> 1426da090917STomer Tayar CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT) & 1) 1427da090917STomer Tayar validation_byte |= ((conn_type & 0xF) << 3) | (crc & 0x7); 1428da090917STomer Tayar else 1429da090917STomer Tayar validation_byte |= crc & 0x7F; 1430da090917STomer Tayar 1431da090917STomer Tayar return validation_byte; 1432da090917STomer Tayar } 1433da090917STomer Tayar 1434da090917STomer Tayar /* Calcualte and set validation bytes for session context */ 1435da090917STomer Tayar void qed_calc_session_ctx_validation(void *p_ctx_mem, 1436da090917STomer Tayar u16 ctx_size, u8 ctx_type, u32 cid) 1437da090917STomer Tayar { 1438da090917STomer Tayar u8 *x_val_ptr, *t_val_ptr, *u_val_ptr, *p_ctx; 1439da090917STomer Tayar 1440da090917STomer Tayar p_ctx = (u8 * const)p_ctx_mem; 1441da090917STomer Tayar x_val_ptr = &p_ctx[con_region_offsets[0][ctx_type]]; 1442da090917STomer Tayar t_val_ptr = &p_ctx[con_region_offsets[1][ctx_type]]; 1443da090917STomer Tayar u_val_ptr = &p_ctx[con_region_offsets[2][ctx_type]]; 1444da090917STomer Tayar 1445da090917STomer Tayar memset(p_ctx, 0, ctx_size); 1446da090917STomer Tayar 1447da090917STomer Tayar *x_val_ptr = qed_calc_cdu_validation_byte(ctx_type, 3, cid); 1448da090917STomer Tayar *t_val_ptr = qed_calc_cdu_validation_byte(ctx_type, 4, cid); 1449da090917STomer Tayar *u_val_ptr = qed_calc_cdu_validation_byte(ctx_type, 5, cid); 1450da090917STomer Tayar } 1451da090917STomer Tayar 1452da090917STomer Tayar /* Calcualte and set validation bytes for task context */ 1453da090917STomer Tayar void qed_calc_task_ctx_validation(void *p_ctx_mem, 1454da090917STomer Tayar u16 ctx_size, u8 ctx_type, u32 tid) 1455da090917STomer Tayar { 1456da090917STomer Tayar u8 *p_ctx, *region1_val_ptr; 1457da090917STomer Tayar 1458da090917STomer Tayar p_ctx = (u8 * const)p_ctx_mem; 1459da090917STomer Tayar region1_val_ptr = &p_ctx[task_region_offsets[0][ctx_type]]; 1460da090917STomer Tayar 1461da090917STomer Tayar memset(p_ctx, 0, ctx_size); 1462da090917STomer Tayar 1463da090917STomer Tayar *region1_val_ptr = qed_calc_cdu_validation_byte(ctx_type, 1, tid); 1464da090917STomer Tayar } 1465da090917STomer Tayar 1466da090917STomer Tayar /* Memset session context to 0 while preserving validation bytes */ 1467da090917STomer Tayar void qed_memset_session_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type) 1468da090917STomer Tayar { 1469da090917STomer Tayar u8 *x_val_ptr, *t_val_ptr, *u_val_ptr, *p_ctx; 1470da090917STomer Tayar u8 x_val, t_val, u_val; 1471da090917STomer Tayar 1472da090917STomer Tayar p_ctx = (u8 * const)p_ctx_mem; 1473da090917STomer Tayar x_val_ptr = &p_ctx[con_region_offsets[0][ctx_type]]; 1474da090917STomer Tayar t_val_ptr = &p_ctx[con_region_offsets[1][ctx_type]]; 1475da090917STomer Tayar u_val_ptr = &p_ctx[con_region_offsets[2][ctx_type]]; 1476da090917STomer Tayar 1477da090917STomer Tayar x_val = *x_val_ptr; 1478da090917STomer Tayar t_val = *t_val_ptr; 1479da090917STomer Tayar u_val = *u_val_ptr; 1480da090917STomer Tayar 1481da090917STomer Tayar memset(p_ctx, 0, ctx_size); 1482da090917STomer Tayar 1483da090917STomer Tayar *x_val_ptr = x_val; 1484da090917STomer Tayar *t_val_ptr = t_val; 1485da090917STomer Tayar *u_val_ptr = u_val; 1486da090917STomer Tayar } 1487da090917STomer Tayar 1488da090917STomer Tayar /* Memset task context to 0 while preserving validation bytes */ 1489da090917STomer Tayar void qed_memset_task_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type) 1490da090917STomer Tayar { 1491da090917STomer Tayar u8 *p_ctx, *region1_val_ptr; 1492da090917STomer Tayar u8 region1_val; 1493da090917STomer Tayar 1494da090917STomer Tayar p_ctx = (u8 * const)p_ctx_mem; 1495da090917STomer Tayar region1_val_ptr = &p_ctx[task_region_offsets[0][ctx_type]]; 1496da090917STomer Tayar 1497da090917STomer Tayar region1_val = *region1_val_ptr; 1498da090917STomer Tayar 1499da090917STomer Tayar memset(p_ctx, 0, ctx_size); 1500da090917STomer Tayar 1501da090917STomer Tayar *region1_val_ptr = region1_val; 1502da090917STomer Tayar } 1503da090917STomer Tayar 1504da090917STomer Tayar /* Enable and configure context validation */ 1505da090917STomer Tayar void qed_enable_context_validation(struct qed_hwfn *p_hwfn, 1506da090917STomer Tayar struct qed_ptt *p_ptt) 1507da090917STomer Tayar { 1508da090917STomer Tayar u32 ctx_validation; 1509da090917STomer Tayar 1510da090917STomer Tayar /* Enable validation for connection region 3: CCFC_CTX_VALID0[31:24] */ 1511da090917STomer Tayar ctx_validation = CDU_VALIDATION_DEFAULT_CFG << 24; 1512da090917STomer Tayar qed_wr(p_hwfn, p_ptt, CDU_REG_CCFC_CTX_VALID0, ctx_validation); 1513da090917STomer Tayar 1514da090917STomer Tayar /* Enable validation for connection region 5: CCFC_CTX_VALID1[15:8] */ 1515da090917STomer Tayar ctx_validation = CDU_VALIDATION_DEFAULT_CFG << 8; 1516da090917STomer Tayar qed_wr(p_hwfn, p_ptt, CDU_REG_CCFC_CTX_VALID1, ctx_validation); 1517da090917STomer Tayar 1518da090917STomer Tayar /* Enable validation for connection region 1: TCFC_CTX_VALID0[15:8] */ 1519da090917STomer Tayar ctx_validation = CDU_VALIDATION_DEFAULT_CFG << 8; 1520da090917STomer Tayar qed_wr(p_hwfn, p_ptt, CDU_REG_TCFC_CTX_VALID0, ctx_validation); 1521d51e4af5SChopra, Manish } 1522d52c89f1SMichal Kalderon 1523d52c89f1SMichal Kalderon static u32 qed_get_rdma_assert_ram_addr(struct qed_hwfn *p_hwfn, u8 storm_id) 1524d52c89f1SMichal Kalderon { 1525d52c89f1SMichal Kalderon switch (storm_id) { 1526d52c89f1SMichal Kalderon case 0: 1527d52c89f1SMichal Kalderon return TSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + 1528d52c89f1SMichal Kalderon TSTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id); 1529d52c89f1SMichal Kalderon case 1: 1530d52c89f1SMichal Kalderon return MSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + 1531d52c89f1SMichal Kalderon MSTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id); 1532d52c89f1SMichal Kalderon case 2: 1533d52c89f1SMichal Kalderon return USEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + 1534d52c89f1SMichal Kalderon USTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id); 1535d52c89f1SMichal Kalderon case 3: 1536d52c89f1SMichal Kalderon return XSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + 1537d52c89f1SMichal Kalderon XSTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id); 1538d52c89f1SMichal Kalderon case 4: 1539d52c89f1SMichal Kalderon return YSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + 1540d52c89f1SMichal Kalderon YSTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id); 1541d52c89f1SMichal Kalderon case 5: 1542d52c89f1SMichal Kalderon return PSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + 1543d52c89f1SMichal Kalderon PSTORM_RDMA_ASSERT_LEVEL_OFFSET(p_hwfn->rel_pf_id); 1544d52c89f1SMichal Kalderon 1545d52c89f1SMichal Kalderon default: 1546d52c89f1SMichal Kalderon return 0; 1547d52c89f1SMichal Kalderon } 1548d52c89f1SMichal Kalderon } 1549d52c89f1SMichal Kalderon 1550d52c89f1SMichal Kalderon void qed_set_rdma_error_level(struct qed_hwfn *p_hwfn, 1551d52c89f1SMichal Kalderon struct qed_ptt *p_ptt, 1552d52c89f1SMichal Kalderon u8 assert_level[NUM_STORMS]) 1553d52c89f1SMichal Kalderon { 1554d52c89f1SMichal Kalderon u8 storm_id; 1555d52c89f1SMichal Kalderon 1556d52c89f1SMichal Kalderon for (storm_id = 0; storm_id < NUM_STORMS; storm_id++) { 1557d52c89f1SMichal Kalderon u32 ram_addr = qed_get_rdma_assert_ram_addr(p_hwfn, storm_id); 1558d52c89f1SMichal Kalderon 1559d52c89f1SMichal Kalderon qed_wr(p_hwfn, p_ptt, ram_addr, assert_level[storm_id]); 1560d52c89f1SMichal Kalderon } 1561d52c89f1SMichal Kalderon } 156230d5f858SMichal Kalderon 156330d5f858SMichal Kalderon #define PHYS_ADDR_DWORDS DIV_ROUND_UP(sizeof(dma_addr_t), 4) 156430d5f858SMichal Kalderon #define OVERLAY_HDR_SIZE_DWORDS (sizeof(struct fw_overlay_buf_hdr) / 4) 156530d5f858SMichal Kalderon 156630d5f858SMichal Kalderon static u32 qed_get_overlay_addr_ram_addr(struct qed_hwfn *p_hwfn, u8 storm_id) 156730d5f858SMichal Kalderon { 156830d5f858SMichal Kalderon switch (storm_id) { 156930d5f858SMichal Kalderon case 0: 157030d5f858SMichal Kalderon return TSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + 157130d5f858SMichal Kalderon TSTORM_OVERLAY_BUF_ADDR_OFFSET; 157230d5f858SMichal Kalderon case 1: 157330d5f858SMichal Kalderon return MSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + 157430d5f858SMichal Kalderon MSTORM_OVERLAY_BUF_ADDR_OFFSET; 157530d5f858SMichal Kalderon case 2: 157630d5f858SMichal Kalderon return USEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + 157730d5f858SMichal Kalderon USTORM_OVERLAY_BUF_ADDR_OFFSET; 157830d5f858SMichal Kalderon case 3: 157930d5f858SMichal Kalderon return XSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + 158030d5f858SMichal Kalderon XSTORM_OVERLAY_BUF_ADDR_OFFSET; 158130d5f858SMichal Kalderon case 4: 158230d5f858SMichal Kalderon return YSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + 158330d5f858SMichal Kalderon YSTORM_OVERLAY_BUF_ADDR_OFFSET; 158430d5f858SMichal Kalderon case 5: 158530d5f858SMichal Kalderon return PSEM_REG_FAST_MEMORY + SEM_FAST_REG_INT_RAM + 158630d5f858SMichal Kalderon PSTORM_OVERLAY_BUF_ADDR_OFFSET; 158730d5f858SMichal Kalderon 158830d5f858SMichal Kalderon default: 158930d5f858SMichal Kalderon return 0; 159030d5f858SMichal Kalderon } 159130d5f858SMichal Kalderon } 159230d5f858SMichal Kalderon 159330d5f858SMichal Kalderon struct phys_mem_desc *qed_fw_overlay_mem_alloc(struct qed_hwfn *p_hwfn, 159430d5f858SMichal Kalderon const u32 * const 159530d5f858SMichal Kalderon fw_overlay_in_buf, 159630d5f858SMichal Kalderon u32 buf_size_in_bytes) 159730d5f858SMichal Kalderon { 159830d5f858SMichal Kalderon u32 buf_size = buf_size_in_bytes / sizeof(u32), buf_offset = 0; 159930d5f858SMichal Kalderon struct phys_mem_desc *allocated_mem; 160030d5f858SMichal Kalderon 160130d5f858SMichal Kalderon if (!buf_size) 160230d5f858SMichal Kalderon return NULL; 160330d5f858SMichal Kalderon 160430d5f858SMichal Kalderon allocated_mem = kcalloc(NUM_STORMS, sizeof(struct phys_mem_desc), 160530d5f858SMichal Kalderon GFP_KERNEL); 160630d5f858SMichal Kalderon if (!allocated_mem) 160730d5f858SMichal Kalderon return NULL; 160830d5f858SMichal Kalderon 160930d5f858SMichal Kalderon memset(allocated_mem, 0, NUM_STORMS * sizeof(struct phys_mem_desc)); 161030d5f858SMichal Kalderon 161130d5f858SMichal Kalderon /* For each Storm, set physical address in RAM */ 161230d5f858SMichal Kalderon while (buf_offset < buf_size) { 161330d5f858SMichal Kalderon struct phys_mem_desc *storm_mem_desc; 161430d5f858SMichal Kalderon struct fw_overlay_buf_hdr *hdr; 161530d5f858SMichal Kalderon u32 storm_buf_size; 161630d5f858SMichal Kalderon u8 storm_id; 161730d5f858SMichal Kalderon 161830d5f858SMichal Kalderon hdr = 161930d5f858SMichal Kalderon (struct fw_overlay_buf_hdr *)&fw_overlay_in_buf[buf_offset]; 162030d5f858SMichal Kalderon storm_buf_size = GET_FIELD(hdr->data, 162130d5f858SMichal Kalderon FW_OVERLAY_BUF_HDR_BUF_SIZE); 162230d5f858SMichal Kalderon storm_id = GET_FIELD(hdr->data, FW_OVERLAY_BUF_HDR_STORM_ID); 162330d5f858SMichal Kalderon storm_mem_desc = allocated_mem + storm_id; 162430d5f858SMichal Kalderon storm_mem_desc->size = storm_buf_size * sizeof(u32); 162530d5f858SMichal Kalderon 162630d5f858SMichal Kalderon /* Allocate physical memory for Storm's overlays buffer */ 162730d5f858SMichal Kalderon storm_mem_desc->virt_addr = 162830d5f858SMichal Kalderon dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 162930d5f858SMichal Kalderon storm_mem_desc->size, 163030d5f858SMichal Kalderon &storm_mem_desc->phys_addr, GFP_KERNEL); 163130d5f858SMichal Kalderon if (!storm_mem_desc->virt_addr) 163230d5f858SMichal Kalderon break; 163330d5f858SMichal Kalderon 163430d5f858SMichal Kalderon /* Skip overlays buffer header */ 163530d5f858SMichal Kalderon buf_offset += OVERLAY_HDR_SIZE_DWORDS; 163630d5f858SMichal Kalderon 163730d5f858SMichal Kalderon /* Copy Storm's overlays buffer to allocated memory */ 163830d5f858SMichal Kalderon memcpy(storm_mem_desc->virt_addr, 163930d5f858SMichal Kalderon &fw_overlay_in_buf[buf_offset], storm_mem_desc->size); 164030d5f858SMichal Kalderon 164130d5f858SMichal Kalderon /* Advance to next Storm */ 164230d5f858SMichal Kalderon buf_offset += storm_buf_size; 164330d5f858SMichal Kalderon } 164430d5f858SMichal Kalderon 164530d5f858SMichal Kalderon /* If memory allocation has failed, free all allocated memory */ 164630d5f858SMichal Kalderon if (buf_offset < buf_size) { 164730d5f858SMichal Kalderon qed_fw_overlay_mem_free(p_hwfn, allocated_mem); 164830d5f858SMichal Kalderon return NULL; 164930d5f858SMichal Kalderon } 165030d5f858SMichal Kalderon 165130d5f858SMichal Kalderon return allocated_mem; 165230d5f858SMichal Kalderon } 165330d5f858SMichal Kalderon 165430d5f858SMichal Kalderon void qed_fw_overlay_init_ram(struct qed_hwfn *p_hwfn, 165530d5f858SMichal Kalderon struct qed_ptt *p_ptt, 165630d5f858SMichal Kalderon struct phys_mem_desc *fw_overlay_mem) 165730d5f858SMichal Kalderon { 165830d5f858SMichal Kalderon u8 storm_id; 165930d5f858SMichal Kalderon 166030d5f858SMichal Kalderon for (storm_id = 0; storm_id < NUM_STORMS; storm_id++) { 166130d5f858SMichal Kalderon struct phys_mem_desc *storm_mem_desc = 166230d5f858SMichal Kalderon (struct phys_mem_desc *)fw_overlay_mem + storm_id; 166330d5f858SMichal Kalderon u32 ram_addr, i; 166430d5f858SMichal Kalderon 166530d5f858SMichal Kalderon /* Skip Storms with no FW overlays */ 166630d5f858SMichal Kalderon if (!storm_mem_desc->virt_addr) 166730d5f858SMichal Kalderon continue; 166830d5f858SMichal Kalderon 166930d5f858SMichal Kalderon /* Calculate overlay RAM GRC address of current PF */ 167030d5f858SMichal Kalderon ram_addr = qed_get_overlay_addr_ram_addr(p_hwfn, storm_id) + 167130d5f858SMichal Kalderon sizeof(dma_addr_t) * p_hwfn->rel_pf_id; 167230d5f858SMichal Kalderon 167330d5f858SMichal Kalderon /* Write Storm's overlay physical address to RAM */ 167430d5f858SMichal Kalderon for (i = 0; i < PHYS_ADDR_DWORDS; i++, ram_addr += sizeof(u32)) 167530d5f858SMichal Kalderon qed_wr(p_hwfn, p_ptt, ram_addr, 167630d5f858SMichal Kalderon ((u32 *)&storm_mem_desc->phys_addr)[i]); 167730d5f858SMichal Kalderon } 167830d5f858SMichal Kalderon } 167930d5f858SMichal Kalderon 168030d5f858SMichal Kalderon void qed_fw_overlay_mem_free(struct qed_hwfn *p_hwfn, 168130d5f858SMichal Kalderon struct phys_mem_desc *fw_overlay_mem) 168230d5f858SMichal Kalderon { 168330d5f858SMichal Kalderon u8 storm_id; 168430d5f858SMichal Kalderon 168530d5f858SMichal Kalderon if (!fw_overlay_mem) 168630d5f858SMichal Kalderon return; 168730d5f858SMichal Kalderon 168830d5f858SMichal Kalderon for (storm_id = 0; storm_id < NUM_STORMS; storm_id++) { 168930d5f858SMichal Kalderon struct phys_mem_desc *storm_mem_desc = 169030d5f858SMichal Kalderon (struct phys_mem_desc *)fw_overlay_mem + storm_id; 169130d5f858SMichal Kalderon 169230d5f858SMichal Kalderon /* Free Storm's physical memory */ 169330d5f858SMichal Kalderon if (storm_mem_desc->virt_addr) 169430d5f858SMichal Kalderon dma_free_coherent(&p_hwfn->cdev->pdev->dev, 169530d5f858SMichal Kalderon storm_mem_desc->size, 169630d5f858SMichal Kalderon storm_mem_desc->virt_addr, 169730d5f858SMichal Kalderon storm_mem_desc->phys_addr); 169830d5f858SMichal Kalderon } 169930d5f858SMichal Kalderon 170030d5f858SMichal Kalderon /* Free allocated virtual memory */ 170130d5f858SMichal Kalderon kfree(fw_overlay_mem); 170230d5f858SMichal Kalderon } 1703