1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #include <linux/types.h> 34fe56b9e6SYuval Mintz #include <linux/io.h> 35fe56b9e6SYuval Mintz #include <linux/delay.h> 36fe56b9e6SYuval Mintz #include <linux/dma-mapping.h> 37fe56b9e6SYuval Mintz #include <linux/errno.h> 38fe56b9e6SYuval Mintz #include <linux/kernel.h> 39fe56b9e6SYuval Mintz #include <linux/list.h> 40fe56b9e6SYuval Mintz #include <linux/mutex.h> 41fe56b9e6SYuval Mintz #include <linux/pci.h> 42fe56b9e6SYuval Mintz #include <linux/slab.h> 43fe56b9e6SYuval Mintz #include <linux/spinlock.h> 44fe56b9e6SYuval Mintz #include <linux/string.h> 45fe56b9e6SYuval Mintz #include <linux/qed/qed_chain.h> 46fe56b9e6SYuval Mintz #include "qed.h" 47fe56b9e6SYuval Mintz #include "qed_hsi.h" 48fe56b9e6SYuval Mintz #include "qed_hw.h" 49fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 501408cc1fSYuval Mintz #include "qed_sriov.h" 51fe56b9e6SYuval Mintz 52fe56b9e6SYuval Mintz #define QED_BAR_ACQUIRE_TIMEOUT 1000 53fe56b9e6SYuval Mintz 54fe56b9e6SYuval Mintz /* Invalid values */ 55fe56b9e6SYuval Mintz #define QED_BAR_INVALID_OFFSET (cpu_to_le32(-1)) 56fe56b9e6SYuval Mintz 57fe56b9e6SYuval Mintz struct qed_ptt { 58fe56b9e6SYuval Mintz struct list_head list_entry; 59fe56b9e6SYuval Mintz unsigned int idx; 60fe56b9e6SYuval Mintz struct pxp_ptt_entry pxp; 613a50d351SMintz, Yuval u8 hwfn_id; 62fe56b9e6SYuval Mintz }; 63fe56b9e6SYuval Mintz 64fe56b9e6SYuval Mintz struct qed_ptt_pool { 65fe56b9e6SYuval Mintz struct list_head free_list; 66fe56b9e6SYuval Mintz spinlock_t lock; /* ptt synchronized access */ 67fe56b9e6SYuval Mintz struct qed_ptt ptts[PXP_EXTERNAL_BAR_PF_WINDOW_NUM]; 68fe56b9e6SYuval Mintz }; 69fe56b9e6SYuval Mintz 70fe56b9e6SYuval Mintz int qed_ptt_pool_alloc(struct qed_hwfn *p_hwfn) 71fe56b9e6SYuval Mintz { 721a635e48SYuval Mintz struct qed_ptt_pool *p_pool = kmalloc(sizeof(*p_pool), GFP_KERNEL); 73fe56b9e6SYuval Mintz int i; 74fe56b9e6SYuval Mintz 75fe56b9e6SYuval Mintz if (!p_pool) 76fe56b9e6SYuval Mintz return -ENOMEM; 77fe56b9e6SYuval Mintz 78fe56b9e6SYuval Mintz INIT_LIST_HEAD(&p_pool->free_list); 79fe56b9e6SYuval Mintz for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) { 80fe56b9e6SYuval Mintz p_pool->ptts[i].idx = i; 81fe56b9e6SYuval Mintz p_pool->ptts[i].pxp.offset = QED_BAR_INVALID_OFFSET; 82fe56b9e6SYuval Mintz p_pool->ptts[i].pxp.pretend.control = 0; 833a50d351SMintz, Yuval p_pool->ptts[i].hwfn_id = p_hwfn->my_id; 84fe56b9e6SYuval Mintz if (i >= RESERVED_PTT_MAX) 85fe56b9e6SYuval Mintz list_add(&p_pool->ptts[i].list_entry, 86fe56b9e6SYuval Mintz &p_pool->free_list); 87fe56b9e6SYuval Mintz } 88fe56b9e6SYuval Mintz 89fe56b9e6SYuval Mintz p_hwfn->p_ptt_pool = p_pool; 90fe56b9e6SYuval Mintz spin_lock_init(&p_pool->lock); 91fe56b9e6SYuval Mintz 92fe56b9e6SYuval Mintz return 0; 93fe56b9e6SYuval Mintz } 94fe56b9e6SYuval Mintz 95fe56b9e6SYuval Mintz void qed_ptt_invalidate(struct qed_hwfn *p_hwfn) 96fe56b9e6SYuval Mintz { 97fe56b9e6SYuval Mintz struct qed_ptt *p_ptt; 98fe56b9e6SYuval Mintz int i; 99fe56b9e6SYuval Mintz 100fe56b9e6SYuval Mintz for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) { 101fe56b9e6SYuval Mintz p_ptt = &p_hwfn->p_ptt_pool->ptts[i]; 102fe56b9e6SYuval Mintz p_ptt->pxp.offset = QED_BAR_INVALID_OFFSET; 103fe56b9e6SYuval Mintz } 104fe56b9e6SYuval Mintz } 105fe56b9e6SYuval Mintz 106fe56b9e6SYuval Mintz void qed_ptt_pool_free(struct qed_hwfn *p_hwfn) 107fe56b9e6SYuval Mintz { 108fe56b9e6SYuval Mintz kfree(p_hwfn->p_ptt_pool); 109fe56b9e6SYuval Mintz p_hwfn->p_ptt_pool = NULL; 110fe56b9e6SYuval Mintz } 111fe56b9e6SYuval Mintz 112fe56b9e6SYuval Mintz struct qed_ptt *qed_ptt_acquire(struct qed_hwfn *p_hwfn) 113fe56b9e6SYuval Mintz { 114fe56b9e6SYuval Mintz struct qed_ptt *p_ptt; 115fe56b9e6SYuval Mintz unsigned int i; 116fe56b9e6SYuval Mintz 117fe56b9e6SYuval Mintz /* Take the free PTT from the list */ 118fe56b9e6SYuval Mintz for (i = 0; i < QED_BAR_ACQUIRE_TIMEOUT; i++) { 119fe56b9e6SYuval Mintz spin_lock_bh(&p_hwfn->p_ptt_pool->lock); 120fe56b9e6SYuval Mintz 121fe56b9e6SYuval Mintz if (!list_empty(&p_hwfn->p_ptt_pool->free_list)) { 122fe56b9e6SYuval Mintz p_ptt = list_first_entry(&p_hwfn->p_ptt_pool->free_list, 123fe56b9e6SYuval Mintz struct qed_ptt, list_entry); 124fe56b9e6SYuval Mintz list_del(&p_ptt->list_entry); 125fe56b9e6SYuval Mintz 126fe56b9e6SYuval Mintz spin_unlock_bh(&p_hwfn->p_ptt_pool->lock); 127fe56b9e6SYuval Mintz 128fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 129fe56b9e6SYuval Mintz "allocated ptt %d\n", p_ptt->idx); 130fe56b9e6SYuval Mintz return p_ptt; 131fe56b9e6SYuval Mintz } 132fe56b9e6SYuval Mintz 133fe56b9e6SYuval Mintz spin_unlock_bh(&p_hwfn->p_ptt_pool->lock); 134fe56b9e6SYuval Mintz usleep_range(1000, 2000); 135fe56b9e6SYuval Mintz } 136fe56b9e6SYuval Mintz 137fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "PTT acquire timeout - failed to allocate PTT\n"); 138fe56b9e6SYuval Mintz return NULL; 139fe56b9e6SYuval Mintz } 140fe56b9e6SYuval Mintz 1411a635e48SYuval Mintz void qed_ptt_release(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 142fe56b9e6SYuval Mintz { 143fe56b9e6SYuval Mintz spin_lock_bh(&p_hwfn->p_ptt_pool->lock); 144fe56b9e6SYuval Mintz list_add(&p_ptt->list_entry, &p_hwfn->p_ptt_pool->free_list); 145fe56b9e6SYuval Mintz spin_unlock_bh(&p_hwfn->p_ptt_pool->lock); 146fe56b9e6SYuval Mintz } 147fe56b9e6SYuval Mintz 1481a635e48SYuval Mintz u32 qed_ptt_get_hw_addr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 149fe56b9e6SYuval Mintz { 150fe56b9e6SYuval Mintz /* The HW is using DWORDS and we need to translate it to Bytes */ 151fe56b9e6SYuval Mintz return le32_to_cpu(p_ptt->pxp.offset) << 2; 152fe56b9e6SYuval Mintz } 153fe56b9e6SYuval Mintz 154fe56b9e6SYuval Mintz static u32 qed_ptt_config_addr(struct qed_ptt *p_ptt) 155fe56b9e6SYuval Mintz { 156fe56b9e6SYuval Mintz return PXP_PF_WINDOW_ADMIN_PER_PF_START + 157fe56b9e6SYuval Mintz p_ptt->idx * sizeof(struct pxp_ptt_entry); 158fe56b9e6SYuval Mintz } 159fe56b9e6SYuval Mintz 160fe56b9e6SYuval Mintz u32 qed_ptt_get_bar_addr(struct qed_ptt *p_ptt) 161fe56b9e6SYuval Mintz { 162fe56b9e6SYuval Mintz return PXP_EXTERNAL_BAR_PF_WINDOW_START + 163fe56b9e6SYuval Mintz p_ptt->idx * PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE; 164fe56b9e6SYuval Mintz } 165fe56b9e6SYuval Mintz 166fe56b9e6SYuval Mintz void qed_ptt_set_win(struct qed_hwfn *p_hwfn, 1671a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 new_hw_addr) 168fe56b9e6SYuval Mintz { 169fe56b9e6SYuval Mintz u32 prev_hw_addr; 170fe56b9e6SYuval Mintz 171fe56b9e6SYuval Mintz prev_hw_addr = qed_ptt_get_hw_addr(p_hwfn, p_ptt); 172fe56b9e6SYuval Mintz 173fe56b9e6SYuval Mintz if (new_hw_addr == prev_hw_addr) 174fe56b9e6SYuval Mintz return; 175fe56b9e6SYuval Mintz 176fe56b9e6SYuval Mintz /* Update PTT entery in admin window */ 177fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 178fe56b9e6SYuval Mintz "Updating PTT entry %d to offset 0x%x\n", 179fe56b9e6SYuval Mintz p_ptt->idx, new_hw_addr); 180fe56b9e6SYuval Mintz 181fe56b9e6SYuval Mintz /* The HW is using DWORDS and the address is in Bytes */ 182fe56b9e6SYuval Mintz p_ptt->pxp.offset = cpu_to_le32(new_hw_addr >> 2); 183fe56b9e6SYuval Mintz 184fe56b9e6SYuval Mintz REG_WR(p_hwfn, 185fe56b9e6SYuval Mintz qed_ptt_config_addr(p_ptt) + 186fe56b9e6SYuval Mintz offsetof(struct pxp_ptt_entry, offset), 187fe56b9e6SYuval Mintz le32_to_cpu(p_ptt->pxp.offset)); 188fe56b9e6SYuval Mintz } 189fe56b9e6SYuval Mintz 190fe56b9e6SYuval Mintz static u32 qed_set_ptt(struct qed_hwfn *p_hwfn, 1911a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 hw_addr) 192fe56b9e6SYuval Mintz { 193fe56b9e6SYuval Mintz u32 win_hw_addr = qed_ptt_get_hw_addr(p_hwfn, p_ptt); 194fe56b9e6SYuval Mintz u32 offset; 195fe56b9e6SYuval Mintz 196fe56b9e6SYuval Mintz offset = hw_addr - win_hw_addr; 197fe56b9e6SYuval Mintz 1983a50d351SMintz, Yuval if (p_ptt->hwfn_id != p_hwfn->my_id) 1993a50d351SMintz, Yuval DP_NOTICE(p_hwfn, 2003a50d351SMintz, Yuval "ptt[%d] of hwfn[%02x] is used by hwfn[%02x]!\n", 2013a50d351SMintz, Yuval p_ptt->idx, p_ptt->hwfn_id, p_hwfn->my_id); 2023a50d351SMintz, Yuval 203fe56b9e6SYuval Mintz /* Verify the address is within the window */ 204fe56b9e6SYuval Mintz if (hw_addr < win_hw_addr || 205fe56b9e6SYuval Mintz offset >= PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) { 206fe56b9e6SYuval Mintz qed_ptt_set_win(p_hwfn, p_ptt, hw_addr); 207fe56b9e6SYuval Mintz offset = 0; 208fe56b9e6SYuval Mintz } 209fe56b9e6SYuval Mintz 210fe56b9e6SYuval Mintz return qed_ptt_get_bar_addr(p_ptt) + offset; 211fe56b9e6SYuval Mintz } 212fe56b9e6SYuval Mintz 213fe56b9e6SYuval Mintz struct qed_ptt *qed_get_reserved_ptt(struct qed_hwfn *p_hwfn, 214fe56b9e6SYuval Mintz enum reserved_ptts ptt_idx) 215fe56b9e6SYuval Mintz { 216fe56b9e6SYuval Mintz if (ptt_idx >= RESERVED_PTT_MAX) { 217fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 218fe56b9e6SYuval Mintz "Requested PTT %d is out of range\n", ptt_idx); 219fe56b9e6SYuval Mintz return NULL; 220fe56b9e6SYuval Mintz } 221fe56b9e6SYuval Mintz 222fe56b9e6SYuval Mintz return &p_hwfn->p_ptt_pool->ptts[ptt_idx]; 223fe56b9e6SYuval Mintz } 224fe56b9e6SYuval Mintz 225fe56b9e6SYuval Mintz void qed_wr(struct qed_hwfn *p_hwfn, 226fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 227fe56b9e6SYuval Mintz u32 hw_addr, u32 val) 228fe56b9e6SYuval Mintz { 229fe56b9e6SYuval Mintz u32 bar_addr = qed_set_ptt(p_hwfn, p_ptt, hw_addr); 230fe56b9e6SYuval Mintz 231fe56b9e6SYuval Mintz REG_WR(p_hwfn, bar_addr, val); 232fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 233fe56b9e6SYuval Mintz "bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n", 234fe56b9e6SYuval Mintz bar_addr, hw_addr, val); 235fe56b9e6SYuval Mintz } 236fe56b9e6SYuval Mintz 237fe56b9e6SYuval Mintz u32 qed_rd(struct qed_hwfn *p_hwfn, 238fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 239fe56b9e6SYuval Mintz u32 hw_addr) 240fe56b9e6SYuval Mintz { 241fe56b9e6SYuval Mintz u32 bar_addr = qed_set_ptt(p_hwfn, p_ptt, hw_addr); 242fe56b9e6SYuval Mintz u32 val = REG_RD(p_hwfn, bar_addr); 243fe56b9e6SYuval Mintz 244fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 245fe56b9e6SYuval Mintz "bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n", 246fe56b9e6SYuval Mintz bar_addr, hw_addr, val); 247fe56b9e6SYuval Mintz 248fe56b9e6SYuval Mintz return val; 249fe56b9e6SYuval Mintz } 250fe56b9e6SYuval Mintz 251fe56b9e6SYuval Mintz static void qed_memcpy_hw(struct qed_hwfn *p_hwfn, 252fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2531a635e48SYuval Mintz void *addr, u32 hw_addr, size_t n, bool to_device) 254fe56b9e6SYuval Mintz { 255fe56b9e6SYuval Mintz u32 dw_count, *host_addr, hw_offset; 256fe56b9e6SYuval Mintz size_t quota, done = 0; 257fe56b9e6SYuval Mintz u32 __iomem *reg_addr; 258fe56b9e6SYuval Mintz 259fe56b9e6SYuval Mintz while (done < n) { 260fe56b9e6SYuval Mintz quota = min_t(size_t, n - done, 261fe56b9e6SYuval Mintz PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE); 262fe56b9e6SYuval Mintz 2631408cc1fSYuval Mintz if (IS_PF(p_hwfn->cdev)) { 264fe56b9e6SYuval Mintz qed_ptt_set_win(p_hwfn, p_ptt, hw_addr + done); 265fe56b9e6SYuval Mintz hw_offset = qed_ptt_get_bar_addr(p_ptt); 2661408cc1fSYuval Mintz } else { 2671408cc1fSYuval Mintz hw_offset = hw_addr + done; 2681408cc1fSYuval Mintz } 269fe56b9e6SYuval Mintz 270fe56b9e6SYuval Mintz dw_count = quota / 4; 271fe56b9e6SYuval Mintz host_addr = (u32 *)((u8 *)addr + done); 272fe56b9e6SYuval Mintz reg_addr = (u32 __iomem *)REG_ADDR(p_hwfn, hw_offset); 273fe56b9e6SYuval Mintz if (to_device) 274fe56b9e6SYuval Mintz while (dw_count--) 275fe56b9e6SYuval Mintz DIRECT_REG_WR(reg_addr++, *host_addr++); 276fe56b9e6SYuval Mintz else 277fe56b9e6SYuval Mintz while (dw_count--) 278fe56b9e6SYuval Mintz *host_addr++ = DIRECT_REG_RD(reg_addr++); 279fe56b9e6SYuval Mintz 280fe56b9e6SYuval Mintz done += quota; 281fe56b9e6SYuval Mintz } 282fe56b9e6SYuval Mintz } 283fe56b9e6SYuval Mintz 284fe56b9e6SYuval Mintz void qed_memcpy_from(struct qed_hwfn *p_hwfn, 2851a635e48SYuval Mintz struct qed_ptt *p_ptt, void *dest, u32 hw_addr, size_t n) 286fe56b9e6SYuval Mintz { 287fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 288fe56b9e6SYuval Mintz "hw_addr 0x%x, dest %p hw_addr 0x%x, size %lu\n", 289fe56b9e6SYuval Mintz hw_addr, dest, hw_addr, (unsigned long)n); 290fe56b9e6SYuval Mintz 291fe56b9e6SYuval Mintz qed_memcpy_hw(p_hwfn, p_ptt, dest, hw_addr, n, false); 292fe56b9e6SYuval Mintz } 293fe56b9e6SYuval Mintz 294fe56b9e6SYuval Mintz void qed_memcpy_to(struct qed_hwfn *p_hwfn, 2951a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 hw_addr, void *src, size_t n) 296fe56b9e6SYuval Mintz { 297fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 298fe56b9e6SYuval Mintz "hw_addr 0x%x, hw_addr 0x%x, src %p size %lu\n", 299fe56b9e6SYuval Mintz hw_addr, hw_addr, src, (unsigned long)n); 300fe56b9e6SYuval Mintz 301fe56b9e6SYuval Mintz qed_memcpy_hw(p_hwfn, p_ptt, src, hw_addr, n, true); 302fe56b9e6SYuval Mintz } 303fe56b9e6SYuval Mintz 3041a635e48SYuval Mintz void qed_fid_pretend(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 fid) 305fe56b9e6SYuval Mintz { 306fe56b9e6SYuval Mintz u16 control = 0; 307fe56b9e6SYuval Mintz 308fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_IS_CONCRETE, 1); 309fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_FUNCTION, 1); 310fe56b9e6SYuval Mintz 311fe56b9e6SYuval Mintz /* Every pretend undos previous pretends, including 312fe56b9e6SYuval Mintz * previous port pretend. 313fe56b9e6SYuval Mintz */ 314fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0); 315fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0); 316fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1); 317fe56b9e6SYuval Mintz 318fe56b9e6SYuval Mintz if (!GET_FIELD(fid, PXP_CONCRETE_FID_VFVALID)) 319fe56b9e6SYuval Mintz fid = GET_FIELD(fid, PXP_CONCRETE_FID_PFID); 320fe56b9e6SYuval Mintz 321fe56b9e6SYuval Mintz p_ptt->pxp.pretend.control = cpu_to_le16(control); 322fe56b9e6SYuval Mintz p_ptt->pxp.pretend.fid.concrete_fid.fid = cpu_to_le16(fid); 323fe56b9e6SYuval Mintz 324fe56b9e6SYuval Mintz REG_WR(p_hwfn, 325fe56b9e6SYuval Mintz qed_ptt_config_addr(p_ptt) + 326fe56b9e6SYuval Mintz offsetof(struct pxp_ptt_entry, pretend), 327fe56b9e6SYuval Mintz *(u32 *)&p_ptt->pxp.pretend); 328fe56b9e6SYuval Mintz } 329fe56b9e6SYuval Mintz 330fe56b9e6SYuval Mintz void qed_port_pretend(struct qed_hwfn *p_hwfn, 3311a635e48SYuval Mintz struct qed_ptt *p_ptt, u8 port_id) 332fe56b9e6SYuval Mintz { 333fe56b9e6SYuval Mintz u16 control = 0; 334fe56b9e6SYuval Mintz 335fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PORT, port_id); 336fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 1); 337fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1); 338fe56b9e6SYuval Mintz 339fe56b9e6SYuval Mintz p_ptt->pxp.pretend.control = cpu_to_le16(control); 340fe56b9e6SYuval Mintz 341fe56b9e6SYuval Mintz REG_WR(p_hwfn, 342fe56b9e6SYuval Mintz qed_ptt_config_addr(p_ptt) + 343fe56b9e6SYuval Mintz offsetof(struct pxp_ptt_entry, pretend), 344fe56b9e6SYuval Mintz *(u32 *)&p_ptt->pxp.pretend); 345fe56b9e6SYuval Mintz } 346fe56b9e6SYuval Mintz 3471a635e48SYuval Mintz void qed_port_unpretend(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 348fe56b9e6SYuval Mintz { 349fe56b9e6SYuval Mintz u16 control = 0; 350fe56b9e6SYuval Mintz 351fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0); 352fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0); 353fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1); 354fe56b9e6SYuval Mintz 355fe56b9e6SYuval Mintz p_ptt->pxp.pretend.control = cpu_to_le16(control); 356fe56b9e6SYuval Mintz 357fe56b9e6SYuval Mintz REG_WR(p_hwfn, 358fe56b9e6SYuval Mintz qed_ptt_config_addr(p_ptt) + 359fe56b9e6SYuval Mintz offsetof(struct pxp_ptt_entry, pretend), 360fe56b9e6SYuval Mintz *(u32 *)&p_ptt->pxp.pretend); 361fe56b9e6SYuval Mintz } 362fe56b9e6SYuval Mintz 36332a47e72SYuval Mintz u32 qed_vfid_to_concrete(struct qed_hwfn *p_hwfn, u8 vfid) 36432a47e72SYuval Mintz { 36532a47e72SYuval Mintz u32 concrete_fid = 0; 36632a47e72SYuval Mintz 36732a47e72SYuval Mintz SET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID, p_hwfn->rel_pf_id); 36832a47e72SYuval Mintz SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID, vfid); 36932a47e72SYuval Mintz SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID, 1); 37032a47e72SYuval Mintz 37132a47e72SYuval Mintz return concrete_fid; 37232a47e72SYuval Mintz } 37332a47e72SYuval Mintz 374fe56b9e6SYuval Mintz /* DMAE */ 375fe56b9e6SYuval Mintz static void qed_dmae_opcode(struct qed_hwfn *p_hwfn, 376fe56b9e6SYuval Mintz const u8 is_src_type_grc, 377fe56b9e6SYuval Mintz const u8 is_dst_type_grc, 378fe56b9e6SYuval Mintz struct qed_dmae_params *p_params) 379fe56b9e6SYuval Mintz { 38037bff2b9SYuval Mintz u16 opcode_b = 0; 381fe56b9e6SYuval Mintz u32 opcode = 0; 382fe56b9e6SYuval Mintz 383fe56b9e6SYuval Mintz /* Whether the source is the PCIe or the GRC. 384fe56b9e6SYuval Mintz * 0- The source is the PCIe 385fe56b9e6SYuval Mintz * 1- The source is the GRC. 386fe56b9e6SYuval Mintz */ 387fe56b9e6SYuval Mintz opcode |= (is_src_type_grc ? DMAE_CMD_SRC_MASK_GRC 388fe56b9e6SYuval Mintz : DMAE_CMD_SRC_MASK_PCIE) << 389fe56b9e6SYuval Mintz DMAE_CMD_SRC_SHIFT; 390fe56b9e6SYuval Mintz opcode |= ((p_hwfn->rel_pf_id & DMAE_CMD_SRC_PF_ID_MASK) << 391fe56b9e6SYuval Mintz DMAE_CMD_SRC_PF_ID_SHIFT); 392fe56b9e6SYuval Mintz 393fe56b9e6SYuval Mintz /* The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */ 394fe56b9e6SYuval Mintz opcode |= (is_dst_type_grc ? DMAE_CMD_DST_MASK_GRC 395fe56b9e6SYuval Mintz : DMAE_CMD_DST_MASK_PCIE) << 396fe56b9e6SYuval Mintz DMAE_CMD_DST_SHIFT; 397fe56b9e6SYuval Mintz opcode |= ((p_hwfn->rel_pf_id & DMAE_CMD_DST_PF_ID_MASK) << 398fe56b9e6SYuval Mintz DMAE_CMD_DST_PF_ID_SHIFT); 399fe56b9e6SYuval Mintz 400fe56b9e6SYuval Mintz /* Whether to write a completion word to the completion destination: 401fe56b9e6SYuval Mintz * 0-Do not write a completion word 402fe56b9e6SYuval Mintz * 1-Write the completion word 403fe56b9e6SYuval Mintz */ 404fe56b9e6SYuval Mintz opcode |= (DMAE_CMD_COMP_WORD_EN_MASK << DMAE_CMD_COMP_WORD_EN_SHIFT); 405fe56b9e6SYuval Mintz opcode |= (DMAE_CMD_SRC_ADDR_RESET_MASK << 406fe56b9e6SYuval Mintz DMAE_CMD_SRC_ADDR_RESET_SHIFT); 407fe56b9e6SYuval Mintz 408fe56b9e6SYuval Mintz if (p_params->flags & QED_DMAE_FLAG_COMPLETION_DST) 409fe56b9e6SYuval Mintz opcode |= (1 << DMAE_CMD_COMP_FUNC_SHIFT); 410fe56b9e6SYuval Mintz 411fe56b9e6SYuval Mintz opcode |= (DMAE_CMD_ENDIANITY << DMAE_CMD_ENDIANITY_MODE_SHIFT); 412fe56b9e6SYuval Mintz 413fe56b9e6SYuval Mintz opcode |= ((p_hwfn->port_id) << DMAE_CMD_PORT_ID_SHIFT); 414fe56b9e6SYuval Mintz 415fe56b9e6SYuval Mintz /* reset source address in next go */ 416fe56b9e6SYuval Mintz opcode |= (DMAE_CMD_SRC_ADDR_RESET_MASK << 417fe56b9e6SYuval Mintz DMAE_CMD_SRC_ADDR_RESET_SHIFT); 418fe56b9e6SYuval Mintz 419fe56b9e6SYuval Mintz /* reset dest address in next go */ 420fe56b9e6SYuval Mintz opcode |= (DMAE_CMD_DST_ADDR_RESET_MASK << 421fe56b9e6SYuval Mintz DMAE_CMD_DST_ADDR_RESET_SHIFT); 422fe56b9e6SYuval Mintz 42337bff2b9SYuval Mintz /* SRC/DST VFID: all 1's - pf, otherwise VF id */ 42437bff2b9SYuval Mintz if (p_params->flags & QED_DMAE_FLAG_VF_SRC) { 42537bff2b9SYuval Mintz opcode |= 1 << DMAE_CMD_SRC_VF_ID_VALID_SHIFT; 42637bff2b9SYuval Mintz opcode_b |= p_params->src_vfid << DMAE_CMD_SRC_VF_ID_SHIFT; 42737bff2b9SYuval Mintz } else { 42837bff2b9SYuval Mintz opcode_b |= DMAE_CMD_SRC_VF_ID_MASK << 42937bff2b9SYuval Mintz DMAE_CMD_SRC_VF_ID_SHIFT; 43037bff2b9SYuval Mintz } 431fe56b9e6SYuval Mintz 43237bff2b9SYuval Mintz if (p_params->flags & QED_DMAE_FLAG_VF_DST) { 43337bff2b9SYuval Mintz opcode |= 1 << DMAE_CMD_DST_VF_ID_VALID_SHIFT; 43437bff2b9SYuval Mintz opcode_b |= p_params->dst_vfid << DMAE_CMD_DST_VF_ID_SHIFT; 43537bff2b9SYuval Mintz } else { 43637bff2b9SYuval Mintz opcode_b |= DMAE_CMD_DST_VF_ID_MASK << DMAE_CMD_DST_VF_ID_SHIFT; 43737bff2b9SYuval Mintz } 438fe56b9e6SYuval Mintz 439fe56b9e6SYuval Mintz p_hwfn->dmae_info.p_dmae_cmd->opcode = cpu_to_le32(opcode); 44037bff2b9SYuval Mintz p_hwfn->dmae_info.p_dmae_cmd->opcode_b = cpu_to_le16(opcode_b); 441fe56b9e6SYuval Mintz } 442fe56b9e6SYuval Mintz 443fe56b9e6SYuval Mintz u32 qed_dmae_idx_to_go_cmd(u8 idx) 444fe56b9e6SYuval Mintz { 445fe56b9e6SYuval Mintz /* All the DMAE 'go' registers form an array in internal memory */ 446fe56b9e6SYuval Mintz return DMAE_REG_GO_C0 + (idx << 2); 447fe56b9e6SYuval Mintz } 448fe56b9e6SYuval Mintz 4491a635e48SYuval Mintz static int qed_dmae_post_command(struct qed_hwfn *p_hwfn, 450fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 451fe56b9e6SYuval Mintz { 4521a635e48SYuval Mintz struct dmae_cmd *p_command = p_hwfn->dmae_info.p_dmae_cmd; 453fe56b9e6SYuval Mintz u8 idx_cmd = p_hwfn->dmae_info.channel, i; 454fe56b9e6SYuval Mintz int qed_status = 0; 455fe56b9e6SYuval Mintz 456fe56b9e6SYuval Mintz /* verify address is not NULL */ 4571a635e48SYuval Mintz if ((((!p_command->dst_addr_lo) && (!p_command->dst_addr_hi)) || 4581a635e48SYuval Mintz ((!p_command->src_addr_lo) && (!p_command->src_addr_hi)))) { 459fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 460fe56b9e6SYuval Mintz "source or destination address 0 idx_cmd=%d\n" 461fe56b9e6SYuval Mintz "opcode = [0x%08x,0x%04x] len=0x%x src=0x%x:%x dst=0x%x:%x\n", 462fe56b9e6SYuval Mintz idx_cmd, 4631a635e48SYuval Mintz le32_to_cpu(p_command->opcode), 4641a635e48SYuval Mintz le16_to_cpu(p_command->opcode_b), 4651a635e48SYuval Mintz le16_to_cpu(p_command->length_dw), 4661a635e48SYuval Mintz le32_to_cpu(p_command->src_addr_hi), 4671a635e48SYuval Mintz le32_to_cpu(p_command->src_addr_lo), 4681a635e48SYuval Mintz le32_to_cpu(p_command->dst_addr_hi), 4691a635e48SYuval Mintz le32_to_cpu(p_command->dst_addr_lo)); 470fe56b9e6SYuval Mintz 471fe56b9e6SYuval Mintz return -EINVAL; 472fe56b9e6SYuval Mintz } 473fe56b9e6SYuval Mintz 474fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, 475fe56b9e6SYuval Mintz NETIF_MSG_HW, 476fe56b9e6SYuval Mintz "Posting DMAE command [idx %d]: opcode = [0x%08x,0x%04x] len=0x%x src=0x%x:%x dst=0x%x:%x\n", 477fe56b9e6SYuval Mintz idx_cmd, 4781a635e48SYuval Mintz le32_to_cpu(p_command->opcode), 4791a635e48SYuval Mintz le16_to_cpu(p_command->opcode_b), 4801a635e48SYuval Mintz le16_to_cpu(p_command->length_dw), 4811a635e48SYuval Mintz le32_to_cpu(p_command->src_addr_hi), 4821a635e48SYuval Mintz le32_to_cpu(p_command->src_addr_lo), 4831a635e48SYuval Mintz le32_to_cpu(p_command->dst_addr_hi), 4841a635e48SYuval Mintz le32_to_cpu(p_command->dst_addr_lo)); 485fe56b9e6SYuval Mintz 486fe56b9e6SYuval Mintz /* Copy the command to DMAE - need to do it before every call 487fe56b9e6SYuval Mintz * for source/dest address no reset. 488fe56b9e6SYuval Mintz * The first 9 DWs are the command registers, the 10 DW is the 489fe56b9e6SYuval Mintz * GO register, and the rest are result registers 490fe56b9e6SYuval Mintz * (which are read only by the client). 491fe56b9e6SYuval Mintz */ 492fe56b9e6SYuval Mintz for (i = 0; i < DMAE_CMD_SIZE; i++) { 493fe56b9e6SYuval Mintz u32 data = (i < DMAE_CMD_SIZE_TO_FILL) ? 4941a635e48SYuval Mintz *(((u32 *)p_command) + i) : 0; 495fe56b9e6SYuval Mintz 496fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 497fe56b9e6SYuval Mintz DMAE_REG_CMD_MEM + 498fe56b9e6SYuval Mintz (idx_cmd * DMAE_CMD_SIZE * sizeof(u32)) + 499fe56b9e6SYuval Mintz (i * sizeof(u32)), data); 500fe56b9e6SYuval Mintz } 501fe56b9e6SYuval Mintz 5021a635e48SYuval Mintz qed_wr(p_hwfn, p_ptt, qed_dmae_idx_to_go_cmd(idx_cmd), DMAE_GO_VALUE); 503fe56b9e6SYuval Mintz 504fe56b9e6SYuval Mintz return qed_status; 505fe56b9e6SYuval Mintz } 506fe56b9e6SYuval Mintz 507fe56b9e6SYuval Mintz int qed_dmae_info_alloc(struct qed_hwfn *p_hwfn) 508fe56b9e6SYuval Mintz { 509fe56b9e6SYuval Mintz dma_addr_t *p_addr = &p_hwfn->dmae_info.completion_word_phys_addr; 510fe56b9e6SYuval Mintz struct dmae_cmd **p_cmd = &p_hwfn->dmae_info.p_dmae_cmd; 511fe56b9e6SYuval Mintz u32 **p_buff = &p_hwfn->dmae_info.p_intermediate_buffer; 512fe56b9e6SYuval Mintz u32 **p_comp = &p_hwfn->dmae_info.p_completion_word; 513fe56b9e6SYuval Mintz 514fe56b9e6SYuval Mintz *p_comp = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 5151a635e48SYuval Mintz sizeof(u32), p_addr, GFP_KERNEL); 5162591c280SJoe Perches if (!*p_comp) 517fe56b9e6SYuval Mintz goto err; 518fe56b9e6SYuval Mintz 519fe56b9e6SYuval Mintz p_addr = &p_hwfn->dmae_info.dmae_cmd_phys_addr; 520fe56b9e6SYuval Mintz *p_cmd = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 521fe56b9e6SYuval Mintz sizeof(struct dmae_cmd), 522fe56b9e6SYuval Mintz p_addr, GFP_KERNEL); 5232591c280SJoe Perches if (!*p_cmd) 524fe56b9e6SYuval Mintz goto err; 525fe56b9e6SYuval Mintz 526fe56b9e6SYuval Mintz p_addr = &p_hwfn->dmae_info.intermediate_buffer_phys_addr; 527fe56b9e6SYuval Mintz *p_buff = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 528fe56b9e6SYuval Mintz sizeof(u32) * DMAE_MAX_RW_SIZE, 529fe56b9e6SYuval Mintz p_addr, GFP_KERNEL); 5302591c280SJoe Perches if (!*p_buff) 531fe56b9e6SYuval Mintz goto err; 532fe56b9e6SYuval Mintz 533fe56b9e6SYuval Mintz p_hwfn->dmae_info.channel = p_hwfn->rel_pf_id; 534fe56b9e6SYuval Mintz 535fe56b9e6SYuval Mintz return 0; 536fe56b9e6SYuval Mintz err: 537fe56b9e6SYuval Mintz qed_dmae_info_free(p_hwfn); 538fe56b9e6SYuval Mintz return -ENOMEM; 539fe56b9e6SYuval Mintz } 540fe56b9e6SYuval Mintz 541fe56b9e6SYuval Mintz void qed_dmae_info_free(struct qed_hwfn *p_hwfn) 542fe56b9e6SYuval Mintz { 543fe56b9e6SYuval Mintz dma_addr_t p_phys; 544fe56b9e6SYuval Mintz 545fe56b9e6SYuval Mintz /* Just make sure no one is in the middle */ 546fe56b9e6SYuval Mintz mutex_lock(&p_hwfn->dmae_info.mutex); 547fe56b9e6SYuval Mintz 548fe56b9e6SYuval Mintz if (p_hwfn->dmae_info.p_completion_word) { 549fe56b9e6SYuval Mintz p_phys = p_hwfn->dmae_info.completion_word_phys_addr; 550fe56b9e6SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 551fe56b9e6SYuval Mintz sizeof(u32), 5521a635e48SYuval Mintz p_hwfn->dmae_info.p_completion_word, p_phys); 553fe56b9e6SYuval Mintz p_hwfn->dmae_info.p_completion_word = NULL; 554fe56b9e6SYuval Mintz } 555fe56b9e6SYuval Mintz 556fe56b9e6SYuval Mintz if (p_hwfn->dmae_info.p_dmae_cmd) { 557fe56b9e6SYuval Mintz p_phys = p_hwfn->dmae_info.dmae_cmd_phys_addr; 558fe56b9e6SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 559fe56b9e6SYuval Mintz sizeof(struct dmae_cmd), 5601a635e48SYuval Mintz p_hwfn->dmae_info.p_dmae_cmd, p_phys); 561fe56b9e6SYuval Mintz p_hwfn->dmae_info.p_dmae_cmd = NULL; 562fe56b9e6SYuval Mintz } 563fe56b9e6SYuval Mintz 564fe56b9e6SYuval Mintz if (p_hwfn->dmae_info.p_intermediate_buffer) { 565fe56b9e6SYuval Mintz p_phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr; 566fe56b9e6SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 567fe56b9e6SYuval Mintz sizeof(u32) * DMAE_MAX_RW_SIZE, 568fe56b9e6SYuval Mintz p_hwfn->dmae_info.p_intermediate_buffer, 569fe56b9e6SYuval Mintz p_phys); 570fe56b9e6SYuval Mintz p_hwfn->dmae_info.p_intermediate_buffer = NULL; 571fe56b9e6SYuval Mintz } 572fe56b9e6SYuval Mintz 573fe56b9e6SYuval Mintz mutex_unlock(&p_hwfn->dmae_info.mutex); 574fe56b9e6SYuval Mintz } 575fe56b9e6SYuval Mintz 576fe56b9e6SYuval Mintz static int qed_dmae_operation_wait(struct qed_hwfn *p_hwfn) 577fe56b9e6SYuval Mintz { 5781a635e48SYuval Mintz u32 wait_cnt_limit = 10000, wait_cnt = 0; 579fe56b9e6SYuval Mintz int qed_status = 0; 580fe56b9e6SYuval Mintz 581fe56b9e6SYuval Mintz barrier(); 582fe56b9e6SYuval Mintz while (*p_hwfn->dmae_info.p_completion_word != DMAE_COMPLETION_VAL) { 583fe56b9e6SYuval Mintz udelay(DMAE_MIN_WAIT_TIME); 584fe56b9e6SYuval Mintz if (++wait_cnt > wait_cnt_limit) { 585fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn->cdev, 586fe56b9e6SYuval Mintz "Timed-out waiting for operation to complete. Completion word is 0x%08x expected 0x%08x.\n", 587fe56b9e6SYuval Mintz *p_hwfn->dmae_info.p_completion_word, 588fe56b9e6SYuval Mintz DMAE_COMPLETION_VAL); 589fe56b9e6SYuval Mintz qed_status = -EBUSY; 590fe56b9e6SYuval Mintz break; 591fe56b9e6SYuval Mintz } 592fe56b9e6SYuval Mintz 593fe56b9e6SYuval Mintz /* to sync the completion_word since we are not 594fe56b9e6SYuval Mintz * using the volatile keyword for p_completion_word 595fe56b9e6SYuval Mintz */ 596fe56b9e6SYuval Mintz barrier(); 597fe56b9e6SYuval Mintz } 598fe56b9e6SYuval Mintz 599fe56b9e6SYuval Mintz if (qed_status == 0) 600fe56b9e6SYuval Mintz *p_hwfn->dmae_info.p_completion_word = 0; 601fe56b9e6SYuval Mintz 602fe56b9e6SYuval Mintz return qed_status; 603fe56b9e6SYuval Mintz } 604fe56b9e6SYuval Mintz 605fe56b9e6SYuval Mintz static int qed_dmae_execute_sub_operation(struct qed_hwfn *p_hwfn, 606fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 607fe56b9e6SYuval Mintz u64 src_addr, 608fe56b9e6SYuval Mintz u64 dst_addr, 609fe56b9e6SYuval Mintz u8 src_type, 610fe56b9e6SYuval Mintz u8 dst_type, 6111a635e48SYuval Mintz u32 length_dw) 612fe56b9e6SYuval Mintz { 613fe56b9e6SYuval Mintz dma_addr_t phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr; 614fe56b9e6SYuval Mintz struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd; 615fe56b9e6SYuval Mintz int qed_status = 0; 616fe56b9e6SYuval Mintz 617fe56b9e6SYuval Mintz switch (src_type) { 618fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_GRC: 619fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_HOST_PHYS: 620fe56b9e6SYuval Mintz cmd->src_addr_hi = cpu_to_le32(upper_32_bits(src_addr)); 621fe56b9e6SYuval Mintz cmd->src_addr_lo = cpu_to_le32(lower_32_bits(src_addr)); 622fe56b9e6SYuval Mintz break; 623fe56b9e6SYuval Mintz /* for virtual source addresses we use the intermediate buffer. */ 624fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_HOST_VIRT: 625fe56b9e6SYuval Mintz cmd->src_addr_hi = cpu_to_le32(upper_32_bits(phys)); 626fe56b9e6SYuval Mintz cmd->src_addr_lo = cpu_to_le32(lower_32_bits(phys)); 627fe56b9e6SYuval Mintz memcpy(&p_hwfn->dmae_info.p_intermediate_buffer[0], 628fe56b9e6SYuval Mintz (void *)(uintptr_t)src_addr, 6291a635e48SYuval Mintz length_dw * sizeof(u32)); 630fe56b9e6SYuval Mintz break; 631fe56b9e6SYuval Mintz default: 632fe56b9e6SYuval Mintz return -EINVAL; 633fe56b9e6SYuval Mintz } 634fe56b9e6SYuval Mintz 635fe56b9e6SYuval Mintz switch (dst_type) { 636fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_GRC: 637fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_HOST_PHYS: 638fe56b9e6SYuval Mintz cmd->dst_addr_hi = cpu_to_le32(upper_32_bits(dst_addr)); 639fe56b9e6SYuval Mintz cmd->dst_addr_lo = cpu_to_le32(lower_32_bits(dst_addr)); 640fe56b9e6SYuval Mintz break; 641fe56b9e6SYuval Mintz /* for virtual source addresses we use the intermediate buffer. */ 642fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_HOST_VIRT: 643fe56b9e6SYuval Mintz cmd->dst_addr_hi = cpu_to_le32(upper_32_bits(phys)); 644fe56b9e6SYuval Mintz cmd->dst_addr_lo = cpu_to_le32(lower_32_bits(phys)); 645fe56b9e6SYuval Mintz break; 646fe56b9e6SYuval Mintz default: 647fe56b9e6SYuval Mintz return -EINVAL; 648fe56b9e6SYuval Mintz } 649fe56b9e6SYuval Mintz 6501a635e48SYuval Mintz cmd->length_dw = cpu_to_le16((u16)length_dw); 651fe56b9e6SYuval Mintz 652fe56b9e6SYuval Mintz qed_dmae_post_command(p_hwfn, p_ptt); 653fe56b9e6SYuval Mintz 654fe56b9e6SYuval Mintz qed_status = qed_dmae_operation_wait(p_hwfn); 655fe56b9e6SYuval Mintz 656fe56b9e6SYuval Mintz if (qed_status) { 657fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 658fe56b9e6SYuval Mintz "qed_dmae_host2grc: Wait Failed. source_addr 0x%llx, grc_addr 0x%llx, size_in_dwords 0x%x\n", 6591a635e48SYuval Mintz src_addr, dst_addr, length_dw); 660fe56b9e6SYuval Mintz return qed_status; 661fe56b9e6SYuval Mintz } 662fe56b9e6SYuval Mintz 663fe56b9e6SYuval Mintz if (dst_type == QED_DMAE_ADDRESS_HOST_VIRT) 664fe56b9e6SYuval Mintz memcpy((void *)(uintptr_t)(dst_addr), 665fe56b9e6SYuval Mintz &p_hwfn->dmae_info.p_intermediate_buffer[0], 6661a635e48SYuval Mintz length_dw * sizeof(u32)); 667fe56b9e6SYuval Mintz 668fe56b9e6SYuval Mintz return 0; 669fe56b9e6SYuval Mintz } 670fe56b9e6SYuval Mintz 671fe56b9e6SYuval Mintz static int qed_dmae_execute_command(struct qed_hwfn *p_hwfn, 672fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 673fe56b9e6SYuval Mintz u64 src_addr, u64 dst_addr, 674fe56b9e6SYuval Mintz u8 src_type, u8 dst_type, 675fe56b9e6SYuval Mintz u32 size_in_dwords, 676fe56b9e6SYuval Mintz struct qed_dmae_params *p_params) 677fe56b9e6SYuval Mintz { 678fe56b9e6SYuval Mintz dma_addr_t phys = p_hwfn->dmae_info.completion_word_phys_addr; 679fe56b9e6SYuval Mintz u16 length_cur = 0, i = 0, cnt_split = 0, length_mod = 0; 680fe56b9e6SYuval Mintz struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd; 681fe56b9e6SYuval Mintz u64 src_addr_split = 0, dst_addr_split = 0; 682fe56b9e6SYuval Mintz u16 length_limit = DMAE_MAX_RW_SIZE; 683fe56b9e6SYuval Mintz int qed_status = 0; 684fe56b9e6SYuval Mintz u32 offset = 0; 685fe56b9e6SYuval Mintz 686fe56b9e6SYuval Mintz qed_dmae_opcode(p_hwfn, 687fe56b9e6SYuval Mintz (src_type == QED_DMAE_ADDRESS_GRC), 688fe56b9e6SYuval Mintz (dst_type == QED_DMAE_ADDRESS_GRC), 689fe56b9e6SYuval Mintz p_params); 690fe56b9e6SYuval Mintz 691fe56b9e6SYuval Mintz cmd->comp_addr_lo = cpu_to_le32(lower_32_bits(phys)); 692fe56b9e6SYuval Mintz cmd->comp_addr_hi = cpu_to_le32(upper_32_bits(phys)); 693fe56b9e6SYuval Mintz cmd->comp_val = cpu_to_le32(DMAE_COMPLETION_VAL); 694fe56b9e6SYuval Mintz 695fe56b9e6SYuval Mintz /* Check if the grc_addr is valid like < MAX_GRC_OFFSET */ 696fe56b9e6SYuval Mintz cnt_split = size_in_dwords / length_limit; 697fe56b9e6SYuval Mintz length_mod = size_in_dwords % length_limit; 698fe56b9e6SYuval Mintz 699fe56b9e6SYuval Mintz src_addr_split = src_addr; 700fe56b9e6SYuval Mintz dst_addr_split = dst_addr; 701fe56b9e6SYuval Mintz 702fe56b9e6SYuval Mintz for (i = 0; i <= cnt_split; i++) { 703fe56b9e6SYuval Mintz offset = length_limit * i; 704fe56b9e6SYuval Mintz 705fe56b9e6SYuval Mintz if (!(p_params->flags & QED_DMAE_FLAG_RW_REPL_SRC)) { 706fe56b9e6SYuval Mintz if (src_type == QED_DMAE_ADDRESS_GRC) 707fe56b9e6SYuval Mintz src_addr_split = src_addr + offset; 708fe56b9e6SYuval Mintz else 709fe56b9e6SYuval Mintz src_addr_split = src_addr + (offset * 4); 710fe56b9e6SYuval Mintz } 711fe56b9e6SYuval Mintz 712fe56b9e6SYuval Mintz if (dst_type == QED_DMAE_ADDRESS_GRC) 713fe56b9e6SYuval Mintz dst_addr_split = dst_addr + offset; 714fe56b9e6SYuval Mintz else 715fe56b9e6SYuval Mintz dst_addr_split = dst_addr + (offset * 4); 716fe56b9e6SYuval Mintz 717fe56b9e6SYuval Mintz length_cur = (cnt_split == i) ? length_mod : length_limit; 718fe56b9e6SYuval Mintz 719fe56b9e6SYuval Mintz /* might be zero on last iteration */ 720fe56b9e6SYuval Mintz if (!length_cur) 721fe56b9e6SYuval Mintz continue; 722fe56b9e6SYuval Mintz 723fe56b9e6SYuval Mintz qed_status = qed_dmae_execute_sub_operation(p_hwfn, 724fe56b9e6SYuval Mintz p_ptt, 725fe56b9e6SYuval Mintz src_addr_split, 726fe56b9e6SYuval Mintz dst_addr_split, 727fe56b9e6SYuval Mintz src_type, 728fe56b9e6SYuval Mintz dst_type, 729fe56b9e6SYuval Mintz length_cur); 730fe56b9e6SYuval Mintz if (qed_status) { 731fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 732fe56b9e6SYuval Mintz "qed_dmae_execute_sub_operation Failed with error 0x%x. source_addr 0x%llx, destination addr 0x%llx, size_in_dwords 0x%x\n", 7331a635e48SYuval Mintz qed_status, src_addr, dst_addr, length_cur); 734fe56b9e6SYuval Mintz break; 735fe56b9e6SYuval Mintz } 736fe56b9e6SYuval Mintz } 737fe56b9e6SYuval Mintz 738fe56b9e6SYuval Mintz return qed_status; 739fe56b9e6SYuval Mintz } 740fe56b9e6SYuval Mintz 741fe56b9e6SYuval Mintz int qed_dmae_host2grc(struct qed_hwfn *p_hwfn, 742fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 7431a635e48SYuval Mintz u64 source_addr, u32 grc_addr, u32 size_in_dwords, u32 flags) 744fe56b9e6SYuval Mintz { 745fe56b9e6SYuval Mintz u32 grc_addr_in_dw = grc_addr / sizeof(u32); 746fe56b9e6SYuval Mintz struct qed_dmae_params params; 747fe56b9e6SYuval Mintz int rc; 748fe56b9e6SYuval Mintz 749fe56b9e6SYuval Mintz memset(¶ms, 0, sizeof(struct qed_dmae_params)); 750fe56b9e6SYuval Mintz params.flags = flags; 751fe56b9e6SYuval Mintz 752fe56b9e6SYuval Mintz mutex_lock(&p_hwfn->dmae_info.mutex); 753fe56b9e6SYuval Mintz 754fe56b9e6SYuval Mintz rc = qed_dmae_execute_command(p_hwfn, p_ptt, source_addr, 755fe56b9e6SYuval Mintz grc_addr_in_dw, 756fe56b9e6SYuval Mintz QED_DMAE_ADDRESS_HOST_VIRT, 757fe56b9e6SYuval Mintz QED_DMAE_ADDRESS_GRC, 758fe56b9e6SYuval Mintz size_in_dwords, ¶ms); 759fe56b9e6SYuval Mintz 760fe56b9e6SYuval Mintz mutex_unlock(&p_hwfn->dmae_info.mutex); 761fe56b9e6SYuval Mintz 762fe56b9e6SYuval Mintz return rc; 763fe56b9e6SYuval Mintz } 764fe56b9e6SYuval Mintz 7651a635e48SYuval Mintz int qed_dmae_grc2host(struct qed_hwfn *p_hwfn, 7661a635e48SYuval Mintz struct qed_ptt *p_ptt, 7671a635e48SYuval Mintz u32 grc_addr, 768722003acSSudarsana Reddy Kalluru dma_addr_t dest_addr, u32 size_in_dwords, u32 flags) 769722003acSSudarsana Reddy Kalluru { 770722003acSSudarsana Reddy Kalluru u32 grc_addr_in_dw = grc_addr / sizeof(u32); 771722003acSSudarsana Reddy Kalluru struct qed_dmae_params params; 772722003acSSudarsana Reddy Kalluru int rc; 773722003acSSudarsana Reddy Kalluru 774722003acSSudarsana Reddy Kalluru memset(¶ms, 0, sizeof(struct qed_dmae_params)); 775722003acSSudarsana Reddy Kalluru params.flags = flags; 776722003acSSudarsana Reddy Kalluru 777722003acSSudarsana Reddy Kalluru mutex_lock(&p_hwfn->dmae_info.mutex); 778722003acSSudarsana Reddy Kalluru 779722003acSSudarsana Reddy Kalluru rc = qed_dmae_execute_command(p_hwfn, p_ptt, grc_addr_in_dw, 780722003acSSudarsana Reddy Kalluru dest_addr, QED_DMAE_ADDRESS_GRC, 781722003acSSudarsana Reddy Kalluru QED_DMAE_ADDRESS_HOST_VIRT, 782722003acSSudarsana Reddy Kalluru size_in_dwords, ¶ms); 783722003acSSudarsana Reddy Kalluru 784722003acSSudarsana Reddy Kalluru mutex_unlock(&p_hwfn->dmae_info.mutex); 785722003acSSudarsana Reddy Kalluru 786722003acSSudarsana Reddy Kalluru return rc; 787722003acSSudarsana Reddy Kalluru } 788722003acSSudarsana Reddy Kalluru 7891a635e48SYuval Mintz int qed_dmae_host2host(struct qed_hwfn *p_hwfn, 79037bff2b9SYuval Mintz struct qed_ptt *p_ptt, 79137bff2b9SYuval Mintz dma_addr_t source_addr, 79237bff2b9SYuval Mintz dma_addr_t dest_addr, 79337bff2b9SYuval Mintz u32 size_in_dwords, struct qed_dmae_params *p_params) 79437bff2b9SYuval Mintz { 79537bff2b9SYuval Mintz int rc; 79637bff2b9SYuval Mintz 79737bff2b9SYuval Mintz mutex_lock(&(p_hwfn->dmae_info.mutex)); 79837bff2b9SYuval Mintz 79937bff2b9SYuval Mintz rc = qed_dmae_execute_command(p_hwfn, p_ptt, source_addr, 80037bff2b9SYuval Mintz dest_addr, 80137bff2b9SYuval Mintz QED_DMAE_ADDRESS_HOST_PHYS, 80237bff2b9SYuval Mintz QED_DMAE_ADDRESS_HOST_PHYS, 80337bff2b9SYuval Mintz size_in_dwords, p_params); 80437bff2b9SYuval Mintz 80537bff2b9SYuval Mintz mutex_unlock(&(p_hwfn->dmae_info.mutex)); 80637bff2b9SYuval Mintz 80737bff2b9SYuval Mintz return rc; 80837bff2b9SYuval Mintz } 80937bff2b9SYuval Mintz 810da090917STomer Tayar int qed_dmae_sanity(struct qed_hwfn *p_hwfn, 811da090917STomer Tayar struct qed_ptt *p_ptt, const char *phase) 812da090917STomer Tayar { 813da090917STomer Tayar u32 size = PAGE_SIZE / 2, val; 814da090917STomer Tayar struct qed_dmae_params params; 815da090917STomer Tayar int rc = 0; 816da090917STomer Tayar dma_addr_t p_phys; 817da090917STomer Tayar void *p_virt; 818da090917STomer Tayar u32 *p_tmp; 819da090917STomer Tayar 820da090917STomer Tayar p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 821da090917STomer Tayar 2 * size, &p_phys, GFP_KERNEL); 822da090917STomer Tayar if (!p_virt) { 823da090917STomer Tayar DP_NOTICE(p_hwfn, 824da090917STomer Tayar "DMAE sanity [%s]: failed to allocate memory\n", 825da090917STomer Tayar phase); 826da090917STomer Tayar return -ENOMEM; 827da090917STomer Tayar } 828da090917STomer Tayar 829da090917STomer Tayar /* Fill the bottom half of the allocated memory with a known pattern */ 830da090917STomer Tayar for (p_tmp = (u32 *)p_virt; 831da090917STomer Tayar p_tmp < (u32 *)((u8 *)p_virt + size); p_tmp++) { 832da090917STomer Tayar /* Save the address itself as the value */ 833da090917STomer Tayar val = (u32)(uintptr_t)p_tmp; 834da090917STomer Tayar *p_tmp = val; 835da090917STomer Tayar } 836da090917STomer Tayar 837da090917STomer Tayar /* Zero the top half of the allocated memory */ 838da090917STomer Tayar memset((u8 *)p_virt + size, 0, size); 839da090917STomer Tayar 840da090917STomer Tayar DP_VERBOSE(p_hwfn, 841da090917STomer Tayar QED_MSG_SP, 842da090917STomer Tayar "DMAE sanity [%s]: src_addr={phys 0x%llx, virt %p}, dst_addr={phys 0x%llx, virt %p}, size 0x%x\n", 843da090917STomer Tayar phase, 844da090917STomer Tayar (u64)p_phys, 845da090917STomer Tayar p_virt, (u64)(p_phys + size), (u8 *)p_virt + size, size); 846da090917STomer Tayar 847da090917STomer Tayar memset(¶ms, 0, sizeof(params)); 848da090917STomer Tayar rc = qed_dmae_host2host(p_hwfn, p_ptt, p_phys, p_phys + size, 849da090917STomer Tayar size / 4 /* size_in_dwords */, ¶ms); 850da090917STomer Tayar if (rc) { 851da090917STomer Tayar DP_NOTICE(p_hwfn, 852da090917STomer Tayar "DMAE sanity [%s]: qed_dmae_host2host() failed. rc = %d.\n", 853da090917STomer Tayar phase, rc); 854da090917STomer Tayar goto out; 855da090917STomer Tayar } 856da090917STomer Tayar 857da090917STomer Tayar /* Verify that the top half of the allocated memory has the pattern */ 858da090917STomer Tayar for (p_tmp = (u32 *)((u8 *)p_virt + size); 859da090917STomer Tayar p_tmp < (u32 *)((u8 *)p_virt + (2 * size)); p_tmp++) { 860da090917STomer Tayar /* The corresponding address in the bottom half */ 861da090917STomer Tayar val = (u32)(uintptr_t)p_tmp - size; 862da090917STomer Tayar 863da090917STomer Tayar if (*p_tmp != val) { 864da090917STomer Tayar DP_NOTICE(p_hwfn, 865da090917STomer Tayar "DMAE sanity [%s]: addr={phys 0x%llx, virt %p}, read_val 0x%08x, expected_val 0x%08x\n", 866da090917STomer Tayar phase, 867da090917STomer Tayar (u64)p_phys + ((u8 *)p_tmp - (u8 *)p_virt), 868da090917STomer Tayar p_tmp, *p_tmp, val); 869da090917STomer Tayar rc = -EINVAL; 870da090917STomer Tayar goto out; 871da090917STomer Tayar } 872da090917STomer Tayar } 873da090917STomer Tayar 874da090917STomer Tayar out: 875da090917STomer Tayar dma_free_coherent(&p_hwfn->cdev->pdev->dev, 2 * size, p_virt, p_phys); 876da090917STomer Tayar return rc; 877da090917STomer Tayar } 878