1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #include <linux/types.h> 34fe56b9e6SYuval Mintz #include <linux/io.h> 35fe56b9e6SYuval Mintz #include <linux/delay.h> 36fe56b9e6SYuval Mintz #include <linux/dma-mapping.h> 37fe56b9e6SYuval Mintz #include <linux/errno.h> 38fe56b9e6SYuval Mintz #include <linux/kernel.h> 39fe56b9e6SYuval Mintz #include <linux/list.h> 40fe56b9e6SYuval Mintz #include <linux/mutex.h> 41fe56b9e6SYuval Mintz #include <linux/pci.h> 42fe56b9e6SYuval Mintz #include <linux/slab.h> 43fe56b9e6SYuval Mintz #include <linux/spinlock.h> 44fe56b9e6SYuval Mintz #include <linux/string.h> 45fe56b9e6SYuval Mintz #include <linux/qed/qed_chain.h> 46fe56b9e6SYuval Mintz #include "qed.h" 47fe56b9e6SYuval Mintz #include "qed_hsi.h" 48fe56b9e6SYuval Mintz #include "qed_hw.h" 49fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 501408cc1fSYuval Mintz #include "qed_sriov.h" 51fe56b9e6SYuval Mintz 52fe56b9e6SYuval Mintz #define QED_BAR_ACQUIRE_TIMEOUT 1000 53fe56b9e6SYuval Mintz 54fe56b9e6SYuval Mintz /* Invalid values */ 55fe56b9e6SYuval Mintz #define QED_BAR_INVALID_OFFSET (cpu_to_le32(-1)) 56fe56b9e6SYuval Mintz 57fe56b9e6SYuval Mintz struct qed_ptt { 58fe56b9e6SYuval Mintz struct list_head list_entry; 59fe56b9e6SYuval Mintz unsigned int idx; 60fe56b9e6SYuval Mintz struct pxp_ptt_entry pxp; 613a50d351SMintz, Yuval u8 hwfn_id; 62fe56b9e6SYuval Mintz }; 63fe56b9e6SYuval Mintz 64fe56b9e6SYuval Mintz struct qed_ptt_pool { 65fe56b9e6SYuval Mintz struct list_head free_list; 66fe56b9e6SYuval Mintz spinlock_t lock; /* ptt synchronized access */ 67fe56b9e6SYuval Mintz struct qed_ptt ptts[PXP_EXTERNAL_BAR_PF_WINDOW_NUM]; 68fe56b9e6SYuval Mintz }; 69fe56b9e6SYuval Mintz 70fe56b9e6SYuval Mintz int qed_ptt_pool_alloc(struct qed_hwfn *p_hwfn) 71fe56b9e6SYuval Mintz { 721a635e48SYuval Mintz struct qed_ptt_pool *p_pool = kmalloc(sizeof(*p_pool), GFP_KERNEL); 73fe56b9e6SYuval Mintz int i; 74fe56b9e6SYuval Mintz 75fe56b9e6SYuval Mintz if (!p_pool) 76fe56b9e6SYuval Mintz return -ENOMEM; 77fe56b9e6SYuval Mintz 78fe56b9e6SYuval Mintz INIT_LIST_HEAD(&p_pool->free_list); 79fe56b9e6SYuval Mintz for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) { 80fe56b9e6SYuval Mintz p_pool->ptts[i].idx = i; 81fe56b9e6SYuval Mintz p_pool->ptts[i].pxp.offset = QED_BAR_INVALID_OFFSET; 82fe56b9e6SYuval Mintz p_pool->ptts[i].pxp.pretend.control = 0; 833a50d351SMintz, Yuval p_pool->ptts[i].hwfn_id = p_hwfn->my_id; 84fe56b9e6SYuval Mintz if (i >= RESERVED_PTT_MAX) 85fe56b9e6SYuval Mintz list_add(&p_pool->ptts[i].list_entry, 86fe56b9e6SYuval Mintz &p_pool->free_list); 87fe56b9e6SYuval Mintz } 88fe56b9e6SYuval Mintz 89fe56b9e6SYuval Mintz p_hwfn->p_ptt_pool = p_pool; 90fe56b9e6SYuval Mintz spin_lock_init(&p_pool->lock); 91fe56b9e6SYuval Mintz 92fe56b9e6SYuval Mintz return 0; 93fe56b9e6SYuval Mintz } 94fe56b9e6SYuval Mintz 95fe56b9e6SYuval Mintz void qed_ptt_invalidate(struct qed_hwfn *p_hwfn) 96fe56b9e6SYuval Mintz { 97fe56b9e6SYuval Mintz struct qed_ptt *p_ptt; 98fe56b9e6SYuval Mintz int i; 99fe56b9e6SYuval Mintz 100fe56b9e6SYuval Mintz for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) { 101fe56b9e6SYuval Mintz p_ptt = &p_hwfn->p_ptt_pool->ptts[i]; 102fe56b9e6SYuval Mintz p_ptt->pxp.offset = QED_BAR_INVALID_OFFSET; 103fe56b9e6SYuval Mintz } 104fe56b9e6SYuval Mintz } 105fe56b9e6SYuval Mintz 106fe56b9e6SYuval Mintz void qed_ptt_pool_free(struct qed_hwfn *p_hwfn) 107fe56b9e6SYuval Mintz { 108fe56b9e6SYuval Mintz kfree(p_hwfn->p_ptt_pool); 109fe56b9e6SYuval Mintz p_hwfn->p_ptt_pool = NULL; 110fe56b9e6SYuval Mintz } 111fe56b9e6SYuval Mintz 112fe56b9e6SYuval Mintz struct qed_ptt *qed_ptt_acquire(struct qed_hwfn *p_hwfn) 113fe56b9e6SYuval Mintz { 114fe56b9e6SYuval Mintz struct qed_ptt *p_ptt; 115fe56b9e6SYuval Mintz unsigned int i; 116fe56b9e6SYuval Mintz 117fe56b9e6SYuval Mintz /* Take the free PTT from the list */ 118fe56b9e6SYuval Mintz for (i = 0; i < QED_BAR_ACQUIRE_TIMEOUT; i++) { 119fe56b9e6SYuval Mintz spin_lock_bh(&p_hwfn->p_ptt_pool->lock); 120fe56b9e6SYuval Mintz 121fe56b9e6SYuval Mintz if (!list_empty(&p_hwfn->p_ptt_pool->free_list)) { 122fe56b9e6SYuval Mintz p_ptt = list_first_entry(&p_hwfn->p_ptt_pool->free_list, 123fe56b9e6SYuval Mintz struct qed_ptt, list_entry); 124fe56b9e6SYuval Mintz list_del(&p_ptt->list_entry); 125fe56b9e6SYuval Mintz 126fe56b9e6SYuval Mintz spin_unlock_bh(&p_hwfn->p_ptt_pool->lock); 127fe56b9e6SYuval Mintz 128fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 129fe56b9e6SYuval Mintz "allocated ptt %d\n", p_ptt->idx); 130fe56b9e6SYuval Mintz return p_ptt; 131fe56b9e6SYuval Mintz } 132fe56b9e6SYuval Mintz 133fe56b9e6SYuval Mintz spin_unlock_bh(&p_hwfn->p_ptt_pool->lock); 134fe56b9e6SYuval Mintz usleep_range(1000, 2000); 135fe56b9e6SYuval Mintz } 136fe56b9e6SYuval Mintz 137fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "PTT acquire timeout - failed to allocate PTT\n"); 138fe56b9e6SYuval Mintz return NULL; 139fe56b9e6SYuval Mintz } 140fe56b9e6SYuval Mintz 1411a635e48SYuval Mintz void qed_ptt_release(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 142fe56b9e6SYuval Mintz { 143fe56b9e6SYuval Mintz spin_lock_bh(&p_hwfn->p_ptt_pool->lock); 144fe56b9e6SYuval Mintz list_add(&p_ptt->list_entry, &p_hwfn->p_ptt_pool->free_list); 145fe56b9e6SYuval Mintz spin_unlock_bh(&p_hwfn->p_ptt_pool->lock); 146fe56b9e6SYuval Mintz } 147fe56b9e6SYuval Mintz 1481a635e48SYuval Mintz u32 qed_ptt_get_hw_addr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 149fe56b9e6SYuval Mintz { 150fe56b9e6SYuval Mintz /* The HW is using DWORDS and we need to translate it to Bytes */ 151fe56b9e6SYuval Mintz return le32_to_cpu(p_ptt->pxp.offset) << 2; 152fe56b9e6SYuval Mintz } 153fe56b9e6SYuval Mintz 154fe56b9e6SYuval Mintz static u32 qed_ptt_config_addr(struct qed_ptt *p_ptt) 155fe56b9e6SYuval Mintz { 156fe56b9e6SYuval Mintz return PXP_PF_WINDOW_ADMIN_PER_PF_START + 157fe56b9e6SYuval Mintz p_ptt->idx * sizeof(struct pxp_ptt_entry); 158fe56b9e6SYuval Mintz } 159fe56b9e6SYuval Mintz 160fe56b9e6SYuval Mintz u32 qed_ptt_get_bar_addr(struct qed_ptt *p_ptt) 161fe56b9e6SYuval Mintz { 162fe56b9e6SYuval Mintz return PXP_EXTERNAL_BAR_PF_WINDOW_START + 163fe56b9e6SYuval Mintz p_ptt->idx * PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE; 164fe56b9e6SYuval Mintz } 165fe56b9e6SYuval Mintz 166fe56b9e6SYuval Mintz void qed_ptt_set_win(struct qed_hwfn *p_hwfn, 1671a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 new_hw_addr) 168fe56b9e6SYuval Mintz { 169fe56b9e6SYuval Mintz u32 prev_hw_addr; 170fe56b9e6SYuval Mintz 171fe56b9e6SYuval Mintz prev_hw_addr = qed_ptt_get_hw_addr(p_hwfn, p_ptt); 172fe56b9e6SYuval Mintz 173fe56b9e6SYuval Mintz if (new_hw_addr == prev_hw_addr) 174fe56b9e6SYuval Mintz return; 175fe56b9e6SYuval Mintz 176fe56b9e6SYuval Mintz /* Update PTT entery in admin window */ 177fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 178fe56b9e6SYuval Mintz "Updating PTT entry %d to offset 0x%x\n", 179fe56b9e6SYuval Mintz p_ptt->idx, new_hw_addr); 180fe56b9e6SYuval Mintz 181fe56b9e6SYuval Mintz /* The HW is using DWORDS and the address is in Bytes */ 182fe56b9e6SYuval Mintz p_ptt->pxp.offset = cpu_to_le32(new_hw_addr >> 2); 183fe56b9e6SYuval Mintz 184fe56b9e6SYuval Mintz REG_WR(p_hwfn, 185fe56b9e6SYuval Mintz qed_ptt_config_addr(p_ptt) + 186fe56b9e6SYuval Mintz offsetof(struct pxp_ptt_entry, offset), 187fe56b9e6SYuval Mintz le32_to_cpu(p_ptt->pxp.offset)); 188fe56b9e6SYuval Mintz } 189fe56b9e6SYuval Mintz 190fe56b9e6SYuval Mintz static u32 qed_set_ptt(struct qed_hwfn *p_hwfn, 1911a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 hw_addr) 192fe56b9e6SYuval Mintz { 193fe56b9e6SYuval Mintz u32 win_hw_addr = qed_ptt_get_hw_addr(p_hwfn, p_ptt); 194fe56b9e6SYuval Mintz u32 offset; 195fe56b9e6SYuval Mintz 196fe56b9e6SYuval Mintz offset = hw_addr - win_hw_addr; 197fe56b9e6SYuval Mintz 1983a50d351SMintz, Yuval if (p_ptt->hwfn_id != p_hwfn->my_id) 1993a50d351SMintz, Yuval DP_NOTICE(p_hwfn, 2003a50d351SMintz, Yuval "ptt[%d] of hwfn[%02x] is used by hwfn[%02x]!\n", 2013a50d351SMintz, Yuval p_ptt->idx, p_ptt->hwfn_id, p_hwfn->my_id); 2023a50d351SMintz, Yuval 203fe56b9e6SYuval Mintz /* Verify the address is within the window */ 204fe56b9e6SYuval Mintz if (hw_addr < win_hw_addr || 205fe56b9e6SYuval Mintz offset >= PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) { 206fe56b9e6SYuval Mintz qed_ptt_set_win(p_hwfn, p_ptt, hw_addr); 207fe56b9e6SYuval Mintz offset = 0; 208fe56b9e6SYuval Mintz } 209fe56b9e6SYuval Mintz 210fe56b9e6SYuval Mintz return qed_ptt_get_bar_addr(p_ptt) + offset; 211fe56b9e6SYuval Mintz } 212fe56b9e6SYuval Mintz 213fe56b9e6SYuval Mintz struct qed_ptt *qed_get_reserved_ptt(struct qed_hwfn *p_hwfn, 214fe56b9e6SYuval Mintz enum reserved_ptts ptt_idx) 215fe56b9e6SYuval Mintz { 216fe56b9e6SYuval Mintz if (ptt_idx >= RESERVED_PTT_MAX) { 217fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 218fe56b9e6SYuval Mintz "Requested PTT %d is out of range\n", ptt_idx); 219fe56b9e6SYuval Mintz return NULL; 220fe56b9e6SYuval Mintz } 221fe56b9e6SYuval Mintz 222fe56b9e6SYuval Mintz return &p_hwfn->p_ptt_pool->ptts[ptt_idx]; 223fe56b9e6SYuval Mintz } 224fe56b9e6SYuval Mintz 225fe56b9e6SYuval Mintz void qed_wr(struct qed_hwfn *p_hwfn, 226fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 227fe56b9e6SYuval Mintz u32 hw_addr, u32 val) 228fe56b9e6SYuval Mintz { 229fe56b9e6SYuval Mintz u32 bar_addr = qed_set_ptt(p_hwfn, p_ptt, hw_addr); 230fe56b9e6SYuval Mintz 231fe56b9e6SYuval Mintz REG_WR(p_hwfn, bar_addr, val); 232fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 233fe56b9e6SYuval Mintz "bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n", 234fe56b9e6SYuval Mintz bar_addr, hw_addr, val); 235fe56b9e6SYuval Mintz } 236fe56b9e6SYuval Mintz 237fe56b9e6SYuval Mintz u32 qed_rd(struct qed_hwfn *p_hwfn, 238fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 239fe56b9e6SYuval Mintz u32 hw_addr) 240fe56b9e6SYuval Mintz { 241fe56b9e6SYuval Mintz u32 bar_addr = qed_set_ptt(p_hwfn, p_ptt, hw_addr); 242fe56b9e6SYuval Mintz u32 val = REG_RD(p_hwfn, bar_addr); 243fe56b9e6SYuval Mintz 244fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 245fe56b9e6SYuval Mintz "bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n", 246fe56b9e6SYuval Mintz bar_addr, hw_addr, val); 247fe56b9e6SYuval Mintz 248fe56b9e6SYuval Mintz return val; 249fe56b9e6SYuval Mintz } 250fe56b9e6SYuval Mintz 251fe56b9e6SYuval Mintz static void qed_memcpy_hw(struct qed_hwfn *p_hwfn, 252fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2531a635e48SYuval Mintz void *addr, u32 hw_addr, size_t n, bool to_device) 254fe56b9e6SYuval Mintz { 255fe56b9e6SYuval Mintz u32 dw_count, *host_addr, hw_offset; 256fe56b9e6SYuval Mintz size_t quota, done = 0; 257fe56b9e6SYuval Mintz u32 __iomem *reg_addr; 258fe56b9e6SYuval Mintz 259fe56b9e6SYuval Mintz while (done < n) { 260fe56b9e6SYuval Mintz quota = min_t(size_t, n - done, 261fe56b9e6SYuval Mintz PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE); 262fe56b9e6SYuval Mintz 2631408cc1fSYuval Mintz if (IS_PF(p_hwfn->cdev)) { 264fe56b9e6SYuval Mintz qed_ptt_set_win(p_hwfn, p_ptt, hw_addr + done); 265fe56b9e6SYuval Mintz hw_offset = qed_ptt_get_bar_addr(p_ptt); 2661408cc1fSYuval Mintz } else { 2671408cc1fSYuval Mintz hw_offset = hw_addr + done; 2681408cc1fSYuval Mintz } 269fe56b9e6SYuval Mintz 270fe56b9e6SYuval Mintz dw_count = quota / 4; 271fe56b9e6SYuval Mintz host_addr = (u32 *)((u8 *)addr + done); 272fe56b9e6SYuval Mintz reg_addr = (u32 __iomem *)REG_ADDR(p_hwfn, hw_offset); 273fe56b9e6SYuval Mintz if (to_device) 274fe56b9e6SYuval Mintz while (dw_count--) 275fe56b9e6SYuval Mintz DIRECT_REG_WR(reg_addr++, *host_addr++); 276fe56b9e6SYuval Mintz else 277fe56b9e6SYuval Mintz while (dw_count--) 278fe56b9e6SYuval Mintz *host_addr++ = DIRECT_REG_RD(reg_addr++); 279fe56b9e6SYuval Mintz 280fe56b9e6SYuval Mintz done += quota; 281fe56b9e6SYuval Mintz } 282fe56b9e6SYuval Mintz } 283fe56b9e6SYuval Mintz 284fe56b9e6SYuval Mintz void qed_memcpy_from(struct qed_hwfn *p_hwfn, 2851a635e48SYuval Mintz struct qed_ptt *p_ptt, void *dest, u32 hw_addr, size_t n) 286fe56b9e6SYuval Mintz { 287fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 288fe56b9e6SYuval Mintz "hw_addr 0x%x, dest %p hw_addr 0x%x, size %lu\n", 289fe56b9e6SYuval Mintz hw_addr, dest, hw_addr, (unsigned long)n); 290fe56b9e6SYuval Mintz 291fe56b9e6SYuval Mintz qed_memcpy_hw(p_hwfn, p_ptt, dest, hw_addr, n, false); 292fe56b9e6SYuval Mintz } 293fe56b9e6SYuval Mintz 294fe56b9e6SYuval Mintz void qed_memcpy_to(struct qed_hwfn *p_hwfn, 2951a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 hw_addr, void *src, size_t n) 296fe56b9e6SYuval Mintz { 297fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 298fe56b9e6SYuval Mintz "hw_addr 0x%x, hw_addr 0x%x, src %p size %lu\n", 299fe56b9e6SYuval Mintz hw_addr, hw_addr, src, (unsigned long)n); 300fe56b9e6SYuval Mintz 301fe56b9e6SYuval Mintz qed_memcpy_hw(p_hwfn, p_ptt, src, hw_addr, n, true); 302fe56b9e6SYuval Mintz } 303fe56b9e6SYuval Mintz 3041a635e48SYuval Mintz void qed_fid_pretend(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 fid) 305fe56b9e6SYuval Mintz { 306fe56b9e6SYuval Mintz u16 control = 0; 307fe56b9e6SYuval Mintz 308fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_IS_CONCRETE, 1); 309fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_FUNCTION, 1); 310fe56b9e6SYuval Mintz 311fe56b9e6SYuval Mintz /* Every pretend undos previous pretends, including 312fe56b9e6SYuval Mintz * previous port pretend. 313fe56b9e6SYuval Mintz */ 314fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0); 315fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0); 316fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1); 317fe56b9e6SYuval Mintz 318fe56b9e6SYuval Mintz if (!GET_FIELD(fid, PXP_CONCRETE_FID_VFVALID)) 319fe56b9e6SYuval Mintz fid = GET_FIELD(fid, PXP_CONCRETE_FID_PFID); 320fe56b9e6SYuval Mintz 321fe56b9e6SYuval Mintz p_ptt->pxp.pretend.control = cpu_to_le16(control); 322fe56b9e6SYuval Mintz p_ptt->pxp.pretend.fid.concrete_fid.fid = cpu_to_le16(fid); 323fe56b9e6SYuval Mintz 324fe56b9e6SYuval Mintz REG_WR(p_hwfn, 325fe56b9e6SYuval Mintz qed_ptt_config_addr(p_ptt) + 326fe56b9e6SYuval Mintz offsetof(struct pxp_ptt_entry, pretend), 327fe56b9e6SYuval Mintz *(u32 *)&p_ptt->pxp.pretend); 328fe56b9e6SYuval Mintz } 329fe56b9e6SYuval Mintz 330fe56b9e6SYuval Mintz void qed_port_pretend(struct qed_hwfn *p_hwfn, 3311a635e48SYuval Mintz struct qed_ptt *p_ptt, u8 port_id) 332fe56b9e6SYuval Mintz { 333fe56b9e6SYuval Mintz u16 control = 0; 334fe56b9e6SYuval Mintz 335fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PORT, port_id); 336fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 1); 337fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1); 338fe56b9e6SYuval Mintz 339fe56b9e6SYuval Mintz p_ptt->pxp.pretend.control = cpu_to_le16(control); 340fe56b9e6SYuval Mintz 341fe56b9e6SYuval Mintz REG_WR(p_hwfn, 342fe56b9e6SYuval Mintz qed_ptt_config_addr(p_ptt) + 343fe56b9e6SYuval Mintz offsetof(struct pxp_ptt_entry, pretend), 344fe56b9e6SYuval Mintz *(u32 *)&p_ptt->pxp.pretend); 345fe56b9e6SYuval Mintz } 346fe56b9e6SYuval Mintz 3471a635e48SYuval Mintz void qed_port_unpretend(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 348fe56b9e6SYuval Mintz { 349fe56b9e6SYuval Mintz u16 control = 0; 350fe56b9e6SYuval Mintz 351fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0); 352fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0); 353fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1); 354fe56b9e6SYuval Mintz 355fe56b9e6SYuval Mintz p_ptt->pxp.pretend.control = cpu_to_le16(control); 356fe56b9e6SYuval Mintz 357fe56b9e6SYuval Mintz REG_WR(p_hwfn, 358fe56b9e6SYuval Mintz qed_ptt_config_addr(p_ptt) + 359fe56b9e6SYuval Mintz offsetof(struct pxp_ptt_entry, pretend), 360fe56b9e6SYuval Mintz *(u32 *)&p_ptt->pxp.pretend); 361fe56b9e6SYuval Mintz } 362fe56b9e6SYuval Mintz 363d52c89f1SMichal Kalderon void qed_port_fid_pretend(struct qed_hwfn *p_hwfn, 364d52c89f1SMichal Kalderon struct qed_ptt *p_ptt, u8 port_id, u16 fid) 365d52c89f1SMichal Kalderon { 366d52c89f1SMichal Kalderon u16 control = 0; 367d52c89f1SMichal Kalderon 368d52c89f1SMichal Kalderon SET_FIELD(control, PXP_PRETEND_CMD_PORT, port_id); 369d52c89f1SMichal Kalderon SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 1); 370d52c89f1SMichal Kalderon SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1); 371d52c89f1SMichal Kalderon SET_FIELD(control, PXP_PRETEND_CMD_IS_CONCRETE, 1); 372d52c89f1SMichal Kalderon SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_FUNCTION, 1); 373d52c89f1SMichal Kalderon if (!GET_FIELD(fid, PXP_CONCRETE_FID_VFVALID)) 374d52c89f1SMichal Kalderon fid = GET_FIELD(fid, PXP_CONCRETE_FID_PFID); 375d52c89f1SMichal Kalderon p_ptt->pxp.pretend.control = cpu_to_le16(control); 376d52c89f1SMichal Kalderon p_ptt->pxp.pretend.fid.concrete_fid.fid = cpu_to_le16(fid); 377d52c89f1SMichal Kalderon REG_WR(p_hwfn, 378d52c89f1SMichal Kalderon qed_ptt_config_addr(p_ptt) + 379d52c89f1SMichal Kalderon offsetof(struct pxp_ptt_entry, pretend), 380d52c89f1SMichal Kalderon *(u32 *)&p_ptt->pxp.pretend); 381d52c89f1SMichal Kalderon } 382d52c89f1SMichal Kalderon 38332a47e72SYuval Mintz u32 qed_vfid_to_concrete(struct qed_hwfn *p_hwfn, u8 vfid) 38432a47e72SYuval Mintz { 38532a47e72SYuval Mintz u32 concrete_fid = 0; 38632a47e72SYuval Mintz 38732a47e72SYuval Mintz SET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID, p_hwfn->rel_pf_id); 38832a47e72SYuval Mintz SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID, vfid); 38932a47e72SYuval Mintz SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID, 1); 39032a47e72SYuval Mintz 39132a47e72SYuval Mintz return concrete_fid; 39232a47e72SYuval Mintz } 39332a47e72SYuval Mintz 394fe56b9e6SYuval Mintz /* DMAE */ 39583bf76e3SMichal Kalderon #define QED_DMAE_FLAGS_IS_SET(params, flag) \ 396804c5702SMichal Kalderon ((params) != NULL && GET_FIELD((params)->flags, QED_DMAE_PARAMS_##flag)) 39783bf76e3SMichal Kalderon 398fe56b9e6SYuval Mintz static void qed_dmae_opcode(struct qed_hwfn *p_hwfn, 399fe56b9e6SYuval Mintz const u8 is_src_type_grc, 400fe56b9e6SYuval Mintz const u8 is_dst_type_grc, 401fe56b9e6SYuval Mintz struct qed_dmae_params *p_params) 402fe56b9e6SYuval Mintz { 40383bf76e3SMichal Kalderon u8 src_pfid, dst_pfid, port_id; 40437bff2b9SYuval Mintz u16 opcode_b = 0; 405fe56b9e6SYuval Mintz u32 opcode = 0; 406fe56b9e6SYuval Mintz 407fe56b9e6SYuval Mintz /* Whether the source is the PCIe or the GRC. 408fe56b9e6SYuval Mintz * 0- The source is the PCIe 409fe56b9e6SYuval Mintz * 1- The source is the GRC. 410fe56b9e6SYuval Mintz */ 411804c5702SMichal Kalderon SET_FIELD(opcode, DMAE_CMD_SRC, 412804c5702SMichal Kalderon (is_src_type_grc ? dmae_cmd_src_grc : dmae_cmd_src_pcie)); 413804c5702SMichal Kalderon src_pfid = QED_DMAE_FLAGS_IS_SET(p_params, SRC_PF_VALID) ? 41483bf76e3SMichal Kalderon p_params->src_pfid : p_hwfn->rel_pf_id; 415804c5702SMichal Kalderon SET_FIELD(opcode, DMAE_CMD_SRC_PF_ID, src_pfid); 416fe56b9e6SYuval Mintz 417fe56b9e6SYuval Mintz /* The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */ 418804c5702SMichal Kalderon SET_FIELD(opcode, DMAE_CMD_DST, 419804c5702SMichal Kalderon (is_dst_type_grc ? dmae_cmd_dst_grc : dmae_cmd_dst_pcie)); 420804c5702SMichal Kalderon dst_pfid = QED_DMAE_FLAGS_IS_SET(p_params, DST_PF_VALID) ? 42183bf76e3SMichal Kalderon p_params->dst_pfid : p_hwfn->rel_pf_id; 422804c5702SMichal Kalderon SET_FIELD(opcode, DMAE_CMD_DST_PF_ID, dst_pfid); 423804c5702SMichal Kalderon 424fe56b9e6SYuval Mintz 425fe56b9e6SYuval Mintz /* Whether to write a completion word to the completion destination: 426fe56b9e6SYuval Mintz * 0-Do not write a completion word 427fe56b9e6SYuval Mintz * 1-Write the completion word 428fe56b9e6SYuval Mintz */ 429804c5702SMichal Kalderon SET_FIELD(opcode, DMAE_CMD_COMP_WORD_EN, 1); 430804c5702SMichal Kalderon SET_FIELD(opcode, DMAE_CMD_SRC_ADDR_RESET, 1); 431fe56b9e6SYuval Mintz 43283bf76e3SMichal Kalderon if (QED_DMAE_FLAGS_IS_SET(p_params, COMPLETION_DST)) 433804c5702SMichal Kalderon SET_FIELD(opcode, DMAE_CMD_COMP_FUNC, 1); 434fe56b9e6SYuval Mintz 435804c5702SMichal Kalderon /* swapping mode 3 - big endian */ 436804c5702SMichal Kalderon SET_FIELD(opcode, DMAE_CMD_ENDIANITY_MODE, DMAE_CMD_ENDIANITY); 437fe56b9e6SYuval Mintz 438804c5702SMichal Kalderon port_id = (QED_DMAE_FLAGS_IS_SET(p_params, PORT_VALID)) ? 43983bf76e3SMichal Kalderon p_params->port_id : p_hwfn->port_id; 440804c5702SMichal Kalderon SET_FIELD(opcode, DMAE_CMD_PORT_ID, port_id); 441fe56b9e6SYuval Mintz 442fe56b9e6SYuval Mintz /* reset source address in next go */ 443804c5702SMichal Kalderon SET_FIELD(opcode, DMAE_CMD_SRC_ADDR_RESET, 1); 444fe56b9e6SYuval Mintz 445fe56b9e6SYuval Mintz /* reset dest address in next go */ 446804c5702SMichal Kalderon SET_FIELD(opcode, DMAE_CMD_DST_ADDR_RESET, 1); 447fe56b9e6SYuval Mintz 44837bff2b9SYuval Mintz /* SRC/DST VFID: all 1's - pf, otherwise VF id */ 449804c5702SMichal Kalderon if (QED_DMAE_FLAGS_IS_SET(p_params, SRC_VF_VALID)) { 450804c5702SMichal Kalderon SET_FIELD(opcode, DMAE_CMD_SRC_VF_ID_VALID, 1); 451804c5702SMichal Kalderon SET_FIELD(opcode_b, DMAE_CMD_SRC_VF_ID, p_params->src_vfid); 45237bff2b9SYuval Mintz } else { 453804c5702SMichal Kalderon SET_FIELD(opcode_b, DMAE_CMD_SRC_VF_ID, 0xFF); 45437bff2b9SYuval Mintz } 455804c5702SMichal Kalderon if (QED_DMAE_FLAGS_IS_SET(p_params, DST_VF_VALID)) { 456804c5702SMichal Kalderon SET_FIELD(opcode, DMAE_CMD_DST_VF_ID_VALID, 1); 457804c5702SMichal Kalderon SET_FIELD(opcode_b, DMAE_CMD_DST_VF_ID, p_params->dst_vfid); 45837bff2b9SYuval Mintz } else { 459804c5702SMichal Kalderon SET_FIELD(opcode_b, DMAE_CMD_DST_VF_ID, 0xFF); 46037bff2b9SYuval Mintz } 461fe56b9e6SYuval Mintz 462fe56b9e6SYuval Mintz p_hwfn->dmae_info.p_dmae_cmd->opcode = cpu_to_le32(opcode); 46337bff2b9SYuval Mintz p_hwfn->dmae_info.p_dmae_cmd->opcode_b = cpu_to_le16(opcode_b); 464fe56b9e6SYuval Mintz } 465fe56b9e6SYuval Mintz 466fe56b9e6SYuval Mintz u32 qed_dmae_idx_to_go_cmd(u8 idx) 467fe56b9e6SYuval Mintz { 468fe56b9e6SYuval Mintz /* All the DMAE 'go' registers form an array in internal memory */ 469fe56b9e6SYuval Mintz return DMAE_REG_GO_C0 + (idx << 2); 470fe56b9e6SYuval Mintz } 471fe56b9e6SYuval Mintz 4721a635e48SYuval Mintz static int qed_dmae_post_command(struct qed_hwfn *p_hwfn, 473fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 474fe56b9e6SYuval Mintz { 4751a635e48SYuval Mintz struct dmae_cmd *p_command = p_hwfn->dmae_info.p_dmae_cmd; 476fe56b9e6SYuval Mintz u8 idx_cmd = p_hwfn->dmae_info.channel, i; 477fe56b9e6SYuval Mintz int qed_status = 0; 478fe56b9e6SYuval Mintz 479fe56b9e6SYuval Mintz /* verify address is not NULL */ 4801a635e48SYuval Mintz if ((((!p_command->dst_addr_lo) && (!p_command->dst_addr_hi)) || 4811a635e48SYuval Mintz ((!p_command->src_addr_lo) && (!p_command->src_addr_hi)))) { 482fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 483fe56b9e6SYuval Mintz "source or destination address 0 idx_cmd=%d\n" 484fe56b9e6SYuval Mintz "opcode = [0x%08x,0x%04x] len=0x%x src=0x%x:%x dst=0x%x:%x\n", 485fe56b9e6SYuval Mintz idx_cmd, 4861a635e48SYuval Mintz le32_to_cpu(p_command->opcode), 4871a635e48SYuval Mintz le16_to_cpu(p_command->opcode_b), 4881a635e48SYuval Mintz le16_to_cpu(p_command->length_dw), 4891a635e48SYuval Mintz le32_to_cpu(p_command->src_addr_hi), 4901a635e48SYuval Mintz le32_to_cpu(p_command->src_addr_lo), 4911a635e48SYuval Mintz le32_to_cpu(p_command->dst_addr_hi), 4921a635e48SYuval Mintz le32_to_cpu(p_command->dst_addr_lo)); 493fe56b9e6SYuval Mintz 494fe56b9e6SYuval Mintz return -EINVAL; 495fe56b9e6SYuval Mintz } 496fe56b9e6SYuval Mintz 497fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, 498fe56b9e6SYuval Mintz NETIF_MSG_HW, 499fe56b9e6SYuval Mintz "Posting DMAE command [idx %d]: opcode = [0x%08x,0x%04x] len=0x%x src=0x%x:%x dst=0x%x:%x\n", 500fe56b9e6SYuval Mintz idx_cmd, 5011a635e48SYuval Mintz le32_to_cpu(p_command->opcode), 5021a635e48SYuval Mintz le16_to_cpu(p_command->opcode_b), 5031a635e48SYuval Mintz le16_to_cpu(p_command->length_dw), 5041a635e48SYuval Mintz le32_to_cpu(p_command->src_addr_hi), 5051a635e48SYuval Mintz le32_to_cpu(p_command->src_addr_lo), 5061a635e48SYuval Mintz le32_to_cpu(p_command->dst_addr_hi), 5071a635e48SYuval Mintz le32_to_cpu(p_command->dst_addr_lo)); 508fe56b9e6SYuval Mintz 509fe56b9e6SYuval Mintz /* Copy the command to DMAE - need to do it before every call 510fe56b9e6SYuval Mintz * for source/dest address no reset. 511fe56b9e6SYuval Mintz * The first 9 DWs are the command registers, the 10 DW is the 512fe56b9e6SYuval Mintz * GO register, and the rest are result registers 513fe56b9e6SYuval Mintz * (which are read only by the client). 514fe56b9e6SYuval Mintz */ 515fe56b9e6SYuval Mintz for (i = 0; i < DMAE_CMD_SIZE; i++) { 516fe56b9e6SYuval Mintz u32 data = (i < DMAE_CMD_SIZE_TO_FILL) ? 5171a635e48SYuval Mintz *(((u32 *)p_command) + i) : 0; 518fe56b9e6SYuval Mintz 519fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 520fe56b9e6SYuval Mintz DMAE_REG_CMD_MEM + 521fe56b9e6SYuval Mintz (idx_cmd * DMAE_CMD_SIZE * sizeof(u32)) + 522fe56b9e6SYuval Mintz (i * sizeof(u32)), data); 523fe56b9e6SYuval Mintz } 524fe56b9e6SYuval Mintz 5251a635e48SYuval Mintz qed_wr(p_hwfn, p_ptt, qed_dmae_idx_to_go_cmd(idx_cmd), DMAE_GO_VALUE); 526fe56b9e6SYuval Mintz 527fe56b9e6SYuval Mintz return qed_status; 528fe56b9e6SYuval Mintz } 529fe56b9e6SYuval Mintz 530fe56b9e6SYuval Mintz int qed_dmae_info_alloc(struct qed_hwfn *p_hwfn) 531fe56b9e6SYuval Mintz { 532fe56b9e6SYuval Mintz dma_addr_t *p_addr = &p_hwfn->dmae_info.completion_word_phys_addr; 533fe56b9e6SYuval Mintz struct dmae_cmd **p_cmd = &p_hwfn->dmae_info.p_dmae_cmd; 534fe56b9e6SYuval Mintz u32 **p_buff = &p_hwfn->dmae_info.p_intermediate_buffer; 535fe56b9e6SYuval Mintz u32 **p_comp = &p_hwfn->dmae_info.p_completion_word; 536fe56b9e6SYuval Mintz 537fe56b9e6SYuval Mintz *p_comp = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 5381a635e48SYuval Mintz sizeof(u32), p_addr, GFP_KERNEL); 5392591c280SJoe Perches if (!*p_comp) 540fe56b9e6SYuval Mintz goto err; 541fe56b9e6SYuval Mintz 542fe56b9e6SYuval Mintz p_addr = &p_hwfn->dmae_info.dmae_cmd_phys_addr; 543fe56b9e6SYuval Mintz *p_cmd = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 544fe56b9e6SYuval Mintz sizeof(struct dmae_cmd), 545fe56b9e6SYuval Mintz p_addr, GFP_KERNEL); 5462591c280SJoe Perches if (!*p_cmd) 547fe56b9e6SYuval Mintz goto err; 548fe56b9e6SYuval Mintz 549fe56b9e6SYuval Mintz p_addr = &p_hwfn->dmae_info.intermediate_buffer_phys_addr; 550fe56b9e6SYuval Mintz *p_buff = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 551fe56b9e6SYuval Mintz sizeof(u32) * DMAE_MAX_RW_SIZE, 552fe56b9e6SYuval Mintz p_addr, GFP_KERNEL); 5532591c280SJoe Perches if (!*p_buff) 554fe56b9e6SYuval Mintz goto err; 555fe56b9e6SYuval Mintz 556fe56b9e6SYuval Mintz p_hwfn->dmae_info.channel = p_hwfn->rel_pf_id; 557fe56b9e6SYuval Mintz 558fe56b9e6SYuval Mintz return 0; 559fe56b9e6SYuval Mintz err: 560fe56b9e6SYuval Mintz qed_dmae_info_free(p_hwfn); 561fe56b9e6SYuval Mintz return -ENOMEM; 562fe56b9e6SYuval Mintz } 563fe56b9e6SYuval Mintz 564fe56b9e6SYuval Mintz void qed_dmae_info_free(struct qed_hwfn *p_hwfn) 565fe56b9e6SYuval Mintz { 566fe56b9e6SYuval Mintz dma_addr_t p_phys; 567fe56b9e6SYuval Mintz 568fe56b9e6SYuval Mintz /* Just make sure no one is in the middle */ 569fe56b9e6SYuval Mintz mutex_lock(&p_hwfn->dmae_info.mutex); 570fe56b9e6SYuval Mintz 571fe56b9e6SYuval Mintz if (p_hwfn->dmae_info.p_completion_word) { 572fe56b9e6SYuval Mintz p_phys = p_hwfn->dmae_info.completion_word_phys_addr; 573fe56b9e6SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 574fe56b9e6SYuval Mintz sizeof(u32), 5751a635e48SYuval Mintz p_hwfn->dmae_info.p_completion_word, p_phys); 576fe56b9e6SYuval Mintz p_hwfn->dmae_info.p_completion_word = NULL; 577fe56b9e6SYuval Mintz } 578fe56b9e6SYuval Mintz 579fe56b9e6SYuval Mintz if (p_hwfn->dmae_info.p_dmae_cmd) { 580fe56b9e6SYuval Mintz p_phys = p_hwfn->dmae_info.dmae_cmd_phys_addr; 581fe56b9e6SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 582fe56b9e6SYuval Mintz sizeof(struct dmae_cmd), 5831a635e48SYuval Mintz p_hwfn->dmae_info.p_dmae_cmd, p_phys); 584fe56b9e6SYuval Mintz p_hwfn->dmae_info.p_dmae_cmd = NULL; 585fe56b9e6SYuval Mintz } 586fe56b9e6SYuval Mintz 587fe56b9e6SYuval Mintz if (p_hwfn->dmae_info.p_intermediate_buffer) { 588fe56b9e6SYuval Mintz p_phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr; 589fe56b9e6SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 590fe56b9e6SYuval Mintz sizeof(u32) * DMAE_MAX_RW_SIZE, 591fe56b9e6SYuval Mintz p_hwfn->dmae_info.p_intermediate_buffer, 592fe56b9e6SYuval Mintz p_phys); 593fe56b9e6SYuval Mintz p_hwfn->dmae_info.p_intermediate_buffer = NULL; 594fe56b9e6SYuval Mintz } 595fe56b9e6SYuval Mintz 596fe56b9e6SYuval Mintz mutex_unlock(&p_hwfn->dmae_info.mutex); 597fe56b9e6SYuval Mintz } 598fe56b9e6SYuval Mintz 599fe56b9e6SYuval Mintz static int qed_dmae_operation_wait(struct qed_hwfn *p_hwfn) 600fe56b9e6SYuval Mintz { 6011a635e48SYuval Mintz u32 wait_cnt_limit = 10000, wait_cnt = 0; 602fe56b9e6SYuval Mintz int qed_status = 0; 603fe56b9e6SYuval Mintz 604fe56b9e6SYuval Mintz barrier(); 605fe56b9e6SYuval Mintz while (*p_hwfn->dmae_info.p_completion_word != DMAE_COMPLETION_VAL) { 606fe56b9e6SYuval Mintz udelay(DMAE_MIN_WAIT_TIME); 607fe56b9e6SYuval Mintz if (++wait_cnt > wait_cnt_limit) { 608fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn->cdev, 609fe56b9e6SYuval Mintz "Timed-out waiting for operation to complete. Completion word is 0x%08x expected 0x%08x.\n", 610fe56b9e6SYuval Mintz *p_hwfn->dmae_info.p_completion_word, 611fe56b9e6SYuval Mintz DMAE_COMPLETION_VAL); 612fe56b9e6SYuval Mintz qed_status = -EBUSY; 613fe56b9e6SYuval Mintz break; 614fe56b9e6SYuval Mintz } 615fe56b9e6SYuval Mintz 616fe56b9e6SYuval Mintz /* to sync the completion_word since we are not 617fe56b9e6SYuval Mintz * using the volatile keyword for p_completion_word 618fe56b9e6SYuval Mintz */ 619fe56b9e6SYuval Mintz barrier(); 620fe56b9e6SYuval Mintz } 621fe56b9e6SYuval Mintz 622fe56b9e6SYuval Mintz if (qed_status == 0) 623fe56b9e6SYuval Mintz *p_hwfn->dmae_info.p_completion_word = 0; 624fe56b9e6SYuval Mintz 625fe56b9e6SYuval Mintz return qed_status; 626fe56b9e6SYuval Mintz } 627fe56b9e6SYuval Mintz 628fe56b9e6SYuval Mintz static int qed_dmae_execute_sub_operation(struct qed_hwfn *p_hwfn, 629fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 630fe56b9e6SYuval Mintz u64 src_addr, 631fe56b9e6SYuval Mintz u64 dst_addr, 632fe56b9e6SYuval Mintz u8 src_type, 633fe56b9e6SYuval Mintz u8 dst_type, 6341a635e48SYuval Mintz u32 length_dw) 635fe56b9e6SYuval Mintz { 636fe56b9e6SYuval Mintz dma_addr_t phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr; 637fe56b9e6SYuval Mintz struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd; 638fe56b9e6SYuval Mintz int qed_status = 0; 639fe56b9e6SYuval Mintz 640fe56b9e6SYuval Mintz switch (src_type) { 641fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_GRC: 642fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_HOST_PHYS: 643fe56b9e6SYuval Mintz cmd->src_addr_hi = cpu_to_le32(upper_32_bits(src_addr)); 644fe56b9e6SYuval Mintz cmd->src_addr_lo = cpu_to_le32(lower_32_bits(src_addr)); 645fe56b9e6SYuval Mintz break; 646fe56b9e6SYuval Mintz /* for virtual source addresses we use the intermediate buffer. */ 647fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_HOST_VIRT: 648fe56b9e6SYuval Mintz cmd->src_addr_hi = cpu_to_le32(upper_32_bits(phys)); 649fe56b9e6SYuval Mintz cmd->src_addr_lo = cpu_to_le32(lower_32_bits(phys)); 650fe56b9e6SYuval Mintz memcpy(&p_hwfn->dmae_info.p_intermediate_buffer[0], 651fe56b9e6SYuval Mintz (void *)(uintptr_t)src_addr, 6521a635e48SYuval Mintz length_dw * sizeof(u32)); 653fe56b9e6SYuval Mintz break; 654fe56b9e6SYuval Mintz default: 655fe56b9e6SYuval Mintz return -EINVAL; 656fe56b9e6SYuval Mintz } 657fe56b9e6SYuval Mintz 658fe56b9e6SYuval Mintz switch (dst_type) { 659fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_GRC: 660fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_HOST_PHYS: 661fe56b9e6SYuval Mintz cmd->dst_addr_hi = cpu_to_le32(upper_32_bits(dst_addr)); 662fe56b9e6SYuval Mintz cmd->dst_addr_lo = cpu_to_le32(lower_32_bits(dst_addr)); 663fe56b9e6SYuval Mintz break; 664fe56b9e6SYuval Mintz /* for virtual source addresses we use the intermediate buffer. */ 665fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_HOST_VIRT: 666fe56b9e6SYuval Mintz cmd->dst_addr_hi = cpu_to_le32(upper_32_bits(phys)); 667fe56b9e6SYuval Mintz cmd->dst_addr_lo = cpu_to_le32(lower_32_bits(phys)); 668fe56b9e6SYuval Mintz break; 669fe56b9e6SYuval Mintz default: 670fe56b9e6SYuval Mintz return -EINVAL; 671fe56b9e6SYuval Mintz } 672fe56b9e6SYuval Mintz 6731a635e48SYuval Mintz cmd->length_dw = cpu_to_le16((u16)length_dw); 674fe56b9e6SYuval Mintz 675fe56b9e6SYuval Mintz qed_dmae_post_command(p_hwfn, p_ptt); 676fe56b9e6SYuval Mintz 677fe56b9e6SYuval Mintz qed_status = qed_dmae_operation_wait(p_hwfn); 678fe56b9e6SYuval Mintz 679fe56b9e6SYuval Mintz if (qed_status) { 680fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 681fe56b9e6SYuval Mintz "qed_dmae_host2grc: Wait Failed. source_addr 0x%llx, grc_addr 0x%llx, size_in_dwords 0x%x\n", 6821a635e48SYuval Mintz src_addr, dst_addr, length_dw); 683fe56b9e6SYuval Mintz return qed_status; 684fe56b9e6SYuval Mintz } 685fe56b9e6SYuval Mintz 686fe56b9e6SYuval Mintz if (dst_type == QED_DMAE_ADDRESS_HOST_VIRT) 687fe56b9e6SYuval Mintz memcpy((void *)(uintptr_t)(dst_addr), 688fe56b9e6SYuval Mintz &p_hwfn->dmae_info.p_intermediate_buffer[0], 6891a635e48SYuval Mintz length_dw * sizeof(u32)); 690fe56b9e6SYuval Mintz 691fe56b9e6SYuval Mintz return 0; 692fe56b9e6SYuval Mintz } 693fe56b9e6SYuval Mintz 694fe56b9e6SYuval Mintz static int qed_dmae_execute_command(struct qed_hwfn *p_hwfn, 695fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 696fe56b9e6SYuval Mintz u64 src_addr, u64 dst_addr, 697fe56b9e6SYuval Mintz u8 src_type, u8 dst_type, 698fe56b9e6SYuval Mintz u32 size_in_dwords, 699fe56b9e6SYuval Mintz struct qed_dmae_params *p_params) 700fe56b9e6SYuval Mintz { 701fe56b9e6SYuval Mintz dma_addr_t phys = p_hwfn->dmae_info.completion_word_phys_addr; 702fe56b9e6SYuval Mintz u16 length_cur = 0, i = 0, cnt_split = 0, length_mod = 0; 703fe56b9e6SYuval Mintz struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd; 704fe56b9e6SYuval Mintz u64 src_addr_split = 0, dst_addr_split = 0; 705fe56b9e6SYuval Mintz u16 length_limit = DMAE_MAX_RW_SIZE; 706fe56b9e6SYuval Mintz int qed_status = 0; 707fe56b9e6SYuval Mintz u32 offset = 0; 708fe56b9e6SYuval Mintz 70964515dc8STomer Tayar if (p_hwfn->cdev->recov_in_prog) { 71064515dc8STomer Tayar DP_VERBOSE(p_hwfn, 71164515dc8STomer Tayar NETIF_MSG_HW, 71264515dc8STomer Tayar "Recovery is in progress. Avoid DMAE transaction [{src: addr 0x%llx, type %d}, {dst: addr 0x%llx, type %d}, size %d].\n", 71364515dc8STomer Tayar src_addr, src_type, dst_addr, dst_type, 71464515dc8STomer Tayar size_in_dwords); 71564515dc8STomer Tayar 71664515dc8STomer Tayar /* Let the flow complete w/o any error handling */ 71764515dc8STomer Tayar return 0; 71864515dc8STomer Tayar } 71964515dc8STomer Tayar 720fe56b9e6SYuval Mintz qed_dmae_opcode(p_hwfn, 721fe56b9e6SYuval Mintz (src_type == QED_DMAE_ADDRESS_GRC), 722fe56b9e6SYuval Mintz (dst_type == QED_DMAE_ADDRESS_GRC), 723fe56b9e6SYuval Mintz p_params); 724fe56b9e6SYuval Mintz 725fe56b9e6SYuval Mintz cmd->comp_addr_lo = cpu_to_le32(lower_32_bits(phys)); 726fe56b9e6SYuval Mintz cmd->comp_addr_hi = cpu_to_le32(upper_32_bits(phys)); 727fe56b9e6SYuval Mintz cmd->comp_val = cpu_to_le32(DMAE_COMPLETION_VAL); 728fe56b9e6SYuval Mintz 729fe56b9e6SYuval Mintz /* Check if the grc_addr is valid like < MAX_GRC_OFFSET */ 730fe56b9e6SYuval Mintz cnt_split = size_in_dwords / length_limit; 731fe56b9e6SYuval Mintz length_mod = size_in_dwords % length_limit; 732fe56b9e6SYuval Mintz 733fe56b9e6SYuval Mintz src_addr_split = src_addr; 734fe56b9e6SYuval Mintz dst_addr_split = dst_addr; 735fe56b9e6SYuval Mintz 736fe56b9e6SYuval Mintz for (i = 0; i <= cnt_split; i++) { 737fe56b9e6SYuval Mintz offset = length_limit * i; 738fe56b9e6SYuval Mintz 73983bf76e3SMichal Kalderon if (!QED_DMAE_FLAGS_IS_SET(p_params, RW_REPL_SRC)) { 740fe56b9e6SYuval Mintz if (src_type == QED_DMAE_ADDRESS_GRC) 741fe56b9e6SYuval Mintz src_addr_split = src_addr + offset; 742fe56b9e6SYuval Mintz else 743fe56b9e6SYuval Mintz src_addr_split = src_addr + (offset * 4); 744fe56b9e6SYuval Mintz } 745fe56b9e6SYuval Mintz 746fe56b9e6SYuval Mintz if (dst_type == QED_DMAE_ADDRESS_GRC) 747fe56b9e6SYuval Mintz dst_addr_split = dst_addr + offset; 748fe56b9e6SYuval Mintz else 749fe56b9e6SYuval Mintz dst_addr_split = dst_addr + (offset * 4); 750fe56b9e6SYuval Mintz 751fe56b9e6SYuval Mintz length_cur = (cnt_split == i) ? length_mod : length_limit; 752fe56b9e6SYuval Mintz 753fe56b9e6SYuval Mintz /* might be zero on last iteration */ 754fe56b9e6SYuval Mintz if (!length_cur) 755fe56b9e6SYuval Mintz continue; 756fe56b9e6SYuval Mintz 757fe56b9e6SYuval Mintz qed_status = qed_dmae_execute_sub_operation(p_hwfn, 758fe56b9e6SYuval Mintz p_ptt, 759fe56b9e6SYuval Mintz src_addr_split, 760fe56b9e6SYuval Mintz dst_addr_split, 761fe56b9e6SYuval Mintz src_type, 762fe56b9e6SYuval Mintz dst_type, 763fe56b9e6SYuval Mintz length_cur); 764fe56b9e6SYuval Mintz if (qed_status) { 7652ec276d5SIgor Russkikh qed_hw_err_notify(p_hwfn, p_ptt, QED_HW_ERR_DMAE_FAIL, 766fe56b9e6SYuval Mintz "qed_dmae_execute_sub_operation Failed with error 0x%x. source_addr 0x%llx, destination addr 0x%llx, size_in_dwords 0x%x\n", 7672ec276d5SIgor Russkikh qed_status, src_addr, 7682ec276d5SIgor Russkikh dst_addr, length_cur); 769fe56b9e6SYuval Mintz break; 770fe56b9e6SYuval Mintz } 771fe56b9e6SYuval Mintz } 772fe56b9e6SYuval Mintz 773fe56b9e6SYuval Mintz return qed_status; 774fe56b9e6SYuval Mintz } 775fe56b9e6SYuval Mintz 776fe56b9e6SYuval Mintz int qed_dmae_host2grc(struct qed_hwfn *p_hwfn, 777fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 77883bf76e3SMichal Kalderon u64 source_addr, u32 grc_addr, u32 size_in_dwords, 77983bf76e3SMichal Kalderon struct qed_dmae_params *p_params) 780fe56b9e6SYuval Mintz { 781fe56b9e6SYuval Mintz u32 grc_addr_in_dw = grc_addr / sizeof(u32); 782fe56b9e6SYuval Mintz int rc; 783fe56b9e6SYuval Mintz 784fe56b9e6SYuval Mintz 785fe56b9e6SYuval Mintz mutex_lock(&p_hwfn->dmae_info.mutex); 786fe56b9e6SYuval Mintz 787fe56b9e6SYuval Mintz rc = qed_dmae_execute_command(p_hwfn, p_ptt, source_addr, 788fe56b9e6SYuval Mintz grc_addr_in_dw, 789fe56b9e6SYuval Mintz QED_DMAE_ADDRESS_HOST_VIRT, 790fe56b9e6SYuval Mintz QED_DMAE_ADDRESS_GRC, 79183bf76e3SMichal Kalderon size_in_dwords, p_params); 792fe56b9e6SYuval Mintz 793fe56b9e6SYuval Mintz mutex_unlock(&p_hwfn->dmae_info.mutex); 794fe56b9e6SYuval Mintz 795fe56b9e6SYuval Mintz return rc; 796fe56b9e6SYuval Mintz } 797fe56b9e6SYuval Mintz 7981a635e48SYuval Mintz int qed_dmae_grc2host(struct qed_hwfn *p_hwfn, 7991a635e48SYuval Mintz struct qed_ptt *p_ptt, 8001a635e48SYuval Mintz u32 grc_addr, 80183bf76e3SMichal Kalderon dma_addr_t dest_addr, u32 size_in_dwords, 80283bf76e3SMichal Kalderon struct qed_dmae_params *p_params) 803722003acSSudarsana Reddy Kalluru { 804722003acSSudarsana Reddy Kalluru u32 grc_addr_in_dw = grc_addr / sizeof(u32); 805722003acSSudarsana Reddy Kalluru int rc; 806722003acSSudarsana Reddy Kalluru 807722003acSSudarsana Reddy Kalluru 808722003acSSudarsana Reddy Kalluru mutex_lock(&p_hwfn->dmae_info.mutex); 809722003acSSudarsana Reddy Kalluru 810722003acSSudarsana Reddy Kalluru rc = qed_dmae_execute_command(p_hwfn, p_ptt, grc_addr_in_dw, 811722003acSSudarsana Reddy Kalluru dest_addr, QED_DMAE_ADDRESS_GRC, 812722003acSSudarsana Reddy Kalluru QED_DMAE_ADDRESS_HOST_VIRT, 81383bf76e3SMichal Kalderon size_in_dwords, p_params); 814722003acSSudarsana Reddy Kalluru 815722003acSSudarsana Reddy Kalluru mutex_unlock(&p_hwfn->dmae_info.mutex); 816722003acSSudarsana Reddy Kalluru 817722003acSSudarsana Reddy Kalluru return rc; 818722003acSSudarsana Reddy Kalluru } 819722003acSSudarsana Reddy Kalluru 8201a635e48SYuval Mintz int qed_dmae_host2host(struct qed_hwfn *p_hwfn, 82137bff2b9SYuval Mintz struct qed_ptt *p_ptt, 82237bff2b9SYuval Mintz dma_addr_t source_addr, 82337bff2b9SYuval Mintz dma_addr_t dest_addr, 82437bff2b9SYuval Mintz u32 size_in_dwords, struct qed_dmae_params *p_params) 82537bff2b9SYuval Mintz { 82637bff2b9SYuval Mintz int rc; 82737bff2b9SYuval Mintz 82837bff2b9SYuval Mintz mutex_lock(&(p_hwfn->dmae_info.mutex)); 82937bff2b9SYuval Mintz 83037bff2b9SYuval Mintz rc = qed_dmae_execute_command(p_hwfn, p_ptt, source_addr, 83137bff2b9SYuval Mintz dest_addr, 83237bff2b9SYuval Mintz QED_DMAE_ADDRESS_HOST_PHYS, 83337bff2b9SYuval Mintz QED_DMAE_ADDRESS_HOST_PHYS, 83437bff2b9SYuval Mintz size_in_dwords, p_params); 83537bff2b9SYuval Mintz 83637bff2b9SYuval Mintz mutex_unlock(&(p_hwfn->dmae_info.mutex)); 83737bff2b9SYuval Mintz 83837bff2b9SYuval Mintz return rc; 83937bff2b9SYuval Mintz } 84037bff2b9SYuval Mintz 841d639836aSIgor Russkikh void qed_hw_err_notify(struct qed_hwfn *p_hwfn, 842d639836aSIgor Russkikh struct qed_ptt *p_ptt, 843d639836aSIgor Russkikh enum qed_hw_err_type err_type, char *fmt, ...) 844d639836aSIgor Russkikh { 845d639836aSIgor Russkikh char buf[QED_HW_ERR_MAX_STR_SIZE]; 846d639836aSIgor Russkikh va_list vl; 847d639836aSIgor Russkikh int len; 848d639836aSIgor Russkikh 849d639836aSIgor Russkikh if (fmt) { 850d639836aSIgor Russkikh va_start(vl, fmt); 851d639836aSIgor Russkikh len = vsnprintf(buf, QED_HW_ERR_MAX_STR_SIZE, fmt, vl); 852d639836aSIgor Russkikh va_end(vl); 853d639836aSIgor Russkikh 854d639836aSIgor Russkikh if (len > QED_HW_ERR_MAX_STR_SIZE - 1) 855d639836aSIgor Russkikh len = QED_HW_ERR_MAX_STR_SIZE - 1; 856d639836aSIgor Russkikh 857d639836aSIgor Russkikh DP_NOTICE(p_hwfn, "%s", buf); 858d639836aSIgor Russkikh } 859d639836aSIgor Russkikh 860d639836aSIgor Russkikh /* Fan failure cannot be masked by handling of another HW error */ 861d639836aSIgor Russkikh if (p_hwfn->cdev->recov_in_prog && 862d639836aSIgor Russkikh err_type != QED_HW_ERR_FAN_FAIL) { 863d639836aSIgor Russkikh DP_VERBOSE(p_hwfn, 864d639836aSIgor Russkikh NETIF_MSG_DRV, 865d639836aSIgor Russkikh "Recovery is in progress. Avoid notifying about HW error %d.\n", 866d639836aSIgor Russkikh err_type); 867d639836aSIgor Russkikh return; 868d639836aSIgor Russkikh } 869d639836aSIgor Russkikh 870d639836aSIgor Russkikh qed_hw_error_occurred(p_hwfn, err_type); 871d8d6c5a7SIgor Russkikh 872d8d6c5a7SIgor Russkikh if (fmt) 873d8d6c5a7SIgor Russkikh qed_mcp_send_raw_debug_data(p_hwfn, p_ptt, buf, len); 874d639836aSIgor Russkikh } 875d639836aSIgor Russkikh 876da090917STomer Tayar int qed_dmae_sanity(struct qed_hwfn *p_hwfn, 877da090917STomer Tayar struct qed_ptt *p_ptt, const char *phase) 878da090917STomer Tayar { 879da090917STomer Tayar u32 size = PAGE_SIZE / 2, val; 880da090917STomer Tayar int rc = 0; 881da090917STomer Tayar dma_addr_t p_phys; 882da090917STomer Tayar void *p_virt; 883da090917STomer Tayar u32 *p_tmp; 884da090917STomer Tayar 885da090917STomer Tayar p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 886da090917STomer Tayar 2 * size, &p_phys, GFP_KERNEL); 887da090917STomer Tayar if (!p_virt) { 888da090917STomer Tayar DP_NOTICE(p_hwfn, 889da090917STomer Tayar "DMAE sanity [%s]: failed to allocate memory\n", 890da090917STomer Tayar phase); 891da090917STomer Tayar return -ENOMEM; 892da090917STomer Tayar } 893da090917STomer Tayar 894da090917STomer Tayar /* Fill the bottom half of the allocated memory with a known pattern */ 895da090917STomer Tayar for (p_tmp = (u32 *)p_virt; 896da090917STomer Tayar p_tmp < (u32 *)((u8 *)p_virt + size); p_tmp++) { 897da090917STomer Tayar /* Save the address itself as the value */ 898da090917STomer Tayar val = (u32)(uintptr_t)p_tmp; 899da090917STomer Tayar *p_tmp = val; 900da090917STomer Tayar } 901da090917STomer Tayar 902da090917STomer Tayar /* Zero the top half of the allocated memory */ 903da090917STomer Tayar memset((u8 *)p_virt + size, 0, size); 904da090917STomer Tayar 905da090917STomer Tayar DP_VERBOSE(p_hwfn, 906da090917STomer Tayar QED_MSG_SP, 907da090917STomer Tayar "DMAE sanity [%s]: src_addr={phys 0x%llx, virt %p}, dst_addr={phys 0x%llx, virt %p}, size 0x%x\n", 908da090917STomer Tayar phase, 909da090917STomer Tayar (u64)p_phys, 910da090917STomer Tayar p_virt, (u64)(p_phys + size), (u8 *)p_virt + size, size); 911da090917STomer Tayar 912da090917STomer Tayar rc = qed_dmae_host2host(p_hwfn, p_ptt, p_phys, p_phys + size, 91383bf76e3SMichal Kalderon size / 4, NULL); 914da090917STomer Tayar if (rc) { 915da090917STomer Tayar DP_NOTICE(p_hwfn, 916da090917STomer Tayar "DMAE sanity [%s]: qed_dmae_host2host() failed. rc = %d.\n", 917da090917STomer Tayar phase, rc); 918da090917STomer Tayar goto out; 919da090917STomer Tayar } 920da090917STomer Tayar 921da090917STomer Tayar /* Verify that the top half of the allocated memory has the pattern */ 922da090917STomer Tayar for (p_tmp = (u32 *)((u8 *)p_virt + size); 923da090917STomer Tayar p_tmp < (u32 *)((u8 *)p_virt + (2 * size)); p_tmp++) { 924da090917STomer Tayar /* The corresponding address in the bottom half */ 925da090917STomer Tayar val = (u32)(uintptr_t)p_tmp - size; 926da090917STomer Tayar 927da090917STomer Tayar if (*p_tmp != val) { 928da090917STomer Tayar DP_NOTICE(p_hwfn, 929da090917STomer Tayar "DMAE sanity [%s]: addr={phys 0x%llx, virt %p}, read_val 0x%08x, expected_val 0x%08x\n", 930da090917STomer Tayar phase, 931da090917STomer Tayar (u64)p_phys + ((u8 *)p_tmp - (u8 *)p_virt), 932da090917STomer Tayar p_tmp, *p_tmp, val); 933da090917STomer Tayar rc = -EINVAL; 934da090917STomer Tayar goto out; 935da090917STomer Tayar } 936da090917STomer Tayar } 937da090917STomer Tayar 938da090917STomer Tayar out: 939da090917STomer Tayar dma_free_coherent(&p_hwfn->cdev->pdev->dev, 2 * size, p_virt, p_phys); 940da090917STomer Tayar return rc; 941da090917STomer Tayar } 942