1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2fe56b9e6SYuval Mintz * Copyright (c) 2015 QLogic Corporation 3fe56b9e6SYuval Mintz * 4fe56b9e6SYuval Mintz * This software is available under the terms of the GNU General Public License 5fe56b9e6SYuval Mintz * (GPL) Version 2, available from the file COPYING in the main directory of 6fe56b9e6SYuval Mintz * this source tree. 7fe56b9e6SYuval Mintz */ 8fe56b9e6SYuval Mintz 9fe56b9e6SYuval Mintz #include <linux/types.h> 10fe56b9e6SYuval Mintz #include <linux/io.h> 11fe56b9e6SYuval Mintz #include <linux/delay.h> 12fe56b9e6SYuval Mintz #include <linux/dma-mapping.h> 13fe56b9e6SYuval Mintz #include <linux/errno.h> 14fe56b9e6SYuval Mintz #include <linux/kernel.h> 15fe56b9e6SYuval Mintz #include <linux/list.h> 16fe56b9e6SYuval Mintz #include <linux/mutex.h> 17fe56b9e6SYuval Mintz #include <linux/pci.h> 18fe56b9e6SYuval Mintz #include <linux/slab.h> 19fe56b9e6SYuval Mintz #include <linux/spinlock.h> 20fe56b9e6SYuval Mintz #include <linux/string.h> 21fe56b9e6SYuval Mintz #include <linux/qed/qed_chain.h> 22fe56b9e6SYuval Mintz #include "qed.h" 23fe56b9e6SYuval Mintz #include "qed_hsi.h" 24fe56b9e6SYuval Mintz #include "qed_hw.h" 25fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 26fe56b9e6SYuval Mintz 27fe56b9e6SYuval Mintz #define QED_BAR_ACQUIRE_TIMEOUT 1000 28fe56b9e6SYuval Mintz 29fe56b9e6SYuval Mintz /* Invalid values */ 30fe56b9e6SYuval Mintz #define QED_BAR_INVALID_OFFSET (cpu_to_le32(-1)) 31fe56b9e6SYuval Mintz 32fe56b9e6SYuval Mintz struct qed_ptt { 33fe56b9e6SYuval Mintz struct list_head list_entry; 34fe56b9e6SYuval Mintz unsigned int idx; 35fe56b9e6SYuval Mintz struct pxp_ptt_entry pxp; 36fe56b9e6SYuval Mintz }; 37fe56b9e6SYuval Mintz 38fe56b9e6SYuval Mintz struct qed_ptt_pool { 39fe56b9e6SYuval Mintz struct list_head free_list; 40fe56b9e6SYuval Mintz spinlock_t lock; /* ptt synchronized access */ 41fe56b9e6SYuval Mintz struct qed_ptt ptts[PXP_EXTERNAL_BAR_PF_WINDOW_NUM]; 42fe56b9e6SYuval Mintz }; 43fe56b9e6SYuval Mintz 44fe56b9e6SYuval Mintz int qed_ptt_pool_alloc(struct qed_hwfn *p_hwfn) 45fe56b9e6SYuval Mintz { 46fe56b9e6SYuval Mintz struct qed_ptt_pool *p_pool = kmalloc(sizeof(*p_pool), 4760fffb3bSYuval Mintz GFP_KERNEL); 48fe56b9e6SYuval Mintz int i; 49fe56b9e6SYuval Mintz 50fe56b9e6SYuval Mintz if (!p_pool) 51fe56b9e6SYuval Mintz return -ENOMEM; 52fe56b9e6SYuval Mintz 53fe56b9e6SYuval Mintz INIT_LIST_HEAD(&p_pool->free_list); 54fe56b9e6SYuval Mintz for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) { 55fe56b9e6SYuval Mintz p_pool->ptts[i].idx = i; 56fe56b9e6SYuval Mintz p_pool->ptts[i].pxp.offset = QED_BAR_INVALID_OFFSET; 57fe56b9e6SYuval Mintz p_pool->ptts[i].pxp.pretend.control = 0; 58fe56b9e6SYuval Mintz if (i >= RESERVED_PTT_MAX) 59fe56b9e6SYuval Mintz list_add(&p_pool->ptts[i].list_entry, 60fe56b9e6SYuval Mintz &p_pool->free_list); 61fe56b9e6SYuval Mintz } 62fe56b9e6SYuval Mintz 63fe56b9e6SYuval Mintz p_hwfn->p_ptt_pool = p_pool; 64fe56b9e6SYuval Mintz spin_lock_init(&p_pool->lock); 65fe56b9e6SYuval Mintz 66fe56b9e6SYuval Mintz return 0; 67fe56b9e6SYuval Mintz } 68fe56b9e6SYuval Mintz 69fe56b9e6SYuval Mintz void qed_ptt_invalidate(struct qed_hwfn *p_hwfn) 70fe56b9e6SYuval Mintz { 71fe56b9e6SYuval Mintz struct qed_ptt *p_ptt; 72fe56b9e6SYuval Mintz int i; 73fe56b9e6SYuval Mintz 74fe56b9e6SYuval Mintz for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) { 75fe56b9e6SYuval Mintz p_ptt = &p_hwfn->p_ptt_pool->ptts[i]; 76fe56b9e6SYuval Mintz p_ptt->pxp.offset = QED_BAR_INVALID_OFFSET; 77fe56b9e6SYuval Mintz } 78fe56b9e6SYuval Mintz } 79fe56b9e6SYuval Mintz 80fe56b9e6SYuval Mintz void qed_ptt_pool_free(struct qed_hwfn *p_hwfn) 81fe56b9e6SYuval Mintz { 82fe56b9e6SYuval Mintz kfree(p_hwfn->p_ptt_pool); 83fe56b9e6SYuval Mintz p_hwfn->p_ptt_pool = NULL; 84fe56b9e6SYuval Mintz } 85fe56b9e6SYuval Mintz 86fe56b9e6SYuval Mintz struct qed_ptt *qed_ptt_acquire(struct qed_hwfn *p_hwfn) 87fe56b9e6SYuval Mintz { 88fe56b9e6SYuval Mintz struct qed_ptt *p_ptt; 89fe56b9e6SYuval Mintz unsigned int i; 90fe56b9e6SYuval Mintz 91fe56b9e6SYuval Mintz /* Take the free PTT from the list */ 92fe56b9e6SYuval Mintz for (i = 0; i < QED_BAR_ACQUIRE_TIMEOUT; i++) { 93fe56b9e6SYuval Mintz spin_lock_bh(&p_hwfn->p_ptt_pool->lock); 94fe56b9e6SYuval Mintz 95fe56b9e6SYuval Mintz if (!list_empty(&p_hwfn->p_ptt_pool->free_list)) { 96fe56b9e6SYuval Mintz p_ptt = list_first_entry(&p_hwfn->p_ptt_pool->free_list, 97fe56b9e6SYuval Mintz struct qed_ptt, list_entry); 98fe56b9e6SYuval Mintz list_del(&p_ptt->list_entry); 99fe56b9e6SYuval Mintz 100fe56b9e6SYuval Mintz spin_unlock_bh(&p_hwfn->p_ptt_pool->lock); 101fe56b9e6SYuval Mintz 102fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 103fe56b9e6SYuval Mintz "allocated ptt %d\n", p_ptt->idx); 104fe56b9e6SYuval Mintz return p_ptt; 105fe56b9e6SYuval Mintz } 106fe56b9e6SYuval Mintz 107fe56b9e6SYuval Mintz spin_unlock_bh(&p_hwfn->p_ptt_pool->lock); 108fe56b9e6SYuval Mintz usleep_range(1000, 2000); 109fe56b9e6SYuval Mintz } 110fe56b9e6SYuval Mintz 111fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "PTT acquire timeout - failed to allocate PTT\n"); 112fe56b9e6SYuval Mintz return NULL; 113fe56b9e6SYuval Mintz } 114fe56b9e6SYuval Mintz 115fe56b9e6SYuval Mintz void qed_ptt_release(struct qed_hwfn *p_hwfn, 116fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 117fe56b9e6SYuval Mintz { 118fe56b9e6SYuval Mintz spin_lock_bh(&p_hwfn->p_ptt_pool->lock); 119fe56b9e6SYuval Mintz list_add(&p_ptt->list_entry, &p_hwfn->p_ptt_pool->free_list); 120fe56b9e6SYuval Mintz spin_unlock_bh(&p_hwfn->p_ptt_pool->lock); 121fe56b9e6SYuval Mintz } 122fe56b9e6SYuval Mintz 123fe56b9e6SYuval Mintz u32 qed_ptt_get_hw_addr(struct qed_hwfn *p_hwfn, 124fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 125fe56b9e6SYuval Mintz { 126fe56b9e6SYuval Mintz /* The HW is using DWORDS and we need to translate it to Bytes */ 127fe56b9e6SYuval Mintz return le32_to_cpu(p_ptt->pxp.offset) << 2; 128fe56b9e6SYuval Mintz } 129fe56b9e6SYuval Mintz 130fe56b9e6SYuval Mintz static u32 qed_ptt_config_addr(struct qed_ptt *p_ptt) 131fe56b9e6SYuval Mintz { 132fe56b9e6SYuval Mintz return PXP_PF_WINDOW_ADMIN_PER_PF_START + 133fe56b9e6SYuval Mintz p_ptt->idx * sizeof(struct pxp_ptt_entry); 134fe56b9e6SYuval Mintz } 135fe56b9e6SYuval Mintz 136fe56b9e6SYuval Mintz u32 qed_ptt_get_bar_addr(struct qed_ptt *p_ptt) 137fe56b9e6SYuval Mintz { 138fe56b9e6SYuval Mintz return PXP_EXTERNAL_BAR_PF_WINDOW_START + 139fe56b9e6SYuval Mintz p_ptt->idx * PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE; 140fe56b9e6SYuval Mintz } 141fe56b9e6SYuval Mintz 142fe56b9e6SYuval Mintz void qed_ptt_set_win(struct qed_hwfn *p_hwfn, 143fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 144fe56b9e6SYuval Mintz u32 new_hw_addr) 145fe56b9e6SYuval Mintz { 146fe56b9e6SYuval Mintz u32 prev_hw_addr; 147fe56b9e6SYuval Mintz 148fe56b9e6SYuval Mintz prev_hw_addr = qed_ptt_get_hw_addr(p_hwfn, p_ptt); 149fe56b9e6SYuval Mintz 150fe56b9e6SYuval Mintz if (new_hw_addr == prev_hw_addr) 151fe56b9e6SYuval Mintz return; 152fe56b9e6SYuval Mintz 153fe56b9e6SYuval Mintz /* Update PTT entery in admin window */ 154fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 155fe56b9e6SYuval Mintz "Updating PTT entry %d to offset 0x%x\n", 156fe56b9e6SYuval Mintz p_ptt->idx, new_hw_addr); 157fe56b9e6SYuval Mintz 158fe56b9e6SYuval Mintz /* The HW is using DWORDS and the address is in Bytes */ 159fe56b9e6SYuval Mintz p_ptt->pxp.offset = cpu_to_le32(new_hw_addr >> 2); 160fe56b9e6SYuval Mintz 161fe56b9e6SYuval Mintz REG_WR(p_hwfn, 162fe56b9e6SYuval Mintz qed_ptt_config_addr(p_ptt) + 163fe56b9e6SYuval Mintz offsetof(struct pxp_ptt_entry, offset), 164fe56b9e6SYuval Mintz le32_to_cpu(p_ptt->pxp.offset)); 165fe56b9e6SYuval Mintz } 166fe56b9e6SYuval Mintz 167fe56b9e6SYuval Mintz static u32 qed_set_ptt(struct qed_hwfn *p_hwfn, 168fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 169fe56b9e6SYuval Mintz u32 hw_addr) 170fe56b9e6SYuval Mintz { 171fe56b9e6SYuval Mintz u32 win_hw_addr = qed_ptt_get_hw_addr(p_hwfn, p_ptt); 172fe56b9e6SYuval Mintz u32 offset; 173fe56b9e6SYuval Mintz 174fe56b9e6SYuval Mintz offset = hw_addr - win_hw_addr; 175fe56b9e6SYuval Mintz 176fe56b9e6SYuval Mintz /* Verify the address is within the window */ 177fe56b9e6SYuval Mintz if (hw_addr < win_hw_addr || 178fe56b9e6SYuval Mintz offset >= PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) { 179fe56b9e6SYuval Mintz qed_ptt_set_win(p_hwfn, p_ptt, hw_addr); 180fe56b9e6SYuval Mintz offset = 0; 181fe56b9e6SYuval Mintz } 182fe56b9e6SYuval Mintz 183fe56b9e6SYuval Mintz return qed_ptt_get_bar_addr(p_ptt) + offset; 184fe56b9e6SYuval Mintz } 185fe56b9e6SYuval Mintz 186fe56b9e6SYuval Mintz struct qed_ptt *qed_get_reserved_ptt(struct qed_hwfn *p_hwfn, 187fe56b9e6SYuval Mintz enum reserved_ptts ptt_idx) 188fe56b9e6SYuval Mintz { 189fe56b9e6SYuval Mintz if (ptt_idx >= RESERVED_PTT_MAX) { 190fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 191fe56b9e6SYuval Mintz "Requested PTT %d is out of range\n", ptt_idx); 192fe56b9e6SYuval Mintz return NULL; 193fe56b9e6SYuval Mintz } 194fe56b9e6SYuval Mintz 195fe56b9e6SYuval Mintz return &p_hwfn->p_ptt_pool->ptts[ptt_idx]; 196fe56b9e6SYuval Mintz } 197fe56b9e6SYuval Mintz 198fe56b9e6SYuval Mintz void qed_wr(struct qed_hwfn *p_hwfn, 199fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 200fe56b9e6SYuval Mintz u32 hw_addr, u32 val) 201fe56b9e6SYuval Mintz { 202fe56b9e6SYuval Mintz u32 bar_addr = qed_set_ptt(p_hwfn, p_ptt, hw_addr); 203fe56b9e6SYuval Mintz 204fe56b9e6SYuval Mintz REG_WR(p_hwfn, bar_addr, val); 205fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 206fe56b9e6SYuval Mintz "bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n", 207fe56b9e6SYuval Mintz bar_addr, hw_addr, val); 208fe56b9e6SYuval Mintz } 209fe56b9e6SYuval Mintz 210fe56b9e6SYuval Mintz u32 qed_rd(struct qed_hwfn *p_hwfn, 211fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 212fe56b9e6SYuval Mintz u32 hw_addr) 213fe56b9e6SYuval Mintz { 214fe56b9e6SYuval Mintz u32 bar_addr = qed_set_ptt(p_hwfn, p_ptt, hw_addr); 215fe56b9e6SYuval Mintz u32 val = REG_RD(p_hwfn, bar_addr); 216fe56b9e6SYuval Mintz 217fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 218fe56b9e6SYuval Mintz "bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n", 219fe56b9e6SYuval Mintz bar_addr, hw_addr, val); 220fe56b9e6SYuval Mintz 221fe56b9e6SYuval Mintz return val; 222fe56b9e6SYuval Mintz } 223fe56b9e6SYuval Mintz 224fe56b9e6SYuval Mintz static void qed_memcpy_hw(struct qed_hwfn *p_hwfn, 225fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 226fe56b9e6SYuval Mintz void *addr, 227fe56b9e6SYuval Mintz u32 hw_addr, 228fe56b9e6SYuval Mintz size_t n, 229fe56b9e6SYuval Mintz bool to_device) 230fe56b9e6SYuval Mintz { 231fe56b9e6SYuval Mintz u32 dw_count, *host_addr, hw_offset; 232fe56b9e6SYuval Mintz size_t quota, done = 0; 233fe56b9e6SYuval Mintz u32 __iomem *reg_addr; 234fe56b9e6SYuval Mintz 235fe56b9e6SYuval Mintz while (done < n) { 236fe56b9e6SYuval Mintz quota = min_t(size_t, n - done, 237fe56b9e6SYuval Mintz PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE); 238fe56b9e6SYuval Mintz 239fe56b9e6SYuval Mintz qed_ptt_set_win(p_hwfn, p_ptt, hw_addr + done); 240fe56b9e6SYuval Mintz hw_offset = qed_ptt_get_bar_addr(p_ptt); 241fe56b9e6SYuval Mintz 242fe56b9e6SYuval Mintz dw_count = quota / 4; 243fe56b9e6SYuval Mintz host_addr = (u32 *)((u8 *)addr + done); 244fe56b9e6SYuval Mintz reg_addr = (u32 __iomem *)REG_ADDR(p_hwfn, hw_offset); 245fe56b9e6SYuval Mintz if (to_device) 246fe56b9e6SYuval Mintz while (dw_count--) 247fe56b9e6SYuval Mintz DIRECT_REG_WR(reg_addr++, *host_addr++); 248fe56b9e6SYuval Mintz else 249fe56b9e6SYuval Mintz while (dw_count--) 250fe56b9e6SYuval Mintz *host_addr++ = DIRECT_REG_RD(reg_addr++); 251fe56b9e6SYuval Mintz 252fe56b9e6SYuval Mintz done += quota; 253fe56b9e6SYuval Mintz } 254fe56b9e6SYuval Mintz } 255fe56b9e6SYuval Mintz 256fe56b9e6SYuval Mintz void qed_memcpy_from(struct qed_hwfn *p_hwfn, 257fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 258fe56b9e6SYuval Mintz void *dest, u32 hw_addr, size_t n) 259fe56b9e6SYuval Mintz { 260fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 261fe56b9e6SYuval Mintz "hw_addr 0x%x, dest %p hw_addr 0x%x, size %lu\n", 262fe56b9e6SYuval Mintz hw_addr, dest, hw_addr, (unsigned long)n); 263fe56b9e6SYuval Mintz 264fe56b9e6SYuval Mintz qed_memcpy_hw(p_hwfn, p_ptt, dest, hw_addr, n, false); 265fe56b9e6SYuval Mintz } 266fe56b9e6SYuval Mintz 267fe56b9e6SYuval Mintz void qed_memcpy_to(struct qed_hwfn *p_hwfn, 268fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 269fe56b9e6SYuval Mintz u32 hw_addr, void *src, size_t n) 270fe56b9e6SYuval Mintz { 271fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 272fe56b9e6SYuval Mintz "hw_addr 0x%x, hw_addr 0x%x, src %p size %lu\n", 273fe56b9e6SYuval Mintz hw_addr, hw_addr, src, (unsigned long)n); 274fe56b9e6SYuval Mintz 275fe56b9e6SYuval Mintz qed_memcpy_hw(p_hwfn, p_ptt, src, hw_addr, n, true); 276fe56b9e6SYuval Mintz } 277fe56b9e6SYuval Mintz 278fe56b9e6SYuval Mintz void qed_fid_pretend(struct qed_hwfn *p_hwfn, 279fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 280fe56b9e6SYuval Mintz u16 fid) 281fe56b9e6SYuval Mintz { 282fe56b9e6SYuval Mintz u16 control = 0; 283fe56b9e6SYuval Mintz 284fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_IS_CONCRETE, 1); 285fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_FUNCTION, 1); 286fe56b9e6SYuval Mintz 287fe56b9e6SYuval Mintz /* Every pretend undos previous pretends, including 288fe56b9e6SYuval Mintz * previous port pretend. 289fe56b9e6SYuval Mintz */ 290fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0); 291fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0); 292fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1); 293fe56b9e6SYuval Mintz 294fe56b9e6SYuval Mintz if (!GET_FIELD(fid, PXP_CONCRETE_FID_VFVALID)) 295fe56b9e6SYuval Mintz fid = GET_FIELD(fid, PXP_CONCRETE_FID_PFID); 296fe56b9e6SYuval Mintz 297fe56b9e6SYuval Mintz p_ptt->pxp.pretend.control = cpu_to_le16(control); 298fe56b9e6SYuval Mintz p_ptt->pxp.pretend.fid.concrete_fid.fid = cpu_to_le16(fid); 299fe56b9e6SYuval Mintz 300fe56b9e6SYuval Mintz REG_WR(p_hwfn, 301fe56b9e6SYuval Mintz qed_ptt_config_addr(p_ptt) + 302fe56b9e6SYuval Mintz offsetof(struct pxp_ptt_entry, pretend), 303fe56b9e6SYuval Mintz *(u32 *)&p_ptt->pxp.pretend); 304fe56b9e6SYuval Mintz } 305fe56b9e6SYuval Mintz 306fe56b9e6SYuval Mintz void qed_port_pretend(struct qed_hwfn *p_hwfn, 307fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 308fe56b9e6SYuval Mintz u8 port_id) 309fe56b9e6SYuval Mintz { 310fe56b9e6SYuval Mintz u16 control = 0; 311fe56b9e6SYuval Mintz 312fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PORT, port_id); 313fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 1); 314fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1); 315fe56b9e6SYuval Mintz 316fe56b9e6SYuval Mintz p_ptt->pxp.pretend.control = cpu_to_le16(control); 317fe56b9e6SYuval Mintz 318fe56b9e6SYuval Mintz REG_WR(p_hwfn, 319fe56b9e6SYuval Mintz qed_ptt_config_addr(p_ptt) + 320fe56b9e6SYuval Mintz offsetof(struct pxp_ptt_entry, pretend), 321fe56b9e6SYuval Mintz *(u32 *)&p_ptt->pxp.pretend); 322fe56b9e6SYuval Mintz } 323fe56b9e6SYuval Mintz 324fe56b9e6SYuval Mintz void qed_port_unpretend(struct qed_hwfn *p_hwfn, 325fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 326fe56b9e6SYuval Mintz { 327fe56b9e6SYuval Mintz u16 control = 0; 328fe56b9e6SYuval Mintz 329fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0); 330fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0); 331fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1); 332fe56b9e6SYuval Mintz 333fe56b9e6SYuval Mintz p_ptt->pxp.pretend.control = cpu_to_le16(control); 334fe56b9e6SYuval Mintz 335fe56b9e6SYuval Mintz REG_WR(p_hwfn, 336fe56b9e6SYuval Mintz qed_ptt_config_addr(p_ptt) + 337fe56b9e6SYuval Mintz offsetof(struct pxp_ptt_entry, pretend), 338fe56b9e6SYuval Mintz *(u32 *)&p_ptt->pxp.pretend); 339fe56b9e6SYuval Mintz } 340fe56b9e6SYuval Mintz 34132a47e72SYuval Mintz u32 qed_vfid_to_concrete(struct qed_hwfn *p_hwfn, u8 vfid) 34232a47e72SYuval Mintz { 34332a47e72SYuval Mintz u32 concrete_fid = 0; 34432a47e72SYuval Mintz 34532a47e72SYuval Mintz SET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID, p_hwfn->rel_pf_id); 34632a47e72SYuval Mintz SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID, vfid); 34732a47e72SYuval Mintz SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID, 1); 34832a47e72SYuval Mintz 34932a47e72SYuval Mintz return concrete_fid; 35032a47e72SYuval Mintz } 35132a47e72SYuval Mintz 352fe56b9e6SYuval Mintz /* DMAE */ 353fe56b9e6SYuval Mintz static void qed_dmae_opcode(struct qed_hwfn *p_hwfn, 354fe56b9e6SYuval Mintz const u8 is_src_type_grc, 355fe56b9e6SYuval Mintz const u8 is_dst_type_grc, 356fe56b9e6SYuval Mintz struct qed_dmae_params *p_params) 357fe56b9e6SYuval Mintz { 35837bff2b9SYuval Mintz u16 opcode_b = 0; 359fe56b9e6SYuval Mintz u32 opcode = 0; 360fe56b9e6SYuval Mintz 361fe56b9e6SYuval Mintz /* Whether the source is the PCIe or the GRC. 362fe56b9e6SYuval Mintz * 0- The source is the PCIe 363fe56b9e6SYuval Mintz * 1- The source is the GRC. 364fe56b9e6SYuval Mintz */ 365fe56b9e6SYuval Mintz opcode |= (is_src_type_grc ? DMAE_CMD_SRC_MASK_GRC 366fe56b9e6SYuval Mintz : DMAE_CMD_SRC_MASK_PCIE) << 367fe56b9e6SYuval Mintz DMAE_CMD_SRC_SHIFT; 368fe56b9e6SYuval Mintz opcode |= ((p_hwfn->rel_pf_id & DMAE_CMD_SRC_PF_ID_MASK) << 369fe56b9e6SYuval Mintz DMAE_CMD_SRC_PF_ID_SHIFT); 370fe56b9e6SYuval Mintz 371fe56b9e6SYuval Mintz /* The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */ 372fe56b9e6SYuval Mintz opcode |= (is_dst_type_grc ? DMAE_CMD_DST_MASK_GRC 373fe56b9e6SYuval Mintz : DMAE_CMD_DST_MASK_PCIE) << 374fe56b9e6SYuval Mintz DMAE_CMD_DST_SHIFT; 375fe56b9e6SYuval Mintz opcode |= ((p_hwfn->rel_pf_id & DMAE_CMD_DST_PF_ID_MASK) << 376fe56b9e6SYuval Mintz DMAE_CMD_DST_PF_ID_SHIFT); 377fe56b9e6SYuval Mintz 378fe56b9e6SYuval Mintz /* Whether to write a completion word to the completion destination: 379fe56b9e6SYuval Mintz * 0-Do not write a completion word 380fe56b9e6SYuval Mintz * 1-Write the completion word 381fe56b9e6SYuval Mintz */ 382fe56b9e6SYuval Mintz opcode |= (DMAE_CMD_COMP_WORD_EN_MASK << DMAE_CMD_COMP_WORD_EN_SHIFT); 383fe56b9e6SYuval Mintz opcode |= (DMAE_CMD_SRC_ADDR_RESET_MASK << 384fe56b9e6SYuval Mintz DMAE_CMD_SRC_ADDR_RESET_SHIFT); 385fe56b9e6SYuval Mintz 386fe56b9e6SYuval Mintz if (p_params->flags & QED_DMAE_FLAG_COMPLETION_DST) 387fe56b9e6SYuval Mintz opcode |= (1 << DMAE_CMD_COMP_FUNC_SHIFT); 388fe56b9e6SYuval Mintz 389fe56b9e6SYuval Mintz opcode |= (DMAE_CMD_ENDIANITY << DMAE_CMD_ENDIANITY_MODE_SHIFT); 390fe56b9e6SYuval Mintz 391fe56b9e6SYuval Mintz opcode |= ((p_hwfn->port_id) << DMAE_CMD_PORT_ID_SHIFT); 392fe56b9e6SYuval Mintz 393fe56b9e6SYuval Mintz /* reset source address in next go */ 394fe56b9e6SYuval Mintz opcode |= (DMAE_CMD_SRC_ADDR_RESET_MASK << 395fe56b9e6SYuval Mintz DMAE_CMD_SRC_ADDR_RESET_SHIFT); 396fe56b9e6SYuval Mintz 397fe56b9e6SYuval Mintz /* reset dest address in next go */ 398fe56b9e6SYuval Mintz opcode |= (DMAE_CMD_DST_ADDR_RESET_MASK << 399fe56b9e6SYuval Mintz DMAE_CMD_DST_ADDR_RESET_SHIFT); 400fe56b9e6SYuval Mintz 40137bff2b9SYuval Mintz /* SRC/DST VFID: all 1's - pf, otherwise VF id */ 40237bff2b9SYuval Mintz if (p_params->flags & QED_DMAE_FLAG_VF_SRC) { 40337bff2b9SYuval Mintz opcode |= 1 << DMAE_CMD_SRC_VF_ID_VALID_SHIFT; 40437bff2b9SYuval Mintz opcode_b |= p_params->src_vfid << DMAE_CMD_SRC_VF_ID_SHIFT; 40537bff2b9SYuval Mintz } else { 40637bff2b9SYuval Mintz opcode_b |= DMAE_CMD_SRC_VF_ID_MASK << 40737bff2b9SYuval Mintz DMAE_CMD_SRC_VF_ID_SHIFT; 40837bff2b9SYuval Mintz } 409fe56b9e6SYuval Mintz 41037bff2b9SYuval Mintz if (p_params->flags & QED_DMAE_FLAG_VF_DST) { 41137bff2b9SYuval Mintz opcode |= 1 << DMAE_CMD_DST_VF_ID_VALID_SHIFT; 41237bff2b9SYuval Mintz opcode_b |= p_params->dst_vfid << DMAE_CMD_DST_VF_ID_SHIFT; 41337bff2b9SYuval Mintz } else { 41437bff2b9SYuval Mintz opcode_b |= DMAE_CMD_DST_VF_ID_MASK << DMAE_CMD_DST_VF_ID_SHIFT; 41537bff2b9SYuval Mintz } 416fe56b9e6SYuval Mintz 417fe56b9e6SYuval Mintz p_hwfn->dmae_info.p_dmae_cmd->opcode = cpu_to_le32(opcode); 41837bff2b9SYuval Mintz p_hwfn->dmae_info.p_dmae_cmd->opcode_b = cpu_to_le16(opcode_b); 419fe56b9e6SYuval Mintz } 420fe56b9e6SYuval Mintz 421fe56b9e6SYuval Mintz u32 qed_dmae_idx_to_go_cmd(u8 idx) 422fe56b9e6SYuval Mintz { 423fe56b9e6SYuval Mintz /* All the DMAE 'go' registers form an array in internal memory */ 424fe56b9e6SYuval Mintz return DMAE_REG_GO_C0 + (idx << 2); 425fe56b9e6SYuval Mintz } 426fe56b9e6SYuval Mintz 427fe56b9e6SYuval Mintz static int 428fe56b9e6SYuval Mintz qed_dmae_post_command(struct qed_hwfn *p_hwfn, 429fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 430fe56b9e6SYuval Mintz { 431fe56b9e6SYuval Mintz struct dmae_cmd *command = p_hwfn->dmae_info.p_dmae_cmd; 432fe56b9e6SYuval Mintz u8 idx_cmd = p_hwfn->dmae_info.channel, i; 433fe56b9e6SYuval Mintz int qed_status = 0; 434fe56b9e6SYuval Mintz 435fe56b9e6SYuval Mintz /* verify address is not NULL */ 436fe56b9e6SYuval Mintz if ((((command->dst_addr_lo == 0) && (command->dst_addr_hi == 0)) || 437fe56b9e6SYuval Mintz ((command->src_addr_lo == 0) && (command->src_addr_hi == 0)))) { 438fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 439fe56b9e6SYuval Mintz "source or destination address 0 idx_cmd=%d\n" 440fe56b9e6SYuval Mintz "opcode = [0x%08x,0x%04x] len=0x%x src=0x%x:%x dst=0x%x:%x\n", 441fe56b9e6SYuval Mintz idx_cmd, 442fe56b9e6SYuval Mintz le32_to_cpu(command->opcode), 443fe56b9e6SYuval Mintz le16_to_cpu(command->opcode_b), 444fe56b9e6SYuval Mintz le16_to_cpu(command->length), 445fe56b9e6SYuval Mintz le32_to_cpu(command->src_addr_hi), 446fe56b9e6SYuval Mintz le32_to_cpu(command->src_addr_lo), 447fe56b9e6SYuval Mintz le32_to_cpu(command->dst_addr_hi), 448fe56b9e6SYuval Mintz le32_to_cpu(command->dst_addr_lo)); 449fe56b9e6SYuval Mintz 450fe56b9e6SYuval Mintz return -EINVAL; 451fe56b9e6SYuval Mintz } 452fe56b9e6SYuval Mintz 453fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, 454fe56b9e6SYuval Mintz NETIF_MSG_HW, 455fe56b9e6SYuval Mintz "Posting DMAE command [idx %d]: opcode = [0x%08x,0x%04x] len=0x%x src=0x%x:%x dst=0x%x:%x\n", 456fe56b9e6SYuval Mintz idx_cmd, 457fe56b9e6SYuval Mintz le32_to_cpu(command->opcode), 458fe56b9e6SYuval Mintz le16_to_cpu(command->opcode_b), 459fe56b9e6SYuval Mintz le16_to_cpu(command->length), 460fe56b9e6SYuval Mintz le32_to_cpu(command->src_addr_hi), 461fe56b9e6SYuval Mintz le32_to_cpu(command->src_addr_lo), 462fe56b9e6SYuval Mintz le32_to_cpu(command->dst_addr_hi), 463fe56b9e6SYuval Mintz le32_to_cpu(command->dst_addr_lo)); 464fe56b9e6SYuval Mintz 465fe56b9e6SYuval Mintz /* Copy the command to DMAE - need to do it before every call 466fe56b9e6SYuval Mintz * for source/dest address no reset. 467fe56b9e6SYuval Mintz * The first 9 DWs are the command registers, the 10 DW is the 468fe56b9e6SYuval Mintz * GO register, and the rest are result registers 469fe56b9e6SYuval Mintz * (which are read only by the client). 470fe56b9e6SYuval Mintz */ 471fe56b9e6SYuval Mintz for (i = 0; i < DMAE_CMD_SIZE; i++) { 472fe56b9e6SYuval Mintz u32 data = (i < DMAE_CMD_SIZE_TO_FILL) ? 473fe56b9e6SYuval Mintz *(((u32 *)command) + i) : 0; 474fe56b9e6SYuval Mintz 475fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 476fe56b9e6SYuval Mintz DMAE_REG_CMD_MEM + 477fe56b9e6SYuval Mintz (idx_cmd * DMAE_CMD_SIZE * sizeof(u32)) + 478fe56b9e6SYuval Mintz (i * sizeof(u32)), data); 479fe56b9e6SYuval Mintz } 480fe56b9e6SYuval Mintz 481fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 482fe56b9e6SYuval Mintz qed_dmae_idx_to_go_cmd(idx_cmd), 483fe56b9e6SYuval Mintz DMAE_GO_VALUE); 484fe56b9e6SYuval Mintz 485fe56b9e6SYuval Mintz return qed_status; 486fe56b9e6SYuval Mintz } 487fe56b9e6SYuval Mintz 488fe56b9e6SYuval Mintz int qed_dmae_info_alloc(struct qed_hwfn *p_hwfn) 489fe56b9e6SYuval Mintz { 490fe56b9e6SYuval Mintz dma_addr_t *p_addr = &p_hwfn->dmae_info.completion_word_phys_addr; 491fe56b9e6SYuval Mintz struct dmae_cmd **p_cmd = &p_hwfn->dmae_info.p_dmae_cmd; 492fe56b9e6SYuval Mintz u32 **p_buff = &p_hwfn->dmae_info.p_intermediate_buffer; 493fe56b9e6SYuval Mintz u32 **p_comp = &p_hwfn->dmae_info.p_completion_word; 494fe56b9e6SYuval Mintz 495fe56b9e6SYuval Mintz *p_comp = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 496fe56b9e6SYuval Mintz sizeof(u32), 497fe56b9e6SYuval Mintz p_addr, 498fe56b9e6SYuval Mintz GFP_KERNEL); 499fe56b9e6SYuval Mintz if (!*p_comp) { 500fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed to allocate `p_completion_word'\n"); 501fe56b9e6SYuval Mintz goto err; 502fe56b9e6SYuval Mintz } 503fe56b9e6SYuval Mintz 504fe56b9e6SYuval Mintz p_addr = &p_hwfn->dmae_info.dmae_cmd_phys_addr; 505fe56b9e6SYuval Mintz *p_cmd = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 506fe56b9e6SYuval Mintz sizeof(struct dmae_cmd), 507fe56b9e6SYuval Mintz p_addr, GFP_KERNEL); 508fe56b9e6SYuval Mintz if (!*p_cmd) { 509fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed to allocate `struct dmae_cmd'\n"); 510fe56b9e6SYuval Mintz goto err; 511fe56b9e6SYuval Mintz } 512fe56b9e6SYuval Mintz 513fe56b9e6SYuval Mintz p_addr = &p_hwfn->dmae_info.intermediate_buffer_phys_addr; 514fe56b9e6SYuval Mintz *p_buff = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 515fe56b9e6SYuval Mintz sizeof(u32) * DMAE_MAX_RW_SIZE, 516fe56b9e6SYuval Mintz p_addr, GFP_KERNEL); 517fe56b9e6SYuval Mintz if (!*p_buff) { 518fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed to allocate `intermediate_buffer'\n"); 519fe56b9e6SYuval Mintz goto err; 520fe56b9e6SYuval Mintz } 521fe56b9e6SYuval Mintz 522fe56b9e6SYuval Mintz p_hwfn->dmae_info.channel = p_hwfn->rel_pf_id; 523fe56b9e6SYuval Mintz 524fe56b9e6SYuval Mintz return 0; 525fe56b9e6SYuval Mintz err: 526fe56b9e6SYuval Mintz qed_dmae_info_free(p_hwfn); 527fe56b9e6SYuval Mintz return -ENOMEM; 528fe56b9e6SYuval Mintz } 529fe56b9e6SYuval Mintz 530fe56b9e6SYuval Mintz void qed_dmae_info_free(struct qed_hwfn *p_hwfn) 531fe56b9e6SYuval Mintz { 532fe56b9e6SYuval Mintz dma_addr_t p_phys; 533fe56b9e6SYuval Mintz 534fe56b9e6SYuval Mintz /* Just make sure no one is in the middle */ 535fe56b9e6SYuval Mintz mutex_lock(&p_hwfn->dmae_info.mutex); 536fe56b9e6SYuval Mintz 537fe56b9e6SYuval Mintz if (p_hwfn->dmae_info.p_completion_word) { 538fe56b9e6SYuval Mintz p_phys = p_hwfn->dmae_info.completion_word_phys_addr; 539fe56b9e6SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 540fe56b9e6SYuval Mintz sizeof(u32), 541fe56b9e6SYuval Mintz p_hwfn->dmae_info.p_completion_word, 542fe56b9e6SYuval Mintz p_phys); 543fe56b9e6SYuval Mintz p_hwfn->dmae_info.p_completion_word = NULL; 544fe56b9e6SYuval Mintz } 545fe56b9e6SYuval Mintz 546fe56b9e6SYuval Mintz if (p_hwfn->dmae_info.p_dmae_cmd) { 547fe56b9e6SYuval Mintz p_phys = p_hwfn->dmae_info.dmae_cmd_phys_addr; 548fe56b9e6SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 549fe56b9e6SYuval Mintz sizeof(struct dmae_cmd), 550fe56b9e6SYuval Mintz p_hwfn->dmae_info.p_dmae_cmd, 551fe56b9e6SYuval Mintz p_phys); 552fe56b9e6SYuval Mintz p_hwfn->dmae_info.p_dmae_cmd = NULL; 553fe56b9e6SYuval Mintz } 554fe56b9e6SYuval Mintz 555fe56b9e6SYuval Mintz if (p_hwfn->dmae_info.p_intermediate_buffer) { 556fe56b9e6SYuval Mintz p_phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr; 557fe56b9e6SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 558fe56b9e6SYuval Mintz sizeof(u32) * DMAE_MAX_RW_SIZE, 559fe56b9e6SYuval Mintz p_hwfn->dmae_info.p_intermediate_buffer, 560fe56b9e6SYuval Mintz p_phys); 561fe56b9e6SYuval Mintz p_hwfn->dmae_info.p_intermediate_buffer = NULL; 562fe56b9e6SYuval Mintz } 563fe56b9e6SYuval Mintz 564fe56b9e6SYuval Mintz mutex_unlock(&p_hwfn->dmae_info.mutex); 565fe56b9e6SYuval Mintz } 566fe56b9e6SYuval Mintz 567fe56b9e6SYuval Mintz static int qed_dmae_operation_wait(struct qed_hwfn *p_hwfn) 568fe56b9e6SYuval Mintz { 569fe56b9e6SYuval Mintz u32 wait_cnt = 0; 570fe56b9e6SYuval Mintz u32 wait_cnt_limit = 10000; 571fe56b9e6SYuval Mintz 572fe56b9e6SYuval Mintz int qed_status = 0; 573fe56b9e6SYuval Mintz 574fe56b9e6SYuval Mintz barrier(); 575fe56b9e6SYuval Mintz while (*p_hwfn->dmae_info.p_completion_word != DMAE_COMPLETION_VAL) { 576fe56b9e6SYuval Mintz udelay(DMAE_MIN_WAIT_TIME); 577fe56b9e6SYuval Mintz if (++wait_cnt > wait_cnt_limit) { 578fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn->cdev, 579fe56b9e6SYuval Mintz "Timed-out waiting for operation to complete. Completion word is 0x%08x expected 0x%08x.\n", 580fe56b9e6SYuval Mintz *p_hwfn->dmae_info.p_completion_word, 581fe56b9e6SYuval Mintz DMAE_COMPLETION_VAL); 582fe56b9e6SYuval Mintz qed_status = -EBUSY; 583fe56b9e6SYuval Mintz break; 584fe56b9e6SYuval Mintz } 585fe56b9e6SYuval Mintz 586fe56b9e6SYuval Mintz /* to sync the completion_word since we are not 587fe56b9e6SYuval Mintz * using the volatile keyword for p_completion_word 588fe56b9e6SYuval Mintz */ 589fe56b9e6SYuval Mintz barrier(); 590fe56b9e6SYuval Mintz } 591fe56b9e6SYuval Mintz 592fe56b9e6SYuval Mintz if (qed_status == 0) 593fe56b9e6SYuval Mintz *p_hwfn->dmae_info.p_completion_word = 0; 594fe56b9e6SYuval Mintz 595fe56b9e6SYuval Mintz return qed_status; 596fe56b9e6SYuval Mintz } 597fe56b9e6SYuval Mintz 598fe56b9e6SYuval Mintz static int qed_dmae_execute_sub_operation(struct qed_hwfn *p_hwfn, 599fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 600fe56b9e6SYuval Mintz u64 src_addr, 601fe56b9e6SYuval Mintz u64 dst_addr, 602fe56b9e6SYuval Mintz u8 src_type, 603fe56b9e6SYuval Mintz u8 dst_type, 604fe56b9e6SYuval Mintz u32 length) 605fe56b9e6SYuval Mintz { 606fe56b9e6SYuval Mintz dma_addr_t phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr; 607fe56b9e6SYuval Mintz struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd; 608fe56b9e6SYuval Mintz int qed_status = 0; 609fe56b9e6SYuval Mintz 610fe56b9e6SYuval Mintz switch (src_type) { 611fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_GRC: 612fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_HOST_PHYS: 613fe56b9e6SYuval Mintz cmd->src_addr_hi = cpu_to_le32(upper_32_bits(src_addr)); 614fe56b9e6SYuval Mintz cmd->src_addr_lo = cpu_to_le32(lower_32_bits(src_addr)); 615fe56b9e6SYuval Mintz break; 616fe56b9e6SYuval Mintz /* for virtual source addresses we use the intermediate buffer. */ 617fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_HOST_VIRT: 618fe56b9e6SYuval Mintz cmd->src_addr_hi = cpu_to_le32(upper_32_bits(phys)); 619fe56b9e6SYuval Mintz cmd->src_addr_lo = cpu_to_le32(lower_32_bits(phys)); 620fe56b9e6SYuval Mintz memcpy(&p_hwfn->dmae_info.p_intermediate_buffer[0], 621fe56b9e6SYuval Mintz (void *)(uintptr_t)src_addr, 622fe56b9e6SYuval Mintz length * sizeof(u32)); 623fe56b9e6SYuval Mintz break; 624fe56b9e6SYuval Mintz default: 625fe56b9e6SYuval Mintz return -EINVAL; 626fe56b9e6SYuval Mintz } 627fe56b9e6SYuval Mintz 628fe56b9e6SYuval Mintz switch (dst_type) { 629fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_GRC: 630fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_HOST_PHYS: 631fe56b9e6SYuval Mintz cmd->dst_addr_hi = cpu_to_le32(upper_32_bits(dst_addr)); 632fe56b9e6SYuval Mintz cmd->dst_addr_lo = cpu_to_le32(lower_32_bits(dst_addr)); 633fe56b9e6SYuval Mintz break; 634fe56b9e6SYuval Mintz /* for virtual source addresses we use the intermediate buffer. */ 635fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_HOST_VIRT: 636fe56b9e6SYuval Mintz cmd->dst_addr_hi = cpu_to_le32(upper_32_bits(phys)); 637fe56b9e6SYuval Mintz cmd->dst_addr_lo = cpu_to_le32(lower_32_bits(phys)); 638fe56b9e6SYuval Mintz break; 639fe56b9e6SYuval Mintz default: 640fe56b9e6SYuval Mintz return -EINVAL; 641fe56b9e6SYuval Mintz } 642fe56b9e6SYuval Mintz 643fe56b9e6SYuval Mintz cmd->length = cpu_to_le16((u16)length); 644fe56b9e6SYuval Mintz 645fe56b9e6SYuval Mintz qed_dmae_post_command(p_hwfn, p_ptt); 646fe56b9e6SYuval Mintz 647fe56b9e6SYuval Mintz qed_status = qed_dmae_operation_wait(p_hwfn); 648fe56b9e6SYuval Mintz 649fe56b9e6SYuval Mintz if (qed_status) { 650fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 651fe56b9e6SYuval Mintz "qed_dmae_host2grc: Wait Failed. source_addr 0x%llx, grc_addr 0x%llx, size_in_dwords 0x%x\n", 652fe56b9e6SYuval Mintz src_addr, 653fe56b9e6SYuval Mintz dst_addr, 654fe56b9e6SYuval Mintz length); 655fe56b9e6SYuval Mintz return qed_status; 656fe56b9e6SYuval Mintz } 657fe56b9e6SYuval Mintz 658fe56b9e6SYuval Mintz if (dst_type == QED_DMAE_ADDRESS_HOST_VIRT) 659fe56b9e6SYuval Mintz memcpy((void *)(uintptr_t)(dst_addr), 660fe56b9e6SYuval Mintz &p_hwfn->dmae_info.p_intermediate_buffer[0], 661fe56b9e6SYuval Mintz length * sizeof(u32)); 662fe56b9e6SYuval Mintz 663fe56b9e6SYuval Mintz return 0; 664fe56b9e6SYuval Mintz } 665fe56b9e6SYuval Mintz 666fe56b9e6SYuval Mintz static int qed_dmae_execute_command(struct qed_hwfn *p_hwfn, 667fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 668fe56b9e6SYuval Mintz u64 src_addr, u64 dst_addr, 669fe56b9e6SYuval Mintz u8 src_type, u8 dst_type, 670fe56b9e6SYuval Mintz u32 size_in_dwords, 671fe56b9e6SYuval Mintz struct qed_dmae_params *p_params) 672fe56b9e6SYuval Mintz { 673fe56b9e6SYuval Mintz dma_addr_t phys = p_hwfn->dmae_info.completion_word_phys_addr; 674fe56b9e6SYuval Mintz u16 length_cur = 0, i = 0, cnt_split = 0, length_mod = 0; 675fe56b9e6SYuval Mintz struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd; 676fe56b9e6SYuval Mintz u64 src_addr_split = 0, dst_addr_split = 0; 677fe56b9e6SYuval Mintz u16 length_limit = DMAE_MAX_RW_SIZE; 678fe56b9e6SYuval Mintz int qed_status = 0; 679fe56b9e6SYuval Mintz u32 offset = 0; 680fe56b9e6SYuval Mintz 681fe56b9e6SYuval Mintz qed_dmae_opcode(p_hwfn, 682fe56b9e6SYuval Mintz (src_type == QED_DMAE_ADDRESS_GRC), 683fe56b9e6SYuval Mintz (dst_type == QED_DMAE_ADDRESS_GRC), 684fe56b9e6SYuval Mintz p_params); 685fe56b9e6SYuval Mintz 686fe56b9e6SYuval Mintz cmd->comp_addr_lo = cpu_to_le32(lower_32_bits(phys)); 687fe56b9e6SYuval Mintz cmd->comp_addr_hi = cpu_to_le32(upper_32_bits(phys)); 688fe56b9e6SYuval Mintz cmd->comp_val = cpu_to_le32(DMAE_COMPLETION_VAL); 689fe56b9e6SYuval Mintz 690fe56b9e6SYuval Mintz /* Check if the grc_addr is valid like < MAX_GRC_OFFSET */ 691fe56b9e6SYuval Mintz cnt_split = size_in_dwords / length_limit; 692fe56b9e6SYuval Mintz length_mod = size_in_dwords % length_limit; 693fe56b9e6SYuval Mintz 694fe56b9e6SYuval Mintz src_addr_split = src_addr; 695fe56b9e6SYuval Mintz dst_addr_split = dst_addr; 696fe56b9e6SYuval Mintz 697fe56b9e6SYuval Mintz for (i = 0; i <= cnt_split; i++) { 698fe56b9e6SYuval Mintz offset = length_limit * i; 699fe56b9e6SYuval Mintz 700fe56b9e6SYuval Mintz if (!(p_params->flags & QED_DMAE_FLAG_RW_REPL_SRC)) { 701fe56b9e6SYuval Mintz if (src_type == QED_DMAE_ADDRESS_GRC) 702fe56b9e6SYuval Mintz src_addr_split = src_addr + offset; 703fe56b9e6SYuval Mintz else 704fe56b9e6SYuval Mintz src_addr_split = src_addr + (offset * 4); 705fe56b9e6SYuval Mintz } 706fe56b9e6SYuval Mintz 707fe56b9e6SYuval Mintz if (dst_type == QED_DMAE_ADDRESS_GRC) 708fe56b9e6SYuval Mintz dst_addr_split = dst_addr + offset; 709fe56b9e6SYuval Mintz else 710fe56b9e6SYuval Mintz dst_addr_split = dst_addr + (offset * 4); 711fe56b9e6SYuval Mintz 712fe56b9e6SYuval Mintz length_cur = (cnt_split == i) ? length_mod : length_limit; 713fe56b9e6SYuval Mintz 714fe56b9e6SYuval Mintz /* might be zero on last iteration */ 715fe56b9e6SYuval Mintz if (!length_cur) 716fe56b9e6SYuval Mintz continue; 717fe56b9e6SYuval Mintz 718fe56b9e6SYuval Mintz qed_status = qed_dmae_execute_sub_operation(p_hwfn, 719fe56b9e6SYuval Mintz p_ptt, 720fe56b9e6SYuval Mintz src_addr_split, 721fe56b9e6SYuval Mintz dst_addr_split, 722fe56b9e6SYuval Mintz src_type, 723fe56b9e6SYuval Mintz dst_type, 724fe56b9e6SYuval Mintz length_cur); 725fe56b9e6SYuval Mintz if (qed_status) { 726fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 727fe56b9e6SYuval Mintz "qed_dmae_execute_sub_operation Failed with error 0x%x. source_addr 0x%llx, destination addr 0x%llx, size_in_dwords 0x%x\n", 728fe56b9e6SYuval Mintz qed_status, 729fe56b9e6SYuval Mintz src_addr, 730fe56b9e6SYuval Mintz dst_addr, 731fe56b9e6SYuval Mintz length_cur); 732fe56b9e6SYuval Mintz break; 733fe56b9e6SYuval Mintz } 734fe56b9e6SYuval Mintz } 735fe56b9e6SYuval Mintz 736fe56b9e6SYuval Mintz return qed_status; 737fe56b9e6SYuval Mintz } 738fe56b9e6SYuval Mintz 739fe56b9e6SYuval Mintz int qed_dmae_host2grc(struct qed_hwfn *p_hwfn, 740fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 741fe56b9e6SYuval Mintz u64 source_addr, 742fe56b9e6SYuval Mintz u32 grc_addr, 743fe56b9e6SYuval Mintz u32 size_in_dwords, 744fe56b9e6SYuval Mintz u32 flags) 745fe56b9e6SYuval Mintz { 746fe56b9e6SYuval Mintz u32 grc_addr_in_dw = grc_addr / sizeof(u32); 747fe56b9e6SYuval Mintz struct qed_dmae_params params; 748fe56b9e6SYuval Mintz int rc; 749fe56b9e6SYuval Mintz 750fe56b9e6SYuval Mintz memset(¶ms, 0, sizeof(struct qed_dmae_params)); 751fe56b9e6SYuval Mintz params.flags = flags; 752fe56b9e6SYuval Mintz 753fe56b9e6SYuval Mintz mutex_lock(&p_hwfn->dmae_info.mutex); 754fe56b9e6SYuval Mintz 755fe56b9e6SYuval Mintz rc = qed_dmae_execute_command(p_hwfn, p_ptt, source_addr, 756fe56b9e6SYuval Mintz grc_addr_in_dw, 757fe56b9e6SYuval Mintz QED_DMAE_ADDRESS_HOST_VIRT, 758fe56b9e6SYuval Mintz QED_DMAE_ADDRESS_GRC, 759fe56b9e6SYuval Mintz size_in_dwords, ¶ms); 760fe56b9e6SYuval Mintz 761fe56b9e6SYuval Mintz mutex_unlock(&p_hwfn->dmae_info.mutex); 762fe56b9e6SYuval Mintz 763fe56b9e6SYuval Mintz return rc; 764fe56b9e6SYuval Mintz } 765fe56b9e6SYuval Mintz 76637bff2b9SYuval Mintz int 76737bff2b9SYuval Mintz qed_dmae_host2host(struct qed_hwfn *p_hwfn, 76837bff2b9SYuval Mintz struct qed_ptt *p_ptt, 76937bff2b9SYuval Mintz dma_addr_t source_addr, 77037bff2b9SYuval Mintz dma_addr_t dest_addr, 77137bff2b9SYuval Mintz u32 size_in_dwords, struct qed_dmae_params *p_params) 77237bff2b9SYuval Mintz { 77337bff2b9SYuval Mintz int rc; 77437bff2b9SYuval Mintz 77537bff2b9SYuval Mintz mutex_lock(&(p_hwfn->dmae_info.mutex)); 77637bff2b9SYuval Mintz 77737bff2b9SYuval Mintz rc = qed_dmae_execute_command(p_hwfn, p_ptt, source_addr, 77837bff2b9SYuval Mintz dest_addr, 77937bff2b9SYuval Mintz QED_DMAE_ADDRESS_HOST_PHYS, 78037bff2b9SYuval Mintz QED_DMAE_ADDRESS_HOST_PHYS, 78137bff2b9SYuval Mintz size_in_dwords, p_params); 78237bff2b9SYuval Mintz 78337bff2b9SYuval Mintz mutex_unlock(&(p_hwfn->dmae_info.mutex)); 78437bff2b9SYuval Mintz 78537bff2b9SYuval Mintz return rc; 78637bff2b9SYuval Mintz } 78737bff2b9SYuval Mintz 788fe56b9e6SYuval Mintz u16 qed_get_qm_pq(struct qed_hwfn *p_hwfn, 789fe56b9e6SYuval Mintz enum protocol_type proto, 790fe56b9e6SYuval Mintz union qed_qm_pq_params *p_params) 791fe56b9e6SYuval Mintz { 792fe56b9e6SYuval Mintz u16 pq_id = 0; 793fe56b9e6SYuval Mintz 794fe56b9e6SYuval Mintz if ((proto == PROTOCOLID_CORE || proto == PROTOCOLID_ETH) && 795fe56b9e6SYuval Mintz !p_params) { 796fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 797fe56b9e6SYuval Mintz "Protocol %d received NULL PQ params\n", 798fe56b9e6SYuval Mintz proto); 799fe56b9e6SYuval Mintz return 0; 800fe56b9e6SYuval Mintz } 801fe56b9e6SYuval Mintz 802fe56b9e6SYuval Mintz switch (proto) { 803fe56b9e6SYuval Mintz case PROTOCOLID_CORE: 804fe56b9e6SYuval Mintz if (p_params->core.tc == LB_TC) 805fe56b9e6SYuval Mintz pq_id = p_hwfn->qm_info.pure_lb_pq; 806fe56b9e6SYuval Mintz else 807fe56b9e6SYuval Mintz pq_id = p_hwfn->qm_info.offload_pq; 808fe56b9e6SYuval Mintz break; 809fe56b9e6SYuval Mintz case PROTOCOLID_ETH: 810fe56b9e6SYuval Mintz pq_id = p_params->eth.tc; 811fe56b9e6SYuval Mintz break; 812fe56b9e6SYuval Mintz default: 813fe56b9e6SYuval Mintz pq_id = 0; 814fe56b9e6SYuval Mintz } 815fe56b9e6SYuval Mintz 816fe56b9e6SYuval Mintz pq_id = CM_TX_PQ_BASE + pq_id + RESC_START(p_hwfn, QED_PQ); 817fe56b9e6SYuval Mintz 818fe56b9e6SYuval Mintz return pq_id; 819fe56b9e6SYuval Mintz } 820