11f4d4ed6SAlexander Lobakin // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 3e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 4fe56b9e6SYuval Mintz */ 5fe56b9e6SYuval Mintz 6fe56b9e6SYuval Mintz #include <linux/types.h> 7fe56b9e6SYuval Mintz #include <linux/io.h> 8fe56b9e6SYuval Mintz #include <linux/delay.h> 9fe56b9e6SYuval Mintz #include <linux/dma-mapping.h> 10fe56b9e6SYuval Mintz #include <linux/errno.h> 11fe56b9e6SYuval Mintz #include <linux/kernel.h> 12fe56b9e6SYuval Mintz #include <linux/list.h> 13fe56b9e6SYuval Mintz #include <linux/mutex.h> 14fe56b9e6SYuval Mintz #include <linux/pci.h> 15fe56b9e6SYuval Mintz #include <linux/slab.h> 16fe56b9e6SYuval Mintz #include <linux/spinlock.h> 17fe56b9e6SYuval Mintz #include <linux/string.h> 18fe56b9e6SYuval Mintz #include <linux/qed/qed_chain.h> 19fe56b9e6SYuval Mintz #include "qed.h" 20fe56b9e6SYuval Mintz #include "qed_hsi.h" 21fe56b9e6SYuval Mintz #include "qed_hw.h" 22fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 231408cc1fSYuval Mintz #include "qed_sriov.h" 24fe56b9e6SYuval Mintz 25fe56b9e6SYuval Mintz #define QED_BAR_ACQUIRE_TIMEOUT 1000 26fe56b9e6SYuval Mintz 27fe56b9e6SYuval Mintz /* Invalid values */ 28fe56b9e6SYuval Mintz #define QED_BAR_INVALID_OFFSET (cpu_to_le32(-1)) 29fe56b9e6SYuval Mintz 30fe56b9e6SYuval Mintz struct qed_ptt { 31fe56b9e6SYuval Mintz struct list_head list_entry; 32fe56b9e6SYuval Mintz unsigned int idx; 33fe56b9e6SYuval Mintz struct pxp_ptt_entry pxp; 343a50d351SMintz, Yuval u8 hwfn_id; 35fe56b9e6SYuval Mintz }; 36fe56b9e6SYuval Mintz 37fe56b9e6SYuval Mintz struct qed_ptt_pool { 38fe56b9e6SYuval Mintz struct list_head free_list; 39fe56b9e6SYuval Mintz spinlock_t lock; /* ptt synchronized access */ 40fe56b9e6SYuval Mintz struct qed_ptt ptts[PXP_EXTERNAL_BAR_PF_WINDOW_NUM]; 41fe56b9e6SYuval Mintz }; 42fe56b9e6SYuval Mintz 43fe56b9e6SYuval Mintz int qed_ptt_pool_alloc(struct qed_hwfn *p_hwfn) 44fe56b9e6SYuval Mintz { 451a635e48SYuval Mintz struct qed_ptt_pool *p_pool = kmalloc(sizeof(*p_pool), GFP_KERNEL); 46fe56b9e6SYuval Mintz int i; 47fe56b9e6SYuval Mintz 48fe56b9e6SYuval Mintz if (!p_pool) 49fe56b9e6SYuval Mintz return -ENOMEM; 50fe56b9e6SYuval Mintz 51fe56b9e6SYuval Mintz INIT_LIST_HEAD(&p_pool->free_list); 52fe56b9e6SYuval Mintz for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) { 53fe56b9e6SYuval Mintz p_pool->ptts[i].idx = i; 54fe56b9e6SYuval Mintz p_pool->ptts[i].pxp.offset = QED_BAR_INVALID_OFFSET; 55fe56b9e6SYuval Mintz p_pool->ptts[i].pxp.pretend.control = 0; 563a50d351SMintz, Yuval p_pool->ptts[i].hwfn_id = p_hwfn->my_id; 57fe56b9e6SYuval Mintz if (i >= RESERVED_PTT_MAX) 58fe56b9e6SYuval Mintz list_add(&p_pool->ptts[i].list_entry, 59fe56b9e6SYuval Mintz &p_pool->free_list); 60fe56b9e6SYuval Mintz } 61fe56b9e6SYuval Mintz 62fe56b9e6SYuval Mintz p_hwfn->p_ptt_pool = p_pool; 63fe56b9e6SYuval Mintz spin_lock_init(&p_pool->lock); 64fe56b9e6SYuval Mintz 65fe56b9e6SYuval Mintz return 0; 66fe56b9e6SYuval Mintz } 67fe56b9e6SYuval Mintz 68fe56b9e6SYuval Mintz void qed_ptt_invalidate(struct qed_hwfn *p_hwfn) 69fe56b9e6SYuval Mintz { 70fe56b9e6SYuval Mintz struct qed_ptt *p_ptt; 71fe56b9e6SYuval Mintz int i; 72fe56b9e6SYuval Mintz 73fe56b9e6SYuval Mintz for (i = 0; i < PXP_EXTERNAL_BAR_PF_WINDOW_NUM; i++) { 74fe56b9e6SYuval Mintz p_ptt = &p_hwfn->p_ptt_pool->ptts[i]; 75fe56b9e6SYuval Mintz p_ptt->pxp.offset = QED_BAR_INVALID_OFFSET; 76fe56b9e6SYuval Mintz } 77fe56b9e6SYuval Mintz } 78fe56b9e6SYuval Mintz 79fe56b9e6SYuval Mintz void qed_ptt_pool_free(struct qed_hwfn *p_hwfn) 80fe56b9e6SYuval Mintz { 81fe56b9e6SYuval Mintz kfree(p_hwfn->p_ptt_pool); 82fe56b9e6SYuval Mintz p_hwfn->p_ptt_pool = NULL; 83fe56b9e6SYuval Mintz } 84fe56b9e6SYuval Mintz 85fe56b9e6SYuval Mintz struct qed_ptt *qed_ptt_acquire(struct qed_hwfn *p_hwfn) 86fe56b9e6SYuval Mintz { 87fe56b9e6SYuval Mintz struct qed_ptt *p_ptt; 88fe56b9e6SYuval Mintz unsigned int i; 89fe56b9e6SYuval Mintz 90fe56b9e6SYuval Mintz /* Take the free PTT from the list */ 91fe56b9e6SYuval Mintz for (i = 0; i < QED_BAR_ACQUIRE_TIMEOUT; i++) { 92fe56b9e6SYuval Mintz spin_lock_bh(&p_hwfn->p_ptt_pool->lock); 93fe56b9e6SYuval Mintz 94fe56b9e6SYuval Mintz if (!list_empty(&p_hwfn->p_ptt_pool->free_list)) { 95fe56b9e6SYuval Mintz p_ptt = list_first_entry(&p_hwfn->p_ptt_pool->free_list, 96fe56b9e6SYuval Mintz struct qed_ptt, list_entry); 97fe56b9e6SYuval Mintz list_del(&p_ptt->list_entry); 98fe56b9e6SYuval Mintz 99fe56b9e6SYuval Mintz spin_unlock_bh(&p_hwfn->p_ptt_pool->lock); 100fe56b9e6SYuval Mintz 101fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 102fe56b9e6SYuval Mintz "allocated ptt %d\n", p_ptt->idx); 103fe56b9e6SYuval Mintz return p_ptt; 104fe56b9e6SYuval Mintz } 105fe56b9e6SYuval Mintz 106fe56b9e6SYuval Mintz spin_unlock_bh(&p_hwfn->p_ptt_pool->lock); 107fe56b9e6SYuval Mintz usleep_range(1000, 2000); 108fe56b9e6SYuval Mintz } 109fe56b9e6SYuval Mintz 110fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "PTT acquire timeout - failed to allocate PTT\n"); 111fe56b9e6SYuval Mintz return NULL; 112fe56b9e6SYuval Mintz } 113fe56b9e6SYuval Mintz 1141a635e48SYuval Mintz void qed_ptt_release(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 115fe56b9e6SYuval Mintz { 116fe56b9e6SYuval Mintz spin_lock_bh(&p_hwfn->p_ptt_pool->lock); 117fe56b9e6SYuval Mintz list_add(&p_ptt->list_entry, &p_hwfn->p_ptt_pool->free_list); 118fe56b9e6SYuval Mintz spin_unlock_bh(&p_hwfn->p_ptt_pool->lock); 119fe56b9e6SYuval Mintz } 120fe56b9e6SYuval Mintz 1211a635e48SYuval Mintz u32 qed_ptt_get_hw_addr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 122fe56b9e6SYuval Mintz { 123fe56b9e6SYuval Mintz /* The HW is using DWORDS and we need to translate it to Bytes */ 124fe56b9e6SYuval Mintz return le32_to_cpu(p_ptt->pxp.offset) << 2; 125fe56b9e6SYuval Mintz } 126fe56b9e6SYuval Mintz 127fe56b9e6SYuval Mintz static u32 qed_ptt_config_addr(struct qed_ptt *p_ptt) 128fe56b9e6SYuval Mintz { 129fe56b9e6SYuval Mintz return PXP_PF_WINDOW_ADMIN_PER_PF_START + 130fe56b9e6SYuval Mintz p_ptt->idx * sizeof(struct pxp_ptt_entry); 131fe56b9e6SYuval Mintz } 132fe56b9e6SYuval Mintz 133fe56b9e6SYuval Mintz u32 qed_ptt_get_bar_addr(struct qed_ptt *p_ptt) 134fe56b9e6SYuval Mintz { 135fe56b9e6SYuval Mintz return PXP_EXTERNAL_BAR_PF_WINDOW_START + 136fe56b9e6SYuval Mintz p_ptt->idx * PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE; 137fe56b9e6SYuval Mintz } 138fe56b9e6SYuval Mintz 139fe56b9e6SYuval Mintz void qed_ptt_set_win(struct qed_hwfn *p_hwfn, 1401a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 new_hw_addr) 141fe56b9e6SYuval Mintz { 142fe56b9e6SYuval Mintz u32 prev_hw_addr; 143fe56b9e6SYuval Mintz 144fe56b9e6SYuval Mintz prev_hw_addr = qed_ptt_get_hw_addr(p_hwfn, p_ptt); 145fe56b9e6SYuval Mintz 146fe56b9e6SYuval Mintz if (new_hw_addr == prev_hw_addr) 147fe56b9e6SYuval Mintz return; 148fe56b9e6SYuval Mintz 149fe56b9e6SYuval Mintz /* Update PTT entery in admin window */ 150fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 151fe56b9e6SYuval Mintz "Updating PTT entry %d to offset 0x%x\n", 152fe56b9e6SYuval Mintz p_ptt->idx, new_hw_addr); 153fe56b9e6SYuval Mintz 154fe56b9e6SYuval Mintz /* The HW is using DWORDS and the address is in Bytes */ 155fe56b9e6SYuval Mintz p_ptt->pxp.offset = cpu_to_le32(new_hw_addr >> 2); 156fe56b9e6SYuval Mintz 157fe56b9e6SYuval Mintz REG_WR(p_hwfn, 158fe56b9e6SYuval Mintz qed_ptt_config_addr(p_ptt) + 159fe56b9e6SYuval Mintz offsetof(struct pxp_ptt_entry, offset), 160fe56b9e6SYuval Mintz le32_to_cpu(p_ptt->pxp.offset)); 161fe56b9e6SYuval Mintz } 162fe56b9e6SYuval Mintz 163fe56b9e6SYuval Mintz static u32 qed_set_ptt(struct qed_hwfn *p_hwfn, 1641a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 hw_addr) 165fe56b9e6SYuval Mintz { 166fe56b9e6SYuval Mintz u32 win_hw_addr = qed_ptt_get_hw_addr(p_hwfn, p_ptt); 167fe56b9e6SYuval Mintz u32 offset; 168fe56b9e6SYuval Mintz 169fe56b9e6SYuval Mintz offset = hw_addr - win_hw_addr; 170fe56b9e6SYuval Mintz 1713a50d351SMintz, Yuval if (p_ptt->hwfn_id != p_hwfn->my_id) 1723a50d351SMintz, Yuval DP_NOTICE(p_hwfn, 1733a50d351SMintz, Yuval "ptt[%d] of hwfn[%02x] is used by hwfn[%02x]!\n", 1743a50d351SMintz, Yuval p_ptt->idx, p_ptt->hwfn_id, p_hwfn->my_id); 1753a50d351SMintz, Yuval 176fe56b9e6SYuval Mintz /* Verify the address is within the window */ 177fe56b9e6SYuval Mintz if (hw_addr < win_hw_addr || 178fe56b9e6SYuval Mintz offset >= PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE) { 179fe56b9e6SYuval Mintz qed_ptt_set_win(p_hwfn, p_ptt, hw_addr); 180fe56b9e6SYuval Mintz offset = 0; 181fe56b9e6SYuval Mintz } 182fe56b9e6SYuval Mintz 183fe56b9e6SYuval Mintz return qed_ptt_get_bar_addr(p_ptt) + offset; 184fe56b9e6SYuval Mintz } 185fe56b9e6SYuval Mintz 186fe56b9e6SYuval Mintz struct qed_ptt *qed_get_reserved_ptt(struct qed_hwfn *p_hwfn, 187fe56b9e6SYuval Mintz enum reserved_ptts ptt_idx) 188fe56b9e6SYuval Mintz { 189fe56b9e6SYuval Mintz if (ptt_idx >= RESERVED_PTT_MAX) { 190fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 191fe56b9e6SYuval Mintz "Requested PTT %d is out of range\n", ptt_idx); 192fe56b9e6SYuval Mintz return NULL; 193fe56b9e6SYuval Mintz } 194fe56b9e6SYuval Mintz 195fe56b9e6SYuval Mintz return &p_hwfn->p_ptt_pool->ptts[ptt_idx]; 196fe56b9e6SYuval Mintz } 197fe56b9e6SYuval Mintz 198fe56b9e6SYuval Mintz void qed_wr(struct qed_hwfn *p_hwfn, 199fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 200fe56b9e6SYuval Mintz u32 hw_addr, u32 val) 201fe56b9e6SYuval Mintz { 202fe56b9e6SYuval Mintz u32 bar_addr = qed_set_ptt(p_hwfn, p_ptt, hw_addr); 203fe56b9e6SYuval Mintz 204fe56b9e6SYuval Mintz REG_WR(p_hwfn, bar_addr, val); 205fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 206fe56b9e6SYuval Mintz "bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n", 207fe56b9e6SYuval Mintz bar_addr, hw_addr, val); 208fe56b9e6SYuval Mintz } 209fe56b9e6SYuval Mintz 210fe56b9e6SYuval Mintz u32 qed_rd(struct qed_hwfn *p_hwfn, 211fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 212fe56b9e6SYuval Mintz u32 hw_addr) 213fe56b9e6SYuval Mintz { 214fe56b9e6SYuval Mintz u32 bar_addr = qed_set_ptt(p_hwfn, p_ptt, hw_addr); 215fe56b9e6SYuval Mintz u32 val = REG_RD(p_hwfn, bar_addr); 216fe56b9e6SYuval Mintz 217fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 218fe56b9e6SYuval Mintz "bar_addr 0x%x, hw_addr 0x%x, val 0x%x\n", 219fe56b9e6SYuval Mintz bar_addr, hw_addr, val); 220fe56b9e6SYuval Mintz 221fe56b9e6SYuval Mintz return val; 222fe56b9e6SYuval Mintz } 223fe56b9e6SYuval Mintz 224fe56b9e6SYuval Mintz static void qed_memcpy_hw(struct qed_hwfn *p_hwfn, 225fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2261a635e48SYuval Mintz void *addr, u32 hw_addr, size_t n, bool to_device) 227fe56b9e6SYuval Mintz { 228fe56b9e6SYuval Mintz u32 dw_count, *host_addr, hw_offset; 229fe56b9e6SYuval Mintz size_t quota, done = 0; 230fe56b9e6SYuval Mintz u32 __iomem *reg_addr; 231fe56b9e6SYuval Mintz 232fe56b9e6SYuval Mintz while (done < n) { 233fe56b9e6SYuval Mintz quota = min_t(size_t, n - done, 234fe56b9e6SYuval Mintz PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE); 235fe56b9e6SYuval Mintz 2361408cc1fSYuval Mintz if (IS_PF(p_hwfn->cdev)) { 237fe56b9e6SYuval Mintz qed_ptt_set_win(p_hwfn, p_ptt, hw_addr + done); 238fe56b9e6SYuval Mintz hw_offset = qed_ptt_get_bar_addr(p_ptt); 2391408cc1fSYuval Mintz } else { 2401408cc1fSYuval Mintz hw_offset = hw_addr + done; 2411408cc1fSYuval Mintz } 242fe56b9e6SYuval Mintz 243fe56b9e6SYuval Mintz dw_count = quota / 4; 244fe56b9e6SYuval Mintz host_addr = (u32 *)((u8 *)addr + done); 245fe56b9e6SYuval Mintz reg_addr = (u32 __iomem *)REG_ADDR(p_hwfn, hw_offset); 246fe56b9e6SYuval Mintz if (to_device) 247fe56b9e6SYuval Mintz while (dw_count--) 248fe56b9e6SYuval Mintz DIRECT_REG_WR(reg_addr++, *host_addr++); 249fe56b9e6SYuval Mintz else 250fe56b9e6SYuval Mintz while (dw_count--) 251fe56b9e6SYuval Mintz *host_addr++ = DIRECT_REG_RD(reg_addr++); 252fe56b9e6SYuval Mintz 253fe56b9e6SYuval Mintz done += quota; 254fe56b9e6SYuval Mintz } 255fe56b9e6SYuval Mintz } 256fe56b9e6SYuval Mintz 257fe56b9e6SYuval Mintz void qed_memcpy_from(struct qed_hwfn *p_hwfn, 2581a635e48SYuval Mintz struct qed_ptt *p_ptt, void *dest, u32 hw_addr, size_t n) 259fe56b9e6SYuval Mintz { 260fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 261fe56b9e6SYuval Mintz "hw_addr 0x%x, dest %p hw_addr 0x%x, size %lu\n", 262fe56b9e6SYuval Mintz hw_addr, dest, hw_addr, (unsigned long)n); 263fe56b9e6SYuval Mintz 264fe56b9e6SYuval Mintz qed_memcpy_hw(p_hwfn, p_ptt, dest, hw_addr, n, false); 265fe56b9e6SYuval Mintz } 266fe56b9e6SYuval Mintz 267fe56b9e6SYuval Mintz void qed_memcpy_to(struct qed_hwfn *p_hwfn, 2681a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 hw_addr, void *src, size_t n) 269fe56b9e6SYuval Mintz { 270fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 271fe56b9e6SYuval Mintz "hw_addr 0x%x, hw_addr 0x%x, src %p size %lu\n", 272fe56b9e6SYuval Mintz hw_addr, hw_addr, src, (unsigned long)n); 273fe56b9e6SYuval Mintz 274fe56b9e6SYuval Mintz qed_memcpy_hw(p_hwfn, p_ptt, src, hw_addr, n, true); 275fe56b9e6SYuval Mintz } 276fe56b9e6SYuval Mintz 2771a635e48SYuval Mintz void qed_fid_pretend(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 fid) 278fe56b9e6SYuval Mintz { 279fe56b9e6SYuval Mintz u16 control = 0; 280fe56b9e6SYuval Mintz 281fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_IS_CONCRETE, 1); 282fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_FUNCTION, 1); 283fe56b9e6SYuval Mintz 284fe56b9e6SYuval Mintz /* Every pretend undos previous pretends, including 285fe56b9e6SYuval Mintz * previous port pretend. 286fe56b9e6SYuval Mintz */ 287fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0); 288fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0); 289fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1); 290fe56b9e6SYuval Mintz 291fe56b9e6SYuval Mintz if (!GET_FIELD(fid, PXP_CONCRETE_FID_VFVALID)) 292fe56b9e6SYuval Mintz fid = GET_FIELD(fid, PXP_CONCRETE_FID_PFID); 293fe56b9e6SYuval Mintz 294fe56b9e6SYuval Mintz p_ptt->pxp.pretend.control = cpu_to_le16(control); 295fe56b9e6SYuval Mintz p_ptt->pxp.pretend.fid.concrete_fid.fid = cpu_to_le16(fid); 296fe56b9e6SYuval Mintz 297fe56b9e6SYuval Mintz REG_WR(p_hwfn, 298fe56b9e6SYuval Mintz qed_ptt_config_addr(p_ptt) + 299fe56b9e6SYuval Mintz offsetof(struct pxp_ptt_entry, pretend), 300fe56b9e6SYuval Mintz *(u32 *)&p_ptt->pxp.pretend); 301fe56b9e6SYuval Mintz } 302fe56b9e6SYuval Mintz 303fe56b9e6SYuval Mintz void qed_port_pretend(struct qed_hwfn *p_hwfn, 3041a635e48SYuval Mintz struct qed_ptt *p_ptt, u8 port_id) 305fe56b9e6SYuval Mintz { 306fe56b9e6SYuval Mintz u16 control = 0; 307fe56b9e6SYuval Mintz 308fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PORT, port_id); 309fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 1); 310fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1); 311fe56b9e6SYuval Mintz 312fe56b9e6SYuval Mintz p_ptt->pxp.pretend.control = cpu_to_le16(control); 313fe56b9e6SYuval Mintz 314fe56b9e6SYuval Mintz REG_WR(p_hwfn, 315fe56b9e6SYuval Mintz qed_ptt_config_addr(p_ptt) + 316fe56b9e6SYuval Mintz offsetof(struct pxp_ptt_entry, pretend), 317fe56b9e6SYuval Mintz *(u32 *)&p_ptt->pxp.pretend); 318fe56b9e6SYuval Mintz } 319fe56b9e6SYuval Mintz 3201a635e48SYuval Mintz void qed_port_unpretend(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 321fe56b9e6SYuval Mintz { 322fe56b9e6SYuval Mintz u16 control = 0; 323fe56b9e6SYuval Mintz 324fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PORT, 0); 325fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 0); 326fe56b9e6SYuval Mintz SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1); 327fe56b9e6SYuval Mintz 328fe56b9e6SYuval Mintz p_ptt->pxp.pretend.control = cpu_to_le16(control); 329fe56b9e6SYuval Mintz 330fe56b9e6SYuval Mintz REG_WR(p_hwfn, 331fe56b9e6SYuval Mintz qed_ptt_config_addr(p_ptt) + 332fe56b9e6SYuval Mintz offsetof(struct pxp_ptt_entry, pretend), 333fe56b9e6SYuval Mintz *(u32 *)&p_ptt->pxp.pretend); 334fe56b9e6SYuval Mintz } 335fe56b9e6SYuval Mintz 336d52c89f1SMichal Kalderon void qed_port_fid_pretend(struct qed_hwfn *p_hwfn, 337d52c89f1SMichal Kalderon struct qed_ptt *p_ptt, u8 port_id, u16 fid) 338d52c89f1SMichal Kalderon { 339d52c89f1SMichal Kalderon u16 control = 0; 340d52c89f1SMichal Kalderon 341d52c89f1SMichal Kalderon SET_FIELD(control, PXP_PRETEND_CMD_PORT, port_id); 342d52c89f1SMichal Kalderon SET_FIELD(control, PXP_PRETEND_CMD_USE_PORT, 1); 343d52c89f1SMichal Kalderon SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_PORT, 1); 344d52c89f1SMichal Kalderon SET_FIELD(control, PXP_PRETEND_CMD_IS_CONCRETE, 1); 345d52c89f1SMichal Kalderon SET_FIELD(control, PXP_PRETEND_CMD_PRETEND_FUNCTION, 1); 346d52c89f1SMichal Kalderon if (!GET_FIELD(fid, PXP_CONCRETE_FID_VFVALID)) 347d52c89f1SMichal Kalderon fid = GET_FIELD(fid, PXP_CONCRETE_FID_PFID); 348d52c89f1SMichal Kalderon p_ptt->pxp.pretend.control = cpu_to_le16(control); 349d52c89f1SMichal Kalderon p_ptt->pxp.pretend.fid.concrete_fid.fid = cpu_to_le16(fid); 350d52c89f1SMichal Kalderon REG_WR(p_hwfn, 351d52c89f1SMichal Kalderon qed_ptt_config_addr(p_ptt) + 352d52c89f1SMichal Kalderon offsetof(struct pxp_ptt_entry, pretend), 353d52c89f1SMichal Kalderon *(u32 *)&p_ptt->pxp.pretend); 354d52c89f1SMichal Kalderon } 355d52c89f1SMichal Kalderon 35632a47e72SYuval Mintz u32 qed_vfid_to_concrete(struct qed_hwfn *p_hwfn, u8 vfid) 35732a47e72SYuval Mintz { 35832a47e72SYuval Mintz u32 concrete_fid = 0; 35932a47e72SYuval Mintz 36032a47e72SYuval Mintz SET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID, p_hwfn->rel_pf_id); 36132a47e72SYuval Mintz SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID, vfid); 36232a47e72SYuval Mintz SET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFVALID, 1); 36332a47e72SYuval Mintz 36432a47e72SYuval Mintz return concrete_fid; 36532a47e72SYuval Mintz } 36632a47e72SYuval Mintz 367fe56b9e6SYuval Mintz /* DMAE */ 36883bf76e3SMichal Kalderon #define QED_DMAE_FLAGS_IS_SET(params, flag) \ 369804c5702SMichal Kalderon ((params) != NULL && GET_FIELD((params)->flags, QED_DMAE_PARAMS_##flag)) 37083bf76e3SMichal Kalderon 371fe56b9e6SYuval Mintz static void qed_dmae_opcode(struct qed_hwfn *p_hwfn, 372fe56b9e6SYuval Mintz const u8 is_src_type_grc, 373fe56b9e6SYuval Mintz const u8 is_dst_type_grc, 374fe56b9e6SYuval Mintz struct qed_dmae_params *p_params) 375fe56b9e6SYuval Mintz { 37683bf76e3SMichal Kalderon u8 src_pfid, dst_pfid, port_id; 37737bff2b9SYuval Mintz u16 opcode_b = 0; 378fe56b9e6SYuval Mintz u32 opcode = 0; 379fe56b9e6SYuval Mintz 380fe56b9e6SYuval Mintz /* Whether the source is the PCIe or the GRC. 381fe56b9e6SYuval Mintz * 0- The source is the PCIe 382fe56b9e6SYuval Mintz * 1- The source is the GRC. 383fe56b9e6SYuval Mintz */ 384804c5702SMichal Kalderon SET_FIELD(opcode, DMAE_CMD_SRC, 385804c5702SMichal Kalderon (is_src_type_grc ? dmae_cmd_src_grc : dmae_cmd_src_pcie)); 386804c5702SMichal Kalderon src_pfid = QED_DMAE_FLAGS_IS_SET(p_params, SRC_PF_VALID) ? 38783bf76e3SMichal Kalderon p_params->src_pfid : p_hwfn->rel_pf_id; 388804c5702SMichal Kalderon SET_FIELD(opcode, DMAE_CMD_SRC_PF_ID, src_pfid); 389fe56b9e6SYuval Mintz 390fe56b9e6SYuval Mintz /* The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */ 391804c5702SMichal Kalderon SET_FIELD(opcode, DMAE_CMD_DST, 392804c5702SMichal Kalderon (is_dst_type_grc ? dmae_cmd_dst_grc : dmae_cmd_dst_pcie)); 393804c5702SMichal Kalderon dst_pfid = QED_DMAE_FLAGS_IS_SET(p_params, DST_PF_VALID) ? 39483bf76e3SMichal Kalderon p_params->dst_pfid : p_hwfn->rel_pf_id; 395804c5702SMichal Kalderon SET_FIELD(opcode, DMAE_CMD_DST_PF_ID, dst_pfid); 396804c5702SMichal Kalderon 397fe56b9e6SYuval Mintz 398fe56b9e6SYuval Mintz /* Whether to write a completion word to the completion destination: 399fe56b9e6SYuval Mintz * 0-Do not write a completion word 400fe56b9e6SYuval Mintz * 1-Write the completion word 401fe56b9e6SYuval Mintz */ 402804c5702SMichal Kalderon SET_FIELD(opcode, DMAE_CMD_COMP_WORD_EN, 1); 403804c5702SMichal Kalderon SET_FIELD(opcode, DMAE_CMD_SRC_ADDR_RESET, 1); 404fe56b9e6SYuval Mintz 40583bf76e3SMichal Kalderon if (QED_DMAE_FLAGS_IS_SET(p_params, COMPLETION_DST)) 406804c5702SMichal Kalderon SET_FIELD(opcode, DMAE_CMD_COMP_FUNC, 1); 407fe56b9e6SYuval Mintz 408804c5702SMichal Kalderon /* swapping mode 3 - big endian */ 409804c5702SMichal Kalderon SET_FIELD(opcode, DMAE_CMD_ENDIANITY_MODE, DMAE_CMD_ENDIANITY); 410fe56b9e6SYuval Mintz 411804c5702SMichal Kalderon port_id = (QED_DMAE_FLAGS_IS_SET(p_params, PORT_VALID)) ? 41283bf76e3SMichal Kalderon p_params->port_id : p_hwfn->port_id; 413804c5702SMichal Kalderon SET_FIELD(opcode, DMAE_CMD_PORT_ID, port_id); 414fe56b9e6SYuval Mintz 415fe56b9e6SYuval Mintz /* reset source address in next go */ 416804c5702SMichal Kalderon SET_FIELD(opcode, DMAE_CMD_SRC_ADDR_RESET, 1); 417fe56b9e6SYuval Mintz 418fe56b9e6SYuval Mintz /* reset dest address in next go */ 419804c5702SMichal Kalderon SET_FIELD(opcode, DMAE_CMD_DST_ADDR_RESET, 1); 420fe56b9e6SYuval Mintz 42137bff2b9SYuval Mintz /* SRC/DST VFID: all 1's - pf, otherwise VF id */ 422804c5702SMichal Kalderon if (QED_DMAE_FLAGS_IS_SET(p_params, SRC_VF_VALID)) { 423804c5702SMichal Kalderon SET_FIELD(opcode, DMAE_CMD_SRC_VF_ID_VALID, 1); 424804c5702SMichal Kalderon SET_FIELD(opcode_b, DMAE_CMD_SRC_VF_ID, p_params->src_vfid); 42537bff2b9SYuval Mintz } else { 426804c5702SMichal Kalderon SET_FIELD(opcode_b, DMAE_CMD_SRC_VF_ID, 0xFF); 42737bff2b9SYuval Mintz } 428804c5702SMichal Kalderon if (QED_DMAE_FLAGS_IS_SET(p_params, DST_VF_VALID)) { 429804c5702SMichal Kalderon SET_FIELD(opcode, DMAE_CMD_DST_VF_ID_VALID, 1); 430804c5702SMichal Kalderon SET_FIELD(opcode_b, DMAE_CMD_DST_VF_ID, p_params->dst_vfid); 43137bff2b9SYuval Mintz } else { 432804c5702SMichal Kalderon SET_FIELD(opcode_b, DMAE_CMD_DST_VF_ID, 0xFF); 43337bff2b9SYuval Mintz } 434fe56b9e6SYuval Mintz 435fe56b9e6SYuval Mintz p_hwfn->dmae_info.p_dmae_cmd->opcode = cpu_to_le32(opcode); 43637bff2b9SYuval Mintz p_hwfn->dmae_info.p_dmae_cmd->opcode_b = cpu_to_le16(opcode_b); 437fe56b9e6SYuval Mintz } 438fe56b9e6SYuval Mintz 439fe56b9e6SYuval Mintz u32 qed_dmae_idx_to_go_cmd(u8 idx) 440fe56b9e6SYuval Mintz { 441fe56b9e6SYuval Mintz /* All the DMAE 'go' registers form an array in internal memory */ 442fe56b9e6SYuval Mintz return DMAE_REG_GO_C0 + (idx << 2); 443fe56b9e6SYuval Mintz } 444fe56b9e6SYuval Mintz 4451a635e48SYuval Mintz static int qed_dmae_post_command(struct qed_hwfn *p_hwfn, 446fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 447fe56b9e6SYuval Mintz { 4481a635e48SYuval Mintz struct dmae_cmd *p_command = p_hwfn->dmae_info.p_dmae_cmd; 449fe56b9e6SYuval Mintz u8 idx_cmd = p_hwfn->dmae_info.channel, i; 450fe56b9e6SYuval Mintz int qed_status = 0; 451fe56b9e6SYuval Mintz 452fe56b9e6SYuval Mintz /* verify address is not NULL */ 4531a635e48SYuval Mintz if ((((!p_command->dst_addr_lo) && (!p_command->dst_addr_hi)) || 4541a635e48SYuval Mintz ((!p_command->src_addr_lo) && (!p_command->src_addr_hi)))) { 455fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 456fe56b9e6SYuval Mintz "source or destination address 0 idx_cmd=%d\n" 457fe56b9e6SYuval Mintz "opcode = [0x%08x,0x%04x] len=0x%x src=0x%x:%x dst=0x%x:%x\n", 458fe56b9e6SYuval Mintz idx_cmd, 4591a635e48SYuval Mintz le32_to_cpu(p_command->opcode), 4601a635e48SYuval Mintz le16_to_cpu(p_command->opcode_b), 4611a635e48SYuval Mintz le16_to_cpu(p_command->length_dw), 4621a635e48SYuval Mintz le32_to_cpu(p_command->src_addr_hi), 4631a635e48SYuval Mintz le32_to_cpu(p_command->src_addr_lo), 4641a635e48SYuval Mintz le32_to_cpu(p_command->dst_addr_hi), 4651a635e48SYuval Mintz le32_to_cpu(p_command->dst_addr_lo)); 466fe56b9e6SYuval Mintz 467fe56b9e6SYuval Mintz return -EINVAL; 468fe56b9e6SYuval Mintz } 469fe56b9e6SYuval Mintz 470fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, 471fe56b9e6SYuval Mintz NETIF_MSG_HW, 472fe56b9e6SYuval Mintz "Posting DMAE command [idx %d]: opcode = [0x%08x,0x%04x] len=0x%x src=0x%x:%x dst=0x%x:%x\n", 473fe56b9e6SYuval Mintz idx_cmd, 4741a635e48SYuval Mintz le32_to_cpu(p_command->opcode), 4751a635e48SYuval Mintz le16_to_cpu(p_command->opcode_b), 4761a635e48SYuval Mintz le16_to_cpu(p_command->length_dw), 4771a635e48SYuval Mintz le32_to_cpu(p_command->src_addr_hi), 4781a635e48SYuval Mintz le32_to_cpu(p_command->src_addr_lo), 4791a635e48SYuval Mintz le32_to_cpu(p_command->dst_addr_hi), 4801a635e48SYuval Mintz le32_to_cpu(p_command->dst_addr_lo)); 481fe56b9e6SYuval Mintz 482fe56b9e6SYuval Mintz /* Copy the command to DMAE - need to do it before every call 483fe56b9e6SYuval Mintz * for source/dest address no reset. 484fe56b9e6SYuval Mintz * The first 9 DWs are the command registers, the 10 DW is the 485fe56b9e6SYuval Mintz * GO register, and the rest are result registers 486fe56b9e6SYuval Mintz * (which are read only by the client). 487fe56b9e6SYuval Mintz */ 488fe56b9e6SYuval Mintz for (i = 0; i < DMAE_CMD_SIZE; i++) { 489fe56b9e6SYuval Mintz u32 data = (i < DMAE_CMD_SIZE_TO_FILL) ? 4901a635e48SYuval Mintz *(((u32 *)p_command) + i) : 0; 491fe56b9e6SYuval Mintz 492fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 493fe56b9e6SYuval Mintz DMAE_REG_CMD_MEM + 494fe56b9e6SYuval Mintz (idx_cmd * DMAE_CMD_SIZE * sizeof(u32)) + 495fe56b9e6SYuval Mintz (i * sizeof(u32)), data); 496fe56b9e6SYuval Mintz } 497fe56b9e6SYuval Mintz 4981a635e48SYuval Mintz qed_wr(p_hwfn, p_ptt, qed_dmae_idx_to_go_cmd(idx_cmd), DMAE_GO_VALUE); 499fe56b9e6SYuval Mintz 500fe56b9e6SYuval Mintz return qed_status; 501fe56b9e6SYuval Mintz } 502fe56b9e6SYuval Mintz 503fe56b9e6SYuval Mintz int qed_dmae_info_alloc(struct qed_hwfn *p_hwfn) 504fe56b9e6SYuval Mintz { 505fe56b9e6SYuval Mintz dma_addr_t *p_addr = &p_hwfn->dmae_info.completion_word_phys_addr; 506fe56b9e6SYuval Mintz struct dmae_cmd **p_cmd = &p_hwfn->dmae_info.p_dmae_cmd; 507fe56b9e6SYuval Mintz u32 **p_buff = &p_hwfn->dmae_info.p_intermediate_buffer; 508fe56b9e6SYuval Mintz u32 **p_comp = &p_hwfn->dmae_info.p_completion_word; 509fe56b9e6SYuval Mintz 510fe56b9e6SYuval Mintz *p_comp = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 5111a635e48SYuval Mintz sizeof(u32), p_addr, GFP_KERNEL); 5122591c280SJoe Perches if (!*p_comp) 513fe56b9e6SYuval Mintz goto err; 514fe56b9e6SYuval Mintz 515fe56b9e6SYuval Mintz p_addr = &p_hwfn->dmae_info.dmae_cmd_phys_addr; 516fe56b9e6SYuval Mintz *p_cmd = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 517fe56b9e6SYuval Mintz sizeof(struct dmae_cmd), 518fe56b9e6SYuval Mintz p_addr, GFP_KERNEL); 5192591c280SJoe Perches if (!*p_cmd) 520fe56b9e6SYuval Mintz goto err; 521fe56b9e6SYuval Mintz 522fe56b9e6SYuval Mintz p_addr = &p_hwfn->dmae_info.intermediate_buffer_phys_addr; 523fe56b9e6SYuval Mintz *p_buff = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 524fe56b9e6SYuval Mintz sizeof(u32) * DMAE_MAX_RW_SIZE, 525fe56b9e6SYuval Mintz p_addr, GFP_KERNEL); 5262591c280SJoe Perches if (!*p_buff) 527fe56b9e6SYuval Mintz goto err; 528fe56b9e6SYuval Mintz 529fe56b9e6SYuval Mintz p_hwfn->dmae_info.channel = p_hwfn->rel_pf_id; 530fe56b9e6SYuval Mintz 531fe56b9e6SYuval Mintz return 0; 532fe56b9e6SYuval Mintz err: 533fe56b9e6SYuval Mintz qed_dmae_info_free(p_hwfn); 534fe56b9e6SYuval Mintz return -ENOMEM; 535fe56b9e6SYuval Mintz } 536fe56b9e6SYuval Mintz 537fe56b9e6SYuval Mintz void qed_dmae_info_free(struct qed_hwfn *p_hwfn) 538fe56b9e6SYuval Mintz { 539fe56b9e6SYuval Mintz dma_addr_t p_phys; 540fe56b9e6SYuval Mintz 541fe56b9e6SYuval Mintz /* Just make sure no one is in the middle */ 542fe56b9e6SYuval Mintz mutex_lock(&p_hwfn->dmae_info.mutex); 543fe56b9e6SYuval Mintz 544fe56b9e6SYuval Mintz if (p_hwfn->dmae_info.p_completion_word) { 545fe56b9e6SYuval Mintz p_phys = p_hwfn->dmae_info.completion_word_phys_addr; 546fe56b9e6SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 547fe56b9e6SYuval Mintz sizeof(u32), 5481a635e48SYuval Mintz p_hwfn->dmae_info.p_completion_word, p_phys); 549fe56b9e6SYuval Mintz p_hwfn->dmae_info.p_completion_word = NULL; 550fe56b9e6SYuval Mintz } 551fe56b9e6SYuval Mintz 552fe56b9e6SYuval Mintz if (p_hwfn->dmae_info.p_dmae_cmd) { 553fe56b9e6SYuval Mintz p_phys = p_hwfn->dmae_info.dmae_cmd_phys_addr; 554fe56b9e6SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 555fe56b9e6SYuval Mintz sizeof(struct dmae_cmd), 5561a635e48SYuval Mintz p_hwfn->dmae_info.p_dmae_cmd, p_phys); 557fe56b9e6SYuval Mintz p_hwfn->dmae_info.p_dmae_cmd = NULL; 558fe56b9e6SYuval Mintz } 559fe56b9e6SYuval Mintz 560fe56b9e6SYuval Mintz if (p_hwfn->dmae_info.p_intermediate_buffer) { 561fe56b9e6SYuval Mintz p_phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr; 562fe56b9e6SYuval Mintz dma_free_coherent(&p_hwfn->cdev->pdev->dev, 563fe56b9e6SYuval Mintz sizeof(u32) * DMAE_MAX_RW_SIZE, 564fe56b9e6SYuval Mintz p_hwfn->dmae_info.p_intermediate_buffer, 565fe56b9e6SYuval Mintz p_phys); 566fe56b9e6SYuval Mintz p_hwfn->dmae_info.p_intermediate_buffer = NULL; 567fe56b9e6SYuval Mintz } 568fe56b9e6SYuval Mintz 569fe56b9e6SYuval Mintz mutex_unlock(&p_hwfn->dmae_info.mutex); 570fe56b9e6SYuval Mintz } 571fe56b9e6SYuval Mintz 572fe56b9e6SYuval Mintz static int qed_dmae_operation_wait(struct qed_hwfn *p_hwfn) 573fe56b9e6SYuval Mintz { 5741a635e48SYuval Mintz u32 wait_cnt_limit = 10000, wait_cnt = 0; 575fe56b9e6SYuval Mintz int qed_status = 0; 576fe56b9e6SYuval Mintz 577fe56b9e6SYuval Mintz barrier(); 578fe56b9e6SYuval Mintz while (*p_hwfn->dmae_info.p_completion_word != DMAE_COMPLETION_VAL) { 579fe56b9e6SYuval Mintz udelay(DMAE_MIN_WAIT_TIME); 580fe56b9e6SYuval Mintz if (++wait_cnt > wait_cnt_limit) { 581fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn->cdev, 582fe56b9e6SYuval Mintz "Timed-out waiting for operation to complete. Completion word is 0x%08x expected 0x%08x.\n", 583fe56b9e6SYuval Mintz *p_hwfn->dmae_info.p_completion_word, 584fe56b9e6SYuval Mintz DMAE_COMPLETION_VAL); 585fe56b9e6SYuval Mintz qed_status = -EBUSY; 586fe56b9e6SYuval Mintz break; 587fe56b9e6SYuval Mintz } 588fe56b9e6SYuval Mintz 589fe56b9e6SYuval Mintz /* to sync the completion_word since we are not 590fe56b9e6SYuval Mintz * using the volatile keyword for p_completion_word 591fe56b9e6SYuval Mintz */ 592fe56b9e6SYuval Mintz barrier(); 593fe56b9e6SYuval Mintz } 594fe56b9e6SYuval Mintz 595fe56b9e6SYuval Mintz if (qed_status == 0) 596fe56b9e6SYuval Mintz *p_hwfn->dmae_info.p_completion_word = 0; 597fe56b9e6SYuval Mintz 598fe56b9e6SYuval Mintz return qed_status; 599fe56b9e6SYuval Mintz } 600fe56b9e6SYuval Mintz 601fe56b9e6SYuval Mintz static int qed_dmae_execute_sub_operation(struct qed_hwfn *p_hwfn, 602fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 603fe56b9e6SYuval Mintz u64 src_addr, 604fe56b9e6SYuval Mintz u64 dst_addr, 605fe56b9e6SYuval Mintz u8 src_type, 606fe56b9e6SYuval Mintz u8 dst_type, 6071a635e48SYuval Mintz u32 length_dw) 608fe56b9e6SYuval Mintz { 609fe56b9e6SYuval Mintz dma_addr_t phys = p_hwfn->dmae_info.intermediate_buffer_phys_addr; 610fe56b9e6SYuval Mintz struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd; 611fe56b9e6SYuval Mintz int qed_status = 0; 612fe56b9e6SYuval Mintz 613fe56b9e6SYuval Mintz switch (src_type) { 614fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_GRC: 615fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_HOST_PHYS: 616fe56b9e6SYuval Mintz cmd->src_addr_hi = cpu_to_le32(upper_32_bits(src_addr)); 617fe56b9e6SYuval Mintz cmd->src_addr_lo = cpu_to_le32(lower_32_bits(src_addr)); 618fe56b9e6SYuval Mintz break; 619fe56b9e6SYuval Mintz /* for virtual source addresses we use the intermediate buffer. */ 620fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_HOST_VIRT: 621fe56b9e6SYuval Mintz cmd->src_addr_hi = cpu_to_le32(upper_32_bits(phys)); 622fe56b9e6SYuval Mintz cmd->src_addr_lo = cpu_to_le32(lower_32_bits(phys)); 623fe56b9e6SYuval Mintz memcpy(&p_hwfn->dmae_info.p_intermediate_buffer[0], 624fe56b9e6SYuval Mintz (void *)(uintptr_t)src_addr, 6251a635e48SYuval Mintz length_dw * sizeof(u32)); 626fe56b9e6SYuval Mintz break; 627fe56b9e6SYuval Mintz default: 628fe56b9e6SYuval Mintz return -EINVAL; 629fe56b9e6SYuval Mintz } 630fe56b9e6SYuval Mintz 631fe56b9e6SYuval Mintz switch (dst_type) { 632fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_GRC: 633fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_HOST_PHYS: 634fe56b9e6SYuval Mintz cmd->dst_addr_hi = cpu_to_le32(upper_32_bits(dst_addr)); 635fe56b9e6SYuval Mintz cmd->dst_addr_lo = cpu_to_le32(lower_32_bits(dst_addr)); 636fe56b9e6SYuval Mintz break; 637fe56b9e6SYuval Mintz /* for virtual source addresses we use the intermediate buffer. */ 638fe56b9e6SYuval Mintz case QED_DMAE_ADDRESS_HOST_VIRT: 639fe56b9e6SYuval Mintz cmd->dst_addr_hi = cpu_to_le32(upper_32_bits(phys)); 640fe56b9e6SYuval Mintz cmd->dst_addr_lo = cpu_to_le32(lower_32_bits(phys)); 641fe56b9e6SYuval Mintz break; 642fe56b9e6SYuval Mintz default: 643fe56b9e6SYuval Mintz return -EINVAL; 644fe56b9e6SYuval Mintz } 645fe56b9e6SYuval Mintz 6461a635e48SYuval Mintz cmd->length_dw = cpu_to_le16((u16)length_dw); 647fe56b9e6SYuval Mintz 648fe56b9e6SYuval Mintz qed_dmae_post_command(p_hwfn, p_ptt); 649fe56b9e6SYuval Mintz 650fe56b9e6SYuval Mintz qed_status = qed_dmae_operation_wait(p_hwfn); 651fe56b9e6SYuval Mintz 652fe56b9e6SYuval Mintz if (qed_status) { 653fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 654fe56b9e6SYuval Mintz "qed_dmae_host2grc: Wait Failed. source_addr 0x%llx, grc_addr 0x%llx, size_in_dwords 0x%x\n", 6551a635e48SYuval Mintz src_addr, dst_addr, length_dw); 656fe56b9e6SYuval Mintz return qed_status; 657fe56b9e6SYuval Mintz } 658fe56b9e6SYuval Mintz 659fe56b9e6SYuval Mintz if (dst_type == QED_DMAE_ADDRESS_HOST_VIRT) 660fe56b9e6SYuval Mintz memcpy((void *)(uintptr_t)(dst_addr), 661fe56b9e6SYuval Mintz &p_hwfn->dmae_info.p_intermediate_buffer[0], 6621a635e48SYuval Mintz length_dw * sizeof(u32)); 663fe56b9e6SYuval Mintz 664fe56b9e6SYuval Mintz return 0; 665fe56b9e6SYuval Mintz } 666fe56b9e6SYuval Mintz 667fe56b9e6SYuval Mintz static int qed_dmae_execute_command(struct qed_hwfn *p_hwfn, 668fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 669fe56b9e6SYuval Mintz u64 src_addr, u64 dst_addr, 670fe56b9e6SYuval Mintz u8 src_type, u8 dst_type, 671fe56b9e6SYuval Mintz u32 size_in_dwords, 672fe56b9e6SYuval Mintz struct qed_dmae_params *p_params) 673fe56b9e6SYuval Mintz { 674fe56b9e6SYuval Mintz dma_addr_t phys = p_hwfn->dmae_info.completion_word_phys_addr; 675fe56b9e6SYuval Mintz u16 length_cur = 0, i = 0, cnt_split = 0, length_mod = 0; 676fe56b9e6SYuval Mintz struct dmae_cmd *cmd = p_hwfn->dmae_info.p_dmae_cmd; 677fe56b9e6SYuval Mintz u64 src_addr_split = 0, dst_addr_split = 0; 678fe56b9e6SYuval Mintz u16 length_limit = DMAE_MAX_RW_SIZE; 679fe56b9e6SYuval Mintz int qed_status = 0; 680fe56b9e6SYuval Mintz u32 offset = 0; 681fe56b9e6SYuval Mintz 68264515dc8STomer Tayar if (p_hwfn->cdev->recov_in_prog) { 68364515dc8STomer Tayar DP_VERBOSE(p_hwfn, 68464515dc8STomer Tayar NETIF_MSG_HW, 68564515dc8STomer Tayar "Recovery is in progress. Avoid DMAE transaction [{src: addr 0x%llx, type %d}, {dst: addr 0x%llx, type %d}, size %d].\n", 68664515dc8STomer Tayar src_addr, src_type, dst_addr, dst_type, 68764515dc8STomer Tayar size_in_dwords); 68864515dc8STomer Tayar 68964515dc8STomer Tayar /* Let the flow complete w/o any error handling */ 69064515dc8STomer Tayar return 0; 69164515dc8STomer Tayar } 69264515dc8STomer Tayar 693fe56b9e6SYuval Mintz qed_dmae_opcode(p_hwfn, 694fe56b9e6SYuval Mintz (src_type == QED_DMAE_ADDRESS_GRC), 695fe56b9e6SYuval Mintz (dst_type == QED_DMAE_ADDRESS_GRC), 696fe56b9e6SYuval Mintz p_params); 697fe56b9e6SYuval Mintz 698fe56b9e6SYuval Mintz cmd->comp_addr_lo = cpu_to_le32(lower_32_bits(phys)); 699fe56b9e6SYuval Mintz cmd->comp_addr_hi = cpu_to_le32(upper_32_bits(phys)); 700fe56b9e6SYuval Mintz cmd->comp_val = cpu_to_le32(DMAE_COMPLETION_VAL); 701fe56b9e6SYuval Mintz 702fe56b9e6SYuval Mintz /* Check if the grc_addr is valid like < MAX_GRC_OFFSET */ 703fe56b9e6SYuval Mintz cnt_split = size_in_dwords / length_limit; 704fe56b9e6SYuval Mintz length_mod = size_in_dwords % length_limit; 705fe56b9e6SYuval Mintz 706fe56b9e6SYuval Mintz src_addr_split = src_addr; 707fe56b9e6SYuval Mintz dst_addr_split = dst_addr; 708fe56b9e6SYuval Mintz 709fe56b9e6SYuval Mintz for (i = 0; i <= cnt_split; i++) { 710fe56b9e6SYuval Mintz offset = length_limit * i; 711fe56b9e6SYuval Mintz 71283bf76e3SMichal Kalderon if (!QED_DMAE_FLAGS_IS_SET(p_params, RW_REPL_SRC)) { 713fe56b9e6SYuval Mintz if (src_type == QED_DMAE_ADDRESS_GRC) 714fe56b9e6SYuval Mintz src_addr_split = src_addr + offset; 715fe56b9e6SYuval Mintz else 716fe56b9e6SYuval Mintz src_addr_split = src_addr + (offset * 4); 717fe56b9e6SYuval Mintz } 718fe56b9e6SYuval Mintz 719fe56b9e6SYuval Mintz if (dst_type == QED_DMAE_ADDRESS_GRC) 720fe56b9e6SYuval Mintz dst_addr_split = dst_addr + offset; 721fe56b9e6SYuval Mintz else 722fe56b9e6SYuval Mintz dst_addr_split = dst_addr + (offset * 4); 723fe56b9e6SYuval Mintz 724fe56b9e6SYuval Mintz length_cur = (cnt_split == i) ? length_mod : length_limit; 725fe56b9e6SYuval Mintz 726fe56b9e6SYuval Mintz /* might be zero on last iteration */ 727fe56b9e6SYuval Mintz if (!length_cur) 728fe56b9e6SYuval Mintz continue; 729fe56b9e6SYuval Mintz 730fe56b9e6SYuval Mintz qed_status = qed_dmae_execute_sub_operation(p_hwfn, 731fe56b9e6SYuval Mintz p_ptt, 732fe56b9e6SYuval Mintz src_addr_split, 733fe56b9e6SYuval Mintz dst_addr_split, 734fe56b9e6SYuval Mintz src_type, 735fe56b9e6SYuval Mintz dst_type, 736fe56b9e6SYuval Mintz length_cur); 737fe56b9e6SYuval Mintz if (qed_status) { 7382ec276d5SIgor Russkikh qed_hw_err_notify(p_hwfn, p_ptt, QED_HW_ERR_DMAE_FAIL, 739fe56b9e6SYuval Mintz "qed_dmae_execute_sub_operation Failed with error 0x%x. source_addr 0x%llx, destination addr 0x%llx, size_in_dwords 0x%x\n", 7402ec276d5SIgor Russkikh qed_status, src_addr, 7412ec276d5SIgor Russkikh dst_addr, length_cur); 742fe56b9e6SYuval Mintz break; 743fe56b9e6SYuval Mintz } 744fe56b9e6SYuval Mintz } 745fe56b9e6SYuval Mintz 746fe56b9e6SYuval Mintz return qed_status; 747fe56b9e6SYuval Mintz } 748fe56b9e6SYuval Mintz 749fe56b9e6SYuval Mintz int qed_dmae_host2grc(struct qed_hwfn *p_hwfn, 750fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 75183bf76e3SMichal Kalderon u64 source_addr, u32 grc_addr, u32 size_in_dwords, 75283bf76e3SMichal Kalderon struct qed_dmae_params *p_params) 753fe56b9e6SYuval Mintz { 754fe56b9e6SYuval Mintz u32 grc_addr_in_dw = grc_addr / sizeof(u32); 755fe56b9e6SYuval Mintz int rc; 756fe56b9e6SYuval Mintz 757fe56b9e6SYuval Mintz 758fe56b9e6SYuval Mintz mutex_lock(&p_hwfn->dmae_info.mutex); 759fe56b9e6SYuval Mintz 760fe56b9e6SYuval Mintz rc = qed_dmae_execute_command(p_hwfn, p_ptt, source_addr, 761fe56b9e6SYuval Mintz grc_addr_in_dw, 762fe56b9e6SYuval Mintz QED_DMAE_ADDRESS_HOST_VIRT, 763fe56b9e6SYuval Mintz QED_DMAE_ADDRESS_GRC, 76483bf76e3SMichal Kalderon size_in_dwords, p_params); 765fe56b9e6SYuval Mintz 766fe56b9e6SYuval Mintz mutex_unlock(&p_hwfn->dmae_info.mutex); 767fe56b9e6SYuval Mintz 768fe56b9e6SYuval Mintz return rc; 769fe56b9e6SYuval Mintz } 770fe56b9e6SYuval Mintz 7711a635e48SYuval Mintz int qed_dmae_grc2host(struct qed_hwfn *p_hwfn, 7721a635e48SYuval Mintz struct qed_ptt *p_ptt, 7731a635e48SYuval Mintz u32 grc_addr, 77483bf76e3SMichal Kalderon dma_addr_t dest_addr, u32 size_in_dwords, 77583bf76e3SMichal Kalderon struct qed_dmae_params *p_params) 776722003acSSudarsana Reddy Kalluru { 777722003acSSudarsana Reddy Kalluru u32 grc_addr_in_dw = grc_addr / sizeof(u32); 778722003acSSudarsana Reddy Kalluru int rc; 779722003acSSudarsana Reddy Kalluru 780722003acSSudarsana Reddy Kalluru 781722003acSSudarsana Reddy Kalluru mutex_lock(&p_hwfn->dmae_info.mutex); 782722003acSSudarsana Reddy Kalluru 783722003acSSudarsana Reddy Kalluru rc = qed_dmae_execute_command(p_hwfn, p_ptt, grc_addr_in_dw, 784722003acSSudarsana Reddy Kalluru dest_addr, QED_DMAE_ADDRESS_GRC, 785722003acSSudarsana Reddy Kalluru QED_DMAE_ADDRESS_HOST_VIRT, 78683bf76e3SMichal Kalderon size_in_dwords, p_params); 787722003acSSudarsana Reddy Kalluru 788722003acSSudarsana Reddy Kalluru mutex_unlock(&p_hwfn->dmae_info.mutex); 789722003acSSudarsana Reddy Kalluru 790722003acSSudarsana Reddy Kalluru return rc; 791722003acSSudarsana Reddy Kalluru } 792722003acSSudarsana Reddy Kalluru 7931a635e48SYuval Mintz int qed_dmae_host2host(struct qed_hwfn *p_hwfn, 79437bff2b9SYuval Mintz struct qed_ptt *p_ptt, 79537bff2b9SYuval Mintz dma_addr_t source_addr, 79637bff2b9SYuval Mintz dma_addr_t dest_addr, 79737bff2b9SYuval Mintz u32 size_in_dwords, struct qed_dmae_params *p_params) 79837bff2b9SYuval Mintz { 79937bff2b9SYuval Mintz int rc; 80037bff2b9SYuval Mintz 80137bff2b9SYuval Mintz mutex_lock(&(p_hwfn->dmae_info.mutex)); 80237bff2b9SYuval Mintz 80337bff2b9SYuval Mintz rc = qed_dmae_execute_command(p_hwfn, p_ptt, source_addr, 80437bff2b9SYuval Mintz dest_addr, 80537bff2b9SYuval Mintz QED_DMAE_ADDRESS_HOST_PHYS, 80637bff2b9SYuval Mintz QED_DMAE_ADDRESS_HOST_PHYS, 80737bff2b9SYuval Mintz size_in_dwords, p_params); 80837bff2b9SYuval Mintz 80937bff2b9SYuval Mintz mutex_unlock(&(p_hwfn->dmae_info.mutex)); 81037bff2b9SYuval Mintz 81137bff2b9SYuval Mintz return rc; 81237bff2b9SYuval Mintz } 81337bff2b9SYuval Mintz 814d639836aSIgor Russkikh void qed_hw_err_notify(struct qed_hwfn *p_hwfn, 815d639836aSIgor Russkikh struct qed_ptt *p_ptt, 816d639836aSIgor Russkikh enum qed_hw_err_type err_type, char *fmt, ...) 817d639836aSIgor Russkikh { 818d639836aSIgor Russkikh char buf[QED_HW_ERR_MAX_STR_SIZE]; 819d639836aSIgor Russkikh va_list vl; 820d639836aSIgor Russkikh int len; 821d639836aSIgor Russkikh 822d639836aSIgor Russkikh if (fmt) { 823d639836aSIgor Russkikh va_start(vl, fmt); 824d639836aSIgor Russkikh len = vsnprintf(buf, QED_HW_ERR_MAX_STR_SIZE, fmt, vl); 825d639836aSIgor Russkikh va_end(vl); 826d639836aSIgor Russkikh 827d639836aSIgor Russkikh if (len > QED_HW_ERR_MAX_STR_SIZE - 1) 828d639836aSIgor Russkikh len = QED_HW_ERR_MAX_STR_SIZE - 1; 829d639836aSIgor Russkikh 830d639836aSIgor Russkikh DP_NOTICE(p_hwfn, "%s", buf); 831d639836aSIgor Russkikh } 832d639836aSIgor Russkikh 833d639836aSIgor Russkikh /* Fan failure cannot be masked by handling of another HW error */ 834d639836aSIgor Russkikh if (p_hwfn->cdev->recov_in_prog && 835d639836aSIgor Russkikh err_type != QED_HW_ERR_FAN_FAIL) { 836d639836aSIgor Russkikh DP_VERBOSE(p_hwfn, 837d639836aSIgor Russkikh NETIF_MSG_DRV, 838d639836aSIgor Russkikh "Recovery is in progress. Avoid notifying about HW error %d.\n", 839d639836aSIgor Russkikh err_type); 840d639836aSIgor Russkikh return; 841d639836aSIgor Russkikh } 842d639836aSIgor Russkikh 843d639836aSIgor Russkikh qed_hw_error_occurred(p_hwfn, err_type); 844d8d6c5a7SIgor Russkikh 845d8d6c5a7SIgor Russkikh if (fmt) 846d8d6c5a7SIgor Russkikh qed_mcp_send_raw_debug_data(p_hwfn, p_ptt, buf, len); 847d639836aSIgor Russkikh } 848d639836aSIgor Russkikh 849da090917STomer Tayar int qed_dmae_sanity(struct qed_hwfn *p_hwfn, 850da090917STomer Tayar struct qed_ptt *p_ptt, const char *phase) 851da090917STomer Tayar { 852da090917STomer Tayar u32 size = PAGE_SIZE / 2, val; 853da090917STomer Tayar int rc = 0; 854da090917STomer Tayar dma_addr_t p_phys; 855da090917STomer Tayar void *p_virt; 856da090917STomer Tayar u32 *p_tmp; 857da090917STomer Tayar 858da090917STomer Tayar p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 859da090917STomer Tayar 2 * size, &p_phys, GFP_KERNEL); 860da090917STomer Tayar if (!p_virt) { 861da090917STomer Tayar DP_NOTICE(p_hwfn, 862da090917STomer Tayar "DMAE sanity [%s]: failed to allocate memory\n", 863da090917STomer Tayar phase); 864da090917STomer Tayar return -ENOMEM; 865da090917STomer Tayar } 866da090917STomer Tayar 867da090917STomer Tayar /* Fill the bottom half of the allocated memory with a known pattern */ 868da090917STomer Tayar for (p_tmp = (u32 *)p_virt; 869da090917STomer Tayar p_tmp < (u32 *)((u8 *)p_virt + size); p_tmp++) { 870da090917STomer Tayar /* Save the address itself as the value */ 871da090917STomer Tayar val = (u32)(uintptr_t)p_tmp; 872da090917STomer Tayar *p_tmp = val; 873da090917STomer Tayar } 874da090917STomer Tayar 875da090917STomer Tayar /* Zero the top half of the allocated memory */ 876da090917STomer Tayar memset((u8 *)p_virt + size, 0, size); 877da090917STomer Tayar 878da090917STomer Tayar DP_VERBOSE(p_hwfn, 879da090917STomer Tayar QED_MSG_SP, 880da090917STomer Tayar "DMAE sanity [%s]: src_addr={phys 0x%llx, virt %p}, dst_addr={phys 0x%llx, virt %p}, size 0x%x\n", 881da090917STomer Tayar phase, 882da090917STomer Tayar (u64)p_phys, 883da090917STomer Tayar p_virt, (u64)(p_phys + size), (u8 *)p_virt + size, size); 884da090917STomer Tayar 885da090917STomer Tayar rc = qed_dmae_host2host(p_hwfn, p_ptt, p_phys, p_phys + size, 88683bf76e3SMichal Kalderon size / 4, NULL); 887da090917STomer Tayar if (rc) { 888da090917STomer Tayar DP_NOTICE(p_hwfn, 889da090917STomer Tayar "DMAE sanity [%s]: qed_dmae_host2host() failed. rc = %d.\n", 890da090917STomer Tayar phase, rc); 891da090917STomer Tayar goto out; 892da090917STomer Tayar } 893da090917STomer Tayar 894da090917STomer Tayar /* Verify that the top half of the allocated memory has the pattern */ 895da090917STomer Tayar for (p_tmp = (u32 *)((u8 *)p_virt + size); 896da090917STomer Tayar p_tmp < (u32 *)((u8 *)p_virt + (2 * size)); p_tmp++) { 897da090917STomer Tayar /* The corresponding address in the bottom half */ 898da090917STomer Tayar val = (u32)(uintptr_t)p_tmp - size; 899da090917STomer Tayar 900da090917STomer Tayar if (*p_tmp != val) { 901da090917STomer Tayar DP_NOTICE(p_hwfn, 902da090917STomer Tayar "DMAE sanity [%s]: addr={phys 0x%llx, virt %p}, read_val 0x%08x, expected_val 0x%08x\n", 903da090917STomer Tayar phase, 904da090917STomer Tayar (u64)p_phys + ((u8 *)p_tmp - (u8 *)p_virt), 905da090917STomer Tayar p_tmp, *p_tmp, val); 906da090917STomer Tayar rc = -EINVAL; 907da090917STomer Tayar goto out; 908da090917STomer Tayar } 909da090917STomer Tayar } 910da090917STomer Tayar 911da090917STomer Tayar out: 912da090917STomer Tayar dma_free_coherent(&p_hwfn->cdev->pdev->dev, 2 * size, p_virt, p_phys); 913da090917STomer Tayar return rc; 914da090917STomer Tayar } 915