1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 /* QLogic qed NIC Driver 3 * Copyright (c) 2015-2017 QLogic Corporation 4 * Copyright (c) 2019-2020 Marvell International Ltd. 5 */ 6 7 #ifndef _QED_HSI_H 8 #define _QED_HSI_H 9 10 #include <linux/types.h> 11 #include <linux/io.h> 12 #include <linux/bitops.h> 13 #include <linux/delay.h> 14 #include <linux/kernel.h> 15 #include <linux/list.h> 16 #include <linux/slab.h> 17 #include <linux/qed/common_hsi.h> 18 #include <linux/qed/storage_common.h> 19 #include <linux/qed/tcp_common.h> 20 #include <linux/qed/fcoe_common.h> 21 #include <linux/qed/eth_common.h> 22 #include <linux/qed/iscsi_common.h> 23 #include <linux/qed/iwarp_common.h> 24 #include <linux/qed/rdma_common.h> 25 #include <linux/qed/roce_common.h> 26 #include <linux/qed/qed_fcoe_if.h> 27 28 struct qed_hwfn; 29 struct qed_ptt; 30 31 /* Opcodes for the event ring */ 32 enum common_event_opcode { 33 COMMON_EVENT_PF_START, 34 COMMON_EVENT_PF_STOP, 35 COMMON_EVENT_VF_START, 36 COMMON_EVENT_VF_STOP, 37 COMMON_EVENT_VF_PF_CHANNEL, 38 COMMON_EVENT_VF_FLR, 39 COMMON_EVENT_PF_UPDATE, 40 COMMON_EVENT_MALICIOUS_VF, 41 COMMON_EVENT_RL_UPDATE, 42 COMMON_EVENT_EMPTY, 43 MAX_COMMON_EVENT_OPCODE 44 }; 45 46 /* Common Ramrod Command IDs */ 47 enum common_ramrod_cmd_id { 48 COMMON_RAMROD_UNUSED, 49 COMMON_RAMROD_PF_START, 50 COMMON_RAMROD_PF_STOP, 51 COMMON_RAMROD_VF_START, 52 COMMON_RAMROD_VF_STOP, 53 COMMON_RAMROD_PF_UPDATE, 54 COMMON_RAMROD_RL_UPDATE, 55 COMMON_RAMROD_EMPTY, 56 MAX_COMMON_RAMROD_CMD_ID 57 }; 58 59 /* How ll2 should deal with packet upon errors */ 60 enum core_error_handle { 61 LL2_DROP_PACKET, 62 LL2_DO_NOTHING, 63 LL2_ASSERT, 64 MAX_CORE_ERROR_HANDLE 65 }; 66 67 /* Opcodes for the event ring */ 68 enum core_event_opcode { 69 CORE_EVENT_TX_QUEUE_START, 70 CORE_EVENT_TX_QUEUE_STOP, 71 CORE_EVENT_RX_QUEUE_START, 72 CORE_EVENT_RX_QUEUE_STOP, 73 CORE_EVENT_RX_QUEUE_FLUSH, 74 CORE_EVENT_TX_QUEUE_UPDATE, 75 CORE_EVENT_QUEUE_STATS_QUERY, 76 MAX_CORE_EVENT_OPCODE 77 }; 78 79 /* The L4 pseudo checksum mode for Core */ 80 enum core_l4_pseudo_checksum_mode { 81 CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH, 82 CORE_L4_PSEUDO_CSUM_ZERO_LENGTH, 83 MAX_CORE_L4_PSEUDO_CHECKSUM_MODE 84 }; 85 86 /* Light-L2 RX Producers in Tstorm RAM */ 87 struct core_ll2_port_stats { 88 struct regpair gsi_invalid_hdr; 89 struct regpair gsi_invalid_pkt_length; 90 struct regpair gsi_unsupported_pkt_typ; 91 struct regpair gsi_crcchksm_error; 92 }; 93 94 /* LL2 TX Per Queue Stats */ 95 struct core_ll2_pstorm_per_queue_stat { 96 struct regpair sent_ucast_bytes; 97 struct regpair sent_mcast_bytes; 98 struct regpair sent_bcast_bytes; 99 struct regpair sent_ucast_pkts; 100 struct regpair sent_mcast_pkts; 101 struct regpair sent_bcast_pkts; 102 struct regpair error_drop_pkts; 103 }; 104 105 /* Light-L2 RX Producers in Tstorm RAM */ 106 struct core_ll2_rx_prod { 107 __le16 bd_prod; 108 __le16 cqe_prod; 109 }; 110 111 struct core_ll2_tstorm_per_queue_stat { 112 struct regpair packet_too_big_discard; 113 struct regpair no_buff_discard; 114 }; 115 116 struct core_ll2_ustorm_per_queue_stat { 117 struct regpair rcv_ucast_bytes; 118 struct regpair rcv_mcast_bytes; 119 struct regpair rcv_bcast_bytes; 120 struct regpair rcv_ucast_pkts; 121 struct regpair rcv_mcast_pkts; 122 struct regpair rcv_bcast_pkts; 123 }; 124 125 /* Structure for doorbell data, in PWM mode, for RX producers update. */ 126 struct core_pwm_prod_update_data { 127 __le16 icid; /* internal CID */ 128 u8 reserved0; 129 u8 params; 130 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_MASK 0x3 131 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_SHIFT 0 132 #define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_MASK 0x3F /* Set 0 */ 133 #define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_SHIFT 2 134 struct core_ll2_rx_prod prod; /* Producers */ 135 }; 136 137 /* Core Ramrod Command IDs (light L2) */ 138 enum core_ramrod_cmd_id { 139 CORE_RAMROD_UNUSED, 140 CORE_RAMROD_RX_QUEUE_START, 141 CORE_RAMROD_TX_QUEUE_START, 142 CORE_RAMROD_RX_QUEUE_STOP, 143 CORE_RAMROD_TX_QUEUE_STOP, 144 CORE_RAMROD_RX_QUEUE_FLUSH, 145 CORE_RAMROD_TX_QUEUE_UPDATE, 146 CORE_RAMROD_QUEUE_STATS_QUERY, 147 MAX_CORE_RAMROD_CMD_ID 148 }; 149 150 /* Core RX CQE Type for Light L2 */ 151 enum core_roce_flavor_type { 152 CORE_ROCE, 153 CORE_RROCE, 154 MAX_CORE_ROCE_FLAVOR_TYPE 155 }; 156 157 /* Specifies how ll2 should deal with packets errors: packet_too_big and 158 * no_buff. 159 */ 160 struct core_rx_action_on_error { 161 u8 error_type; 162 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3 163 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0 164 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3 165 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT 2 166 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF 167 #define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT 4 168 }; 169 170 /* Core RX BD for Light L2 */ 171 struct core_rx_bd { 172 struct regpair addr; 173 __le16 reserved[4]; 174 }; 175 176 /* Core RX CM offload BD for Light L2 */ 177 struct core_rx_bd_with_buff_len { 178 struct regpair addr; 179 __le16 buff_length; 180 __le16 reserved[3]; 181 }; 182 183 /* Core RX CM offload BD for Light L2 */ 184 union core_rx_bd_union { 185 struct core_rx_bd rx_bd; 186 struct core_rx_bd_with_buff_len rx_bd_with_len; 187 }; 188 189 /* Opaque Data for Light L2 RX CQE */ 190 struct core_rx_cqe_opaque_data { 191 __le32 data[2]; 192 }; 193 194 /* Core RX CQE Type for Light L2 */ 195 enum core_rx_cqe_type { 196 CORE_RX_CQE_ILLEGAL_TYPE, 197 CORE_RX_CQE_TYPE_REGULAR, 198 CORE_RX_CQE_TYPE_GSI_OFFLOAD, 199 CORE_RX_CQE_TYPE_SLOW_PATH, 200 MAX_CORE_RX_CQE_TYPE 201 }; 202 203 /* Core RX CQE for Light L2 */ 204 struct core_rx_fast_path_cqe { 205 u8 type; 206 u8 placement_offset; 207 struct parsing_and_err_flags parse_flags; 208 __le16 packet_length; 209 __le16 vlan; 210 struct core_rx_cqe_opaque_data opaque_data; 211 struct parsing_err_flags err_flags; 212 __le16 reserved0; 213 __le32 reserved1[3]; 214 }; 215 216 /* Core Rx CM offload CQE */ 217 struct core_rx_gsi_offload_cqe { 218 u8 type; 219 u8 data_length_error; 220 struct parsing_and_err_flags parse_flags; 221 __le16 data_length; 222 __le16 vlan; 223 __le32 src_mac_addrhi; 224 __le16 src_mac_addrlo; 225 __le16 qp_id; 226 __le32 src_qp; 227 struct core_rx_cqe_opaque_data opaque_data; 228 __le32 reserved; 229 }; 230 231 /* Core RX CQE for Light L2 */ 232 struct core_rx_slow_path_cqe { 233 u8 type; 234 u8 ramrod_cmd_id; 235 __le16 echo; 236 struct core_rx_cqe_opaque_data opaque_data; 237 __le32 reserved1[5]; 238 }; 239 240 /* Core RX CM offload BD for Light L2 */ 241 union core_rx_cqe_union { 242 struct core_rx_fast_path_cqe rx_cqe_fp; 243 struct core_rx_gsi_offload_cqe rx_cqe_gsi; 244 struct core_rx_slow_path_cqe rx_cqe_sp; 245 }; 246 247 /* Ramrod data for rx queue start ramrod */ 248 struct core_rx_start_ramrod_data { 249 struct regpair bd_base; 250 struct regpair cqe_pbl_addr; 251 __le16 mtu; 252 __le16 sb_id; 253 u8 sb_index; 254 u8 complete_cqe_flg; 255 u8 complete_event_flg; 256 u8 drop_ttl0_flg; 257 __le16 num_of_pbl_pages; 258 u8 inner_vlan_stripping_en; 259 u8 report_outer_vlan; 260 u8 queue_id; 261 u8 main_func_queue; 262 u8 mf_si_bcast_accept_all; 263 u8 mf_si_mcast_accept_all; 264 struct core_rx_action_on_error action_on_error; 265 u8 gsi_offload_flag; 266 u8 vport_id_valid; 267 u8 vport_id; 268 u8 zero_prod_flg; 269 u8 wipe_inner_vlan_pri_en; 270 u8 reserved[2]; 271 }; 272 273 /* Ramrod data for rx queue stop ramrod */ 274 struct core_rx_stop_ramrod_data { 275 u8 complete_cqe_flg; 276 u8 complete_event_flg; 277 u8 queue_id; 278 u8 reserved1; 279 __le16 reserved2[2]; 280 }; 281 282 /* Flags for Core TX BD */ 283 struct core_tx_bd_data { 284 __le16 as_bitfield; 285 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1 286 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0 287 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1 288 #define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT 1 289 #define CORE_TX_BD_DATA_START_BD_MASK 0x1 290 #define CORE_TX_BD_DATA_START_BD_SHIFT 2 291 #define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1 292 #define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3 293 #define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1 294 #define CORE_TX_BD_DATA_L4_CSUM_SHIFT 4 295 #define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1 296 #define CORE_TX_BD_DATA_IPV6_EXT_SHIFT 5 297 #define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1 298 #define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT 6 299 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1 300 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT 7 301 #define CORE_TX_BD_DATA_NBDS_MASK 0xF 302 #define CORE_TX_BD_DATA_NBDS_SHIFT 8 303 #define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1 304 #define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT 12 305 #define CORE_TX_BD_DATA_IP_LEN_MASK 0x1 306 #define CORE_TX_BD_DATA_IP_LEN_SHIFT 13 307 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_MASK 0x1 308 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_SHIFT 14 309 #define CORE_TX_BD_DATA_RESERVED0_MASK 0x1 310 #define CORE_TX_BD_DATA_RESERVED0_SHIFT 15 311 }; 312 313 /* Core TX BD for Light L2 */ 314 struct core_tx_bd { 315 struct regpair addr; 316 __le16 nbytes; 317 __le16 nw_vlan_or_lb_echo; 318 struct core_tx_bd_data bd_data; 319 __le16 bitfield1; 320 #define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF 321 #define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0 322 #define CORE_TX_BD_TX_DST_MASK 0x3 323 #define CORE_TX_BD_TX_DST_SHIFT 14 324 }; 325 326 /* Light L2 TX Destination */ 327 enum core_tx_dest { 328 CORE_TX_DEST_NW, 329 CORE_TX_DEST_LB, 330 CORE_TX_DEST_RESERVED, 331 CORE_TX_DEST_DROP, 332 MAX_CORE_TX_DEST 333 }; 334 335 /* Ramrod data for tx queue start ramrod */ 336 struct core_tx_start_ramrod_data { 337 struct regpair pbl_base_addr; 338 __le16 mtu; 339 __le16 sb_id; 340 u8 sb_index; 341 u8 stats_en; 342 u8 stats_id; 343 u8 conn_type; 344 __le16 pbl_size; 345 __le16 qm_pq_id; 346 u8 gsi_offload_flag; 347 u8 ctx_stats_en; 348 u8 vport_id_valid; 349 u8 vport_id; 350 u8 enforce_security_flag; 351 u8 reserved[7]; 352 }; 353 354 /* Ramrod data for tx queue stop ramrod */ 355 struct core_tx_stop_ramrod_data { 356 __le32 reserved0[2]; 357 }; 358 359 /* Ramrod data for tx queue update ramrod */ 360 struct core_tx_update_ramrod_data { 361 u8 update_qm_pq_id_flg; 362 u8 reserved0; 363 __le16 qm_pq_id; 364 __le32 reserved1[1]; 365 }; 366 367 /* Enum flag for what type of dcb data to update */ 368 enum dcb_dscp_update_mode { 369 DONT_UPDATE_DCB_DSCP, 370 UPDATE_DCB, 371 UPDATE_DSCP, 372 UPDATE_DCB_DSCP, 373 MAX_DCB_DSCP_UPDATE_MODE 374 }; 375 376 /* The core storm context for the Ystorm */ 377 struct ystorm_core_conn_st_ctx { 378 __le32 reserved[4]; 379 }; 380 381 /* The core storm context for the Pstorm */ 382 struct pstorm_core_conn_st_ctx { 383 __le32 reserved[20]; 384 }; 385 386 /* Core Slowpath Connection storm context of Xstorm */ 387 struct xstorm_core_conn_st_ctx { 388 __le32 spq_base_lo; 389 __le32 spq_base_hi; 390 struct regpair consolid_base_addr; 391 __le16 spq_cons; 392 __le16 consolid_cons; 393 __le32 reserved0[55]; 394 }; 395 396 struct e4_xstorm_core_conn_ag_ctx { 397 u8 reserved0; 398 u8 state; 399 u8 flags0; 400 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 401 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 402 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1 403 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1 404 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1 405 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2 406 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 407 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 408 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1 409 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4 410 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1 411 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5 412 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1 413 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6 414 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1 415 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7 416 u8 flags1; 417 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1 418 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0 419 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1 420 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1 421 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1 422 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2 423 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1 424 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3 425 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1 426 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4 427 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1 428 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5 429 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 430 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 431 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 432 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 433 u8 flags2; 434 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 435 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0 436 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 437 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2 438 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 439 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4 440 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 441 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6 442 u8 flags3; 443 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 444 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0 445 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 446 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2 447 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 448 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4 449 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 450 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6 451 u8 flags4; 452 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 453 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0 454 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 455 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2 456 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 457 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4 458 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3 459 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6 460 u8 flags5; 461 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3 462 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0 463 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3 464 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2 465 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3 466 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4 467 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3 468 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6 469 u8 flags6; 470 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3 471 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0 472 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3 473 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2 474 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3 475 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4 476 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 477 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 478 u8 flags7; 479 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 480 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 481 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3 482 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2 483 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 484 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 485 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 486 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6 487 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 488 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7 489 u8 flags8; 490 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 491 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0 492 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 493 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1 494 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 495 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2 496 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 497 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3 498 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 499 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4 500 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 501 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5 502 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 503 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6 504 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 505 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7 506 u8 flags9; 507 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 508 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0 509 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1 510 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1 511 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1 512 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2 513 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1 514 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3 515 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1 516 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4 517 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1 518 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5 519 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1 520 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6 521 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1 522 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7 523 u8 flags10; 524 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 525 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 526 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 527 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 528 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 529 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 530 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1 531 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3 532 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 533 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 534 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1 535 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5 536 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1 537 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6 538 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1 539 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7 540 u8 flags11; 541 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1 542 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0 543 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1 544 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1 545 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 546 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 547 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 548 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3 549 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 550 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4 551 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 552 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5 553 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 554 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 555 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1 556 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7 557 u8 flags12; 558 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1 559 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0 560 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1 561 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1 562 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 563 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 564 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 565 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 566 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1 567 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4 568 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1 569 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5 570 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1 571 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6 572 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1 573 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7 574 u8 flags13; 575 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1 576 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0 577 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1 578 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1 579 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 580 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 581 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 582 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 583 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 584 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 585 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 586 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 587 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 588 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 589 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 590 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 591 u8 flags14; 592 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1 593 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0 594 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1 595 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1 596 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1 597 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2 598 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1 599 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3 600 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1 601 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4 602 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1 603 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5 604 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3 605 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6 606 u8 byte2; 607 __le16 physical_q0; 608 __le16 consolid_prod; 609 __le16 reserved16; 610 __le16 tx_bd_cons; 611 __le16 tx_bd_or_spq_prod; 612 __le16 updated_qm_pq_id; 613 __le16 conn_dpi; 614 u8 byte3; 615 u8 byte4; 616 u8 byte5; 617 u8 byte6; 618 __le32 reg0; 619 __le32 reg1; 620 __le32 reg2; 621 __le32 reg3; 622 __le32 reg4; 623 __le32 reg5; 624 __le32 reg6; 625 __le16 word7; 626 __le16 word8; 627 __le16 word9; 628 __le16 word10; 629 __le32 reg7; 630 __le32 reg8; 631 __le32 reg9; 632 u8 byte7; 633 u8 byte8; 634 u8 byte9; 635 u8 byte10; 636 u8 byte11; 637 u8 byte12; 638 u8 byte13; 639 u8 byte14; 640 u8 byte15; 641 u8 e5_reserved; 642 __le16 word11; 643 __le32 reg10; 644 __le32 reg11; 645 __le32 reg12; 646 __le32 reg13; 647 __le32 reg14; 648 __le32 reg15; 649 __le32 reg16; 650 __le32 reg17; 651 __le32 reg18; 652 __le32 reg19; 653 __le16 word12; 654 __le16 word13; 655 __le16 word14; 656 __le16 word15; 657 }; 658 659 struct e4_tstorm_core_conn_ag_ctx { 660 u8 byte0; 661 u8 byte1; 662 u8 flags0; 663 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 664 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 665 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 666 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 667 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1 668 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2 669 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1 670 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3 671 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1 672 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4 673 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1 674 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5 675 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 676 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6 677 u8 flags1; 678 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 679 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0 680 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 681 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2 682 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 683 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4 684 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 685 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6 686 u8 flags2; 687 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 688 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0 689 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 690 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2 691 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 692 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4 693 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 694 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6 695 u8 flags3; 696 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 697 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0 698 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 699 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2 700 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 701 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4 702 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 703 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5 704 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 705 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6 706 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 707 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7 708 u8 flags4; 709 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 710 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0 711 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 712 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1 713 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 714 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2 715 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 716 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3 717 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 718 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4 719 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 720 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5 721 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 722 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6 723 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 724 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7 725 u8 flags5; 726 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 727 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0 728 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 729 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1 730 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 731 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2 732 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 733 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3 734 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 735 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4 736 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 737 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5 738 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 739 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6 740 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 741 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7 742 __le32 reg0; 743 __le32 reg1; 744 __le32 reg2; 745 __le32 reg3; 746 __le32 reg4; 747 __le32 reg5; 748 __le32 reg6; 749 __le32 reg7; 750 __le32 reg8; 751 u8 byte2; 752 u8 byte3; 753 __le16 word0; 754 u8 byte4; 755 u8 byte5; 756 __le16 word1; 757 __le16 word2; 758 __le16 word3; 759 __le32 ll2_rx_prod; 760 __le32 reg10; 761 }; 762 763 struct e4_ustorm_core_conn_ag_ctx { 764 u8 reserved; 765 u8 byte1; 766 u8 flags0; 767 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 768 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 769 #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 770 #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 771 #define E4_USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 772 #define E4_USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 773 #define E4_USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 774 #define E4_USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 775 #define E4_USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 776 #define E4_USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 777 u8 flags1; 778 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 779 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0 780 #define E4_USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 781 #define E4_USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2 782 #define E4_USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 783 #define E4_USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4 784 #define E4_USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 785 #define E4_USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6 786 u8 flags2; 787 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 788 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 789 #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 790 #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 791 #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 792 #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 793 #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 794 #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3 795 #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 796 #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4 797 #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 798 #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5 799 #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 800 #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6 801 #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 802 #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7 803 u8 flags3; 804 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 805 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0 806 #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 807 #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1 808 #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 809 #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2 810 #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 811 #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3 812 #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 813 #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4 814 #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 815 #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5 816 #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 817 #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6 818 #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 819 #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7 820 u8 byte2; 821 u8 byte3; 822 __le16 word0; 823 __le16 word1; 824 __le32 rx_producers; 825 __le32 reg1; 826 __le32 reg2; 827 __le32 reg3; 828 __le16 word2; 829 __le16 word3; 830 }; 831 832 /* The core storm context for the Mstorm */ 833 struct mstorm_core_conn_st_ctx { 834 __le32 reserved[40]; 835 }; 836 837 /* The core storm context for the Ustorm */ 838 struct ustorm_core_conn_st_ctx { 839 __le32 reserved[20]; 840 }; 841 842 /* The core storm context for the Tstorm */ 843 struct tstorm_core_conn_st_ctx { 844 __le32 reserved[4]; 845 }; 846 847 /* core connection context */ 848 struct e4_core_conn_context { 849 struct ystorm_core_conn_st_ctx ystorm_st_context; 850 struct regpair ystorm_st_padding[2]; 851 struct pstorm_core_conn_st_ctx pstorm_st_context; 852 struct regpair pstorm_st_padding[2]; 853 struct xstorm_core_conn_st_ctx xstorm_st_context; 854 struct e4_xstorm_core_conn_ag_ctx xstorm_ag_context; 855 struct e4_tstorm_core_conn_ag_ctx tstorm_ag_context; 856 struct e4_ustorm_core_conn_ag_ctx ustorm_ag_context; 857 struct mstorm_core_conn_st_ctx mstorm_st_context; 858 struct ustorm_core_conn_st_ctx ustorm_st_context; 859 struct regpair ustorm_st_padding[2]; 860 struct tstorm_core_conn_st_ctx tstorm_st_context; 861 struct regpair tstorm_st_padding[2]; 862 }; 863 864 struct eth_mstorm_per_pf_stat { 865 struct regpair gre_discard_pkts; 866 struct regpair vxlan_discard_pkts; 867 struct regpair geneve_discard_pkts; 868 struct regpair lb_discard_pkts; 869 }; 870 871 struct eth_mstorm_per_queue_stat { 872 struct regpair ttl0_discard; 873 struct regpair packet_too_big_discard; 874 struct regpair no_buff_discard; 875 struct regpair not_active_discard; 876 struct regpair tpa_coalesced_pkts; 877 struct regpair tpa_coalesced_events; 878 struct regpair tpa_aborts_num; 879 struct regpair tpa_coalesced_bytes; 880 }; 881 882 /* Ethernet TX Per PF */ 883 struct eth_pstorm_per_pf_stat { 884 struct regpair sent_lb_ucast_bytes; 885 struct regpair sent_lb_mcast_bytes; 886 struct regpair sent_lb_bcast_bytes; 887 struct regpair sent_lb_ucast_pkts; 888 struct regpair sent_lb_mcast_pkts; 889 struct regpair sent_lb_bcast_pkts; 890 struct regpair sent_gre_bytes; 891 struct regpair sent_vxlan_bytes; 892 struct regpair sent_geneve_bytes; 893 struct regpair sent_mpls_bytes; 894 struct regpair sent_gre_mpls_bytes; 895 struct regpair sent_udp_mpls_bytes; 896 struct regpair sent_gre_pkts; 897 struct regpair sent_vxlan_pkts; 898 struct regpair sent_geneve_pkts; 899 struct regpair sent_mpls_pkts; 900 struct regpair sent_gre_mpls_pkts; 901 struct regpair sent_udp_mpls_pkts; 902 struct regpair gre_drop_pkts; 903 struct regpair vxlan_drop_pkts; 904 struct regpair geneve_drop_pkts; 905 struct regpair mpls_drop_pkts; 906 struct regpair gre_mpls_drop_pkts; 907 struct regpair udp_mpls_drop_pkts; 908 }; 909 910 /* Ethernet TX Per Queue Stats */ 911 struct eth_pstorm_per_queue_stat { 912 struct regpair sent_ucast_bytes; 913 struct regpair sent_mcast_bytes; 914 struct regpair sent_bcast_bytes; 915 struct regpair sent_ucast_pkts; 916 struct regpair sent_mcast_pkts; 917 struct regpair sent_bcast_pkts; 918 struct regpair error_drop_pkts; 919 }; 920 921 /* ETH Rx producers data */ 922 struct eth_rx_rate_limit { 923 __le16 mult; 924 __le16 cnst; 925 u8 add_sub_cnst; 926 u8 reserved0; 927 __le16 reserved1; 928 }; 929 930 /* Update RSS indirection table entry command */ 931 struct eth_tstorm_rss_update_data { 932 u8 valid; 933 u8 vport_id; 934 u8 ind_table_index; 935 u8 reserved; 936 __le16 ind_table_value; 937 __le16 reserved1; 938 }; 939 940 struct eth_ustorm_per_pf_stat { 941 struct regpair rcv_lb_ucast_bytes; 942 struct regpair rcv_lb_mcast_bytes; 943 struct regpair rcv_lb_bcast_bytes; 944 struct regpair rcv_lb_ucast_pkts; 945 struct regpair rcv_lb_mcast_pkts; 946 struct regpair rcv_lb_bcast_pkts; 947 struct regpair rcv_gre_bytes; 948 struct regpair rcv_vxlan_bytes; 949 struct regpair rcv_geneve_bytes; 950 struct regpair rcv_gre_pkts; 951 struct regpair rcv_vxlan_pkts; 952 struct regpair rcv_geneve_pkts; 953 }; 954 955 struct eth_ustorm_per_queue_stat { 956 struct regpair rcv_ucast_bytes; 957 struct regpair rcv_mcast_bytes; 958 struct regpair rcv_bcast_bytes; 959 struct regpair rcv_ucast_pkts; 960 struct regpair rcv_mcast_pkts; 961 struct regpair rcv_bcast_pkts; 962 }; 963 964 /* Event Ring VF-PF Channel data */ 965 struct vf_pf_channel_eqe_data { 966 struct regpair msg_addr; 967 }; 968 969 /* Event Ring malicious VF data */ 970 struct malicious_vf_eqe_data { 971 u8 vf_id; 972 u8 err_id; 973 __le16 reserved[3]; 974 }; 975 976 /* Event Ring initial cleanup data */ 977 struct initial_cleanup_eqe_data { 978 u8 vf_id; 979 u8 reserved[7]; 980 }; 981 982 /* Event Data Union */ 983 union event_ring_data { 984 u8 bytes[8]; 985 struct vf_pf_channel_eqe_data vf_pf_channel; 986 struct iscsi_eqe_data iscsi_info; 987 struct iscsi_connect_done_results iscsi_conn_done_info; 988 union rdma_eqe_data rdma_data; 989 struct malicious_vf_eqe_data malicious_vf; 990 struct initial_cleanup_eqe_data vf_init_cleanup; 991 }; 992 993 /* Event Ring Entry */ 994 struct event_ring_entry { 995 u8 protocol_id; 996 u8 opcode; 997 u8 reserved0; 998 u8 vf_id; 999 __le16 echo; 1000 u8 fw_return_code; 1001 u8 flags; 1002 #define EVENT_RING_ENTRY_ASYNC_MASK 0x1 1003 #define EVENT_RING_ENTRY_ASYNC_SHIFT 0 1004 #define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F 1005 #define EVENT_RING_ENTRY_RESERVED1_SHIFT 1 1006 union event_ring_data data; 1007 }; 1008 1009 /* Event Ring Next Page Address */ 1010 struct event_ring_next_addr { 1011 struct regpair addr; 1012 __le32 reserved[2]; 1013 }; 1014 1015 /* Event Ring Element */ 1016 union event_ring_element { 1017 struct event_ring_entry entry; 1018 struct event_ring_next_addr next_addr; 1019 }; 1020 1021 /* Ports mode */ 1022 enum fw_flow_ctrl_mode { 1023 flow_ctrl_pause, 1024 flow_ctrl_pfc, 1025 MAX_FW_FLOW_CTRL_MODE 1026 }; 1027 1028 /* GFT profile type */ 1029 enum gft_profile_type { 1030 GFT_PROFILE_TYPE_4_TUPLE, 1031 GFT_PROFILE_TYPE_L4_DST_PORT, 1032 GFT_PROFILE_TYPE_IP_DST_ADDR, 1033 GFT_PROFILE_TYPE_IP_SRC_ADDR, 1034 GFT_PROFILE_TYPE_TUNNEL_TYPE, 1035 MAX_GFT_PROFILE_TYPE 1036 }; 1037 1038 /* Major and Minor hsi Versions */ 1039 struct hsi_fp_ver_struct { 1040 u8 minor_ver_arr[2]; 1041 u8 major_ver_arr[2]; 1042 }; 1043 1044 enum iwarp_ll2_tx_queues { 1045 IWARP_LL2_IN_ORDER_TX_QUEUE = 1, 1046 IWARP_LL2_ALIGNED_TX_QUEUE, 1047 IWARP_LL2_ALIGNED_RIGHT_TRIMMED_TX_QUEUE, 1048 IWARP_LL2_ERROR, 1049 MAX_IWARP_LL2_TX_QUEUES 1050 }; 1051 1052 /* Malicious VF error ID */ 1053 enum malicious_vf_error_id { 1054 MALICIOUS_VF_NO_ERROR, 1055 VF_PF_CHANNEL_NOT_READY, 1056 VF_ZONE_MSG_NOT_VALID, 1057 VF_ZONE_FUNC_NOT_ENABLED, 1058 ETH_PACKET_TOO_SMALL, 1059 ETH_ILLEGAL_VLAN_MODE, 1060 ETH_MTU_VIOLATION, 1061 ETH_ILLEGAL_INBAND_TAGS, 1062 ETH_VLAN_INSERT_AND_INBAND_VLAN, 1063 ETH_ILLEGAL_NBDS, 1064 ETH_FIRST_BD_WO_SOP, 1065 ETH_INSUFFICIENT_BDS, 1066 ETH_ILLEGAL_LSO_HDR_NBDS, 1067 ETH_ILLEGAL_LSO_MSS, 1068 ETH_ZERO_SIZE_BD, 1069 ETH_ILLEGAL_LSO_HDR_LEN, 1070 ETH_INSUFFICIENT_PAYLOAD, 1071 ETH_EDPM_OUT_OF_SYNC, 1072 ETH_TUNN_IPV6_EXT_NBD_ERR, 1073 ETH_CONTROL_PACKET_VIOLATION, 1074 ETH_ANTI_SPOOFING_ERR, 1075 ETH_PACKET_SIZE_TOO_LARGE, 1076 CORE_ILLEGAL_VLAN_MODE, 1077 CORE_ILLEGAL_NBDS, 1078 CORE_FIRST_BD_WO_SOP, 1079 CORE_INSUFFICIENT_BDS, 1080 CORE_PACKET_TOO_SMALL, 1081 CORE_ILLEGAL_INBAND_TAGS, 1082 CORE_VLAN_INSERT_AND_INBAND_VLAN, 1083 CORE_MTU_VIOLATION, 1084 CORE_CONTROL_PACKET_VIOLATION, 1085 CORE_ANTI_SPOOFING_ERR, 1086 CORE_PACKET_SIZE_TOO_LARGE, 1087 CORE_ILLEGAL_BD_FLAGS, 1088 CORE_GSI_PACKET_VIOLATION, 1089 MAX_MALICIOUS_VF_ERROR_ID, 1090 }; 1091 1092 /* Mstorm non-triggering VF zone */ 1093 struct mstorm_non_trigger_vf_zone { 1094 struct eth_mstorm_per_queue_stat eth_queue_stat; 1095 struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD]; 1096 }; 1097 1098 /* Mstorm VF zone */ 1099 struct mstorm_vf_zone { 1100 struct mstorm_non_trigger_vf_zone non_trigger; 1101 }; 1102 1103 /* vlan header including TPID and TCI fields */ 1104 struct vlan_header { 1105 __le16 tpid; 1106 __le16 tci; 1107 }; 1108 1109 /* outer tag configurations */ 1110 struct outer_tag_config_struct { 1111 u8 enable_stag_pri_change; 1112 u8 pri_map_valid; 1113 u8 reserved[2]; 1114 struct vlan_header outer_tag; 1115 u8 inner_to_outer_pri_map[8]; 1116 }; 1117 1118 /* personality per PF */ 1119 enum personality_type { 1120 BAD_PERSONALITY_TYP, 1121 PERSONALITY_ISCSI, 1122 PERSONALITY_FCOE, 1123 PERSONALITY_RDMA_AND_ETH, 1124 PERSONALITY_RDMA, 1125 PERSONALITY_CORE, 1126 PERSONALITY_ETH, 1127 PERSONALITY_RESERVED, 1128 MAX_PERSONALITY_TYPE 1129 }; 1130 1131 /* tunnel configuration */ 1132 struct pf_start_tunnel_config { 1133 u8 set_vxlan_udp_port_flg; 1134 u8 set_geneve_udp_port_flg; 1135 u8 set_no_inner_l2_vxlan_udp_port_flg; 1136 u8 tunnel_clss_vxlan; 1137 u8 tunnel_clss_l2geneve; 1138 u8 tunnel_clss_ipgeneve; 1139 u8 tunnel_clss_l2gre; 1140 u8 tunnel_clss_ipgre; 1141 __le16 vxlan_udp_port; 1142 __le16 geneve_udp_port; 1143 __le16 no_inner_l2_vxlan_udp_port; 1144 __le16 reserved[3]; 1145 }; 1146 1147 /* Ramrod data for PF start ramrod */ 1148 struct pf_start_ramrod_data { 1149 struct regpair event_ring_pbl_addr; 1150 struct regpair consolid_q_pbl_addr; 1151 struct pf_start_tunnel_config tunnel_config; 1152 __le16 event_ring_sb_id; 1153 u8 base_vf_id; 1154 u8 num_vfs; 1155 u8 event_ring_num_pages; 1156 u8 event_ring_sb_index; 1157 u8 path_id; 1158 u8 warning_as_error; 1159 u8 dont_log_ramrods; 1160 u8 personality; 1161 __le16 log_type_mask; 1162 u8 mf_mode; 1163 u8 integ_phase; 1164 u8 allow_npar_tx_switching; 1165 u8 reserved0; 1166 struct hsi_fp_ver_struct hsi_fp_ver; 1167 struct outer_tag_config_struct outer_tag_config; 1168 }; 1169 1170 /* Data for port update ramrod */ 1171 struct protocol_dcb_data { 1172 u8 dcb_enable_flag; 1173 u8 dscp_enable_flag; 1174 u8 dcb_priority; 1175 u8 dcb_tc; 1176 u8 dscp_val; 1177 u8 dcb_dont_add_vlan0; 1178 }; 1179 1180 /* Update tunnel configuration */ 1181 struct pf_update_tunnel_config { 1182 u8 update_rx_pf_clss; 1183 u8 update_rx_def_ucast_clss; 1184 u8 update_rx_def_non_ucast_clss; 1185 u8 set_vxlan_udp_port_flg; 1186 u8 set_geneve_udp_port_flg; 1187 u8 set_no_inner_l2_vxlan_udp_port_flg; 1188 u8 tunnel_clss_vxlan; 1189 u8 tunnel_clss_l2geneve; 1190 u8 tunnel_clss_ipgeneve; 1191 u8 tunnel_clss_l2gre; 1192 u8 tunnel_clss_ipgre; 1193 u8 reserved; 1194 __le16 vxlan_udp_port; 1195 __le16 geneve_udp_port; 1196 __le16 no_inner_l2_vxlan_udp_port; 1197 __le16 reserved1[3]; 1198 }; 1199 1200 /* Data for port update ramrod */ 1201 struct pf_update_ramrod_data { 1202 u8 update_eth_dcb_data_mode; 1203 u8 update_fcoe_dcb_data_mode; 1204 u8 update_iscsi_dcb_data_mode; 1205 u8 update_roce_dcb_data_mode; 1206 u8 update_rroce_dcb_data_mode; 1207 u8 update_iwarp_dcb_data_mode; 1208 u8 update_mf_vlan_flag; 1209 u8 update_enable_stag_pri_change; 1210 struct protocol_dcb_data eth_dcb_data; 1211 struct protocol_dcb_data fcoe_dcb_data; 1212 struct protocol_dcb_data iscsi_dcb_data; 1213 struct protocol_dcb_data roce_dcb_data; 1214 struct protocol_dcb_data rroce_dcb_data; 1215 struct protocol_dcb_data iwarp_dcb_data; 1216 __le16 mf_vlan; 1217 u8 enable_stag_pri_change; 1218 u8 reserved; 1219 struct pf_update_tunnel_config tunnel_config; 1220 }; 1221 1222 /* Ports mode */ 1223 enum ports_mode { 1224 ENGX2_PORTX1, 1225 ENGX2_PORTX2, 1226 ENGX1_PORTX1, 1227 ENGX1_PORTX2, 1228 ENGX1_PORTX4, 1229 MAX_PORTS_MODE 1230 }; 1231 1232 /* use to index in hsi_fp_[major|minor]_ver_arr per protocol */ 1233 enum protocol_version_array_key { 1234 ETH_VER_KEY = 0, 1235 ROCE_VER_KEY, 1236 MAX_PROTOCOL_VERSION_ARRAY_KEY 1237 }; 1238 1239 /* RDMA TX Stats */ 1240 struct rdma_sent_stats { 1241 struct regpair sent_bytes; 1242 struct regpair sent_pkts; 1243 }; 1244 1245 /* Pstorm non-triggering VF zone */ 1246 struct pstorm_non_trigger_vf_zone { 1247 struct eth_pstorm_per_queue_stat eth_queue_stat; 1248 struct rdma_sent_stats rdma_stats; 1249 }; 1250 1251 /* Pstorm VF zone */ 1252 struct pstorm_vf_zone { 1253 struct pstorm_non_trigger_vf_zone non_trigger; 1254 struct regpair reserved[7]; 1255 }; 1256 1257 /* Ramrod Header of SPQE */ 1258 struct ramrod_header { 1259 __le32 cid; 1260 u8 cmd_id; 1261 u8 protocol_id; 1262 __le16 echo; 1263 }; 1264 1265 /* RDMA RX Stats */ 1266 struct rdma_rcv_stats { 1267 struct regpair rcv_bytes; 1268 struct regpair rcv_pkts; 1269 }; 1270 1271 /* Data for update QCN/DCQCN RL ramrod */ 1272 struct rl_update_ramrod_data { 1273 u8 qcn_update_param_flg; 1274 u8 dcqcn_update_param_flg; 1275 u8 rl_init_flg; 1276 u8 rl_start_flg; 1277 u8 rl_stop_flg; 1278 u8 rl_id_first; 1279 u8 rl_id_last; 1280 u8 rl_dc_qcn_flg; 1281 u8 dcqcn_reset_alpha_on_idle; 1282 u8 rl_bc_stage_th; 1283 u8 rl_timer_stage_th; 1284 u8 reserved1; 1285 __le32 rl_bc_rate; 1286 __le16 rl_max_rate; 1287 __le16 rl_r_ai; 1288 __le16 rl_r_hai; 1289 __le16 dcqcn_g; 1290 __le32 dcqcn_k_us; 1291 __le32 dcqcn_timeuot_us; 1292 __le32 qcn_timeuot_us; 1293 __le32 reserved2; 1294 }; 1295 1296 /* Slowpath Element (SPQE) */ 1297 struct slow_path_element { 1298 struct ramrod_header hdr; 1299 struct regpair data_ptr; 1300 }; 1301 1302 /* Tstorm non-triggering VF zone */ 1303 struct tstorm_non_trigger_vf_zone { 1304 struct rdma_rcv_stats rdma_stats; 1305 }; 1306 1307 struct tstorm_per_port_stat { 1308 struct regpair trunc_error_discard; 1309 struct regpair mac_error_discard; 1310 struct regpair mftag_filter_discard; 1311 struct regpair eth_mac_filter_discard; 1312 struct regpair ll2_mac_filter_discard; 1313 struct regpair ll2_conn_disabled_discard; 1314 struct regpair iscsi_irregular_pkt; 1315 struct regpair fcoe_irregular_pkt; 1316 struct regpair roce_irregular_pkt; 1317 struct regpair iwarp_irregular_pkt; 1318 struct regpair eth_irregular_pkt; 1319 struct regpair toe_irregular_pkt; 1320 struct regpair preroce_irregular_pkt; 1321 struct regpair eth_gre_tunn_filter_discard; 1322 struct regpair eth_vxlan_tunn_filter_discard; 1323 struct regpair eth_geneve_tunn_filter_discard; 1324 struct regpair eth_gft_drop_pkt; 1325 }; 1326 1327 /* Tstorm VF zone */ 1328 struct tstorm_vf_zone { 1329 struct tstorm_non_trigger_vf_zone non_trigger; 1330 }; 1331 1332 /* Tunnel classification scheme */ 1333 enum tunnel_clss { 1334 TUNNEL_CLSS_MAC_VLAN = 0, 1335 TUNNEL_CLSS_MAC_VNI, 1336 TUNNEL_CLSS_INNER_MAC_VLAN, 1337 TUNNEL_CLSS_INNER_MAC_VNI, 1338 TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE, 1339 MAX_TUNNEL_CLSS 1340 }; 1341 1342 /* Ustorm non-triggering VF zone */ 1343 struct ustorm_non_trigger_vf_zone { 1344 struct eth_ustorm_per_queue_stat eth_queue_stat; 1345 struct regpair vf_pf_msg_addr; 1346 }; 1347 1348 /* Ustorm triggering VF zone */ 1349 struct ustorm_trigger_vf_zone { 1350 u8 vf_pf_msg_valid; 1351 u8 reserved[7]; 1352 }; 1353 1354 /* Ustorm VF zone */ 1355 struct ustorm_vf_zone { 1356 struct ustorm_non_trigger_vf_zone non_trigger; 1357 struct ustorm_trigger_vf_zone trigger; 1358 }; 1359 1360 /* VF-PF channel data */ 1361 struct vf_pf_channel_data { 1362 __le32 ready; 1363 u8 valid; 1364 u8 reserved0; 1365 __le16 reserved1; 1366 }; 1367 1368 /* Ramrod data for VF start ramrod */ 1369 struct vf_start_ramrod_data { 1370 u8 vf_id; 1371 u8 enable_flr_ack; 1372 __le16 opaque_fid; 1373 u8 personality; 1374 u8 reserved[7]; 1375 struct hsi_fp_ver_struct hsi_fp_ver; 1376 1377 }; 1378 1379 /* Ramrod data for VF start ramrod */ 1380 struct vf_stop_ramrod_data { 1381 u8 vf_id; 1382 u8 reserved0; 1383 __le16 reserved1; 1384 __le32 reserved2; 1385 }; 1386 1387 /* VF zone size mode */ 1388 enum vf_zone_size_mode { 1389 VF_ZONE_SIZE_MODE_DEFAULT, 1390 VF_ZONE_SIZE_MODE_DOUBLE, 1391 VF_ZONE_SIZE_MODE_QUAD, 1392 MAX_VF_ZONE_SIZE_MODE 1393 }; 1394 1395 /* Xstorm non-triggering VF zone */ 1396 struct xstorm_non_trigger_vf_zone { 1397 struct regpair non_edpm_ack_pkts; 1398 }; 1399 1400 /* Tstorm VF zone */ 1401 struct xstorm_vf_zone { 1402 struct xstorm_non_trigger_vf_zone non_trigger; 1403 }; 1404 1405 /* Attentions status block */ 1406 struct atten_status_block { 1407 __le32 atten_bits; 1408 __le32 atten_ack; 1409 __le16 reserved0; 1410 __le16 sb_index; 1411 __le32 reserved1; 1412 }; 1413 1414 /* DMAE command */ 1415 struct dmae_cmd { 1416 __le32 opcode; 1417 #define DMAE_CMD_SRC_MASK 0x1 1418 #define DMAE_CMD_SRC_SHIFT 0 1419 #define DMAE_CMD_DST_MASK 0x3 1420 #define DMAE_CMD_DST_SHIFT 1 1421 #define DMAE_CMD_C_DST_MASK 0x1 1422 #define DMAE_CMD_C_DST_SHIFT 3 1423 #define DMAE_CMD_CRC_RESET_MASK 0x1 1424 #define DMAE_CMD_CRC_RESET_SHIFT 4 1425 #define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1 1426 #define DMAE_CMD_SRC_ADDR_RESET_SHIFT 5 1427 #define DMAE_CMD_DST_ADDR_RESET_MASK 0x1 1428 #define DMAE_CMD_DST_ADDR_RESET_SHIFT 6 1429 #define DMAE_CMD_COMP_FUNC_MASK 0x1 1430 #define DMAE_CMD_COMP_FUNC_SHIFT 7 1431 #define DMAE_CMD_COMP_WORD_EN_MASK 0x1 1432 #define DMAE_CMD_COMP_WORD_EN_SHIFT 8 1433 #define DMAE_CMD_COMP_CRC_EN_MASK 0x1 1434 #define DMAE_CMD_COMP_CRC_EN_SHIFT 9 1435 #define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7 1436 #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10 1437 #define DMAE_CMD_RESERVED1_MASK 0x1 1438 #define DMAE_CMD_RESERVED1_SHIFT 13 1439 #define DMAE_CMD_ENDIANITY_MODE_MASK 0x3 1440 #define DMAE_CMD_ENDIANITY_MODE_SHIFT 14 1441 #define DMAE_CMD_ERR_HANDLING_MASK 0x3 1442 #define DMAE_CMD_ERR_HANDLING_SHIFT 16 1443 #define DMAE_CMD_PORT_ID_MASK 0x3 1444 #define DMAE_CMD_PORT_ID_SHIFT 18 1445 #define DMAE_CMD_SRC_PF_ID_MASK 0xF 1446 #define DMAE_CMD_SRC_PF_ID_SHIFT 20 1447 #define DMAE_CMD_DST_PF_ID_MASK 0xF 1448 #define DMAE_CMD_DST_PF_ID_SHIFT 24 1449 #define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1 1450 #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28 1451 #define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1 1452 #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29 1453 #define DMAE_CMD_RESERVED2_MASK 0x3 1454 #define DMAE_CMD_RESERVED2_SHIFT 30 1455 __le32 src_addr_lo; 1456 __le32 src_addr_hi; 1457 __le32 dst_addr_lo; 1458 __le32 dst_addr_hi; 1459 __le16 length_dw; 1460 __le16 opcode_b; 1461 #define DMAE_CMD_SRC_VF_ID_MASK 0xFF 1462 #define DMAE_CMD_SRC_VF_ID_SHIFT 0 1463 #define DMAE_CMD_DST_VF_ID_MASK 0xFF 1464 #define DMAE_CMD_DST_VF_ID_SHIFT 8 1465 __le32 comp_addr_lo; 1466 __le32 comp_addr_hi; 1467 __le32 comp_val; 1468 __le32 crc32; 1469 __le32 crc_32_c; 1470 __le16 crc16; 1471 __le16 crc16_c; 1472 __le16 crc10; 1473 __le16 error_bit_reserved; 1474 #define DMAE_CMD_ERROR_BIT_MASK 0x1 1475 #define DMAE_CMD_ERROR_BIT_SHIFT 0 1476 #define DMAE_CMD_RESERVED_MASK 0x7FFF 1477 #define DMAE_CMD_RESERVED_SHIFT 1 1478 __le16 xsum16; 1479 __le16 xsum8; 1480 }; 1481 1482 enum dmae_cmd_comp_crc_en_enum { 1483 dmae_cmd_comp_crc_disabled, 1484 dmae_cmd_comp_crc_enabled, 1485 MAX_DMAE_CMD_COMP_CRC_EN_ENUM 1486 }; 1487 1488 enum dmae_cmd_comp_func_enum { 1489 dmae_cmd_comp_func_to_src, 1490 dmae_cmd_comp_func_to_dst, 1491 MAX_DMAE_CMD_COMP_FUNC_ENUM 1492 }; 1493 1494 enum dmae_cmd_comp_word_en_enum { 1495 dmae_cmd_comp_word_disabled, 1496 dmae_cmd_comp_word_enabled, 1497 MAX_DMAE_CMD_COMP_WORD_EN_ENUM 1498 }; 1499 1500 enum dmae_cmd_c_dst_enum { 1501 dmae_cmd_c_dst_pcie, 1502 dmae_cmd_c_dst_grc, 1503 MAX_DMAE_CMD_C_DST_ENUM 1504 }; 1505 1506 enum dmae_cmd_dst_enum { 1507 dmae_cmd_dst_none_0, 1508 dmae_cmd_dst_pcie, 1509 dmae_cmd_dst_grc, 1510 dmae_cmd_dst_none_3, 1511 MAX_DMAE_CMD_DST_ENUM 1512 }; 1513 1514 enum dmae_cmd_error_handling_enum { 1515 dmae_cmd_error_handling_send_regular_comp, 1516 dmae_cmd_error_handling_send_comp_with_err, 1517 dmae_cmd_error_handling_dont_send_comp, 1518 MAX_DMAE_CMD_ERROR_HANDLING_ENUM 1519 }; 1520 1521 enum dmae_cmd_src_enum { 1522 dmae_cmd_src_pcie, 1523 dmae_cmd_src_grc, 1524 MAX_DMAE_CMD_SRC_ENUM 1525 }; 1526 1527 struct e4_mstorm_core_conn_ag_ctx { 1528 u8 byte0; 1529 u8 byte1; 1530 u8 flags0; 1531 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 1532 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 1533 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 1534 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 1535 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 1536 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 1537 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 1538 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 1539 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 1540 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 1541 u8 flags1; 1542 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 1543 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 1544 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 1545 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 1546 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 1547 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 1548 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 1549 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3 1550 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 1551 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4 1552 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 1553 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5 1554 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 1555 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6 1556 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 1557 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7 1558 __le16 word0; 1559 __le16 word1; 1560 __le32 reg0; 1561 __le32 reg1; 1562 }; 1563 1564 struct e4_ystorm_core_conn_ag_ctx { 1565 u8 byte0; 1566 u8 byte1; 1567 u8 flags0; 1568 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 1569 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 1570 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 1571 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 1572 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 1573 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 1574 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 1575 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 1576 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 1577 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 1578 u8 flags1; 1579 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 1580 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 1581 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 1582 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 1583 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 1584 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 1585 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 1586 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3 1587 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 1588 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4 1589 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 1590 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5 1591 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 1592 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6 1593 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 1594 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7 1595 u8 byte2; 1596 u8 byte3; 1597 __le16 word0; 1598 __le32 reg0; 1599 __le32 reg1; 1600 __le16 word1; 1601 __le16 word2; 1602 __le16 word3; 1603 __le16 word4; 1604 __le32 reg2; 1605 __le32 reg3; 1606 }; 1607 1608 /* DMAE parameters */ 1609 struct qed_dmae_params { 1610 u32 flags; 1611 /* If QED_DMAE_PARAMS_RW_REPL_SRC flag is set and the 1612 * source is a block of length DMAE_MAX_RW_SIZE and the 1613 * destination is larger, the source block will be duplicated as 1614 * many times as required to fill the destination block. This is 1615 * used mostly to write a zeroed buffer to destination address 1616 * using DMA 1617 */ 1618 #define QED_DMAE_PARAMS_RW_REPL_SRC_MASK 0x1 1619 #define QED_DMAE_PARAMS_RW_REPL_SRC_SHIFT 0 1620 #define QED_DMAE_PARAMS_SRC_VF_VALID_MASK 0x1 1621 #define QED_DMAE_PARAMS_SRC_VF_VALID_SHIFT 1 1622 #define QED_DMAE_PARAMS_DST_VF_VALID_MASK 0x1 1623 #define QED_DMAE_PARAMS_DST_VF_VALID_SHIFT 2 1624 #define QED_DMAE_PARAMS_COMPLETION_DST_MASK 0x1 1625 #define QED_DMAE_PARAMS_COMPLETION_DST_SHIFT 3 1626 #define QED_DMAE_PARAMS_PORT_VALID_MASK 0x1 1627 #define QED_DMAE_PARAMS_PORT_VALID_SHIFT 4 1628 #define QED_DMAE_PARAMS_SRC_PF_VALID_MASK 0x1 1629 #define QED_DMAE_PARAMS_SRC_PF_VALID_SHIFT 5 1630 #define QED_DMAE_PARAMS_DST_PF_VALID_MASK 0x1 1631 #define QED_DMAE_PARAMS_DST_PF_VALID_SHIFT 6 1632 #define QED_DMAE_PARAMS_RESERVED_MASK 0x1FFFFFF 1633 #define QED_DMAE_PARAMS_RESERVED_SHIFT 7 1634 u8 src_vfid; 1635 u8 dst_vfid; 1636 u8 port_id; 1637 u8 src_pfid; 1638 u8 dst_pfid; 1639 u8 reserved1; 1640 __le16 reserved2; 1641 }; 1642 1643 /* IGU cleanup command */ 1644 struct igu_cleanup { 1645 __le32 sb_id_and_flags; 1646 #define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF 1647 #define IGU_CLEANUP_RESERVED0_SHIFT 0 1648 #define IGU_CLEANUP_CLEANUP_SET_MASK 0x1 1649 #define IGU_CLEANUP_CLEANUP_SET_SHIFT 27 1650 #define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7 1651 #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28 1652 #define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1 1653 #define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31 1654 __le32 reserved1; 1655 }; 1656 1657 /* IGU firmware driver command */ 1658 union igu_command { 1659 struct igu_prod_cons_update prod_cons_update; 1660 struct igu_cleanup cleanup; 1661 }; 1662 1663 /* IGU firmware driver command */ 1664 struct igu_command_reg_ctrl { 1665 __le16 opaque_fid; 1666 __le16 igu_command_reg_ctrl_fields; 1667 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF 1668 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0 1669 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7 1670 #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT 12 1671 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1 1672 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15 1673 }; 1674 1675 /* IGU mapping line structure */ 1676 struct igu_mapping_line { 1677 __le32 igu_mapping_line_fields; 1678 #define IGU_MAPPING_LINE_VALID_MASK 0x1 1679 #define IGU_MAPPING_LINE_VALID_SHIFT 0 1680 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF 1681 #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT 1 1682 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF 1683 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9 1684 #define IGU_MAPPING_LINE_PF_VALID_MASK 0x1 1685 #define IGU_MAPPING_LINE_PF_VALID_SHIFT 17 1686 #define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F 1687 #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT 18 1688 #define IGU_MAPPING_LINE_RESERVED_MASK 0xFF 1689 #define IGU_MAPPING_LINE_RESERVED_SHIFT 24 1690 }; 1691 1692 /* IGU MSIX line structure */ 1693 struct igu_msix_vector { 1694 struct regpair address; 1695 __le32 data; 1696 __le32 msix_vector_fields; 1697 #define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1 1698 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0 1699 #define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF 1700 #define IGU_MSIX_VECTOR_RESERVED0_SHIFT 1 1701 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF 1702 #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16 1703 #define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF 1704 #define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24 1705 }; 1706 /* per encapsulation type enabling flags */ 1707 struct prs_reg_encapsulation_type_en { 1708 u8 flags; 1709 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1 1710 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0 1711 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1 1712 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT 1 1713 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1 1714 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT 2 1715 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1 1716 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT 3 1717 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1 1718 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4 1719 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1 1720 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT 5 1721 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3 1722 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT 6 1723 }; 1724 1725 enum pxp_tph_st_hint { 1726 TPH_ST_HINT_BIDIR, 1727 TPH_ST_HINT_REQUESTER, 1728 TPH_ST_HINT_TARGET, 1729 TPH_ST_HINT_TARGET_PRIO, 1730 MAX_PXP_TPH_ST_HINT 1731 }; 1732 1733 /* QM hardware structure of enable bypass credit mask */ 1734 struct qm_rf_bypass_mask { 1735 u8 flags; 1736 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1 1737 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0 1738 #define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1 1739 #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1 1740 #define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1 1741 #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT 2 1742 #define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1 1743 #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT 3 1744 #define QM_RF_BYPASS_MASK_PFRL_MASK 0x1 1745 #define QM_RF_BYPASS_MASK_PFRL_SHIFT 4 1746 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1 1747 #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT 5 1748 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1 1749 #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT 6 1750 #define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1 1751 #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7 1752 }; 1753 1754 /* QM hardware structure of opportunistic credit mask */ 1755 struct qm_rf_opportunistic_mask { 1756 __le16 flags; 1757 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1 1758 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0 1759 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1 1760 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT 1 1761 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1 1762 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT 2 1763 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1 1764 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT 3 1765 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1 1766 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT 4 1767 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1 1768 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT 5 1769 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1 1770 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT 6 1771 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1 1772 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT 7 1773 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1 1774 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8 1775 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F 1776 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT 9 1777 }; 1778 1779 /* QM hardware structure of QM map memory */ 1780 struct qm_rf_pq_map_e4 { 1781 __le32 reg; 1782 #define QM_RF_PQ_MAP_E4_PQ_VALID_MASK 0x1 1783 #define QM_RF_PQ_MAP_E4_PQ_VALID_SHIFT 0 1784 #define QM_RF_PQ_MAP_E4_RL_ID_MASK 0xFF 1785 #define QM_RF_PQ_MAP_E4_RL_ID_SHIFT 1 1786 #define QM_RF_PQ_MAP_E4_VP_PQ_ID_MASK 0x1FF 1787 #define QM_RF_PQ_MAP_E4_VP_PQ_ID_SHIFT 9 1788 #define QM_RF_PQ_MAP_E4_VOQ_MASK 0x1F 1789 #define QM_RF_PQ_MAP_E4_VOQ_SHIFT 18 1790 #define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_MASK 0x3 1791 #define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_SHIFT 23 1792 #define QM_RF_PQ_MAP_E4_RL_VALID_MASK 0x1 1793 #define QM_RF_PQ_MAP_E4_RL_VALID_SHIFT 25 1794 #define QM_RF_PQ_MAP_E4_RESERVED_MASK 0x3F 1795 #define QM_RF_PQ_MAP_E4_RESERVED_SHIFT 26 1796 }; 1797 1798 /* Completion params for aggregated interrupt completion */ 1799 struct sdm_agg_int_comp_params { 1800 __le16 params; 1801 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F 1802 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0 1803 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1 1804 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6 1805 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF 1806 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT 7 1807 }; 1808 1809 /* SDM operation gen command (generate aggregative interrupt) */ 1810 struct sdm_op_gen { 1811 __le32 command; 1812 #define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF 1813 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0 1814 #define SDM_OP_GEN_COMP_TYPE_MASK 0xF 1815 #define SDM_OP_GEN_COMP_TYPE_SHIFT 16 1816 #define SDM_OP_GEN_RESERVED_MASK 0xFFF 1817 #define SDM_OP_GEN_RESERVED_SHIFT 20 1818 }; 1819 1820 /* Physical memory descriptor */ 1821 struct phys_mem_desc { 1822 dma_addr_t phys_addr; 1823 void *virt_addr; 1824 u32 size; /* In bytes */ 1825 }; 1826 1827 /* Virtual memory descriptor */ 1828 struct virt_mem_desc { 1829 void *ptr; 1830 u32 size; /* In bytes */ 1831 }; 1832 1833 /****************************************/ 1834 /* Debug Tools HSI constants and macros */ 1835 /****************************************/ 1836 1837 enum block_id { 1838 BLOCK_GRC, 1839 BLOCK_MISCS, 1840 BLOCK_MISC, 1841 BLOCK_DBU, 1842 BLOCK_PGLUE_B, 1843 BLOCK_CNIG, 1844 BLOCK_CPMU, 1845 BLOCK_NCSI, 1846 BLOCK_OPTE, 1847 BLOCK_BMB, 1848 BLOCK_PCIE, 1849 BLOCK_MCP, 1850 BLOCK_MCP2, 1851 BLOCK_PSWHST, 1852 BLOCK_PSWHST2, 1853 BLOCK_PSWRD, 1854 BLOCK_PSWRD2, 1855 BLOCK_PSWWR, 1856 BLOCK_PSWWR2, 1857 BLOCK_PSWRQ, 1858 BLOCK_PSWRQ2, 1859 BLOCK_PGLCS, 1860 BLOCK_DMAE, 1861 BLOCK_PTU, 1862 BLOCK_TCM, 1863 BLOCK_MCM, 1864 BLOCK_UCM, 1865 BLOCK_XCM, 1866 BLOCK_YCM, 1867 BLOCK_PCM, 1868 BLOCK_QM, 1869 BLOCK_TM, 1870 BLOCK_DORQ, 1871 BLOCK_BRB, 1872 BLOCK_SRC, 1873 BLOCK_PRS, 1874 BLOCK_TSDM, 1875 BLOCK_MSDM, 1876 BLOCK_USDM, 1877 BLOCK_XSDM, 1878 BLOCK_YSDM, 1879 BLOCK_PSDM, 1880 BLOCK_TSEM, 1881 BLOCK_MSEM, 1882 BLOCK_USEM, 1883 BLOCK_XSEM, 1884 BLOCK_YSEM, 1885 BLOCK_PSEM, 1886 BLOCK_RSS, 1887 BLOCK_TMLD, 1888 BLOCK_MULD, 1889 BLOCK_YULD, 1890 BLOCK_XYLD, 1891 BLOCK_PRM, 1892 BLOCK_PBF_PB1, 1893 BLOCK_PBF_PB2, 1894 BLOCK_RPB, 1895 BLOCK_BTB, 1896 BLOCK_PBF, 1897 BLOCK_RDIF, 1898 BLOCK_TDIF, 1899 BLOCK_CDU, 1900 BLOCK_CCFC, 1901 BLOCK_TCFC, 1902 BLOCK_IGU, 1903 BLOCK_CAU, 1904 BLOCK_UMAC, 1905 BLOCK_XMAC, 1906 BLOCK_MSTAT, 1907 BLOCK_DBG, 1908 BLOCK_NIG, 1909 BLOCK_WOL, 1910 BLOCK_BMBN, 1911 BLOCK_IPC, 1912 BLOCK_NWM, 1913 BLOCK_NWS, 1914 BLOCK_MS, 1915 BLOCK_PHY_PCIE, 1916 BLOCK_LED, 1917 BLOCK_AVS_WRAP, 1918 BLOCK_PXPREQBUS, 1919 BLOCK_BAR0_MAP, 1920 BLOCK_MCP_FIO, 1921 BLOCK_LAST_INIT, 1922 BLOCK_PRS_FC, 1923 BLOCK_PBF_FC, 1924 BLOCK_NIG_LB_FC, 1925 BLOCK_NIG_LB_FC_PLLH, 1926 BLOCK_NIG_TX_FC_PLLH, 1927 BLOCK_NIG_TX_FC, 1928 BLOCK_NIG_RX_FC_PLLH, 1929 BLOCK_NIG_RX_FC, 1930 MAX_BLOCK_ID 1931 }; 1932 1933 /* binary debug buffer types */ 1934 enum bin_dbg_buffer_type { 1935 BIN_BUF_DBG_MODE_TREE, 1936 BIN_BUF_DBG_DUMP_REG, 1937 BIN_BUF_DBG_DUMP_MEM, 1938 BIN_BUF_DBG_IDLE_CHK_REGS, 1939 BIN_BUF_DBG_IDLE_CHK_IMMS, 1940 BIN_BUF_DBG_IDLE_CHK_RULES, 1941 BIN_BUF_DBG_IDLE_CHK_PARSING_DATA, 1942 BIN_BUF_DBG_ATTN_BLOCKS, 1943 BIN_BUF_DBG_ATTN_REGS, 1944 BIN_BUF_DBG_ATTN_INDEXES, 1945 BIN_BUF_DBG_ATTN_NAME_OFFSETS, 1946 BIN_BUF_DBG_BLOCKS, 1947 BIN_BUF_DBG_BLOCKS_CHIP_DATA, 1948 BIN_BUF_DBG_BUS_LINES, 1949 BIN_BUF_DBG_BLOCKS_USER_DATA, 1950 BIN_BUF_DBG_BLOCKS_CHIP_USER_DATA, 1951 BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS, 1952 BIN_BUF_DBG_RESET_REGS, 1953 BIN_BUF_DBG_PARSING_STRINGS, 1954 MAX_BIN_DBG_BUFFER_TYPE 1955 }; 1956 1957 1958 /* Attention bit mapping */ 1959 struct dbg_attn_bit_mapping { 1960 u16 data; 1961 #define DBG_ATTN_BIT_MAPPING_VAL_MASK 0x7FFF 1962 #define DBG_ATTN_BIT_MAPPING_VAL_SHIFT 0 1963 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK 0x1 1964 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT 15 1965 }; 1966 1967 /* Attention block per-type data */ 1968 struct dbg_attn_block_type_data { 1969 u16 names_offset; 1970 u16 reserved1; 1971 u8 num_regs; 1972 u8 reserved2; 1973 u16 regs_offset; 1974 1975 }; 1976 1977 /* Block attentions */ 1978 struct dbg_attn_block { 1979 struct dbg_attn_block_type_data per_type_data[2]; 1980 }; 1981 1982 /* Attention register result */ 1983 struct dbg_attn_reg_result { 1984 u32 data; 1985 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK 0xFFFFFF 1986 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT 0 1987 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK 0xFF 1988 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_SHIFT 24 1989 u16 block_attn_offset; 1990 u16 reserved; 1991 u32 sts_val; 1992 u32 mask_val; 1993 }; 1994 1995 /* Attention block result */ 1996 struct dbg_attn_block_result { 1997 u8 block_id; 1998 u8 data; 1999 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK 0x3 2000 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT 0 2001 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK 0x3F 2002 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT 2 2003 u16 names_offset; 2004 struct dbg_attn_reg_result reg_results[15]; 2005 }; 2006 2007 /* Mode header */ 2008 struct dbg_mode_hdr { 2009 u16 data; 2010 #define DBG_MODE_HDR_EVAL_MODE_MASK 0x1 2011 #define DBG_MODE_HDR_EVAL_MODE_SHIFT 0 2012 #define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK 0x7FFF 2013 #define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT 1 2014 }; 2015 2016 /* Attention register */ 2017 struct dbg_attn_reg { 2018 struct dbg_mode_hdr mode; 2019 u16 block_attn_offset; 2020 u32 data; 2021 #define DBG_ATTN_REG_STS_ADDRESS_MASK 0xFFFFFF 2022 #define DBG_ATTN_REG_STS_ADDRESS_SHIFT 0 2023 #define DBG_ATTN_REG_NUM_REG_ATTN_MASK 0xFF 2024 #define DBG_ATTN_REG_NUM_REG_ATTN_SHIFT 24 2025 u32 sts_clr_address; 2026 u32 mask_address; 2027 }; 2028 2029 /* Attention types */ 2030 enum dbg_attn_type { 2031 ATTN_TYPE_INTERRUPT, 2032 ATTN_TYPE_PARITY, 2033 MAX_DBG_ATTN_TYPE 2034 }; 2035 2036 /* Block debug data */ 2037 struct dbg_block { 2038 u8 name[15]; 2039 u8 associated_storm_letter; 2040 }; 2041 2042 /* Chip-specific block debug data */ 2043 struct dbg_block_chip { 2044 u8 flags; 2045 #define DBG_BLOCK_CHIP_IS_REMOVED_MASK 0x1 2046 #define DBG_BLOCK_CHIP_IS_REMOVED_SHIFT 0 2047 #define DBG_BLOCK_CHIP_HAS_RESET_REG_MASK 0x1 2048 #define DBG_BLOCK_CHIP_HAS_RESET_REG_SHIFT 1 2049 #define DBG_BLOCK_CHIP_UNRESET_BEFORE_DUMP_MASK 0x1 2050 #define DBG_BLOCK_CHIP_UNRESET_BEFORE_DUMP_SHIFT 2 2051 #define DBG_BLOCK_CHIP_HAS_DBG_BUS_MASK 0x1 2052 #define DBG_BLOCK_CHIP_HAS_DBG_BUS_SHIFT 3 2053 #define DBG_BLOCK_CHIP_HAS_LATENCY_EVENTS_MASK 0x1 2054 #define DBG_BLOCK_CHIP_HAS_LATENCY_EVENTS_SHIFT 4 2055 #define DBG_BLOCK_CHIP_RESERVED0_MASK 0x7 2056 #define DBG_BLOCK_CHIP_RESERVED0_SHIFT 5 2057 u8 dbg_client_id; 2058 u8 reset_reg_id; 2059 u8 reset_reg_bit_offset; 2060 struct dbg_mode_hdr dbg_bus_mode; 2061 u16 reserved1; 2062 u8 reserved2; 2063 u8 num_of_dbg_bus_lines; 2064 u16 dbg_bus_lines_offset; 2065 u32 dbg_select_reg_addr; 2066 u32 dbg_dword_enable_reg_addr; 2067 u32 dbg_shift_reg_addr; 2068 u32 dbg_force_valid_reg_addr; 2069 u32 dbg_force_frame_reg_addr; 2070 }; 2071 2072 /* Chip-specific block user debug data */ 2073 struct dbg_block_chip_user { 2074 u8 num_of_dbg_bus_lines; 2075 u8 has_latency_events; 2076 u16 names_offset; 2077 }; 2078 2079 /* Block user debug data */ 2080 struct dbg_block_user { 2081 u8 name[16]; 2082 }; 2083 2084 /* Block Debug line data */ 2085 struct dbg_bus_line { 2086 u8 data; 2087 #define DBG_BUS_LINE_NUM_OF_GROUPS_MASK 0xF 2088 #define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT 0 2089 #define DBG_BUS_LINE_IS_256B_MASK 0x1 2090 #define DBG_BUS_LINE_IS_256B_SHIFT 4 2091 #define DBG_BUS_LINE_RESERVED_MASK 0x7 2092 #define DBG_BUS_LINE_RESERVED_SHIFT 5 2093 u8 group_sizes; 2094 }; 2095 2096 /* Condition header for registers dump */ 2097 struct dbg_dump_cond_hdr { 2098 struct dbg_mode_hdr mode; /* Mode header */ 2099 u8 block_id; /* block ID */ 2100 u8 data_size; /* size in dwords of the data following this header */ 2101 }; 2102 2103 /* Memory data for registers dump */ 2104 struct dbg_dump_mem { 2105 u32 dword0; 2106 #define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF 2107 #define DBG_DUMP_MEM_ADDRESS_SHIFT 0 2108 #define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF 2109 #define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24 2110 u32 dword1; 2111 #define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF 2112 #define DBG_DUMP_MEM_LENGTH_SHIFT 0 2113 #define DBG_DUMP_MEM_WIDE_BUS_MASK 0x1 2114 #define DBG_DUMP_MEM_WIDE_BUS_SHIFT 24 2115 #define DBG_DUMP_MEM_RESERVED_MASK 0x7F 2116 #define DBG_DUMP_MEM_RESERVED_SHIFT 25 2117 }; 2118 2119 /* Register data for registers dump */ 2120 struct dbg_dump_reg { 2121 u32 data; 2122 #define DBG_DUMP_REG_ADDRESS_MASK 0x7FFFFF 2123 #define DBG_DUMP_REG_ADDRESS_SHIFT 0 2124 #define DBG_DUMP_REG_WIDE_BUS_MASK 0x1 2125 #define DBG_DUMP_REG_WIDE_BUS_SHIFT 23 2126 #define DBG_DUMP_REG_LENGTH_MASK 0xFF 2127 #define DBG_DUMP_REG_LENGTH_SHIFT 24 2128 }; 2129 2130 /* Split header for registers dump */ 2131 struct dbg_dump_split_hdr { 2132 u32 hdr; 2133 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF 2134 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0 2135 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF 2136 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24 2137 }; 2138 2139 /* Condition header for idle check */ 2140 struct dbg_idle_chk_cond_hdr { 2141 struct dbg_mode_hdr mode; /* Mode header */ 2142 u16 data_size; /* size in dwords of the data following this header */ 2143 }; 2144 2145 /* Idle Check condition register */ 2146 struct dbg_idle_chk_cond_reg { 2147 u32 data; 2148 #define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0x7FFFFF 2149 #define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0 2150 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK 0x1 2151 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT 23 2152 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF 2153 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24 2154 u16 num_entries; 2155 u8 entry_size; 2156 u8 start_entry; 2157 }; 2158 2159 /* Idle Check info register */ 2160 struct dbg_idle_chk_info_reg { 2161 u32 data; 2162 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0x7FFFFF 2163 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0 2164 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK 0x1 2165 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT 23 2166 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF 2167 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24 2168 u16 size; /* register size in dwords */ 2169 struct dbg_mode_hdr mode; /* Mode header */ 2170 }; 2171 2172 /* Idle Check register */ 2173 union dbg_idle_chk_reg { 2174 struct dbg_idle_chk_cond_reg cond_reg; /* condition register */ 2175 struct dbg_idle_chk_info_reg info_reg; /* info register */ 2176 }; 2177 2178 /* Idle Check result header */ 2179 struct dbg_idle_chk_result_hdr { 2180 u16 rule_id; /* Failing rule index */ 2181 u16 mem_entry_id; /* Failing memory entry index */ 2182 u8 num_dumped_cond_regs; /* number of dumped condition registers */ 2183 u8 num_dumped_info_regs; /* number of dumped condition registers */ 2184 u8 severity; /* from dbg_idle_chk_severity_types enum */ 2185 u8 reserved; 2186 }; 2187 2188 /* Idle Check result register header */ 2189 struct dbg_idle_chk_result_reg_hdr { 2190 u8 data; 2191 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK 0x1 2192 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0 2193 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK 0x7F 2194 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1 2195 u8 start_entry; /* index of the first checked entry */ 2196 u16 size; /* register size in dwords */ 2197 }; 2198 2199 /* Idle Check rule */ 2200 struct dbg_idle_chk_rule { 2201 u16 rule_id; /* Idle Check rule ID */ 2202 u8 severity; /* value from dbg_idle_chk_severity_types enum */ 2203 u8 cond_id; /* Condition ID */ 2204 u8 num_cond_regs; /* number of condition registers */ 2205 u8 num_info_regs; /* number of info registers */ 2206 u8 num_imms; /* number of immediates in the condition */ 2207 u8 reserved1; 2208 u16 reg_offset; /* offset of this rules registers in the idle check 2209 * register array (in dbg_idle_chk_reg units). 2210 */ 2211 u16 imm_offset; /* offset of this rules immediate values in the 2212 * immediate values array (in dwords). 2213 */ 2214 }; 2215 2216 /* Idle Check rule parsing data */ 2217 struct dbg_idle_chk_rule_parsing_data { 2218 u32 data; 2219 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1 2220 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0 2221 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF 2222 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1 2223 }; 2224 2225 /* Idle check severity types */ 2226 enum dbg_idle_chk_severity_types { 2227 /* idle check failure should cause an error */ 2228 IDLE_CHK_SEVERITY_ERROR, 2229 /* idle check failure should cause an error only if theres no traffic */ 2230 IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC, 2231 /* idle check failure should cause a warning */ 2232 IDLE_CHK_SEVERITY_WARNING, 2233 MAX_DBG_IDLE_CHK_SEVERITY_TYPES 2234 }; 2235 2236 /* Reset register */ 2237 struct dbg_reset_reg { 2238 u32 data; 2239 #define DBG_RESET_REG_ADDR_MASK 0xFFFFFF 2240 #define DBG_RESET_REG_ADDR_SHIFT 0 2241 #define DBG_RESET_REG_IS_REMOVED_MASK 0x1 2242 #define DBG_RESET_REG_IS_REMOVED_SHIFT 24 2243 #define DBG_RESET_REG_RESERVED_MASK 0x7F 2244 #define DBG_RESET_REG_RESERVED_SHIFT 25 2245 }; 2246 2247 /* Debug Bus block data */ 2248 struct dbg_bus_block_data { 2249 u8 enable_mask; 2250 u8 right_shift; 2251 u8 force_valid_mask; 2252 u8 force_frame_mask; 2253 u8 dword_mask; 2254 u8 line_num; 2255 u8 hw_id; 2256 u8 flags; 2257 #define DBG_BUS_BLOCK_DATA_IS_256B_LINE_MASK 0x1 2258 #define DBG_BUS_BLOCK_DATA_IS_256B_LINE_SHIFT 0 2259 #define DBG_BUS_BLOCK_DATA_RESERVED_MASK 0x7F 2260 #define DBG_BUS_BLOCK_DATA_RESERVED_SHIFT 1 2261 }; 2262 2263 enum dbg_bus_clients { 2264 DBG_BUS_CLIENT_RBCN, 2265 DBG_BUS_CLIENT_RBCP, 2266 DBG_BUS_CLIENT_RBCR, 2267 DBG_BUS_CLIENT_RBCT, 2268 DBG_BUS_CLIENT_RBCU, 2269 DBG_BUS_CLIENT_RBCF, 2270 DBG_BUS_CLIENT_RBCX, 2271 DBG_BUS_CLIENT_RBCS, 2272 DBG_BUS_CLIENT_RBCH, 2273 DBG_BUS_CLIENT_RBCZ, 2274 DBG_BUS_CLIENT_OTHER_ENGINE, 2275 DBG_BUS_CLIENT_TIMESTAMP, 2276 DBG_BUS_CLIENT_CPU, 2277 DBG_BUS_CLIENT_RBCY, 2278 DBG_BUS_CLIENT_RBCQ, 2279 DBG_BUS_CLIENT_RBCM, 2280 DBG_BUS_CLIENT_RBCB, 2281 DBG_BUS_CLIENT_RBCW, 2282 DBG_BUS_CLIENT_RBCV, 2283 MAX_DBG_BUS_CLIENTS 2284 }; 2285 2286 /* Debug Bus constraint operation types */ 2287 enum dbg_bus_constraint_ops { 2288 DBG_BUS_CONSTRAINT_OP_EQ, 2289 DBG_BUS_CONSTRAINT_OP_NE, 2290 DBG_BUS_CONSTRAINT_OP_LT, 2291 DBG_BUS_CONSTRAINT_OP_LTC, 2292 DBG_BUS_CONSTRAINT_OP_LE, 2293 DBG_BUS_CONSTRAINT_OP_LEC, 2294 DBG_BUS_CONSTRAINT_OP_GT, 2295 DBG_BUS_CONSTRAINT_OP_GTC, 2296 DBG_BUS_CONSTRAINT_OP_GE, 2297 DBG_BUS_CONSTRAINT_OP_GEC, 2298 MAX_DBG_BUS_CONSTRAINT_OPS 2299 }; 2300 2301 /* Debug Bus trigger state data */ 2302 struct dbg_bus_trigger_state_data { 2303 u8 msg_len; 2304 u8 constraint_dword_mask; 2305 u8 storm_id; 2306 u8 reserved; 2307 }; 2308 2309 /* Debug Bus memory address */ 2310 struct dbg_bus_mem_addr { 2311 u32 lo; 2312 u32 hi; 2313 }; 2314 2315 /* Debug Bus PCI buffer data */ 2316 struct dbg_bus_pci_buf_data { 2317 struct dbg_bus_mem_addr phys_addr; /* PCI buffer physical address */ 2318 struct dbg_bus_mem_addr virt_addr; /* PCI buffer virtual address */ 2319 u32 size; /* PCI buffer size in bytes */ 2320 }; 2321 2322 /* Debug Bus Storm EID range filter params */ 2323 struct dbg_bus_storm_eid_range_params { 2324 u8 min; /* Minimal event ID to filter on */ 2325 u8 max; /* Maximal event ID to filter on */ 2326 }; 2327 2328 /* Debug Bus Storm EID mask filter params */ 2329 struct dbg_bus_storm_eid_mask_params { 2330 u8 val; /* Event ID value */ 2331 u8 mask; /* Event ID mask. 1s in the mask = dont care bits. */ 2332 }; 2333 2334 /* Debug Bus Storm EID filter params */ 2335 union dbg_bus_storm_eid_params { 2336 struct dbg_bus_storm_eid_range_params range; 2337 struct dbg_bus_storm_eid_mask_params mask; 2338 }; 2339 2340 /* Debug Bus Storm data */ 2341 struct dbg_bus_storm_data { 2342 u8 enabled; 2343 u8 mode; 2344 u8 hw_id; 2345 u8 eid_filter_en; 2346 u8 eid_range_not_mask; 2347 u8 cid_filter_en; 2348 union dbg_bus_storm_eid_params eid_filter_params; 2349 u32 cid; 2350 }; 2351 2352 /* Debug Bus data */ 2353 struct dbg_bus_data { 2354 u32 app_version; 2355 u8 state; 2356 u8 mode_256b_en; 2357 u8 num_enabled_blocks; 2358 u8 num_enabled_storms; 2359 u8 target; 2360 u8 one_shot_en; 2361 u8 grc_input_en; 2362 u8 timestamp_input_en; 2363 u8 filter_en; 2364 u8 adding_filter; 2365 u8 filter_pre_trigger; 2366 u8 filter_post_trigger; 2367 u8 trigger_en; 2368 u8 filter_constraint_dword_mask; 2369 u8 next_trigger_state; 2370 u8 next_constraint_id; 2371 struct dbg_bus_trigger_state_data trigger_states[3]; 2372 u8 filter_msg_len; 2373 u8 rcv_from_other_engine; 2374 u8 blocks_dword_mask; 2375 u8 blocks_dword_overlap; 2376 u32 hw_id_mask; 2377 struct dbg_bus_pci_buf_data pci_buf; 2378 struct dbg_bus_block_data blocks[132]; 2379 struct dbg_bus_storm_data storms[6]; 2380 }; 2381 2382 /* Debug bus states */ 2383 enum dbg_bus_states { 2384 DBG_BUS_STATE_IDLE, 2385 DBG_BUS_STATE_READY, 2386 DBG_BUS_STATE_RECORDING, 2387 DBG_BUS_STATE_STOPPED, 2388 MAX_DBG_BUS_STATES 2389 }; 2390 2391 /* Debug Bus Storm modes */ 2392 enum dbg_bus_storm_modes { 2393 DBG_BUS_STORM_MODE_PRINTF, 2394 DBG_BUS_STORM_MODE_PRAM_ADDR, 2395 DBG_BUS_STORM_MODE_DRA_RW, 2396 DBG_BUS_STORM_MODE_DRA_W, 2397 DBG_BUS_STORM_MODE_LD_ST_ADDR, 2398 DBG_BUS_STORM_MODE_DRA_FSM, 2399 DBG_BUS_STORM_MODE_FAST_DBGMUX, 2400 DBG_BUS_STORM_MODE_RH, 2401 DBG_BUS_STORM_MODE_RH_WITH_STORE, 2402 DBG_BUS_STORM_MODE_FOC, 2403 DBG_BUS_STORM_MODE_EXT_STORE, 2404 MAX_DBG_BUS_STORM_MODES 2405 }; 2406 2407 /* Debug bus target IDs */ 2408 enum dbg_bus_targets { 2409 DBG_BUS_TARGET_ID_INT_BUF, 2410 DBG_BUS_TARGET_ID_NIG, 2411 DBG_BUS_TARGET_ID_PCI, 2412 MAX_DBG_BUS_TARGETS 2413 }; 2414 2415 /* GRC Dump data */ 2416 struct dbg_grc_data { 2417 u8 params_initialized; 2418 u8 reserved1; 2419 u16 reserved2; 2420 u32 param_val[48]; 2421 }; 2422 2423 /* Debug GRC params */ 2424 enum dbg_grc_params { 2425 DBG_GRC_PARAM_DUMP_TSTORM, 2426 DBG_GRC_PARAM_DUMP_MSTORM, 2427 DBG_GRC_PARAM_DUMP_USTORM, 2428 DBG_GRC_PARAM_DUMP_XSTORM, 2429 DBG_GRC_PARAM_DUMP_YSTORM, 2430 DBG_GRC_PARAM_DUMP_PSTORM, 2431 DBG_GRC_PARAM_DUMP_REGS, 2432 DBG_GRC_PARAM_DUMP_RAM, 2433 DBG_GRC_PARAM_DUMP_PBUF, 2434 DBG_GRC_PARAM_DUMP_IOR, 2435 DBG_GRC_PARAM_DUMP_VFC, 2436 DBG_GRC_PARAM_DUMP_CM_CTX, 2437 DBG_GRC_PARAM_DUMP_PXP, 2438 DBG_GRC_PARAM_DUMP_RSS, 2439 DBG_GRC_PARAM_DUMP_CAU, 2440 DBG_GRC_PARAM_DUMP_QM, 2441 DBG_GRC_PARAM_DUMP_MCP, 2442 DBG_GRC_PARAM_DUMP_DORQ, 2443 DBG_GRC_PARAM_DUMP_CFC, 2444 DBG_GRC_PARAM_DUMP_IGU, 2445 DBG_GRC_PARAM_DUMP_BRB, 2446 DBG_GRC_PARAM_DUMP_BTB, 2447 DBG_GRC_PARAM_DUMP_BMB, 2448 DBG_GRC_PARAM_RESERVD1, 2449 DBG_GRC_PARAM_DUMP_MULD, 2450 DBG_GRC_PARAM_DUMP_PRS, 2451 DBG_GRC_PARAM_DUMP_DMAE, 2452 DBG_GRC_PARAM_DUMP_TM, 2453 DBG_GRC_PARAM_DUMP_SDM, 2454 DBG_GRC_PARAM_DUMP_DIF, 2455 DBG_GRC_PARAM_DUMP_STATIC, 2456 DBG_GRC_PARAM_UNSTALL, 2457 DBG_GRC_PARAM_RESERVED2, 2458 DBG_GRC_PARAM_MCP_TRACE_META_SIZE, 2459 DBG_GRC_PARAM_EXCLUDE_ALL, 2460 DBG_GRC_PARAM_CRASH, 2461 DBG_GRC_PARAM_PARITY_SAFE, 2462 DBG_GRC_PARAM_DUMP_CM, 2463 DBG_GRC_PARAM_DUMP_PHY, 2464 DBG_GRC_PARAM_NO_MCP, 2465 DBG_GRC_PARAM_NO_FW_VER, 2466 DBG_GRC_PARAM_RESERVED3, 2467 DBG_GRC_PARAM_DUMP_MCP_HW_DUMP, 2468 DBG_GRC_PARAM_DUMP_ILT_CDUC, 2469 DBG_GRC_PARAM_DUMP_ILT_CDUT, 2470 DBG_GRC_PARAM_DUMP_CAU_EXT, 2471 MAX_DBG_GRC_PARAMS 2472 }; 2473 2474 /* Debug status codes */ 2475 enum dbg_status { 2476 DBG_STATUS_OK, 2477 DBG_STATUS_APP_VERSION_NOT_SET, 2478 DBG_STATUS_UNSUPPORTED_APP_VERSION, 2479 DBG_STATUS_DBG_BLOCK_NOT_RESET, 2480 DBG_STATUS_INVALID_ARGS, 2481 DBG_STATUS_OUTPUT_ALREADY_SET, 2482 DBG_STATUS_INVALID_PCI_BUF_SIZE, 2483 DBG_STATUS_PCI_BUF_ALLOC_FAILED, 2484 DBG_STATUS_PCI_BUF_NOT_ALLOCATED, 2485 DBG_STATUS_INVALID_FILTER_TRIGGER_DWORDS, 2486 DBG_STATUS_NO_MATCHING_FRAMING_MODE, 2487 DBG_STATUS_VFC_READ_ERROR, 2488 DBG_STATUS_STORM_ALREADY_ENABLED, 2489 DBG_STATUS_STORM_NOT_ENABLED, 2490 DBG_STATUS_BLOCK_ALREADY_ENABLED, 2491 DBG_STATUS_BLOCK_NOT_ENABLED, 2492 DBG_STATUS_NO_INPUT_ENABLED, 2493 DBG_STATUS_NO_FILTER_TRIGGER_256B, 2494 DBG_STATUS_FILTER_ALREADY_ENABLED, 2495 DBG_STATUS_TRIGGER_ALREADY_ENABLED, 2496 DBG_STATUS_TRIGGER_NOT_ENABLED, 2497 DBG_STATUS_CANT_ADD_CONSTRAINT, 2498 DBG_STATUS_TOO_MANY_TRIGGER_STATES, 2499 DBG_STATUS_TOO_MANY_CONSTRAINTS, 2500 DBG_STATUS_RECORDING_NOT_STARTED, 2501 DBG_STATUS_DATA_DIDNT_TRIGGER, 2502 DBG_STATUS_NO_DATA_RECORDED, 2503 DBG_STATUS_DUMP_BUF_TOO_SMALL, 2504 DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED, 2505 DBG_STATUS_UNKNOWN_CHIP, 2506 DBG_STATUS_VIRT_MEM_ALLOC_FAILED, 2507 DBG_STATUS_BLOCK_IN_RESET, 2508 DBG_STATUS_INVALID_TRACE_SIGNATURE, 2509 DBG_STATUS_INVALID_NVRAM_BUNDLE, 2510 DBG_STATUS_NVRAM_GET_IMAGE_FAILED, 2511 DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE, 2512 DBG_STATUS_NVRAM_READ_FAILED, 2513 DBG_STATUS_IDLE_CHK_PARSE_FAILED, 2514 DBG_STATUS_MCP_TRACE_BAD_DATA, 2515 DBG_STATUS_MCP_TRACE_NO_META, 2516 DBG_STATUS_MCP_COULD_NOT_HALT, 2517 DBG_STATUS_MCP_COULD_NOT_RESUME, 2518 DBG_STATUS_RESERVED0, 2519 DBG_STATUS_SEMI_FIFO_NOT_EMPTY, 2520 DBG_STATUS_IGU_FIFO_BAD_DATA, 2521 DBG_STATUS_MCP_COULD_NOT_MASK_PRTY, 2522 DBG_STATUS_FW_ASSERTS_PARSE_FAILED, 2523 DBG_STATUS_REG_FIFO_BAD_DATA, 2524 DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA, 2525 DBG_STATUS_DBG_ARRAY_NOT_SET, 2526 DBG_STATUS_RESERVED1, 2527 DBG_STATUS_NON_MATCHING_LINES, 2528 DBG_STATUS_INSUFFICIENT_HW_IDS, 2529 DBG_STATUS_DBG_BUS_IN_USE, 2530 DBG_STATUS_INVALID_STORM_DBG_MODE, 2531 DBG_STATUS_OTHER_ENGINE_BB_ONLY, 2532 DBG_STATUS_FILTER_SINGLE_HW_ID, 2533 DBG_STATUS_TRIGGER_SINGLE_HW_ID, 2534 DBG_STATUS_MISSING_TRIGGER_STATE_STORM, 2535 MAX_DBG_STATUS 2536 }; 2537 2538 /* Debug Storms IDs */ 2539 enum dbg_storms { 2540 DBG_TSTORM_ID, 2541 DBG_MSTORM_ID, 2542 DBG_USTORM_ID, 2543 DBG_XSTORM_ID, 2544 DBG_YSTORM_ID, 2545 DBG_PSTORM_ID, 2546 MAX_DBG_STORMS 2547 }; 2548 2549 /* Idle Check data */ 2550 struct idle_chk_data { 2551 u32 buf_size; 2552 u8 buf_size_set; 2553 u8 reserved1; 2554 u16 reserved2; 2555 }; 2556 2557 struct pretend_params { 2558 u8 split_type; 2559 u8 reserved; 2560 u16 split_id; 2561 }; 2562 2563 /* Debug Tools data (per HW function) 2564 */ 2565 struct dbg_tools_data { 2566 struct dbg_grc_data grc; 2567 struct dbg_bus_data bus; 2568 struct idle_chk_data idle_chk; 2569 u8 mode_enable[40]; 2570 u8 block_in_reset[132]; 2571 u8 chip_id; 2572 u8 hw_type; 2573 u8 num_ports; 2574 u8 num_pfs_per_port; 2575 u8 num_vfs; 2576 u8 initialized; 2577 u8 use_dmae; 2578 u8 reserved; 2579 struct pretend_params pretend; 2580 u32 num_regs_read; 2581 }; 2582 2583 /* ILT Clients */ 2584 enum ilt_clients { 2585 ILT_CLI_CDUC, 2586 ILT_CLI_CDUT, 2587 ILT_CLI_QM, 2588 ILT_CLI_TM, 2589 ILT_CLI_SRC, 2590 ILT_CLI_TSDM, 2591 ILT_CLI_RGFS, 2592 ILT_CLI_TGFS, 2593 MAX_ILT_CLIENTS 2594 }; 2595 2596 /********************************/ 2597 /* HSI Init Functions constants */ 2598 /********************************/ 2599 2600 /* Number of VLAN priorities */ 2601 #define NUM_OF_VLAN_PRIORITIES 8 2602 2603 /* BRB RAM init requirements */ 2604 struct init_brb_ram_req { 2605 u32 guranteed_per_tc; 2606 u32 headroom_per_tc; 2607 u32 min_pkt_size; 2608 u32 max_ports_per_engine; 2609 u8 num_active_tcs[MAX_NUM_PORTS]; 2610 }; 2611 2612 /* ETS per-TC init requirements */ 2613 struct init_ets_tc_req { 2614 u8 use_sp; 2615 u8 use_wfq; 2616 u16 weight; 2617 }; 2618 2619 /* ETS init requirements */ 2620 struct init_ets_req { 2621 u32 mtu; 2622 struct init_ets_tc_req tc_req[NUM_OF_TCS]; 2623 }; 2624 2625 /* NIG LB RL init requirements */ 2626 struct init_nig_lb_rl_req { 2627 u16 lb_mac_rate; 2628 u16 lb_rate; 2629 u32 mtu; 2630 u16 tc_rate[NUM_OF_PHYS_TCS]; 2631 }; 2632 2633 /* NIG TC mapping for each priority */ 2634 struct init_nig_pri_tc_map_entry { 2635 u8 tc_id; 2636 u8 valid; 2637 }; 2638 2639 /* NIG priority to TC map init requirements */ 2640 struct init_nig_pri_tc_map_req { 2641 struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES]; 2642 }; 2643 2644 /* QM per global RL init parameters */ 2645 struct init_qm_global_rl_params { 2646 u32 rate_limit; 2647 }; 2648 2649 /* QM per-port init parameters */ 2650 struct init_qm_port_params { 2651 u16 active_phys_tcs; 2652 u16 num_pbf_cmd_lines; 2653 u16 num_btb_blocks; 2654 u8 active; 2655 u8 reserved; 2656 }; 2657 2658 /* QM per-PQ init parameters */ 2659 struct init_qm_pq_params { 2660 u8 vport_id; 2661 u8 tc_id; 2662 u8 wrr_group; 2663 u8 rl_valid; 2664 u16 rl_id; 2665 u8 port_id; 2666 u8 reserved; 2667 }; 2668 2669 /* QM per-vport init parameters */ 2670 struct init_qm_vport_params { 2671 u16 wfq; 2672 u16 first_tx_pq_id[NUM_OF_TCS]; 2673 }; 2674 2675 /**************************************/ 2676 /* Init Tool HSI constants and macros */ 2677 /**************************************/ 2678 2679 /* Width of GRC address in bits (addresses are specified in dwords) */ 2680 #define GRC_ADDR_BITS 23 2681 #define MAX_GRC_ADDR (BIT(GRC_ADDR_BITS) - 1) 2682 2683 /* indicates an init that should be applied to any phase ID */ 2684 #define ANY_PHASE_ID 0xffff 2685 2686 /* Max size in dwords of a zipped array */ 2687 #define MAX_ZIPPED_SIZE 8192 2688 enum chip_ids { 2689 CHIP_BB, 2690 CHIP_K2, 2691 MAX_CHIP_IDS 2692 }; 2693 2694 struct fw_asserts_ram_section { 2695 __le16 section_ram_line_offset; 2696 __le16 section_ram_line_size; 2697 u8 list_dword_offset; 2698 u8 list_element_dword_size; 2699 u8 list_num_elements; 2700 u8 list_next_index_dword_offset; 2701 }; 2702 2703 struct fw_ver_num { 2704 u8 major; 2705 u8 minor; 2706 u8 rev; 2707 u8 eng; 2708 }; 2709 2710 struct fw_ver_info { 2711 __le16 tools_ver; 2712 u8 image_id; 2713 u8 reserved1; 2714 struct fw_ver_num num; 2715 __le32 timestamp; 2716 __le32 reserved2; 2717 }; 2718 2719 struct fw_info { 2720 struct fw_ver_info ver; 2721 struct fw_asserts_ram_section fw_asserts_section; 2722 }; 2723 2724 struct fw_info_location { 2725 __le32 grc_addr; 2726 __le32 size; 2727 }; 2728 2729 enum init_modes { 2730 MODE_RESERVED, 2731 MODE_BB, 2732 MODE_K2, 2733 MODE_ASIC, 2734 MODE_RESERVED2, 2735 MODE_RESERVED3, 2736 MODE_RESERVED4, 2737 MODE_RESERVED5, 2738 MODE_SF, 2739 MODE_MF_SD, 2740 MODE_MF_SI, 2741 MODE_PORTS_PER_ENG_1, 2742 MODE_PORTS_PER_ENG_2, 2743 MODE_PORTS_PER_ENG_4, 2744 MODE_100G, 2745 MODE_RESERVED6, 2746 MODE_RESERVED7, 2747 MAX_INIT_MODES 2748 }; 2749 2750 enum init_phases { 2751 PHASE_ENGINE, 2752 PHASE_PORT, 2753 PHASE_PF, 2754 PHASE_VF, 2755 PHASE_QM_PF, 2756 MAX_INIT_PHASES 2757 }; 2758 2759 enum init_split_types { 2760 SPLIT_TYPE_NONE, 2761 SPLIT_TYPE_PORT, 2762 SPLIT_TYPE_PF, 2763 SPLIT_TYPE_PORT_PF, 2764 SPLIT_TYPE_VF, 2765 MAX_INIT_SPLIT_TYPES 2766 }; 2767 2768 /* Binary buffer header */ 2769 struct bin_buffer_hdr { 2770 u32 offset; 2771 u32 length; 2772 }; 2773 2774 /* Binary init buffer types */ 2775 enum bin_init_buffer_type { 2776 BIN_BUF_INIT_FW_VER_INFO, 2777 BIN_BUF_INIT_CMD, 2778 BIN_BUF_INIT_VAL, 2779 BIN_BUF_INIT_MODE_TREE, 2780 BIN_BUF_INIT_IRO, 2781 BIN_BUF_INIT_OVERLAYS, 2782 MAX_BIN_INIT_BUFFER_TYPE 2783 }; 2784 2785 /* FW overlay buffer header */ 2786 struct fw_overlay_buf_hdr { 2787 u32 data; 2788 #define FW_OVERLAY_BUF_HDR_STORM_ID_MASK 0xFF 2789 #define FW_OVERLAY_BUF_HDR_STORM_ID_SHIFT 0 2790 #define FW_OVERLAY_BUF_HDR_BUF_SIZE_MASK 0xFFFFFF 2791 #define FW_OVERLAY_BUF_HDR_BUF_SIZE_SHIFT 8 2792 }; 2793 2794 /* init array header: raw */ 2795 struct init_array_raw_hdr { 2796 u32 data; 2797 #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF 2798 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0 2799 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF 2800 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4 2801 }; 2802 2803 /* init array header: standard */ 2804 struct init_array_standard_hdr { 2805 u32 data; 2806 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF 2807 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0 2808 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF 2809 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4 2810 }; 2811 2812 /* init array header: zipped */ 2813 struct init_array_zipped_hdr { 2814 u32 data; 2815 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF 2816 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0 2817 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF 2818 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4 2819 }; 2820 2821 /* init array header: pattern */ 2822 struct init_array_pattern_hdr { 2823 u32 data; 2824 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF 2825 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0 2826 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF 2827 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4 2828 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF 2829 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8 2830 }; 2831 2832 /* init array header union */ 2833 union init_array_hdr { 2834 struct init_array_raw_hdr raw; 2835 struct init_array_standard_hdr standard; 2836 struct init_array_zipped_hdr zipped; 2837 struct init_array_pattern_hdr pattern; 2838 }; 2839 2840 /* init array types */ 2841 enum init_array_types { 2842 INIT_ARR_STANDARD, 2843 INIT_ARR_ZIPPED, 2844 INIT_ARR_PATTERN, 2845 MAX_INIT_ARRAY_TYPES 2846 }; 2847 2848 /* init operation: callback */ 2849 struct init_callback_op { 2850 u32 op_data; 2851 #define INIT_CALLBACK_OP_OP_MASK 0xF 2852 #define INIT_CALLBACK_OP_OP_SHIFT 0 2853 #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF 2854 #define INIT_CALLBACK_OP_RESERVED_SHIFT 4 2855 u16 callback_id; 2856 u16 block_id; 2857 }; 2858 2859 /* init operation: delay */ 2860 struct init_delay_op { 2861 u32 op_data; 2862 #define INIT_DELAY_OP_OP_MASK 0xF 2863 #define INIT_DELAY_OP_OP_SHIFT 0 2864 #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF 2865 #define INIT_DELAY_OP_RESERVED_SHIFT 4 2866 u32 delay; 2867 }; 2868 2869 /* init operation: if_mode */ 2870 struct init_if_mode_op { 2871 u32 op_data; 2872 #define INIT_IF_MODE_OP_OP_MASK 0xF 2873 #define INIT_IF_MODE_OP_OP_SHIFT 0 2874 #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF 2875 #define INIT_IF_MODE_OP_RESERVED1_SHIFT 4 2876 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF 2877 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16 2878 u16 reserved2; 2879 u16 modes_buf_offset; 2880 }; 2881 2882 /* init operation: if_phase */ 2883 struct init_if_phase_op { 2884 u32 op_data; 2885 #define INIT_IF_PHASE_OP_OP_MASK 0xF 2886 #define INIT_IF_PHASE_OP_OP_SHIFT 0 2887 #define INIT_IF_PHASE_OP_RESERVED1_MASK 0xFFF 2888 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT 4 2889 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF 2890 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16 2891 u32 phase_data; 2892 #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF 2893 #define INIT_IF_PHASE_OP_PHASE_SHIFT 0 2894 #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF 2895 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8 2896 #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF 2897 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16 2898 }; 2899 2900 /* init mode operators */ 2901 enum init_mode_ops { 2902 INIT_MODE_OP_NOT, 2903 INIT_MODE_OP_OR, 2904 INIT_MODE_OP_AND, 2905 MAX_INIT_MODE_OPS 2906 }; 2907 2908 /* init operation: raw */ 2909 struct init_raw_op { 2910 u32 op_data; 2911 #define INIT_RAW_OP_OP_MASK 0xF 2912 #define INIT_RAW_OP_OP_SHIFT 0 2913 #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF 2914 #define INIT_RAW_OP_PARAM1_SHIFT 4 2915 u32 param2; 2916 }; 2917 2918 /* init array params */ 2919 struct init_op_array_params { 2920 u16 size; 2921 u16 offset; 2922 }; 2923 2924 /* Write init operation arguments */ 2925 union init_write_args { 2926 u32 inline_val; 2927 u32 zeros_count; 2928 u32 array_offset; 2929 struct init_op_array_params runtime; 2930 }; 2931 2932 /* init operation: write */ 2933 struct init_write_op { 2934 u32 data; 2935 #define INIT_WRITE_OP_OP_MASK 0xF 2936 #define INIT_WRITE_OP_OP_SHIFT 0 2937 #define INIT_WRITE_OP_SOURCE_MASK 0x7 2938 #define INIT_WRITE_OP_SOURCE_SHIFT 4 2939 #define INIT_WRITE_OP_RESERVED_MASK 0x1 2940 #define INIT_WRITE_OP_RESERVED_SHIFT 7 2941 #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1 2942 #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8 2943 #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF 2944 #define INIT_WRITE_OP_ADDRESS_SHIFT 9 2945 union init_write_args args; 2946 }; 2947 2948 /* init operation: read */ 2949 struct init_read_op { 2950 u32 op_data; 2951 #define INIT_READ_OP_OP_MASK 0xF 2952 #define INIT_READ_OP_OP_SHIFT 0 2953 #define INIT_READ_OP_POLL_TYPE_MASK 0xF 2954 #define INIT_READ_OP_POLL_TYPE_SHIFT 4 2955 #define INIT_READ_OP_RESERVED_MASK 0x1 2956 #define INIT_READ_OP_RESERVED_SHIFT 8 2957 #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF 2958 #define INIT_READ_OP_ADDRESS_SHIFT 9 2959 u32 expected_val; 2960 }; 2961 2962 /* Init operations union */ 2963 union init_op { 2964 struct init_raw_op raw; 2965 struct init_write_op write; 2966 struct init_read_op read; 2967 struct init_if_mode_op if_mode; 2968 struct init_if_phase_op if_phase; 2969 struct init_callback_op callback; 2970 struct init_delay_op delay; 2971 }; 2972 2973 /* Init command operation types */ 2974 enum init_op_types { 2975 INIT_OP_READ, 2976 INIT_OP_WRITE, 2977 INIT_OP_IF_MODE, 2978 INIT_OP_IF_PHASE, 2979 INIT_OP_DELAY, 2980 INIT_OP_CALLBACK, 2981 MAX_INIT_OP_TYPES 2982 }; 2983 2984 /* init polling types */ 2985 enum init_poll_types { 2986 INIT_POLL_NONE, 2987 INIT_POLL_EQ, 2988 INIT_POLL_OR, 2989 INIT_POLL_AND, 2990 MAX_INIT_POLL_TYPES 2991 }; 2992 2993 /* init source types */ 2994 enum init_source_types { 2995 INIT_SRC_INLINE, 2996 INIT_SRC_ZEROS, 2997 INIT_SRC_ARRAY, 2998 INIT_SRC_RUNTIME, 2999 MAX_INIT_SOURCE_TYPES 3000 }; 3001 3002 /* Internal RAM Offsets macro data */ 3003 struct iro { 3004 u32 base; 3005 u16 m1; 3006 u16 m2; 3007 u16 m3; 3008 u16 size; 3009 }; 3010 3011 /***************************** Public Functions *******************************/ 3012 3013 /** 3014 * @brief qed_dbg_set_bin_ptr - Sets a pointer to the binary data with debug 3015 * arrays. 3016 * 3017 * @param p_hwfn - HW device data 3018 * @param bin_ptr - a pointer to the binary data with debug arrays. 3019 */ 3020 enum dbg_status qed_dbg_set_bin_ptr(struct qed_hwfn *p_hwfn, 3021 const u8 * const bin_ptr); 3022 3023 /** 3024 * @brief qed_read_regs - Reads registers into a buffer (using GRC). 3025 * 3026 * @param p_hwfn - HW device data 3027 * @param p_ptt - Ptt window used for writing the registers. 3028 * @param buf - Destination buffer. 3029 * @param addr - Source GRC address in dwords. 3030 * @param len - Number of registers to read. 3031 */ 3032 void qed_read_regs(struct qed_hwfn *p_hwfn, 3033 struct qed_ptt *p_ptt, u32 *buf, u32 addr, u32 len); 3034 3035 /** 3036 * @brief qed_read_fw_info - Reads FW info from the chip. 3037 * 3038 * The FW info contains FW-related information, such as the FW version, 3039 * FW image (main/L2B/kuku), FW timestamp, etc. 3040 * The FW info is read from the internal RAM of the first Storm that is not in 3041 * reset. 3042 * 3043 * @param p_hwfn - HW device data 3044 * @param p_ptt - Ptt window used for writing the registers. 3045 * @param fw_info - Out: a pointer to write the FW info into. 3046 * 3047 * @return true if the FW info was read successfully from one of the Storms, 3048 * or false if all Storms are in reset. 3049 */ 3050 bool qed_read_fw_info(struct qed_hwfn *p_hwfn, 3051 struct qed_ptt *p_ptt, struct fw_info *fw_info); 3052 /** 3053 * @brief qed_dbg_grc_config - Sets the value of a GRC parameter. 3054 * 3055 * @param p_hwfn - HW device data 3056 * @param grc_param - GRC parameter 3057 * @param val - Value to set. 3058 * 3059 * @return error if one of the following holds: 3060 * - the version wasn't set 3061 * - grc_param is invalid 3062 * - val is outside the allowed boundaries 3063 */ 3064 enum dbg_status qed_dbg_grc_config(struct qed_hwfn *p_hwfn, 3065 enum dbg_grc_params grc_param, u32 val); 3066 3067 /** 3068 * @brief qed_dbg_grc_set_params_default - Reverts all GRC parameters to their 3069 * default value. 3070 * 3071 * @param p_hwfn - HW device data 3072 */ 3073 void qed_dbg_grc_set_params_default(struct qed_hwfn *p_hwfn); 3074 /** 3075 * @brief qed_dbg_grc_get_dump_buf_size - Returns the required buffer size for 3076 * GRC Dump. 3077 * 3078 * @param p_hwfn - HW device data 3079 * @param p_ptt - Ptt window used for writing the registers. 3080 * @param buf_size - OUT: required buffer size (in dwords) for the GRC Dump 3081 * data. 3082 * 3083 * @return error if one of the following holds: 3084 * - the version wasn't set 3085 * Otherwise, returns ok. 3086 */ 3087 enum dbg_status qed_dbg_grc_get_dump_buf_size(struct qed_hwfn *p_hwfn, 3088 struct qed_ptt *p_ptt, 3089 u32 *buf_size); 3090 3091 /** 3092 * @brief qed_dbg_grc_dump - Dumps GRC data into the specified buffer. 3093 * 3094 * @param p_hwfn - HW device data 3095 * @param p_ptt - Ptt window used for writing the registers. 3096 * @param dump_buf - Pointer to write the collected GRC data into. 3097 * @param buf_size_in_dwords - Size of the specified buffer in dwords. 3098 * @param num_dumped_dwords - OUT: number of dumped dwords. 3099 * 3100 * @return error if one of the following holds: 3101 * - the version wasn't set 3102 * - the specified dump buffer is too small 3103 * Otherwise, returns ok. 3104 */ 3105 enum dbg_status qed_dbg_grc_dump(struct qed_hwfn *p_hwfn, 3106 struct qed_ptt *p_ptt, 3107 u32 *dump_buf, 3108 u32 buf_size_in_dwords, 3109 u32 *num_dumped_dwords); 3110 3111 /** 3112 * @brief qed_dbg_idle_chk_get_dump_buf_size - Returns the required buffer size 3113 * for idle check results. 3114 * 3115 * @param p_hwfn - HW device data 3116 * @param p_ptt - Ptt window used for writing the registers. 3117 * @param buf_size - OUT: required buffer size (in dwords) for the idle check 3118 * data. 3119 * 3120 * @return error if one of the following holds: 3121 * - the version wasn't set 3122 * Otherwise, returns ok. 3123 */ 3124 enum dbg_status qed_dbg_idle_chk_get_dump_buf_size(struct qed_hwfn *p_hwfn, 3125 struct qed_ptt *p_ptt, 3126 u32 *buf_size); 3127 3128 /** 3129 * @brief qed_dbg_idle_chk_dump - Performs idle check and writes the results 3130 * into the specified buffer. 3131 * 3132 * @param p_hwfn - HW device data 3133 * @param p_ptt - Ptt window used for writing the registers. 3134 * @param dump_buf - Pointer to write the idle check data into. 3135 * @param buf_size_in_dwords - Size of the specified buffer in dwords. 3136 * @param num_dumped_dwords - OUT: number of dumped dwords. 3137 * 3138 * @return error if one of the following holds: 3139 * - the version wasn't set 3140 * - the specified buffer is too small 3141 * Otherwise, returns ok. 3142 */ 3143 enum dbg_status qed_dbg_idle_chk_dump(struct qed_hwfn *p_hwfn, 3144 struct qed_ptt *p_ptt, 3145 u32 *dump_buf, 3146 u32 buf_size_in_dwords, 3147 u32 *num_dumped_dwords); 3148 3149 /** 3150 * @brief qed_dbg_mcp_trace_get_dump_buf_size - Returns the required buffer size 3151 * for mcp trace results. 3152 * 3153 * @param p_hwfn - HW device data 3154 * @param p_ptt - Ptt window used for writing the registers. 3155 * @param buf_size - OUT: required buffer size (in dwords) for mcp trace data. 3156 * 3157 * @return error if one of the following holds: 3158 * - the version wasn't set 3159 * - the trace data in MCP scratchpad contain an invalid signature 3160 * - the bundle ID in NVRAM is invalid 3161 * - the trace meta data cannot be found (in NVRAM or image file) 3162 * Otherwise, returns ok. 3163 */ 3164 enum dbg_status qed_dbg_mcp_trace_get_dump_buf_size(struct qed_hwfn *p_hwfn, 3165 struct qed_ptt *p_ptt, 3166 u32 *buf_size); 3167 3168 /** 3169 * @brief qed_dbg_mcp_trace_dump - Performs mcp trace and writes the results 3170 * into the specified buffer. 3171 * 3172 * @param p_hwfn - HW device data 3173 * @param p_ptt - Ptt window used for writing the registers. 3174 * @param dump_buf - Pointer to write the mcp trace data into. 3175 * @param buf_size_in_dwords - Size of the specified buffer in dwords. 3176 * @param num_dumped_dwords - OUT: number of dumped dwords. 3177 * 3178 * @return error if one of the following holds: 3179 * - the version wasn't set 3180 * - the specified buffer is too small 3181 * - the trace data in MCP scratchpad contain an invalid signature 3182 * - the bundle ID in NVRAM is invalid 3183 * - the trace meta data cannot be found (in NVRAM or image file) 3184 * - the trace meta data cannot be read (from NVRAM or image file) 3185 * Otherwise, returns ok. 3186 */ 3187 enum dbg_status qed_dbg_mcp_trace_dump(struct qed_hwfn *p_hwfn, 3188 struct qed_ptt *p_ptt, 3189 u32 *dump_buf, 3190 u32 buf_size_in_dwords, 3191 u32 *num_dumped_dwords); 3192 3193 /** 3194 * @brief qed_dbg_reg_fifo_get_dump_buf_size - Returns the required buffer size 3195 * for grc trace fifo results. 3196 * 3197 * @param p_hwfn - HW device data 3198 * @param p_ptt - Ptt window used for writing the registers. 3199 * @param buf_size - OUT: required buffer size (in dwords) for reg fifo data. 3200 * 3201 * @return error if one of the following holds: 3202 * - the version wasn't set 3203 * Otherwise, returns ok. 3204 */ 3205 enum dbg_status qed_dbg_reg_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn, 3206 struct qed_ptt *p_ptt, 3207 u32 *buf_size); 3208 3209 /** 3210 * @brief qed_dbg_reg_fifo_dump - Reads the reg fifo and writes the results into 3211 * the specified buffer. 3212 * 3213 * @param p_hwfn - HW device data 3214 * @param p_ptt - Ptt window used for writing the registers. 3215 * @param dump_buf - Pointer to write the reg fifo data into. 3216 * @param buf_size_in_dwords - Size of the specified buffer in dwords. 3217 * @param num_dumped_dwords - OUT: number of dumped dwords. 3218 * 3219 * @return error if one of the following holds: 3220 * - the version wasn't set 3221 * - the specified buffer is too small 3222 * - DMAE transaction failed 3223 * Otherwise, returns ok. 3224 */ 3225 enum dbg_status qed_dbg_reg_fifo_dump(struct qed_hwfn *p_hwfn, 3226 struct qed_ptt *p_ptt, 3227 u32 *dump_buf, 3228 u32 buf_size_in_dwords, 3229 u32 *num_dumped_dwords); 3230 3231 /** 3232 * @brief qed_dbg_igu_fifo_get_dump_buf_size - Returns the required buffer size 3233 * for the IGU fifo results. 3234 * 3235 * @param p_hwfn - HW device data 3236 * @param p_ptt - Ptt window used for writing the registers. 3237 * @param buf_size - OUT: required buffer size (in dwords) for the IGU fifo 3238 * data. 3239 * 3240 * @return error if one of the following holds: 3241 * - the version wasn't set 3242 * Otherwise, returns ok. 3243 */ 3244 enum dbg_status qed_dbg_igu_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn, 3245 struct qed_ptt *p_ptt, 3246 u32 *buf_size); 3247 3248 /** 3249 * @brief qed_dbg_igu_fifo_dump - Reads the IGU fifo and writes the results into 3250 * the specified buffer. 3251 * 3252 * @param p_hwfn - HW device data 3253 * @param p_ptt - Ptt window used for writing the registers. 3254 * @param dump_buf - Pointer to write the IGU fifo data into. 3255 * @param buf_size_in_dwords - Size of the specified buffer in dwords. 3256 * @param num_dumped_dwords - OUT: number of dumped dwords. 3257 * 3258 * @return error if one of the following holds: 3259 * - the version wasn't set 3260 * - the specified buffer is too small 3261 * - DMAE transaction failed 3262 * Otherwise, returns ok. 3263 */ 3264 enum dbg_status qed_dbg_igu_fifo_dump(struct qed_hwfn *p_hwfn, 3265 struct qed_ptt *p_ptt, 3266 u32 *dump_buf, 3267 u32 buf_size_in_dwords, 3268 u32 *num_dumped_dwords); 3269 3270 /** 3271 * @brief qed_dbg_protection_override_get_dump_buf_size - Returns the required 3272 * buffer size for protection override window results. 3273 * 3274 * @param p_hwfn - HW device data 3275 * @param p_ptt - Ptt window used for writing the registers. 3276 * @param buf_size - OUT: required buffer size (in dwords) for protection 3277 * override data. 3278 * 3279 * @return error if one of the following holds: 3280 * - the version wasn't set 3281 * Otherwise, returns ok. 3282 */ 3283 enum dbg_status 3284 qed_dbg_protection_override_get_dump_buf_size(struct qed_hwfn *p_hwfn, 3285 struct qed_ptt *p_ptt, 3286 u32 *buf_size); 3287 /** 3288 * @brief qed_dbg_protection_override_dump - Reads protection override window 3289 * entries and writes the results into the specified buffer. 3290 * 3291 * @param p_hwfn - HW device data 3292 * @param p_ptt - Ptt window used for writing the registers. 3293 * @param dump_buf - Pointer to write the protection override data into. 3294 * @param buf_size_in_dwords - Size of the specified buffer in dwords. 3295 * @param num_dumped_dwords - OUT: number of dumped dwords. 3296 * 3297 * @return error if one of the following holds: 3298 * - the version wasn't set 3299 * - the specified buffer is too small 3300 * - DMAE transaction failed 3301 * Otherwise, returns ok. 3302 */ 3303 enum dbg_status qed_dbg_protection_override_dump(struct qed_hwfn *p_hwfn, 3304 struct qed_ptt *p_ptt, 3305 u32 *dump_buf, 3306 u32 buf_size_in_dwords, 3307 u32 *num_dumped_dwords); 3308 /** 3309 * @brief qed_dbg_fw_asserts_get_dump_buf_size - Returns the required buffer 3310 * size for FW Asserts results. 3311 * 3312 * @param p_hwfn - HW device data 3313 * @param p_ptt - Ptt window used for writing the registers. 3314 * @param buf_size - OUT: required buffer size (in dwords) for FW Asserts data. 3315 * 3316 * @return error if one of the following holds: 3317 * - the version wasn't set 3318 * Otherwise, returns ok. 3319 */ 3320 enum dbg_status qed_dbg_fw_asserts_get_dump_buf_size(struct qed_hwfn *p_hwfn, 3321 struct qed_ptt *p_ptt, 3322 u32 *buf_size); 3323 /** 3324 * @brief qed_dbg_fw_asserts_dump - Reads the FW Asserts and writes the results 3325 * into the specified buffer. 3326 * 3327 * @param p_hwfn - HW device data 3328 * @param p_ptt - Ptt window used for writing the registers. 3329 * @param dump_buf - Pointer to write the FW Asserts data into. 3330 * @param buf_size_in_dwords - Size of the specified buffer in dwords. 3331 * @param num_dumped_dwords - OUT: number of dumped dwords. 3332 * 3333 * @return error if one of the following holds: 3334 * - the version wasn't set 3335 * - the specified buffer is too small 3336 * Otherwise, returns ok. 3337 */ 3338 enum dbg_status qed_dbg_fw_asserts_dump(struct qed_hwfn *p_hwfn, 3339 struct qed_ptt *p_ptt, 3340 u32 *dump_buf, 3341 u32 buf_size_in_dwords, 3342 u32 *num_dumped_dwords); 3343 3344 /** 3345 * @brief qed_dbg_read_attn - Reads the attention registers of the specified 3346 * block and type, and writes the results into the specified buffer. 3347 * 3348 * @param p_hwfn - HW device data 3349 * @param p_ptt - Ptt window used for writing the registers. 3350 * @param block - Block ID. 3351 * @param attn_type - Attention type. 3352 * @param clear_status - Indicates if the attention status should be cleared. 3353 * @param results - OUT: Pointer to write the read results into 3354 * 3355 * @return error if one of the following holds: 3356 * - the version wasn't set 3357 * Otherwise, returns ok. 3358 */ 3359 enum dbg_status qed_dbg_read_attn(struct qed_hwfn *p_hwfn, 3360 struct qed_ptt *p_ptt, 3361 enum block_id block, 3362 enum dbg_attn_type attn_type, 3363 bool clear_status, 3364 struct dbg_attn_block_result *results); 3365 3366 /** 3367 * @brief qed_dbg_print_attn - Prints attention registers values in the 3368 * specified results struct. 3369 * 3370 * @param p_hwfn 3371 * @param results - Pointer to the attention read results 3372 * 3373 * @return error if one of the following holds: 3374 * - the version wasn't set 3375 * Otherwise, returns ok. 3376 */ 3377 enum dbg_status qed_dbg_print_attn(struct qed_hwfn *p_hwfn, 3378 struct dbg_attn_block_result *results); 3379 3380 /******************************* Data Types **********************************/ 3381 3382 struct mcp_trace_format { 3383 u32 data; 3384 #define MCP_TRACE_FORMAT_MODULE_MASK 0x0000ffff 3385 #define MCP_TRACE_FORMAT_MODULE_OFFSET 0 3386 #define MCP_TRACE_FORMAT_LEVEL_MASK 0x00030000 3387 #define MCP_TRACE_FORMAT_LEVEL_OFFSET 16 3388 #define MCP_TRACE_FORMAT_P1_SIZE_MASK 0x000c0000 3389 #define MCP_TRACE_FORMAT_P1_SIZE_OFFSET 18 3390 #define MCP_TRACE_FORMAT_P2_SIZE_MASK 0x00300000 3391 #define MCP_TRACE_FORMAT_P2_SIZE_OFFSET 20 3392 #define MCP_TRACE_FORMAT_P3_SIZE_MASK 0x00c00000 3393 #define MCP_TRACE_FORMAT_P3_SIZE_OFFSET 22 3394 #define MCP_TRACE_FORMAT_LEN_MASK 0xff000000 3395 #define MCP_TRACE_FORMAT_LEN_OFFSET 24 3396 3397 char *format_str; 3398 }; 3399 3400 /* MCP Trace Meta data structure */ 3401 struct mcp_trace_meta { 3402 u32 modules_num; 3403 char **modules; 3404 u32 formats_num; 3405 struct mcp_trace_format *formats; 3406 bool is_allocated; 3407 }; 3408 3409 /* Debug Tools user data */ 3410 struct dbg_tools_user_data { 3411 struct mcp_trace_meta mcp_trace_meta; 3412 const u32 *mcp_trace_user_meta_buf; 3413 }; 3414 3415 /******************************** Constants **********************************/ 3416 3417 #define MAX_NAME_LEN 16 3418 3419 /***************************** Public Functions *******************************/ 3420 3421 /** 3422 * @brief qed_dbg_user_set_bin_ptr - Sets a pointer to the binary data with 3423 * debug arrays. 3424 * 3425 * @param p_hwfn - HW device data 3426 * @param bin_ptr - a pointer to the binary data with debug arrays. 3427 */ 3428 enum dbg_status qed_dbg_user_set_bin_ptr(struct qed_hwfn *p_hwfn, 3429 const u8 * const bin_ptr); 3430 3431 /** 3432 * @brief qed_dbg_alloc_user_data - Allocates user debug data. 3433 * 3434 * @param p_hwfn - HW device data 3435 * @param user_data_ptr - OUT: a pointer to the allocated memory. 3436 */ 3437 enum dbg_status qed_dbg_alloc_user_data(struct qed_hwfn *p_hwfn, 3438 void **user_data_ptr); 3439 3440 /** 3441 * @brief qed_dbg_get_status_str - Returns a string for the specified status. 3442 * 3443 * @param status - a debug status code. 3444 * 3445 * @return a string for the specified status 3446 */ 3447 const char *qed_dbg_get_status_str(enum dbg_status status); 3448 3449 /** 3450 * @brief qed_get_idle_chk_results_buf_size - Returns the required buffer size 3451 * for idle check results (in bytes). 3452 * 3453 * @param p_hwfn - HW device data 3454 * @param dump_buf - idle check dump buffer. 3455 * @param num_dumped_dwords - number of dwords that were dumped. 3456 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed 3457 * results. 3458 * 3459 * @return error if the parsing fails, ok otherwise. 3460 */ 3461 enum dbg_status qed_get_idle_chk_results_buf_size(struct qed_hwfn *p_hwfn, 3462 u32 *dump_buf, 3463 u32 num_dumped_dwords, 3464 u32 *results_buf_size); 3465 /** 3466 * @brief qed_print_idle_chk_results - Prints idle check results 3467 * 3468 * @param p_hwfn - HW device data 3469 * @param dump_buf - idle check dump buffer. 3470 * @param num_dumped_dwords - number of dwords that were dumped. 3471 * @param results_buf - buffer for printing the idle check results. 3472 * @param num_errors - OUT: number of errors found in idle check. 3473 * @param num_warnings - OUT: number of warnings found in idle check. 3474 * 3475 * @return error if the parsing fails, ok otherwise. 3476 */ 3477 enum dbg_status qed_print_idle_chk_results(struct qed_hwfn *p_hwfn, 3478 u32 *dump_buf, 3479 u32 num_dumped_dwords, 3480 char *results_buf, 3481 u32 *num_errors, 3482 u32 *num_warnings); 3483 3484 /** 3485 * @brief qed_dbg_mcp_trace_set_meta_data - Sets the MCP Trace meta data. 3486 * 3487 * Needed in case the MCP Trace dump doesn't contain the meta data (e.g. due to 3488 * no NVRAM access). 3489 * 3490 * @param data - pointer to MCP Trace meta data 3491 * @param size - size of MCP Trace meta data in dwords 3492 */ 3493 void qed_dbg_mcp_trace_set_meta_data(struct qed_hwfn *p_hwfn, 3494 const u32 *meta_buf); 3495 3496 /** 3497 * @brief qed_get_mcp_trace_results_buf_size - Returns the required buffer size 3498 * for MCP Trace results (in bytes). 3499 * 3500 * @param p_hwfn - HW device data 3501 * @param dump_buf - MCP Trace dump buffer. 3502 * @param num_dumped_dwords - number of dwords that were dumped. 3503 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed 3504 * results. 3505 * 3506 * @return error if the parsing fails, ok otherwise. 3507 */ 3508 enum dbg_status qed_get_mcp_trace_results_buf_size(struct qed_hwfn *p_hwfn, 3509 u32 *dump_buf, 3510 u32 num_dumped_dwords, 3511 u32 *results_buf_size); 3512 3513 /** 3514 * @brief qed_print_mcp_trace_results - Prints MCP Trace results 3515 * 3516 * @param p_hwfn - HW device data 3517 * @param dump_buf - mcp trace dump buffer, starting from the header. 3518 * @param num_dumped_dwords - number of dwords that were dumped. 3519 * @param results_buf - buffer for printing the mcp trace results. 3520 * 3521 * @return error if the parsing fails, ok otherwise. 3522 */ 3523 enum dbg_status qed_print_mcp_trace_results(struct qed_hwfn *p_hwfn, 3524 u32 *dump_buf, 3525 u32 num_dumped_dwords, 3526 char *results_buf); 3527 3528 /** 3529 * @brief qed_print_mcp_trace_results_cont - Prints MCP Trace results, and 3530 * keeps the MCP trace meta data allocated, to support continuous MCP Trace 3531 * parsing. After the continuous parsing ends, mcp_trace_free_meta_data should 3532 * be called to free the meta data. 3533 * 3534 * @param p_hwfn - HW device data 3535 * @param dump_buf - mcp trace dump buffer, starting from the header. 3536 * @param results_buf - buffer for printing the mcp trace results. 3537 * 3538 * @return error if the parsing fails, ok otherwise. 3539 */ 3540 enum dbg_status qed_print_mcp_trace_results_cont(struct qed_hwfn *p_hwfn, 3541 u32 *dump_buf, 3542 char *results_buf); 3543 3544 /** 3545 * @brief print_mcp_trace_line - Prints MCP Trace results for a single line 3546 * 3547 * @param p_hwfn - HW device data 3548 * @param dump_buf - mcp trace dump buffer, starting from the header. 3549 * @param num_dumped_bytes - number of bytes that were dumped. 3550 * @param results_buf - buffer for printing the mcp trace results. 3551 * 3552 * @return error if the parsing fails, ok otherwise. 3553 */ 3554 enum dbg_status qed_print_mcp_trace_line(struct qed_hwfn *p_hwfn, 3555 u8 *dump_buf, 3556 u32 num_dumped_bytes, 3557 char *results_buf); 3558 3559 /** 3560 * @brief mcp_trace_free_meta_data - Frees the MCP Trace meta data. 3561 * Should be called after continuous MCP Trace parsing. 3562 * 3563 * @param p_hwfn - HW device data 3564 */ 3565 void qed_mcp_trace_free_meta_data(struct qed_hwfn *p_hwfn); 3566 3567 /** 3568 * @brief qed_get_reg_fifo_results_buf_size - Returns the required buffer size 3569 * for reg_fifo results (in bytes). 3570 * 3571 * @param p_hwfn - HW device data 3572 * @param dump_buf - reg fifo dump buffer. 3573 * @param num_dumped_dwords - number of dwords that were dumped. 3574 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed 3575 * results. 3576 * 3577 * @return error if the parsing fails, ok otherwise. 3578 */ 3579 enum dbg_status qed_get_reg_fifo_results_buf_size(struct qed_hwfn *p_hwfn, 3580 u32 *dump_buf, 3581 u32 num_dumped_dwords, 3582 u32 *results_buf_size); 3583 3584 /** 3585 * @brief qed_print_reg_fifo_results - Prints reg fifo results 3586 * 3587 * @param p_hwfn - HW device data 3588 * @param dump_buf - reg fifo dump buffer, starting from the header. 3589 * @param num_dumped_dwords - number of dwords that were dumped. 3590 * @param results_buf - buffer for printing the reg fifo results. 3591 * 3592 * @return error if the parsing fails, ok otherwise. 3593 */ 3594 enum dbg_status qed_print_reg_fifo_results(struct qed_hwfn *p_hwfn, 3595 u32 *dump_buf, 3596 u32 num_dumped_dwords, 3597 char *results_buf); 3598 3599 /** 3600 * @brief qed_get_igu_fifo_results_buf_size - Returns the required buffer size 3601 * for igu_fifo results (in bytes). 3602 * 3603 * @param p_hwfn - HW device data 3604 * @param dump_buf - IGU fifo dump buffer. 3605 * @param num_dumped_dwords - number of dwords that were dumped. 3606 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed 3607 * results. 3608 * 3609 * @return error if the parsing fails, ok otherwise. 3610 */ 3611 enum dbg_status qed_get_igu_fifo_results_buf_size(struct qed_hwfn *p_hwfn, 3612 u32 *dump_buf, 3613 u32 num_dumped_dwords, 3614 u32 *results_buf_size); 3615 3616 /** 3617 * @brief qed_print_igu_fifo_results - Prints IGU fifo results 3618 * 3619 * @param p_hwfn - HW device data 3620 * @param dump_buf - IGU fifo dump buffer, starting from the header. 3621 * @param num_dumped_dwords - number of dwords that were dumped. 3622 * @param results_buf - buffer for printing the IGU fifo results. 3623 * 3624 * @return error if the parsing fails, ok otherwise. 3625 */ 3626 enum dbg_status qed_print_igu_fifo_results(struct qed_hwfn *p_hwfn, 3627 u32 *dump_buf, 3628 u32 num_dumped_dwords, 3629 char *results_buf); 3630 3631 /** 3632 * @brief qed_get_protection_override_results_buf_size - Returns the required 3633 * buffer size for protection override results (in bytes). 3634 * 3635 * @param p_hwfn - HW device data 3636 * @param dump_buf - protection override dump buffer. 3637 * @param num_dumped_dwords - number of dwords that were dumped. 3638 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed 3639 * results. 3640 * 3641 * @return error if the parsing fails, ok otherwise. 3642 */ 3643 enum dbg_status 3644 qed_get_protection_override_results_buf_size(struct qed_hwfn *p_hwfn, 3645 u32 *dump_buf, 3646 u32 num_dumped_dwords, 3647 u32 *results_buf_size); 3648 3649 /** 3650 * @brief qed_print_protection_override_results - Prints protection override 3651 * results. 3652 * 3653 * @param p_hwfn - HW device data 3654 * @param dump_buf - protection override dump buffer, starting from the header. 3655 * @param num_dumped_dwords - number of dwords that were dumped. 3656 * @param results_buf - buffer for printing the reg fifo results. 3657 * 3658 * @return error if the parsing fails, ok otherwise. 3659 */ 3660 enum dbg_status qed_print_protection_override_results(struct qed_hwfn *p_hwfn, 3661 u32 *dump_buf, 3662 u32 num_dumped_dwords, 3663 char *results_buf); 3664 3665 /** 3666 * @brief qed_get_fw_asserts_results_buf_size - Returns the required buffer size 3667 * for FW Asserts results (in bytes). 3668 * 3669 * @param p_hwfn - HW device data 3670 * @param dump_buf - FW Asserts dump buffer. 3671 * @param num_dumped_dwords - number of dwords that were dumped. 3672 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed 3673 * results. 3674 * 3675 * @return error if the parsing fails, ok otherwise. 3676 */ 3677 enum dbg_status qed_get_fw_asserts_results_buf_size(struct qed_hwfn *p_hwfn, 3678 u32 *dump_buf, 3679 u32 num_dumped_dwords, 3680 u32 *results_buf_size); 3681 3682 /** 3683 * @brief qed_print_fw_asserts_results - Prints FW Asserts results 3684 * 3685 * @param p_hwfn - HW device data 3686 * @param dump_buf - FW Asserts dump buffer, starting from the header. 3687 * @param num_dumped_dwords - number of dwords that were dumped. 3688 * @param results_buf - buffer for printing the FW Asserts results. 3689 * 3690 * @return error if the parsing fails, ok otherwise. 3691 */ 3692 enum dbg_status qed_print_fw_asserts_results(struct qed_hwfn *p_hwfn, 3693 u32 *dump_buf, 3694 u32 num_dumped_dwords, 3695 char *results_buf); 3696 3697 /** 3698 * @brief qed_dbg_parse_attn - Parses and prints attention registers values in 3699 * the specified results struct. 3700 * 3701 * @param p_hwfn - HW device data 3702 * @param results - Pointer to the attention read results 3703 * 3704 * @return error if one of the following holds: 3705 * - the version wasn't set 3706 * Otherwise, returns ok. 3707 */ 3708 enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn, 3709 struct dbg_attn_block_result *results); 3710 3711 /* Win 2 */ 3712 #define GTT_BAR0_MAP_REG_IGU_CMD 0x00f000UL 3713 3714 /* Win 3 */ 3715 #define GTT_BAR0_MAP_REG_TSDM_RAM 0x010000UL 3716 3717 /* Win 4 */ 3718 #define GTT_BAR0_MAP_REG_MSDM_RAM 0x011000UL 3719 3720 /* Win 5 */ 3721 #define GTT_BAR0_MAP_REG_MSDM_RAM_1024 0x012000UL 3722 3723 /* Win 6 */ 3724 #define GTT_BAR0_MAP_REG_MSDM_RAM_2048 0x013000UL 3725 3726 /* Win 7 */ 3727 #define GTT_BAR0_MAP_REG_USDM_RAM 0x014000UL 3728 3729 /* Win 8 */ 3730 #define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x015000UL 3731 3732 /* Win 9 */ 3733 #define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x016000UL 3734 3735 /* Win 10 */ 3736 #define GTT_BAR0_MAP_REG_XSDM_RAM 0x017000UL 3737 3738 /* Win 11 */ 3739 #define GTT_BAR0_MAP_REG_XSDM_RAM_1024 0x018000UL 3740 3741 /* Win 12 */ 3742 #define GTT_BAR0_MAP_REG_YSDM_RAM 0x019000UL 3743 3744 /* Win 13 */ 3745 #define GTT_BAR0_MAP_REG_PSDM_RAM 0x01a000UL 3746 3747 /** 3748 * @brief qed_qm_pf_mem_size - prepare QM ILT sizes 3749 * 3750 * Returns the required host memory size in 4KB units. 3751 * Must be called before all QM init HSI functions. 3752 * 3753 * @param num_pf_cids - number of connections used by this PF 3754 * @param num_vf_cids - number of connections used by VFs of this PF 3755 * @param num_tids - number of tasks used by this PF 3756 * @param num_pf_pqs - number of PQs used by this PF 3757 * @param num_vf_pqs - number of PQs used by VFs of this PF 3758 * 3759 * @return The required host memory size in 4KB units. 3760 */ 3761 u32 qed_qm_pf_mem_size(u32 num_pf_cids, 3762 u32 num_vf_cids, 3763 u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs); 3764 3765 struct qed_qm_common_rt_init_params { 3766 u8 max_ports_per_engine; 3767 u8 max_phys_tcs_per_port; 3768 bool pf_rl_en; 3769 bool pf_wfq_en; 3770 bool global_rl_en; 3771 bool vport_wfq_en; 3772 struct init_qm_port_params *port_params; 3773 }; 3774 3775 int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn, 3776 struct qed_qm_common_rt_init_params *p_params); 3777 3778 struct qed_qm_pf_rt_init_params { 3779 u8 port_id; 3780 u8 pf_id; 3781 u8 max_phys_tcs_per_port; 3782 bool is_pf_loading; 3783 u32 num_pf_cids; 3784 u32 num_vf_cids; 3785 u32 num_tids; 3786 u16 start_pq; 3787 u16 num_pf_pqs; 3788 u16 num_vf_pqs; 3789 u16 start_vport; 3790 u16 num_vports; 3791 u16 pf_wfq; 3792 u32 pf_rl; 3793 struct init_qm_pq_params *pq_params; 3794 struct init_qm_vport_params *vport_params; 3795 }; 3796 3797 int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn, 3798 struct qed_ptt *p_ptt, 3799 struct qed_qm_pf_rt_init_params *p_params); 3800 3801 /** 3802 * @brief qed_init_pf_wfq - Initializes the WFQ weight of the specified PF 3803 * 3804 * @param p_hwfn 3805 * @param p_ptt - ptt window used for writing the registers 3806 * @param pf_id - PF ID 3807 * @param pf_wfq - WFQ weight. Must be non-zero. 3808 * 3809 * @return 0 on success, -1 on error. 3810 */ 3811 int qed_init_pf_wfq(struct qed_hwfn *p_hwfn, 3812 struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq); 3813 3814 /** 3815 * @brief qed_init_pf_rl - Initializes the rate limit of the specified PF 3816 * 3817 * @param p_hwfn 3818 * @param p_ptt - ptt window used for writing the registers 3819 * @param pf_id - PF ID 3820 * @param pf_rl - rate limit in Mb/sec units 3821 * 3822 * @return 0 on success, -1 on error. 3823 */ 3824 int qed_init_pf_rl(struct qed_hwfn *p_hwfn, 3825 struct qed_ptt *p_ptt, u8 pf_id, u32 pf_rl); 3826 3827 /** 3828 * @brief qed_init_vport_wfq Initializes the WFQ weight of the specified VPORT 3829 * 3830 * @param p_hwfn 3831 * @param p_ptt - ptt window used for writing the registers 3832 * @param first_tx_pq_id- An array containing the first Tx PQ ID associated 3833 * with the VPORT for each TC. This array is filled by 3834 * qed_qm_pf_rt_init 3835 * @param vport_wfq - WFQ weight. Must be non-zero. 3836 * 3837 * @return 0 on success, -1 on error. 3838 */ 3839 int qed_init_vport_wfq(struct qed_hwfn *p_hwfn, 3840 struct qed_ptt *p_ptt, 3841 u16 first_tx_pq_id[NUM_OF_TCS], u16 wfq); 3842 3843 /** 3844 * @brief qed_init_global_rl - Initializes the rate limit of the specified 3845 * rate limiter 3846 * 3847 * @param p_hwfn 3848 * @param p_ptt - ptt window used for writing the registers 3849 * @param rl_id - RL ID 3850 * @param rate_limit - rate limit in Mb/sec units 3851 * 3852 * @return 0 on success, -1 on error. 3853 */ 3854 int qed_init_global_rl(struct qed_hwfn *p_hwfn, 3855 struct qed_ptt *p_ptt, 3856 u16 rl_id, u32 rate_limit); 3857 3858 /** 3859 * @brief qed_send_qm_stop_cmd Sends a stop command to the QM 3860 * 3861 * @param p_hwfn 3862 * @param p_ptt 3863 * @param is_release_cmd - true for release, false for stop. 3864 * @param is_tx_pq - true for Tx PQs, false for Other PQs. 3865 * @param start_pq - first PQ ID to stop 3866 * @param num_pqs - Number of PQs to stop, starting from start_pq. 3867 * 3868 * @return bool, true if successful, false if timeout occurred while waiting for 3869 * QM command done. 3870 */ 3871 bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn, 3872 struct qed_ptt *p_ptt, 3873 bool is_release_cmd, 3874 bool is_tx_pq, u16 start_pq, u16 num_pqs); 3875 3876 /** 3877 * @brief qed_set_vxlan_dest_port - initializes vxlan tunnel destination udp port 3878 * 3879 * @param p_hwfn 3880 * @param p_ptt - ptt window used for writing the registers. 3881 * @param dest_port - vxlan destination udp port. 3882 */ 3883 void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn, 3884 struct qed_ptt *p_ptt, u16 dest_port); 3885 3886 /** 3887 * @brief qed_set_vxlan_enable - enable or disable VXLAN tunnel in HW 3888 * 3889 * @param p_hwfn 3890 * @param p_ptt - ptt window used for writing the registers. 3891 * @param vxlan_enable - vxlan enable flag. 3892 */ 3893 void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn, 3894 struct qed_ptt *p_ptt, bool vxlan_enable); 3895 3896 /** 3897 * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW 3898 * 3899 * @param p_hwfn 3900 * @param p_ptt - ptt window used for writing the registers. 3901 * @param eth_gre_enable - eth GRE enable enable flag. 3902 * @param ip_gre_enable - IP GRE enable enable flag. 3903 */ 3904 void qed_set_gre_enable(struct qed_hwfn *p_hwfn, 3905 struct qed_ptt *p_ptt, 3906 bool eth_gre_enable, bool ip_gre_enable); 3907 3908 /** 3909 * @brief qed_set_geneve_dest_port - initializes geneve tunnel destination udp port 3910 * 3911 * @param p_hwfn 3912 * @param p_ptt - ptt window used for writing the registers. 3913 * @param dest_port - geneve destination udp port. 3914 */ 3915 void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn, 3916 struct qed_ptt *p_ptt, u16 dest_port); 3917 3918 /** 3919 * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW 3920 * 3921 * @param p_ptt - ptt window used for writing the registers. 3922 * @param eth_geneve_enable - eth GENEVE enable enable flag. 3923 * @param ip_geneve_enable - IP GENEVE enable enable flag. 3924 */ 3925 void qed_set_geneve_enable(struct qed_hwfn *p_hwfn, 3926 struct qed_ptt *p_ptt, 3927 bool eth_geneve_enable, bool ip_geneve_enable); 3928 3929 void qed_set_vxlan_no_l2_enable(struct qed_hwfn *p_hwfn, 3930 struct qed_ptt *p_ptt, bool enable); 3931 3932 /** 3933 * @brief qed_gft_disable - Disable GFT 3934 * 3935 * @param p_hwfn 3936 * @param p_ptt - ptt window used for writing the registers. 3937 * @param pf_id - pf on which to disable GFT. 3938 */ 3939 void qed_gft_disable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 pf_id); 3940 3941 /** 3942 * @brief qed_gft_config - Enable and configure HW for GFT 3943 * 3944 * @param p_hwfn - HW device data 3945 * @param p_ptt - ptt window used for writing the registers. 3946 * @param pf_id - pf on which to enable GFT. 3947 * @param tcp - set profile tcp packets. 3948 * @param udp - set profile udp packet. 3949 * @param ipv4 - set profile ipv4 packet. 3950 * @param ipv6 - set profile ipv6 packet. 3951 * @param profile_type - define packet same fields. Use enum gft_profile_type. 3952 */ 3953 void qed_gft_config(struct qed_hwfn *p_hwfn, 3954 struct qed_ptt *p_ptt, 3955 u16 pf_id, 3956 bool tcp, 3957 bool udp, 3958 bool ipv4, bool ipv6, enum gft_profile_type profile_type); 3959 3960 /** 3961 * @brief qed_enable_context_validation - Enable and configure context 3962 * validation. 3963 * 3964 * @param p_hwfn 3965 * @param p_ptt - ptt window used for writing the registers. 3966 */ 3967 void qed_enable_context_validation(struct qed_hwfn *p_hwfn, 3968 struct qed_ptt *p_ptt); 3969 3970 /** 3971 * @brief qed_calc_session_ctx_validation - Calcualte validation byte for 3972 * session context. 3973 * 3974 * @param p_ctx_mem - pointer to context memory. 3975 * @param ctx_size - context size. 3976 * @param ctx_type - context type. 3977 * @param cid - context cid. 3978 */ 3979 void qed_calc_session_ctx_validation(void *p_ctx_mem, 3980 u16 ctx_size, u8 ctx_type, u32 cid); 3981 3982 /** 3983 * @brief qed_calc_task_ctx_validation - Calcualte validation byte for task 3984 * context. 3985 * 3986 * @param p_ctx_mem - pointer to context memory. 3987 * @param ctx_size - context size. 3988 * @param ctx_type - context type. 3989 * @param tid - context tid. 3990 */ 3991 void qed_calc_task_ctx_validation(void *p_ctx_mem, 3992 u16 ctx_size, u8 ctx_type, u32 tid); 3993 3994 /** 3995 * @brief qed_memset_session_ctx - Memset session context to 0 while 3996 * preserving validation bytes. 3997 * 3998 * @param p_hwfn - 3999 * @param p_ctx_mem - pointer to context memory. 4000 * @param ctx_size - size to initialzie. 4001 * @param ctx_type - context type. 4002 */ 4003 void qed_memset_session_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type); 4004 4005 /** 4006 * @brief qed_memset_task_ctx - Memset task context to 0 while preserving 4007 * validation bytes. 4008 * 4009 * @param p_ctx_mem - pointer to context memory. 4010 * @param ctx_size - size to initialzie. 4011 * @param ctx_type - context type. 4012 */ 4013 void qed_memset_task_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type); 4014 4015 #define NUM_STORMS 6 4016 4017 /** 4018 * @brief qed_set_rdma_error_level - Sets the RDMA assert level. 4019 * If the severity of the error will be 4020 * above the level, the FW will assert. 4021 * @param p_hwfn - HW device data 4022 * @param p_ptt - ptt window used for writing the registers 4023 * @param assert_level - An array of assert levels for each storm. 4024 * 4025 */ 4026 void qed_set_rdma_error_level(struct qed_hwfn *p_hwfn, 4027 struct qed_ptt *p_ptt, 4028 u8 assert_level[NUM_STORMS]); 4029 /** 4030 * @brief qed_fw_overlay_mem_alloc - Allocates and fills the FW overlay memory. 4031 * 4032 * @param p_hwfn - HW device data 4033 * @param fw_overlay_in_buf - the input FW overlay buffer. 4034 * @param buf_size - the size of the input FW overlay buffer in bytes. 4035 * must be aligned to dwords. 4036 * @param fw_overlay_out_mem - OUT: a pointer to the allocated overlays memory. 4037 * 4038 * @return a pointer to the allocated overlays memory, 4039 * or NULL in case of failures. 4040 */ 4041 struct phys_mem_desc * 4042 qed_fw_overlay_mem_alloc(struct qed_hwfn *p_hwfn, 4043 const u32 * const fw_overlay_in_buf, 4044 u32 buf_size_in_bytes); 4045 4046 /** 4047 * @brief qed_fw_overlay_init_ram - Initializes the FW overlay RAM. 4048 * 4049 * @param p_hwfn - HW device data. 4050 * @param p_ptt - ptt window used for writing the registers. 4051 * @param fw_overlay_mem - the allocated FW overlay memory. 4052 */ 4053 void qed_fw_overlay_init_ram(struct qed_hwfn *p_hwfn, 4054 struct qed_ptt *p_ptt, 4055 struct phys_mem_desc *fw_overlay_mem); 4056 4057 /** 4058 * @brief qed_fw_overlay_mem_free - Frees the FW overlay memory. 4059 * 4060 * @param p_hwfn - HW device data. 4061 * @param fw_overlay_mem - the allocated FW overlay memory to free. 4062 */ 4063 void qed_fw_overlay_mem_free(struct qed_hwfn *p_hwfn, 4064 struct phys_mem_desc *fw_overlay_mem); 4065 4066 /* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */ 4067 #define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base) 4068 #define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size) 4069 4070 /* Tstorm port statistics */ 4071 #define TSTORM_PORT_STAT_OFFSET(port_id) \ 4072 (IRO[1].base + ((port_id) * IRO[1].m1)) 4073 #define TSTORM_PORT_STAT_SIZE (IRO[1].size) 4074 4075 /* Tstorm ll2 port statistics */ 4076 #define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \ 4077 (IRO[2].base + ((port_id) * IRO[2].m1)) 4078 #define TSTORM_LL2_PORT_STAT_SIZE (IRO[2].size) 4079 4080 /* Ustorm VF-PF Channel ready flag */ 4081 #define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \ 4082 (IRO[3].base + ((vf_id) * IRO[3].m1)) 4083 #define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size) 4084 4085 /* Ustorm Final flr cleanup ack */ 4086 #define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) \ 4087 (IRO[4].base + ((pf_id) * IRO[4].m1)) 4088 #define USTORM_FLR_FINAL_ACK_SIZE (IRO[4].size) 4089 4090 /* Ustorm Event ring consumer */ 4091 #define USTORM_EQE_CONS_OFFSET(pf_id) \ 4092 (IRO[5].base + ((pf_id) * IRO[5].m1)) 4093 #define USTORM_EQE_CONS_SIZE (IRO[5].size) 4094 4095 /* Ustorm eth queue zone */ 4096 #define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) \ 4097 (IRO[6].base + ((queue_zone_id) * IRO[6].m1)) 4098 #define USTORM_ETH_QUEUE_ZONE_SIZE (IRO[6].size) 4099 4100 /* Ustorm Common Queue ring consumer */ 4101 #define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) \ 4102 (IRO[7].base + ((queue_zone_id) * IRO[7].m1)) 4103 #define USTORM_COMMON_QUEUE_CONS_SIZE (IRO[7].size) 4104 4105 /* Xstorm common PQ info */ 4106 #define XSTORM_PQ_INFO_OFFSET(pq_id) \ 4107 (IRO[8].base + ((pq_id) * IRO[8].m1)) 4108 #define XSTORM_PQ_INFO_SIZE (IRO[8].size) 4109 4110 /* Xstorm Integration Test Data */ 4111 #define XSTORM_INTEG_TEST_DATA_OFFSET (IRO[9].base) 4112 #define XSTORM_INTEG_TEST_DATA_SIZE (IRO[9].size) 4113 4114 /* Ystorm Integration Test Data */ 4115 #define YSTORM_INTEG_TEST_DATA_OFFSET (IRO[10].base) 4116 #define YSTORM_INTEG_TEST_DATA_SIZE (IRO[10].size) 4117 4118 /* Pstorm Integration Test Data */ 4119 #define PSTORM_INTEG_TEST_DATA_OFFSET (IRO[11].base) 4120 #define PSTORM_INTEG_TEST_DATA_SIZE (IRO[11].size) 4121 4122 /* Tstorm Integration Test Data */ 4123 #define TSTORM_INTEG_TEST_DATA_OFFSET (IRO[12].base) 4124 #define TSTORM_INTEG_TEST_DATA_SIZE (IRO[12].size) 4125 4126 /* Mstorm Integration Test Data */ 4127 #define MSTORM_INTEG_TEST_DATA_OFFSET (IRO[13].base) 4128 #define MSTORM_INTEG_TEST_DATA_SIZE (IRO[13].size) 4129 4130 /* Ustorm Integration Test Data */ 4131 #define USTORM_INTEG_TEST_DATA_OFFSET (IRO[14].base) 4132 #define USTORM_INTEG_TEST_DATA_SIZE (IRO[14].size) 4133 4134 /* Xstorm overlay buffer host address */ 4135 #define XSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[15].base) 4136 #define XSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[15].size) 4137 4138 /* Ystorm overlay buffer host address */ 4139 #define YSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[16].base) 4140 #define YSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[16].size) 4141 4142 /* Pstorm overlay buffer host address */ 4143 #define PSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[17].base) 4144 #define PSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[17].size) 4145 4146 /* Tstorm overlay buffer host address */ 4147 #define TSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[18].base) 4148 #define TSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[18].size) 4149 4150 /* Mstorm overlay buffer host address */ 4151 #define MSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[19].base) 4152 #define MSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[19].size) 4153 4154 /* Ustorm overlay buffer host address */ 4155 #define USTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[20].base) 4156 #define USTORM_OVERLAY_BUF_ADDR_SIZE (IRO[20].size) 4157 4158 /* Tstorm producers */ 4159 #define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \ 4160 (IRO[21].base + ((core_rx_queue_id) * IRO[21].m1)) 4161 #define TSTORM_LL2_RX_PRODS_SIZE (IRO[21].size) 4162 4163 /* Tstorm LightL2 queue statistics */ 4164 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \ 4165 (IRO[22].base + ((core_rx_queue_id) * IRO[22].m1)) 4166 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE (IRO[22].size) 4167 4168 /* Ustorm LiteL2 queue statistics */ 4169 #define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \ 4170 (IRO[23].base + ((core_rx_queue_id) * IRO[23].m1)) 4171 #define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE (IRO[23].size) 4172 4173 /* Pstorm LiteL2 queue statistics */ 4174 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \ 4175 (IRO[24].base + ((core_tx_stats_id) * IRO[24].m1)) 4176 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE (IRO[24].size) 4177 4178 /* Mstorm queue statistics */ 4179 #define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \ 4180 (IRO[25].base + ((stat_counter_id) * IRO[25].m1)) 4181 #define MSTORM_QUEUE_STAT_SIZE (IRO[25].size) 4182 4183 /* TPA agregation timeout in us resolution (on ASIC) */ 4184 #define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[26].base) 4185 #define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[26].size) 4186 4187 /* Mstorm ETH VF queues producers offset in RAM. Used in default VF zone size 4188 * mode 4189 */ 4190 #define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \ 4191 (IRO[27].base + ((vf_id) * IRO[27].m1) + ((vf_queue_id) * IRO[27].m2)) 4192 #define MSTORM_ETH_VF_PRODS_SIZE (IRO[27].size) 4193 4194 /* Mstorm ETH PF queues producers */ 4195 #define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) \ 4196 (IRO[28].base + ((queue_id) * IRO[28].m1)) 4197 #define MSTORM_ETH_PF_PRODS_SIZE (IRO[28].size) 4198 4199 /* Mstorm pf statistics */ 4200 #define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \ 4201 (IRO[29].base + ((pf_id) * IRO[29].m1)) 4202 #define MSTORM_ETH_PF_STAT_SIZE (IRO[29].size) 4203 4204 /* Ustorm queue statistics */ 4205 #define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \ 4206 (IRO[30].base + ((stat_counter_id) * IRO[30].m1)) 4207 #define USTORM_QUEUE_STAT_SIZE (IRO[30].size) 4208 4209 /* Ustorm pf statistics */ 4210 #define USTORM_ETH_PF_STAT_OFFSET(pf_id) \ 4211 (IRO[31].base + ((pf_id) * IRO[31].m1)) 4212 #define USTORM_ETH_PF_STAT_SIZE (IRO[31].size) 4213 4214 /* Pstorm queue statistics */ 4215 #define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \ 4216 (IRO[32].base + ((stat_counter_id) * IRO[32].m1)) 4217 #define PSTORM_QUEUE_STAT_SIZE (IRO[32].size) 4218 4219 /* Pstorm pf statistics */ 4220 #define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \ 4221 (IRO[33].base + ((pf_id) * IRO[33].m1)) 4222 #define PSTORM_ETH_PF_STAT_SIZE (IRO[33].size) 4223 4224 /* Control frame's EthType configuration for TX control frame security */ 4225 #define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(eth_type_id) \ 4226 (IRO[34].base + ((eth_type_id) * IRO[34].m1)) 4227 #define PSTORM_CTL_FRAME_ETHTYPE_SIZE (IRO[34].size) 4228 4229 /* Tstorm last parser message */ 4230 #define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[35].base) 4231 #define TSTORM_ETH_PRS_INPUT_SIZE (IRO[35].size) 4232 4233 /* Tstorm Eth limit Rx rate */ 4234 #define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \ 4235 (IRO[36].base + ((pf_id) * IRO[36].m1)) 4236 #define ETH_RX_RATE_LIMIT_SIZE (IRO[36].size) 4237 4238 /* RSS indirection table entry update command per PF offset in TSTORM PF BAR0. 4239 * Use eth_tstorm_rss_update_data for update 4240 */ 4241 #define TSTORM_ETH_RSS_UPDATE_OFFSET(pf_id) \ 4242 (IRO[37].base + ((pf_id) * IRO[37].m1)) 4243 #define TSTORM_ETH_RSS_UPDATE_SIZE (IRO[37].size) 4244 4245 /* Xstorm queue zone */ 4246 #define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \ 4247 (IRO[38].base + ((queue_id) * IRO[38].m1)) 4248 #define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[38].size) 4249 4250 /* Ystorm cqe producer */ 4251 #define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) \ 4252 (IRO[39].base + ((rss_id) * IRO[39].m1)) 4253 #define YSTORM_TOE_CQ_PROD_SIZE (IRO[39].size) 4254 4255 /* Ustorm cqe producer */ 4256 #define USTORM_TOE_CQ_PROD_OFFSET(rss_id) \ 4257 (IRO[40].base + ((rss_id) * IRO[40].m1)) 4258 #define USTORM_TOE_CQ_PROD_SIZE (IRO[40].size) 4259 4260 /* Ustorm grq producer */ 4261 #define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) \ 4262 (IRO[41].base + ((pf_id) * IRO[41].m1)) 4263 #define USTORM_TOE_GRQ_PROD_SIZE (IRO[41].size) 4264 4265 /* Tstorm cmdq-cons of given command queue-id */ 4266 #define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \ 4267 (IRO[42].base + ((cmdq_queue_id) * IRO[42].m1)) 4268 #define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[42].size) 4269 4270 /* Tstorm (reflects M-Storm) bdq-external-producer of given function ID, 4271 * BDqueue-id 4272 */ 4273 #define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(storage_func_id, bdq_id) \ 4274 (IRO[43].base + ((storage_func_id) * IRO[43].m1) + \ 4275 ((bdq_id) * IRO[43].m2)) 4276 #define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[43].size) 4277 4278 /* Mstorm bdq-external-producer of given BDQ resource ID, BDqueue-id */ 4279 #define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(storage_func_id, bdq_id) \ 4280 (IRO[44].base + ((storage_func_id) * IRO[44].m1) + \ 4281 ((bdq_id) * IRO[44].m2)) 4282 #define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[44].size) 4283 4284 /* Tstorm iSCSI RX stats */ 4285 #define TSTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \ 4286 (IRO[45].base + ((storage_func_id) * IRO[45].m1)) 4287 #define TSTORM_ISCSI_RX_STATS_SIZE (IRO[45].size) 4288 4289 /* Mstorm iSCSI RX stats */ 4290 #define MSTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \ 4291 (IRO[46].base + ((storage_func_id) * IRO[46].m1)) 4292 #define MSTORM_ISCSI_RX_STATS_SIZE (IRO[46].size) 4293 4294 /* Ustorm iSCSI RX stats */ 4295 #define USTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \ 4296 (IRO[47].base + ((storage_func_id) * IRO[47].m1)) 4297 #define USTORM_ISCSI_RX_STATS_SIZE (IRO[47].size) 4298 4299 /* Xstorm iSCSI TX stats */ 4300 #define XSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \ 4301 (IRO[48].base + ((storage_func_id) * IRO[48].m1)) 4302 #define XSTORM_ISCSI_TX_STATS_SIZE (IRO[48].size) 4303 4304 /* Ystorm iSCSI TX stats */ 4305 #define YSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \ 4306 (IRO[49].base + ((storage_func_id) * IRO[49].m1)) 4307 #define YSTORM_ISCSI_TX_STATS_SIZE (IRO[49].size) 4308 4309 /* Pstorm iSCSI TX stats */ 4310 #define PSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \ 4311 (IRO[50].base + ((storage_func_id) * IRO[50].m1)) 4312 #define PSTORM_ISCSI_TX_STATS_SIZE (IRO[50].size) 4313 4314 /* Tstorm FCoE RX stats */ 4315 #define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \ 4316 (IRO[51].base + ((pf_id) * IRO[51].m1)) 4317 #define TSTORM_FCOE_RX_STATS_SIZE (IRO[51].size) 4318 4319 /* Pstorm FCoE TX stats */ 4320 #define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \ 4321 (IRO[52].base + ((pf_id) * IRO[52].m1)) 4322 #define PSTORM_FCOE_TX_STATS_SIZE (IRO[52].size) 4323 4324 /* Pstorm RDMA queue statistics */ 4325 #define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \ 4326 (IRO[53].base + ((rdma_stat_counter_id) * IRO[53].m1)) 4327 #define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[53].size) 4328 4329 /* Tstorm RDMA queue statistics */ 4330 #define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \ 4331 (IRO[54].base + ((rdma_stat_counter_id) * IRO[54].m1)) 4332 #define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[54].size) 4333 4334 /* Xstorm error level for assert */ 4335 #define XSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \ 4336 (IRO[55].base + ((pf_id) * IRO[55].m1)) 4337 #define XSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[55].size) 4338 4339 /* Ystorm error level for assert */ 4340 #define YSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \ 4341 (IRO[56].base + ((pf_id) * IRO[56].m1)) 4342 #define YSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[56].size) 4343 4344 /* Pstorm error level for assert */ 4345 #define PSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \ 4346 (IRO[57].base + ((pf_id) * IRO[57].m1)) 4347 #define PSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[57].size) 4348 4349 /* Tstorm error level for assert */ 4350 #define TSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \ 4351 (IRO[58].base + ((pf_id) * IRO[58].m1)) 4352 #define TSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[58].size) 4353 4354 /* Mstorm error level for assert */ 4355 #define MSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \ 4356 (IRO[59].base + ((pf_id) * IRO[59].m1)) 4357 #define MSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[59].size) 4358 4359 /* Ustorm error level for assert */ 4360 #define USTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \ 4361 (IRO[60].base + ((pf_id) * IRO[60].m1)) 4362 #define USTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[60].size) 4363 4364 /* Xstorm iWARP rxmit stats */ 4365 #define XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id) \ 4366 (IRO[61].base + ((pf_id) * IRO[61].m1)) 4367 #define XSTORM_IWARP_RXMIT_STATS_SIZE (IRO[61].size) 4368 4369 /* Tstorm RoCE Event Statistics */ 4370 #define TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id) \ 4371 (IRO[62].base + ((roce_pf_id) * IRO[62].m1)) 4372 #define TSTORM_ROCE_EVENTS_STAT_SIZE (IRO[62].size) 4373 4374 /* DCQCN Received Statistics */ 4375 #define YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id)\ 4376 (IRO[63].base + ((roce_pf_id) * IRO[63].m1)) 4377 #define YSTORM_ROCE_DCQCN_RECEIVED_STATS_SIZE (IRO[63].size) 4378 4379 /* RoCE Error Statistics */ 4380 #define YSTORM_ROCE_ERROR_STATS_OFFSET(roce_pf_id) \ 4381 (IRO[64].base + ((roce_pf_id) * IRO[64].m1)) 4382 #define YSTORM_ROCE_ERROR_STATS_SIZE (IRO[64].size) 4383 4384 /* DCQCN Sent Statistics */ 4385 #define PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id) \ 4386 (IRO[65].base + ((roce_pf_id) * IRO[65].m1)) 4387 #define PSTORM_ROCE_DCQCN_SENT_STATS_SIZE (IRO[65].size) 4388 4389 /* RoCE CQEs Statistics */ 4390 #define USTORM_ROCE_CQE_STATS_OFFSET(roce_pf_id) \ 4391 (IRO[66].base + ((roce_pf_id) * IRO[66].m1)) 4392 #define USTORM_ROCE_CQE_STATS_SIZE (IRO[66].size) 4393 4394 /* IRO Array */ 4395 static const u32 iro_arr[] = { 4396 0x00000000, 0x00000000, 0x00080000, 4397 0x00003288, 0x00000088, 0x00880000, 4398 0x000058e8, 0x00000020, 0x00200000, 4399 0x00000b00, 0x00000008, 0x00040000, 4400 0x00000a80, 0x00000008, 0x00040000, 4401 0x00000000, 0x00000008, 0x00020000, 4402 0x00000080, 0x00000008, 0x00040000, 4403 0x00000084, 0x00000008, 0x00020000, 4404 0x00005718, 0x00000004, 0x00040000, 4405 0x00004dd0, 0x00000000, 0x00780000, 4406 0x00003e40, 0x00000000, 0x00780000, 4407 0x00004480, 0x00000000, 0x00780000, 4408 0x00003210, 0x00000000, 0x00780000, 4409 0x00003b50, 0x00000000, 0x00780000, 4410 0x00007f58, 0x00000000, 0x00780000, 4411 0x00005f58, 0x00000000, 0x00080000, 4412 0x00007100, 0x00000000, 0x00080000, 4413 0x0000aea0, 0x00000000, 0x00080000, 4414 0x00004398, 0x00000000, 0x00080000, 4415 0x0000a5a0, 0x00000000, 0x00080000, 4416 0x0000bde8, 0x00000000, 0x00080000, 4417 0x00000020, 0x00000004, 0x00040000, 4418 0x000056c8, 0x00000010, 0x00100000, 4419 0x0000c210, 0x00000030, 0x00300000, 4420 0x0000b088, 0x00000038, 0x00380000, 4421 0x00003d20, 0x00000080, 0x00400000, 4422 0x0000bf60, 0x00000000, 0x00040000, 4423 0x00004560, 0x00040080, 0x00040000, 4424 0x000001f8, 0x00000004, 0x00040000, 4425 0x00003d60, 0x00000080, 0x00200000, 4426 0x00008960, 0x00000040, 0x00300000, 4427 0x0000e840, 0x00000060, 0x00600000, 4428 0x00004618, 0x00000080, 0x00380000, 4429 0x00010738, 0x000000c0, 0x00c00000, 4430 0x000001f8, 0x00000002, 0x00020000, 4431 0x0000a2a0, 0x00000000, 0x01080000, 4432 0x0000a3a8, 0x00000008, 0x00080000, 4433 0x000001c0, 0x00000008, 0x00080000, 4434 0x000001f8, 0x00000008, 0x00080000, 4435 0x00000ac0, 0x00000008, 0x00080000, 4436 0x00002578, 0x00000008, 0x00080000, 4437 0x000024f8, 0x00000008, 0x00080000, 4438 0x00000280, 0x00000008, 0x00080000, 4439 0x00000680, 0x00080018, 0x00080000, 4440 0x00000b78, 0x00080018, 0x00020000, 4441 0x0000c640, 0x00000050, 0x003c0000, 4442 0x00012038, 0x00000018, 0x00100000, 4443 0x00011b00, 0x00000040, 0x00180000, 4444 0x000095d0, 0x00000050, 0x00200000, 4445 0x00008b10, 0x00000040, 0x00280000, 4446 0x00011640, 0x00000018, 0x00100000, 4447 0x0000c828, 0x00000048, 0x00380000, 4448 0x00011710, 0x00000020, 0x00200000, 4449 0x00004650, 0x00000080, 0x00100000, 4450 0x00003618, 0x00000010, 0x00100000, 4451 0x0000a968, 0x00000008, 0x00010000, 4452 0x000097a0, 0x00000008, 0x00010000, 4453 0x00011990, 0x00000008, 0x00010000, 4454 0x0000f018, 0x00000008, 0x00010000, 4455 0x00012628, 0x00000008, 0x00010000, 4456 0x00011da8, 0x00000008, 0x00010000, 4457 0x0000aa78, 0x00000030, 0x00100000, 4458 0x0000d768, 0x00000028, 0x00280000, 4459 0x00009a58, 0x00000018, 0x00180000, 4460 0x00009bd8, 0x00000008, 0x00080000, 4461 0x00013a18, 0x00000008, 0x00080000, 4462 0x000126e8, 0x00000018, 0x00180000, 4463 0x0000e608, 0x00500288, 0x00100000, 4464 0x00012970, 0x00000138, 0x00280000, 4465 }; 4466 4467 /* Runtime array offsets */ 4468 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0 4469 #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1 4470 #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2 4471 #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3 4472 #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4 4473 #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5 4474 #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6 4475 #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7 4476 #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8 4477 #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9 4478 #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10 4479 #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11 4480 #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12 4481 #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13 4482 #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14 4483 #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15 4484 #define DORQ_REG_VF_ICID_BIT_SHIFT_NORM_RT_OFFSET 16 4485 #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 17 4486 #define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 18 4487 #define IGU_REG_PF_CONFIGURATION_RT_OFFSET 19 4488 #define IGU_REG_VF_CONFIGURATION_RT_OFFSET 20 4489 #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 21 4490 #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 22 4491 #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 23 4492 #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 24 4493 #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 25 4494 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 26 4495 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736 4496 #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 762 4497 #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736 4498 #define CAU_REG_PI_MEMORY_RT_OFFSET 1498 4499 #define CAU_REG_PI_MEMORY_RT_SIZE 4416 4500 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 5914 4501 #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 5915 4502 #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 5916 4503 #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 5917 4504 #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 5918 4505 #define PRS_REG_SEARCH_TCP_RT_OFFSET 5919 4506 #define PRS_REG_SEARCH_FCOE_RT_OFFSET 5920 4507 #define PRS_REG_SEARCH_ROCE_RT_OFFSET 5921 4508 #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 5922 4509 #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 5923 4510 #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 5924 4511 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 5925 4512 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 5926 4513 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 5927 4514 #define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 5928 4515 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 5929 4516 #define SRC_REG_FIRSTFREE_RT_OFFSET 5930 4517 #define SRC_REG_FIRSTFREE_RT_SIZE 2 4518 #define SRC_REG_LASTFREE_RT_OFFSET 5932 4519 #define SRC_REG_LASTFREE_RT_SIZE 2 4520 #define SRC_REG_COUNTFREE_RT_OFFSET 5934 4521 #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 5935 4522 #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 5936 4523 #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 5937 4524 #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 5938 4525 #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 5939 4526 #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 5940 4527 #define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 5941 4528 #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 5942 4529 #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 5943 4530 #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 5944 4531 #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 5945 4532 #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 5946 4533 #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 5947 4534 #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 5948 4535 #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 5949 4536 #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 5950 4537 #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 5951 4538 #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 5952 4539 #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 5953 4540 #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 5954 4541 #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 5955 4542 #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 5956 4543 #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 5957 4544 #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 5958 4545 #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 5959 4546 #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 5960 4547 #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 5961 4548 #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 5962 4549 #define PSWRQ2_REG_VF_BASE_RT_OFFSET 5963 4550 #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 5964 4551 #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 5965 4552 #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 5966 4553 #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 5967 4554 #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000 4555 #define PGLUE_REG_B_VF_BASE_RT_OFFSET 27967 4556 #define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 27968 4557 #define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 27969 4558 #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 27970 4559 #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 27971 4560 #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 27972 4561 #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 27973 4562 #define TM_REG_VF_ENABLE_CONN_RT_OFFSET 27974 4563 #define TM_REG_PF_ENABLE_CONN_RT_OFFSET 27975 4564 #define TM_REG_PF_ENABLE_TASK_RT_OFFSET 27976 4565 #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 27977 4566 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 27978 4567 #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 27979 4568 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416 4569 #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 28395 4570 #define TM_REG_CONFIG_TASK_MEM_RT_SIZE 512 4571 #define QM_REG_MAXPQSIZE_0_RT_OFFSET 28907 4572 #define QM_REG_MAXPQSIZE_1_RT_OFFSET 28908 4573 #define QM_REG_MAXPQSIZE_2_RT_OFFSET 28909 4574 #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 28910 4575 #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 28911 4576 #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 28912 4577 #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 28913 4578 #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 28914 4579 #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 28915 4580 #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 28916 4581 #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 28917 4582 #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 28918 4583 #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 28919 4584 #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 28920 4585 #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 28921 4586 #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 28922 4587 #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 28923 4588 #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 28924 4589 #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 28925 4590 #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 28926 4591 #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 28927 4592 #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 28928 4593 #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 28929 4594 #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 28930 4595 #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 28931 4596 #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 28932 4597 #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 28933 4598 #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 28934 4599 #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 28935 4600 #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 28936 4601 #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 28937 4602 #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 28938 4603 #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 28939 4604 #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 28940 4605 #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 28941 4606 #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 28942 4607 #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 28943 4608 #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 28944 4609 #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 28945 4610 #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 28946 4611 #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 28947 4612 #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 28948 4613 #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 28949 4614 #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 28950 4615 #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 28951 4616 #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 28952 4617 #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 28953 4618 #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 28954 4619 #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 28955 4620 #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 28956 4621 #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 28957 4622 #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 28958 4623 #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 28959 4624 #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 28960 4625 #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 28961 4626 #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 28962 4627 #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 28963 4628 #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 28964 4629 #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 28965 4630 #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 28966 4631 #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 28967 4632 #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 28968 4633 #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 28969 4634 #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 28970 4635 #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 28971 4636 #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 28972 4637 #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 28973 4638 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET 28974 4639 #define QM_REG_BASEADDROTHERPQ_RT_SIZE 128 4640 #define QM_REG_PTRTBLOTHER_RT_OFFSET 29102 4641 #define QM_REG_PTRTBLOTHER_RT_SIZE 256 4642 #define QM_REG_VOQCRDLINE_RT_OFFSET 29358 4643 #define QM_REG_VOQCRDLINE_RT_SIZE 20 4644 #define QM_REG_VOQINITCRDLINE_RT_OFFSET 29378 4645 #define QM_REG_VOQINITCRDLINE_RT_SIZE 20 4646 #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29398 4647 #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29399 4648 #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29400 4649 #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29401 4650 #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29402 4651 #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29403 4652 #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29404 4653 #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29405 4654 #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29406 4655 #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29407 4656 #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29408 4657 #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29409 4658 #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29410 4659 #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29411 4660 #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29412 4661 #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29413 4662 #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29414 4663 #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29415 4664 #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29416 4665 #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29417 4666 #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29418 4667 #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29419 4668 #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29420 4669 #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29421 4670 #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29422 4671 #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29423 4672 #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29424 4673 #define QM_REG_PQTX2PF_0_RT_OFFSET 29425 4674 #define QM_REG_PQTX2PF_1_RT_OFFSET 29426 4675 #define QM_REG_PQTX2PF_2_RT_OFFSET 29427 4676 #define QM_REG_PQTX2PF_3_RT_OFFSET 29428 4677 #define QM_REG_PQTX2PF_4_RT_OFFSET 29429 4678 #define QM_REG_PQTX2PF_5_RT_OFFSET 29430 4679 #define QM_REG_PQTX2PF_6_RT_OFFSET 29431 4680 #define QM_REG_PQTX2PF_7_RT_OFFSET 29432 4681 #define QM_REG_PQTX2PF_8_RT_OFFSET 29433 4682 #define QM_REG_PQTX2PF_9_RT_OFFSET 29434 4683 #define QM_REG_PQTX2PF_10_RT_OFFSET 29435 4684 #define QM_REG_PQTX2PF_11_RT_OFFSET 29436 4685 #define QM_REG_PQTX2PF_12_RT_OFFSET 29437 4686 #define QM_REG_PQTX2PF_13_RT_OFFSET 29438 4687 #define QM_REG_PQTX2PF_14_RT_OFFSET 29439 4688 #define QM_REG_PQTX2PF_15_RT_OFFSET 29440 4689 #define QM_REG_PQTX2PF_16_RT_OFFSET 29441 4690 #define QM_REG_PQTX2PF_17_RT_OFFSET 29442 4691 #define QM_REG_PQTX2PF_18_RT_OFFSET 29443 4692 #define QM_REG_PQTX2PF_19_RT_OFFSET 29444 4693 #define QM_REG_PQTX2PF_20_RT_OFFSET 29445 4694 #define QM_REG_PQTX2PF_21_RT_OFFSET 29446 4695 #define QM_REG_PQTX2PF_22_RT_OFFSET 29447 4696 #define QM_REG_PQTX2PF_23_RT_OFFSET 29448 4697 #define QM_REG_PQTX2PF_24_RT_OFFSET 29449 4698 #define QM_REG_PQTX2PF_25_RT_OFFSET 29450 4699 #define QM_REG_PQTX2PF_26_RT_OFFSET 29451 4700 #define QM_REG_PQTX2PF_27_RT_OFFSET 29452 4701 #define QM_REG_PQTX2PF_28_RT_OFFSET 29453 4702 #define QM_REG_PQTX2PF_29_RT_OFFSET 29454 4703 #define QM_REG_PQTX2PF_30_RT_OFFSET 29455 4704 #define QM_REG_PQTX2PF_31_RT_OFFSET 29456 4705 #define QM_REG_PQTX2PF_32_RT_OFFSET 29457 4706 #define QM_REG_PQTX2PF_33_RT_OFFSET 29458 4707 #define QM_REG_PQTX2PF_34_RT_OFFSET 29459 4708 #define QM_REG_PQTX2PF_35_RT_OFFSET 29460 4709 #define QM_REG_PQTX2PF_36_RT_OFFSET 29461 4710 #define QM_REG_PQTX2PF_37_RT_OFFSET 29462 4711 #define QM_REG_PQTX2PF_38_RT_OFFSET 29463 4712 #define QM_REG_PQTX2PF_39_RT_OFFSET 29464 4713 #define QM_REG_PQTX2PF_40_RT_OFFSET 29465 4714 #define QM_REG_PQTX2PF_41_RT_OFFSET 29466 4715 #define QM_REG_PQTX2PF_42_RT_OFFSET 29467 4716 #define QM_REG_PQTX2PF_43_RT_OFFSET 29468 4717 #define QM_REG_PQTX2PF_44_RT_OFFSET 29469 4718 #define QM_REG_PQTX2PF_45_RT_OFFSET 29470 4719 #define QM_REG_PQTX2PF_46_RT_OFFSET 29471 4720 #define QM_REG_PQTX2PF_47_RT_OFFSET 29472 4721 #define QM_REG_PQTX2PF_48_RT_OFFSET 29473 4722 #define QM_REG_PQTX2PF_49_RT_OFFSET 29474 4723 #define QM_REG_PQTX2PF_50_RT_OFFSET 29475 4724 #define QM_REG_PQTX2PF_51_RT_OFFSET 29476 4725 #define QM_REG_PQTX2PF_52_RT_OFFSET 29477 4726 #define QM_REG_PQTX2PF_53_RT_OFFSET 29478 4727 #define QM_REG_PQTX2PF_54_RT_OFFSET 29479 4728 #define QM_REG_PQTX2PF_55_RT_OFFSET 29480 4729 #define QM_REG_PQTX2PF_56_RT_OFFSET 29481 4730 #define QM_REG_PQTX2PF_57_RT_OFFSET 29482 4731 #define QM_REG_PQTX2PF_58_RT_OFFSET 29483 4732 #define QM_REG_PQTX2PF_59_RT_OFFSET 29484 4733 #define QM_REG_PQTX2PF_60_RT_OFFSET 29485 4734 #define QM_REG_PQTX2PF_61_RT_OFFSET 29486 4735 #define QM_REG_PQTX2PF_62_RT_OFFSET 29487 4736 #define QM_REG_PQTX2PF_63_RT_OFFSET 29488 4737 #define QM_REG_PQOTHER2PF_0_RT_OFFSET 29489 4738 #define QM_REG_PQOTHER2PF_1_RT_OFFSET 29490 4739 #define QM_REG_PQOTHER2PF_2_RT_OFFSET 29491 4740 #define QM_REG_PQOTHER2PF_3_RT_OFFSET 29492 4741 #define QM_REG_PQOTHER2PF_4_RT_OFFSET 29493 4742 #define QM_REG_PQOTHER2PF_5_RT_OFFSET 29494 4743 #define QM_REG_PQOTHER2PF_6_RT_OFFSET 29495 4744 #define QM_REG_PQOTHER2PF_7_RT_OFFSET 29496 4745 #define QM_REG_PQOTHER2PF_8_RT_OFFSET 29497 4746 #define QM_REG_PQOTHER2PF_9_RT_OFFSET 29498 4747 #define QM_REG_PQOTHER2PF_10_RT_OFFSET 29499 4748 #define QM_REG_PQOTHER2PF_11_RT_OFFSET 29500 4749 #define QM_REG_PQOTHER2PF_12_RT_OFFSET 29501 4750 #define QM_REG_PQOTHER2PF_13_RT_OFFSET 29502 4751 #define QM_REG_PQOTHER2PF_14_RT_OFFSET 29503 4752 #define QM_REG_PQOTHER2PF_15_RT_OFFSET 29504 4753 #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 29505 4754 #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 29506 4755 #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 29507 4756 #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 29508 4757 #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 29509 4758 #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 29510 4759 #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 29511 4760 #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 29512 4761 #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 29513 4762 #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 29514 4763 #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 29515 4764 #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 29516 4765 #define QM_REG_RLGLBLINCVAL_RT_OFFSET 29517 4766 #define QM_REG_RLGLBLINCVAL_RT_SIZE 256 4767 #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 29773 4768 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256 4769 #define QM_REG_RLGLBLCRD_RT_OFFSET 30029 4770 #define QM_REG_RLGLBLCRD_RT_SIZE 256 4771 #define QM_REG_RLGLBLENABLE_RT_OFFSET 30285 4772 #define QM_REG_RLPFPERIOD_RT_OFFSET 30286 4773 #define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30287 4774 #define QM_REG_RLPFINCVAL_RT_OFFSET 30288 4775 #define QM_REG_RLPFINCVAL_RT_SIZE 16 4776 #define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30304 4777 #define QM_REG_RLPFUPPERBOUND_RT_SIZE 16 4778 #define QM_REG_RLPFCRD_RT_OFFSET 30320 4779 #define QM_REG_RLPFCRD_RT_SIZE 16 4780 #define QM_REG_RLPFENABLE_RT_OFFSET 30336 4781 #define QM_REG_RLPFVOQENABLE_RT_OFFSET 30337 4782 #define QM_REG_WFQPFWEIGHT_RT_OFFSET 30338 4783 #define QM_REG_WFQPFWEIGHT_RT_SIZE 16 4784 #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30354 4785 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16 4786 #define QM_REG_WFQPFCRD_RT_OFFSET 30370 4787 #define QM_REG_WFQPFCRD_RT_SIZE 160 4788 #define QM_REG_WFQPFENABLE_RT_OFFSET 30530 4789 #define QM_REG_WFQVPENABLE_RT_OFFSET 30531 4790 #define QM_REG_BASEADDRTXPQ_RT_OFFSET 30532 4791 #define QM_REG_BASEADDRTXPQ_RT_SIZE 512 4792 #define QM_REG_TXPQMAP_RT_OFFSET 31044 4793 #define QM_REG_TXPQMAP_RT_SIZE 512 4794 #define QM_REG_WFQVPWEIGHT_RT_OFFSET 31556 4795 #define QM_REG_WFQVPWEIGHT_RT_SIZE 512 4796 #define QM_REG_WFQVPCRD_RT_OFFSET 32068 4797 #define QM_REG_WFQVPCRD_RT_SIZE 512 4798 #define QM_REG_WFQVPMAP_RT_OFFSET 32580 4799 #define QM_REG_WFQVPMAP_RT_SIZE 512 4800 #define QM_REG_PTRTBLTX_RT_OFFSET 33092 4801 #define QM_REG_PTRTBLTX_RT_SIZE 1024 4802 #define QM_REG_WFQPFCRD_MSB_RT_OFFSET 34116 4803 #define QM_REG_WFQPFCRD_MSB_RT_SIZE 160 4804 #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 34276 4805 #define NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET 34277 4806 #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 34278 4807 #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 34279 4808 #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 34280 4809 #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 34281 4810 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 34282 4811 #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 34283 4812 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4 4813 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 34287 4814 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4 4815 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 34291 4816 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32 4817 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 34323 4818 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16 4819 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 34339 4820 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16 4821 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 34355 4822 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16 4823 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 34371 4824 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16 4825 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 34387 4826 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET 34388 4827 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE 8 4828 #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 34396 4829 #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 34397 4830 #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 34398 4831 #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 34399 4832 #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 34400 4833 #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 34401 4834 #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 34402 4835 #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 34403 4836 #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 34404 4837 #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 34405 4838 #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 34406 4839 #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 34407 4840 #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 34408 4841 #define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 34409 4842 #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 34410 4843 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 34411 4844 #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 34412 4845 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 34413 4846 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 34414 4847 #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 34415 4848 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 34416 4849 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 34417 4850 #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 34418 4851 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 34419 4852 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 34420 4853 #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 34421 4854 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 34422 4855 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 34423 4856 #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 34424 4857 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 34425 4858 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 34426 4859 #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 34427 4860 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 34428 4861 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 34429 4862 #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 34430 4863 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 34431 4864 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 34432 4865 #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 34433 4866 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 34434 4867 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 34435 4868 #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 34436 4869 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 34437 4870 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 34438 4871 #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 34439 4872 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 34440 4873 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 34441 4874 #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 34442 4875 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 34443 4876 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 34444 4877 #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 34445 4878 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 34446 4879 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 34447 4880 #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 34448 4881 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 34449 4882 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 34450 4883 #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 34451 4884 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 34452 4885 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 34453 4886 #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 34454 4887 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 34455 4888 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 34456 4889 #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 34457 4890 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 34458 4891 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 34459 4892 #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 34460 4893 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 34461 4894 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 34462 4895 #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 34463 4896 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 34464 4897 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 34465 4898 #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 34466 4899 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 34467 4900 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 34468 4901 #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 34469 4902 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 34470 4903 #define XCM_REG_CON_PHY_Q3_RT_OFFSET 34471 4904 4905 #define RUNTIME_ARRAY_SIZE 34472 4906 4907 /* Init Callbacks */ 4908 #define DMAE_READY_CB 0 4909 4910 /* The eth storm context for the Tstorm */ 4911 struct tstorm_eth_conn_st_ctx { 4912 __le32 reserved[4]; 4913 }; 4914 4915 /* The eth storm context for the Pstorm */ 4916 struct pstorm_eth_conn_st_ctx { 4917 __le32 reserved[8]; 4918 }; 4919 4920 /* The eth storm context for the Xstorm */ 4921 struct xstorm_eth_conn_st_ctx { 4922 __le32 reserved[60]; 4923 }; 4924 4925 struct e4_xstorm_eth_conn_ag_ctx { 4926 u8 reserved0; 4927 u8 state; 4928 u8 flags0; 4929 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 4930 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 4931 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1 4932 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1 4933 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1 4934 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2 4935 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 4936 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 4937 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1 4938 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4 4939 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1 4940 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5 4941 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1 4942 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6 4943 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1 4944 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7 4945 u8 flags1; 4946 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1 4947 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0 4948 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1 4949 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1 4950 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1 4951 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2 4952 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1 4953 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3 4954 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 4955 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_SHIFT 4 4956 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 4957 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_SHIFT 5 4958 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 4959 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 4960 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 4961 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 4962 u8 flags2; 4963 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 4964 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0 4965 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 4966 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2 4967 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 4968 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4 4969 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 4970 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6 4971 u8 flags3; 4972 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 4973 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0 4974 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 4975 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2 4976 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 4977 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4 4978 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 4979 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6 4980 u8 flags4; 4981 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 4982 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0 4983 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 4984 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2 4985 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 4986 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4 4987 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3 4988 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6 4989 u8 flags5; 4990 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3 4991 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0 4992 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3 4993 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2 4994 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3 4995 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4 4996 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3 4997 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6 4998 u8 flags6; 4999 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 5000 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 5001 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 5002 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 5003 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3 5004 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4 5005 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 5006 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 5007 u8 flags7; 5008 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 5009 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 5010 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3 5011 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2 5012 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3 5013 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4 5014 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 5015 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6 5016 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 5017 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7 5018 u8 flags8; 5019 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 5020 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0 5021 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 5022 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1 5023 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 5024 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2 5025 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 5026 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3 5027 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 5028 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4 5029 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 5030 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5 5031 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 5032 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6 5033 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 5034 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7 5035 u8 flags9; 5036 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 5037 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0 5038 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1 5039 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1 5040 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1 5041 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2 5042 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1 5043 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3 5044 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1 5045 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4 5046 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1 5047 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5 5048 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 5049 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 5050 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 5051 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 5052 u8 flags10; 5053 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 5054 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 5055 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 5056 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 5057 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 5058 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 5059 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1 5060 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3 5061 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 5062 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 5063 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 5064 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 5065 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1 5066 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6 5067 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1 5068 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7 5069 u8 flags11; 5070 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1 5071 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0 5072 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1 5073 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1 5074 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 5075 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 5076 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 5077 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3 5078 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 5079 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4 5080 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 5081 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5 5082 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 5083 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 5084 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1 5085 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7 5086 u8 flags12; 5087 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1 5088 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0 5089 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1 5090 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1 5091 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 5092 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 5093 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 5094 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 5095 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1 5096 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4 5097 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1 5098 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5 5099 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1 5100 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6 5101 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1 5102 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7 5103 u8 flags13; 5104 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1 5105 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0 5106 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1 5107 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1 5108 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 5109 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 5110 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 5111 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 5112 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 5113 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 5114 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 5115 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 5116 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 5117 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 5118 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 5119 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 5120 u8 flags14; 5121 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 5122 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 5123 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 5124 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 5125 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 5126 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 5127 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 5128 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 5129 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 5130 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 5131 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 5132 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 5133 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 5134 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 5135 u8 edpm_event_id; 5136 __le16 physical_q0; 5137 __le16 e5_reserved1; 5138 __le16 edpm_num_bds; 5139 __le16 tx_bd_cons; 5140 __le16 tx_bd_prod; 5141 __le16 updated_qm_pq_id; 5142 __le16 conn_dpi; 5143 u8 byte3; 5144 u8 byte4; 5145 u8 byte5; 5146 u8 byte6; 5147 __le32 reg0; 5148 __le32 reg1; 5149 __le32 reg2; 5150 __le32 reg3; 5151 __le32 reg4; 5152 __le32 reg5; 5153 __le32 reg6; 5154 __le16 word7; 5155 __le16 word8; 5156 __le16 word9; 5157 __le16 word10; 5158 __le32 reg7; 5159 __le32 reg8; 5160 __le32 reg9; 5161 u8 byte7; 5162 u8 byte8; 5163 u8 byte9; 5164 u8 byte10; 5165 u8 byte11; 5166 u8 byte12; 5167 u8 byte13; 5168 u8 byte14; 5169 u8 byte15; 5170 u8 e5_reserved; 5171 __le16 word11; 5172 __le32 reg10; 5173 __le32 reg11; 5174 __le32 reg12; 5175 __le32 reg13; 5176 __le32 reg14; 5177 __le32 reg15; 5178 __le32 reg16; 5179 __le32 reg17; 5180 __le32 reg18; 5181 __le32 reg19; 5182 __le16 word12; 5183 __le16 word13; 5184 __le16 word14; 5185 __le16 word15; 5186 }; 5187 5188 /* The eth storm context for the Ystorm */ 5189 struct ystorm_eth_conn_st_ctx { 5190 __le32 reserved[8]; 5191 }; 5192 5193 struct e4_ystorm_eth_conn_ag_ctx { 5194 u8 byte0; 5195 u8 state; 5196 u8 flags0; 5197 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 5198 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 5199 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 5200 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 5201 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 5202 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2 5203 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3 5204 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4 5205 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 5206 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 5207 u8 flags1; 5208 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 5209 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0 5210 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1 5211 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1 5212 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 5213 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 5214 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 5215 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 5216 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 5217 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 5218 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 5219 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 5220 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 5221 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 5222 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 5223 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 5224 u8 tx_q0_int_coallecing_timeset; 5225 u8 byte3; 5226 __le16 word0; 5227 __le32 terminate_spqe; 5228 __le32 reg1; 5229 __le16 tx_bd_cons_upd; 5230 __le16 word2; 5231 __le16 word3; 5232 __le16 word4; 5233 __le32 reg2; 5234 __le32 reg3; 5235 }; 5236 5237 struct e4_tstorm_eth_conn_ag_ctx { 5238 u8 byte0; 5239 u8 byte1; 5240 u8 flags0; 5241 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 5242 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 5243 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 5244 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 5245 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1 5246 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2 5247 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1 5248 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3 5249 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1 5250 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4 5251 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1 5252 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5 5253 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 5254 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6 5255 u8 flags1; 5256 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 5257 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0 5258 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 5259 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2 5260 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 5261 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4 5262 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 5263 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6 5264 u8 flags2; 5265 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 5266 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0 5267 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 5268 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2 5269 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 5270 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4 5271 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 5272 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6 5273 u8 flags3; 5274 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 5275 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0 5276 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 5277 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2 5278 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 5279 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4 5280 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 5281 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5 5282 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 5283 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6 5284 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 5285 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7 5286 u8 flags4; 5287 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 5288 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0 5289 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 5290 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1 5291 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 5292 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2 5293 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 5294 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3 5295 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 5296 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4 5297 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 5298 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5 5299 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 5300 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6 5301 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 5302 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 5303 u8 flags5; 5304 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 5305 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 5306 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 5307 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 5308 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 5309 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 5310 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 5311 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 5312 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 5313 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 5314 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1 5315 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5 5316 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 5317 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 5318 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 5319 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 5320 __le32 reg0; 5321 __le32 reg1; 5322 __le32 reg2; 5323 __le32 reg3; 5324 __le32 reg4; 5325 __le32 reg5; 5326 __le32 reg6; 5327 __le32 reg7; 5328 __le32 reg8; 5329 u8 byte2; 5330 u8 byte3; 5331 __le16 rx_bd_cons; 5332 u8 byte4; 5333 u8 byte5; 5334 __le16 rx_bd_prod; 5335 __le16 word2; 5336 __le16 word3; 5337 __le32 reg9; 5338 __le32 reg10; 5339 }; 5340 5341 struct e4_ustorm_eth_conn_ag_ctx { 5342 u8 byte0; 5343 u8 byte1; 5344 u8 flags0; 5345 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 5346 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 5347 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 5348 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 5349 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3 5350 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2 5351 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3 5352 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4 5353 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 5354 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 5355 u8 flags1; 5356 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 5357 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0 5358 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3 5359 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2 5360 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3 5361 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4 5362 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 5363 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6 5364 u8 flags2; 5365 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1 5366 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0 5367 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1 5368 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1 5369 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 5370 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 5371 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 5372 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3 5373 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1 5374 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4 5375 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1 5376 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5 5377 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 5378 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6 5379 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 5380 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 5381 u8 flags3; 5382 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 5383 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 5384 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 5385 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 5386 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 5387 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 5388 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 5389 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 5390 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 5391 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 5392 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 5393 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5 5394 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 5395 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 5396 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 5397 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 5398 u8 byte2; 5399 u8 byte3; 5400 __le16 word0; 5401 __le16 tx_bd_cons; 5402 __le32 reg0; 5403 __le32 reg1; 5404 __le32 reg2; 5405 __le32 tx_int_coallecing_timeset; 5406 __le16 tx_drv_bd_cons; 5407 __le16 rx_drv_cqe_cons; 5408 }; 5409 5410 /* The eth storm context for the Ustorm */ 5411 struct ustorm_eth_conn_st_ctx { 5412 __le32 reserved[40]; 5413 }; 5414 5415 /* The eth storm context for the Mstorm */ 5416 struct mstorm_eth_conn_st_ctx { 5417 __le32 reserved[8]; 5418 }; 5419 5420 /* eth connection context */ 5421 struct e4_eth_conn_context { 5422 struct tstorm_eth_conn_st_ctx tstorm_st_context; 5423 struct regpair tstorm_st_padding[2]; 5424 struct pstorm_eth_conn_st_ctx pstorm_st_context; 5425 struct xstorm_eth_conn_st_ctx xstorm_st_context; 5426 struct e4_xstorm_eth_conn_ag_ctx xstorm_ag_context; 5427 struct e4_tstorm_eth_conn_ag_ctx tstorm_ag_context; 5428 struct ystorm_eth_conn_st_ctx ystorm_st_context; 5429 struct e4_ystorm_eth_conn_ag_ctx ystorm_ag_context; 5430 struct e4_ustorm_eth_conn_ag_ctx ustorm_ag_context; 5431 struct ustorm_eth_conn_st_ctx ustorm_st_context; 5432 struct mstorm_eth_conn_st_ctx mstorm_st_context; 5433 }; 5434 5435 /* Ethernet filter types: mac/vlan/pair */ 5436 enum eth_error_code { 5437 ETH_OK = 0x00, 5438 ETH_FILTERS_MAC_ADD_FAIL_FULL, 5439 ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2, 5440 ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2, 5441 ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2, 5442 ETH_FILTERS_MAC_DEL_FAIL_NOF, 5443 ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2, 5444 ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2, 5445 ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC, 5446 ETH_FILTERS_VLAN_ADD_FAIL_FULL, 5447 ETH_FILTERS_VLAN_ADD_FAIL_DUP, 5448 ETH_FILTERS_VLAN_DEL_FAIL_NOF, 5449 ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1, 5450 ETH_FILTERS_PAIR_ADD_FAIL_DUP, 5451 ETH_FILTERS_PAIR_ADD_FAIL_FULL, 5452 ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC, 5453 ETH_FILTERS_PAIR_DEL_FAIL_NOF, 5454 ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1, 5455 ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC, 5456 ETH_FILTERS_VNI_ADD_FAIL_FULL, 5457 ETH_FILTERS_VNI_ADD_FAIL_DUP, 5458 ETH_FILTERS_GFT_UPDATE_FAIL, 5459 ETH_RX_QUEUE_FAIL_LOAD_VF_DATA, 5460 ETH_FILTERS_GFS_ADD_FILTER_FAIL_MAX_HOPS, 5461 ETH_FILTERS_GFS_ADD_FILTER_FAIL_NO_FREE_ENRTY, 5462 ETH_FILTERS_GFS_ADD_FILTER_FAIL_ALREADY_EXISTS, 5463 ETH_FILTERS_GFS_ADD_FILTER_FAIL_PCI_ERROR, 5464 ETH_FILTERS_GFS_ADD_FINLER_FAIL_MAGIC_NUM_ERROR, 5465 ETH_FILTERS_GFS_DEL_FILTER_FAIL_MAX_HOPS, 5466 ETH_FILTERS_GFS_DEL_FILTER_FAIL_NO_MATCH_ENRTY, 5467 ETH_FILTERS_GFS_DEL_FILTER_FAIL_PCI_ERROR, 5468 ETH_FILTERS_GFS_DEL_FILTER_FAIL_MAGIC_NUM_ERROR, 5469 MAX_ETH_ERROR_CODE 5470 }; 5471 5472 /* Opcodes for the event ring */ 5473 enum eth_event_opcode { 5474 ETH_EVENT_UNUSED, 5475 ETH_EVENT_VPORT_START, 5476 ETH_EVENT_VPORT_UPDATE, 5477 ETH_EVENT_VPORT_STOP, 5478 ETH_EVENT_TX_QUEUE_START, 5479 ETH_EVENT_TX_QUEUE_STOP, 5480 ETH_EVENT_RX_QUEUE_START, 5481 ETH_EVENT_RX_QUEUE_UPDATE, 5482 ETH_EVENT_RX_QUEUE_STOP, 5483 ETH_EVENT_FILTERS_UPDATE, 5484 ETH_EVENT_RX_ADD_OPENFLOW_FILTER, 5485 ETH_EVENT_RX_DELETE_OPENFLOW_FILTER, 5486 ETH_EVENT_RX_CREATE_OPENFLOW_ACTION, 5487 ETH_EVENT_RX_ADD_UDP_FILTER, 5488 ETH_EVENT_RX_DELETE_UDP_FILTER, 5489 ETH_EVENT_RX_CREATE_GFT_ACTION, 5490 ETH_EVENT_RX_GFT_UPDATE_FILTER, 5491 ETH_EVENT_TX_QUEUE_UPDATE, 5492 ETH_EVENT_RGFS_ADD_FILTER, 5493 ETH_EVENT_RGFS_DEL_FILTER, 5494 ETH_EVENT_TGFS_ADD_FILTER, 5495 ETH_EVENT_TGFS_DEL_FILTER, 5496 ETH_EVENT_GFS_COUNTERS_REPORT_REQUEST, 5497 MAX_ETH_EVENT_OPCODE 5498 }; 5499 5500 /* Classify rule types in E2/E3 */ 5501 enum eth_filter_action { 5502 ETH_FILTER_ACTION_UNUSED, 5503 ETH_FILTER_ACTION_REMOVE, 5504 ETH_FILTER_ACTION_ADD, 5505 ETH_FILTER_ACTION_REMOVE_ALL, 5506 MAX_ETH_FILTER_ACTION 5507 }; 5508 5509 /* Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$ */ 5510 struct eth_filter_cmd { 5511 u8 type; 5512 u8 vport_id; 5513 u8 action; 5514 u8 reserved0; 5515 __le32 vni; 5516 __le16 mac_lsb; 5517 __le16 mac_mid; 5518 __le16 mac_msb; 5519 __le16 vlan_id; 5520 }; 5521 5522 /* $$KEEP_ENDIANNESS$$ */ 5523 struct eth_filter_cmd_header { 5524 u8 rx; 5525 u8 tx; 5526 u8 cmd_cnt; 5527 u8 assert_on_error; 5528 u8 reserved1[4]; 5529 }; 5530 5531 /* Ethernet filter types: mac/vlan/pair */ 5532 enum eth_filter_type { 5533 ETH_FILTER_TYPE_UNUSED, 5534 ETH_FILTER_TYPE_MAC, 5535 ETH_FILTER_TYPE_VLAN, 5536 ETH_FILTER_TYPE_PAIR, 5537 ETH_FILTER_TYPE_INNER_MAC, 5538 ETH_FILTER_TYPE_INNER_VLAN, 5539 ETH_FILTER_TYPE_INNER_PAIR, 5540 ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR, 5541 ETH_FILTER_TYPE_MAC_VNI_PAIR, 5542 ETH_FILTER_TYPE_VNI, 5543 MAX_ETH_FILTER_TYPE 5544 }; 5545 5546 /* inner to inner vlan priority translation configurations */ 5547 struct eth_in_to_in_pri_map_cfg { 5548 u8 inner_vlan_pri_remap_en; 5549 u8 reserved[7]; 5550 u8 non_rdma_in_to_in_pri_map[8]; 5551 u8 rdma_in_to_in_pri_map[8]; 5552 }; 5553 5554 /* Eth IPv4 Fragment Type */ 5555 enum eth_ipv4_frag_type { 5556 ETH_IPV4_NOT_FRAG, 5557 ETH_IPV4_FIRST_FRAG, 5558 ETH_IPV4_NON_FIRST_FRAG, 5559 MAX_ETH_IPV4_FRAG_TYPE 5560 }; 5561 5562 /* eth IPv4 Fragment Type */ 5563 enum eth_ip_type { 5564 ETH_IPV4, 5565 ETH_IPV6, 5566 MAX_ETH_IP_TYPE 5567 }; 5568 5569 /* Ethernet Ramrod Command IDs */ 5570 enum eth_ramrod_cmd_id { 5571 ETH_RAMROD_UNUSED, 5572 ETH_RAMROD_VPORT_START, 5573 ETH_RAMROD_VPORT_UPDATE, 5574 ETH_RAMROD_VPORT_STOP, 5575 ETH_RAMROD_RX_QUEUE_START, 5576 ETH_RAMROD_RX_QUEUE_STOP, 5577 ETH_RAMROD_TX_QUEUE_START, 5578 ETH_RAMROD_TX_QUEUE_STOP, 5579 ETH_RAMROD_FILTERS_UPDATE, 5580 ETH_RAMROD_RX_QUEUE_UPDATE, 5581 ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION, 5582 ETH_RAMROD_RX_ADD_OPENFLOW_FILTER, 5583 ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER, 5584 ETH_RAMROD_RX_ADD_UDP_FILTER, 5585 ETH_RAMROD_RX_DELETE_UDP_FILTER, 5586 ETH_RAMROD_RX_CREATE_GFT_ACTION, 5587 ETH_RAMROD_GFT_UPDATE_FILTER, 5588 ETH_RAMROD_TX_QUEUE_UPDATE, 5589 ETH_RAMROD_RGFS_FILTER_ADD, 5590 ETH_RAMROD_RGFS_FILTER_DEL, 5591 ETH_RAMROD_TGFS_FILTER_ADD, 5592 ETH_RAMROD_TGFS_FILTER_DEL, 5593 ETH_RAMROD_GFS_COUNTERS_REPORT_REQUEST, 5594 MAX_ETH_RAMROD_CMD_ID 5595 }; 5596 5597 /* Return code from eth sp ramrods */ 5598 struct eth_return_code { 5599 u8 value; 5600 #define ETH_RETURN_CODE_ERR_CODE_MASK 0x3F 5601 #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0 5602 #define ETH_RETURN_CODE_RESERVED_MASK 0x1 5603 #define ETH_RETURN_CODE_RESERVED_SHIFT 6 5604 #define ETH_RETURN_CODE_RX_TX_MASK 0x1 5605 #define ETH_RETURN_CODE_RX_TX_SHIFT 7 5606 }; 5607 5608 /* tx destination enum */ 5609 enum eth_tx_dst_mode_config_enum { 5610 ETH_TX_DST_MODE_CONFIG_DISABLE, 5611 ETH_TX_DST_MODE_CONFIG_FORWARD_DATA_IN_BD, 5612 ETH_TX_DST_MODE_CONFIG_FORWARD_DATA_IN_VPORT, 5613 MAX_ETH_TX_DST_MODE_CONFIG_ENUM 5614 }; 5615 5616 /* What to do in case an error occurs */ 5617 enum eth_tx_err { 5618 ETH_TX_ERR_DROP, 5619 ETH_TX_ERR_ASSERT_MALICIOUS, 5620 MAX_ETH_TX_ERR 5621 }; 5622 5623 /* Array of the different error type behaviors */ 5624 struct eth_tx_err_vals { 5625 __le16 values; 5626 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1 5627 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0 5628 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1 5629 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1 5630 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1 5631 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2 5632 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1 5633 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3 5634 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1 5635 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4 5636 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1 5637 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5 5638 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1 5639 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6 5640 #define ETH_TX_ERR_VALS_ILLEGAL_BD_FLAGS_MASK 0x1 5641 #define ETH_TX_ERR_VALS_ILLEGAL_BD_FLAGS_SHIFT 7 5642 #define ETH_TX_ERR_VALS_RESERVED_MASK 0xFF 5643 #define ETH_TX_ERR_VALS_RESERVED_SHIFT 8 5644 }; 5645 5646 /* vport rss configuration data */ 5647 struct eth_vport_rss_config { 5648 __le16 capabilities; 5649 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1 5650 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0 5651 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1 5652 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1 5653 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1 5654 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2 5655 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1 5656 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3 5657 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1 5658 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4 5659 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1 5660 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5 5661 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1 5662 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6 5663 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF 5664 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7 5665 u8 rss_id; 5666 u8 rss_mode; 5667 u8 update_rss_key; 5668 u8 update_rss_ind_table; 5669 u8 update_rss_capabilities; 5670 u8 tbl_size; 5671 __le32 reserved2[2]; 5672 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM]; 5673 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS]; 5674 __le32 reserved3[2]; 5675 }; 5676 5677 /* eth vport RSS mode */ 5678 enum eth_vport_rss_mode { 5679 ETH_VPORT_RSS_MODE_DISABLED, 5680 ETH_VPORT_RSS_MODE_REGULAR, 5681 MAX_ETH_VPORT_RSS_MODE 5682 }; 5683 5684 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */ 5685 struct eth_vport_rx_mode { 5686 __le16 state; 5687 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1 5688 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0 5689 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1 5690 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1 5691 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1 5692 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2 5693 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1 5694 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3 5695 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1 5696 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4 5697 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1 5698 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5 5699 #define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_MASK 0x1 5700 #define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_SHIFT 6 5701 #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x1FF 5702 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 7 5703 }; 5704 5705 /* Command for setting tpa parameters */ 5706 struct eth_vport_tpa_param { 5707 u8 tpa_ipv4_en_flg; 5708 u8 tpa_ipv6_en_flg; 5709 u8 tpa_ipv4_tunn_en_flg; 5710 u8 tpa_ipv6_tunn_en_flg; 5711 u8 tpa_pkt_split_flg; 5712 u8 tpa_hdr_data_split_flg; 5713 u8 tpa_gro_consistent_flg; 5714 5715 u8 tpa_max_aggs_num; 5716 5717 __le16 tpa_max_size; 5718 __le16 tpa_min_size_to_start; 5719 5720 __le16 tpa_min_size_to_cont; 5721 u8 max_buff_num; 5722 u8 reserved; 5723 }; 5724 5725 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */ 5726 struct eth_vport_tx_mode { 5727 __le16 state; 5728 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1 5729 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0 5730 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1 5731 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1 5732 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1 5733 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2 5734 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1 5735 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3 5736 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1 5737 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4 5738 #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF 5739 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5 5740 }; 5741 5742 /* GFT filter update action type */ 5743 enum gft_filter_update_action { 5744 GFT_ADD_FILTER, 5745 GFT_DELETE_FILTER, 5746 MAX_GFT_FILTER_UPDATE_ACTION 5747 }; 5748 5749 /* Ramrod data for rx add openflow filter */ 5750 struct rx_add_openflow_filter_data { 5751 __le16 action_icid; 5752 u8 priority; 5753 u8 reserved0; 5754 __le32 tenant_id; 5755 __le16 dst_mac_hi; 5756 __le16 dst_mac_mid; 5757 __le16 dst_mac_lo; 5758 __le16 src_mac_hi; 5759 __le16 src_mac_mid; 5760 __le16 src_mac_lo; 5761 __le16 vlan_id; 5762 __le16 l2_eth_type; 5763 u8 ipv4_dscp; 5764 u8 ipv4_frag_type; 5765 u8 ipv4_over_ip; 5766 u8 tenant_id_exists; 5767 __le32 ipv4_dst_addr; 5768 __le32 ipv4_src_addr; 5769 __le16 l4_dst_port; 5770 __le16 l4_src_port; 5771 }; 5772 5773 /* Ramrod data for rx create gft action */ 5774 struct rx_create_gft_action_data { 5775 u8 vport_id; 5776 u8 reserved[7]; 5777 }; 5778 5779 /* Ramrod data for rx create openflow action */ 5780 struct rx_create_openflow_action_data { 5781 u8 vport_id; 5782 u8 reserved[7]; 5783 }; 5784 5785 /* Ramrod data for rx queue start ramrod */ 5786 struct rx_queue_start_ramrod_data { 5787 __le16 rx_queue_id; 5788 __le16 num_of_pbl_pages; 5789 __le16 bd_max_bytes; 5790 __le16 sb_id; 5791 u8 sb_index; 5792 u8 vport_id; 5793 u8 default_rss_queue_flg; 5794 u8 complete_cqe_flg; 5795 u8 complete_event_flg; 5796 u8 stats_counter_id; 5797 u8 pin_context; 5798 u8 pxp_tph_valid_bd; 5799 u8 pxp_tph_valid_pkt; 5800 u8 pxp_st_hint; 5801 5802 __le16 pxp_st_index; 5803 u8 pmd_mode; 5804 5805 u8 notify_en; 5806 u8 toggle_val; 5807 5808 u8 vf_rx_prod_index; 5809 u8 vf_rx_prod_use_zone_a; 5810 u8 reserved[5]; 5811 __le16 reserved1; 5812 struct regpair cqe_pbl_addr; 5813 struct regpair bd_base; 5814 struct regpair reserved2; 5815 }; 5816 5817 /* Ramrod data for rx queue stop ramrod */ 5818 struct rx_queue_stop_ramrod_data { 5819 __le16 rx_queue_id; 5820 u8 complete_cqe_flg; 5821 u8 complete_event_flg; 5822 u8 vport_id; 5823 u8 reserved[3]; 5824 }; 5825 5826 /* Ramrod data for rx queue update ramrod */ 5827 struct rx_queue_update_ramrod_data { 5828 __le16 rx_queue_id; 5829 u8 complete_cqe_flg; 5830 u8 complete_event_flg; 5831 u8 vport_id; 5832 u8 set_default_rss_queue; 5833 u8 reserved[3]; 5834 u8 reserved1; 5835 u8 reserved2; 5836 u8 reserved3; 5837 __le16 reserved4; 5838 __le16 reserved5; 5839 struct regpair reserved6; 5840 }; 5841 5842 /* Ramrod data for rx Add UDP Filter */ 5843 struct rx_udp_filter_data { 5844 __le16 action_icid; 5845 __le16 vlan_id; 5846 u8 ip_type; 5847 u8 tenant_id_exists; 5848 __le16 reserved1; 5849 __le32 ip_dst_addr[4]; 5850 __le32 ip_src_addr[4]; 5851 __le16 udp_dst_port; 5852 __le16 udp_src_port; 5853 __le32 tenant_id; 5854 }; 5855 5856 /* Add or delete GFT filter - filter is packet header of type of packet wished 5857 * to pass certain FW flow. 5858 */ 5859 struct rx_update_gft_filter_data { 5860 struct regpair pkt_hdr_addr; 5861 __le16 pkt_hdr_length; 5862 __le16 action_icid; 5863 __le16 rx_qid; 5864 __le16 flow_id; 5865 __le16 vport_id; 5866 u8 action_icid_valid; 5867 u8 rx_qid_valid; 5868 u8 flow_id_valid; 5869 u8 filter_action; 5870 u8 assert_on_error; 5871 u8 inner_vlan_removal_en; 5872 }; 5873 5874 /* Ramrod data for tx queue start ramrod */ 5875 struct tx_queue_start_ramrod_data { 5876 __le16 sb_id; 5877 u8 sb_index; 5878 u8 vport_id; 5879 u8 reserved0; 5880 u8 stats_counter_id; 5881 __le16 qm_pq_id; 5882 u8 flags; 5883 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1 5884 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0 5885 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1 5886 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1 5887 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1 5888 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 2 5889 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1 5890 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 3 5891 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1 5892 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 4 5893 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x7 5894 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 5 5895 u8 pxp_st_hint; 5896 u8 pxp_tph_valid_bd; 5897 u8 pxp_tph_valid_pkt; 5898 __le16 pxp_st_index; 5899 __le16 comp_agg_size; 5900 __le16 queue_zone_id; 5901 __le16 reserved2; 5902 __le16 pbl_size; 5903 __le16 tx_queue_id; 5904 __le16 same_as_last_id; 5905 __le16 reserved[3]; 5906 struct regpair pbl_base_addr; 5907 struct regpair bd_cons_address; 5908 }; 5909 5910 /* Ramrod data for tx queue stop ramrod */ 5911 struct tx_queue_stop_ramrod_data { 5912 __le16 reserved[4]; 5913 }; 5914 5915 /* Ramrod data for tx queue update ramrod */ 5916 struct tx_queue_update_ramrod_data { 5917 __le16 update_qm_pq_id_flg; 5918 __le16 qm_pq_id; 5919 __le32 reserved0; 5920 struct regpair reserved1[5]; 5921 }; 5922 5923 /* Inner to Inner VLAN priority map update mode */ 5924 enum update_in_to_in_pri_map_mode_enum { 5925 ETH_IN_TO_IN_PRI_MAP_UPDATE_DISABLED, 5926 ETH_IN_TO_IN_PRI_MAP_UPDATE_NON_RDMA_TBL, 5927 ETH_IN_TO_IN_PRI_MAP_UPDATE_RDMA_TBL, 5928 MAX_UPDATE_IN_TO_IN_PRI_MAP_MODE_ENUM 5929 }; 5930 5931 /* Ramrod data for vport update ramrod */ 5932 struct vport_filter_update_ramrod_data { 5933 struct eth_filter_cmd_header filter_cmd_hdr; 5934 struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT]; 5935 }; 5936 5937 /* Ramrod data for vport start ramrod */ 5938 struct vport_start_ramrod_data { 5939 u8 vport_id; 5940 u8 sw_fid; 5941 __le16 mtu; 5942 u8 drop_ttl0_en; 5943 u8 inner_vlan_removal_en; 5944 struct eth_vport_rx_mode rx_mode; 5945 struct eth_vport_tx_mode tx_mode; 5946 struct eth_vport_tpa_param tpa_param; 5947 __le16 default_vlan; 5948 u8 tx_switching_en; 5949 u8 anti_spoofing_en; 5950 u8 default_vlan_en; 5951 u8 handle_ptp_pkts; 5952 u8 silent_vlan_removal_en; 5953 u8 untagged; 5954 struct eth_tx_err_vals tx_err_behav; 5955 u8 zero_placement_offset; 5956 u8 ctl_frame_mac_check_en; 5957 u8 ctl_frame_ethtype_check_en; 5958 u8 reserved0; 5959 u8 reserved1; 5960 u8 tx_dst_port_mode_config; 5961 u8 dst_vport_id; 5962 u8 tx_dst_port_mode; 5963 u8 dst_vport_id_valid; 5964 u8 wipe_inner_vlan_pri_en; 5965 u8 reserved2[2]; 5966 struct eth_in_to_in_pri_map_cfg in_to_in_vlan_pri_map_cfg; 5967 }; 5968 5969 /* Ramrod data for vport stop ramrod */ 5970 struct vport_stop_ramrod_data { 5971 u8 vport_id; 5972 u8 reserved[7]; 5973 }; 5974 5975 /* Ramrod data for vport update ramrod */ 5976 struct vport_update_ramrod_data_cmn { 5977 u8 vport_id; 5978 u8 update_rx_active_flg; 5979 u8 rx_active_flg; 5980 u8 update_tx_active_flg; 5981 u8 tx_active_flg; 5982 u8 update_rx_mode_flg; 5983 u8 update_tx_mode_flg; 5984 u8 update_approx_mcast_flg; 5985 5986 u8 update_rss_flg; 5987 u8 update_inner_vlan_removal_en_flg; 5988 5989 u8 inner_vlan_removal_en; 5990 u8 update_tpa_param_flg; 5991 u8 update_tpa_en_flg; 5992 u8 update_tx_switching_en_flg; 5993 5994 u8 tx_switching_en; 5995 u8 update_anti_spoofing_en_flg; 5996 5997 u8 anti_spoofing_en; 5998 u8 update_handle_ptp_pkts; 5999 6000 u8 handle_ptp_pkts; 6001 u8 update_default_vlan_en_flg; 6002 6003 u8 default_vlan_en; 6004 6005 u8 update_default_vlan_flg; 6006 6007 __le16 default_vlan; 6008 u8 update_accept_any_vlan_flg; 6009 6010 u8 accept_any_vlan; 6011 u8 silent_vlan_removal_en; 6012 u8 update_mtu_flg; 6013 6014 __le16 mtu; 6015 u8 update_ctl_frame_checks_en_flg; 6016 u8 ctl_frame_mac_check_en; 6017 u8 ctl_frame_ethtype_check_en; 6018 u8 update_in_to_in_pri_map_mode; 6019 u8 in_to_in_pri_map[8]; 6020 u8 reserved[6]; 6021 }; 6022 6023 struct vport_update_ramrod_mcast { 6024 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS]; 6025 }; 6026 6027 /* Ramrod data for vport update ramrod */ 6028 struct vport_update_ramrod_data { 6029 struct vport_update_ramrod_data_cmn common; 6030 6031 struct eth_vport_rx_mode rx_mode; 6032 struct eth_vport_tx_mode tx_mode; 6033 __le32 reserved[3]; 6034 struct eth_vport_tpa_param tpa_param; 6035 struct vport_update_ramrod_mcast approx_mcast; 6036 struct eth_vport_rss_config rss_config; 6037 }; 6038 6039 struct e4_xstorm_eth_conn_ag_ctx_dq_ext_ldpart { 6040 u8 reserved0; 6041 u8 state; 6042 u8 flags0; 6043 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 6044 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 6045 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1 6046 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1 6047 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1 6048 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2 6049 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 6050 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 6051 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1 6052 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4 6053 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1 6054 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5 6055 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1 6056 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6 6057 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1 6058 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7 6059 u8 flags1; 6060 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1 6061 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0 6062 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1 6063 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1 6064 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1 6065 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2 6066 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 6067 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 6068 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_MASK 0x1 6069 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_SHIFT 4 6070 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_MASK 0x1 6071 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_SHIFT 5 6072 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1 6073 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6 6074 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1 6075 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7 6076 u8 flags2; 6077 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3 6078 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0 6079 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3 6080 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2 6081 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3 6082 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4 6083 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3 6084 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6 6085 u8 flags3; 6086 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3 6087 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0 6088 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3 6089 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2 6090 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3 6091 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4 6092 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3 6093 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6 6094 u8 flags4; 6095 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3 6096 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0 6097 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3 6098 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2 6099 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3 6100 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4 6101 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3 6102 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6 6103 u8 flags5; 6104 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3 6105 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0 6106 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3 6107 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2 6108 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3 6109 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4 6110 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3 6111 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6 6112 u8 flags6; 6113 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3 6114 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0 6115 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3 6116 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2 6117 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3 6118 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4 6119 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3 6120 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6 6121 u8 flags7; 6122 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3 6123 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0 6124 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3 6125 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2 6126 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 6127 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 6128 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 6129 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 6130 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 6131 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 6132 u8 flags8; 6133 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 6134 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 6135 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 6136 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 6137 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 6138 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 6139 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 6140 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 6141 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 6142 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 6143 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1 6144 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5 6145 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 6146 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 6147 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 6148 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 6149 u8 flags9; 6150 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 6151 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 6152 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 6153 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 6154 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 6155 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 6156 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 6157 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 6158 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 6159 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 6160 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 6161 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 6162 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1 6163 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6 6164 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1 6165 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7 6166 u8 flags10; 6167 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1 6168 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0 6169 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1 6170 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1 6171 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1 6172 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2 6173 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1 6174 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3 6175 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 6176 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 6177 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1 6178 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5 6179 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1 6180 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6 6181 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1 6182 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7 6183 u8 flags11; 6184 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1 6185 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0 6186 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1 6187 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1 6188 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1 6189 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2 6190 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 6191 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 6192 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 6193 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 6194 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 6195 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 6196 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 6197 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 6198 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 6199 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 6200 u8 flags12; 6201 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 6202 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 6203 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 6204 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 6205 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 6206 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 6207 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 6208 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 6209 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 6210 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 6211 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 6212 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 6213 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 6214 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 6215 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 6216 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 6217 u8 flags13; 6218 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 6219 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 6220 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 6221 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 6222 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 6223 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 6224 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 6225 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 6226 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 6227 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 6228 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 6229 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 6230 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 6231 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 6232 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 6233 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 6234 u8 flags14; 6235 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1 6236 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0 6237 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1 6238 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1 6239 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1 6240 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2 6241 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1 6242 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3 6243 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1 6244 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4 6245 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 6246 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 6247 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3 6248 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6 6249 u8 edpm_event_id; 6250 __le16 physical_q0; 6251 __le16 e5_reserved1; 6252 __le16 edpm_num_bds; 6253 __le16 tx_bd_cons; 6254 __le16 tx_bd_prod; 6255 __le16 updated_qm_pq_id; 6256 __le16 conn_dpi; 6257 u8 byte3; 6258 u8 byte4; 6259 u8 byte5; 6260 u8 byte6; 6261 __le32 reg0; 6262 __le32 reg1; 6263 __le32 reg2; 6264 __le32 reg3; 6265 __le32 reg4; 6266 }; 6267 6268 struct e4_mstorm_eth_conn_ag_ctx { 6269 u8 byte0; 6270 u8 byte1; 6271 u8 flags0; 6272 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 6273 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 6274 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 6275 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 6276 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 6277 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2 6278 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 6279 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4 6280 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 6281 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 6282 u8 flags1; 6283 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 6284 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0 6285 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 6286 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1 6287 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 6288 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 6289 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 6290 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 6291 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 6292 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 6293 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 6294 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 6295 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 6296 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 6297 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 6298 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 6299 __le16 word0; 6300 __le16 word1; 6301 __le32 reg0; 6302 __le32 reg1; 6303 }; 6304 6305 struct e4_xstorm_eth_hw_conn_ag_ctx { 6306 u8 reserved0; 6307 u8 state; 6308 u8 flags0; 6309 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 6310 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 6311 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1 6312 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1 6313 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1 6314 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2 6315 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 6316 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 6317 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1 6318 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4 6319 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1 6320 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5 6321 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1 6322 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6 6323 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1 6324 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7 6325 u8 flags1; 6326 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1 6327 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0 6328 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1 6329 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1 6330 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1 6331 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2 6332 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1 6333 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3 6334 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 6335 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_SHIFT 4 6336 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 6337 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_SHIFT 5 6338 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 6339 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 6340 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 6341 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 6342 u8 flags2; 6343 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3 6344 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0 6345 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3 6346 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2 6347 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3 6348 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4 6349 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3 6350 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6 6351 u8 flags3; 6352 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3 6353 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0 6354 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3 6355 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2 6356 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3 6357 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4 6358 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3 6359 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6 6360 u8 flags4; 6361 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3 6362 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0 6363 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3 6364 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2 6365 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3 6366 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4 6367 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3 6368 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6 6369 u8 flags5; 6370 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3 6371 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0 6372 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3 6373 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2 6374 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3 6375 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4 6376 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3 6377 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6 6378 u8 flags6; 6379 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 6380 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 6381 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 6382 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 6383 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3 6384 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4 6385 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 6386 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 6387 u8 flags7; 6388 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 6389 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 6390 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3 6391 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2 6392 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3 6393 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4 6394 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1 6395 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6 6396 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1 6397 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7 6398 u8 flags8; 6399 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1 6400 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0 6401 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1 6402 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1 6403 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1 6404 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2 6405 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1 6406 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3 6407 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1 6408 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4 6409 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1 6410 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5 6411 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1 6412 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6 6413 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1 6414 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7 6415 u8 flags9; 6416 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1 6417 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0 6418 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1 6419 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1 6420 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1 6421 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2 6422 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1 6423 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3 6424 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1 6425 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4 6426 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1 6427 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5 6428 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 6429 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 6430 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 6431 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 6432 u8 flags10; 6433 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 6434 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 6435 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 6436 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 6437 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 6438 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 6439 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1 6440 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3 6441 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 6442 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 6443 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 6444 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 6445 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1 6446 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6 6447 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1 6448 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7 6449 u8 flags11; 6450 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1 6451 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0 6452 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1 6453 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1 6454 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 6455 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 6456 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1 6457 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3 6458 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1 6459 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4 6460 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1 6461 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5 6462 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 6463 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 6464 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1 6465 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7 6466 u8 flags12; 6467 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1 6468 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0 6469 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1 6470 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1 6471 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 6472 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 6473 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 6474 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 6475 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1 6476 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4 6477 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1 6478 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5 6479 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1 6480 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6 6481 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1 6482 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7 6483 u8 flags13; 6484 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1 6485 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0 6486 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1 6487 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1 6488 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 6489 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 6490 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 6491 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 6492 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 6493 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 6494 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 6495 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 6496 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 6497 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 6498 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 6499 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 6500 u8 flags14; 6501 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 6502 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 6503 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 6504 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 6505 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 6506 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 6507 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 6508 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 6509 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 6510 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 6511 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 6512 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 6513 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 6514 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 6515 u8 edpm_event_id; 6516 __le16 physical_q0; 6517 __le16 e5_reserved1; 6518 __le16 edpm_num_bds; 6519 __le16 tx_bd_cons; 6520 __le16 tx_bd_prod; 6521 __le16 updated_qm_pq_id; 6522 __le16 conn_dpi; 6523 }; 6524 6525 /* GFT CAM line struct with fields breakout */ 6526 struct gft_cam_line_mapped { 6527 __le32 camline; 6528 #define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1 6529 #define GFT_CAM_LINE_MAPPED_VALID_SHIFT 0 6530 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK 0x1 6531 #define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT 1 6532 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK 0x1 6533 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT 2 6534 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK 0xF 6535 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT 3 6536 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK 0xF 6537 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT 7 6538 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK 0xF 6539 #define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT 11 6540 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK 0x1 6541 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT 15 6542 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK 0x1 6543 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT 16 6544 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK 0xF 6545 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT 17 6546 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK 0xF 6547 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT 21 6548 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK 0xF 6549 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT 25 6550 #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK 0x7 6551 #define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT 29 6552 }; 6553 6554 6555 /* Used in gft_profile_key: Indication for ip version */ 6556 enum gft_profile_ip_version { 6557 GFT_PROFILE_IPV4 = 0, 6558 GFT_PROFILE_IPV6 = 1, 6559 MAX_GFT_PROFILE_IP_VERSION 6560 }; 6561 6562 /* Profile key stucr fot GFT logic in Prs */ 6563 struct gft_profile_key { 6564 __le16 profile_key; 6565 #define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1 6566 #define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0 6567 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1 6568 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT 1 6569 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF 6570 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2 6571 #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF 6572 #define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT 6 6573 #define GFT_PROFILE_KEY_PF_ID_MASK 0xF 6574 #define GFT_PROFILE_KEY_PF_ID_SHIFT 10 6575 #define GFT_PROFILE_KEY_RESERVED0_MASK 0x3 6576 #define GFT_PROFILE_KEY_RESERVED0_SHIFT 14 6577 }; 6578 6579 /* Used in gft_profile_key: Indication for tunnel type */ 6580 enum gft_profile_tunnel_type { 6581 GFT_PROFILE_NO_TUNNEL = 0, 6582 GFT_PROFILE_VXLAN_TUNNEL = 1, 6583 GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL = 2, 6584 GFT_PROFILE_GRE_IP_TUNNEL = 3, 6585 GFT_PROFILE_GENEVE_MAC_TUNNEL = 4, 6586 GFT_PROFILE_GENEVE_IP_TUNNEL = 5, 6587 MAX_GFT_PROFILE_TUNNEL_TYPE 6588 }; 6589 6590 /* Used in gft_profile_key: Indication for protocol type */ 6591 enum gft_profile_upper_protocol_type { 6592 GFT_PROFILE_ROCE_PROTOCOL = 0, 6593 GFT_PROFILE_RROCE_PROTOCOL = 1, 6594 GFT_PROFILE_FCOE_PROTOCOL = 2, 6595 GFT_PROFILE_ICMP_PROTOCOL = 3, 6596 GFT_PROFILE_ARP_PROTOCOL = 4, 6597 GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER = 5, 6598 GFT_PROFILE_USER_TCP_DST_PORT_1_INNER = 6, 6599 GFT_PROFILE_TCP_PROTOCOL = 7, 6600 GFT_PROFILE_USER_UDP_DST_PORT_1_INNER = 8, 6601 GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER = 9, 6602 GFT_PROFILE_UDP_PROTOCOL = 10, 6603 GFT_PROFILE_USER_IP_1_INNER = 11, 6604 GFT_PROFILE_USER_IP_2_OUTER = 12, 6605 GFT_PROFILE_USER_ETH_1_INNER = 13, 6606 GFT_PROFILE_USER_ETH_2_OUTER = 14, 6607 GFT_PROFILE_RAW = 15, 6608 MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE 6609 }; 6610 6611 /* GFT RAM line struct */ 6612 struct gft_ram_line { 6613 __le32 lo; 6614 #define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3 6615 #define GFT_RAM_LINE_VLAN_SELECT_SHIFT 0 6616 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK 0x1 6617 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT 2 6618 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK 0x1 6619 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT 3 6620 #define GFT_RAM_LINE_TUNNEL_TTL_MASK 0x1 6621 #define GFT_RAM_LINE_TUNNEL_TTL_SHIFT 4 6622 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK 0x1 6623 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT 5 6624 #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK 0x1 6625 #define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT 6 6626 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK 0x1 6627 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT 7 6628 #define GFT_RAM_LINE_TUNNEL_DSCP_MASK 0x1 6629 #define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT 8 6630 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK 0x1 6631 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT 9 6632 #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK 0x1 6633 #define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT 10 6634 #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK 0x1 6635 #define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT 11 6636 #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK 0x1 6637 #define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT 12 6638 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK 0x1 6639 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT 13 6640 #define GFT_RAM_LINE_TUNNEL_VLAN_MASK 0x1 6641 #define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT 14 6642 #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK 0x1 6643 #define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT 15 6644 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK 0x1 6645 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT 16 6646 #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK 0x1 6647 #define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT 17 6648 #define GFT_RAM_LINE_TTL_MASK 0x1 6649 #define GFT_RAM_LINE_TTL_SHIFT 18 6650 #define GFT_RAM_LINE_ETHERTYPE_MASK 0x1 6651 #define GFT_RAM_LINE_ETHERTYPE_SHIFT 19 6652 #define GFT_RAM_LINE_RESERVED0_MASK 0x1 6653 #define GFT_RAM_LINE_RESERVED0_SHIFT 20 6654 #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK 0x1 6655 #define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT 21 6656 #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK 0x1 6657 #define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT 22 6658 #define GFT_RAM_LINE_TCP_FLAG_RST_MASK 0x1 6659 #define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT 23 6660 #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK 0x1 6661 #define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT 24 6662 #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK 0x1 6663 #define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT 25 6664 #define GFT_RAM_LINE_TCP_FLAG_URG_MASK 0x1 6665 #define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT 26 6666 #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK 0x1 6667 #define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT 27 6668 #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK 0x1 6669 #define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT 28 6670 #define GFT_RAM_LINE_TCP_FLAG_NS_MASK 0x1 6671 #define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT 29 6672 #define GFT_RAM_LINE_DST_PORT_MASK 0x1 6673 #define GFT_RAM_LINE_DST_PORT_SHIFT 30 6674 #define GFT_RAM_LINE_SRC_PORT_MASK 0x1 6675 #define GFT_RAM_LINE_SRC_PORT_SHIFT 31 6676 __le32 hi; 6677 #define GFT_RAM_LINE_DSCP_MASK 0x1 6678 #define GFT_RAM_LINE_DSCP_SHIFT 0 6679 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK 0x1 6680 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT 1 6681 #define GFT_RAM_LINE_DST_IP_MASK 0x1 6682 #define GFT_RAM_LINE_DST_IP_SHIFT 2 6683 #define GFT_RAM_LINE_SRC_IP_MASK 0x1 6684 #define GFT_RAM_LINE_SRC_IP_SHIFT 3 6685 #define GFT_RAM_LINE_PRIORITY_MASK 0x1 6686 #define GFT_RAM_LINE_PRIORITY_SHIFT 4 6687 #define GFT_RAM_LINE_PROVIDER_VLAN_MASK 0x1 6688 #define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT 5 6689 #define GFT_RAM_LINE_VLAN_MASK 0x1 6690 #define GFT_RAM_LINE_VLAN_SHIFT 6 6691 #define GFT_RAM_LINE_DST_MAC_MASK 0x1 6692 #define GFT_RAM_LINE_DST_MAC_SHIFT 7 6693 #define GFT_RAM_LINE_SRC_MAC_MASK 0x1 6694 #define GFT_RAM_LINE_SRC_MAC_SHIFT 8 6695 #define GFT_RAM_LINE_TENANT_ID_MASK 0x1 6696 #define GFT_RAM_LINE_TENANT_ID_SHIFT 9 6697 #define GFT_RAM_LINE_RESERVED1_MASK 0x3FFFFF 6698 #define GFT_RAM_LINE_RESERVED1_SHIFT 10 6699 }; 6700 6701 /* Used in the first 2 bits for gft_ram_line: Indication for vlan mask */ 6702 enum gft_vlan_select { 6703 INNER_PROVIDER_VLAN = 0, 6704 INNER_VLAN = 1, 6705 OUTER_PROVIDER_VLAN = 2, 6706 OUTER_VLAN = 3, 6707 MAX_GFT_VLAN_SELECT 6708 }; 6709 6710 /* The rdma task context of Mstorm */ 6711 struct ystorm_rdma_task_st_ctx { 6712 struct regpair temp[4]; 6713 }; 6714 6715 struct e4_ystorm_rdma_task_ag_ctx { 6716 u8 reserved; 6717 u8 byte1; 6718 __le16 msem_ctx_upd_seq; 6719 u8 flags0; 6720 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF 6721 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 6722 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 6723 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 6724 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 6725 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 6726 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1 6727 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6 6728 #define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1 6729 #define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT 7 6730 u8 flags1; 6731 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 6732 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 6733 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 6734 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 6735 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 6736 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4 6737 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 6738 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 6739 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 6740 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 6741 u8 flags2; 6742 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 6743 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 6744 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 6745 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 6746 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 6747 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 6748 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 6749 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 6750 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 6751 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 6752 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 6753 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 6754 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 6755 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 6756 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 6757 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 6758 u8 key; 6759 __le32 mw_cnt_or_qp_id; 6760 u8 ref_cnt_seq; 6761 u8 ctx_upd_seq; 6762 __le16 dif_flags; 6763 __le16 tx_ref_count; 6764 __le16 last_used_ltid; 6765 __le16 parent_mr_lo; 6766 __le16 parent_mr_hi; 6767 __le32 fbo_lo; 6768 __le32 fbo_hi; 6769 }; 6770 6771 struct e4_mstorm_rdma_task_ag_ctx { 6772 u8 reserved; 6773 u8 byte1; 6774 __le16 icid; 6775 u8 flags0; 6776 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF 6777 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 6778 #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 6779 #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 6780 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 6781 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 6782 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 6783 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 6784 #define E4_MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1 6785 #define E4_MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT 7 6786 u8 flags1; 6787 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 6788 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 6789 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 6790 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 6791 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 6792 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4 6793 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 6794 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 6795 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 6796 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 6797 u8 flags2; 6798 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 6799 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0 6800 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 6801 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 6802 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 6803 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 6804 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 6805 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 6806 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 6807 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 6808 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 6809 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 6810 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 6811 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 6812 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 6813 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 6814 u8 key; 6815 __le32 mw_cnt_or_qp_id; 6816 u8 ref_cnt_seq; 6817 u8 ctx_upd_seq; 6818 __le16 dif_flags; 6819 __le16 tx_ref_count; 6820 __le16 last_used_ltid; 6821 __le16 parent_mr_lo; 6822 __le16 parent_mr_hi; 6823 __le32 fbo_lo; 6824 __le32 fbo_hi; 6825 }; 6826 6827 /* The roce task context of Mstorm */ 6828 struct mstorm_rdma_task_st_ctx { 6829 struct regpair temp[4]; 6830 }; 6831 6832 /* The roce task context of Ustorm */ 6833 struct ustorm_rdma_task_st_ctx { 6834 struct regpair temp[6]; 6835 }; 6836 6837 struct e4_ustorm_rdma_task_ag_ctx { 6838 u8 reserved; 6839 u8 state; 6840 __le16 icid; 6841 u8 flags0; 6842 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF 6843 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 6844 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 6845 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 6846 #define E4_USTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 6847 #define E4_USTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 6848 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3 6849 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6 6850 u8 flags1; 6851 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3 6852 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0 6853 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3 6854 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2 6855 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_MASK 0x3 6856 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_SHIFT 4 6857 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 6858 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6 6859 u8 flags2; 6860 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1 6861 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0 6862 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1 6863 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1 6864 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1 6865 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2 6866 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED4_MASK 0x1 6867 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED4_SHIFT 3 6868 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 6869 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4 6870 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 6871 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5 6872 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 6873 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6 6874 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 6875 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7 6876 u8 flags3; 6877 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_MASK 0x1 6878 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_SHIFT 0 6879 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 6880 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1 6881 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_PROD_CONS_EN_MASK 0x1 6882 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_PROD_CONS_EN_SHIFT 2 6883 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 6884 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3 6885 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF 6886 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4 6887 __le32 dif_err_intervals; 6888 __le32 dif_error_1st_interval; 6889 __le32 dif_rxmit_cons; 6890 __le32 dif_rxmit_prod; 6891 __le32 sge_index; 6892 __le32 sq_cons; 6893 u8 byte2; 6894 u8 byte3; 6895 __le16 dif_write_cons; 6896 __le16 dif_write_prod; 6897 __le16 word3; 6898 __le32 dif_error_buffer_address_lo; 6899 __le32 dif_error_buffer_address_hi; 6900 }; 6901 6902 /* RDMA task context */ 6903 struct e4_rdma_task_context { 6904 struct ystorm_rdma_task_st_ctx ystorm_st_context; 6905 struct e4_ystorm_rdma_task_ag_ctx ystorm_ag_context; 6906 struct tdif_task_context tdif_context; 6907 struct e4_mstorm_rdma_task_ag_ctx mstorm_ag_context; 6908 struct mstorm_rdma_task_st_ctx mstorm_st_context; 6909 struct rdif_task_context rdif_context; 6910 struct ustorm_rdma_task_st_ctx ustorm_st_context; 6911 struct regpair ustorm_st_padding[2]; 6912 struct e4_ustorm_rdma_task_ag_ctx ustorm_ag_context; 6913 }; 6914 6915 /* rdma function init ramrod data */ 6916 struct rdma_close_func_ramrod_data { 6917 u8 cnq_start_offset; 6918 u8 num_cnqs; 6919 u8 vf_id; 6920 u8 vf_valid; 6921 u8 reserved[4]; 6922 }; 6923 6924 /* rdma function init CNQ parameters */ 6925 struct rdma_cnq_params { 6926 __le16 sb_num; 6927 u8 sb_index; 6928 u8 num_pbl_pages; 6929 __le32 reserved; 6930 struct regpair pbl_base_addr; 6931 __le16 queue_zone_num; 6932 u8 reserved1[6]; 6933 }; 6934 6935 /* rdma create cq ramrod data */ 6936 struct rdma_create_cq_ramrod_data { 6937 struct regpair cq_handle; 6938 struct regpair pbl_addr; 6939 __le32 max_cqes; 6940 __le16 pbl_num_pages; 6941 __le16 dpi; 6942 u8 is_two_level_pbl; 6943 u8 cnq_id; 6944 u8 pbl_log_page_size; 6945 u8 toggle_bit; 6946 __le16 int_timeout; 6947 u8 vf_id; 6948 u8 flags; 6949 #define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1 6950 #define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_SHIFT 0 6951 #define RDMA_CREATE_CQ_RAMROD_DATA_RESERVED1_MASK 0x7F 6952 #define RDMA_CREATE_CQ_RAMROD_DATA_RESERVED1_SHIFT 1 6953 }; 6954 6955 /* rdma deregister tid ramrod data */ 6956 struct rdma_deregister_tid_ramrod_data { 6957 __le32 itid; 6958 __le32 reserved; 6959 }; 6960 6961 /* rdma destroy cq output params */ 6962 struct rdma_destroy_cq_output_params { 6963 __le16 cnq_num; 6964 __le16 reserved0; 6965 __le32 reserved1; 6966 }; 6967 6968 /* rdma destroy cq ramrod data */ 6969 struct rdma_destroy_cq_ramrod_data { 6970 struct regpair output_params_addr; 6971 }; 6972 6973 /* RDMA slow path EQ cmd IDs */ 6974 enum rdma_event_opcode { 6975 RDMA_EVENT_UNUSED, 6976 RDMA_EVENT_FUNC_INIT, 6977 RDMA_EVENT_FUNC_CLOSE, 6978 RDMA_EVENT_REGISTER_MR, 6979 RDMA_EVENT_DEREGISTER_MR, 6980 RDMA_EVENT_CREATE_CQ, 6981 RDMA_EVENT_RESIZE_CQ, 6982 RDMA_EVENT_DESTROY_CQ, 6983 RDMA_EVENT_CREATE_SRQ, 6984 RDMA_EVENT_MODIFY_SRQ, 6985 RDMA_EVENT_DESTROY_SRQ, 6986 MAX_RDMA_EVENT_OPCODE 6987 }; 6988 6989 /* RDMA FW return code for slow path ramrods */ 6990 enum rdma_fw_return_code { 6991 RDMA_RETURN_OK = 0, 6992 RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR, 6993 RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR, 6994 RDMA_RETURN_RESIZE_CQ_ERR, 6995 RDMA_RETURN_NIG_DRAIN_REQ, 6996 RDMA_RETURN_GENERAL_ERR, 6997 MAX_RDMA_FW_RETURN_CODE 6998 }; 6999 7000 /* rdma function init header */ 7001 struct rdma_init_func_hdr { 7002 u8 cnq_start_offset; 7003 u8 num_cnqs; 7004 u8 cq_ring_mode; 7005 u8 vf_id; 7006 u8 vf_valid; 7007 u8 relaxed_ordering; 7008 __le16 first_reg_srq_id; 7009 __le32 reg_srq_base_addr; 7010 u8 searcher_mode; 7011 u8 pvrdma_mode; 7012 u8 max_num_ns_log; 7013 u8 reserved; 7014 }; 7015 7016 /* rdma function init ramrod data */ 7017 struct rdma_init_func_ramrod_data { 7018 struct rdma_init_func_hdr params_header; 7019 struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES]; 7020 }; 7021 7022 /* RDMA ramrod command IDs */ 7023 enum rdma_ramrod_cmd_id { 7024 RDMA_RAMROD_UNUSED, 7025 RDMA_RAMROD_FUNC_INIT, 7026 RDMA_RAMROD_FUNC_CLOSE, 7027 RDMA_RAMROD_REGISTER_MR, 7028 RDMA_RAMROD_DEREGISTER_MR, 7029 RDMA_RAMROD_CREATE_CQ, 7030 RDMA_RAMROD_RESIZE_CQ, 7031 RDMA_RAMROD_DESTROY_CQ, 7032 RDMA_RAMROD_CREATE_SRQ, 7033 RDMA_RAMROD_MODIFY_SRQ, 7034 RDMA_RAMROD_DESTROY_SRQ, 7035 MAX_RDMA_RAMROD_CMD_ID 7036 }; 7037 7038 /* rdma register tid ramrod data */ 7039 struct rdma_register_tid_ramrod_data { 7040 __le16 flags; 7041 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK 0x1F 7042 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT 0 7043 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1 7044 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT 5 7045 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1 7046 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT 6 7047 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1 7048 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT 7 7049 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1 7050 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT 8 7051 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1 7052 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT 9 7053 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1 7054 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT 10 7055 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1 7056 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT 11 7057 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1 7058 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT 12 7059 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1 7060 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT 13 7061 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK 0x3 7062 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_SHIFT 14 7063 u8 flags1; 7064 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK 0x1F 7065 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0 7066 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK 0x7 7067 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT 5 7068 u8 flags2; 7069 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1 7070 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT 0 7071 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK 0x1 7072 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT 1 7073 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK 0x3F 7074 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT 2 7075 u8 key; 7076 u8 length_hi; 7077 u8 vf_id; 7078 u8 vf_valid; 7079 __le16 pd; 7080 __le16 reserved2; 7081 __le32 length_lo; 7082 __le32 itid; 7083 __le32 reserved3; 7084 struct regpair va; 7085 struct regpair pbl_base; 7086 struct regpair dif_error_addr; 7087 __le32 reserved4[4]; 7088 }; 7089 7090 /* rdma resize cq output params */ 7091 struct rdma_resize_cq_output_params { 7092 __le32 old_cq_cons; 7093 __le32 old_cq_prod; 7094 }; 7095 7096 /* rdma resize cq ramrod data */ 7097 struct rdma_resize_cq_ramrod_data { 7098 u8 flags; 7099 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1 7100 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0 7101 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1 7102 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1 7103 #define RDMA_RESIZE_CQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1 7104 #define RDMA_RESIZE_CQ_RAMROD_DATA_VF_ID_VALID_SHIFT 2 7105 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x1F 7106 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 3 7107 u8 pbl_log_page_size; 7108 __le16 pbl_num_pages; 7109 __le32 max_cqes; 7110 struct regpair pbl_addr; 7111 struct regpair output_params_addr; 7112 u8 vf_id; 7113 u8 reserved1[7]; 7114 }; 7115 7116 /* The rdma SRQ context */ 7117 struct rdma_srq_context { 7118 struct regpair temp[8]; 7119 }; 7120 7121 /* rdma create qp requester ramrod data */ 7122 struct rdma_srq_create_ramrod_data { 7123 u8 flags; 7124 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_MASK 0x1 7125 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_SHIFT 0 7126 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1 7127 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 1 7128 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_MASK 0x3F 7129 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_SHIFT 2 7130 u8 reserved2; 7131 __le16 xrc_domain; 7132 __le32 xrc_srq_cq_cid; 7133 struct regpair pbl_base_addr; 7134 __le16 pages_in_srq_pbl; 7135 __le16 pd_id; 7136 struct rdma_srq_id srq_id; 7137 __le16 page_size; 7138 __le16 reserved3; 7139 __le32 reserved4; 7140 struct regpair producers_addr; 7141 }; 7142 7143 /* rdma create qp requester ramrod data */ 7144 struct rdma_srq_destroy_ramrod_data { 7145 struct rdma_srq_id srq_id; 7146 __le32 reserved; 7147 }; 7148 7149 /* rdma create qp requester ramrod data */ 7150 struct rdma_srq_modify_ramrod_data { 7151 struct rdma_srq_id srq_id; 7152 __le32 wqe_limit; 7153 }; 7154 7155 /* RDMA Tid type enumeration (for register_tid ramrod) */ 7156 enum rdma_tid_type { 7157 RDMA_TID_REGISTERED_MR, 7158 RDMA_TID_FMR, 7159 RDMA_TID_MW, 7160 MAX_RDMA_TID_TYPE 7161 }; 7162 7163 /* The rdma XRC SRQ context */ 7164 struct rdma_xrc_srq_context { 7165 struct regpair temp[9]; 7166 }; 7167 7168 struct e4_tstorm_rdma_task_ag_ctx { 7169 u8 byte0; 7170 u8 byte1; 7171 __le16 word0; 7172 u8 flags0; 7173 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF 7174 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0 7175 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1 7176 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4 7177 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 7178 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 7179 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 7180 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 7181 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 7182 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 7183 u8 flags1; 7184 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 7185 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 7186 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1 7187 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1 7188 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 7189 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2 7190 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 7191 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4 7192 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 7193 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6 7194 u8 flags2; 7195 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 7196 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0 7197 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3 7198 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2 7199 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3 7200 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4 7201 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3 7202 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6 7203 u8 flags3; 7204 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3 7205 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0 7206 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 7207 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2 7208 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 7209 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3 7210 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 7211 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4 7212 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 7213 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5 7214 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1 7215 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6 7216 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1 7217 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7 7218 u8 flags4; 7219 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1 7220 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0 7221 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1 7222 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1 7223 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 7224 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2 7225 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 7226 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3 7227 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 7228 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4 7229 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 7230 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5 7231 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 7232 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6 7233 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 7234 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7 7235 u8 byte2; 7236 __le16 word1; 7237 __le32 reg0; 7238 u8 byte3; 7239 u8 byte4; 7240 __le16 word2; 7241 __le16 word3; 7242 __le16 word4; 7243 __le32 reg1; 7244 __le32 reg2; 7245 }; 7246 7247 struct e4_ustorm_rdma_conn_ag_ctx { 7248 u8 reserved; 7249 u8 byte1; 7250 u8 flags0; 7251 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 7252 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 7253 #define E4_USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_MASK 0x1 7254 #define E4_USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_SHIFT 1 7255 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 7256 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2 7257 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 7258 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 7259 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 7260 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 7261 u8 flags1; 7262 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 7263 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0 7264 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 7265 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 7266 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 7267 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 7268 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 7269 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6 7270 u8 flags2; 7271 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 7272 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 7273 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 7274 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 7275 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 7276 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 7277 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 7278 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3 7279 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 7280 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 7281 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 7282 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 7283 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 7284 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6 7285 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 7286 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 7287 u8 flags3; 7288 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1 7289 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0 7290 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 7291 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 7292 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 7293 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 7294 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 7295 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 7296 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 7297 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 7298 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 7299 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 7300 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 7301 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 7302 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 7303 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 7304 u8 byte2; 7305 u8 nvmf_only; 7306 __le16 conn_dpi; 7307 __le16 word1; 7308 __le32 cq_cons; 7309 __le32 cq_se_prod; 7310 __le32 cq_prod; 7311 __le32 reg3; 7312 __le16 int_timeout; 7313 __le16 word3; 7314 }; 7315 7316 struct e4_xstorm_roce_conn_ag_ctx { 7317 u8 reserved0; 7318 u8 state; 7319 u8 flags0; 7320 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 7321 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 7322 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 7323 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 7324 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT2_MASK 0x1 7325 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT2_SHIFT 2 7326 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 7327 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 7328 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT4_MASK 0x1 7329 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT4_SHIFT 4 7330 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT5_MASK 0x1 7331 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT5_SHIFT 5 7332 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT6_MASK 0x1 7333 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT6_SHIFT 6 7334 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT7_MASK 0x1 7335 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT7_SHIFT 7 7336 u8 flags1; 7337 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT8_MASK 0x1 7338 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT8_SHIFT 0 7339 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT9_MASK 0x1 7340 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT9_SHIFT 1 7341 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT10_MASK 0x1 7342 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT10_SHIFT 2 7343 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT11_MASK 0x1 7344 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT11_SHIFT 3 7345 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1 7346 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_SHIFT 4 7347 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1 7348 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_SHIFT 5 7349 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT14_MASK 0x1 7350 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT14_SHIFT 6 7351 #define E4_XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 7352 #define E4_XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 7353 u8 flags2; 7354 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3 7355 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 0 7356 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3 7357 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT 2 7358 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3 7359 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 4 7360 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3_MASK 0x3 7361 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3_SHIFT 6 7362 u8 flags3; 7363 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4_MASK 0x3 7364 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4_SHIFT 0 7365 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5_MASK 0x3 7366 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT 2 7367 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6_MASK 0x3 7368 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6_SHIFT 4 7369 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 7370 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 7371 u8 flags4; 7372 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8_MASK 0x3 7373 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT 0 7374 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9_MASK 0x3 7375 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT 2 7376 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10_MASK 0x3 7377 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10_SHIFT 4 7378 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11_MASK 0x3 7379 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11_SHIFT 6 7380 u8 flags5; 7381 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12_MASK 0x3 7382 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12_SHIFT 0 7383 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13_MASK 0x3 7384 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13_SHIFT 2 7385 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14_MASK 0x3 7386 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14_SHIFT 4 7387 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15_MASK 0x3 7388 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15_SHIFT 6 7389 u8 flags6; 7390 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16_MASK 0x3 7391 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16_SHIFT 0 7392 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17_MASK 0x3 7393 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17_SHIFT 2 7394 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18_MASK 0x3 7395 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18_SHIFT 4 7396 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19_MASK 0x3 7397 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19_SHIFT 6 7398 u8 flags7; 7399 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20_MASK 0x3 7400 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20_SHIFT 0 7401 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21_MASK 0x3 7402 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21_SHIFT 2 7403 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 7404 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 7405 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1 7406 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 6 7407 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1 7408 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT 7 7409 u8 flags8; 7410 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 7411 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 0 7412 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3EN_MASK 0x1 7413 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3EN_SHIFT 1 7414 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4EN_MASK 0x1 7415 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4EN_SHIFT 2 7416 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK 0x1 7417 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5EN_SHIFT 3 7418 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1 7419 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6EN_SHIFT 4 7420 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 7421 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 7422 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK 0x1 7423 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8EN_SHIFT 6 7424 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK 0x1 7425 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9EN_SHIFT 7 7426 u8 flags9; 7427 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1 7428 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT 0 7429 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11EN_MASK 0x1 7430 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11EN_SHIFT 1 7431 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12EN_MASK 0x1 7432 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12EN_SHIFT 2 7433 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13EN_MASK 0x1 7434 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13EN_SHIFT 3 7435 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14EN_MASK 0x1 7436 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14EN_SHIFT 4 7437 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15EN_MASK 0x1 7438 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15EN_SHIFT 5 7439 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16EN_MASK 0x1 7440 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16EN_SHIFT 6 7441 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17EN_MASK 0x1 7442 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17EN_SHIFT 7 7443 u8 flags10; 7444 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18EN_MASK 0x1 7445 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18EN_SHIFT 0 7446 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19EN_MASK 0x1 7447 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19EN_SHIFT 1 7448 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20EN_MASK 0x1 7449 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20EN_SHIFT 2 7450 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21EN_MASK 0x1 7451 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21EN_SHIFT 3 7452 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 7453 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 7454 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23EN_MASK 0x1 7455 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23EN_SHIFT 5 7456 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1 7457 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 6 7458 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1 7459 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 7 7460 u8 flags11; 7461 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 7462 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 0 7463 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1 7464 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 1 7465 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 7466 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 2 7467 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1 7468 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE5EN_SHIFT 3 7469 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1 7470 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE6EN_SHIFT 4 7471 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1 7472 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE7EN_SHIFT 5 7473 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 7474 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 7475 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE9EN_MASK 0x1 7476 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE9EN_SHIFT 7 7477 u8 flags12; 7478 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE10EN_MASK 0x1 7479 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE10EN_SHIFT 0 7480 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE11EN_MASK 0x1 7481 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE11EN_SHIFT 1 7482 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 7483 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 7484 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 7485 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 7486 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE14EN_MASK 0x1 7487 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE14EN_SHIFT 4 7488 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE15EN_MASK 0x1 7489 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE15EN_SHIFT 5 7490 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE16EN_MASK 0x1 7491 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE16EN_SHIFT 6 7492 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE17EN_MASK 0x1 7493 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE17EN_SHIFT 7 7494 u8 flags13; 7495 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE18EN_MASK 0x1 7496 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE18EN_SHIFT 0 7497 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE19EN_MASK 0x1 7498 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE19EN_SHIFT 1 7499 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 7500 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 7501 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 7502 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 7503 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 7504 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 7505 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 7506 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 7507 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 7508 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 7509 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 7510 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 7511 u8 flags14; 7512 #define E4_XSTORM_ROCE_CONN_AG_CTX_MIGRATION_MASK 0x1 7513 #define E4_XSTORM_ROCE_CONN_AG_CTX_MIGRATION_SHIFT 0 7514 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT17_MASK 0x1 7515 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT17_SHIFT 1 7516 #define E4_XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 7517 #define E4_XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 7518 #define E4_XSTORM_ROCE_CONN_AG_CTX_RESERVED_MASK 0x1 7519 #define E4_XSTORM_ROCE_CONN_AG_CTX_RESERVED_SHIFT 4 7520 #define E4_XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 7521 #define E4_XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 7522 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23_MASK 0x3 7523 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23_SHIFT 6 7524 u8 byte2; 7525 __le16 physical_q0; 7526 __le16 word1; 7527 __le16 word2; 7528 __le16 word3; 7529 __le16 word4; 7530 __le16 word5; 7531 __le16 conn_dpi; 7532 u8 byte3; 7533 u8 byte4; 7534 u8 byte5; 7535 u8 byte6; 7536 __le32 reg0; 7537 __le32 reg1; 7538 __le32 reg2; 7539 __le32 snd_nxt_psn; 7540 __le32 reg4; 7541 __le32 reg5; 7542 __le32 reg6; 7543 }; 7544 7545 struct e4_tstorm_roce_conn_ag_ctx { 7546 u8 reserved0; 7547 u8 byte1; 7548 u8 flags0; 7549 #define E4_TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 7550 #define E4_TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 7551 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 7552 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 7553 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT2_MASK 0x1 7554 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT2_SHIFT 2 7555 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT3_MASK 0x1 7556 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT3_SHIFT 3 7557 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT4_MASK 0x1 7558 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT4_SHIFT 4 7559 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT5_MASK 0x1 7560 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT5_SHIFT 5 7561 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3 7562 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 6 7563 u8 flags1; 7564 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 7565 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 7566 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3 7567 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 2 7568 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 7569 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 7570 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 7571 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 7572 u8 flags2; 7573 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5_MASK 0x3 7574 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT 0 7575 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6_MASK 0x3 7576 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6_SHIFT 2 7577 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7_MASK 0x3 7578 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7_SHIFT 4 7579 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8_MASK 0x3 7580 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT 6 7581 u8 flags3; 7582 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9_MASK 0x3 7583 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT 0 7584 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10_MASK 0x3 7585 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10_SHIFT 2 7586 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1 7587 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 4 7588 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 7589 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 5 7590 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 7591 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 6 7592 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 7593 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 7594 u8 flags4; 7595 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 7596 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 7597 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK 0x1 7598 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5EN_SHIFT 1 7599 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1 7600 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6EN_SHIFT 2 7601 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7EN_MASK 0x1 7602 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7EN_SHIFT 3 7603 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK 0x1 7604 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8EN_SHIFT 4 7605 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK 0x1 7606 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9EN_SHIFT 5 7607 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1 7608 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT 6 7609 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1 7610 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 7 7611 u8 flags5; 7612 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1 7613 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 0 7614 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 7615 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 1 7616 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1 7617 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 2 7618 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 7619 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 3 7620 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1 7621 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE5EN_SHIFT 4 7622 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1 7623 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE6EN_SHIFT 5 7624 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1 7625 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE7EN_SHIFT 6 7626 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE8EN_MASK 0x1 7627 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE8EN_SHIFT 7 7628 __le32 reg0; 7629 __le32 reg1; 7630 __le32 reg2; 7631 __le32 reg3; 7632 __le32 reg4; 7633 __le32 reg5; 7634 __le32 reg6; 7635 __le32 reg7; 7636 __le32 reg8; 7637 u8 byte2; 7638 u8 byte3; 7639 __le16 word0; 7640 u8 byte4; 7641 u8 byte5; 7642 __le16 word1; 7643 __le16 word2; 7644 __le16 word3; 7645 __le32 reg9; 7646 __le32 reg10; 7647 }; 7648 7649 /* The roce storm context of Ystorm */ 7650 struct ystorm_roce_conn_st_ctx { 7651 struct regpair temp[2]; 7652 }; 7653 7654 /* The roce storm context of Mstorm */ 7655 struct pstorm_roce_conn_st_ctx { 7656 struct regpair temp[16]; 7657 }; 7658 7659 /* The roce storm context of Xstorm */ 7660 struct xstorm_roce_conn_st_ctx { 7661 struct regpair temp[24]; 7662 }; 7663 7664 /* The roce storm context of Tstorm */ 7665 struct tstorm_roce_conn_st_ctx { 7666 struct regpair temp[30]; 7667 }; 7668 7669 /* The roce storm context of Mstorm */ 7670 struct mstorm_roce_conn_st_ctx { 7671 struct regpair temp[6]; 7672 }; 7673 7674 /* The roce storm context of Ustorm */ 7675 struct ustorm_roce_conn_st_ctx { 7676 struct regpair temp[14]; 7677 }; 7678 7679 /* roce connection context */ 7680 struct e4_roce_conn_context { 7681 struct ystorm_roce_conn_st_ctx ystorm_st_context; 7682 struct regpair ystorm_st_padding[2]; 7683 struct pstorm_roce_conn_st_ctx pstorm_st_context; 7684 struct xstorm_roce_conn_st_ctx xstorm_st_context; 7685 struct e4_xstorm_roce_conn_ag_ctx xstorm_ag_context; 7686 struct e4_tstorm_roce_conn_ag_ctx tstorm_ag_context; 7687 struct timers_context timer_context; 7688 struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context; 7689 struct tstorm_roce_conn_st_ctx tstorm_st_context; 7690 struct regpair tstorm_st_padding[2]; 7691 struct mstorm_roce_conn_st_ctx mstorm_st_context; 7692 struct regpair mstorm_st_padding[2]; 7693 struct ustorm_roce_conn_st_ctx ustorm_st_context; 7694 struct regpair ustorm_st_padding[2]; 7695 }; 7696 7697 /* roce cqes statistics */ 7698 struct roce_cqe_stats { 7699 __le32 req_cqe_error; 7700 __le32 req_remote_access_errors; 7701 __le32 req_remote_invalid_request; 7702 __le32 resp_cqe_error; 7703 __le32 resp_local_length_error; 7704 __le32 reserved; 7705 }; 7706 7707 /* roce create qp requester ramrod data */ 7708 struct roce_create_qp_req_ramrod_data { 7709 __le16 flags; 7710 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 7711 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0 7712 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1 7713 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 2 7714 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1 7715 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT 3 7716 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7 7717 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT 4 7718 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_MASK 0x1 7719 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_SHIFT 7 7720 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF 7721 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 8 7722 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF 7723 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 12 7724 u8 max_ord; 7725 u8 traffic_class; 7726 u8 hop_limit; 7727 u8 orq_num_pages; 7728 __le16 p_key; 7729 __le32 flow_label; 7730 __le32 dst_qp_id; 7731 __le32 ack_timeout_val; 7732 __le32 initial_psn; 7733 __le16 mtu; 7734 __le16 pd; 7735 __le16 sq_num_pages; 7736 __le16 low_latency_phy_queue; 7737 struct regpair sq_pbl_addr; 7738 struct regpair orq_pbl_addr; 7739 __le16 local_mac_addr[3]; 7740 __le16 remote_mac_addr[3]; 7741 __le16 vlan_id; 7742 __le16 udp_src_port; 7743 __le32 src_gid[4]; 7744 __le32 dst_gid[4]; 7745 __le32 cq_cid; 7746 struct regpair qp_handle_for_cqe; 7747 struct regpair qp_handle_for_async; 7748 u8 stats_counter_id; 7749 u8 vf_id; 7750 u8 vport_id; 7751 u8 flags2; 7752 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_MASK 0x1 7753 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_SHIFT 0 7754 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1 7755 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_VF_ID_VALID_SHIFT 1 7756 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK 0x3F 7757 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT 2 7758 u8 name_space; 7759 u8 reserved3[3]; 7760 __le16 regular_latency_phy_queue; 7761 __le16 dpi; 7762 }; 7763 7764 /* roce create qp responder ramrod data */ 7765 struct roce_create_qp_resp_ramrod_data { 7766 __le32 flags; 7767 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 7768 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0 7769 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 7770 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2 7771 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 7772 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3 7773 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 7774 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 4 7775 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1 7776 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT 5 7777 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1 7778 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT 6 7779 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1 7780 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 7 7781 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK 0x7 7782 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT 8 7783 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F 7784 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 11 7785 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_MASK 0x1 7786 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_SHIFT 16 7787 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_VF_ID_VALID_MASK 0x1 7788 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_VF_ID_VALID_SHIFT 17 7789 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_MASK 0x3FFF 7790 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_SHIFT 18 7791 __le16 xrc_domain; 7792 u8 max_ird; 7793 u8 traffic_class; 7794 u8 hop_limit; 7795 u8 irq_num_pages; 7796 __le16 p_key; 7797 __le32 flow_label; 7798 __le32 dst_qp_id; 7799 u8 stats_counter_id; 7800 u8 reserved1; 7801 __le16 mtu; 7802 __le32 initial_psn; 7803 __le16 pd; 7804 __le16 rq_num_pages; 7805 struct rdma_srq_id srq_id; 7806 struct regpair rq_pbl_addr; 7807 struct regpair irq_pbl_addr; 7808 __le16 local_mac_addr[3]; 7809 __le16 remote_mac_addr[3]; 7810 __le16 vlan_id; 7811 __le16 udp_src_port; 7812 __le32 src_gid[4]; 7813 __le32 dst_gid[4]; 7814 struct regpair qp_handle_for_cqe; 7815 struct regpair qp_handle_for_async; 7816 __le16 low_latency_phy_queue; 7817 u8 vf_id; 7818 u8 vport_id; 7819 __le32 cq_cid; 7820 __le16 regular_latency_phy_queue; 7821 __le16 dpi; 7822 __le32 src_qp_id; 7823 u8 name_space; 7824 u8 reserved3[3]; 7825 }; 7826 7827 /* roce DCQCN received statistics */ 7828 struct roce_dcqcn_received_stats { 7829 struct regpair ecn_pkt_rcv; 7830 struct regpair cnp_pkt_rcv; 7831 }; 7832 7833 /* roce DCQCN sent statistics */ 7834 struct roce_dcqcn_sent_stats { 7835 struct regpair cnp_pkt_sent; 7836 }; 7837 7838 /* RoCE destroy qp requester output params */ 7839 struct roce_destroy_qp_req_output_params { 7840 __le32 cq_prod; 7841 __le32 reserved; 7842 }; 7843 7844 /* RoCE destroy qp requester ramrod data */ 7845 struct roce_destroy_qp_req_ramrod_data { 7846 struct regpair output_params_addr; 7847 }; 7848 7849 /* RoCE destroy qp responder output params */ 7850 struct roce_destroy_qp_resp_output_params { 7851 __le32 cq_prod; 7852 __le32 reserved; 7853 }; 7854 7855 /* RoCE destroy qp responder ramrod data */ 7856 struct roce_destroy_qp_resp_ramrod_data { 7857 struct regpair output_params_addr; 7858 __le32 src_qp_id; 7859 __le32 reserved; 7860 }; 7861 7862 /* roce error statistics */ 7863 struct roce_error_stats { 7864 __le32 resp_remote_access_errors; 7865 __le32 reserved; 7866 }; 7867 7868 /* roce special events statistics */ 7869 struct roce_events_stats { 7870 __le32 silent_drops; 7871 __le32 rnr_naks_sent; 7872 __le32 retransmit_count; 7873 __le32 icrc_error_count; 7874 __le32 implied_nak_seq_err; 7875 __le32 duplicate_request; 7876 __le32 local_ack_timeout_err; 7877 __le32 out_of_sequence; 7878 __le32 packet_seq_err; 7879 __le32 rnr_nak_retry_err; 7880 }; 7881 7882 /* roce slow path EQ cmd IDs */ 7883 enum roce_event_opcode { 7884 ROCE_EVENT_CREATE_QP = 11, 7885 ROCE_EVENT_MODIFY_QP, 7886 ROCE_EVENT_QUERY_QP, 7887 ROCE_EVENT_DESTROY_QP, 7888 ROCE_EVENT_CREATE_UD_QP, 7889 ROCE_EVENT_DESTROY_UD_QP, 7890 ROCE_EVENT_FUNC_UPDATE, 7891 MAX_ROCE_EVENT_OPCODE 7892 }; 7893 7894 /* roce func init ramrod data */ 7895 struct roce_init_func_params { 7896 u8 ll2_queue_id; 7897 u8 cnp_vlan_priority; 7898 u8 cnp_dscp; 7899 u8 flags; 7900 #define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_MASK 0x1 7901 #define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_SHIFT 0 7902 #define ROCE_INIT_FUNC_PARAMS_DCQCN_RP_EN_MASK 0x1 7903 #define ROCE_INIT_FUNC_PARAMS_DCQCN_RP_EN_SHIFT 1 7904 #define ROCE_INIT_FUNC_PARAMS_RESERVED0_MASK 0x3F 7905 #define ROCE_INIT_FUNC_PARAMS_RESERVED0_SHIFT 2 7906 __le32 cnp_send_timeout; 7907 __le16 rl_offset; 7908 u8 rl_count_log; 7909 u8 reserved1[5]; 7910 }; 7911 7912 /* roce func init ramrod data */ 7913 struct roce_init_func_ramrod_data { 7914 struct rdma_init_func_ramrod_data rdma; 7915 struct roce_init_func_params roce; 7916 }; 7917 7918 /* roce modify qp requester ramrod data */ 7919 struct roce_modify_qp_req_ramrod_data { 7920 __le16 flags; 7921 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1 7922 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0 7923 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK 0x1 7924 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT 1 7925 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK 0x1 7926 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT 2 7927 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK 0x1 7928 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT 3 7929 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1 7930 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 4 7931 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK 0x1 7932 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT 5 7933 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK 0x1 7934 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT 6 7935 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK 0x1 7936 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT 7 7937 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK 0x1 7938 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT 8 7939 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK 0x1 7940 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT 9 7941 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7 7942 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT 10 7943 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1 7944 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT 13 7945 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x3 7946 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT 14 7947 u8 fields; 7948 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF 7949 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 0 7950 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF 7951 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 4 7952 u8 max_ord; 7953 u8 traffic_class; 7954 u8 hop_limit; 7955 __le16 p_key; 7956 __le32 flow_label; 7957 __le32 ack_timeout_val; 7958 __le16 mtu; 7959 __le16 reserved2; 7960 __le32 reserved3[2]; 7961 __le16 low_latency_phy_queue; 7962 __le16 regular_latency_phy_queue; 7963 __le32 src_gid[4]; 7964 __le32 dst_gid[4]; 7965 }; 7966 7967 /* roce modify qp responder ramrod data */ 7968 struct roce_modify_qp_resp_ramrod_data { 7969 __le16 flags; 7970 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1 7971 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0 7972 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 7973 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 1 7974 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 7975 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 2 7976 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 7977 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 3 7978 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK 0x1 7979 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT 4 7980 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1 7981 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 5 7982 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK 0x1 7983 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT 6 7984 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK 0x1 7985 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT 7 7986 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK 0x1 7987 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8 7988 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1 7989 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 9 7990 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1 7991 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT 10 7992 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0x1F 7993 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT 11 7994 u8 fields; 7995 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK 0x7 7996 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT 0 7997 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F 7998 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 3 7999 u8 max_ird; 8000 u8 traffic_class; 8001 u8 hop_limit; 8002 __le16 p_key; 8003 __le32 flow_label; 8004 __le16 mtu; 8005 __le16 low_latency_phy_queue; 8006 __le16 regular_latency_phy_queue; 8007 u8 reserved2[6]; 8008 __le32 src_gid[4]; 8009 __le32 dst_gid[4]; 8010 }; 8011 8012 /* RoCE query qp requester output params */ 8013 struct roce_query_qp_req_output_params { 8014 __le32 psn; 8015 __le32 flags; 8016 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1 8017 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0 8018 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK 0x1 8019 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT 1 8020 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x3FFFFFFF 8021 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT 2 8022 }; 8023 8024 /* RoCE query qp requester ramrod data */ 8025 struct roce_query_qp_req_ramrod_data { 8026 struct regpair output_params_addr; 8027 }; 8028 8029 /* RoCE query qp responder output params */ 8030 struct roce_query_qp_resp_output_params { 8031 __le32 psn; 8032 __le32 flags; 8033 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1 8034 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0 8035 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF 8036 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1 8037 }; 8038 8039 /* RoCE query qp responder ramrod data */ 8040 struct roce_query_qp_resp_ramrod_data { 8041 struct regpair output_params_addr; 8042 }; 8043 8044 /* ROCE ramrod command IDs */ 8045 enum roce_ramrod_cmd_id { 8046 ROCE_RAMROD_CREATE_QP = 11, 8047 ROCE_RAMROD_MODIFY_QP, 8048 ROCE_RAMROD_QUERY_QP, 8049 ROCE_RAMROD_DESTROY_QP, 8050 ROCE_RAMROD_CREATE_UD_QP, 8051 ROCE_RAMROD_DESTROY_UD_QP, 8052 ROCE_RAMROD_FUNC_UPDATE, 8053 MAX_ROCE_RAMROD_CMD_ID 8054 }; 8055 8056 /* RoCE func init ramrod data */ 8057 struct roce_update_func_params { 8058 u8 cnp_vlan_priority; 8059 u8 cnp_dscp; 8060 __le16 flags; 8061 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_MASK 0x1 8062 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_SHIFT 0 8063 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_RP_EN_MASK 0x1 8064 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_RP_EN_SHIFT 1 8065 #define ROCE_UPDATE_FUNC_PARAMS_RESERVED0_MASK 0x3FFF 8066 #define ROCE_UPDATE_FUNC_PARAMS_RESERVED0_SHIFT 2 8067 __le32 cnp_send_timeout; 8068 }; 8069 8070 struct e4_xstorm_roce_conn_ag_ctx_dq_ext_ld_part { 8071 u8 reserved0; 8072 u8 state; 8073 u8 flags0; 8074 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 8075 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 8076 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1 8077 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1 8078 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1 8079 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2 8080 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 8081 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 8082 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1 8083 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4 8084 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1 8085 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5 8086 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1 8087 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6 8088 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1 8089 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7 8090 u8 flags1; 8091 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1 8092 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0 8093 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1 8094 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1 8095 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1 8096 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2 8097 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 8098 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 8099 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_MASK 0x1 8100 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_SHIFT 4 8101 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_MASK 0x1 8102 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_SHIFT 5 8103 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1 8104 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6 8105 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1 8106 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7 8107 u8 flags2; 8108 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3 8109 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0 8110 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3 8111 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2 8112 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3 8113 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4 8114 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3 8115 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6 8116 u8 flags3; 8117 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3 8118 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0 8119 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3 8120 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2 8121 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3 8122 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4 8123 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3 8124 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6 8125 u8 flags4; 8126 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3 8127 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0 8128 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3 8129 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2 8130 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3 8131 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4 8132 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3 8133 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6 8134 u8 flags5; 8135 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3 8136 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0 8137 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3 8138 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2 8139 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3 8140 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4 8141 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3 8142 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6 8143 u8 flags6; 8144 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3 8145 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0 8146 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3 8147 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2 8148 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3 8149 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4 8150 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3 8151 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6 8152 u8 flags7; 8153 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3 8154 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0 8155 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3 8156 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2 8157 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 8158 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 8159 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 8160 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 8161 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 8162 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 8163 u8 flags8; 8164 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 8165 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 8166 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 8167 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 8168 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 8169 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 8170 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 8171 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 8172 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 8173 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 8174 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1 8175 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5 8176 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 8177 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 8178 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 8179 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 8180 u8 flags9; 8181 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 8182 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 8183 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 8184 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 8185 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 8186 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 8187 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 8188 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 8189 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 8190 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 8191 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 8192 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 8193 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1 8194 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6 8195 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1 8196 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7 8197 u8 flags10; 8198 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1 8199 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0 8200 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1 8201 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1 8202 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1 8203 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2 8204 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1 8205 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3 8206 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 8207 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 8208 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1 8209 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5 8210 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1 8211 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6 8212 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1 8213 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7 8214 u8 flags11; 8215 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1 8216 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0 8217 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1 8218 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1 8219 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1 8220 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2 8221 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 8222 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 8223 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 8224 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 8225 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 8226 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 8227 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 8228 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 8229 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 8230 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 8231 u8 flags12; 8232 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 8233 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 8234 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 8235 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 8236 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 8237 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 8238 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 8239 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 8240 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 8241 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 8242 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 8243 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 8244 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 8245 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 8246 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 8247 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 8248 u8 flags13; 8249 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 8250 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 8251 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 8252 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 8253 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 8254 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 8255 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 8256 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 8257 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 8258 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 8259 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 8260 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 8261 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 8262 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 8263 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 8264 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 8265 u8 flags14; 8266 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1 8267 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0 8268 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1 8269 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1 8270 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3 8271 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2 8272 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1 8273 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4 8274 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 8275 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 8276 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3 8277 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6 8278 u8 byte2; 8279 __le16 physical_q0; 8280 __le16 word1; 8281 __le16 word2; 8282 __le16 word3; 8283 __le16 word4; 8284 __le16 word5; 8285 __le16 conn_dpi; 8286 u8 byte3; 8287 u8 byte4; 8288 u8 byte5; 8289 u8 byte6; 8290 __le32 reg0; 8291 __le32 reg1; 8292 __le32 reg2; 8293 __le32 snd_nxt_psn; 8294 __le32 reg4; 8295 }; 8296 8297 struct e4_mstorm_roce_conn_ag_ctx { 8298 u8 byte0; 8299 u8 byte1; 8300 u8 flags0; 8301 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT0_MASK 0x1 8302 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT 0 8303 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 8304 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 8305 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3 8306 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 2 8307 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3 8308 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT 4 8309 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3 8310 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 6 8311 u8 flags1; 8312 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1 8313 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 0 8314 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1 8315 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT 1 8316 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 8317 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 2 8318 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1 8319 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3 8320 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1 8321 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4 8322 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 8323 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5 8324 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1 8325 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 6 8326 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 8327 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7 8328 __le16 word0; 8329 __le16 word1; 8330 __le32 reg0; 8331 __le32 reg1; 8332 }; 8333 8334 struct e4_mstorm_roce_req_conn_ag_ctx { 8335 u8 byte0; 8336 u8 byte1; 8337 u8 flags0; 8338 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 8339 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 8340 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 8341 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 8342 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 8343 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 8344 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 8345 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 8346 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 8347 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 8348 u8 flags1; 8349 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 8350 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 8351 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 8352 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 8353 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 8354 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 8355 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 8356 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 8357 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 8358 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 8359 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 8360 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 8361 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 8362 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 8363 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 8364 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 8365 __le16 word0; 8366 __le16 word1; 8367 __le32 reg0; 8368 __le32 reg1; 8369 }; 8370 8371 struct e4_mstorm_roce_resp_conn_ag_ctx { 8372 u8 byte0; 8373 u8 byte1; 8374 u8 flags0; 8375 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 8376 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 8377 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 8378 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 8379 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 8380 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 8381 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 8382 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 8383 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 8384 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 8385 u8 flags1; 8386 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 8387 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 8388 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 8389 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 8390 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 8391 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 8392 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 8393 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 8394 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 8395 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 8396 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 8397 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 8398 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 8399 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 8400 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 8401 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 8402 __le16 word0; 8403 __le16 word1; 8404 __le32 reg0; 8405 __le32 reg1; 8406 }; 8407 8408 struct e4_tstorm_roce_req_conn_ag_ctx { 8409 u8 reserved0; 8410 u8 state; 8411 u8 flags0; 8412 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 8413 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 8414 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_MASK 0x1 8415 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_SHIFT 1 8416 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_MASK 0x1 8417 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_SHIFT 2 8418 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1 8419 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3 8420 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 8421 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 8422 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 8423 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5 8424 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3 8425 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6 8426 u8 flags1; 8427 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 8428 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 8429 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3 8430 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2 8431 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 8432 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 8433 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 8434 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 8435 u8 flags2; 8436 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_MASK 0x3 8437 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_SHIFT 0 8438 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3 8439 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2 8440 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3 8441 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4 8442 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3 8443 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6 8444 u8 flags3; 8445 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3 8446 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0 8447 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3 8448 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2 8449 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1 8450 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4 8451 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 8452 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 5 8453 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1 8454 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6 8455 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 8456 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 8457 u8 flags4; 8458 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 8459 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 8460 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_MASK 0x1 8461 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_SHIFT 1 8462 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1 8463 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2 8464 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1 8465 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3 8466 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1 8467 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4 8468 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1 8469 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5 8470 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1 8471 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6 8472 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 8473 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 8474 u8 flags5; 8475 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 8476 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 8477 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_DIF_CNT_EN_MASK 0x1 8478 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_DIF_CNT_EN_SHIFT 1 8479 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 8480 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 8481 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 8482 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 8483 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 8484 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 8485 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1 8486 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5 8487 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 8488 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 8489 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 8490 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 8491 __le32 dif_rxmit_cnt; 8492 __le32 snd_nxt_psn; 8493 __le32 snd_max_psn; 8494 __le32 orq_prod; 8495 __le32 reg4; 8496 __le32 dif_acked_cnt; 8497 __le32 dif_cnt; 8498 __le32 reg7; 8499 __le32 reg8; 8500 u8 tx_cqe_error_type; 8501 u8 orq_cache_idx; 8502 __le16 snd_sq_cons_th; 8503 u8 byte4; 8504 u8 byte5; 8505 __le16 snd_sq_cons; 8506 __le16 conn_dpi; 8507 __le16 force_comp_cons; 8508 __le32 dif_rxmit_acked_cnt; 8509 __le32 reg10; 8510 }; 8511 8512 struct e4_tstorm_roce_resp_conn_ag_ctx { 8513 u8 byte0; 8514 u8 state; 8515 u8 flags0; 8516 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 8517 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 8518 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1 8519 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1 8520 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1 8521 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2 8522 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1 8523 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3 8524 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 8525 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 8526 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1 8527 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5 8528 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 8529 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6 8530 u8 flags1; 8531 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 8532 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 8533 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3 8534 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2 8535 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 8536 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4 8537 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 8538 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 8539 u8 flags2; 8540 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 8541 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0 8542 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 8543 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2 8544 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3 8545 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4 8546 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 8547 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6 8548 u8 flags3; 8549 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 8550 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0 8551 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 8552 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2 8553 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 8554 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4 8555 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 8556 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 5 8557 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1 8558 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6 8559 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 8560 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7 8561 u8 flags4; 8562 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 8563 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 8564 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 8565 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 1 8566 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 8567 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2 8568 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1 8569 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3 8570 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 8571 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4 8572 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 8573 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5 8574 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 8575 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6 8576 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 8577 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 8578 u8 flags5; 8579 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 8580 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 8581 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 8582 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 8583 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 8584 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 8585 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 8586 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 8587 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 8588 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 8589 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1 8590 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5 8591 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 8592 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 8593 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 8594 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 8595 __le32 psn_and_rxmit_id_echo; 8596 __le32 reg1; 8597 __le32 reg2; 8598 __le32 reg3; 8599 __le32 reg4; 8600 __le32 reg5; 8601 __le32 reg6; 8602 __le32 reg7; 8603 __le32 reg8; 8604 u8 tx_async_error_type; 8605 u8 byte3; 8606 __le16 rq_cons; 8607 u8 byte4; 8608 u8 byte5; 8609 __le16 rq_prod; 8610 __le16 conn_dpi; 8611 __le16 irq_cons; 8612 __le32 reg9; 8613 __le32 reg10; 8614 }; 8615 8616 struct e4_ustorm_roce_req_conn_ag_ctx { 8617 u8 byte0; 8618 u8 byte1; 8619 u8 flags0; 8620 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 8621 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 8622 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 8623 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 8624 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 8625 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 8626 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 8627 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 8628 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 8629 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 8630 u8 flags1; 8631 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 8632 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0 8633 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3 8634 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2 8635 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3 8636 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4 8637 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3 8638 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6 8639 u8 flags2; 8640 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 8641 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 8642 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 8643 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 8644 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 8645 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 8646 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 8647 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3 8648 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1 8649 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4 8650 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1 8651 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5 8652 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1 8653 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6 8654 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 8655 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 8656 u8 flags3; 8657 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 8658 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 8659 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 8660 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1 8661 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 8662 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 8663 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 8664 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 8665 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 8666 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 8667 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 8668 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5 8669 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 8670 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 8671 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 8672 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 8673 u8 byte2; 8674 u8 byte3; 8675 __le16 word0; 8676 __le16 word1; 8677 __le32 reg0; 8678 __le32 reg1; 8679 __le32 reg2; 8680 __le32 reg3; 8681 __le16 word2; 8682 __le16 word3; 8683 }; 8684 8685 struct e4_ustorm_roce_resp_conn_ag_ctx { 8686 u8 byte0; 8687 u8 byte1; 8688 u8 flags0; 8689 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 8690 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 8691 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 8692 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 8693 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 8694 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 8695 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 8696 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 8697 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 8698 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 8699 u8 flags1; 8700 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 8701 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0 8702 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3 8703 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2 8704 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3 8705 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4 8706 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 8707 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6 8708 u8 flags2; 8709 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 8710 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 8711 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 8712 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 8713 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 8714 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 8715 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 8716 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3 8717 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1 8718 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4 8719 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1 8720 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5 8721 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 8722 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6 8723 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 8724 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 8725 u8 flags3; 8726 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 8727 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 8728 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 8729 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 8730 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 8731 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 8732 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 8733 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 8734 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 8735 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 8736 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 8737 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5 8738 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 8739 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 8740 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 8741 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 8742 u8 byte2; 8743 u8 byte3; 8744 __le16 word0; 8745 __le16 word1; 8746 __le32 reg0; 8747 __le32 reg1; 8748 __le32 reg2; 8749 __le32 reg3; 8750 __le16 word2; 8751 __le16 word3; 8752 }; 8753 8754 struct e4_xstorm_roce_req_conn_ag_ctx { 8755 u8 reserved0; 8756 u8 state; 8757 u8 flags0; 8758 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 8759 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 8760 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1 8761 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1 8762 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1 8763 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2 8764 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 8765 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 8766 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1 8767 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4 8768 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1 8769 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5 8770 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1 8771 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6 8772 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1 8773 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7 8774 u8 flags1; 8775 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1 8776 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0 8777 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1 8778 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1 8779 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1 8780 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2 8781 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1 8782 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3 8783 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1 8784 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSDM_FLUSH_SHIFT 4 8785 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1 8786 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSEM_FLUSH_SHIFT 5 8787 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1 8788 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6 8789 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 8790 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 8791 u8 flags2; 8792 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 8793 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0 8794 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 8795 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2 8796 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 8797 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4 8798 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 8799 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6 8800 u8 flags3; 8801 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 8802 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0 8803 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 8804 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 8805 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3 8806 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4 8807 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 8808 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 8809 u8 flags4; 8810 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_MASK 0x3 8811 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_SHIFT 0 8812 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_MASK 0x3 8813 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_SHIFT 2 8814 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3 8815 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4 8816 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3 8817 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6 8818 u8 flags5; 8819 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3 8820 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0 8821 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3 8822 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2 8823 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3 8824 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4 8825 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3 8826 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6 8827 u8 flags6; 8828 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3 8829 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0 8830 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3 8831 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2 8832 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3 8833 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4 8834 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3 8835 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6 8836 u8 flags7; 8837 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3 8838 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0 8839 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3 8840 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2 8841 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3 8842 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4 8843 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 8844 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6 8845 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 8846 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7 8847 u8 flags8; 8848 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 8849 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0 8850 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 8851 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1 8852 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 8853 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2 8854 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 8855 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 8856 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1 8857 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4 8858 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 8859 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 8860 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 8861 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_SHIFT 6 8862 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_MASK 0x1 8863 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_SHIFT 7 8864 u8 flags9; 8865 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1 8866 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0 8867 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1 8868 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1 8869 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1 8870 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2 8871 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1 8872 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3 8873 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1 8874 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4 8875 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1 8876 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5 8877 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1 8878 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6 8879 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1 8880 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7 8881 u8 flags10; 8882 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1 8883 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0 8884 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1 8885 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1 8886 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1 8887 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2 8888 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1 8889 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3 8890 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 8891 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 8892 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1 8893 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5 8894 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 8895 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6 8896 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 8897 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7 8898 u8 flags11; 8899 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 8900 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0 8901 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 8902 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1 8903 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 8904 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2 8905 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 8906 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3 8907 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 8908 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4 8909 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1 8910 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5 8911 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 8912 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 8913 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1 8914 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7 8915 u8 flags12; 8916 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1 8917 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0 8918 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1 8919 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1 8920 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 8921 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 8922 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 8923 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 8924 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1 8925 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4 8926 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1 8927 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5 8928 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1 8929 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6 8930 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1 8931 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7 8932 u8 flags13; 8933 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1 8934 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0 8935 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1 8936 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1 8937 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 8938 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 8939 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 8940 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 8941 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 8942 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 8943 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 8944 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 8945 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 8946 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 8947 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 8948 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 8949 u8 flags14; 8950 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1 8951 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0 8952 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1 8953 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1 8954 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 8955 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 8956 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1 8957 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4 8958 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 8959 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 8960 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3 8961 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6 8962 u8 byte2; 8963 __le16 physical_q0; 8964 __le16 word1; 8965 __le16 sq_cmp_cons; 8966 __le16 sq_cons; 8967 __le16 sq_prod; 8968 __le16 dif_error_first_sq_cons; 8969 __le16 conn_dpi; 8970 u8 dif_error_sge_index; 8971 u8 byte4; 8972 u8 byte5; 8973 u8 byte6; 8974 __le32 lsn; 8975 __le32 ssn; 8976 __le32 snd_una_psn; 8977 __le32 snd_nxt_psn; 8978 __le32 dif_error_offset; 8979 __le32 orq_cons_th; 8980 __le32 orq_cons; 8981 }; 8982 8983 struct e4_xstorm_roce_resp_conn_ag_ctx { 8984 u8 reserved0; 8985 u8 state; 8986 u8 flags0; 8987 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 8988 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 8989 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1 8990 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1 8991 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1 8992 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2 8993 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 8994 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 8995 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1 8996 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4 8997 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1 8998 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5 8999 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1 9000 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6 9001 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1 9002 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7 9003 u8 flags1; 9004 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1 9005 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0 9006 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1 9007 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1 9008 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1 9009 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2 9010 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1 9011 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3 9012 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1 9013 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSDM_FLUSH_SHIFT 4 9014 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1 9015 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSEM_FLUSH_SHIFT 5 9016 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1 9017 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6 9018 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 9019 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 9020 u8 flags2; 9021 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 9022 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0 9023 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 9024 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2 9025 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 9026 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4 9027 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 9028 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6 9029 u8 flags3; 9030 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3 9031 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0 9032 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 9033 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 9034 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3 9035 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4 9036 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 9037 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 9038 u8 flags4; 9039 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 9040 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0 9041 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 9042 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2 9043 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 9044 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4 9045 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3 9046 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6 9047 u8 flags5; 9048 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3 9049 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0 9050 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3 9051 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2 9052 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3 9053 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4 9054 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3 9055 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6 9056 u8 flags6; 9057 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3 9058 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0 9059 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3 9060 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2 9061 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3 9062 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4 9063 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3 9064 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6 9065 u8 flags7; 9066 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3 9067 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0 9068 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3 9069 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2 9070 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 9071 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4 9072 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 9073 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6 9074 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 9075 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7 9076 u8 flags8; 9077 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 9078 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0 9079 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 9080 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1 9081 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1 9082 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2 9083 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 9084 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 9085 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1 9086 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4 9087 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 9088 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 9089 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 9090 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6 9091 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 9092 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7 9093 u8 flags9; 9094 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 9095 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0 9096 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1 9097 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1 9098 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1 9099 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2 9100 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1 9101 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3 9102 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1 9103 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4 9104 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1 9105 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5 9106 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1 9107 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6 9108 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1 9109 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7 9110 u8 flags10; 9111 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1 9112 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0 9113 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1 9114 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1 9115 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1 9116 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2 9117 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1 9118 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3 9119 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 9120 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 9121 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1 9122 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5 9123 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 9124 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6 9125 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 9126 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7 9127 u8 flags11; 9128 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 9129 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0 9130 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 9131 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1 9132 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 9133 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2 9134 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 9135 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3 9136 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 9137 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4 9138 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 9139 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5 9140 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 9141 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 9142 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1 9143 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7 9144 u8 flags12; 9145 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1 9146 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 0 9147 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_MASK 0x1 9148 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_SHIFT 1 9149 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 9150 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 9151 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 9152 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 9153 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1 9154 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4 9155 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1 9156 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5 9157 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1 9158 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6 9159 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1 9160 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7 9161 u8 flags13; 9162 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1 9163 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0 9164 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1 9165 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1 9166 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 9167 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 9168 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 9169 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 9170 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 9171 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 9172 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 9173 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 9174 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 9175 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 9176 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 9177 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 9178 u8 flags14; 9179 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1 9180 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0 9181 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1 9182 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1 9183 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1 9184 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2 9185 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1 9186 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3 9187 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1 9188 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4 9189 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1 9190 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5 9191 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3 9192 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6 9193 u8 byte2; 9194 __le16 physical_q0; 9195 __le16 irq_prod_shadow; 9196 __le16 word2; 9197 __le16 irq_cons; 9198 __le16 irq_prod; 9199 __le16 e5_reserved1; 9200 __le16 conn_dpi; 9201 u8 rxmit_opcode; 9202 u8 byte4; 9203 u8 byte5; 9204 u8 byte6; 9205 __le32 rxmit_psn_and_id; 9206 __le32 rxmit_bytes_length; 9207 __le32 psn; 9208 __le32 reg3; 9209 __le32 reg4; 9210 __le32 reg5; 9211 __le32 msn_and_syndrome; 9212 }; 9213 9214 struct e4_ystorm_roce_conn_ag_ctx { 9215 u8 byte0; 9216 u8 byte1; 9217 u8 flags0; 9218 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT0_MASK 0x1 9219 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT 0 9220 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 9221 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 9222 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3 9223 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 2 9224 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3 9225 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT 4 9226 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3 9227 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 6 9228 u8 flags1; 9229 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1 9230 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 0 9231 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1 9232 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT 1 9233 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 9234 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 2 9235 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1 9236 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3 9237 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1 9238 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4 9239 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 9240 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5 9241 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1 9242 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 6 9243 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 9244 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7 9245 u8 byte2; 9246 u8 byte3; 9247 __le16 word0; 9248 __le32 reg0; 9249 __le32 reg1; 9250 __le16 word1; 9251 __le16 word2; 9252 __le16 word3; 9253 __le16 word4; 9254 __le32 reg2; 9255 __le32 reg3; 9256 }; 9257 9258 struct e4_ystorm_roce_req_conn_ag_ctx { 9259 u8 byte0; 9260 u8 byte1; 9261 u8 flags0; 9262 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 9263 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 9264 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 9265 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 9266 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 9267 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 9268 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 9269 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 9270 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 9271 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 9272 u8 flags1; 9273 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 9274 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 9275 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 9276 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 9277 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 9278 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 9279 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 9280 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 9281 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 9282 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 9283 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 9284 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 9285 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 9286 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 9287 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 9288 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 9289 u8 byte2; 9290 u8 byte3; 9291 __le16 word0; 9292 __le32 reg0; 9293 __le32 reg1; 9294 __le16 word1; 9295 __le16 word2; 9296 __le16 word3; 9297 __le16 word4; 9298 __le32 reg2; 9299 __le32 reg3; 9300 }; 9301 9302 struct e4_ystorm_roce_resp_conn_ag_ctx { 9303 u8 byte0; 9304 u8 byte1; 9305 u8 flags0; 9306 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 9307 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 9308 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 9309 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 9310 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 9311 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 9312 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 9313 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 9314 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 9315 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 9316 u8 flags1; 9317 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 9318 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 9319 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 9320 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 9321 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 9322 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 9323 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 9324 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 9325 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 9326 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 9327 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 9328 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 9329 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 9330 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 9331 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 9332 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 9333 u8 byte2; 9334 u8 byte3; 9335 __le16 word0; 9336 __le32 reg0; 9337 __le32 reg1; 9338 __le16 word1; 9339 __le16 word2; 9340 __le16 word3; 9341 __le16 word4; 9342 __le32 reg2; 9343 __le32 reg3; 9344 }; 9345 9346 /* Roce doorbell data */ 9347 enum roce_flavor { 9348 PLAIN_ROCE, 9349 RROCE_IPV4, 9350 RROCE_IPV6, 9351 MAX_ROCE_FLAVOR 9352 }; 9353 9354 /* The iwarp storm context of Ystorm */ 9355 struct ystorm_iwarp_conn_st_ctx { 9356 __le32 reserved[4]; 9357 }; 9358 9359 /* The iwarp storm context of Pstorm */ 9360 struct pstorm_iwarp_conn_st_ctx { 9361 __le32 reserved[36]; 9362 }; 9363 9364 /* The iwarp storm context of Xstorm */ 9365 struct xstorm_iwarp_conn_st_ctx { 9366 __le32 reserved[48]; 9367 }; 9368 9369 struct e4_xstorm_iwarp_conn_ag_ctx { 9370 u8 reserved0; 9371 u8 state; 9372 u8 flags0; 9373 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 9374 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 9375 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1 9376 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1 9377 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK 0x1 9378 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_SHIFT 2 9379 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 9380 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 9381 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 9382 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4 9383 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1 9384 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT 5 9385 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1 9386 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT 6 9387 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1 9388 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT 7 9389 u8 flags1; 9390 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1 9391 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT 0 9392 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1 9393 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT 1 9394 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1 9395 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT 2 9396 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1 9397 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT 3 9398 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1 9399 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT 4 9400 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1 9401 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT 5 9402 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1 9403 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT 6 9404 #define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1 9405 #define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7 9406 u8 flags2; 9407 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 9408 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 0 9409 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 9410 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 2 9411 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 9412 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 4 9413 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 9414 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6 9415 u8 flags3; 9416 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 9417 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 0 9418 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 9419 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 2 9420 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 9421 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 4 9422 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 9423 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 6 9424 u8 flags4; 9425 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 9426 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 0 9427 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3 9428 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_SHIFT 2 9429 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3 9430 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT 4 9431 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3 9432 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT 6 9433 u8 flags5; 9434 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3 9435 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT 0 9436 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3 9437 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT 2 9438 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 9439 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 4 9440 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3 9441 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT 6 9442 u8 flags6; 9443 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3 9444 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0 9445 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3 9446 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT 2 9447 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3 9448 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT 4 9449 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 9450 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT 6 9451 u8 flags7; 9452 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 9453 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 9454 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3 9455 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT 2 9456 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 9457 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT 4 9458 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 9459 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 6 9460 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 9461 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 7 9462 u8 flags8; 9463 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 9464 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 0 9465 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 9466 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1 9467 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 9468 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 2 9469 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 9470 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 3 9471 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 9472 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 4 9473 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 9474 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 5 9475 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 9476 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 6 9477 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1 9478 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT 7 9479 u8 flags9; 9480 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1 9481 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 0 9482 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1 9483 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT 1 9484 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1 9485 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT 2 9486 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1 9487 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT 3 9488 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 9489 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 4 9490 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1 9491 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT 5 9492 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1 9493 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6 9494 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1 9495 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT 7 9496 u8 flags10; 9497 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1 9498 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT 0 9499 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1 9500 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1 9501 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 9502 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 9503 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1 9504 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3 9505 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 9506 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 9507 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_MASK 0x1 9508 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_SHIFT 5 9509 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 9510 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 6 9511 #define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1 9512 #define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7 9513 u8 flags11; 9514 #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1 9515 #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0 9516 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 9517 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 1 9518 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1 9519 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT 2 9520 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 9521 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 3 9522 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1 9523 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 4 9524 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 9525 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 5 9526 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 9527 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 9528 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1 9529 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT 7 9530 u8 flags12; 9531 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1 9532 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT 0 9533 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1 9534 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT 1 9535 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 9536 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 9537 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 9538 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 9539 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1 9540 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT 4 9541 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1 9542 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT 5 9543 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1 9544 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT 6 9545 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1 9546 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT 7 9547 u8 flags13; 9548 #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1 9549 #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0 9550 #define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK 0x1 9551 #define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT 1 9552 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1 9553 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT 2 9554 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1 9555 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT 3 9556 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 9557 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 9558 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1 9559 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT 5 9560 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 9561 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 9562 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 9563 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 9564 u8 flags14; 9565 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1 9566 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT 0 9567 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1 9568 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT 1 9569 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK 0x1 9570 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_SHIFT 2 9571 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK 0x1 9572 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_SHIFT 3 9573 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 9574 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_SHIFT 4 9575 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 9576 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_SHIFT 5 9577 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_MASK 0x3 9578 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_SHIFT 6 9579 u8 byte2; 9580 __le16 physical_q0; 9581 __le16 physical_q1; 9582 __le16 sq_comp_cons; 9583 __le16 sq_tx_cons; 9584 __le16 sq_prod; 9585 __le16 word5; 9586 __le16 conn_dpi; 9587 u8 byte3; 9588 u8 byte4; 9589 u8 byte5; 9590 u8 byte6; 9591 __le32 reg0; 9592 __le32 reg1; 9593 __le32 reg2; 9594 __le32 more_to_send_seq; 9595 __le32 reg4; 9596 __le32 rewinded_snd_max_or_term_opcode; 9597 __le32 rd_msn; 9598 __le16 irq_prod_via_msdm; 9599 __le16 irq_cons; 9600 __le16 hq_cons_th_or_mpa_data; 9601 __le16 hq_cons; 9602 __le32 atom_msn; 9603 __le32 orq_cons; 9604 __le32 orq_cons_th; 9605 u8 byte7; 9606 u8 wqe_data_pad_bytes; 9607 u8 max_ord; 9608 u8 former_hq_prod; 9609 u8 irq_prod_via_msem; 9610 u8 byte12; 9611 u8 max_pkt_pdu_size_lo; 9612 u8 max_pkt_pdu_size_hi; 9613 u8 byte15; 9614 u8 e5_reserved; 9615 __le16 e5_reserved4; 9616 __le32 reg10; 9617 __le32 reg11; 9618 __le32 shared_queue_page_addr_lo; 9619 __le32 shared_queue_page_addr_hi; 9620 __le32 reg14; 9621 __le32 reg15; 9622 __le32 reg16; 9623 __le32 reg17; 9624 }; 9625 9626 struct e4_tstorm_iwarp_conn_ag_ctx { 9627 u8 reserved0; 9628 u8 state; 9629 u8 flags0; 9630 #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 9631 #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 9632 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 9633 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 9634 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1 9635 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT 2 9636 #define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_MASK 0x1 9637 #define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_SHIFT 3 9638 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 9639 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4 9640 #define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 9641 #define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT 5 9642 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 9643 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 6 9644 u8 flags1; 9645 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3 9646 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT 0 9647 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK 0x3 9648 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_SHIFT 2 9649 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 9650 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4 9651 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 9652 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 6 9653 u8 flags2; 9654 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 9655 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 0 9656 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 9657 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 2 9658 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 9659 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 4 9660 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 9661 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 6 9662 u8 flags3; 9663 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_MASK 0x3 9664 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_SHIFT 0 9665 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3 9666 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT 2 9667 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 9668 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 4 9669 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1 9670 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT 5 9671 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK 0x1 9672 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_SHIFT 6 9673 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 9674 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7 9675 u8 flags4; 9676 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 9677 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 0 9678 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 9679 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 1 9680 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 9681 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 2 9682 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 9683 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 3 9684 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 9685 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 4 9686 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_MASK 0x1 9687 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_SHIFT 5 9688 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1 9689 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT 6 9690 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 9691 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 7 9692 u8 flags5; 9693 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 9694 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 0 9695 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 9696 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1 9697 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 9698 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2 9699 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 9700 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3 9701 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 9702 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4 9703 #define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1 9704 #define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT 5 9705 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 9706 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6 9707 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1 9708 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7 9709 __le32 reg0; 9710 __le32 reg1; 9711 __le32 unaligned_nxt_seq; 9712 __le32 reg3; 9713 __le32 reg4; 9714 __le32 reg5; 9715 __le32 reg6; 9716 __le32 reg7; 9717 __le32 reg8; 9718 u8 orq_cache_idx; 9719 u8 hq_prod; 9720 __le16 sq_tx_cons_th; 9721 u8 orq_prod; 9722 u8 irq_cons; 9723 __le16 sq_tx_cons; 9724 __le16 conn_dpi; 9725 __le16 rq_prod; 9726 __le32 snd_seq; 9727 __le32 last_hq_sequence; 9728 }; 9729 9730 /* The iwarp storm context of Tstorm */ 9731 struct tstorm_iwarp_conn_st_ctx { 9732 __le32 reserved[60]; 9733 }; 9734 9735 /* The iwarp storm context of Mstorm */ 9736 struct mstorm_iwarp_conn_st_ctx { 9737 __le32 reserved[32]; 9738 }; 9739 9740 /* The iwarp storm context of Ustorm */ 9741 struct ustorm_iwarp_conn_st_ctx { 9742 struct regpair reserved[14]; 9743 }; 9744 9745 /* iwarp connection context */ 9746 struct e4_iwarp_conn_context { 9747 struct ystorm_iwarp_conn_st_ctx ystorm_st_context; 9748 struct regpair ystorm_st_padding[2]; 9749 struct pstorm_iwarp_conn_st_ctx pstorm_st_context; 9750 struct regpair pstorm_st_padding[2]; 9751 struct xstorm_iwarp_conn_st_ctx xstorm_st_context; 9752 struct e4_xstorm_iwarp_conn_ag_ctx xstorm_ag_context; 9753 struct e4_tstorm_iwarp_conn_ag_ctx tstorm_ag_context; 9754 struct timers_context timer_context; 9755 struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context; 9756 struct tstorm_iwarp_conn_st_ctx tstorm_st_context; 9757 struct regpair tstorm_st_padding[2]; 9758 struct mstorm_iwarp_conn_st_ctx mstorm_st_context; 9759 struct ustorm_iwarp_conn_st_ctx ustorm_st_context; 9760 struct regpair ustorm_st_padding[2]; 9761 }; 9762 9763 /* iWARP create QP params passed by driver to FW in CreateQP Request Ramrod */ 9764 struct iwarp_create_qp_ramrod_data { 9765 u8 flags; 9766 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1 9767 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 0 9768 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK 0x1 9769 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_SHIFT 1 9770 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 9771 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2 9772 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 9773 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3 9774 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 9775 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 4 9776 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK 0x1 9777 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_SHIFT 5 9778 #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_MASK 0x1 9779 #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_SHIFT 6 9780 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK 0x1 9781 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_SHIFT 7 9782 u8 reserved1; 9783 __le16 pd; 9784 __le16 sq_num_pages; 9785 __le16 rq_num_pages; 9786 __le32 reserved3[2]; 9787 struct regpair qp_handle_for_cqe; 9788 struct rdma_srq_id srq_id; 9789 __le32 cq_cid_for_sq; 9790 __le32 cq_cid_for_rq; 9791 __le16 dpi; 9792 __le16 physical_q0; 9793 __le16 physical_q1; 9794 u8 reserved2[6]; 9795 }; 9796 9797 /* iWARP completion queue types */ 9798 enum iwarp_eqe_async_opcode { 9799 IWARP_EVENT_TYPE_ASYNC_CONNECT_COMPLETE, 9800 IWARP_EVENT_TYPE_ASYNC_ENHANCED_MPA_REPLY_ARRIVED, 9801 IWARP_EVENT_TYPE_ASYNC_MPA_HANDSHAKE_COMPLETE, 9802 IWARP_EVENT_TYPE_ASYNC_CID_CLEANED, 9803 IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED, 9804 IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE, 9805 IWARP_EVENT_TYPE_ASYNC_CQ_OVERFLOW, 9806 IWARP_EVENT_TYPE_ASYNC_SRQ_EMPTY, 9807 IWARP_EVENT_TYPE_ASYNC_SRQ_LIMIT, 9808 MAX_IWARP_EQE_ASYNC_OPCODE 9809 }; 9810 9811 struct iwarp_eqe_data_mpa_async_completion { 9812 __le16 ulp_data_len; 9813 u8 rtr_type_sent; 9814 u8 reserved[5]; 9815 }; 9816 9817 struct iwarp_eqe_data_tcp_async_completion { 9818 __le16 ulp_data_len; 9819 u8 mpa_handshake_mode; 9820 u8 reserved[5]; 9821 }; 9822 9823 /* iWARP completion queue types */ 9824 enum iwarp_eqe_sync_opcode { 9825 IWARP_EVENT_TYPE_TCP_OFFLOAD = 9826 11, 9827 IWARP_EVENT_TYPE_MPA_OFFLOAD, 9828 IWARP_EVENT_TYPE_MPA_OFFLOAD_SEND_RTR, 9829 IWARP_EVENT_TYPE_CREATE_QP, 9830 IWARP_EVENT_TYPE_QUERY_QP, 9831 IWARP_EVENT_TYPE_MODIFY_QP, 9832 IWARP_EVENT_TYPE_DESTROY_QP, 9833 IWARP_EVENT_TYPE_ABORT_TCP_OFFLOAD, 9834 MAX_IWARP_EQE_SYNC_OPCODE 9835 }; 9836 9837 /* iWARP EQE completion status */ 9838 enum iwarp_fw_return_code { 9839 IWARP_CONN_ERROR_TCP_CONNECT_INVALID_PACKET = 6, 9840 IWARP_CONN_ERROR_TCP_CONNECTION_RST, 9841 IWARP_CONN_ERROR_TCP_CONNECT_TIMEOUT, 9842 IWARP_CONN_ERROR_MPA_ERROR_REJECT, 9843 IWARP_CONN_ERROR_MPA_NOT_SUPPORTED_VER, 9844 IWARP_CONN_ERROR_MPA_RST, 9845 IWARP_CONN_ERROR_MPA_FIN, 9846 IWARP_CONN_ERROR_MPA_RTR_MISMATCH, 9847 IWARP_CONN_ERROR_MPA_INSUF_IRD, 9848 IWARP_CONN_ERROR_MPA_INVALID_PACKET, 9849 IWARP_CONN_ERROR_MPA_LOCAL_ERROR, 9850 IWARP_CONN_ERROR_MPA_TIMEOUT, 9851 IWARP_CONN_ERROR_MPA_TERMINATE, 9852 IWARP_QP_IN_ERROR_GOOD_CLOSE, 9853 IWARP_QP_IN_ERROR_BAD_CLOSE, 9854 IWARP_EXCEPTION_DETECTED_LLP_CLOSED, 9855 IWARP_EXCEPTION_DETECTED_LLP_RESET, 9856 IWARP_EXCEPTION_DETECTED_IRQ_FULL, 9857 IWARP_EXCEPTION_DETECTED_RQ_EMPTY, 9858 IWARP_EXCEPTION_DETECTED_SRQ_EMPTY, 9859 IWARP_EXCEPTION_DETECTED_SRQ_LIMIT, 9860 IWARP_EXCEPTION_DETECTED_LLP_TIMEOUT, 9861 IWARP_EXCEPTION_DETECTED_REMOTE_PROTECTION_ERROR, 9862 IWARP_EXCEPTION_DETECTED_CQ_OVERFLOW, 9863 IWARP_EXCEPTION_DETECTED_LOCAL_CATASTROPHIC, 9864 IWARP_EXCEPTION_DETECTED_LOCAL_ACCESS_ERROR, 9865 IWARP_EXCEPTION_DETECTED_REMOTE_OPERATION_ERROR, 9866 IWARP_EXCEPTION_DETECTED_TERMINATE_RECEIVED, 9867 MAX_IWARP_FW_RETURN_CODE 9868 }; 9869 9870 /* unaligned opaque data received from LL2 */ 9871 struct iwarp_init_func_params { 9872 u8 ll2_ooo_q_index; 9873 u8 reserved1[7]; 9874 }; 9875 9876 /* iwarp func init ramrod data */ 9877 struct iwarp_init_func_ramrod_data { 9878 struct rdma_init_func_ramrod_data rdma; 9879 struct tcp_init_params tcp; 9880 struct iwarp_init_func_params iwarp; 9881 }; 9882 9883 /* iWARP QP - possible states to transition to */ 9884 enum iwarp_modify_qp_new_state_type { 9885 IWARP_MODIFY_QP_STATE_CLOSING = 1, 9886 IWARP_MODIFY_QP_STATE_ERROR = 2, 9887 MAX_IWARP_MODIFY_QP_NEW_STATE_TYPE 9888 }; 9889 9890 /* iwarp modify qp responder ramrod data */ 9891 struct iwarp_modify_qp_ramrod_data { 9892 __le16 transition_to_state; 9893 __le16 flags; 9894 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 9895 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 0 9896 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 9897 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 1 9898 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 9899 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 2 9900 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK 0x1 9901 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_SHIFT 3 9902 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1 9903 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 4 9904 #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1 9905 #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT 5 9906 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK 0x3FF 9907 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_SHIFT 6 9908 __le16 physical_q0; 9909 __le16 physical_q1; 9910 __le32 reserved1[10]; 9911 }; 9912 9913 /* MPA params for Enhanced mode */ 9914 struct mpa_rq_params { 9915 __le32 ird; 9916 __le32 ord; 9917 }; 9918 9919 /* MPA host Address-Len for private data */ 9920 struct mpa_ulp_buffer { 9921 struct regpair addr; 9922 __le16 len; 9923 __le16 reserved[3]; 9924 }; 9925 9926 /* iWARP MPA offload params common to Basic and Enhanced modes */ 9927 struct mpa_outgoing_params { 9928 u8 crc_needed; 9929 u8 reject; 9930 u8 reserved[6]; 9931 struct mpa_rq_params out_rq; 9932 struct mpa_ulp_buffer outgoing_ulp_buffer; 9933 }; 9934 9935 /* iWARP MPA offload params passed by driver to FW in MPA Offload Request 9936 * Ramrod. 9937 */ 9938 struct iwarp_mpa_offload_ramrod_data { 9939 struct mpa_outgoing_params common; 9940 __le32 tcp_cid; 9941 u8 mode; 9942 u8 tcp_connect_side; 9943 u8 rtr_pref; 9944 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_MASK 0x7 9945 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT 0 9946 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK 0x1F 9947 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_SHIFT 3 9948 u8 reserved2; 9949 struct mpa_ulp_buffer incoming_ulp_buffer; 9950 struct regpair async_eqe_output_buf; 9951 struct regpair handle_for_async; 9952 struct regpair shared_queue_addr; 9953 __le16 rcv_wnd; 9954 u8 stats_counter_id; 9955 u8 reserved3[13]; 9956 }; 9957 9958 /* iWARP TCP connection offload params passed by driver to FW */ 9959 struct iwarp_offload_params { 9960 struct mpa_ulp_buffer incoming_ulp_buffer; 9961 struct regpair async_eqe_output_buf; 9962 struct regpair handle_for_async; 9963 __le16 physical_q0; 9964 __le16 physical_q1; 9965 u8 stats_counter_id; 9966 u8 mpa_mode; 9967 u8 reserved[10]; 9968 }; 9969 9970 /* iWARP query QP output params */ 9971 struct iwarp_query_qp_output_params { 9972 __le32 flags; 9973 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1 9974 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0 9975 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF 9976 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_SHIFT 1 9977 u8 reserved1[4]; 9978 }; 9979 9980 /* iWARP query QP ramrod data */ 9981 struct iwarp_query_qp_ramrod_data { 9982 struct regpair output_params_addr; 9983 }; 9984 9985 /* iWARP Ramrod Command IDs */ 9986 enum iwarp_ramrod_cmd_id { 9987 IWARP_RAMROD_CMD_ID_TCP_OFFLOAD = 11, 9988 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD, 9989 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD_SEND_RTR, 9990 IWARP_RAMROD_CMD_ID_CREATE_QP, 9991 IWARP_RAMROD_CMD_ID_QUERY_QP, 9992 IWARP_RAMROD_CMD_ID_MODIFY_QP, 9993 IWARP_RAMROD_CMD_ID_DESTROY_QP, 9994 IWARP_RAMROD_CMD_ID_ABORT_TCP_OFFLOAD, 9995 MAX_IWARP_RAMROD_CMD_ID 9996 }; 9997 9998 /* Per PF iWARP retransmit path statistics */ 9999 struct iwarp_rxmit_stats_drv { 10000 struct regpair tx_go_to_slow_start_event_cnt; 10001 struct regpair tx_fast_retransmit_event_cnt; 10002 }; 10003 10004 /* iWARP and TCP connection offload params passed by driver to FW in iWARP 10005 * offload ramrod. 10006 */ 10007 struct iwarp_tcp_offload_ramrod_data { 10008 struct tcp_offload_params_opt2 tcp; 10009 struct iwarp_offload_params iwarp; 10010 }; 10011 10012 /* iWARP MPA negotiation types */ 10013 enum mpa_negotiation_mode { 10014 MPA_NEGOTIATION_TYPE_BASIC = 1, 10015 MPA_NEGOTIATION_TYPE_ENHANCED = 2, 10016 MAX_MPA_NEGOTIATION_MODE 10017 }; 10018 10019 /* iWARP MPA Enhanced mode RTR types */ 10020 enum mpa_rtr_type { 10021 MPA_RTR_TYPE_NONE = 0, 10022 MPA_RTR_TYPE_ZERO_SEND = 1, 10023 MPA_RTR_TYPE_ZERO_WRITE = 2, 10024 MPA_RTR_TYPE_ZERO_SEND_AND_WRITE = 3, 10025 MPA_RTR_TYPE_ZERO_READ = 4, 10026 MPA_RTR_TYPE_ZERO_SEND_AND_READ = 5, 10027 MPA_RTR_TYPE_ZERO_WRITE_AND_READ = 6, 10028 MPA_RTR_TYPE_ZERO_SEND_AND_WRITE_AND_READ = 7, 10029 MAX_MPA_RTR_TYPE 10030 }; 10031 10032 /* unaligned opaque data received from LL2 */ 10033 struct unaligned_opaque_data { 10034 __le16 first_mpa_offset; 10035 u8 tcp_payload_offset; 10036 u8 flags; 10037 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK 0x1 10038 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT 0 10039 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK 0x1 10040 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_SHIFT 1 10041 #define UNALIGNED_OPAQUE_DATA_RESERVED_MASK 0x3F 10042 #define UNALIGNED_OPAQUE_DATA_RESERVED_SHIFT 2 10043 __le32 cid; 10044 }; 10045 10046 struct e4_mstorm_iwarp_conn_ag_ctx { 10047 u8 reserved; 10048 u8 state; 10049 u8 flags0; 10050 #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 10051 #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 10052 #define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 10053 #define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 10054 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3 10055 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT 2 10056 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 10057 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 10058 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 10059 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 10060 u8 flags1; 10061 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1 10062 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0 10063 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 10064 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 10065 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 10066 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 10067 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 10068 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3 10069 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 10070 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4 10071 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 10072 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5 10073 #define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1 10074 #define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT 6 10075 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 10076 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7 10077 __le16 rcq_cons; 10078 __le16 rcq_cons_th; 10079 __le32 reg0; 10080 __le32 reg1; 10081 }; 10082 10083 struct e4_ustorm_iwarp_conn_ag_ctx { 10084 u8 reserved; 10085 u8 byte1; 10086 u8 flags0; 10087 #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 10088 #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 10089 #define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 10090 #define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 10091 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 10092 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2 10093 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 10094 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 10095 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 10096 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 10097 u8 flags1; 10098 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3 10099 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT 0 10100 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 10101 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 10102 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 10103 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 10104 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 10105 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 6 10106 u8 flags2; 10107 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 10108 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0 10109 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 10110 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 10111 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 10112 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 10113 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1 10114 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT 3 10115 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 10116 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 10117 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 10118 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 10119 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 10120 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 6 10121 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 10122 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 10123 u8 flags3; 10124 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1 10125 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT 0 10126 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 10127 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1 10128 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 10129 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2 10130 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 10131 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3 10132 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 10133 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4 10134 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1 10135 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 5 10136 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 10137 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6 10138 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1 10139 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7 10140 u8 byte2; 10141 u8 byte3; 10142 __le16 word0; 10143 __le16 word1; 10144 __le32 cq_cons; 10145 __le32 cq_se_prod; 10146 __le32 cq_prod; 10147 __le32 reg3; 10148 __le16 word2; 10149 __le16 word3; 10150 }; 10151 10152 struct e4_ystorm_iwarp_conn_ag_ctx { 10153 u8 byte0; 10154 u8 byte1; 10155 u8 flags0; 10156 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK 0x1 10157 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT 0 10158 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 10159 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 10160 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 10161 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2 10162 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 10163 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 10164 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 10165 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 10166 u8 flags1; 10167 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 10168 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0 10169 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 10170 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 10171 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 10172 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 10173 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 10174 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3 10175 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 10176 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4 10177 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 10178 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5 10179 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 10180 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 6 10181 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 10182 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7 10183 u8 byte2; 10184 u8 byte3; 10185 __le16 word0; 10186 __le32 reg0; 10187 __le32 reg1; 10188 __le16 word1; 10189 __le16 word2; 10190 __le16 word3; 10191 __le16 word4; 10192 __le32 reg2; 10193 __le32 reg3; 10194 }; 10195 10196 /* The fcoe storm context of Ystorm */ 10197 struct ystorm_fcoe_conn_st_ctx { 10198 u8 func_mode; 10199 u8 cos; 10200 u8 conf_version; 10201 u8 eth_hdr_size; 10202 __le16 stat_ram_addr; 10203 __le16 mtu; 10204 __le16 max_fc_payload_len; 10205 __le16 tx_max_fc_pay_len; 10206 u8 fcp_cmd_size; 10207 u8 fcp_rsp_size; 10208 __le16 mss; 10209 struct regpair reserved; 10210 __le16 min_frame_size; 10211 u8 protection_info_flags; 10212 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1 10213 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 0 10214 #define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1 10215 #define YSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 1 10216 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK 0x3F 10217 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_SHIFT 2 10218 u8 dst_protection_per_mss; 10219 u8 src_protection_per_mss; 10220 u8 ptu_log_page_size; 10221 u8 flags; 10222 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 10223 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 0 10224 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1 10225 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 1 10226 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x3F 10227 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 2 10228 u8 fcp_xfer_size; 10229 }; 10230 10231 /* FCoE 16-bits vlan structure */ 10232 struct fcoe_vlan_fields { 10233 __le16 fields; 10234 #define FCOE_VLAN_FIELDS_VID_MASK 0xFFF 10235 #define FCOE_VLAN_FIELDS_VID_SHIFT 0 10236 #define FCOE_VLAN_FIELDS_CLI_MASK 0x1 10237 #define FCOE_VLAN_FIELDS_CLI_SHIFT 12 10238 #define FCOE_VLAN_FIELDS_PRI_MASK 0x7 10239 #define FCOE_VLAN_FIELDS_PRI_SHIFT 13 10240 }; 10241 10242 /* FCoE 16-bits vlan union */ 10243 union fcoe_vlan_field_union { 10244 struct fcoe_vlan_fields fields; 10245 __le16 val; 10246 }; 10247 10248 /* FCoE 16-bits vlan, vif union */ 10249 union fcoe_vlan_vif_field_union { 10250 union fcoe_vlan_field_union vlan; 10251 __le16 vif; 10252 }; 10253 10254 /* Ethernet context section */ 10255 struct pstorm_fcoe_eth_context_section { 10256 u8 remote_addr_3; 10257 u8 remote_addr_2; 10258 u8 remote_addr_1; 10259 u8 remote_addr_0; 10260 u8 local_addr_1; 10261 u8 local_addr_0; 10262 u8 remote_addr_5; 10263 u8 remote_addr_4; 10264 u8 local_addr_5; 10265 u8 local_addr_4; 10266 u8 local_addr_3; 10267 u8 local_addr_2; 10268 union fcoe_vlan_vif_field_union vif_outer_vlan; 10269 __le16 vif_outer_eth_type; 10270 union fcoe_vlan_vif_field_union inner_vlan; 10271 __le16 inner_eth_type; 10272 }; 10273 10274 /* The fcoe storm context of Pstorm */ 10275 struct pstorm_fcoe_conn_st_ctx { 10276 u8 func_mode; 10277 u8 cos; 10278 u8 conf_version; 10279 u8 rsrv; 10280 __le16 stat_ram_addr; 10281 __le16 mss; 10282 struct regpair abts_cleanup_addr; 10283 struct pstorm_fcoe_eth_context_section eth; 10284 u8 sid_2; 10285 u8 sid_1; 10286 u8 sid_0; 10287 u8 flags; 10288 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1 10289 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT 0 10290 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1 10291 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT 1 10292 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 10293 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 2 10294 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1 10295 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 3 10296 #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_MASK 0x1 10297 #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_SHIFT 4 10298 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x7 10299 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 5 10300 u8 did_2; 10301 u8 did_1; 10302 u8 did_0; 10303 u8 src_mac_index; 10304 __le16 rec_rr_tov_val; 10305 u8 q_relative_offset; 10306 u8 reserved1; 10307 }; 10308 10309 /* The fcoe storm context of Xstorm */ 10310 struct xstorm_fcoe_conn_st_ctx { 10311 u8 func_mode; 10312 u8 src_mac_index; 10313 u8 conf_version; 10314 u8 cached_wqes_avail; 10315 __le16 stat_ram_addr; 10316 u8 flags; 10317 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK 0x1 10318 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT 0 10319 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 10320 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 1 10321 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK 0x1 10322 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_SHIFT 2 10323 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3 10324 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT 3 10325 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x7 10326 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 5 10327 u8 cached_wqes_offset; 10328 u8 reserved2; 10329 u8 eth_hdr_size; 10330 u8 seq_id; 10331 u8 max_conc_seqs; 10332 __le16 num_pages_in_pbl; 10333 __le16 reserved; 10334 struct regpair sq_pbl_addr; 10335 struct regpair sq_curr_page_addr; 10336 struct regpair sq_next_page_addr; 10337 struct regpair xferq_pbl_addr; 10338 struct regpair xferq_curr_page_addr; 10339 struct regpair xferq_next_page_addr; 10340 struct regpair respq_pbl_addr; 10341 struct regpair respq_curr_page_addr; 10342 struct regpair respq_next_page_addr; 10343 __le16 mtu; 10344 __le16 tx_max_fc_pay_len; 10345 __le16 max_fc_payload_len; 10346 __le16 min_frame_size; 10347 __le16 sq_pbl_next_index; 10348 __le16 respq_pbl_next_index; 10349 u8 fcp_cmd_byte_credit; 10350 u8 fcp_rsp_byte_credit; 10351 __le16 protection_info; 10352 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK 0x1 10353 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT 0 10354 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1 10355 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 1 10356 #define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1 10357 #define XSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 2 10358 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK 0x1 10359 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT 3 10360 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK 0xF 10361 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_SHIFT 4 10362 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK 0xFF 10363 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_SHIFT 8 10364 __le16 xferq_pbl_next_index; 10365 __le16 page_size; 10366 u8 mid_seq; 10367 u8 fcp_xfer_byte_credit; 10368 u8 reserved1[2]; 10369 struct fcoe_wqe cached_wqes[16]; 10370 }; 10371 10372 struct e4_xstorm_fcoe_conn_ag_ctx { 10373 u8 reserved0; 10374 u8 state; 10375 u8 flags0; 10376 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 10377 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 10378 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1 10379 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT 1 10380 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1 10381 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT 2 10382 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 10383 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 10384 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1 10385 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT 4 10386 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1 10387 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT 5 10388 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1 10389 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT 6 10390 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1 10391 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT 7 10392 u8 flags1; 10393 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1 10394 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0 10395 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1 10396 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT 1 10397 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1 10398 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT 2 10399 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1 10400 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT 3 10401 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1 10402 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT 4 10403 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1 10404 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT 5 10405 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1 10406 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT 6 10407 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1 10408 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT 7 10409 u8 flags2; 10410 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 10411 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0 10412 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 10413 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 2 10414 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 10415 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 4 10416 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3 10417 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 6 10418 u8 flags3; 10419 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 10420 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0 10421 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 10422 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 2 10423 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 10424 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 4 10425 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3 10426 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 6 10427 u8 flags4; 10428 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3 10429 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0 10430 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3 10431 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 2 10432 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3 10433 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 4 10434 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3 10435 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT 6 10436 u8 flags5; 10437 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3 10438 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0 10439 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3 10440 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT 2 10441 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3 10442 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT 4 10443 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3 10444 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT 6 10445 u8 flags6; 10446 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3 10447 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0 10448 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3 10449 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT 2 10450 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3 10451 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT 4 10452 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3 10453 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT 6 10454 u8 flags7; 10455 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 10456 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 10457 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3 10458 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT 2 10459 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 10460 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 10461 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 10462 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 6 10463 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 10464 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 7 10465 u8 flags8; 10466 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 10467 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0 10468 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 10469 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 1 10470 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 10471 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 2 10472 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 10473 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 3 10474 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 10475 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 4 10476 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 10477 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 5 10478 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 10479 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 6 10480 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 10481 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 7 10482 u8 flags9; 10483 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 10484 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0 10485 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1 10486 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT 1 10487 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1 10488 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT 2 10489 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1 10490 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT 3 10491 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1 10492 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT 4 10493 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1 10494 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT 5 10495 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1 10496 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT 6 10497 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1 10498 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT 7 10499 u8 flags10; 10500 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1 10501 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0 10502 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 10503 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT 1 10504 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 10505 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 10506 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1 10507 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT 3 10508 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 10509 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 10510 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1 10511 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT 5 10512 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1 10513 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT 6 10514 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1 10515 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT 7 10516 u8 flags11; 10517 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1 10518 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0 10519 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1 10520 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT 1 10521 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1 10522 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT 2 10523 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 10524 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 3 10525 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 10526 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 4 10527 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 10528 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 5 10529 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 10530 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 10531 #define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1 10532 #define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7 10533 u8 flags12; 10534 #define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1 10535 #define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0 10536 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1 10537 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT 1 10538 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 10539 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 10540 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 10541 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 10542 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1 10543 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT 4 10544 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1 10545 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT 5 10546 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1 10547 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT 6 10548 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1 10549 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT 7 10550 u8 flags13; 10551 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1 10552 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0 10553 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1 10554 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT 1 10555 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 10556 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 10557 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 10558 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 10559 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 10560 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 10561 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 10562 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 10563 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 10564 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 10565 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 10566 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 10567 u8 flags14; 10568 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1 10569 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0 10570 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1 10571 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT 1 10572 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1 10573 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT 2 10574 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1 10575 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT 3 10576 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1 10577 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT 4 10578 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1 10579 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT 5 10580 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3 10581 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT 6 10582 u8 byte2; 10583 __le16 physical_q0; 10584 __le16 word1; 10585 __le16 word2; 10586 __le16 sq_cons; 10587 __le16 sq_prod; 10588 __le16 xferq_prod; 10589 __le16 xferq_cons; 10590 u8 byte3; 10591 u8 byte4; 10592 u8 byte5; 10593 u8 byte6; 10594 __le32 remain_io; 10595 __le32 reg1; 10596 __le32 reg2; 10597 __le32 reg3; 10598 __le32 reg4; 10599 __le32 reg5; 10600 __le32 reg6; 10601 __le16 respq_prod; 10602 __le16 respq_cons; 10603 __le16 word9; 10604 __le16 word10; 10605 __le32 reg7; 10606 __le32 reg8; 10607 }; 10608 10609 /* The fcoe storm context of Ustorm */ 10610 struct ustorm_fcoe_conn_st_ctx { 10611 struct regpair respq_pbl_addr; 10612 __le16 num_pages_in_pbl; 10613 u8 ptu_log_page_size; 10614 u8 log_page_size; 10615 __le16 respq_prod; 10616 u8 reserved[2]; 10617 }; 10618 10619 struct e4_tstorm_fcoe_conn_ag_ctx { 10620 u8 reserved0; 10621 u8 state; 10622 u8 flags0; 10623 #define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 10624 #define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 10625 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 10626 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 10627 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1 10628 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT 2 10629 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1 10630 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT 3 10631 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1 10632 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT 4 10633 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1 10634 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT 5 10635 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3 10636 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT 6 10637 u8 flags1; 10638 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 10639 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0 10640 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 10641 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 2 10642 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 10643 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 10644 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 10645 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 6 10646 u8 flags2; 10647 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 10648 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0 10649 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 10650 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 2 10651 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3 10652 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 4 10653 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3 10654 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 6 10655 u8 flags3; 10656 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3 10657 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0 10658 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3 10659 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 2 10660 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1 10661 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT 4 10662 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 10663 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 10664 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 10665 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 6 10666 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 10667 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 10668 u8 flags4; 10669 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 10670 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0 10671 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 10672 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 1 10673 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 10674 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 2 10675 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 10676 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 3 10677 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 10678 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 4 10679 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 10680 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 5 10681 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 10682 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 6 10683 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 10684 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7 10685 u8 flags5; 10686 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 10687 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0 10688 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 10689 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1 10690 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 10691 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2 10692 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 10693 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3 10694 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 10695 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4 10696 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 10697 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5 10698 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 10699 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6 10700 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 10701 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7 10702 __le32 reg0; 10703 __le32 reg1; 10704 }; 10705 10706 struct e4_ustorm_fcoe_conn_ag_ctx { 10707 u8 byte0; 10708 u8 byte1; 10709 u8 flags0; 10710 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 10711 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 10712 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 10713 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 10714 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 10715 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 10716 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 10717 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 10718 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 10719 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 10720 u8 flags1; 10721 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3 10722 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0 10723 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 10724 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 2 10725 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 10726 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 4 10727 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 10728 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 6 10729 u8 flags2; 10730 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 10731 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 10732 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 10733 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 10734 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 10735 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 10736 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 10737 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 3 10738 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 10739 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 4 10740 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 10741 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 5 10742 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 10743 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 6 10744 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 10745 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7 10746 u8 flags3; 10747 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 10748 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0 10749 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 10750 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1 10751 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 10752 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2 10753 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 10754 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3 10755 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 10756 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4 10757 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 10758 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5 10759 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 10760 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6 10761 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 10762 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7 10763 u8 byte2; 10764 u8 byte3; 10765 __le16 word0; 10766 __le16 word1; 10767 __le32 reg0; 10768 __le32 reg1; 10769 __le32 reg2; 10770 __le32 reg3; 10771 __le16 word2; 10772 __le16 word3; 10773 }; 10774 10775 /* The fcoe storm context of Tstorm */ 10776 struct tstorm_fcoe_conn_st_ctx { 10777 __le16 stat_ram_addr; 10778 __le16 rx_max_fc_payload_len; 10779 __le16 e_d_tov_val; 10780 u8 flags; 10781 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK 0x1 10782 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT 0 10783 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK 0x1 10784 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT 1 10785 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK 0x3F 10786 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT 2 10787 u8 timers_cleanup_invocation_cnt; 10788 __le32 reserved1[2]; 10789 __le32 dst_mac_address_bytes_0_to_3; 10790 __le16 dst_mac_address_bytes_4_to_5; 10791 __le16 ramrod_echo; 10792 u8 flags1; 10793 #define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK 0x3 10794 #define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT 0 10795 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x3F 10796 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 2 10797 u8 cq_relative_offset; 10798 u8 cmdq_relative_offset; 10799 u8 bdq_resource_id; 10800 u8 reserved0[4]; 10801 }; 10802 10803 struct e4_mstorm_fcoe_conn_ag_ctx { 10804 u8 byte0; 10805 u8 byte1; 10806 u8 flags0; 10807 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 10808 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 10809 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 10810 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 10811 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 10812 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 10813 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 10814 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 10815 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 10816 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 10817 u8 flags1; 10818 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 10819 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 10820 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 10821 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 10822 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 10823 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 10824 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 10825 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3 10826 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 10827 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4 10828 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 10829 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5 10830 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 10831 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6 10832 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 10833 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7 10834 __le16 word0; 10835 __le16 word1; 10836 __le32 reg0; 10837 __le32 reg1; 10838 }; 10839 10840 /* Fast path part of the fcoe storm context of Mstorm */ 10841 struct fcoe_mstorm_fcoe_conn_st_ctx_fp { 10842 __le16 xfer_prod; 10843 u8 num_cqs; 10844 u8 reserved1; 10845 u8 protection_info; 10846 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK 0x1 10847 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_SHIFT 0 10848 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK 0x1 10849 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_SHIFT 1 10850 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_MASK 0x3F 10851 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_SHIFT 2 10852 u8 q_relative_offset; 10853 u8 reserved2[2]; 10854 }; 10855 10856 /* Non fast path part of the fcoe storm context of Mstorm */ 10857 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp { 10858 __le16 conn_id; 10859 __le16 stat_ram_addr; 10860 __le16 num_pages_in_pbl; 10861 u8 ptu_log_page_size; 10862 u8 log_page_size; 10863 __le16 unsolicited_cq_count; 10864 __le16 cmdq_count; 10865 u8 bdq_resource_id; 10866 u8 reserved0[3]; 10867 struct regpair xferq_pbl_addr; 10868 struct regpair reserved1; 10869 struct regpair reserved2[3]; 10870 }; 10871 10872 /* The fcoe storm context of Mstorm */ 10873 struct mstorm_fcoe_conn_st_ctx { 10874 struct fcoe_mstorm_fcoe_conn_st_ctx_fp fp; 10875 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp non_fp; 10876 }; 10877 10878 /* fcoe connection context */ 10879 struct e4_fcoe_conn_context { 10880 struct ystorm_fcoe_conn_st_ctx ystorm_st_context; 10881 struct pstorm_fcoe_conn_st_ctx pstorm_st_context; 10882 struct regpair pstorm_st_padding[2]; 10883 struct xstorm_fcoe_conn_st_ctx xstorm_st_context; 10884 struct e4_xstorm_fcoe_conn_ag_ctx xstorm_ag_context; 10885 struct regpair xstorm_ag_padding[6]; 10886 struct ustorm_fcoe_conn_st_ctx ustorm_st_context; 10887 struct regpair ustorm_st_padding[2]; 10888 struct e4_tstorm_fcoe_conn_ag_ctx tstorm_ag_context; 10889 struct regpair tstorm_ag_padding[2]; 10890 struct timers_context timer_context; 10891 struct e4_ustorm_fcoe_conn_ag_ctx ustorm_ag_context; 10892 struct tstorm_fcoe_conn_st_ctx tstorm_st_context; 10893 struct e4_mstorm_fcoe_conn_ag_ctx mstorm_ag_context; 10894 struct mstorm_fcoe_conn_st_ctx mstorm_st_context; 10895 }; 10896 10897 /* FCoE connection offload params passed by driver to FW in FCoE offload 10898 * ramrod. 10899 */ 10900 struct fcoe_conn_offload_ramrod_params { 10901 struct fcoe_conn_offload_ramrod_data offload_ramrod_data; 10902 }; 10903 10904 /* FCoE connection terminate params passed by driver to FW in FCoE terminate 10905 * conn ramrod. 10906 */ 10907 struct fcoe_conn_terminate_ramrod_params { 10908 struct fcoe_conn_terminate_ramrod_data terminate_ramrod_data; 10909 }; 10910 10911 /* FCoE event type */ 10912 enum fcoe_event_type { 10913 FCOE_EVENT_INIT_FUNC, 10914 FCOE_EVENT_DESTROY_FUNC, 10915 FCOE_EVENT_STAT_FUNC, 10916 FCOE_EVENT_OFFLOAD_CONN, 10917 FCOE_EVENT_TERMINATE_CONN, 10918 FCOE_EVENT_ERROR, 10919 MAX_FCOE_EVENT_TYPE 10920 }; 10921 10922 /* FCoE init params passed by driver to FW in FCoE init ramrod */ 10923 struct fcoe_init_ramrod_params { 10924 struct fcoe_init_func_ramrod_data init_ramrod_data; 10925 }; 10926 10927 /* FCoE ramrod Command IDs */ 10928 enum fcoe_ramrod_cmd_id { 10929 FCOE_RAMROD_CMD_ID_INIT_FUNC, 10930 FCOE_RAMROD_CMD_ID_DESTROY_FUNC, 10931 FCOE_RAMROD_CMD_ID_STAT_FUNC, 10932 FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, 10933 FCOE_RAMROD_CMD_ID_TERMINATE_CONN, 10934 MAX_FCOE_RAMROD_CMD_ID 10935 }; 10936 10937 /* FCoE statistics params buffer passed by driver to FW in FCoE statistics 10938 * ramrod. 10939 */ 10940 struct fcoe_stat_ramrod_params { 10941 struct fcoe_stat_ramrod_data stat_ramrod_data; 10942 }; 10943 10944 struct e4_ystorm_fcoe_conn_ag_ctx { 10945 u8 byte0; 10946 u8 byte1; 10947 u8 flags0; 10948 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 10949 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 10950 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 10951 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 10952 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 10953 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 10954 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 10955 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 10956 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 10957 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 10958 u8 flags1; 10959 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 10960 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 10961 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 10962 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 10963 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 10964 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 10965 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 10966 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3 10967 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 10968 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4 10969 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 10970 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5 10971 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 10972 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6 10973 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 10974 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7 10975 u8 byte2; 10976 u8 byte3; 10977 __le16 word0; 10978 __le32 reg0; 10979 __le32 reg1; 10980 __le16 word1; 10981 __le16 word2; 10982 __le16 word3; 10983 __le16 word4; 10984 __le32 reg2; 10985 __le32 reg3; 10986 }; 10987 10988 /* The iscsi storm connection context of Ystorm */ 10989 struct ystorm_iscsi_conn_st_ctx { 10990 __le32 reserved[8]; 10991 }; 10992 10993 /* Combined iSCSI and TCP storm connection of Pstorm */ 10994 struct pstorm_iscsi_tcp_conn_st_ctx { 10995 __le32 tcp[32]; 10996 __le32 iscsi[4]; 10997 }; 10998 10999 /* The combined tcp and iscsi storm context of Xstorm */ 11000 struct xstorm_iscsi_tcp_conn_st_ctx { 11001 __le32 reserved_tcp[4]; 11002 __le32 reserved_iscsi[44]; 11003 }; 11004 11005 struct e4_xstorm_iscsi_conn_ag_ctx { 11006 u8 cdu_validation; 11007 u8 state; 11008 u8 flags0; 11009 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 11010 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 11011 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1 11012 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1 11013 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1 11014 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_SHIFT 2 11015 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 11016 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 11017 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1 11018 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4 11019 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1 11020 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_SHIFT 5 11021 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1 11022 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_SHIFT 6 11023 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1 11024 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_SHIFT 7 11025 u8 flags1; 11026 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1 11027 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT 0 11028 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK 0x1 11029 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT9_SHIFT 1 11030 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK 0x1 11031 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT10_SHIFT 2 11032 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK 0x1 11033 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT11_SHIFT 3 11034 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK 0x1 11035 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT12_SHIFT 4 11036 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK 0x1 11037 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT13_SHIFT 5 11038 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK 0x1 11039 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT14_SHIFT 6 11040 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK 0x1 11041 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_SHIFT 7 11042 u8 flags2; 11043 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 11044 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 0 11045 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 11046 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 2 11047 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 11048 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 4 11049 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 11050 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6 11051 u8 flags3; 11052 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3 11053 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 0 11054 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3 11055 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 2 11056 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3 11057 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 4 11058 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3 11059 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 6 11060 u8 flags4; 11061 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3 11062 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 0 11063 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3 11064 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9_SHIFT 2 11065 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3 11066 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 4 11067 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK 0x3 11068 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11_SHIFT 6 11069 u8 flags5; 11070 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK 0x3 11071 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT 0 11072 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK 0x3 11073 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13_SHIFT 2 11074 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK 0x3 11075 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14_SHIFT 4 11076 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK 0x3 11077 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_SHIFT 6 11078 u8 flags6; 11079 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK 0x3 11080 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT 0 11081 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK 0x3 11082 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17_SHIFT 2 11083 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK 0x3 11084 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18_SHIFT 4 11085 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 11086 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_SHIFT 6 11087 u8 flags7; 11088 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK 0x3 11089 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_SHIFT 0 11090 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK 0x3 11091 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_SHIFT 2 11092 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK 0x3 11093 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_SHIFT 4 11094 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 11095 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 6 11096 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 11097 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 7 11098 u8 flags8; 11099 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 11100 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 0 11101 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 11102 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1 11103 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1 11104 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 2 11105 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1 11106 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 3 11107 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1 11108 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 4 11109 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1 11110 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 5 11111 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1 11112 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 6 11113 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK 0x1 11114 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9EN_SHIFT 7 11115 u8 flags9; 11116 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1 11117 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 0 11118 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK 0x1 11119 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11EN_SHIFT 1 11120 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK 0x1 11121 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12EN_SHIFT 2 11122 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK 0x1 11123 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13EN_SHIFT 3 11124 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK 0x1 11125 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14EN_SHIFT 4 11126 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK 0x1 11127 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_SHIFT 5 11128 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK 0x1 11129 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16EN_SHIFT 6 11130 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK 0x1 11131 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17EN_SHIFT 7 11132 u8 flags10; 11133 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK 0x1 11134 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT 0 11135 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1 11136 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1 11137 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK 0x1 11138 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_SHIFT 2 11139 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK 0x1 11140 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_SHIFT 3 11141 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 11142 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 11143 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK 0x1 11144 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_SHIFT 5 11145 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 11146 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 6 11147 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK 0x1 11148 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_SHIFT 7 11149 u8 flags11; 11150 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1 11151 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0 11152 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 11153 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 1 11154 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK 0x1 11155 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_SHIFT 2 11156 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1 11157 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 3 11158 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1 11159 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 4 11160 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1 11161 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 5 11162 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 11163 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 11164 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK 0x1 11165 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_SHIFT 7 11166 u8 flags12; 11167 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK 0x1 11168 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT 0 11169 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK 0x1 11170 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_SHIFT 1 11171 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 11172 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 11173 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 11174 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 11175 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK 0x1 11176 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_SHIFT 4 11177 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK 0x1 11178 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_SHIFT 5 11179 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK 0x1 11180 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_SHIFT 6 11181 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK 0x1 11182 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_SHIFT 7 11183 u8 flags13; 11184 #define E4_XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK 0x1 11185 #define E4_XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT 0 11186 #define E4_XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK 0x1 11187 #define E4_XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_SHIFT 1 11188 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 11189 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 11190 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 11191 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 11192 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 11193 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 11194 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 11195 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 11196 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 11197 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 11198 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 11199 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 11200 u8 flags14; 11201 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK 0x1 11202 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT 0 11203 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK 0x1 11204 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT17_SHIFT 1 11205 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK 0x1 11206 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT18_SHIFT 2 11207 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK 0x1 11208 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT19_SHIFT 3 11209 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK 0x1 11210 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT20_SHIFT 4 11211 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK 0x1 11212 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_SHIFT 5 11213 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK 0x3 11214 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_SHIFT 6 11215 u8 byte2; 11216 __le16 physical_q0; 11217 __le16 physical_q1; 11218 __le16 dummy_dorq_var; 11219 __le16 sq_cons; 11220 __le16 sq_prod; 11221 __le16 word5; 11222 __le16 slow_io_total_data_tx_update; 11223 u8 byte3; 11224 u8 byte4; 11225 u8 byte5; 11226 u8 byte6; 11227 __le32 reg0; 11228 __le32 reg1; 11229 __le32 reg2; 11230 __le32 more_to_send_seq; 11231 __le32 reg4; 11232 __le32 reg5; 11233 __le32 hq_scan_next_relevant_ack; 11234 __le16 r2tq_prod; 11235 __le16 r2tq_cons; 11236 __le16 hq_prod; 11237 __le16 hq_cons; 11238 __le32 remain_seq; 11239 __le32 bytes_to_next_pdu; 11240 __le32 hq_tcp_seq; 11241 u8 byte7; 11242 u8 byte8; 11243 u8 byte9; 11244 u8 byte10; 11245 u8 byte11; 11246 u8 byte12; 11247 u8 byte13; 11248 u8 byte14; 11249 u8 byte15; 11250 u8 e5_reserved; 11251 __le16 word11; 11252 __le32 reg10; 11253 __le32 reg11; 11254 __le32 exp_stat_sn; 11255 __le32 ongoing_fast_rxmit_seq; 11256 __le32 reg14; 11257 __le32 reg15; 11258 __le32 reg16; 11259 __le32 reg17; 11260 }; 11261 11262 struct e4_tstorm_iscsi_conn_ag_ctx { 11263 u8 reserved0; 11264 u8 state; 11265 u8 flags0; 11266 #define E4_TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 11267 #define E4_TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 11268 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 11269 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 11270 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK 0x1 11271 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT2_SHIFT 2 11272 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK 0x1 11273 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT3_SHIFT 3 11274 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1 11275 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4 11276 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK 0x1 11277 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT5_SHIFT 5 11278 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 11279 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 6 11280 u8 flags1; 11281 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK 0x3 11282 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_SHIFT 0 11283 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK 0x3 11284 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_SHIFT 2 11285 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 11286 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4 11287 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3 11288 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 6 11289 u8 flags2; 11290 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3 11291 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 0 11292 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3 11293 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 2 11294 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3 11295 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 4 11296 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3 11297 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 6 11298 u8 flags3; 11299 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 11300 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 11301 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_MASK 0x3 11302 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_SHIFT 2 11303 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 11304 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 4 11305 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK 0x1 11306 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_SHIFT 5 11307 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK 0x1 11308 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_SHIFT 6 11309 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 11310 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7 11311 u8 flags4; 11312 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1 11313 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 0 11314 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1 11315 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 1 11316 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1 11317 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 2 11318 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1 11319 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 3 11320 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1 11321 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 4 11322 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 11323 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5 11324 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_EN_MASK 0x1 11325 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_EN_SHIFT 6 11326 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 11327 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7 11328 u8 flags5; 11329 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 11330 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0 11331 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 11332 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1 11333 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 11334 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2 11335 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 11336 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3 11337 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1 11338 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4 11339 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1 11340 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5 11341 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1 11342 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6 11343 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1 11344 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7 11345 __le32 reg0; 11346 __le32 reg1; 11347 __le32 rx_tcp_checksum_err_cnt; 11348 __le32 reg3; 11349 __le32 reg4; 11350 __le32 reg5; 11351 __le32 reg6; 11352 __le32 reg7; 11353 __le32 reg8; 11354 u8 cid_offload_cnt; 11355 u8 byte3; 11356 __le16 word0; 11357 }; 11358 11359 struct e4_ustorm_iscsi_conn_ag_ctx { 11360 u8 byte0; 11361 u8 byte1; 11362 u8 flags0; 11363 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1 11364 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0 11365 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 11366 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 11367 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 11368 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2 11369 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 11370 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4 11371 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 11372 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6 11373 u8 flags1; 11374 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3_MASK 0x3 11375 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT 0 11376 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3 11377 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 2 11378 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3 11379 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 4 11380 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3 11381 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 6 11382 u8 flags2; 11383 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 11384 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0 11385 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 11386 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1 11387 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 11388 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2 11389 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK 0x1 11390 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3EN_SHIFT 3 11391 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1 11392 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 4 11393 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1 11394 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 5 11395 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1 11396 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 6 11397 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 11398 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7 11399 u8 flags3; 11400 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 11401 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0 11402 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 11403 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1 11404 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 11405 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2 11406 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 11407 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3 11408 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1 11409 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4 11410 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1 11411 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5 11412 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1 11413 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6 11414 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1 11415 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7 11416 u8 byte2; 11417 u8 byte3; 11418 __le16 word0; 11419 __le16 word1; 11420 __le32 reg0; 11421 __le32 reg1; 11422 __le32 reg2; 11423 __le32 reg3; 11424 __le16 word2; 11425 __le16 word3; 11426 }; 11427 11428 /* The iscsi storm connection context of Tstorm */ 11429 struct tstorm_iscsi_conn_st_ctx { 11430 __le32 reserved[44]; 11431 }; 11432 11433 struct e4_mstorm_iscsi_conn_ag_ctx { 11434 u8 reserved; 11435 u8 state; 11436 u8 flags0; 11437 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1 11438 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0 11439 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 11440 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 11441 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 11442 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2 11443 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 11444 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4 11445 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 11446 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6 11447 u8 flags1; 11448 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 11449 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0 11450 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 11451 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1 11452 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 11453 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2 11454 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 11455 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3 11456 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 11457 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4 11458 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 11459 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5 11460 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 11461 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6 11462 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 11463 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7 11464 __le16 word0; 11465 __le16 word1; 11466 __le32 reg0; 11467 __le32 reg1; 11468 }; 11469 11470 /* Combined iSCSI and TCP storm connection of Mstorm */ 11471 struct mstorm_iscsi_tcp_conn_st_ctx { 11472 __le32 reserved_tcp[20]; 11473 __le32 reserved_iscsi[12]; 11474 }; 11475 11476 /* The iscsi storm context of Ustorm */ 11477 struct ustorm_iscsi_conn_st_ctx { 11478 __le32 reserved[52]; 11479 }; 11480 11481 /* iscsi connection context */ 11482 struct e4_iscsi_conn_context { 11483 struct ystorm_iscsi_conn_st_ctx ystorm_st_context; 11484 struct pstorm_iscsi_tcp_conn_st_ctx pstorm_st_context; 11485 struct regpair pstorm_st_padding[2]; 11486 struct pb_context xpb2_context; 11487 struct xstorm_iscsi_tcp_conn_st_ctx xstorm_st_context; 11488 struct regpair xstorm_st_padding[2]; 11489 struct e4_xstorm_iscsi_conn_ag_ctx xstorm_ag_context; 11490 struct e4_tstorm_iscsi_conn_ag_ctx tstorm_ag_context; 11491 struct regpair tstorm_ag_padding[2]; 11492 struct timers_context timer_context; 11493 struct e4_ustorm_iscsi_conn_ag_ctx ustorm_ag_context; 11494 struct pb_context upb_context; 11495 struct tstorm_iscsi_conn_st_ctx tstorm_st_context; 11496 struct regpair tstorm_st_padding[2]; 11497 struct e4_mstorm_iscsi_conn_ag_ctx mstorm_ag_context; 11498 struct mstorm_iscsi_tcp_conn_st_ctx mstorm_st_context; 11499 struct ustorm_iscsi_conn_st_ctx ustorm_st_context; 11500 }; 11501 11502 /* iSCSI init params passed by driver to FW in iSCSI init ramrod */ 11503 struct iscsi_init_ramrod_params { 11504 struct iscsi_spe_func_init iscsi_init_spe; 11505 struct tcp_init_params tcp_init; 11506 }; 11507 11508 struct e4_ystorm_iscsi_conn_ag_ctx { 11509 u8 byte0; 11510 u8 byte1; 11511 u8 flags0; 11512 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1 11513 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0 11514 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 11515 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 11516 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 11517 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2 11518 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 11519 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4 11520 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 11521 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6 11522 u8 flags1; 11523 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 11524 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0 11525 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 11526 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1 11527 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 11528 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2 11529 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 11530 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3 11531 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 11532 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4 11533 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 11534 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5 11535 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 11536 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6 11537 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 11538 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7 11539 u8 byte2; 11540 u8 byte3; 11541 __le16 word0; 11542 __le32 reg0; 11543 __le32 reg1; 11544 __le16 word1; 11545 __le16 word2; 11546 __le16 word3; 11547 __le16 word4; 11548 __le32 reg2; 11549 __le32 reg3; 11550 }; 11551 11552 #define MFW_TRACE_SIGNATURE 0x25071946 11553 11554 /* The trace in the buffer */ 11555 #define MFW_TRACE_EVENTID_MASK 0x00ffff 11556 #define MFW_TRACE_PRM_SIZE_MASK 0x0f0000 11557 #define MFW_TRACE_PRM_SIZE_OFFSET 16 11558 #define MFW_TRACE_ENTRY_SIZE 3 11559 11560 struct mcp_trace { 11561 u32 signature; /* Help to identify that the trace is valid */ 11562 u32 size; /* the size of the trace buffer in bytes */ 11563 u32 curr_level; /* 2 - all will be written to the buffer 11564 * 1 - debug trace will not be written 11565 * 0 - just errors will be written to the buffer 11566 */ 11567 u32 modules_mask[2]; /* a bit per module, 1 means write it, 0 means 11568 * mask it. 11569 */ 11570 11571 /* Warning: the following pointers are assumed to be 32bits as they are 11572 * used only in the MFW. 11573 */ 11574 u32 trace_prod; /* The next trace will be written to this offset */ 11575 u32 trace_oldest; /* The oldest valid trace starts at this offset 11576 * (usually very close after the current producer). 11577 */ 11578 }; 11579 11580 #define VF_MAX_STATIC 192 11581 11582 #define MCP_GLOB_PATH_MAX 2 11583 #define MCP_PORT_MAX 2 11584 #define MCP_GLOB_PORT_MAX 4 11585 #define MCP_GLOB_FUNC_MAX 16 11586 11587 typedef u32 offsize_t; /* In DWORDS !!! */ 11588 /* Offset from the beginning of the MCP scratchpad */ 11589 #define OFFSIZE_OFFSET_SHIFT 0 11590 #define OFFSIZE_OFFSET_MASK 0x0000ffff 11591 /* Size of specific element (not the whole array if any) */ 11592 #define OFFSIZE_SIZE_SHIFT 16 11593 #define OFFSIZE_SIZE_MASK 0xffff0000 11594 11595 #define SECTION_OFFSET(_offsize) ((((_offsize & \ 11596 OFFSIZE_OFFSET_MASK) >> \ 11597 OFFSIZE_OFFSET_SHIFT) << 2)) 11598 11599 #define QED_SECTION_SIZE(_offsize) (((_offsize & \ 11600 OFFSIZE_SIZE_MASK) >> \ 11601 OFFSIZE_SIZE_SHIFT) << 2) 11602 11603 #define SECTION_ADDR(_offsize, idx) (MCP_REG_SCRATCH + \ 11604 SECTION_OFFSET(_offsize) + \ 11605 (QED_SECTION_SIZE(_offsize) * idx)) 11606 11607 #define SECTION_OFFSIZE_ADDR(_pub_base, _section) \ 11608 (_pub_base + offsetof(struct mcp_public_data, sections[_section])) 11609 11610 /* PHY configuration */ 11611 struct eth_phy_cfg { 11612 u32 speed; 11613 #define ETH_SPEED_AUTONEG 0 11614 #define ETH_SPEED_SMARTLINQ 0x8 11615 11616 u32 pause; 11617 #define ETH_PAUSE_NONE 0x0 11618 #define ETH_PAUSE_AUTONEG 0x1 11619 #define ETH_PAUSE_RX 0x2 11620 #define ETH_PAUSE_TX 0x4 11621 11622 u32 adv_speed; 11623 u32 loopback_mode; 11624 #define ETH_LOOPBACK_NONE (0) 11625 #define ETH_LOOPBACK_INT_PHY (1) 11626 #define ETH_LOOPBACK_EXT_PHY (2) 11627 #define ETH_LOOPBACK_EXT (3) 11628 #define ETH_LOOPBACK_MAC (4) 11629 11630 u32 eee_cfg; 11631 #define EEE_CFG_EEE_ENABLED BIT(0) 11632 #define EEE_CFG_TX_LPI BIT(1) 11633 #define EEE_CFG_ADV_SPEED_1G BIT(2) 11634 #define EEE_CFG_ADV_SPEED_10G BIT(3) 11635 #define EEE_TX_TIMER_USEC_MASK (0xfffffff0) 11636 #define EEE_TX_TIMER_USEC_OFFSET 4 11637 #define EEE_TX_TIMER_USEC_BALANCED_TIME (0xa00) 11638 #define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME (0x100) 11639 #define EEE_TX_TIMER_USEC_LATENCY_TIME (0x6000) 11640 11641 u32 feature_config_flags; 11642 #define ETH_EEE_MODE_ADV_LPI (1 << 0) 11643 }; 11644 11645 struct port_mf_cfg { 11646 u32 dynamic_cfg; 11647 #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff 11648 #define PORT_MF_CFG_OV_TAG_SHIFT 0 11649 #define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK 11650 11651 u32 reserved[1]; 11652 }; 11653 11654 struct eth_stats { 11655 u64 r64; 11656 u64 r127; 11657 u64 r255; 11658 u64 r511; 11659 u64 r1023; 11660 u64 r1518; 11661 11662 union { 11663 struct { 11664 u64 r1522; 11665 u64 r2047; 11666 u64 r4095; 11667 u64 r9216; 11668 u64 r16383; 11669 } bb0; 11670 struct { 11671 u64 unused1; 11672 u64 r1519_to_max; 11673 u64 unused2; 11674 u64 unused3; 11675 u64 unused4; 11676 } ah0; 11677 } u0; 11678 11679 u64 rfcs; 11680 u64 rxcf; 11681 u64 rxpf; 11682 u64 rxpp; 11683 u64 raln; 11684 u64 rfcr; 11685 u64 rovr; 11686 u64 rjbr; 11687 u64 rund; 11688 u64 rfrg; 11689 u64 t64; 11690 u64 t127; 11691 u64 t255; 11692 u64 t511; 11693 u64 t1023; 11694 u64 t1518; 11695 11696 union { 11697 struct { 11698 u64 t2047; 11699 u64 t4095; 11700 u64 t9216; 11701 u64 t16383; 11702 } bb1; 11703 struct { 11704 u64 t1519_to_max; 11705 u64 unused6; 11706 u64 unused7; 11707 u64 unused8; 11708 } ah1; 11709 } u1; 11710 11711 u64 txpf; 11712 u64 txpp; 11713 11714 union { 11715 struct { 11716 u64 tlpiec; 11717 u64 tncl; 11718 } bb2; 11719 struct { 11720 u64 unused9; 11721 u64 unused10; 11722 } ah2; 11723 } u2; 11724 11725 u64 rbyte; 11726 u64 rxuca; 11727 u64 rxmca; 11728 u64 rxbca; 11729 u64 rxpok; 11730 u64 tbyte; 11731 u64 txuca; 11732 u64 txmca; 11733 u64 txbca; 11734 u64 txcf; 11735 }; 11736 11737 struct brb_stats { 11738 u64 brb_truncate[8]; 11739 u64 brb_discard[8]; 11740 }; 11741 11742 struct port_stats { 11743 struct brb_stats brb; 11744 struct eth_stats eth; 11745 }; 11746 11747 struct couple_mode_teaming { 11748 u8 port_cmt[MCP_GLOB_PORT_MAX]; 11749 #define PORT_CMT_IN_TEAM (1 << 0) 11750 11751 #define PORT_CMT_PORT_ROLE (1 << 1) 11752 #define PORT_CMT_PORT_INACTIVE (0 << 1) 11753 #define PORT_CMT_PORT_ACTIVE (1 << 1) 11754 11755 #define PORT_CMT_TEAM_MASK (1 << 2) 11756 #define PORT_CMT_TEAM0 (0 << 2) 11757 #define PORT_CMT_TEAM1 (1 << 2) 11758 }; 11759 11760 #define LLDP_CHASSIS_ID_STAT_LEN 4 11761 #define LLDP_PORT_ID_STAT_LEN 4 11762 #define DCBX_MAX_APP_PROTOCOL 32 11763 #define MAX_SYSTEM_LLDP_TLV_DATA 32 11764 11765 enum _lldp_agent { 11766 LLDP_NEAREST_BRIDGE = 0, 11767 LLDP_NEAREST_NON_TPMR_BRIDGE, 11768 LLDP_NEAREST_CUSTOMER_BRIDGE, 11769 LLDP_MAX_LLDP_AGENTS 11770 }; 11771 11772 struct lldp_config_params_s { 11773 u32 config; 11774 #define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff 11775 #define LLDP_CONFIG_TX_INTERVAL_SHIFT 0 11776 #define LLDP_CONFIG_HOLD_MASK 0x00000f00 11777 #define LLDP_CONFIG_HOLD_SHIFT 8 11778 #define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000 11779 #define LLDP_CONFIG_MAX_CREDIT_SHIFT 12 11780 #define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000 11781 #define LLDP_CONFIG_ENABLE_RX_SHIFT 30 11782 #define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000 11783 #define LLDP_CONFIG_ENABLE_TX_SHIFT 31 11784 u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; 11785 u32 local_port_id[LLDP_PORT_ID_STAT_LEN]; 11786 }; 11787 11788 struct lldp_status_params_s { 11789 u32 prefix_seq_num; 11790 u32 status; 11791 u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; 11792 u32 peer_port_id[LLDP_PORT_ID_STAT_LEN]; 11793 u32 suffix_seq_num; 11794 }; 11795 11796 struct dcbx_ets_feature { 11797 u32 flags; 11798 #define DCBX_ETS_ENABLED_MASK 0x00000001 11799 #define DCBX_ETS_ENABLED_SHIFT 0 11800 #define DCBX_ETS_WILLING_MASK 0x00000002 11801 #define DCBX_ETS_WILLING_SHIFT 1 11802 #define DCBX_ETS_ERROR_MASK 0x00000004 11803 #define DCBX_ETS_ERROR_SHIFT 2 11804 #define DCBX_ETS_CBS_MASK 0x00000008 11805 #define DCBX_ETS_CBS_SHIFT 3 11806 #define DCBX_ETS_MAX_TCS_MASK 0x000000f0 11807 #define DCBX_ETS_MAX_TCS_SHIFT 4 11808 #define DCBX_OOO_TC_MASK 0x00000f00 11809 #define DCBX_OOO_TC_SHIFT 8 11810 u32 pri_tc_tbl[1]; 11811 #define DCBX_TCP_OOO_TC (4) 11812 11813 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_TCP_OOO_TC + 1) 11814 #define DCBX_CEE_STRICT_PRIORITY 0xf 11815 u32 tc_bw_tbl[2]; 11816 u32 tc_tsa_tbl[2]; 11817 #define DCBX_ETS_TSA_STRICT 0 11818 #define DCBX_ETS_TSA_CBS 1 11819 #define DCBX_ETS_TSA_ETS 2 11820 }; 11821 11822 #define DCBX_TCP_OOO_TC (4) 11823 #define DCBX_TCP_OOO_K2_4PORT_TC (3) 11824 11825 struct dcbx_app_priority_entry { 11826 u32 entry; 11827 #define DCBX_APP_PRI_MAP_MASK 0x000000ff 11828 #define DCBX_APP_PRI_MAP_SHIFT 0 11829 #define DCBX_APP_PRI_0 0x01 11830 #define DCBX_APP_PRI_1 0x02 11831 #define DCBX_APP_PRI_2 0x04 11832 #define DCBX_APP_PRI_3 0x08 11833 #define DCBX_APP_PRI_4 0x10 11834 #define DCBX_APP_PRI_5 0x20 11835 #define DCBX_APP_PRI_6 0x40 11836 #define DCBX_APP_PRI_7 0x80 11837 #define DCBX_APP_SF_MASK 0x00000300 11838 #define DCBX_APP_SF_SHIFT 8 11839 #define DCBX_APP_SF_ETHTYPE 0 11840 #define DCBX_APP_SF_PORT 1 11841 #define DCBX_APP_SF_IEEE_MASK 0x0000f000 11842 #define DCBX_APP_SF_IEEE_SHIFT 12 11843 #define DCBX_APP_SF_IEEE_RESERVED 0 11844 #define DCBX_APP_SF_IEEE_ETHTYPE 1 11845 #define DCBX_APP_SF_IEEE_TCP_PORT 2 11846 #define DCBX_APP_SF_IEEE_UDP_PORT 3 11847 #define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4 11848 11849 #define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000 11850 #define DCBX_APP_PROTOCOL_ID_SHIFT 16 11851 }; 11852 11853 struct dcbx_app_priority_feature { 11854 u32 flags; 11855 #define DCBX_APP_ENABLED_MASK 0x00000001 11856 #define DCBX_APP_ENABLED_SHIFT 0 11857 #define DCBX_APP_WILLING_MASK 0x00000002 11858 #define DCBX_APP_WILLING_SHIFT 1 11859 #define DCBX_APP_ERROR_MASK 0x00000004 11860 #define DCBX_APP_ERROR_SHIFT 2 11861 #define DCBX_APP_MAX_TCS_MASK 0x0000f000 11862 #define DCBX_APP_MAX_TCS_SHIFT 12 11863 #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000 11864 #define DCBX_APP_NUM_ENTRIES_SHIFT 16 11865 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 11866 }; 11867 11868 struct dcbx_features { 11869 struct dcbx_ets_feature ets; 11870 u32 pfc; 11871 #define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff 11872 #define DCBX_PFC_PRI_EN_BITMAP_SHIFT 0 11873 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01 11874 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02 11875 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04 11876 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08 11877 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10 11878 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20 11879 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40 11880 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80 11881 11882 #define DCBX_PFC_FLAGS_MASK 0x0000ff00 11883 #define DCBX_PFC_FLAGS_SHIFT 8 11884 #define DCBX_PFC_CAPS_MASK 0x00000f00 11885 #define DCBX_PFC_CAPS_SHIFT 8 11886 #define DCBX_PFC_MBC_MASK 0x00004000 11887 #define DCBX_PFC_MBC_SHIFT 14 11888 #define DCBX_PFC_WILLING_MASK 0x00008000 11889 #define DCBX_PFC_WILLING_SHIFT 15 11890 #define DCBX_PFC_ENABLED_MASK 0x00010000 11891 #define DCBX_PFC_ENABLED_SHIFT 16 11892 #define DCBX_PFC_ERROR_MASK 0x00020000 11893 #define DCBX_PFC_ERROR_SHIFT 17 11894 11895 struct dcbx_app_priority_feature app; 11896 }; 11897 11898 struct dcbx_local_params { 11899 u32 config; 11900 #define DCBX_CONFIG_VERSION_MASK 0x00000007 11901 #define DCBX_CONFIG_VERSION_SHIFT 0 11902 #define DCBX_CONFIG_VERSION_DISABLED 0 11903 #define DCBX_CONFIG_VERSION_IEEE 1 11904 #define DCBX_CONFIG_VERSION_CEE 2 11905 #define DCBX_CONFIG_VERSION_STATIC 4 11906 11907 u32 flags; 11908 struct dcbx_features features; 11909 }; 11910 11911 struct dcbx_mib { 11912 u32 prefix_seq_num; 11913 u32 flags; 11914 struct dcbx_features features; 11915 u32 suffix_seq_num; 11916 }; 11917 11918 struct lldp_system_tlvs_buffer_s { 11919 u16 valid; 11920 u16 length; 11921 u32 data[MAX_SYSTEM_LLDP_TLV_DATA]; 11922 }; 11923 11924 struct dcb_dscp_map { 11925 u32 flags; 11926 #define DCB_DSCP_ENABLE_MASK 0x1 11927 #define DCB_DSCP_ENABLE_SHIFT 0 11928 #define DCB_DSCP_ENABLE 1 11929 u32 dscp_pri_map[8]; 11930 }; 11931 11932 struct public_global { 11933 u32 max_path; 11934 u32 max_ports; 11935 #define MODE_1P 1 11936 #define MODE_2P 2 11937 #define MODE_3P 3 11938 #define MODE_4P 4 11939 u32 debug_mb_offset; 11940 u32 phymod_dbg_mb_offset; 11941 struct couple_mode_teaming cmt; 11942 s32 internal_temperature; 11943 u32 mfw_ver; 11944 u32 running_bundle_id; 11945 s32 external_temperature; 11946 u32 mdump_reason; 11947 u64 reserved; 11948 u32 data_ptr; 11949 u32 data_size; 11950 }; 11951 11952 struct fw_flr_mb { 11953 u32 aggint; 11954 u32 opgen_addr; 11955 u32 accum_ack; 11956 }; 11957 11958 struct public_path { 11959 struct fw_flr_mb flr_mb; 11960 u32 mcp_vf_disabled[VF_MAX_STATIC / 32]; 11961 11962 u32 process_kill; 11963 #define PROCESS_KILL_COUNTER_MASK 0x0000ffff 11964 #define PROCESS_KILL_COUNTER_SHIFT 0 11965 #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000 11966 #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16 11967 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit) 11968 }; 11969 11970 struct public_port { 11971 u32 validity_map; 11972 11973 u32 link_status; 11974 #define LINK_STATUS_LINK_UP 0x00000001 11975 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e 11976 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1 << 1) 11977 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1) 11978 #define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1) 11979 #define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1) 11980 #define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1) 11981 #define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1) 11982 #define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1) 11983 #define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1) 11984 11985 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 11986 11987 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 11988 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 11989 11990 #define LINK_STATUS_PFC_ENABLED 0x00000100 11991 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 11992 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 11993 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800 11994 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000 11995 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000 11996 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000 11997 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000 11998 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000 11999 12000 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 12001 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18) 12002 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1 << 18) 12003 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18) 12004 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18) 12005 12006 #define LINK_STATUS_SFP_TX_FAULT 0x00100000 12007 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000 12008 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000 12009 #define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000 12010 #define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000 12011 #define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000 12012 #define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000 12013 12014 u32 link_status1; 12015 u32 ext_phy_fw_version; 12016 u32 drv_phy_cfg_addr; 12017 12018 u32 port_stx; 12019 12020 u32 stat_nig_timer; 12021 12022 struct port_mf_cfg port_mf_config; 12023 struct port_stats stats; 12024 12025 u32 media_type; 12026 #define MEDIA_UNSPECIFIED 0x0 12027 #define MEDIA_SFPP_10G_FIBER 0x1 12028 #define MEDIA_XFP_FIBER 0x2 12029 #define MEDIA_DA_TWINAX 0x3 12030 #define MEDIA_BASE_T 0x4 12031 #define MEDIA_SFP_1G_FIBER 0x5 12032 #define MEDIA_MODULE_FIBER 0x6 12033 #define MEDIA_KR 0xf0 12034 #define MEDIA_NOT_PRESENT 0xff 12035 12036 u32 lfa_status; 12037 u32 link_change_count; 12038 12039 struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS]; 12040 struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS]; 12041 struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf; 12042 12043 /* DCBX related MIB */ 12044 struct dcbx_local_params local_admin_dcbx_mib; 12045 struct dcbx_mib remote_dcbx_mib; 12046 struct dcbx_mib operational_dcbx_mib; 12047 12048 u32 reserved[2]; 12049 u32 transceiver_data; 12050 #define ETH_TRANSCEIVER_STATE_MASK 0x000000FF 12051 #define ETH_TRANSCEIVER_STATE_SHIFT 0x00000000 12052 #define ETH_TRANSCEIVER_STATE_OFFSET 0x00000000 12053 #define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000 12054 #define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001 12055 #define ETH_TRANSCEIVER_STATE_VALID 0x00000003 12056 #define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008 12057 #define ETH_TRANSCEIVER_TYPE_MASK 0x0000FF00 12058 #define ETH_TRANSCEIVER_TYPE_OFFSET 0x8 12059 #define ETH_TRANSCEIVER_TYPE_NONE 0x00 12060 #define ETH_TRANSCEIVER_TYPE_UNKNOWN 0xFF 12061 #define ETH_TRANSCEIVER_TYPE_1G_PCC 0x01 12062 #define ETH_TRANSCEIVER_TYPE_1G_ACC 0x02 12063 #define ETH_TRANSCEIVER_TYPE_1G_LX 0x03 12064 #define ETH_TRANSCEIVER_TYPE_1G_SX 0x04 12065 #define ETH_TRANSCEIVER_TYPE_10G_SR 0x05 12066 #define ETH_TRANSCEIVER_TYPE_10G_LR 0x06 12067 #define ETH_TRANSCEIVER_TYPE_10G_LRM 0x07 12068 #define ETH_TRANSCEIVER_TYPE_10G_ER 0x08 12069 #define ETH_TRANSCEIVER_TYPE_10G_PCC 0x09 12070 #define ETH_TRANSCEIVER_TYPE_10G_ACC 0x0a 12071 #define ETH_TRANSCEIVER_TYPE_XLPPI 0x0b 12072 #define ETH_TRANSCEIVER_TYPE_40G_LR4 0x0c 12073 #define ETH_TRANSCEIVER_TYPE_40G_SR4 0x0d 12074 #define ETH_TRANSCEIVER_TYPE_40G_CR4 0x0e 12075 #define ETH_TRANSCEIVER_TYPE_100G_AOC 0x0f 12076 #define ETH_TRANSCEIVER_TYPE_100G_SR4 0x10 12077 #define ETH_TRANSCEIVER_TYPE_100G_LR4 0x11 12078 #define ETH_TRANSCEIVER_TYPE_100G_ER4 0x12 12079 #define ETH_TRANSCEIVER_TYPE_100G_ACC 0x13 12080 #define ETH_TRANSCEIVER_TYPE_100G_CR4 0x14 12081 #define ETH_TRANSCEIVER_TYPE_4x10G_SR 0x15 12082 #define ETH_TRANSCEIVER_TYPE_25G_CA_N 0x16 12083 #define ETH_TRANSCEIVER_TYPE_25G_ACC_S 0x17 12084 #define ETH_TRANSCEIVER_TYPE_25G_CA_S 0x18 12085 #define ETH_TRANSCEIVER_TYPE_25G_ACC_M 0x19 12086 #define ETH_TRANSCEIVER_TYPE_25G_CA_L 0x1a 12087 #define ETH_TRANSCEIVER_TYPE_25G_ACC_L 0x1b 12088 #define ETH_TRANSCEIVER_TYPE_25G_SR 0x1c 12089 #define ETH_TRANSCEIVER_TYPE_25G_LR 0x1d 12090 #define ETH_TRANSCEIVER_TYPE_25G_AOC 0x1e 12091 #define ETH_TRANSCEIVER_TYPE_4x10G 0x1f 12092 #define ETH_TRANSCEIVER_TYPE_4x25G_CR 0x20 12093 #define ETH_TRANSCEIVER_TYPE_1000BASET 0x21 12094 #define ETH_TRANSCEIVER_TYPE_10G_BASET 0x22 12095 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR 0x30 12096 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR 0x31 12097 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR 0x32 12098 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR 0x33 12099 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR 0x34 12100 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR 0x35 12101 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC 0x36 12102 u32 wol_info; 12103 u32 wol_pkt_len; 12104 u32 wol_pkt_details; 12105 struct dcb_dscp_map dcb_dscp_map; 12106 12107 u32 eee_status; 12108 #define EEE_ACTIVE_BIT BIT(0) 12109 #define EEE_LD_ADV_STATUS_MASK 0x000000f0 12110 #define EEE_LD_ADV_STATUS_OFFSET 4 12111 #define EEE_1G_ADV BIT(1) 12112 #define EEE_10G_ADV BIT(2) 12113 #define EEE_LP_ADV_STATUS_MASK 0x00000f00 12114 #define EEE_LP_ADV_STATUS_OFFSET 8 12115 #define EEE_SUPPORTED_SPEED_MASK 0x0000f000 12116 #define EEE_SUPPORTED_SPEED_OFFSET 12 12117 #define EEE_1G_SUPPORTED BIT(1) 12118 #define EEE_10G_SUPPORTED BIT(2) 12119 12120 u32 eee_remote; 12121 #define EEE_REMOTE_TW_TX_MASK 0x0000ffff 12122 #define EEE_REMOTE_TW_TX_OFFSET 0 12123 #define EEE_REMOTE_TW_RX_MASK 0xffff0000 12124 #define EEE_REMOTE_TW_RX_OFFSET 16 12125 12126 u32 reserved1; 12127 u32 oem_cfg_port; 12128 #define OEM_CFG_CHANNEL_TYPE_MASK 0x00000003 12129 #define OEM_CFG_CHANNEL_TYPE_OFFSET 0 12130 #define OEM_CFG_CHANNEL_TYPE_VLAN_PARTITION 0x1 12131 #define OEM_CFG_CHANNEL_TYPE_STAGGED 0x2 12132 #define OEM_CFG_SCHED_TYPE_MASK 0x0000000C 12133 #define OEM_CFG_SCHED_TYPE_OFFSET 2 12134 #define OEM_CFG_SCHED_TYPE_ETS 0x1 12135 #define OEM_CFG_SCHED_TYPE_VNIC_BW 0x2 12136 }; 12137 12138 struct public_func { 12139 u32 reserved0[2]; 12140 12141 u32 mtu_size; 12142 12143 u32 reserved[7]; 12144 12145 u32 config; 12146 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 12147 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002 12148 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001 12149 12150 #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0 12151 #define FUNC_MF_CFG_PROTOCOL_SHIFT 4 12152 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000 12153 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010 12154 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020 12155 #define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030 12156 #define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030 12157 12158 #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00 12159 #define FUNC_MF_CFG_MIN_BW_SHIFT 8 12160 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 12161 #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000 12162 #define FUNC_MF_CFG_MAX_BW_SHIFT 16 12163 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000 12164 12165 u32 status; 12166 #define FUNC_STATUS_VIRTUAL_LINK_UP 0x00000001 12167 12168 u32 mac_upper; 12169 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 12170 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 12171 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 12172 u32 mac_lower; 12173 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 12174 12175 u32 fcoe_wwn_port_name_upper; 12176 u32 fcoe_wwn_port_name_lower; 12177 12178 u32 fcoe_wwn_node_name_upper; 12179 u32 fcoe_wwn_node_name_lower; 12180 12181 u32 ovlan_stag; 12182 #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff 12183 #define FUNC_MF_CFG_OV_STAG_SHIFT 0 12184 #define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK 12185 12186 u32 pf_allocation; 12187 12188 u32 preserve_data; 12189 12190 u32 driver_last_activity_ts; 12191 12192 u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32]; 12193 12194 u32 drv_id; 12195 #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff 12196 #define DRV_ID_PDA_COMP_VER_SHIFT 0 12197 12198 #define LOAD_REQ_HSI_VERSION 2 12199 #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000 12200 #define DRV_ID_MCP_HSI_VER_SHIFT 16 12201 #define DRV_ID_MCP_HSI_VER_CURRENT (LOAD_REQ_HSI_VERSION << \ 12202 DRV_ID_MCP_HSI_VER_SHIFT) 12203 12204 #define DRV_ID_DRV_TYPE_MASK 0x7f000000 12205 #define DRV_ID_DRV_TYPE_SHIFT 24 12206 #define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT) 12207 #define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_SHIFT) 12208 12209 #define DRV_ID_DRV_INIT_HW_MASK 0x80000000 12210 #define DRV_ID_DRV_INIT_HW_SHIFT 31 12211 #define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_SHIFT) 12212 12213 u32 oem_cfg_func; 12214 #define OEM_CFG_FUNC_TC_MASK 0x0000000F 12215 #define OEM_CFG_FUNC_TC_OFFSET 0 12216 #define OEM_CFG_FUNC_TC_0 0x0 12217 #define OEM_CFG_FUNC_TC_1 0x1 12218 #define OEM_CFG_FUNC_TC_2 0x2 12219 #define OEM_CFG_FUNC_TC_3 0x3 12220 #define OEM_CFG_FUNC_TC_4 0x4 12221 #define OEM_CFG_FUNC_TC_5 0x5 12222 #define OEM_CFG_FUNC_TC_6 0x6 12223 #define OEM_CFG_FUNC_TC_7 0x7 12224 12225 #define OEM_CFG_FUNC_HOST_PRI_CTRL_MASK 0x00000030 12226 #define OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET 4 12227 #define OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC 0x1 12228 #define OEM_CFG_FUNC_HOST_PRI_CTRL_OS 0x2 12229 }; 12230 12231 struct mcp_mac { 12232 u32 mac_upper; 12233 u32 mac_lower; 12234 }; 12235 12236 struct mcp_val64 { 12237 u32 lo; 12238 u32 hi; 12239 }; 12240 12241 struct mcp_file_att { 12242 u32 nvm_start_addr; 12243 u32 len; 12244 }; 12245 12246 struct bist_nvm_image_att { 12247 u32 return_code; 12248 u32 image_type; 12249 u32 nvm_start_addr; 12250 u32 len; 12251 }; 12252 12253 #define MCP_DRV_VER_STR_SIZE 16 12254 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32)) 12255 #define MCP_DRV_NVM_BUF_LEN 32 12256 struct drv_version_stc { 12257 u32 version; 12258 u8 name[MCP_DRV_VER_STR_SIZE - 4]; 12259 }; 12260 12261 struct lan_stats_stc { 12262 u64 ucast_rx_pkts; 12263 u64 ucast_tx_pkts; 12264 u32 fcs_err; 12265 u32 rserved; 12266 }; 12267 12268 struct fcoe_stats_stc { 12269 u64 rx_pkts; 12270 u64 tx_pkts; 12271 u32 fcs_err; 12272 u32 login_failure; 12273 }; 12274 12275 struct ocbb_data_stc { 12276 u32 ocbb_host_addr; 12277 u32 ocsd_host_addr; 12278 u32 ocsd_req_update_interval; 12279 }; 12280 12281 #define MAX_NUM_OF_SENSORS 7 12282 struct temperature_status_stc { 12283 u32 num_of_sensors; 12284 u32 sensor[MAX_NUM_OF_SENSORS]; 12285 }; 12286 12287 /* crash dump configuration header */ 12288 struct mdump_config_stc { 12289 u32 version; 12290 u32 config; 12291 u32 epoc; 12292 u32 num_of_logs; 12293 u32 valid_logs; 12294 }; 12295 12296 enum resource_id_enum { 12297 RESOURCE_NUM_SB_E = 0, 12298 RESOURCE_NUM_L2_QUEUE_E = 1, 12299 RESOURCE_NUM_VPORT_E = 2, 12300 RESOURCE_NUM_VMQ_E = 3, 12301 RESOURCE_FACTOR_NUM_RSS_PF_E = 4, 12302 RESOURCE_FACTOR_RSS_PER_VF_E = 5, 12303 RESOURCE_NUM_RL_E = 6, 12304 RESOURCE_NUM_PQ_E = 7, 12305 RESOURCE_NUM_VF_E = 8, 12306 RESOURCE_VFC_FILTER_E = 9, 12307 RESOURCE_ILT_E = 10, 12308 RESOURCE_CQS_E = 11, 12309 RESOURCE_GFT_PROFILES_E = 12, 12310 RESOURCE_NUM_TC_E = 13, 12311 RESOURCE_NUM_RSS_ENGINES_E = 14, 12312 RESOURCE_LL2_QUEUE_E = 15, 12313 RESOURCE_RDMA_STATS_QUEUE_E = 16, 12314 RESOURCE_BDQ_E = 17, 12315 RESOURCE_QCN_E = 18, 12316 RESOURCE_LLH_FILTER_E = 19, 12317 RESOURCE_VF_MAC_ADDR = 20, 12318 RESOURCE_LL2_CQS_E = 21, 12319 RESOURCE_VF_CNQS = 22, 12320 RESOURCE_MAX_NUM, 12321 RESOURCE_NUM_INVALID = 0xFFFFFFFF 12322 }; 12323 12324 /* Resource ID is to be filled by the driver in the MB request 12325 * Size, offset & flags to be filled by the MFW in the MB response 12326 */ 12327 struct resource_info { 12328 enum resource_id_enum res_id; 12329 u32 size; /* number of allocated resources */ 12330 u32 offset; /* Offset of the 1st resource */ 12331 u32 vf_size; 12332 u32 vf_offset; 12333 u32 flags; 12334 #define RESOURCE_ELEMENT_STRICT (1 << 0) 12335 }; 12336 12337 #define DRV_ROLE_NONE 0 12338 #define DRV_ROLE_PREBOOT 1 12339 #define DRV_ROLE_OS 2 12340 #define DRV_ROLE_KDUMP 3 12341 12342 struct load_req_stc { 12343 u32 drv_ver_0; 12344 u32 drv_ver_1; 12345 u32 fw_ver; 12346 u32 misc0; 12347 #define LOAD_REQ_ROLE_MASK 0x000000FF 12348 #define LOAD_REQ_ROLE_SHIFT 0 12349 #define LOAD_REQ_LOCK_TO_MASK 0x0000FF00 12350 #define LOAD_REQ_LOCK_TO_SHIFT 8 12351 #define LOAD_REQ_LOCK_TO_DEFAULT 0 12352 #define LOAD_REQ_LOCK_TO_NONE 255 12353 #define LOAD_REQ_FORCE_MASK 0x000F0000 12354 #define LOAD_REQ_FORCE_SHIFT 16 12355 #define LOAD_REQ_FORCE_NONE 0 12356 #define LOAD_REQ_FORCE_PF 1 12357 #define LOAD_REQ_FORCE_ALL 2 12358 #define LOAD_REQ_FLAGS0_MASK 0x00F00000 12359 #define LOAD_REQ_FLAGS0_SHIFT 20 12360 #define LOAD_REQ_FLAGS0_AVOID_RESET (0x1 << 0) 12361 }; 12362 12363 struct load_rsp_stc { 12364 u32 drv_ver_0; 12365 u32 drv_ver_1; 12366 u32 fw_ver; 12367 u32 misc0; 12368 #define LOAD_RSP_ROLE_MASK 0x000000FF 12369 #define LOAD_RSP_ROLE_SHIFT 0 12370 #define LOAD_RSP_HSI_MASK 0x0000FF00 12371 #define LOAD_RSP_HSI_SHIFT 8 12372 #define LOAD_RSP_FLAGS0_MASK 0x000F0000 12373 #define LOAD_RSP_FLAGS0_SHIFT 16 12374 #define LOAD_RSP_FLAGS0_DRV_EXISTS (0x1 << 0) 12375 }; 12376 12377 struct mdump_retain_data_stc { 12378 u32 valid; 12379 u32 epoch; 12380 u32 pf; 12381 u32 status; 12382 }; 12383 12384 union drv_union_data { 12385 u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD]; 12386 struct mcp_mac wol_mac; 12387 12388 struct eth_phy_cfg drv_phy_cfg; 12389 12390 struct mcp_val64 val64; 12391 12392 u8 raw_data[MCP_DRV_NVM_BUF_LEN]; 12393 12394 struct mcp_file_att file_att; 12395 12396 u32 ack_vf_disabled[VF_MAX_STATIC / 32]; 12397 12398 struct drv_version_stc drv_version; 12399 12400 struct lan_stats_stc lan_stats; 12401 struct fcoe_stats_stc fcoe_stats; 12402 struct ocbb_data_stc ocbb_info; 12403 struct temperature_status_stc temp_info; 12404 struct resource_info resource; 12405 struct bist_nvm_image_att nvm_image_att; 12406 struct mdump_config_stc mdump_config; 12407 }; 12408 12409 struct public_drv_mb { 12410 u32 drv_mb_header; 12411 #define DRV_MSG_CODE_MASK 0xffff0000 12412 #define DRV_MSG_CODE_LOAD_REQ 0x10000000 12413 #define DRV_MSG_CODE_LOAD_DONE 0x11000000 12414 #define DRV_MSG_CODE_INIT_HW 0x12000000 12415 #define DRV_MSG_CODE_CANCEL_LOAD_REQ 0x13000000 12416 #define DRV_MSG_CODE_UNLOAD_REQ 0x20000000 12417 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 12418 #define DRV_MSG_CODE_INIT_PHY 0x22000000 12419 #define DRV_MSG_CODE_LINK_RESET 0x23000000 12420 #define DRV_MSG_CODE_SET_DCBX 0x25000000 12421 #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000 12422 #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM 0x27000000 12423 #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS 0x28000000 12424 #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER 0x29000000 12425 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE 0x31000000 12426 #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000 12427 #define DRV_MSG_CODE_OV_UPDATE_MTU 0x33000000 12428 #define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000 12429 #define DRV_MSG_SET_RESOURCE_VALUE_MSG 0x35000000 12430 #define DRV_MSG_CODE_OV_UPDATE_WOL 0x38000000 12431 #define DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE 0x39000000 12432 #define DRV_MSG_CODE_GET_OEM_UPDATES 0x41000000 12433 12434 #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000 12435 #define DRV_MSG_CODE_NIG_DRAIN 0x30000000 12436 #define DRV_MSG_CODE_S_TAG_UPDATE_ACK 0x3b000000 12437 #define DRV_MSG_CODE_GET_NVM_CFG_OPTION 0x003e0000 12438 #define DRV_MSG_CODE_SET_NVM_CFG_OPTION 0x003f0000 12439 #define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000 12440 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 12441 #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000 12442 #define DRV_MSG_CODE_CFG_PF_VFS_MSIX 0xc0020000 12443 #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN 0x00010000 12444 #define DRV_MSG_CODE_NVM_PUT_FILE_DATA 0x00020000 12445 #define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000 12446 #define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000 12447 #define DRV_MSG_CODE_NVM_WRITE_NVRAM 0x00060000 12448 #define DRV_MSG_CODE_MCP_RESET 0x00090000 12449 #define DRV_MSG_CODE_SET_VERSION 0x000f0000 12450 #define DRV_MSG_CODE_MCP_HALT 0x00100000 12451 #define DRV_MSG_CODE_SET_VMAC 0x00110000 12452 #define DRV_MSG_CODE_GET_VMAC 0x00120000 12453 #define DRV_MSG_CODE_VMAC_TYPE_SHIFT 4 12454 #define DRV_MSG_CODE_VMAC_TYPE_MASK 0x30 12455 #define DRV_MSG_CODE_VMAC_TYPE_MAC 1 12456 #define DRV_MSG_CODE_VMAC_TYPE_WWNN 2 12457 #define DRV_MSG_CODE_VMAC_TYPE_WWPN 3 12458 12459 #define DRV_MSG_CODE_GET_STATS 0x00130000 12460 #define DRV_MSG_CODE_STATS_TYPE_LAN 1 12461 #define DRV_MSG_CODE_STATS_TYPE_FCOE 2 12462 #define DRV_MSG_CODE_STATS_TYPE_ISCSI 3 12463 #define DRV_MSG_CODE_STATS_TYPE_RDMA 4 12464 12465 #define DRV_MSG_CODE_TRANSCEIVER_READ 0x00160000 12466 12467 #define DRV_MSG_CODE_MASK_PARITIES 0x001a0000 12468 12469 #define DRV_MSG_CODE_BIST_TEST 0x001e0000 12470 #define DRV_MSG_CODE_SET_LED_MODE 0x00200000 12471 #define DRV_MSG_CODE_RESOURCE_CMD 0x00230000 12472 /* Send crash dump commands with param[3:0] - opcode */ 12473 #define DRV_MSG_CODE_MDUMP_CMD 0x00250000 12474 #define DRV_MSG_CODE_GET_TLV_DONE 0x002f0000 12475 #define DRV_MSG_CODE_GET_ENGINE_CONFIG 0x00370000 12476 #define DRV_MSG_CODE_GET_PPFID_BITMAP 0x43000000 12477 12478 #define DRV_MSG_CODE_DEBUG_DATA_SEND 0xc0040000 12479 12480 #define RESOURCE_CMD_REQ_RESC_MASK 0x0000001F 12481 #define RESOURCE_CMD_REQ_RESC_SHIFT 0 12482 #define RESOURCE_CMD_REQ_OPCODE_MASK 0x000000E0 12483 #define RESOURCE_CMD_REQ_OPCODE_SHIFT 5 12484 #define RESOURCE_OPCODE_REQ 1 12485 #define RESOURCE_OPCODE_REQ_WO_AGING 2 12486 #define RESOURCE_OPCODE_REQ_W_AGING 3 12487 #define RESOURCE_OPCODE_RELEASE 4 12488 #define RESOURCE_OPCODE_FORCE_RELEASE 5 12489 #define RESOURCE_CMD_REQ_AGE_MASK 0x0000FF00 12490 #define RESOURCE_CMD_REQ_AGE_SHIFT 8 12491 12492 #define RESOURCE_CMD_RSP_OWNER_MASK 0x000000FF 12493 #define RESOURCE_CMD_RSP_OWNER_SHIFT 0 12494 #define RESOURCE_CMD_RSP_OPCODE_MASK 0x00000700 12495 #define RESOURCE_CMD_RSP_OPCODE_SHIFT 8 12496 #define RESOURCE_OPCODE_GNT 1 12497 #define RESOURCE_OPCODE_BUSY 2 12498 #define RESOURCE_OPCODE_RELEASED 3 12499 #define RESOURCE_OPCODE_RELEASED_PREVIOUS 4 12500 #define RESOURCE_OPCODE_WRONG_OWNER 5 12501 #define RESOURCE_OPCODE_UNKNOWN_CMD 255 12502 12503 #define RESOURCE_DUMP 0 12504 12505 /* DRV_MSG_CODE_MDUMP_CMD parameters */ 12506 #define MDUMP_DRV_PARAM_OPCODE_MASK 0x0000000f 12507 #define DRV_MSG_CODE_MDUMP_ACK 0x01 12508 #define DRV_MSG_CODE_MDUMP_SET_VALUES 0x02 12509 #define DRV_MSG_CODE_MDUMP_TRIGGER 0x03 12510 #define DRV_MSG_CODE_MDUMP_GET_CONFIG 0x04 12511 #define DRV_MSG_CODE_MDUMP_SET_ENABLE 0x05 12512 #define DRV_MSG_CODE_MDUMP_CLEAR_LOGS 0x06 12513 #define DRV_MSG_CODE_MDUMP_GET_RETAIN 0x07 12514 #define DRV_MSG_CODE_MDUMP_CLR_RETAIN 0x08 12515 12516 #define DRV_MSG_CODE_HW_DUMP_TRIGGER 0x0a 12517 #define DRV_MSG_CODE_MDUMP_GEN_MDUMP2 0x0b 12518 #define DRV_MSG_CODE_MDUMP_FREE_MDUMP2 0x0c 12519 12520 #define DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL 0x002b0000 12521 #define DRV_MSG_CODE_OS_WOL 0x002e0000 12522 12523 #define DRV_MSG_CODE_FEATURE_SUPPORT 0x00300000 12524 #define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT 0x00310000 12525 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 12526 12527 u32 drv_mb_param; 12528 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000 12529 #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001 12530 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002 12531 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003 12532 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x000000FF 12533 #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3 12534 12535 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MBI 0x3 12536 #define DRV_MB_PARAM_NVM_OFFSET_OFFSET 0 12537 #define DRV_MB_PARAM_NVM_OFFSET_MASK 0x00FFFFFF 12538 #define DRV_MB_PARAM_NVM_LEN_OFFSET 24 12539 #define DRV_MB_PARAM_NVM_LEN_MASK 0xFF000000 12540 12541 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0 12542 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF 12543 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT 8 12544 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00 12545 #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001 12546 #define DRV_MB_PARAM_LLDP_SEND_SHIFT 0 12547 12548 #define DRV_MB_PARAM_OV_CURR_CFG_SHIFT 0 12549 #define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F 12550 #define DRV_MB_PARAM_OV_CURR_CFG_NONE 0 12551 #define DRV_MB_PARAM_OV_CURR_CFG_OS 1 12552 #define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC 2 12553 #define DRV_MB_PARAM_OV_CURR_CFG_OTHER 3 12554 12555 #define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT 0 12556 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF 12557 #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000 12558 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000 12559 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00 12560 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF 12561 12562 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT 0 12563 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF 12564 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1 12565 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2 12566 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3 12567 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4 12568 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5 12569 12570 #define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT 0 12571 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF 12572 12573 #define DRV_MB_PARAM_WOL_MASK (DRV_MB_PARAM_WOL_DEFAULT | \ 12574 DRV_MB_PARAM_WOL_DISABLED | \ 12575 DRV_MB_PARAM_WOL_ENABLED) 12576 #define DRV_MB_PARAM_WOL_DEFAULT DRV_MB_PARAM_UNLOAD_WOL_MCP 12577 #define DRV_MB_PARAM_WOL_DISABLED DRV_MB_PARAM_UNLOAD_WOL_DISABLED 12578 #define DRV_MB_PARAM_WOL_ENABLED DRV_MB_PARAM_UNLOAD_WOL_ENABLED 12579 12580 #define DRV_MB_PARAM_ESWITCH_MODE_MASK (DRV_MB_PARAM_ESWITCH_MODE_NONE | \ 12581 DRV_MB_PARAM_ESWITCH_MODE_VEB | \ 12582 DRV_MB_PARAM_ESWITCH_MODE_VEPA) 12583 #define DRV_MB_PARAM_ESWITCH_MODE_NONE 0x0 12584 #define DRV_MB_PARAM_ESWITCH_MODE_VEB 0x1 12585 #define DRV_MB_PARAM_ESWITCH_MODE_VEPA 0x2 12586 12587 #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_MASK 0x1 12588 #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET 0 12589 12590 #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0 12591 #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1 12592 #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2 12593 12594 #define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET 0 12595 #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK 0x00000003 12596 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET 2 12597 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK 0x000000FC 12598 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET 8 12599 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK 0x0000FF00 12600 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET 16 12601 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK 0xFFFF0000 12602 12603 /* Resource Allocation params - Driver version support */ 12604 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 12605 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16 12606 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF 12607 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0 12608 12609 #define DRV_MB_PARAM_BIST_REGISTER_TEST 1 12610 #define DRV_MB_PARAM_BIST_CLOCK_TEST 2 12611 #define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3 12612 #define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4 12613 12614 #define DRV_MB_PARAM_BIST_RC_UNKNOWN 0 12615 #define DRV_MB_PARAM_BIST_RC_PASSED 1 12616 #define DRV_MB_PARAM_BIST_RC_FAILED 2 12617 #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3 12618 12619 #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0 12620 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF 12621 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT 8 12622 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF00 12623 12624 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK 0x0000FFFF 12625 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET 0 12626 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE 0x00000002 12627 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK 0x00010000 12628 12629 /* DRV_MSG_CODE_DEBUG_DATA_SEND parameters */ 12630 #define DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE_OFFSET 0 12631 #define DRV_MSG_CODE_DEBUG_DATA_SEND_SIZE_MASK 0xFF 12632 12633 /* Driver attributes params */ 12634 #define DRV_MB_PARAM_ATTRIBUTE_KEY_OFFSET 0 12635 #define DRV_MB_PARAM_ATTRIBUTE_KEY_MASK 0x00FFFFFF 12636 #define DRV_MB_PARAM_ATTRIBUTE_CMD_OFFSET 24 12637 #define DRV_MB_PARAM_ATTRIBUTE_CMD_MASK 0xFF000000 12638 12639 #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_OFFSET 0 12640 #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_SHIFT 0 12641 #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_MASK 0x0000FFFF 12642 #define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_SHIFT 16 12643 #define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_MASK 0x00010000 12644 #define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_SHIFT 17 12645 #define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_MASK 0x00020000 12646 #define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_SHIFT 18 12647 #define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_MASK 0x00040000 12648 #define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_SHIFT 19 12649 #define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_MASK 0x00080000 12650 #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_SHIFT 20 12651 #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_MASK 0x00100000 12652 #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_SHIFT 24 12653 #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_MASK 0x0f000000 12654 12655 u32 fw_mb_header; 12656 #define FW_MSG_CODE_MASK 0xffff0000 12657 #define FW_MSG_CODE_UNSUPPORTED 0x00000000 12658 #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000 12659 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 12660 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 12661 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000 12662 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1 0x10210000 12663 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000 12664 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10230000 12665 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE 0x10300000 12666 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT 0x10310000 12667 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 12668 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000 12669 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000 12670 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000 12671 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 12672 #define FW_MSG_CODE_RESOURCE_ALLOC_OK 0x34000000 12673 #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN 0x35000000 12674 #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED 0x36000000 12675 #define FW_MSG_CODE_S_TAG_UPDATE_ACK_DONE 0x3b000000 12676 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000 12677 12678 #define FW_MSG_CODE_NVM_OK 0x00010000 12679 #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK 0x00400000 12680 #define FW_MSG_CODE_PHY_OK 0x00110000 12681 #define FW_MSG_CODE_OK 0x00160000 12682 #define FW_MSG_CODE_ERROR 0x00170000 12683 #define FW_MSG_CODE_TRANSCEIVER_DIAG_OK 0x00160000 12684 #define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR 0x00170000 12685 #define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT 0x00020000 12686 12687 #define FW_MSG_CODE_OS_WOL_SUPPORTED 0x00800000 12688 #define FW_MSG_CODE_OS_WOL_NOT_SUPPORTED 0x00810000 12689 #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE 0x00870000 12690 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 12691 12692 #define FW_MSG_CODE_DEBUG_DATA_SEND_INV_ARG 0xb0070000 12693 #define FW_MSG_CODE_DEBUG_DATA_SEND_BUF_FULL 0xb0080000 12694 #define FW_MSG_CODE_DEBUG_DATA_SEND_NO_BUF 0xb0090000 12695 #define FW_MSG_CODE_DEBUG_NOT_ENABLED 0xb00a0000 12696 #define FW_MSG_CODE_DEBUG_DATA_SEND_OK 0xb00b0000 12697 12698 #define FW_MSG_CODE_MDUMP_INVALID_CMD 0x00030000 12699 12700 u32 fw_mb_param; 12701 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 12702 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16 12703 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF 12704 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0 12705 12706 /* get pf rdma protocol command responce */ 12707 #define FW_MB_PARAM_GET_PF_RDMA_NONE 0x0 12708 #define FW_MB_PARAM_GET_PF_RDMA_ROCE 0x1 12709 #define FW_MB_PARAM_GET_PF_RDMA_IWARP 0x2 12710 #define FW_MB_PARAM_GET_PF_RDMA_BOTH 0x3 12711 12712 /* get MFW feature support response */ 12713 #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ 0x00000001 12714 #define FW_MB_PARAM_FEATURE_SUPPORT_EEE 0x00000002 12715 #define FW_MB_PARAM_FEATURE_SUPPORT_VLINK 0x00010000 12716 12717 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1 << 0) 12718 12719 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_MASK 0x00000001 12720 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_SHIFT 0 12721 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_MASK 0x00000002 12722 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_SHIFT 1 12723 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_MASK 0x00000004 12724 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_SHIFT 2 12725 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_MASK 0x00000008 12726 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_SHIFT 3 12727 12728 #define FW_MB_PARAM_PPFID_BITMAP_MASK 0xFF 12729 #define FW_MB_PARAM_PPFID_BITMAP_SHIFT 0 12730 12731 u32 drv_pulse_mb; 12732 #define DRV_PULSE_SEQ_MASK 0x00007fff 12733 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 12734 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 12735 12736 u32 mcp_pulse_mb; 12737 #define MCP_PULSE_SEQ_MASK 0x00007fff 12738 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 12739 #define MCP_EVENT_MASK 0xffff0000 12740 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 12741 12742 union drv_union_data union_data; 12743 }; 12744 12745 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_MASK 0x00ffffff 12746 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_SHIFT 0 12747 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE_MASK 0xff000000 12748 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE_SHIFT 24 12749 12750 enum MFW_DRV_MSG_TYPE { 12751 MFW_DRV_MSG_LINK_CHANGE, 12752 MFW_DRV_MSG_FLR_FW_ACK_FAILED, 12753 MFW_DRV_MSG_VF_DISABLED, 12754 MFW_DRV_MSG_LLDP_DATA_UPDATED, 12755 MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED, 12756 MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED, 12757 MFW_DRV_MSG_ERROR_RECOVERY, 12758 MFW_DRV_MSG_BW_UPDATE, 12759 MFW_DRV_MSG_S_TAG_UPDATE, 12760 MFW_DRV_MSG_GET_LAN_STATS, 12761 MFW_DRV_MSG_GET_FCOE_STATS, 12762 MFW_DRV_MSG_GET_ISCSI_STATS, 12763 MFW_DRV_MSG_GET_RDMA_STATS, 12764 MFW_DRV_MSG_FAILURE_DETECTED, 12765 MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE, 12766 MFW_DRV_MSG_CRITICAL_ERROR_OCCURRED, 12767 MFW_DRV_MSG_RESERVED, 12768 MFW_DRV_MSG_GET_TLV_REQ, 12769 MFW_DRV_MSG_OEM_CFG_UPDATE, 12770 MFW_DRV_MSG_MAX 12771 }; 12772 12773 #define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1) 12774 #define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2) 12775 #define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3) 12776 #define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id)) 12777 12778 struct public_mfw_mb { 12779 u32 sup_msgs; 12780 u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; 12781 u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; 12782 }; 12783 12784 enum public_sections { 12785 PUBLIC_DRV_MB, 12786 PUBLIC_MFW_MB, 12787 PUBLIC_GLOBAL, 12788 PUBLIC_PATH, 12789 PUBLIC_PORT, 12790 PUBLIC_FUNC, 12791 PUBLIC_MAX_SECTIONS 12792 }; 12793 12794 struct mcp_public_data { 12795 u32 num_sections; 12796 u32 sections[PUBLIC_MAX_SECTIONS]; 12797 struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX]; 12798 struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX]; 12799 struct public_global global; 12800 struct public_path path[MCP_GLOB_PATH_MAX]; 12801 struct public_port port[MCP_GLOB_PORT_MAX]; 12802 struct public_func func[MCP_GLOB_FUNC_MAX]; 12803 }; 12804 12805 #define MAX_I2C_TRANSACTION_SIZE 16 12806 12807 /* OCBB definitions */ 12808 enum tlvs { 12809 /* Category 1: Device Properties */ 12810 DRV_TLV_CLP_STR, 12811 DRV_TLV_CLP_STR_CTD, 12812 /* Category 6: Device Configuration */ 12813 DRV_TLV_SCSI_TO, 12814 DRV_TLV_R_T_TOV, 12815 DRV_TLV_R_A_TOV, 12816 DRV_TLV_E_D_TOV, 12817 DRV_TLV_CR_TOV, 12818 DRV_TLV_BOOT_TYPE, 12819 /* Category 8: Port Configuration */ 12820 DRV_TLV_NPIV_ENABLED, 12821 /* Category 10: Function Configuration */ 12822 DRV_TLV_FEATURE_FLAGS, 12823 DRV_TLV_LOCAL_ADMIN_ADDR, 12824 DRV_TLV_ADDITIONAL_MAC_ADDR_1, 12825 DRV_TLV_ADDITIONAL_MAC_ADDR_2, 12826 DRV_TLV_LSO_MAX_OFFLOAD_SIZE, 12827 DRV_TLV_LSO_MIN_SEGMENT_COUNT, 12828 DRV_TLV_PROMISCUOUS_MODE, 12829 DRV_TLV_TX_DESCRIPTORS_QUEUE_SIZE, 12830 DRV_TLV_RX_DESCRIPTORS_QUEUE_SIZE, 12831 DRV_TLV_NUM_OF_NET_QUEUE_VMQ_CFG, 12832 DRV_TLV_FLEX_NIC_OUTER_VLAN_ID, 12833 DRV_TLV_OS_DRIVER_STATES, 12834 DRV_TLV_PXE_BOOT_PROGRESS, 12835 /* Category 12: FC/FCoE Configuration */ 12836 DRV_TLV_NPIV_STATE, 12837 DRV_TLV_NUM_OF_NPIV_IDS, 12838 DRV_TLV_SWITCH_NAME, 12839 DRV_TLV_SWITCH_PORT_NUM, 12840 DRV_TLV_SWITCH_PORT_ID, 12841 DRV_TLV_VENDOR_NAME, 12842 DRV_TLV_SWITCH_MODEL, 12843 DRV_TLV_SWITCH_FW_VER, 12844 DRV_TLV_QOS_PRIORITY_PER_802_1P, 12845 DRV_TLV_PORT_ALIAS, 12846 DRV_TLV_PORT_STATE, 12847 DRV_TLV_FIP_TX_DESCRIPTORS_QUEUE_SIZE, 12848 DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_SIZE, 12849 DRV_TLV_LINK_FAILURE_COUNT, 12850 DRV_TLV_FCOE_BOOT_PROGRESS, 12851 /* Category 13: iSCSI Configuration */ 12852 DRV_TLV_TARGET_LLMNR_ENABLED, 12853 DRV_TLV_HEADER_DIGEST_FLAG_ENABLED, 12854 DRV_TLV_DATA_DIGEST_FLAG_ENABLED, 12855 DRV_TLV_AUTHENTICATION_METHOD, 12856 DRV_TLV_ISCSI_BOOT_TARGET_PORTAL, 12857 DRV_TLV_MAX_FRAME_SIZE, 12858 DRV_TLV_PDU_TX_DESCRIPTORS_QUEUE_SIZE, 12859 DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_SIZE, 12860 DRV_TLV_ISCSI_BOOT_PROGRESS, 12861 /* Category 20: Device Data */ 12862 DRV_TLV_PCIE_BUS_RX_UTILIZATION, 12863 DRV_TLV_PCIE_BUS_TX_UTILIZATION, 12864 DRV_TLV_DEVICE_CPU_CORES_UTILIZATION, 12865 DRV_TLV_LAST_VALID_DCC_TLV_RECEIVED, 12866 DRV_TLV_NCSI_RX_BYTES_RECEIVED, 12867 DRV_TLV_NCSI_TX_BYTES_SENT, 12868 /* Category 22: Base Port Data */ 12869 DRV_TLV_RX_DISCARDS, 12870 DRV_TLV_RX_ERRORS, 12871 DRV_TLV_TX_ERRORS, 12872 DRV_TLV_TX_DISCARDS, 12873 DRV_TLV_RX_FRAMES_RECEIVED, 12874 DRV_TLV_TX_FRAMES_SENT, 12875 /* Category 23: FC/FCoE Port Data */ 12876 DRV_TLV_RX_BROADCAST_PACKETS, 12877 DRV_TLV_TX_BROADCAST_PACKETS, 12878 /* Category 28: Base Function Data */ 12879 DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV4, 12880 DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV6, 12881 DRV_TLV_TX_DESCRIPTOR_QUEUE_AVG_DEPTH, 12882 DRV_TLV_RX_DESCRIPTORS_QUEUE_AVG_DEPTH, 12883 DRV_TLV_PF_RX_FRAMES_RECEIVED, 12884 DRV_TLV_RX_BYTES_RECEIVED, 12885 DRV_TLV_PF_TX_FRAMES_SENT, 12886 DRV_TLV_TX_BYTES_SENT, 12887 DRV_TLV_IOV_OFFLOAD, 12888 DRV_TLV_PCI_ERRORS_CAP_ID, 12889 DRV_TLV_UNCORRECTABLE_ERROR_STATUS, 12890 DRV_TLV_UNCORRECTABLE_ERROR_MASK, 12891 DRV_TLV_CORRECTABLE_ERROR_STATUS, 12892 DRV_TLV_CORRECTABLE_ERROR_MASK, 12893 DRV_TLV_PCI_ERRORS_AECC_REGISTER, 12894 DRV_TLV_TX_QUEUES_EMPTY, 12895 DRV_TLV_RX_QUEUES_EMPTY, 12896 DRV_TLV_TX_QUEUES_FULL, 12897 DRV_TLV_RX_QUEUES_FULL, 12898 /* Category 29: FC/FCoE Function Data */ 12899 DRV_TLV_FCOE_TX_DESCRIPTOR_QUEUE_AVG_DEPTH, 12900 DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_AVG_DEPTH, 12901 DRV_TLV_FCOE_RX_FRAMES_RECEIVED, 12902 DRV_TLV_FCOE_RX_BYTES_RECEIVED, 12903 DRV_TLV_FCOE_TX_FRAMES_SENT, 12904 DRV_TLV_FCOE_TX_BYTES_SENT, 12905 DRV_TLV_CRC_ERROR_COUNT, 12906 DRV_TLV_CRC_ERROR_1_RECEIVED_SOURCE_FC_ID, 12907 DRV_TLV_CRC_ERROR_1_TIMESTAMP, 12908 DRV_TLV_CRC_ERROR_2_RECEIVED_SOURCE_FC_ID, 12909 DRV_TLV_CRC_ERROR_2_TIMESTAMP, 12910 DRV_TLV_CRC_ERROR_3_RECEIVED_SOURCE_FC_ID, 12911 DRV_TLV_CRC_ERROR_3_TIMESTAMP, 12912 DRV_TLV_CRC_ERROR_4_RECEIVED_SOURCE_FC_ID, 12913 DRV_TLV_CRC_ERROR_4_TIMESTAMP, 12914 DRV_TLV_CRC_ERROR_5_RECEIVED_SOURCE_FC_ID, 12915 DRV_TLV_CRC_ERROR_5_TIMESTAMP, 12916 DRV_TLV_LOSS_OF_SYNC_ERROR_COUNT, 12917 DRV_TLV_LOSS_OF_SIGNAL_ERRORS, 12918 DRV_TLV_PRIMITIVE_SEQUENCE_PROTOCOL_ERROR_COUNT, 12919 DRV_TLV_DISPARITY_ERROR_COUNT, 12920 DRV_TLV_CODE_VIOLATION_ERROR_COUNT, 12921 DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_1, 12922 DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_2, 12923 DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_3, 12924 DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_4, 12925 DRV_TLV_LAST_FLOGI_TIMESTAMP, 12926 DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_1, 12927 DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_2, 12928 DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_3, 12929 DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_4, 12930 DRV_TLV_LAST_FLOGI_ACC_TIMESTAMP, 12931 DRV_TLV_LAST_FLOGI_RJT, 12932 DRV_TLV_LAST_FLOGI_RJT_TIMESTAMP, 12933 DRV_TLV_FDISCS_SENT_COUNT, 12934 DRV_TLV_FDISC_ACCS_RECEIVED, 12935 DRV_TLV_FDISC_RJTS_RECEIVED, 12936 DRV_TLV_PLOGI_SENT_COUNT, 12937 DRV_TLV_PLOGI_ACCS_RECEIVED, 12938 DRV_TLV_PLOGI_RJTS_RECEIVED, 12939 DRV_TLV_PLOGI_1_SENT_DESTINATION_FC_ID, 12940 DRV_TLV_PLOGI_1_TIMESTAMP, 12941 DRV_TLV_PLOGI_2_SENT_DESTINATION_FC_ID, 12942 DRV_TLV_PLOGI_2_TIMESTAMP, 12943 DRV_TLV_PLOGI_3_SENT_DESTINATION_FC_ID, 12944 DRV_TLV_PLOGI_3_TIMESTAMP, 12945 DRV_TLV_PLOGI_4_SENT_DESTINATION_FC_ID, 12946 DRV_TLV_PLOGI_4_TIMESTAMP, 12947 DRV_TLV_PLOGI_5_SENT_DESTINATION_FC_ID, 12948 DRV_TLV_PLOGI_5_TIMESTAMP, 12949 DRV_TLV_PLOGI_1_ACC_RECEIVED_SOURCE_FC_ID, 12950 DRV_TLV_PLOGI_1_ACC_TIMESTAMP, 12951 DRV_TLV_PLOGI_2_ACC_RECEIVED_SOURCE_FC_ID, 12952 DRV_TLV_PLOGI_2_ACC_TIMESTAMP, 12953 DRV_TLV_PLOGI_3_ACC_RECEIVED_SOURCE_FC_ID, 12954 DRV_TLV_PLOGI_3_ACC_TIMESTAMP, 12955 DRV_TLV_PLOGI_4_ACC_RECEIVED_SOURCE_FC_ID, 12956 DRV_TLV_PLOGI_4_ACC_TIMESTAMP, 12957 DRV_TLV_PLOGI_5_ACC_RECEIVED_SOURCE_FC_ID, 12958 DRV_TLV_PLOGI_5_ACC_TIMESTAMP, 12959 DRV_TLV_LOGOS_ISSUED, 12960 DRV_TLV_LOGO_ACCS_RECEIVED, 12961 DRV_TLV_LOGO_RJTS_RECEIVED, 12962 DRV_TLV_LOGO_1_RECEIVED_SOURCE_FC_ID, 12963 DRV_TLV_LOGO_1_TIMESTAMP, 12964 DRV_TLV_LOGO_2_RECEIVED_SOURCE_FC_ID, 12965 DRV_TLV_LOGO_2_TIMESTAMP, 12966 DRV_TLV_LOGO_3_RECEIVED_SOURCE_FC_ID, 12967 DRV_TLV_LOGO_3_TIMESTAMP, 12968 DRV_TLV_LOGO_4_RECEIVED_SOURCE_FC_ID, 12969 DRV_TLV_LOGO_4_TIMESTAMP, 12970 DRV_TLV_LOGO_5_RECEIVED_SOURCE_FC_ID, 12971 DRV_TLV_LOGO_5_TIMESTAMP, 12972 DRV_TLV_LOGOS_RECEIVED, 12973 DRV_TLV_ACCS_ISSUED, 12974 DRV_TLV_PRLIS_ISSUED, 12975 DRV_TLV_ACCS_RECEIVED, 12976 DRV_TLV_ABTS_SENT_COUNT, 12977 DRV_TLV_ABTS_ACCS_RECEIVED, 12978 DRV_TLV_ABTS_RJTS_RECEIVED, 12979 DRV_TLV_ABTS_1_SENT_DESTINATION_FC_ID, 12980 DRV_TLV_ABTS_1_TIMESTAMP, 12981 DRV_TLV_ABTS_2_SENT_DESTINATION_FC_ID, 12982 DRV_TLV_ABTS_2_TIMESTAMP, 12983 DRV_TLV_ABTS_3_SENT_DESTINATION_FC_ID, 12984 DRV_TLV_ABTS_3_TIMESTAMP, 12985 DRV_TLV_ABTS_4_SENT_DESTINATION_FC_ID, 12986 DRV_TLV_ABTS_4_TIMESTAMP, 12987 DRV_TLV_ABTS_5_SENT_DESTINATION_FC_ID, 12988 DRV_TLV_ABTS_5_TIMESTAMP, 12989 DRV_TLV_RSCNS_RECEIVED, 12990 DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_1, 12991 DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_2, 12992 DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_3, 12993 DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_4, 12994 DRV_TLV_LUN_RESETS_ISSUED, 12995 DRV_TLV_ABORT_TASK_SETS_ISSUED, 12996 DRV_TLV_TPRLOS_SENT, 12997 DRV_TLV_NOS_SENT_COUNT, 12998 DRV_TLV_NOS_RECEIVED_COUNT, 12999 DRV_TLV_OLS_COUNT, 13000 DRV_TLV_LR_COUNT, 13001 DRV_TLV_LRR_COUNT, 13002 DRV_TLV_LIP_SENT_COUNT, 13003 DRV_TLV_LIP_RECEIVED_COUNT, 13004 DRV_TLV_EOFA_COUNT, 13005 DRV_TLV_EOFNI_COUNT, 13006 DRV_TLV_SCSI_STATUS_CHECK_CONDITION_COUNT, 13007 DRV_TLV_SCSI_STATUS_CONDITION_MET_COUNT, 13008 DRV_TLV_SCSI_STATUS_BUSY_COUNT, 13009 DRV_TLV_SCSI_STATUS_INTERMEDIATE_COUNT, 13010 DRV_TLV_SCSI_STATUS_INTERMEDIATE_CONDITION_MET_COUNT, 13011 DRV_TLV_SCSI_STATUS_RESERVATION_CONFLICT_COUNT, 13012 DRV_TLV_SCSI_STATUS_TASK_SET_FULL_COUNT, 13013 DRV_TLV_SCSI_STATUS_ACA_ACTIVE_COUNT, 13014 DRV_TLV_SCSI_STATUS_TASK_ABORTED_COUNT, 13015 DRV_TLV_SCSI_CHECK_CONDITION_1_RECEIVED_SK_ASC_ASCQ, 13016 DRV_TLV_SCSI_CHECK_1_TIMESTAMP, 13017 DRV_TLV_SCSI_CHECK_CONDITION_2_RECEIVED_SK_ASC_ASCQ, 13018 DRV_TLV_SCSI_CHECK_2_TIMESTAMP, 13019 DRV_TLV_SCSI_CHECK_CONDITION_3_RECEIVED_SK_ASC_ASCQ, 13020 DRV_TLV_SCSI_CHECK_3_TIMESTAMP, 13021 DRV_TLV_SCSI_CHECK_CONDITION_4_RECEIVED_SK_ASC_ASCQ, 13022 DRV_TLV_SCSI_CHECK_4_TIMESTAMP, 13023 DRV_TLV_SCSI_CHECK_CONDITION_5_RECEIVED_SK_ASC_ASCQ, 13024 DRV_TLV_SCSI_CHECK_5_TIMESTAMP, 13025 /* Category 30: iSCSI Function Data */ 13026 DRV_TLV_PDU_TX_DESCRIPTOR_QUEUE_AVG_DEPTH, 13027 DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_AVG_DEPTH, 13028 DRV_TLV_ISCSI_PDU_RX_FRAMES_RECEIVED, 13029 DRV_TLV_ISCSI_PDU_RX_BYTES_RECEIVED, 13030 DRV_TLV_ISCSI_PDU_TX_FRAMES_SENT, 13031 DRV_TLV_ISCSI_PDU_TX_BYTES_SENT 13032 }; 13033 13034 struct nvm_cfg_mac_address { 13035 u32 mac_addr_hi; 13036 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF 13037 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0 13038 u32 mac_addr_lo; 13039 }; 13040 13041 struct nvm_cfg1_glob { 13042 u32 generic_cont0; 13043 #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0 13044 #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4 13045 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0 13046 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1 13047 #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2 13048 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3 13049 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4 13050 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5 13051 #define NVM_CFG1_GLOB_MF_MODE_BD 0x6 13052 #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7 13053 u32 engineering_change[3]; 13054 u32 manufacturing_id; 13055 u32 serial_number[4]; 13056 u32 pcie_cfg; 13057 u32 mgmt_traffic; 13058 u32 core_cfg; 13059 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF 13060 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0 13061 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0 13062 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1 13063 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2 13064 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3 13065 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4 13066 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5 13067 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xB 13068 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC 13069 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD 13070 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE 13071 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xF 13072 13073 u32 e_lane_cfg1; 13074 u32 e_lane_cfg2; 13075 u32 f_lane_cfg1; 13076 u32 f_lane_cfg2; 13077 u32 mps10_preemphasis; 13078 u32 mps10_driver_current; 13079 u32 mps25_preemphasis; 13080 u32 mps25_driver_current; 13081 u32 pci_id; 13082 u32 pci_subsys_id; 13083 u32 bar; 13084 u32 mps10_txfir_main; 13085 u32 mps10_txfir_post; 13086 u32 mps25_txfir_main; 13087 u32 mps25_txfir_post; 13088 u32 manufacture_ver; 13089 u32 manufacture_time; 13090 u32 led_global_settings; 13091 u32 generic_cont1; 13092 u32 mbi_version; 13093 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF 13094 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0 13095 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00 13096 #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8 13097 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000 13098 #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16 13099 u32 mbi_date; 13100 u32 misc_sig; 13101 u32 device_capabilities; 13102 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1 13103 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2 13104 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4 13105 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8 13106 u32 power_dissipated; 13107 u32 power_consumed; 13108 u32 efi_version; 13109 u32 multi_network_modes_capability; 13110 u32 reserved[41]; 13111 }; 13112 13113 struct nvm_cfg1_path { 13114 u32 reserved[30]; 13115 }; 13116 13117 struct nvm_cfg1_port { 13118 u32 reserved__m_relocated_to_option_123; 13119 u32 reserved__m_relocated_to_option_124; 13120 u32 generic_cont0; 13121 #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000 13122 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16 13123 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0 13124 #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1 13125 #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2 13126 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3 13127 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000 13128 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20 13129 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1 13130 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2 13131 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4 13132 u32 pcie_cfg; 13133 u32 features; 13134 u32 speed_cap_mask; 13135 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 13136 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 13137 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1 13138 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2 13139 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G 0x4 13140 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8 13141 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10 13142 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20 13143 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 13144 u32 link_settings; 13145 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F 13146 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0 13147 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0 13148 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1 13149 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2 13150 #define NVM_CFG1_PORT_DRV_LINK_SPEED_20G 0x3 13151 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4 13152 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5 13153 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6 13154 #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7 13155 #define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ 0x8 13156 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070 13157 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4 13158 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1 13159 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2 13160 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4 13161 u32 phy_cfg; 13162 u32 mgmt_traffic; 13163 13164 u32 ext_phy; 13165 /* EEE power saving mode */ 13166 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK 0x00FF0000 13167 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET 16 13168 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED 0x0 13169 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED 0x1 13170 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE 0x2 13171 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY 0x3 13172 13173 u32 mba_cfg1; 13174 u32 mba_cfg2; 13175 u32 vf_cfg; 13176 struct nvm_cfg_mac_address lldp_mac_address; 13177 u32 led_port_settings; 13178 u32 transceiver_00; 13179 u32 device_ids; 13180 u32 board_cfg; 13181 #define NVM_CFG1_PORT_PORT_TYPE_MASK 0x000000FF 13182 #define NVM_CFG1_PORT_PORT_TYPE_OFFSET 0 13183 #define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED 0x0 13184 #define NVM_CFG1_PORT_PORT_TYPE_MODULE 0x1 13185 #define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE 0x2 13186 #define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY 0x3 13187 #define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE 0x4 13188 u32 mnm_10g_cap; 13189 u32 mnm_10g_ctrl; 13190 u32 mnm_10g_misc; 13191 u32 mnm_25g_cap; 13192 u32 mnm_25g_ctrl; 13193 u32 mnm_25g_misc; 13194 u32 mnm_40g_cap; 13195 u32 mnm_40g_ctrl; 13196 u32 mnm_40g_misc; 13197 u32 mnm_50g_cap; 13198 u32 mnm_50g_ctrl; 13199 u32 mnm_50g_misc; 13200 u32 mnm_100g_cap; 13201 u32 mnm_100g_ctrl; 13202 u32 mnm_100g_misc; 13203 u32 reserved[116]; 13204 }; 13205 13206 struct nvm_cfg1_func { 13207 struct nvm_cfg_mac_address mac_address; 13208 u32 rsrv1; 13209 u32 rsrv2; 13210 u32 device_id; 13211 u32 cmn_cfg; 13212 u32 pci_cfg; 13213 struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr; 13214 struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr; 13215 u32 preboot_generic_cfg; 13216 u32 reserved[8]; 13217 }; 13218 13219 struct nvm_cfg1 { 13220 struct nvm_cfg1_glob glob; 13221 struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX]; 13222 struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX]; 13223 struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX]; 13224 }; 13225 13226 enum spad_sections { 13227 SPAD_SECTION_TRACE, 13228 SPAD_SECTION_NVM_CFG, 13229 SPAD_SECTION_PUBLIC, 13230 SPAD_SECTION_PRIVATE, 13231 SPAD_SECTION_MAX 13232 }; 13233 13234 #define MCP_TRACE_SIZE 2048 /* 2kb */ 13235 13236 /* This section is located at a fixed location in the beginning of the 13237 * scratchpad, to ensure that the MCP trace is not run over during MFW upgrade. 13238 * All the rest of data has a floating location which differs from version to 13239 * version, and is pointed by the mcp_meta_data below. 13240 * Moreover, the spad_layout section is part of the MFW firmware, and is loaded 13241 * with it from nvram in order to clear this portion. 13242 */ 13243 struct static_init { 13244 u32 num_sections; 13245 offsize_t sections[SPAD_SECTION_MAX]; 13246 #define SECTION(_sec_) (*((offsize_t *)(STRUCT_OFFSET(sections[_sec_])))) 13247 13248 struct mcp_trace trace; 13249 #define MCP_TRACE_P ((struct mcp_trace *)(STRUCT_OFFSET(trace))) 13250 u8 trace_buffer[MCP_TRACE_SIZE]; 13251 #define MCP_TRACE_BUF ((u8 *)(STRUCT_OFFSET(trace_buffer))) 13252 /* running_mfw has the same definition as in nvm_map.h. 13253 * This bit indicate both the running dir, and the running bundle. 13254 * It is set once when the LIM is loaded. 13255 */ 13256 u32 running_mfw; 13257 #define RUNNING_MFW (*((u32 *)(STRUCT_OFFSET(running_mfw)))) 13258 u32 build_time; 13259 #define MFW_BUILD_TIME (*((u32 *)(STRUCT_OFFSET(build_time)))) 13260 u32 reset_type; 13261 #define RESET_TYPE (*((u32 *)(STRUCT_OFFSET(reset_type)))) 13262 u32 mfw_secure_mode; 13263 #define MFW_SECURE_MODE (*((u32 *)(STRUCT_OFFSET(mfw_secure_mode)))) 13264 u16 pme_status_pf_bitmap; 13265 #define PME_STATUS_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_status_pf_bitmap)))) 13266 u16 pme_enable_pf_bitmap; 13267 #define PME_ENABLE_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_enable_pf_bitmap)))) 13268 u32 mim_nvm_addr; 13269 u32 mim_start_addr; 13270 u32 ah_pcie_link_params; 13271 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_MASK (0x000000ff) 13272 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_SHIFT (0) 13273 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_MASK (0x0000ff00) 13274 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_SHIFT (8) 13275 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_MASK (0x00ff0000) 13276 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_SHIFT (16) 13277 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_MASK (0xff000000) 13278 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_SHIFT (24) 13279 #define AH_PCIE_LINK_PARAMS (*((u32 *)(STRUCT_OFFSET(ah_pcie_link_params)))) 13280 13281 u32 rsrv_persist[5]; /* Persist reserved for MFW upgrades */ 13282 }; 13283 13284 #define NVM_MAGIC_VALUE 0x669955aa 13285 13286 enum nvm_image_type { 13287 NVM_TYPE_TIM1 = 0x01, 13288 NVM_TYPE_TIM2 = 0x02, 13289 NVM_TYPE_MIM1 = 0x03, 13290 NVM_TYPE_MIM2 = 0x04, 13291 NVM_TYPE_MBA = 0x05, 13292 NVM_TYPE_MODULES_PN = 0x06, 13293 NVM_TYPE_VPD = 0x07, 13294 NVM_TYPE_MFW_TRACE1 = 0x08, 13295 NVM_TYPE_MFW_TRACE2 = 0x09, 13296 NVM_TYPE_NVM_CFG1 = 0x0a, 13297 NVM_TYPE_L2B = 0x0b, 13298 NVM_TYPE_DIR1 = 0x0c, 13299 NVM_TYPE_EAGLE_FW1 = 0x0d, 13300 NVM_TYPE_FALCON_FW1 = 0x0e, 13301 NVM_TYPE_PCIE_FW1 = 0x0f, 13302 NVM_TYPE_HW_SET = 0x10, 13303 NVM_TYPE_LIM = 0x11, 13304 NVM_TYPE_AVS_FW1 = 0x12, 13305 NVM_TYPE_DIR2 = 0x13, 13306 NVM_TYPE_CCM = 0x14, 13307 NVM_TYPE_EAGLE_FW2 = 0x15, 13308 NVM_TYPE_FALCON_FW2 = 0x16, 13309 NVM_TYPE_PCIE_FW2 = 0x17, 13310 NVM_TYPE_AVS_FW2 = 0x18, 13311 NVM_TYPE_INIT_HW = 0x19, 13312 NVM_TYPE_DEFAULT_CFG = 0x1a, 13313 NVM_TYPE_MDUMP = 0x1b, 13314 NVM_TYPE_META = 0x1c, 13315 NVM_TYPE_ISCSI_CFG = 0x1d, 13316 NVM_TYPE_FCOE_CFG = 0x1f, 13317 NVM_TYPE_ETH_PHY_FW1 = 0x20, 13318 NVM_TYPE_ETH_PHY_FW2 = 0x21, 13319 NVM_TYPE_BDN = 0x22, 13320 NVM_TYPE_8485X_PHY_FW = 0x23, 13321 NVM_TYPE_PUB_KEY = 0x24, 13322 NVM_TYPE_RECOVERY = 0x25, 13323 NVM_TYPE_PLDM = 0x26, 13324 NVM_TYPE_UPK1 = 0x27, 13325 NVM_TYPE_UPK2 = 0x28, 13326 NVM_TYPE_MASTER_KC = 0x29, 13327 NVM_TYPE_BACKUP_KC = 0x2a, 13328 NVM_TYPE_HW_DUMP = 0x2b, 13329 NVM_TYPE_HW_DUMP_OUT = 0x2c, 13330 NVM_TYPE_BIN_NVM_META = 0x30, 13331 NVM_TYPE_ROM_TEST = 0xf0, 13332 NVM_TYPE_88X33X0_PHY_FW = 0x31, 13333 NVM_TYPE_88X33X0_PHY_SLAVE_FW = 0x32, 13334 NVM_TYPE_MAX, 13335 }; 13336 13337 #define DIR_ID_1 (0) 13338 13339 #endif 13340