1 /* QLogic qed NIC Driver
2  * Copyright (c) 2015-2017  QLogic Corporation
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and /or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef _QED_HSI_H
34 #define _QED_HSI_H
35 
36 #include <linux/types.h>
37 #include <linux/io.h>
38 #include <linux/bitops.h>
39 #include <linux/delay.h>
40 #include <linux/kernel.h>
41 #include <linux/list.h>
42 #include <linux/slab.h>
43 #include <linux/qed/common_hsi.h>
44 #include <linux/qed/storage_common.h>
45 #include <linux/qed/tcp_common.h>
46 #include <linux/qed/fcoe_common.h>
47 #include <linux/qed/eth_common.h>
48 #include <linux/qed/iscsi_common.h>
49 #include <linux/qed/iwarp_common.h>
50 #include <linux/qed/rdma_common.h>
51 #include <linux/qed/roce_common.h>
52 #include <linux/qed/qed_fcoe_if.h>
53 
54 struct qed_hwfn;
55 struct qed_ptt;
56 
57 /* Opcodes for the event ring */
58 enum common_event_opcode {
59 	COMMON_EVENT_PF_START,
60 	COMMON_EVENT_PF_STOP,
61 	COMMON_EVENT_VF_START,
62 	COMMON_EVENT_VF_STOP,
63 	COMMON_EVENT_VF_PF_CHANNEL,
64 	COMMON_EVENT_VF_FLR,
65 	COMMON_EVENT_PF_UPDATE,
66 	COMMON_EVENT_MALICIOUS_VF,
67 	COMMON_EVENT_RL_UPDATE,
68 	COMMON_EVENT_EMPTY,
69 	MAX_COMMON_EVENT_OPCODE
70 };
71 
72 /* Common Ramrod Command IDs */
73 enum common_ramrod_cmd_id {
74 	COMMON_RAMROD_UNUSED,
75 	COMMON_RAMROD_PF_START,
76 	COMMON_RAMROD_PF_STOP,
77 	COMMON_RAMROD_VF_START,
78 	COMMON_RAMROD_VF_STOP,
79 	COMMON_RAMROD_PF_UPDATE,
80 	COMMON_RAMROD_RL_UPDATE,
81 	COMMON_RAMROD_EMPTY,
82 	MAX_COMMON_RAMROD_CMD_ID
83 };
84 
85 /* How ll2 should deal with packet upon errors */
86 enum core_error_handle {
87 	LL2_DROP_PACKET,
88 	LL2_DO_NOTHING,
89 	LL2_ASSERT,
90 	MAX_CORE_ERROR_HANDLE
91 };
92 
93 /* Opcodes for the event ring */
94 enum core_event_opcode {
95 	CORE_EVENT_TX_QUEUE_START,
96 	CORE_EVENT_TX_QUEUE_STOP,
97 	CORE_EVENT_RX_QUEUE_START,
98 	CORE_EVENT_RX_QUEUE_STOP,
99 	CORE_EVENT_RX_QUEUE_FLUSH,
100 	CORE_EVENT_TX_QUEUE_UPDATE,
101 	MAX_CORE_EVENT_OPCODE
102 };
103 
104 /* The L4 pseudo checksum mode for Core */
105 enum core_l4_pseudo_checksum_mode {
106 	CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH,
107 	CORE_L4_PSEUDO_CSUM_ZERO_LENGTH,
108 	MAX_CORE_L4_PSEUDO_CHECKSUM_MODE
109 };
110 
111 /* Light-L2 RX Producers in Tstorm RAM */
112 struct core_ll2_port_stats {
113 	struct regpair gsi_invalid_hdr;
114 	struct regpair gsi_invalid_pkt_length;
115 	struct regpair gsi_unsupported_pkt_typ;
116 	struct regpair gsi_crcchksm_error;
117 };
118 
119 /* Ethernet TX Per Queue Stats */
120 struct core_ll2_pstorm_per_queue_stat {
121 	struct regpair sent_ucast_bytes;
122 	struct regpair sent_mcast_bytes;
123 	struct regpair sent_bcast_bytes;
124 	struct regpair sent_ucast_pkts;
125 	struct regpair sent_mcast_pkts;
126 	struct regpair sent_bcast_pkts;
127 };
128 
129 /* Light-L2 RX Producers in Tstorm RAM */
130 struct core_ll2_rx_prod {
131 	__le16 bd_prod;
132 	__le16 cqe_prod;
133 	__le32 reserved;
134 };
135 
136 struct core_ll2_tstorm_per_queue_stat {
137 	struct regpair packet_too_big_discard;
138 	struct regpair no_buff_discard;
139 };
140 
141 struct core_ll2_ustorm_per_queue_stat {
142 	struct regpair rcv_ucast_bytes;
143 	struct regpair rcv_mcast_bytes;
144 	struct regpair rcv_bcast_bytes;
145 	struct regpair rcv_ucast_pkts;
146 	struct regpair rcv_mcast_pkts;
147 	struct regpair rcv_bcast_pkts;
148 };
149 
150 /* Core Ramrod Command IDs (light L2) */
151 enum core_ramrod_cmd_id {
152 	CORE_RAMROD_UNUSED,
153 	CORE_RAMROD_RX_QUEUE_START,
154 	CORE_RAMROD_TX_QUEUE_START,
155 	CORE_RAMROD_RX_QUEUE_STOP,
156 	CORE_RAMROD_TX_QUEUE_STOP,
157 	CORE_RAMROD_RX_QUEUE_FLUSH,
158 	CORE_RAMROD_TX_QUEUE_UPDATE,
159 	MAX_CORE_RAMROD_CMD_ID
160 };
161 
162 /* Core RX CQE Type for Light L2 */
163 enum core_roce_flavor_type {
164 	CORE_ROCE,
165 	CORE_RROCE,
166 	MAX_CORE_ROCE_FLAVOR_TYPE
167 };
168 
169 /* Specifies how ll2 should deal with packets errors: packet_too_big and
170  * no_buff.
171  */
172 struct core_rx_action_on_error {
173 	u8 error_type;
174 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK	0x3
175 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT	0
176 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK		0x3
177 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT		2
178 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK		0xF
179 #define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT		4
180 };
181 
182 /* Core RX BD for Light L2 */
183 struct core_rx_bd {
184 	struct regpair addr;
185 	__le16 reserved[4];
186 };
187 
188 /* Core RX CM offload BD for Light L2 */
189 struct core_rx_bd_with_buff_len {
190 	struct regpair addr;
191 	__le16 buff_length;
192 	__le16 reserved[3];
193 };
194 
195 /* Core RX CM offload BD for Light L2 */
196 union core_rx_bd_union {
197 	struct core_rx_bd rx_bd;
198 	struct core_rx_bd_with_buff_len rx_bd_with_len;
199 };
200 
201 /* Opaque Data for Light L2 RX CQE */
202 struct core_rx_cqe_opaque_data {
203 	__le32 data[2];
204 };
205 
206 /* Core RX CQE Type for Light L2 */
207 enum core_rx_cqe_type {
208 	CORE_RX_CQE_ILLEGAL_TYPE,
209 	CORE_RX_CQE_TYPE_REGULAR,
210 	CORE_RX_CQE_TYPE_GSI_OFFLOAD,
211 	CORE_RX_CQE_TYPE_SLOW_PATH,
212 	MAX_CORE_RX_CQE_TYPE
213 };
214 
215 /* Core RX CQE for Light L2 */
216 struct core_rx_fast_path_cqe {
217 	u8 type;
218 	u8 placement_offset;
219 	struct parsing_and_err_flags parse_flags;
220 	__le16 packet_length;
221 	__le16 vlan;
222 	struct core_rx_cqe_opaque_data opaque_data;
223 	struct parsing_err_flags err_flags;
224 	__le16 reserved0;
225 	__le32 reserved1[3];
226 };
227 
228 /* Core Rx CM offload CQE */
229 struct core_rx_gsi_offload_cqe {
230 	u8 type;
231 	u8 data_length_error;
232 	struct parsing_and_err_flags parse_flags;
233 	__le16 data_length;
234 	__le16 vlan;
235 	__le32 src_mac_addrhi;
236 	__le16 src_mac_addrlo;
237 	__le16 qp_id;
238 	__le32 src_qp;
239 	__le32 reserved[3];
240 };
241 
242 /* Core RX CQE for Light L2 */
243 struct core_rx_slow_path_cqe {
244 	u8 type;
245 	u8 ramrod_cmd_id;
246 	__le16 echo;
247 	struct core_rx_cqe_opaque_data opaque_data;
248 	__le32 reserved1[5];
249 };
250 
251 /* Core RX CM offload BD for Light L2 */
252 union core_rx_cqe_union {
253 	struct core_rx_fast_path_cqe rx_cqe_fp;
254 	struct core_rx_gsi_offload_cqe rx_cqe_gsi;
255 	struct core_rx_slow_path_cqe rx_cqe_sp;
256 };
257 
258 /* Ramrod data for rx queue start ramrod */
259 struct core_rx_start_ramrod_data {
260 	struct regpair bd_base;
261 	struct regpair cqe_pbl_addr;
262 	__le16 mtu;
263 	__le16 sb_id;
264 	u8 sb_index;
265 	u8 complete_cqe_flg;
266 	u8 complete_event_flg;
267 	u8 drop_ttl0_flg;
268 	__le16 num_of_pbl_pages;
269 	u8 inner_vlan_stripping_en;
270 	u8 report_outer_vlan;
271 	u8 queue_id;
272 	u8 main_func_queue;
273 	u8 mf_si_bcast_accept_all;
274 	u8 mf_si_mcast_accept_all;
275 	struct core_rx_action_on_error action_on_error;
276 	u8 gsi_offload_flag;
277 	u8 wipe_inner_vlan_pri_en;
278 	u8 reserved[5];
279 };
280 
281 /* Ramrod data for rx queue stop ramrod */
282 struct core_rx_stop_ramrod_data {
283 	u8 complete_cqe_flg;
284 	u8 complete_event_flg;
285 	u8 queue_id;
286 	u8 reserved1;
287 	__le16 reserved2[2];
288 };
289 
290 /* Flags for Core TX BD */
291 struct core_tx_bd_data {
292 	__le16 as_bitfield;
293 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK		0x1
294 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT		0
295 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK		0x1
296 #define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT		1
297 #define CORE_TX_BD_DATA_START_BD_MASK			0x1
298 #define CORE_TX_BD_DATA_START_BD_SHIFT			2
299 #define CORE_TX_BD_DATA_IP_CSUM_MASK			0x1
300 #define CORE_TX_BD_DATA_IP_CSUM_SHIFT			3
301 #define CORE_TX_BD_DATA_L4_CSUM_MASK			0x1
302 #define CORE_TX_BD_DATA_L4_CSUM_SHIFT			4
303 #define CORE_TX_BD_DATA_IPV6_EXT_MASK			0x1
304 #define CORE_TX_BD_DATA_IPV6_EXT_SHIFT			5
305 #define CORE_TX_BD_DATA_L4_PROTOCOL_MASK		0x1
306 #define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT		6
307 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK	0x1
308 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT	7
309 #define CORE_TX_BD_DATA_NBDS_MASK			0xF
310 #define CORE_TX_BD_DATA_NBDS_SHIFT			8
311 #define CORE_TX_BD_DATA_ROCE_FLAV_MASK			0x1
312 #define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT			12
313 #define CORE_TX_BD_DATA_IP_LEN_MASK			0x1
314 #define CORE_TX_BD_DATA_IP_LEN_SHIFT			13
315 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_MASK	0x1
316 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_SHIFT	14
317 #define CORE_TX_BD_DATA_RESERVED0_MASK			0x1
318 #define CORE_TX_BD_DATA_RESERVED0_SHIFT			15
319 };
320 
321 /* Core TX BD for Light L2 */
322 struct core_tx_bd {
323 	struct regpair addr;
324 	__le16 nbytes;
325 	__le16 nw_vlan_or_lb_echo;
326 	struct core_tx_bd_data bd_data;
327 	__le16 bitfield1;
328 #define CORE_TX_BD_L4_HDR_OFFSET_W_MASK		0x3FFF
329 #define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT	0
330 #define CORE_TX_BD_TX_DST_MASK			0x3
331 #define CORE_TX_BD_TX_DST_SHIFT			14
332 };
333 
334 /* Light L2 TX Destination */
335 enum core_tx_dest {
336 	CORE_TX_DEST_NW,
337 	CORE_TX_DEST_LB,
338 	CORE_TX_DEST_RESERVED,
339 	CORE_TX_DEST_DROP,
340 	MAX_CORE_TX_DEST
341 };
342 
343 /* Ramrod data for tx queue start ramrod */
344 struct core_tx_start_ramrod_data {
345 	struct regpair pbl_base_addr;
346 	__le16 mtu;
347 	__le16 sb_id;
348 	u8 sb_index;
349 	u8 stats_en;
350 	u8 stats_id;
351 	u8 conn_type;
352 	__le16 pbl_size;
353 	__le16 qm_pq_id;
354 	u8 gsi_offload_flag;
355 	u8 vport_id;
356 	u8 resrved[2];
357 };
358 
359 /* Ramrod data for tx queue stop ramrod */
360 struct core_tx_stop_ramrod_data {
361 	__le32 reserved0[2];
362 };
363 
364 /* Ramrod data for tx queue update ramrod */
365 struct core_tx_update_ramrod_data {
366 	u8 update_qm_pq_id_flg;
367 	u8 reserved0;
368 	__le16 qm_pq_id;
369 	__le32 reserved1[1];
370 };
371 
372 /* Enum flag for what type of dcb data to update */
373 enum dcb_dscp_update_mode {
374 	DONT_UPDATE_DCB_DSCP,
375 	UPDATE_DCB,
376 	UPDATE_DSCP,
377 	UPDATE_DCB_DSCP,
378 	MAX_DCB_DSCP_UPDATE_MODE
379 };
380 
381 /* The core storm context for the Ystorm */
382 struct ystorm_core_conn_st_ctx {
383 	__le32 reserved[4];
384 };
385 
386 /* The core storm context for the Pstorm */
387 struct pstorm_core_conn_st_ctx {
388 	__le32 reserved[4];
389 };
390 
391 /* Core Slowpath Connection storm context of Xstorm */
392 struct xstorm_core_conn_st_ctx {
393 	__le32 spq_base_lo;
394 	__le32 spq_base_hi;
395 	struct regpair consolid_base_addr;
396 	__le16 spq_cons;
397 	__le16 consolid_cons;
398 	__le32 reserved0[55];
399 };
400 
401 struct e4_xstorm_core_conn_ag_ctx {
402 	u8 reserved0;
403 	u8 state;
404 	u8 flags0;
405 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
406 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
407 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK	0x1
408 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT	1
409 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK	0x1
410 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT	2
411 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
412 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT	3
413 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK	0x1
414 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT	4
415 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK	0x1
416 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT	5
417 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK	0x1
418 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT	6
419 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK	0x1
420 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT	7
421 	u8 flags1;
422 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK	0x1
423 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT	0
424 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK	0x1
425 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT	1
426 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK	0x1
427 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT	2
428 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_MASK		0x1
429 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT		3
430 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_MASK		0x1
431 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT		4
432 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_MASK		0x1
433 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT		5
434 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK	0x1
435 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT	6
436 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK	0x1
437 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT	7
438 	u8 flags2;
439 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_MASK	0x3
440 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT	0
441 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_MASK	0x3
442 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT	2
443 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_MASK	0x3
444 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT	4
445 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_MASK	0x3
446 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT	6
447 	u8 flags3;
448 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_MASK	0x3
449 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT	0
450 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_MASK	0x3
451 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT	2
452 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_MASK	0x3
453 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT	4
454 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_MASK	0x3
455 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT	6
456 	u8 flags4;
457 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_MASK	0x3
458 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT	0
459 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_MASK	0x3
460 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT	2
461 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_MASK	0x3
462 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT	4
463 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_MASK	0x3
464 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT	6
465 	u8 flags5;
466 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_MASK	0x3
467 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT	0
468 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_MASK	0x3
469 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT	2
470 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_MASK	0x3
471 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT	4
472 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_MASK	0x3
473 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT	6
474 	u8 flags6;
475 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK	0x3
476 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT	0
477 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_MASK			0x3
478 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT			2
479 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK			0x3
480 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT			4
481 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK		0x3
482 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT		6
483 	u8 flags7;
484 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK	0x3
485 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT	0
486 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK	0x3
487 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT	2
488 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK	0x3
489 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT	4
490 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK		0x1
491 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT		6
492 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK		0x1
493 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT		7
494 	u8 flags8;
495 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK	0x1
496 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT	0
497 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK	0x1
498 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT	1
499 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK	0x1
500 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT	2
501 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK	0x1
502 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT	3
503 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK	0x1
504 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT	4
505 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK	0x1
506 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT	5
507 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK	0x1
508 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT	6
509 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK	0x1
510 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT	7
511 	u8 flags9;
512 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK			0x1
513 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT			0
514 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK			0x1
515 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT			1
516 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK			0x1
517 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT			2
518 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK			0x1
519 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT			3
520 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK			0x1
521 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT			4
522 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK			0x1
523 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT			5
524 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK	0x1
525 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT	6
526 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK			0x1
527 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT			7
528 	u8 flags10;
529 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK		0x1
530 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT		0
531 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK		0x1
532 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT	1
533 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK		0x1
534 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT		2
535 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK		0x1
536 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT		3
537 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK		0x1
538 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT		4
539 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK			0x1
540 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT			5
541 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK		0x1
542 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT		6
543 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK		0x1
544 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT		7
545 	u8 flags11;
546 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK	0x1
547 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT	0
548 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK	0x1
549 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT	1
550 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK	0x1
551 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT	2
552 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK		0x1
553 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT	3
554 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK		0x1
555 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT	4
556 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK		0x1
557 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT	5
558 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK	0x1
559 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT	6
560 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK		0x1
561 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT	7
562 	u8 flags12;
563 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK	0x1
564 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT	0
565 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK	0x1
566 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT	1
567 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK	0x1
568 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT	2
569 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK	0x1
570 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT	3
571 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK	0x1
572 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT	4
573 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK	0x1
574 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT	5
575 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK	0x1
576 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT	6
577 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK	0x1
578 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT	7
579 	u8 flags13;
580 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK	0x1
581 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT	0
582 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK	0x1
583 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT	1
584 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK	0x1
585 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT	2
586 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK	0x1
587 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT	3
588 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK	0x1
589 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT	4
590 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK	0x1
591 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT	5
592 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK	0x1
593 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT	6
594 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK	0x1
595 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT	7
596 	u8 flags14;
597 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_MASK	0x1
598 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT	0
599 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_MASK	0x1
600 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT	1
601 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_MASK	0x1
602 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT	2
603 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_MASK	0x1
604 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT	3
605 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_MASK	0x1
606 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT	4
607 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_MASK	0x1
608 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT	5
609 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_MASK	0x3
610 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT	6
611 	u8 byte2;
612 	__le16 physical_q0;
613 	__le16 consolid_prod;
614 	__le16 reserved16;
615 	__le16 tx_bd_cons;
616 	__le16 tx_bd_or_spq_prod;
617 	__le16 updated_qm_pq_id;
618 	__le16 conn_dpi;
619 	u8 byte3;
620 	u8 byte4;
621 	u8 byte5;
622 	u8 byte6;
623 	__le32 reg0;
624 	__le32 reg1;
625 	__le32 reg2;
626 	__le32 reg3;
627 	__le32 reg4;
628 	__le32 reg5;
629 	__le32 reg6;
630 	__le16 word7;
631 	__le16 word8;
632 	__le16 word9;
633 	__le16 word10;
634 	__le32 reg7;
635 	__le32 reg8;
636 	__le32 reg9;
637 	u8 byte7;
638 	u8 byte8;
639 	u8 byte9;
640 	u8 byte10;
641 	u8 byte11;
642 	u8 byte12;
643 	u8 byte13;
644 	u8 byte14;
645 	u8 byte15;
646 	u8 e5_reserved;
647 	__le16 word11;
648 	__le32 reg10;
649 	__le32 reg11;
650 	__le32 reg12;
651 	__le32 reg13;
652 	__le32 reg14;
653 	__le32 reg15;
654 	__le32 reg16;
655 	__le32 reg17;
656 	__le32 reg18;
657 	__le32 reg19;
658 	__le16 word12;
659 	__le16 word13;
660 	__le16 word14;
661 	__le16 word15;
662 };
663 
664 struct e4_tstorm_core_conn_ag_ctx {
665 	u8 byte0;
666 	u8 byte1;
667 	u8 flags0;
668 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_MASK	0x1
669 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT	0
670 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_MASK	0x1
671 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT	1
672 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_MASK	0x1
673 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT	2
674 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_MASK	0x1
675 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT	3
676 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_MASK	0x1
677 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT	4
678 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_MASK	0x1
679 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT	5
680 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_MASK	0x3
681 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT	6
682 	u8 flags1;
683 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_MASK	0x3
684 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT	0
685 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_MASK	0x3
686 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT	2
687 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_MASK	0x3
688 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT	4
689 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_MASK	0x3
690 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT	6
691 	u8 flags2;
692 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_MASK	0x3
693 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT	0
694 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_MASK	0x3
695 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT	2
696 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_MASK	0x3
697 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT	4
698 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_MASK	0x3
699 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT	6
700 	u8 flags3;
701 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_MASK	0x3
702 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT	0
703 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_MASK	0x3
704 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT	2
705 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK	0x1
706 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT	4
707 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK	0x1
708 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT	5
709 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK	0x1
710 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT	6
711 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK	0x1
712 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT	7
713 	u8 flags4;
714 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK		0x1
715 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT		0
716 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK		0x1
717 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT		1
718 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK		0x1
719 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT		2
720 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK		0x1
721 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT		3
722 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK		0x1
723 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT		4
724 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK		0x1
725 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT		5
726 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK		0x1
727 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT		6
728 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK		0x1
729 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT	7
730 	u8 flags5;
731 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK		0x1
732 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT	0
733 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK		0x1
734 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT	1
735 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK		0x1
736 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT	2
737 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK		0x1
738 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT	3
739 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK		0x1
740 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT	4
741 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK		0x1
742 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT	5
743 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK		0x1
744 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT	6
745 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK		0x1
746 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT	7
747 	__le32 reg0;
748 	__le32 reg1;
749 	__le32 reg2;
750 	__le32 reg3;
751 	__le32 reg4;
752 	__le32 reg5;
753 	__le32 reg6;
754 	__le32 reg7;
755 	__le32 reg8;
756 	u8 byte2;
757 	u8 byte3;
758 	__le16 word0;
759 	u8 byte4;
760 	u8 byte5;
761 	__le16 word1;
762 	__le16 word2;
763 	__le16 word3;
764 	__le32 reg9;
765 	__le32 reg10;
766 };
767 
768 struct e4_ustorm_core_conn_ag_ctx {
769 	u8 reserved;
770 	u8 byte1;
771 	u8 flags0;
772 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_MASK	0x1
773 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT	0
774 #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_MASK	0x1
775 #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT	1
776 #define E4_USTORM_CORE_CONN_AG_CTX_CF0_MASK	0x3
777 #define E4_USTORM_CORE_CONN_AG_CTX_CF0_SHIFT	2
778 #define E4_USTORM_CORE_CONN_AG_CTX_CF1_MASK	0x3
779 #define E4_USTORM_CORE_CONN_AG_CTX_CF1_SHIFT	4
780 #define E4_USTORM_CORE_CONN_AG_CTX_CF2_MASK	0x3
781 #define E4_USTORM_CORE_CONN_AG_CTX_CF2_SHIFT	6
782 	u8 flags1;
783 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_MASK	0x3
784 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_SHIFT	0
785 #define E4_USTORM_CORE_CONN_AG_CTX_CF4_MASK	0x3
786 #define E4_USTORM_CORE_CONN_AG_CTX_CF4_SHIFT	2
787 #define E4_USTORM_CORE_CONN_AG_CTX_CF5_MASK	0x3
788 #define E4_USTORM_CORE_CONN_AG_CTX_CF5_SHIFT	4
789 #define E4_USTORM_CORE_CONN_AG_CTX_CF6_MASK	0x3
790 #define E4_USTORM_CORE_CONN_AG_CTX_CF6_SHIFT	6
791 	u8 flags2;
792 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_MASK		0x1
793 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT		0
794 #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_MASK		0x1
795 #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT		1
796 #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_MASK		0x1
797 #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT		2
798 #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_MASK		0x1
799 #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT		3
800 #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_MASK		0x1
801 #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT		4
802 #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_MASK		0x1
803 #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT		5
804 #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_MASK		0x1
805 #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT		6
806 #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK		0x1
807 #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT	7
808 	u8 flags3;
809 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK		0x1
810 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT	0
811 #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK		0x1
812 #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT	1
813 #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK		0x1
814 #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT	2
815 #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK		0x1
816 #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT	3
817 #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK		0x1
818 #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT	4
819 #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK		0x1
820 #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT	5
821 #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK		0x1
822 #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT	6
823 #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK		0x1
824 #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT	7
825 	u8 byte2;
826 	u8 byte3;
827 	__le16 word0;
828 	__le16 word1;
829 	__le32 rx_producers;
830 	__le32 reg1;
831 	__le32 reg2;
832 	__le32 reg3;
833 	__le16 word2;
834 	__le16 word3;
835 };
836 
837 /* The core storm context for the Mstorm */
838 struct mstorm_core_conn_st_ctx {
839 	__le32 reserved[24];
840 };
841 
842 /* The core storm context for the Ustorm */
843 struct ustorm_core_conn_st_ctx {
844 	__le32 reserved[4];
845 };
846 
847 /* core connection context */
848 struct e4_core_conn_context {
849 	struct ystorm_core_conn_st_ctx ystorm_st_context;
850 	struct regpair ystorm_st_padding[2];
851 	struct pstorm_core_conn_st_ctx pstorm_st_context;
852 	struct regpair pstorm_st_padding[2];
853 	struct xstorm_core_conn_st_ctx xstorm_st_context;
854 	struct e4_xstorm_core_conn_ag_ctx xstorm_ag_context;
855 	struct e4_tstorm_core_conn_ag_ctx tstorm_ag_context;
856 	struct e4_ustorm_core_conn_ag_ctx ustorm_ag_context;
857 	struct mstorm_core_conn_st_ctx mstorm_st_context;
858 	struct ustorm_core_conn_st_ctx ustorm_st_context;
859 	struct regpair ustorm_st_padding[2];
860 };
861 
862 struct eth_mstorm_per_pf_stat {
863 	struct regpair gre_discard_pkts;
864 	struct regpair vxlan_discard_pkts;
865 	struct regpair geneve_discard_pkts;
866 	struct regpair lb_discard_pkts;
867 };
868 
869 struct eth_mstorm_per_queue_stat {
870 	struct regpair ttl0_discard;
871 	struct regpair packet_too_big_discard;
872 	struct regpair no_buff_discard;
873 	struct regpair not_active_discard;
874 	struct regpair tpa_coalesced_pkts;
875 	struct regpair tpa_coalesced_events;
876 	struct regpair tpa_aborts_num;
877 	struct regpair tpa_coalesced_bytes;
878 };
879 
880 /* Ethernet TX Per PF */
881 struct eth_pstorm_per_pf_stat {
882 	struct regpair sent_lb_ucast_bytes;
883 	struct regpair sent_lb_mcast_bytes;
884 	struct regpair sent_lb_bcast_bytes;
885 	struct regpair sent_lb_ucast_pkts;
886 	struct regpair sent_lb_mcast_pkts;
887 	struct regpair sent_lb_bcast_pkts;
888 	struct regpair sent_gre_bytes;
889 	struct regpair sent_vxlan_bytes;
890 	struct regpair sent_geneve_bytes;
891 	struct regpair sent_gre_pkts;
892 	struct regpair sent_vxlan_pkts;
893 	struct regpair sent_geneve_pkts;
894 	struct regpair gre_drop_pkts;
895 	struct regpair vxlan_drop_pkts;
896 	struct regpair geneve_drop_pkts;
897 };
898 
899 /* Ethernet TX Per Queue Stats */
900 struct eth_pstorm_per_queue_stat {
901 	struct regpair sent_ucast_bytes;
902 	struct regpair sent_mcast_bytes;
903 	struct regpair sent_bcast_bytes;
904 	struct regpair sent_ucast_pkts;
905 	struct regpair sent_mcast_pkts;
906 	struct regpair sent_bcast_pkts;
907 	struct regpair error_drop_pkts;
908 };
909 
910 /* ETH Rx producers data */
911 struct eth_rx_rate_limit {
912 	__le16 mult;
913 	__le16 cnst;
914 	u8 add_sub_cnst;
915 	u8 reserved0;
916 	__le16 reserved1;
917 };
918 
919 /* Update RSS indirection table entry command */
920 struct eth_tstorm_rss_update_data {
921 	u8 valid;
922 	u8 vport_id;
923 	u8 ind_table_index;
924 	u8 reserved;
925 	__le16 ind_table_value;
926 	__le16 reserved1;
927 };
928 
929 struct eth_ustorm_per_pf_stat {
930 	struct regpair rcv_lb_ucast_bytes;
931 	struct regpair rcv_lb_mcast_bytes;
932 	struct regpair rcv_lb_bcast_bytes;
933 	struct regpair rcv_lb_ucast_pkts;
934 	struct regpair rcv_lb_mcast_pkts;
935 	struct regpair rcv_lb_bcast_pkts;
936 	struct regpair rcv_gre_bytes;
937 	struct regpair rcv_vxlan_bytes;
938 	struct regpair rcv_geneve_bytes;
939 	struct regpair rcv_gre_pkts;
940 	struct regpair rcv_vxlan_pkts;
941 	struct regpair rcv_geneve_pkts;
942 };
943 
944 struct eth_ustorm_per_queue_stat {
945 	struct regpair rcv_ucast_bytes;
946 	struct regpair rcv_mcast_bytes;
947 	struct regpair rcv_bcast_bytes;
948 	struct regpair rcv_ucast_pkts;
949 	struct regpair rcv_mcast_pkts;
950 	struct regpair rcv_bcast_pkts;
951 };
952 
953 /* Event Ring VF-PF Channel data */
954 struct vf_pf_channel_eqe_data {
955 	struct regpair msg_addr;
956 };
957 
958 /* Event Ring malicious VF data */
959 struct malicious_vf_eqe_data {
960 	u8 vf_id;
961 	u8 err_id;
962 	__le16 reserved[3];
963 };
964 
965 /* Event Ring initial cleanup data */
966 struct initial_cleanup_eqe_data {
967 	u8 vf_id;
968 	u8 reserved[7];
969 };
970 
971 /* Event Data Union */
972 union event_ring_data {
973 	u8 bytes[8];
974 	struct vf_pf_channel_eqe_data vf_pf_channel;
975 	struct iscsi_eqe_data iscsi_info;
976 	struct iscsi_connect_done_results iscsi_conn_done_info;
977 	union rdma_eqe_data rdma_data;
978 	struct malicious_vf_eqe_data malicious_vf;
979 	struct initial_cleanup_eqe_data vf_init_cleanup;
980 };
981 
982 /* Event Ring Entry */
983 struct event_ring_entry {
984 	u8 protocol_id;
985 	u8 opcode;
986 	__le16 reserved0;
987 	__le16 echo;
988 	u8 fw_return_code;
989 	u8 flags;
990 #define EVENT_RING_ENTRY_ASYNC_MASK		0x1
991 #define EVENT_RING_ENTRY_ASYNC_SHIFT		0
992 #define EVENT_RING_ENTRY_RESERVED1_MASK		0x7F
993 #define EVENT_RING_ENTRY_RESERVED1_SHIFT	1
994 	union event_ring_data data;
995 };
996 
997 /* Event Ring Next Page Address */
998 struct event_ring_next_addr {
999 	struct regpair addr;
1000 	__le32 reserved[2];
1001 };
1002 
1003 /* Event Ring Element */
1004 union event_ring_element {
1005 	struct event_ring_entry entry;
1006 	struct event_ring_next_addr next_addr;
1007 };
1008 
1009 /* Ports mode */
1010 enum fw_flow_ctrl_mode {
1011 	flow_ctrl_pause,
1012 	flow_ctrl_pfc,
1013 	MAX_FW_FLOW_CTRL_MODE
1014 };
1015 
1016 /* GFT profile type */
1017 enum gft_profile_type {
1018 	GFT_PROFILE_TYPE_4_TUPLE,
1019 	GFT_PROFILE_TYPE_L4_DST_PORT,
1020 	GFT_PROFILE_TYPE_IP_DST_ADDR,
1021 	GFT_PROFILE_TYPE_IP_SRC_ADDR,
1022 	GFT_PROFILE_TYPE_TUNNEL_TYPE,
1023 	MAX_GFT_PROFILE_TYPE
1024 };
1025 
1026 /* Major and Minor hsi Versions */
1027 struct hsi_fp_ver_struct {
1028 	u8 minor_ver_arr[2];
1029 	u8 major_ver_arr[2];
1030 };
1031 
1032 enum iwarp_ll2_tx_queues {
1033 	IWARP_LL2_IN_ORDER_TX_QUEUE = 1,
1034 	IWARP_LL2_ALIGNED_TX_QUEUE,
1035 	IWARP_LL2_ALIGNED_RIGHT_TRIMMED_TX_QUEUE,
1036 	IWARP_LL2_ERROR,
1037 	MAX_IWARP_LL2_TX_QUEUES
1038 };
1039 
1040 /* Malicious VF error ID */
1041 enum malicious_vf_error_id {
1042 	MALICIOUS_VF_NO_ERROR,
1043 	VF_PF_CHANNEL_NOT_READY,
1044 	VF_ZONE_MSG_NOT_VALID,
1045 	VF_ZONE_FUNC_NOT_ENABLED,
1046 	ETH_PACKET_TOO_SMALL,
1047 	ETH_ILLEGAL_VLAN_MODE,
1048 	ETH_MTU_VIOLATION,
1049 	ETH_ILLEGAL_INBAND_TAGS,
1050 	ETH_VLAN_INSERT_AND_INBAND_VLAN,
1051 	ETH_ILLEGAL_NBDS,
1052 	ETH_FIRST_BD_WO_SOP,
1053 	ETH_INSUFFICIENT_BDS,
1054 	ETH_ILLEGAL_LSO_HDR_NBDS,
1055 	ETH_ILLEGAL_LSO_MSS,
1056 	ETH_ZERO_SIZE_BD,
1057 	ETH_ILLEGAL_LSO_HDR_LEN,
1058 	ETH_INSUFFICIENT_PAYLOAD,
1059 	ETH_EDPM_OUT_OF_SYNC,
1060 	ETH_TUNN_IPV6_EXT_NBD_ERR,
1061 	ETH_CONTROL_PACKET_VIOLATION,
1062 	ETH_ANTI_SPOOFING_ERR,
1063 	ETH_PACKET_SIZE_TOO_LARGE,
1064 	MAX_MALICIOUS_VF_ERROR_ID
1065 };
1066 
1067 /* Mstorm non-triggering VF zone */
1068 struct mstorm_non_trigger_vf_zone {
1069 	struct eth_mstorm_per_queue_stat eth_queue_stat;
1070 	struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD];
1071 };
1072 
1073 /* Mstorm VF zone */
1074 struct mstorm_vf_zone {
1075 	struct mstorm_non_trigger_vf_zone non_trigger;
1076 };
1077 
1078 /* vlan header including TPID and TCI fields */
1079 struct vlan_header {
1080 	__le16 tpid;
1081 	__le16 tci;
1082 };
1083 
1084 /* outer tag configurations */
1085 struct outer_tag_config_struct {
1086 	u8 enable_stag_pri_change;
1087 	u8 pri_map_valid;
1088 	u8 reserved[2];
1089 	struct vlan_header outer_tag;
1090 	u8 inner_to_outer_pri_map[8];
1091 };
1092 
1093 /* personality per PF */
1094 enum personality_type {
1095 	BAD_PERSONALITY_TYP,
1096 	PERSONALITY_ISCSI,
1097 	PERSONALITY_FCOE,
1098 	PERSONALITY_RDMA_AND_ETH,
1099 	PERSONALITY_RDMA,
1100 	PERSONALITY_CORE,
1101 	PERSONALITY_ETH,
1102 	PERSONALITY_RESERVED,
1103 	MAX_PERSONALITY_TYPE
1104 };
1105 
1106 /* tunnel configuration */
1107 struct pf_start_tunnel_config {
1108 	u8 set_vxlan_udp_port_flg;
1109 	u8 set_geneve_udp_port_flg;
1110 	u8 set_no_inner_l2_vxlan_udp_port_flg;
1111 	u8 tunnel_clss_vxlan;
1112 	u8 tunnel_clss_l2geneve;
1113 	u8 tunnel_clss_ipgeneve;
1114 	u8 tunnel_clss_l2gre;
1115 	u8 tunnel_clss_ipgre;
1116 	__le16 vxlan_udp_port;
1117 	__le16 geneve_udp_port;
1118 	__le16 no_inner_l2_vxlan_udp_port;
1119 	__le16 reserved[3];
1120 };
1121 
1122 /* Ramrod data for PF start ramrod */
1123 struct pf_start_ramrod_data {
1124 	struct regpair event_ring_pbl_addr;
1125 	struct regpair consolid_q_pbl_addr;
1126 	struct pf_start_tunnel_config tunnel_config;
1127 	__le16 event_ring_sb_id;
1128 	u8 base_vf_id;
1129 	u8 num_vfs;
1130 	u8 event_ring_num_pages;
1131 	u8 event_ring_sb_index;
1132 	u8 path_id;
1133 	u8 warning_as_error;
1134 	u8 dont_log_ramrods;
1135 	u8 personality;
1136 	__le16 log_type_mask;
1137 	u8 mf_mode;
1138 	u8 integ_phase;
1139 	u8 allow_npar_tx_switching;
1140 	u8 reserved0;
1141 	struct hsi_fp_ver_struct hsi_fp_ver;
1142 	struct outer_tag_config_struct outer_tag_config;
1143 };
1144 
1145 /* Data for port update ramrod */
1146 struct protocol_dcb_data {
1147 	u8 dcb_enable_flag;
1148 	u8 dscp_enable_flag;
1149 	u8 dcb_priority;
1150 	u8 dcb_tc;
1151 	u8 dscp_val;
1152 	u8 dcb_dont_add_vlan0;
1153 };
1154 
1155 /* Update tunnel configuration */
1156 struct pf_update_tunnel_config {
1157 	u8 update_rx_pf_clss;
1158 	u8 update_rx_def_ucast_clss;
1159 	u8 update_rx_def_non_ucast_clss;
1160 	u8 set_vxlan_udp_port_flg;
1161 	u8 set_geneve_udp_port_flg;
1162 	u8 set_no_inner_l2_vxlan_udp_port_flg;
1163 	u8 tunnel_clss_vxlan;
1164 	u8 tunnel_clss_l2geneve;
1165 	u8 tunnel_clss_ipgeneve;
1166 	u8 tunnel_clss_l2gre;
1167 	u8 tunnel_clss_ipgre;
1168 	u8 reserved;
1169 	__le16 vxlan_udp_port;
1170 	__le16 geneve_udp_port;
1171 	__le16 no_inner_l2_vxlan_udp_port;
1172 	__le16 reserved1[3];
1173 };
1174 
1175 /* Data for port update ramrod */
1176 struct pf_update_ramrod_data {
1177 	u8 update_eth_dcb_data_mode;
1178 	u8 update_fcoe_dcb_data_mode;
1179 	u8 update_iscsi_dcb_data_mode;
1180 	u8 update_roce_dcb_data_mode;
1181 	u8 update_rroce_dcb_data_mode;
1182 	u8 update_iwarp_dcb_data_mode;
1183 	u8 update_mf_vlan_flag;
1184 	u8 update_enable_stag_pri_change;
1185 	struct protocol_dcb_data eth_dcb_data;
1186 	struct protocol_dcb_data fcoe_dcb_data;
1187 	struct protocol_dcb_data iscsi_dcb_data;
1188 	struct protocol_dcb_data roce_dcb_data;
1189 	struct protocol_dcb_data rroce_dcb_data;
1190 	struct protocol_dcb_data iwarp_dcb_data;
1191 	__le16 mf_vlan;
1192 	u8 enable_stag_pri_change;
1193 	u8 reserved;
1194 	struct pf_update_tunnel_config tunnel_config;
1195 };
1196 
1197 /* Ports mode */
1198 enum ports_mode {
1199 	ENGX2_PORTX1,
1200 	ENGX2_PORTX2,
1201 	ENGX1_PORTX1,
1202 	ENGX1_PORTX2,
1203 	ENGX1_PORTX4,
1204 	MAX_PORTS_MODE
1205 };
1206 
1207 /* use to index in hsi_fp_[major|minor]_ver_arr per protocol */
1208 enum protocol_version_array_key {
1209 	ETH_VER_KEY = 0,
1210 	ROCE_VER_KEY,
1211 	MAX_PROTOCOL_VERSION_ARRAY_KEY
1212 };
1213 
1214 /* RDMA TX Stats */
1215 struct rdma_sent_stats {
1216 	struct regpair sent_bytes;
1217 	struct regpair sent_pkts;
1218 };
1219 
1220 /* Pstorm non-triggering VF zone */
1221 struct pstorm_non_trigger_vf_zone {
1222 	struct eth_pstorm_per_queue_stat eth_queue_stat;
1223 	struct rdma_sent_stats rdma_stats;
1224 };
1225 
1226 /* Pstorm VF zone */
1227 struct pstorm_vf_zone {
1228 	struct pstorm_non_trigger_vf_zone non_trigger;
1229 	struct regpair reserved[7];
1230 };
1231 
1232 /* Ramrod Header of SPQE */
1233 struct ramrod_header {
1234 	__le32 cid;
1235 	u8 cmd_id;
1236 	u8 protocol_id;
1237 	__le16 echo;
1238 };
1239 
1240 /* RDMA RX Stats */
1241 struct rdma_rcv_stats {
1242 	struct regpair rcv_bytes;
1243 	struct regpair rcv_pkts;
1244 };
1245 
1246 /* Data for update QCN/DCQCN RL ramrod */
1247 struct rl_update_ramrod_data {
1248 	u8 qcn_update_param_flg;
1249 	u8 dcqcn_update_param_flg;
1250 	u8 rl_init_flg;
1251 	u8 rl_start_flg;
1252 	u8 rl_stop_flg;
1253 	u8 rl_id_first;
1254 	u8 rl_id_last;
1255 	u8 rl_dc_qcn_flg;
1256 	u8 dcqcn_reset_alpha_on_idle;
1257 	u8 rl_bc_stage_th;
1258 	u8 rl_timer_stage_th;
1259 	u8 reserved1;
1260 	__le32 rl_bc_rate;
1261 	__le16 rl_max_rate;
1262 	__le16 rl_r_ai;
1263 	__le16 rl_r_hai;
1264 	__le16 dcqcn_g;
1265 	__le32 dcqcn_k_us;
1266 	__le32 dcqcn_timeuot_us;
1267 	__le32 qcn_timeuot_us;
1268 	__le32 reserved2;
1269 };
1270 
1271 /* Slowpath Element (SPQE) */
1272 struct slow_path_element {
1273 	struct ramrod_header hdr;
1274 	struct regpair data_ptr;
1275 };
1276 
1277 /* Tstorm non-triggering VF zone */
1278 struct tstorm_non_trigger_vf_zone {
1279 	struct rdma_rcv_stats rdma_stats;
1280 };
1281 
1282 struct tstorm_per_port_stat {
1283 	struct regpair trunc_error_discard;
1284 	struct regpair mac_error_discard;
1285 	struct regpair mftag_filter_discard;
1286 	struct regpair eth_mac_filter_discard;
1287 	struct regpair ll2_mac_filter_discard;
1288 	struct regpair ll2_conn_disabled_discard;
1289 	struct regpair iscsi_irregular_pkt;
1290 	struct regpair fcoe_irregular_pkt;
1291 	struct regpair roce_irregular_pkt;
1292 	struct regpair iwarp_irregular_pkt;
1293 	struct regpair eth_irregular_pkt;
1294 	struct regpair toe_irregular_pkt;
1295 	struct regpair preroce_irregular_pkt;
1296 	struct regpair eth_gre_tunn_filter_discard;
1297 	struct regpair eth_vxlan_tunn_filter_discard;
1298 	struct regpair eth_geneve_tunn_filter_discard;
1299 	struct regpair eth_gft_drop_pkt;
1300 };
1301 
1302 /* Tstorm VF zone */
1303 struct tstorm_vf_zone {
1304 	struct tstorm_non_trigger_vf_zone non_trigger;
1305 };
1306 
1307 /* Tunnel classification scheme */
1308 enum tunnel_clss {
1309 	TUNNEL_CLSS_MAC_VLAN = 0,
1310 	TUNNEL_CLSS_MAC_VNI,
1311 	TUNNEL_CLSS_INNER_MAC_VLAN,
1312 	TUNNEL_CLSS_INNER_MAC_VNI,
1313 	TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE,
1314 	MAX_TUNNEL_CLSS
1315 };
1316 
1317 /* Ustorm non-triggering VF zone */
1318 struct ustorm_non_trigger_vf_zone {
1319 	struct eth_ustorm_per_queue_stat eth_queue_stat;
1320 	struct regpair vf_pf_msg_addr;
1321 };
1322 
1323 /* Ustorm triggering VF zone */
1324 struct ustorm_trigger_vf_zone {
1325 	u8 vf_pf_msg_valid;
1326 	u8 reserved[7];
1327 };
1328 
1329 /* Ustorm VF zone */
1330 struct ustorm_vf_zone {
1331 	struct ustorm_non_trigger_vf_zone non_trigger;
1332 	struct ustorm_trigger_vf_zone trigger;
1333 };
1334 
1335 /* VF-PF channel data */
1336 struct vf_pf_channel_data {
1337 	__le32 ready;
1338 	u8 valid;
1339 	u8 reserved0;
1340 	__le16 reserved1;
1341 };
1342 
1343 /* Ramrod data for VF start ramrod */
1344 struct vf_start_ramrod_data {
1345 	u8 vf_id;
1346 	u8 enable_flr_ack;
1347 	__le16 opaque_fid;
1348 	u8 personality;
1349 	u8 reserved[7];
1350 	struct hsi_fp_ver_struct hsi_fp_ver;
1351 
1352 };
1353 
1354 /* Ramrod data for VF start ramrod */
1355 struct vf_stop_ramrod_data {
1356 	u8 vf_id;
1357 	u8 reserved0;
1358 	__le16 reserved1;
1359 	__le32 reserved2;
1360 };
1361 
1362 /* VF zone size mode */
1363 enum vf_zone_size_mode {
1364 	VF_ZONE_SIZE_MODE_DEFAULT,
1365 	VF_ZONE_SIZE_MODE_DOUBLE,
1366 	VF_ZONE_SIZE_MODE_QUAD,
1367 	MAX_VF_ZONE_SIZE_MODE
1368 };
1369 
1370 /* Attentions status block */
1371 struct atten_status_block {
1372 	__le32 atten_bits;
1373 	__le32 atten_ack;
1374 	__le16 reserved0;
1375 	__le16 sb_index;
1376 	__le32 reserved1;
1377 };
1378 
1379 /* DMAE command */
1380 struct dmae_cmd {
1381 	__le32 opcode;
1382 #define DMAE_CMD_SRC_MASK		0x1
1383 #define DMAE_CMD_SRC_SHIFT		0
1384 #define DMAE_CMD_DST_MASK		0x3
1385 #define DMAE_CMD_DST_SHIFT		1
1386 #define DMAE_CMD_C_DST_MASK		0x1
1387 #define DMAE_CMD_C_DST_SHIFT		3
1388 #define DMAE_CMD_CRC_RESET_MASK		0x1
1389 #define DMAE_CMD_CRC_RESET_SHIFT	4
1390 #define DMAE_CMD_SRC_ADDR_RESET_MASK	0x1
1391 #define DMAE_CMD_SRC_ADDR_RESET_SHIFT	5
1392 #define DMAE_CMD_DST_ADDR_RESET_MASK	0x1
1393 #define DMAE_CMD_DST_ADDR_RESET_SHIFT	6
1394 #define DMAE_CMD_COMP_FUNC_MASK		0x1
1395 #define DMAE_CMD_COMP_FUNC_SHIFT	7
1396 #define DMAE_CMD_COMP_WORD_EN_MASK	0x1
1397 #define DMAE_CMD_COMP_WORD_EN_SHIFT	8
1398 #define DMAE_CMD_COMP_CRC_EN_MASK	0x1
1399 #define DMAE_CMD_COMP_CRC_EN_SHIFT	9
1400 #define DMAE_CMD_COMP_CRC_OFFSET_MASK	0x7
1401 #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
1402 #define DMAE_CMD_RESERVED1_MASK		0x1
1403 #define DMAE_CMD_RESERVED1_SHIFT	13
1404 #define DMAE_CMD_ENDIANITY_MODE_MASK	0x3
1405 #define DMAE_CMD_ENDIANITY_MODE_SHIFT	14
1406 #define DMAE_CMD_ERR_HANDLING_MASK	0x3
1407 #define DMAE_CMD_ERR_HANDLING_SHIFT	16
1408 #define DMAE_CMD_PORT_ID_MASK		0x3
1409 #define DMAE_CMD_PORT_ID_SHIFT		18
1410 #define DMAE_CMD_SRC_PF_ID_MASK		0xF
1411 #define DMAE_CMD_SRC_PF_ID_SHIFT	20
1412 #define DMAE_CMD_DST_PF_ID_MASK		0xF
1413 #define DMAE_CMD_DST_PF_ID_SHIFT	24
1414 #define DMAE_CMD_SRC_VF_ID_VALID_MASK	0x1
1415 #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
1416 #define DMAE_CMD_DST_VF_ID_VALID_MASK	0x1
1417 #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
1418 #define DMAE_CMD_RESERVED2_MASK		0x3
1419 #define DMAE_CMD_RESERVED2_SHIFT	30
1420 	__le32 src_addr_lo;
1421 	__le32 src_addr_hi;
1422 	__le32 dst_addr_lo;
1423 	__le32 dst_addr_hi;
1424 	__le16 length_dw;
1425 	__le16 opcode_b;
1426 #define DMAE_CMD_SRC_VF_ID_MASK		0xFF
1427 #define DMAE_CMD_SRC_VF_ID_SHIFT	0
1428 #define DMAE_CMD_DST_VF_ID_MASK		0xFF
1429 #define DMAE_CMD_DST_VF_ID_SHIFT	8
1430 	__le32 comp_addr_lo;
1431 	__le32 comp_addr_hi;
1432 	__le32 comp_val;
1433 	__le32 crc32;
1434 	__le32 crc_32_c;
1435 	__le16 crc16;
1436 	__le16 crc16_c;
1437 	__le16 crc10;
1438 	__le16 reserved;
1439 	__le16 xsum16;
1440 	__le16 xsum8;
1441 };
1442 
1443 enum dmae_cmd_comp_crc_en_enum {
1444 	dmae_cmd_comp_crc_disabled,
1445 	dmae_cmd_comp_crc_enabled,
1446 	MAX_DMAE_CMD_COMP_CRC_EN_ENUM
1447 };
1448 
1449 enum dmae_cmd_comp_func_enum {
1450 	dmae_cmd_comp_func_to_src,
1451 	dmae_cmd_comp_func_to_dst,
1452 	MAX_DMAE_CMD_COMP_FUNC_ENUM
1453 };
1454 
1455 enum dmae_cmd_comp_word_en_enum {
1456 	dmae_cmd_comp_word_disabled,
1457 	dmae_cmd_comp_word_enabled,
1458 	MAX_DMAE_CMD_COMP_WORD_EN_ENUM
1459 };
1460 
1461 enum dmae_cmd_c_dst_enum {
1462 	dmae_cmd_c_dst_pcie,
1463 	dmae_cmd_c_dst_grc,
1464 	MAX_DMAE_CMD_C_DST_ENUM
1465 };
1466 
1467 enum dmae_cmd_dst_enum {
1468 	dmae_cmd_dst_none_0,
1469 	dmae_cmd_dst_pcie,
1470 	dmae_cmd_dst_grc,
1471 	dmae_cmd_dst_none_3,
1472 	MAX_DMAE_CMD_DST_ENUM
1473 };
1474 
1475 enum dmae_cmd_error_handling_enum {
1476 	dmae_cmd_error_handling_send_regular_comp,
1477 	dmae_cmd_error_handling_send_comp_with_err,
1478 	dmae_cmd_error_handling_dont_send_comp,
1479 	MAX_DMAE_CMD_ERROR_HANDLING_ENUM
1480 };
1481 
1482 enum dmae_cmd_src_enum {
1483 	dmae_cmd_src_pcie,
1484 	dmae_cmd_src_grc,
1485 	MAX_DMAE_CMD_SRC_ENUM
1486 };
1487 
1488 struct e4_mstorm_core_conn_ag_ctx {
1489 	u8 byte0;
1490 	u8 byte1;
1491 	u8 flags0;
1492 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_MASK	0x1
1493 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT	0
1494 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_MASK	0x1
1495 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT	1
1496 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_MASK	0x3
1497 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT	2
1498 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_MASK	0x3
1499 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT	4
1500 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_MASK	0x3
1501 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT	6
1502 	u8 flags1;
1503 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK		0x1
1504 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT		0
1505 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK		0x1
1506 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT		1
1507 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK		0x1
1508 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT		2
1509 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK		0x1
1510 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT	3
1511 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK		0x1
1512 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT	4
1513 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK		0x1
1514 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT	5
1515 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK		0x1
1516 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT	6
1517 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK		0x1
1518 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT	7
1519 	__le16 word0;
1520 	__le16 word1;
1521 	__le32 reg0;
1522 	__le32 reg1;
1523 };
1524 
1525 struct e4_ystorm_core_conn_ag_ctx {
1526 	u8 byte0;
1527 	u8 byte1;
1528 	u8 flags0;
1529 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_MASK	0x1
1530 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT	0
1531 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_MASK	0x1
1532 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT	1
1533 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_MASK	0x3
1534 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT	2
1535 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_MASK	0x3
1536 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT	4
1537 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_MASK	0x3
1538 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT	6
1539 	u8 flags1;
1540 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK		0x1
1541 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT		0
1542 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK		0x1
1543 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT		1
1544 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK		0x1
1545 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT		2
1546 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK		0x1
1547 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT	3
1548 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK		0x1
1549 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT	4
1550 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK		0x1
1551 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT	5
1552 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK		0x1
1553 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT	6
1554 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK		0x1
1555 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT	7
1556 	u8 byte2;
1557 	u8 byte3;
1558 	__le16 word0;
1559 	__le32 reg0;
1560 	__le32 reg1;
1561 	__le16 word1;
1562 	__le16 word2;
1563 	__le16 word3;
1564 	__le16 word4;
1565 	__le32 reg2;
1566 	__le32 reg3;
1567 };
1568 
1569 /* IGU cleanup command */
1570 struct igu_cleanup {
1571 	__le32 sb_id_and_flags;
1572 #define IGU_CLEANUP_RESERVED0_MASK	0x7FFFFFF
1573 #define IGU_CLEANUP_RESERVED0_SHIFT	0
1574 #define IGU_CLEANUP_CLEANUP_SET_MASK	0x1
1575 #define IGU_CLEANUP_CLEANUP_SET_SHIFT	27
1576 #define IGU_CLEANUP_CLEANUP_TYPE_MASK	0x7
1577 #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT	28
1578 #define IGU_CLEANUP_COMMAND_TYPE_MASK	0x1
1579 #define IGU_CLEANUP_COMMAND_TYPE_SHIFT	31
1580 	__le32 reserved1;
1581 };
1582 
1583 /* IGU firmware driver command */
1584 union igu_command {
1585 	struct igu_prod_cons_update prod_cons_update;
1586 	struct igu_cleanup cleanup;
1587 };
1588 
1589 /* IGU firmware driver command */
1590 struct igu_command_reg_ctrl {
1591 	__le16 opaque_fid;
1592 	__le16 igu_command_reg_ctrl_fields;
1593 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK	0xFFF
1594 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT	0
1595 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK	0x7
1596 #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT	12
1597 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK	0x1
1598 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT	15
1599 };
1600 
1601 /* IGU mapping line structure */
1602 struct igu_mapping_line {
1603 	__le32 igu_mapping_line_fields;
1604 #define IGU_MAPPING_LINE_VALID_MASK		0x1
1605 #define IGU_MAPPING_LINE_VALID_SHIFT		0
1606 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK	0xFF
1607 #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT	1
1608 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK	0xFF
1609 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT	9
1610 #define IGU_MAPPING_LINE_PF_VALID_MASK		0x1
1611 #define IGU_MAPPING_LINE_PF_VALID_SHIFT		17
1612 #define IGU_MAPPING_LINE_IPS_GROUP_MASK		0x3F
1613 #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT	18
1614 #define IGU_MAPPING_LINE_RESERVED_MASK		0xFF
1615 #define IGU_MAPPING_LINE_RESERVED_SHIFT		24
1616 };
1617 
1618 /* IGU MSIX line structure */
1619 struct igu_msix_vector {
1620 	struct regpair address;
1621 	__le32 data;
1622 	__le32 msix_vector_fields;
1623 #define IGU_MSIX_VECTOR_MASK_BIT_MASK		0x1
1624 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT		0
1625 #define IGU_MSIX_VECTOR_RESERVED0_MASK		0x7FFF
1626 #define IGU_MSIX_VECTOR_RESERVED0_SHIFT		1
1627 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK	0xFF
1628 #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT	16
1629 #define IGU_MSIX_VECTOR_RESERVED1_MASK		0xFF
1630 #define IGU_MSIX_VECTOR_RESERVED1_SHIFT		24
1631 };
1632 /* per encapsulation type enabling flags */
1633 struct prs_reg_encapsulation_type_en {
1634 	u8 flags;
1635 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK		0x1
1636 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT		0
1637 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK		0x1
1638 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT		1
1639 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK			0x1
1640 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT		2
1641 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK			0x1
1642 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT		3
1643 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK	0x1
1644 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT	4
1645 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK	0x1
1646 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT	5
1647 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK			0x3
1648 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT			6
1649 };
1650 
1651 enum pxp_tph_st_hint {
1652 	TPH_ST_HINT_BIDIR,
1653 	TPH_ST_HINT_REQUESTER,
1654 	TPH_ST_HINT_TARGET,
1655 	TPH_ST_HINT_TARGET_PRIO,
1656 	MAX_PXP_TPH_ST_HINT
1657 };
1658 
1659 /* QM hardware structure of enable bypass credit mask */
1660 struct qm_rf_bypass_mask {
1661 	u8 flags;
1662 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK		0x1
1663 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT		0
1664 #define QM_RF_BYPASS_MASK_RESERVED0_MASK	0x1
1665 #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT	1
1666 #define QM_RF_BYPASS_MASK_PFWFQ_MASK		0x1
1667 #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT		2
1668 #define QM_RF_BYPASS_MASK_VPWFQ_MASK		0x1
1669 #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT		3
1670 #define QM_RF_BYPASS_MASK_PFRL_MASK		0x1
1671 #define QM_RF_BYPASS_MASK_PFRL_SHIFT		4
1672 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK		0x1
1673 #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT		5
1674 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK		0x1
1675 #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT		6
1676 #define QM_RF_BYPASS_MASK_RESERVED1_MASK	0x1
1677 #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT	7
1678 };
1679 
1680 /* QM hardware structure of opportunistic credit mask */
1681 struct qm_rf_opportunistic_mask {
1682 	__le16 flags;
1683 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK		0x1
1684 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT		0
1685 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK		0x1
1686 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT		1
1687 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK		0x1
1688 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT		2
1689 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK		0x1
1690 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT		3
1691 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK		0x1
1692 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT		4
1693 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK		0x1
1694 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT		5
1695 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK		0x1
1696 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT		6
1697 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK		0x1
1698 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT	7
1699 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK	0x1
1700 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT	8
1701 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK		0x7F
1702 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT	9
1703 };
1704 
1705 /* QM hardware structure of QM map memory */
1706 struct qm_rf_pq_map_e4 {
1707 	__le32 reg;
1708 #define QM_RF_PQ_MAP_E4_PQ_VALID_MASK		0x1
1709 #define QM_RF_PQ_MAP_E4_PQ_VALID_SHIFT		0
1710 #define QM_RF_PQ_MAP_E4_RL_ID_MASK		0xFF
1711 #define QM_RF_PQ_MAP_E4_RL_ID_SHIFT		1
1712 #define QM_RF_PQ_MAP_E4_VP_PQ_ID_MASK		0x1FF
1713 #define QM_RF_PQ_MAP_E4_VP_PQ_ID_SHIFT		9
1714 #define QM_RF_PQ_MAP_E4_VOQ_MASK		0x1F
1715 #define QM_RF_PQ_MAP_E4_VOQ_SHIFT		18
1716 #define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_MASK	0x3
1717 #define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_SHIFT	23
1718 #define QM_RF_PQ_MAP_E4_RL_VALID_MASK		0x1
1719 #define QM_RF_PQ_MAP_E4_RL_VALID_SHIFT		25
1720 #define QM_RF_PQ_MAP_E4_RESERVED_MASK		0x3F
1721 #define QM_RF_PQ_MAP_E4_RESERVED_SHIFT		26
1722 };
1723 
1724 /* Completion params for aggregated interrupt completion */
1725 struct sdm_agg_int_comp_params {
1726 	__le16 params;
1727 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK	0x3F
1728 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT	0
1729 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK	0x1
1730 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT	6
1731 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK	0x1FF
1732 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT	7
1733 };
1734 
1735 /* SDM operation gen command (generate aggregative interrupt) */
1736 struct sdm_op_gen {
1737 	__le32 command;
1738 #define SDM_OP_GEN_COMP_PARAM_MASK	0xFFFF
1739 #define SDM_OP_GEN_COMP_PARAM_SHIFT	0
1740 #define SDM_OP_GEN_COMP_TYPE_MASK	0xF
1741 #define SDM_OP_GEN_COMP_TYPE_SHIFT	16
1742 #define SDM_OP_GEN_RESERVED_MASK	0xFFF
1743 #define SDM_OP_GEN_RESERVED_SHIFT	20
1744 };
1745 
1746 /****************************************/
1747 /* Debug Tools HSI constants and macros */
1748 /****************************************/
1749 
1750 enum block_addr {
1751 	GRCBASE_GRC = 0x50000,
1752 	GRCBASE_MISCS = 0x9000,
1753 	GRCBASE_MISC = 0x8000,
1754 	GRCBASE_DBU = 0xa000,
1755 	GRCBASE_PGLUE_B = 0x2a8000,
1756 	GRCBASE_CNIG = 0x218000,
1757 	GRCBASE_CPMU = 0x30000,
1758 	GRCBASE_NCSI = 0x40000,
1759 	GRCBASE_OPTE = 0x53000,
1760 	GRCBASE_BMB = 0x540000,
1761 	GRCBASE_PCIE = 0x54000,
1762 	GRCBASE_MCP = 0xe00000,
1763 	GRCBASE_MCP2 = 0x52000,
1764 	GRCBASE_PSWHST = 0x2a0000,
1765 	GRCBASE_PSWHST2 = 0x29e000,
1766 	GRCBASE_PSWRD = 0x29c000,
1767 	GRCBASE_PSWRD2 = 0x29d000,
1768 	GRCBASE_PSWWR = 0x29a000,
1769 	GRCBASE_PSWWR2 = 0x29b000,
1770 	GRCBASE_PSWRQ = 0x280000,
1771 	GRCBASE_PSWRQ2 = 0x240000,
1772 	GRCBASE_PGLCS = 0x0,
1773 	GRCBASE_DMAE = 0xc000,
1774 	GRCBASE_PTU = 0x560000,
1775 	GRCBASE_TCM = 0x1180000,
1776 	GRCBASE_MCM = 0x1200000,
1777 	GRCBASE_UCM = 0x1280000,
1778 	GRCBASE_XCM = 0x1000000,
1779 	GRCBASE_YCM = 0x1080000,
1780 	GRCBASE_PCM = 0x1100000,
1781 	GRCBASE_QM = 0x2f0000,
1782 	GRCBASE_TM = 0x2c0000,
1783 	GRCBASE_DORQ = 0x100000,
1784 	GRCBASE_BRB = 0x340000,
1785 	GRCBASE_SRC = 0x238000,
1786 	GRCBASE_PRS = 0x1f0000,
1787 	GRCBASE_TSDM = 0xfb0000,
1788 	GRCBASE_MSDM = 0xfc0000,
1789 	GRCBASE_USDM = 0xfd0000,
1790 	GRCBASE_XSDM = 0xf80000,
1791 	GRCBASE_YSDM = 0xf90000,
1792 	GRCBASE_PSDM = 0xfa0000,
1793 	GRCBASE_TSEM = 0x1700000,
1794 	GRCBASE_MSEM = 0x1800000,
1795 	GRCBASE_USEM = 0x1900000,
1796 	GRCBASE_XSEM = 0x1400000,
1797 	GRCBASE_YSEM = 0x1500000,
1798 	GRCBASE_PSEM = 0x1600000,
1799 	GRCBASE_RSS = 0x238800,
1800 	GRCBASE_TMLD = 0x4d0000,
1801 	GRCBASE_MULD = 0x4e0000,
1802 	GRCBASE_YULD = 0x4c8000,
1803 	GRCBASE_XYLD = 0x4c0000,
1804 	GRCBASE_PTLD = 0x5a0000,
1805 	GRCBASE_YPLD = 0x5c0000,
1806 	GRCBASE_PRM = 0x230000,
1807 	GRCBASE_PBF_PB1 = 0xda0000,
1808 	GRCBASE_PBF_PB2 = 0xda4000,
1809 	GRCBASE_RPB = 0x23c000,
1810 	GRCBASE_BTB = 0xdb0000,
1811 	GRCBASE_PBF = 0xd80000,
1812 	GRCBASE_RDIF = 0x300000,
1813 	GRCBASE_TDIF = 0x310000,
1814 	GRCBASE_CDU = 0x580000,
1815 	GRCBASE_CCFC = 0x2e0000,
1816 	GRCBASE_TCFC = 0x2d0000,
1817 	GRCBASE_IGU = 0x180000,
1818 	GRCBASE_CAU = 0x1c0000,
1819 	GRCBASE_RGFS = 0xf00000,
1820 	GRCBASE_RGSRC = 0x320000,
1821 	GRCBASE_TGFS = 0xd00000,
1822 	GRCBASE_TGSRC = 0x322000,
1823 	GRCBASE_UMAC = 0x51000,
1824 	GRCBASE_XMAC = 0x210000,
1825 	GRCBASE_DBG = 0x10000,
1826 	GRCBASE_NIG = 0x500000,
1827 	GRCBASE_WOL = 0x600000,
1828 	GRCBASE_BMBN = 0x610000,
1829 	GRCBASE_IPC = 0x20000,
1830 	GRCBASE_NWM = 0x800000,
1831 	GRCBASE_NWS = 0x700000,
1832 	GRCBASE_MS = 0x6a0000,
1833 	GRCBASE_PHY_PCIE = 0x620000,
1834 	GRCBASE_LED = 0x6b8000,
1835 	GRCBASE_AVS_WRAP = 0x6b0000,
1836 	GRCBASE_PXPREQBUS = 0x56000,
1837 	GRCBASE_MISC_AEU = 0x8000,
1838 	GRCBASE_BAR0_MAP = 0x1c00000,
1839 	MAX_BLOCK_ADDR
1840 };
1841 
1842 enum block_id {
1843 	BLOCK_GRC,
1844 	BLOCK_MISCS,
1845 	BLOCK_MISC,
1846 	BLOCK_DBU,
1847 	BLOCK_PGLUE_B,
1848 	BLOCK_CNIG,
1849 	BLOCK_CPMU,
1850 	BLOCK_NCSI,
1851 	BLOCK_OPTE,
1852 	BLOCK_BMB,
1853 	BLOCK_PCIE,
1854 	BLOCK_MCP,
1855 	BLOCK_MCP2,
1856 	BLOCK_PSWHST,
1857 	BLOCK_PSWHST2,
1858 	BLOCK_PSWRD,
1859 	BLOCK_PSWRD2,
1860 	BLOCK_PSWWR,
1861 	BLOCK_PSWWR2,
1862 	BLOCK_PSWRQ,
1863 	BLOCK_PSWRQ2,
1864 	BLOCK_PGLCS,
1865 	BLOCK_DMAE,
1866 	BLOCK_PTU,
1867 	BLOCK_TCM,
1868 	BLOCK_MCM,
1869 	BLOCK_UCM,
1870 	BLOCK_XCM,
1871 	BLOCK_YCM,
1872 	BLOCK_PCM,
1873 	BLOCK_QM,
1874 	BLOCK_TM,
1875 	BLOCK_DORQ,
1876 	BLOCK_BRB,
1877 	BLOCK_SRC,
1878 	BLOCK_PRS,
1879 	BLOCK_TSDM,
1880 	BLOCK_MSDM,
1881 	BLOCK_USDM,
1882 	BLOCK_XSDM,
1883 	BLOCK_YSDM,
1884 	BLOCK_PSDM,
1885 	BLOCK_TSEM,
1886 	BLOCK_MSEM,
1887 	BLOCK_USEM,
1888 	BLOCK_XSEM,
1889 	BLOCK_YSEM,
1890 	BLOCK_PSEM,
1891 	BLOCK_RSS,
1892 	BLOCK_TMLD,
1893 	BLOCK_MULD,
1894 	BLOCK_YULD,
1895 	BLOCK_XYLD,
1896 	BLOCK_PTLD,
1897 	BLOCK_YPLD,
1898 	BLOCK_PRM,
1899 	BLOCK_PBF_PB1,
1900 	BLOCK_PBF_PB2,
1901 	BLOCK_RPB,
1902 	BLOCK_BTB,
1903 	BLOCK_PBF,
1904 	BLOCK_RDIF,
1905 	BLOCK_TDIF,
1906 	BLOCK_CDU,
1907 	BLOCK_CCFC,
1908 	BLOCK_TCFC,
1909 	BLOCK_IGU,
1910 	BLOCK_CAU,
1911 	BLOCK_RGFS,
1912 	BLOCK_RGSRC,
1913 	BLOCK_TGFS,
1914 	BLOCK_TGSRC,
1915 	BLOCK_UMAC,
1916 	BLOCK_XMAC,
1917 	BLOCK_DBG,
1918 	BLOCK_NIG,
1919 	BLOCK_WOL,
1920 	BLOCK_BMBN,
1921 	BLOCK_IPC,
1922 	BLOCK_NWM,
1923 	BLOCK_NWS,
1924 	BLOCK_MS,
1925 	BLOCK_PHY_PCIE,
1926 	BLOCK_LED,
1927 	BLOCK_AVS_WRAP,
1928 	BLOCK_PXPREQBUS,
1929 	BLOCK_MISC_AEU,
1930 	BLOCK_BAR0_MAP,
1931 	MAX_BLOCK_ID
1932 };
1933 
1934 /* binary debug buffer types */
1935 enum bin_dbg_buffer_type {
1936 	BIN_BUF_DBG_MODE_TREE,
1937 	BIN_BUF_DBG_DUMP_REG,
1938 	BIN_BUF_DBG_DUMP_MEM,
1939 	BIN_BUF_DBG_IDLE_CHK_REGS,
1940 	BIN_BUF_DBG_IDLE_CHK_IMMS,
1941 	BIN_BUF_DBG_IDLE_CHK_RULES,
1942 	BIN_BUF_DBG_IDLE_CHK_PARSING_DATA,
1943 	BIN_BUF_DBG_ATTN_BLOCKS,
1944 	BIN_BUF_DBG_ATTN_REGS,
1945 	BIN_BUF_DBG_ATTN_INDEXES,
1946 	BIN_BUF_DBG_ATTN_NAME_OFFSETS,
1947 	BIN_BUF_DBG_BUS_BLOCKS,
1948 	BIN_BUF_DBG_BUS_LINES,
1949 	BIN_BUF_DBG_BUS_BLOCKS_USER_DATA,
1950 	BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS,
1951 	BIN_BUF_DBG_PARSING_STRINGS,
1952 	MAX_BIN_DBG_BUFFER_TYPE
1953 };
1954 
1955 
1956 /* Attention bit mapping */
1957 struct dbg_attn_bit_mapping {
1958 	u16 data;
1959 #define DBG_ATTN_BIT_MAPPING_VAL_MASK			0x7FFF
1960 #define DBG_ATTN_BIT_MAPPING_VAL_SHIFT			0
1961 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK	0x1
1962 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT	15
1963 };
1964 
1965 /* Attention block per-type data */
1966 struct dbg_attn_block_type_data {
1967 	u16 names_offset;
1968 	u16 reserved1;
1969 	u8 num_regs;
1970 	u8 reserved2;
1971 	u16 regs_offset;
1972 
1973 };
1974 
1975 /* Block attentions */
1976 struct dbg_attn_block {
1977 	struct dbg_attn_block_type_data per_type_data[2];
1978 };
1979 
1980 /* Attention register result */
1981 struct dbg_attn_reg_result {
1982 	u32 data;
1983 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK	0xFFFFFF
1984 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT	0
1985 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK	0xFF
1986 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_SHIFT	24
1987 	u16 block_attn_offset;
1988 	u16 reserved;
1989 	u32 sts_val;
1990 	u32 mask_val;
1991 };
1992 
1993 /* Attention block result */
1994 struct dbg_attn_block_result {
1995 	u8 block_id;
1996 	u8 data;
1997 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK	0x3
1998 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT	0
1999 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK	0x3F
2000 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT	2
2001 	u16 names_offset;
2002 	struct dbg_attn_reg_result reg_results[15];
2003 };
2004 
2005 /* Mode header */
2006 struct dbg_mode_hdr {
2007 	u16 data;
2008 #define DBG_MODE_HDR_EVAL_MODE_MASK		0x1
2009 #define DBG_MODE_HDR_EVAL_MODE_SHIFT		0
2010 #define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK	0x7FFF
2011 #define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT	1
2012 };
2013 
2014 /* Attention register */
2015 struct dbg_attn_reg {
2016 	struct dbg_mode_hdr mode;
2017 	u16 block_attn_offset;
2018 	u32 data;
2019 #define DBG_ATTN_REG_STS_ADDRESS_MASK	0xFFFFFF
2020 #define DBG_ATTN_REG_STS_ADDRESS_SHIFT	0
2021 #define DBG_ATTN_REG_NUM_REG_ATTN_MASK	0xFF
2022 #define DBG_ATTN_REG_NUM_REG_ATTN_SHIFT 24
2023 	u32 sts_clr_address;
2024 	u32 mask_address;
2025 };
2026 
2027 /* Attention types */
2028 enum dbg_attn_type {
2029 	ATTN_TYPE_INTERRUPT,
2030 	ATTN_TYPE_PARITY,
2031 	MAX_DBG_ATTN_TYPE
2032 };
2033 
2034 /* Debug Bus block data */
2035 struct dbg_bus_block {
2036 	u8 num_of_lines;
2037 	u8 has_latency_events;
2038 	u16 lines_offset;
2039 };
2040 
2041 /* Debug Bus block user data */
2042 struct dbg_bus_block_user_data {
2043 	u8 num_of_lines;
2044 	u8 has_latency_events;
2045 	u16 names_offset;
2046 };
2047 
2048 /* Block Debug line data */
2049 struct dbg_bus_line {
2050 	u8 data;
2051 #define DBG_BUS_LINE_NUM_OF_GROUPS_MASK		0xF
2052 #define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT	0
2053 #define DBG_BUS_LINE_IS_256B_MASK		0x1
2054 #define DBG_BUS_LINE_IS_256B_SHIFT		4
2055 #define DBG_BUS_LINE_RESERVED_MASK		0x7
2056 #define DBG_BUS_LINE_RESERVED_SHIFT		5
2057 	u8 group_sizes;
2058 };
2059 
2060 /* Condition header for registers dump */
2061 struct dbg_dump_cond_hdr {
2062 	struct dbg_mode_hdr mode; /* Mode header */
2063 	u8 block_id; /* block ID */
2064 	u8 data_size; /* size in dwords of the data following this header */
2065 };
2066 
2067 /* Memory data for registers dump */
2068 struct dbg_dump_mem {
2069 	u32 dword0;
2070 #define DBG_DUMP_MEM_ADDRESS_MASK	0xFFFFFF
2071 #define DBG_DUMP_MEM_ADDRESS_SHIFT	0
2072 #define DBG_DUMP_MEM_MEM_GROUP_ID_MASK	0xFF
2073 #define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT	24
2074 	u32 dword1;
2075 #define DBG_DUMP_MEM_LENGTH_MASK	0xFFFFFF
2076 #define DBG_DUMP_MEM_LENGTH_SHIFT	0
2077 #define DBG_DUMP_MEM_WIDE_BUS_MASK	0x1
2078 #define DBG_DUMP_MEM_WIDE_BUS_SHIFT	24
2079 #define DBG_DUMP_MEM_RESERVED_MASK	0x7F
2080 #define DBG_DUMP_MEM_RESERVED_SHIFT	25
2081 };
2082 
2083 /* Register data for registers dump */
2084 struct dbg_dump_reg {
2085 	u32 data;
2086 #define DBG_DUMP_REG_ADDRESS_MASK	0x7FFFFF
2087 #define DBG_DUMP_REG_ADDRESS_SHIFT	0
2088 #define DBG_DUMP_REG_WIDE_BUS_MASK	0x1
2089 #define DBG_DUMP_REG_WIDE_BUS_SHIFT	23
2090 #define DBG_DUMP_REG_LENGTH_MASK	0xFF
2091 #define DBG_DUMP_REG_LENGTH_SHIFT	24
2092 };
2093 
2094 /* Split header for registers dump */
2095 struct dbg_dump_split_hdr {
2096 	u32 hdr;
2097 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK	0xFFFFFF
2098 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT	0
2099 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK	0xFF
2100 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT	24
2101 };
2102 
2103 /* Condition header for idle check */
2104 struct dbg_idle_chk_cond_hdr {
2105 	struct dbg_mode_hdr mode; /* Mode header */
2106 	u16 data_size; /* size in dwords of the data following this header */
2107 };
2108 
2109 /* Idle Check condition register */
2110 struct dbg_idle_chk_cond_reg {
2111 	u32 data;
2112 #define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK	0x7FFFFF
2113 #define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT	0
2114 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK	0x1
2115 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT	23
2116 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK	0xFF
2117 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT	24
2118 	u16 num_entries;
2119 	u8 entry_size;
2120 	u8 start_entry;
2121 };
2122 
2123 /* Idle Check info register */
2124 struct dbg_idle_chk_info_reg {
2125 	u32 data;
2126 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK	0x7FFFFF
2127 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT	0
2128 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK	0x1
2129 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT	23
2130 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK	0xFF
2131 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT	24
2132 	u16 size; /* register size in dwords */
2133 	struct dbg_mode_hdr mode; /* Mode header */
2134 };
2135 
2136 /* Idle Check register */
2137 union dbg_idle_chk_reg {
2138 	struct dbg_idle_chk_cond_reg cond_reg; /* condition register */
2139 	struct dbg_idle_chk_info_reg info_reg; /* info register */
2140 };
2141 
2142 /* Idle Check result header */
2143 struct dbg_idle_chk_result_hdr {
2144 	u16 rule_id; /* Failing rule index */
2145 	u16 mem_entry_id; /* Failing memory entry index */
2146 	u8 num_dumped_cond_regs; /* number of dumped condition registers */
2147 	u8 num_dumped_info_regs; /* number of dumped condition registers */
2148 	u8 severity; /* from dbg_idle_chk_severity_types enum */
2149 	u8 reserved;
2150 };
2151 
2152 /* Idle Check result register header */
2153 struct dbg_idle_chk_result_reg_hdr {
2154 	u8 data;
2155 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK  0x1
2156 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0
2157 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK  0x7F
2158 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1
2159 	u8 start_entry; /* index of the first checked entry */
2160 	u16 size; /* register size in dwords */
2161 };
2162 
2163 /* Idle Check rule */
2164 struct dbg_idle_chk_rule {
2165 	u16 rule_id; /* Idle Check rule ID */
2166 	u8 severity; /* value from dbg_idle_chk_severity_types enum */
2167 	u8 cond_id; /* Condition ID */
2168 	u8 num_cond_regs; /* number of condition registers */
2169 	u8 num_info_regs; /* number of info registers */
2170 	u8 num_imms; /* number of immediates in the condition */
2171 	u8 reserved1;
2172 	u16 reg_offset; /* offset of this rules registers in the idle check
2173 			 * register array (in dbg_idle_chk_reg units).
2174 			 */
2175 	u16 imm_offset; /* offset of this rules immediate values in the
2176 			 * immediate values array (in dwords).
2177 			 */
2178 };
2179 
2180 /* Idle Check rule parsing data */
2181 struct dbg_idle_chk_rule_parsing_data {
2182 	u32 data;
2183 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK	0x1
2184 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT	0
2185 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK	0x7FFFFFFF
2186 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT	1
2187 };
2188 
2189 /* Idle check severity types */
2190 enum dbg_idle_chk_severity_types {
2191 	/* idle check failure should cause an error */
2192 	IDLE_CHK_SEVERITY_ERROR,
2193 	/* idle check failure should cause an error only if theres no traffic */
2194 	IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC,
2195 	/* idle check failure should cause a warning */
2196 	IDLE_CHK_SEVERITY_WARNING,
2197 	MAX_DBG_IDLE_CHK_SEVERITY_TYPES
2198 };
2199 
2200 /* Debug Bus block data */
2201 struct dbg_bus_block_data {
2202 	u16 data;
2203 #define DBG_BUS_BLOCK_DATA_ENABLE_MASK_MASK		0xF
2204 #define DBG_BUS_BLOCK_DATA_ENABLE_MASK_SHIFT		0
2205 #define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_MASK		0xF
2206 #define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_SHIFT		4
2207 #define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_MASK	0xF
2208 #define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_SHIFT	8
2209 #define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_MASK	0xF
2210 #define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_SHIFT	12
2211 	u8 line_num;
2212 	u8 hw_id;
2213 };
2214 
2215 /* Debug Bus Clients */
2216 enum dbg_bus_clients {
2217 	DBG_BUS_CLIENT_RBCN,
2218 	DBG_BUS_CLIENT_RBCP,
2219 	DBG_BUS_CLIENT_RBCR,
2220 	DBG_BUS_CLIENT_RBCT,
2221 	DBG_BUS_CLIENT_RBCU,
2222 	DBG_BUS_CLIENT_RBCF,
2223 	DBG_BUS_CLIENT_RBCX,
2224 	DBG_BUS_CLIENT_RBCS,
2225 	DBG_BUS_CLIENT_RBCH,
2226 	DBG_BUS_CLIENT_RBCZ,
2227 	DBG_BUS_CLIENT_OTHER_ENGINE,
2228 	DBG_BUS_CLIENT_TIMESTAMP,
2229 	DBG_BUS_CLIENT_CPU,
2230 	DBG_BUS_CLIENT_RBCY,
2231 	DBG_BUS_CLIENT_RBCQ,
2232 	DBG_BUS_CLIENT_RBCM,
2233 	DBG_BUS_CLIENT_RBCB,
2234 	DBG_BUS_CLIENT_RBCW,
2235 	DBG_BUS_CLIENT_RBCV,
2236 	MAX_DBG_BUS_CLIENTS
2237 };
2238 
2239 /* Debug Bus constraint operation types */
2240 enum dbg_bus_constraint_ops {
2241 	DBG_BUS_CONSTRAINT_OP_EQ,
2242 	DBG_BUS_CONSTRAINT_OP_NE,
2243 	DBG_BUS_CONSTRAINT_OP_LT,
2244 	DBG_BUS_CONSTRAINT_OP_LTC,
2245 	DBG_BUS_CONSTRAINT_OP_LE,
2246 	DBG_BUS_CONSTRAINT_OP_LEC,
2247 	DBG_BUS_CONSTRAINT_OP_GT,
2248 	DBG_BUS_CONSTRAINT_OP_GTC,
2249 	DBG_BUS_CONSTRAINT_OP_GE,
2250 	DBG_BUS_CONSTRAINT_OP_GEC,
2251 	MAX_DBG_BUS_CONSTRAINT_OPS
2252 };
2253 
2254 /* Debug Bus trigger state data */
2255 struct dbg_bus_trigger_state_data {
2256 	u8 data;
2257 #define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_MASK	0xF
2258 #define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_SHIFT	0
2259 #define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_MASK		0xF
2260 #define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_SHIFT		4
2261 };
2262 
2263 /* Debug Bus memory address */
2264 struct dbg_bus_mem_addr {
2265 	u32 lo;
2266 	u32 hi;
2267 };
2268 
2269 /* Debug Bus PCI buffer data */
2270 struct dbg_bus_pci_buf_data {
2271 	struct dbg_bus_mem_addr phys_addr; /* PCI buffer physical address */
2272 	struct dbg_bus_mem_addr virt_addr; /* PCI buffer virtual address */
2273 	u32 size; /* PCI buffer size in bytes */
2274 };
2275 
2276 /* Debug Bus Storm EID range filter params */
2277 struct dbg_bus_storm_eid_range_params {
2278 	u8 min; /* Minimal event ID to filter on */
2279 	u8 max; /* Maximal event ID to filter on */
2280 };
2281 
2282 /* Debug Bus Storm EID mask filter params */
2283 struct dbg_bus_storm_eid_mask_params {
2284 	u8 val; /* Event ID value */
2285 	u8 mask; /* Event ID mask. 1s in the mask = dont care bits. */
2286 };
2287 
2288 /* Debug Bus Storm EID filter params */
2289 union dbg_bus_storm_eid_params {
2290 	struct dbg_bus_storm_eid_range_params range;
2291 	struct dbg_bus_storm_eid_mask_params mask;
2292 };
2293 
2294 /* Debug Bus Storm data */
2295 struct dbg_bus_storm_data {
2296 	u8 enabled;
2297 	u8 mode;
2298 	u8 hw_id;
2299 	u8 eid_filter_en;
2300 	u8 eid_range_not_mask;
2301 	u8 cid_filter_en;
2302 	union dbg_bus_storm_eid_params eid_filter_params;
2303 	u32 cid;
2304 };
2305 
2306 /* Debug Bus data */
2307 struct dbg_bus_data {
2308 	u32 app_version;
2309 	u8 state;
2310 	u8 hw_dwords;
2311 	u16 hw_id_mask;
2312 	u8 num_enabled_blocks;
2313 	u8 num_enabled_storms;
2314 	u8 target;
2315 	u8 one_shot_en;
2316 	u8 grc_input_en;
2317 	u8 timestamp_input_en;
2318 	u8 filter_en;
2319 	u8 adding_filter;
2320 	u8 filter_pre_trigger;
2321 	u8 filter_post_trigger;
2322 	u16 reserved;
2323 	u8 trigger_en;
2324 	struct dbg_bus_trigger_state_data trigger_states[3];
2325 	u8 next_trigger_state;
2326 	u8 next_constraint_id;
2327 	u8 unify_inputs;
2328 	u8 rcv_from_other_engine;
2329 	struct dbg_bus_pci_buf_data pci_buf;
2330 	struct dbg_bus_block_data blocks[88];
2331 	struct dbg_bus_storm_data storms[6];
2332 };
2333 
2334 /* Debug bus filter types */
2335 enum dbg_bus_filter_types {
2336 	DBG_BUS_FILTER_TYPE_OFF,
2337 	DBG_BUS_FILTER_TYPE_PRE,
2338 	DBG_BUS_FILTER_TYPE_POST,
2339 	DBG_BUS_FILTER_TYPE_ON,
2340 	MAX_DBG_BUS_FILTER_TYPES
2341 };
2342 
2343 /* Debug bus frame modes */
2344 enum dbg_bus_frame_modes {
2345 	DBG_BUS_FRAME_MODE_0HW_4ST = 0, /* 0 HW dwords, 4 Storm dwords */
2346 	DBG_BUS_FRAME_MODE_4HW_0ST = 3, /* 4 HW dwords, 0 Storm dwords */
2347 	DBG_BUS_FRAME_MODE_8HW_0ST = 4, /* 8 HW dwords, 0 Storm dwords */
2348 	MAX_DBG_BUS_FRAME_MODES
2349 };
2350 
2351 /* Debug bus other engine mode */
2352 enum dbg_bus_other_engine_modes {
2353 	DBG_BUS_OTHER_ENGINE_MODE_NONE,
2354 	DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX,
2355 	DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_RX,
2356 	DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX,
2357 	DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX,
2358 	MAX_DBG_BUS_OTHER_ENGINE_MODES
2359 };
2360 
2361 /* Debug bus post-trigger recording types */
2362 enum dbg_bus_post_trigger_types {
2363 	DBG_BUS_POST_TRIGGER_RECORD,
2364 	DBG_BUS_POST_TRIGGER_DROP,
2365 	MAX_DBG_BUS_POST_TRIGGER_TYPES
2366 };
2367 
2368 /* Debug bus pre-trigger recording types */
2369 enum dbg_bus_pre_trigger_types {
2370 	DBG_BUS_PRE_TRIGGER_START_FROM_ZERO,
2371 	DBG_BUS_PRE_TRIGGER_NUM_CHUNKS,
2372 	DBG_BUS_PRE_TRIGGER_DROP,
2373 	MAX_DBG_BUS_PRE_TRIGGER_TYPES
2374 };
2375 
2376 /* Debug bus SEMI frame modes */
2377 enum dbg_bus_semi_frame_modes {
2378 	DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST = 0,
2379 	DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST = 3,
2380 	MAX_DBG_BUS_SEMI_FRAME_MODES
2381 };
2382 
2383 /* Debug bus states */
2384 enum dbg_bus_states {
2385 	DBG_BUS_STATE_IDLE,
2386 	DBG_BUS_STATE_READY,
2387 	DBG_BUS_STATE_RECORDING,
2388 	DBG_BUS_STATE_STOPPED,
2389 	MAX_DBG_BUS_STATES
2390 };
2391 
2392 /* Debug Bus Storm modes */
2393 enum dbg_bus_storm_modes {
2394 	DBG_BUS_STORM_MODE_PRINTF,
2395 	DBG_BUS_STORM_MODE_PRAM_ADDR,
2396 	DBG_BUS_STORM_MODE_DRA_RW,
2397 	DBG_BUS_STORM_MODE_DRA_W,
2398 	DBG_BUS_STORM_MODE_LD_ST_ADDR,
2399 	DBG_BUS_STORM_MODE_DRA_FSM,
2400 	DBG_BUS_STORM_MODE_RH,
2401 	DBG_BUS_STORM_MODE_FOC,
2402 	DBG_BUS_STORM_MODE_EXT_STORE,
2403 	MAX_DBG_BUS_STORM_MODES
2404 };
2405 
2406 /* Debug bus target IDs */
2407 enum dbg_bus_targets {
2408 	DBG_BUS_TARGET_ID_INT_BUF,
2409 	DBG_BUS_TARGET_ID_NIG,
2410 	DBG_BUS_TARGET_ID_PCI,
2411 	MAX_DBG_BUS_TARGETS
2412 };
2413 
2414 /* GRC Dump data */
2415 struct dbg_grc_data {
2416 	u8 params_initialized;
2417 	u8 reserved1;
2418 	u16 reserved2;
2419 	u32 param_val[48];
2420 };
2421 
2422 /* Debug GRC params */
2423 enum dbg_grc_params {
2424 	DBG_GRC_PARAM_DUMP_TSTORM,
2425 	DBG_GRC_PARAM_DUMP_MSTORM,
2426 	DBG_GRC_PARAM_DUMP_USTORM,
2427 	DBG_GRC_PARAM_DUMP_XSTORM,
2428 	DBG_GRC_PARAM_DUMP_YSTORM,
2429 	DBG_GRC_PARAM_DUMP_PSTORM,
2430 	DBG_GRC_PARAM_DUMP_REGS,
2431 	DBG_GRC_PARAM_DUMP_RAM,
2432 	DBG_GRC_PARAM_DUMP_PBUF,
2433 	DBG_GRC_PARAM_DUMP_IOR,
2434 	DBG_GRC_PARAM_DUMP_VFC,
2435 	DBG_GRC_PARAM_DUMP_CM_CTX,
2436 	DBG_GRC_PARAM_DUMP_PXP,
2437 	DBG_GRC_PARAM_DUMP_RSS,
2438 	DBG_GRC_PARAM_DUMP_CAU,
2439 	DBG_GRC_PARAM_DUMP_QM,
2440 	DBG_GRC_PARAM_DUMP_MCP,
2441 	DBG_GRC_PARAM_MCP_TRACE_META_SIZE,
2442 	DBG_GRC_PARAM_DUMP_CFC,
2443 	DBG_GRC_PARAM_DUMP_IGU,
2444 	DBG_GRC_PARAM_DUMP_BRB,
2445 	DBG_GRC_PARAM_DUMP_BTB,
2446 	DBG_GRC_PARAM_DUMP_BMB,
2447 	DBG_GRC_PARAM_DUMP_NIG,
2448 	DBG_GRC_PARAM_DUMP_MULD,
2449 	DBG_GRC_PARAM_DUMP_PRS,
2450 	DBG_GRC_PARAM_DUMP_DMAE,
2451 	DBG_GRC_PARAM_DUMP_TM,
2452 	DBG_GRC_PARAM_DUMP_SDM,
2453 	DBG_GRC_PARAM_DUMP_DIF,
2454 	DBG_GRC_PARAM_DUMP_STATIC,
2455 	DBG_GRC_PARAM_UNSTALL,
2456 	DBG_GRC_PARAM_NUM_LCIDS,
2457 	DBG_GRC_PARAM_NUM_LTIDS,
2458 	DBG_GRC_PARAM_EXCLUDE_ALL,
2459 	DBG_GRC_PARAM_CRASH,
2460 	DBG_GRC_PARAM_PARITY_SAFE,
2461 	DBG_GRC_PARAM_DUMP_CM,
2462 	DBG_GRC_PARAM_DUMP_PHY,
2463 	DBG_GRC_PARAM_NO_MCP,
2464 	DBG_GRC_PARAM_NO_FW_VER,
2465 	MAX_DBG_GRC_PARAMS
2466 };
2467 
2468 /* Debug reset registers */
2469 enum dbg_reset_regs {
2470 	DBG_RESET_REG_MISCS_PL_UA,
2471 	DBG_RESET_REG_MISCS_PL_HV,
2472 	DBG_RESET_REG_MISCS_PL_HV_2,
2473 	DBG_RESET_REG_MISC_PL_UA,
2474 	DBG_RESET_REG_MISC_PL_HV,
2475 	DBG_RESET_REG_MISC_PL_PDA_VMAIN_1,
2476 	DBG_RESET_REG_MISC_PL_PDA_VMAIN_2,
2477 	DBG_RESET_REG_MISC_PL_PDA_VAUX,
2478 	MAX_DBG_RESET_REGS
2479 };
2480 
2481 /* Debug status codes */
2482 enum dbg_status {
2483 	DBG_STATUS_OK,
2484 	DBG_STATUS_APP_VERSION_NOT_SET,
2485 	DBG_STATUS_UNSUPPORTED_APP_VERSION,
2486 	DBG_STATUS_DBG_BLOCK_NOT_RESET,
2487 	DBG_STATUS_INVALID_ARGS,
2488 	DBG_STATUS_OUTPUT_ALREADY_SET,
2489 	DBG_STATUS_INVALID_PCI_BUF_SIZE,
2490 	DBG_STATUS_PCI_BUF_ALLOC_FAILED,
2491 	DBG_STATUS_PCI_BUF_NOT_ALLOCATED,
2492 	DBG_STATUS_TOO_MANY_INPUTS,
2493 	DBG_STATUS_INPUT_OVERLAP,
2494 	DBG_STATUS_HW_ONLY_RECORDING,
2495 	DBG_STATUS_STORM_ALREADY_ENABLED,
2496 	DBG_STATUS_STORM_NOT_ENABLED,
2497 	DBG_STATUS_BLOCK_ALREADY_ENABLED,
2498 	DBG_STATUS_BLOCK_NOT_ENABLED,
2499 	DBG_STATUS_NO_INPUT_ENABLED,
2500 	DBG_STATUS_NO_FILTER_TRIGGER_64B,
2501 	DBG_STATUS_FILTER_ALREADY_ENABLED,
2502 	DBG_STATUS_TRIGGER_ALREADY_ENABLED,
2503 	DBG_STATUS_TRIGGER_NOT_ENABLED,
2504 	DBG_STATUS_CANT_ADD_CONSTRAINT,
2505 	DBG_STATUS_TOO_MANY_TRIGGER_STATES,
2506 	DBG_STATUS_TOO_MANY_CONSTRAINTS,
2507 	DBG_STATUS_RECORDING_NOT_STARTED,
2508 	DBG_STATUS_DATA_DIDNT_TRIGGER,
2509 	DBG_STATUS_NO_DATA_RECORDED,
2510 	DBG_STATUS_DUMP_BUF_TOO_SMALL,
2511 	DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED,
2512 	DBG_STATUS_UNKNOWN_CHIP,
2513 	DBG_STATUS_VIRT_MEM_ALLOC_FAILED,
2514 	DBG_STATUS_BLOCK_IN_RESET,
2515 	DBG_STATUS_INVALID_TRACE_SIGNATURE,
2516 	DBG_STATUS_INVALID_NVRAM_BUNDLE,
2517 	DBG_STATUS_NVRAM_GET_IMAGE_FAILED,
2518 	DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE,
2519 	DBG_STATUS_NVRAM_READ_FAILED,
2520 	DBG_STATUS_IDLE_CHK_PARSE_FAILED,
2521 	DBG_STATUS_MCP_TRACE_BAD_DATA,
2522 	DBG_STATUS_MCP_TRACE_NO_META,
2523 	DBG_STATUS_MCP_COULD_NOT_HALT,
2524 	DBG_STATUS_MCP_COULD_NOT_RESUME,
2525 	DBG_STATUS_RESERVED2,
2526 	DBG_STATUS_SEMI_FIFO_NOT_EMPTY,
2527 	DBG_STATUS_IGU_FIFO_BAD_DATA,
2528 	DBG_STATUS_MCP_COULD_NOT_MASK_PRTY,
2529 	DBG_STATUS_FW_ASSERTS_PARSE_FAILED,
2530 	DBG_STATUS_REG_FIFO_BAD_DATA,
2531 	DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA,
2532 	DBG_STATUS_DBG_ARRAY_NOT_SET,
2533 	DBG_STATUS_FILTER_BUG,
2534 	DBG_STATUS_NON_MATCHING_LINES,
2535 	DBG_STATUS_INVALID_TRIGGER_DWORD_OFFSET,
2536 	DBG_STATUS_DBG_BUS_IN_USE,
2537 	MAX_DBG_STATUS
2538 };
2539 
2540 /* Debug Storms IDs */
2541 enum dbg_storms {
2542 	DBG_TSTORM_ID,
2543 	DBG_MSTORM_ID,
2544 	DBG_USTORM_ID,
2545 	DBG_XSTORM_ID,
2546 	DBG_YSTORM_ID,
2547 	DBG_PSTORM_ID,
2548 	MAX_DBG_STORMS
2549 };
2550 
2551 /* Idle Check data */
2552 struct idle_chk_data {
2553 	u32 buf_size;
2554 	u8 buf_size_set;
2555 	u8 reserved1;
2556 	u16 reserved2;
2557 };
2558 
2559 struct pretend_params {
2560 	u8 split_type;
2561 	u8 reserved;
2562 	u16 split_id;
2563 };
2564 
2565 /* Debug Tools data (per HW function)
2566  */
2567 struct dbg_tools_data {
2568 	struct dbg_grc_data grc;
2569 	struct dbg_bus_data bus;
2570 	struct idle_chk_data idle_chk;
2571 	u8 mode_enable[40];
2572 	u8 block_in_reset[88];
2573 	u8 chip_id;
2574 	u8 platform_id;
2575 	u8 num_ports;
2576 	u8 num_pfs_per_port;
2577 	u8 num_vfs;
2578 	u8 initialized;
2579 	u8 use_dmae;
2580 	u8 reserved;
2581 	struct pretend_params pretend;
2582 	u32 num_regs_read;
2583 };
2584 
2585 /********************************/
2586 /* HSI Init Functions constants */
2587 /********************************/
2588 
2589 /* Number of VLAN priorities */
2590 #define NUM_OF_VLAN_PRIORITIES	8
2591 
2592 /* BRB RAM init requirements */
2593 struct init_brb_ram_req {
2594 	u32 guranteed_per_tc;
2595 	u32 headroom_per_tc;
2596 	u32 min_pkt_size;
2597 	u32 max_ports_per_engine;
2598 	u8 num_active_tcs[MAX_NUM_PORTS];
2599 };
2600 
2601 /* ETS per-TC init requirements */
2602 struct init_ets_tc_req {
2603 	u8 use_sp;
2604 	u8 use_wfq;
2605 	u16 weight;
2606 };
2607 
2608 /* ETS init requirements */
2609 struct init_ets_req {
2610 	u32 mtu;
2611 	struct init_ets_tc_req tc_req[NUM_OF_TCS];
2612 };
2613 
2614 /* NIG LB RL init requirements */
2615 struct init_nig_lb_rl_req {
2616 	u16 lb_mac_rate;
2617 	u16 lb_rate;
2618 	u32 mtu;
2619 	u16 tc_rate[NUM_OF_PHYS_TCS];
2620 };
2621 
2622 /* NIG TC mapping for each priority */
2623 struct init_nig_pri_tc_map_entry {
2624 	u8 tc_id;
2625 	u8 valid;
2626 };
2627 
2628 /* NIG priority to TC map init requirements */
2629 struct init_nig_pri_tc_map_req {
2630 	struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES];
2631 };
2632 
2633 /* QM per-port init parameters */
2634 struct init_qm_port_params {
2635 	u8 active;
2636 	u8 active_phys_tcs;
2637 	u16 num_pbf_cmd_lines;
2638 	u16 num_btb_blocks;
2639 	u16 reserved;
2640 };
2641 
2642 /* QM per-PQ init parameters */
2643 struct init_qm_pq_params {
2644 	u8 vport_id;
2645 	u8 tc_id;
2646 	u8 wrr_group;
2647 	u8 rl_valid;
2648 	u8 port_id;
2649 	u8 reserved0;
2650 	u16 reserved1;
2651 };
2652 
2653 /* QM per-vport init parameters */
2654 struct init_qm_vport_params {
2655 	u32 vport_rl;
2656 	u16 vport_wfq;
2657 	u16 first_tx_pq_id[NUM_OF_TCS];
2658 };
2659 
2660 /**************************************/
2661 /* Init Tool HSI constants and macros */
2662 /**************************************/
2663 
2664 /* Width of GRC address in bits (addresses are specified in dwords) */
2665 #define GRC_ADDR_BITS	23
2666 #define MAX_GRC_ADDR	(BIT(GRC_ADDR_BITS) - 1)
2667 
2668 /* indicates an init that should be applied to any phase ID */
2669 #define ANY_PHASE_ID	0xffff
2670 
2671 /* Max size in dwords of a zipped array */
2672 #define MAX_ZIPPED_SIZE	8192
2673 enum chip_ids {
2674 	CHIP_BB,
2675 	CHIP_K2,
2676 	CHIP_RESERVED,
2677 	MAX_CHIP_IDS
2678 };
2679 
2680 struct fw_asserts_ram_section {
2681 	u16 section_ram_line_offset;
2682 	u16 section_ram_line_size;
2683 	u8 list_dword_offset;
2684 	u8 list_element_dword_size;
2685 	u8 list_num_elements;
2686 	u8 list_next_index_dword_offset;
2687 };
2688 
2689 struct fw_ver_num {
2690 	u8 major;
2691 	u8 minor;
2692 	u8 rev;
2693 	u8 eng;
2694 };
2695 
2696 struct fw_ver_info {
2697 	__le16 tools_ver;
2698 	u8 image_id;
2699 	u8 reserved1;
2700 	struct fw_ver_num num;
2701 	__le32 timestamp;
2702 	__le32 reserved2;
2703 };
2704 
2705 struct fw_info {
2706 	struct fw_ver_info ver;
2707 	struct fw_asserts_ram_section fw_asserts_section;
2708 };
2709 
2710 struct fw_info_location {
2711 	__le32 grc_addr;
2712 	__le32 size;
2713 };
2714 
2715 enum init_modes {
2716 	MODE_RESERVED,
2717 	MODE_BB,
2718 	MODE_K2,
2719 	MODE_ASIC,
2720 	MODE_RESERVED2,
2721 	MODE_RESERVED3,
2722 	MODE_RESERVED4,
2723 	MODE_RESERVED5,
2724 	MODE_SF,
2725 	MODE_MF_SD,
2726 	MODE_MF_SI,
2727 	MODE_PORTS_PER_ENG_1,
2728 	MODE_PORTS_PER_ENG_2,
2729 	MODE_PORTS_PER_ENG_4,
2730 	MODE_100G,
2731 	MODE_RESERVED6,
2732 	MAX_INIT_MODES
2733 };
2734 
2735 enum init_phases {
2736 	PHASE_ENGINE,
2737 	PHASE_PORT,
2738 	PHASE_PF,
2739 	PHASE_VF,
2740 	PHASE_QM_PF,
2741 	MAX_INIT_PHASES
2742 };
2743 
2744 enum init_split_types {
2745 	SPLIT_TYPE_NONE,
2746 	SPLIT_TYPE_PORT,
2747 	SPLIT_TYPE_PF,
2748 	SPLIT_TYPE_PORT_PF,
2749 	SPLIT_TYPE_VF,
2750 	MAX_INIT_SPLIT_TYPES
2751 };
2752 
2753 /* Binary buffer header */
2754 struct bin_buffer_hdr {
2755 	u32 offset;
2756 	u32 length;
2757 };
2758 
2759 /* Binary init buffer types */
2760 enum bin_init_buffer_type {
2761 	BIN_BUF_INIT_FW_VER_INFO,
2762 	BIN_BUF_INIT_CMD,
2763 	BIN_BUF_INIT_VAL,
2764 	BIN_BUF_INIT_MODE_TREE,
2765 	BIN_BUF_INIT_IRO,
2766 	MAX_BIN_INIT_BUFFER_TYPE
2767 };
2768 
2769 /* init array header: raw */
2770 struct init_array_raw_hdr {
2771 	u32 data;
2772 #define INIT_ARRAY_RAW_HDR_TYPE_MASK	0xF
2773 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT	0
2774 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK	0xFFFFFFF
2775 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT	4
2776 };
2777 
2778 /* init array header: standard */
2779 struct init_array_standard_hdr {
2780 	u32 data;
2781 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK	0xF
2782 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT	0
2783 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK	0xFFFFFFF
2784 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT	4
2785 };
2786 
2787 /* init array header: zipped */
2788 struct init_array_zipped_hdr {
2789 	u32 data;
2790 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK		0xF
2791 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT	0
2792 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK	0xFFFFFFF
2793 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT	4
2794 };
2795 
2796 /* init array header: pattern */
2797 struct init_array_pattern_hdr {
2798 	u32 data;
2799 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK		0xF
2800 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT		0
2801 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK	0xF
2802 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT	4
2803 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK		0xFFFFFF
2804 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT	8
2805 };
2806 
2807 /* init array header union */
2808 union init_array_hdr {
2809 	struct init_array_raw_hdr raw;
2810 	struct init_array_standard_hdr standard;
2811 	struct init_array_zipped_hdr zipped;
2812 	struct init_array_pattern_hdr pattern;
2813 };
2814 
2815 /* init array types */
2816 enum init_array_types {
2817 	INIT_ARR_STANDARD,
2818 	INIT_ARR_ZIPPED,
2819 	INIT_ARR_PATTERN,
2820 	MAX_INIT_ARRAY_TYPES
2821 };
2822 
2823 /* init operation: callback */
2824 struct init_callback_op {
2825 	u32 op_data;
2826 #define INIT_CALLBACK_OP_OP_MASK	0xF
2827 #define INIT_CALLBACK_OP_OP_SHIFT	0
2828 #define INIT_CALLBACK_OP_RESERVED_MASK	0xFFFFFFF
2829 #define INIT_CALLBACK_OP_RESERVED_SHIFT	4
2830 	u16 callback_id;
2831 	u16 block_id;
2832 };
2833 
2834 /* init operation: delay */
2835 struct init_delay_op {
2836 	u32 op_data;
2837 #define INIT_DELAY_OP_OP_MASK		0xF
2838 #define INIT_DELAY_OP_OP_SHIFT		0
2839 #define INIT_DELAY_OP_RESERVED_MASK	0xFFFFFFF
2840 #define INIT_DELAY_OP_RESERVED_SHIFT	4
2841 	u32 delay;
2842 };
2843 
2844 /* init operation: if_mode */
2845 struct init_if_mode_op {
2846 	u32 op_data;
2847 #define INIT_IF_MODE_OP_OP_MASK			0xF
2848 #define INIT_IF_MODE_OP_OP_SHIFT		0
2849 #define INIT_IF_MODE_OP_RESERVED1_MASK		0xFFF
2850 #define INIT_IF_MODE_OP_RESERVED1_SHIFT		4
2851 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK		0xFFFF
2852 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT	16
2853 	u16 reserved2;
2854 	u16 modes_buf_offset;
2855 };
2856 
2857 /* init operation: if_phase */
2858 struct init_if_phase_op {
2859 	u32 op_data;
2860 #define INIT_IF_PHASE_OP_OP_MASK		0xF
2861 #define INIT_IF_PHASE_OP_OP_SHIFT		0
2862 #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK	0x1
2863 #define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT	4
2864 #define INIT_IF_PHASE_OP_RESERVED1_MASK		0x7FF
2865 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT	5
2866 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK	0xFFFF
2867 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT	16
2868 	u32 phase_data;
2869 #define INIT_IF_PHASE_OP_PHASE_MASK		0xFF
2870 #define INIT_IF_PHASE_OP_PHASE_SHIFT		0
2871 #define INIT_IF_PHASE_OP_RESERVED2_MASK		0xFF
2872 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT	8
2873 #define INIT_IF_PHASE_OP_PHASE_ID_MASK		0xFFFF
2874 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT		16
2875 };
2876 
2877 /* init mode operators */
2878 enum init_mode_ops {
2879 	INIT_MODE_OP_NOT,
2880 	INIT_MODE_OP_OR,
2881 	INIT_MODE_OP_AND,
2882 	MAX_INIT_MODE_OPS
2883 };
2884 
2885 /* init operation: raw */
2886 struct init_raw_op {
2887 	u32 op_data;
2888 #define INIT_RAW_OP_OP_MASK		0xF
2889 #define INIT_RAW_OP_OP_SHIFT		0
2890 #define INIT_RAW_OP_PARAM1_MASK		0xFFFFFFF
2891 #define INIT_RAW_OP_PARAM1_SHIFT	4
2892 	u32 param2;
2893 };
2894 
2895 /* init array params */
2896 struct init_op_array_params {
2897 	u16 size;
2898 	u16 offset;
2899 };
2900 
2901 /* Write init operation arguments */
2902 union init_write_args {
2903 	u32 inline_val;
2904 	u32 zeros_count;
2905 	u32 array_offset;
2906 	struct init_op_array_params runtime;
2907 };
2908 
2909 /* init operation: write */
2910 struct init_write_op {
2911 	u32 data;
2912 #define INIT_WRITE_OP_OP_MASK		0xF
2913 #define INIT_WRITE_OP_OP_SHIFT		0
2914 #define INIT_WRITE_OP_SOURCE_MASK	0x7
2915 #define INIT_WRITE_OP_SOURCE_SHIFT	4
2916 #define INIT_WRITE_OP_RESERVED_MASK	0x1
2917 #define INIT_WRITE_OP_RESERVED_SHIFT	7
2918 #define INIT_WRITE_OP_WIDE_BUS_MASK	0x1
2919 #define INIT_WRITE_OP_WIDE_BUS_SHIFT	8
2920 #define INIT_WRITE_OP_ADDRESS_MASK	0x7FFFFF
2921 #define INIT_WRITE_OP_ADDRESS_SHIFT	9
2922 	union init_write_args args;
2923 };
2924 
2925 /* init operation: read */
2926 struct init_read_op {
2927 	u32 op_data;
2928 #define INIT_READ_OP_OP_MASK		0xF
2929 #define INIT_READ_OP_OP_SHIFT		0
2930 #define INIT_READ_OP_POLL_TYPE_MASK	0xF
2931 #define INIT_READ_OP_POLL_TYPE_SHIFT	4
2932 #define INIT_READ_OP_RESERVED_MASK	0x1
2933 #define INIT_READ_OP_RESERVED_SHIFT	8
2934 #define INIT_READ_OP_ADDRESS_MASK	0x7FFFFF
2935 #define INIT_READ_OP_ADDRESS_SHIFT	9
2936 	u32 expected_val;
2937 };
2938 
2939 /* Init operations union */
2940 union init_op {
2941 	struct init_raw_op raw;
2942 	struct init_write_op write;
2943 	struct init_read_op read;
2944 	struct init_if_mode_op if_mode;
2945 	struct init_if_phase_op if_phase;
2946 	struct init_callback_op callback;
2947 	struct init_delay_op delay;
2948 };
2949 
2950 /* Init command operation types */
2951 enum init_op_types {
2952 	INIT_OP_READ,
2953 	INIT_OP_WRITE,
2954 	INIT_OP_IF_MODE,
2955 	INIT_OP_IF_PHASE,
2956 	INIT_OP_DELAY,
2957 	INIT_OP_CALLBACK,
2958 	MAX_INIT_OP_TYPES
2959 };
2960 
2961 /* init polling types */
2962 enum init_poll_types {
2963 	INIT_POLL_NONE,
2964 	INIT_POLL_EQ,
2965 	INIT_POLL_OR,
2966 	INIT_POLL_AND,
2967 	MAX_INIT_POLL_TYPES
2968 };
2969 
2970 /* init source types */
2971 enum init_source_types {
2972 	INIT_SRC_INLINE,
2973 	INIT_SRC_ZEROS,
2974 	INIT_SRC_ARRAY,
2975 	INIT_SRC_RUNTIME,
2976 	MAX_INIT_SOURCE_TYPES
2977 };
2978 
2979 /* Internal RAM Offsets macro data */
2980 struct iro {
2981 	u32 base;
2982 	u16 m1;
2983 	u16 m2;
2984 	u16 m3;
2985 	u16 size;
2986 };
2987 
2988 /***************************** Public Functions *******************************/
2989 
2990 /**
2991  * @brief qed_dbg_set_bin_ptr - Sets a pointer to the binary data with debug
2992  *	arrays.
2993  *
2994  * @param bin_ptr - a pointer to the binary data with debug arrays.
2995  */
2996 enum dbg_status qed_dbg_set_bin_ptr(const u8 * const bin_ptr);
2997 
2998 /**
2999  * @brief qed_read_regs - Reads registers into a buffer (using GRC).
3000  *
3001  * @param p_hwfn - HW device data
3002  * @param p_ptt - Ptt window used for writing the registers.
3003  * @param buf - Destination buffer.
3004  * @param addr - Source GRC address in dwords.
3005  * @param len - Number of registers to read.
3006  */
3007 void qed_read_regs(struct qed_hwfn *p_hwfn,
3008 		   struct qed_ptt *p_ptt, u32 *buf, u32 addr, u32 len);
3009 
3010 /**
3011  * @brief qed_read_fw_info - Reads FW info from the chip.
3012  *
3013  * The FW info contains FW-related information, such as the FW version,
3014  * FW image (main/L2B/kuku), FW timestamp, etc.
3015  * The FW info is read from the internal RAM of the first Storm that is not in
3016  * reset.
3017  *
3018  * @param p_hwfn -	    HW device data
3019  * @param p_ptt -	    Ptt window used for writing the registers.
3020  * @param fw_info -	Out: a pointer to write the FW info into.
3021  *
3022  * @return true if the FW info was read successfully from one of the Storms,
3023  * or false if all Storms are in reset.
3024  */
3025 bool qed_read_fw_info(struct qed_hwfn *p_hwfn,
3026 		      struct qed_ptt *p_ptt, struct fw_info *fw_info);
3027 
3028 /**
3029  * @brief qed_dbg_grc_set_params_default - Reverts all GRC parameters to their
3030  *	default value.
3031  *
3032  * @param p_hwfn		- HW device data
3033  */
3034 void qed_dbg_grc_set_params_default(struct qed_hwfn *p_hwfn);
3035 /**
3036  * @brief qed_dbg_grc_get_dump_buf_size - Returns the required buffer size for
3037  *	GRC Dump.
3038  *
3039  * @param p_hwfn - HW device data
3040  * @param p_ptt - Ptt window used for writing the registers.
3041  * @param buf_size - OUT: required buffer size (in dwords) for the GRC Dump
3042  *	data.
3043  *
3044  * @return error if one of the following holds:
3045  *	- the version wasn't set
3046  * Otherwise, returns ok.
3047  */
3048 enum dbg_status qed_dbg_grc_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3049 					      struct qed_ptt *p_ptt,
3050 					      u32 *buf_size);
3051 
3052 /**
3053  * @brief qed_dbg_grc_dump - Dumps GRC data into the specified buffer.
3054  *
3055  * @param p_hwfn - HW device data
3056  * @param p_ptt - Ptt window used for writing the registers.
3057  * @param dump_buf - Pointer to write the collected GRC data into.
3058  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3059  * @param num_dumped_dwords - OUT: number of dumped dwords.
3060  *
3061  * @return error if one of the following holds:
3062  *	- the version wasn't set
3063  *	- the specified dump buffer is too small
3064  * Otherwise, returns ok.
3065  */
3066 enum dbg_status qed_dbg_grc_dump(struct qed_hwfn *p_hwfn,
3067 				 struct qed_ptt *p_ptt,
3068 				 u32 *dump_buf,
3069 				 u32 buf_size_in_dwords,
3070 				 u32 *num_dumped_dwords);
3071 
3072 /**
3073  * @brief qed_dbg_idle_chk_get_dump_buf_size - Returns the required buffer size
3074  *	for idle check results.
3075  *
3076  * @param p_hwfn - HW device data
3077  * @param p_ptt - Ptt window used for writing the registers.
3078  * @param buf_size - OUT: required buffer size (in dwords) for the idle check
3079  *	data.
3080  *
3081  * @return error if one of the following holds:
3082  *	- the version wasn't set
3083  * Otherwise, returns ok.
3084  */
3085 enum dbg_status qed_dbg_idle_chk_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3086 						   struct qed_ptt *p_ptt,
3087 						   u32 *buf_size);
3088 
3089 /**
3090  * @brief qed_dbg_idle_chk_dump - Performs idle check and writes the results
3091  *	into the specified buffer.
3092  *
3093  * @param p_hwfn - HW device data
3094  * @param p_ptt - Ptt window used for writing the registers.
3095  * @param dump_buf - Pointer to write the idle check data into.
3096  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3097  * @param num_dumped_dwords - OUT: number of dumped dwords.
3098  *
3099  * @return error if one of the following holds:
3100  *	- the version wasn't set
3101  *	- the specified buffer is too small
3102  * Otherwise, returns ok.
3103  */
3104 enum dbg_status qed_dbg_idle_chk_dump(struct qed_hwfn *p_hwfn,
3105 				      struct qed_ptt *p_ptt,
3106 				      u32 *dump_buf,
3107 				      u32 buf_size_in_dwords,
3108 				      u32 *num_dumped_dwords);
3109 
3110 /**
3111  * @brief qed_dbg_mcp_trace_get_dump_buf_size - Returns the required buffer size
3112  *	for mcp trace results.
3113  *
3114  * @param p_hwfn - HW device data
3115  * @param p_ptt - Ptt window used for writing the registers.
3116  * @param buf_size - OUT: required buffer size (in dwords) for mcp trace data.
3117  *
3118  * @return error if one of the following holds:
3119  *	- the version wasn't set
3120  *	- the trace data in MCP scratchpad contain an invalid signature
3121  *	- the bundle ID in NVRAM is invalid
3122  *	- the trace meta data cannot be found (in NVRAM or image file)
3123  * Otherwise, returns ok.
3124  */
3125 enum dbg_status qed_dbg_mcp_trace_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3126 						    struct qed_ptt *p_ptt,
3127 						    u32 *buf_size);
3128 
3129 /**
3130  * @brief qed_dbg_mcp_trace_dump - Performs mcp trace and writes the results
3131  *	into the specified buffer.
3132  *
3133  * @param p_hwfn - HW device data
3134  * @param p_ptt - Ptt window used for writing the registers.
3135  * @param dump_buf - Pointer to write the mcp trace data into.
3136  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3137  * @param num_dumped_dwords - OUT: number of dumped dwords.
3138  *
3139  * @return error if one of the following holds:
3140  *	- the version wasn't set
3141  *	- the specified buffer is too small
3142  *	- the trace data in MCP scratchpad contain an invalid signature
3143  *	- the bundle ID in NVRAM is invalid
3144  *	- the trace meta data cannot be found (in NVRAM or image file)
3145  *	- the trace meta data cannot be read (from NVRAM or image file)
3146  * Otherwise, returns ok.
3147  */
3148 enum dbg_status qed_dbg_mcp_trace_dump(struct qed_hwfn *p_hwfn,
3149 				       struct qed_ptt *p_ptt,
3150 				       u32 *dump_buf,
3151 				       u32 buf_size_in_dwords,
3152 				       u32 *num_dumped_dwords);
3153 
3154 /**
3155  * @brief qed_dbg_reg_fifo_get_dump_buf_size - Returns the required buffer size
3156  *	for grc trace fifo results.
3157  *
3158  * @param p_hwfn - HW device data
3159  * @param p_ptt - Ptt window used for writing the registers.
3160  * @param buf_size - OUT: required buffer size (in dwords) for reg fifo data.
3161  *
3162  * @return error if one of the following holds:
3163  *	- the version wasn't set
3164  * Otherwise, returns ok.
3165  */
3166 enum dbg_status qed_dbg_reg_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3167 						   struct qed_ptt *p_ptt,
3168 						   u32 *buf_size);
3169 
3170 /**
3171  * @brief qed_dbg_reg_fifo_dump - Reads the reg fifo and writes the results into
3172  *	the specified buffer.
3173  *
3174  * @param p_hwfn - HW device data
3175  * @param p_ptt - Ptt window used for writing the registers.
3176  * @param dump_buf - Pointer to write the reg fifo data into.
3177  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3178  * @param num_dumped_dwords - OUT: number of dumped dwords.
3179  *
3180  * @return error if one of the following holds:
3181  *	- the version wasn't set
3182  *	- the specified buffer is too small
3183  *	- DMAE transaction failed
3184  * Otherwise, returns ok.
3185  */
3186 enum dbg_status qed_dbg_reg_fifo_dump(struct qed_hwfn *p_hwfn,
3187 				      struct qed_ptt *p_ptt,
3188 				      u32 *dump_buf,
3189 				      u32 buf_size_in_dwords,
3190 				      u32 *num_dumped_dwords);
3191 
3192 /**
3193  * @brief qed_dbg_igu_fifo_get_dump_buf_size - Returns the required buffer size
3194  *	for the IGU fifo results.
3195  *
3196  * @param p_hwfn - HW device data
3197  * @param p_ptt - Ptt window used for writing the registers.
3198  * @param buf_size - OUT: required buffer size (in dwords) for the IGU fifo
3199  *	data.
3200  *
3201  * @return error if one of the following holds:
3202  *	- the version wasn't set
3203  * Otherwise, returns ok.
3204  */
3205 enum dbg_status qed_dbg_igu_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3206 						   struct qed_ptt *p_ptt,
3207 						   u32 *buf_size);
3208 
3209 /**
3210  * @brief qed_dbg_igu_fifo_dump - Reads the IGU fifo and writes the results into
3211  *	the specified buffer.
3212  *
3213  * @param p_hwfn - HW device data
3214  * @param p_ptt - Ptt window used for writing the registers.
3215  * @param dump_buf - Pointer to write the IGU fifo data into.
3216  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3217  * @param num_dumped_dwords - OUT: number of dumped dwords.
3218  *
3219  * @return error if one of the following holds:
3220  *	- the version wasn't set
3221  *	- the specified buffer is too small
3222  *	- DMAE transaction failed
3223  * Otherwise, returns ok.
3224  */
3225 enum dbg_status qed_dbg_igu_fifo_dump(struct qed_hwfn *p_hwfn,
3226 				      struct qed_ptt *p_ptt,
3227 				      u32 *dump_buf,
3228 				      u32 buf_size_in_dwords,
3229 				      u32 *num_dumped_dwords);
3230 
3231 /**
3232  * @brief qed_dbg_protection_override_get_dump_buf_size - Returns the required
3233  *	buffer size for protection override window results.
3234  *
3235  * @param p_hwfn - HW device data
3236  * @param p_ptt - Ptt window used for writing the registers.
3237  * @param buf_size - OUT: required buffer size (in dwords) for protection
3238  *	override data.
3239  *
3240  * @return error if one of the following holds:
3241  *	- the version wasn't set
3242  * Otherwise, returns ok.
3243  */
3244 enum dbg_status
3245 qed_dbg_protection_override_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3246 					      struct qed_ptt *p_ptt,
3247 					      u32 *buf_size);
3248 /**
3249  * @brief qed_dbg_protection_override_dump - Reads protection override window
3250  *	entries and writes the results into the specified buffer.
3251  *
3252  * @param p_hwfn - HW device data
3253  * @param p_ptt - Ptt window used for writing the registers.
3254  * @param dump_buf - Pointer to write the protection override data into.
3255  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3256  * @param num_dumped_dwords - OUT: number of dumped dwords.
3257  *
3258  * @return error if one of the following holds:
3259  *	- the version wasn't set
3260  *	- the specified buffer is too small
3261  *	- DMAE transaction failed
3262  * Otherwise, returns ok.
3263  */
3264 enum dbg_status qed_dbg_protection_override_dump(struct qed_hwfn *p_hwfn,
3265 						 struct qed_ptt *p_ptt,
3266 						 u32 *dump_buf,
3267 						 u32 buf_size_in_dwords,
3268 						 u32 *num_dumped_dwords);
3269 /**
3270  * @brief qed_dbg_fw_asserts_get_dump_buf_size - Returns the required buffer
3271  *	size for FW Asserts results.
3272  *
3273  * @param p_hwfn - HW device data
3274  * @param p_ptt - Ptt window used for writing the registers.
3275  * @param buf_size - OUT: required buffer size (in dwords) for FW Asserts data.
3276  *
3277  * @return error if one of the following holds:
3278  *	- the version wasn't set
3279  * Otherwise, returns ok.
3280  */
3281 enum dbg_status qed_dbg_fw_asserts_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3282 						     struct qed_ptt *p_ptt,
3283 						     u32 *buf_size);
3284 /**
3285  * @brief qed_dbg_fw_asserts_dump - Reads the FW Asserts and writes the results
3286  *	into the specified buffer.
3287  *
3288  * @param p_hwfn - HW device data
3289  * @param p_ptt - Ptt window used for writing the registers.
3290  * @param dump_buf - Pointer to write the FW Asserts data into.
3291  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3292  * @param num_dumped_dwords - OUT: number of dumped dwords.
3293  *
3294  * @return error if one of the following holds:
3295  *	- the version wasn't set
3296  *	- the specified buffer is too small
3297  * Otherwise, returns ok.
3298  */
3299 enum dbg_status qed_dbg_fw_asserts_dump(struct qed_hwfn *p_hwfn,
3300 					struct qed_ptt *p_ptt,
3301 					u32 *dump_buf,
3302 					u32 buf_size_in_dwords,
3303 					u32 *num_dumped_dwords);
3304 
3305 /**
3306  * @brief qed_dbg_read_attn - Reads the attention registers of the specified
3307  * block and type, and writes the results into the specified buffer.
3308  *
3309  * @param p_hwfn -	 HW device data
3310  * @param p_ptt -	 Ptt window used for writing the registers.
3311  * @param block -	 Block ID.
3312  * @param attn_type -	 Attention type.
3313  * @param clear_status - Indicates if the attention status should be cleared.
3314  * @param results -	 OUT: Pointer to write the read results into
3315  *
3316  * @return error if one of the following holds:
3317  *	- the version wasn't set
3318  * Otherwise, returns ok.
3319  */
3320 enum dbg_status qed_dbg_read_attn(struct qed_hwfn *p_hwfn,
3321 				  struct qed_ptt *p_ptt,
3322 				  enum block_id block,
3323 				  enum dbg_attn_type attn_type,
3324 				  bool clear_status,
3325 				  struct dbg_attn_block_result *results);
3326 
3327 /**
3328  * @brief qed_dbg_print_attn - Prints attention registers values in the
3329  *	specified results struct.
3330  *
3331  * @param p_hwfn
3332  * @param results - Pointer to the attention read results
3333  *
3334  * @return error if one of the following holds:
3335  *	- the version wasn't set
3336  * Otherwise, returns ok.
3337  */
3338 enum dbg_status qed_dbg_print_attn(struct qed_hwfn *p_hwfn,
3339 				   struct dbg_attn_block_result *results);
3340 
3341 /******************************* Data Types **********************************/
3342 
3343 struct mcp_trace_format {
3344 	u32 data;
3345 #define MCP_TRACE_FORMAT_MODULE_MASK	0x0000ffff
3346 #define MCP_TRACE_FORMAT_MODULE_SHIFT	0
3347 #define MCP_TRACE_FORMAT_LEVEL_MASK	0x00030000
3348 #define MCP_TRACE_FORMAT_LEVEL_SHIFT	16
3349 #define MCP_TRACE_FORMAT_P1_SIZE_MASK	0x000c0000
3350 #define MCP_TRACE_FORMAT_P1_SIZE_SHIFT	18
3351 #define MCP_TRACE_FORMAT_P2_SIZE_MASK	0x00300000
3352 #define MCP_TRACE_FORMAT_P2_SIZE_SHIFT	20
3353 #define MCP_TRACE_FORMAT_P3_SIZE_MASK	0x00c00000
3354 #define MCP_TRACE_FORMAT_P3_SIZE_SHIFT	22
3355 #define MCP_TRACE_FORMAT_LEN_MASK	0xff000000
3356 #define MCP_TRACE_FORMAT_LEN_SHIFT	24
3357 	char *format_str;
3358 };
3359 
3360 /******************************** Constants **********************************/
3361 
3362 #define MAX_NAME_LEN	16
3363 
3364 /***************************** Public Functions *******************************/
3365 
3366 /**
3367  * @brief qed_dbg_user_set_bin_ptr - Sets a pointer to the binary data with
3368  *	debug arrays.
3369  *
3370  * @param bin_ptr - a pointer to the binary data with debug arrays.
3371  */
3372 enum dbg_status qed_dbg_user_set_bin_ptr(const u8 * const bin_ptr);
3373 
3374 /**
3375  * @brief qed_dbg_alloc_user_data - Allocates user debug data.
3376  *
3377  * @param p_hwfn -		 HW device data
3378  */
3379 enum dbg_status qed_dbg_alloc_user_data(struct qed_hwfn *p_hwfn);
3380 
3381 /**
3382  * @brief qed_dbg_get_status_str - Returns a string for the specified status.
3383  *
3384  * @param status - a debug status code.
3385  *
3386  * @return a string for the specified status
3387  */
3388 const char *qed_dbg_get_status_str(enum dbg_status status);
3389 
3390 /**
3391  * @brief qed_get_idle_chk_results_buf_size - Returns the required buffer size
3392  *	for idle check results (in bytes).
3393  *
3394  * @param p_hwfn - HW device data
3395  * @param dump_buf - idle check dump buffer.
3396  * @param num_dumped_dwords - number of dwords that were dumped.
3397  * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3398  *	results.
3399  *
3400  * @return error if the parsing fails, ok otherwise.
3401  */
3402 enum dbg_status qed_get_idle_chk_results_buf_size(struct qed_hwfn *p_hwfn,
3403 						  u32 *dump_buf,
3404 						  u32  num_dumped_dwords,
3405 						  u32 *results_buf_size);
3406 /**
3407  * @brief qed_print_idle_chk_results - Prints idle check results
3408  *
3409  * @param p_hwfn - HW device data
3410  * @param dump_buf - idle check dump buffer.
3411  * @param num_dumped_dwords - number of dwords that were dumped.
3412  * @param results_buf - buffer for printing the idle check results.
3413  * @param num_errors - OUT: number of errors found in idle check.
3414  * @param num_warnings - OUT: number of warnings found in idle check.
3415  *
3416  * @return error if the parsing fails, ok otherwise.
3417  */
3418 enum dbg_status qed_print_idle_chk_results(struct qed_hwfn *p_hwfn,
3419 					   u32 *dump_buf,
3420 					   u32 num_dumped_dwords,
3421 					   char *results_buf,
3422 					   u32 *num_errors,
3423 					   u32 *num_warnings);
3424 
3425 /**
3426  * @brief qed_dbg_mcp_trace_set_meta_data - Sets the MCP Trace meta data.
3427  *
3428  * Needed in case the MCP Trace dump doesn't contain the meta data (e.g. due to
3429  * no NVRAM access).
3430  *
3431  * @param data - pointer to MCP Trace meta data
3432  * @param size - size of MCP Trace meta data in dwords
3433  */
3434 void qed_dbg_mcp_trace_set_meta_data(struct qed_hwfn *p_hwfn,
3435 				     const u32 *meta_buf);
3436 
3437 /**
3438  * @brief qed_get_mcp_trace_results_buf_size - Returns the required buffer size
3439  *	for MCP Trace results (in bytes).
3440  *
3441  * @param p_hwfn - HW device data
3442  * @param dump_buf - MCP Trace dump buffer.
3443  * @param num_dumped_dwords - number of dwords that were dumped.
3444  * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3445  *	results.
3446  *
3447  * @return error if the parsing fails, ok otherwise.
3448  */
3449 enum dbg_status qed_get_mcp_trace_results_buf_size(struct qed_hwfn *p_hwfn,
3450 						   u32 *dump_buf,
3451 						   u32 num_dumped_dwords,
3452 						   u32 *results_buf_size);
3453 
3454 /**
3455  * @brief qed_print_mcp_trace_results - Prints MCP Trace results
3456  *
3457  * @param p_hwfn - HW device data
3458  * @param dump_buf - mcp trace dump buffer, starting from the header.
3459  * @param num_dumped_dwords - number of dwords that were dumped.
3460  * @param results_buf - buffer for printing the mcp trace results.
3461  *
3462  * @return error if the parsing fails, ok otherwise.
3463  */
3464 enum dbg_status qed_print_mcp_trace_results(struct qed_hwfn *p_hwfn,
3465 					    u32 *dump_buf,
3466 					    u32 num_dumped_dwords,
3467 					    char *results_buf);
3468 
3469 /**
3470  * @brief qed_print_mcp_trace_results_cont - Prints MCP Trace results, and
3471  * keeps the MCP trace meta data allocated, to support continuous MCP Trace
3472  * parsing. After the continuous parsing ends, mcp_trace_free_meta_data should
3473  * be called to free the meta data.
3474  *
3475  * @param p_hwfn -	      HW device data
3476  * @param dump_buf -	      mcp trace dump buffer, starting from the header.
3477  * @param results_buf -	      buffer for printing the mcp trace results.
3478  *
3479  * @return error if the parsing fails, ok otherwise.
3480  */
3481 enum dbg_status qed_print_mcp_trace_results_cont(struct qed_hwfn *p_hwfn,
3482 						 u32 *dump_buf,
3483 						 char *results_buf);
3484 
3485 /**
3486  * @brief print_mcp_trace_line - Prints MCP Trace results for a single line
3487  *
3488  * @param p_hwfn -	      HW device data
3489  * @param dump_buf -	      mcp trace dump buffer, starting from the header.
3490  * @param num_dumped_bytes -  number of bytes that were dumped.
3491  * @param results_buf -	      buffer for printing the mcp trace results.
3492  *
3493  * @return error if the parsing fails, ok otherwise.
3494  */
3495 enum dbg_status qed_print_mcp_trace_line(struct qed_hwfn *p_hwfn,
3496 					 u8 *dump_buf,
3497 					 u32 num_dumped_bytes,
3498 					 char *results_buf);
3499 
3500 /**
3501  * @brief mcp_trace_free_meta_data - Frees the MCP Trace meta data.
3502  * Should be called after continuous MCP Trace parsing.
3503  *
3504  * @param p_hwfn - HW device data
3505  */
3506 void qed_mcp_trace_free_meta_data(struct qed_hwfn *p_hwfn);
3507 
3508 /**
3509  * @brief qed_get_reg_fifo_results_buf_size - Returns the required buffer size
3510  *	for reg_fifo results (in bytes).
3511  *
3512  * @param p_hwfn - HW device data
3513  * @param dump_buf - reg fifo dump buffer.
3514  * @param num_dumped_dwords - number of dwords that were dumped.
3515  * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3516  *	results.
3517  *
3518  * @return error if the parsing fails, ok otherwise.
3519  */
3520 enum dbg_status qed_get_reg_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
3521 						  u32 *dump_buf,
3522 						  u32 num_dumped_dwords,
3523 						  u32 *results_buf_size);
3524 
3525 /**
3526  * @brief qed_print_reg_fifo_results - Prints reg fifo results
3527  *
3528  * @param p_hwfn - HW device data
3529  * @param dump_buf - reg fifo dump buffer, starting from the header.
3530  * @param num_dumped_dwords - number of dwords that were dumped.
3531  * @param results_buf - buffer for printing the reg fifo results.
3532  *
3533  * @return error if the parsing fails, ok otherwise.
3534  */
3535 enum dbg_status qed_print_reg_fifo_results(struct qed_hwfn *p_hwfn,
3536 					   u32 *dump_buf,
3537 					   u32 num_dumped_dwords,
3538 					   char *results_buf);
3539 
3540 /**
3541  * @brief qed_get_igu_fifo_results_buf_size - Returns the required buffer size
3542  *	for igu_fifo results (in bytes).
3543  *
3544  * @param p_hwfn - HW device data
3545  * @param dump_buf - IGU fifo dump buffer.
3546  * @param num_dumped_dwords - number of dwords that were dumped.
3547  * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3548  *	results.
3549  *
3550  * @return error if the parsing fails, ok otherwise.
3551  */
3552 enum dbg_status qed_get_igu_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
3553 						  u32 *dump_buf,
3554 						  u32 num_dumped_dwords,
3555 						  u32 *results_buf_size);
3556 
3557 /**
3558  * @brief qed_print_igu_fifo_results - Prints IGU fifo results
3559  *
3560  * @param p_hwfn - HW device data
3561  * @param dump_buf - IGU fifo dump buffer, starting from the header.
3562  * @param num_dumped_dwords - number of dwords that were dumped.
3563  * @param results_buf - buffer for printing the IGU fifo results.
3564  *
3565  * @return error if the parsing fails, ok otherwise.
3566  */
3567 enum dbg_status qed_print_igu_fifo_results(struct qed_hwfn *p_hwfn,
3568 					   u32 *dump_buf,
3569 					   u32 num_dumped_dwords,
3570 					   char *results_buf);
3571 
3572 /**
3573  * @brief qed_get_protection_override_results_buf_size - Returns the required
3574  *	buffer size for protection override results (in bytes).
3575  *
3576  * @param p_hwfn - HW device data
3577  * @param dump_buf - protection override dump buffer.
3578  * @param num_dumped_dwords - number of dwords that were dumped.
3579  * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3580  *	results.
3581  *
3582  * @return error if the parsing fails, ok otherwise.
3583  */
3584 enum dbg_status
3585 qed_get_protection_override_results_buf_size(struct qed_hwfn *p_hwfn,
3586 					     u32 *dump_buf,
3587 					     u32 num_dumped_dwords,
3588 					     u32 *results_buf_size);
3589 
3590 /**
3591  * @brief qed_print_protection_override_results - Prints protection override
3592  *	results.
3593  *
3594  * @param p_hwfn - HW device data
3595  * @param dump_buf - protection override dump buffer, starting from the header.
3596  * @param num_dumped_dwords - number of dwords that were dumped.
3597  * @param results_buf - buffer for printing the reg fifo results.
3598  *
3599  * @return error if the parsing fails, ok otherwise.
3600  */
3601 enum dbg_status qed_print_protection_override_results(struct qed_hwfn *p_hwfn,
3602 						      u32 *dump_buf,
3603 						      u32 num_dumped_dwords,
3604 						      char *results_buf);
3605 
3606 /**
3607  * @brief qed_get_fw_asserts_results_buf_size - Returns the required buffer size
3608  *	for FW Asserts results (in bytes).
3609  *
3610  * @param p_hwfn - HW device data
3611  * @param dump_buf - FW Asserts dump buffer.
3612  * @param num_dumped_dwords - number of dwords that were dumped.
3613  * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3614  *	results.
3615  *
3616  * @return error if the parsing fails, ok otherwise.
3617  */
3618 enum dbg_status qed_get_fw_asserts_results_buf_size(struct qed_hwfn *p_hwfn,
3619 						    u32 *dump_buf,
3620 						    u32 num_dumped_dwords,
3621 						    u32 *results_buf_size);
3622 
3623 /**
3624  * @brief qed_print_fw_asserts_results - Prints FW Asserts results
3625  *
3626  * @param p_hwfn - HW device data
3627  * @param dump_buf - FW Asserts dump buffer, starting from the header.
3628  * @param num_dumped_dwords - number of dwords that were dumped.
3629  * @param results_buf - buffer for printing the FW Asserts results.
3630  *
3631  * @return error if the parsing fails, ok otherwise.
3632  */
3633 enum dbg_status qed_print_fw_asserts_results(struct qed_hwfn *p_hwfn,
3634 					     u32 *dump_buf,
3635 					     u32 num_dumped_dwords,
3636 					     char *results_buf);
3637 
3638 /**
3639  * @brief qed_dbg_parse_attn - Parses and prints attention registers values in
3640  * the specified results struct.
3641  *
3642  * @param p_hwfn -  HW device data
3643  * @param results - Pointer to the attention read results
3644  *
3645  * @return error if one of the following holds:
3646  *	- the version wasn't set
3647  * Otherwise, returns ok.
3648  */
3649 enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn,
3650 				   struct dbg_attn_block_result *results);
3651 
3652 /* Debug Bus blocks */
3653 static const u32 dbg_bus_blocks[] = {
3654 	0x0000000f,		/* grc, bb, 15 lines */
3655 	0x0000000f,		/* grc, k2, 15 lines */
3656 	0x00000000,
3657 	0x00000000,		/* miscs, bb, 0 lines */
3658 	0x00000000,		/* miscs, k2, 0 lines */
3659 	0x00000000,
3660 	0x00000000,		/* misc, bb, 0 lines */
3661 	0x00000000,		/* misc, k2, 0 lines */
3662 	0x00000000,
3663 	0x00000000,		/* dbu, bb, 0 lines */
3664 	0x00000000,		/* dbu, k2, 0 lines */
3665 	0x00000000,
3666 	0x000f0127,		/* pglue_b, bb, 39 lines */
3667 	0x0036012a,		/* pglue_b, k2, 42 lines */
3668 	0x00000000,
3669 	0x00000000,		/* cnig, bb, 0 lines */
3670 	0x00120102,		/* cnig, k2, 2 lines */
3671 	0x00000000,
3672 	0x00000000,		/* cpmu, bb, 0 lines */
3673 	0x00000000,		/* cpmu, k2, 0 lines */
3674 	0x00000000,
3675 	0x00000001,		/* ncsi, bb, 1 lines */
3676 	0x00000001,		/* ncsi, k2, 1 lines */
3677 	0x00000000,
3678 	0x00000000,		/* opte, bb, 0 lines */
3679 	0x00000000,		/* opte, k2, 0 lines */
3680 	0x00000000,
3681 	0x00600085,		/* bmb, bb, 133 lines */
3682 	0x00600085,		/* bmb, k2, 133 lines */
3683 	0x00000000,
3684 	0x00000000,		/* pcie, bb, 0 lines */
3685 	0x00e50033,		/* pcie, k2, 51 lines */
3686 	0x00000000,
3687 	0x00000000,		/* mcp, bb, 0 lines */
3688 	0x00000000,		/* mcp, k2, 0 lines */
3689 	0x00000000,
3690 	0x01180009,		/* mcp2, bb, 9 lines */
3691 	0x01180009,		/* mcp2, k2, 9 lines */
3692 	0x00000000,
3693 	0x01210104,		/* pswhst, bb, 4 lines */
3694 	0x01210104,		/* pswhst, k2, 4 lines */
3695 	0x00000000,
3696 	0x01250103,		/* pswhst2, bb, 3 lines */
3697 	0x01250103,		/* pswhst2, k2, 3 lines */
3698 	0x00000000,
3699 	0x00340101,		/* pswrd, bb, 1 lines */
3700 	0x00340101,		/* pswrd, k2, 1 lines */
3701 	0x00000000,
3702 	0x01280119,		/* pswrd2, bb, 25 lines */
3703 	0x01280119,		/* pswrd2, k2, 25 lines */
3704 	0x00000000,
3705 	0x01410109,		/* pswwr, bb, 9 lines */
3706 	0x01410109,		/* pswwr, k2, 9 lines */
3707 	0x00000000,
3708 	0x00000000,		/* pswwr2, bb, 0 lines */
3709 	0x00000000,		/* pswwr2, k2, 0 lines */
3710 	0x00000000,
3711 	0x001c0001,		/* pswrq, bb, 1 lines */
3712 	0x001c0001,		/* pswrq, k2, 1 lines */
3713 	0x00000000,
3714 	0x014a0015,		/* pswrq2, bb, 21 lines */
3715 	0x014a0015,		/* pswrq2, k2, 21 lines */
3716 	0x00000000,
3717 	0x00000000,		/* pglcs, bb, 0 lines */
3718 	0x00120006,		/* pglcs, k2, 6 lines */
3719 	0x00000000,
3720 	0x00100001,		/* dmae, bb, 1 lines */
3721 	0x00100001,		/* dmae, k2, 1 lines */
3722 	0x00000000,
3723 	0x015f0105,		/* ptu, bb, 5 lines */
3724 	0x015f0105,		/* ptu, k2, 5 lines */
3725 	0x00000000,
3726 	0x01640120,		/* tcm, bb, 32 lines */
3727 	0x01640120,		/* tcm, k2, 32 lines */
3728 	0x00000000,
3729 	0x01640120,		/* mcm, bb, 32 lines */
3730 	0x01640120,		/* mcm, k2, 32 lines */
3731 	0x00000000,
3732 	0x01640120,		/* ucm, bb, 32 lines */
3733 	0x01640120,		/* ucm, k2, 32 lines */
3734 	0x00000000,
3735 	0x01640120,		/* xcm, bb, 32 lines */
3736 	0x01640120,		/* xcm, k2, 32 lines */
3737 	0x00000000,
3738 	0x01640120,		/* ycm, bb, 32 lines */
3739 	0x01640120,		/* ycm, k2, 32 lines */
3740 	0x00000000,
3741 	0x01640120,		/* pcm, bb, 32 lines */
3742 	0x01640120,		/* pcm, k2, 32 lines */
3743 	0x00000000,
3744 	0x01840062,		/* qm, bb, 98 lines */
3745 	0x01840062,		/* qm, k2, 98 lines */
3746 	0x00000000,
3747 	0x01e60021,		/* tm, bb, 33 lines */
3748 	0x01e60021,		/* tm, k2, 33 lines */
3749 	0x00000000,
3750 	0x02070107,		/* dorq, bb, 7 lines */
3751 	0x02070107,		/* dorq, k2, 7 lines */
3752 	0x00000000,
3753 	0x00600185,		/* brb, bb, 133 lines */
3754 	0x00600185,		/* brb, k2, 133 lines */
3755 	0x00000000,
3756 	0x020e0019,		/* src, bb, 25 lines */
3757 	0x020c001a,		/* src, k2, 26 lines */
3758 	0x00000000,
3759 	0x02270104,		/* prs, bb, 4 lines */
3760 	0x02270104,		/* prs, k2, 4 lines */
3761 	0x00000000,
3762 	0x022b0133,		/* tsdm, bb, 51 lines */
3763 	0x022b0133,		/* tsdm, k2, 51 lines */
3764 	0x00000000,
3765 	0x022b0133,		/* msdm, bb, 51 lines */
3766 	0x022b0133,		/* msdm, k2, 51 lines */
3767 	0x00000000,
3768 	0x022b0133,		/* usdm, bb, 51 lines */
3769 	0x022b0133,		/* usdm, k2, 51 lines */
3770 	0x00000000,
3771 	0x022b0133,		/* xsdm, bb, 51 lines */
3772 	0x022b0133,		/* xsdm, k2, 51 lines */
3773 	0x00000000,
3774 	0x022b0133,		/* ysdm, bb, 51 lines */
3775 	0x022b0133,		/* ysdm, k2, 51 lines */
3776 	0x00000000,
3777 	0x022b0133,		/* psdm, bb, 51 lines */
3778 	0x022b0133,		/* psdm, k2, 51 lines */
3779 	0x00000000,
3780 	0x025e010c,		/* tsem, bb, 12 lines */
3781 	0x025e010c,		/* tsem, k2, 12 lines */
3782 	0x00000000,
3783 	0x025e010c,		/* msem, bb, 12 lines */
3784 	0x025e010c,		/* msem, k2, 12 lines */
3785 	0x00000000,
3786 	0x025e010c,		/* usem, bb, 12 lines */
3787 	0x025e010c,		/* usem, k2, 12 lines */
3788 	0x00000000,
3789 	0x025e010c,		/* xsem, bb, 12 lines */
3790 	0x025e010c,		/* xsem, k2, 12 lines */
3791 	0x00000000,
3792 	0x025e010c,		/* ysem, bb, 12 lines */
3793 	0x025e010c,		/* ysem, k2, 12 lines */
3794 	0x00000000,
3795 	0x025e010c,		/* psem, bb, 12 lines */
3796 	0x025e010c,		/* psem, k2, 12 lines */
3797 	0x00000000,
3798 	0x026a000d,		/* rss, bb, 13 lines */
3799 	0x026a000d,		/* rss, k2, 13 lines */
3800 	0x00000000,
3801 	0x02770106,		/* tmld, bb, 6 lines */
3802 	0x02770106,		/* tmld, k2, 6 lines */
3803 	0x00000000,
3804 	0x027d0106,		/* muld, bb, 6 lines */
3805 	0x027d0106,		/* muld, k2, 6 lines */
3806 	0x00000000,
3807 	0x02770005,		/* yuld, bb, 5 lines */
3808 	0x02770005,		/* yuld, k2, 5 lines */
3809 	0x00000000,
3810 	0x02830107,		/* xyld, bb, 7 lines */
3811 	0x027d0107,		/* xyld, k2, 7 lines */
3812 	0x00000000,
3813 	0x00000000,		/* ptld, bb, 0 lines */
3814 	0x00000000,		/* ptld, k2, 0 lines */
3815 	0x00000000,
3816 	0x00000000,		/* ypld, bb, 0 lines */
3817 	0x00000000,		/* ypld, k2, 0 lines */
3818 	0x00000000,
3819 	0x028a010e,		/* prm, bb, 14 lines */
3820 	0x02980110,		/* prm, k2, 16 lines */
3821 	0x00000000,
3822 	0x02a8000d,		/* pbf_pb1, bb, 13 lines */
3823 	0x02a8000d,		/* pbf_pb1, k2, 13 lines */
3824 	0x00000000,
3825 	0x02a8000d,		/* pbf_pb2, bb, 13 lines */
3826 	0x02a8000d,		/* pbf_pb2, k2, 13 lines */
3827 	0x00000000,
3828 	0x02a8000d,		/* rpb, bb, 13 lines */
3829 	0x02a8000d,		/* rpb, k2, 13 lines */
3830 	0x00000000,
3831 	0x00600185,		/* btb, bb, 133 lines */
3832 	0x00600185,		/* btb, k2, 133 lines */
3833 	0x00000000,
3834 	0x02b50117,		/* pbf, bb, 23 lines */
3835 	0x02b50117,		/* pbf, k2, 23 lines */
3836 	0x00000000,
3837 	0x02cc0006,		/* rdif, bb, 6 lines */
3838 	0x02cc0006,		/* rdif, k2, 6 lines */
3839 	0x00000000,
3840 	0x02d20006,		/* tdif, bb, 6 lines */
3841 	0x02d20006,		/* tdif, k2, 6 lines */
3842 	0x00000000,
3843 	0x02d80003,		/* cdu, bb, 3 lines */
3844 	0x02db000e,		/* cdu, k2, 14 lines */
3845 	0x00000000,
3846 	0x02e9010d,		/* ccfc, bb, 13 lines */
3847 	0x02f60117,		/* ccfc, k2, 23 lines */
3848 	0x00000000,
3849 	0x02e9010d,		/* tcfc, bb, 13 lines */
3850 	0x02f60117,		/* tcfc, k2, 23 lines */
3851 	0x00000000,
3852 	0x030d0133,		/* igu, bb, 51 lines */
3853 	0x030d0133,		/* igu, k2, 51 lines */
3854 	0x00000000,
3855 	0x03400106,		/* cau, bb, 6 lines */
3856 	0x03400106,		/* cau, k2, 6 lines */
3857 	0x00000000,
3858 	0x00000000,		/* rgfs, bb, 0 lines */
3859 	0x00000000,		/* rgfs, k2, 0 lines */
3860 	0x00000000,
3861 	0x00000000,		/* rgsrc, bb, 0 lines */
3862 	0x00000000,		/* rgsrc, k2, 0 lines */
3863 	0x00000000,
3864 	0x00000000,		/* tgfs, bb, 0 lines */
3865 	0x00000000,		/* tgfs, k2, 0 lines */
3866 	0x00000000,
3867 	0x00000000,		/* tgsrc, bb, 0 lines */
3868 	0x00000000,		/* tgsrc, k2, 0 lines */
3869 	0x00000000,
3870 	0x00000000,		/* umac, bb, 0 lines */
3871 	0x00120006,		/* umac, k2, 6 lines */
3872 	0x00000000,
3873 	0x00000000,		/* xmac, bb, 0 lines */
3874 	0x00000000,		/* xmac, k2, 0 lines */
3875 	0x00000000,
3876 	0x00000000,		/* dbg, bb, 0 lines */
3877 	0x00000000,		/* dbg, k2, 0 lines */
3878 	0x00000000,
3879 	0x0346012b,		/* nig, bb, 43 lines */
3880 	0x0346011d,		/* nig, k2, 29 lines */
3881 	0x00000000,
3882 	0x00000000,		/* wol, bb, 0 lines */
3883 	0x001c0002,		/* wol, k2, 2 lines */
3884 	0x00000000,
3885 	0x00000000,		/* bmbn, bb, 0 lines */
3886 	0x00210008,		/* bmbn, k2, 8 lines */
3887 	0x00000000,
3888 	0x00000000,		/* ipc, bb, 0 lines */
3889 	0x00000000,		/* ipc, k2, 0 lines */
3890 	0x00000000,
3891 	0x00000000,		/* nwm, bb, 0 lines */
3892 	0x0371000b,		/* nwm, k2, 11 lines */
3893 	0x00000000,
3894 	0x00000000,		/* nws, bb, 0 lines */
3895 	0x037c0009,		/* nws, k2, 9 lines */
3896 	0x00000000,
3897 	0x00000000,		/* ms, bb, 0 lines */
3898 	0x00120004,		/* ms, k2, 4 lines */
3899 	0x00000000,
3900 	0x00000000,		/* phy_pcie, bb, 0 lines */
3901 	0x00e5001a,		/* phy_pcie, k2, 26 lines */
3902 	0x00000000,
3903 	0x00000000,		/* led, bb, 0 lines */
3904 	0x00000000,		/* led, k2, 0 lines */
3905 	0x00000000,
3906 	0x00000000,		/* avs_wrap, bb, 0 lines */
3907 	0x00000000,		/* avs_wrap, k2, 0 lines */
3908 	0x00000000,
3909 	0x00000000,		/* bar0_map, bb, 0 lines */
3910 	0x00000000,		/* bar0_map, k2, 0 lines */
3911 	0x00000000,
3912 	0x00000000,		/* bar0_map, bb, 0 lines */
3913 	0x00000000,		/* bar0_map, k2, 0 lines */
3914 	0x00000000,
3915 };
3916 
3917 /* Win 2 */
3918 #define GTT_BAR0_MAP_REG_IGU_CMD	0x00f000UL
3919 
3920 /* Win 3 */
3921 #define GTT_BAR0_MAP_REG_TSDM_RAM	0x010000UL
3922 
3923 /* Win 4 */
3924 #define GTT_BAR0_MAP_REG_MSDM_RAM	0x011000UL
3925 
3926 /* Win 5 */
3927 #define GTT_BAR0_MAP_REG_MSDM_RAM_1024	0x012000UL
3928 
3929 /* Win 6 */
3930 #define GTT_BAR0_MAP_REG_USDM_RAM	0x013000UL
3931 
3932 /* Win 7 */
3933 #define GTT_BAR0_MAP_REG_USDM_RAM_1024	0x014000UL
3934 
3935 /* Win 8 */
3936 #define GTT_BAR0_MAP_REG_USDM_RAM_2048	0x015000UL
3937 
3938 /* Win 9 */
3939 #define GTT_BAR0_MAP_REG_XSDM_RAM	0x016000UL
3940 
3941 /* Win 10 */
3942 #define GTT_BAR0_MAP_REG_YSDM_RAM	0x017000UL
3943 
3944 /* Win 11 */
3945 #define GTT_BAR0_MAP_REG_PSDM_RAM	0x018000UL
3946 
3947 /**
3948  * @brief qed_qm_pf_mem_size - prepare QM ILT sizes
3949  *
3950  * Returns the required host memory size in 4KB units.
3951  * Must be called before all QM init HSI functions.
3952  *
3953  * @param num_pf_cids - number of connections used by this PF
3954  * @param num_vf_cids - number of connections used by VFs of this PF
3955  * @param num_tids - number of tasks used by this PF
3956  * @param num_pf_pqs - number of PQs used by this PF
3957  * @param num_vf_pqs - number of PQs used by VFs of this PF
3958  *
3959  * @return The required host memory size in 4KB units.
3960  */
3961 u32 qed_qm_pf_mem_size(u32 num_pf_cids,
3962 		       u32 num_vf_cids,
3963 		       u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs);
3964 
3965 struct qed_qm_common_rt_init_params {
3966 	u8 max_ports_per_engine;
3967 	u8 max_phys_tcs_per_port;
3968 	bool pf_rl_en;
3969 	bool pf_wfq_en;
3970 	bool vport_rl_en;
3971 	bool vport_wfq_en;
3972 	struct init_qm_port_params *port_params;
3973 };
3974 
3975 int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn,
3976 			  struct qed_qm_common_rt_init_params *p_params);
3977 
3978 struct qed_qm_pf_rt_init_params {
3979 	u8 port_id;
3980 	u8 pf_id;
3981 	u8 max_phys_tcs_per_port;
3982 	bool is_pf_loading;
3983 	u32 num_pf_cids;
3984 	u32 num_vf_cids;
3985 	u32 num_tids;
3986 	u16 start_pq;
3987 	u16 num_pf_pqs;
3988 	u16 num_vf_pqs;
3989 	u8 start_vport;
3990 	u8 num_vports;
3991 	u16 pf_wfq;
3992 	u32 pf_rl;
3993 	u32 link_speed;
3994 	struct init_qm_pq_params *pq_params;
3995 	struct init_qm_vport_params *vport_params;
3996 };
3997 
3998 int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
3999 	struct qed_ptt *p_ptt,
4000 	struct qed_qm_pf_rt_init_params *p_params);
4001 
4002 /**
4003  * @brief qed_init_pf_wfq - Initializes the WFQ weight of the specified PF
4004  *
4005  * @param p_hwfn
4006  * @param p_ptt - ptt window used for writing the registers
4007  * @param pf_id - PF ID
4008  * @param pf_wfq - WFQ weight. Must be non-zero.
4009  *
4010  * @return 0 on success, -1 on error.
4011  */
4012 int qed_init_pf_wfq(struct qed_hwfn *p_hwfn,
4013 		    struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq);
4014 
4015 /**
4016  * @brief qed_init_pf_rl - Initializes the rate limit of the specified PF
4017  *
4018  * @param p_hwfn
4019  * @param p_ptt - ptt window used for writing the registers
4020  * @param pf_id - PF ID
4021  * @param pf_rl - rate limit in Mb/sec units
4022  *
4023  * @return 0 on success, -1 on error.
4024  */
4025 int qed_init_pf_rl(struct qed_hwfn *p_hwfn,
4026 		   struct qed_ptt *p_ptt, u8 pf_id, u32 pf_rl);
4027 
4028 /**
4029  * @brief qed_init_vport_wfq Initializes the WFQ weight of the specified VPORT
4030  *
4031  * @param p_hwfn
4032  * @param p_ptt - ptt window used for writing the registers
4033  * @param first_tx_pq_id- An array containing the first Tx PQ ID associated
4034  *	  with the VPORT for each TC. This array is filled by
4035  *	  qed_qm_pf_rt_init
4036  * @param vport_wfq - WFQ weight. Must be non-zero.
4037  *
4038  * @return 0 on success, -1 on error.
4039  */
4040 int qed_init_vport_wfq(struct qed_hwfn *p_hwfn,
4041 		       struct qed_ptt *p_ptt,
4042 		       u16 first_tx_pq_id[NUM_OF_TCS], u16 vport_wfq);
4043 
4044 /**
4045  * @brief qed_init_vport_rl - Initializes the rate limit of the specified VPORT
4046  *
4047  * @param p_hwfn
4048  * @param p_ptt - ptt window used for writing the registers
4049  * @param vport_id - VPORT ID
4050  * @param vport_rl - rate limit in Mb/sec units
4051  * @param link_speed - link speed in Mbps.
4052  *
4053  * @return 0 on success, -1 on error.
4054  */
4055 int qed_init_vport_rl(struct qed_hwfn *p_hwfn,
4056 		      struct qed_ptt *p_ptt,
4057 		      u8 vport_id, u32 vport_rl, u32 link_speed);
4058 
4059 /**
4060  * @brief qed_send_qm_stop_cmd  Sends a stop command to the QM
4061  *
4062  * @param p_hwfn
4063  * @param p_ptt
4064  * @param is_release_cmd - true for release, false for stop.
4065  * @param is_tx_pq - true for Tx PQs, false for Other PQs.
4066  * @param start_pq - first PQ ID to stop
4067  * @param num_pqs - Number of PQs to stop, starting from start_pq.
4068  *
4069  * @return bool, true if successful, false if timeout occurred while waiting for
4070  *	QM command done.
4071  */
4072 bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
4073 			  struct qed_ptt *p_ptt,
4074 			  bool is_release_cmd,
4075 			  bool is_tx_pq, u16 start_pq, u16 num_pqs);
4076 
4077 /**
4078  * @brief qed_set_vxlan_dest_port - initializes vxlan tunnel destination udp port
4079  *
4080  * @param p_hwfn
4081  * @param p_ptt - ptt window used for writing the registers.
4082  * @param dest_port - vxlan destination udp port.
4083  */
4084 void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn,
4085 			     struct qed_ptt *p_ptt, u16 dest_port);
4086 
4087 /**
4088  * @brief qed_set_vxlan_enable - enable or disable VXLAN tunnel in HW
4089  *
4090  * @param p_hwfn
4091  * @param p_ptt - ptt window used for writing the registers.
4092  * @param vxlan_enable - vxlan enable flag.
4093  */
4094 void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn,
4095 			  struct qed_ptt *p_ptt, bool vxlan_enable);
4096 
4097 /**
4098  * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
4099  *
4100  * @param p_hwfn
4101  * @param p_ptt - ptt window used for writing the registers.
4102  * @param eth_gre_enable - eth GRE enable enable flag.
4103  * @param ip_gre_enable - IP GRE enable enable flag.
4104  */
4105 void qed_set_gre_enable(struct qed_hwfn *p_hwfn,
4106 			struct qed_ptt *p_ptt,
4107 			bool eth_gre_enable, bool ip_gre_enable);
4108 
4109 /**
4110  * @brief qed_set_geneve_dest_port - initializes geneve tunnel destination udp port
4111  *
4112  * @param p_hwfn
4113  * @param p_ptt - ptt window used for writing the registers.
4114  * @param dest_port - geneve destination udp port.
4115  */
4116 void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn,
4117 			      struct qed_ptt *p_ptt, u16 dest_port);
4118 
4119 /**
4120  * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
4121  *
4122  * @param p_ptt - ptt window used for writing the registers.
4123  * @param eth_geneve_enable - eth GENEVE enable enable flag.
4124  * @param ip_geneve_enable - IP GENEVE enable enable flag.
4125  */
4126 void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
4127 			   struct qed_ptt *p_ptt,
4128 			   bool eth_geneve_enable, bool ip_geneve_enable);
4129 
4130 void qed_set_vxlan_no_l2_enable(struct qed_hwfn *p_hwfn,
4131 				struct qed_ptt *p_ptt, bool enable);
4132 
4133 /**
4134  * @brief qed_gft_disable - Disable GFT
4135  *
4136  * @param p_hwfn
4137  * @param p_ptt - ptt window used for writing the registers.
4138  * @param pf_id - pf on which to disable GFT.
4139  */
4140 void qed_gft_disable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 pf_id);
4141 
4142 /**
4143  * @brief qed_gft_config - Enable and configure HW for GFT
4144  *
4145  * @param p_hwfn
4146  * @param p_ptt - ptt window used for writing the registers.
4147  * @param pf_id - pf on which to enable GFT.
4148  * @param tcp - set profile tcp packets.
4149  * @param udp - set profile udp  packet.
4150  * @param ipv4 - set profile ipv4 packet.
4151  * @param ipv6 - set profile ipv6 packet.
4152  * @param profile_type - define packet same fields. Use enum gft_profile_type.
4153  */
4154 void qed_gft_config(struct qed_hwfn *p_hwfn,
4155 		    struct qed_ptt *p_ptt,
4156 		    u16 pf_id,
4157 		    bool tcp,
4158 		    bool udp,
4159 		    bool ipv4, bool ipv6, enum gft_profile_type profile_type);
4160 
4161 /**
4162  * @brief qed_enable_context_validation - Enable and configure context
4163  *	validation.
4164  *
4165  * @param p_hwfn
4166  * @param p_ptt - ptt window used for writing the registers.
4167  */
4168 void qed_enable_context_validation(struct qed_hwfn *p_hwfn,
4169 				   struct qed_ptt *p_ptt);
4170 
4171 /**
4172  * @brief qed_calc_session_ctx_validation - Calcualte validation byte for
4173  *	session context.
4174  *
4175  * @param p_ctx_mem - pointer to context memory.
4176  * @param ctx_size - context size.
4177  * @param ctx_type - context type.
4178  * @param cid - context cid.
4179  */
4180 void qed_calc_session_ctx_validation(void *p_ctx_mem,
4181 				     u16 ctx_size, u8 ctx_type, u32 cid);
4182 
4183 /**
4184  * @brief qed_calc_task_ctx_validation - Calcualte validation byte for task
4185  *	context.
4186  *
4187  * @param p_ctx_mem - pointer to context memory.
4188  * @param ctx_size - context size.
4189  * @param ctx_type - context type.
4190  * @param tid - context tid.
4191  */
4192 void qed_calc_task_ctx_validation(void *p_ctx_mem,
4193 				  u16 ctx_size, u8 ctx_type, u32 tid);
4194 
4195 /**
4196  * @brief qed_memset_session_ctx - Memset session context to 0 while
4197  *	preserving validation bytes.
4198  *
4199  * @param p_hwfn -
4200  * @param p_ctx_mem - pointer to context memory.
4201  * @param ctx_size - size to initialzie.
4202  * @param ctx_type - context type.
4203  */
4204 void qed_memset_session_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type);
4205 
4206 /**
4207  * @brief qed_memset_task_ctx - Memset task context to 0 while preserving
4208  *	validation bytes.
4209  *
4210  * @param p_ctx_mem - pointer to context memory.
4211  * @param ctx_size - size to initialzie.
4212  * @param ctx_type - context type.
4213  */
4214 void qed_memset_task_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type);
4215 
4216 #define NUM_STORMS 6
4217 
4218 /**
4219  * @brief qed_set_rdma_error_level - Sets the RDMA assert level.
4220  *                                   If the severity of the error will be
4221  *                                   above the level, the FW will assert.
4222  * @param p_hwfn - HW device data
4223  * @param p_ptt - ptt window used for writing the registers
4224  * @param assert_level - An array of assert levels for each storm.
4225  *
4226  */
4227 void qed_set_rdma_error_level(struct qed_hwfn *p_hwfn,
4228 			      struct qed_ptt *p_ptt,
4229 			      u8 assert_level[NUM_STORMS]);
4230 
4231 /* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */
4232 #define YSTORM_FLOW_CONTROL_MODE_OFFSET			(IRO[0].base)
4233 #define YSTORM_FLOW_CONTROL_MODE_SIZE			(IRO[0].size)
4234 
4235 /* Tstorm port statistics */
4236 #define TSTORM_PORT_STAT_OFFSET(port_id) \
4237 	(IRO[1].base + ((port_id) * IRO[1].m1))
4238 #define TSTORM_PORT_STAT_SIZE				(IRO[1].size)
4239 
4240 /* Tstorm ll2 port statistics */
4241 #define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \
4242 	(IRO[2].base + ((port_id) * IRO[2].m1))
4243 #define TSTORM_LL2_PORT_STAT_SIZE			(IRO[2].size)
4244 
4245 /* Ustorm VF-PF Channel ready flag */
4246 #define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \
4247 	(IRO[3].base + ((vf_id) * IRO[3].m1))
4248 #define USTORM_VF_PF_CHANNEL_READY_SIZE			(IRO[3].size)
4249 
4250 /* Ustorm Final flr cleanup ack */
4251 #define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) \
4252 	(IRO[4].base + ((pf_id) * IRO[4].m1))
4253 #define USTORM_FLR_FINAL_ACK_SIZE			(IRO[4].size)
4254 
4255 /* Ustorm Event ring consumer */
4256 #define USTORM_EQE_CONS_OFFSET(pf_id) \
4257 	(IRO[5].base + ((pf_id) * IRO[5].m1))
4258 #define USTORM_EQE_CONS_SIZE				(IRO[5].size)
4259 
4260 /* Ustorm eth queue zone */
4261 #define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) \
4262 	(IRO[6].base + ((queue_zone_id) * IRO[6].m1))
4263 #define USTORM_ETH_QUEUE_ZONE_SIZE			(IRO[6].size)
4264 
4265 /* Ustorm Common Queue ring consumer */
4266 #define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) \
4267 	(IRO[7].base + ((queue_zone_id) * IRO[7].m1))
4268 #define USTORM_COMMON_QUEUE_CONS_SIZE			(IRO[7].size)
4269 
4270 /* Xstorm Integration Test Data */
4271 #define XSTORM_INTEG_TEST_DATA_OFFSET			(IRO[8].base)
4272 #define XSTORM_INTEG_TEST_DATA_SIZE			(IRO[8].size)
4273 
4274 /* Ystorm Integration Test Data */
4275 #define YSTORM_INTEG_TEST_DATA_OFFSET			(IRO[9].base)
4276 #define YSTORM_INTEG_TEST_DATA_SIZE			(IRO[9].size)
4277 
4278 /* Pstorm Integration Test Data */
4279 #define PSTORM_INTEG_TEST_DATA_OFFSET			(IRO[10].base)
4280 #define PSTORM_INTEG_TEST_DATA_SIZE			(IRO[10].size)
4281 
4282 /* Tstorm Integration Test Data */
4283 #define TSTORM_INTEG_TEST_DATA_OFFSET			(IRO[11].base)
4284 #define TSTORM_INTEG_TEST_DATA_SIZE			(IRO[11].size)
4285 
4286 /* Mstorm Integration Test Data */
4287 #define MSTORM_INTEG_TEST_DATA_OFFSET			(IRO[12].base)
4288 #define MSTORM_INTEG_TEST_DATA_SIZE			(IRO[12].size)
4289 
4290 /* Ustorm Integration Test Data */
4291 #define USTORM_INTEG_TEST_DATA_OFFSET			(IRO[13].base)
4292 #define USTORM_INTEG_TEST_DATA_SIZE			(IRO[13].size)
4293 
4294 /* Tstorm producers */
4295 #define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \
4296 	(IRO[14].base + ((core_rx_queue_id) * IRO[14].m1))
4297 #define TSTORM_LL2_RX_PRODS_SIZE			(IRO[14].size)
4298 
4299 /* Tstorm LightL2 queue statistics */
4300 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
4301 	(IRO[15].base + ((core_rx_queue_id) * IRO[15].m1))
4302 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE		(IRO[15].size)
4303 
4304 /* Ustorm LiteL2 queue statistics */
4305 #define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
4306 	(IRO[16].base + ((core_rx_queue_id) * IRO[16].m1))
4307 #define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE		(IRO[16].size)
4308 
4309 /* Pstorm LiteL2 queue statistics */
4310 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
4311 	(IRO[17].base + ((core_tx_stats_id) * IRO[17].m1))
4312 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE		(IRO[17].size)
4313 
4314 /* Mstorm queue statistics */
4315 #define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
4316 	(IRO[18].base + ((stat_counter_id) * IRO[18].m1))
4317 #define MSTORM_QUEUE_STAT_SIZE				(IRO[18].size)
4318 
4319 /* Mstorm ETH PF queues producers */
4320 #define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) \
4321 	(IRO[19].base + ((queue_id) * IRO[19].m1))
4322 #define MSTORM_ETH_PF_PRODS_SIZE			(IRO[19].size)
4323 
4324 /* Mstorm ETH VF queues producers offset in RAM. Used in default VF zone size
4325  * mode.
4326  */
4327 #define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \
4328 	(IRO[20].base + ((vf_id) * IRO[20].m1) + ((vf_queue_id) * IRO[20].m2))
4329 #define MSTORM_ETH_VF_PRODS_SIZE			(IRO[20].size)
4330 
4331 /* TPA agregation timeout in us resolution (on ASIC) */
4332 #define MSTORM_TPA_TIMEOUT_US_OFFSET			(IRO[21].base)
4333 #define MSTORM_TPA_TIMEOUT_US_SIZE			(IRO[21].size)
4334 
4335 /* Mstorm pf statistics */
4336 #define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \
4337 	(IRO[22].base + ((pf_id) * IRO[22].m1))
4338 #define MSTORM_ETH_PF_STAT_SIZE				(IRO[22].size)
4339 
4340 /* Ustorm queue statistics */
4341 #define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
4342 	(IRO[23].base + ((stat_counter_id) * IRO[23].m1))
4343 #define USTORM_QUEUE_STAT_SIZE				(IRO[23].size)
4344 
4345 /* Ustorm pf statistics */
4346 #define USTORM_ETH_PF_STAT_OFFSET(pf_id)\
4347 	(IRO[24].base + ((pf_id) * IRO[24].m1))
4348 #define USTORM_ETH_PF_STAT_SIZE				(IRO[24].size)
4349 
4350 /* Pstorm queue statistics */
4351 #define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
4352 	(IRO[25].base + ((stat_counter_id) * IRO[25].m1))
4353 #define PSTORM_QUEUE_STAT_SIZE				(IRO[25].size)
4354 
4355 /* Pstorm pf statistics */
4356 #define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \
4357 	(IRO[26].base + ((pf_id) * IRO[26].m1))
4358 #define PSTORM_ETH_PF_STAT_SIZE				(IRO[26].size)
4359 
4360 /* Control frame's EthType configuration for TX control frame security */
4361 #define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(eth_type_id) \
4362 	(IRO[27].base + ((eth_type_id) * IRO[27].m1))
4363 #define PSTORM_CTL_FRAME_ETHTYPE_SIZE			(IRO[27].size)
4364 
4365 /* Tstorm last parser message */
4366 #define TSTORM_ETH_PRS_INPUT_OFFSET			(IRO[28].base)
4367 #define TSTORM_ETH_PRS_INPUT_SIZE			(IRO[28].size)
4368 
4369 /* Tstorm Eth limit Rx rate */
4370 #define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \
4371 	(IRO[29].base + ((pf_id) * IRO[29].m1))
4372 #define ETH_RX_RATE_LIMIT_SIZE				(IRO[29].size)
4373 
4374 /* RSS indirection table entry update command per PF offset in TSTORM PF BAR0.
4375  * Use eth_tstorm_rss_update_data for update.
4376  */
4377 #define TSTORM_ETH_RSS_UPDATE_OFFSET(pf_id) \
4378 	(IRO[30].base + ((pf_id) * IRO[30].m1))
4379 #define TSTORM_ETH_RSS_UPDATE_SIZE			(IRO[30].size)
4380 
4381 /* Xstorm queue zone */
4382 #define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
4383 	(IRO[31].base + ((queue_id) * IRO[31].m1))
4384 #define XSTORM_ETH_QUEUE_ZONE_SIZE			(IRO[31].size)
4385 
4386 /* Ystorm cqe producer */
4387 #define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) \
4388 	(IRO[32].base + ((rss_id) * IRO[32].m1))
4389 #define YSTORM_TOE_CQ_PROD_SIZE				(IRO[32].size)
4390 
4391 /* Ustorm cqe producer */
4392 #define USTORM_TOE_CQ_PROD_OFFSET(rss_id) \
4393 	(IRO[33].base + ((rss_id) * IRO[33].m1))
4394 #define USTORM_TOE_CQ_PROD_SIZE				(IRO[33].size)
4395 
4396 /* Ustorm grq producer */
4397 #define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) \
4398 	(IRO[34].base + ((pf_id) * IRO[34].m1))
4399 #define USTORM_TOE_GRQ_PROD_SIZE			(IRO[34].size)
4400 
4401 /* Tstorm cmdq-cons of given command queue-id */
4402 #define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \
4403 	(IRO[35].base + ((cmdq_queue_id) * IRO[35].m1))
4404 #define TSTORM_SCSI_CMDQ_CONS_SIZE			(IRO[35].size)
4405 
4406 /* Tstorm (reflects M-Storm) bdq-external-producer of given function ID,
4407  * BDqueue-id.
4408  */
4409 #define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
4410 	(IRO[36].base + ((func_id) * IRO[36].m1) + ((bdq_id) * IRO[36].m2))
4411 #define TSTORM_SCSI_BDQ_EXT_PROD_SIZE			(IRO[36].size)
4412 
4413 /* Mstorm bdq-external-producer of given BDQ resource ID, BDqueue-id */
4414 #define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \
4415 	(IRO[37].base + ((func_id) * IRO[37].m1) + ((bdq_id) * IRO[37].m2))
4416 #define MSTORM_SCSI_BDQ_EXT_PROD_SIZE			(IRO[37].size)
4417 
4418 /* Tstorm iSCSI RX stats */
4419 #define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
4420 	(IRO[38].base + ((pf_id) * IRO[38].m1))
4421 #define TSTORM_ISCSI_RX_STATS_SIZE			(IRO[38].size)
4422 
4423 /* Mstorm iSCSI RX stats */
4424 #define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
4425 	(IRO[39].base + ((pf_id) * IRO[39].m1))
4426 #define MSTORM_ISCSI_RX_STATS_SIZE			(IRO[39].size)
4427 
4428 /* Ustorm iSCSI RX stats */
4429 #define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) \
4430 	(IRO[40].base + ((pf_id) * IRO[40].m1))
4431 #define USTORM_ISCSI_RX_STATS_SIZE			(IRO[40].size)
4432 
4433 /* Xstorm iSCSI TX stats */
4434 #define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
4435 	(IRO[41].base + ((pf_id) * IRO[41].m1))
4436 #define XSTORM_ISCSI_TX_STATS_SIZE			(IRO[41].size)
4437 
4438 /* Ystorm iSCSI TX stats */
4439 #define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
4440 	(IRO[42].base + ((pf_id) * IRO[42].m1))
4441 #define YSTORM_ISCSI_TX_STATS_SIZE			(IRO[42].size)
4442 
4443 /* Pstorm iSCSI TX stats */
4444 #define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \
4445 	(IRO[43].base + ((pf_id) * IRO[43].m1))
4446 #define PSTORM_ISCSI_TX_STATS_SIZE			(IRO[43].size)
4447 
4448 /* Tstorm FCoE RX stats */
4449 #define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
4450 	(IRO[44].base + ((pf_id) * IRO[44].m1))
4451 #define TSTORM_FCOE_RX_STATS_SIZE			(IRO[44].size)
4452 
4453 /* Pstorm FCoE TX stats */
4454 #define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \
4455 	(IRO[45].base + ((pf_id) * IRO[45].m1))
4456 #define PSTORM_FCOE_TX_STATS_SIZE			(IRO[45].size)
4457 
4458 /* Pstorm RDMA queue statistics */
4459 #define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
4460 	(IRO[46].base + ((rdma_stat_counter_id) * IRO[46].m1))
4461 #define PSTORM_RDMA_QUEUE_STAT_SIZE			(IRO[46].size)
4462 
4463 /* Tstorm RDMA queue statistics */
4464 #define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
4465 	(IRO[47].base + ((rdma_stat_counter_id) * IRO[47].m1))
4466 #define TSTORM_RDMA_QUEUE_STAT_SIZE			(IRO[47].size)
4467 
4468 /* Xstorm error level for assert */
4469 #define XSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4470 	(IRO[48].base +	((pf_id) * IRO[48].m1))
4471 #define XSTORM_RDMA_ASSERT_LEVEL_SIZE			(IRO[48].size)
4472 
4473 /* Ystorm error level for assert */
4474 #define YSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4475 	(IRO[49].base + ((pf_id) * IRO[49].m1))
4476 #define YSTORM_RDMA_ASSERT_LEVEL_SIZE			(IRO[49].size)
4477 
4478 /* Pstorm error level for assert */
4479 #define PSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4480 	(IRO[50].base +	((pf_id) * IRO[50].m1))
4481 #define PSTORM_RDMA_ASSERT_LEVEL_SIZE			(IRO[50].size)
4482 
4483 /* Tstorm error level for assert */
4484 #define TSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4485 	(IRO[51].base +	((pf_id) * IRO[51].m1))
4486 #define TSTORM_RDMA_ASSERT_LEVEL_SIZE			(IRO[51].size)
4487 
4488 /* Mstorm error level for assert */
4489 #define MSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4490 	(IRO[52].base + ((pf_id) * IRO[52].m1))
4491 #define MSTORM_RDMA_ASSERT_LEVEL_SIZE			(IRO[52].size)
4492 
4493 /* Ustorm error level for assert */
4494 #define USTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4495 	(IRO[53].base + ((pf_id) * IRO[53].m1))
4496 #define USTORM_RDMA_ASSERT_LEVEL_SIZE			(IRO[53].size)
4497 
4498 /* Xstorm iWARP rxmit stats */
4499 #define XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id) \
4500 	(IRO[54].base +	((pf_id) * IRO[54].m1))
4501 #define XSTORM_IWARP_RXMIT_STATS_SIZE			(IRO[54].size)
4502 
4503 /* Tstorm RoCE Event Statistics */
4504 #define TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id) \
4505 	(IRO[55].base + ((roce_pf_id) * IRO[55].m1))
4506 #define TSTORM_ROCE_EVENTS_STAT_SIZE			(IRO[55].size)
4507 
4508 /* DCQCN Received Statistics */
4509 #define YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id) \
4510 	(IRO[56].base + ((roce_pf_id) * IRO[56].m1))
4511 #define YSTORM_ROCE_DCQCN_RECEIVED_STATS_SIZE		(IRO[56].size)
4512 
4513 /* RoCE Error Statistics */
4514 #define YSTORM_ROCE_ERROR_STATS_OFFSET(roce_pf_id) \
4515 	(IRO[57].base + ((roce_pf_id) * IRO[57].m1))
4516 #define YSTORM_ROCE_ERROR_STATS_SIZE			(IRO[57].size)
4517 
4518 /* DCQCN Sent Statistics */
4519 #define PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id) \
4520 	(IRO[58].base + ((roce_pf_id) * IRO[58].m1))
4521 #define PSTORM_ROCE_DCQCN_SENT_STATS_SIZE		(IRO[58].size)
4522 
4523 /* RoCE CQEs Statistics */
4524 #define USTORM_ROCE_CQE_STATS_OFFSET(roce_pf_id) \
4525 	(IRO[59].base + ((roce_pf_id) * IRO[59].m1))
4526 #define USTORM_ROCE_CQE_STATS_SIZE			(IRO[59].size)
4527 
4528 static const struct iro iro_arr[60] = {
4529 	{0x0, 0x0, 0x0, 0x0, 0x8},
4530 	{0x4cb8, 0x88, 0x0, 0x0, 0x88},
4531 	{0x6530, 0x20, 0x0, 0x0, 0x20},
4532 	{0xb00, 0x8, 0x0, 0x0, 0x4},
4533 	{0xa80, 0x8, 0x0, 0x0, 0x4},
4534 	{0x0, 0x8, 0x0, 0x0, 0x2},
4535 	{0x80, 0x8, 0x0, 0x0, 0x4},
4536 	{0x84, 0x8, 0x0, 0x0, 0x2},
4537 	{0x4c48, 0x0, 0x0, 0x0, 0x78},
4538 	{0x3e38, 0x0, 0x0, 0x0, 0x78},
4539 	{0x3ef8, 0x0, 0x0, 0x0, 0x78},
4540 	{0x4c40, 0x0, 0x0, 0x0, 0x78},
4541 	{0x4998, 0x0, 0x0, 0x0, 0x78},
4542 	{0x7f50, 0x0, 0x0, 0x0, 0x78},
4543 	{0xa28, 0x8, 0x0, 0x0, 0x8},
4544 	{0x6210, 0x10, 0x0, 0x0, 0x10},
4545 	{0xb820, 0x30, 0x0, 0x0, 0x30},
4546 	{0xa990, 0x30, 0x0, 0x0, 0x30},
4547 	{0x4b68, 0x80, 0x0, 0x0, 0x40},
4548 	{0x1f8, 0x4, 0x0, 0x0, 0x4},
4549 	{0x53a8, 0x80, 0x4, 0x0, 0x4},
4550 	{0xc7d0, 0x0, 0x0, 0x0, 0x4},
4551 	{0x4ba8, 0x80, 0x0, 0x0, 0x20},
4552 	{0x8158, 0x40, 0x0, 0x0, 0x30},
4553 	{0xe770, 0x60, 0x0, 0x0, 0x60},
4554 	{0x4090, 0x80, 0x0, 0x0, 0x38},
4555 	{0xfea8, 0x78, 0x0, 0x0, 0x78},
4556 	{0x1f8, 0x4, 0x0, 0x0, 0x4},
4557 	{0xaf20, 0x0, 0x0, 0x0, 0xf0},
4558 	{0xb010, 0x8, 0x0, 0x0, 0x8},
4559 	{0xc00, 0x8, 0x0, 0x0, 0x8},
4560 	{0x1f8, 0x8, 0x0, 0x0, 0x8},
4561 	{0xac0, 0x8, 0x0, 0x0, 0x8},
4562 	{0x2578, 0x8, 0x0, 0x0, 0x8},
4563 	{0x24f8, 0x8, 0x0, 0x0, 0x8},
4564 	{0x0, 0x8, 0x0, 0x0, 0x8},
4565 	{0x400, 0x18, 0x8, 0x0, 0x8},
4566 	{0xb78, 0x18, 0x8, 0x0, 0x2},
4567 	{0xd898, 0x50, 0x0, 0x0, 0x3c},
4568 	{0x12908, 0x18, 0x0, 0x0, 0x10},
4569 	{0x11aa8, 0x40, 0x0, 0x0, 0x18},
4570 	{0xa588, 0x50, 0x0, 0x0, 0x20},
4571 	{0x8f00, 0x40, 0x0, 0x0, 0x28},
4572 	{0x10e30, 0x18, 0x0, 0x0, 0x10},
4573 	{0xde48, 0x48, 0x0, 0x0, 0x38},
4574 	{0x11298, 0x20, 0x0, 0x0, 0x20},
4575 	{0x40c8, 0x80, 0x0, 0x0, 0x10},
4576 	{0x5048, 0x10, 0x0, 0x0, 0x10},
4577 	{0xc748, 0x8, 0x0, 0x0, 0x1},
4578 	{0xa928, 0x8, 0x0, 0x0, 0x1},
4579 	{0x11a30, 0x8, 0x0, 0x0, 0x1},
4580 	{0xf030, 0x8, 0x0, 0x0, 0x1},
4581 	{0x13028, 0x8, 0x0, 0x0, 0x1},
4582 	{0x12c58, 0x8, 0x0, 0x0, 0x1},
4583 	{0xc9b8, 0x30, 0x0, 0x0, 0x10},
4584 	{0xed90, 0x28, 0x0, 0x0, 0x28},
4585 	{0xad20, 0x18, 0x0, 0x0, 0x18},
4586 	{0xaea0, 0x8, 0x0, 0x0, 0x8},
4587 	{0x13c38, 0x8, 0x0, 0x0, 0x8},
4588 	{0x13c50, 0x18, 0x0, 0x0, 0x18},
4589 };
4590 
4591 /* Runtime array offsets */
4592 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET			0
4593 #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET			1
4594 #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET			2
4595 #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET			3
4596 #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET			4
4597 #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET			5
4598 #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET			6
4599 #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET			7
4600 #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET			8
4601 #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET			9
4602 #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET			10
4603 #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET			11
4604 #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET			12
4605 #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET			13
4606 #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET			14
4607 #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET			15
4608 #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET				16
4609 #define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET			17
4610 #define DORQ_REG_GLB_MAX_ICID_0_RT_OFFSET			18
4611 #define DORQ_REG_GLB_MAX_ICID_1_RT_OFFSET			19
4612 #define DORQ_REG_GLB_RANGE2CONN_TYPE_0_RT_OFFSET		20
4613 #define DORQ_REG_GLB_RANGE2CONN_TYPE_1_RT_OFFSET		21
4614 #define DORQ_REG_PRV_PF_MAX_ICID_2_RT_OFFSET			22
4615 #define DORQ_REG_PRV_PF_MAX_ICID_3_RT_OFFSET			23
4616 #define DORQ_REG_PRV_PF_MAX_ICID_4_RT_OFFSET			24
4617 #define DORQ_REG_PRV_PF_MAX_ICID_5_RT_OFFSET			25
4618 #define DORQ_REG_PRV_VF_MAX_ICID_2_RT_OFFSET			26
4619 #define DORQ_REG_PRV_VF_MAX_ICID_3_RT_OFFSET			27
4620 #define DORQ_REG_PRV_VF_MAX_ICID_4_RT_OFFSET			28
4621 #define DORQ_REG_PRV_VF_MAX_ICID_5_RT_OFFSET			29
4622 #define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_2_RT_OFFSET		30
4623 #define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_3_RT_OFFSET		31
4624 #define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_4_RT_OFFSET		32
4625 #define DORQ_REG_PRV_PF_RANGE2CONN_TYPE_5_RT_OFFSET		33
4626 #define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_2_RT_OFFSET		34
4627 #define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_3_RT_OFFSET		35
4628 #define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_4_RT_OFFSET		36
4629 #define DORQ_REG_PRV_VF_RANGE2CONN_TYPE_5_RT_OFFSET		37
4630 #define IGU_REG_PF_CONFIGURATION_RT_OFFSET			38
4631 #define IGU_REG_VF_CONFIGURATION_RT_OFFSET			39
4632 #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET			40
4633 #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET			41
4634 #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET			42
4635 #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET			43
4636 #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET			44
4637 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET				45
4638 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE				1024
4639 #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET			1069
4640 #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE				1024
4641 #define CAU_REG_PI_MEMORY_RT_OFFSET				2093
4642 #define CAU_REG_PI_MEMORY_RT_SIZE				4416
4643 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET		6509
4644 #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET		6510
4645 #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET		6511
4646 #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET			6512
4647 #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET			6513
4648 #define PRS_REG_SEARCH_TCP_RT_OFFSET				6514
4649 #define PRS_REG_SEARCH_FCOE_RT_OFFSET				6515
4650 #define PRS_REG_SEARCH_ROCE_RT_OFFSET				6516
4651 #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET			6517
4652 #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET			6518
4653 #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET			6519
4654 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET		6520
4655 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET	6521
4656 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET		6522
4657 #define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET			6523
4658 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET			6524
4659 #define SRC_REG_FIRSTFREE_RT_OFFSET				6525
4660 #define SRC_REG_FIRSTFREE_RT_SIZE				2
4661 #define SRC_REG_LASTFREE_RT_OFFSET				6527
4662 #define SRC_REG_LASTFREE_RT_SIZE				2
4663 #define SRC_REG_COUNTFREE_RT_OFFSET				6529
4664 #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET			6530
4665 #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET			6531
4666 #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET			6532
4667 #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET				6533
4668 #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET				6534
4669 #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET				6535
4670 #define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET			6536
4671 #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET			6537
4672 #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET			6538
4673 #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET			6539
4674 #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET			6540
4675 #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET			6541
4676 #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET			6542
4677 #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET			6543
4678 #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET			6544
4679 #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET			6545
4680 #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET			6546
4681 #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET			6547
4682 #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET			6548
4683 #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET		6549
4684 #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET		6550
4685 #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET		6551
4686 #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET			6552
4687 #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET			6553
4688 #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET			6554
4689 #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET			6555
4690 #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET			6556
4691 #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET			6557
4692 #define PSWRQ2_REG_VF_BASE_RT_OFFSET				6558
4693 #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET			6559
4694 #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET			6560
4695 #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET			6561
4696 #define PSWRQ2_REG_TGSRC_FIRST_ILT_RT_OFFSET			6562
4697 #define PSWRQ2_REG_RGSRC_FIRST_ILT_RT_OFFSET			6563
4698 #define PSWRQ2_REG_TGSRC_LAST_ILT_RT_OFFSET			6564
4699 #define PSWRQ2_REG_RGSRC_LAST_ILT_RT_OFFSET			6565
4700 #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET				6566
4701 #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE				26414
4702 #define PGLUE_REG_B_VF_BASE_RT_OFFSET				32980
4703 #define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET		32981
4704 #define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET			32982
4705 #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET			32983
4706 #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET			32984
4707 #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET			32985
4708 #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET			32986
4709 #define TM_REG_VF_ENABLE_CONN_RT_OFFSET				32987
4710 #define TM_REG_PF_ENABLE_CONN_RT_OFFSET				32988
4711 #define TM_REG_PF_ENABLE_TASK_RT_OFFSET				32989
4712 #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET		32990
4713 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET		32991
4714 #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET			32992
4715 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE				416
4716 #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET			33408
4717 #define TM_REG_CONFIG_TASK_MEM_RT_SIZE				608
4718 #define QM_REG_MAXPQSIZE_0_RT_OFFSET				34016
4719 #define QM_REG_MAXPQSIZE_1_RT_OFFSET				34017
4720 #define QM_REG_MAXPQSIZE_2_RT_OFFSET				34018
4721 #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET			34019
4722 #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET			34020
4723 #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET			34021
4724 #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET			34022
4725 #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET			34023
4726 #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET			34024
4727 #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET			34025
4728 #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET			34026
4729 #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET			34027
4730 #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET			34028
4731 #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET			34029
4732 #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET			34030
4733 #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET			34031
4734 #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET			34032
4735 #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET			34033
4736 #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET			34034
4737 #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET			34035
4738 #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET			34036
4739 #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET			34037
4740 #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET			34038
4741 #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET			34039
4742 #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET			34040
4743 #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET			34041
4744 #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET			34042
4745 #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET			34043
4746 #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET			34044
4747 #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET			34045
4748 #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET			34046
4749 #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET			34047
4750 #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET			34048
4751 #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET			34049
4752 #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET			34050
4753 #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET			34051
4754 #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET			34052
4755 #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET			34053
4756 #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET			34054
4757 #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET			34055
4758 #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET			34056
4759 #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET			34057
4760 #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET			34058
4761 #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET			34059
4762 #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET			34060
4763 #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET			34061
4764 #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET			34062
4765 #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET			34063
4766 #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET			34064
4767 #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET			34065
4768 #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET			34066
4769 #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET			34067
4770 #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET			34068
4771 #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET			34069
4772 #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET			34070
4773 #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET			34071
4774 #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET			34072
4775 #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET			34073
4776 #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET			34074
4777 #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET			34075
4778 #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET			34076
4779 #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET			34077
4780 #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET			34078
4781 #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET			34079
4782 #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET			34080
4783 #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET			34081
4784 #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET			34082
4785 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET			34083
4786 #define QM_REG_BASEADDROTHERPQ_RT_SIZE				128
4787 #define QM_REG_PTRTBLOTHER_RT_OFFSET				34211
4788 #define QM_REG_PTRTBLOTHER_RT_SIZE				256
4789 #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET			34467
4790 #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET			34468
4791 #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET			34469
4792 #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET			34470
4793 #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET			34471
4794 #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET			34472
4795 #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET			34473
4796 #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET			34474
4797 #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET			34475
4798 #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET			34476
4799 #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET			34477
4800 #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET			34478
4801 #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET			34479
4802 #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET			34480
4803 #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET			34481
4804 #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET			34482
4805 #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET			34483
4806 #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET			34484
4807 #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET			34485
4808 #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET			34486
4809 #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET			34487
4810 #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET			34488
4811 #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET			34489
4812 #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET			34490
4813 #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET			34491
4814 #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET			34492
4815 #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET			34493
4816 #define QM_REG_PQTX2PF_0_RT_OFFSET				34494
4817 #define QM_REG_PQTX2PF_1_RT_OFFSET				34495
4818 #define QM_REG_PQTX2PF_2_RT_OFFSET				34496
4819 #define QM_REG_PQTX2PF_3_RT_OFFSET				34497
4820 #define QM_REG_PQTX2PF_4_RT_OFFSET				34498
4821 #define QM_REG_PQTX2PF_5_RT_OFFSET				34499
4822 #define QM_REG_PQTX2PF_6_RT_OFFSET				34500
4823 #define QM_REG_PQTX2PF_7_RT_OFFSET				34501
4824 #define QM_REG_PQTX2PF_8_RT_OFFSET				34502
4825 #define QM_REG_PQTX2PF_9_RT_OFFSET				34503
4826 #define QM_REG_PQTX2PF_10_RT_OFFSET				34504
4827 #define QM_REG_PQTX2PF_11_RT_OFFSET				34505
4828 #define QM_REG_PQTX2PF_12_RT_OFFSET				34506
4829 #define QM_REG_PQTX2PF_13_RT_OFFSET				34507
4830 #define QM_REG_PQTX2PF_14_RT_OFFSET				34508
4831 #define QM_REG_PQTX2PF_15_RT_OFFSET				34509
4832 #define QM_REG_PQTX2PF_16_RT_OFFSET				34510
4833 #define QM_REG_PQTX2PF_17_RT_OFFSET				34511
4834 #define QM_REG_PQTX2PF_18_RT_OFFSET				34512
4835 #define QM_REG_PQTX2PF_19_RT_OFFSET				34513
4836 #define QM_REG_PQTX2PF_20_RT_OFFSET				34514
4837 #define QM_REG_PQTX2PF_21_RT_OFFSET				34515
4838 #define QM_REG_PQTX2PF_22_RT_OFFSET				34516
4839 #define QM_REG_PQTX2PF_23_RT_OFFSET				34517
4840 #define QM_REG_PQTX2PF_24_RT_OFFSET				34518
4841 #define QM_REG_PQTX2PF_25_RT_OFFSET				34519
4842 #define QM_REG_PQTX2PF_26_RT_OFFSET				34520
4843 #define QM_REG_PQTX2PF_27_RT_OFFSET				34521
4844 #define QM_REG_PQTX2PF_28_RT_OFFSET				34522
4845 #define QM_REG_PQTX2PF_29_RT_OFFSET				34523
4846 #define QM_REG_PQTX2PF_30_RT_OFFSET				34524
4847 #define QM_REG_PQTX2PF_31_RT_OFFSET				34525
4848 #define QM_REG_PQTX2PF_32_RT_OFFSET				34526
4849 #define QM_REG_PQTX2PF_33_RT_OFFSET				34527
4850 #define QM_REG_PQTX2PF_34_RT_OFFSET				34528
4851 #define QM_REG_PQTX2PF_35_RT_OFFSET				34529
4852 #define QM_REG_PQTX2PF_36_RT_OFFSET				34530
4853 #define QM_REG_PQTX2PF_37_RT_OFFSET				34531
4854 #define QM_REG_PQTX2PF_38_RT_OFFSET				34532
4855 #define QM_REG_PQTX2PF_39_RT_OFFSET				34533
4856 #define QM_REG_PQTX2PF_40_RT_OFFSET				34534
4857 #define QM_REG_PQTX2PF_41_RT_OFFSET				34535
4858 #define QM_REG_PQTX2PF_42_RT_OFFSET				34536
4859 #define QM_REG_PQTX2PF_43_RT_OFFSET				34537
4860 #define QM_REG_PQTX2PF_44_RT_OFFSET				34538
4861 #define QM_REG_PQTX2PF_45_RT_OFFSET				34539
4862 #define QM_REG_PQTX2PF_46_RT_OFFSET				34540
4863 #define QM_REG_PQTX2PF_47_RT_OFFSET				34541
4864 #define QM_REG_PQTX2PF_48_RT_OFFSET				34542
4865 #define QM_REG_PQTX2PF_49_RT_OFFSET				34543
4866 #define QM_REG_PQTX2PF_50_RT_OFFSET				34544
4867 #define QM_REG_PQTX2PF_51_RT_OFFSET				34545
4868 #define QM_REG_PQTX2PF_52_RT_OFFSET				34546
4869 #define QM_REG_PQTX2PF_53_RT_OFFSET				34547
4870 #define QM_REG_PQTX2PF_54_RT_OFFSET				34548
4871 #define QM_REG_PQTX2PF_55_RT_OFFSET				34549
4872 #define QM_REG_PQTX2PF_56_RT_OFFSET				34550
4873 #define QM_REG_PQTX2PF_57_RT_OFFSET				34551
4874 #define QM_REG_PQTX2PF_58_RT_OFFSET				34552
4875 #define QM_REG_PQTX2PF_59_RT_OFFSET				34553
4876 #define QM_REG_PQTX2PF_60_RT_OFFSET				34554
4877 #define QM_REG_PQTX2PF_61_RT_OFFSET				34555
4878 #define QM_REG_PQTX2PF_62_RT_OFFSET				34556
4879 #define QM_REG_PQTX2PF_63_RT_OFFSET				34557
4880 #define QM_REG_PQOTHER2PF_0_RT_OFFSET				34558
4881 #define QM_REG_PQOTHER2PF_1_RT_OFFSET				34559
4882 #define QM_REG_PQOTHER2PF_2_RT_OFFSET				34560
4883 #define QM_REG_PQOTHER2PF_3_RT_OFFSET				34561
4884 #define QM_REG_PQOTHER2PF_4_RT_OFFSET				34562
4885 #define QM_REG_PQOTHER2PF_5_RT_OFFSET				34563
4886 #define QM_REG_PQOTHER2PF_6_RT_OFFSET				34564
4887 #define QM_REG_PQOTHER2PF_7_RT_OFFSET				34565
4888 #define QM_REG_PQOTHER2PF_8_RT_OFFSET				34566
4889 #define QM_REG_PQOTHER2PF_9_RT_OFFSET				34567
4890 #define QM_REG_PQOTHER2PF_10_RT_OFFSET				34568
4891 #define QM_REG_PQOTHER2PF_11_RT_OFFSET				34569
4892 #define QM_REG_PQOTHER2PF_12_RT_OFFSET				34570
4893 #define QM_REG_PQOTHER2PF_13_RT_OFFSET				34571
4894 #define QM_REG_PQOTHER2PF_14_RT_OFFSET				34572
4895 #define QM_REG_PQOTHER2PF_15_RT_OFFSET				34573
4896 #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET				34574
4897 #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET				34575
4898 #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET			34576
4899 #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET			34577
4900 #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET			34578
4901 #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET			34579
4902 #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET			34580
4903 #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET			34581
4904 #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET			34582
4905 #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET			34583
4906 #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET			34584
4907 #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET			34585
4908 #define QM_REG_RLGLBLINCVAL_RT_OFFSET				34586
4909 #define QM_REG_RLGLBLINCVAL_RT_SIZE				256
4910 #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET			34842
4911 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE				256
4912 #define QM_REG_RLGLBLCRD_RT_OFFSET				35098
4913 #define QM_REG_RLGLBLCRD_RT_SIZE				256
4914 #define QM_REG_RLGLBLENABLE_RT_OFFSET				35354
4915 #define QM_REG_RLPFPERIOD_RT_OFFSET				35355
4916 #define QM_REG_RLPFPERIODTIMER_RT_OFFSET			35356
4917 #define QM_REG_RLPFINCVAL_RT_OFFSET				35357
4918 #define QM_REG_RLPFINCVAL_RT_SIZE				16
4919 #define QM_REG_RLPFUPPERBOUND_RT_OFFSET				35373
4920 #define QM_REG_RLPFUPPERBOUND_RT_SIZE				16
4921 #define QM_REG_RLPFCRD_RT_OFFSET				35389
4922 #define QM_REG_RLPFCRD_RT_SIZE					16
4923 #define QM_REG_RLPFENABLE_RT_OFFSET				35405
4924 #define QM_REG_RLPFVOQENABLE_RT_OFFSET				35406
4925 #define QM_REG_WFQPFWEIGHT_RT_OFFSET				35407
4926 #define QM_REG_WFQPFWEIGHT_RT_SIZE				16
4927 #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET			35423
4928 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE				16
4929 #define QM_REG_WFQPFCRD_RT_OFFSET				35439
4930 #define QM_REG_WFQPFCRD_RT_SIZE					256
4931 #define QM_REG_WFQPFENABLE_RT_OFFSET				35695
4932 #define QM_REG_WFQVPENABLE_RT_OFFSET				35696
4933 #define QM_REG_BASEADDRTXPQ_RT_OFFSET				35697
4934 #define QM_REG_BASEADDRTXPQ_RT_SIZE				512
4935 #define QM_REG_TXPQMAP_RT_OFFSET				36209
4936 #define QM_REG_TXPQMAP_RT_SIZE					512
4937 #define QM_REG_WFQVPWEIGHT_RT_OFFSET				36721
4938 #define QM_REG_WFQVPWEIGHT_RT_SIZE				512
4939 #define QM_REG_WFQVPCRD_RT_OFFSET				37233
4940 #define QM_REG_WFQVPCRD_RT_SIZE					512
4941 #define QM_REG_WFQVPMAP_RT_OFFSET				37745
4942 #define QM_REG_WFQVPMAP_RT_SIZE					512
4943 #define QM_REG_PTRTBLTX_RT_OFFSET				38257
4944 #define QM_REG_PTRTBLTX_RT_SIZE					1024
4945 #define QM_REG_WFQPFCRD_MSB_RT_OFFSET				39281
4946 #define QM_REG_WFQPFCRD_MSB_RT_SIZE				320
4947 #define QM_REG_VOQCRDLINE_RT_OFFSET				39601
4948 #define QM_REG_VOQCRDLINE_RT_SIZE				36
4949 #define QM_REG_VOQINITCRDLINE_RT_OFFSET				39637
4950 #define QM_REG_VOQINITCRDLINE_RT_SIZE				36
4951 #define QM_REG_RLPFVOQENABLE_MSB_RT_OFFSET			39673
4952 #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET			39674
4953 #define NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET			39675
4954 #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET			39676
4955 #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET			39677
4956 #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET			39678
4957 #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET			39679
4958 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET		39680
4959 #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET			39681
4960 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE				4
4961 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET			39685
4962 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE			4
4963 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET			39689
4964 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE			32
4965 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET			39721
4966 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE			16
4967 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET			39737
4968 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE			16
4969 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET		39753
4970 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE		16
4971 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET		39769
4972 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE			16
4973 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET				39785
4974 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET                             39786
4975 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE                               8
4976 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_OFFSET                  39794
4977 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_VALUE_RT_SIZE                    1024
4978 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_OFFSET                     40818
4979 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_EN_RT_SIZE                       512
4980 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_OFFSET                   41330
4981 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_MODE_RT_SIZE                     512
4982 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET          41842
4983 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE            512
4984 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_OFFSET                42354
4985 #define NIG_REG_LLH_PF_CLS_FUNC_FILTER_HDR_SEL_RT_SIZE                  512
4986 #define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_OFFSET                        42866
4987 #define NIG_REG_LLH_PF_CLS_FILTERS_MAP_RT_SIZE                          32
4988 #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET                               42898
4989 #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET                               42899
4990 #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET                               42900
4991 #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET                           42901
4992 #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET                           42902
4993 #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET                           42903
4994 #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET                           42904
4995 #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET                        42905
4996 #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET                        42906
4997 #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET                        42907
4998 #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET                        42908
4999 #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET                            42909
5000 #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET                         42910
5001 #define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET                               42911
5002 #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET                          42912
5003 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET                        42913
5004 #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET                           42914
5005 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET                    42915
5006 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET                        42916
5007 #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET                           42917
5008 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET                    42918
5009 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET                        42919
5010 #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET                           42920
5011 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET                    42921
5012 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET                        42922
5013 #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET                           42923
5014 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET                    42924
5015 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET                        42925
5016 #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET                           42926
5017 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET                    42927
5018 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET                        42928
5019 #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET                           42929
5020 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET                    42930
5021 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET                        42931
5022 #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET                           42932
5023 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET                    42933
5024 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET                        42934
5025 #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET                           42935
5026 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET                    42936
5027 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET                        42937
5028 #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET                           42938
5029 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET                    42939
5030 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET                        42940
5031 #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET                           42941
5032 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET                    42942
5033 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET                       42943
5034 #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET                          42944
5035 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET                   42945
5036 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET                       42946
5037 #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET                          42947
5038 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET                   42948
5039 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET                       42949
5040 #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET                          42950
5041 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET                   42951
5042 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET                       42952
5043 #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET                          42953
5044 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET                   42954
5045 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET                       42955
5046 #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET                          42956
5047 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET                   42957
5048 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET                       42958
5049 #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET                          42959
5050 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET                   42960
5051 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET                       42961
5052 #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET                          42962
5053 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET                   42963
5054 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET                       42964
5055 #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET                          42965
5056 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET                   42966
5057 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET                       42967
5058 #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET                          42968
5059 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET                   42969
5060 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET                       42970
5061 #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET                          42971
5062 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET                   42972
5063 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ20_RT_OFFSET                       42973
5064 #define PBF_REG_BTB_GUARANTEED_VOQ20_RT_OFFSET                          42974
5065 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ20_RT_OFFSET                   42975
5066 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ21_RT_OFFSET                       42976
5067 #define PBF_REG_BTB_GUARANTEED_VOQ21_RT_OFFSET                          42977
5068 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ21_RT_OFFSET                   42978
5069 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ22_RT_OFFSET                       42979
5070 #define PBF_REG_BTB_GUARANTEED_VOQ22_RT_OFFSET                          42980
5071 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ22_RT_OFFSET                   42981
5072 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ23_RT_OFFSET                       42982
5073 #define PBF_REG_BTB_GUARANTEED_VOQ23_RT_OFFSET                          42983
5074 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ23_RT_OFFSET                   42984
5075 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ24_RT_OFFSET                       42985
5076 #define PBF_REG_BTB_GUARANTEED_VOQ24_RT_OFFSET                          42986
5077 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ24_RT_OFFSET                   42987
5078 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ25_RT_OFFSET                       42988
5079 #define PBF_REG_BTB_GUARANTEED_VOQ25_RT_OFFSET                          42989
5080 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ25_RT_OFFSET                   42990
5081 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ26_RT_OFFSET                       42991
5082 #define PBF_REG_BTB_GUARANTEED_VOQ26_RT_OFFSET                          42992
5083 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ26_RT_OFFSET                   42993
5084 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ27_RT_OFFSET                       42994
5085 #define PBF_REG_BTB_GUARANTEED_VOQ27_RT_OFFSET                          42995
5086 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ27_RT_OFFSET                   42996
5087 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ28_RT_OFFSET                       42997
5088 #define PBF_REG_BTB_GUARANTEED_VOQ28_RT_OFFSET                          42998
5089 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ28_RT_OFFSET                   42999
5090 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ29_RT_OFFSET                       43000
5091 #define PBF_REG_BTB_GUARANTEED_VOQ29_RT_OFFSET                          43001
5092 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ29_RT_OFFSET                   43002
5093 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ30_RT_OFFSET                       43003
5094 #define PBF_REG_BTB_GUARANTEED_VOQ30_RT_OFFSET                          43004
5095 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ30_RT_OFFSET                   43005
5096 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ31_RT_OFFSET                       43006
5097 #define PBF_REG_BTB_GUARANTEED_VOQ31_RT_OFFSET                          43007
5098 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ31_RT_OFFSET                   43008
5099 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ32_RT_OFFSET                       43009
5100 #define PBF_REG_BTB_GUARANTEED_VOQ32_RT_OFFSET                          43010
5101 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ32_RT_OFFSET                   43011
5102 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ33_RT_OFFSET                       43012
5103 #define PBF_REG_BTB_GUARANTEED_VOQ33_RT_OFFSET                          43013
5104 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ33_RT_OFFSET                   43014
5105 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ34_RT_OFFSET                       43015
5106 #define PBF_REG_BTB_GUARANTEED_VOQ34_RT_OFFSET                          43016
5107 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ34_RT_OFFSET                   43017
5108 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ35_RT_OFFSET                       43018
5109 #define PBF_REG_BTB_GUARANTEED_VOQ35_RT_OFFSET                          43019
5110 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ35_RT_OFFSET                   43020
5111 #define XCM_REG_CON_PHY_Q3_RT_OFFSET                                    43021
5112 
5113 #define RUNTIME_ARRAY_SIZE 43022
5114 
5115 
5116 /* Init Callbacks */
5117 #define DMAE_READY_CB	0
5118 
5119 /* The eth storm context for the Tstorm */
5120 struct tstorm_eth_conn_st_ctx {
5121 	__le32 reserved[4];
5122 };
5123 
5124 /* The eth storm context for the Pstorm */
5125 struct pstorm_eth_conn_st_ctx {
5126 	__le32 reserved[8];
5127 };
5128 
5129 /* The eth storm context for the Xstorm */
5130 struct xstorm_eth_conn_st_ctx {
5131 	__le32 reserved[60];
5132 };
5133 
5134 struct e4_xstorm_eth_conn_ag_ctx {
5135 	u8 reserved0;
5136 	u8 state;
5137 	u8 flags0;
5138 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
5139 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
5140 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK	0x1
5141 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT	1
5142 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK	0x1
5143 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT	2
5144 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
5145 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT	3
5146 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK	0x1
5147 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT	4
5148 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK	0x1
5149 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT	5
5150 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK	0x1
5151 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT	6
5152 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK	0x1
5153 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT	7
5154 		u8 flags1;
5155 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK	0x1
5156 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT	0
5157 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK	0x1
5158 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT	1
5159 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK	0x1
5160 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT	2
5161 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_MASK		0x1
5162 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT		3
5163 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_MASK	0x1
5164 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_SHIFT	4
5165 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_MASK	0x1
5166 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_SHIFT	5
5167 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK	0x1
5168 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT	6
5169 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK	0x1
5170 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT	7
5171 	u8 flags2;
5172 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_MASK	0x3
5173 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT	0
5174 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_MASK	0x3
5175 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT	2
5176 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_MASK	0x3
5177 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT	4
5178 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_MASK	0x3
5179 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT	6
5180 	u8 flags3;
5181 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_MASK	0x3
5182 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT	0
5183 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_MASK	0x3
5184 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT	2
5185 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_MASK	0x3
5186 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT	4
5187 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_MASK	0x3
5188 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT	6
5189 		u8 flags4;
5190 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_MASK	0x3
5191 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT	0
5192 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_MASK	0x3
5193 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT	2
5194 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_MASK	0x3
5195 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT	4
5196 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_MASK	0x3
5197 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT	6
5198 	u8 flags5;
5199 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_MASK	0x3
5200 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT	0
5201 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_MASK	0x3
5202 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT	2
5203 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_MASK	0x3
5204 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT	4
5205 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_MASK	0x3
5206 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT	6
5207 	u8 flags6;
5208 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK		0x3
5209 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT	0
5210 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK		0x3
5211 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT	2
5212 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK			0x3
5213 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT			4
5214 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK		0x3
5215 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT		6
5216 	u8 flags7;
5217 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK		0x3
5218 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT	0
5219 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK	0x3
5220 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT	2
5221 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK	0x3
5222 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT	4
5223 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK		0x1
5224 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT		6
5225 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK		0x1
5226 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT		7
5227 	u8 flags8;
5228 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK	0x1
5229 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT	0
5230 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK	0x1
5231 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT	1
5232 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK	0x1
5233 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT	2
5234 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK	0x1
5235 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT	3
5236 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK	0x1
5237 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT	4
5238 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK	0x1
5239 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT	5
5240 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK	0x1
5241 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT	6
5242 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK	0x1
5243 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT	7
5244 	u8 flags9;
5245 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK			0x1
5246 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT			0
5247 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK			0x1
5248 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT			1
5249 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK			0x1
5250 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT			2
5251 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK			0x1
5252 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT			3
5253 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK			0x1
5254 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT			4
5255 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK			0x1
5256 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT			5
5257 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK	0x1
5258 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT	6
5259 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK	0x1
5260 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT	7
5261 	u8 flags10;
5262 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK			0x1
5263 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT		0
5264 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK		0x1
5265 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT		1
5266 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK		0x1
5267 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT		2
5268 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK		0x1
5269 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT		3
5270 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK		0x1
5271 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT		4
5272 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK	0x1
5273 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT	5
5274 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK		0x1
5275 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT		6
5276 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK		0x1
5277 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT		7
5278 	u8 flags11;
5279 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK	0x1
5280 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT	0
5281 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK	0x1
5282 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT	1
5283 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK	0x1
5284 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT	2
5285 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK		0x1
5286 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT		3
5287 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK		0x1
5288 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT		4
5289 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK		0x1
5290 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT		5
5291 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK	0x1
5292 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT	6
5293 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK		0x1
5294 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT		7
5295 	u8 flags12;
5296 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK		0x1
5297 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT	0
5298 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK		0x1
5299 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT	1
5300 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK	0x1
5301 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT	2
5302 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK	0x1
5303 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT	3
5304 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK		0x1
5305 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT	4
5306 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK		0x1
5307 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT	5
5308 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK		0x1
5309 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT	6
5310 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK		0x1
5311 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT	7
5312 	u8 flags13;
5313 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK		0x1
5314 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT	0
5315 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK		0x1
5316 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT	1
5317 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK	0x1
5318 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT	2
5319 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK	0x1
5320 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT	3
5321 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK	0x1
5322 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT	4
5323 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK	0x1
5324 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT	5
5325 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK	0x1
5326 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT	6
5327 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK	0x1
5328 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT	7
5329 	u8 flags14;
5330 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK		0x1
5331 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT	0
5332 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK	0x1
5333 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT	1
5334 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK	0x1
5335 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT	2
5336 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK	0x1
5337 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT	3
5338 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK		0x1
5339 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT		4
5340 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK		0x1
5341 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT	5
5342 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK		0x3
5343 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT		6
5344 	u8 edpm_event_id;
5345 	__le16 physical_q0;
5346 	__le16 e5_reserved1;
5347 	__le16 edpm_num_bds;
5348 	__le16 tx_bd_cons;
5349 	__le16 tx_bd_prod;
5350 	__le16 updated_qm_pq_id;
5351 	__le16 conn_dpi;
5352 	u8 byte3;
5353 	u8 byte4;
5354 	u8 byte5;
5355 	u8 byte6;
5356 	__le32 reg0;
5357 	__le32 reg1;
5358 	__le32 reg2;
5359 	__le32 reg3;
5360 	__le32 reg4;
5361 	__le32 reg5;
5362 	__le32 reg6;
5363 	__le16 word7;
5364 	__le16 word8;
5365 	__le16 word9;
5366 	__le16 word10;
5367 	__le32 reg7;
5368 	__le32 reg8;
5369 	__le32 reg9;
5370 	u8 byte7;
5371 	u8 byte8;
5372 	u8 byte9;
5373 	u8 byte10;
5374 	u8 byte11;
5375 	u8 byte12;
5376 	u8 byte13;
5377 	u8 byte14;
5378 	u8 byte15;
5379 	u8 e5_reserved;
5380 	__le16 word11;
5381 	__le32 reg10;
5382 	__le32 reg11;
5383 	__le32 reg12;
5384 	__le32 reg13;
5385 	__le32 reg14;
5386 	__le32 reg15;
5387 	__le32 reg16;
5388 	__le32 reg17;
5389 	__le32 reg18;
5390 	__le32 reg19;
5391 	__le16 word12;
5392 	__le16 word13;
5393 	__le16 word14;
5394 	__le16 word15;
5395 };
5396 
5397 /* The eth storm context for the Ystorm */
5398 struct ystorm_eth_conn_st_ctx {
5399 	__le32 reserved[8];
5400 };
5401 
5402 struct e4_ystorm_eth_conn_ag_ctx {
5403 	u8 byte0;
5404 	u8 state;
5405 	u8 flags0;
5406 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_MASK			0x1
5407 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT			0
5408 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_MASK			0x1
5409 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT			1
5410 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK	0x3
5411 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT	2
5412 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK		0x3
5413 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT	4
5414 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_MASK			0x3
5415 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT			6
5416 	u8 flags1;
5417 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK	0x1
5418 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT	0
5419 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK	0x1
5420 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT	1
5421 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK			0x1
5422 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT			2
5423 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK			0x1
5424 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT			3
5425 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK			0x1
5426 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT			4
5427 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK			0x1
5428 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT			5
5429 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK			0x1
5430 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT			6
5431 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK			0x1
5432 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT			7
5433 	u8 tx_q0_int_coallecing_timeset;
5434 	u8 byte3;
5435 	__le16 word0;
5436 	__le32 terminate_spqe;
5437 	__le32 reg1;
5438 	__le16 tx_bd_cons_upd;
5439 	__le16 word2;
5440 	__le16 word3;
5441 	__le16 word4;
5442 	__le32 reg2;
5443 	__le32 reg3;
5444 };
5445 
5446 struct e4_tstorm_eth_conn_ag_ctx {
5447 	u8 byte0;
5448 	u8 byte1;
5449 	u8 flags0;
5450 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_MASK	0x1
5451 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT	0
5452 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_MASK	0x1
5453 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT	1
5454 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_MASK	0x1
5455 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT	2
5456 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_MASK	0x1
5457 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT	3
5458 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_MASK	0x1
5459 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT	4
5460 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_MASK	0x1
5461 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT	5
5462 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_MASK	0x3
5463 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT	6
5464 	u8 flags1;
5465 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_MASK	0x3
5466 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT	0
5467 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_MASK	0x3
5468 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT	2
5469 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_MASK	0x3
5470 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT	4
5471 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_MASK	0x3
5472 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT	6
5473 	u8 flags2;
5474 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_MASK	0x3
5475 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT	0
5476 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_MASK	0x3
5477 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT	2
5478 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_MASK	0x3
5479 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT	4
5480 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_MASK	0x3
5481 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT	6
5482 	u8 flags3;
5483 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_MASK	0x3
5484 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT	0
5485 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_MASK	0x3
5486 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT	2
5487 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK	0x1
5488 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT	4
5489 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK	0x1
5490 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT	5
5491 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK	0x1
5492 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT	6
5493 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK	0x1
5494 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT	7
5495 	u8 flags4;
5496 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK	0x1
5497 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT	0
5498 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK	0x1
5499 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT	1
5500 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK	0x1
5501 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT	2
5502 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK	0x1
5503 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT	3
5504 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK	0x1
5505 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT	4
5506 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK	0x1
5507 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT	5
5508 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK	0x1
5509 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT	6
5510 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK	0x1
5511 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT	7
5512 	u8 flags5;
5513 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK		0x1
5514 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT		0
5515 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK		0x1
5516 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT		1
5517 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK		0x1
5518 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT		2
5519 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK		0x1
5520 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT		3
5521 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK		0x1
5522 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT		4
5523 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK		0x1
5524 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT	5
5525 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK		0x1
5526 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT		6
5527 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK		0x1
5528 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT		7
5529 	__le32 reg0;
5530 	__le32 reg1;
5531 	__le32 reg2;
5532 	__le32 reg3;
5533 	__le32 reg4;
5534 	__le32 reg5;
5535 	__le32 reg6;
5536 	__le32 reg7;
5537 	__le32 reg8;
5538 	u8 byte2;
5539 	u8 byte3;
5540 	__le16 rx_bd_cons;
5541 	u8 byte4;
5542 	u8 byte5;
5543 	__le16 rx_bd_prod;
5544 	__le16 word2;
5545 	__le16 word3;
5546 	__le32 reg9;
5547 	__le32 reg10;
5548 };
5549 
5550 struct e4_ustorm_eth_conn_ag_ctx {
5551 	u8 byte0;
5552 	u8 byte1;
5553 	u8 flags0;
5554 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_MASK			0x1
5555 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT			0
5556 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_MASK			0x1
5557 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT			1
5558 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK	0x3
5559 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT	2
5560 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK	0x3
5561 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT	4
5562 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_MASK			0x3
5563 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_SHIFT			6
5564 	u8 flags1;
5565 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_MASK			0x3
5566 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_SHIFT			0
5567 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK		0x3
5568 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT		2
5569 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK		0x3
5570 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT		4
5571 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK	0x3
5572 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT	6
5573 	u8 flags2;
5574 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK	0x1
5575 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT	0
5576 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK	0x1
5577 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT	1
5578 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_MASK			0x1
5579 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT			2
5580 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_MASK			0x1
5581 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT			3
5582 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK		0x1
5583 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT		4
5584 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK		0x1
5585 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT		5
5586 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK	0x1
5587 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT	6
5588 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK			0x1
5589 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT			7
5590 	u8 flags3;
5591 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK	0x1
5592 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT	0
5593 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK	0x1
5594 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT	1
5595 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK	0x1
5596 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT	2
5597 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK	0x1
5598 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT	3
5599 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK	0x1
5600 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT	4
5601 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK	0x1
5602 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT	5
5603 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK	0x1
5604 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT	6
5605 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK	0x1
5606 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT	7
5607 	u8 byte2;
5608 	u8 byte3;
5609 	__le16 word0;
5610 	__le16 tx_bd_cons;
5611 	__le32 reg0;
5612 	__le32 reg1;
5613 	__le32 reg2;
5614 	__le32 tx_int_coallecing_timeset;
5615 	__le16 tx_drv_bd_cons;
5616 	__le16 rx_drv_cqe_cons;
5617 };
5618 
5619 /* The eth storm context for the Ustorm */
5620 struct ustorm_eth_conn_st_ctx {
5621 	__le32 reserved[40];
5622 };
5623 
5624 /* The eth storm context for the Mstorm */
5625 struct mstorm_eth_conn_st_ctx {
5626 	__le32 reserved[8];
5627 };
5628 
5629 /* eth connection context */
5630 struct e4_eth_conn_context {
5631 	struct tstorm_eth_conn_st_ctx tstorm_st_context;
5632 	struct regpair tstorm_st_padding[2];
5633 	struct pstorm_eth_conn_st_ctx pstorm_st_context;
5634 	struct xstorm_eth_conn_st_ctx xstorm_st_context;
5635 	struct e4_xstorm_eth_conn_ag_ctx xstorm_ag_context;
5636 	struct ystorm_eth_conn_st_ctx ystorm_st_context;
5637 	struct e4_ystorm_eth_conn_ag_ctx ystorm_ag_context;
5638 	struct e4_tstorm_eth_conn_ag_ctx tstorm_ag_context;
5639 	struct e4_ustorm_eth_conn_ag_ctx ustorm_ag_context;
5640 	struct ustorm_eth_conn_st_ctx ustorm_st_context;
5641 	struct mstorm_eth_conn_st_ctx mstorm_st_context;
5642 };
5643 
5644 /* Ethernet filter types: mac/vlan/pair */
5645 enum eth_error_code {
5646 	ETH_OK = 0x00,
5647 	ETH_FILTERS_MAC_ADD_FAIL_FULL,
5648 	ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2,
5649 	ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2,
5650 	ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2,
5651 	ETH_FILTERS_MAC_DEL_FAIL_NOF,
5652 	ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2,
5653 	ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2,
5654 	ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC,
5655 	ETH_FILTERS_VLAN_ADD_FAIL_FULL,
5656 	ETH_FILTERS_VLAN_ADD_FAIL_DUP,
5657 	ETH_FILTERS_VLAN_DEL_FAIL_NOF,
5658 	ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1,
5659 	ETH_FILTERS_PAIR_ADD_FAIL_DUP,
5660 	ETH_FILTERS_PAIR_ADD_FAIL_FULL,
5661 	ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC,
5662 	ETH_FILTERS_PAIR_DEL_FAIL_NOF,
5663 	ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1,
5664 	ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC,
5665 	ETH_FILTERS_VNI_ADD_FAIL_FULL,
5666 	ETH_FILTERS_VNI_ADD_FAIL_DUP,
5667 	ETH_FILTERS_GFT_UPDATE_FAIL,
5668 	MAX_ETH_ERROR_CODE
5669 };
5670 
5671 /* Opcodes for the event ring */
5672 enum eth_event_opcode {
5673 	ETH_EVENT_UNUSED,
5674 	ETH_EVENT_VPORT_START,
5675 	ETH_EVENT_VPORT_UPDATE,
5676 	ETH_EVENT_VPORT_STOP,
5677 	ETH_EVENT_TX_QUEUE_START,
5678 	ETH_EVENT_TX_QUEUE_STOP,
5679 	ETH_EVENT_RX_QUEUE_START,
5680 	ETH_EVENT_RX_QUEUE_UPDATE,
5681 	ETH_EVENT_RX_QUEUE_STOP,
5682 	ETH_EVENT_FILTERS_UPDATE,
5683 	ETH_EVENT_RX_ADD_OPENFLOW_FILTER,
5684 	ETH_EVENT_RX_DELETE_OPENFLOW_FILTER,
5685 	ETH_EVENT_RX_CREATE_OPENFLOW_ACTION,
5686 	ETH_EVENT_RX_ADD_UDP_FILTER,
5687 	ETH_EVENT_RX_DELETE_UDP_FILTER,
5688 	ETH_EVENT_RX_CREATE_GFT_ACTION,
5689 	ETH_EVENT_RX_GFT_UPDATE_FILTER,
5690 	ETH_EVENT_TX_QUEUE_UPDATE,
5691 	MAX_ETH_EVENT_OPCODE
5692 };
5693 
5694 /* Classify rule types in E2/E3 */
5695 enum eth_filter_action {
5696 	ETH_FILTER_ACTION_UNUSED,
5697 	ETH_FILTER_ACTION_REMOVE,
5698 	ETH_FILTER_ACTION_ADD,
5699 	ETH_FILTER_ACTION_REMOVE_ALL,
5700 	MAX_ETH_FILTER_ACTION
5701 };
5702 
5703 /* Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$ */
5704 struct eth_filter_cmd {
5705 	u8 type;
5706 	u8 vport_id;
5707 	u8 action;
5708 	u8 reserved0;
5709 	__le32 vni;
5710 	__le16 mac_lsb;
5711 	__le16 mac_mid;
5712 	__le16 mac_msb;
5713 	__le16 vlan_id;
5714 };
5715 
5716 /*	$$KEEP_ENDIANNESS$$ */
5717 struct eth_filter_cmd_header {
5718 	u8 rx;
5719 	u8 tx;
5720 	u8 cmd_cnt;
5721 	u8 assert_on_error;
5722 	u8 reserved1[4];
5723 };
5724 
5725 /* Ethernet filter types: mac/vlan/pair */
5726 enum eth_filter_type {
5727 	ETH_FILTER_TYPE_UNUSED,
5728 	ETH_FILTER_TYPE_MAC,
5729 	ETH_FILTER_TYPE_VLAN,
5730 	ETH_FILTER_TYPE_PAIR,
5731 	ETH_FILTER_TYPE_INNER_MAC,
5732 	ETH_FILTER_TYPE_INNER_VLAN,
5733 	ETH_FILTER_TYPE_INNER_PAIR,
5734 	ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR,
5735 	ETH_FILTER_TYPE_MAC_VNI_PAIR,
5736 	ETH_FILTER_TYPE_VNI,
5737 	MAX_ETH_FILTER_TYPE
5738 };
5739 
5740 /* inner to inner vlan priority translation configurations */
5741 struct eth_in_to_in_pri_map_cfg {
5742 	u8 inner_vlan_pri_remap_en;
5743 	u8 reserved[7];
5744 	u8 non_rdma_in_to_in_pri_map[8];
5745 	u8 rdma_in_to_in_pri_map[8];
5746 };
5747 
5748 /* Eth IPv4 Fragment Type */
5749 enum eth_ipv4_frag_type {
5750 	ETH_IPV4_NOT_FRAG,
5751 	ETH_IPV4_FIRST_FRAG,
5752 	ETH_IPV4_NON_FIRST_FRAG,
5753 	MAX_ETH_IPV4_FRAG_TYPE
5754 };
5755 
5756 /* eth IPv4 Fragment Type */
5757 enum eth_ip_type {
5758 	ETH_IPV4,
5759 	ETH_IPV6,
5760 	MAX_ETH_IP_TYPE
5761 };
5762 
5763 /* Ethernet Ramrod Command IDs */
5764 enum eth_ramrod_cmd_id {
5765 	ETH_RAMROD_UNUSED,
5766 	ETH_RAMROD_VPORT_START,
5767 	ETH_RAMROD_VPORT_UPDATE,
5768 	ETH_RAMROD_VPORT_STOP,
5769 	ETH_RAMROD_RX_QUEUE_START,
5770 	ETH_RAMROD_RX_QUEUE_STOP,
5771 	ETH_RAMROD_TX_QUEUE_START,
5772 	ETH_RAMROD_TX_QUEUE_STOP,
5773 	ETH_RAMROD_FILTERS_UPDATE,
5774 	ETH_RAMROD_RX_QUEUE_UPDATE,
5775 	ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION,
5776 	ETH_RAMROD_RX_ADD_OPENFLOW_FILTER,
5777 	ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER,
5778 	ETH_RAMROD_RX_ADD_UDP_FILTER,
5779 	ETH_RAMROD_RX_DELETE_UDP_FILTER,
5780 	ETH_RAMROD_RX_CREATE_GFT_ACTION,
5781 	ETH_RAMROD_GFT_UPDATE_FILTER,
5782 	ETH_RAMROD_TX_QUEUE_UPDATE,
5783 	MAX_ETH_RAMROD_CMD_ID
5784 };
5785 
5786 /* Return code from eth sp ramrods */
5787 struct eth_return_code {
5788 	u8 value;
5789 #define ETH_RETURN_CODE_ERR_CODE_MASK	0x1F
5790 #define ETH_RETURN_CODE_ERR_CODE_SHIFT	0
5791 #define ETH_RETURN_CODE_RESERVED_MASK	0x3
5792 #define ETH_RETURN_CODE_RESERVED_SHIFT	5
5793 #define ETH_RETURN_CODE_RX_TX_MASK	0x1
5794 #define ETH_RETURN_CODE_RX_TX_SHIFT	7
5795 };
5796 
5797 /* What to do in case an error occurs */
5798 enum eth_tx_err {
5799 	ETH_TX_ERR_DROP,
5800 	ETH_TX_ERR_ASSERT_MALICIOUS,
5801 	MAX_ETH_TX_ERR
5802 };
5803 
5804 /* Array of the different error type behaviors */
5805 struct eth_tx_err_vals {
5806 	__le16 values;
5807 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK			0x1
5808 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT			0
5809 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK			0x1
5810 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT			1
5811 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK			0x1
5812 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT			2
5813 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK		0x1
5814 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT		3
5815 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK	0x1
5816 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT	4
5817 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK			0x1
5818 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT			5
5819 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK		0x1
5820 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT		6
5821 #define ETH_TX_ERR_VALS_RESERVED_MASK				0x1FF
5822 #define ETH_TX_ERR_VALS_RESERVED_SHIFT				7
5823 };
5824 
5825 /* vport rss configuration data */
5826 struct eth_vport_rss_config {
5827 	__le16 capabilities;
5828 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK		0x1
5829 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT		0
5830 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK		0x1
5831 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT		1
5832 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK		0x1
5833 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT		2
5834 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK		0x1
5835 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT		3
5836 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK		0x1
5837 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT		4
5838 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK		0x1
5839 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT		5
5840 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK		0x1
5841 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT	6
5842 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK			0x1FF
5843 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT			7
5844 	u8 rss_id;
5845 	u8 rss_mode;
5846 	u8 update_rss_key;
5847 	u8 update_rss_ind_table;
5848 	u8 update_rss_capabilities;
5849 	u8 tbl_size;
5850 	__le32 reserved2[2];
5851 	__le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
5852 
5853 	__le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
5854 	__le32 reserved3[2];
5855 };
5856 
5857 /* eth vport RSS mode */
5858 enum eth_vport_rss_mode {
5859 	ETH_VPORT_RSS_MODE_DISABLED,
5860 	ETH_VPORT_RSS_MODE_REGULAR,
5861 	MAX_ETH_VPORT_RSS_MODE
5862 };
5863 
5864 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
5865 struct eth_vport_rx_mode {
5866 	__le16 state;
5867 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK		0x1
5868 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT		0
5869 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK		0x1
5870 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT	1
5871 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK	0x1
5872 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT	2
5873 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK		0x1
5874 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT		3
5875 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK		0x1
5876 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT	4
5877 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK		0x1
5878 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT	5
5879 #define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_MASK		0x1
5880 #define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_SHIFT		6
5881 #define ETH_VPORT_RX_MODE_RESERVED1_MASK		0x1FF
5882 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT		7
5883 };
5884 
5885 /* Command for setting tpa parameters */
5886 struct eth_vport_tpa_param {
5887 	u8 tpa_ipv4_en_flg;
5888 	u8 tpa_ipv6_en_flg;
5889 	u8 tpa_ipv4_tunn_en_flg;
5890 	u8 tpa_ipv6_tunn_en_flg;
5891 	u8 tpa_pkt_split_flg;
5892 	u8 tpa_hdr_data_split_flg;
5893 	u8 tpa_gro_consistent_flg;
5894 
5895 	u8 tpa_max_aggs_num;
5896 
5897 	__le16 tpa_max_size;
5898 	__le16 tpa_min_size_to_start;
5899 
5900 	__le16 tpa_min_size_to_cont;
5901 	u8 max_buff_num;
5902 	u8 reserved;
5903 };
5904 
5905 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
5906 struct eth_vport_tx_mode {
5907 	__le16 state;
5908 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK		0x1
5909 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT		0
5910 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK		0x1
5911 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT	1
5912 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK		0x1
5913 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT		2
5914 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK		0x1
5915 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT	3
5916 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK		0x1
5917 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT	4
5918 #define ETH_VPORT_TX_MODE_RESERVED1_MASK		0x7FF
5919 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT		5
5920 };
5921 
5922 /* GFT filter update action type */
5923 enum gft_filter_update_action {
5924 	GFT_ADD_FILTER,
5925 	GFT_DELETE_FILTER,
5926 	MAX_GFT_FILTER_UPDATE_ACTION
5927 };
5928 
5929 /* Ramrod data for rx add openflow filter */
5930 struct rx_add_openflow_filter_data {
5931 	__le16 action_icid;
5932 	u8 priority;
5933 	u8 reserved0;
5934 	__le32 tenant_id;
5935 	__le16 dst_mac_hi;
5936 	__le16 dst_mac_mid;
5937 	__le16 dst_mac_lo;
5938 	__le16 src_mac_hi;
5939 	__le16 src_mac_mid;
5940 	__le16 src_mac_lo;
5941 	__le16 vlan_id;
5942 	__le16 l2_eth_type;
5943 	u8 ipv4_dscp;
5944 	u8 ipv4_frag_type;
5945 	u8 ipv4_over_ip;
5946 	u8 tenant_id_exists;
5947 	__le32 ipv4_dst_addr;
5948 	__le32 ipv4_src_addr;
5949 	__le16 l4_dst_port;
5950 	__le16 l4_src_port;
5951 };
5952 
5953 /* Ramrod data for rx create gft action */
5954 struct rx_create_gft_action_data {
5955 	u8 vport_id;
5956 	u8 reserved[7];
5957 };
5958 
5959 /* Ramrod data for rx create openflow action */
5960 struct rx_create_openflow_action_data {
5961 	u8 vport_id;
5962 	u8 reserved[7];
5963 };
5964 
5965 /* Ramrod data for rx queue start ramrod */
5966 struct rx_queue_start_ramrod_data {
5967 	__le16 rx_queue_id;
5968 	__le16 num_of_pbl_pages;
5969 	__le16 bd_max_bytes;
5970 	__le16 sb_id;
5971 	u8 sb_index;
5972 	u8 vport_id;
5973 	u8 default_rss_queue_flg;
5974 	u8 complete_cqe_flg;
5975 	u8 complete_event_flg;
5976 	u8 stats_counter_id;
5977 	u8 pin_context;
5978 	u8 pxp_tph_valid_bd;
5979 	u8 pxp_tph_valid_pkt;
5980 	u8 pxp_st_hint;
5981 
5982 	__le16 pxp_st_index;
5983 	u8 pmd_mode;
5984 
5985 	u8 notify_en;
5986 	u8 toggle_val;
5987 
5988 	u8 vf_rx_prod_index;
5989 	u8 vf_rx_prod_use_zone_a;
5990 	u8 reserved[5];
5991 	__le16 reserved1;
5992 	struct regpair cqe_pbl_addr;
5993 	struct regpair bd_base;
5994 	struct regpair reserved2;
5995 };
5996 
5997 /* Ramrod data for rx queue stop ramrod */
5998 struct rx_queue_stop_ramrod_data {
5999 	__le16 rx_queue_id;
6000 	u8 complete_cqe_flg;
6001 	u8 complete_event_flg;
6002 	u8 vport_id;
6003 	u8 reserved[3];
6004 };
6005 
6006 /* Ramrod data for rx queue update ramrod */
6007 struct rx_queue_update_ramrod_data {
6008 	__le16 rx_queue_id;
6009 	u8 complete_cqe_flg;
6010 	u8 complete_event_flg;
6011 	u8 vport_id;
6012 	u8 set_default_rss_queue;
6013 	u8 reserved[3];
6014 	u8 reserved1;
6015 	u8 reserved2;
6016 	u8 reserved3;
6017 	__le16 reserved4;
6018 	__le16 reserved5;
6019 	struct regpair reserved6;
6020 };
6021 
6022 /* Ramrod data for rx Add UDP Filter */
6023 struct rx_udp_filter_data {
6024 	__le16 action_icid;
6025 	__le16 vlan_id;
6026 	u8 ip_type;
6027 	u8 tenant_id_exists;
6028 	__le16 reserved1;
6029 	__le32 ip_dst_addr[4];
6030 	__le32 ip_src_addr[4];
6031 	__le16 udp_dst_port;
6032 	__le16 udp_src_port;
6033 	__le32 tenant_id;
6034 };
6035 
6036 /* Add or delete GFT filter - filter is packet header of type of packet wished
6037  * to pass certain FW flow.
6038  */
6039 struct rx_update_gft_filter_data {
6040 	struct regpair pkt_hdr_addr;
6041 	__le16 pkt_hdr_length;
6042 	__le16 action_icid;
6043 	__le16 rx_qid;
6044 	__le16 flow_id;
6045 	__le16 vport_id;
6046 	u8 action_icid_valid;
6047 	u8 rx_qid_valid;
6048 	u8 flow_id_valid;
6049 	u8 filter_action;
6050 	u8 assert_on_error;
6051 	u8 inner_vlan_removal_en;
6052 };
6053 
6054 /* Ramrod data for rx queue start ramrod */
6055 struct tx_queue_start_ramrod_data {
6056 	__le16 sb_id;
6057 	u8 sb_index;
6058 	u8 vport_id;
6059 	u8 reserved0;
6060 	u8 stats_counter_id;
6061 	__le16 qm_pq_id;
6062 	u8 flags;
6063 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK	0x1
6064 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT	0
6065 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK	0x1
6066 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT	1
6067 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK	0x1
6068 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT	2
6069 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK		0x1
6070 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT		3
6071 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK		0x1
6072 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT		4
6073 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK		0x1
6074 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT		5
6075 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK		0x3
6076 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT		6
6077 	u8 pxp_st_hint;
6078 	u8 pxp_tph_valid_bd;
6079 	u8 pxp_tph_valid_pkt;
6080 	__le16 pxp_st_index;
6081 	__le16 comp_agg_size;
6082 	__le16 queue_zone_id;
6083 	__le16 reserved2;
6084 	__le16 pbl_size;
6085 	__le16 tx_queue_id;
6086 	__le16 same_as_last_id;
6087 	__le16 reserved[3];
6088 	struct regpair pbl_base_addr;
6089 	struct regpair bd_cons_address;
6090 };
6091 
6092 /* Ramrod data for tx queue stop ramrod */
6093 struct tx_queue_stop_ramrod_data {
6094 	__le16 reserved[4];
6095 };
6096 
6097 /* Ramrod data for tx queue update ramrod */
6098 struct tx_queue_update_ramrod_data {
6099 	__le16 update_qm_pq_id_flg;
6100 	__le16 qm_pq_id;
6101 	__le32 reserved0;
6102 	struct regpair reserved1[5];
6103 };
6104 
6105 /* Inner to Inner VLAN priority map update mode */
6106 enum update_in_to_in_pri_map_mode_enum {
6107 	ETH_IN_TO_IN_PRI_MAP_UPDATE_DISABLED,
6108 	ETH_IN_TO_IN_PRI_MAP_UPDATE_NON_RDMA_TBL,
6109 	ETH_IN_TO_IN_PRI_MAP_UPDATE_RDMA_TBL,
6110 	MAX_UPDATE_IN_TO_IN_PRI_MAP_MODE_ENUM
6111 };
6112 
6113 /* Ramrod data for vport update ramrod */
6114 struct vport_filter_update_ramrod_data {
6115 	struct eth_filter_cmd_header filter_cmd_hdr;
6116 	struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT];
6117 };
6118 
6119 /* Ramrod data for vport start ramrod */
6120 struct vport_start_ramrod_data {
6121 	u8 vport_id;
6122 	u8 sw_fid;
6123 	__le16 mtu;
6124 	u8 drop_ttl0_en;
6125 	u8 inner_vlan_removal_en;
6126 	struct eth_vport_rx_mode rx_mode;
6127 	struct eth_vport_tx_mode tx_mode;
6128 	struct eth_vport_tpa_param tpa_param;
6129 	__le16 default_vlan;
6130 	u8 tx_switching_en;
6131 	u8 anti_spoofing_en;
6132 
6133 	u8 default_vlan_en;
6134 
6135 	u8 handle_ptp_pkts;
6136 	u8 silent_vlan_removal_en;
6137 	u8 untagged;
6138 	struct eth_tx_err_vals tx_err_behav;
6139 
6140 	u8 zero_placement_offset;
6141 	u8 ctl_frame_mac_check_en;
6142 	u8 ctl_frame_ethtype_check_en;
6143 	u8 wipe_inner_vlan_pri_en;
6144 	struct eth_in_to_in_pri_map_cfg in_to_in_vlan_pri_map_cfg;
6145 };
6146 
6147 /* Ramrod data for vport stop ramrod */
6148 struct vport_stop_ramrod_data {
6149 	u8 vport_id;
6150 	u8 reserved[7];
6151 };
6152 
6153 /* Ramrod data for vport update ramrod */
6154 struct vport_update_ramrod_data_cmn {
6155 	u8 vport_id;
6156 	u8 update_rx_active_flg;
6157 	u8 rx_active_flg;
6158 	u8 update_tx_active_flg;
6159 	u8 tx_active_flg;
6160 	u8 update_rx_mode_flg;
6161 	u8 update_tx_mode_flg;
6162 	u8 update_approx_mcast_flg;
6163 
6164 	u8 update_rss_flg;
6165 	u8 update_inner_vlan_removal_en_flg;
6166 
6167 	u8 inner_vlan_removal_en;
6168 	u8 update_tpa_param_flg;
6169 	u8 update_tpa_en_flg;
6170 	u8 update_tx_switching_en_flg;
6171 
6172 	u8 tx_switching_en;
6173 	u8 update_anti_spoofing_en_flg;
6174 
6175 	u8 anti_spoofing_en;
6176 	u8 update_handle_ptp_pkts;
6177 
6178 	u8 handle_ptp_pkts;
6179 	u8 update_default_vlan_en_flg;
6180 
6181 	u8 default_vlan_en;
6182 
6183 	u8 update_default_vlan_flg;
6184 
6185 	__le16 default_vlan;
6186 	u8 update_accept_any_vlan_flg;
6187 
6188 	u8 accept_any_vlan;
6189 	u8 silent_vlan_removal_en;
6190 	u8 update_mtu_flg;
6191 
6192 	__le16 mtu;
6193 	u8 update_ctl_frame_checks_en_flg;
6194 	u8 ctl_frame_mac_check_en;
6195 	u8 ctl_frame_ethtype_check_en;
6196 	u8 update_in_to_in_pri_map_mode;
6197 	u8 in_to_in_pri_map[8];
6198 	u8 reserved[6];
6199 };
6200 
6201 struct vport_update_ramrod_mcast {
6202 	__le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
6203 };
6204 
6205 /* Ramrod data for vport update ramrod */
6206 struct vport_update_ramrod_data {
6207 	struct vport_update_ramrod_data_cmn common;
6208 
6209 	struct eth_vport_rx_mode rx_mode;
6210 	struct eth_vport_tx_mode tx_mode;
6211 	__le32 reserved[3];
6212 	struct eth_vport_tpa_param tpa_param;
6213 	struct vport_update_ramrod_mcast approx_mcast;
6214 	struct eth_vport_rss_config rss_config;
6215 };
6216 
6217 struct e4_xstorm_eth_conn_ag_ctx_dq_ext_ldpart {
6218 	u8 reserved0;
6219 	u8 state;
6220 	u8 flags0;
6221 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK	0x1
6222 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT	0
6223 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK		0x1
6224 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT		1
6225 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK		0x1
6226 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT		2
6227 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK	0x1
6228 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT	3
6229 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK		0x1
6230 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT		4
6231 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK		0x1
6232 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT		5
6233 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK		0x1
6234 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT		6
6235 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK		0x1
6236 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT		7
6237 	u8 flags1;
6238 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK		0x1
6239 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT		0
6240 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK		0x1
6241 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT		1
6242 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK		0x1
6243 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT		2
6244 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK		0x1
6245 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT		3
6246 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_MASK	0x1
6247 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_SHIFT	4
6248 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_MASK	0x1
6249 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_SHIFT	5
6250 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK	0x1
6251 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT	6
6252 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK	0x1
6253 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT	7
6254 	u8 flags2;
6255 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK	0x3
6256 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT	0
6257 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK	0x3
6258 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT	2
6259 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK	0x3
6260 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT	4
6261 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK	0x3
6262 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT	6
6263 	u8 flags3;
6264 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK	0x3
6265 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT	0
6266 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK	0x3
6267 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT	2
6268 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK	0x3
6269 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT	4
6270 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK	0x3
6271 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT	6
6272 	u8 flags4;
6273 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK	0x3
6274 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT	0
6275 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK	0x3
6276 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT	2
6277 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK	0x3
6278 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT	4
6279 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK	0x3
6280 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT	6
6281 	u8 flags5;
6282 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK	0x3
6283 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT	0
6284 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK	0x3
6285 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT	2
6286 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK	0x3
6287 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT	4
6288 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK	0x3
6289 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT	6
6290 	u8 flags6;
6291 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK	0x3
6292 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT	0
6293 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK	0x3
6294 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT	2
6295 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK		0x3
6296 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT		4
6297 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK	0x3
6298 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT	6
6299 	u8 flags7;
6300 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK		0x3
6301 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT		0
6302 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK		0x3
6303 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT	2
6304 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK		0x3
6305 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT		4
6306 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK		0x1
6307 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT		6
6308 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK		0x1
6309 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT		7
6310 	u8 flags8;
6311 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK	0x1
6312 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT	0
6313 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK	0x1
6314 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT	1
6315 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK	0x1
6316 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT	2
6317 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK	0x1
6318 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT	3
6319 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK	0x1
6320 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT	4
6321 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK	0x1
6322 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT	5
6323 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK	0x1
6324 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT	6
6325 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK	0x1
6326 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT	7
6327 	u8 flags9;
6328 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK			0x1
6329 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT			0
6330 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK			0x1
6331 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT			1
6332 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK			0x1
6333 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT			2
6334 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK			0x1
6335 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT			3
6336 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK			0x1
6337 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT			4
6338 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK			0x1
6339 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT			5
6340 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK	0x1
6341 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT	6
6342 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK	0x1
6343 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT	7
6344 	u8 flags10;
6345 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK			0x1
6346 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT			0
6347 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK		0x1
6348 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT		1
6349 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK		0x1
6350 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT		2
6351 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK			0x1
6352 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT		3
6353 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK		0x1
6354 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT		4
6355 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK	0x1
6356 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT	5
6357 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK			0x1
6358 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT		6
6359 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK			0x1
6360 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT		7
6361 	u8 flags11;
6362 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK		0x1
6363 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT	0
6364 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK		0x1
6365 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT	1
6366 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK	0x1
6367 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT	2
6368 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK		0x1
6369 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT		3
6370 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK		0x1
6371 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT		4
6372 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK		0x1
6373 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT		5
6374 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK	0x1
6375 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT	6
6376 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK		0x1
6377 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT		7
6378 	u8 flags12;
6379 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK		0x1
6380 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT		0
6381 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK		0x1
6382 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT		1
6383 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK	0x1
6384 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT	2
6385 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK	0x1
6386 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT	3
6387 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK		0x1
6388 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT		4
6389 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK		0x1
6390 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT		5
6391 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK		0x1
6392 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT		6
6393 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK		0x1
6394 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT		7
6395 	u8 flags13;
6396 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK		0x1
6397 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT		0
6398 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK		0x1
6399 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT		1
6400 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK	0x1
6401 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT	2
6402 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK	0x1
6403 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT	3
6404 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK	0x1
6405 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT	4
6406 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK	0x1
6407 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT	5
6408 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK	0x1
6409 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT	6
6410 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK	0x1
6411 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT	7
6412 	u8 flags14;
6413 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK		0x1
6414 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT		0
6415 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK		0x1
6416 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT	1
6417 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK	0x1
6418 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT	2
6419 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK	0x1
6420 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT	3
6421 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK		0x1
6422 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT		4
6423 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK		0x1
6424 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT		5
6425 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK			0x3
6426 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT		6
6427 	u8 edpm_event_id;
6428 	__le16 physical_q0;
6429 	__le16 e5_reserved1;
6430 	__le16 edpm_num_bds;
6431 	__le16 tx_bd_cons;
6432 	__le16 tx_bd_prod;
6433 	__le16 updated_qm_pq_id;
6434 	__le16 conn_dpi;
6435 	u8 byte3;
6436 	u8 byte4;
6437 	u8 byte5;
6438 	u8 byte6;
6439 	__le32 reg0;
6440 	__le32 reg1;
6441 	__le32 reg2;
6442 	__le32 reg3;
6443 	__le32 reg4;
6444 };
6445 
6446 struct e4_mstorm_eth_conn_ag_ctx {
6447 	u8 byte0;
6448 	u8 byte1;
6449 	u8 flags0;
6450 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
6451 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	 0
6452 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_MASK		0x1
6453 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT		1
6454 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_MASK		0x3
6455 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT		2
6456 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_MASK		0x3
6457 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT		4
6458 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_MASK		0x3
6459 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT		6
6460 	u8 flags1;
6461 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK	0x1
6462 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT	0
6463 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK	0x1
6464 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT	1
6465 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK	0x1
6466 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT	2
6467 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK	0x1
6468 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT	3
6469 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK	0x1
6470 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT	4
6471 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK	0x1
6472 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT	5
6473 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK	0x1
6474 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT	6
6475 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK	0x1
6476 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT	7
6477 	__le16 word0;
6478 	__le16 word1;
6479 	__le32 reg0;
6480 	__le32 reg1;
6481 };
6482 
6483 struct e4_xstorm_eth_hw_conn_ag_ctx {
6484 	u8 reserved0;
6485 	u8 state;
6486 	u8 flags0;
6487 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
6488 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
6489 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK	0x1
6490 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT	1
6491 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK	0x1
6492 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT	2
6493 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
6494 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT	3
6495 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK	0x1
6496 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT	4
6497 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK	0x1
6498 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT	5
6499 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK	0x1
6500 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT	6
6501 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK	0x1
6502 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT	7
6503 	u8 flags1;
6504 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK		0x1
6505 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT		0
6506 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK		0x1
6507 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT		1
6508 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK		0x1
6509 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT		2
6510 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK			0x1
6511 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT		3
6512 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_MASK		0x1
6513 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_SHIFT		4
6514 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_MASK		0x1
6515 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_SHIFT		5
6516 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK	0x1
6517 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT	6
6518 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK		0x1
6519 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT		7
6520 	u8 flags2;
6521 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK	0x3
6522 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT	0
6523 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK	0x3
6524 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT	2
6525 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK	0x3
6526 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT	4
6527 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK	0x3
6528 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT	6
6529 	u8 flags3;
6530 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK	0x3
6531 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT	0
6532 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK	0x3
6533 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT	2
6534 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK	0x3
6535 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT	4
6536 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK	0x3
6537 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT	6
6538 	u8 flags4;
6539 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK	0x3
6540 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT	0
6541 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK	0x3
6542 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT	2
6543 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK	0x3
6544 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT	4
6545 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK	0x3
6546 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT	6
6547 	u8 flags5;
6548 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK	0x3
6549 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT	0
6550 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK	0x3
6551 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT	2
6552 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK	0x3
6553 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT	4
6554 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK	0x3
6555 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT	6
6556 	u8 flags6;
6557 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK	0x3
6558 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT	0
6559 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK	0x3
6560 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT	2
6561 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK			0x3
6562 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT		4
6563 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK		0x3
6564 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT		6
6565 	u8 flags7;
6566 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK	0x3
6567 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT	0
6568 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK	0x3
6569 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT	2
6570 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK	0x3
6571 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT	4
6572 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK		0x1
6573 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT	6
6574 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK		0x1
6575 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT	7
6576 	u8 flags8;
6577 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK		0x1
6578 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT	0
6579 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK		0x1
6580 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT	1
6581 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK		0x1
6582 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT	2
6583 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK		0x1
6584 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT	3
6585 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK		0x1
6586 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT	4
6587 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK		0x1
6588 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT	5
6589 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK		0x1
6590 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT	6
6591 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK		0x1
6592 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT	7
6593 	u8 flags9;
6594 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK		0x1
6595 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT		0
6596 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK		0x1
6597 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT		1
6598 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK		0x1
6599 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT		2
6600 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK		0x1
6601 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT		3
6602 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK		0x1
6603 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT		4
6604 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK		0x1
6605 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT		5
6606 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK	0x1
6607 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT	6
6608 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK	0x1
6609 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT	7
6610 	u8 flags10;
6611 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK			0x1
6612 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT			0
6613 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK		0x1
6614 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT		1
6615 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK			0x1
6616 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT			2
6617 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK			0x1
6618 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT			3
6619 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK			0x1
6620 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT			4
6621 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK	0x1
6622 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT	5
6623 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK			0x1
6624 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT			6
6625 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK			0x1
6626 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT			7
6627 	u8 flags11;
6628 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK		0x1
6629 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT		0
6630 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK		0x1
6631 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT		1
6632 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK	0x1
6633 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT	2
6634 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK		0x1
6635 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT		3
6636 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK		0x1
6637 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT		4
6638 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK		0x1
6639 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT		5
6640 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK		0x1
6641 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT		6
6642 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK		0x1
6643 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT		7
6644 	u8 flags12;
6645 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK	0x1
6646 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT	0
6647 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK	0x1
6648 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT	1
6649 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK	0x1
6650 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT	2
6651 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK	0x1
6652 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT	3
6653 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK	0x1
6654 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT	4
6655 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK	0x1
6656 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT	5
6657 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK	0x1
6658 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT	6
6659 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK	0x1
6660 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT	7
6661 	u8 flags13;
6662 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK	0x1
6663 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT	0
6664 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK	0x1
6665 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT	1
6666 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK	0x1
6667 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT	2
6668 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK	0x1
6669 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT	3
6670 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK	0x1
6671 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT	4
6672 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK	0x1
6673 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT	5
6674 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK	0x1
6675 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT	6
6676 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK	0x1
6677 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT	7
6678 	u8 flags14;
6679 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK	0x1
6680 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT	0
6681 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK	0x1
6682 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT	1
6683 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK	0x1
6684 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT	2
6685 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK	0x1
6686 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT	3
6687 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK	0x1
6688 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT	4
6689 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK	0x1
6690 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT	5
6691 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK		0x3
6692 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT		6
6693 	u8 edpm_event_id;
6694 	__le16 physical_q0;
6695 	__le16 e5_reserved1;
6696 	__le16 edpm_num_bds;
6697 	__le16 tx_bd_cons;
6698 	__le16 tx_bd_prod;
6699 	__le16 updated_qm_pq_id;
6700 	__le16 conn_dpi;
6701 };
6702 
6703 /* GFT CAM line struct */
6704 struct gft_cam_line {
6705 	__le32 camline;
6706 #define GFT_CAM_LINE_VALID_MASK		0x1
6707 #define GFT_CAM_LINE_VALID_SHIFT	0
6708 #define GFT_CAM_LINE_DATA_MASK		0x3FFF
6709 #define GFT_CAM_LINE_DATA_SHIFT		1
6710 #define GFT_CAM_LINE_MASK_BITS_MASK	0x3FFF
6711 #define GFT_CAM_LINE_MASK_BITS_SHIFT	15
6712 #define GFT_CAM_LINE_RESERVED1_MASK	0x7
6713 #define GFT_CAM_LINE_RESERVED1_SHIFT	29
6714 };
6715 
6716 /* GFT CAM line struct with fields breakout */
6717 struct gft_cam_line_mapped {
6718 	__le32 camline;
6719 #define GFT_CAM_LINE_MAPPED_VALID_MASK				0x1
6720 #define GFT_CAM_LINE_MAPPED_VALID_SHIFT				0
6721 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK			0x1
6722 #define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT			1
6723 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK		0x1
6724 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT		2
6725 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK		0xF
6726 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT		3
6727 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK			0xF
6728 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT			7
6729 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK				0xF
6730 #define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT				11
6731 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK		0x1
6732 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT		15
6733 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK		0x1
6734 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT	16
6735 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK	0xF
6736 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT	17
6737 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK		0xF
6738 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT		21
6739 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK			0xF
6740 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT			25
6741 #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK			0x7
6742 #define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT			29
6743 };
6744 
6745 union gft_cam_line_union {
6746 	struct gft_cam_line cam_line;
6747 	struct gft_cam_line_mapped cam_line_mapped;
6748 };
6749 
6750 /* Used in gft_profile_key: Indication for ip version */
6751 enum gft_profile_ip_version {
6752 	GFT_PROFILE_IPV4 = 0,
6753 	GFT_PROFILE_IPV6 = 1,
6754 	MAX_GFT_PROFILE_IP_VERSION
6755 };
6756 
6757 /* Profile key stucr fot GFT logic in Prs */
6758 struct gft_profile_key {
6759 	__le16 profile_key;
6760 #define GFT_PROFILE_KEY_IP_VERSION_MASK			0x1
6761 #define GFT_PROFILE_KEY_IP_VERSION_SHIFT		0
6762 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK		0x1
6763 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT		1
6764 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK	0xF
6765 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT	2
6766 #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK		0xF
6767 #define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT		6
6768 #define GFT_PROFILE_KEY_PF_ID_MASK			0xF
6769 #define GFT_PROFILE_KEY_PF_ID_SHIFT			10
6770 #define GFT_PROFILE_KEY_RESERVED0_MASK			0x3
6771 #define GFT_PROFILE_KEY_RESERVED0_SHIFT			14
6772 };
6773 
6774 /* Used in gft_profile_key: Indication for tunnel type */
6775 enum gft_profile_tunnel_type {
6776 	GFT_PROFILE_NO_TUNNEL = 0,
6777 	GFT_PROFILE_VXLAN_TUNNEL = 1,
6778 	GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL = 2,
6779 	GFT_PROFILE_GRE_IP_TUNNEL = 3,
6780 	GFT_PROFILE_GENEVE_MAC_TUNNEL = 4,
6781 	GFT_PROFILE_GENEVE_IP_TUNNEL = 5,
6782 	MAX_GFT_PROFILE_TUNNEL_TYPE
6783 };
6784 
6785 /* Used in gft_profile_key: Indication for protocol type */
6786 enum gft_profile_upper_protocol_type {
6787 	GFT_PROFILE_ROCE_PROTOCOL = 0,
6788 	GFT_PROFILE_RROCE_PROTOCOL = 1,
6789 	GFT_PROFILE_FCOE_PROTOCOL = 2,
6790 	GFT_PROFILE_ICMP_PROTOCOL = 3,
6791 	GFT_PROFILE_ARP_PROTOCOL = 4,
6792 	GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER = 5,
6793 	GFT_PROFILE_USER_TCP_DST_PORT_1_INNER = 6,
6794 	GFT_PROFILE_TCP_PROTOCOL = 7,
6795 	GFT_PROFILE_USER_UDP_DST_PORT_1_INNER = 8,
6796 	GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER = 9,
6797 	GFT_PROFILE_UDP_PROTOCOL = 10,
6798 	GFT_PROFILE_USER_IP_1_INNER = 11,
6799 	GFT_PROFILE_USER_IP_2_OUTER = 12,
6800 	GFT_PROFILE_USER_ETH_1_INNER = 13,
6801 	GFT_PROFILE_USER_ETH_2_OUTER = 14,
6802 	GFT_PROFILE_RAW = 15,
6803 	MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE
6804 };
6805 
6806 /* GFT RAM line struct */
6807 struct gft_ram_line {
6808 	__le32 lo;
6809 #define GFT_RAM_LINE_VLAN_SELECT_MASK			0x3
6810 #define GFT_RAM_LINE_VLAN_SELECT_SHIFT			0
6811 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK		0x1
6812 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT		2
6813 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK		0x1
6814 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT		3
6815 #define GFT_RAM_LINE_TUNNEL_TTL_MASK			0x1
6816 #define GFT_RAM_LINE_TUNNEL_TTL_SHIFT			4
6817 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK		0x1
6818 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT		5
6819 #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK		0x1
6820 #define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT		6
6821 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK		0x1
6822 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT		7
6823 #define GFT_RAM_LINE_TUNNEL_DSCP_MASK			0x1
6824 #define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT			8
6825 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK	0x1
6826 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT	9
6827 #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK			0x1
6828 #define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT		10
6829 #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK			0x1
6830 #define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT		11
6831 #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK		0x1
6832 #define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT		12
6833 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK		0x1
6834 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT		13
6835 #define GFT_RAM_LINE_TUNNEL_VLAN_MASK			0x1
6836 #define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT			14
6837 #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK		0x1
6838 #define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT		15
6839 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK		0x1
6840 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT		16
6841 #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK			0x1
6842 #define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT		17
6843 #define GFT_RAM_LINE_TTL_MASK				0x1
6844 #define GFT_RAM_LINE_TTL_SHIFT				18
6845 #define GFT_RAM_LINE_ETHERTYPE_MASK			0x1
6846 #define GFT_RAM_LINE_ETHERTYPE_SHIFT			19
6847 #define GFT_RAM_LINE_RESERVED0_MASK			0x1
6848 #define GFT_RAM_LINE_RESERVED0_SHIFT			20
6849 #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK			0x1
6850 #define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT			21
6851 #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK			0x1
6852 #define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT			22
6853 #define GFT_RAM_LINE_TCP_FLAG_RST_MASK			0x1
6854 #define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT			23
6855 #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK			0x1
6856 #define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT			24
6857 #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK			0x1
6858 #define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT			25
6859 #define GFT_RAM_LINE_TCP_FLAG_URG_MASK			0x1
6860 #define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT			26
6861 #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK			0x1
6862 #define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT			27
6863 #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK			0x1
6864 #define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT			28
6865 #define GFT_RAM_LINE_TCP_FLAG_NS_MASK			0x1
6866 #define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT			29
6867 #define GFT_RAM_LINE_DST_PORT_MASK			0x1
6868 #define GFT_RAM_LINE_DST_PORT_SHIFT			30
6869 #define GFT_RAM_LINE_SRC_PORT_MASK			0x1
6870 #define GFT_RAM_LINE_SRC_PORT_SHIFT			31
6871 	__le32 hi;
6872 #define GFT_RAM_LINE_DSCP_MASK				0x1
6873 #define GFT_RAM_LINE_DSCP_SHIFT				0
6874 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK		0x1
6875 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT		1
6876 #define GFT_RAM_LINE_DST_IP_MASK			0x1
6877 #define GFT_RAM_LINE_DST_IP_SHIFT			2
6878 #define GFT_RAM_LINE_SRC_IP_MASK			0x1
6879 #define GFT_RAM_LINE_SRC_IP_SHIFT			3
6880 #define GFT_RAM_LINE_PRIORITY_MASK			0x1
6881 #define GFT_RAM_LINE_PRIORITY_SHIFT			4
6882 #define GFT_RAM_LINE_PROVIDER_VLAN_MASK			0x1
6883 #define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT		5
6884 #define GFT_RAM_LINE_VLAN_MASK				0x1
6885 #define GFT_RAM_LINE_VLAN_SHIFT				6
6886 #define GFT_RAM_LINE_DST_MAC_MASK			0x1
6887 #define GFT_RAM_LINE_DST_MAC_SHIFT			7
6888 #define GFT_RAM_LINE_SRC_MAC_MASK			0x1
6889 #define GFT_RAM_LINE_SRC_MAC_SHIFT			8
6890 #define GFT_RAM_LINE_TENANT_ID_MASK			0x1
6891 #define GFT_RAM_LINE_TENANT_ID_SHIFT			9
6892 #define GFT_RAM_LINE_RESERVED1_MASK			0x3FFFFF
6893 #define GFT_RAM_LINE_RESERVED1_SHIFT			10
6894 };
6895 
6896 /* Used in the first 2 bits for gft_ram_line: Indication for vlan mask */
6897 enum gft_vlan_select {
6898 	INNER_PROVIDER_VLAN = 0,
6899 	INNER_VLAN = 1,
6900 	OUTER_PROVIDER_VLAN = 2,
6901 	OUTER_VLAN = 3,
6902 	MAX_GFT_VLAN_SELECT
6903 };
6904 
6905 /* The rdma task context of Mstorm */
6906 struct ystorm_rdma_task_st_ctx {
6907 	struct regpair temp[4];
6908 };
6909 
6910 struct e4_ystorm_rdma_task_ag_ctx {
6911 	u8 reserved;
6912 	u8 byte1;
6913 	__le16 msem_ctx_upd_seq;
6914 	u8 flags0;
6915 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK		0xF
6916 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT	0
6917 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK		0x1
6918 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT		4
6919 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK			0x1
6920 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT			5
6921 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK			0x1
6922 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT			6
6923 #define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK		0x1
6924 #define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT		7
6925 	u8 flags1;
6926 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK		0x3
6927 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT		0
6928 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK		0x3
6929 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT		2
6930 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK	0x3
6931 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT	4
6932 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK		0x1
6933 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT		6
6934 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK		0x1
6935 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT		7
6936 	u8 flags2;
6937 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK		0x1
6938 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT		0
6939 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK		0x1
6940 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT	1
6941 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK		0x1
6942 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT	2
6943 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK		0x1
6944 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT	3
6945 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK		0x1
6946 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT	4
6947 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK		0x1
6948 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT	5
6949 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK		0x1
6950 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT	6
6951 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK		0x1
6952 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT	7
6953 	u8 key;
6954 	__le32 mw_cnt_or_qp_id;
6955 	u8 ref_cnt_seq;
6956 	u8 ctx_upd_seq;
6957 	__le16 dif_flags;
6958 	__le16 tx_ref_count;
6959 	__le16 last_used_ltid;
6960 	__le16 parent_mr_lo;
6961 	__le16 parent_mr_hi;
6962 	__le32 fbo_lo;
6963 	__le32 fbo_hi;
6964 };
6965 
6966 struct e4_mstorm_rdma_task_ag_ctx {
6967 	u8 reserved;
6968 	u8 byte1;
6969 	__le16 icid;
6970 	u8 flags0;
6971 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK		0xF
6972 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT	0
6973 #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK		0x1
6974 #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT		4
6975 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK			0x1
6976 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT			5
6977 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK			0x1
6978 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT			6
6979 #define E4_MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK		0x1
6980 #define E4_MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT		7
6981 	u8 flags1;
6982 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK	0x3
6983 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT	0
6984 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK	0x3
6985 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT	2
6986 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK	0x3
6987 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT	4
6988 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK	0x1
6989 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT	6
6990 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK	0x1
6991 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT	7
6992 	u8 flags2;
6993 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK		0x1
6994 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT		0
6995 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK		0x1
6996 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT	1
6997 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK		0x1
6998 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT	2
6999 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK		0x1
7000 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT	3
7001 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK		0x1
7002 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT	4
7003 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK		0x1
7004 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT	5
7005 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK		0x1
7006 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT	6
7007 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK		0x1
7008 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT	7
7009 	u8 key;
7010 	__le32 mw_cnt_or_qp_id;
7011 	u8 ref_cnt_seq;
7012 	u8 ctx_upd_seq;
7013 	__le16 dif_flags;
7014 	__le16 tx_ref_count;
7015 	__le16 last_used_ltid;
7016 	__le16 parent_mr_lo;
7017 	__le16 parent_mr_hi;
7018 	__le32 fbo_lo;
7019 	__le32 fbo_hi;
7020 };
7021 
7022 /* The roce task context of Mstorm */
7023 struct mstorm_rdma_task_st_ctx {
7024 	struct regpair temp[4];
7025 };
7026 
7027 struct e4_ustorm_rdma_task_ag_ctx {
7028 	u8 reserved;
7029 	u8 state;
7030 	__le16 icid;
7031 	u8 flags0;
7032 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK		0xF
7033 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT	0
7034 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK		0x1
7035 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT		4
7036 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK		0x1
7037 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT		5
7038 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK	0x3
7039 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT	6
7040 	u8 flags1;
7041 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK	0x3
7042 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT	0
7043 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK		0x3
7044 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT		2
7045 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_MASK          0x3
7046 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_SHIFT         4
7047 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK		0x3
7048 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT		6
7049 	u8 flags2;
7050 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK	0x1
7051 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT	0
7052 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK		0x1
7053 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT		1
7054 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK		0x1
7055 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT		2
7056 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED4_MASK               0x1
7057 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED4_SHIFT              3
7058 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK		0x1
7059 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT	4
7060 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK			0x1
7061 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT		5
7062 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK			0x1
7063 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT		6
7064 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK			0x1
7065 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT		7
7066 	u8 flags3;
7067 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK		0x1
7068 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT	0
7069 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK		0x1
7070 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT	1
7071 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK		0x1
7072 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT	2
7073 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK		0x1
7074 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT	3
7075 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK	0xF
7076 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT	4
7077 	__le32 dif_err_intervals;
7078 	__le32 dif_error_1st_interval;
7079 	__le32 sq_cons;
7080 	__le32 dif_runt_value;
7081 	__le32 sge_index;
7082 	__le32 reg5;
7083 	u8 byte2;
7084 	u8 byte3;
7085 	__le16 word1;
7086 	__le16 word2;
7087 	__le16 word3;
7088 	__le32 reg6;
7089 	__le32 reg7;
7090 };
7091 
7092 /* RDMA task context */
7093 struct e4_rdma_task_context {
7094 	struct ystorm_rdma_task_st_ctx ystorm_st_context;
7095 	struct e4_ystorm_rdma_task_ag_ctx ystorm_ag_context;
7096 	struct tdif_task_context tdif_context;
7097 	struct e4_mstorm_rdma_task_ag_ctx mstorm_ag_context;
7098 	struct mstorm_rdma_task_st_ctx mstorm_st_context;
7099 	struct rdif_task_context rdif_context;
7100 	struct e4_ustorm_rdma_task_ag_ctx ustorm_ag_context;
7101 };
7102 
7103 /* rdma function init ramrod data */
7104 struct rdma_close_func_ramrod_data {
7105 	u8 cnq_start_offset;
7106 	u8 num_cnqs;
7107 	u8 vf_id;
7108 	u8 vf_valid;
7109 	u8 reserved[4];
7110 };
7111 
7112 /* rdma function init CNQ parameters */
7113 struct rdma_cnq_params {
7114 	__le16 sb_num;
7115 	u8 sb_index;
7116 	u8 num_pbl_pages;
7117 	__le32 reserved;
7118 	struct regpair pbl_base_addr;
7119 	__le16 queue_zone_num;
7120 	u8 reserved1[6];
7121 };
7122 
7123 /* rdma create cq ramrod data */
7124 struct rdma_create_cq_ramrod_data {
7125 	struct regpair cq_handle;
7126 	struct regpair pbl_addr;
7127 	__le32 max_cqes;
7128 	__le16 pbl_num_pages;
7129 	__le16 dpi;
7130 	u8 is_two_level_pbl;
7131 	u8 cnq_id;
7132 	u8 pbl_log_page_size;
7133 	u8 toggle_bit;
7134 	__le16 int_timeout;
7135 	__le16 reserved1;
7136 };
7137 
7138 /* rdma deregister tid ramrod data */
7139 struct rdma_deregister_tid_ramrod_data {
7140 	__le32 itid;
7141 	__le32 reserved;
7142 };
7143 
7144 /* rdma destroy cq output params */
7145 struct rdma_destroy_cq_output_params {
7146 	__le16 cnq_num;
7147 	__le16 reserved0;
7148 	__le32 reserved1;
7149 };
7150 
7151 /* rdma destroy cq ramrod data */
7152 struct rdma_destroy_cq_ramrod_data {
7153 	struct regpair output_params_addr;
7154 };
7155 
7156 /* RDMA slow path EQ cmd IDs */
7157 enum rdma_event_opcode {
7158 	RDMA_EVENT_UNUSED,
7159 	RDMA_EVENT_FUNC_INIT,
7160 	RDMA_EVENT_FUNC_CLOSE,
7161 	RDMA_EVENT_REGISTER_MR,
7162 	RDMA_EVENT_DEREGISTER_MR,
7163 	RDMA_EVENT_CREATE_CQ,
7164 	RDMA_EVENT_RESIZE_CQ,
7165 	RDMA_EVENT_DESTROY_CQ,
7166 	RDMA_EVENT_CREATE_SRQ,
7167 	RDMA_EVENT_MODIFY_SRQ,
7168 	RDMA_EVENT_DESTROY_SRQ,
7169 	MAX_RDMA_EVENT_OPCODE
7170 };
7171 
7172 /* RDMA FW return code for slow path ramrods */
7173 enum rdma_fw_return_code {
7174 	RDMA_RETURN_OK = 0,
7175 	RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR,
7176 	RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR,
7177 	RDMA_RETURN_RESIZE_CQ_ERR,
7178 	RDMA_RETURN_NIG_DRAIN_REQ,
7179 	MAX_RDMA_FW_RETURN_CODE
7180 };
7181 
7182 /* rdma function init header */
7183 struct rdma_init_func_hdr {
7184 	u8 cnq_start_offset;
7185 	u8 num_cnqs;
7186 	u8 cq_ring_mode;
7187 	u8 vf_id;
7188 	u8 vf_valid;
7189 	u8 relaxed_ordering;
7190 	__le16 first_reg_srq_id;
7191 	__le32 reg_srq_base_addr;
7192 	__le32 reserved;
7193 };
7194 
7195 /* rdma function init ramrod data */
7196 struct rdma_init_func_ramrod_data {
7197 	struct rdma_init_func_hdr params_header;
7198 	struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES];
7199 };
7200 
7201 /* RDMA ramrod command IDs */
7202 enum rdma_ramrod_cmd_id {
7203 	RDMA_RAMROD_UNUSED,
7204 	RDMA_RAMROD_FUNC_INIT,
7205 	RDMA_RAMROD_FUNC_CLOSE,
7206 	RDMA_RAMROD_REGISTER_MR,
7207 	RDMA_RAMROD_DEREGISTER_MR,
7208 	RDMA_RAMROD_CREATE_CQ,
7209 	RDMA_RAMROD_RESIZE_CQ,
7210 	RDMA_RAMROD_DESTROY_CQ,
7211 	RDMA_RAMROD_CREATE_SRQ,
7212 	RDMA_RAMROD_MODIFY_SRQ,
7213 	RDMA_RAMROD_DESTROY_SRQ,
7214 	MAX_RDMA_RAMROD_CMD_ID
7215 };
7216 
7217 /* rdma register tid ramrod data */
7218 struct rdma_register_tid_ramrod_data {
7219 	__le16 flags;
7220 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK	0x1F
7221 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT	0
7222 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK	0x1
7223 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT	5
7224 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK		0x1
7225 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT		6
7226 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK		0x1
7227 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT		7
7228 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK		0x1
7229 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT		8
7230 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK		0x1
7231 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT	9
7232 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK	0x1
7233 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT	10
7234 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK		0x1
7235 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT		11
7236 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK		0x1
7237 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT		12
7238 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK	0x1
7239 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT	13
7240 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK		0x3
7241 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_SHIFT		14
7242 	u8 flags1;
7243 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK	0x1F
7244 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT	0
7245 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK		0x7
7246 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT		5
7247 	u8 flags2;
7248 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK		0x1
7249 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT		0
7250 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK	0x1
7251 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT	1
7252 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK		0x3F
7253 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT		2
7254 	u8 key;
7255 	u8 length_hi;
7256 	u8 vf_id;
7257 	u8 vf_valid;
7258 	__le16 pd;
7259 	__le16 reserved2;
7260 	__le32 length_lo;
7261 	__le32 itid;
7262 	__le32 reserved3;
7263 	struct regpair va;
7264 	struct regpair pbl_base;
7265 	struct regpair dif_error_addr;
7266 	__le32 reserved4[4];
7267 };
7268 
7269 /* rdma resize cq output params */
7270 struct rdma_resize_cq_output_params {
7271 	__le32 old_cq_cons;
7272 	__le32 old_cq_prod;
7273 };
7274 
7275 /* rdma resize cq ramrod data */
7276 struct rdma_resize_cq_ramrod_data {
7277 	u8 flags;
7278 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK		0x1
7279 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT		0
7280 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK	0x1
7281 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT	1
7282 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK		0x3F
7283 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT		2
7284 	u8 pbl_log_page_size;
7285 	__le16 pbl_num_pages;
7286 	__le32 max_cqes;
7287 	struct regpair pbl_addr;
7288 	struct regpair output_params_addr;
7289 };
7290 
7291 /* The rdma storm context of Mstorm */
7292 struct rdma_srq_context {
7293 	struct regpair temp[8];
7294 };
7295 
7296 /* rdma create qp requester ramrod data */
7297 struct rdma_srq_create_ramrod_data {
7298 	u8 flags;
7299 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_MASK         0x1
7300 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_SHIFT        0
7301 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_MASK  0x1
7302 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 1
7303 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_MASK        0x3F
7304 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_SHIFT       2
7305 	u8 reserved2;
7306 	__le16 xrc_domain;
7307 	__le32 xrc_srq_cq_cid;
7308 	struct regpair pbl_base_addr;
7309 	__le16 pages_in_srq_pbl;
7310 	__le16 pd_id;
7311 	struct rdma_srq_id srq_id;
7312 	__le16 page_size;
7313 	__le16 reserved3;
7314 	__le32 reserved4;
7315 	struct regpair producers_addr;
7316 };
7317 
7318 /* rdma create qp requester ramrod data */
7319 struct rdma_srq_destroy_ramrod_data {
7320 	struct rdma_srq_id srq_id;
7321 	__le32 reserved;
7322 };
7323 
7324 /* rdma create qp requester ramrod data */
7325 struct rdma_srq_modify_ramrod_data {
7326 	struct rdma_srq_id srq_id;
7327 	__le32 wqe_limit;
7328 };
7329 
7330 /* RDMA Tid type enumeration (for register_tid ramrod) */
7331 enum rdma_tid_type {
7332 	RDMA_TID_REGISTERED_MR,
7333 	RDMA_TID_FMR,
7334 	RDMA_TID_MW,
7335 	MAX_RDMA_TID_TYPE
7336 };
7337 
7338 struct rdma_xrc_srq_context {
7339 	struct regpair temp[9];
7340 };
7341 
7342 struct e4_tstorm_rdma_task_ag_ctx {
7343 	u8 byte0;
7344 	u8 byte1;
7345 	__le16 word0;
7346 	u8 flags0;
7347 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK		0xF
7348 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT	0
7349 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK		0x1
7350 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT		4
7351 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK		0x1
7352 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT		5
7353 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK		0x1
7354 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT		6
7355 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK		0x1
7356 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT		7
7357 	u8 flags1;
7358 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK	0x1
7359 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT	0
7360 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK	0x1
7361 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT	1
7362 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK	0x3
7363 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT	2
7364 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK	0x3
7365 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT	4
7366 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK	0x3
7367 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT	6
7368 	u8 flags2;
7369 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK	0x3
7370 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT	0
7371 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK	0x3
7372 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT	2
7373 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK	0x3
7374 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT	4
7375 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK	0x3
7376 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT	6
7377 	u8 flags3;
7378 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK	0x3
7379 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT	0
7380 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK	0x1
7381 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT	2
7382 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK	0x1
7383 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT	3
7384 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK	0x1
7385 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT	4
7386 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK	0x1
7387 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT	5
7388 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK	0x1
7389 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT	6
7390 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK	0x1
7391 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT	7
7392 	u8 flags4;
7393 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK		0x1
7394 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT		0
7395 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK		0x1
7396 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT		1
7397 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK		0x1
7398 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT	2
7399 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK		0x1
7400 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT	3
7401 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK		0x1
7402 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT	4
7403 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK		0x1
7404 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT	5
7405 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK		0x1
7406 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT	6
7407 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK		0x1
7408 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT	7
7409 	u8 byte2;
7410 	__le16 word1;
7411 	__le32 reg0;
7412 	u8 byte3;
7413 	u8 byte4;
7414 	__le16 word2;
7415 	__le16 word3;
7416 	__le16 word4;
7417 	__le32 reg1;
7418 	__le32 reg2;
7419 };
7420 
7421 struct e4_ustorm_rdma_conn_ag_ctx {
7422 	u8 reserved;
7423 	u8 byte1;
7424 	u8 flags0;
7425 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
7426 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
7427 #define E4_USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_MASK  0x1
7428 #define E4_USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_SHIFT 1
7429 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK	0x3
7430 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT	2
7431 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_MASK		0x3
7432 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT		4
7433 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_MASK		0x3
7434 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT		6
7435 	u8 flags1;
7436 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_MASK		0x3
7437 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT		0
7438 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK	0x3
7439 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT	2
7440 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK	0x3
7441 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT	4
7442 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_MASK		0x3
7443 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT		6
7444 	u8 flags2;
7445 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK		0x1
7446 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT		0
7447 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK			0x1
7448 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT			1
7449 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK			0x1
7450 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT			2
7451 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK			0x1
7452 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT			3
7453 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK		0x1
7454 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT	4
7455 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK		0x1
7456 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT		5
7457 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK			0x1
7458 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT			6
7459 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK		0x1
7460 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT		7
7461 	u8 flags3;
7462 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK		0x1
7463 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT		0
7464 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK		0x1
7465 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT	1
7466 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK		0x1
7467 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT	2
7468 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK		0x1
7469 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT	3
7470 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK		0x1
7471 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT	4
7472 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK		0x1
7473 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT	5
7474 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK		0x1
7475 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT	6
7476 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK		0x1
7477 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT	7
7478 	u8 byte2;
7479 	u8 nvmf_only;
7480 	__le16 conn_dpi;
7481 	__le16 word1;
7482 	__le32 cq_cons;
7483 	__le32 cq_se_prod;
7484 	__le32 cq_prod;
7485 	__le32 reg3;
7486 	__le16 int_timeout;
7487 	__le16 word3;
7488 };
7489 
7490 struct e4_xstorm_roce_conn_ag_ctx {
7491 	u8 reserved0;
7492 	u8 state;
7493 	u8 flags0;
7494 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK      0x1
7495 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT     0
7496 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT1_MASK              0x1
7497 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT             1
7498 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT2_MASK              0x1
7499 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT2_SHIFT             2
7500 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_MASK      0x1
7501 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT     3
7502 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT4_MASK              0x1
7503 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT4_SHIFT             4
7504 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT5_MASK              0x1
7505 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT5_SHIFT             5
7506 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT6_MASK              0x1
7507 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT6_SHIFT             6
7508 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT7_MASK              0x1
7509 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT7_SHIFT             7
7510 	u8 flags1;
7511 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT8_MASK              0x1
7512 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT8_SHIFT             0
7513 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT9_MASK              0x1
7514 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT9_SHIFT             1
7515 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT10_MASK             0x1
7516 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT10_SHIFT            2
7517 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT11_MASK             0x1
7518 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT11_SHIFT            3
7519 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT12_MASK             0x1
7520 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT12_SHIFT            4
7521 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_MASK        0x1
7522 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_SHIFT       5
7523 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_MASK        0x1
7524 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_SHIFT       6
7525 #define E4_XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_MASK      0x1
7526 #define E4_XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_SHIFT     7
7527 	u8 flags2;
7528 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0_MASK               0x3
7529 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT              0
7530 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1_MASK               0x3
7531 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT              2
7532 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2_MASK               0x3
7533 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT              4
7534 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3_MASK               0x3
7535 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3_SHIFT              6
7536 	u8 flags3;
7537 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4_MASK               0x3
7538 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4_SHIFT              0
7539 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5_MASK               0x3
7540 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT              2
7541 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6_MASK               0x3
7542 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6_SHIFT              4
7543 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK       0x3
7544 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT      6
7545 	u8 flags4;
7546 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8_MASK               0x3
7547 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT              0
7548 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9_MASK               0x3
7549 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT              2
7550 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10_MASK              0x3
7551 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10_SHIFT             4
7552 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11_MASK              0x3
7553 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11_SHIFT             6
7554 	u8 flags5;
7555 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12_MASK              0x3
7556 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12_SHIFT             0
7557 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13_MASK              0x3
7558 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13_SHIFT             2
7559 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14_MASK              0x3
7560 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14_SHIFT             4
7561 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15_MASK              0x3
7562 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15_SHIFT             6
7563 	u8 flags6;
7564 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16_MASK              0x3
7565 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16_SHIFT             0
7566 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17_MASK              0x3
7567 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17_SHIFT             2
7568 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18_MASK              0x3
7569 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18_SHIFT             4
7570 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19_MASK              0x3
7571 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19_SHIFT             6
7572 	u8 flags7;
7573 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20_MASK              0x3
7574 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20_SHIFT             0
7575 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21_MASK              0x3
7576 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21_SHIFT             2
7577 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_MASK         0x3
7578 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_SHIFT        4
7579 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK             0x1
7580 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT            6
7581 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK             0x1
7582 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT            7
7583 	u8 flags8;
7584 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK             0x1
7585 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT            0
7586 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3EN_MASK             0x1
7587 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3EN_SHIFT            1
7588 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4EN_MASK             0x1
7589 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4EN_SHIFT            2
7590 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK             0x1
7591 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5EN_SHIFT            3
7592 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK             0x1
7593 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6EN_SHIFT            4
7594 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK    0x1
7595 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT   5
7596 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK             0x1
7597 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8EN_SHIFT            6
7598 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK             0x1
7599 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9EN_SHIFT            7
7600 	u8 flags9;
7601 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK            0x1
7602 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT           0
7603 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11EN_MASK            0x1
7604 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11EN_SHIFT           1
7605 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12EN_MASK            0x1
7606 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12EN_SHIFT           2
7607 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13EN_MASK            0x1
7608 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13EN_SHIFT           3
7609 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14EN_MASK            0x1
7610 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14EN_SHIFT           4
7611 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15EN_MASK            0x1
7612 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15EN_SHIFT           5
7613 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16EN_MASK            0x1
7614 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16EN_SHIFT           6
7615 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17EN_MASK            0x1
7616 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17EN_SHIFT           7
7617 	u8 flags10;
7618 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18EN_MASK            0x1
7619 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18EN_SHIFT           0
7620 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19EN_MASK            0x1
7621 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19EN_SHIFT           1
7622 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20EN_MASK            0x1
7623 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20EN_SHIFT           2
7624 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21EN_MASK            0x1
7625 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21EN_SHIFT           3
7626 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_MASK      0x1
7627 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT     4
7628 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23EN_MASK            0x1
7629 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23EN_SHIFT           5
7630 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK           0x1
7631 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT          6
7632 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK           0x1
7633 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT          7
7634 	u8 flags11;
7635 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK           0x1
7636 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT          0
7637 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK           0x1
7638 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT          1
7639 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK           0x1
7640 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT          2
7641 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK           0x1
7642 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE5EN_SHIFT          3
7643 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK           0x1
7644 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE6EN_SHIFT          4
7645 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK           0x1
7646 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE7EN_SHIFT          5
7647 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_MASK      0x1
7648 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_SHIFT     6
7649 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE9EN_MASK           0x1
7650 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE9EN_SHIFT          7
7651 	u8 flags12;
7652 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE10EN_MASK          0x1
7653 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE10EN_SHIFT         0
7654 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE11EN_MASK          0x1
7655 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE11EN_SHIFT         1
7656 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_MASK      0x1
7657 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_SHIFT     2
7658 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_MASK      0x1
7659 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_SHIFT     3
7660 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE14EN_MASK          0x1
7661 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE14EN_SHIFT         4
7662 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE15EN_MASK          0x1
7663 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE15EN_SHIFT         5
7664 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE16EN_MASK          0x1
7665 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE16EN_SHIFT         6
7666 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE17EN_MASK          0x1
7667 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE17EN_SHIFT         7
7668 	u8 flags13;
7669 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE18EN_MASK          0x1
7670 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE18EN_SHIFT         0
7671 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE19EN_MASK          0x1
7672 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE19EN_SHIFT         1
7673 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_MASK      0x1
7674 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_SHIFT     2
7675 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_MASK      0x1
7676 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_SHIFT     3
7677 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_MASK      0x1
7678 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_SHIFT     4
7679 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_MASK      0x1
7680 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_SHIFT     5
7681 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_MASK      0x1
7682 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_SHIFT     6
7683 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_MASK      0x1
7684 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_SHIFT     7
7685 	u8 flags14;
7686 #define E4_XSTORM_ROCE_CONN_AG_CTX_MIGRATION_MASK         0x1
7687 #define E4_XSTORM_ROCE_CONN_AG_CTX_MIGRATION_SHIFT        0
7688 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT17_MASK             0x1
7689 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT17_SHIFT            1
7690 #define E4_XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_MASK      0x3
7691 #define E4_XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_SHIFT     2
7692 #define E4_XSTORM_ROCE_CONN_AG_CTX_RESERVED_MASK          0x1
7693 #define E4_XSTORM_ROCE_CONN_AG_CTX_RESERVED_SHIFT         4
7694 #define E4_XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK  0x1
7695 #define E4_XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
7696 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23_MASK              0x3
7697 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23_SHIFT             6
7698 	u8 byte2;
7699 	__le16 physical_q0;
7700 	__le16 word1;
7701 	__le16 word2;
7702 	__le16 word3;
7703 	__le16 word4;
7704 	__le16 word5;
7705 	__le16 conn_dpi;
7706 	u8 byte3;
7707 	u8 byte4;
7708 	u8 byte5;
7709 	u8 byte6;
7710 	__le32 reg0;
7711 	__le32 reg1;
7712 	__le32 reg2;
7713 	__le32 snd_nxt_psn;
7714 	__le32 reg4;
7715 	__le32 reg5;
7716 	__le32 reg6;
7717 };
7718 
7719 struct e4_tstorm_roce_conn_ag_ctx {
7720 	u8 reserved0;
7721 	u8 byte1;
7722 	u8 flags0;
7723 #define E4_TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK          0x1
7724 #define E4_TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT         0
7725 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT1_MASK                  0x1
7726 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT                 1
7727 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT2_MASK                  0x1
7728 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT2_SHIFT                 2
7729 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT3_MASK                  0x1
7730 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT3_SHIFT                 3
7731 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT4_MASK                  0x1
7732 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT4_SHIFT                 4
7733 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT5_MASK                  0x1
7734 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT5_SHIFT                 5
7735 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0_MASK                   0x3
7736 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT                  6
7737 	u8 flags1;
7738 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK       0x3
7739 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT      0
7740 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2_MASK                   0x3
7741 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT                  2
7742 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK     0x3
7743 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT    4
7744 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK           0x3
7745 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT          6
7746 	u8 flags2;
7747 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5_MASK                   0x3
7748 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT                  0
7749 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6_MASK                   0x3
7750 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6_SHIFT                  2
7751 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7_MASK                   0x3
7752 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7_SHIFT                  4
7753 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8_MASK                   0x3
7754 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT                  6
7755 	u8 flags3;
7756 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9_MASK                   0x3
7757 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT                  0
7758 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10_MASK                  0x3
7759 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10_SHIFT                 2
7760 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK                 0x1
7761 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT                4
7762 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK    0x1
7763 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT   5
7764 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK                 0x1
7765 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT                6
7766 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK  0x1
7767 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
7768 	u8 flags4;
7769 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK        0x1
7770 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT       0
7771 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK                 0x1
7772 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5EN_SHIFT                1
7773 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK                 0x1
7774 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6EN_SHIFT                2
7775 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7EN_MASK                 0x1
7776 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7EN_SHIFT                3
7777 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK                 0x1
7778 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8EN_SHIFT                4
7779 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK                 0x1
7780 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9EN_SHIFT                5
7781 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK                0x1
7782 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT               6
7783 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK               0x1
7784 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT              7
7785 	u8 flags5;
7786 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK               0x1
7787 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT              0
7788 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK               0x1
7789 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT              1
7790 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK               0x1
7791 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT              2
7792 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK               0x1
7793 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT              3
7794 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK               0x1
7795 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE5EN_SHIFT              4
7796 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK               0x1
7797 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE6EN_SHIFT              5
7798 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK               0x1
7799 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE7EN_SHIFT              6
7800 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE8EN_MASK               0x1
7801 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE8EN_SHIFT              7
7802 	__le32 reg0;
7803 	__le32 reg1;
7804 	__le32 reg2;
7805 	__le32 reg3;
7806 	__le32 reg4;
7807 	__le32 reg5;
7808 	__le32 reg6;
7809 	__le32 reg7;
7810 	__le32 reg8;
7811 	u8 byte2;
7812 	u8 byte3;
7813 	__le16 word0;
7814 	u8 byte4;
7815 	u8 byte5;
7816 	__le16 word1;
7817 	__le16 word2;
7818 	__le16 word3;
7819 	__le32 reg9;
7820 	__le32 reg10;
7821 };
7822 
7823 /* The roce storm context of Ystorm */
7824 struct ystorm_roce_conn_st_ctx {
7825 	struct regpair temp[2];
7826 };
7827 
7828 /* The roce storm context of Mstorm */
7829 struct pstorm_roce_conn_st_ctx {
7830 	struct regpair temp[16];
7831 };
7832 
7833 /* The roce storm context of Xstorm */
7834 struct xstorm_roce_conn_st_ctx {
7835 	struct regpair temp[24];
7836 };
7837 
7838 /* The roce storm context of Tstorm */
7839 struct tstorm_roce_conn_st_ctx {
7840 	struct regpair temp[30];
7841 };
7842 
7843 /* The roce storm context of Mstorm */
7844 struct mstorm_roce_conn_st_ctx {
7845 	struct regpair temp[6];
7846 };
7847 
7848 /* The roce storm context of Ystorm */
7849 struct ustorm_roce_conn_st_ctx {
7850 	struct regpair temp[12];
7851 };
7852 
7853 /* roce connection context */
7854 struct e4_roce_conn_context {
7855 	struct ystorm_roce_conn_st_ctx ystorm_st_context;
7856 	struct regpair ystorm_st_padding[2];
7857 	struct pstorm_roce_conn_st_ctx pstorm_st_context;
7858 	struct xstorm_roce_conn_st_ctx xstorm_st_context;
7859 	struct e4_xstorm_roce_conn_ag_ctx xstorm_ag_context;
7860 	struct e4_tstorm_roce_conn_ag_ctx tstorm_ag_context;
7861 	struct timers_context timer_context;
7862 	struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context;
7863 	struct tstorm_roce_conn_st_ctx tstorm_st_context;
7864 	struct regpair tstorm_st_padding[2];
7865 	struct mstorm_roce_conn_st_ctx mstorm_st_context;
7866 	struct regpair mstorm_st_padding[2];
7867 	struct ustorm_roce_conn_st_ctx ustorm_st_context;
7868 };
7869 
7870 /* roce cqes statistics */
7871 struct roce_cqe_stats {
7872 	__le32 req_cqe_error;
7873 	__le32 req_remote_access_errors;
7874 	__le32 req_remote_invalid_request;
7875 	__le32 resp_cqe_error;
7876 	__le32 resp_local_length_error;
7877 	__le32 reserved;
7878 };
7879 
7880 /* roce create qp requester ramrod data */
7881 struct roce_create_qp_req_ramrod_data {
7882 	__le16 flags;
7883 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK			0x3
7884 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT		0
7885 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK		0x1
7886 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT	2
7887 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK		0x1
7888 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT		3
7889 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK				0x7
7890 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT			4
7891 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_MASK			0x1
7892 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_SHIFT			7
7893 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK		0xF
7894 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT		8
7895 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK			0xF
7896 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT		12
7897 	u8 max_ord;
7898 	u8 traffic_class;
7899 	u8 hop_limit;
7900 	u8 orq_num_pages;
7901 	__le16 p_key;
7902 	__le32 flow_label;
7903 	__le32 dst_qp_id;
7904 	__le32 ack_timeout_val;
7905 	__le32 initial_psn;
7906 	__le16 mtu;
7907 	__le16 pd;
7908 	__le16 sq_num_pages;
7909 	__le16 low_latency_phy_queue;
7910 	struct regpair sq_pbl_addr;
7911 	struct regpair orq_pbl_addr;
7912 	__le16 local_mac_addr[3];
7913 	__le16 remote_mac_addr[3];
7914 	__le16 vlan_id;
7915 	__le16 udp_src_port;
7916 	__le32 src_gid[4];
7917 	__le32 dst_gid[4];
7918 	__le32 cq_cid;
7919 	struct regpair qp_handle_for_cqe;
7920 	struct regpair qp_handle_for_async;
7921 	u8 stats_counter_id;
7922 	u8 reserved3[6];
7923 	u8 flags2;
7924 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_MASK			0x1
7925 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_SHIFT			0
7926 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK			0x7F
7927 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT			1
7928 	__le16 regular_latency_phy_queue;
7929 	__le16 dpi;
7930 };
7931 
7932 /* roce create qp responder ramrod data */
7933 struct roce_create_qp_resp_ramrod_data {
7934 	__le32 flags;
7935 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK		0x3
7936 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT		0
7937 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK			0x1
7938 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT		2
7939 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK			0x1
7940 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT		3
7941 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK			0x1
7942 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT			4
7943 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK			0x1
7944 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT			5
7945 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK	0x1
7946 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT	6
7947 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK		0x1
7948 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT		7
7949 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK			0x7
7950 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT			8
7951 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK		0x1F
7952 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT		11
7953 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_MASK             0x1
7954 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_SHIFT            16
7955 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_MASK             0x7FFF
7956 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_SHIFT            17
7957 	__le16 xrc_domain;
7958 	u8 max_ird;
7959 	u8 traffic_class;
7960 	u8 hop_limit;
7961 	u8 irq_num_pages;
7962 	__le16 p_key;
7963 	__le32 flow_label;
7964 	__le32 dst_qp_id;
7965 	u8 stats_counter_id;
7966 	u8 reserved1;
7967 	__le16 mtu;
7968 	__le32 initial_psn;
7969 	__le16 pd;
7970 	__le16 rq_num_pages;
7971 	struct rdma_srq_id srq_id;
7972 	struct regpair rq_pbl_addr;
7973 	struct regpair irq_pbl_addr;
7974 	__le16 local_mac_addr[3];
7975 	__le16 remote_mac_addr[3];
7976 	__le16 vlan_id;
7977 	__le16 udp_src_port;
7978 	__le32 src_gid[4];
7979 	__le32 dst_gid[4];
7980 	struct regpair qp_handle_for_cqe;
7981 	struct regpair qp_handle_for_async;
7982 	__le16 low_latency_phy_queue;
7983 	u8 reserved2[2];
7984 	__le32 cq_cid;
7985 	__le16 regular_latency_phy_queue;
7986 	__le16 dpi;
7987 };
7988 
7989 /* roce DCQCN received statistics */
7990 struct roce_dcqcn_received_stats {
7991 	struct regpair ecn_pkt_rcv;
7992 	struct regpair cnp_pkt_rcv;
7993 };
7994 
7995 /* roce DCQCN sent statistics */
7996 struct roce_dcqcn_sent_stats {
7997 	struct regpair cnp_pkt_sent;
7998 };
7999 
8000 /* RoCE destroy qp requester output params */
8001 struct roce_destroy_qp_req_output_params {
8002 	__le32 cq_prod;
8003 	__le32 reserved;
8004 };
8005 
8006 /* RoCE destroy qp requester ramrod data */
8007 struct roce_destroy_qp_req_ramrod_data {
8008 	struct regpair output_params_addr;
8009 };
8010 
8011 /* RoCE destroy qp responder output params */
8012 struct roce_destroy_qp_resp_output_params {
8013 	__le32 cq_prod;
8014 	__le32 reserved;
8015 };
8016 
8017 /* RoCE destroy qp responder ramrod data */
8018 struct roce_destroy_qp_resp_ramrod_data {
8019 	struct regpair output_params_addr;
8020 };
8021 
8022 /* roce error statistics */
8023 struct roce_error_stats {
8024 	__le32 resp_remote_access_errors;
8025 	__le32 reserved;
8026 };
8027 
8028 /* roce special events statistics */
8029 struct roce_events_stats {
8030 	__le32 silent_drops;
8031 	__le32 rnr_naks_sent;
8032 	__le32 retransmit_count;
8033 	__le32 icrc_error_count;
8034 	__le32 implied_nak_seq_err;
8035 	__le32 duplicate_request;
8036 	__le32 local_ack_timeout_err;
8037 	__le32 out_of_sequence;
8038 	__le32 packet_seq_err;
8039 	__le32 rnr_nak_retry_err;
8040 };
8041 
8042 /* roce slow path EQ cmd IDs */
8043 enum roce_event_opcode {
8044 	ROCE_EVENT_CREATE_QP = 11,
8045 	ROCE_EVENT_MODIFY_QP,
8046 	ROCE_EVENT_QUERY_QP,
8047 	ROCE_EVENT_DESTROY_QP,
8048 	ROCE_EVENT_CREATE_UD_QP,
8049 	ROCE_EVENT_DESTROY_UD_QP,
8050 	ROCE_EVENT_FUNC_UPDATE,
8051 	MAX_ROCE_EVENT_OPCODE
8052 };
8053 
8054 /* roce func init ramrod data */
8055 struct roce_init_func_params {
8056 	u8 ll2_queue_id;
8057 	u8 cnp_vlan_priority;
8058 	u8 cnp_dscp;
8059 	u8 flags;
8060 #define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_MASK		0x1
8061 #define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_SHIFT		0
8062 #define ROCE_INIT_FUNC_PARAMS_DCQCN_RP_EN_MASK		0x1
8063 #define ROCE_INIT_FUNC_PARAMS_DCQCN_RP_EN_SHIFT		1
8064 #define ROCE_INIT_FUNC_PARAMS_RESERVED0_MASK		0x3F
8065 #define ROCE_INIT_FUNC_PARAMS_RESERVED0_SHIFT		2
8066 	__le32 cnp_send_timeout;
8067 	__le16 rl_offset;
8068 	u8 rl_count_log;
8069 	u8 reserved1[5];
8070 };
8071 
8072 /* roce func init ramrod data */
8073 struct roce_init_func_ramrod_data {
8074 	struct rdma_init_func_ramrod_data rdma;
8075 	struct roce_init_func_params roce;
8076 };
8077 
8078 /* roce modify qp requester ramrod data */
8079 struct roce_modify_qp_req_ramrod_data {
8080 	__le16 flags;
8081 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK		0x1
8082 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT		0
8083 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK		0x1
8084 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT		1
8085 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK		0x1
8086 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT	2
8087 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK			0x1
8088 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT			3
8089 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK		0x1
8090 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT		4
8091 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK			0x1
8092 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT		5
8093 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK		0x1
8094 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT		6
8095 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK		0x1
8096 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT		7
8097 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK		0x1
8098 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT		8
8099 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK			0x1
8100 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT			9
8101 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK				0x7
8102 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT			10
8103 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUES_FLG_MASK		0x1
8104 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUES_FLG_SHIFT	13
8105 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK			0x3
8106 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT			14
8107 	u8 fields;
8108 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK	0xF
8109 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT	0
8110 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK		0xF
8111 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT	4
8112 	u8 max_ord;
8113 	u8 traffic_class;
8114 	u8 hop_limit;
8115 	__le16 p_key;
8116 	__le32 flow_label;
8117 	__le32 ack_timeout_val;
8118 	__le16 mtu;
8119 	__le16 reserved2;
8120 	__le32 reserved3[2];
8121 	__le16 low_latency_phy_queue;
8122 	__le16 regular_latency_phy_queue;
8123 	__le32 src_gid[4];
8124 	__le32 dst_gid[4];
8125 };
8126 
8127 /* roce modify qp responder ramrod data */
8128 struct roce_modify_qp_resp_ramrod_data {
8129 	__le16 flags;
8130 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK		0x1
8131 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT		0
8132 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK			0x1
8133 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT		1
8134 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK			0x1
8135 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT		2
8136 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK			0x1
8137 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT			3
8138 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK			0x1
8139 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT			4
8140 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK		0x1
8141 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT	5
8142 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK		0x1
8143 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT		6
8144 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK			0x1
8145 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT			7
8146 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK	0x1
8147 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT	8
8148 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK		0x1
8149 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT		9
8150 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUES_FLG_MASK	0x1
8151 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUES_FLG_SHIFT	10
8152 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK			0x1F
8153 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT			11
8154 	u8 fields;
8155 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK		0x7
8156 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT		0
8157 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK	0x1F
8158 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT	3
8159 	u8 max_ird;
8160 	u8 traffic_class;
8161 	u8 hop_limit;
8162 	__le16 p_key;
8163 	__le32 flow_label;
8164 	__le16 mtu;
8165 	__le16 low_latency_phy_queue;
8166 	__le16 regular_latency_phy_queue;
8167 	u8 reserved2[6];
8168 	__le32 src_gid[4];
8169 	__le32 dst_gid[4];
8170 };
8171 
8172 /* RoCE query qp requester output params */
8173 struct roce_query_qp_req_output_params {
8174 	__le32 psn;
8175 	__le32 flags;
8176 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK		0x1
8177 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT		0
8178 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK	0x1
8179 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT	1
8180 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK		0x3FFFFFFF
8181 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT		2
8182 };
8183 
8184 /* RoCE query qp requester ramrod data */
8185 struct roce_query_qp_req_ramrod_data {
8186 	struct regpair output_params_addr;
8187 };
8188 
8189 /* RoCE query qp responder output params */
8190 struct roce_query_qp_resp_output_params {
8191 	__le32 psn;
8192 	__le32 err_flag;
8193 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK  0x1
8194 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
8195 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK  0x7FFFFFFF
8196 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
8197 };
8198 
8199 /* RoCE query qp responder ramrod data */
8200 struct roce_query_qp_resp_ramrod_data {
8201 	struct regpair output_params_addr;
8202 };
8203 
8204 /* ROCE ramrod command IDs */
8205 enum roce_ramrod_cmd_id {
8206 	ROCE_RAMROD_CREATE_QP = 11,
8207 	ROCE_RAMROD_MODIFY_QP,
8208 	ROCE_RAMROD_QUERY_QP,
8209 	ROCE_RAMROD_DESTROY_QP,
8210 	ROCE_RAMROD_CREATE_UD_QP,
8211 	ROCE_RAMROD_DESTROY_UD_QP,
8212 	ROCE_RAMROD_FUNC_UPDATE,
8213 	MAX_ROCE_RAMROD_CMD_ID
8214 };
8215 
8216 /* RoCE func init ramrod data */
8217 struct roce_update_func_params {
8218 	u8 cnp_vlan_priority;
8219 	u8 cnp_dscp;
8220 	__le16 flags;
8221 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_MASK	0x1
8222 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_SHIFT	0
8223 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_RP_EN_MASK	0x1
8224 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_RP_EN_SHIFT	1
8225 #define ROCE_UPDATE_FUNC_PARAMS_RESERVED0_MASK		0x3FFF
8226 #define ROCE_UPDATE_FUNC_PARAMS_RESERVED0_SHIFT		2
8227 	__le32 cnp_send_timeout;
8228 };
8229 
8230 struct e4_xstorm_roce_conn_ag_ctx_dq_ext_ld_part {
8231 	u8 reserved0;
8232 	u8 state;
8233 	u8 flags0;
8234 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK	0x1
8235 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT	0
8236 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK		0x1
8237 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT		1
8238 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK		0x1
8239 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT		2
8240 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK	0x1
8241 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT	3
8242 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK		0x1
8243 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT		4
8244 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK		0x1
8245 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT		5
8246 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK		0x1
8247 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT		6
8248 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK		0x1
8249 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT		7
8250 	u8 flags1;
8251 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK		0x1
8252 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT		0
8253 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK		0x1
8254 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT		1
8255 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK		0x1
8256 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT		2
8257 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK		0x1
8258 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT		3
8259 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK		0x1
8260 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT		4
8261 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_MASK        0x1
8262 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_SHIFT       5
8263 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_MASK        0x1
8264 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_SHIFT       6
8265 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK	0x1
8266 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT	7
8267 	u8 flags2;
8268 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK	0x3
8269 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT	0
8270 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK	0x3
8271 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT	2
8272 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK	0x3
8273 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT	4
8274 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK	0x3
8275 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT	6
8276 	u8 flags3;
8277 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK		0x3
8278 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT		0
8279 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK		0x3
8280 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT		2
8281 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK		0x3
8282 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT		4
8283 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK	0x3
8284 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT	6
8285 	u8 flags4;
8286 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK	0x3
8287 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT	0
8288 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK	0x3
8289 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT	2
8290 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK	0x3
8291 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT	4
8292 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK	0x3
8293 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT	6
8294 	u8 flags5;
8295 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK	0x3
8296 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT	0
8297 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK	0x3
8298 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT	2
8299 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK	0x3
8300 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT	4
8301 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK	0x3
8302 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT	6
8303 	u8 flags6;
8304 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK	0x3
8305 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT	0
8306 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK	0x3
8307 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT	2
8308 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK	0x3
8309 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT	4
8310 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK	0x3
8311 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT	6
8312 	u8 flags7;
8313 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK		0x3
8314 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT		0
8315 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK		0x3
8316 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT		2
8317 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK		0x3
8318 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT	4
8319 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK		0x1
8320 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT		6
8321 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK		0x1
8322 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT		7
8323 	u8 flags8;
8324 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK		0x1
8325 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT		0
8326 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK		0x1
8327 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT		1
8328 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK		0x1
8329 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT		2
8330 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK		0x1
8331 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT		3
8332 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK		0x1
8333 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT		4
8334 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK	0x1
8335 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT	5
8336 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK		0x1
8337 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT		6
8338 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK		0x1
8339 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT		7
8340 	u8 flags9;
8341 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK	0x1
8342 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT	0
8343 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK	0x1
8344 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT	1
8345 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK	0x1
8346 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT	2
8347 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK	0x1
8348 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT	3
8349 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK	0x1
8350 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT	4
8351 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK	0x1
8352 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT	5
8353 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK	0x1
8354 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT	6
8355 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK	0x1
8356 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT	7
8357 	u8 flags10;
8358 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK		0x1
8359 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT		0
8360 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK		0x1
8361 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT		1
8362 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK		0x1
8363 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT		2
8364 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK		0x1
8365 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT		3
8366 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK	0x1
8367 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT	4
8368 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK		0x1
8369 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT		5
8370 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK		0x1
8371 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT		6
8372 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK		0x1
8373 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT		7
8374 	u8 flags11;
8375 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK		0x1
8376 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT		0
8377 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK		0x1
8378 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT		1
8379 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK		0x1
8380 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT		2
8381 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK		0x1
8382 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT		3
8383 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK		0x1
8384 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT		4
8385 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK		0x1
8386 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT		5
8387 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK	0x1
8388 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT	6
8389 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK		0x1
8390 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT		7
8391 	u8 flags12;
8392 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK		0x1
8393 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT		0
8394 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK		0x1
8395 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT		1
8396 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK	0x1
8397 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT	2
8398 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK	0x1
8399 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT	3
8400 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK		0x1
8401 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT		4
8402 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK		0x1
8403 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT		5
8404 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK		0x1
8405 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT		6
8406 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK		0x1
8407 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT		7
8408 	u8 flags13;
8409 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK		0x1
8410 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT		0
8411 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK		0x1
8412 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT		1
8413 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK	0x1
8414 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT	2
8415 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK	0x1
8416 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT	3
8417 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK	0x1
8418 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT	4
8419 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK	0x1
8420 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT	5
8421 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK	0x1
8422 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT	6
8423 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK	0x1
8424 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT	7
8425 	u8 flags14;
8426 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK		0x1
8427 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT	0
8428 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK		0x1
8429 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT		1
8430 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK	0x3
8431 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT	2
8432 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK		0x1
8433 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT		4
8434 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK	0x1
8435 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT	5
8436 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK		0x3
8437 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT		6
8438 	u8 byte2;
8439 	__le16 physical_q0;
8440 	__le16 word1;
8441 	__le16 word2;
8442 	__le16 word3;
8443 	__le16 word4;
8444 	__le16 word5;
8445 	__le16 conn_dpi;
8446 	u8 byte3;
8447 	u8 byte4;
8448 	u8 byte5;
8449 	u8 byte6;
8450 	__le32 reg0;
8451 	__le32 reg1;
8452 	__le32 reg2;
8453 	__le32 snd_nxt_psn;
8454 	__le32 reg4;
8455 };
8456 
8457 struct e4_mstorm_roce_conn_ag_ctx {
8458 	u8 byte0;
8459 	u8 byte1;
8460 	u8 flags0;
8461 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT0_MASK     0x1
8462 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT    0
8463 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT1_MASK     0x1
8464 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT    1
8465 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0_MASK      0x3
8466 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT     2
8467 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1_MASK      0x3
8468 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT     4
8469 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2_MASK      0x3
8470 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT     6
8471 	u8 flags1;
8472 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK    0x1
8473 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT   0
8474 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK    0x1
8475 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT   1
8476 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK    0x1
8477 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT   2
8478 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK  0x1
8479 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3
8480 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK  0x1
8481 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4
8482 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK  0x1
8483 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5
8484 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK  0x1
8485 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 6
8486 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK  0x1
8487 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7
8488 	__le16 word0;
8489 	__le16 word1;
8490 	__le32 reg0;
8491 	__le32 reg1;
8492 };
8493 
8494 struct e4_mstorm_roce_req_conn_ag_ctx {
8495 	u8 byte0;
8496 	u8 byte1;
8497 	u8 flags0;
8498 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK	0x1
8499 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT	0
8500 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK	0x1
8501 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT	1
8502 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK		0x3
8503 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT	2
8504 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK		0x3
8505 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT	4
8506 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK		0x3
8507 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT	6
8508 	u8 flags1;
8509 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK	0x1
8510 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT	0
8511 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK	0x1
8512 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT	1
8513 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK	0x1
8514 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT	2
8515 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK	0x1
8516 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT	3
8517 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK	0x1
8518 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT	4
8519 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK	0x1
8520 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT	5
8521 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK	0x1
8522 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT	6
8523 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK	0x1
8524 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT	7
8525 	__le16 word0;
8526 	__le16 word1;
8527 	__le32 reg0;
8528 	__le32 reg1;
8529 };
8530 
8531 struct e4_mstorm_roce_resp_conn_ag_ctx {
8532 	u8 byte0;
8533 	u8 byte1;
8534 	u8 flags0;
8535 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK	0x1
8536 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT	0
8537 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK	0x1
8538 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT	1
8539 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK	0x3
8540 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT	2
8541 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK	0x3
8542 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT	4
8543 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK	0x3
8544 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT	6
8545 	u8 flags1;
8546 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK	0x1
8547 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT	0
8548 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK	0x1
8549 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT	1
8550 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK	0x1
8551 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT	2
8552 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK	0x1
8553 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT	3
8554 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK	0x1
8555 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT	4
8556 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK	0x1
8557 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT	5
8558 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK	0x1
8559 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT	6
8560 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK	0x1
8561 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT	7
8562 	__le16 word0;
8563 	__le16 word1;
8564 	__le32 reg0;
8565 	__le32 reg1;
8566 };
8567 
8568 struct e4_tstorm_roce_req_conn_ag_ctx {
8569 	u8 reserved0;
8570 	u8 state;
8571 	u8 flags0;
8572 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK		0x1
8573 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT		0
8574 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_MASK		0x1
8575 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_SHIFT		1
8576 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_MASK	0x1
8577 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_SHIFT	2
8578 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK			0x1
8579 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT			3
8580 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK		0x1
8581 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT		4
8582 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK			0x1
8583 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT			5
8584 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK			0x3
8585 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT			6
8586 	u8 flags1;
8587 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK             0x3
8588 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT            0
8589 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK			0x3
8590 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT		2
8591 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK		0x3
8592 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT		4
8593 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK			0x3
8594 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT		6
8595 	u8 flags2;
8596 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_MASK               0x3
8597 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_SHIFT              0
8598 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK	0x3
8599 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT	2
8600 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK	0x3
8601 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT	4
8602 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK	0x3
8603 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT	6
8604 	u8 flags3;
8605 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK	0x3
8606 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT	0
8607 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK	0x3
8608 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT	2
8609 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK			0x1
8610 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT		4
8611 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK          0x1
8612 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT         5
8613 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK		0x1
8614 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT		6
8615 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK	0x1
8616 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT	7
8617 	u8 flags4;
8618 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK		0x1
8619 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT		0
8620 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_MASK            0x1
8621 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_SHIFT           1
8622 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK		0x1
8623 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT		2
8624 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK	0x1
8625 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT	3
8626 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK		0x1
8627 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT		4
8628 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK	0x1
8629 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT	5
8630 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK	0x1
8631 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT	6
8632 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK			0x1
8633 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT			7
8634 	u8 flags5;
8635 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK		0x1
8636 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT		0
8637 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK		0x1
8638 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT		1
8639 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK		0x1
8640 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT		2
8641 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK		0x1
8642 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT		3
8643 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK		0x1
8644 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT		4
8645 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK	0x1
8646 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT	5
8647 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK		0x1
8648 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT		6
8649 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK		0x1
8650 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT		7
8651 	__le32 reg0;
8652 	__le32 snd_nxt_psn;
8653 	__le32 snd_max_psn;
8654 	__le32 orq_prod;
8655 	__le32 reg4;
8656 	__le32 reg5;
8657 	__le32 reg6;
8658 	__le32 reg7;
8659 	__le32 reg8;
8660 	u8 tx_cqe_error_type;
8661 	u8 orq_cache_idx;
8662 	__le16 snd_sq_cons_th;
8663 	u8 byte4;
8664 	u8 byte5;
8665 	__le16 snd_sq_cons;
8666 	__le16 conn_dpi;
8667 	__le16 force_comp_cons;
8668 	__le32 reg9;
8669 	__le32 reg10;
8670 };
8671 
8672 struct e4_tstorm_roce_resp_conn_ag_ctx {
8673 	u8 byte0;
8674 	u8 state;
8675 	u8 flags0;
8676 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK		0x1
8677 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT		0
8678 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK	0x1
8679 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT	1
8680 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK			0x1
8681 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT			2
8682 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK			0x1
8683 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT			3
8684 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK		0x1
8685 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT		4
8686 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK			0x1
8687 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT			5
8688 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK			0x3
8689 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT			6
8690 	u8 flags1;
8691 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK            0x3
8692 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT           0
8693 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK	0x3
8694 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT	2
8695 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK		0x3
8696 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT		4
8697 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK	0x3
8698 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT	6
8699 	u8 flags2;
8700 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK                0x3
8701 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT               0
8702 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK		0x3
8703 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT		2
8704 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK		0x3
8705 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT		4
8706 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK		0x3
8707 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT		6
8708 	u8 flags3;
8709 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK		0x3
8710 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT		0
8711 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK		0x3
8712 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT		2
8713 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK		0x1
8714 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT		4
8715 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK         0x1
8716 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT        5
8717 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK	0x1
8718 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT	6
8719 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK		0x1
8720 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT		7
8721 	u8 flags4;
8722 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK		0x1
8723 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT		0
8724 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK             0x1
8725 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT            1
8726 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK			0x1
8727 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT			2
8728 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK			0x1
8729 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT			3
8730 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK			0x1
8731 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT			4
8732 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK			0x1
8733 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT			5
8734 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK			0x1
8735 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT			6
8736 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK			0x1
8737 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT			7
8738 	u8 flags5;
8739 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK		0x1
8740 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT		0
8741 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK		0x1
8742 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT		1
8743 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK		0x1
8744 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT		2
8745 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK		0x1
8746 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT		3
8747 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK		0x1
8748 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT		4
8749 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK		0x1
8750 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT	5
8751 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK		0x1
8752 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT		6
8753 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK		0x1
8754 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT		7
8755 	__le32 psn_and_rxmit_id_echo;
8756 	__le32 reg1;
8757 	__le32 reg2;
8758 	__le32 reg3;
8759 	__le32 reg4;
8760 	__le32 reg5;
8761 	__le32 reg6;
8762 	__le32 reg7;
8763 	__le32 reg8;
8764 	u8 tx_async_error_type;
8765 	u8 byte3;
8766 	__le16 rq_cons;
8767 	u8 byte4;
8768 	u8 byte5;
8769 	__le16 rq_prod;
8770 	__le16 conn_dpi;
8771 	__le16 irq_cons;
8772 	__le32 reg9;
8773 	__le32 reg10;
8774 };
8775 
8776 struct e4_ustorm_roce_req_conn_ag_ctx {
8777 	u8 byte0;
8778 	u8 byte1;
8779 	u8 flags0;
8780 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK	0x1
8781 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT	0
8782 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK	0x1
8783 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT	1
8784 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK		0x3
8785 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT	2
8786 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK		0x3
8787 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT	4
8788 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK		0x3
8789 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT	6
8790 	u8 flags1;
8791 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK		0x3
8792 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT	0
8793 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK		0x3
8794 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT	2
8795 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK		0x3
8796 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT	4
8797 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK		0x3
8798 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT	6
8799 	u8 flags2;
8800 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK	0x1
8801 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT	0
8802 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK	0x1
8803 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT	1
8804 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK	0x1
8805 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT	2
8806 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK	0x1
8807 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT	3
8808 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK	0x1
8809 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT	4
8810 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK	0x1
8811 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT	5
8812 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK	0x1
8813 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT	6
8814 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK	0x1
8815 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT	7
8816 	u8 flags3;
8817 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK	0x1
8818 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT	0
8819 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK	0x1
8820 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT	1
8821 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK	0x1
8822 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT	2
8823 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK	0x1
8824 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT	3
8825 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK	0x1
8826 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT	4
8827 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK	0x1
8828 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT	5
8829 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK	0x1
8830 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT	6
8831 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK	0x1
8832 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT	7
8833 	u8 byte2;
8834 	u8 byte3;
8835 	__le16 word0;
8836 	__le16 word1;
8837 	__le32 reg0;
8838 	__le32 reg1;
8839 	__le32 reg2;
8840 	__le32 reg3;
8841 	__le16 word2;
8842 	__le16 word3;
8843 };
8844 
8845 struct e4_ustorm_roce_resp_conn_ag_ctx {
8846 	u8 byte0;
8847 	u8 byte1;
8848 	u8 flags0;
8849 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK	0x1
8850 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT	0
8851 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK	0x1
8852 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT	1
8853 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK	0x3
8854 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT	2
8855 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK	0x3
8856 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT	4
8857 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK	0x3
8858 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT	6
8859 	u8 flags1;
8860 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK	0x3
8861 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT	0
8862 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK	0x3
8863 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT	2
8864 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK	0x3
8865 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT	4
8866 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK	0x3
8867 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT	6
8868 	u8 flags2;
8869 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK	0x1
8870 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT	0
8871 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK	0x1
8872 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT	1
8873 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK	0x1
8874 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT	2
8875 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK	0x1
8876 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT	3
8877 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK	0x1
8878 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT	4
8879 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK	0x1
8880 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT	5
8881 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK	0x1
8882 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT	6
8883 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK	0x1
8884 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT	7
8885 	u8 flags3;
8886 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK	0x1
8887 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT	0
8888 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK	0x1
8889 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT	1
8890 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK	0x1
8891 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT	2
8892 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK	0x1
8893 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT	3
8894 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK	0x1
8895 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT	4
8896 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK	0x1
8897 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT	5
8898 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK	0x1
8899 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT	6
8900 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK	0x1
8901 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT	7
8902 	u8 byte2;
8903 	u8 byte3;
8904 	__le16 word0;
8905 	__le16 word1;
8906 	__le32 reg0;
8907 	__le32 reg1;
8908 	__le32 reg2;
8909 	__le32 reg3;
8910 	__le16 word2;
8911 	__le16 word3;
8912 };
8913 
8914 struct e4_xstorm_roce_req_conn_ag_ctx {
8915 	u8 reserved0;
8916 	u8 state;
8917 	u8 flags0;
8918 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
8919 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
8920 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK		0x1
8921 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT		1
8922 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK		0x1
8923 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT		2
8924 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
8925 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT	3
8926 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK		0x1
8927 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT		4
8928 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK		0x1
8929 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT		5
8930 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK		0x1
8931 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT		6
8932 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK		0x1
8933 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT		7
8934 	u8 flags1;
8935 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK		0x1
8936 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT		0
8937 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK		0x1
8938 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT		1
8939 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK		0x1
8940 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT		2
8941 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK		0x1
8942 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT		3
8943 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK		0x1
8944 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT		4
8945 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK		0x1
8946 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT		5
8947 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK		0x1
8948 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT	6
8949 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK	0x1
8950 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT	7
8951 	u8 flags2;
8952 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK		0x3
8953 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT	0
8954 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK		0x3
8955 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT	2
8956 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK		0x3
8957 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT	4
8958 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK		0x3
8959 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT	6
8960 	u8 flags3;
8961 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK		0x3
8962 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT	0
8963 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK		0x3
8964 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT	2
8965 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK	0x3
8966 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT	4
8967 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK		0x3
8968 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT	6
8969 	u8 flags4;
8970 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_MASK        0x3
8971 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_SHIFT       0
8972 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_MASK     0x3
8973 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_SHIFT    2
8974 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK	0x3
8975 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT	4
8976 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK	0x3
8977 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT	6
8978 	u8 flags5;
8979 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK		0x3
8980 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT		0
8981 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK		0x3
8982 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT		2
8983 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK	0x3
8984 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT	4
8985 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK		0x3
8986 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT		6
8987 	u8 flags6;
8988 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK	0x3
8989 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT	0
8990 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK	0x3
8991 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT	2
8992 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK	0x3
8993 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT	4
8994 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK	0x3
8995 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT	6
8996 	u8 flags7;
8997 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK	0x3
8998 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT	0
8999 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK	0x3
9000 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT	2
9001 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK	0x3
9002 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT	4
9003 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK	0x1
9004 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT	6
9005 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK	0x1
9006 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT	7
9007 	u8 flags8;
9008 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK		0x1
9009 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT		0
9010 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK		0x1
9011 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT		1
9012 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK	0x1
9013 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT	2
9014 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK	0x1
9015 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT	3
9016 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK	0x1
9017 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT	4
9018 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK	0x1
9019 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT	5
9020 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_MASK     0x1
9021 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_SHIFT    6
9022 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_MASK  0x1
9023 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_SHIFT 7
9024 	u8 flags9;
9025 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK		0x1
9026 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT		0
9027 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK		0x1
9028 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT		1
9029 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK		0x1
9030 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT		2
9031 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK		0x1
9032 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT		3
9033 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK	0x1
9034 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT	4
9035 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK		0x1
9036 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT		5
9037 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK		0x1
9038 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT		6
9039 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK		0x1
9040 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT		7
9041 	u8 flags10;
9042 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK		0x1
9043 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT		0
9044 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK		0x1
9045 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT		1
9046 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK		0x1
9047 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT		2
9048 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK		0x1
9049 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT		3
9050 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK	0x1
9051 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT	4
9052 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK		0x1
9053 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT		5
9054 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK		0x1
9055 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT		6
9056 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK		0x1
9057 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT		7
9058 	u8 flags11;
9059 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK		0x1
9060 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT		0
9061 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK		0x1
9062 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT		1
9063 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK		0x1
9064 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT		2
9065 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK		0x1
9066 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT		3
9067 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK		0x1
9068 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT		4
9069 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK	0x1
9070 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT	5
9071 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK	0x1
9072 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT	6
9073 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK		0x1
9074 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT		7
9075 	u8 flags12;
9076 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK		0x1
9077 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT		0
9078 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK		0x1
9079 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT		1
9080 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK	0x1
9081 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT	2
9082 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK	0x1
9083 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT	3
9084 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK	0x1
9085 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT	4
9086 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK		0x1
9087 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT		5
9088 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK	0x1
9089 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT	6
9090 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK	0x1
9091 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT	7
9092 	u8 flags13;
9093 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK		0x1
9094 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT		0
9095 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK		0x1
9096 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT		1
9097 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK	0x1
9098 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT	2
9099 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK	0x1
9100 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT	3
9101 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK	0x1
9102 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT	4
9103 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK	0x1
9104 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT	5
9105 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK	0x1
9106 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT	6
9107 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK	0x1
9108 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT	7
9109 	u8 flags14;
9110 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK	0x1
9111 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT	0
9112 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK		0x1
9113 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT		1
9114 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK	0x3
9115 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT	2
9116 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK		0x1
9117 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT		4
9118 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK	0x1
9119 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT	5
9120 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK		0x3
9121 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT		6
9122 	u8 byte2;
9123 	__le16 physical_q0;
9124 	__le16 word1;
9125 	__le16 sq_cmp_cons;
9126 	__le16 sq_cons;
9127 	__le16 sq_prod;
9128 	__le16 dif_error_first_sq_cons;
9129 	__le16 conn_dpi;
9130 	u8 dif_error_sge_index;
9131 	u8 byte4;
9132 	u8 byte5;
9133 	u8 byte6;
9134 	__le32 lsn;
9135 	__le32 ssn;
9136 	__le32 snd_una_psn;
9137 	__le32 snd_nxt_psn;
9138 	__le32 dif_error_offset;
9139 	__le32 orq_cons_th;
9140 	__le32 orq_cons;
9141 };
9142 
9143 struct e4_xstorm_roce_resp_conn_ag_ctx {
9144 	u8 reserved0;
9145 	u8 state;
9146 	u8 flags0;
9147 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
9148 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
9149 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK		0x1
9150 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT		1
9151 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK		0x1
9152 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT		2
9153 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
9154 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT	3
9155 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK		0x1
9156 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT		4
9157 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK		0x1
9158 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT		5
9159 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK		0x1
9160 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT		6
9161 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK		0x1
9162 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT		7
9163 	u8 flags1;
9164 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK		0x1
9165 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT		0
9166 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK		0x1
9167 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT		1
9168 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK		0x1
9169 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT		2
9170 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK		0x1
9171 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT		3
9172 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK		0x1
9173 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT		4
9174 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK		0x1
9175 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT		5
9176 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK	0x1
9177 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT	6
9178 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK	0x1
9179 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT	7
9180 	u8 flags2;
9181 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK	0x3
9182 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT	0
9183 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK	0x3
9184 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT	2
9185 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK	0x3
9186 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT	4
9187 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK	0x3
9188 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT	6
9189 	u8 flags3;
9190 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK		0x3
9191 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT		0
9192 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK	0x3
9193 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT	2
9194 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK	0x3
9195 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT	4
9196 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK	0x3
9197 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT	6
9198 	u8 flags4;
9199 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK	0x3
9200 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT	0
9201 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK	0x3
9202 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT	2
9203 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK	0x3
9204 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT	4
9205 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK	0x3
9206 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT	6
9207 	u8 flags5;
9208 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK	0x3
9209 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT	0
9210 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK	0x3
9211 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT	2
9212 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK	0x3
9213 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT	4
9214 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK	0x3
9215 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT	6
9216 	u8 flags6;
9217 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK	0x3
9218 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT	0
9219 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK	0x3
9220 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT	2
9221 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK	0x3
9222 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT	4
9223 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK	0x3
9224 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT	6
9225 	u8 flags7;
9226 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK	0x3
9227 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT	0
9228 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK	0x3
9229 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT	2
9230 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK	0x3
9231 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT	4
9232 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK	0x1
9233 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT	6
9234 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK	0x1
9235 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT	7
9236 	u8 flags8;
9237 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK		0x1
9238 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT		0
9239 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK		0x1
9240 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT		1
9241 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK	0x1
9242 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT	2
9243 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK	0x1
9244 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT	3
9245 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK	0x1
9246 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT	4
9247 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK	0x1
9248 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT	5
9249 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK		0x1
9250 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT		6
9251 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK		0x1
9252 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT		7
9253 	u8 flags9;
9254 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK	0x1
9255 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT	0
9256 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK	0x1
9257 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT	1
9258 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK	0x1
9259 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT	2
9260 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK	0x1
9261 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT	3
9262 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK	0x1
9263 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT	4
9264 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK	0x1
9265 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT	5
9266 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK	0x1
9267 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT	6
9268 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK	0x1
9269 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT	7
9270 	u8 flags10;
9271 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK		0x1
9272 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT		0
9273 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK		0x1
9274 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT		1
9275 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK		0x1
9276 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT		2
9277 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK		0x1
9278 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT		3
9279 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK	0x1
9280 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT	4
9281 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK		0x1
9282 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT		5
9283 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK		0x1
9284 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT		6
9285 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK		0x1
9286 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT		7
9287 	u8 flags11;
9288 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK		0x1
9289 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT		0
9290 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK		0x1
9291 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT		1
9292 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK		0x1
9293 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT		2
9294 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK		0x1
9295 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT		3
9296 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK		0x1
9297 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT		4
9298 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK		0x1
9299 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT		5
9300 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK	0x1
9301 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT	6
9302 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK		0x1
9303 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT		7
9304 	u8 flags12;
9305 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK	0x1
9306 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT	0
9307 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_MASK		0x1
9308 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_SHIFT		1
9309 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK	0x1
9310 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT	2
9311 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK	0x1
9312 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT	3
9313 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK		0x1
9314 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT		4
9315 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK		0x1
9316 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT		5
9317 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK		0x1
9318 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT		6
9319 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK		0x1
9320 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT		7
9321 	u8 flags13;
9322 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK		0x1
9323 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT		0
9324 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK		0x1
9325 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT		1
9326 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK	0x1
9327 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT	2
9328 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK	0x1
9329 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT	3
9330 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK	0x1
9331 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT	4
9332 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK	0x1
9333 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT	5
9334 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK	0x1
9335 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT	6
9336 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK	0x1
9337 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT	7
9338 	u8 flags14;
9339 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK	0x1
9340 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT	0
9341 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK	0x1
9342 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT	1
9343 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK	0x1
9344 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT	2
9345 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK	0x1
9346 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT	3
9347 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK	0x1
9348 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT	4
9349 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK	0x1
9350 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT	5
9351 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK	0x3
9352 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT	6
9353 	u8 byte2;
9354 	__le16 physical_q0;
9355 	__le16 irq_prod_shadow;
9356 	__le16 word2;
9357 	__le16 irq_cons;
9358 	__le16 irq_prod;
9359 	__le16 e5_reserved1;
9360 	__le16 conn_dpi;
9361 	u8 rxmit_opcode;
9362 	u8 byte4;
9363 	u8 byte5;
9364 	u8 byte6;
9365 	__le32 rxmit_psn_and_id;
9366 	__le32 rxmit_bytes_length;
9367 	__le32 psn;
9368 	__le32 reg3;
9369 	__le32 reg4;
9370 	__le32 reg5;
9371 	__le32 msn_and_syndrome;
9372 };
9373 
9374 struct e4_ystorm_roce_conn_ag_ctx {
9375 	u8 byte0;
9376 	u8 byte1;
9377 	u8 flags0;
9378 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT0_MASK     0x1
9379 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT    0
9380 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT1_MASK     0x1
9381 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT    1
9382 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0_MASK      0x3
9383 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT     2
9384 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1_MASK      0x3
9385 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT     4
9386 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2_MASK      0x3
9387 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT     6
9388 	u8 flags1;
9389 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK    0x1
9390 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT   0
9391 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK    0x1
9392 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT   1
9393 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK    0x1
9394 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT   2
9395 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK  0x1
9396 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3
9397 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK  0x1
9398 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4
9399 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK  0x1
9400 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5
9401 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK  0x1
9402 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 6
9403 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK  0x1
9404 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7
9405 	u8 byte2;
9406 	u8 byte3;
9407 	__le16 word0;
9408 	__le32 reg0;
9409 	__le32 reg1;
9410 	__le16 word1;
9411 	__le16 word2;
9412 	__le16 word3;
9413 	__le16 word4;
9414 	__le32 reg2;
9415 	__le32 reg3;
9416 };
9417 
9418 struct e4_ystorm_roce_req_conn_ag_ctx {
9419 	u8 byte0;
9420 	u8 byte1;
9421 	u8 flags0;
9422 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK	0x1
9423 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT	0
9424 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK	0x1
9425 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT	1
9426 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK		0x3
9427 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT	2
9428 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK		0x3
9429 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT	4
9430 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK		0x3
9431 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT	6
9432 	u8 flags1;
9433 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK	0x1
9434 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT	0
9435 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK	0x1
9436 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT	1
9437 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK	0x1
9438 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT	2
9439 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK	0x1
9440 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT	3
9441 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK	0x1
9442 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT	4
9443 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK	0x1
9444 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT	5
9445 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK	0x1
9446 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT	6
9447 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK	0x1
9448 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT	7
9449 	u8 byte2;
9450 	u8 byte3;
9451 	__le16 word0;
9452 	__le32 reg0;
9453 	__le32 reg1;
9454 	__le16 word1;
9455 	__le16 word2;
9456 	__le16 word3;
9457 	__le16 word4;
9458 	__le32 reg2;
9459 	__le32 reg3;
9460 };
9461 
9462 struct e4_ystorm_roce_resp_conn_ag_ctx {
9463 	u8 byte0;
9464 	u8 byte1;
9465 	u8 flags0;
9466 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK	0x1
9467 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT	0
9468 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK	0x1
9469 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT	1
9470 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK	0x3
9471 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT	2
9472 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK	0x3
9473 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT	4
9474 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK	0x3
9475 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT	6
9476 	u8 flags1;
9477 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK	0x1
9478 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT	0
9479 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK	0x1
9480 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT	1
9481 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK	0x1
9482 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT	2
9483 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK	0x1
9484 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT	3
9485 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK	0x1
9486 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT	4
9487 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK	0x1
9488 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT	5
9489 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK	0x1
9490 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT	6
9491 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK	0x1
9492 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT	7
9493 	u8 byte2;
9494 	u8 byte3;
9495 	__le16 word0;
9496 	__le32 reg0;
9497 	__le32 reg1;
9498 	__le16 word1;
9499 	__le16 word2;
9500 	__le16 word3;
9501 	__le16 word4;
9502 	__le32 reg2;
9503 	__le32 reg3;
9504 };
9505 
9506 /* Roce doorbell data */
9507 enum roce_flavor {
9508 	PLAIN_ROCE,
9509 	RROCE_IPV4,
9510 	RROCE_IPV6,
9511 	MAX_ROCE_FLAVOR
9512 };
9513 
9514 /* The iwarp storm context of Ystorm */
9515 struct ystorm_iwarp_conn_st_ctx {
9516 	__le32 reserved[4];
9517 };
9518 
9519 /* The iwarp storm context of Pstorm */
9520 struct pstorm_iwarp_conn_st_ctx {
9521 	__le32 reserved[36];
9522 };
9523 
9524 /* The iwarp storm context of Xstorm */
9525 struct xstorm_iwarp_conn_st_ctx {
9526 	__le32 reserved[48];
9527 };
9528 
9529 struct e4_xstorm_iwarp_conn_ag_ctx {
9530 	u8 reserved0;
9531 	u8 state;
9532 	u8 flags0;
9533 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
9534 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
9535 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK	0x1
9536 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_SHIFT	1
9537 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK	0x1
9538 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_SHIFT	2
9539 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
9540 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT	3
9541 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK		0x1
9542 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT		4
9543 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK	0x1
9544 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT	5
9545 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK		0x1
9546 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT		6
9547 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK		0x1
9548 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT		7
9549 	u8 flags1;
9550 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK				0x1
9551 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT				0
9552 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK				0x1
9553 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT				1
9554 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK				0x1
9555 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT				2
9556 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK				0x1
9557 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT				3
9558 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK				0x1
9559 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT				4
9560 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK				0x1
9561 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT				5
9562 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK				0x1
9563 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT				6
9564 #define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK	0x1
9565 #define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7
9566 	u8 flags2;
9567 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_MASK			0x3
9568 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT			0
9569 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_MASK			0x3
9570 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT			2
9571 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_MASK			0x3
9572 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT			4
9573 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK		0x3
9574 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT	6
9575 	u8 flags3;
9576 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_MASK	0x3
9577 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT	0
9578 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_MASK	0x3
9579 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT	2
9580 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_MASK	0x3
9581 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT	4
9582 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_MASK	0x3
9583 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT	6
9584 	u8 flags4;
9585 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_MASK	0x3
9586 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT	0
9587 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_MASK	0x3
9588 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_SHIFT	2
9589 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_MASK	0x3
9590 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT	4
9591 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_MASK	0x3
9592 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT	6
9593 	u8 flags5;
9594 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_MASK		0x3
9595 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT		0
9596 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_MASK		0x3
9597 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT		2
9598 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK	0x3
9599 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT	4
9600 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_MASK		0x3
9601 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT		6
9602 	u8 flags6;
9603 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK	0x3
9604 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0
9605 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_MASK				0x3
9606 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT				2
9607 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_MASK				0x3
9608 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT				4
9609 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK			0x3
9610 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT			6
9611 	u8 flags7;
9612 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK	0x3
9613 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT	0
9614 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK	0x3
9615 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT	2
9616 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK	0x3
9617 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT	4
9618 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK		0x1
9619 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT		6
9620 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK		0x1
9621 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT		7
9622 	u8 flags8;
9623 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK			0x1
9624 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT			0
9625 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK	0x1
9626 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT	1
9627 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK			0x1
9628 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT			2
9629 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK			0x1
9630 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT			3
9631 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK			0x1
9632 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT			4
9633 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK			0x1
9634 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT			5
9635 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK			0x1
9636 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT			6
9637 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK			0x1
9638 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT			7
9639 	u8 flags9;
9640 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK				0x1
9641 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT			0
9642 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK				0x1
9643 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT			1
9644 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK				0x1
9645 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT			2
9646 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK				0x1
9647 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT			3
9648 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK			0x1
9649 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT		4
9650 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK				0x1
9651 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT			5
9652 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1
9653 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6
9654 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK				0x1
9655 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT			7
9656 	u8 flags10;
9657 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK			0x1
9658 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT		0
9659 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK		0x1
9660 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT		1
9661 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK		0x1
9662 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT		2
9663 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK		0x1
9664 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT		3
9665 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK		0x1
9666 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT		4
9667 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_MASK               0x1
9668 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_SHIFT              5
9669 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK		0x1
9670 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT		6
9671 #define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK	0x1
9672 #define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT	7
9673 	u8 flags11;
9674 #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK	0x1
9675 #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT	0
9676 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK	0x1
9677 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT	1
9678 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK	0x1
9679 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT	2
9680 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK	0x1
9681 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT	3
9682 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK	0x1
9683 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT	4
9684 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK	0x1
9685 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT	5
9686 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK	0x1
9687 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT	6
9688 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK	0x1
9689 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT	7
9690 	u8 flags12;
9691 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK	0x1
9692 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT	0
9693 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK		0x1
9694 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT		1
9695 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK		0x1
9696 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT		2
9697 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK		0x1
9698 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT		3
9699 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK	0x1
9700 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT	4
9701 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK		0x1
9702 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT		5
9703 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK		0x1
9704 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT		6
9705 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK		0x1
9706 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT		7
9707 	u8 flags13;
9708 #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK	0x1
9709 #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT	0
9710 #define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK	0x1
9711 #define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT	1
9712 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK	0x1
9713 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT	2
9714 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK		0x1
9715 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT		3
9716 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK		0x1
9717 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT		4
9718 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK	0x1
9719 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT	5
9720 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK		0x1
9721 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT		6
9722 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK		0x1
9723 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT		7
9724 	u8 flags14;
9725 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK		0x1
9726 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT		0
9727 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK		0x1
9728 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT		1
9729 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK		0x1
9730 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_SHIFT		2
9731 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK	0x1
9732 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_SHIFT	3
9733 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK	0x1
9734 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_SHIFT	4
9735 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK	0x1
9736 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_SHIFT	5
9737 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_MASK	0x3
9738 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_SHIFT	6
9739 	u8 byte2;
9740 	__le16 physical_q0;
9741 	__le16 physical_q1;
9742 	__le16 sq_comp_cons;
9743 	__le16 sq_tx_cons;
9744 	__le16 sq_prod;
9745 	__le16 word5;
9746 	__le16 conn_dpi;
9747 	u8 byte3;
9748 	u8 byte4;
9749 	u8 byte5;
9750 	u8 byte6;
9751 	__le32 reg0;
9752 	__le32 reg1;
9753 	__le32 reg2;
9754 	__le32 more_to_send_seq;
9755 	__le32 reg4;
9756 	__le32 rewinded_snd_max_or_term_opcode;
9757 	__le32 rd_msn;
9758 	__le16 irq_prod_via_msdm;
9759 	__le16 irq_cons;
9760 	__le16 hq_cons_th_or_mpa_data;
9761 	__le16 hq_cons;
9762 	__le32 atom_msn;
9763 	__le32 orq_cons;
9764 	__le32 orq_cons_th;
9765 	u8 byte7;
9766 	u8 wqe_data_pad_bytes;
9767 	u8 max_ord;
9768 	u8 former_hq_prod;
9769 	u8 irq_prod_via_msem;
9770 	u8 byte12;
9771 	u8 max_pkt_pdu_size_lo;
9772 	u8 max_pkt_pdu_size_hi;
9773 	u8 byte15;
9774 	u8 e5_reserved;
9775 	__le16 e5_reserved4;
9776 	__le32 reg10;
9777 	__le32 reg11;
9778 	__le32 shared_queue_page_addr_lo;
9779 	__le32 shared_queue_page_addr_hi;
9780 	__le32 reg14;
9781 	__le32 reg15;
9782 	__le32 reg16;
9783 	__le32 reg17;
9784 };
9785 
9786 struct e4_tstorm_iwarp_conn_ag_ctx {
9787 	u8 reserved0;
9788 	u8 state;
9789 	u8 flags0;
9790 #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
9791 #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
9792 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK		0x1
9793 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT		1
9794 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK		0x1
9795 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT		2
9796 #define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_MASK  0x1
9797 #define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_SHIFT 3
9798 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK		0x1
9799 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT		4
9800 #define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK	0x1
9801 #define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT	5
9802 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_MASK		0x3
9803 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT		6
9804 	u8 flags1;
9805 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK		0x3
9806 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT		0
9807 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK		0x3
9808 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_SHIFT	2
9809 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK		0x3
9810 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT	4
9811 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_MASK			0x3
9812 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT			6
9813 	u8 flags2;
9814 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_MASK	0x3
9815 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT	0
9816 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_MASK	0x3
9817 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT	2
9818 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_MASK	0x3
9819 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT	4
9820 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_MASK	0x3
9821 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT	6
9822 	u8 flags3;
9823 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_MASK 0x3
9824 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_SHIFT 0
9825 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK	0x3
9826 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT	2
9827 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK				0x1
9828 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT				4
9829 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK			0x1
9830 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT			5
9831 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK		0x1
9832 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_SHIFT		6
9833 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK		0x1
9834 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT		7
9835 	u8 flags4;
9836 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK				0x1
9837 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT				0
9838 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK				0x1
9839 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT				1
9840 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK				0x1
9841 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT				2
9842 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK				0x1
9843 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT				3
9844 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK				0x1
9845 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT				4
9846 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_MASK 0x1
9847 #define	E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_SHIFT 5
9848 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK	0x1
9849 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT	6
9850 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK			0x1
9851 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT			7
9852 	u8 flags5;
9853 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK		0x1
9854 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT		0
9855 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK		0x1
9856 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT		1
9857 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK		0x1
9858 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT		2
9859 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK		0x1
9860 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT		3
9861 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK		0x1
9862 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT		4
9863 #define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK	0x1
9864 #define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT	5
9865 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK		0x1
9866 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT		6
9867 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK		0x1
9868 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT		7
9869 	__le32 reg0;
9870 	__le32 reg1;
9871 	__le32 unaligned_nxt_seq;
9872 	__le32 reg3;
9873 	__le32 reg4;
9874 	__le32 reg5;
9875 	__le32 reg6;
9876 	__le32 reg7;
9877 	__le32 reg8;
9878 	u8 orq_cache_idx;
9879 	u8 hq_prod;
9880 	__le16 sq_tx_cons_th;
9881 	u8 orq_prod;
9882 	u8 irq_cons;
9883 	__le16 sq_tx_cons;
9884 	__le16 conn_dpi;
9885 	__le16 rq_prod;
9886 	__le32 snd_seq;
9887 	__le32 last_hq_sequence;
9888 };
9889 
9890 /* The iwarp storm context of Tstorm */
9891 struct tstorm_iwarp_conn_st_ctx {
9892 	__le32 reserved[60];
9893 };
9894 
9895 /* The iwarp storm context of Mstorm */
9896 struct mstorm_iwarp_conn_st_ctx {
9897 	__le32 reserved[32];
9898 };
9899 
9900 /* The iwarp storm context of Ustorm */
9901 struct ustorm_iwarp_conn_st_ctx {
9902 	__le32 reserved[24];
9903 };
9904 
9905 /* iwarp connection context */
9906 struct e4_iwarp_conn_context {
9907 	struct ystorm_iwarp_conn_st_ctx ystorm_st_context;
9908 	struct regpair ystorm_st_padding[2];
9909 	struct pstorm_iwarp_conn_st_ctx pstorm_st_context;
9910 	struct regpair pstorm_st_padding[2];
9911 	struct xstorm_iwarp_conn_st_ctx xstorm_st_context;
9912 	struct e4_xstorm_iwarp_conn_ag_ctx xstorm_ag_context;
9913 	struct e4_tstorm_iwarp_conn_ag_ctx tstorm_ag_context;
9914 	struct timers_context timer_context;
9915 	struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context;
9916 	struct tstorm_iwarp_conn_st_ctx tstorm_st_context;
9917 	struct regpair tstorm_st_padding[2];
9918 	struct mstorm_iwarp_conn_st_ctx mstorm_st_context;
9919 	struct ustorm_iwarp_conn_st_ctx ustorm_st_context;
9920 };
9921 
9922 /* iWARP create QP params passed by driver to FW in CreateQP Request Ramrod */
9923 struct iwarp_create_qp_ramrod_data {
9924 	u8 flags;
9925 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK	0x1
9926 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT	0
9927 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK		0x1
9928 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_SHIFT		1
9929 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK		0x1
9930 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT		2
9931 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK		0x1
9932 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT		3
9933 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK		0x1
9934 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_SHIFT		4
9935 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK		0x1
9936 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_SHIFT		5
9937 #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_MASK	0x1
9938 #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_SHIFT	6
9939 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK		0x1
9940 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_SHIFT		7
9941 	u8 reserved1;
9942 	__le16 pd;
9943 	__le16 sq_num_pages;
9944 	__le16 rq_num_pages;
9945 	__le32 reserved3[2];
9946 	struct regpair qp_handle_for_cqe;
9947 	struct rdma_srq_id srq_id;
9948 	__le32 cq_cid_for_sq;
9949 	__le32 cq_cid_for_rq;
9950 	__le16 dpi;
9951 	__le16 physical_q0;
9952 	__le16 physical_q1;
9953 	u8 reserved2[6];
9954 };
9955 
9956 /* iWARP completion queue types */
9957 enum iwarp_eqe_async_opcode {
9958 	IWARP_EVENT_TYPE_ASYNC_CONNECT_COMPLETE,
9959 	IWARP_EVENT_TYPE_ASYNC_ENHANCED_MPA_REPLY_ARRIVED,
9960 	IWARP_EVENT_TYPE_ASYNC_MPA_HANDSHAKE_COMPLETE,
9961 	IWARP_EVENT_TYPE_ASYNC_CID_CLEANED,
9962 	IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED,
9963 	IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE,
9964 	IWARP_EVENT_TYPE_ASYNC_CQ_OVERFLOW,
9965 	IWARP_EVENT_TYPE_ASYNC_SRQ_EMPTY,
9966 	IWARP_EVENT_TYPE_ASYNC_SRQ_LIMIT,
9967 	MAX_IWARP_EQE_ASYNC_OPCODE
9968 };
9969 
9970 struct iwarp_eqe_data_mpa_async_completion {
9971 	__le16 ulp_data_len;
9972 	u8 reserved[6];
9973 };
9974 
9975 struct iwarp_eqe_data_tcp_async_completion {
9976 	__le16 ulp_data_len;
9977 	u8 mpa_handshake_mode;
9978 	u8 reserved[5];
9979 };
9980 
9981 /* iWARP completion queue types */
9982 enum iwarp_eqe_sync_opcode {
9983 	IWARP_EVENT_TYPE_TCP_OFFLOAD =
9984 	11,
9985 	IWARP_EVENT_TYPE_MPA_OFFLOAD,
9986 	IWARP_EVENT_TYPE_MPA_OFFLOAD_SEND_RTR,
9987 	IWARP_EVENT_TYPE_CREATE_QP,
9988 	IWARP_EVENT_TYPE_QUERY_QP,
9989 	IWARP_EVENT_TYPE_MODIFY_QP,
9990 	IWARP_EVENT_TYPE_DESTROY_QP,
9991 	IWARP_EVENT_TYPE_ABORT_TCP_OFFLOAD,
9992 	MAX_IWARP_EQE_SYNC_OPCODE
9993 };
9994 
9995 /* iWARP EQE completion status */
9996 enum iwarp_fw_return_code {
9997 	IWARP_CONN_ERROR_TCP_CONNECT_INVALID_PACKET = 5,
9998 	IWARP_CONN_ERROR_TCP_CONNECTION_RST,
9999 	IWARP_CONN_ERROR_TCP_CONNECT_TIMEOUT,
10000 	IWARP_CONN_ERROR_MPA_ERROR_REJECT,
10001 	IWARP_CONN_ERROR_MPA_NOT_SUPPORTED_VER,
10002 	IWARP_CONN_ERROR_MPA_RST,
10003 	IWARP_CONN_ERROR_MPA_FIN,
10004 	IWARP_CONN_ERROR_MPA_RTR_MISMATCH,
10005 	IWARP_CONN_ERROR_MPA_INSUF_IRD,
10006 	IWARP_CONN_ERROR_MPA_INVALID_PACKET,
10007 	IWARP_CONN_ERROR_MPA_LOCAL_ERROR,
10008 	IWARP_CONN_ERROR_MPA_TIMEOUT,
10009 	IWARP_CONN_ERROR_MPA_TERMINATE,
10010 	IWARP_QP_IN_ERROR_GOOD_CLOSE,
10011 	IWARP_QP_IN_ERROR_BAD_CLOSE,
10012 	IWARP_EXCEPTION_DETECTED_LLP_CLOSED,
10013 	IWARP_EXCEPTION_DETECTED_LLP_RESET,
10014 	IWARP_EXCEPTION_DETECTED_IRQ_FULL,
10015 	IWARP_EXCEPTION_DETECTED_RQ_EMPTY,
10016 	IWARP_EXCEPTION_DETECTED_SRQ_EMPTY,
10017 	IWARP_EXCEPTION_DETECTED_SRQ_LIMIT,
10018 	IWARP_EXCEPTION_DETECTED_LLP_TIMEOUT,
10019 	IWARP_EXCEPTION_DETECTED_REMOTE_PROTECTION_ERROR,
10020 	IWARP_EXCEPTION_DETECTED_CQ_OVERFLOW,
10021 	IWARP_EXCEPTION_DETECTED_LOCAL_CATASTROPHIC,
10022 	IWARP_EXCEPTION_DETECTED_LOCAL_ACCESS_ERROR,
10023 	IWARP_EXCEPTION_DETECTED_REMOTE_OPERATION_ERROR,
10024 	IWARP_EXCEPTION_DETECTED_TERMINATE_RECEIVED,
10025 	MAX_IWARP_FW_RETURN_CODE
10026 };
10027 
10028 /* unaligned opaque data received from LL2 */
10029 struct iwarp_init_func_params {
10030 	u8 ll2_ooo_q_index;
10031 	u8 reserved1[7];
10032 };
10033 
10034 /* iwarp func init ramrod data */
10035 struct iwarp_init_func_ramrod_data {
10036 	struct rdma_init_func_ramrod_data rdma;
10037 	struct tcp_init_params tcp;
10038 	struct iwarp_init_func_params iwarp;
10039 };
10040 
10041 /* iWARP QP - possible states to transition to */
10042 enum iwarp_modify_qp_new_state_type {
10043 	IWARP_MODIFY_QP_STATE_CLOSING = 1,
10044 	IWARP_MODIFY_QP_STATE_ERROR = 2,
10045 	MAX_IWARP_MODIFY_QP_NEW_STATE_TYPE
10046 };
10047 
10048 /* iwarp modify qp responder ramrod data */
10049 struct iwarp_modify_qp_ramrod_data {
10050 	__le16 transition_to_state;
10051 	__le16 flags;
10052 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK		0x1
10053 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT		0
10054 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK		0x1
10055 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT		1
10056 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK		0x1
10057 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_SHIFT		2
10058 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK		0x1
10059 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_SHIFT	3
10060 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK	0x1
10061 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT	4
10062 #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK	0x1
10063 #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT	5
10064 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK		0x3FF
10065 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_SHIFT		6
10066 	__le16 physical_q0;
10067 	__le16 physical_q1;
10068 	__le32 reserved1[10];
10069 };
10070 
10071 /* MPA params for Enhanced mode */
10072 struct mpa_rq_params {
10073 	__le32 ird;
10074 	__le32 ord;
10075 };
10076 
10077 /* MPA host Address-Len for private data */
10078 struct mpa_ulp_buffer {
10079 	struct regpair addr;
10080 	__le16 len;
10081 	__le16 reserved[3];
10082 };
10083 
10084 /* iWARP MPA offload params common to Basic and Enhanced modes */
10085 struct mpa_outgoing_params {
10086 	u8 crc_needed;
10087 	u8 reject;
10088 	u8 reserved[6];
10089 	struct mpa_rq_params out_rq;
10090 	struct mpa_ulp_buffer outgoing_ulp_buffer;
10091 };
10092 
10093 /* iWARP MPA offload params passed by driver to FW in MPA Offload Request
10094  * Ramrod.
10095  */
10096 struct iwarp_mpa_offload_ramrod_data {
10097 	struct mpa_outgoing_params common;
10098 	__le32 tcp_cid;
10099 	u8 mode;
10100 	u8 tcp_connect_side;
10101 	u8 rtr_pref;
10102 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_MASK	0x7
10103 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT	0
10104 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK		0x1F
10105 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_SHIFT		3
10106 	u8 reserved2;
10107 	struct mpa_ulp_buffer incoming_ulp_buffer;
10108 	struct regpair async_eqe_output_buf;
10109 	struct regpair handle_for_async;
10110 	struct regpair shared_queue_addr;
10111 	__le16 rcv_wnd;
10112 	u8 stats_counter_id;
10113 	u8 reserved3[13];
10114 };
10115 
10116 /* iWARP TCP connection offload params passed by driver to FW */
10117 struct iwarp_offload_params {
10118 	struct mpa_ulp_buffer incoming_ulp_buffer;
10119 	struct regpair async_eqe_output_buf;
10120 	struct regpair handle_for_async;
10121 	__le16 physical_q0;
10122 	__le16 physical_q1;
10123 	u8 stats_counter_id;
10124 	u8 mpa_mode;
10125 	u8 reserved[10];
10126 };
10127 
10128 /* iWARP query QP output params */
10129 struct iwarp_query_qp_output_params {
10130 	__le32 flags;
10131 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK	0x1
10132 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT	0
10133 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_MASK	0x7FFFFFFF
10134 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_SHIFT	1
10135 	u8 reserved1[4];
10136 };
10137 
10138 /* iWARP query QP ramrod data */
10139 struct iwarp_query_qp_ramrod_data {
10140 	struct regpair output_params_addr;
10141 };
10142 
10143 /* iWARP Ramrod Command IDs */
10144 enum iwarp_ramrod_cmd_id {
10145 	IWARP_RAMROD_CMD_ID_TCP_OFFLOAD = 11,
10146 	IWARP_RAMROD_CMD_ID_MPA_OFFLOAD,
10147 	IWARP_RAMROD_CMD_ID_MPA_OFFLOAD_SEND_RTR,
10148 	IWARP_RAMROD_CMD_ID_CREATE_QP,
10149 	IWARP_RAMROD_CMD_ID_QUERY_QP,
10150 	IWARP_RAMROD_CMD_ID_MODIFY_QP,
10151 	IWARP_RAMROD_CMD_ID_DESTROY_QP,
10152 	IWARP_RAMROD_CMD_ID_ABORT_TCP_OFFLOAD,
10153 	MAX_IWARP_RAMROD_CMD_ID
10154 };
10155 
10156 /* Per PF iWARP retransmit path statistics */
10157 struct iwarp_rxmit_stats_drv {
10158 	struct regpair tx_go_to_slow_start_event_cnt;
10159 	struct regpair tx_fast_retransmit_event_cnt;
10160 };
10161 
10162 /* iWARP and TCP connection offload params passed by driver to FW in iWARP
10163  * offload ramrod.
10164  */
10165 struct iwarp_tcp_offload_ramrod_data {
10166 	struct iwarp_offload_params iwarp;
10167 	struct tcp_offload_params_opt2 tcp;
10168 };
10169 
10170 /* iWARP MPA negotiation types */
10171 enum mpa_negotiation_mode {
10172 	MPA_NEGOTIATION_TYPE_BASIC = 1,
10173 	MPA_NEGOTIATION_TYPE_ENHANCED = 2,
10174 	MAX_MPA_NEGOTIATION_MODE
10175 };
10176 
10177 /* iWARP MPA Enhanced mode RTR types */
10178 enum mpa_rtr_type {
10179 	MPA_RTR_TYPE_NONE = 0,
10180 	MPA_RTR_TYPE_ZERO_SEND = 1,
10181 	MPA_RTR_TYPE_ZERO_WRITE = 2,
10182 	MPA_RTR_TYPE_ZERO_SEND_AND_WRITE = 3,
10183 	MPA_RTR_TYPE_ZERO_READ = 4,
10184 	MPA_RTR_TYPE_ZERO_SEND_AND_READ = 5,
10185 	MPA_RTR_TYPE_ZERO_WRITE_AND_READ = 6,
10186 	MPA_RTR_TYPE_ZERO_SEND_AND_WRITE_AND_READ = 7,
10187 	MAX_MPA_RTR_TYPE
10188 };
10189 
10190 /* unaligned opaque data received from LL2 */
10191 struct unaligned_opaque_data {
10192 	__le16 first_mpa_offset;
10193 	u8 tcp_payload_offset;
10194 	u8 flags;
10195 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK	0x1
10196 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT	0
10197 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK		0x1
10198 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_SHIFT		1
10199 #define UNALIGNED_OPAQUE_DATA_RESERVED_MASK			0x3F
10200 #define UNALIGNED_OPAQUE_DATA_RESERVED_SHIFT			2
10201 	__le32 cid;
10202 };
10203 
10204 struct e4_mstorm_iwarp_conn_ag_ctx {
10205 	u8 reserved;
10206 	u8 state;
10207 	u8 flags0;
10208 #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK		0x1
10209 #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT		0
10210 #define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK			0x1
10211 #define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT			1
10212 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK	0x3
10213 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT	2
10214 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_MASK			0x3
10215 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT			4
10216 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_MASK			0x3
10217 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT			6
10218 	u8 flags1;
10219 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK	0x1
10220 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT	0
10221 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK			0x1
10222 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT			1
10223 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK			0x1
10224 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT			2
10225 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK		0x1
10226 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT		3
10227 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK		0x1
10228 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT		4
10229 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK		0x1
10230 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT		5
10231 #define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK		0x1
10232 #define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT		6
10233 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK		0x1
10234 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT		7
10235 	__le16 rcq_cons;
10236 	__le16 rcq_cons_th;
10237 	__le32 reg0;
10238 	__le32 reg1;
10239 };
10240 
10241 struct e4_ustorm_iwarp_conn_ag_ctx {
10242 	u8 reserved;
10243 	u8 byte1;
10244 	u8 flags0;
10245 #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
10246 #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
10247 #define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_MASK		0x1
10248 #define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT		1
10249 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0_MASK		0x3
10250 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT		2
10251 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1_MASK		0x3
10252 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT		4
10253 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2_MASK		0x3
10254 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT		6
10255 	u8 flags1;
10256 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_MASK		0x3
10257 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT		0
10258 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK	0x3
10259 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT	2
10260 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK	0x3
10261 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT	4
10262 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6_MASK		0x3
10263 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT		6
10264 	u8 flags2;
10265 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK			0x1
10266 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT			0
10267 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK			0x1
10268 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT			1
10269 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK			0x1
10270 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT			2
10271 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK			0x1
10272 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT			3
10273 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK	0x1
10274 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT	4
10275 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK		0x1
10276 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT		5
10277 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK			0x1
10278 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT			6
10279 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK		0x1
10280 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT		7
10281 	u8 flags3;
10282 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK		0x1
10283 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT		0
10284 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK	0x1
10285 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT	1
10286 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK	0x1
10287 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT	2
10288 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK	0x1
10289 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT	3
10290 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK	0x1
10291 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT	4
10292 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK	0x1
10293 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT	5
10294 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK	0x1
10295 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT	6
10296 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK	0x1
10297 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT	7
10298 	u8 byte2;
10299 	u8 byte3;
10300 	__le16 word0;
10301 	__le16 word1;
10302 	__le32 cq_cons;
10303 	__le32 cq_se_prod;
10304 	__le32 cq_prod;
10305 	__le32 reg3;
10306 	__le16 word2;
10307 	__le16 word3;
10308 };
10309 
10310 struct e4_ystorm_iwarp_conn_ag_ctx {
10311 	u8 byte0;
10312 	u8 byte1;
10313 	u8 flags0;
10314 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK	0x1
10315 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT	0
10316 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK	0x1
10317 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT	1
10318 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_MASK	0x3
10319 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT	2
10320 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_MASK	0x3
10321 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT	4
10322 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_MASK	0x3
10323 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT	6
10324 	u8 flags1;
10325 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK		0x1
10326 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT		0
10327 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK		0x1
10328 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT		1
10329 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK		0x1
10330 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT		2
10331 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK	0x1
10332 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT	3
10333 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK	0x1
10334 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT	4
10335 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK	0x1
10336 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT	5
10337 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK	0x1
10338 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT	6
10339 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK	0x1
10340 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT	7
10341 	u8 byte2;
10342 	u8 byte3;
10343 	__le16 word0;
10344 	__le32 reg0;
10345 	__le32 reg1;
10346 	__le16 word1;
10347 	__le16 word2;
10348 	__le16 word3;
10349 	__le16 word4;
10350 	__le32 reg2;
10351 	__le32 reg3;
10352 };
10353 
10354 /* The fcoe storm context of Ystorm */
10355 struct ystorm_fcoe_conn_st_ctx {
10356 	u8 func_mode;
10357 	u8 cos;
10358 	u8 conf_version;
10359 	u8 eth_hdr_size;
10360 	__le16 stat_ram_addr;
10361 	__le16 mtu;
10362 	__le16 max_fc_payload_len;
10363 	__le16 tx_max_fc_pay_len;
10364 	u8 fcp_cmd_size;
10365 	u8 fcp_rsp_size;
10366 	__le16 mss;
10367 	struct regpair reserved;
10368 	__le16 min_frame_size;
10369 	u8 protection_info_flags;
10370 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK		0x1
10371 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT	0
10372 #define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK			0x1
10373 #define YSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT			1
10374 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK			0x3F
10375 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_SHIFT			2
10376 	u8 dst_protection_per_mss;
10377 	u8 src_protection_per_mss;
10378 	u8 ptu_log_page_size;
10379 	u8 flags;
10380 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK	0x1
10381 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT	0
10382 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK	0x1
10383 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT	1
10384 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK		0x3F
10385 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT		2
10386 	u8 fcp_xfer_size;
10387 };
10388 
10389 /* FCoE 16-bits vlan structure */
10390 struct fcoe_vlan_fields {
10391 	__le16 fields;
10392 #define FCOE_VLAN_FIELDS_VID_MASK	0xFFF
10393 #define FCOE_VLAN_FIELDS_VID_SHIFT	0
10394 #define FCOE_VLAN_FIELDS_CLI_MASK	0x1
10395 #define FCOE_VLAN_FIELDS_CLI_SHIFT	12
10396 #define FCOE_VLAN_FIELDS_PRI_MASK	0x7
10397 #define FCOE_VLAN_FIELDS_PRI_SHIFT	13
10398 };
10399 
10400 /* FCoE 16-bits vlan union */
10401 union fcoe_vlan_field_union {
10402 	struct fcoe_vlan_fields fields;
10403 	__le16 val;
10404 };
10405 
10406 /* FCoE 16-bits vlan, vif union */
10407 union fcoe_vlan_vif_field_union {
10408 	union fcoe_vlan_field_union vlan;
10409 	__le16 vif;
10410 };
10411 
10412 /* Ethernet context section */
10413 struct pstorm_fcoe_eth_context_section {
10414 	u8 remote_addr_3;
10415 	u8 remote_addr_2;
10416 	u8 remote_addr_1;
10417 	u8 remote_addr_0;
10418 	u8 local_addr_1;
10419 	u8 local_addr_0;
10420 	u8 remote_addr_5;
10421 	u8 remote_addr_4;
10422 	u8 local_addr_5;
10423 	u8 local_addr_4;
10424 	u8 local_addr_3;
10425 	u8 local_addr_2;
10426 	union fcoe_vlan_vif_field_union vif_outer_vlan;
10427 	__le16 vif_outer_eth_type;
10428 	union fcoe_vlan_vif_field_union inner_vlan;
10429 	__le16 inner_eth_type;
10430 };
10431 
10432 /* The fcoe storm context of Pstorm */
10433 struct pstorm_fcoe_conn_st_ctx {
10434 	u8 func_mode;
10435 	u8 cos;
10436 	u8 conf_version;
10437 	u8 rsrv;
10438 	__le16 stat_ram_addr;
10439 	__le16 mss;
10440 	struct regpair abts_cleanup_addr;
10441 	struct pstorm_fcoe_eth_context_section eth;
10442 	u8 sid_2;
10443 	u8 sid_1;
10444 	u8 sid_0;
10445 	u8 flags;
10446 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK			0x1
10447 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT		0
10448 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK		0x1
10449 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT	1
10450 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK		0x1
10451 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT		2
10452 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK		0x1
10453 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT		3
10454 #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_MASK		0x1
10455 #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_SHIFT		4
10456 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK			0x7
10457 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT			5
10458 	u8 did_2;
10459 	u8 did_1;
10460 	u8 did_0;
10461 	u8 src_mac_index;
10462 	__le16 rec_rr_tov_val;
10463 	u8 q_relative_offset;
10464 	u8 reserved1;
10465 };
10466 
10467 /* The fcoe storm context of Xstorm */
10468 struct xstorm_fcoe_conn_st_ctx {
10469 	u8 func_mode;
10470 	u8 src_mac_index;
10471 	u8 conf_version;
10472 	u8 cached_wqes_avail;
10473 	__le16 stat_ram_addr;
10474 	u8 flags;
10475 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK		0x1
10476 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT		0
10477 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK		0x1
10478 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT		1
10479 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK	0x1
10480 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_SHIFT	2
10481 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK		0x3
10482 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT	3
10483 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK			0x7
10484 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT			5
10485 	u8 cached_wqes_offset;
10486 	u8 reserved2;
10487 	u8 eth_hdr_size;
10488 	u8 seq_id;
10489 	u8 max_conc_seqs;
10490 	__le16 num_pages_in_pbl;
10491 	__le16 reserved;
10492 	struct regpair sq_pbl_addr;
10493 	struct regpair sq_curr_page_addr;
10494 	struct regpair sq_next_page_addr;
10495 	struct regpair xferq_pbl_addr;
10496 	struct regpair xferq_curr_page_addr;
10497 	struct regpair xferq_next_page_addr;
10498 	struct regpair respq_pbl_addr;
10499 	struct regpair respq_curr_page_addr;
10500 	struct regpair respq_next_page_addr;
10501 	__le16 mtu;
10502 	__le16 tx_max_fc_pay_len;
10503 	__le16 max_fc_payload_len;
10504 	__le16 min_frame_size;
10505 	__le16 sq_pbl_next_index;
10506 	__le16 respq_pbl_next_index;
10507 	u8 fcp_cmd_byte_credit;
10508 	u8 fcp_rsp_byte_credit;
10509 	__le16 protection_info;
10510 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK		0x1
10511 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT		0
10512 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK		0x1
10513 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT	1
10514 #define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK			0x1
10515 #define XSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT			2
10516 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK		0x1
10517 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT	3
10518 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK			0xF
10519 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_SHIFT			4
10520 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK	0xFF
10521 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_SHIFT	8
10522 	__le16 xferq_pbl_next_index;
10523 	__le16 page_size;
10524 	u8 mid_seq;
10525 	u8 fcp_xfer_byte_credit;
10526 	u8 reserved1[2];
10527 	struct fcoe_wqe cached_wqes[16];
10528 };
10529 
10530 struct e4_xstorm_fcoe_conn_ag_ctx {
10531 	u8 reserved0;
10532 	u8 state;
10533 	u8 flags0;
10534 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
10535 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
10536 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK	0x1
10537 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT	1
10538 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK	0x1
10539 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT	2
10540 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
10541 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT	3
10542 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK	0x1
10543 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT	4
10544 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK	0x1
10545 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT	5
10546 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK	0x1
10547 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT	6
10548 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK	0x1
10549 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT	7
10550 	u8 flags1;
10551 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK	0x1
10552 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT	0
10553 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK	0x1
10554 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT	1
10555 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK	0x1
10556 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT	2
10557 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK		0x1
10558 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT		3
10559 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK		0x1
10560 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT		4
10561 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK		0x1
10562 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT		5
10563 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK		0x1
10564 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT		6
10565 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK		0x1
10566 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT		7
10567 	u8 flags2;
10568 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_MASK	0x3
10569 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT	0
10570 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_MASK	0x3
10571 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT	2
10572 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_MASK	0x3
10573 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT	4
10574 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_MASK	0x3
10575 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT	6
10576 	u8 flags3;
10577 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_MASK	0x3
10578 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT	0
10579 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_MASK	0x3
10580 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT	2
10581 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_MASK	0x3
10582 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT	4
10583 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_MASK	0x3
10584 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT	6
10585 	u8 flags4;
10586 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_MASK	0x3
10587 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT	0
10588 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_MASK	0x3
10589 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT	2
10590 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_MASK	0x3
10591 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT	4
10592 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_MASK	0x3
10593 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT	6
10594 	u8 flags5;
10595 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_MASK	0x3
10596 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT	0
10597 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_MASK	0x3
10598 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT	2
10599 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_MASK	0x3
10600 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT	4
10601 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_MASK	0x3
10602 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT	6
10603 	u8 flags6;
10604 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_MASK	0x3
10605 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT	0
10606 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_MASK	0x3
10607 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT	2
10608 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_MASK	0x3
10609 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT	4
10610 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK	0x3
10611 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT	6
10612 	u8 flags7;
10613 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK	0x3
10614 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT	0
10615 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK	0x3
10616 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT	2
10617 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK	0x3
10618 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT	4
10619 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK		0x1
10620 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT		6
10621 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK		0x1
10622 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT		7
10623 	u8 flags8;
10624 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK	0x1
10625 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT	0
10626 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK	0x1
10627 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT	1
10628 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK	0x1
10629 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT	2
10630 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK	0x1
10631 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT	3
10632 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK	0x1
10633 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT	4
10634 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK	0x1
10635 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT	5
10636 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK	0x1
10637 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT	6
10638 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK	0x1
10639 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT	7
10640 	u8 flags9;
10641 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK	0x1
10642 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT	0
10643 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK	0x1
10644 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT	1
10645 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK	0x1
10646 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT	2
10647 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK	0x1
10648 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT	3
10649 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK	0x1
10650 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT	4
10651 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK	0x1
10652 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT	5
10653 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK	0x1
10654 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT	6
10655 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK	0x1
10656 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT	7
10657 	u8 flags10;
10658 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK		0x1
10659 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT		0
10660 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK	0x1
10661 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT	1
10662 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK	0x1
10663 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT	2
10664 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK	0x1
10665 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT	3
10666 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK	0x1
10667 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT	4
10668 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK		0x1
10669 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT		5
10670 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK	0x1
10671 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT	6
10672 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK	0x1
10673 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT	7
10674 	u8 flags11;
10675 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK		0x1
10676 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT		0
10677 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK		0x1
10678 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT		1
10679 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK		0x1
10680 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT		2
10681 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK			0x1
10682 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT		3
10683 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK			0x1
10684 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT		4
10685 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK			0x1
10686 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT		5
10687 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK		0x1
10688 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT		6
10689 #define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK	0x1
10690 #define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT	7
10691 	u8 flags12;
10692 #define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK	0x1
10693 #define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT	0
10694 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK	0x1
10695 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT	1
10696 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK	0x1
10697 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT	2
10698 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK	0x1
10699 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT	3
10700 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK	0x1
10701 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT	4
10702 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK	0x1
10703 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT	5
10704 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK	0x1
10705 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT	6
10706 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK	0x1
10707 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT	7
10708 	u8 flags13;
10709 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK	0x1
10710 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT	0
10711 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK		0x1
10712 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT		1
10713 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK		0x1
10714 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT		2
10715 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK		0x1
10716 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT		3
10717 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK		0x1
10718 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT		4
10719 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK		0x1
10720 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT		5
10721 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK		0x1
10722 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT		6
10723 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK		0x1
10724 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT		7
10725 	u8 flags14;
10726 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK	0x1
10727 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT	0
10728 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK	0x1
10729 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT	1
10730 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK	0x1
10731 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT	2
10732 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK	0x1
10733 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT	3
10734 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK	0x1
10735 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT	4
10736 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK	0x1
10737 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT	5
10738 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_MASK	0x3
10739 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT	6
10740 	u8 byte2;
10741 	__le16 physical_q0;
10742 	__le16 word1;
10743 	__le16 word2;
10744 	__le16 sq_cons;
10745 	__le16 sq_prod;
10746 	__le16 xferq_prod;
10747 	__le16 xferq_cons;
10748 	u8 byte3;
10749 	u8 byte4;
10750 	u8 byte5;
10751 	u8 byte6;
10752 	__le32 remain_io;
10753 	__le32 reg1;
10754 	__le32 reg2;
10755 	__le32 reg3;
10756 	__le32 reg4;
10757 	__le32 reg5;
10758 	__le32 reg6;
10759 	__le16 respq_prod;
10760 	__le16 respq_cons;
10761 	__le16 word9;
10762 	__le16 word10;
10763 	__le32 reg7;
10764 	__le32 reg8;
10765 };
10766 
10767 /* The fcoe storm context of Ustorm */
10768 struct ustorm_fcoe_conn_st_ctx {
10769 	struct regpair respq_pbl_addr;
10770 	__le16 num_pages_in_pbl;
10771 	u8 ptu_log_page_size;
10772 	u8 log_page_size;
10773 	__le16 respq_prod;
10774 	u8 reserved[2];
10775 };
10776 
10777 struct e4_tstorm_fcoe_conn_ag_ctx {
10778 	u8 reserved0;
10779 	u8 state;
10780 	u8 flags0;
10781 #define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
10782 #define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
10783 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK		0x1
10784 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT		1
10785 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK		0x1
10786 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT		2
10787 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK		0x1
10788 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT		3
10789 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK		0x1
10790 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT		4
10791 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK		0x1
10792 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT		5
10793 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK	0x3
10794 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT	6
10795 	u8 flags1;
10796 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK		0x3
10797 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT		0
10798 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_MASK			0x3
10799 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT			2
10800 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK	0x3
10801 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT	4
10802 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_MASK			0x3
10803 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT			6
10804 	u8 flags2;
10805 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_MASK	0x3
10806 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT	0
10807 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_MASK	0x3
10808 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT	2
10809 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_MASK	0x3
10810 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT	4
10811 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_MASK	0x3
10812 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT	6
10813 	u8 flags3;
10814 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_MASK			0x3
10815 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT			0
10816 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_MASK			0x3
10817 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT			2
10818 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK	0x1
10819 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT	4
10820 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK		0x1
10821 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT		5
10822 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK			0x1
10823 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT			6
10824 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK	0x1
10825 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT	7
10826 	u8 flags4;
10827 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK		0x1
10828 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT		0
10829 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK		0x1
10830 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT		1
10831 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK		0x1
10832 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT		2
10833 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK		0x1
10834 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT		3
10835 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK		0x1
10836 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT		4
10837 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK		0x1
10838 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT		5
10839 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK		0x1
10840 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT		6
10841 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK		0x1
10842 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT	7
10843 	u8 flags5;
10844 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK		0x1
10845 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT	0
10846 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK		0x1
10847 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT	1
10848 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK		0x1
10849 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT	2
10850 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK		0x1
10851 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT	3
10852 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK		0x1
10853 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT	4
10854 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK		0x1
10855 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT	5
10856 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK		0x1
10857 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT	6
10858 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK		0x1
10859 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT	7
10860 	__le32 reg0;
10861 	__le32 reg1;
10862 };
10863 
10864 struct e4_ustorm_fcoe_conn_ag_ctx {
10865 	u8 byte0;
10866 	u8 byte1;
10867 	u8 flags0;
10868 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_MASK	0x1
10869 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT	0
10870 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_MASK	0x1
10871 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT	1
10872 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0_MASK	0x3
10873 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT	2
10874 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1_MASK	0x3
10875 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT	4
10876 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2_MASK	0x3
10877 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT	6
10878 	u8 flags1;
10879 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3_MASK	0x3
10880 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT	0
10881 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4_MASK	0x3
10882 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT	2
10883 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5_MASK	0x3
10884 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT	4
10885 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6_MASK	0x3
10886 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT	6
10887 	u8 flags2;
10888 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK		0x1
10889 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT		0
10890 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK		0x1
10891 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT		1
10892 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK		0x1
10893 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT		2
10894 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK		0x1
10895 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT		3
10896 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK		0x1
10897 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT		4
10898 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK		0x1
10899 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT		5
10900 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK		0x1
10901 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT		6
10902 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK		0x1
10903 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT	7
10904 	u8 flags3;
10905 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK		0x1
10906 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT	0
10907 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK		0x1
10908 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT	1
10909 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK		0x1
10910 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT	2
10911 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK		0x1
10912 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT	3
10913 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK		0x1
10914 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT	4
10915 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK		0x1
10916 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT	5
10917 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK		0x1
10918 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT	6
10919 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK		0x1
10920 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT	7
10921 	u8 byte2;
10922 	u8 byte3;
10923 	__le16 word0;
10924 	__le16 word1;
10925 	__le32 reg0;
10926 	__le32 reg1;
10927 	__le32 reg2;
10928 	__le32 reg3;
10929 	__le16 word2;
10930 	__le16 word3;
10931 };
10932 
10933 /* The fcoe storm context of Tstorm */
10934 struct tstorm_fcoe_conn_st_ctx {
10935 	__le16 stat_ram_addr;
10936 	__le16 rx_max_fc_payload_len;
10937 	__le16 e_d_tov_val;
10938 	u8 flags;
10939 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK	0x1
10940 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT	0
10941 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK	0x1
10942 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT	1
10943 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK		0x3F
10944 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT		2
10945 	u8 timers_cleanup_invocation_cnt;
10946 	__le32 reserved1[2];
10947 	__le32 dst_mac_address_bytes_0_to_3;
10948 	__le16 dst_mac_address_bytes_4_to_5;
10949 	__le16 ramrod_echo;
10950 	u8 flags1;
10951 #define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK	0x3
10952 #define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT	0
10953 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK	0x3F
10954 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT	2
10955 	u8 cq_relative_offset;
10956 	u8 cmdq_relative_offset;
10957 	u8 bdq_resource_id;
10958 	u8 reserved0[4];
10959 };
10960 
10961 struct e4_mstorm_fcoe_conn_ag_ctx {
10962 	u8 byte0;
10963 	u8 byte1;
10964 	u8 flags0;
10965 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK	0x1
10966 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT	0
10967 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK	0x1
10968 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT	1
10969 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_MASK	0x3
10970 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT	2
10971 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_MASK	0x3
10972 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT	4
10973 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_MASK	0x3
10974 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT	6
10975 	u8 flags1;
10976 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK		0x1
10977 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT		0
10978 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK		0x1
10979 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT		1
10980 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK		0x1
10981 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT		2
10982 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK		0x1
10983 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT	3
10984 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK		0x1
10985 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT	4
10986 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK		0x1
10987 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT	5
10988 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK		0x1
10989 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT	6
10990 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK		0x1
10991 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT	7
10992 	__le16 word0;
10993 	__le16 word1;
10994 	__le32 reg0;
10995 	__le32 reg1;
10996 };
10997 
10998 /* Fast path part of the fcoe storm context of Mstorm */
10999 struct fcoe_mstorm_fcoe_conn_st_ctx_fp {
11000 	__le16 xfer_prod;
11001 	u8 num_cqs;
11002 	u8 reserved1;
11003 	u8 protection_info;
11004 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK  0x1
11005 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_SHIFT 0
11006 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK               0x1
11007 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_SHIFT              1
11008 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_MASK           0x3F
11009 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_SHIFT          2
11010 	u8 q_relative_offset;
11011 	u8 reserved2[2];
11012 };
11013 
11014 /* Non fast path part of the fcoe storm context of Mstorm */
11015 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp {
11016 	__le16 conn_id;
11017 	__le16 stat_ram_addr;
11018 	__le16 num_pages_in_pbl;
11019 	u8 ptu_log_page_size;
11020 	u8 log_page_size;
11021 	__le16 unsolicited_cq_count;
11022 	__le16 cmdq_count;
11023 	u8 bdq_resource_id;
11024 	u8 reserved0[3];
11025 	struct regpair xferq_pbl_addr;
11026 	struct regpair reserved1;
11027 	struct regpair reserved2[3];
11028 };
11029 
11030 /* The fcoe storm context of Mstorm */
11031 struct mstorm_fcoe_conn_st_ctx {
11032 	struct fcoe_mstorm_fcoe_conn_st_ctx_fp fp;
11033 	struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp non_fp;
11034 };
11035 
11036 /* fcoe connection context */
11037 struct e4_fcoe_conn_context {
11038 	struct ystorm_fcoe_conn_st_ctx ystorm_st_context;
11039 	struct pstorm_fcoe_conn_st_ctx pstorm_st_context;
11040 	struct regpair pstorm_st_padding[2];
11041 	struct xstorm_fcoe_conn_st_ctx xstorm_st_context;
11042 	struct e4_xstorm_fcoe_conn_ag_ctx xstorm_ag_context;
11043 	struct regpair xstorm_ag_padding[6];
11044 	struct ustorm_fcoe_conn_st_ctx ustorm_st_context;
11045 	struct regpair ustorm_st_padding[2];
11046 	struct e4_tstorm_fcoe_conn_ag_ctx tstorm_ag_context;
11047 	struct regpair tstorm_ag_padding[2];
11048 	struct timers_context timer_context;
11049 	struct e4_ustorm_fcoe_conn_ag_ctx ustorm_ag_context;
11050 	struct tstorm_fcoe_conn_st_ctx tstorm_st_context;
11051 	struct e4_mstorm_fcoe_conn_ag_ctx mstorm_ag_context;
11052 	struct mstorm_fcoe_conn_st_ctx mstorm_st_context;
11053 };
11054 
11055 /* FCoE connection offload params passed by driver to FW in FCoE offload
11056  * ramrod.
11057  */
11058 struct fcoe_conn_offload_ramrod_params {
11059 	struct fcoe_conn_offload_ramrod_data offload_ramrod_data;
11060 };
11061 
11062 /* FCoE connection terminate params passed by driver to FW in FCoE terminate
11063  * conn ramrod.
11064  */
11065 struct fcoe_conn_terminate_ramrod_params {
11066 	struct fcoe_conn_terminate_ramrod_data terminate_ramrod_data;
11067 };
11068 
11069 /* FCoE event type */
11070 enum fcoe_event_type {
11071 	FCOE_EVENT_INIT_FUNC,
11072 	FCOE_EVENT_DESTROY_FUNC,
11073 	FCOE_EVENT_STAT_FUNC,
11074 	FCOE_EVENT_OFFLOAD_CONN,
11075 	FCOE_EVENT_TERMINATE_CONN,
11076 	FCOE_EVENT_ERROR,
11077 	MAX_FCOE_EVENT_TYPE
11078 };
11079 
11080 /* FCoE init params passed by driver to FW in FCoE init ramrod */
11081 struct fcoe_init_ramrod_params {
11082 	struct fcoe_init_func_ramrod_data init_ramrod_data;
11083 };
11084 
11085 /* FCoE ramrod Command IDs */
11086 enum fcoe_ramrod_cmd_id {
11087 	FCOE_RAMROD_CMD_ID_INIT_FUNC,
11088 	FCOE_RAMROD_CMD_ID_DESTROY_FUNC,
11089 	FCOE_RAMROD_CMD_ID_STAT_FUNC,
11090 	FCOE_RAMROD_CMD_ID_OFFLOAD_CONN,
11091 	FCOE_RAMROD_CMD_ID_TERMINATE_CONN,
11092 	MAX_FCOE_RAMROD_CMD_ID
11093 };
11094 
11095 /* FCoE statistics params buffer passed by driver to FW in FCoE statistics
11096  * ramrod.
11097  */
11098 struct fcoe_stat_ramrod_params {
11099 	struct fcoe_stat_ramrod_data stat_ramrod_data;
11100 };
11101 
11102 struct e4_ystorm_fcoe_conn_ag_ctx {
11103 	u8 byte0;
11104 	u8 byte1;
11105 	u8 flags0;
11106 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK	0x1
11107 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT	0
11108 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK	0x1
11109 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT	1
11110 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_MASK	0x3
11111 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT	2
11112 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_MASK	0x3
11113 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT	4
11114 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_MASK	0x3
11115 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT	6
11116 	u8 flags1;
11117 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK		0x1
11118 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT		0
11119 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK		0x1
11120 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT		1
11121 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK		0x1
11122 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT		2
11123 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK		0x1
11124 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT	3
11125 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK		0x1
11126 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT	4
11127 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK		0x1
11128 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT	5
11129 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK		0x1
11130 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT	6
11131 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK		0x1
11132 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT	7
11133 	u8 byte2;
11134 	u8 byte3;
11135 	__le16 word0;
11136 	__le32 reg0;
11137 	__le32 reg1;
11138 	__le16 word1;
11139 	__le16 word2;
11140 	__le16 word3;
11141 	__le16 word4;
11142 	__le32 reg2;
11143 	__le32 reg3;
11144 };
11145 
11146 /* The iscsi storm connection context of Ystorm */
11147 struct ystorm_iscsi_conn_st_ctx {
11148 	__le32 reserved[8];
11149 };
11150 
11151 /* Combined iSCSI and TCP storm connection of Pstorm */
11152 struct pstorm_iscsi_tcp_conn_st_ctx {
11153 	__le32 tcp[32];
11154 	__le32 iscsi[4];
11155 };
11156 
11157 /* The combined tcp and iscsi storm context of Xstorm */
11158 struct xstorm_iscsi_tcp_conn_st_ctx {
11159 	__le32 reserved_tcp[4];
11160 	__le32 reserved_iscsi[44];
11161 };
11162 
11163 struct e4_xstorm_iscsi_conn_ag_ctx {
11164 	u8 cdu_validation;
11165 	u8 state;
11166 	u8 flags0;
11167 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
11168 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
11169 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK	0x1
11170 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_SHIFT	1
11171 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK	0x1
11172 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_SHIFT	2
11173 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
11174 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_SHIFT	3
11175 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK		0x1
11176 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT		4
11177 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK	0x1
11178 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_SHIFT	5
11179 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK		0x1
11180 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_SHIFT		6
11181 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK		0x1
11182 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_SHIFT		7
11183 	u8 flags1;
11184 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK		0x1
11185 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT		0
11186 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK		0x1
11187 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT9_SHIFT		1
11188 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK		0x1
11189 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT10_SHIFT		2
11190 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK		0x1
11191 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT11_SHIFT		3
11192 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK		0x1
11193 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT12_SHIFT		4
11194 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK		0x1
11195 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT13_SHIFT		5
11196 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK		0x1
11197 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT14_SHIFT		6
11198 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK	0x1
11199 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_SHIFT	7
11200 	u8 flags2;
11201 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK			0x3
11202 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT			0
11203 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK			0x3
11204 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT			2
11205 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK			0x3
11206 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT			4
11207 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK		0x3
11208 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT	6
11209 	u8 flags3;
11210 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK	0x3
11211 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT	0
11212 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK	0x3
11213 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT	2
11214 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK	0x3
11215 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT	4
11216 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK	0x3
11217 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT	6
11218 	u8 flags4;
11219 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK	0x3
11220 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT	0
11221 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK	0x3
11222 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9_SHIFT	2
11223 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK	0x3
11224 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT	4
11225 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK	0x3
11226 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11_SHIFT	6
11227 	u8 flags5;
11228 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK				0x3
11229 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT				0
11230 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK				0x3
11231 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13_SHIFT				2
11232 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK				0x3
11233 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14_SHIFT				4
11234 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK	0x3
11235 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_SHIFT	6
11236 	u8 flags6;
11237 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK		0x3
11238 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT		0
11239 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK		0x3
11240 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17_SHIFT		2
11241 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK		0x3
11242 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18_SHIFT		4
11243 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK	0x3
11244 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_SHIFT	6
11245 	u8 flags7;
11246 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK	0x3
11247 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_SHIFT	0
11248 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK	0x3
11249 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_SHIFT	2
11250 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK		0x3
11251 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_SHIFT		4
11252 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK			0x1
11253 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT			6
11254 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK			0x1
11255 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT			7
11256 	u8 flags8;
11257 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK			0x1
11258 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT			0
11259 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK	0x1
11260 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT	1
11261 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK			0x1
11262 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT			2
11263 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK			0x1
11264 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT			3
11265 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK			0x1
11266 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT			4
11267 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK			0x1
11268 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT			5
11269 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK			0x1
11270 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT			6
11271 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK			0x1
11272 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9EN_SHIFT			7
11273 	u8 flags9;
11274 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK				0x1
11275 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT			0
11276 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK				0x1
11277 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11EN_SHIFT			1
11278 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK				0x1
11279 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12EN_SHIFT			2
11280 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK				0x1
11281 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13EN_SHIFT			3
11282 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK				0x1
11283 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14EN_SHIFT			4
11284 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK	0x1
11285 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_SHIFT	5
11286 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK				0x1
11287 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16EN_SHIFT			6
11288 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK				0x1
11289 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17EN_SHIFT			7
11290 	u8 flags10;
11291 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK				0x1
11292 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT			0
11293 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK			0x1
11294 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT			1
11295 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK		0x1
11296 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_SHIFT	2
11297 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK		0x1
11298 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_SHIFT	3
11299 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK			0x1
11300 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_SHIFT			4
11301 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK		0x1
11302 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_SHIFT		5
11303 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK			0x1
11304 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT			6
11305 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK	0x1
11306 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_SHIFT	7
11307 	u8 flags11;
11308 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK	0x1
11309 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT	0
11310 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK	0x1
11311 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT	1
11312 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK	0x1
11313 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_SHIFT	2
11314 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK	0x1
11315 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT	3
11316 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK	0x1
11317 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT	4
11318 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK	0x1
11319 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT	5
11320 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK	0x1
11321 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_SHIFT	6
11322 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK	0x1
11323 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_SHIFT	7
11324 	u8 flags12;
11325 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK		0x1
11326 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT	0
11327 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK		0x1
11328 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_SHIFT		1
11329 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK		0x1
11330 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_SHIFT		2
11331 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK		0x1
11332 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_SHIFT		3
11333 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK		0x1
11334 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_SHIFT		4
11335 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK		0x1
11336 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_SHIFT		5
11337 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK		0x1
11338 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_SHIFT		6
11339 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK		0x1
11340 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_SHIFT		7
11341 	u8 flags13;
11342 #define E4_XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK	0x1
11343 #define E4_XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT	0
11344 #define E4_XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK		0x1
11345 #define E4_XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_SHIFT	1
11346 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK		0x1
11347 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_SHIFT		2
11348 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK		0x1
11349 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_SHIFT		3
11350 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK		0x1
11351 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_SHIFT		4
11352 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK		0x1
11353 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_SHIFT		5
11354 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK		0x1
11355 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_SHIFT		6
11356 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK		0x1
11357 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_SHIFT		7
11358 	u8 flags14;
11359 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK			0x1
11360 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT			0
11361 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK			0x1
11362 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT17_SHIFT			1
11363 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK			0x1
11364 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT18_SHIFT			2
11365 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK			0x1
11366 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT19_SHIFT			3
11367 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK			0x1
11368 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT20_SHIFT			4
11369 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK	0x1
11370 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_SHIFT	5
11371 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK	0x3
11372 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_SHIFT	6
11373 	u8 byte2;
11374 	__le16 physical_q0;
11375 	__le16 physical_q1;
11376 	__le16 dummy_dorq_var;
11377 	__le16 sq_cons;
11378 	__le16 sq_prod;
11379 	__le16 word5;
11380 	__le16 slow_io_total_data_tx_update;
11381 	u8 byte3;
11382 	u8 byte4;
11383 	u8 byte5;
11384 	u8 byte6;
11385 	__le32 reg0;
11386 	__le32 reg1;
11387 	__le32 reg2;
11388 	__le32 more_to_send_seq;
11389 	__le32 reg4;
11390 	__le32 reg5;
11391 	__le32 hq_scan_next_relevant_ack;
11392 	__le16 r2tq_prod;
11393 	__le16 r2tq_cons;
11394 	__le16 hq_prod;
11395 	__le16 hq_cons;
11396 	__le32 remain_seq;
11397 	__le32 bytes_to_next_pdu;
11398 	__le32 hq_tcp_seq;
11399 	u8 byte7;
11400 	u8 byte8;
11401 	u8 byte9;
11402 	u8 byte10;
11403 	u8 byte11;
11404 	u8 byte12;
11405 	u8 byte13;
11406 	u8 byte14;
11407 	u8 byte15;
11408 	u8 e5_reserved;
11409 	__le16 word11;
11410 	__le32 reg10;
11411 	__le32 reg11;
11412 	__le32 exp_stat_sn;
11413 	__le32 ongoing_fast_rxmit_seq;
11414 	__le32 reg14;
11415 	__le32 reg15;
11416 	__le32 reg16;
11417 	__le32 reg17;
11418 };
11419 
11420 struct e4_tstorm_iscsi_conn_ag_ctx {
11421 	u8 reserved0;
11422 	u8 state;
11423 	u8 flags0;
11424 #define E4_TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
11425 #define E4_TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
11426 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK		0x1
11427 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT		1
11428 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK		0x1
11429 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT2_SHIFT		2
11430 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK		0x1
11431 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT3_SHIFT		3
11432 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK		0x1
11433 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT		4
11434 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK		0x1
11435 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT5_SHIFT		5
11436 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK		0x3
11437 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT		6
11438 	u8 flags1;
11439 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK		0x3
11440 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_SHIFT		0
11441 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK		0x3
11442 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_SHIFT		2
11443 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK		0x3
11444 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT	4
11445 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK			0x3
11446 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT			6
11447 	u8 flags2;
11448 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK	0x3
11449 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT	0
11450 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK	0x3
11451 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT	2
11452 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK	0x3
11453 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT	4
11454 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK	0x3
11455 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT	6
11456 	u8 flags3;
11457 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK		0x3
11458 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT		0
11459 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10_MASK			0x3
11460 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT			2
11461 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK			0x1
11462 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT			4
11463 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK	0x1
11464 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_SHIFT	5
11465 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK	0x1
11466 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_SHIFT	6
11467 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK	0x1
11468 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT	7
11469 	u8 flags4;
11470 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK		0x1
11471 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT		0
11472 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK		0x1
11473 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT		1
11474 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK		0x1
11475 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT		2
11476 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK		0x1
11477 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT		3
11478 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK		0x1
11479 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT		4
11480 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK	0x1
11481 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT	5
11482 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK		0x1
11483 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT	6
11484 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK	0x1
11485 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT	7
11486 	u8 flags5;
11487 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK	0x1
11488 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT	0
11489 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK	0x1
11490 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT	1
11491 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK	0x1
11492 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT	2
11493 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK	0x1
11494 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT	3
11495 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK	0x1
11496 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT	4
11497 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK	0x1
11498 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT	5
11499 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK	0x1
11500 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT	6
11501 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK	0x1
11502 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT	7
11503 	__le32 reg0;
11504 	__le32 reg1;
11505 	__le32 rx_tcp_checksum_err_cnt;
11506 	__le32 reg3;
11507 	__le32 reg4;
11508 	__le32 reg5;
11509 	__le32 reg6;
11510 	__le32 reg7;
11511 	__le32 reg8;
11512 	u8 cid_offload_cnt;
11513 	u8 byte3;
11514 	__le16 word0;
11515 };
11516 
11517 struct e4_ustorm_iscsi_conn_ag_ctx {
11518 	u8 byte0;
11519 	u8 byte1;
11520 	u8 flags0;
11521 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK	0x1
11522 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT	0
11523 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK	0x1
11524 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT	1
11525 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0_MASK	0x3
11526 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT	2
11527 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1_MASK	0x3
11528 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT	4
11529 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2_MASK	0x3
11530 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT	6
11531 	u8 flags1;
11532 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3_MASK	0x3
11533 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT	0
11534 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4_MASK	0x3
11535 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT	2
11536 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5_MASK	0x3
11537 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT	4
11538 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6_MASK	0x3
11539 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT	6
11540 	u8 flags2;
11541 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK		0x1
11542 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT		0
11543 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK		0x1
11544 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT		1
11545 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK		0x1
11546 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT		2
11547 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK		0x1
11548 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3EN_SHIFT		3
11549 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK		0x1
11550 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT		4
11551 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK		0x1
11552 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT		5
11553 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK		0x1
11554 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT		6
11555 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK	0x1
11556 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT	7
11557 	u8 flags3;
11558 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK	0x1
11559 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT	0
11560 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK	0x1
11561 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT	1
11562 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK	0x1
11563 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT	2
11564 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK	0x1
11565 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT	3
11566 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK	0x1
11567 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT	4
11568 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK	0x1
11569 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT	5
11570 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK	0x1
11571 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT	6
11572 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK	0x1
11573 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT	7
11574 	u8 byte2;
11575 	u8 byte3;
11576 	__le16 word0;
11577 	__le16 word1;
11578 	__le32 reg0;
11579 	__le32 reg1;
11580 	__le32 reg2;
11581 	__le32 reg3;
11582 	__le16 word2;
11583 	__le16 word3;
11584 };
11585 
11586 /* The iscsi storm connection context of Tstorm */
11587 struct tstorm_iscsi_conn_st_ctx {
11588 	__le32 reserved[44];
11589 };
11590 
11591 struct e4_mstorm_iscsi_conn_ag_ctx {
11592 	u8 reserved;
11593 	u8 state;
11594 	u8 flags0;
11595 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK	0x1
11596 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT	0
11597 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK	0x1
11598 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT	1
11599 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK	0x3
11600 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT	2
11601 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK	0x3
11602 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT	4
11603 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK	0x3
11604 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT	6
11605 	u8 flags1;
11606 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK		0x1
11607 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT		0
11608 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK		0x1
11609 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT		1
11610 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK		0x1
11611 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT		2
11612 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK	0x1
11613 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT	3
11614 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK	0x1
11615 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT	4
11616 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK	0x1
11617 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT	5
11618 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK	0x1
11619 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT	6
11620 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK	0x1
11621 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT	7
11622 	__le16 word0;
11623 	__le16 word1;
11624 	__le32 reg0;
11625 	__le32 reg1;
11626 };
11627 
11628 /* Combined iSCSI and TCP storm connection of Mstorm */
11629 struct mstorm_iscsi_tcp_conn_st_ctx {
11630 	__le32 reserved_tcp[20];
11631 	__le32 reserved_iscsi[12];
11632 };
11633 
11634 /* The iscsi storm context of Ustorm */
11635 struct ustorm_iscsi_conn_st_ctx {
11636 	__le32 reserved[52];
11637 };
11638 
11639 /* iscsi connection context */
11640 struct e4_iscsi_conn_context {
11641 	struct ystorm_iscsi_conn_st_ctx ystorm_st_context;
11642 	struct pstorm_iscsi_tcp_conn_st_ctx pstorm_st_context;
11643 	struct regpair pstorm_st_padding[2];
11644 	struct pb_context xpb2_context;
11645 	struct xstorm_iscsi_tcp_conn_st_ctx xstorm_st_context;
11646 	struct regpair xstorm_st_padding[2];
11647 	struct e4_xstorm_iscsi_conn_ag_ctx xstorm_ag_context;
11648 	struct e4_tstorm_iscsi_conn_ag_ctx tstorm_ag_context;
11649 	struct regpair tstorm_ag_padding[2];
11650 	struct timers_context timer_context;
11651 	struct e4_ustorm_iscsi_conn_ag_ctx ustorm_ag_context;
11652 	struct pb_context upb_context;
11653 	struct tstorm_iscsi_conn_st_ctx tstorm_st_context;
11654 	struct regpair tstorm_st_padding[2];
11655 	struct e4_mstorm_iscsi_conn_ag_ctx mstorm_ag_context;
11656 	struct mstorm_iscsi_tcp_conn_st_ctx mstorm_st_context;
11657 	struct ustorm_iscsi_conn_st_ctx ustorm_st_context;
11658 };
11659 
11660 /* iSCSI init params passed by driver to FW in iSCSI init ramrod */
11661 struct iscsi_init_ramrod_params {
11662 	struct iscsi_spe_func_init iscsi_init_spe;
11663 	struct tcp_init_params tcp_init;
11664 };
11665 
11666 struct e4_ystorm_iscsi_conn_ag_ctx {
11667 	u8 byte0;
11668 	u8 byte1;
11669 	u8 flags0;
11670 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK	0x1
11671 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT	0
11672 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK	0x1
11673 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT	1
11674 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK	0x3
11675 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT	2
11676 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK	0x3
11677 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT	4
11678 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK	0x3
11679 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT	6
11680 	u8 flags1;
11681 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK		0x1
11682 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT		0
11683 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK		0x1
11684 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT		1
11685 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK		0x1
11686 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT		2
11687 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK	0x1
11688 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT	3
11689 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK	0x1
11690 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT	4
11691 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK	0x1
11692 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT	5
11693 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK	0x1
11694 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT	6
11695 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK	0x1
11696 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT	7
11697 	u8 byte2;
11698 	u8 byte3;
11699 	__le16 word0;
11700 	__le32 reg0;
11701 	__le32 reg1;
11702 	__le16 word1;
11703 	__le16 word2;
11704 	__le16 word3;
11705 	__le16 word4;
11706 	__le32 reg2;
11707 	__le32 reg3;
11708 };
11709 
11710 #define MFW_TRACE_SIGNATURE     0x25071946
11711 
11712 /* The trace in the buffer */
11713 #define MFW_TRACE_EVENTID_MASK          0x00ffff
11714 #define MFW_TRACE_PRM_SIZE_MASK         0x0f0000
11715 #define MFW_TRACE_PRM_SIZE_SHIFT        16
11716 #define MFW_TRACE_ENTRY_SIZE            3
11717 
11718 struct mcp_trace {
11719 	u32 signature;		/* Help to identify that the trace is valid */
11720 	u32 size;		/* the size of the trace buffer in bytes */
11721 	u32 curr_level;		/* 2 - all will be written to the buffer
11722 				 * 1 - debug trace will not be written
11723 				 * 0 - just errors will be written to the buffer
11724 				 */
11725 	u32 modules_mask[2];	/* a bit per module, 1 means write it, 0 means
11726 				 * mask it.
11727 				 */
11728 
11729 	/* Warning: the following pointers are assumed to be 32bits as they are
11730 	 * used only in the MFW.
11731 	 */
11732 	u32 trace_prod; /* The next trace will be written to this offset */
11733 	u32 trace_oldest; /* The oldest valid trace starts at this offset
11734 			   * (usually very close after the current producer).
11735 			   */
11736 };
11737 
11738 #define VF_MAX_STATIC 192
11739 
11740 #define MCP_GLOB_PATH_MAX	2
11741 #define MCP_PORT_MAX		2
11742 #define MCP_GLOB_PORT_MAX	4
11743 #define MCP_GLOB_FUNC_MAX	16
11744 
11745 typedef u32 offsize_t;		/* In DWORDS !!! */
11746 /* Offset from the beginning of the MCP scratchpad */
11747 #define OFFSIZE_OFFSET_SHIFT	0
11748 #define OFFSIZE_OFFSET_MASK	0x0000ffff
11749 /* Size of specific element (not the whole array if any) */
11750 #define OFFSIZE_SIZE_SHIFT	16
11751 #define OFFSIZE_SIZE_MASK	0xffff0000
11752 
11753 #define SECTION_OFFSET(_offsize) ((((_offsize &			\
11754 				     OFFSIZE_OFFSET_MASK) >>	\
11755 				    OFFSIZE_OFFSET_SHIFT) << 2))
11756 
11757 #define QED_SECTION_SIZE(_offsize) (((_offsize &		\
11758 				      OFFSIZE_SIZE_MASK) >>	\
11759 				     OFFSIZE_SIZE_SHIFT) << 2)
11760 
11761 #define SECTION_ADDR(_offsize, idx) (MCP_REG_SCRATCH +			\
11762 				     SECTION_OFFSET(_offsize) +		\
11763 				     (QED_SECTION_SIZE(_offsize) * idx))
11764 
11765 #define SECTION_OFFSIZE_ADDR(_pub_base, _section)	\
11766 	(_pub_base + offsetof(struct mcp_public_data, sections[_section]))
11767 
11768 /* PHY configuration */
11769 struct eth_phy_cfg {
11770 	u32 speed;
11771 #define ETH_SPEED_AUTONEG	0
11772 #define ETH_SPEED_SMARTLINQ	0x8
11773 
11774 	u32 pause;
11775 #define ETH_PAUSE_NONE		0x0
11776 #define ETH_PAUSE_AUTONEG	0x1
11777 #define ETH_PAUSE_RX		0x2
11778 #define ETH_PAUSE_TX		0x4
11779 
11780 	u32 adv_speed;
11781 	u32 loopback_mode;
11782 #define ETH_LOOPBACK_NONE		(0)
11783 #define ETH_LOOPBACK_INT_PHY		(1)
11784 #define ETH_LOOPBACK_EXT_PHY		(2)
11785 #define ETH_LOOPBACK_EXT		(3)
11786 #define ETH_LOOPBACK_MAC		(4)
11787 
11788 	u32 eee_cfg;
11789 #define EEE_CFG_EEE_ENABLED			BIT(0)
11790 #define EEE_CFG_TX_LPI				BIT(1)
11791 #define EEE_CFG_ADV_SPEED_1G			BIT(2)
11792 #define EEE_CFG_ADV_SPEED_10G			BIT(3)
11793 #define EEE_TX_TIMER_USEC_MASK			(0xfffffff0)
11794 #define EEE_TX_TIMER_USEC_OFFSET		4
11795 #define EEE_TX_TIMER_USEC_BALANCED_TIME		(0xa00)
11796 #define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME	(0x100)
11797 #define EEE_TX_TIMER_USEC_LATENCY_TIME		(0x6000)
11798 
11799 	u32 feature_config_flags;
11800 #define ETH_EEE_MODE_ADV_LPI		(1 << 0)
11801 };
11802 
11803 struct port_mf_cfg {
11804 	u32 dynamic_cfg;
11805 #define PORT_MF_CFG_OV_TAG_MASK		0x0000ffff
11806 #define PORT_MF_CFG_OV_TAG_SHIFT	0
11807 #define PORT_MF_CFG_OV_TAG_DEFAULT	PORT_MF_CFG_OV_TAG_MASK
11808 
11809 	u32 reserved[1];
11810 };
11811 
11812 struct eth_stats {
11813 	u64 r64;
11814 	u64 r127;
11815 	u64 r255;
11816 	u64 r511;
11817 	u64 r1023;
11818 	u64 r1518;
11819 
11820 	union {
11821 		struct {
11822 			u64 r1522;
11823 			u64 r2047;
11824 			u64 r4095;
11825 			u64 r9216;
11826 			u64 r16383;
11827 		} bb0;
11828 		struct {
11829 			u64 unused1;
11830 			u64 r1519_to_max;
11831 			u64 unused2;
11832 			u64 unused3;
11833 			u64 unused4;
11834 		} ah0;
11835 	} u0;
11836 
11837 	u64 rfcs;
11838 	u64 rxcf;
11839 	u64 rxpf;
11840 	u64 rxpp;
11841 	u64 raln;
11842 	u64 rfcr;
11843 	u64 rovr;
11844 	u64 rjbr;
11845 	u64 rund;
11846 	u64 rfrg;
11847 	u64 t64;
11848 	u64 t127;
11849 	u64 t255;
11850 	u64 t511;
11851 	u64 t1023;
11852 	u64 t1518;
11853 
11854 	union {
11855 		struct {
11856 			u64 t2047;
11857 			u64 t4095;
11858 			u64 t9216;
11859 			u64 t16383;
11860 		} bb1;
11861 		struct {
11862 			u64 t1519_to_max;
11863 			u64 unused6;
11864 			u64 unused7;
11865 			u64 unused8;
11866 		} ah1;
11867 	} u1;
11868 
11869 	u64 txpf;
11870 	u64 txpp;
11871 
11872 	union {
11873 		struct {
11874 			u64 tlpiec;
11875 			u64 tncl;
11876 		} bb2;
11877 		struct {
11878 			u64 unused9;
11879 			u64 unused10;
11880 		} ah2;
11881 	} u2;
11882 
11883 	u64 rbyte;
11884 	u64 rxuca;
11885 	u64 rxmca;
11886 	u64 rxbca;
11887 	u64 rxpok;
11888 	u64 tbyte;
11889 	u64 txuca;
11890 	u64 txmca;
11891 	u64 txbca;
11892 	u64 txcf;
11893 };
11894 
11895 struct brb_stats {
11896 	u64 brb_truncate[8];
11897 	u64 brb_discard[8];
11898 };
11899 
11900 struct port_stats {
11901 	struct brb_stats brb;
11902 	struct eth_stats eth;
11903 };
11904 
11905 struct couple_mode_teaming {
11906 	u8 port_cmt[MCP_GLOB_PORT_MAX];
11907 #define PORT_CMT_IN_TEAM	(1 << 0)
11908 
11909 #define PORT_CMT_PORT_ROLE	(1 << 1)
11910 #define PORT_CMT_PORT_INACTIVE	(0 << 1)
11911 #define PORT_CMT_PORT_ACTIVE	(1 << 1)
11912 
11913 #define PORT_CMT_TEAM_MASK	(1 << 2)
11914 #define PORT_CMT_TEAM0		(0 << 2)
11915 #define PORT_CMT_TEAM1		(1 << 2)
11916 };
11917 
11918 #define LLDP_CHASSIS_ID_STAT_LEN	4
11919 #define LLDP_PORT_ID_STAT_LEN		4
11920 #define DCBX_MAX_APP_PROTOCOL		32
11921 #define MAX_SYSTEM_LLDP_TLV_DATA	32
11922 
11923 enum _lldp_agent {
11924 	LLDP_NEAREST_BRIDGE = 0,
11925 	LLDP_NEAREST_NON_TPMR_BRIDGE,
11926 	LLDP_NEAREST_CUSTOMER_BRIDGE,
11927 	LLDP_MAX_LLDP_AGENTS
11928 };
11929 
11930 struct lldp_config_params_s {
11931 	u32 config;
11932 #define LLDP_CONFIG_TX_INTERVAL_MASK	0x000000ff
11933 #define LLDP_CONFIG_TX_INTERVAL_SHIFT	0
11934 #define LLDP_CONFIG_HOLD_MASK		0x00000f00
11935 #define LLDP_CONFIG_HOLD_SHIFT		8
11936 #define LLDP_CONFIG_MAX_CREDIT_MASK	0x0000f000
11937 #define LLDP_CONFIG_MAX_CREDIT_SHIFT	12
11938 #define LLDP_CONFIG_ENABLE_RX_MASK	0x40000000
11939 #define LLDP_CONFIG_ENABLE_RX_SHIFT	30
11940 #define LLDP_CONFIG_ENABLE_TX_MASK	0x80000000
11941 #define LLDP_CONFIG_ENABLE_TX_SHIFT	31
11942 	u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
11943 	u32 local_port_id[LLDP_PORT_ID_STAT_LEN];
11944 };
11945 
11946 struct lldp_status_params_s {
11947 	u32 prefix_seq_num;
11948 	u32 status;
11949 	u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
11950 	u32 peer_port_id[LLDP_PORT_ID_STAT_LEN];
11951 	u32 suffix_seq_num;
11952 };
11953 
11954 struct dcbx_ets_feature {
11955 	u32 flags;
11956 #define DCBX_ETS_ENABLED_MASK	0x00000001
11957 #define DCBX_ETS_ENABLED_SHIFT	0
11958 #define DCBX_ETS_WILLING_MASK	0x00000002
11959 #define DCBX_ETS_WILLING_SHIFT	1
11960 #define DCBX_ETS_ERROR_MASK	0x00000004
11961 #define DCBX_ETS_ERROR_SHIFT	2
11962 #define DCBX_ETS_CBS_MASK	0x00000008
11963 #define DCBX_ETS_CBS_SHIFT	3
11964 #define DCBX_ETS_MAX_TCS_MASK	0x000000f0
11965 #define DCBX_ETS_MAX_TCS_SHIFT	4
11966 #define DCBX_OOO_TC_MASK	0x00000f00
11967 #define DCBX_OOO_TC_SHIFT	8
11968 	u32 pri_tc_tbl[1];
11969 #define DCBX_TCP_OOO_TC		(4)
11970 
11971 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET	(DCBX_TCP_OOO_TC + 1)
11972 #define DCBX_CEE_STRICT_PRIORITY	0xf
11973 	u32 tc_bw_tbl[2];
11974 	u32 tc_tsa_tbl[2];
11975 #define DCBX_ETS_TSA_STRICT	0
11976 #define DCBX_ETS_TSA_CBS	1
11977 #define DCBX_ETS_TSA_ETS	2
11978 };
11979 
11980 #define DCBX_TCP_OOO_TC			(4)
11981 #define DCBX_TCP_OOO_K2_4PORT_TC	(3)
11982 
11983 struct dcbx_app_priority_entry {
11984 	u32 entry;
11985 #define DCBX_APP_PRI_MAP_MASK		0x000000ff
11986 #define DCBX_APP_PRI_MAP_SHIFT		0
11987 #define DCBX_APP_PRI_0			0x01
11988 #define DCBX_APP_PRI_1			0x02
11989 #define DCBX_APP_PRI_2			0x04
11990 #define DCBX_APP_PRI_3			0x08
11991 #define DCBX_APP_PRI_4			0x10
11992 #define DCBX_APP_PRI_5			0x20
11993 #define DCBX_APP_PRI_6			0x40
11994 #define DCBX_APP_PRI_7			0x80
11995 #define DCBX_APP_SF_MASK		0x00000300
11996 #define DCBX_APP_SF_SHIFT		8
11997 #define DCBX_APP_SF_ETHTYPE		0
11998 #define DCBX_APP_SF_PORT		1
11999 #define DCBX_APP_SF_IEEE_MASK		0x0000f000
12000 #define DCBX_APP_SF_IEEE_SHIFT		12
12001 #define DCBX_APP_SF_IEEE_RESERVED	0
12002 #define DCBX_APP_SF_IEEE_ETHTYPE	1
12003 #define DCBX_APP_SF_IEEE_TCP_PORT	2
12004 #define DCBX_APP_SF_IEEE_UDP_PORT	3
12005 #define DCBX_APP_SF_IEEE_TCP_UDP_PORT	4
12006 
12007 #define DCBX_APP_PROTOCOL_ID_MASK	0xffff0000
12008 #define DCBX_APP_PROTOCOL_ID_SHIFT	16
12009 };
12010 
12011 struct dcbx_app_priority_feature {
12012 	u32 flags;
12013 #define DCBX_APP_ENABLED_MASK		0x00000001
12014 #define DCBX_APP_ENABLED_SHIFT		0
12015 #define DCBX_APP_WILLING_MASK		0x00000002
12016 #define DCBX_APP_WILLING_SHIFT		1
12017 #define DCBX_APP_ERROR_MASK		0x00000004
12018 #define DCBX_APP_ERROR_SHIFT		2
12019 #define DCBX_APP_MAX_TCS_MASK		0x0000f000
12020 #define DCBX_APP_MAX_TCS_SHIFT		12
12021 #define DCBX_APP_NUM_ENTRIES_MASK	0x00ff0000
12022 #define DCBX_APP_NUM_ENTRIES_SHIFT	16
12023 	struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
12024 };
12025 
12026 struct dcbx_features {
12027 	struct dcbx_ets_feature ets;
12028 	u32 pfc;
12029 #define DCBX_PFC_PRI_EN_BITMAP_MASK	0x000000ff
12030 #define DCBX_PFC_PRI_EN_BITMAP_SHIFT	0
12031 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0	0x01
12032 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1	0x02
12033 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2	0x04
12034 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3	0x08
12035 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4	0x10
12036 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5	0x20
12037 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6	0x40
12038 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7	0x80
12039 
12040 #define DCBX_PFC_FLAGS_MASK		0x0000ff00
12041 #define DCBX_PFC_FLAGS_SHIFT		8
12042 #define DCBX_PFC_CAPS_MASK		0x00000f00
12043 #define DCBX_PFC_CAPS_SHIFT		8
12044 #define DCBX_PFC_MBC_MASK		0x00004000
12045 #define DCBX_PFC_MBC_SHIFT		14
12046 #define DCBX_PFC_WILLING_MASK		0x00008000
12047 #define DCBX_PFC_WILLING_SHIFT		15
12048 #define DCBX_PFC_ENABLED_MASK		0x00010000
12049 #define DCBX_PFC_ENABLED_SHIFT		16
12050 #define DCBX_PFC_ERROR_MASK		0x00020000
12051 #define DCBX_PFC_ERROR_SHIFT		17
12052 
12053 	struct dcbx_app_priority_feature app;
12054 };
12055 
12056 struct dcbx_local_params {
12057 	u32 config;
12058 #define DCBX_CONFIG_VERSION_MASK	0x00000007
12059 #define DCBX_CONFIG_VERSION_SHIFT	0
12060 #define DCBX_CONFIG_VERSION_DISABLED	0
12061 #define DCBX_CONFIG_VERSION_IEEE	1
12062 #define DCBX_CONFIG_VERSION_CEE		2
12063 #define DCBX_CONFIG_VERSION_STATIC	4
12064 
12065 	u32 flags;
12066 	struct dcbx_features features;
12067 };
12068 
12069 struct dcbx_mib {
12070 	u32 prefix_seq_num;
12071 	u32 flags;
12072 	struct dcbx_features features;
12073 	u32 suffix_seq_num;
12074 };
12075 
12076 struct lldp_system_tlvs_buffer_s {
12077 	u16 valid;
12078 	u16 length;
12079 	u32 data[MAX_SYSTEM_LLDP_TLV_DATA];
12080 };
12081 
12082 struct dcb_dscp_map {
12083 	u32 flags;
12084 #define DCB_DSCP_ENABLE_MASK	0x1
12085 #define DCB_DSCP_ENABLE_SHIFT	0
12086 #define DCB_DSCP_ENABLE	1
12087 	u32 dscp_pri_map[8];
12088 };
12089 
12090 struct public_global {
12091 	u32 max_path;
12092 	u32 max_ports;
12093 #define MODE_1P 1
12094 #define MODE_2P 2
12095 #define MODE_3P 3
12096 #define MODE_4P 4
12097 	u32 debug_mb_offset;
12098 	u32 phymod_dbg_mb_offset;
12099 	struct couple_mode_teaming cmt;
12100 	s32 internal_temperature;
12101 	u32 mfw_ver;
12102 	u32 running_bundle_id;
12103 	s32 external_temperature;
12104 	u32 mdump_reason;
12105 	u64 reserved;
12106 	u32 data_ptr;
12107 	u32 data_size;
12108 };
12109 
12110 struct fw_flr_mb {
12111 	u32 aggint;
12112 	u32 opgen_addr;
12113 	u32 accum_ack;
12114 };
12115 
12116 struct public_path {
12117 	struct fw_flr_mb flr_mb;
12118 	u32 mcp_vf_disabled[VF_MAX_STATIC / 32];
12119 
12120 	u32 process_kill;
12121 #define PROCESS_KILL_COUNTER_MASK	0x0000ffff
12122 #define PROCESS_KILL_COUNTER_SHIFT	0
12123 #define PROCESS_KILL_GLOB_AEU_BIT_MASK	0xffff0000
12124 #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT	16
12125 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit)
12126 };
12127 
12128 struct public_port {
12129 	u32 validity_map;
12130 
12131 	u32 link_status;
12132 #define LINK_STATUS_LINK_UP			0x00000001
12133 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK	0x0000001e
12134 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD	(1 << 1)
12135 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD	(2 << 1)
12136 #define LINK_STATUS_SPEED_AND_DUPLEX_10G	(3 << 1)
12137 #define LINK_STATUS_SPEED_AND_DUPLEX_20G	(4 << 1)
12138 #define LINK_STATUS_SPEED_AND_DUPLEX_40G	(5 << 1)
12139 #define LINK_STATUS_SPEED_AND_DUPLEX_50G	(6 << 1)
12140 #define LINK_STATUS_SPEED_AND_DUPLEX_100G	(7 << 1)
12141 #define LINK_STATUS_SPEED_AND_DUPLEX_25G	(8 << 1)
12142 
12143 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED	0x00000020
12144 
12145 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE	0x00000040
12146 #define LINK_STATUS_PARALLEL_DETECTION_USED	0x00000080
12147 
12148 #define LINK_STATUS_PFC_ENABLED				0x00000100
12149 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
12150 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
12151 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE		0x00000800
12152 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE		0x00001000
12153 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE		0x00002000
12154 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE		0x00004000
12155 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE		0x00008000
12156 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE		0x00010000
12157 
12158 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK	0x000C0000
12159 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE	(0 << 18)
12160 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE	(1 << 18)
12161 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE	(2 << 18)
12162 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE		(3 << 18)
12163 
12164 #define LINK_STATUS_SFP_TX_FAULT			0x00100000
12165 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED		0x00200000
12166 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED		0x00400000
12167 #define LINK_STATUS_RX_SIGNAL_PRESENT			0x00800000
12168 #define LINK_STATUS_MAC_LOCAL_FAULT			0x01000000
12169 #define LINK_STATUS_MAC_REMOTE_FAULT			0x02000000
12170 #define LINK_STATUS_UNSUPPORTED_SPD_REQ			0x04000000
12171 
12172 	u32 link_status1;
12173 	u32 ext_phy_fw_version;
12174 	u32 drv_phy_cfg_addr;
12175 
12176 	u32 port_stx;
12177 
12178 	u32 stat_nig_timer;
12179 
12180 	struct port_mf_cfg port_mf_config;
12181 	struct port_stats stats;
12182 
12183 	u32 media_type;
12184 #define MEDIA_UNSPECIFIED	0x0
12185 #define MEDIA_SFPP_10G_FIBER	0x1
12186 #define MEDIA_XFP_FIBER		0x2
12187 #define MEDIA_DA_TWINAX		0x3
12188 #define MEDIA_BASE_T		0x4
12189 #define MEDIA_SFP_1G_FIBER	0x5
12190 #define MEDIA_MODULE_FIBER	0x6
12191 #define MEDIA_KR		0xf0
12192 #define MEDIA_NOT_PRESENT	0xff
12193 
12194 	u32 lfa_status;
12195 	u32 link_change_count;
12196 
12197 	struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS];
12198 	struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS];
12199 	struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf;
12200 
12201 	/* DCBX related MIB */
12202 	struct dcbx_local_params local_admin_dcbx_mib;
12203 	struct dcbx_mib remote_dcbx_mib;
12204 	struct dcbx_mib operational_dcbx_mib;
12205 
12206 	u32 reserved[2];
12207 	u32 transceiver_data;
12208 #define ETH_TRANSCEIVER_STATE_MASK	0x000000FF
12209 #define ETH_TRANSCEIVER_STATE_SHIFT	0x00000000
12210 #define ETH_TRANSCEIVER_STATE_OFFSET	0x00000000
12211 #define ETH_TRANSCEIVER_STATE_UNPLUGGED	0x00000000
12212 #define ETH_TRANSCEIVER_STATE_PRESENT	0x00000001
12213 #define ETH_TRANSCEIVER_STATE_VALID	0x00000003
12214 #define ETH_TRANSCEIVER_STATE_UPDATING	0x00000008
12215 #define ETH_TRANSCEIVER_TYPE_MASK       0x0000FF00
12216 #define ETH_TRANSCEIVER_TYPE_OFFSET     0x8
12217 #define ETH_TRANSCEIVER_TYPE_NONE                       0x00
12218 #define ETH_TRANSCEIVER_TYPE_UNKNOWN                    0xFF
12219 #define ETH_TRANSCEIVER_TYPE_1G_PCC                     0x01
12220 #define ETH_TRANSCEIVER_TYPE_1G_ACC                     0x02
12221 #define ETH_TRANSCEIVER_TYPE_1G_LX                      0x03
12222 #define ETH_TRANSCEIVER_TYPE_1G_SX                      0x04
12223 #define ETH_TRANSCEIVER_TYPE_10G_SR                     0x05
12224 #define ETH_TRANSCEIVER_TYPE_10G_LR                     0x06
12225 #define ETH_TRANSCEIVER_TYPE_10G_LRM                    0x07
12226 #define ETH_TRANSCEIVER_TYPE_10G_ER                     0x08
12227 #define ETH_TRANSCEIVER_TYPE_10G_PCC                    0x09
12228 #define ETH_TRANSCEIVER_TYPE_10G_ACC                    0x0a
12229 #define ETH_TRANSCEIVER_TYPE_XLPPI                      0x0b
12230 #define ETH_TRANSCEIVER_TYPE_40G_LR4                    0x0c
12231 #define ETH_TRANSCEIVER_TYPE_40G_SR4                    0x0d
12232 #define ETH_TRANSCEIVER_TYPE_40G_CR4                    0x0e
12233 #define ETH_TRANSCEIVER_TYPE_100G_AOC                   0x0f
12234 #define ETH_TRANSCEIVER_TYPE_100G_SR4                   0x10
12235 #define ETH_TRANSCEIVER_TYPE_100G_LR4                   0x11
12236 #define ETH_TRANSCEIVER_TYPE_100G_ER4                   0x12
12237 #define ETH_TRANSCEIVER_TYPE_100G_ACC                   0x13
12238 #define ETH_TRANSCEIVER_TYPE_100G_CR4                   0x14
12239 #define ETH_TRANSCEIVER_TYPE_4x10G_SR                   0x15
12240 #define ETH_TRANSCEIVER_TYPE_25G_CA_N                   0x16
12241 #define ETH_TRANSCEIVER_TYPE_25G_ACC_S                  0x17
12242 #define ETH_TRANSCEIVER_TYPE_25G_CA_S                   0x18
12243 #define ETH_TRANSCEIVER_TYPE_25G_ACC_M                  0x19
12244 #define ETH_TRANSCEIVER_TYPE_25G_CA_L                   0x1a
12245 #define ETH_TRANSCEIVER_TYPE_25G_ACC_L                  0x1b
12246 #define ETH_TRANSCEIVER_TYPE_25G_SR                     0x1c
12247 #define ETH_TRANSCEIVER_TYPE_25G_LR                     0x1d
12248 #define ETH_TRANSCEIVER_TYPE_25G_AOC                    0x1e
12249 #define ETH_TRANSCEIVER_TYPE_4x10G                      0x1f
12250 #define ETH_TRANSCEIVER_TYPE_4x25G_CR                   0x20
12251 #define ETH_TRANSCEIVER_TYPE_1000BASET                  0x21
12252 #define ETH_TRANSCEIVER_TYPE_10G_BASET                  0x22
12253 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR      0x30
12254 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR      0x31
12255 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR      0x32
12256 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR     0x33
12257 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR     0x34
12258 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR     0x35
12259 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC    0x36
12260 	u32 wol_info;
12261 	u32 wol_pkt_len;
12262 	u32 wol_pkt_details;
12263 	struct dcb_dscp_map dcb_dscp_map;
12264 
12265 	u32 eee_status;
12266 #define EEE_ACTIVE_BIT			BIT(0)
12267 #define EEE_LD_ADV_STATUS_MASK		0x000000f0
12268 #define EEE_LD_ADV_STATUS_OFFSET	4
12269 #define EEE_1G_ADV			BIT(1)
12270 #define EEE_10G_ADV			BIT(2)
12271 #define EEE_LP_ADV_STATUS_MASK		0x00000f00
12272 #define EEE_LP_ADV_STATUS_OFFSET	8
12273 #define EEE_SUPPORTED_SPEED_MASK	0x0000f000
12274 #define EEE_SUPPORTED_SPEED_OFFSET	12
12275 #define EEE_1G_SUPPORTED		BIT(1)
12276 #define EEE_10G_SUPPORTED		BIT(2)
12277 
12278 	u32 eee_remote;
12279 #define EEE_REMOTE_TW_TX_MASK   0x0000ffff
12280 #define EEE_REMOTE_TW_TX_OFFSET 0
12281 #define EEE_REMOTE_TW_RX_MASK   0xffff0000
12282 #define EEE_REMOTE_TW_RX_OFFSET 16
12283 
12284 	u32 reserved1;
12285 	u32 oem_cfg_port;
12286 #define OEM_CFG_CHANNEL_TYPE_MASK                       0x00000003
12287 #define OEM_CFG_CHANNEL_TYPE_OFFSET                     0
12288 #define OEM_CFG_CHANNEL_TYPE_VLAN_PARTITION             0x1
12289 #define OEM_CFG_CHANNEL_TYPE_STAGGED                    0x2
12290 #define OEM_CFG_SCHED_TYPE_MASK                         0x0000000C
12291 #define OEM_CFG_SCHED_TYPE_OFFSET                       2
12292 #define OEM_CFG_SCHED_TYPE_ETS                          0x1
12293 #define OEM_CFG_SCHED_TYPE_VNIC_BW                      0x2
12294 };
12295 
12296 struct public_func {
12297 	u32 reserved0[2];
12298 
12299 	u32 mtu_size;
12300 
12301 	u32 reserved[7];
12302 
12303 	u32 config;
12304 #define FUNC_MF_CFG_FUNC_HIDE			0x00000001
12305 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING		0x00000002
12306 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT	0x00000001
12307 
12308 #define FUNC_MF_CFG_PROTOCOL_MASK	0x000000f0
12309 #define FUNC_MF_CFG_PROTOCOL_SHIFT	4
12310 #define FUNC_MF_CFG_PROTOCOL_ETHERNET	0x00000000
12311 #define FUNC_MF_CFG_PROTOCOL_ISCSI              0x00000010
12312 #define FUNC_MF_CFG_PROTOCOL_FCOE               0x00000020
12313 #define FUNC_MF_CFG_PROTOCOL_ROCE               0x00000030
12314 #define FUNC_MF_CFG_PROTOCOL_MAX	0x00000030
12315 
12316 #define FUNC_MF_CFG_MIN_BW_MASK		0x0000ff00
12317 #define FUNC_MF_CFG_MIN_BW_SHIFT	8
12318 #define FUNC_MF_CFG_MIN_BW_DEFAULT	0x00000000
12319 #define FUNC_MF_CFG_MAX_BW_MASK		0x00ff0000
12320 #define FUNC_MF_CFG_MAX_BW_SHIFT	16
12321 #define FUNC_MF_CFG_MAX_BW_DEFAULT	0x00640000
12322 
12323 	u32 status;
12324 #define FUNC_STATUS_VIRTUAL_LINK_UP	0x00000001
12325 
12326 	u32 mac_upper;
12327 #define FUNC_MF_CFG_UPPERMAC_MASK	0x0000ffff
12328 #define FUNC_MF_CFG_UPPERMAC_SHIFT	0
12329 #define FUNC_MF_CFG_UPPERMAC_DEFAULT	FUNC_MF_CFG_UPPERMAC_MASK
12330 	u32 mac_lower;
12331 #define FUNC_MF_CFG_LOWERMAC_DEFAULT	0xffffffff
12332 
12333 	u32 fcoe_wwn_port_name_upper;
12334 	u32 fcoe_wwn_port_name_lower;
12335 
12336 	u32 fcoe_wwn_node_name_upper;
12337 	u32 fcoe_wwn_node_name_lower;
12338 
12339 	u32 ovlan_stag;
12340 #define FUNC_MF_CFG_OV_STAG_MASK	0x0000ffff
12341 #define FUNC_MF_CFG_OV_STAG_SHIFT	0
12342 #define FUNC_MF_CFG_OV_STAG_DEFAULT	FUNC_MF_CFG_OV_STAG_MASK
12343 
12344 	u32 pf_allocation;
12345 
12346 	u32 preserve_data;
12347 
12348 	u32 driver_last_activity_ts;
12349 
12350 	u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32];
12351 
12352 	u32 drv_id;
12353 #define DRV_ID_PDA_COMP_VER_MASK	0x0000ffff
12354 #define DRV_ID_PDA_COMP_VER_SHIFT	0
12355 
12356 #define LOAD_REQ_HSI_VERSION		2
12357 #define DRV_ID_MCP_HSI_VER_MASK		0x00ff0000
12358 #define DRV_ID_MCP_HSI_VER_SHIFT	16
12359 #define DRV_ID_MCP_HSI_VER_CURRENT	(LOAD_REQ_HSI_VERSION << \
12360 					 DRV_ID_MCP_HSI_VER_SHIFT)
12361 
12362 #define DRV_ID_DRV_TYPE_MASK		0x7f000000
12363 #define DRV_ID_DRV_TYPE_SHIFT		24
12364 #define DRV_ID_DRV_TYPE_UNKNOWN		(0 << DRV_ID_DRV_TYPE_SHIFT)
12365 #define DRV_ID_DRV_TYPE_LINUX		(1 << DRV_ID_DRV_TYPE_SHIFT)
12366 
12367 #define DRV_ID_DRV_INIT_HW_MASK		0x80000000
12368 #define DRV_ID_DRV_INIT_HW_SHIFT	31
12369 #define DRV_ID_DRV_INIT_HW_FLAG		(1 << DRV_ID_DRV_INIT_HW_SHIFT)
12370 
12371 	u32 oem_cfg_func;
12372 #define OEM_CFG_FUNC_TC_MASK                    0x0000000F
12373 #define OEM_CFG_FUNC_TC_OFFSET                  0
12374 #define OEM_CFG_FUNC_TC_0                       0x0
12375 #define OEM_CFG_FUNC_TC_1                       0x1
12376 #define OEM_CFG_FUNC_TC_2                       0x2
12377 #define OEM_CFG_FUNC_TC_3                       0x3
12378 #define OEM_CFG_FUNC_TC_4                       0x4
12379 #define OEM_CFG_FUNC_TC_5                       0x5
12380 #define OEM_CFG_FUNC_TC_6                       0x6
12381 #define OEM_CFG_FUNC_TC_7                       0x7
12382 
12383 #define OEM_CFG_FUNC_HOST_PRI_CTRL_MASK         0x00000030
12384 #define OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET       4
12385 #define OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC         0x1
12386 #define OEM_CFG_FUNC_HOST_PRI_CTRL_OS           0x2
12387 };
12388 
12389 struct mcp_mac {
12390 	u32 mac_upper;
12391 	u32 mac_lower;
12392 };
12393 
12394 struct mcp_val64 {
12395 	u32 lo;
12396 	u32 hi;
12397 };
12398 
12399 struct mcp_file_att {
12400 	u32 nvm_start_addr;
12401 	u32 len;
12402 };
12403 
12404 struct bist_nvm_image_att {
12405 	u32 return_code;
12406 	u32 image_type;
12407 	u32 nvm_start_addr;
12408 	u32 len;
12409 };
12410 
12411 #define MCP_DRV_VER_STR_SIZE 16
12412 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
12413 #define MCP_DRV_NVM_BUF_LEN 32
12414 struct drv_version_stc {
12415 	u32 version;
12416 	u8 name[MCP_DRV_VER_STR_SIZE - 4];
12417 };
12418 
12419 struct lan_stats_stc {
12420 	u64 ucast_rx_pkts;
12421 	u64 ucast_tx_pkts;
12422 	u32 fcs_err;
12423 	u32 rserved;
12424 };
12425 
12426 struct fcoe_stats_stc {
12427 	u64 rx_pkts;
12428 	u64 tx_pkts;
12429 	u32 fcs_err;
12430 	u32 login_failure;
12431 };
12432 
12433 struct ocbb_data_stc {
12434 	u32 ocbb_host_addr;
12435 	u32 ocsd_host_addr;
12436 	u32 ocsd_req_update_interval;
12437 };
12438 
12439 #define MAX_NUM_OF_SENSORS 7
12440 struct temperature_status_stc {
12441 	u32 num_of_sensors;
12442 	u32 sensor[MAX_NUM_OF_SENSORS];
12443 };
12444 
12445 /* crash dump configuration header */
12446 struct mdump_config_stc {
12447 	u32 version;
12448 	u32 config;
12449 	u32 epoc;
12450 	u32 num_of_logs;
12451 	u32 valid_logs;
12452 };
12453 
12454 enum resource_id_enum {
12455 	RESOURCE_NUM_SB_E = 0,
12456 	RESOURCE_NUM_L2_QUEUE_E = 1,
12457 	RESOURCE_NUM_VPORT_E = 2,
12458 	RESOURCE_NUM_VMQ_E = 3,
12459 	RESOURCE_FACTOR_NUM_RSS_PF_E = 4,
12460 	RESOURCE_FACTOR_RSS_PER_VF_E = 5,
12461 	RESOURCE_NUM_RL_E = 6,
12462 	RESOURCE_NUM_PQ_E = 7,
12463 	RESOURCE_NUM_VF_E = 8,
12464 	RESOURCE_VFC_FILTER_E = 9,
12465 	RESOURCE_ILT_E = 10,
12466 	RESOURCE_CQS_E = 11,
12467 	RESOURCE_GFT_PROFILES_E = 12,
12468 	RESOURCE_NUM_TC_E = 13,
12469 	RESOURCE_NUM_RSS_ENGINES_E = 14,
12470 	RESOURCE_LL2_QUEUE_E = 15,
12471 	RESOURCE_RDMA_STATS_QUEUE_E = 16,
12472 	RESOURCE_BDQ_E = 17,
12473 	RESOURCE_MAX_NUM,
12474 	RESOURCE_NUM_INVALID = 0xFFFFFFFF
12475 };
12476 
12477 /* Resource ID is to be filled by the driver in the MB request
12478  * Size, offset & flags to be filled by the MFW in the MB response
12479  */
12480 struct resource_info {
12481 	enum resource_id_enum res_id;
12482 	u32 size;		/* number of allocated resources */
12483 	u32 offset;		/* Offset of the 1st resource */
12484 	u32 vf_size;
12485 	u32 vf_offset;
12486 	u32 flags;
12487 #define RESOURCE_ELEMENT_STRICT (1 << 0)
12488 };
12489 
12490 #define DRV_ROLE_NONE           0
12491 #define DRV_ROLE_PREBOOT        1
12492 #define DRV_ROLE_OS             2
12493 #define DRV_ROLE_KDUMP          3
12494 
12495 struct load_req_stc {
12496 	u32 drv_ver_0;
12497 	u32 drv_ver_1;
12498 	u32 fw_ver;
12499 	u32 misc0;
12500 #define LOAD_REQ_ROLE_MASK              0x000000FF
12501 #define LOAD_REQ_ROLE_SHIFT             0
12502 #define LOAD_REQ_LOCK_TO_MASK           0x0000FF00
12503 #define LOAD_REQ_LOCK_TO_SHIFT          8
12504 #define LOAD_REQ_LOCK_TO_DEFAULT        0
12505 #define LOAD_REQ_LOCK_TO_NONE           255
12506 #define LOAD_REQ_FORCE_MASK             0x000F0000
12507 #define LOAD_REQ_FORCE_SHIFT            16
12508 #define LOAD_REQ_FORCE_NONE             0
12509 #define LOAD_REQ_FORCE_PF               1
12510 #define LOAD_REQ_FORCE_ALL              2
12511 #define LOAD_REQ_FLAGS0_MASK            0x00F00000
12512 #define LOAD_REQ_FLAGS0_SHIFT           20
12513 #define LOAD_REQ_FLAGS0_AVOID_RESET     (0x1 << 0)
12514 };
12515 
12516 struct load_rsp_stc {
12517 	u32 drv_ver_0;
12518 	u32 drv_ver_1;
12519 	u32 fw_ver;
12520 	u32 misc0;
12521 #define LOAD_RSP_ROLE_MASK              0x000000FF
12522 #define LOAD_RSP_ROLE_SHIFT             0
12523 #define LOAD_RSP_HSI_MASK               0x0000FF00
12524 #define LOAD_RSP_HSI_SHIFT              8
12525 #define LOAD_RSP_FLAGS0_MASK            0x000F0000
12526 #define LOAD_RSP_FLAGS0_SHIFT           16
12527 #define LOAD_RSP_FLAGS0_DRV_EXISTS      (0x1 << 0)
12528 };
12529 
12530 union drv_union_data {
12531 	u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD];
12532 	struct mcp_mac wol_mac;
12533 
12534 	struct eth_phy_cfg drv_phy_cfg;
12535 
12536 	struct mcp_val64 val64;
12537 
12538 	u8 raw_data[MCP_DRV_NVM_BUF_LEN];
12539 
12540 	struct mcp_file_att file_att;
12541 
12542 	u32 ack_vf_disabled[VF_MAX_STATIC / 32];
12543 
12544 	struct drv_version_stc drv_version;
12545 
12546 	struct lan_stats_stc lan_stats;
12547 	struct fcoe_stats_stc fcoe_stats;
12548 	struct ocbb_data_stc ocbb_info;
12549 	struct temperature_status_stc temp_info;
12550 	struct resource_info resource;
12551 	struct bist_nvm_image_att nvm_image_att;
12552 	struct mdump_config_stc mdump_config;
12553 };
12554 
12555 struct public_drv_mb {
12556 	u32 drv_mb_header;
12557 #define DRV_MSG_CODE_MASK			0xffff0000
12558 #define DRV_MSG_CODE_LOAD_REQ			0x10000000
12559 #define DRV_MSG_CODE_LOAD_DONE			0x11000000
12560 #define DRV_MSG_CODE_INIT_HW			0x12000000
12561 #define DRV_MSG_CODE_CANCEL_LOAD_REQ            0x13000000
12562 #define DRV_MSG_CODE_UNLOAD_REQ			0x20000000
12563 #define DRV_MSG_CODE_UNLOAD_DONE		0x21000000
12564 #define DRV_MSG_CODE_INIT_PHY			0x22000000
12565 #define DRV_MSG_CODE_LINK_RESET			0x23000000
12566 #define DRV_MSG_CODE_SET_DCBX			0x25000000
12567 #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG         0x26000000
12568 #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM          0x27000000
12569 #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS    0x28000000
12570 #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER     0x29000000
12571 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE     0x31000000
12572 #define DRV_MSG_CODE_BW_UPDATE_ACK              0x32000000
12573 #define DRV_MSG_CODE_OV_UPDATE_MTU              0x33000000
12574 #define DRV_MSG_GET_RESOURCE_ALLOC_MSG		0x34000000
12575 #define DRV_MSG_SET_RESOURCE_VALUE_MSG		0x35000000
12576 #define DRV_MSG_CODE_OV_UPDATE_WOL              0x38000000
12577 #define DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE     0x39000000
12578 #define DRV_MSG_CODE_GET_OEM_UPDATES            0x41000000
12579 
12580 #define DRV_MSG_CODE_BW_UPDATE_ACK		0x32000000
12581 #define DRV_MSG_CODE_NIG_DRAIN			0x30000000
12582 #define DRV_MSG_CODE_S_TAG_UPDATE_ACK		0x3b000000
12583 #define DRV_MSG_CODE_INITIATE_PF_FLR            0x02010000
12584 #define DRV_MSG_CODE_VF_DISABLED_DONE		0xc0000000
12585 #define DRV_MSG_CODE_CFG_VF_MSIX		0xc0010000
12586 #define DRV_MSG_CODE_CFG_PF_VFS_MSIX		0xc0020000
12587 #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN		0x00010000
12588 #define DRV_MSG_CODE_NVM_PUT_FILE_DATA		0x00020000
12589 #define DRV_MSG_CODE_NVM_GET_FILE_ATT		0x00030000
12590 #define DRV_MSG_CODE_NVM_READ_NVRAM		0x00050000
12591 #define DRV_MSG_CODE_NVM_WRITE_NVRAM		0x00060000
12592 #define DRV_MSG_CODE_MCP_RESET			0x00090000
12593 #define DRV_MSG_CODE_SET_VERSION		0x000f0000
12594 #define DRV_MSG_CODE_MCP_HALT                   0x00100000
12595 #define DRV_MSG_CODE_SET_VMAC                   0x00110000
12596 #define DRV_MSG_CODE_GET_VMAC                   0x00120000
12597 #define DRV_MSG_CODE_VMAC_TYPE_SHIFT            4
12598 #define DRV_MSG_CODE_VMAC_TYPE_MASK             0x30
12599 #define DRV_MSG_CODE_VMAC_TYPE_MAC              1
12600 #define DRV_MSG_CODE_VMAC_TYPE_WWNN             2
12601 #define DRV_MSG_CODE_VMAC_TYPE_WWPN             3
12602 
12603 #define DRV_MSG_CODE_GET_STATS                  0x00130000
12604 #define DRV_MSG_CODE_STATS_TYPE_LAN             1
12605 #define DRV_MSG_CODE_STATS_TYPE_FCOE            2
12606 #define DRV_MSG_CODE_STATS_TYPE_ISCSI           3
12607 #define DRV_MSG_CODE_STATS_TYPE_RDMA            4
12608 
12609 #define DRV_MSG_CODE_TRANSCEIVER_READ           0x00160000
12610 
12611 #define DRV_MSG_CODE_MASK_PARITIES              0x001a0000
12612 
12613 #define DRV_MSG_CODE_BIST_TEST			0x001e0000
12614 #define DRV_MSG_CODE_SET_LED_MODE		0x00200000
12615 #define DRV_MSG_CODE_RESOURCE_CMD	0x00230000
12616 #define DRV_MSG_CODE_GET_TLV_DONE		0x002f0000
12617 
12618 #define RESOURCE_CMD_REQ_RESC_MASK		0x0000001F
12619 #define RESOURCE_CMD_REQ_RESC_SHIFT		0
12620 #define RESOURCE_CMD_REQ_OPCODE_MASK		0x000000E0
12621 #define RESOURCE_CMD_REQ_OPCODE_SHIFT		5
12622 #define RESOURCE_OPCODE_REQ			1
12623 #define RESOURCE_OPCODE_REQ_WO_AGING		2
12624 #define RESOURCE_OPCODE_REQ_W_AGING		3
12625 #define RESOURCE_OPCODE_RELEASE			4
12626 #define RESOURCE_OPCODE_FORCE_RELEASE		5
12627 #define RESOURCE_CMD_REQ_AGE_MASK		0x0000FF00
12628 #define RESOURCE_CMD_REQ_AGE_SHIFT		8
12629 
12630 #define RESOURCE_CMD_RSP_OWNER_MASK		0x000000FF
12631 #define RESOURCE_CMD_RSP_OWNER_SHIFT		0
12632 #define RESOURCE_CMD_RSP_OPCODE_MASK		0x00000700
12633 #define RESOURCE_CMD_RSP_OPCODE_SHIFT		8
12634 #define RESOURCE_OPCODE_GNT			1
12635 #define RESOURCE_OPCODE_BUSY			2
12636 #define RESOURCE_OPCODE_RELEASED		3
12637 #define RESOURCE_OPCODE_RELEASED_PREVIOUS	4
12638 #define RESOURCE_OPCODE_WRONG_OWNER		5
12639 #define RESOURCE_OPCODE_UNKNOWN_CMD		255
12640 
12641 #define RESOURCE_DUMP				0
12642 
12643 #define DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL	0x002b0000
12644 #define DRV_MSG_CODE_OS_WOL			0x002e0000
12645 
12646 #define DRV_MSG_CODE_FEATURE_SUPPORT		0x00300000
12647 #define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT	0x00310000
12648 #define DRV_MSG_SEQ_NUMBER_MASK			0x0000ffff
12649 
12650 	u32 drv_mb_param;
12651 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN         0x00000000
12652 #define DRV_MB_PARAM_UNLOAD_WOL_MCP             0x00000001
12653 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED        0x00000002
12654 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED         0x00000003
12655 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK		0x000000FF
12656 #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT		3
12657 
12658 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MBI     0x3
12659 #define DRV_MB_PARAM_NVM_LEN_OFFSET		24
12660 
12661 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT	0
12662 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK	0x000000FF
12663 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT	8
12664 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK	0x0000FF00
12665 #define DRV_MB_PARAM_LLDP_SEND_MASK		0x00000001
12666 #define DRV_MB_PARAM_LLDP_SEND_SHIFT		0
12667 
12668 #define DRV_MB_PARAM_OV_CURR_CFG_SHIFT		0
12669 #define DRV_MB_PARAM_OV_CURR_CFG_MASK		0x0000000F
12670 #define DRV_MB_PARAM_OV_CURR_CFG_NONE		0
12671 #define DRV_MB_PARAM_OV_CURR_CFG_OS		1
12672 #define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC	2
12673 #define DRV_MB_PARAM_OV_CURR_CFG_OTHER		3
12674 
12675 #define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT	0
12676 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK	0xFFFFFFFF
12677 #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK	0xFF000000
12678 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK	0x00FF0000
12679 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK	0x0000FF00
12680 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK	0x000000FF
12681 
12682 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT	0
12683 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK	0xF
12684 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN	0x1
12685 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED	0x2
12686 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING	0x3
12687 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED	0x4
12688 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE	0x5
12689 
12690 #define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT	0
12691 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK	0xFFFFFFFF
12692 
12693 #define DRV_MB_PARAM_WOL_MASK	(DRV_MB_PARAM_WOL_DEFAULT | \
12694 				 DRV_MB_PARAM_WOL_DISABLED | \
12695 				 DRV_MB_PARAM_WOL_ENABLED)
12696 #define DRV_MB_PARAM_WOL_DEFAULT	DRV_MB_PARAM_UNLOAD_WOL_MCP
12697 #define DRV_MB_PARAM_WOL_DISABLED	DRV_MB_PARAM_UNLOAD_WOL_DISABLED
12698 #define DRV_MB_PARAM_WOL_ENABLED	DRV_MB_PARAM_UNLOAD_WOL_ENABLED
12699 
12700 #define DRV_MB_PARAM_ESWITCH_MODE_MASK	(DRV_MB_PARAM_ESWITCH_MODE_NONE | \
12701 					 DRV_MB_PARAM_ESWITCH_MODE_VEB | \
12702 					 DRV_MB_PARAM_ESWITCH_MODE_VEPA)
12703 #define DRV_MB_PARAM_ESWITCH_MODE_NONE	0x0
12704 #define DRV_MB_PARAM_ESWITCH_MODE_VEB	0x1
12705 #define DRV_MB_PARAM_ESWITCH_MODE_VEPA	0x2
12706 
12707 #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_MASK	0x1
12708 #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET	0
12709 
12710 #define DRV_MB_PARAM_SET_LED_MODE_OPER		0x0
12711 #define DRV_MB_PARAM_SET_LED_MODE_ON		0x1
12712 #define DRV_MB_PARAM_SET_LED_MODE_OFF		0x2
12713 
12714 #define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET		0
12715 #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK		0x00000003
12716 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET		2
12717 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK		0x000000FC
12718 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET	8
12719 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK	0x0000FF00
12720 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET		16
12721 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK		0xFFFF0000
12722 
12723 	/* Resource Allocation params - Driver version support */
12724 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK	0xFFFF0000
12725 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT	16
12726 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK	0x0000FFFF
12727 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT	0
12728 
12729 #define DRV_MB_PARAM_BIST_REGISTER_TEST		1
12730 #define DRV_MB_PARAM_BIST_CLOCK_TEST		2
12731 #define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES	3
12732 #define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX	4
12733 
12734 #define DRV_MB_PARAM_BIST_RC_UNKNOWN		0
12735 #define DRV_MB_PARAM_BIST_RC_PASSED		1
12736 #define DRV_MB_PARAM_BIST_RC_FAILED		2
12737 #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER	3
12738 
12739 #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT	0
12740 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK	0x000000FF
12741 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT	8
12742 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK		0x0000FF00
12743 
12744 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK		0x0000FFFF
12745 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET	0
12746 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE		0x00000002
12747 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK		0x00010000
12748 
12749 	u32 fw_mb_header;
12750 #define FW_MSG_CODE_MASK			0xffff0000
12751 #define FW_MSG_CODE_UNSUPPORTED                 0x00000000
12752 #define FW_MSG_CODE_DRV_LOAD_ENGINE		0x10100000
12753 #define FW_MSG_CODE_DRV_LOAD_PORT		0x10110000
12754 #define FW_MSG_CODE_DRV_LOAD_FUNCTION		0x10120000
12755 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA	0x10200000
12756 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1	0x10210000
12757 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG	0x10220000
12758 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI        0x10230000
12759 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE 0x10300000
12760 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT     0x10310000
12761 #define FW_MSG_CODE_DRV_LOAD_DONE		0x11100000
12762 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE		0x20110000
12763 #define FW_MSG_CODE_DRV_UNLOAD_PORT		0x20120000
12764 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION		0x20130000
12765 #define FW_MSG_CODE_DRV_UNLOAD_DONE		0x21100000
12766 #define FW_MSG_CODE_RESOURCE_ALLOC_OK           0x34000000
12767 #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN      0x35000000
12768 #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED   0x36000000
12769 #define FW_MSG_CODE_S_TAG_UPDATE_ACK_DONE	0x3b000000
12770 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE	0xb0010000
12771 
12772 #define FW_MSG_CODE_NVM_OK			0x00010000
12773 #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK	0x00400000
12774 #define FW_MSG_CODE_PHY_OK			0x00110000
12775 #define FW_MSG_CODE_OK				0x00160000
12776 #define FW_MSG_CODE_ERROR			0x00170000
12777 #define FW_MSG_CODE_TRANSCEIVER_DIAG_OK		0x00160000
12778 #define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR	0x00170000
12779 #define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT	0x00020000
12780 
12781 #define FW_MSG_CODE_OS_WOL_SUPPORTED            0x00800000
12782 #define FW_MSG_CODE_OS_WOL_NOT_SUPPORTED        0x00810000
12783 #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE	0x00870000
12784 #define FW_MSG_SEQ_NUMBER_MASK			0x0000ffff
12785 
12786 	u32 fw_mb_param;
12787 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK	0xFFFF0000
12788 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT	16
12789 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK	0x0000FFFF
12790 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT	0
12791 
12792 	/* get pf rdma protocol command responce */
12793 #define FW_MB_PARAM_GET_PF_RDMA_NONE		0x0
12794 #define FW_MB_PARAM_GET_PF_RDMA_ROCE		0x1
12795 #define FW_MB_PARAM_GET_PF_RDMA_IWARP		0x2
12796 #define FW_MB_PARAM_GET_PF_RDMA_BOTH		0x3
12797 
12798 /* get MFW feature support response */
12799 #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ	0x00000001
12800 #define FW_MB_PARAM_FEATURE_SUPPORT_EEE		0x00000002
12801 #define FW_MB_PARAM_FEATURE_SUPPORT_VLINK	0x00010000
12802 
12803 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR	(1 << 0)
12804 
12805 	u32 drv_pulse_mb;
12806 #define DRV_PULSE_SEQ_MASK			0x00007fff
12807 #define DRV_PULSE_SYSTEM_TIME_MASK		0xffff0000
12808 #define DRV_PULSE_ALWAYS_ALIVE			0x00008000
12809 
12810 	u32 mcp_pulse_mb;
12811 #define MCP_PULSE_SEQ_MASK			0x00007fff
12812 #define MCP_PULSE_ALWAYS_ALIVE			0x00008000
12813 #define MCP_EVENT_MASK				0xffff0000
12814 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ	0x00010000
12815 
12816 	union drv_union_data union_data;
12817 };
12818 
12819 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_MASK	0x00ffffff
12820 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_SHIFT	0
12821 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE_MASK		0xff000000
12822 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE_SHIFT		24
12823 
12824 enum MFW_DRV_MSG_TYPE {
12825 	MFW_DRV_MSG_LINK_CHANGE,
12826 	MFW_DRV_MSG_FLR_FW_ACK_FAILED,
12827 	MFW_DRV_MSG_VF_DISABLED,
12828 	MFW_DRV_MSG_LLDP_DATA_UPDATED,
12829 	MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
12830 	MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
12831 	MFW_DRV_MSG_ERROR_RECOVERY,
12832 	MFW_DRV_MSG_BW_UPDATE,
12833 	MFW_DRV_MSG_S_TAG_UPDATE,
12834 	MFW_DRV_MSG_GET_LAN_STATS,
12835 	MFW_DRV_MSG_GET_FCOE_STATS,
12836 	MFW_DRV_MSG_GET_ISCSI_STATS,
12837 	MFW_DRV_MSG_GET_RDMA_STATS,
12838 	MFW_DRV_MSG_BW_UPDATE10,
12839 	MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
12840 	MFW_DRV_MSG_BW_UPDATE11,
12841 	MFW_DRV_MSG_RESERVED,
12842 	MFW_DRV_MSG_GET_TLV_REQ,
12843 	MFW_DRV_MSG_OEM_CFG_UPDATE,
12844 	MFW_DRV_MSG_MAX
12845 };
12846 
12847 #define MFW_DRV_MSG_MAX_DWORDS(msgs)	(((msgs - 1) >> 2) + 1)
12848 #define MFW_DRV_MSG_DWORD(msg_id)	(msg_id >> 2)
12849 #define MFW_DRV_MSG_OFFSET(msg_id)	((msg_id & 0x3) << 3)
12850 #define MFW_DRV_MSG_MASK(msg_id)	(0xff << MFW_DRV_MSG_OFFSET(msg_id))
12851 
12852 struct public_mfw_mb {
12853 	u32 sup_msgs;
12854 	u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
12855 	u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
12856 };
12857 
12858 enum public_sections {
12859 	PUBLIC_DRV_MB,
12860 	PUBLIC_MFW_MB,
12861 	PUBLIC_GLOBAL,
12862 	PUBLIC_PATH,
12863 	PUBLIC_PORT,
12864 	PUBLIC_FUNC,
12865 	PUBLIC_MAX_SECTIONS
12866 };
12867 
12868 struct mcp_public_data {
12869 	u32 num_sections;
12870 	u32 sections[PUBLIC_MAX_SECTIONS];
12871 	struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX];
12872 	struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX];
12873 	struct public_global global;
12874 	struct public_path path[MCP_GLOB_PATH_MAX];
12875 	struct public_port port[MCP_GLOB_PORT_MAX];
12876 	struct public_func func[MCP_GLOB_FUNC_MAX];
12877 };
12878 
12879 #define MAX_I2C_TRANSACTION_SIZE	16
12880 
12881 /* OCBB definitions */
12882 enum tlvs {
12883 	/* Category 1: Device Properties */
12884 	DRV_TLV_CLP_STR,
12885 	DRV_TLV_CLP_STR_CTD,
12886 	/* Category 6: Device Configuration */
12887 	DRV_TLV_SCSI_TO,
12888 	DRV_TLV_R_T_TOV,
12889 	DRV_TLV_R_A_TOV,
12890 	DRV_TLV_E_D_TOV,
12891 	DRV_TLV_CR_TOV,
12892 	DRV_TLV_BOOT_TYPE,
12893 	/* Category 8: Port Configuration */
12894 	DRV_TLV_NPIV_ENABLED,
12895 	/* Category 10: Function Configuration */
12896 	DRV_TLV_FEATURE_FLAGS,
12897 	DRV_TLV_LOCAL_ADMIN_ADDR,
12898 	DRV_TLV_ADDITIONAL_MAC_ADDR_1,
12899 	DRV_TLV_ADDITIONAL_MAC_ADDR_2,
12900 	DRV_TLV_LSO_MAX_OFFLOAD_SIZE,
12901 	DRV_TLV_LSO_MIN_SEGMENT_COUNT,
12902 	DRV_TLV_PROMISCUOUS_MODE,
12903 	DRV_TLV_TX_DESCRIPTORS_QUEUE_SIZE,
12904 	DRV_TLV_RX_DESCRIPTORS_QUEUE_SIZE,
12905 	DRV_TLV_NUM_OF_NET_QUEUE_VMQ_CFG,
12906 	DRV_TLV_FLEX_NIC_OUTER_VLAN_ID,
12907 	DRV_TLV_OS_DRIVER_STATES,
12908 	DRV_TLV_PXE_BOOT_PROGRESS,
12909 	/* Category 12: FC/FCoE Configuration */
12910 	DRV_TLV_NPIV_STATE,
12911 	DRV_TLV_NUM_OF_NPIV_IDS,
12912 	DRV_TLV_SWITCH_NAME,
12913 	DRV_TLV_SWITCH_PORT_NUM,
12914 	DRV_TLV_SWITCH_PORT_ID,
12915 	DRV_TLV_VENDOR_NAME,
12916 	DRV_TLV_SWITCH_MODEL,
12917 	DRV_TLV_SWITCH_FW_VER,
12918 	DRV_TLV_QOS_PRIORITY_PER_802_1P,
12919 	DRV_TLV_PORT_ALIAS,
12920 	DRV_TLV_PORT_STATE,
12921 	DRV_TLV_FIP_TX_DESCRIPTORS_QUEUE_SIZE,
12922 	DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_SIZE,
12923 	DRV_TLV_LINK_FAILURE_COUNT,
12924 	DRV_TLV_FCOE_BOOT_PROGRESS,
12925 	/* Category 13: iSCSI Configuration */
12926 	DRV_TLV_TARGET_LLMNR_ENABLED,
12927 	DRV_TLV_HEADER_DIGEST_FLAG_ENABLED,
12928 	DRV_TLV_DATA_DIGEST_FLAG_ENABLED,
12929 	DRV_TLV_AUTHENTICATION_METHOD,
12930 	DRV_TLV_ISCSI_BOOT_TARGET_PORTAL,
12931 	DRV_TLV_MAX_FRAME_SIZE,
12932 	DRV_TLV_PDU_TX_DESCRIPTORS_QUEUE_SIZE,
12933 	DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_SIZE,
12934 	DRV_TLV_ISCSI_BOOT_PROGRESS,
12935 	/* Category 20: Device Data */
12936 	DRV_TLV_PCIE_BUS_RX_UTILIZATION,
12937 	DRV_TLV_PCIE_BUS_TX_UTILIZATION,
12938 	DRV_TLV_DEVICE_CPU_CORES_UTILIZATION,
12939 	DRV_TLV_LAST_VALID_DCC_TLV_RECEIVED,
12940 	DRV_TLV_NCSI_RX_BYTES_RECEIVED,
12941 	DRV_TLV_NCSI_TX_BYTES_SENT,
12942 	/* Category 22: Base Port Data */
12943 	DRV_TLV_RX_DISCARDS,
12944 	DRV_TLV_RX_ERRORS,
12945 	DRV_TLV_TX_ERRORS,
12946 	DRV_TLV_TX_DISCARDS,
12947 	DRV_TLV_RX_FRAMES_RECEIVED,
12948 	DRV_TLV_TX_FRAMES_SENT,
12949 	/* Category 23: FC/FCoE Port Data */
12950 	DRV_TLV_RX_BROADCAST_PACKETS,
12951 	DRV_TLV_TX_BROADCAST_PACKETS,
12952 	/* Category 28: Base Function Data */
12953 	DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV4,
12954 	DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV6,
12955 	DRV_TLV_TX_DESCRIPTOR_QUEUE_AVG_DEPTH,
12956 	DRV_TLV_RX_DESCRIPTORS_QUEUE_AVG_DEPTH,
12957 	DRV_TLV_PF_RX_FRAMES_RECEIVED,
12958 	DRV_TLV_RX_BYTES_RECEIVED,
12959 	DRV_TLV_PF_TX_FRAMES_SENT,
12960 	DRV_TLV_TX_BYTES_SENT,
12961 	DRV_TLV_IOV_OFFLOAD,
12962 	DRV_TLV_PCI_ERRORS_CAP_ID,
12963 	DRV_TLV_UNCORRECTABLE_ERROR_STATUS,
12964 	DRV_TLV_UNCORRECTABLE_ERROR_MASK,
12965 	DRV_TLV_CORRECTABLE_ERROR_STATUS,
12966 	DRV_TLV_CORRECTABLE_ERROR_MASK,
12967 	DRV_TLV_PCI_ERRORS_AECC_REGISTER,
12968 	DRV_TLV_TX_QUEUES_EMPTY,
12969 	DRV_TLV_RX_QUEUES_EMPTY,
12970 	DRV_TLV_TX_QUEUES_FULL,
12971 	DRV_TLV_RX_QUEUES_FULL,
12972 	/* Category 29: FC/FCoE Function Data */
12973 	DRV_TLV_FCOE_TX_DESCRIPTOR_QUEUE_AVG_DEPTH,
12974 	DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_AVG_DEPTH,
12975 	DRV_TLV_FCOE_RX_FRAMES_RECEIVED,
12976 	DRV_TLV_FCOE_RX_BYTES_RECEIVED,
12977 	DRV_TLV_FCOE_TX_FRAMES_SENT,
12978 	DRV_TLV_FCOE_TX_BYTES_SENT,
12979 	DRV_TLV_CRC_ERROR_COUNT,
12980 	DRV_TLV_CRC_ERROR_1_RECEIVED_SOURCE_FC_ID,
12981 	DRV_TLV_CRC_ERROR_1_TIMESTAMP,
12982 	DRV_TLV_CRC_ERROR_2_RECEIVED_SOURCE_FC_ID,
12983 	DRV_TLV_CRC_ERROR_2_TIMESTAMP,
12984 	DRV_TLV_CRC_ERROR_3_RECEIVED_SOURCE_FC_ID,
12985 	DRV_TLV_CRC_ERROR_3_TIMESTAMP,
12986 	DRV_TLV_CRC_ERROR_4_RECEIVED_SOURCE_FC_ID,
12987 	DRV_TLV_CRC_ERROR_4_TIMESTAMP,
12988 	DRV_TLV_CRC_ERROR_5_RECEIVED_SOURCE_FC_ID,
12989 	DRV_TLV_CRC_ERROR_5_TIMESTAMP,
12990 	DRV_TLV_LOSS_OF_SYNC_ERROR_COUNT,
12991 	DRV_TLV_LOSS_OF_SIGNAL_ERRORS,
12992 	DRV_TLV_PRIMITIVE_SEQUENCE_PROTOCOL_ERROR_COUNT,
12993 	DRV_TLV_DISPARITY_ERROR_COUNT,
12994 	DRV_TLV_CODE_VIOLATION_ERROR_COUNT,
12995 	DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_1,
12996 	DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_2,
12997 	DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_3,
12998 	DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_4,
12999 	DRV_TLV_LAST_FLOGI_TIMESTAMP,
13000 	DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_1,
13001 	DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_2,
13002 	DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_3,
13003 	DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_4,
13004 	DRV_TLV_LAST_FLOGI_ACC_TIMESTAMP,
13005 	DRV_TLV_LAST_FLOGI_RJT,
13006 	DRV_TLV_LAST_FLOGI_RJT_TIMESTAMP,
13007 	DRV_TLV_FDISCS_SENT_COUNT,
13008 	DRV_TLV_FDISC_ACCS_RECEIVED,
13009 	DRV_TLV_FDISC_RJTS_RECEIVED,
13010 	DRV_TLV_PLOGI_SENT_COUNT,
13011 	DRV_TLV_PLOGI_ACCS_RECEIVED,
13012 	DRV_TLV_PLOGI_RJTS_RECEIVED,
13013 	DRV_TLV_PLOGI_1_SENT_DESTINATION_FC_ID,
13014 	DRV_TLV_PLOGI_1_TIMESTAMP,
13015 	DRV_TLV_PLOGI_2_SENT_DESTINATION_FC_ID,
13016 	DRV_TLV_PLOGI_2_TIMESTAMP,
13017 	DRV_TLV_PLOGI_3_SENT_DESTINATION_FC_ID,
13018 	DRV_TLV_PLOGI_3_TIMESTAMP,
13019 	DRV_TLV_PLOGI_4_SENT_DESTINATION_FC_ID,
13020 	DRV_TLV_PLOGI_4_TIMESTAMP,
13021 	DRV_TLV_PLOGI_5_SENT_DESTINATION_FC_ID,
13022 	DRV_TLV_PLOGI_5_TIMESTAMP,
13023 	DRV_TLV_PLOGI_1_ACC_RECEIVED_SOURCE_FC_ID,
13024 	DRV_TLV_PLOGI_1_ACC_TIMESTAMP,
13025 	DRV_TLV_PLOGI_2_ACC_RECEIVED_SOURCE_FC_ID,
13026 	DRV_TLV_PLOGI_2_ACC_TIMESTAMP,
13027 	DRV_TLV_PLOGI_3_ACC_RECEIVED_SOURCE_FC_ID,
13028 	DRV_TLV_PLOGI_3_ACC_TIMESTAMP,
13029 	DRV_TLV_PLOGI_4_ACC_RECEIVED_SOURCE_FC_ID,
13030 	DRV_TLV_PLOGI_4_ACC_TIMESTAMP,
13031 	DRV_TLV_PLOGI_5_ACC_RECEIVED_SOURCE_FC_ID,
13032 	DRV_TLV_PLOGI_5_ACC_TIMESTAMP,
13033 	DRV_TLV_LOGOS_ISSUED,
13034 	DRV_TLV_LOGO_ACCS_RECEIVED,
13035 	DRV_TLV_LOGO_RJTS_RECEIVED,
13036 	DRV_TLV_LOGO_1_RECEIVED_SOURCE_FC_ID,
13037 	DRV_TLV_LOGO_1_TIMESTAMP,
13038 	DRV_TLV_LOGO_2_RECEIVED_SOURCE_FC_ID,
13039 	DRV_TLV_LOGO_2_TIMESTAMP,
13040 	DRV_TLV_LOGO_3_RECEIVED_SOURCE_FC_ID,
13041 	DRV_TLV_LOGO_3_TIMESTAMP,
13042 	DRV_TLV_LOGO_4_RECEIVED_SOURCE_FC_ID,
13043 	DRV_TLV_LOGO_4_TIMESTAMP,
13044 	DRV_TLV_LOGO_5_RECEIVED_SOURCE_FC_ID,
13045 	DRV_TLV_LOGO_5_TIMESTAMP,
13046 	DRV_TLV_LOGOS_RECEIVED,
13047 	DRV_TLV_ACCS_ISSUED,
13048 	DRV_TLV_PRLIS_ISSUED,
13049 	DRV_TLV_ACCS_RECEIVED,
13050 	DRV_TLV_ABTS_SENT_COUNT,
13051 	DRV_TLV_ABTS_ACCS_RECEIVED,
13052 	DRV_TLV_ABTS_RJTS_RECEIVED,
13053 	DRV_TLV_ABTS_1_SENT_DESTINATION_FC_ID,
13054 	DRV_TLV_ABTS_1_TIMESTAMP,
13055 	DRV_TLV_ABTS_2_SENT_DESTINATION_FC_ID,
13056 	DRV_TLV_ABTS_2_TIMESTAMP,
13057 	DRV_TLV_ABTS_3_SENT_DESTINATION_FC_ID,
13058 	DRV_TLV_ABTS_3_TIMESTAMP,
13059 	DRV_TLV_ABTS_4_SENT_DESTINATION_FC_ID,
13060 	DRV_TLV_ABTS_4_TIMESTAMP,
13061 	DRV_TLV_ABTS_5_SENT_DESTINATION_FC_ID,
13062 	DRV_TLV_ABTS_5_TIMESTAMP,
13063 	DRV_TLV_RSCNS_RECEIVED,
13064 	DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_1,
13065 	DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_2,
13066 	DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_3,
13067 	DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_4,
13068 	DRV_TLV_LUN_RESETS_ISSUED,
13069 	DRV_TLV_ABORT_TASK_SETS_ISSUED,
13070 	DRV_TLV_TPRLOS_SENT,
13071 	DRV_TLV_NOS_SENT_COUNT,
13072 	DRV_TLV_NOS_RECEIVED_COUNT,
13073 	DRV_TLV_OLS_COUNT,
13074 	DRV_TLV_LR_COUNT,
13075 	DRV_TLV_LRR_COUNT,
13076 	DRV_TLV_LIP_SENT_COUNT,
13077 	DRV_TLV_LIP_RECEIVED_COUNT,
13078 	DRV_TLV_EOFA_COUNT,
13079 	DRV_TLV_EOFNI_COUNT,
13080 	DRV_TLV_SCSI_STATUS_CHECK_CONDITION_COUNT,
13081 	DRV_TLV_SCSI_STATUS_CONDITION_MET_COUNT,
13082 	DRV_TLV_SCSI_STATUS_BUSY_COUNT,
13083 	DRV_TLV_SCSI_STATUS_INTERMEDIATE_COUNT,
13084 	DRV_TLV_SCSI_STATUS_INTERMEDIATE_CONDITION_MET_COUNT,
13085 	DRV_TLV_SCSI_STATUS_RESERVATION_CONFLICT_COUNT,
13086 	DRV_TLV_SCSI_STATUS_TASK_SET_FULL_COUNT,
13087 	DRV_TLV_SCSI_STATUS_ACA_ACTIVE_COUNT,
13088 	DRV_TLV_SCSI_STATUS_TASK_ABORTED_COUNT,
13089 	DRV_TLV_SCSI_CHECK_CONDITION_1_RECEIVED_SK_ASC_ASCQ,
13090 	DRV_TLV_SCSI_CHECK_1_TIMESTAMP,
13091 	DRV_TLV_SCSI_CHECK_CONDITION_2_RECEIVED_SK_ASC_ASCQ,
13092 	DRV_TLV_SCSI_CHECK_2_TIMESTAMP,
13093 	DRV_TLV_SCSI_CHECK_CONDITION_3_RECEIVED_SK_ASC_ASCQ,
13094 	DRV_TLV_SCSI_CHECK_3_TIMESTAMP,
13095 	DRV_TLV_SCSI_CHECK_CONDITION_4_RECEIVED_SK_ASC_ASCQ,
13096 	DRV_TLV_SCSI_CHECK_4_TIMESTAMP,
13097 	DRV_TLV_SCSI_CHECK_CONDITION_5_RECEIVED_SK_ASC_ASCQ,
13098 	DRV_TLV_SCSI_CHECK_5_TIMESTAMP,
13099 	/* Category 30: iSCSI Function Data */
13100 	DRV_TLV_PDU_TX_DESCRIPTOR_QUEUE_AVG_DEPTH,
13101 	DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_AVG_DEPTH,
13102 	DRV_TLV_ISCSI_PDU_RX_FRAMES_RECEIVED,
13103 	DRV_TLV_ISCSI_PDU_RX_BYTES_RECEIVED,
13104 	DRV_TLV_ISCSI_PDU_TX_FRAMES_SENT,
13105 	DRV_TLV_ISCSI_PDU_TX_BYTES_SENT
13106 };
13107 
13108 struct nvm_cfg_mac_address {
13109 	u32 mac_addr_hi;
13110 #define NVM_CFG_MAC_ADDRESS_HI_MASK	0x0000FFFF
13111 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET	0
13112 	u32 mac_addr_lo;
13113 };
13114 
13115 struct nvm_cfg1_glob {
13116 	u32 generic_cont0;
13117 #define NVM_CFG1_GLOB_MF_MODE_MASK		0x00000FF0
13118 #define NVM_CFG1_GLOB_MF_MODE_OFFSET		4
13119 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED	0x0
13120 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT		0x1
13121 #define NVM_CFG1_GLOB_MF_MODE_SPIO4		0x2
13122 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0		0x3
13123 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5		0x4
13124 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0		0x5
13125 #define NVM_CFG1_GLOB_MF_MODE_BD		0x6
13126 #define NVM_CFG1_GLOB_MF_MODE_UFP		0x7
13127 	u32 engineering_change[3];
13128 	u32 manufacturing_id;
13129 	u32 serial_number[4];
13130 	u32 pcie_cfg;
13131 	u32 mgmt_traffic;
13132 	u32 core_cfg;
13133 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK		0x000000FF
13134 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET		0
13135 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G	0x0
13136 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G		0x1
13137 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G	0x2
13138 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F		0x3
13139 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E	0x4
13140 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G	0x5
13141 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G		0xB
13142 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G		0xC
13143 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G		0xD
13144 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G		0xE
13145 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G		0xF
13146 
13147 	u32 e_lane_cfg1;
13148 	u32 e_lane_cfg2;
13149 	u32 f_lane_cfg1;
13150 	u32 f_lane_cfg2;
13151 	u32 mps10_preemphasis;
13152 	u32 mps10_driver_current;
13153 	u32 mps25_preemphasis;
13154 	u32 mps25_driver_current;
13155 	u32 pci_id;
13156 	u32 pci_subsys_id;
13157 	u32 bar;
13158 	u32 mps10_txfir_main;
13159 	u32 mps10_txfir_post;
13160 	u32 mps25_txfir_main;
13161 	u32 mps25_txfir_post;
13162 	u32 manufacture_ver;
13163 	u32 manufacture_time;
13164 	u32 led_global_settings;
13165 	u32 generic_cont1;
13166 	u32 mbi_version;
13167 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK		0x000000FF
13168 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET		0
13169 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK		0x0000FF00
13170 #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET		8
13171 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK		0x00FF0000
13172 #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET		16
13173 	u32 mbi_date;
13174 	u32 misc_sig;
13175 	u32 device_capabilities;
13176 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET	0x1
13177 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE		0x2
13178 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI		0x4
13179 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE		0x8
13180 	u32 power_dissipated;
13181 	u32 power_consumed;
13182 	u32 efi_version;
13183 	u32 multi_network_modes_capability;
13184 	u32 reserved[41];
13185 };
13186 
13187 struct nvm_cfg1_path {
13188 	u32 reserved[30];
13189 };
13190 
13191 struct nvm_cfg1_port {
13192 	u32 reserved__m_relocated_to_option_123;
13193 	u32 reserved__m_relocated_to_option_124;
13194 	u32 generic_cont0;
13195 #define NVM_CFG1_PORT_DCBX_MODE_MASK				0x000F0000
13196 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET				16
13197 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED			0x0
13198 #define NVM_CFG1_PORT_DCBX_MODE_IEEE				0x1
13199 #define NVM_CFG1_PORT_DCBX_MODE_CEE				0x2
13200 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC				0x3
13201 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK		0x00F00000
13202 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET		20
13203 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET	0x1
13204 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE		0x2
13205 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI		0x4
13206 	u32 pcie_cfg;
13207 	u32 features;
13208 	u32 speed_cap_mask;
13209 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK		0x0000FFFF
13210 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET		0
13211 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G		0x1
13212 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G		0x2
13213 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G             0x4
13214 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G		0x8
13215 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G		0x10
13216 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G		0x20
13217 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G		0x40
13218 	u32 link_settings;
13219 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK			0x0000000F
13220 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET			0
13221 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG			0x0
13222 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G				0x1
13223 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G			0x2
13224 #define NVM_CFG1_PORT_DRV_LINK_SPEED_20G                        0x3
13225 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G			0x4
13226 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G			0x5
13227 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G			0x6
13228 #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G			0x7
13229 #define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ			0x8
13230 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK			0x00000070
13231 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET			4
13232 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG			0x1
13233 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX			0x2
13234 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX			0x4
13235 	u32 phy_cfg;
13236 	u32 mgmt_traffic;
13237 
13238 	u32 ext_phy;
13239 	/* EEE power saving mode */
13240 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK		0x00FF0000
13241 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET		16
13242 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED		0x0
13243 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED		0x1
13244 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE		0x2
13245 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY		0x3
13246 
13247 	u32 mba_cfg1;
13248 	u32 mba_cfg2;
13249 	u32 vf_cfg;
13250 	struct nvm_cfg_mac_address lldp_mac_address;
13251 	u32 led_port_settings;
13252 	u32 transceiver_00;
13253 	u32 device_ids;
13254 	u32 board_cfg;
13255 #define NVM_CFG1_PORT_PORT_TYPE_MASK                            0x000000FF
13256 #define NVM_CFG1_PORT_PORT_TYPE_OFFSET                          0
13257 #define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED                       0x0
13258 #define NVM_CFG1_PORT_PORT_TYPE_MODULE                          0x1
13259 #define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE                       0x2
13260 #define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY                         0x3
13261 #define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE                    0x4
13262 	u32 mnm_10g_cap;
13263 	u32 mnm_10g_ctrl;
13264 	u32 mnm_10g_misc;
13265 	u32 mnm_25g_cap;
13266 	u32 mnm_25g_ctrl;
13267 	u32 mnm_25g_misc;
13268 	u32 mnm_40g_cap;
13269 	u32 mnm_40g_ctrl;
13270 	u32 mnm_40g_misc;
13271 	u32 mnm_50g_cap;
13272 	u32 mnm_50g_ctrl;
13273 	u32 mnm_50g_misc;
13274 	u32 mnm_100g_cap;
13275 	u32 mnm_100g_ctrl;
13276 	u32 mnm_100g_misc;
13277 	u32 reserved[116];
13278 };
13279 
13280 struct nvm_cfg1_func {
13281 	struct nvm_cfg_mac_address mac_address;
13282 	u32 rsrv1;
13283 	u32 rsrv2;
13284 	u32 device_id;
13285 	u32 cmn_cfg;
13286 	u32 pci_cfg;
13287 	struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr;
13288 	struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr;
13289 	u32 preboot_generic_cfg;
13290 	u32 reserved[8];
13291 };
13292 
13293 struct nvm_cfg1 {
13294 	struct nvm_cfg1_glob glob;
13295 	struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX];
13296 	struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX];
13297 	struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX];
13298 };
13299 
13300 enum spad_sections {
13301 	SPAD_SECTION_TRACE,
13302 	SPAD_SECTION_NVM_CFG,
13303 	SPAD_SECTION_PUBLIC,
13304 	SPAD_SECTION_PRIVATE,
13305 	SPAD_SECTION_MAX
13306 };
13307 
13308 #define MCP_TRACE_SIZE          2048	/* 2kb */
13309 
13310 /* This section is located at a fixed location in the beginning of the
13311  * scratchpad, to ensure that the MCP trace is not run over during MFW upgrade.
13312  * All the rest of data has a floating location which differs from version to
13313  * version, and is pointed by the mcp_meta_data below.
13314  * Moreover, the spad_layout section is part of the MFW firmware, and is loaded
13315  * with it from nvram in order to clear this portion.
13316  */
13317 struct static_init {
13318 	u32 num_sections;
13319 	offsize_t sections[SPAD_SECTION_MAX];
13320 #define SECTION(_sec_) (*((offsize_t *)(STRUCT_OFFSET(sections[_sec_]))))
13321 
13322 	struct mcp_trace trace;
13323 #define MCP_TRACE_P ((struct mcp_trace *)(STRUCT_OFFSET(trace)))
13324 	u8 trace_buffer[MCP_TRACE_SIZE];
13325 #define MCP_TRACE_BUF ((u8 *)(STRUCT_OFFSET(trace_buffer)))
13326 	/* running_mfw has the same definition as in nvm_map.h.
13327 	 * This bit indicate both the running dir, and the running bundle.
13328 	 * It is set once when the LIM is loaded.
13329 	 */
13330 	u32 running_mfw;
13331 #define RUNNING_MFW (*((u32 *)(STRUCT_OFFSET(running_mfw))))
13332 	u32 build_time;
13333 #define MFW_BUILD_TIME (*((u32 *)(STRUCT_OFFSET(build_time))))
13334 	u32 reset_type;
13335 #define RESET_TYPE (*((u32 *)(STRUCT_OFFSET(reset_type))))
13336 	u32 mfw_secure_mode;
13337 #define MFW_SECURE_MODE (*((u32 *)(STRUCT_OFFSET(mfw_secure_mode))))
13338 	u16 pme_status_pf_bitmap;
13339 #define PME_STATUS_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_status_pf_bitmap))))
13340 	u16 pme_enable_pf_bitmap;
13341 #define PME_ENABLE_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_enable_pf_bitmap))))
13342 	u32 mim_nvm_addr;
13343 	u32 mim_start_addr;
13344 	u32 ah_pcie_link_params;
13345 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_MASK     (0x000000ff)
13346 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_SHIFT    (0)
13347 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_MASK     (0x0000ff00)
13348 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_SHIFT    (8)
13349 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_MASK      (0x00ff0000)
13350 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_SHIFT     (16)
13351 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_MASK       (0xff000000)
13352 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_SHIFT      (24)
13353 #define AH_PCIE_LINK_PARAMS (*((u32 *)(STRUCT_OFFSET(ah_pcie_link_params))))
13354 
13355 	u32 rsrv_persist[5];	/* Persist reserved for MFW upgrades */
13356 };
13357 
13358 #define NVM_MAGIC_VALUE		0x669955aa
13359 
13360 enum nvm_image_type {
13361 	NVM_TYPE_TIM1 = 0x01,
13362 	NVM_TYPE_TIM2 = 0x02,
13363 	NVM_TYPE_MIM1 = 0x03,
13364 	NVM_TYPE_MIM2 = 0x04,
13365 	NVM_TYPE_MBA = 0x05,
13366 	NVM_TYPE_MODULES_PN = 0x06,
13367 	NVM_TYPE_VPD = 0x07,
13368 	NVM_TYPE_MFW_TRACE1 = 0x08,
13369 	NVM_TYPE_MFW_TRACE2 = 0x09,
13370 	NVM_TYPE_NVM_CFG1 = 0x0a,
13371 	NVM_TYPE_L2B = 0x0b,
13372 	NVM_TYPE_DIR1 = 0x0c,
13373 	NVM_TYPE_EAGLE_FW1 = 0x0d,
13374 	NVM_TYPE_FALCON_FW1 = 0x0e,
13375 	NVM_TYPE_PCIE_FW1 = 0x0f,
13376 	NVM_TYPE_HW_SET = 0x10,
13377 	NVM_TYPE_LIM = 0x11,
13378 	NVM_TYPE_AVS_FW1 = 0x12,
13379 	NVM_TYPE_DIR2 = 0x13,
13380 	NVM_TYPE_CCM = 0x14,
13381 	NVM_TYPE_EAGLE_FW2 = 0x15,
13382 	NVM_TYPE_FALCON_FW2 = 0x16,
13383 	NVM_TYPE_PCIE_FW2 = 0x17,
13384 	NVM_TYPE_AVS_FW2 = 0x18,
13385 	NVM_TYPE_INIT_HW = 0x19,
13386 	NVM_TYPE_DEFAULT_CFG = 0x1a,
13387 	NVM_TYPE_MDUMP = 0x1b,
13388 	NVM_TYPE_META = 0x1c,
13389 	NVM_TYPE_ISCSI_CFG = 0x1d,
13390 	NVM_TYPE_FCOE_CFG = 0x1f,
13391 	NVM_TYPE_ETH_PHY_FW1 = 0x20,
13392 	NVM_TYPE_ETH_PHY_FW2 = 0x21,
13393 	NVM_TYPE_MAX,
13394 };
13395 
13396 #define DIR_ID_1    (0)
13397 
13398 #endif
13399