1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2 /* QLogic qed NIC Driver 3 * Copyright (c) 2015-2017 QLogic Corporation 4 * Copyright (c) 2019-2020 Marvell International Ltd. 5 */ 6 7 #ifndef _QED_HSI_H 8 #define _QED_HSI_H 9 10 #include <linux/types.h> 11 #include <linux/io.h> 12 #include <linux/bitops.h> 13 #include <linux/delay.h> 14 #include <linux/kernel.h> 15 #include <linux/list.h> 16 #include <linux/slab.h> 17 #include <linux/qed/common_hsi.h> 18 #include <linux/qed/storage_common.h> 19 #include <linux/qed/tcp_common.h> 20 #include <linux/qed/fcoe_common.h> 21 #include <linux/qed/eth_common.h> 22 #include <linux/qed/iscsi_common.h> 23 #include <linux/qed/nvmetcp_common.h> 24 #include <linux/qed/iwarp_common.h> 25 #include <linux/qed/rdma_common.h> 26 #include <linux/qed/roce_common.h> 27 #include <linux/qed/qed_fcoe_if.h> 28 29 struct qed_hwfn; 30 struct qed_ptt; 31 32 /* Opcodes for the event ring */ 33 enum common_event_opcode { 34 COMMON_EVENT_PF_START, 35 COMMON_EVENT_PF_STOP, 36 COMMON_EVENT_VF_START, 37 COMMON_EVENT_VF_STOP, 38 COMMON_EVENT_VF_PF_CHANNEL, 39 COMMON_EVENT_VF_FLR, 40 COMMON_EVENT_PF_UPDATE, 41 COMMON_EVENT_MALICIOUS_VF, 42 COMMON_EVENT_RL_UPDATE, 43 COMMON_EVENT_EMPTY, 44 MAX_COMMON_EVENT_OPCODE 45 }; 46 47 /* Common Ramrod Command IDs */ 48 enum common_ramrod_cmd_id { 49 COMMON_RAMROD_UNUSED, 50 COMMON_RAMROD_PF_START, 51 COMMON_RAMROD_PF_STOP, 52 COMMON_RAMROD_VF_START, 53 COMMON_RAMROD_VF_STOP, 54 COMMON_RAMROD_PF_UPDATE, 55 COMMON_RAMROD_RL_UPDATE, 56 COMMON_RAMROD_EMPTY, 57 MAX_COMMON_RAMROD_CMD_ID 58 }; 59 60 /* How ll2 should deal with packet upon errors */ 61 enum core_error_handle { 62 LL2_DROP_PACKET, 63 LL2_DO_NOTHING, 64 LL2_ASSERT, 65 MAX_CORE_ERROR_HANDLE 66 }; 67 68 /* Opcodes for the event ring */ 69 enum core_event_opcode { 70 CORE_EVENT_TX_QUEUE_START, 71 CORE_EVENT_TX_QUEUE_STOP, 72 CORE_EVENT_RX_QUEUE_START, 73 CORE_EVENT_RX_QUEUE_STOP, 74 CORE_EVENT_RX_QUEUE_FLUSH, 75 CORE_EVENT_TX_QUEUE_UPDATE, 76 CORE_EVENT_QUEUE_STATS_QUERY, 77 MAX_CORE_EVENT_OPCODE 78 }; 79 80 /* The L4 pseudo checksum mode for Core */ 81 enum core_l4_pseudo_checksum_mode { 82 CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH, 83 CORE_L4_PSEUDO_CSUM_ZERO_LENGTH, 84 MAX_CORE_L4_PSEUDO_CHECKSUM_MODE 85 }; 86 87 /* Light-L2 RX Producers in Tstorm RAM */ 88 struct core_ll2_port_stats { 89 struct regpair gsi_invalid_hdr; 90 struct regpair gsi_invalid_pkt_length; 91 struct regpair gsi_unsupported_pkt_typ; 92 struct regpair gsi_crcchksm_error; 93 }; 94 95 /* LL2 TX Per Queue Stats */ 96 struct core_ll2_pstorm_per_queue_stat { 97 struct regpair sent_ucast_bytes; 98 struct regpair sent_mcast_bytes; 99 struct regpair sent_bcast_bytes; 100 struct regpair sent_ucast_pkts; 101 struct regpair sent_mcast_pkts; 102 struct regpair sent_bcast_pkts; 103 struct regpair error_drop_pkts; 104 }; 105 106 /* Light-L2 RX Producers in Tstorm RAM */ 107 struct core_ll2_rx_prod { 108 __le16 bd_prod; 109 __le16 cqe_prod; 110 }; 111 112 struct core_ll2_tstorm_per_queue_stat { 113 struct regpair packet_too_big_discard; 114 struct regpair no_buff_discard; 115 }; 116 117 struct core_ll2_ustorm_per_queue_stat { 118 struct regpair rcv_ucast_bytes; 119 struct regpair rcv_mcast_bytes; 120 struct regpair rcv_bcast_bytes; 121 struct regpair rcv_ucast_pkts; 122 struct regpair rcv_mcast_pkts; 123 struct regpair rcv_bcast_pkts; 124 }; 125 126 /* Structure for doorbell data, in PWM mode, for RX producers update. */ 127 struct core_pwm_prod_update_data { 128 __le16 icid; /* internal CID */ 129 u8 reserved0; 130 u8 params; 131 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_MASK 0x3 132 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_SHIFT 0 133 #define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_MASK 0x3F /* Set 0 */ 134 #define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_SHIFT 2 135 struct core_ll2_rx_prod prod; /* Producers */ 136 }; 137 138 /* Core Ramrod Command IDs (light L2) */ 139 enum core_ramrod_cmd_id { 140 CORE_RAMROD_UNUSED, 141 CORE_RAMROD_RX_QUEUE_START, 142 CORE_RAMROD_TX_QUEUE_START, 143 CORE_RAMROD_RX_QUEUE_STOP, 144 CORE_RAMROD_TX_QUEUE_STOP, 145 CORE_RAMROD_RX_QUEUE_FLUSH, 146 CORE_RAMROD_TX_QUEUE_UPDATE, 147 CORE_RAMROD_QUEUE_STATS_QUERY, 148 MAX_CORE_RAMROD_CMD_ID 149 }; 150 151 /* Core RX CQE Type for Light L2 */ 152 enum core_roce_flavor_type { 153 CORE_ROCE, 154 CORE_RROCE, 155 MAX_CORE_ROCE_FLAVOR_TYPE 156 }; 157 158 /* Specifies how ll2 should deal with packets errors: packet_too_big and 159 * no_buff. 160 */ 161 struct core_rx_action_on_error { 162 u8 error_type; 163 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3 164 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0 165 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3 166 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT 2 167 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF 168 #define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT 4 169 }; 170 171 /* Core RX BD for Light L2 */ 172 struct core_rx_bd { 173 struct regpair addr; 174 __le16 reserved[4]; 175 }; 176 177 /* Core RX CM offload BD for Light L2 */ 178 struct core_rx_bd_with_buff_len { 179 struct regpair addr; 180 __le16 buff_length; 181 __le16 reserved[3]; 182 }; 183 184 /* Core RX CM offload BD for Light L2 */ 185 union core_rx_bd_union { 186 struct core_rx_bd rx_bd; 187 struct core_rx_bd_with_buff_len rx_bd_with_len; 188 }; 189 190 /* Opaque Data for Light L2 RX CQE */ 191 struct core_rx_cqe_opaque_data { 192 __le32 data[2]; 193 }; 194 195 /* Core RX CQE Type for Light L2 */ 196 enum core_rx_cqe_type { 197 CORE_RX_CQE_ILLEGAL_TYPE, 198 CORE_RX_CQE_TYPE_REGULAR, 199 CORE_RX_CQE_TYPE_GSI_OFFLOAD, 200 CORE_RX_CQE_TYPE_SLOW_PATH, 201 MAX_CORE_RX_CQE_TYPE 202 }; 203 204 /* Core RX CQE for Light L2 */ 205 struct core_rx_fast_path_cqe { 206 u8 type; 207 u8 placement_offset; 208 struct parsing_and_err_flags parse_flags; 209 __le16 packet_length; 210 __le16 vlan; 211 struct core_rx_cqe_opaque_data opaque_data; 212 struct parsing_err_flags err_flags; 213 __le16 reserved0; 214 __le32 reserved1[3]; 215 }; 216 217 /* Core Rx CM offload CQE */ 218 struct core_rx_gsi_offload_cqe { 219 u8 type; 220 u8 data_length_error; 221 struct parsing_and_err_flags parse_flags; 222 __le16 data_length; 223 __le16 vlan; 224 __le32 src_mac_addrhi; 225 __le16 src_mac_addrlo; 226 __le16 qp_id; 227 __le32 src_qp; 228 struct core_rx_cqe_opaque_data opaque_data; 229 __le32 reserved; 230 }; 231 232 /* Core RX CQE for Light L2 */ 233 struct core_rx_slow_path_cqe { 234 u8 type; 235 u8 ramrod_cmd_id; 236 __le16 echo; 237 struct core_rx_cqe_opaque_data opaque_data; 238 __le32 reserved1[5]; 239 }; 240 241 /* Core RX CM offload BD for Light L2 */ 242 union core_rx_cqe_union { 243 struct core_rx_fast_path_cqe rx_cqe_fp; 244 struct core_rx_gsi_offload_cqe rx_cqe_gsi; 245 struct core_rx_slow_path_cqe rx_cqe_sp; 246 }; 247 248 /* Ramrod data for rx queue start ramrod */ 249 struct core_rx_start_ramrod_data { 250 struct regpair bd_base; 251 struct regpair cqe_pbl_addr; 252 __le16 mtu; 253 __le16 sb_id; 254 u8 sb_index; 255 u8 complete_cqe_flg; 256 u8 complete_event_flg; 257 u8 drop_ttl0_flg; 258 __le16 num_of_pbl_pages; 259 u8 inner_vlan_stripping_en; 260 u8 report_outer_vlan; 261 u8 queue_id; 262 u8 main_func_queue; 263 u8 mf_si_bcast_accept_all; 264 u8 mf_si_mcast_accept_all; 265 struct core_rx_action_on_error action_on_error; 266 u8 gsi_offload_flag; 267 u8 vport_id_valid; 268 u8 vport_id; 269 u8 zero_prod_flg; 270 u8 wipe_inner_vlan_pri_en; 271 u8 reserved[2]; 272 }; 273 274 /* Ramrod data for rx queue stop ramrod */ 275 struct core_rx_stop_ramrod_data { 276 u8 complete_cqe_flg; 277 u8 complete_event_flg; 278 u8 queue_id; 279 u8 reserved1; 280 __le16 reserved2[2]; 281 }; 282 283 /* Flags for Core TX BD */ 284 struct core_tx_bd_data { 285 __le16 as_bitfield; 286 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1 287 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0 288 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1 289 #define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT 1 290 #define CORE_TX_BD_DATA_START_BD_MASK 0x1 291 #define CORE_TX_BD_DATA_START_BD_SHIFT 2 292 #define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1 293 #define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3 294 #define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1 295 #define CORE_TX_BD_DATA_L4_CSUM_SHIFT 4 296 #define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1 297 #define CORE_TX_BD_DATA_IPV6_EXT_SHIFT 5 298 #define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1 299 #define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT 6 300 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1 301 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT 7 302 #define CORE_TX_BD_DATA_NBDS_MASK 0xF 303 #define CORE_TX_BD_DATA_NBDS_SHIFT 8 304 #define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1 305 #define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT 12 306 #define CORE_TX_BD_DATA_IP_LEN_MASK 0x1 307 #define CORE_TX_BD_DATA_IP_LEN_SHIFT 13 308 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_MASK 0x1 309 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_SHIFT 14 310 #define CORE_TX_BD_DATA_RESERVED0_MASK 0x1 311 #define CORE_TX_BD_DATA_RESERVED0_SHIFT 15 312 }; 313 314 /* Core TX BD for Light L2 */ 315 struct core_tx_bd { 316 struct regpair addr; 317 __le16 nbytes; 318 __le16 nw_vlan_or_lb_echo; 319 struct core_tx_bd_data bd_data; 320 __le16 bitfield1; 321 #define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF 322 #define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0 323 #define CORE_TX_BD_TX_DST_MASK 0x3 324 #define CORE_TX_BD_TX_DST_SHIFT 14 325 }; 326 327 /* Light L2 TX Destination */ 328 enum core_tx_dest { 329 CORE_TX_DEST_NW, 330 CORE_TX_DEST_LB, 331 CORE_TX_DEST_RESERVED, 332 CORE_TX_DEST_DROP, 333 MAX_CORE_TX_DEST 334 }; 335 336 /* Ramrod data for tx queue start ramrod */ 337 struct core_tx_start_ramrod_data { 338 struct regpair pbl_base_addr; 339 __le16 mtu; 340 __le16 sb_id; 341 u8 sb_index; 342 u8 stats_en; 343 u8 stats_id; 344 u8 conn_type; 345 __le16 pbl_size; 346 __le16 qm_pq_id; 347 u8 gsi_offload_flag; 348 u8 ctx_stats_en; 349 u8 vport_id_valid; 350 u8 vport_id; 351 u8 enforce_security_flag; 352 u8 reserved[7]; 353 }; 354 355 /* Ramrod data for tx queue stop ramrod */ 356 struct core_tx_stop_ramrod_data { 357 __le32 reserved0[2]; 358 }; 359 360 /* Ramrod data for tx queue update ramrod */ 361 struct core_tx_update_ramrod_data { 362 u8 update_qm_pq_id_flg; 363 u8 reserved0; 364 __le16 qm_pq_id; 365 __le32 reserved1; 366 }; 367 368 /* Enum flag for what type of dcb data to update */ 369 enum dcb_dscp_update_mode { 370 DONT_UPDATE_DCB_DSCP, 371 UPDATE_DCB, 372 UPDATE_DSCP, 373 UPDATE_DCB_DSCP, 374 MAX_DCB_DSCP_UPDATE_MODE 375 }; 376 377 /* The core storm context for the Ystorm */ 378 struct ystorm_core_conn_st_ctx { 379 __le32 reserved[4]; 380 }; 381 382 /* The core storm context for the Pstorm */ 383 struct pstorm_core_conn_st_ctx { 384 __le32 reserved[20]; 385 }; 386 387 /* Core Slowpath Connection storm context of Xstorm */ 388 struct xstorm_core_conn_st_ctx { 389 __le32 spq_base_lo; 390 __le32 spq_base_hi; 391 struct regpair consolid_base_addr; 392 __le16 spq_cons; 393 __le16 consolid_cons; 394 __le32 reserved0[55]; 395 }; 396 397 struct xstorm_core_conn_ag_ctx { 398 u8 reserved0; 399 u8 state; 400 u8 flags0; 401 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 402 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 403 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1 404 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1 405 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1 406 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2 407 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 408 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 409 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1 410 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4 411 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1 412 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5 413 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1 414 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6 415 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1 416 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7 417 u8 flags1; 418 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1 419 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0 420 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1 421 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1 422 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1 423 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2 424 #define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1 425 #define XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3 426 #define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1 427 #define XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4 428 #define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1 429 #define XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5 430 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 431 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 432 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 433 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 434 u8 flags2; 435 #define XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 436 #define XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0 437 #define XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 438 #define XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2 439 #define XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 440 #define XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4 441 #define XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 442 #define XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6 443 u8 flags3; 444 #define XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 445 #define XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0 446 #define XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 447 #define XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2 448 #define XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 449 #define XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4 450 #define XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 451 #define XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6 452 u8 flags4; 453 #define XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 454 #define XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0 455 #define XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 456 #define XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2 457 #define XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 458 #define XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4 459 #define XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3 460 #define XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6 461 u8 flags5; 462 #define XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3 463 #define XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0 464 #define XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3 465 #define XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2 466 #define XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3 467 #define XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4 468 #define XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3 469 #define XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6 470 u8 flags6; 471 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3 472 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0 473 #define XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3 474 #define XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2 475 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3 476 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4 477 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 478 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 479 u8 flags7; 480 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 481 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 482 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3 483 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2 484 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 485 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 486 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 487 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6 488 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 489 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7 490 u8 flags8; 491 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 492 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0 493 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 494 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1 495 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 496 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2 497 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 498 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3 499 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 500 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4 501 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 502 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5 503 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 504 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6 505 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 506 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7 507 u8 flags9; 508 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 509 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0 510 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1 511 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1 512 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1 513 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2 514 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1 515 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3 516 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1 517 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4 518 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1 519 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5 520 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1 521 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6 522 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1 523 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7 524 u8 flags10; 525 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 526 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 527 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 528 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 529 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 530 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 531 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1 532 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3 533 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 534 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 535 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1 536 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5 537 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1 538 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6 539 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1 540 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7 541 u8 flags11; 542 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1 543 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0 544 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1 545 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1 546 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 547 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 548 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 549 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3 550 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 551 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4 552 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 553 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5 554 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 555 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 556 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1 557 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7 558 u8 flags12; 559 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1 560 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0 561 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1 562 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1 563 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 564 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 565 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 566 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 567 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1 568 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4 569 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1 570 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5 571 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1 572 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6 573 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1 574 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7 575 u8 flags13; 576 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1 577 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0 578 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1 579 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1 580 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 581 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 582 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 583 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 584 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 585 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 586 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 587 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 588 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 589 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 590 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 591 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 592 u8 flags14; 593 #define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1 594 #define XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0 595 #define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1 596 #define XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1 597 #define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1 598 #define XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2 599 #define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1 600 #define XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3 601 #define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1 602 #define XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4 603 #define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1 604 #define XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5 605 #define XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3 606 #define XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6 607 u8 byte2; 608 __le16 physical_q0; 609 __le16 consolid_prod; 610 __le16 reserved16; 611 __le16 tx_bd_cons; 612 __le16 tx_bd_or_spq_prod; 613 __le16 updated_qm_pq_id; 614 __le16 conn_dpi; 615 u8 byte3; 616 u8 byte4; 617 u8 byte5; 618 u8 byte6; 619 __le32 reg0; 620 __le32 reg1; 621 __le32 reg2; 622 __le32 reg3; 623 __le32 reg4; 624 __le32 reg5; 625 __le32 reg6; 626 __le16 word7; 627 __le16 word8; 628 __le16 word9; 629 __le16 word10; 630 __le32 reg7; 631 __le32 reg8; 632 __le32 reg9; 633 u8 byte7; 634 u8 byte8; 635 u8 byte9; 636 u8 byte10; 637 u8 byte11; 638 u8 byte12; 639 u8 byte13; 640 u8 byte14; 641 u8 byte15; 642 u8 e5_reserved; 643 __le16 word11; 644 __le32 reg10; 645 __le32 reg11; 646 __le32 reg12; 647 __le32 reg13; 648 __le32 reg14; 649 __le32 reg15; 650 __le32 reg16; 651 __le32 reg17; 652 __le32 reg18; 653 __le32 reg19; 654 __le16 word12; 655 __le16 word13; 656 __le16 word14; 657 __le16 word15; 658 }; 659 660 struct tstorm_core_conn_ag_ctx { 661 u8 byte0; 662 u8 byte1; 663 u8 flags0; 664 #define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 665 #define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 666 #define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 667 #define TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 668 #define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1 669 #define TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2 670 #define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1 671 #define TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3 672 #define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1 673 #define TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4 674 #define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1 675 #define TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5 676 #define TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 677 #define TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6 678 u8 flags1; 679 #define TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 680 #define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0 681 #define TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 682 #define TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2 683 #define TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 684 #define TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4 685 #define TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 686 #define TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6 687 u8 flags2; 688 #define TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 689 #define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0 690 #define TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 691 #define TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2 692 #define TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 693 #define TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4 694 #define TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 695 #define TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6 696 u8 flags3; 697 #define TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 698 #define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0 699 #define TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 700 #define TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2 701 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 702 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4 703 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 704 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5 705 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 706 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6 707 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 708 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7 709 u8 flags4; 710 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 711 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0 712 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 713 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1 714 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 715 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2 716 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 717 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3 718 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 719 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4 720 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 721 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5 722 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 723 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6 724 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 725 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7 726 u8 flags5; 727 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 728 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0 729 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 730 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1 731 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 732 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2 733 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 734 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3 735 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 736 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4 737 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 738 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5 739 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 740 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6 741 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 742 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7 743 __le32 reg0; 744 __le32 reg1; 745 __le32 reg2; 746 __le32 reg3; 747 __le32 reg4; 748 __le32 reg5; 749 __le32 reg6; 750 __le32 reg7; 751 __le32 reg8; 752 u8 byte2; 753 u8 byte3; 754 __le16 word0; 755 u8 byte4; 756 u8 byte5; 757 __le16 word1; 758 __le16 word2; 759 __le16 word3; 760 __le32 ll2_rx_prod; 761 __le32 reg10; 762 }; 763 764 struct ustorm_core_conn_ag_ctx { 765 u8 reserved; 766 u8 byte1; 767 u8 flags0; 768 #define USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 769 #define USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 770 #define USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 771 #define USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 772 #define USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 773 #define USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 774 #define USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 775 #define USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 776 #define USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 777 #define USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 778 u8 flags1; 779 #define USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 780 #define USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0 781 #define USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 782 #define USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2 783 #define USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 784 #define USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4 785 #define USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 786 #define USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6 787 u8 flags2; 788 #define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 789 #define USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 790 #define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 791 #define USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 792 #define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 793 #define USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 794 #define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 795 #define USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3 796 #define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 797 #define USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4 798 #define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 799 #define USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5 800 #define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 801 #define USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6 802 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 803 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7 804 u8 flags3; 805 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 806 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0 807 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 808 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1 809 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 810 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2 811 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 812 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3 813 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 814 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4 815 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 816 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5 817 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 818 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6 819 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 820 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7 821 u8 byte2; 822 u8 byte3; 823 __le16 word0; 824 __le16 word1; 825 __le32 rx_producers; 826 __le32 reg1; 827 __le32 reg2; 828 __le32 reg3; 829 __le16 word2; 830 __le16 word3; 831 }; 832 833 /* The core storm context for the Mstorm */ 834 struct mstorm_core_conn_st_ctx { 835 __le32 reserved[40]; 836 }; 837 838 /* The core storm context for the Ustorm */ 839 struct ustorm_core_conn_st_ctx { 840 __le32 reserved[20]; 841 }; 842 843 /* The core storm context for the Tstorm */ 844 struct tstorm_core_conn_st_ctx { 845 __le32 reserved[4]; 846 }; 847 848 /* core connection context */ 849 struct core_conn_context { 850 struct ystorm_core_conn_st_ctx ystorm_st_context; 851 struct regpair ystorm_st_padding[2]; 852 struct pstorm_core_conn_st_ctx pstorm_st_context; 853 struct regpair pstorm_st_padding[2]; 854 struct xstorm_core_conn_st_ctx xstorm_st_context; 855 struct xstorm_core_conn_ag_ctx xstorm_ag_context; 856 struct tstorm_core_conn_ag_ctx tstorm_ag_context; 857 struct ustorm_core_conn_ag_ctx ustorm_ag_context; 858 struct mstorm_core_conn_st_ctx mstorm_st_context; 859 struct ustorm_core_conn_st_ctx ustorm_st_context; 860 struct regpair ustorm_st_padding[2]; 861 struct tstorm_core_conn_st_ctx tstorm_st_context; 862 struct regpair tstorm_st_padding[2]; 863 }; 864 865 struct eth_mstorm_per_pf_stat { 866 struct regpair gre_discard_pkts; 867 struct regpair vxlan_discard_pkts; 868 struct regpair geneve_discard_pkts; 869 struct regpair lb_discard_pkts; 870 }; 871 872 struct eth_mstorm_per_queue_stat { 873 struct regpair ttl0_discard; 874 struct regpair packet_too_big_discard; 875 struct regpair no_buff_discard; 876 struct regpair not_active_discard; 877 struct regpair tpa_coalesced_pkts; 878 struct regpair tpa_coalesced_events; 879 struct regpair tpa_aborts_num; 880 struct regpair tpa_coalesced_bytes; 881 }; 882 883 /* Ethernet TX Per PF */ 884 struct eth_pstorm_per_pf_stat { 885 struct regpair sent_lb_ucast_bytes; 886 struct regpair sent_lb_mcast_bytes; 887 struct regpair sent_lb_bcast_bytes; 888 struct regpair sent_lb_ucast_pkts; 889 struct regpair sent_lb_mcast_pkts; 890 struct regpair sent_lb_bcast_pkts; 891 struct regpair sent_gre_bytes; 892 struct regpair sent_vxlan_bytes; 893 struct regpair sent_geneve_bytes; 894 struct regpair sent_mpls_bytes; 895 struct regpair sent_gre_mpls_bytes; 896 struct regpair sent_udp_mpls_bytes; 897 struct regpair sent_gre_pkts; 898 struct regpair sent_vxlan_pkts; 899 struct regpair sent_geneve_pkts; 900 struct regpair sent_mpls_pkts; 901 struct regpair sent_gre_mpls_pkts; 902 struct regpair sent_udp_mpls_pkts; 903 struct regpair gre_drop_pkts; 904 struct regpair vxlan_drop_pkts; 905 struct regpair geneve_drop_pkts; 906 struct regpair mpls_drop_pkts; 907 struct regpair gre_mpls_drop_pkts; 908 struct regpair udp_mpls_drop_pkts; 909 }; 910 911 /* Ethernet TX Per Queue Stats */ 912 struct eth_pstorm_per_queue_stat { 913 struct regpair sent_ucast_bytes; 914 struct regpair sent_mcast_bytes; 915 struct regpair sent_bcast_bytes; 916 struct regpair sent_ucast_pkts; 917 struct regpair sent_mcast_pkts; 918 struct regpair sent_bcast_pkts; 919 struct regpair error_drop_pkts; 920 }; 921 922 /* ETH Rx producers data */ 923 struct eth_rx_rate_limit { 924 __le16 mult; 925 __le16 cnst; 926 u8 add_sub_cnst; 927 u8 reserved0; 928 __le16 reserved1; 929 }; 930 931 /* Update RSS indirection table entry command */ 932 struct eth_tstorm_rss_update_data { 933 u8 valid; 934 u8 vport_id; 935 u8 ind_table_index; 936 u8 reserved; 937 __le16 ind_table_value; 938 __le16 reserved1; 939 }; 940 941 struct eth_ustorm_per_pf_stat { 942 struct regpair rcv_lb_ucast_bytes; 943 struct regpair rcv_lb_mcast_bytes; 944 struct regpair rcv_lb_bcast_bytes; 945 struct regpair rcv_lb_ucast_pkts; 946 struct regpair rcv_lb_mcast_pkts; 947 struct regpair rcv_lb_bcast_pkts; 948 struct regpair rcv_gre_bytes; 949 struct regpair rcv_vxlan_bytes; 950 struct regpair rcv_geneve_bytes; 951 struct regpair rcv_gre_pkts; 952 struct regpair rcv_vxlan_pkts; 953 struct regpair rcv_geneve_pkts; 954 }; 955 956 struct eth_ustorm_per_queue_stat { 957 struct regpair rcv_ucast_bytes; 958 struct regpair rcv_mcast_bytes; 959 struct regpair rcv_bcast_bytes; 960 struct regpair rcv_ucast_pkts; 961 struct regpair rcv_mcast_pkts; 962 struct regpair rcv_bcast_pkts; 963 }; 964 965 /* Event Ring VF-PF Channel data */ 966 struct vf_pf_channel_eqe_data { 967 struct regpair msg_addr; 968 }; 969 970 /* Event Ring malicious VF data */ 971 struct malicious_vf_eqe_data { 972 u8 vf_id; 973 u8 err_id; 974 __le16 reserved[3]; 975 }; 976 977 /* Event Ring initial cleanup data */ 978 struct initial_cleanup_eqe_data { 979 u8 vf_id; 980 u8 reserved[7]; 981 }; 982 983 /* Event Data Union */ 984 union event_ring_data { 985 u8 bytes[8]; 986 struct vf_pf_channel_eqe_data vf_pf_channel; 987 struct iscsi_eqe_data iscsi_info; 988 struct iscsi_connect_done_results iscsi_conn_done_info; 989 union rdma_eqe_data rdma_data; 990 struct malicious_vf_eqe_data malicious_vf; 991 struct initial_cleanup_eqe_data vf_init_cleanup; 992 }; 993 994 /* Event Ring Entry */ 995 struct event_ring_entry { 996 u8 protocol_id; 997 u8 opcode; 998 u8 reserved0; 999 u8 vf_id; 1000 __le16 echo; 1001 u8 fw_return_code; 1002 u8 flags; 1003 #define EVENT_RING_ENTRY_ASYNC_MASK 0x1 1004 #define EVENT_RING_ENTRY_ASYNC_SHIFT 0 1005 #define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F 1006 #define EVENT_RING_ENTRY_RESERVED1_SHIFT 1 1007 union event_ring_data data; 1008 }; 1009 1010 /* Event Ring Next Page Address */ 1011 struct event_ring_next_addr { 1012 struct regpair addr; 1013 __le32 reserved[2]; 1014 }; 1015 1016 /* Event Ring Element */ 1017 union event_ring_element { 1018 struct event_ring_entry entry; 1019 struct event_ring_next_addr next_addr; 1020 }; 1021 1022 /* Ports mode */ 1023 enum fw_flow_ctrl_mode { 1024 flow_ctrl_pause, 1025 flow_ctrl_pfc, 1026 MAX_FW_FLOW_CTRL_MODE 1027 }; 1028 1029 /* GFT profile type */ 1030 enum gft_profile_type { 1031 GFT_PROFILE_TYPE_4_TUPLE, 1032 GFT_PROFILE_TYPE_L4_DST_PORT, 1033 GFT_PROFILE_TYPE_IP_DST_ADDR, 1034 GFT_PROFILE_TYPE_IP_SRC_ADDR, 1035 GFT_PROFILE_TYPE_TUNNEL_TYPE, 1036 MAX_GFT_PROFILE_TYPE 1037 }; 1038 1039 /* Major and Minor hsi Versions */ 1040 struct hsi_fp_ver_struct { 1041 u8 minor_ver_arr[2]; 1042 u8 major_ver_arr[2]; 1043 }; 1044 1045 enum iwarp_ll2_tx_queues { 1046 IWARP_LL2_IN_ORDER_TX_QUEUE = 1, 1047 IWARP_LL2_ALIGNED_TX_QUEUE, 1048 IWARP_LL2_ALIGNED_RIGHT_TRIMMED_TX_QUEUE, 1049 IWARP_LL2_ERROR, 1050 MAX_IWARP_LL2_TX_QUEUES 1051 }; 1052 1053 /* Malicious VF error ID */ 1054 enum malicious_vf_error_id { 1055 MALICIOUS_VF_NO_ERROR, 1056 VF_PF_CHANNEL_NOT_READY, 1057 VF_ZONE_MSG_NOT_VALID, 1058 VF_ZONE_FUNC_NOT_ENABLED, 1059 ETH_PACKET_TOO_SMALL, 1060 ETH_ILLEGAL_VLAN_MODE, 1061 ETH_MTU_VIOLATION, 1062 ETH_ILLEGAL_INBAND_TAGS, 1063 ETH_VLAN_INSERT_AND_INBAND_VLAN, 1064 ETH_ILLEGAL_NBDS, 1065 ETH_FIRST_BD_WO_SOP, 1066 ETH_INSUFFICIENT_BDS, 1067 ETH_ILLEGAL_LSO_HDR_NBDS, 1068 ETH_ILLEGAL_LSO_MSS, 1069 ETH_ZERO_SIZE_BD, 1070 ETH_ILLEGAL_LSO_HDR_LEN, 1071 ETH_INSUFFICIENT_PAYLOAD, 1072 ETH_EDPM_OUT_OF_SYNC, 1073 ETH_TUNN_IPV6_EXT_NBD_ERR, 1074 ETH_CONTROL_PACKET_VIOLATION, 1075 ETH_ANTI_SPOOFING_ERR, 1076 ETH_PACKET_SIZE_TOO_LARGE, 1077 CORE_ILLEGAL_VLAN_MODE, 1078 CORE_ILLEGAL_NBDS, 1079 CORE_FIRST_BD_WO_SOP, 1080 CORE_INSUFFICIENT_BDS, 1081 CORE_PACKET_TOO_SMALL, 1082 CORE_ILLEGAL_INBAND_TAGS, 1083 CORE_VLAN_INSERT_AND_INBAND_VLAN, 1084 CORE_MTU_VIOLATION, 1085 CORE_CONTROL_PACKET_VIOLATION, 1086 CORE_ANTI_SPOOFING_ERR, 1087 CORE_PACKET_SIZE_TOO_LARGE, 1088 CORE_ILLEGAL_BD_FLAGS, 1089 CORE_GSI_PACKET_VIOLATION, 1090 MAX_MALICIOUS_VF_ERROR_ID, 1091 }; 1092 1093 /* Mstorm non-triggering VF zone */ 1094 struct mstorm_non_trigger_vf_zone { 1095 struct eth_mstorm_per_queue_stat eth_queue_stat; 1096 struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_RXQ_VF_QUAD]; 1097 }; 1098 1099 /* Mstorm VF zone */ 1100 struct mstorm_vf_zone { 1101 struct mstorm_non_trigger_vf_zone non_trigger; 1102 }; 1103 1104 /* vlan header including TPID and TCI fields */ 1105 struct vlan_header { 1106 __le16 tpid; 1107 __le16 tci; 1108 }; 1109 1110 /* outer tag configurations */ 1111 struct outer_tag_config_struct { 1112 u8 enable_stag_pri_change; 1113 u8 pri_map_valid; 1114 u8 reserved[2]; 1115 struct vlan_header outer_tag; 1116 u8 inner_to_outer_pri_map[8]; 1117 }; 1118 1119 /* personality per PF */ 1120 enum personality_type { 1121 BAD_PERSONALITY_TYP, 1122 PERSONALITY_TCP_ULP, 1123 PERSONALITY_FCOE, 1124 PERSONALITY_RDMA_AND_ETH, 1125 PERSONALITY_RDMA, 1126 PERSONALITY_CORE, 1127 PERSONALITY_ETH, 1128 PERSONALITY_RESERVED, 1129 MAX_PERSONALITY_TYPE 1130 }; 1131 1132 /* tunnel configuration */ 1133 struct pf_start_tunnel_config { 1134 u8 set_vxlan_udp_port_flg; 1135 u8 set_geneve_udp_port_flg; 1136 u8 set_no_inner_l2_vxlan_udp_port_flg; 1137 u8 tunnel_clss_vxlan; 1138 u8 tunnel_clss_l2geneve; 1139 u8 tunnel_clss_ipgeneve; 1140 u8 tunnel_clss_l2gre; 1141 u8 tunnel_clss_ipgre; 1142 __le16 vxlan_udp_port; 1143 __le16 geneve_udp_port; 1144 __le16 no_inner_l2_vxlan_udp_port; 1145 __le16 reserved[3]; 1146 }; 1147 1148 /* Ramrod data for PF start ramrod */ 1149 struct pf_start_ramrod_data { 1150 struct regpair event_ring_pbl_addr; 1151 struct regpair consolid_q_pbl_addr; 1152 struct pf_start_tunnel_config tunnel_config; 1153 __le16 event_ring_sb_id; 1154 u8 base_vf_id; 1155 u8 num_vfs; 1156 u8 event_ring_num_pages; 1157 u8 event_ring_sb_index; 1158 u8 path_id; 1159 u8 warning_as_error; 1160 u8 dont_log_ramrods; 1161 u8 personality; 1162 __le16 log_type_mask; 1163 u8 mf_mode; 1164 u8 integ_phase; 1165 u8 allow_npar_tx_switching; 1166 u8 reserved0; 1167 struct hsi_fp_ver_struct hsi_fp_ver; 1168 struct outer_tag_config_struct outer_tag_config; 1169 }; 1170 1171 /* Data for port update ramrod */ 1172 struct protocol_dcb_data { 1173 u8 dcb_enable_flag; 1174 u8 dscp_enable_flag; 1175 u8 dcb_priority; 1176 u8 dcb_tc; 1177 u8 dscp_val; 1178 u8 dcb_dont_add_vlan0; 1179 }; 1180 1181 /* Update tunnel configuration */ 1182 struct pf_update_tunnel_config { 1183 u8 update_rx_pf_clss; 1184 u8 update_rx_def_ucast_clss; 1185 u8 update_rx_def_non_ucast_clss; 1186 u8 set_vxlan_udp_port_flg; 1187 u8 set_geneve_udp_port_flg; 1188 u8 set_no_inner_l2_vxlan_udp_port_flg; 1189 u8 tunnel_clss_vxlan; 1190 u8 tunnel_clss_l2geneve; 1191 u8 tunnel_clss_ipgeneve; 1192 u8 tunnel_clss_l2gre; 1193 u8 tunnel_clss_ipgre; 1194 u8 reserved; 1195 __le16 vxlan_udp_port; 1196 __le16 geneve_udp_port; 1197 __le16 no_inner_l2_vxlan_udp_port; 1198 __le16 reserved1[3]; 1199 }; 1200 1201 /* Data for port update ramrod */ 1202 struct pf_update_ramrod_data { 1203 u8 update_eth_dcb_data_mode; 1204 u8 update_fcoe_dcb_data_mode; 1205 u8 update_iscsi_dcb_data_mode; 1206 u8 update_roce_dcb_data_mode; 1207 u8 update_rroce_dcb_data_mode; 1208 u8 update_iwarp_dcb_data_mode; 1209 u8 update_mf_vlan_flag; 1210 u8 update_enable_stag_pri_change; 1211 struct protocol_dcb_data eth_dcb_data; 1212 struct protocol_dcb_data fcoe_dcb_data; 1213 struct protocol_dcb_data iscsi_dcb_data; 1214 struct protocol_dcb_data roce_dcb_data; 1215 struct protocol_dcb_data rroce_dcb_data; 1216 struct protocol_dcb_data iwarp_dcb_data; 1217 __le16 mf_vlan; 1218 u8 enable_stag_pri_change; 1219 u8 reserved; 1220 struct pf_update_tunnel_config tunnel_config; 1221 }; 1222 1223 /* Ports mode */ 1224 enum ports_mode { 1225 ENGX2_PORTX1, 1226 ENGX2_PORTX2, 1227 ENGX1_PORTX1, 1228 ENGX1_PORTX2, 1229 ENGX1_PORTX4, 1230 MAX_PORTS_MODE 1231 }; 1232 1233 /* use to index in hsi_fp_[major|minor]_ver_arr per protocol */ 1234 enum protocol_version_array_key { 1235 ETH_VER_KEY = 0, 1236 ROCE_VER_KEY, 1237 MAX_PROTOCOL_VERSION_ARRAY_KEY 1238 }; 1239 1240 /* RDMA TX Stats */ 1241 struct rdma_sent_stats { 1242 struct regpair sent_bytes; 1243 struct regpair sent_pkts; 1244 }; 1245 1246 /* Pstorm non-triggering VF zone */ 1247 struct pstorm_non_trigger_vf_zone { 1248 struct eth_pstorm_per_queue_stat eth_queue_stat; 1249 struct rdma_sent_stats rdma_stats; 1250 }; 1251 1252 /* Pstorm VF zone */ 1253 struct pstorm_vf_zone { 1254 struct pstorm_non_trigger_vf_zone non_trigger; 1255 struct regpair reserved[7]; 1256 }; 1257 1258 /* Ramrod Header of SPQE */ 1259 struct ramrod_header { 1260 __le32 cid; 1261 u8 cmd_id; 1262 u8 protocol_id; 1263 __le16 echo; 1264 }; 1265 1266 /* RDMA RX Stats */ 1267 struct rdma_rcv_stats { 1268 struct regpair rcv_bytes; 1269 struct regpair rcv_pkts; 1270 }; 1271 1272 /* Data for update QCN/DCQCN RL ramrod */ 1273 struct rl_update_ramrod_data { 1274 u8 qcn_update_param_flg; 1275 u8 dcqcn_update_param_flg; 1276 u8 rl_init_flg; 1277 u8 rl_start_flg; 1278 u8 rl_stop_flg; 1279 u8 rl_id_first; 1280 u8 rl_id_last; 1281 u8 rl_dc_qcn_flg; 1282 u8 dcqcn_reset_alpha_on_idle; 1283 u8 rl_bc_stage_th; 1284 u8 rl_timer_stage_th; 1285 u8 reserved1; 1286 __le32 rl_bc_rate; 1287 __le16 rl_max_rate; 1288 __le16 rl_r_ai; 1289 __le16 rl_r_hai; 1290 __le16 dcqcn_g; 1291 __le32 dcqcn_k_us; 1292 __le32 dcqcn_timeuot_us; 1293 __le32 qcn_timeuot_us; 1294 __le32 reserved2; 1295 }; 1296 1297 /* Slowpath Element (SPQE) */ 1298 struct slow_path_element { 1299 struct ramrod_header hdr; 1300 struct regpair data_ptr; 1301 }; 1302 1303 /* Tstorm non-triggering VF zone */ 1304 struct tstorm_non_trigger_vf_zone { 1305 struct rdma_rcv_stats rdma_stats; 1306 }; 1307 1308 struct tstorm_per_port_stat { 1309 struct regpair trunc_error_discard; 1310 struct regpair mac_error_discard; 1311 struct regpair mftag_filter_discard; 1312 struct regpair eth_mac_filter_discard; 1313 struct regpair ll2_mac_filter_discard; 1314 struct regpair ll2_conn_disabled_discard; 1315 struct regpair iscsi_irregular_pkt; 1316 struct regpair fcoe_irregular_pkt; 1317 struct regpair roce_irregular_pkt; 1318 struct regpair iwarp_irregular_pkt; 1319 struct regpair eth_irregular_pkt; 1320 struct regpair toe_irregular_pkt; 1321 struct regpair preroce_irregular_pkt; 1322 struct regpair eth_gre_tunn_filter_discard; 1323 struct regpair eth_vxlan_tunn_filter_discard; 1324 struct regpair eth_geneve_tunn_filter_discard; 1325 struct regpair eth_gft_drop_pkt; 1326 }; 1327 1328 /* Tstorm VF zone */ 1329 struct tstorm_vf_zone { 1330 struct tstorm_non_trigger_vf_zone non_trigger; 1331 }; 1332 1333 /* Tunnel classification scheme */ 1334 enum tunnel_clss { 1335 TUNNEL_CLSS_MAC_VLAN = 0, 1336 TUNNEL_CLSS_MAC_VNI, 1337 TUNNEL_CLSS_INNER_MAC_VLAN, 1338 TUNNEL_CLSS_INNER_MAC_VNI, 1339 TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE, 1340 MAX_TUNNEL_CLSS 1341 }; 1342 1343 /* Ustorm non-triggering VF zone */ 1344 struct ustorm_non_trigger_vf_zone { 1345 struct eth_ustorm_per_queue_stat eth_queue_stat; 1346 struct regpair vf_pf_msg_addr; 1347 }; 1348 1349 /* Ustorm triggering VF zone */ 1350 struct ustorm_trigger_vf_zone { 1351 u8 vf_pf_msg_valid; 1352 u8 reserved[7]; 1353 }; 1354 1355 /* Ustorm VF zone */ 1356 struct ustorm_vf_zone { 1357 struct ustorm_non_trigger_vf_zone non_trigger; 1358 struct ustorm_trigger_vf_zone trigger; 1359 }; 1360 1361 /* VF-PF channel data */ 1362 struct vf_pf_channel_data { 1363 __le32 ready; 1364 u8 valid; 1365 u8 reserved0; 1366 __le16 reserved1; 1367 }; 1368 1369 /* Ramrod data for VF start ramrod */ 1370 struct vf_start_ramrod_data { 1371 u8 vf_id; 1372 u8 enable_flr_ack; 1373 __le16 opaque_fid; 1374 u8 personality; 1375 u8 reserved[7]; 1376 struct hsi_fp_ver_struct hsi_fp_ver; 1377 1378 }; 1379 1380 /* Ramrod data for VF start ramrod */ 1381 struct vf_stop_ramrod_data { 1382 u8 vf_id; 1383 u8 reserved0; 1384 __le16 reserved1; 1385 __le32 reserved2; 1386 }; 1387 1388 /* VF zone size mode */ 1389 enum vf_zone_size_mode { 1390 VF_ZONE_SIZE_MODE_DEFAULT, 1391 VF_ZONE_SIZE_MODE_DOUBLE, 1392 VF_ZONE_SIZE_MODE_QUAD, 1393 MAX_VF_ZONE_SIZE_MODE 1394 }; 1395 1396 /* Xstorm non-triggering VF zone */ 1397 struct xstorm_non_trigger_vf_zone { 1398 struct regpair non_edpm_ack_pkts; 1399 }; 1400 1401 /* Tstorm VF zone */ 1402 struct xstorm_vf_zone { 1403 struct xstorm_non_trigger_vf_zone non_trigger; 1404 }; 1405 1406 /* Attentions status block */ 1407 struct atten_status_block { 1408 __le32 atten_bits; 1409 __le32 atten_ack; 1410 __le16 reserved0; 1411 __le16 sb_index; 1412 __le32 reserved1; 1413 }; 1414 1415 /* DMAE command */ 1416 struct dmae_cmd { 1417 __le32 opcode; 1418 #define DMAE_CMD_SRC_MASK 0x1 1419 #define DMAE_CMD_SRC_SHIFT 0 1420 #define DMAE_CMD_DST_MASK 0x3 1421 #define DMAE_CMD_DST_SHIFT 1 1422 #define DMAE_CMD_C_DST_MASK 0x1 1423 #define DMAE_CMD_C_DST_SHIFT 3 1424 #define DMAE_CMD_CRC_RESET_MASK 0x1 1425 #define DMAE_CMD_CRC_RESET_SHIFT 4 1426 #define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1 1427 #define DMAE_CMD_SRC_ADDR_RESET_SHIFT 5 1428 #define DMAE_CMD_DST_ADDR_RESET_MASK 0x1 1429 #define DMAE_CMD_DST_ADDR_RESET_SHIFT 6 1430 #define DMAE_CMD_COMP_FUNC_MASK 0x1 1431 #define DMAE_CMD_COMP_FUNC_SHIFT 7 1432 #define DMAE_CMD_COMP_WORD_EN_MASK 0x1 1433 #define DMAE_CMD_COMP_WORD_EN_SHIFT 8 1434 #define DMAE_CMD_COMP_CRC_EN_MASK 0x1 1435 #define DMAE_CMD_COMP_CRC_EN_SHIFT 9 1436 #define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7 1437 #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10 1438 #define DMAE_CMD_RESERVED1_MASK 0x1 1439 #define DMAE_CMD_RESERVED1_SHIFT 13 1440 #define DMAE_CMD_ENDIANITY_MODE_MASK 0x3 1441 #define DMAE_CMD_ENDIANITY_MODE_SHIFT 14 1442 #define DMAE_CMD_ERR_HANDLING_MASK 0x3 1443 #define DMAE_CMD_ERR_HANDLING_SHIFT 16 1444 #define DMAE_CMD_PORT_ID_MASK 0x3 1445 #define DMAE_CMD_PORT_ID_SHIFT 18 1446 #define DMAE_CMD_SRC_PF_ID_MASK 0xF 1447 #define DMAE_CMD_SRC_PF_ID_SHIFT 20 1448 #define DMAE_CMD_DST_PF_ID_MASK 0xF 1449 #define DMAE_CMD_DST_PF_ID_SHIFT 24 1450 #define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1 1451 #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28 1452 #define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1 1453 #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29 1454 #define DMAE_CMD_RESERVED2_MASK 0x3 1455 #define DMAE_CMD_RESERVED2_SHIFT 30 1456 __le32 src_addr_lo; 1457 __le32 src_addr_hi; 1458 __le32 dst_addr_lo; 1459 __le32 dst_addr_hi; 1460 __le16 length_dw; 1461 __le16 opcode_b; 1462 #define DMAE_CMD_SRC_VF_ID_MASK 0xFF 1463 #define DMAE_CMD_SRC_VF_ID_SHIFT 0 1464 #define DMAE_CMD_DST_VF_ID_MASK 0xFF 1465 #define DMAE_CMD_DST_VF_ID_SHIFT 8 1466 __le32 comp_addr_lo; 1467 __le32 comp_addr_hi; 1468 __le32 comp_val; 1469 __le32 crc32; 1470 __le32 crc_32_c; 1471 __le16 crc16; 1472 __le16 crc16_c; 1473 __le16 crc10; 1474 __le16 error_bit_reserved; 1475 #define DMAE_CMD_ERROR_BIT_MASK 0x1 1476 #define DMAE_CMD_ERROR_BIT_SHIFT 0 1477 #define DMAE_CMD_RESERVED_MASK 0x7FFF 1478 #define DMAE_CMD_RESERVED_SHIFT 1 1479 __le16 xsum16; 1480 __le16 xsum8; 1481 }; 1482 1483 enum dmae_cmd_comp_crc_en_enum { 1484 dmae_cmd_comp_crc_disabled, 1485 dmae_cmd_comp_crc_enabled, 1486 MAX_DMAE_CMD_COMP_CRC_EN_ENUM 1487 }; 1488 1489 enum dmae_cmd_comp_func_enum { 1490 dmae_cmd_comp_func_to_src, 1491 dmae_cmd_comp_func_to_dst, 1492 MAX_DMAE_CMD_COMP_FUNC_ENUM 1493 }; 1494 1495 enum dmae_cmd_comp_word_en_enum { 1496 dmae_cmd_comp_word_disabled, 1497 dmae_cmd_comp_word_enabled, 1498 MAX_DMAE_CMD_COMP_WORD_EN_ENUM 1499 }; 1500 1501 enum dmae_cmd_c_dst_enum { 1502 dmae_cmd_c_dst_pcie, 1503 dmae_cmd_c_dst_grc, 1504 MAX_DMAE_CMD_C_DST_ENUM 1505 }; 1506 1507 enum dmae_cmd_dst_enum { 1508 dmae_cmd_dst_none_0, 1509 dmae_cmd_dst_pcie, 1510 dmae_cmd_dst_grc, 1511 dmae_cmd_dst_none_3, 1512 MAX_DMAE_CMD_DST_ENUM 1513 }; 1514 1515 enum dmae_cmd_error_handling_enum { 1516 dmae_cmd_error_handling_send_regular_comp, 1517 dmae_cmd_error_handling_send_comp_with_err, 1518 dmae_cmd_error_handling_dont_send_comp, 1519 MAX_DMAE_CMD_ERROR_HANDLING_ENUM 1520 }; 1521 1522 enum dmae_cmd_src_enum { 1523 dmae_cmd_src_pcie, 1524 dmae_cmd_src_grc, 1525 MAX_DMAE_CMD_SRC_ENUM 1526 }; 1527 1528 struct mstorm_core_conn_ag_ctx { 1529 u8 byte0; 1530 u8 byte1; 1531 u8 flags0; 1532 #define MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 1533 #define MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 1534 #define MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 1535 #define MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 1536 #define MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 1537 #define MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 1538 #define MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 1539 #define MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 1540 #define MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 1541 #define MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 1542 u8 flags1; 1543 #define MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 1544 #define MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 1545 #define MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 1546 #define MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 1547 #define MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 1548 #define MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 1549 #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 1550 #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3 1551 #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 1552 #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4 1553 #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 1554 #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5 1555 #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 1556 #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6 1557 #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 1558 #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7 1559 __le16 word0; 1560 __le16 word1; 1561 __le32 reg0; 1562 __le32 reg1; 1563 }; 1564 1565 struct ystorm_core_conn_ag_ctx { 1566 u8 byte0; 1567 u8 byte1; 1568 u8 flags0; 1569 #define YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 1570 #define YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 1571 #define YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 1572 #define YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 1573 #define YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 1574 #define YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 1575 #define YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 1576 #define YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 1577 #define YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 1578 #define YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 1579 u8 flags1; 1580 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 1581 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 1582 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 1583 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 1584 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 1585 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 1586 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 1587 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3 1588 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 1589 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4 1590 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 1591 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5 1592 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 1593 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6 1594 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 1595 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7 1596 u8 byte2; 1597 u8 byte3; 1598 __le16 word0; 1599 __le32 reg0; 1600 __le32 reg1; 1601 __le16 word1; 1602 __le16 word2; 1603 __le16 word3; 1604 __le16 word4; 1605 __le32 reg2; 1606 __le32 reg3; 1607 }; 1608 1609 /* DMAE parameters */ 1610 struct qed_dmae_params { 1611 u32 flags; 1612 /* If QED_DMAE_PARAMS_RW_REPL_SRC flag is set and the 1613 * source is a block of length DMAE_MAX_RW_SIZE and the 1614 * destination is larger, the source block will be duplicated as 1615 * many times as required to fill the destination block. This is 1616 * used mostly to write a zeroed buffer to destination address 1617 * using DMA 1618 */ 1619 #define QED_DMAE_PARAMS_RW_REPL_SRC_MASK 0x1 1620 #define QED_DMAE_PARAMS_RW_REPL_SRC_SHIFT 0 1621 #define QED_DMAE_PARAMS_SRC_VF_VALID_MASK 0x1 1622 #define QED_DMAE_PARAMS_SRC_VF_VALID_SHIFT 1 1623 #define QED_DMAE_PARAMS_DST_VF_VALID_MASK 0x1 1624 #define QED_DMAE_PARAMS_DST_VF_VALID_SHIFT 2 1625 #define QED_DMAE_PARAMS_COMPLETION_DST_MASK 0x1 1626 #define QED_DMAE_PARAMS_COMPLETION_DST_SHIFT 3 1627 #define QED_DMAE_PARAMS_PORT_VALID_MASK 0x1 1628 #define QED_DMAE_PARAMS_PORT_VALID_SHIFT 4 1629 #define QED_DMAE_PARAMS_SRC_PF_VALID_MASK 0x1 1630 #define QED_DMAE_PARAMS_SRC_PF_VALID_SHIFT 5 1631 #define QED_DMAE_PARAMS_DST_PF_VALID_MASK 0x1 1632 #define QED_DMAE_PARAMS_DST_PF_VALID_SHIFT 6 1633 #define QED_DMAE_PARAMS_RESERVED_MASK 0x1FFFFFF 1634 #define QED_DMAE_PARAMS_RESERVED_SHIFT 7 1635 u8 src_vfid; 1636 u8 dst_vfid; 1637 u8 port_id; 1638 u8 src_pfid; 1639 u8 dst_pfid; 1640 u8 reserved1; 1641 __le16 reserved2; 1642 }; 1643 1644 /* IGU cleanup command */ 1645 struct igu_cleanup { 1646 __le32 sb_id_and_flags; 1647 #define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF 1648 #define IGU_CLEANUP_RESERVED0_SHIFT 0 1649 #define IGU_CLEANUP_CLEANUP_SET_MASK 0x1 1650 #define IGU_CLEANUP_CLEANUP_SET_SHIFT 27 1651 #define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7 1652 #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28 1653 #define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1 1654 #define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31 1655 __le32 reserved1; 1656 }; 1657 1658 /* IGU firmware driver command */ 1659 union igu_command { 1660 struct igu_prod_cons_update prod_cons_update; 1661 struct igu_cleanup cleanup; 1662 }; 1663 1664 /* IGU firmware driver command */ 1665 struct igu_command_reg_ctrl { 1666 __le16 opaque_fid; 1667 __le16 igu_command_reg_ctrl_fields; 1668 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF 1669 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0 1670 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7 1671 #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT 12 1672 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1 1673 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15 1674 }; 1675 1676 /* IGU mapping line structure */ 1677 struct igu_mapping_line { 1678 __le32 igu_mapping_line_fields; 1679 #define IGU_MAPPING_LINE_VALID_MASK 0x1 1680 #define IGU_MAPPING_LINE_VALID_SHIFT 0 1681 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF 1682 #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT 1 1683 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF 1684 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9 1685 #define IGU_MAPPING_LINE_PF_VALID_MASK 0x1 1686 #define IGU_MAPPING_LINE_PF_VALID_SHIFT 17 1687 #define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F 1688 #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT 18 1689 #define IGU_MAPPING_LINE_RESERVED_MASK 0xFF 1690 #define IGU_MAPPING_LINE_RESERVED_SHIFT 24 1691 }; 1692 1693 /* IGU MSIX line structure */ 1694 struct igu_msix_vector { 1695 struct regpair address; 1696 __le32 data; 1697 __le32 msix_vector_fields; 1698 #define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1 1699 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0 1700 #define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF 1701 #define IGU_MSIX_VECTOR_RESERVED0_SHIFT 1 1702 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF 1703 #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16 1704 #define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF 1705 #define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24 1706 }; 1707 /* per encapsulation type enabling flags */ 1708 struct prs_reg_encapsulation_type_en { 1709 u8 flags; 1710 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1 1711 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0 1712 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1 1713 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT 1 1714 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1 1715 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT 2 1716 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1 1717 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT 3 1718 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1 1719 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4 1720 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1 1721 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT 5 1722 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3 1723 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT 6 1724 }; 1725 1726 enum pxp_tph_st_hint { 1727 TPH_ST_HINT_BIDIR, 1728 TPH_ST_HINT_REQUESTER, 1729 TPH_ST_HINT_TARGET, 1730 TPH_ST_HINT_TARGET_PRIO, 1731 MAX_PXP_TPH_ST_HINT 1732 }; 1733 1734 /* QM hardware structure of enable bypass credit mask */ 1735 struct qm_rf_bypass_mask { 1736 u8 flags; 1737 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1 1738 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0 1739 #define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1 1740 #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1 1741 #define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1 1742 #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT 2 1743 #define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1 1744 #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT 3 1745 #define QM_RF_BYPASS_MASK_PFRL_MASK 0x1 1746 #define QM_RF_BYPASS_MASK_PFRL_SHIFT 4 1747 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1 1748 #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT 5 1749 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1 1750 #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT 6 1751 #define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1 1752 #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7 1753 }; 1754 1755 /* QM hardware structure of opportunistic credit mask */ 1756 struct qm_rf_opportunistic_mask { 1757 __le16 flags; 1758 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1 1759 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0 1760 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1 1761 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT 1 1762 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1 1763 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT 2 1764 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1 1765 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT 3 1766 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1 1767 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT 4 1768 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1 1769 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT 5 1770 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1 1771 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT 6 1772 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1 1773 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT 7 1774 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1 1775 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8 1776 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F 1777 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT 9 1778 }; 1779 1780 /* QM hardware structure of QM map memory */ 1781 struct qm_rf_pq_map { 1782 __le32 reg; 1783 #define QM_RF_PQ_MAP_PQ_VALID_MASK 0x1 1784 #define QM_RF_PQ_MAP_PQ_VALID_SHIFT 0 1785 #define QM_RF_PQ_MAP_RL_ID_MASK 0xFF 1786 #define QM_RF_PQ_MAP_RL_ID_SHIFT 1 1787 #define QM_RF_PQ_MAP_VP_PQ_ID_MASK 0x1FF 1788 #define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT 9 1789 #define QM_RF_PQ_MAP_VOQ_MASK 0x1F 1790 #define QM_RF_PQ_MAP_VOQ_SHIFT 18 1791 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK 0x3 1792 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT 23 1793 #define QM_RF_PQ_MAP_RL_VALID_MASK 0x1 1794 #define QM_RF_PQ_MAP_RL_VALID_SHIFT 25 1795 #define QM_RF_PQ_MAP_RESERVED_MASK 0x3F 1796 #define QM_RF_PQ_MAP_RESERVED_SHIFT 26 1797 }; 1798 1799 /* Completion params for aggregated interrupt completion */ 1800 struct sdm_agg_int_comp_params { 1801 __le16 params; 1802 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F 1803 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0 1804 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1 1805 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6 1806 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF 1807 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT 7 1808 }; 1809 1810 /* SDM operation gen command (generate aggregative interrupt) */ 1811 struct sdm_op_gen { 1812 __le32 command; 1813 #define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF 1814 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0 1815 #define SDM_OP_GEN_COMP_TYPE_MASK 0xF 1816 #define SDM_OP_GEN_COMP_TYPE_SHIFT 16 1817 #define SDM_OP_GEN_RESERVED_MASK 0xFFF 1818 #define SDM_OP_GEN_RESERVED_SHIFT 20 1819 }; 1820 1821 /* Physical memory descriptor */ 1822 struct phys_mem_desc { 1823 dma_addr_t phys_addr; 1824 void *virt_addr; 1825 u32 size; /* In bytes */ 1826 }; 1827 1828 /* Virtual memory descriptor */ 1829 struct virt_mem_desc { 1830 void *ptr; 1831 u32 size; /* In bytes */ 1832 }; 1833 1834 /********************************/ 1835 /* HSI Init Functions constants */ 1836 /********************************/ 1837 1838 /* Number of VLAN priorities */ 1839 #define NUM_OF_VLAN_PRIORITIES 8 1840 1841 /* BRB RAM init requirements */ 1842 struct init_brb_ram_req { 1843 u32 guranteed_per_tc; 1844 u32 headroom_per_tc; 1845 u32 min_pkt_size; 1846 u32 max_ports_per_engine; 1847 u8 num_active_tcs[MAX_NUM_PORTS]; 1848 }; 1849 1850 /* ETS per-TC init requirements */ 1851 struct init_ets_tc_req { 1852 u8 use_sp; 1853 u8 use_wfq; 1854 u16 weight; 1855 }; 1856 1857 /* ETS init requirements */ 1858 struct init_ets_req { 1859 u32 mtu; 1860 struct init_ets_tc_req tc_req[NUM_OF_TCS]; 1861 }; 1862 1863 /* NIG LB RL init requirements */ 1864 struct init_nig_lb_rl_req { 1865 u16 lb_mac_rate; 1866 u16 lb_rate; 1867 u32 mtu; 1868 u16 tc_rate[NUM_OF_PHYS_TCS]; 1869 }; 1870 1871 /* NIG TC mapping for each priority */ 1872 struct init_nig_pri_tc_map_entry { 1873 u8 tc_id; 1874 u8 valid; 1875 }; 1876 1877 /* NIG priority to TC map init requirements */ 1878 struct init_nig_pri_tc_map_req { 1879 struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES]; 1880 }; 1881 1882 /* QM per global RL init parameters */ 1883 struct init_qm_global_rl_params { 1884 u32 rate_limit; 1885 }; 1886 1887 /* QM per-port init parameters */ 1888 struct init_qm_port_params { 1889 u16 active_phys_tcs; 1890 u16 num_pbf_cmd_lines; 1891 u16 num_btb_blocks; 1892 u8 active; 1893 u8 reserved; 1894 }; 1895 1896 /* QM per-PQ init parameters */ 1897 struct init_qm_pq_params { 1898 u8 vport_id; 1899 u8 tc_id; 1900 u8 wrr_group; 1901 u8 rl_valid; 1902 u16 rl_id; 1903 u8 port_id; 1904 u8 reserved; 1905 }; 1906 1907 /* QM per-vport init parameters */ 1908 struct init_qm_vport_params { 1909 u16 wfq; 1910 u16 first_tx_pq_id[NUM_OF_TCS]; 1911 }; 1912 1913 /**************************************/ 1914 /* Init Tool HSI constants and macros */ 1915 /**************************************/ 1916 1917 /* Width of GRC address in bits (addresses are specified in dwords) */ 1918 #define GRC_ADDR_BITS 23 1919 #define MAX_GRC_ADDR (BIT(GRC_ADDR_BITS) - 1) 1920 1921 /* indicates an init that should be applied to any phase ID */ 1922 #define ANY_PHASE_ID 0xffff 1923 1924 /* Max size in dwords of a zipped array */ 1925 #define MAX_ZIPPED_SIZE 8192 1926 enum chip_ids { 1927 CHIP_BB, 1928 CHIP_K2, 1929 MAX_CHIP_IDS 1930 }; 1931 1932 struct fw_asserts_ram_section { 1933 __le16 section_ram_line_offset; 1934 __le16 section_ram_line_size; 1935 u8 list_dword_offset; 1936 u8 list_element_dword_size; 1937 u8 list_num_elements; 1938 u8 list_next_index_dword_offset; 1939 }; 1940 1941 struct fw_ver_num { 1942 u8 major; 1943 u8 minor; 1944 u8 rev; 1945 u8 eng; 1946 }; 1947 1948 struct fw_ver_info { 1949 __le16 tools_ver; 1950 u8 image_id; 1951 u8 reserved1; 1952 struct fw_ver_num num; 1953 __le32 timestamp; 1954 __le32 reserved2; 1955 }; 1956 1957 struct fw_info { 1958 struct fw_ver_info ver; 1959 struct fw_asserts_ram_section fw_asserts_section; 1960 }; 1961 1962 struct fw_info_location { 1963 __le32 grc_addr; 1964 __le32 size; 1965 }; 1966 1967 enum init_modes { 1968 MODE_RESERVED, 1969 MODE_BB, 1970 MODE_K2, 1971 MODE_ASIC, 1972 MODE_RESERVED2, 1973 MODE_RESERVED3, 1974 MODE_RESERVED4, 1975 MODE_RESERVED5, 1976 MODE_SF, 1977 MODE_MF_SD, 1978 MODE_MF_SI, 1979 MODE_PORTS_PER_ENG_1, 1980 MODE_PORTS_PER_ENG_2, 1981 MODE_PORTS_PER_ENG_4, 1982 MODE_100G, 1983 MODE_RESERVED6, 1984 MODE_RESERVED7, 1985 MAX_INIT_MODES 1986 }; 1987 1988 enum init_phases { 1989 PHASE_ENGINE, 1990 PHASE_PORT, 1991 PHASE_PF, 1992 PHASE_VF, 1993 PHASE_QM_PF, 1994 MAX_INIT_PHASES 1995 }; 1996 1997 enum init_split_types { 1998 SPLIT_TYPE_NONE, 1999 SPLIT_TYPE_PORT, 2000 SPLIT_TYPE_PF, 2001 SPLIT_TYPE_PORT_PF, 2002 SPLIT_TYPE_VF, 2003 MAX_INIT_SPLIT_TYPES 2004 }; 2005 2006 /* Binary buffer header */ 2007 struct bin_buffer_hdr { 2008 u32 offset; 2009 u32 length; 2010 }; 2011 2012 /* Binary init buffer types */ 2013 enum bin_init_buffer_type { 2014 BIN_BUF_INIT_FW_VER_INFO, 2015 BIN_BUF_INIT_CMD, 2016 BIN_BUF_INIT_VAL, 2017 BIN_BUF_INIT_MODE_TREE, 2018 BIN_BUF_INIT_IRO, 2019 BIN_BUF_INIT_OVERLAYS, 2020 MAX_BIN_INIT_BUFFER_TYPE 2021 }; 2022 2023 /* FW overlay buffer header */ 2024 struct fw_overlay_buf_hdr { 2025 u32 data; 2026 #define FW_OVERLAY_BUF_HDR_STORM_ID_MASK 0xFF 2027 #define FW_OVERLAY_BUF_HDR_STORM_ID_SHIFT 0 2028 #define FW_OVERLAY_BUF_HDR_BUF_SIZE_MASK 0xFFFFFF 2029 #define FW_OVERLAY_BUF_HDR_BUF_SIZE_SHIFT 8 2030 }; 2031 2032 /* init array header: raw */ 2033 struct init_array_raw_hdr { 2034 __le32 data; 2035 #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF 2036 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0 2037 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF 2038 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4 2039 }; 2040 2041 /* init array header: standard */ 2042 struct init_array_standard_hdr { 2043 __le32 data; 2044 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF 2045 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0 2046 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF 2047 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4 2048 }; 2049 2050 /* init array header: zipped */ 2051 struct init_array_zipped_hdr { 2052 __le32 data; 2053 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF 2054 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0 2055 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF 2056 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4 2057 }; 2058 2059 /* init array header: pattern */ 2060 struct init_array_pattern_hdr { 2061 __le32 data; 2062 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF 2063 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0 2064 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF 2065 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4 2066 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF 2067 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8 2068 }; 2069 2070 /* init array header union */ 2071 union init_array_hdr { 2072 struct init_array_raw_hdr raw; 2073 struct init_array_standard_hdr standard; 2074 struct init_array_zipped_hdr zipped; 2075 struct init_array_pattern_hdr pattern; 2076 }; 2077 2078 /* init array types */ 2079 enum init_array_types { 2080 INIT_ARR_STANDARD, 2081 INIT_ARR_ZIPPED, 2082 INIT_ARR_PATTERN, 2083 MAX_INIT_ARRAY_TYPES 2084 }; 2085 2086 /* init operation: callback */ 2087 struct init_callback_op { 2088 __le32 op_data; 2089 #define INIT_CALLBACK_OP_OP_MASK 0xF 2090 #define INIT_CALLBACK_OP_OP_SHIFT 0 2091 #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF 2092 #define INIT_CALLBACK_OP_RESERVED_SHIFT 4 2093 __le16 callback_id; 2094 __le16 block_id; 2095 }; 2096 2097 /* init operation: delay */ 2098 struct init_delay_op { 2099 __le32 op_data; 2100 #define INIT_DELAY_OP_OP_MASK 0xF 2101 #define INIT_DELAY_OP_OP_SHIFT 0 2102 #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF 2103 #define INIT_DELAY_OP_RESERVED_SHIFT 4 2104 __le32 delay; 2105 }; 2106 2107 /* init operation: if_mode */ 2108 struct init_if_mode_op { 2109 __le32 op_data; 2110 #define INIT_IF_MODE_OP_OP_MASK 0xF 2111 #define INIT_IF_MODE_OP_OP_SHIFT 0 2112 #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF 2113 #define INIT_IF_MODE_OP_RESERVED1_SHIFT 4 2114 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF 2115 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16 2116 __le16 reserved2; 2117 __le16 modes_buf_offset; 2118 }; 2119 2120 /* init operation: if_phase */ 2121 struct init_if_phase_op { 2122 __le32 op_data; 2123 #define INIT_IF_PHASE_OP_OP_MASK 0xF 2124 #define INIT_IF_PHASE_OP_OP_SHIFT 0 2125 #define INIT_IF_PHASE_OP_RESERVED1_MASK 0xFFF 2126 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT 4 2127 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF 2128 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16 2129 __le32 phase_data; 2130 #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF 2131 #define INIT_IF_PHASE_OP_PHASE_SHIFT 0 2132 #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF 2133 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8 2134 #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF 2135 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16 2136 }; 2137 2138 /* init mode operators */ 2139 enum init_mode_ops { 2140 INIT_MODE_OP_NOT, 2141 INIT_MODE_OP_OR, 2142 INIT_MODE_OP_AND, 2143 MAX_INIT_MODE_OPS 2144 }; 2145 2146 /* init operation: raw */ 2147 struct init_raw_op { 2148 __le32 op_data; 2149 #define INIT_RAW_OP_OP_MASK 0xF 2150 #define INIT_RAW_OP_OP_SHIFT 0 2151 #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF 2152 #define INIT_RAW_OP_PARAM1_SHIFT 4 2153 __le32 param2; 2154 }; 2155 2156 /* init array params */ 2157 struct init_op_array_params { 2158 __le16 size; 2159 __le16 offset; 2160 }; 2161 2162 /* Write init operation arguments */ 2163 union init_write_args { 2164 __le32 inline_val; 2165 __le32 zeros_count; 2166 __le32 array_offset; 2167 struct init_op_array_params runtime; 2168 }; 2169 2170 /* init operation: write */ 2171 struct init_write_op { 2172 __le32 data; 2173 #define INIT_WRITE_OP_OP_MASK 0xF 2174 #define INIT_WRITE_OP_OP_SHIFT 0 2175 #define INIT_WRITE_OP_SOURCE_MASK 0x7 2176 #define INIT_WRITE_OP_SOURCE_SHIFT 4 2177 #define INIT_WRITE_OP_RESERVED_MASK 0x1 2178 #define INIT_WRITE_OP_RESERVED_SHIFT 7 2179 #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1 2180 #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8 2181 #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF 2182 #define INIT_WRITE_OP_ADDRESS_SHIFT 9 2183 union init_write_args args; 2184 }; 2185 2186 /* init operation: read */ 2187 struct init_read_op { 2188 __le32 op_data; 2189 #define INIT_READ_OP_OP_MASK 0xF 2190 #define INIT_READ_OP_OP_SHIFT 0 2191 #define INIT_READ_OP_POLL_TYPE_MASK 0xF 2192 #define INIT_READ_OP_POLL_TYPE_SHIFT 4 2193 #define INIT_READ_OP_RESERVED_MASK 0x1 2194 #define INIT_READ_OP_RESERVED_SHIFT 8 2195 #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF 2196 #define INIT_READ_OP_ADDRESS_SHIFT 9 2197 __le32 expected_val; 2198 }; 2199 2200 /* Init operations union */ 2201 union init_op { 2202 struct init_raw_op raw; 2203 struct init_write_op write; 2204 struct init_read_op read; 2205 struct init_if_mode_op if_mode; 2206 struct init_if_phase_op if_phase; 2207 struct init_callback_op callback; 2208 struct init_delay_op delay; 2209 }; 2210 2211 /* Init command operation types */ 2212 enum init_op_types { 2213 INIT_OP_READ, 2214 INIT_OP_WRITE, 2215 INIT_OP_IF_MODE, 2216 INIT_OP_IF_PHASE, 2217 INIT_OP_DELAY, 2218 INIT_OP_CALLBACK, 2219 MAX_INIT_OP_TYPES 2220 }; 2221 2222 /* init polling types */ 2223 enum init_poll_types { 2224 INIT_POLL_NONE, 2225 INIT_POLL_EQ, 2226 INIT_POLL_OR, 2227 INIT_POLL_AND, 2228 MAX_INIT_POLL_TYPES 2229 }; 2230 2231 /* init source types */ 2232 enum init_source_types { 2233 INIT_SRC_INLINE, 2234 INIT_SRC_ZEROS, 2235 INIT_SRC_ARRAY, 2236 INIT_SRC_RUNTIME, 2237 MAX_INIT_SOURCE_TYPES 2238 }; 2239 2240 /* Internal RAM Offsets macro data */ 2241 struct iro { 2242 u32 base; 2243 u16 m1; 2244 u16 m2; 2245 u16 m3; 2246 u16 size; 2247 }; 2248 2249 /* Win 2 */ 2250 #define GTT_BAR0_MAP_REG_IGU_CMD 0x00f000UL 2251 2252 /* Win 3 */ 2253 #define GTT_BAR0_MAP_REG_TSDM_RAM 0x010000UL 2254 2255 /* Win 4 */ 2256 #define GTT_BAR0_MAP_REG_MSDM_RAM 0x011000UL 2257 2258 /* Win 5 */ 2259 #define GTT_BAR0_MAP_REG_MSDM_RAM_1024 0x012000UL 2260 2261 /* Win 6 */ 2262 #define GTT_BAR0_MAP_REG_MSDM_RAM_2048 0x013000UL 2263 2264 /* Win 7 */ 2265 #define GTT_BAR0_MAP_REG_USDM_RAM 0x014000UL 2266 2267 /* Win 8 */ 2268 #define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x015000UL 2269 2270 /* Win 9 */ 2271 #define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x016000UL 2272 2273 /* Win 10 */ 2274 #define GTT_BAR0_MAP_REG_XSDM_RAM 0x017000UL 2275 2276 /* Win 11 */ 2277 #define GTT_BAR0_MAP_REG_XSDM_RAM_1024 0x018000UL 2278 2279 /* Win 12 */ 2280 #define GTT_BAR0_MAP_REG_YSDM_RAM 0x019000UL 2281 2282 /* Win 13 */ 2283 #define GTT_BAR0_MAP_REG_PSDM_RAM 0x01a000UL 2284 2285 /** 2286 * qed_qm_pf_mem_size(): Prepare QM ILT sizes. 2287 * 2288 * @num_pf_cids: Number of connections used by this PF. 2289 * @num_vf_cids: Number of connections used by VFs of this PF. 2290 * @num_tids: Number of tasks used by this PF. 2291 * @num_pf_pqs: Number of PQs used by this PF. 2292 * @num_vf_pqs: Number of PQs used by VFs of this PF. 2293 * 2294 * Return: The required host memory size in 4KB units. 2295 * 2296 * Returns the required host memory size in 4KB units. 2297 * Must be called before all QM init HSI functions. 2298 */ 2299 u32 qed_qm_pf_mem_size(u32 num_pf_cids, 2300 u32 num_vf_cids, 2301 u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs); 2302 2303 struct qed_qm_common_rt_init_params { 2304 u8 max_ports_per_engine; 2305 u8 max_phys_tcs_per_port; 2306 bool pf_rl_en; 2307 bool pf_wfq_en; 2308 bool global_rl_en; 2309 bool vport_wfq_en; 2310 struct init_qm_port_params *port_params; 2311 }; 2312 2313 int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn, 2314 struct qed_qm_common_rt_init_params *p_params); 2315 2316 struct qed_qm_pf_rt_init_params { 2317 u8 port_id; 2318 u8 pf_id; 2319 u8 max_phys_tcs_per_port; 2320 bool is_pf_loading; 2321 u32 num_pf_cids; 2322 u32 num_vf_cids; 2323 u32 num_tids; 2324 u16 start_pq; 2325 u16 num_pf_pqs; 2326 u16 num_vf_pqs; 2327 u16 start_vport; 2328 u16 num_vports; 2329 u16 pf_wfq; 2330 u32 pf_rl; 2331 struct init_qm_pq_params *pq_params; 2332 struct init_qm_vport_params *vport_params; 2333 }; 2334 2335 int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn, 2336 struct qed_ptt *p_ptt, 2337 struct qed_qm_pf_rt_init_params *p_params); 2338 2339 /** 2340 * qed_init_pf_wfq(): Initializes the WFQ weight of the specified PF. 2341 * 2342 * @p_hwfn: HW device data. 2343 * @p_ptt: Ptt window used for writing the registers 2344 * @pf_id: PF ID 2345 * @pf_wfq: WFQ weight. Must be non-zero. 2346 * 2347 * Return: 0 on success, -1 on error. 2348 */ 2349 int qed_init_pf_wfq(struct qed_hwfn *p_hwfn, 2350 struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq); 2351 2352 /** 2353 * qed_init_pf_rl(): Initializes the rate limit of the specified PF 2354 * 2355 * @p_hwfn: HW device data. 2356 * @p_ptt: Ptt window used for writing the registers. 2357 * @pf_id: PF ID. 2358 * @pf_rl: rate limit in Mb/sec units 2359 * 2360 * Return: 0 on success, -1 on error. 2361 */ 2362 int qed_init_pf_rl(struct qed_hwfn *p_hwfn, 2363 struct qed_ptt *p_ptt, u8 pf_id, u32 pf_rl); 2364 2365 /** 2366 * qed_init_vport_wfq(): Initializes the WFQ weight of the specified VPORT 2367 * 2368 * @p_hwfn: HW device data. 2369 * @p_ptt: Ptt window used for writing the registers 2370 * @first_tx_pq_id: An array containing the first Tx PQ ID associated 2371 * with the VPORT for each TC. This array is filled by 2372 * qed_qm_pf_rt_init 2373 * @wfq: WFQ weight. Must be non-zero. 2374 * 2375 * Return: 0 on success, -1 on error. 2376 */ 2377 int qed_init_vport_wfq(struct qed_hwfn *p_hwfn, 2378 struct qed_ptt *p_ptt, 2379 u16 first_tx_pq_id[NUM_OF_TCS], u16 wfq); 2380 2381 /** 2382 * qed_init_global_rl(): Initializes the rate limit of the specified 2383 * rate limiter. 2384 * 2385 * @p_hwfn: HW device data. 2386 * @p_ptt: Ptt window used for writing the registers. 2387 * @rl_id: RL ID. 2388 * @rate_limit: Rate limit in Mb/sec units 2389 * 2390 * Return: 0 on success, -1 on error. 2391 */ 2392 int qed_init_global_rl(struct qed_hwfn *p_hwfn, 2393 struct qed_ptt *p_ptt, 2394 u16 rl_id, u32 rate_limit); 2395 2396 /** 2397 * qed_send_qm_stop_cmd(): Sends a stop command to the QM. 2398 * 2399 * @p_hwfn: HW device data. 2400 * @p_ptt: Ptt window used for writing the registers. 2401 * @is_release_cmd: true for release, false for stop. 2402 * @is_tx_pq: true for Tx PQs, false for Other PQs. 2403 * @start_pq: first PQ ID to stop 2404 * @num_pqs: Number of PQs to stop, starting from start_pq. 2405 * 2406 * Return: Bool, true if successful, false if timeout occurred while waiting 2407 * for QM command done. 2408 */ 2409 bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn, 2410 struct qed_ptt *p_ptt, 2411 bool is_release_cmd, 2412 bool is_tx_pq, u16 start_pq, u16 num_pqs); 2413 2414 /** 2415 * qed_set_vxlan_dest_port(): Initializes vxlan tunnel destination udp port. 2416 * 2417 * @p_hwfn: HW device data. 2418 * @p_ptt: Ptt window used for writing the registers. 2419 * @dest_port: vxlan destination udp port. 2420 * 2421 * Return: Void. 2422 */ 2423 void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn, 2424 struct qed_ptt *p_ptt, u16 dest_port); 2425 2426 /** 2427 * qed_set_vxlan_enable(): Enable or disable VXLAN tunnel in HW. 2428 * 2429 * @p_hwfn: HW device data. 2430 * @p_ptt: Ptt window used for writing the registers. 2431 * @vxlan_enable: vxlan enable flag. 2432 * 2433 * Return: Void. 2434 */ 2435 void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn, 2436 struct qed_ptt *p_ptt, bool vxlan_enable); 2437 2438 /** 2439 * qed_set_gre_enable(): Enable or disable GRE tunnel in HW. 2440 * 2441 * @p_hwfn: HW device data. 2442 * @p_ptt: Ptt window used for writing the registers. 2443 * @eth_gre_enable: Eth GRE enable flag. 2444 * @ip_gre_enable: IP GRE enable flag. 2445 * 2446 * Return: Void. 2447 */ 2448 void qed_set_gre_enable(struct qed_hwfn *p_hwfn, 2449 struct qed_ptt *p_ptt, 2450 bool eth_gre_enable, bool ip_gre_enable); 2451 2452 /** 2453 * qed_set_geneve_dest_port(): Initializes geneve tunnel destination udp port 2454 * 2455 * @p_hwfn: HW device data. 2456 * @p_ptt: Ptt window used for writing the registers. 2457 * @dest_port: Geneve destination udp port. 2458 * 2459 * Retur: Void. 2460 */ 2461 void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn, 2462 struct qed_ptt *p_ptt, u16 dest_port); 2463 2464 /** 2465 * qed_set_geneve_enable(): Enable or disable GRE tunnel in HW. 2466 * 2467 * @p_hwfn: HW device data. 2468 * @p_ptt: Ptt window used for writing the registers. 2469 * @eth_geneve_enable: Eth GENEVE enable flag. 2470 * @ip_geneve_enable: IP GENEVE enable flag. 2471 * 2472 * Return: Void. 2473 */ 2474 void qed_set_geneve_enable(struct qed_hwfn *p_hwfn, 2475 struct qed_ptt *p_ptt, 2476 bool eth_geneve_enable, bool ip_geneve_enable); 2477 2478 void qed_set_vxlan_no_l2_enable(struct qed_hwfn *p_hwfn, 2479 struct qed_ptt *p_ptt, bool enable); 2480 2481 /** 2482 * qed_gft_disable(): Disable GFT. 2483 * 2484 * @p_hwfn: HW device data. 2485 * @p_ptt: Ptt window used for writing the registers. 2486 * @pf_id: PF on which to disable GFT. 2487 * 2488 * Return: Void. 2489 */ 2490 void qed_gft_disable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 pf_id); 2491 2492 /** 2493 * qed_gft_config(): Enable and configure HW for GFT. 2494 * 2495 * @p_hwfn: HW device data. 2496 * @p_ptt: Ptt window used for writing the registers. 2497 * @pf_id: PF on which to enable GFT. 2498 * @tcp: Set profile tcp packets. 2499 * @udp: Set profile udp packet. 2500 * @ipv4: Set profile ipv4 packet. 2501 * @ipv6: Set profile ipv6 packet. 2502 * @profile_type: Define packet same fields. Use enum gft_profile_type. 2503 * 2504 * Return: Void. 2505 */ 2506 void qed_gft_config(struct qed_hwfn *p_hwfn, 2507 struct qed_ptt *p_ptt, 2508 u16 pf_id, 2509 bool tcp, 2510 bool udp, 2511 bool ipv4, bool ipv6, enum gft_profile_type profile_type); 2512 2513 /** 2514 * qed_enable_context_validation(): Enable and configure context 2515 * validation. 2516 * 2517 * @p_hwfn: HW device data. 2518 * @p_ptt: Ptt window used for writing the registers. 2519 * 2520 * Return: Void. 2521 */ 2522 void qed_enable_context_validation(struct qed_hwfn *p_hwfn, 2523 struct qed_ptt *p_ptt); 2524 2525 /** 2526 * qed_calc_session_ctx_validation(): Calcualte validation byte for 2527 * session context. 2528 * 2529 * @p_ctx_mem: Pointer to context memory. 2530 * @ctx_size: Context size. 2531 * @ctx_type: Context type. 2532 * @cid: Context cid. 2533 * 2534 * Return: Void. 2535 */ 2536 void qed_calc_session_ctx_validation(void *p_ctx_mem, 2537 u16 ctx_size, u8 ctx_type, u32 cid); 2538 2539 /** 2540 * qed_calc_task_ctx_validation(): Calcualte validation byte for task 2541 * context. 2542 * 2543 * @p_ctx_mem: Pointer to context memory. 2544 * @ctx_size: Context size. 2545 * @ctx_type: Context type. 2546 * @tid: Context tid. 2547 * 2548 * Return: Void. 2549 */ 2550 void qed_calc_task_ctx_validation(void *p_ctx_mem, 2551 u16 ctx_size, u8 ctx_type, u32 tid); 2552 2553 /** 2554 * qed_memset_session_ctx(): Memset session context to 0 while 2555 * preserving validation bytes. 2556 * 2557 * @p_ctx_mem: Pointer to context memory. 2558 * @ctx_size: Size to initialzie. 2559 * @ctx_type: Context type. 2560 * 2561 * Return: Void. 2562 */ 2563 void qed_memset_session_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type); 2564 2565 /** 2566 * qed_memset_task_ctx(): Memset task context to 0 while preserving 2567 * validation bytes. 2568 * 2569 * @p_ctx_mem: Pointer to context memory. 2570 * @ctx_size: size to initialzie. 2571 * @ctx_type: context type. 2572 * 2573 * Return: Void. 2574 */ 2575 void qed_memset_task_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type); 2576 2577 #define NUM_STORMS 6 2578 2579 /** 2580 * qed_set_rdma_error_level(): Sets the RDMA assert level. 2581 * If the severity of the error will be 2582 * above the level, the FW will assert. 2583 * @p_hwfn: HW device data. 2584 * @p_ptt: Ptt window used for writing the registers. 2585 * @assert_level: An array of assert levels for each storm. 2586 * 2587 * Return: Void. 2588 */ 2589 void qed_set_rdma_error_level(struct qed_hwfn *p_hwfn, 2590 struct qed_ptt *p_ptt, 2591 u8 assert_level[NUM_STORMS]); 2592 /** 2593 * qed_fw_overlay_mem_alloc(): Allocates and fills the FW overlay memory. 2594 * 2595 * @p_hwfn: HW device data. 2596 * @fw_overlay_in_buf: The input FW overlay buffer. 2597 * @buf_size_in_bytes: The size of the input FW overlay buffer in bytes. 2598 * must be aligned to dwords. 2599 * 2600 * Return: A pointer to the allocated overlays memory, 2601 * or NULL in case of failures. 2602 */ 2603 struct phys_mem_desc * 2604 qed_fw_overlay_mem_alloc(struct qed_hwfn *p_hwfn, 2605 const u32 *const fw_overlay_in_buf, 2606 u32 buf_size_in_bytes); 2607 2608 /** 2609 * qed_fw_overlay_init_ram(): Initializes the FW overlay RAM. 2610 * 2611 * @p_hwfn: HW device data. 2612 * @p_ptt: Ptt window used for writing the registers. 2613 * @fw_overlay_mem: the allocated FW overlay memory. 2614 * 2615 * Return: Void. 2616 */ 2617 void qed_fw_overlay_init_ram(struct qed_hwfn *p_hwfn, 2618 struct qed_ptt *p_ptt, 2619 struct phys_mem_desc *fw_overlay_mem); 2620 2621 /** 2622 * qed_fw_overlay_mem_free(): Frees the FW overlay memory. 2623 * 2624 * @p_hwfn: HW device data. 2625 * @fw_overlay_mem: The allocated FW overlay memory to free. 2626 * 2627 * Return: Void. 2628 */ 2629 void qed_fw_overlay_mem_free(struct qed_hwfn *p_hwfn, 2630 struct phys_mem_desc *fw_overlay_mem); 2631 2632 /* Runtime array offsets */ 2633 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0 2634 #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1 2635 #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2 2636 #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3 2637 #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4 2638 #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5 2639 #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6 2640 #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7 2641 #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8 2642 #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9 2643 #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10 2644 #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11 2645 #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12 2646 #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13 2647 #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14 2648 #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15 2649 #define DORQ_REG_VF_ICID_BIT_SHIFT_NORM_RT_OFFSET 16 2650 #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 17 2651 #define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 18 2652 #define IGU_REG_PF_CONFIGURATION_RT_OFFSET 19 2653 #define IGU_REG_VF_CONFIGURATION_RT_OFFSET 20 2654 #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 21 2655 #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 22 2656 #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 23 2657 #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 24 2658 #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 25 2659 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 26 2660 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736 2661 #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 762 2662 #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736 2663 #define CAU_REG_PI_MEMORY_RT_OFFSET 1498 2664 #define CAU_REG_PI_MEMORY_RT_SIZE 4416 2665 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 5914 2666 #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 5915 2667 #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 5916 2668 #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 5917 2669 #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 5918 2670 #define PRS_REG_SEARCH_TCP_RT_OFFSET 5919 2671 #define PRS_REG_SEARCH_FCOE_RT_OFFSET 5920 2672 #define PRS_REG_SEARCH_ROCE_RT_OFFSET 5921 2673 #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 5922 2674 #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 5923 2675 #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 5924 2676 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 5925 2677 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 5926 2678 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 5927 2679 #define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 5928 2680 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 5929 2681 #define SRC_REG_FIRSTFREE_RT_OFFSET 5930 2682 #define SRC_REG_FIRSTFREE_RT_SIZE 2 2683 #define SRC_REG_LASTFREE_RT_OFFSET 5932 2684 #define SRC_REG_LASTFREE_RT_SIZE 2 2685 #define SRC_REG_COUNTFREE_RT_OFFSET 5934 2686 #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 5935 2687 #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 5936 2688 #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 5937 2689 #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 5938 2690 #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 5939 2691 #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 5940 2692 #define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 5941 2693 #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 5942 2694 #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 5943 2695 #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 5944 2696 #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 5945 2697 #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 5946 2698 #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 5947 2699 #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 5948 2700 #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 5949 2701 #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 5950 2702 #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 5951 2703 #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 5952 2704 #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 5953 2705 #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 5954 2706 #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 5955 2707 #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 5956 2708 #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 5957 2709 #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 5958 2710 #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 5959 2711 #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 5960 2712 #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 5961 2713 #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 5962 2714 #define PSWRQ2_REG_VF_BASE_RT_OFFSET 5963 2715 #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 5964 2716 #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 5965 2717 #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 5966 2718 #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 5967 2719 #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000 2720 #define PGLUE_REG_B_VF_BASE_RT_OFFSET 27967 2721 #define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 27968 2722 #define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 27969 2723 #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 27970 2724 #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 27971 2725 #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 27972 2726 #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 27973 2727 #define TM_REG_VF_ENABLE_CONN_RT_OFFSET 27974 2728 #define TM_REG_PF_ENABLE_CONN_RT_OFFSET 27975 2729 #define TM_REG_PF_ENABLE_TASK_RT_OFFSET 27976 2730 #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 27977 2731 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 27978 2732 #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 27979 2733 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416 2734 #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 28395 2735 #define TM_REG_CONFIG_TASK_MEM_RT_SIZE 512 2736 #define QM_REG_MAXPQSIZE_0_RT_OFFSET 28907 2737 #define QM_REG_MAXPQSIZE_1_RT_OFFSET 28908 2738 #define QM_REG_MAXPQSIZE_2_RT_OFFSET 28909 2739 #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 28910 2740 #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 28911 2741 #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 28912 2742 #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 28913 2743 #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 28914 2744 #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 28915 2745 #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 28916 2746 #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 28917 2747 #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 28918 2748 #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 28919 2749 #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 28920 2750 #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 28921 2751 #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 28922 2752 #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 28923 2753 #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 28924 2754 #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 28925 2755 #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 28926 2756 #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 28927 2757 #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 28928 2758 #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 28929 2759 #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 28930 2760 #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 28931 2761 #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 28932 2762 #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 28933 2763 #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 28934 2764 #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 28935 2765 #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 28936 2766 #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 28937 2767 #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 28938 2768 #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 28939 2769 #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 28940 2770 #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 28941 2771 #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 28942 2772 #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 28943 2773 #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 28944 2774 #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 28945 2775 #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 28946 2776 #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 28947 2777 #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 28948 2778 #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 28949 2779 #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 28950 2780 #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 28951 2781 #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 28952 2782 #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 28953 2783 #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 28954 2784 #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 28955 2785 #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 28956 2786 #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 28957 2787 #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 28958 2788 #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 28959 2789 #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 28960 2790 #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 28961 2791 #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 28962 2792 #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 28963 2793 #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 28964 2794 #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 28965 2795 #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 28966 2796 #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 28967 2797 #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 28968 2798 #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 28969 2799 #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 28970 2800 #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 28971 2801 #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 28972 2802 #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 28973 2803 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET 28974 2804 #define QM_REG_BASEADDROTHERPQ_RT_SIZE 128 2805 #define QM_REG_PTRTBLOTHER_RT_OFFSET 29102 2806 #define QM_REG_PTRTBLOTHER_RT_SIZE 256 2807 #define QM_REG_VOQCRDLINE_RT_OFFSET 29358 2808 #define QM_REG_VOQCRDLINE_RT_SIZE 20 2809 #define QM_REG_VOQINITCRDLINE_RT_OFFSET 29378 2810 #define QM_REG_VOQINITCRDLINE_RT_SIZE 20 2811 #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29398 2812 #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29399 2813 #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29400 2814 #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29401 2815 #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29402 2816 #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29403 2817 #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29404 2818 #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29405 2819 #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29406 2820 #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29407 2821 #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29408 2822 #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29409 2823 #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29410 2824 #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29411 2825 #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29412 2826 #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29413 2827 #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29414 2828 #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29415 2829 #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29416 2830 #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29417 2831 #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29418 2832 #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29419 2833 #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29420 2834 #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29421 2835 #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29422 2836 #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29423 2837 #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29424 2838 #define QM_REG_PQTX2PF_0_RT_OFFSET 29425 2839 #define QM_REG_PQTX2PF_1_RT_OFFSET 29426 2840 #define QM_REG_PQTX2PF_2_RT_OFFSET 29427 2841 #define QM_REG_PQTX2PF_3_RT_OFFSET 29428 2842 #define QM_REG_PQTX2PF_4_RT_OFFSET 29429 2843 #define QM_REG_PQTX2PF_5_RT_OFFSET 29430 2844 #define QM_REG_PQTX2PF_6_RT_OFFSET 29431 2845 #define QM_REG_PQTX2PF_7_RT_OFFSET 29432 2846 #define QM_REG_PQTX2PF_8_RT_OFFSET 29433 2847 #define QM_REG_PQTX2PF_9_RT_OFFSET 29434 2848 #define QM_REG_PQTX2PF_10_RT_OFFSET 29435 2849 #define QM_REG_PQTX2PF_11_RT_OFFSET 29436 2850 #define QM_REG_PQTX2PF_12_RT_OFFSET 29437 2851 #define QM_REG_PQTX2PF_13_RT_OFFSET 29438 2852 #define QM_REG_PQTX2PF_14_RT_OFFSET 29439 2853 #define QM_REG_PQTX2PF_15_RT_OFFSET 29440 2854 #define QM_REG_PQTX2PF_16_RT_OFFSET 29441 2855 #define QM_REG_PQTX2PF_17_RT_OFFSET 29442 2856 #define QM_REG_PQTX2PF_18_RT_OFFSET 29443 2857 #define QM_REG_PQTX2PF_19_RT_OFFSET 29444 2858 #define QM_REG_PQTX2PF_20_RT_OFFSET 29445 2859 #define QM_REG_PQTX2PF_21_RT_OFFSET 29446 2860 #define QM_REG_PQTX2PF_22_RT_OFFSET 29447 2861 #define QM_REG_PQTX2PF_23_RT_OFFSET 29448 2862 #define QM_REG_PQTX2PF_24_RT_OFFSET 29449 2863 #define QM_REG_PQTX2PF_25_RT_OFFSET 29450 2864 #define QM_REG_PQTX2PF_26_RT_OFFSET 29451 2865 #define QM_REG_PQTX2PF_27_RT_OFFSET 29452 2866 #define QM_REG_PQTX2PF_28_RT_OFFSET 29453 2867 #define QM_REG_PQTX2PF_29_RT_OFFSET 29454 2868 #define QM_REG_PQTX2PF_30_RT_OFFSET 29455 2869 #define QM_REG_PQTX2PF_31_RT_OFFSET 29456 2870 #define QM_REG_PQTX2PF_32_RT_OFFSET 29457 2871 #define QM_REG_PQTX2PF_33_RT_OFFSET 29458 2872 #define QM_REG_PQTX2PF_34_RT_OFFSET 29459 2873 #define QM_REG_PQTX2PF_35_RT_OFFSET 29460 2874 #define QM_REG_PQTX2PF_36_RT_OFFSET 29461 2875 #define QM_REG_PQTX2PF_37_RT_OFFSET 29462 2876 #define QM_REG_PQTX2PF_38_RT_OFFSET 29463 2877 #define QM_REG_PQTX2PF_39_RT_OFFSET 29464 2878 #define QM_REG_PQTX2PF_40_RT_OFFSET 29465 2879 #define QM_REG_PQTX2PF_41_RT_OFFSET 29466 2880 #define QM_REG_PQTX2PF_42_RT_OFFSET 29467 2881 #define QM_REG_PQTX2PF_43_RT_OFFSET 29468 2882 #define QM_REG_PQTX2PF_44_RT_OFFSET 29469 2883 #define QM_REG_PQTX2PF_45_RT_OFFSET 29470 2884 #define QM_REG_PQTX2PF_46_RT_OFFSET 29471 2885 #define QM_REG_PQTX2PF_47_RT_OFFSET 29472 2886 #define QM_REG_PQTX2PF_48_RT_OFFSET 29473 2887 #define QM_REG_PQTX2PF_49_RT_OFFSET 29474 2888 #define QM_REG_PQTX2PF_50_RT_OFFSET 29475 2889 #define QM_REG_PQTX2PF_51_RT_OFFSET 29476 2890 #define QM_REG_PQTX2PF_52_RT_OFFSET 29477 2891 #define QM_REG_PQTX2PF_53_RT_OFFSET 29478 2892 #define QM_REG_PQTX2PF_54_RT_OFFSET 29479 2893 #define QM_REG_PQTX2PF_55_RT_OFFSET 29480 2894 #define QM_REG_PQTX2PF_56_RT_OFFSET 29481 2895 #define QM_REG_PQTX2PF_57_RT_OFFSET 29482 2896 #define QM_REG_PQTX2PF_58_RT_OFFSET 29483 2897 #define QM_REG_PQTX2PF_59_RT_OFFSET 29484 2898 #define QM_REG_PQTX2PF_60_RT_OFFSET 29485 2899 #define QM_REG_PQTX2PF_61_RT_OFFSET 29486 2900 #define QM_REG_PQTX2PF_62_RT_OFFSET 29487 2901 #define QM_REG_PQTX2PF_63_RT_OFFSET 29488 2902 #define QM_REG_PQOTHER2PF_0_RT_OFFSET 29489 2903 #define QM_REG_PQOTHER2PF_1_RT_OFFSET 29490 2904 #define QM_REG_PQOTHER2PF_2_RT_OFFSET 29491 2905 #define QM_REG_PQOTHER2PF_3_RT_OFFSET 29492 2906 #define QM_REG_PQOTHER2PF_4_RT_OFFSET 29493 2907 #define QM_REG_PQOTHER2PF_5_RT_OFFSET 29494 2908 #define QM_REG_PQOTHER2PF_6_RT_OFFSET 29495 2909 #define QM_REG_PQOTHER2PF_7_RT_OFFSET 29496 2910 #define QM_REG_PQOTHER2PF_8_RT_OFFSET 29497 2911 #define QM_REG_PQOTHER2PF_9_RT_OFFSET 29498 2912 #define QM_REG_PQOTHER2PF_10_RT_OFFSET 29499 2913 #define QM_REG_PQOTHER2PF_11_RT_OFFSET 29500 2914 #define QM_REG_PQOTHER2PF_12_RT_OFFSET 29501 2915 #define QM_REG_PQOTHER2PF_13_RT_OFFSET 29502 2916 #define QM_REG_PQOTHER2PF_14_RT_OFFSET 29503 2917 #define QM_REG_PQOTHER2PF_15_RT_OFFSET 29504 2918 #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 29505 2919 #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 29506 2920 #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 29507 2921 #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 29508 2922 #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 29509 2923 #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 29510 2924 #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 29511 2925 #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 29512 2926 #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 29513 2927 #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 29514 2928 #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 29515 2929 #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 29516 2930 #define QM_REG_RLGLBLINCVAL_RT_OFFSET 29517 2931 #define QM_REG_RLGLBLINCVAL_RT_SIZE 256 2932 #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 29773 2933 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256 2934 #define QM_REG_RLGLBLCRD_RT_OFFSET 30029 2935 #define QM_REG_RLGLBLCRD_RT_SIZE 256 2936 #define QM_REG_RLGLBLENABLE_RT_OFFSET 30285 2937 #define QM_REG_RLPFPERIOD_RT_OFFSET 30286 2938 #define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30287 2939 #define QM_REG_RLPFINCVAL_RT_OFFSET 30288 2940 #define QM_REG_RLPFINCVAL_RT_SIZE 16 2941 #define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30304 2942 #define QM_REG_RLPFUPPERBOUND_RT_SIZE 16 2943 #define QM_REG_RLPFCRD_RT_OFFSET 30320 2944 #define QM_REG_RLPFCRD_RT_SIZE 16 2945 #define QM_REG_RLPFENABLE_RT_OFFSET 30336 2946 #define QM_REG_RLPFVOQENABLE_RT_OFFSET 30337 2947 #define QM_REG_WFQPFWEIGHT_RT_OFFSET 30338 2948 #define QM_REG_WFQPFWEIGHT_RT_SIZE 16 2949 #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30354 2950 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16 2951 #define QM_REG_WFQPFCRD_RT_OFFSET 30370 2952 #define QM_REG_WFQPFCRD_RT_SIZE 160 2953 #define QM_REG_WFQPFENABLE_RT_OFFSET 30530 2954 #define QM_REG_WFQVPENABLE_RT_OFFSET 30531 2955 #define QM_REG_BASEADDRTXPQ_RT_OFFSET 30532 2956 #define QM_REG_BASEADDRTXPQ_RT_SIZE 512 2957 #define QM_REG_TXPQMAP_RT_OFFSET 31044 2958 #define QM_REG_TXPQMAP_RT_SIZE 512 2959 #define QM_REG_WFQVPWEIGHT_RT_OFFSET 31556 2960 #define QM_REG_WFQVPWEIGHT_RT_SIZE 512 2961 #define QM_REG_WFQVPCRD_RT_OFFSET 32068 2962 #define QM_REG_WFQVPCRD_RT_SIZE 512 2963 #define QM_REG_WFQVPMAP_RT_OFFSET 32580 2964 #define QM_REG_WFQVPMAP_RT_SIZE 512 2965 #define QM_REG_PTRTBLTX_RT_OFFSET 33092 2966 #define QM_REG_PTRTBLTX_RT_SIZE 1024 2967 #define QM_REG_WFQPFCRD_MSB_RT_OFFSET 34116 2968 #define QM_REG_WFQPFCRD_MSB_RT_SIZE 160 2969 #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 34276 2970 #define NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET 34277 2971 #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 34278 2972 #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 34279 2973 #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 34280 2974 #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 34281 2975 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 34282 2976 #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 34283 2977 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4 2978 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 34287 2979 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4 2980 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 34291 2981 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32 2982 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 34323 2983 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16 2984 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 34339 2985 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16 2986 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 34355 2987 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16 2988 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 34371 2989 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16 2990 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 34387 2991 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET 34388 2992 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE 8 2993 #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 34396 2994 #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 34397 2995 #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 34398 2996 #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 34399 2997 #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 34400 2998 #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 34401 2999 #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 34402 3000 #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 34403 3001 #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 34404 3002 #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 34405 3003 #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 34406 3004 #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 34407 3005 #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 34408 3006 #define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 34409 3007 #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 34410 3008 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 34411 3009 #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 34412 3010 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 34413 3011 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 34414 3012 #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 34415 3013 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 34416 3014 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 34417 3015 #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 34418 3016 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 34419 3017 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 34420 3018 #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 34421 3019 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 34422 3020 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 34423 3021 #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 34424 3022 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 34425 3023 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 34426 3024 #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 34427 3025 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 34428 3026 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 34429 3027 #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 34430 3028 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 34431 3029 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 34432 3030 #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 34433 3031 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 34434 3032 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 34435 3033 #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 34436 3034 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 34437 3035 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 34438 3036 #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 34439 3037 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 34440 3038 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 34441 3039 #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 34442 3040 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 34443 3041 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 34444 3042 #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 34445 3043 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 34446 3044 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 34447 3045 #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 34448 3046 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 34449 3047 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 34450 3048 #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 34451 3049 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 34452 3050 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 34453 3051 #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 34454 3052 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 34455 3053 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 34456 3054 #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 34457 3055 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 34458 3056 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 34459 3057 #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 34460 3058 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 34461 3059 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 34462 3060 #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 34463 3061 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 34464 3062 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 34465 3063 #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 34466 3064 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 34467 3065 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 34468 3066 #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 34469 3067 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 34470 3068 #define XCM_REG_CON_PHY_Q3_RT_OFFSET 34471 3069 3070 #define RUNTIME_ARRAY_SIZE 34472 3071 3072 /* Init Callbacks */ 3073 #define DMAE_READY_CB 0 3074 3075 /* The eth storm context for the Tstorm */ 3076 struct tstorm_eth_conn_st_ctx { 3077 __le32 reserved[4]; 3078 }; 3079 3080 /* The eth storm context for the Pstorm */ 3081 struct pstorm_eth_conn_st_ctx { 3082 __le32 reserved[8]; 3083 }; 3084 3085 /* The eth storm context for the Xstorm */ 3086 struct xstorm_eth_conn_st_ctx { 3087 __le32 reserved[60]; 3088 }; 3089 3090 struct xstorm_eth_conn_ag_ctx { 3091 u8 reserved0; 3092 u8 state; 3093 u8 flags0; 3094 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 3095 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 3096 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1 3097 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1 3098 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1 3099 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2 3100 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 3101 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 3102 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1 3103 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4 3104 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1 3105 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5 3106 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1 3107 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6 3108 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1 3109 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7 3110 u8 flags1; 3111 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1 3112 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0 3113 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1 3114 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1 3115 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1 3116 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2 3117 #define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1 3118 #define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3 3119 #define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 3120 #define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_SHIFT 4 3121 #define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 3122 #define XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_SHIFT 5 3123 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 3124 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 3125 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 3126 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 3127 u8 flags2; 3128 #define XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 3129 #define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0 3130 #define XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 3131 #define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2 3132 #define XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 3133 #define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4 3134 #define XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 3135 #define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6 3136 u8 flags3; 3137 #define XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 3138 #define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0 3139 #define XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 3140 #define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2 3141 #define XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 3142 #define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4 3143 #define XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 3144 #define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6 3145 u8 flags4; 3146 #define XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 3147 #define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0 3148 #define XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 3149 #define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2 3150 #define XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 3151 #define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4 3152 #define XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3 3153 #define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6 3154 u8 flags5; 3155 #define XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3 3156 #define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0 3157 #define XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3 3158 #define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2 3159 #define XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3 3160 #define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4 3161 #define XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3 3162 #define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6 3163 u8 flags6; 3164 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 3165 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 3166 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 3167 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 3168 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3 3169 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4 3170 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 3171 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 3172 u8 flags7; 3173 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 3174 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 3175 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3 3176 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2 3177 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3 3178 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4 3179 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 3180 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6 3181 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 3182 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7 3183 u8 flags8; 3184 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 3185 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0 3186 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 3187 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1 3188 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 3189 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2 3190 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 3191 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3 3192 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 3193 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4 3194 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 3195 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5 3196 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 3197 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6 3198 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 3199 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7 3200 u8 flags9; 3201 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 3202 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0 3203 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1 3204 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1 3205 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1 3206 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2 3207 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1 3208 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3 3209 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1 3210 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4 3211 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1 3212 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5 3213 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 3214 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 3215 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 3216 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 3217 u8 flags10; 3218 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 3219 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 3220 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 3221 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 3222 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 3223 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 3224 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1 3225 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3 3226 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 3227 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 3228 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 3229 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 3230 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1 3231 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6 3232 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1 3233 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7 3234 u8 flags11; 3235 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1 3236 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0 3237 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1 3238 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1 3239 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 3240 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 3241 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 3242 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3 3243 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 3244 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4 3245 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 3246 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5 3247 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 3248 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 3249 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1 3250 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7 3251 u8 flags12; 3252 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1 3253 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0 3254 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1 3255 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1 3256 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 3257 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 3258 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 3259 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 3260 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1 3261 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4 3262 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1 3263 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5 3264 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1 3265 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6 3266 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1 3267 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7 3268 u8 flags13; 3269 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1 3270 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0 3271 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1 3272 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1 3273 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 3274 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 3275 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 3276 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 3277 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 3278 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 3279 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 3280 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 3281 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 3282 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 3283 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 3284 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 3285 u8 flags14; 3286 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 3287 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 3288 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 3289 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 3290 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 3291 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 3292 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 3293 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 3294 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 3295 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 3296 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 3297 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 3298 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 3299 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 3300 u8 edpm_event_id; 3301 __le16 physical_q0; 3302 __le16 e5_reserved1; 3303 __le16 edpm_num_bds; 3304 __le16 tx_bd_cons; 3305 __le16 tx_bd_prod; 3306 __le16 updated_qm_pq_id; 3307 __le16 conn_dpi; 3308 u8 byte3; 3309 u8 byte4; 3310 u8 byte5; 3311 u8 byte6; 3312 __le32 reg0; 3313 __le32 reg1; 3314 __le32 reg2; 3315 __le32 reg3; 3316 __le32 reg4; 3317 __le32 reg5; 3318 __le32 reg6; 3319 __le16 word7; 3320 __le16 word8; 3321 __le16 word9; 3322 __le16 word10; 3323 __le32 reg7; 3324 __le32 reg8; 3325 __le32 reg9; 3326 u8 byte7; 3327 u8 byte8; 3328 u8 byte9; 3329 u8 byte10; 3330 u8 byte11; 3331 u8 byte12; 3332 u8 byte13; 3333 u8 byte14; 3334 u8 byte15; 3335 u8 e5_reserved; 3336 __le16 word11; 3337 __le32 reg10; 3338 __le32 reg11; 3339 __le32 reg12; 3340 __le32 reg13; 3341 __le32 reg14; 3342 __le32 reg15; 3343 __le32 reg16; 3344 __le32 reg17; 3345 __le32 reg18; 3346 __le32 reg19; 3347 __le16 word12; 3348 __le16 word13; 3349 __le16 word14; 3350 __le16 word15; 3351 }; 3352 3353 /* The eth storm context for the Ystorm */ 3354 struct ystorm_eth_conn_st_ctx { 3355 __le32 reserved[8]; 3356 }; 3357 3358 struct ystorm_eth_conn_ag_ctx { 3359 u8 byte0; 3360 u8 state; 3361 u8 flags0; 3362 #define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 3363 #define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 3364 #define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 3365 #define YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 3366 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 3367 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2 3368 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3 3369 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4 3370 #define YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 3371 #define YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 3372 u8 flags1; 3373 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 3374 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0 3375 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1 3376 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1 3377 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 3378 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 3379 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 3380 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 3381 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 3382 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 3383 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 3384 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 3385 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 3386 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 3387 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 3388 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 3389 u8 tx_q0_int_coallecing_timeset; 3390 u8 byte3; 3391 __le16 word0; 3392 __le32 terminate_spqe; 3393 __le32 reg1; 3394 __le16 tx_bd_cons_upd; 3395 __le16 word2; 3396 __le16 word3; 3397 __le16 word4; 3398 __le32 reg2; 3399 __le32 reg3; 3400 }; 3401 3402 struct tstorm_eth_conn_ag_ctx { 3403 u8 byte0; 3404 u8 byte1; 3405 u8 flags0; 3406 #define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 3407 #define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 3408 #define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 3409 #define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 3410 #define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1 3411 #define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2 3412 #define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1 3413 #define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3 3414 #define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1 3415 #define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4 3416 #define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1 3417 #define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5 3418 #define TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 3419 #define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6 3420 u8 flags1; 3421 #define TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 3422 #define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0 3423 #define TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 3424 #define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2 3425 #define TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 3426 #define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4 3427 #define TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 3428 #define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6 3429 u8 flags2; 3430 #define TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 3431 #define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0 3432 #define TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 3433 #define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2 3434 #define TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 3435 #define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4 3436 #define TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 3437 #define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6 3438 u8 flags3; 3439 #define TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 3440 #define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0 3441 #define TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 3442 #define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2 3443 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 3444 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4 3445 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 3446 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5 3447 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 3448 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6 3449 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 3450 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7 3451 u8 flags4; 3452 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 3453 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0 3454 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 3455 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1 3456 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 3457 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2 3458 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 3459 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3 3460 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 3461 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4 3462 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 3463 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5 3464 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 3465 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6 3466 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 3467 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 3468 u8 flags5; 3469 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 3470 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 3471 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 3472 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 3473 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 3474 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 3475 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 3476 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 3477 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 3478 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 3479 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1 3480 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5 3481 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 3482 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 3483 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 3484 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 3485 __le32 reg0; 3486 __le32 reg1; 3487 __le32 reg2; 3488 __le32 reg3; 3489 __le32 reg4; 3490 __le32 reg5; 3491 __le32 reg6; 3492 __le32 reg7; 3493 __le32 reg8; 3494 u8 byte2; 3495 u8 byte3; 3496 __le16 rx_bd_cons; 3497 u8 byte4; 3498 u8 byte5; 3499 __le16 rx_bd_prod; 3500 __le16 word2; 3501 __le16 word3; 3502 __le32 reg9; 3503 __le32 reg10; 3504 }; 3505 3506 struct ustorm_eth_conn_ag_ctx { 3507 u8 byte0; 3508 u8 byte1; 3509 u8 flags0; 3510 #define USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 3511 #define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 3512 #define USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 3513 #define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 3514 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3 3515 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2 3516 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3 3517 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4 3518 #define USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 3519 #define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 3520 u8 flags1; 3521 #define USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 3522 #define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0 3523 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3 3524 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2 3525 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3 3526 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4 3527 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 3528 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6 3529 u8 flags2; 3530 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1 3531 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0 3532 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1 3533 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1 3534 #define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 3535 #define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 3536 #define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 3537 #define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3 3538 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1 3539 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4 3540 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1 3541 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5 3542 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 3543 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6 3544 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 3545 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 3546 u8 flags3; 3547 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 3548 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 3549 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 3550 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 3551 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 3552 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 3553 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 3554 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 3555 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 3556 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 3557 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 3558 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5 3559 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 3560 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 3561 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 3562 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 3563 u8 byte2; 3564 u8 byte3; 3565 __le16 word0; 3566 __le16 tx_bd_cons; 3567 __le32 reg0; 3568 __le32 reg1; 3569 __le32 reg2; 3570 __le32 tx_int_coallecing_timeset; 3571 __le16 tx_drv_bd_cons; 3572 __le16 rx_drv_cqe_cons; 3573 }; 3574 3575 /* The eth storm context for the Ustorm */ 3576 struct ustorm_eth_conn_st_ctx { 3577 __le32 reserved[40]; 3578 }; 3579 3580 /* The eth storm context for the Mstorm */ 3581 struct mstorm_eth_conn_st_ctx { 3582 __le32 reserved[8]; 3583 }; 3584 3585 /* eth connection context */ 3586 struct eth_conn_context { 3587 struct tstorm_eth_conn_st_ctx tstorm_st_context; 3588 struct regpair tstorm_st_padding[2]; 3589 struct pstorm_eth_conn_st_ctx pstorm_st_context; 3590 struct xstorm_eth_conn_st_ctx xstorm_st_context; 3591 struct xstorm_eth_conn_ag_ctx xstorm_ag_context; 3592 struct tstorm_eth_conn_ag_ctx tstorm_ag_context; 3593 struct ystorm_eth_conn_st_ctx ystorm_st_context; 3594 struct ystorm_eth_conn_ag_ctx ystorm_ag_context; 3595 struct ustorm_eth_conn_ag_ctx ustorm_ag_context; 3596 struct ustorm_eth_conn_st_ctx ustorm_st_context; 3597 struct mstorm_eth_conn_st_ctx mstorm_st_context; 3598 }; 3599 3600 /* Ethernet filter types: mac/vlan/pair */ 3601 enum eth_error_code { 3602 ETH_OK = 0x00, 3603 ETH_FILTERS_MAC_ADD_FAIL_FULL, 3604 ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2, 3605 ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2, 3606 ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2, 3607 ETH_FILTERS_MAC_DEL_FAIL_NOF, 3608 ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2, 3609 ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2, 3610 ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC, 3611 ETH_FILTERS_VLAN_ADD_FAIL_FULL, 3612 ETH_FILTERS_VLAN_ADD_FAIL_DUP, 3613 ETH_FILTERS_VLAN_DEL_FAIL_NOF, 3614 ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1, 3615 ETH_FILTERS_PAIR_ADD_FAIL_DUP, 3616 ETH_FILTERS_PAIR_ADD_FAIL_FULL, 3617 ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC, 3618 ETH_FILTERS_PAIR_DEL_FAIL_NOF, 3619 ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1, 3620 ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC, 3621 ETH_FILTERS_VNI_ADD_FAIL_FULL, 3622 ETH_FILTERS_VNI_ADD_FAIL_DUP, 3623 ETH_FILTERS_GFT_UPDATE_FAIL, 3624 ETH_RX_QUEUE_FAIL_LOAD_VF_DATA, 3625 ETH_FILTERS_GFS_ADD_FILTER_FAIL_MAX_HOPS, 3626 ETH_FILTERS_GFS_ADD_FILTER_FAIL_NO_FREE_ENRTY, 3627 ETH_FILTERS_GFS_ADD_FILTER_FAIL_ALREADY_EXISTS, 3628 ETH_FILTERS_GFS_ADD_FILTER_FAIL_PCI_ERROR, 3629 ETH_FILTERS_GFS_ADD_FINLER_FAIL_MAGIC_NUM_ERROR, 3630 ETH_FILTERS_GFS_DEL_FILTER_FAIL_MAX_HOPS, 3631 ETH_FILTERS_GFS_DEL_FILTER_FAIL_NO_MATCH_ENRTY, 3632 ETH_FILTERS_GFS_DEL_FILTER_FAIL_PCI_ERROR, 3633 ETH_FILTERS_GFS_DEL_FILTER_FAIL_MAGIC_NUM_ERROR, 3634 MAX_ETH_ERROR_CODE 3635 }; 3636 3637 /* Opcodes for the event ring */ 3638 enum eth_event_opcode { 3639 ETH_EVENT_UNUSED, 3640 ETH_EVENT_VPORT_START, 3641 ETH_EVENT_VPORT_UPDATE, 3642 ETH_EVENT_VPORT_STOP, 3643 ETH_EVENT_TX_QUEUE_START, 3644 ETH_EVENT_TX_QUEUE_STOP, 3645 ETH_EVENT_RX_QUEUE_START, 3646 ETH_EVENT_RX_QUEUE_UPDATE, 3647 ETH_EVENT_RX_QUEUE_STOP, 3648 ETH_EVENT_FILTERS_UPDATE, 3649 ETH_EVENT_RX_ADD_OPENFLOW_FILTER, 3650 ETH_EVENT_RX_DELETE_OPENFLOW_FILTER, 3651 ETH_EVENT_RX_CREATE_OPENFLOW_ACTION, 3652 ETH_EVENT_RX_ADD_UDP_FILTER, 3653 ETH_EVENT_RX_DELETE_UDP_FILTER, 3654 ETH_EVENT_RX_CREATE_GFT_ACTION, 3655 ETH_EVENT_RX_GFT_UPDATE_FILTER, 3656 ETH_EVENT_TX_QUEUE_UPDATE, 3657 ETH_EVENT_RGFS_ADD_FILTER, 3658 ETH_EVENT_RGFS_DEL_FILTER, 3659 ETH_EVENT_TGFS_ADD_FILTER, 3660 ETH_EVENT_TGFS_DEL_FILTER, 3661 ETH_EVENT_GFS_COUNTERS_REPORT_REQUEST, 3662 MAX_ETH_EVENT_OPCODE 3663 }; 3664 3665 /* Classify rule types in E2/E3 */ 3666 enum eth_filter_action { 3667 ETH_FILTER_ACTION_UNUSED, 3668 ETH_FILTER_ACTION_REMOVE, 3669 ETH_FILTER_ACTION_ADD, 3670 ETH_FILTER_ACTION_REMOVE_ALL, 3671 MAX_ETH_FILTER_ACTION 3672 }; 3673 3674 /* Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$ */ 3675 struct eth_filter_cmd { 3676 u8 type; 3677 u8 vport_id; 3678 u8 action; 3679 u8 reserved0; 3680 __le32 vni; 3681 __le16 mac_lsb; 3682 __le16 mac_mid; 3683 __le16 mac_msb; 3684 __le16 vlan_id; 3685 }; 3686 3687 /* $$KEEP_ENDIANNESS$$ */ 3688 struct eth_filter_cmd_header { 3689 u8 rx; 3690 u8 tx; 3691 u8 cmd_cnt; 3692 u8 assert_on_error; 3693 u8 reserved1[4]; 3694 }; 3695 3696 /* Ethernet filter types: mac/vlan/pair */ 3697 enum eth_filter_type { 3698 ETH_FILTER_TYPE_UNUSED, 3699 ETH_FILTER_TYPE_MAC, 3700 ETH_FILTER_TYPE_VLAN, 3701 ETH_FILTER_TYPE_PAIR, 3702 ETH_FILTER_TYPE_INNER_MAC, 3703 ETH_FILTER_TYPE_INNER_VLAN, 3704 ETH_FILTER_TYPE_INNER_PAIR, 3705 ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR, 3706 ETH_FILTER_TYPE_MAC_VNI_PAIR, 3707 ETH_FILTER_TYPE_VNI, 3708 MAX_ETH_FILTER_TYPE 3709 }; 3710 3711 /* inner to inner vlan priority translation configurations */ 3712 struct eth_in_to_in_pri_map_cfg { 3713 u8 inner_vlan_pri_remap_en; 3714 u8 reserved[7]; 3715 u8 non_rdma_in_to_in_pri_map[8]; 3716 u8 rdma_in_to_in_pri_map[8]; 3717 }; 3718 3719 /* Eth IPv4 Fragment Type */ 3720 enum eth_ipv4_frag_type { 3721 ETH_IPV4_NOT_FRAG, 3722 ETH_IPV4_FIRST_FRAG, 3723 ETH_IPV4_NON_FIRST_FRAG, 3724 MAX_ETH_IPV4_FRAG_TYPE 3725 }; 3726 3727 /* eth IPv4 Fragment Type */ 3728 enum eth_ip_type { 3729 ETH_IPV4, 3730 ETH_IPV6, 3731 MAX_ETH_IP_TYPE 3732 }; 3733 3734 /* Ethernet Ramrod Command IDs */ 3735 enum eth_ramrod_cmd_id { 3736 ETH_RAMROD_UNUSED, 3737 ETH_RAMROD_VPORT_START, 3738 ETH_RAMROD_VPORT_UPDATE, 3739 ETH_RAMROD_VPORT_STOP, 3740 ETH_RAMROD_RX_QUEUE_START, 3741 ETH_RAMROD_RX_QUEUE_STOP, 3742 ETH_RAMROD_TX_QUEUE_START, 3743 ETH_RAMROD_TX_QUEUE_STOP, 3744 ETH_RAMROD_FILTERS_UPDATE, 3745 ETH_RAMROD_RX_QUEUE_UPDATE, 3746 ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION, 3747 ETH_RAMROD_RX_ADD_OPENFLOW_FILTER, 3748 ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER, 3749 ETH_RAMROD_RX_ADD_UDP_FILTER, 3750 ETH_RAMROD_RX_DELETE_UDP_FILTER, 3751 ETH_RAMROD_RX_CREATE_GFT_ACTION, 3752 ETH_RAMROD_GFT_UPDATE_FILTER, 3753 ETH_RAMROD_TX_QUEUE_UPDATE, 3754 ETH_RAMROD_RGFS_FILTER_ADD, 3755 ETH_RAMROD_RGFS_FILTER_DEL, 3756 ETH_RAMROD_TGFS_FILTER_ADD, 3757 ETH_RAMROD_TGFS_FILTER_DEL, 3758 ETH_RAMROD_GFS_COUNTERS_REPORT_REQUEST, 3759 MAX_ETH_RAMROD_CMD_ID 3760 }; 3761 3762 /* Return code from eth sp ramrods */ 3763 struct eth_return_code { 3764 u8 value; 3765 #define ETH_RETURN_CODE_ERR_CODE_MASK 0x3F 3766 #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0 3767 #define ETH_RETURN_CODE_RESERVED_MASK 0x1 3768 #define ETH_RETURN_CODE_RESERVED_SHIFT 6 3769 #define ETH_RETURN_CODE_RX_TX_MASK 0x1 3770 #define ETH_RETURN_CODE_RX_TX_SHIFT 7 3771 }; 3772 3773 /* tx destination enum */ 3774 enum eth_tx_dst_mode_config_enum { 3775 ETH_TX_DST_MODE_CONFIG_DISABLE, 3776 ETH_TX_DST_MODE_CONFIG_FORWARD_DATA_IN_BD, 3777 ETH_TX_DST_MODE_CONFIG_FORWARD_DATA_IN_VPORT, 3778 MAX_ETH_TX_DST_MODE_CONFIG_ENUM 3779 }; 3780 3781 /* What to do in case an error occurs */ 3782 enum eth_tx_err { 3783 ETH_TX_ERR_DROP, 3784 ETH_TX_ERR_ASSERT_MALICIOUS, 3785 MAX_ETH_TX_ERR 3786 }; 3787 3788 /* Array of the different error type behaviors */ 3789 struct eth_tx_err_vals { 3790 __le16 values; 3791 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1 3792 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0 3793 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1 3794 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1 3795 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1 3796 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2 3797 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1 3798 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3 3799 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1 3800 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4 3801 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1 3802 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5 3803 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1 3804 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6 3805 #define ETH_TX_ERR_VALS_ILLEGAL_BD_FLAGS_MASK 0x1 3806 #define ETH_TX_ERR_VALS_ILLEGAL_BD_FLAGS_SHIFT 7 3807 #define ETH_TX_ERR_VALS_RESERVED_MASK 0xFF 3808 #define ETH_TX_ERR_VALS_RESERVED_SHIFT 8 3809 }; 3810 3811 /* vport rss configuration data */ 3812 struct eth_vport_rss_config { 3813 __le16 capabilities; 3814 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1 3815 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0 3816 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1 3817 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1 3818 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1 3819 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2 3820 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1 3821 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3 3822 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1 3823 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4 3824 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1 3825 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5 3826 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1 3827 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6 3828 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF 3829 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7 3830 u8 rss_id; 3831 u8 rss_mode; 3832 u8 update_rss_key; 3833 u8 update_rss_ind_table; 3834 u8 update_rss_capabilities; 3835 u8 tbl_size; 3836 __le32 reserved2[2]; 3837 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM]; 3838 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS]; 3839 __le32 reserved3[2]; 3840 }; 3841 3842 /* eth vport RSS mode */ 3843 enum eth_vport_rss_mode { 3844 ETH_VPORT_RSS_MODE_DISABLED, 3845 ETH_VPORT_RSS_MODE_REGULAR, 3846 MAX_ETH_VPORT_RSS_MODE 3847 }; 3848 3849 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */ 3850 struct eth_vport_rx_mode { 3851 __le16 state; 3852 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1 3853 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0 3854 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1 3855 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1 3856 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1 3857 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2 3858 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1 3859 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3 3860 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1 3861 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4 3862 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1 3863 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5 3864 #define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_MASK 0x1 3865 #define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_SHIFT 6 3866 #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x1FF 3867 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 7 3868 }; 3869 3870 /* Command for setting tpa parameters */ 3871 struct eth_vport_tpa_param { 3872 u8 tpa_ipv4_en_flg; 3873 u8 tpa_ipv6_en_flg; 3874 u8 tpa_ipv4_tunn_en_flg; 3875 u8 tpa_ipv6_tunn_en_flg; 3876 u8 tpa_pkt_split_flg; 3877 u8 tpa_hdr_data_split_flg; 3878 u8 tpa_gro_consistent_flg; 3879 3880 u8 tpa_max_aggs_num; 3881 3882 __le16 tpa_max_size; 3883 __le16 tpa_min_size_to_start; 3884 3885 __le16 tpa_min_size_to_cont; 3886 u8 max_buff_num; 3887 u8 reserved; 3888 }; 3889 3890 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */ 3891 struct eth_vport_tx_mode { 3892 __le16 state; 3893 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1 3894 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0 3895 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1 3896 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1 3897 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1 3898 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2 3899 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1 3900 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3 3901 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1 3902 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4 3903 #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF 3904 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5 3905 }; 3906 3907 /* GFT filter update action type */ 3908 enum gft_filter_update_action { 3909 GFT_ADD_FILTER, 3910 GFT_DELETE_FILTER, 3911 MAX_GFT_FILTER_UPDATE_ACTION 3912 }; 3913 3914 /* Ramrod data for rx add openflow filter */ 3915 struct rx_add_openflow_filter_data { 3916 __le16 action_icid; 3917 u8 priority; 3918 u8 reserved0; 3919 __le32 tenant_id; 3920 __le16 dst_mac_hi; 3921 __le16 dst_mac_mid; 3922 __le16 dst_mac_lo; 3923 __le16 src_mac_hi; 3924 __le16 src_mac_mid; 3925 __le16 src_mac_lo; 3926 __le16 vlan_id; 3927 __le16 l2_eth_type; 3928 u8 ipv4_dscp; 3929 u8 ipv4_frag_type; 3930 u8 ipv4_over_ip; 3931 u8 tenant_id_exists; 3932 __le32 ipv4_dst_addr; 3933 __le32 ipv4_src_addr; 3934 __le16 l4_dst_port; 3935 __le16 l4_src_port; 3936 }; 3937 3938 /* Ramrod data for rx create gft action */ 3939 struct rx_create_gft_action_data { 3940 u8 vport_id; 3941 u8 reserved[7]; 3942 }; 3943 3944 /* Ramrod data for rx create openflow action */ 3945 struct rx_create_openflow_action_data { 3946 u8 vport_id; 3947 u8 reserved[7]; 3948 }; 3949 3950 /* Ramrod data for rx queue start ramrod */ 3951 struct rx_queue_start_ramrod_data { 3952 __le16 rx_queue_id; 3953 __le16 num_of_pbl_pages; 3954 __le16 bd_max_bytes; 3955 __le16 sb_id; 3956 u8 sb_index; 3957 u8 vport_id; 3958 u8 default_rss_queue_flg; 3959 u8 complete_cqe_flg; 3960 u8 complete_event_flg; 3961 u8 stats_counter_id; 3962 u8 pin_context; 3963 u8 pxp_tph_valid_bd; 3964 u8 pxp_tph_valid_pkt; 3965 u8 pxp_st_hint; 3966 3967 __le16 pxp_st_index; 3968 u8 pmd_mode; 3969 3970 u8 notify_en; 3971 u8 toggle_val; 3972 3973 u8 vf_rx_prod_index; 3974 u8 vf_rx_prod_use_zone_a; 3975 u8 reserved[5]; 3976 __le16 reserved1; 3977 struct regpair cqe_pbl_addr; 3978 struct regpair bd_base; 3979 struct regpair reserved2; 3980 }; 3981 3982 /* Ramrod data for rx queue stop ramrod */ 3983 struct rx_queue_stop_ramrod_data { 3984 __le16 rx_queue_id; 3985 u8 complete_cqe_flg; 3986 u8 complete_event_flg; 3987 u8 vport_id; 3988 u8 reserved[3]; 3989 }; 3990 3991 /* Ramrod data for rx queue update ramrod */ 3992 struct rx_queue_update_ramrod_data { 3993 __le16 rx_queue_id; 3994 u8 complete_cqe_flg; 3995 u8 complete_event_flg; 3996 u8 vport_id; 3997 u8 set_default_rss_queue; 3998 u8 reserved[3]; 3999 u8 reserved1; 4000 u8 reserved2; 4001 u8 reserved3; 4002 __le16 reserved4; 4003 __le16 reserved5; 4004 struct regpair reserved6; 4005 }; 4006 4007 /* Ramrod data for rx Add UDP Filter */ 4008 struct rx_udp_filter_data { 4009 __le16 action_icid; 4010 __le16 vlan_id; 4011 u8 ip_type; 4012 u8 tenant_id_exists; 4013 __le16 reserved1; 4014 __le32 ip_dst_addr[4]; 4015 __le32 ip_src_addr[4]; 4016 __le16 udp_dst_port; 4017 __le16 udp_src_port; 4018 __le32 tenant_id; 4019 }; 4020 4021 /* Add or delete GFT filter - filter is packet header of type of packet wished 4022 * to pass certain FW flow. 4023 */ 4024 struct rx_update_gft_filter_data { 4025 struct regpair pkt_hdr_addr; 4026 __le16 pkt_hdr_length; 4027 __le16 action_icid; 4028 __le16 rx_qid; 4029 __le16 flow_id; 4030 __le16 vport_id; 4031 u8 action_icid_valid; 4032 u8 rx_qid_valid; 4033 u8 flow_id_valid; 4034 u8 filter_action; 4035 u8 assert_on_error; 4036 u8 inner_vlan_removal_en; 4037 }; 4038 4039 /* Ramrod data for tx queue start ramrod */ 4040 struct tx_queue_start_ramrod_data { 4041 __le16 sb_id; 4042 u8 sb_index; 4043 u8 vport_id; 4044 u8 reserved0; 4045 u8 stats_counter_id; 4046 __le16 qm_pq_id; 4047 u8 flags; 4048 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1 4049 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0 4050 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1 4051 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1 4052 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1 4053 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 2 4054 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1 4055 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 3 4056 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1 4057 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 4 4058 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x7 4059 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 5 4060 u8 pxp_st_hint; 4061 u8 pxp_tph_valid_bd; 4062 u8 pxp_tph_valid_pkt; 4063 __le16 pxp_st_index; 4064 __le16 comp_agg_size; 4065 __le16 queue_zone_id; 4066 __le16 reserved2; 4067 __le16 pbl_size; 4068 __le16 tx_queue_id; 4069 __le16 same_as_last_id; 4070 __le16 reserved[3]; 4071 struct regpair pbl_base_addr; 4072 struct regpair bd_cons_address; 4073 }; 4074 4075 /* Ramrod data for tx queue stop ramrod */ 4076 struct tx_queue_stop_ramrod_data { 4077 __le16 reserved[4]; 4078 }; 4079 4080 /* Ramrod data for tx queue update ramrod */ 4081 struct tx_queue_update_ramrod_data { 4082 __le16 update_qm_pq_id_flg; 4083 __le16 qm_pq_id; 4084 __le32 reserved0; 4085 struct regpair reserved1[5]; 4086 }; 4087 4088 /* Inner to Inner VLAN priority map update mode */ 4089 enum update_in_to_in_pri_map_mode_enum { 4090 ETH_IN_TO_IN_PRI_MAP_UPDATE_DISABLED, 4091 ETH_IN_TO_IN_PRI_MAP_UPDATE_NON_RDMA_TBL, 4092 ETH_IN_TO_IN_PRI_MAP_UPDATE_RDMA_TBL, 4093 MAX_UPDATE_IN_TO_IN_PRI_MAP_MODE_ENUM 4094 }; 4095 4096 /* Ramrod data for vport update ramrod */ 4097 struct vport_filter_update_ramrod_data { 4098 struct eth_filter_cmd_header filter_cmd_hdr; 4099 struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT]; 4100 }; 4101 4102 /* Ramrod data for vport start ramrod */ 4103 struct vport_start_ramrod_data { 4104 u8 vport_id; 4105 u8 sw_fid; 4106 __le16 mtu; 4107 u8 drop_ttl0_en; 4108 u8 inner_vlan_removal_en; 4109 struct eth_vport_rx_mode rx_mode; 4110 struct eth_vport_tx_mode tx_mode; 4111 struct eth_vport_tpa_param tpa_param; 4112 __le16 default_vlan; 4113 u8 tx_switching_en; 4114 u8 anti_spoofing_en; 4115 u8 default_vlan_en; 4116 u8 handle_ptp_pkts; 4117 u8 silent_vlan_removal_en; 4118 u8 untagged; 4119 struct eth_tx_err_vals tx_err_behav; 4120 u8 zero_placement_offset; 4121 u8 ctl_frame_mac_check_en; 4122 u8 ctl_frame_ethtype_check_en; 4123 u8 reserved0; 4124 u8 reserved1; 4125 u8 tx_dst_port_mode_config; 4126 u8 dst_vport_id; 4127 u8 tx_dst_port_mode; 4128 u8 dst_vport_id_valid; 4129 u8 wipe_inner_vlan_pri_en; 4130 u8 reserved2[2]; 4131 struct eth_in_to_in_pri_map_cfg in_to_in_vlan_pri_map_cfg; 4132 }; 4133 4134 /* Ramrod data for vport stop ramrod */ 4135 struct vport_stop_ramrod_data { 4136 u8 vport_id; 4137 u8 reserved[7]; 4138 }; 4139 4140 /* Ramrod data for vport update ramrod */ 4141 struct vport_update_ramrod_data_cmn { 4142 u8 vport_id; 4143 u8 update_rx_active_flg; 4144 u8 rx_active_flg; 4145 u8 update_tx_active_flg; 4146 u8 tx_active_flg; 4147 u8 update_rx_mode_flg; 4148 u8 update_tx_mode_flg; 4149 u8 update_approx_mcast_flg; 4150 4151 u8 update_rss_flg; 4152 u8 update_inner_vlan_removal_en_flg; 4153 4154 u8 inner_vlan_removal_en; 4155 u8 update_tpa_param_flg; 4156 u8 update_tpa_en_flg; 4157 u8 update_tx_switching_en_flg; 4158 4159 u8 tx_switching_en; 4160 u8 update_anti_spoofing_en_flg; 4161 4162 u8 anti_spoofing_en; 4163 u8 update_handle_ptp_pkts; 4164 4165 u8 handle_ptp_pkts; 4166 u8 update_default_vlan_en_flg; 4167 4168 u8 default_vlan_en; 4169 4170 u8 update_default_vlan_flg; 4171 4172 __le16 default_vlan; 4173 u8 update_accept_any_vlan_flg; 4174 4175 u8 accept_any_vlan; 4176 u8 silent_vlan_removal_en; 4177 u8 update_mtu_flg; 4178 4179 __le16 mtu; 4180 u8 update_ctl_frame_checks_en_flg; 4181 u8 ctl_frame_mac_check_en; 4182 u8 ctl_frame_ethtype_check_en; 4183 u8 update_in_to_in_pri_map_mode; 4184 u8 in_to_in_pri_map[8]; 4185 u8 reserved[6]; 4186 }; 4187 4188 struct vport_update_ramrod_mcast { 4189 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS]; 4190 }; 4191 4192 /* Ramrod data for vport update ramrod */ 4193 struct vport_update_ramrod_data { 4194 struct vport_update_ramrod_data_cmn common; 4195 4196 struct eth_vport_rx_mode rx_mode; 4197 struct eth_vport_tx_mode tx_mode; 4198 __le32 reserved[3]; 4199 struct eth_vport_tpa_param tpa_param; 4200 struct vport_update_ramrod_mcast approx_mcast; 4201 struct eth_vport_rss_config rss_config; 4202 }; 4203 4204 struct xstorm_eth_conn_ag_ctx_dq_ext_ldpart { 4205 u8 reserved0; 4206 u8 state; 4207 u8 flags0; 4208 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 4209 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 4210 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1 4211 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1 4212 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1 4213 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2 4214 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 4215 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 4216 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1 4217 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4 4218 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1 4219 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5 4220 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1 4221 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6 4222 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1 4223 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7 4224 u8 flags1; 4225 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1 4226 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0 4227 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1 4228 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1 4229 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1 4230 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2 4231 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 4232 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 4233 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_MASK 0x1 4234 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_SHIFT 4 4235 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_MASK 0x1 4236 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_SHIFT 5 4237 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1 4238 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6 4239 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1 4240 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7 4241 u8 flags2; 4242 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3 4243 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0 4244 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3 4245 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2 4246 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3 4247 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4 4248 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3 4249 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6 4250 u8 flags3; 4251 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3 4252 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0 4253 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3 4254 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2 4255 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3 4256 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4 4257 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3 4258 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6 4259 u8 flags4; 4260 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3 4261 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0 4262 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3 4263 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2 4264 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3 4265 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4 4266 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3 4267 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6 4268 u8 flags5; 4269 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3 4270 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0 4271 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3 4272 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2 4273 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3 4274 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4 4275 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3 4276 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6 4277 u8 flags6; 4278 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3 4279 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0 4280 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3 4281 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2 4282 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3 4283 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4 4284 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3 4285 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6 4286 u8 flags7; 4287 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3 4288 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0 4289 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3 4290 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2 4291 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 4292 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 4293 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 4294 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 4295 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 4296 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 4297 u8 flags8; 4298 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 4299 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 4300 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 4301 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 4302 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 4303 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 4304 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 4305 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 4306 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 4307 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 4308 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1 4309 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5 4310 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 4311 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 4312 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 4313 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 4314 u8 flags9; 4315 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 4316 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 4317 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 4318 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 4319 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 4320 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 4321 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 4322 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 4323 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 4324 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 4325 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 4326 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 4327 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1 4328 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6 4329 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1 4330 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7 4331 u8 flags10; 4332 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1 4333 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0 4334 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1 4335 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1 4336 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1 4337 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2 4338 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1 4339 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3 4340 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 4341 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 4342 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1 4343 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5 4344 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1 4345 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6 4346 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1 4347 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7 4348 u8 flags11; 4349 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1 4350 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0 4351 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1 4352 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1 4353 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1 4354 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2 4355 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 4356 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 4357 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 4358 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 4359 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 4360 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 4361 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 4362 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 4363 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 4364 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 4365 u8 flags12; 4366 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 4367 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 4368 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 4369 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 4370 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 4371 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 4372 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 4373 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 4374 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 4375 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 4376 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 4377 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 4378 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 4379 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 4380 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 4381 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 4382 u8 flags13; 4383 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 4384 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 4385 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 4386 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 4387 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 4388 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 4389 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 4390 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 4391 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 4392 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 4393 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 4394 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 4395 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 4396 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 4397 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 4398 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 4399 u8 flags14; 4400 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1 4401 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0 4402 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1 4403 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1 4404 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1 4405 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2 4406 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1 4407 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3 4408 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1 4409 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4 4410 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 4411 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 4412 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3 4413 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6 4414 u8 edpm_event_id; 4415 __le16 physical_q0; 4416 __le16 e5_reserved1; 4417 __le16 edpm_num_bds; 4418 __le16 tx_bd_cons; 4419 __le16 tx_bd_prod; 4420 __le16 updated_qm_pq_id; 4421 __le16 conn_dpi; 4422 u8 byte3; 4423 u8 byte4; 4424 u8 byte5; 4425 u8 byte6; 4426 __le32 reg0; 4427 __le32 reg1; 4428 __le32 reg2; 4429 __le32 reg3; 4430 __le32 reg4; 4431 }; 4432 4433 struct mstorm_eth_conn_ag_ctx { 4434 u8 byte0; 4435 u8 byte1; 4436 u8 flags0; 4437 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 4438 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 4439 #define MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 4440 #define MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 4441 #define MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 4442 #define MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2 4443 #define MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 4444 #define MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4 4445 #define MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 4446 #define MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 4447 u8 flags1; 4448 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 4449 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0 4450 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 4451 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1 4452 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 4453 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 4454 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 4455 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 4456 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 4457 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 4458 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 4459 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 4460 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 4461 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 4462 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 4463 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 4464 __le16 word0; 4465 __le16 word1; 4466 __le32 reg0; 4467 __le32 reg1; 4468 }; 4469 4470 struct xstorm_eth_hw_conn_ag_ctx { 4471 u8 reserved0; 4472 u8 state; 4473 u8 flags0; 4474 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 4475 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 4476 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1 4477 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1 4478 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1 4479 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2 4480 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 4481 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 4482 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1 4483 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4 4484 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1 4485 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5 4486 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1 4487 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6 4488 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1 4489 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7 4490 u8 flags1; 4491 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1 4492 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0 4493 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1 4494 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1 4495 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1 4496 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2 4497 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1 4498 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3 4499 #define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 4500 #define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_SHIFT 4 4501 #define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 4502 #define XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_SHIFT 5 4503 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 4504 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 4505 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 4506 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 4507 u8 flags2; 4508 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3 4509 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0 4510 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3 4511 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2 4512 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3 4513 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4 4514 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3 4515 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6 4516 u8 flags3; 4517 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3 4518 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0 4519 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3 4520 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2 4521 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3 4522 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4 4523 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3 4524 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6 4525 u8 flags4; 4526 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3 4527 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0 4528 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3 4529 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2 4530 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3 4531 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4 4532 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3 4533 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6 4534 u8 flags5; 4535 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3 4536 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0 4537 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3 4538 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2 4539 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3 4540 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4 4541 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3 4542 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6 4543 u8 flags6; 4544 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 4545 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 4546 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 4547 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 4548 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3 4549 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4 4550 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 4551 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 4552 u8 flags7; 4553 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 4554 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 4555 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3 4556 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2 4557 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3 4558 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4 4559 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1 4560 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6 4561 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1 4562 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7 4563 u8 flags8; 4564 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1 4565 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0 4566 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1 4567 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1 4568 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1 4569 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2 4570 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1 4571 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3 4572 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1 4573 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4 4574 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1 4575 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5 4576 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1 4577 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6 4578 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1 4579 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7 4580 u8 flags9; 4581 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1 4582 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0 4583 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1 4584 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1 4585 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1 4586 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2 4587 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1 4588 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3 4589 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1 4590 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4 4591 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1 4592 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5 4593 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 4594 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 4595 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 4596 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 4597 u8 flags10; 4598 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 4599 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 4600 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 4601 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 4602 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 4603 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 4604 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1 4605 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3 4606 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 4607 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 4608 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 4609 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 4610 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1 4611 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6 4612 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1 4613 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7 4614 u8 flags11; 4615 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1 4616 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0 4617 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1 4618 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1 4619 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 4620 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 4621 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1 4622 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3 4623 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1 4624 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4 4625 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1 4626 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5 4627 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 4628 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 4629 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1 4630 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7 4631 u8 flags12; 4632 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1 4633 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0 4634 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1 4635 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1 4636 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 4637 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 4638 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 4639 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 4640 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1 4641 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4 4642 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1 4643 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5 4644 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1 4645 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6 4646 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1 4647 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7 4648 u8 flags13; 4649 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1 4650 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0 4651 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1 4652 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1 4653 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 4654 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 4655 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 4656 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 4657 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 4658 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 4659 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 4660 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 4661 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 4662 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 4663 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 4664 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 4665 u8 flags14; 4666 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 4667 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 4668 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 4669 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 4670 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 4671 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 4672 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 4673 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 4674 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 4675 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 4676 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 4677 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 4678 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 4679 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 4680 u8 edpm_event_id; 4681 __le16 physical_q0; 4682 __le16 e5_reserved1; 4683 __le16 edpm_num_bds; 4684 __le16 tx_bd_cons; 4685 __le16 tx_bd_prod; 4686 __le16 updated_qm_pq_id; 4687 __le16 conn_dpi; 4688 }; 4689 4690 /* GFT CAM line struct with fields breakout */ 4691 struct gft_cam_line_mapped { 4692 __le32 camline; 4693 #define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1 4694 #define GFT_CAM_LINE_MAPPED_VALID_SHIFT 0 4695 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK 0x1 4696 #define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT 1 4697 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK 0x1 4698 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT 2 4699 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK 0xF 4700 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT 3 4701 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK 0xF 4702 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT 7 4703 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK 0xF 4704 #define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT 11 4705 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK 0x1 4706 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT 15 4707 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK 0x1 4708 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT 16 4709 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK 0xF 4710 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT 17 4711 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK 0xF 4712 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT 21 4713 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK 0xF 4714 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT 25 4715 #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK 0x7 4716 #define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT 29 4717 }; 4718 4719 4720 /* Used in gft_profile_key: Indication for ip version */ 4721 enum gft_profile_ip_version { 4722 GFT_PROFILE_IPV4 = 0, 4723 GFT_PROFILE_IPV6 = 1, 4724 MAX_GFT_PROFILE_IP_VERSION 4725 }; 4726 4727 /* Profile key stucr fot GFT logic in Prs */ 4728 struct gft_profile_key { 4729 __le16 profile_key; 4730 #define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1 4731 #define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0 4732 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1 4733 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT 1 4734 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF 4735 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2 4736 #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF 4737 #define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT 6 4738 #define GFT_PROFILE_KEY_PF_ID_MASK 0xF 4739 #define GFT_PROFILE_KEY_PF_ID_SHIFT 10 4740 #define GFT_PROFILE_KEY_RESERVED0_MASK 0x3 4741 #define GFT_PROFILE_KEY_RESERVED0_SHIFT 14 4742 }; 4743 4744 /* Used in gft_profile_key: Indication for tunnel type */ 4745 enum gft_profile_tunnel_type { 4746 GFT_PROFILE_NO_TUNNEL = 0, 4747 GFT_PROFILE_VXLAN_TUNNEL = 1, 4748 GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL = 2, 4749 GFT_PROFILE_GRE_IP_TUNNEL = 3, 4750 GFT_PROFILE_GENEVE_MAC_TUNNEL = 4, 4751 GFT_PROFILE_GENEVE_IP_TUNNEL = 5, 4752 MAX_GFT_PROFILE_TUNNEL_TYPE 4753 }; 4754 4755 /* Used in gft_profile_key: Indication for protocol type */ 4756 enum gft_profile_upper_protocol_type { 4757 GFT_PROFILE_ROCE_PROTOCOL = 0, 4758 GFT_PROFILE_RROCE_PROTOCOL = 1, 4759 GFT_PROFILE_FCOE_PROTOCOL = 2, 4760 GFT_PROFILE_ICMP_PROTOCOL = 3, 4761 GFT_PROFILE_ARP_PROTOCOL = 4, 4762 GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER = 5, 4763 GFT_PROFILE_USER_TCP_DST_PORT_1_INNER = 6, 4764 GFT_PROFILE_TCP_PROTOCOL = 7, 4765 GFT_PROFILE_USER_UDP_DST_PORT_1_INNER = 8, 4766 GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER = 9, 4767 GFT_PROFILE_UDP_PROTOCOL = 10, 4768 GFT_PROFILE_USER_IP_1_INNER = 11, 4769 GFT_PROFILE_USER_IP_2_OUTER = 12, 4770 GFT_PROFILE_USER_ETH_1_INNER = 13, 4771 GFT_PROFILE_USER_ETH_2_OUTER = 14, 4772 GFT_PROFILE_RAW = 15, 4773 MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE 4774 }; 4775 4776 /* GFT RAM line struct */ 4777 struct gft_ram_line { 4778 __le32 lo; 4779 #define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3 4780 #define GFT_RAM_LINE_VLAN_SELECT_SHIFT 0 4781 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK 0x1 4782 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT 2 4783 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK 0x1 4784 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT 3 4785 #define GFT_RAM_LINE_TUNNEL_TTL_MASK 0x1 4786 #define GFT_RAM_LINE_TUNNEL_TTL_SHIFT 4 4787 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK 0x1 4788 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT 5 4789 #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK 0x1 4790 #define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT 6 4791 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK 0x1 4792 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT 7 4793 #define GFT_RAM_LINE_TUNNEL_DSCP_MASK 0x1 4794 #define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT 8 4795 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK 0x1 4796 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT 9 4797 #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK 0x1 4798 #define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT 10 4799 #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK 0x1 4800 #define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT 11 4801 #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK 0x1 4802 #define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT 12 4803 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK 0x1 4804 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT 13 4805 #define GFT_RAM_LINE_TUNNEL_VLAN_MASK 0x1 4806 #define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT 14 4807 #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK 0x1 4808 #define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT 15 4809 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK 0x1 4810 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT 16 4811 #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK 0x1 4812 #define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT 17 4813 #define GFT_RAM_LINE_TTL_MASK 0x1 4814 #define GFT_RAM_LINE_TTL_SHIFT 18 4815 #define GFT_RAM_LINE_ETHERTYPE_MASK 0x1 4816 #define GFT_RAM_LINE_ETHERTYPE_SHIFT 19 4817 #define GFT_RAM_LINE_RESERVED0_MASK 0x1 4818 #define GFT_RAM_LINE_RESERVED0_SHIFT 20 4819 #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK 0x1 4820 #define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT 21 4821 #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK 0x1 4822 #define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT 22 4823 #define GFT_RAM_LINE_TCP_FLAG_RST_MASK 0x1 4824 #define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT 23 4825 #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK 0x1 4826 #define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT 24 4827 #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK 0x1 4828 #define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT 25 4829 #define GFT_RAM_LINE_TCP_FLAG_URG_MASK 0x1 4830 #define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT 26 4831 #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK 0x1 4832 #define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT 27 4833 #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK 0x1 4834 #define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT 28 4835 #define GFT_RAM_LINE_TCP_FLAG_NS_MASK 0x1 4836 #define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT 29 4837 #define GFT_RAM_LINE_DST_PORT_MASK 0x1 4838 #define GFT_RAM_LINE_DST_PORT_SHIFT 30 4839 #define GFT_RAM_LINE_SRC_PORT_MASK 0x1 4840 #define GFT_RAM_LINE_SRC_PORT_SHIFT 31 4841 __le32 hi; 4842 #define GFT_RAM_LINE_DSCP_MASK 0x1 4843 #define GFT_RAM_LINE_DSCP_SHIFT 0 4844 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK 0x1 4845 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT 1 4846 #define GFT_RAM_LINE_DST_IP_MASK 0x1 4847 #define GFT_RAM_LINE_DST_IP_SHIFT 2 4848 #define GFT_RAM_LINE_SRC_IP_MASK 0x1 4849 #define GFT_RAM_LINE_SRC_IP_SHIFT 3 4850 #define GFT_RAM_LINE_PRIORITY_MASK 0x1 4851 #define GFT_RAM_LINE_PRIORITY_SHIFT 4 4852 #define GFT_RAM_LINE_PROVIDER_VLAN_MASK 0x1 4853 #define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT 5 4854 #define GFT_RAM_LINE_VLAN_MASK 0x1 4855 #define GFT_RAM_LINE_VLAN_SHIFT 6 4856 #define GFT_RAM_LINE_DST_MAC_MASK 0x1 4857 #define GFT_RAM_LINE_DST_MAC_SHIFT 7 4858 #define GFT_RAM_LINE_SRC_MAC_MASK 0x1 4859 #define GFT_RAM_LINE_SRC_MAC_SHIFT 8 4860 #define GFT_RAM_LINE_TENANT_ID_MASK 0x1 4861 #define GFT_RAM_LINE_TENANT_ID_SHIFT 9 4862 #define GFT_RAM_LINE_RESERVED1_MASK 0x3FFFFF 4863 #define GFT_RAM_LINE_RESERVED1_SHIFT 10 4864 }; 4865 4866 /* Used in the first 2 bits for gft_ram_line: Indication for vlan mask */ 4867 enum gft_vlan_select { 4868 INNER_PROVIDER_VLAN = 0, 4869 INNER_VLAN = 1, 4870 OUTER_PROVIDER_VLAN = 2, 4871 OUTER_VLAN = 3, 4872 MAX_GFT_VLAN_SELECT 4873 }; 4874 4875 /* The rdma task context of Mstorm */ 4876 struct ystorm_rdma_task_st_ctx { 4877 struct regpair temp[4]; 4878 }; 4879 4880 struct ystorm_rdma_task_ag_ctx { 4881 u8 reserved; 4882 u8 byte1; 4883 __le16 msem_ctx_upd_seq; 4884 u8 flags0; 4885 #define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF 4886 #define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 4887 #define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 4888 #define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 4889 #define YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 4890 #define YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 4891 #define YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1 4892 #define YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6 4893 #define YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1 4894 #define YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT 7 4895 u8 flags1; 4896 #define YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 4897 #define YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 4898 #define YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 4899 #define YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 4900 #define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 4901 #define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4 4902 #define YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 4903 #define YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 4904 #define YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 4905 #define YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 4906 u8 flags2; 4907 #define YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 4908 #define YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 4909 #define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 4910 #define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 4911 #define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 4912 #define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 4913 #define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 4914 #define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 4915 #define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 4916 #define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 4917 #define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 4918 #define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 4919 #define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 4920 #define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 4921 #define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 4922 #define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 4923 u8 key; 4924 __le32 mw_cnt_or_qp_id; 4925 u8 ref_cnt_seq; 4926 u8 ctx_upd_seq; 4927 __le16 dif_flags; 4928 __le16 tx_ref_count; 4929 __le16 last_used_ltid; 4930 __le16 parent_mr_lo; 4931 __le16 parent_mr_hi; 4932 __le32 fbo_lo; 4933 __le32 fbo_hi; 4934 }; 4935 4936 struct mstorm_rdma_task_ag_ctx { 4937 u8 reserved; 4938 u8 byte1; 4939 __le16 icid; 4940 u8 flags0; 4941 #define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF 4942 #define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 4943 #define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 4944 #define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 4945 #define MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 4946 #define MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 4947 #define MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 4948 #define MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 4949 #define MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1 4950 #define MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT 7 4951 u8 flags1; 4952 #define MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 4953 #define MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 4954 #define MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 4955 #define MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 4956 #define MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 4957 #define MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4 4958 #define MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 4959 #define MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 4960 #define MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 4961 #define MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 4962 u8 flags2; 4963 #define MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 4964 #define MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0 4965 #define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 4966 #define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 4967 #define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 4968 #define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 4969 #define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 4970 #define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 4971 #define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 4972 #define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 4973 #define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 4974 #define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 4975 #define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 4976 #define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 4977 #define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 4978 #define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 4979 u8 key; 4980 __le32 mw_cnt_or_qp_id; 4981 u8 ref_cnt_seq; 4982 u8 ctx_upd_seq; 4983 __le16 dif_flags; 4984 __le16 tx_ref_count; 4985 __le16 last_used_ltid; 4986 __le16 parent_mr_lo; 4987 __le16 parent_mr_hi; 4988 __le32 fbo_lo; 4989 __le32 fbo_hi; 4990 }; 4991 4992 /* The roce task context of Mstorm */ 4993 struct mstorm_rdma_task_st_ctx { 4994 struct regpair temp[4]; 4995 }; 4996 4997 /* The roce task context of Ustorm */ 4998 struct ustorm_rdma_task_st_ctx { 4999 struct regpair temp[6]; 5000 }; 5001 5002 struct ustorm_rdma_task_ag_ctx { 5003 u8 reserved; 5004 u8 state; 5005 __le16 icid; 5006 u8 flags0; 5007 #define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF 5008 #define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 5009 #define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 5010 #define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 5011 #define USTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 5012 #define USTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 5013 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3 5014 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6 5015 u8 flags1; 5016 #define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3 5017 #define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0 5018 #define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3 5019 #define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2 5020 #define USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_MASK 0x3 5021 #define USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_SHIFT 4 5022 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 5023 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6 5024 u8 flags2; 5025 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1 5026 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0 5027 #define USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1 5028 #define USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1 5029 #define USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1 5030 #define USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2 5031 #define USTORM_RDMA_TASK_AG_CTX_RESERVED4_MASK 0x1 5032 #define USTORM_RDMA_TASK_AG_CTX_RESERVED4_SHIFT 3 5033 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 5034 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4 5035 #define USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 5036 #define USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5 5037 #define USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 5038 #define USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6 5039 #define USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 5040 #define USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7 5041 u8 flags3; 5042 #define USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_MASK 0x1 5043 #define USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_SHIFT 0 5044 #define USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 5045 #define USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1 5046 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_PROD_CONS_EN_MASK 0x1 5047 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_PROD_CONS_EN_SHIFT 2 5048 #define USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 5049 #define USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3 5050 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF 5051 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4 5052 __le32 dif_err_intervals; 5053 __le32 dif_error_1st_interval; 5054 __le32 dif_rxmit_cons; 5055 __le32 dif_rxmit_prod; 5056 __le32 sge_index; 5057 __le32 sq_cons; 5058 u8 byte2; 5059 u8 byte3; 5060 __le16 dif_write_cons; 5061 __le16 dif_write_prod; 5062 __le16 word3; 5063 __le32 dif_error_buffer_address_lo; 5064 __le32 dif_error_buffer_address_hi; 5065 }; 5066 5067 /* RDMA task context */ 5068 struct rdma_task_context { 5069 struct ystorm_rdma_task_st_ctx ystorm_st_context; 5070 struct ystorm_rdma_task_ag_ctx ystorm_ag_context; 5071 struct tdif_task_context tdif_context; 5072 struct mstorm_rdma_task_ag_ctx mstorm_ag_context; 5073 struct mstorm_rdma_task_st_ctx mstorm_st_context; 5074 struct rdif_task_context rdif_context; 5075 struct ustorm_rdma_task_st_ctx ustorm_st_context; 5076 struct regpair ustorm_st_padding[2]; 5077 struct ustorm_rdma_task_ag_ctx ustorm_ag_context; 5078 }; 5079 5080 /* rdma function init ramrod data */ 5081 struct rdma_close_func_ramrod_data { 5082 u8 cnq_start_offset; 5083 u8 num_cnqs; 5084 u8 vf_id; 5085 u8 vf_valid; 5086 u8 reserved[4]; 5087 }; 5088 5089 /* rdma function init CNQ parameters */ 5090 struct rdma_cnq_params { 5091 __le16 sb_num; 5092 u8 sb_index; 5093 u8 num_pbl_pages; 5094 __le32 reserved; 5095 struct regpair pbl_base_addr; 5096 __le16 queue_zone_num; 5097 u8 reserved1[6]; 5098 }; 5099 5100 /* rdma create cq ramrod data */ 5101 struct rdma_create_cq_ramrod_data { 5102 struct regpair cq_handle; 5103 struct regpair pbl_addr; 5104 __le32 max_cqes; 5105 __le16 pbl_num_pages; 5106 __le16 dpi; 5107 u8 is_two_level_pbl; 5108 u8 cnq_id; 5109 u8 pbl_log_page_size; 5110 u8 toggle_bit; 5111 __le16 int_timeout; 5112 u8 vf_id; 5113 u8 flags; 5114 #define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1 5115 #define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_SHIFT 0 5116 #define RDMA_CREATE_CQ_RAMROD_DATA_RESERVED1_MASK 0x7F 5117 #define RDMA_CREATE_CQ_RAMROD_DATA_RESERVED1_SHIFT 1 5118 }; 5119 5120 /* rdma deregister tid ramrod data */ 5121 struct rdma_deregister_tid_ramrod_data { 5122 __le32 itid; 5123 __le32 reserved; 5124 }; 5125 5126 /* rdma destroy cq output params */ 5127 struct rdma_destroy_cq_output_params { 5128 __le16 cnq_num; 5129 __le16 reserved0; 5130 __le32 reserved1; 5131 }; 5132 5133 /* rdma destroy cq ramrod data */ 5134 struct rdma_destroy_cq_ramrod_data { 5135 struct regpair output_params_addr; 5136 }; 5137 5138 /* RDMA slow path EQ cmd IDs */ 5139 enum rdma_event_opcode { 5140 RDMA_EVENT_UNUSED, 5141 RDMA_EVENT_FUNC_INIT, 5142 RDMA_EVENT_FUNC_CLOSE, 5143 RDMA_EVENT_REGISTER_MR, 5144 RDMA_EVENT_DEREGISTER_MR, 5145 RDMA_EVENT_CREATE_CQ, 5146 RDMA_EVENT_RESIZE_CQ, 5147 RDMA_EVENT_DESTROY_CQ, 5148 RDMA_EVENT_CREATE_SRQ, 5149 RDMA_EVENT_MODIFY_SRQ, 5150 RDMA_EVENT_DESTROY_SRQ, 5151 MAX_RDMA_EVENT_OPCODE 5152 }; 5153 5154 /* RDMA FW return code for slow path ramrods */ 5155 enum rdma_fw_return_code { 5156 RDMA_RETURN_OK = 0, 5157 RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR, 5158 RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR, 5159 RDMA_RETURN_RESIZE_CQ_ERR, 5160 RDMA_RETURN_NIG_DRAIN_REQ, 5161 RDMA_RETURN_GENERAL_ERR, 5162 MAX_RDMA_FW_RETURN_CODE 5163 }; 5164 5165 /* rdma function init header */ 5166 struct rdma_init_func_hdr { 5167 u8 cnq_start_offset; 5168 u8 num_cnqs; 5169 u8 cq_ring_mode; 5170 u8 vf_id; 5171 u8 vf_valid; 5172 u8 relaxed_ordering; 5173 __le16 first_reg_srq_id; 5174 __le32 reg_srq_base_addr; 5175 u8 searcher_mode; 5176 u8 pvrdma_mode; 5177 u8 max_num_ns_log; 5178 u8 reserved; 5179 }; 5180 5181 /* rdma function init ramrod data */ 5182 struct rdma_init_func_ramrod_data { 5183 struct rdma_init_func_hdr params_header; 5184 struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES]; 5185 }; 5186 5187 /* RDMA ramrod command IDs */ 5188 enum rdma_ramrod_cmd_id { 5189 RDMA_RAMROD_UNUSED, 5190 RDMA_RAMROD_FUNC_INIT, 5191 RDMA_RAMROD_FUNC_CLOSE, 5192 RDMA_RAMROD_REGISTER_MR, 5193 RDMA_RAMROD_DEREGISTER_MR, 5194 RDMA_RAMROD_CREATE_CQ, 5195 RDMA_RAMROD_RESIZE_CQ, 5196 RDMA_RAMROD_DESTROY_CQ, 5197 RDMA_RAMROD_CREATE_SRQ, 5198 RDMA_RAMROD_MODIFY_SRQ, 5199 RDMA_RAMROD_DESTROY_SRQ, 5200 MAX_RDMA_RAMROD_CMD_ID 5201 }; 5202 5203 /* rdma register tid ramrod data */ 5204 struct rdma_register_tid_ramrod_data { 5205 __le16 flags; 5206 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK 0x1F 5207 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT 0 5208 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1 5209 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT 5 5210 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1 5211 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT 6 5212 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1 5213 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT 7 5214 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1 5215 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT 8 5216 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1 5217 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT 9 5218 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1 5219 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT 10 5220 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1 5221 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT 11 5222 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1 5223 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT 12 5224 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1 5225 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT 13 5226 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK 0x3 5227 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_SHIFT 14 5228 u8 flags1; 5229 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK 0x1F 5230 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0 5231 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK 0x7 5232 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT 5 5233 u8 flags2; 5234 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1 5235 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT 0 5236 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK 0x1 5237 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT 1 5238 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK 0x3F 5239 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT 2 5240 u8 key; 5241 u8 length_hi; 5242 u8 vf_id; 5243 u8 vf_valid; 5244 __le16 pd; 5245 __le16 reserved2; 5246 __le32 length_lo; 5247 __le32 itid; 5248 __le32 reserved3; 5249 struct regpair va; 5250 struct regpair pbl_base; 5251 struct regpair dif_error_addr; 5252 __le32 reserved4[4]; 5253 }; 5254 5255 /* rdma resize cq output params */ 5256 struct rdma_resize_cq_output_params { 5257 __le32 old_cq_cons; 5258 __le32 old_cq_prod; 5259 }; 5260 5261 /* rdma resize cq ramrod data */ 5262 struct rdma_resize_cq_ramrod_data { 5263 u8 flags; 5264 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1 5265 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0 5266 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1 5267 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1 5268 #define RDMA_RESIZE_CQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1 5269 #define RDMA_RESIZE_CQ_RAMROD_DATA_VF_ID_VALID_SHIFT 2 5270 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x1F 5271 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 3 5272 u8 pbl_log_page_size; 5273 __le16 pbl_num_pages; 5274 __le32 max_cqes; 5275 struct regpair pbl_addr; 5276 struct regpair output_params_addr; 5277 u8 vf_id; 5278 u8 reserved1[7]; 5279 }; 5280 5281 /* The rdma SRQ context */ 5282 struct rdma_srq_context { 5283 struct regpair temp[8]; 5284 }; 5285 5286 /* rdma create qp requester ramrod data */ 5287 struct rdma_srq_create_ramrod_data { 5288 u8 flags; 5289 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_MASK 0x1 5290 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_SHIFT 0 5291 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1 5292 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 1 5293 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_MASK 0x3F 5294 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_SHIFT 2 5295 u8 reserved2; 5296 __le16 xrc_domain; 5297 __le32 xrc_srq_cq_cid; 5298 struct regpair pbl_base_addr; 5299 __le16 pages_in_srq_pbl; 5300 __le16 pd_id; 5301 struct rdma_srq_id srq_id; 5302 __le16 page_size; 5303 __le16 reserved3; 5304 __le32 reserved4; 5305 struct regpair producers_addr; 5306 }; 5307 5308 /* rdma create qp requester ramrod data */ 5309 struct rdma_srq_destroy_ramrod_data { 5310 struct rdma_srq_id srq_id; 5311 __le32 reserved; 5312 }; 5313 5314 /* rdma create qp requester ramrod data */ 5315 struct rdma_srq_modify_ramrod_data { 5316 struct rdma_srq_id srq_id; 5317 __le32 wqe_limit; 5318 }; 5319 5320 /* RDMA Tid type enumeration (for register_tid ramrod) */ 5321 enum rdma_tid_type { 5322 RDMA_TID_REGISTERED_MR, 5323 RDMA_TID_FMR, 5324 RDMA_TID_MW, 5325 MAX_RDMA_TID_TYPE 5326 }; 5327 5328 /* The rdma XRC SRQ context */ 5329 struct rdma_xrc_srq_context { 5330 struct regpair temp[9]; 5331 }; 5332 5333 struct tstorm_rdma_task_ag_ctx { 5334 u8 byte0; 5335 u8 byte1; 5336 __le16 word0; 5337 u8 flags0; 5338 #define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF 5339 #define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0 5340 #define TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1 5341 #define TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4 5342 #define TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 5343 #define TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 5344 #define TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 5345 #define TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 5346 #define TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 5347 #define TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 5348 u8 flags1; 5349 #define TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 5350 #define TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 5351 #define TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1 5352 #define TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1 5353 #define TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 5354 #define TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2 5355 #define TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 5356 #define TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4 5357 #define TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 5358 #define TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6 5359 u8 flags2; 5360 #define TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 5361 #define TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0 5362 #define TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3 5363 #define TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2 5364 #define TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3 5365 #define TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4 5366 #define TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3 5367 #define TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6 5368 u8 flags3; 5369 #define TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3 5370 #define TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0 5371 #define TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 5372 #define TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2 5373 #define TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 5374 #define TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3 5375 #define TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 5376 #define TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4 5377 #define TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 5378 #define TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5 5379 #define TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1 5380 #define TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6 5381 #define TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1 5382 #define TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7 5383 u8 flags4; 5384 #define TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1 5385 #define TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0 5386 #define TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1 5387 #define TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1 5388 #define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 5389 #define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2 5390 #define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 5391 #define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3 5392 #define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 5393 #define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4 5394 #define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 5395 #define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5 5396 #define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 5397 #define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6 5398 #define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 5399 #define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7 5400 u8 byte2; 5401 __le16 word1; 5402 __le32 reg0; 5403 u8 byte3; 5404 u8 byte4; 5405 __le16 word2; 5406 __le16 word3; 5407 __le16 word4; 5408 __le32 reg1; 5409 __le32 reg2; 5410 }; 5411 5412 struct ustorm_rdma_conn_ag_ctx { 5413 u8 reserved; 5414 u8 byte1; 5415 u8 flags0; 5416 #define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 5417 #define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 5418 #define USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_MASK 0x1 5419 #define USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_SHIFT 1 5420 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 5421 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2 5422 #define USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 5423 #define USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 5424 #define USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 5425 #define USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 5426 u8 flags1; 5427 #define USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 5428 #define USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0 5429 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 5430 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 5431 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 5432 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 5433 #define USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 5434 #define USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6 5435 u8 flags2; 5436 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 5437 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 5438 #define USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 5439 #define USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 5440 #define USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 5441 #define USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 5442 #define USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 5443 #define USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3 5444 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 5445 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 5446 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 5447 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 5448 #define USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 5449 #define USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6 5450 #define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 5451 #define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 5452 u8 flags3; 5453 #define USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1 5454 #define USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0 5455 #define USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 5456 #define USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 5457 #define USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 5458 #define USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 5459 #define USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 5460 #define USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 5461 #define USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 5462 #define USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 5463 #define USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 5464 #define USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 5465 #define USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 5466 #define USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 5467 #define USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 5468 #define USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 5469 u8 byte2; 5470 u8 nvmf_only; 5471 __le16 conn_dpi; 5472 __le16 word1; 5473 __le32 cq_cons; 5474 __le32 cq_se_prod; 5475 __le32 cq_prod; 5476 __le32 reg3; 5477 __le16 int_timeout; 5478 __le16 word3; 5479 }; 5480 5481 struct xstorm_roce_conn_ag_ctx { 5482 u8 reserved0; 5483 u8 state; 5484 u8 flags0; 5485 #define XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 5486 #define XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 5487 #define XSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 5488 #define XSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 5489 #define XSTORM_ROCE_CONN_AG_CTX_BIT2_MASK 0x1 5490 #define XSTORM_ROCE_CONN_AG_CTX_BIT2_SHIFT 2 5491 #define XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 5492 #define XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 5493 #define XSTORM_ROCE_CONN_AG_CTX_BIT4_MASK 0x1 5494 #define XSTORM_ROCE_CONN_AG_CTX_BIT4_SHIFT 4 5495 #define XSTORM_ROCE_CONN_AG_CTX_BIT5_MASK 0x1 5496 #define XSTORM_ROCE_CONN_AG_CTX_BIT5_SHIFT 5 5497 #define XSTORM_ROCE_CONN_AG_CTX_BIT6_MASK 0x1 5498 #define XSTORM_ROCE_CONN_AG_CTX_BIT6_SHIFT 6 5499 #define XSTORM_ROCE_CONN_AG_CTX_BIT7_MASK 0x1 5500 #define XSTORM_ROCE_CONN_AG_CTX_BIT7_SHIFT 7 5501 u8 flags1; 5502 #define XSTORM_ROCE_CONN_AG_CTX_BIT8_MASK 0x1 5503 #define XSTORM_ROCE_CONN_AG_CTX_BIT8_SHIFT 0 5504 #define XSTORM_ROCE_CONN_AG_CTX_BIT9_MASK 0x1 5505 #define XSTORM_ROCE_CONN_AG_CTX_BIT9_SHIFT 1 5506 #define XSTORM_ROCE_CONN_AG_CTX_BIT10_MASK 0x1 5507 #define XSTORM_ROCE_CONN_AG_CTX_BIT10_SHIFT 2 5508 #define XSTORM_ROCE_CONN_AG_CTX_BIT11_MASK 0x1 5509 #define XSTORM_ROCE_CONN_AG_CTX_BIT11_SHIFT 3 5510 #define XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1 5511 #define XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_SHIFT 4 5512 #define XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1 5513 #define XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_SHIFT 5 5514 #define XSTORM_ROCE_CONN_AG_CTX_BIT14_MASK 0x1 5515 #define XSTORM_ROCE_CONN_AG_CTX_BIT14_SHIFT 6 5516 #define XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 5517 #define XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 5518 u8 flags2; 5519 #define XSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3 5520 #define XSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 0 5521 #define XSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3 5522 #define XSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT 2 5523 #define XSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3 5524 #define XSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 4 5525 #define XSTORM_ROCE_CONN_AG_CTX_CF3_MASK 0x3 5526 #define XSTORM_ROCE_CONN_AG_CTX_CF3_SHIFT 6 5527 u8 flags3; 5528 #define XSTORM_ROCE_CONN_AG_CTX_CF4_MASK 0x3 5529 #define XSTORM_ROCE_CONN_AG_CTX_CF4_SHIFT 0 5530 #define XSTORM_ROCE_CONN_AG_CTX_CF5_MASK 0x3 5531 #define XSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT 2 5532 #define XSTORM_ROCE_CONN_AG_CTX_CF6_MASK 0x3 5533 #define XSTORM_ROCE_CONN_AG_CTX_CF6_SHIFT 4 5534 #define XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 5535 #define XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 5536 u8 flags4; 5537 #define XSTORM_ROCE_CONN_AG_CTX_CF8_MASK 0x3 5538 #define XSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT 0 5539 #define XSTORM_ROCE_CONN_AG_CTX_CF9_MASK 0x3 5540 #define XSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT 2 5541 #define XSTORM_ROCE_CONN_AG_CTX_CF10_MASK 0x3 5542 #define XSTORM_ROCE_CONN_AG_CTX_CF10_SHIFT 4 5543 #define XSTORM_ROCE_CONN_AG_CTX_CF11_MASK 0x3 5544 #define XSTORM_ROCE_CONN_AG_CTX_CF11_SHIFT 6 5545 u8 flags5; 5546 #define XSTORM_ROCE_CONN_AG_CTX_CF12_MASK 0x3 5547 #define XSTORM_ROCE_CONN_AG_CTX_CF12_SHIFT 0 5548 #define XSTORM_ROCE_CONN_AG_CTX_CF13_MASK 0x3 5549 #define XSTORM_ROCE_CONN_AG_CTX_CF13_SHIFT 2 5550 #define XSTORM_ROCE_CONN_AG_CTX_CF14_MASK 0x3 5551 #define XSTORM_ROCE_CONN_AG_CTX_CF14_SHIFT 4 5552 #define XSTORM_ROCE_CONN_AG_CTX_CF15_MASK 0x3 5553 #define XSTORM_ROCE_CONN_AG_CTX_CF15_SHIFT 6 5554 u8 flags6; 5555 #define XSTORM_ROCE_CONN_AG_CTX_CF16_MASK 0x3 5556 #define XSTORM_ROCE_CONN_AG_CTX_CF16_SHIFT 0 5557 #define XSTORM_ROCE_CONN_AG_CTX_CF17_MASK 0x3 5558 #define XSTORM_ROCE_CONN_AG_CTX_CF17_SHIFT 2 5559 #define XSTORM_ROCE_CONN_AG_CTX_CF18_MASK 0x3 5560 #define XSTORM_ROCE_CONN_AG_CTX_CF18_SHIFT 4 5561 #define XSTORM_ROCE_CONN_AG_CTX_CF19_MASK 0x3 5562 #define XSTORM_ROCE_CONN_AG_CTX_CF19_SHIFT 6 5563 u8 flags7; 5564 #define XSTORM_ROCE_CONN_AG_CTX_CF20_MASK 0x3 5565 #define XSTORM_ROCE_CONN_AG_CTX_CF20_SHIFT 0 5566 #define XSTORM_ROCE_CONN_AG_CTX_CF21_MASK 0x3 5567 #define XSTORM_ROCE_CONN_AG_CTX_CF21_SHIFT 2 5568 #define XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 5569 #define XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 5570 #define XSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1 5571 #define XSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 6 5572 #define XSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1 5573 #define XSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT 7 5574 u8 flags8; 5575 #define XSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 5576 #define XSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 0 5577 #define XSTORM_ROCE_CONN_AG_CTX_CF3EN_MASK 0x1 5578 #define XSTORM_ROCE_CONN_AG_CTX_CF3EN_SHIFT 1 5579 #define XSTORM_ROCE_CONN_AG_CTX_CF4EN_MASK 0x1 5580 #define XSTORM_ROCE_CONN_AG_CTX_CF4EN_SHIFT 2 5581 #define XSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK 0x1 5582 #define XSTORM_ROCE_CONN_AG_CTX_CF5EN_SHIFT 3 5583 #define XSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1 5584 #define XSTORM_ROCE_CONN_AG_CTX_CF6EN_SHIFT 4 5585 #define XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 5586 #define XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 5587 #define XSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK 0x1 5588 #define XSTORM_ROCE_CONN_AG_CTX_CF8EN_SHIFT 6 5589 #define XSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK 0x1 5590 #define XSTORM_ROCE_CONN_AG_CTX_CF9EN_SHIFT 7 5591 u8 flags9; 5592 #define XSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1 5593 #define XSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT 0 5594 #define XSTORM_ROCE_CONN_AG_CTX_CF11EN_MASK 0x1 5595 #define XSTORM_ROCE_CONN_AG_CTX_CF11EN_SHIFT 1 5596 #define XSTORM_ROCE_CONN_AG_CTX_CF12EN_MASK 0x1 5597 #define XSTORM_ROCE_CONN_AG_CTX_CF12EN_SHIFT 2 5598 #define XSTORM_ROCE_CONN_AG_CTX_CF13EN_MASK 0x1 5599 #define XSTORM_ROCE_CONN_AG_CTX_CF13EN_SHIFT 3 5600 #define XSTORM_ROCE_CONN_AG_CTX_CF14EN_MASK 0x1 5601 #define XSTORM_ROCE_CONN_AG_CTX_CF14EN_SHIFT 4 5602 #define XSTORM_ROCE_CONN_AG_CTX_CF15EN_MASK 0x1 5603 #define XSTORM_ROCE_CONN_AG_CTX_CF15EN_SHIFT 5 5604 #define XSTORM_ROCE_CONN_AG_CTX_CF16EN_MASK 0x1 5605 #define XSTORM_ROCE_CONN_AG_CTX_CF16EN_SHIFT 6 5606 #define XSTORM_ROCE_CONN_AG_CTX_CF17EN_MASK 0x1 5607 #define XSTORM_ROCE_CONN_AG_CTX_CF17EN_SHIFT 7 5608 u8 flags10; 5609 #define XSTORM_ROCE_CONN_AG_CTX_CF18EN_MASK 0x1 5610 #define XSTORM_ROCE_CONN_AG_CTX_CF18EN_SHIFT 0 5611 #define XSTORM_ROCE_CONN_AG_CTX_CF19EN_MASK 0x1 5612 #define XSTORM_ROCE_CONN_AG_CTX_CF19EN_SHIFT 1 5613 #define XSTORM_ROCE_CONN_AG_CTX_CF20EN_MASK 0x1 5614 #define XSTORM_ROCE_CONN_AG_CTX_CF20EN_SHIFT 2 5615 #define XSTORM_ROCE_CONN_AG_CTX_CF21EN_MASK 0x1 5616 #define XSTORM_ROCE_CONN_AG_CTX_CF21EN_SHIFT 3 5617 #define XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 5618 #define XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 5619 #define XSTORM_ROCE_CONN_AG_CTX_CF23EN_MASK 0x1 5620 #define XSTORM_ROCE_CONN_AG_CTX_CF23EN_SHIFT 5 5621 #define XSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1 5622 #define XSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 6 5623 #define XSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1 5624 #define XSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 7 5625 u8 flags11; 5626 #define XSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 5627 #define XSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 0 5628 #define XSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1 5629 #define XSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 1 5630 #define XSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 5631 #define XSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 2 5632 #define XSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1 5633 #define XSTORM_ROCE_CONN_AG_CTX_RULE5EN_SHIFT 3 5634 #define XSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1 5635 #define XSTORM_ROCE_CONN_AG_CTX_RULE6EN_SHIFT 4 5636 #define XSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1 5637 #define XSTORM_ROCE_CONN_AG_CTX_RULE7EN_SHIFT 5 5638 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 5639 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 5640 #define XSTORM_ROCE_CONN_AG_CTX_RULE9EN_MASK 0x1 5641 #define XSTORM_ROCE_CONN_AG_CTX_RULE9EN_SHIFT 7 5642 u8 flags12; 5643 #define XSTORM_ROCE_CONN_AG_CTX_RULE10EN_MASK 0x1 5644 #define XSTORM_ROCE_CONN_AG_CTX_RULE10EN_SHIFT 0 5645 #define XSTORM_ROCE_CONN_AG_CTX_RULE11EN_MASK 0x1 5646 #define XSTORM_ROCE_CONN_AG_CTX_RULE11EN_SHIFT 1 5647 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 5648 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 5649 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 5650 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 5651 #define XSTORM_ROCE_CONN_AG_CTX_RULE14EN_MASK 0x1 5652 #define XSTORM_ROCE_CONN_AG_CTX_RULE14EN_SHIFT 4 5653 #define XSTORM_ROCE_CONN_AG_CTX_RULE15EN_MASK 0x1 5654 #define XSTORM_ROCE_CONN_AG_CTX_RULE15EN_SHIFT 5 5655 #define XSTORM_ROCE_CONN_AG_CTX_RULE16EN_MASK 0x1 5656 #define XSTORM_ROCE_CONN_AG_CTX_RULE16EN_SHIFT 6 5657 #define XSTORM_ROCE_CONN_AG_CTX_RULE17EN_MASK 0x1 5658 #define XSTORM_ROCE_CONN_AG_CTX_RULE17EN_SHIFT 7 5659 u8 flags13; 5660 #define XSTORM_ROCE_CONN_AG_CTX_RULE18EN_MASK 0x1 5661 #define XSTORM_ROCE_CONN_AG_CTX_RULE18EN_SHIFT 0 5662 #define XSTORM_ROCE_CONN_AG_CTX_RULE19EN_MASK 0x1 5663 #define XSTORM_ROCE_CONN_AG_CTX_RULE19EN_SHIFT 1 5664 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 5665 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 5666 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 5667 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 5668 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 5669 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 5670 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 5671 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 5672 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 5673 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 5674 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 5675 #define XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 5676 u8 flags14; 5677 #define XSTORM_ROCE_CONN_AG_CTX_MIGRATION_MASK 0x1 5678 #define XSTORM_ROCE_CONN_AG_CTX_MIGRATION_SHIFT 0 5679 #define XSTORM_ROCE_CONN_AG_CTX_BIT17_MASK 0x1 5680 #define XSTORM_ROCE_CONN_AG_CTX_BIT17_SHIFT 1 5681 #define XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 5682 #define XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 5683 #define XSTORM_ROCE_CONN_AG_CTX_RESERVED_MASK 0x1 5684 #define XSTORM_ROCE_CONN_AG_CTX_RESERVED_SHIFT 4 5685 #define XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 5686 #define XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 5687 #define XSTORM_ROCE_CONN_AG_CTX_CF23_MASK 0x3 5688 #define XSTORM_ROCE_CONN_AG_CTX_CF23_SHIFT 6 5689 u8 byte2; 5690 __le16 physical_q0; 5691 __le16 word1; 5692 __le16 word2; 5693 __le16 word3; 5694 __le16 word4; 5695 __le16 word5; 5696 __le16 conn_dpi; 5697 u8 byte3; 5698 u8 byte4; 5699 u8 byte5; 5700 u8 byte6; 5701 __le32 reg0; 5702 __le32 reg1; 5703 __le32 reg2; 5704 __le32 snd_nxt_psn; 5705 __le32 reg4; 5706 __le32 reg5; 5707 __le32 reg6; 5708 }; 5709 5710 struct tstorm_roce_conn_ag_ctx { 5711 u8 reserved0; 5712 u8 byte1; 5713 u8 flags0; 5714 #define TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 5715 #define TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 5716 #define TSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 5717 #define TSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 5718 #define TSTORM_ROCE_CONN_AG_CTX_BIT2_MASK 0x1 5719 #define TSTORM_ROCE_CONN_AG_CTX_BIT2_SHIFT 2 5720 #define TSTORM_ROCE_CONN_AG_CTX_BIT3_MASK 0x1 5721 #define TSTORM_ROCE_CONN_AG_CTX_BIT3_SHIFT 3 5722 #define TSTORM_ROCE_CONN_AG_CTX_BIT4_MASK 0x1 5723 #define TSTORM_ROCE_CONN_AG_CTX_BIT4_SHIFT 4 5724 #define TSTORM_ROCE_CONN_AG_CTX_BIT5_MASK 0x1 5725 #define TSTORM_ROCE_CONN_AG_CTX_BIT5_SHIFT 5 5726 #define TSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3 5727 #define TSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 6 5728 u8 flags1; 5729 #define TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 5730 #define TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 5731 #define TSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3 5732 #define TSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 2 5733 #define TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 5734 #define TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 5735 #define TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 5736 #define TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 5737 u8 flags2; 5738 #define TSTORM_ROCE_CONN_AG_CTX_CF5_MASK 0x3 5739 #define TSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT 0 5740 #define TSTORM_ROCE_CONN_AG_CTX_CF6_MASK 0x3 5741 #define TSTORM_ROCE_CONN_AG_CTX_CF6_SHIFT 2 5742 #define TSTORM_ROCE_CONN_AG_CTX_CF7_MASK 0x3 5743 #define TSTORM_ROCE_CONN_AG_CTX_CF7_SHIFT 4 5744 #define TSTORM_ROCE_CONN_AG_CTX_CF8_MASK 0x3 5745 #define TSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT 6 5746 u8 flags3; 5747 #define TSTORM_ROCE_CONN_AG_CTX_CF9_MASK 0x3 5748 #define TSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT 0 5749 #define TSTORM_ROCE_CONN_AG_CTX_CF10_MASK 0x3 5750 #define TSTORM_ROCE_CONN_AG_CTX_CF10_SHIFT 2 5751 #define TSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1 5752 #define TSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 4 5753 #define TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 5754 #define TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 5 5755 #define TSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 5756 #define TSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 6 5757 #define TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 5758 #define TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 5759 u8 flags4; 5760 #define TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 5761 #define TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 5762 #define TSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK 0x1 5763 #define TSTORM_ROCE_CONN_AG_CTX_CF5EN_SHIFT 1 5764 #define TSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK 0x1 5765 #define TSTORM_ROCE_CONN_AG_CTX_CF6EN_SHIFT 2 5766 #define TSTORM_ROCE_CONN_AG_CTX_CF7EN_MASK 0x1 5767 #define TSTORM_ROCE_CONN_AG_CTX_CF7EN_SHIFT 3 5768 #define TSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK 0x1 5769 #define TSTORM_ROCE_CONN_AG_CTX_CF8EN_SHIFT 4 5770 #define TSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK 0x1 5771 #define TSTORM_ROCE_CONN_AG_CTX_CF9EN_SHIFT 5 5772 #define TSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK 0x1 5773 #define TSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT 6 5774 #define TSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1 5775 #define TSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 7 5776 u8 flags5; 5777 #define TSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1 5778 #define TSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 0 5779 #define TSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 5780 #define TSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 1 5781 #define TSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1 5782 #define TSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 2 5783 #define TSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 5784 #define TSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 3 5785 #define TSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK 0x1 5786 #define TSTORM_ROCE_CONN_AG_CTX_RULE5EN_SHIFT 4 5787 #define TSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK 0x1 5788 #define TSTORM_ROCE_CONN_AG_CTX_RULE6EN_SHIFT 5 5789 #define TSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK 0x1 5790 #define TSTORM_ROCE_CONN_AG_CTX_RULE7EN_SHIFT 6 5791 #define TSTORM_ROCE_CONN_AG_CTX_RULE8EN_MASK 0x1 5792 #define TSTORM_ROCE_CONN_AG_CTX_RULE8EN_SHIFT 7 5793 __le32 reg0; 5794 __le32 reg1; 5795 __le32 reg2; 5796 __le32 reg3; 5797 __le32 reg4; 5798 __le32 reg5; 5799 __le32 reg6; 5800 __le32 reg7; 5801 __le32 reg8; 5802 u8 byte2; 5803 u8 byte3; 5804 __le16 word0; 5805 u8 byte4; 5806 u8 byte5; 5807 __le16 word1; 5808 __le16 word2; 5809 __le16 word3; 5810 __le32 reg9; 5811 __le32 reg10; 5812 }; 5813 5814 /* The roce storm context of Ystorm */ 5815 struct ystorm_roce_conn_st_ctx { 5816 struct regpair temp[2]; 5817 }; 5818 5819 /* The roce storm context of Mstorm */ 5820 struct pstorm_roce_conn_st_ctx { 5821 struct regpair temp[16]; 5822 }; 5823 5824 /* The roce storm context of Xstorm */ 5825 struct xstorm_roce_conn_st_ctx { 5826 struct regpair temp[24]; 5827 }; 5828 5829 /* The roce storm context of Tstorm */ 5830 struct tstorm_roce_conn_st_ctx { 5831 struct regpair temp[30]; 5832 }; 5833 5834 /* The roce storm context of Mstorm */ 5835 struct mstorm_roce_conn_st_ctx { 5836 struct regpair temp[6]; 5837 }; 5838 5839 /* The roce storm context of Ustorm */ 5840 struct ustorm_roce_conn_st_ctx { 5841 struct regpair temp[14]; 5842 }; 5843 5844 /* roce connection context */ 5845 struct roce_conn_context { 5846 struct ystorm_roce_conn_st_ctx ystorm_st_context; 5847 struct regpair ystorm_st_padding[2]; 5848 struct pstorm_roce_conn_st_ctx pstorm_st_context; 5849 struct xstorm_roce_conn_st_ctx xstorm_st_context; 5850 struct xstorm_roce_conn_ag_ctx xstorm_ag_context; 5851 struct tstorm_roce_conn_ag_ctx tstorm_ag_context; 5852 struct timers_context timer_context; 5853 struct ustorm_rdma_conn_ag_ctx ustorm_ag_context; 5854 struct tstorm_roce_conn_st_ctx tstorm_st_context; 5855 struct regpair tstorm_st_padding[2]; 5856 struct mstorm_roce_conn_st_ctx mstorm_st_context; 5857 struct regpair mstorm_st_padding[2]; 5858 struct ustorm_roce_conn_st_ctx ustorm_st_context; 5859 struct regpair ustorm_st_padding[2]; 5860 }; 5861 5862 /* roce cqes statistics */ 5863 struct roce_cqe_stats { 5864 __le32 req_cqe_error; 5865 __le32 req_remote_access_errors; 5866 __le32 req_remote_invalid_request; 5867 __le32 resp_cqe_error; 5868 __le32 resp_local_length_error; 5869 __le32 reserved; 5870 }; 5871 5872 /* roce create qp requester ramrod data */ 5873 struct roce_create_qp_req_ramrod_data { 5874 __le16 flags; 5875 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 5876 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0 5877 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1 5878 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 2 5879 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1 5880 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT 3 5881 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7 5882 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT 4 5883 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_MASK 0x1 5884 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_SHIFT 7 5885 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF 5886 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 8 5887 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF 5888 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 12 5889 u8 max_ord; 5890 u8 traffic_class; 5891 u8 hop_limit; 5892 u8 orq_num_pages; 5893 __le16 p_key; 5894 __le32 flow_label; 5895 __le32 dst_qp_id; 5896 __le32 ack_timeout_val; 5897 __le32 initial_psn; 5898 __le16 mtu; 5899 __le16 pd; 5900 __le16 sq_num_pages; 5901 __le16 low_latency_phy_queue; 5902 struct regpair sq_pbl_addr; 5903 struct regpair orq_pbl_addr; 5904 __le16 local_mac_addr[3]; 5905 __le16 remote_mac_addr[3]; 5906 __le16 vlan_id; 5907 __le16 udp_src_port; 5908 __le32 src_gid[4]; 5909 __le32 dst_gid[4]; 5910 __le32 cq_cid; 5911 struct regpair qp_handle_for_cqe; 5912 struct regpair qp_handle_for_async; 5913 u8 stats_counter_id; 5914 u8 vf_id; 5915 u8 vport_id; 5916 u8 flags2; 5917 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_MASK 0x1 5918 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_SHIFT 0 5919 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_VF_ID_VALID_MASK 0x1 5920 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_VF_ID_VALID_SHIFT 1 5921 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK 0x3F 5922 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT 2 5923 u8 name_space; 5924 u8 reserved3[3]; 5925 __le16 regular_latency_phy_queue; 5926 __le16 dpi; 5927 }; 5928 5929 /* roce create qp responder ramrod data */ 5930 struct roce_create_qp_resp_ramrod_data { 5931 __le32 flags; 5932 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 5933 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0 5934 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 5935 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2 5936 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 5937 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3 5938 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 5939 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 4 5940 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1 5941 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT 5 5942 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1 5943 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT 6 5944 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1 5945 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 7 5946 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK 0x7 5947 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT 8 5948 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F 5949 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 11 5950 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_MASK 0x1 5951 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_SHIFT 16 5952 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_VF_ID_VALID_MASK 0x1 5953 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_VF_ID_VALID_SHIFT 17 5954 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_MASK 0x3FFF 5955 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_SHIFT 18 5956 __le16 xrc_domain; 5957 u8 max_ird; 5958 u8 traffic_class; 5959 u8 hop_limit; 5960 u8 irq_num_pages; 5961 __le16 p_key; 5962 __le32 flow_label; 5963 __le32 dst_qp_id; 5964 u8 stats_counter_id; 5965 u8 reserved1; 5966 __le16 mtu; 5967 __le32 initial_psn; 5968 __le16 pd; 5969 __le16 rq_num_pages; 5970 struct rdma_srq_id srq_id; 5971 struct regpair rq_pbl_addr; 5972 struct regpair irq_pbl_addr; 5973 __le16 local_mac_addr[3]; 5974 __le16 remote_mac_addr[3]; 5975 __le16 vlan_id; 5976 __le16 udp_src_port; 5977 __le32 src_gid[4]; 5978 __le32 dst_gid[4]; 5979 struct regpair qp_handle_for_cqe; 5980 struct regpair qp_handle_for_async; 5981 __le16 low_latency_phy_queue; 5982 u8 vf_id; 5983 u8 vport_id; 5984 __le32 cq_cid; 5985 __le16 regular_latency_phy_queue; 5986 __le16 dpi; 5987 __le32 src_qp_id; 5988 u8 name_space; 5989 u8 reserved3[3]; 5990 }; 5991 5992 /* roce DCQCN received statistics */ 5993 struct roce_dcqcn_received_stats { 5994 struct regpair ecn_pkt_rcv; 5995 struct regpair cnp_pkt_rcv; 5996 }; 5997 5998 /* roce DCQCN sent statistics */ 5999 struct roce_dcqcn_sent_stats { 6000 struct regpair cnp_pkt_sent; 6001 }; 6002 6003 /* RoCE destroy qp requester output params */ 6004 struct roce_destroy_qp_req_output_params { 6005 __le32 cq_prod; 6006 __le32 reserved; 6007 }; 6008 6009 /* RoCE destroy qp requester ramrod data */ 6010 struct roce_destroy_qp_req_ramrod_data { 6011 struct regpair output_params_addr; 6012 }; 6013 6014 /* RoCE destroy qp responder output params */ 6015 struct roce_destroy_qp_resp_output_params { 6016 __le32 cq_prod; 6017 __le32 reserved; 6018 }; 6019 6020 /* RoCE destroy qp responder ramrod data */ 6021 struct roce_destroy_qp_resp_ramrod_data { 6022 struct regpair output_params_addr; 6023 __le32 src_qp_id; 6024 __le32 reserved; 6025 }; 6026 6027 /* roce error statistics */ 6028 struct roce_error_stats { 6029 __le32 resp_remote_access_errors; 6030 __le32 reserved; 6031 }; 6032 6033 /* roce special events statistics */ 6034 struct roce_events_stats { 6035 __le32 silent_drops; 6036 __le32 rnr_naks_sent; 6037 __le32 retransmit_count; 6038 __le32 icrc_error_count; 6039 __le32 implied_nak_seq_err; 6040 __le32 duplicate_request; 6041 __le32 local_ack_timeout_err; 6042 __le32 out_of_sequence; 6043 __le32 packet_seq_err; 6044 __le32 rnr_nak_retry_err; 6045 }; 6046 6047 /* roce slow path EQ cmd IDs */ 6048 enum roce_event_opcode { 6049 ROCE_EVENT_CREATE_QP = 11, 6050 ROCE_EVENT_MODIFY_QP, 6051 ROCE_EVENT_QUERY_QP, 6052 ROCE_EVENT_DESTROY_QP, 6053 ROCE_EVENT_CREATE_UD_QP, 6054 ROCE_EVENT_DESTROY_UD_QP, 6055 ROCE_EVENT_FUNC_UPDATE, 6056 MAX_ROCE_EVENT_OPCODE 6057 }; 6058 6059 /* roce func init ramrod data */ 6060 struct roce_init_func_params { 6061 u8 ll2_queue_id; 6062 u8 cnp_vlan_priority; 6063 u8 cnp_dscp; 6064 u8 flags; 6065 #define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_MASK 0x1 6066 #define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_SHIFT 0 6067 #define ROCE_INIT_FUNC_PARAMS_DCQCN_RP_EN_MASK 0x1 6068 #define ROCE_INIT_FUNC_PARAMS_DCQCN_RP_EN_SHIFT 1 6069 #define ROCE_INIT_FUNC_PARAMS_RESERVED0_MASK 0x3F 6070 #define ROCE_INIT_FUNC_PARAMS_RESERVED0_SHIFT 2 6071 __le32 cnp_send_timeout; 6072 __le16 rl_offset; 6073 u8 rl_count_log; 6074 u8 reserved1[5]; 6075 }; 6076 6077 /* roce func init ramrod data */ 6078 struct roce_init_func_ramrod_data { 6079 struct rdma_init_func_ramrod_data rdma; 6080 struct roce_init_func_params roce; 6081 }; 6082 6083 /* roce modify qp requester ramrod data */ 6084 struct roce_modify_qp_req_ramrod_data { 6085 __le16 flags; 6086 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1 6087 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0 6088 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK 0x1 6089 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT 1 6090 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK 0x1 6091 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT 2 6092 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK 0x1 6093 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT 3 6094 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1 6095 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 4 6096 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK 0x1 6097 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT 5 6098 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK 0x1 6099 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT 6 6100 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK 0x1 6101 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT 7 6102 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK 0x1 6103 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT 8 6104 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK 0x1 6105 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT 9 6106 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7 6107 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT 10 6108 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1 6109 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT 13 6110 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x3 6111 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT 14 6112 u8 fields; 6113 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF 6114 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 0 6115 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF 6116 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 4 6117 u8 max_ord; 6118 u8 traffic_class; 6119 u8 hop_limit; 6120 __le16 p_key; 6121 __le32 flow_label; 6122 __le32 ack_timeout_val; 6123 __le16 mtu; 6124 __le16 reserved2; 6125 __le32 reserved3[2]; 6126 __le16 low_latency_phy_queue; 6127 __le16 regular_latency_phy_queue; 6128 __le32 src_gid[4]; 6129 __le32 dst_gid[4]; 6130 }; 6131 6132 /* roce modify qp responder ramrod data */ 6133 struct roce_modify_qp_resp_ramrod_data { 6134 __le16 flags; 6135 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1 6136 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0 6137 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 6138 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 1 6139 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 6140 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 2 6141 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 6142 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 3 6143 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK 0x1 6144 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT 4 6145 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1 6146 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 5 6147 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK 0x1 6148 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT 6 6149 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK 0x1 6150 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT 7 6151 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK 0x1 6152 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8 6153 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1 6154 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 9 6155 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1 6156 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT 10 6157 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0x1F 6158 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT 11 6159 u8 fields; 6160 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK 0x7 6161 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT 0 6162 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F 6163 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 3 6164 u8 max_ird; 6165 u8 traffic_class; 6166 u8 hop_limit; 6167 __le16 p_key; 6168 __le32 flow_label; 6169 __le16 mtu; 6170 __le16 low_latency_phy_queue; 6171 __le16 regular_latency_phy_queue; 6172 u8 reserved2[6]; 6173 __le32 src_gid[4]; 6174 __le32 dst_gid[4]; 6175 }; 6176 6177 /* RoCE query qp requester output params */ 6178 struct roce_query_qp_req_output_params { 6179 __le32 psn; 6180 __le32 flags; 6181 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1 6182 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0 6183 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK 0x1 6184 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT 1 6185 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x3FFFFFFF 6186 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT 2 6187 }; 6188 6189 /* RoCE query qp requester ramrod data */ 6190 struct roce_query_qp_req_ramrod_data { 6191 struct regpair output_params_addr; 6192 }; 6193 6194 /* RoCE query qp responder output params */ 6195 struct roce_query_qp_resp_output_params { 6196 __le32 psn; 6197 __le32 flags; 6198 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1 6199 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0 6200 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF 6201 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1 6202 }; 6203 6204 /* RoCE query qp responder ramrod data */ 6205 struct roce_query_qp_resp_ramrod_data { 6206 struct regpair output_params_addr; 6207 }; 6208 6209 /* ROCE ramrod command IDs */ 6210 enum roce_ramrod_cmd_id { 6211 ROCE_RAMROD_CREATE_QP = 11, 6212 ROCE_RAMROD_MODIFY_QP, 6213 ROCE_RAMROD_QUERY_QP, 6214 ROCE_RAMROD_DESTROY_QP, 6215 ROCE_RAMROD_CREATE_UD_QP, 6216 ROCE_RAMROD_DESTROY_UD_QP, 6217 ROCE_RAMROD_FUNC_UPDATE, 6218 MAX_ROCE_RAMROD_CMD_ID 6219 }; 6220 6221 /* RoCE func init ramrod data */ 6222 struct roce_update_func_params { 6223 u8 cnp_vlan_priority; 6224 u8 cnp_dscp; 6225 __le16 flags; 6226 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_MASK 0x1 6227 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_SHIFT 0 6228 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_RP_EN_MASK 0x1 6229 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_RP_EN_SHIFT 1 6230 #define ROCE_UPDATE_FUNC_PARAMS_RESERVED0_MASK 0x3FFF 6231 #define ROCE_UPDATE_FUNC_PARAMS_RESERVED0_SHIFT 2 6232 __le32 cnp_send_timeout; 6233 }; 6234 6235 struct xstorm_roce_conn_ag_ctx_dq_ext_ld_part { 6236 u8 reserved0; 6237 u8 state; 6238 u8 flags0; 6239 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 6240 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 6241 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1 6242 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1 6243 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1 6244 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2 6245 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 6246 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 6247 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1 6248 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4 6249 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1 6250 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5 6251 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1 6252 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6 6253 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1 6254 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7 6255 u8 flags1; 6256 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1 6257 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0 6258 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1 6259 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1 6260 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1 6261 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2 6262 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 6263 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 6264 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_MASK 0x1 6265 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_SHIFT 4 6266 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_MASK 0x1 6267 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_SHIFT 5 6268 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1 6269 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6 6270 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1 6271 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7 6272 u8 flags2; 6273 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3 6274 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0 6275 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3 6276 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2 6277 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3 6278 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4 6279 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3 6280 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6 6281 u8 flags3; 6282 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3 6283 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0 6284 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3 6285 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2 6286 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3 6287 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4 6288 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3 6289 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6 6290 u8 flags4; 6291 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3 6292 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0 6293 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3 6294 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2 6295 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3 6296 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4 6297 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3 6298 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6 6299 u8 flags5; 6300 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3 6301 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0 6302 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3 6303 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2 6304 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3 6305 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4 6306 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3 6307 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6 6308 u8 flags6; 6309 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3 6310 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0 6311 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3 6312 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2 6313 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3 6314 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4 6315 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3 6316 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6 6317 u8 flags7; 6318 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3 6319 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0 6320 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3 6321 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2 6322 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 6323 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 6324 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 6325 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 6326 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 6327 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 6328 u8 flags8; 6329 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 6330 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 6331 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 6332 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 6333 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 6334 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 6335 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 6336 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 6337 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 6338 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 6339 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1 6340 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5 6341 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 6342 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 6343 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 6344 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 6345 u8 flags9; 6346 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 6347 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 6348 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 6349 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 6350 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 6351 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 6352 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 6353 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 6354 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 6355 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 6356 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 6357 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 6358 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1 6359 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6 6360 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1 6361 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7 6362 u8 flags10; 6363 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1 6364 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0 6365 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1 6366 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1 6367 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1 6368 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2 6369 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1 6370 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3 6371 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 6372 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 6373 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1 6374 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5 6375 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1 6376 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6 6377 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1 6378 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7 6379 u8 flags11; 6380 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1 6381 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0 6382 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1 6383 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1 6384 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1 6385 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2 6386 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 6387 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 6388 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 6389 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 6390 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 6391 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 6392 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 6393 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 6394 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 6395 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 6396 u8 flags12; 6397 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 6398 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 6399 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 6400 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 6401 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 6402 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 6403 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 6404 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 6405 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 6406 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 6407 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 6408 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 6409 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 6410 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 6411 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 6412 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 6413 u8 flags13; 6414 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 6415 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 6416 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 6417 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 6418 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 6419 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 6420 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 6421 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 6422 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 6423 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 6424 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 6425 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 6426 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 6427 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 6428 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 6429 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 6430 u8 flags14; 6431 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1 6432 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0 6433 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1 6434 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1 6435 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3 6436 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2 6437 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1 6438 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4 6439 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 6440 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 6441 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3 6442 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6 6443 u8 byte2; 6444 __le16 physical_q0; 6445 __le16 word1; 6446 __le16 word2; 6447 __le16 word3; 6448 __le16 word4; 6449 __le16 word5; 6450 __le16 conn_dpi; 6451 u8 byte3; 6452 u8 byte4; 6453 u8 byte5; 6454 u8 byte6; 6455 __le32 reg0; 6456 __le32 reg1; 6457 __le32 reg2; 6458 __le32 snd_nxt_psn; 6459 __le32 reg4; 6460 }; 6461 6462 struct mstorm_roce_conn_ag_ctx { 6463 u8 byte0; 6464 u8 byte1; 6465 u8 flags0; 6466 #define MSTORM_ROCE_CONN_AG_CTX_BIT0_MASK 0x1 6467 #define MSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT 0 6468 #define MSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 6469 #define MSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 6470 #define MSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3 6471 #define MSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 2 6472 #define MSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3 6473 #define MSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT 4 6474 #define MSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3 6475 #define MSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 6 6476 u8 flags1; 6477 #define MSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1 6478 #define MSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 0 6479 #define MSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1 6480 #define MSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT 1 6481 #define MSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 6482 #define MSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 2 6483 #define MSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1 6484 #define MSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3 6485 #define MSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1 6486 #define MSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4 6487 #define MSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 6488 #define MSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5 6489 #define MSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1 6490 #define MSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 6 6491 #define MSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 6492 #define MSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7 6493 __le16 word0; 6494 __le16 word1; 6495 __le32 reg0; 6496 __le32 reg1; 6497 }; 6498 6499 struct mstorm_roce_req_conn_ag_ctx { 6500 u8 byte0; 6501 u8 byte1; 6502 u8 flags0; 6503 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 6504 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 6505 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 6506 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 6507 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 6508 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 6509 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 6510 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 6511 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 6512 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 6513 u8 flags1; 6514 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 6515 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 6516 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 6517 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 6518 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 6519 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 6520 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 6521 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 6522 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 6523 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 6524 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 6525 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 6526 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 6527 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 6528 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 6529 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 6530 __le16 word0; 6531 __le16 word1; 6532 __le32 reg0; 6533 __le32 reg1; 6534 }; 6535 6536 struct mstorm_roce_resp_conn_ag_ctx { 6537 u8 byte0; 6538 u8 byte1; 6539 u8 flags0; 6540 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 6541 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 6542 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 6543 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 6544 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 6545 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 6546 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 6547 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 6548 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 6549 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 6550 u8 flags1; 6551 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 6552 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 6553 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 6554 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 6555 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 6556 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 6557 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 6558 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 6559 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 6560 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 6561 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 6562 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 6563 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 6564 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 6565 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 6566 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 6567 __le16 word0; 6568 __le16 word1; 6569 __le32 reg0; 6570 __le32 reg1; 6571 }; 6572 6573 struct tstorm_roce_req_conn_ag_ctx { 6574 u8 reserved0; 6575 u8 state; 6576 u8 flags0; 6577 #define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 6578 #define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 6579 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_MASK 0x1 6580 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_SHIFT 1 6581 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_MASK 0x1 6582 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_SHIFT 2 6583 #define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1 6584 #define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3 6585 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 6586 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 6587 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 6588 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5 6589 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3 6590 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6 6591 u8 flags1; 6592 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 6593 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 6594 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3 6595 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2 6596 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 6597 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 6598 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 6599 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 6600 u8 flags2; 6601 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_MASK 0x3 6602 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_SHIFT 0 6603 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3 6604 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2 6605 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3 6606 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4 6607 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3 6608 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6 6609 u8 flags3; 6610 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3 6611 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0 6612 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3 6613 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2 6614 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1 6615 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4 6616 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 6617 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 5 6618 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1 6619 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6 6620 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 6621 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 6622 u8 flags4; 6623 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 6624 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 6625 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_MASK 0x1 6626 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_SHIFT 1 6627 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1 6628 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2 6629 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1 6630 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3 6631 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1 6632 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4 6633 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1 6634 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5 6635 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1 6636 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6 6637 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 6638 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 6639 u8 flags5; 6640 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 6641 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 6642 #define TSTORM_ROCE_REQ_CONN_AG_CTX_DIF_CNT_EN_MASK 0x1 6643 #define TSTORM_ROCE_REQ_CONN_AG_CTX_DIF_CNT_EN_SHIFT 1 6644 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 6645 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 6646 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 6647 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 6648 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 6649 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 6650 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1 6651 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5 6652 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 6653 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 6654 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 6655 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 6656 __le32 dif_rxmit_cnt; 6657 __le32 snd_nxt_psn; 6658 __le32 snd_max_psn; 6659 __le32 orq_prod; 6660 __le32 reg4; 6661 __le32 dif_acked_cnt; 6662 __le32 dif_cnt; 6663 __le32 reg7; 6664 __le32 reg8; 6665 u8 tx_cqe_error_type; 6666 u8 orq_cache_idx; 6667 __le16 snd_sq_cons_th; 6668 u8 byte4; 6669 u8 byte5; 6670 __le16 snd_sq_cons; 6671 __le16 conn_dpi; 6672 __le16 force_comp_cons; 6673 __le32 dif_rxmit_acked_cnt; 6674 __le32 reg10; 6675 }; 6676 6677 struct tstorm_roce_resp_conn_ag_ctx { 6678 u8 byte0; 6679 u8 state; 6680 u8 flags0; 6681 #define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 6682 #define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 6683 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1 6684 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1 6685 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1 6686 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2 6687 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1 6688 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3 6689 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 6690 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 6691 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1 6692 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5 6693 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 6694 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6 6695 u8 flags1; 6696 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 6697 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 6698 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3 6699 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2 6700 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 6701 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4 6702 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 6703 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 6704 u8 flags2; 6705 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 6706 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0 6707 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 6708 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2 6709 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3 6710 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4 6711 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 6712 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6 6713 u8 flags3; 6714 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 6715 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0 6716 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 6717 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2 6718 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 6719 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4 6720 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 6721 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 5 6722 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1 6723 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6 6724 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 6725 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7 6726 u8 flags4; 6727 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 6728 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 6729 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 6730 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 1 6731 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 6732 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2 6733 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1 6734 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3 6735 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 6736 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4 6737 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 6738 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5 6739 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 6740 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6 6741 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 6742 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 6743 u8 flags5; 6744 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 6745 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 6746 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 6747 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 6748 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 6749 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 6750 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 6751 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 6752 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 6753 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 6754 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1 6755 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5 6756 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 6757 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 6758 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 6759 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 6760 __le32 psn_and_rxmit_id_echo; 6761 __le32 reg1; 6762 __le32 reg2; 6763 __le32 reg3; 6764 __le32 reg4; 6765 __le32 reg5; 6766 __le32 reg6; 6767 __le32 reg7; 6768 __le32 reg8; 6769 u8 tx_async_error_type; 6770 u8 byte3; 6771 __le16 rq_cons; 6772 u8 byte4; 6773 u8 byte5; 6774 __le16 rq_prod; 6775 __le16 conn_dpi; 6776 __le16 irq_cons; 6777 __le32 reg9; 6778 __le32 reg10; 6779 }; 6780 6781 struct ustorm_roce_req_conn_ag_ctx { 6782 u8 byte0; 6783 u8 byte1; 6784 u8 flags0; 6785 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 6786 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 6787 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 6788 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 6789 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 6790 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 6791 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 6792 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 6793 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 6794 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 6795 u8 flags1; 6796 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 6797 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0 6798 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3 6799 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2 6800 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3 6801 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4 6802 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3 6803 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6 6804 u8 flags2; 6805 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 6806 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 6807 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 6808 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 6809 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 6810 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 6811 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 6812 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3 6813 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1 6814 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4 6815 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1 6816 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5 6817 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1 6818 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6 6819 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 6820 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 6821 u8 flags3; 6822 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 6823 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 6824 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 6825 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1 6826 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 6827 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 6828 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 6829 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 6830 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 6831 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 6832 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 6833 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5 6834 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 6835 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 6836 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 6837 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 6838 u8 byte2; 6839 u8 byte3; 6840 __le16 word0; 6841 __le16 word1; 6842 __le32 reg0; 6843 __le32 reg1; 6844 __le32 reg2; 6845 __le32 reg3; 6846 __le16 word2; 6847 __le16 word3; 6848 }; 6849 6850 struct ustorm_roce_resp_conn_ag_ctx { 6851 u8 byte0; 6852 u8 byte1; 6853 u8 flags0; 6854 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 6855 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 6856 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 6857 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 6858 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 6859 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 6860 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 6861 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 6862 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 6863 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 6864 u8 flags1; 6865 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 6866 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0 6867 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3 6868 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2 6869 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3 6870 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4 6871 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 6872 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6 6873 u8 flags2; 6874 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 6875 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 6876 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 6877 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 6878 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 6879 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 6880 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 6881 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3 6882 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1 6883 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4 6884 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1 6885 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5 6886 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 6887 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6 6888 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 6889 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 6890 u8 flags3; 6891 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 6892 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 6893 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 6894 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 6895 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 6896 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 6897 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 6898 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 6899 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 6900 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 6901 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 6902 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5 6903 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 6904 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 6905 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 6906 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 6907 u8 byte2; 6908 u8 byte3; 6909 __le16 word0; 6910 __le16 word1; 6911 __le32 reg0; 6912 __le32 reg1; 6913 __le32 reg2; 6914 __le32 reg3; 6915 __le16 word2; 6916 __le16 word3; 6917 }; 6918 6919 struct xstorm_roce_req_conn_ag_ctx { 6920 u8 reserved0; 6921 u8 state; 6922 u8 flags0; 6923 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 6924 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 6925 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1 6926 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1 6927 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1 6928 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2 6929 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 6930 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 6931 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1 6932 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4 6933 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1 6934 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5 6935 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1 6936 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6 6937 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1 6938 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7 6939 u8 flags1; 6940 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1 6941 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0 6942 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1 6943 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1 6944 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1 6945 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2 6946 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1 6947 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3 6948 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1 6949 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MSDM_FLUSH_SHIFT 4 6950 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1 6951 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MSEM_FLUSH_SHIFT 5 6952 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1 6953 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6 6954 #define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 6955 #define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 6956 u8 flags2; 6957 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 6958 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0 6959 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 6960 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2 6961 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 6962 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4 6963 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 6964 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6 6965 u8 flags3; 6966 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 6967 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0 6968 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 6969 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 6970 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3 6971 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4 6972 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 6973 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 6974 u8 flags4; 6975 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_MASK 0x3 6976 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_SHIFT 0 6977 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_MASK 0x3 6978 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_SHIFT 2 6979 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3 6980 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4 6981 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3 6982 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6 6983 u8 flags5; 6984 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3 6985 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0 6986 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3 6987 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2 6988 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3 6989 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4 6990 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3 6991 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6 6992 u8 flags6; 6993 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3 6994 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0 6995 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3 6996 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2 6997 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3 6998 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4 6999 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3 7000 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6 7001 u8 flags7; 7002 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3 7003 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0 7004 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3 7005 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2 7006 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3 7007 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4 7008 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 7009 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6 7010 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 7011 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7 7012 u8 flags8; 7013 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 7014 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0 7015 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 7016 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1 7017 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 7018 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2 7019 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 7020 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 7021 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1 7022 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4 7023 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 7024 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 7025 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 7026 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_SHIFT 6 7027 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_MASK 0x1 7028 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_SHIFT 7 7029 u8 flags9; 7030 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1 7031 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0 7032 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1 7033 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1 7034 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1 7035 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2 7036 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1 7037 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3 7038 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1 7039 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4 7040 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1 7041 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5 7042 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1 7043 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6 7044 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1 7045 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7 7046 u8 flags10; 7047 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1 7048 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0 7049 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1 7050 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1 7051 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1 7052 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2 7053 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1 7054 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3 7055 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 7056 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 7057 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1 7058 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5 7059 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 7060 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6 7061 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 7062 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7 7063 u8 flags11; 7064 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 7065 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0 7066 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 7067 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1 7068 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 7069 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2 7070 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 7071 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3 7072 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 7073 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4 7074 #define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1 7075 #define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5 7076 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 7077 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 7078 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1 7079 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7 7080 u8 flags12; 7081 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1 7082 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0 7083 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1 7084 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1 7085 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 7086 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 7087 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 7088 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 7089 #define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1 7090 #define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4 7091 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1 7092 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5 7093 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1 7094 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6 7095 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1 7096 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7 7097 u8 flags13; 7098 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1 7099 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0 7100 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1 7101 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1 7102 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 7103 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 7104 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 7105 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 7106 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 7107 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 7108 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 7109 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 7110 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 7111 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 7112 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 7113 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 7114 u8 flags14; 7115 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1 7116 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0 7117 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1 7118 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1 7119 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 7120 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 7121 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1 7122 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4 7123 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 7124 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 7125 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3 7126 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6 7127 u8 byte2; 7128 __le16 physical_q0; 7129 __le16 word1; 7130 __le16 sq_cmp_cons; 7131 __le16 sq_cons; 7132 __le16 sq_prod; 7133 __le16 dif_error_first_sq_cons; 7134 __le16 conn_dpi; 7135 u8 dif_error_sge_index; 7136 u8 byte4; 7137 u8 byte5; 7138 u8 byte6; 7139 __le32 lsn; 7140 __le32 ssn; 7141 __le32 snd_una_psn; 7142 __le32 snd_nxt_psn; 7143 __le32 dif_error_offset; 7144 __le32 orq_cons_th; 7145 __le32 orq_cons; 7146 }; 7147 7148 struct xstorm_roce_resp_conn_ag_ctx { 7149 u8 reserved0; 7150 u8 state; 7151 u8 flags0; 7152 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 7153 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 7154 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1 7155 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1 7156 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1 7157 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2 7158 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 7159 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 7160 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1 7161 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4 7162 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1 7163 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5 7164 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1 7165 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6 7166 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1 7167 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7 7168 u8 flags1; 7169 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1 7170 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0 7171 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1 7172 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1 7173 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1 7174 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2 7175 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1 7176 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3 7177 #define XSTORM_ROCE_RESP_CONN_AG_CTX_MSDM_FLUSH_MASK 0x1 7178 #define XSTORM_ROCE_RESP_CONN_AG_CTX_MSDM_FLUSH_SHIFT 4 7179 #define XSTORM_ROCE_RESP_CONN_AG_CTX_MSEM_FLUSH_MASK 0x1 7180 #define XSTORM_ROCE_RESP_CONN_AG_CTX_MSEM_FLUSH_SHIFT 5 7181 #define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1 7182 #define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6 7183 #define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 7184 #define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 7185 u8 flags2; 7186 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 7187 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0 7188 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 7189 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2 7190 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 7191 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4 7192 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 7193 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6 7194 u8 flags3; 7195 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3 7196 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0 7197 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 7198 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 7199 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3 7200 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4 7201 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 7202 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 7203 u8 flags4; 7204 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 7205 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0 7206 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 7207 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2 7208 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 7209 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4 7210 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3 7211 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6 7212 u8 flags5; 7213 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3 7214 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0 7215 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3 7216 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2 7217 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3 7218 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4 7219 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3 7220 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6 7221 u8 flags6; 7222 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3 7223 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0 7224 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3 7225 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2 7226 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3 7227 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4 7228 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3 7229 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6 7230 u8 flags7; 7231 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3 7232 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0 7233 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3 7234 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2 7235 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 7236 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4 7237 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 7238 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6 7239 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 7240 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7 7241 u8 flags8; 7242 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 7243 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0 7244 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 7245 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1 7246 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1 7247 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2 7248 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 7249 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 7250 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1 7251 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4 7252 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 7253 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 7254 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 7255 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6 7256 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 7257 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7 7258 u8 flags9; 7259 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 7260 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0 7261 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1 7262 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1 7263 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1 7264 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2 7265 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1 7266 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3 7267 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1 7268 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4 7269 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1 7270 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5 7271 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1 7272 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6 7273 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1 7274 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7 7275 u8 flags10; 7276 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1 7277 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0 7278 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1 7279 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1 7280 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1 7281 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2 7282 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1 7283 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3 7284 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 7285 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 7286 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1 7287 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5 7288 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 7289 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6 7290 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 7291 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7 7292 u8 flags11; 7293 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 7294 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0 7295 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 7296 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1 7297 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 7298 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2 7299 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 7300 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3 7301 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 7302 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4 7303 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 7304 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5 7305 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 7306 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 7307 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1 7308 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7 7309 u8 flags12; 7310 #define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1 7311 #define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 0 7312 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_MASK 0x1 7313 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_SHIFT 1 7314 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 7315 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 7316 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 7317 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 7318 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1 7319 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4 7320 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1 7321 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5 7322 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1 7323 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6 7324 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1 7325 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7 7326 u8 flags13; 7327 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1 7328 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0 7329 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1 7330 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1 7331 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 7332 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 7333 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 7334 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 7335 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 7336 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 7337 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 7338 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 7339 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 7340 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 7341 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 7342 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 7343 u8 flags14; 7344 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1 7345 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0 7346 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1 7347 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1 7348 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1 7349 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2 7350 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1 7351 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3 7352 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1 7353 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4 7354 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1 7355 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5 7356 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3 7357 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6 7358 u8 byte2; 7359 __le16 physical_q0; 7360 __le16 irq_prod_shadow; 7361 __le16 word2; 7362 __le16 irq_cons; 7363 __le16 irq_prod; 7364 __le16 e5_reserved1; 7365 __le16 conn_dpi; 7366 u8 rxmit_opcode; 7367 u8 byte4; 7368 u8 byte5; 7369 u8 byte6; 7370 __le32 rxmit_psn_and_id; 7371 __le32 rxmit_bytes_length; 7372 __le32 psn; 7373 __le32 reg3; 7374 __le32 reg4; 7375 __le32 reg5; 7376 __le32 msn_and_syndrome; 7377 }; 7378 7379 struct ystorm_roce_conn_ag_ctx { 7380 u8 byte0; 7381 u8 byte1; 7382 u8 flags0; 7383 #define YSTORM_ROCE_CONN_AG_CTX_BIT0_MASK 0x1 7384 #define YSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT 0 7385 #define YSTORM_ROCE_CONN_AG_CTX_BIT1_MASK 0x1 7386 #define YSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT 1 7387 #define YSTORM_ROCE_CONN_AG_CTX_CF0_MASK 0x3 7388 #define YSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT 2 7389 #define YSTORM_ROCE_CONN_AG_CTX_CF1_MASK 0x3 7390 #define YSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT 4 7391 #define YSTORM_ROCE_CONN_AG_CTX_CF2_MASK 0x3 7392 #define YSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT 6 7393 u8 flags1; 7394 #define YSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK 0x1 7395 #define YSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT 0 7396 #define YSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK 0x1 7397 #define YSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT 1 7398 #define YSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK 0x1 7399 #define YSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT 2 7400 #define YSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK 0x1 7401 #define YSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3 7402 #define YSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK 0x1 7403 #define YSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4 7404 #define YSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK 0x1 7405 #define YSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5 7406 #define YSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK 0x1 7407 #define YSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 6 7408 #define YSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK 0x1 7409 #define YSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7 7410 u8 byte2; 7411 u8 byte3; 7412 __le16 word0; 7413 __le32 reg0; 7414 __le32 reg1; 7415 __le16 word1; 7416 __le16 word2; 7417 __le16 word3; 7418 __le16 word4; 7419 __le32 reg2; 7420 __le32 reg3; 7421 }; 7422 7423 struct ystorm_roce_req_conn_ag_ctx { 7424 u8 byte0; 7425 u8 byte1; 7426 u8 flags0; 7427 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 7428 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 7429 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 7430 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 7431 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 7432 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 7433 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 7434 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 7435 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 7436 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 7437 u8 flags1; 7438 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 7439 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 7440 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 7441 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 7442 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 7443 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 7444 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 7445 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 7446 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 7447 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 7448 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 7449 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 7450 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 7451 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 7452 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 7453 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 7454 u8 byte2; 7455 u8 byte3; 7456 __le16 word0; 7457 __le32 reg0; 7458 __le32 reg1; 7459 __le16 word1; 7460 __le16 word2; 7461 __le16 word3; 7462 __le16 word4; 7463 __le32 reg2; 7464 __le32 reg3; 7465 }; 7466 7467 struct ystorm_roce_resp_conn_ag_ctx { 7468 u8 byte0; 7469 u8 byte1; 7470 u8 flags0; 7471 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 7472 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 7473 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 7474 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 7475 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 7476 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 7477 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 7478 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 7479 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 7480 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 7481 u8 flags1; 7482 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 7483 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 7484 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 7485 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 7486 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 7487 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 7488 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 7489 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 7490 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 7491 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 7492 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 7493 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 7494 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 7495 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 7496 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 7497 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 7498 u8 byte2; 7499 u8 byte3; 7500 __le16 word0; 7501 __le32 reg0; 7502 __le32 reg1; 7503 __le16 word1; 7504 __le16 word2; 7505 __le16 word3; 7506 __le16 word4; 7507 __le32 reg2; 7508 __le32 reg3; 7509 }; 7510 7511 /* Roce doorbell data */ 7512 enum roce_flavor { 7513 PLAIN_ROCE, 7514 RROCE_IPV4, 7515 RROCE_IPV6, 7516 MAX_ROCE_FLAVOR 7517 }; 7518 7519 /* The iwarp storm context of Ystorm */ 7520 struct ystorm_iwarp_conn_st_ctx { 7521 __le32 reserved[4]; 7522 }; 7523 7524 /* The iwarp storm context of Pstorm */ 7525 struct pstorm_iwarp_conn_st_ctx { 7526 __le32 reserved[36]; 7527 }; 7528 7529 /* The iwarp storm context of Xstorm */ 7530 struct xstorm_iwarp_conn_st_ctx { 7531 __le32 reserved[48]; 7532 }; 7533 7534 struct xstorm_iwarp_conn_ag_ctx { 7535 u8 reserved0; 7536 u8 state; 7537 u8 flags0; 7538 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 7539 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 7540 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1 7541 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1 7542 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK 0x1 7543 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_SHIFT 2 7544 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 7545 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 7546 #define XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 7547 #define XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4 7548 #define XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1 7549 #define XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT 5 7550 #define XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1 7551 #define XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT 6 7552 #define XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1 7553 #define XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT 7 7554 u8 flags1; 7555 #define XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1 7556 #define XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT 0 7557 #define XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1 7558 #define XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT 1 7559 #define XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1 7560 #define XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT 2 7561 #define XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1 7562 #define XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT 3 7563 #define XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1 7564 #define XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT 4 7565 #define XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1 7566 #define XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT 5 7567 #define XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1 7568 #define XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT 6 7569 #define XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1 7570 #define XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7 7571 u8 flags2; 7572 #define XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 7573 #define XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 0 7574 #define XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 7575 #define XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 2 7576 #define XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 7577 #define XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 4 7578 #define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 7579 #define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6 7580 u8 flags3; 7581 #define XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 7582 #define XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 0 7583 #define XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 7584 #define XSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 2 7585 #define XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 7586 #define XSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 4 7587 #define XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 7588 #define XSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 6 7589 u8 flags4; 7590 #define XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 7591 #define XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 0 7592 #define XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3 7593 #define XSTORM_IWARP_CONN_AG_CTX_CF9_SHIFT 2 7594 #define XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3 7595 #define XSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT 4 7596 #define XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3 7597 #define XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT 6 7598 u8 flags5; 7599 #define XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3 7600 #define XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT 0 7601 #define XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3 7602 #define XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT 2 7603 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 7604 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 4 7605 #define XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3 7606 #define XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT 6 7607 u8 flags6; 7608 #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3 7609 #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0 7610 #define XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3 7611 #define XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT 2 7612 #define XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3 7613 #define XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT 4 7614 #define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 7615 #define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT 6 7616 u8 flags7; 7617 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 7618 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 7619 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3 7620 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT 2 7621 #define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 7622 #define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT 4 7623 #define XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 7624 #define XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 6 7625 #define XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 7626 #define XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 7 7627 u8 flags8; 7628 #define XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 7629 #define XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 0 7630 #define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 7631 #define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1 7632 #define XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 7633 #define XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 2 7634 #define XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 7635 #define XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 3 7636 #define XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 7637 #define XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 4 7638 #define XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 7639 #define XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 5 7640 #define XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 7641 #define XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 6 7642 #define XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1 7643 #define XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT 7 7644 u8 flags9; 7645 #define XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1 7646 #define XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 0 7647 #define XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1 7648 #define XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT 1 7649 #define XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1 7650 #define XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT 2 7651 #define XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1 7652 #define XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT 3 7653 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 7654 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 4 7655 #define XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1 7656 #define XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT 5 7657 #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1 7658 #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6 7659 #define XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1 7660 #define XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT 7 7661 u8 flags10; 7662 #define XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1 7663 #define XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT 0 7664 #define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1 7665 #define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1 7666 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 7667 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 7668 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1 7669 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3 7670 #define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 7671 #define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 7672 #define XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_MASK 0x1 7673 #define XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_SHIFT 5 7674 #define XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 7675 #define XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 6 7676 #define XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1 7677 #define XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7 7678 u8 flags11; 7679 #define XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1 7680 #define XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0 7681 #define XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 7682 #define XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 1 7683 #define XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1 7684 #define XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT 2 7685 #define XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 7686 #define XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 3 7687 #define XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1 7688 #define XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 4 7689 #define XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 7690 #define XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 5 7691 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 7692 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 7693 #define XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1 7694 #define XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT 7 7695 u8 flags12; 7696 #define XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1 7697 #define XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT 0 7698 #define XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1 7699 #define XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT 1 7700 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 7701 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 7702 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 7703 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 7704 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1 7705 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT 4 7706 #define XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1 7707 #define XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT 5 7708 #define XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1 7709 #define XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT 6 7710 #define XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1 7711 #define XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT 7 7712 u8 flags13; 7713 #define XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1 7714 #define XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0 7715 #define XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK 0x1 7716 #define XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT 1 7717 #define XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1 7718 #define XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT 2 7719 #define XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1 7720 #define XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT 3 7721 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 7722 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 7723 #define XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1 7724 #define XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT 5 7725 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 7726 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 7727 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 7728 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 7729 u8 flags14; 7730 #define XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1 7731 #define XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT 0 7732 #define XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1 7733 #define XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT 1 7734 #define XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK 0x1 7735 #define XSTORM_IWARP_CONN_AG_CTX_BIT18_SHIFT 2 7736 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK 0x1 7737 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_SHIFT 3 7738 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 7739 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_SHIFT 4 7740 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 7741 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_SHIFT 5 7742 #define XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_MASK 0x3 7743 #define XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_SHIFT 6 7744 u8 byte2; 7745 __le16 physical_q0; 7746 __le16 physical_q1; 7747 __le16 sq_comp_cons; 7748 __le16 sq_tx_cons; 7749 __le16 sq_prod; 7750 __le16 word5; 7751 __le16 conn_dpi; 7752 u8 byte3; 7753 u8 byte4; 7754 u8 byte5; 7755 u8 byte6; 7756 __le32 reg0; 7757 __le32 reg1; 7758 __le32 reg2; 7759 __le32 more_to_send_seq; 7760 __le32 reg4; 7761 __le32 rewinded_snd_max_or_term_opcode; 7762 __le32 rd_msn; 7763 __le16 irq_prod_via_msdm; 7764 __le16 irq_cons; 7765 __le16 hq_cons_th_or_mpa_data; 7766 __le16 hq_cons; 7767 __le32 atom_msn; 7768 __le32 orq_cons; 7769 __le32 orq_cons_th; 7770 u8 byte7; 7771 u8 wqe_data_pad_bytes; 7772 u8 max_ord; 7773 u8 former_hq_prod; 7774 u8 irq_prod_via_msem; 7775 u8 byte12; 7776 u8 max_pkt_pdu_size_lo; 7777 u8 max_pkt_pdu_size_hi; 7778 u8 byte15; 7779 u8 e5_reserved; 7780 __le16 e5_reserved4; 7781 __le32 reg10; 7782 __le32 reg11; 7783 __le32 shared_queue_page_addr_lo; 7784 __le32 shared_queue_page_addr_hi; 7785 __le32 reg14; 7786 __le32 reg15; 7787 __le32 reg16; 7788 __le32 reg17; 7789 }; 7790 7791 struct tstorm_iwarp_conn_ag_ctx { 7792 u8 reserved0; 7793 u8 state; 7794 u8 flags0; 7795 #define TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 7796 #define TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 7797 #define TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 7798 #define TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 7799 #define TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1 7800 #define TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT 2 7801 #define TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_MASK 0x1 7802 #define TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_SHIFT 3 7803 #define TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 7804 #define TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4 7805 #define TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 7806 #define TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT 5 7807 #define TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 7808 #define TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 6 7809 u8 flags1; 7810 #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3 7811 #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT 0 7812 #define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK 0x3 7813 #define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_SHIFT 2 7814 #define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 7815 #define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4 7816 #define TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 7817 #define TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 6 7818 u8 flags2; 7819 #define TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 7820 #define TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 0 7821 #define TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 7822 #define TSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 2 7823 #define TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 7824 #define TSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 4 7825 #define TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 7826 #define TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 6 7827 u8 flags3; 7828 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_MASK 0x3 7829 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_SHIFT 0 7830 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3 7831 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT 2 7832 #define TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 7833 #define TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 4 7834 #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1 7835 #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT 5 7836 #define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK 0x1 7837 #define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_SHIFT 6 7838 #define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 7839 #define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7 7840 u8 flags4; 7841 #define TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 7842 #define TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 0 7843 #define TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 7844 #define TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 1 7845 #define TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 7846 #define TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 2 7847 #define TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 7848 #define TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 3 7849 #define TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 7850 #define TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 4 7851 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_MASK 0x1 7852 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_SHIFT 5 7853 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1 7854 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT 6 7855 #define TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 7856 #define TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 7 7857 u8 flags5; 7858 #define TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 7859 #define TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 0 7860 #define TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 7861 #define TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1 7862 #define TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 7863 #define TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2 7864 #define TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 7865 #define TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3 7866 #define TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 7867 #define TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4 7868 #define TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1 7869 #define TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT 5 7870 #define TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 7871 #define TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6 7872 #define TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1 7873 #define TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7 7874 __le32 reg0; 7875 __le32 reg1; 7876 __le32 unaligned_nxt_seq; 7877 __le32 reg3; 7878 __le32 reg4; 7879 __le32 reg5; 7880 __le32 reg6; 7881 __le32 reg7; 7882 __le32 reg8; 7883 u8 orq_cache_idx; 7884 u8 hq_prod; 7885 __le16 sq_tx_cons_th; 7886 u8 orq_prod; 7887 u8 irq_cons; 7888 __le16 sq_tx_cons; 7889 __le16 conn_dpi; 7890 __le16 rq_prod; 7891 __le32 snd_seq; 7892 __le32 last_hq_sequence; 7893 }; 7894 7895 /* The iwarp storm context of Tstorm */ 7896 struct tstorm_iwarp_conn_st_ctx { 7897 __le32 reserved[60]; 7898 }; 7899 7900 /* The iwarp storm context of Mstorm */ 7901 struct mstorm_iwarp_conn_st_ctx { 7902 __le32 reserved[32]; 7903 }; 7904 7905 /* The iwarp storm context of Ustorm */ 7906 struct ustorm_iwarp_conn_st_ctx { 7907 struct regpair reserved[14]; 7908 }; 7909 7910 /* iwarp connection context */ 7911 struct iwarp_conn_context { 7912 struct ystorm_iwarp_conn_st_ctx ystorm_st_context; 7913 struct regpair ystorm_st_padding[2]; 7914 struct pstorm_iwarp_conn_st_ctx pstorm_st_context; 7915 struct regpair pstorm_st_padding[2]; 7916 struct xstorm_iwarp_conn_st_ctx xstorm_st_context; 7917 struct xstorm_iwarp_conn_ag_ctx xstorm_ag_context; 7918 struct tstorm_iwarp_conn_ag_ctx tstorm_ag_context; 7919 struct timers_context timer_context; 7920 struct ustorm_rdma_conn_ag_ctx ustorm_ag_context; 7921 struct tstorm_iwarp_conn_st_ctx tstorm_st_context; 7922 struct regpair tstorm_st_padding[2]; 7923 struct mstorm_iwarp_conn_st_ctx mstorm_st_context; 7924 struct ustorm_iwarp_conn_st_ctx ustorm_st_context; 7925 struct regpair ustorm_st_padding[2]; 7926 }; 7927 7928 /* iWARP create QP params passed by driver to FW in CreateQP Request Ramrod */ 7929 struct iwarp_create_qp_ramrod_data { 7930 u8 flags; 7931 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1 7932 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 0 7933 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK 0x1 7934 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_SHIFT 1 7935 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 7936 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2 7937 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 7938 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3 7939 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 7940 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 4 7941 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK 0x1 7942 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_SHIFT 5 7943 #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_MASK 0x1 7944 #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_SHIFT 6 7945 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK 0x1 7946 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_SHIFT 7 7947 u8 reserved1; 7948 __le16 pd; 7949 __le16 sq_num_pages; 7950 __le16 rq_num_pages; 7951 __le32 reserved3[2]; 7952 struct regpair qp_handle_for_cqe; 7953 struct rdma_srq_id srq_id; 7954 __le32 cq_cid_for_sq; 7955 __le32 cq_cid_for_rq; 7956 __le16 dpi; 7957 __le16 physical_q0; 7958 __le16 physical_q1; 7959 u8 reserved2[6]; 7960 }; 7961 7962 /* iWARP completion queue types */ 7963 enum iwarp_eqe_async_opcode { 7964 IWARP_EVENT_TYPE_ASYNC_CONNECT_COMPLETE, 7965 IWARP_EVENT_TYPE_ASYNC_ENHANCED_MPA_REPLY_ARRIVED, 7966 IWARP_EVENT_TYPE_ASYNC_MPA_HANDSHAKE_COMPLETE, 7967 IWARP_EVENT_TYPE_ASYNC_CID_CLEANED, 7968 IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED, 7969 IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE, 7970 IWARP_EVENT_TYPE_ASYNC_CQ_OVERFLOW, 7971 IWARP_EVENT_TYPE_ASYNC_SRQ_EMPTY, 7972 IWARP_EVENT_TYPE_ASYNC_SRQ_LIMIT, 7973 MAX_IWARP_EQE_ASYNC_OPCODE 7974 }; 7975 7976 struct iwarp_eqe_data_mpa_async_completion { 7977 __le16 ulp_data_len; 7978 u8 rtr_type_sent; 7979 u8 reserved[5]; 7980 }; 7981 7982 struct iwarp_eqe_data_tcp_async_completion { 7983 __le16 ulp_data_len; 7984 u8 mpa_handshake_mode; 7985 u8 reserved[5]; 7986 }; 7987 7988 /* iWARP completion queue types */ 7989 enum iwarp_eqe_sync_opcode { 7990 IWARP_EVENT_TYPE_TCP_OFFLOAD = 7991 11, 7992 IWARP_EVENT_TYPE_MPA_OFFLOAD, 7993 IWARP_EVENT_TYPE_MPA_OFFLOAD_SEND_RTR, 7994 IWARP_EVENT_TYPE_CREATE_QP, 7995 IWARP_EVENT_TYPE_QUERY_QP, 7996 IWARP_EVENT_TYPE_MODIFY_QP, 7997 IWARP_EVENT_TYPE_DESTROY_QP, 7998 IWARP_EVENT_TYPE_ABORT_TCP_OFFLOAD, 7999 MAX_IWARP_EQE_SYNC_OPCODE 8000 }; 8001 8002 /* iWARP EQE completion status */ 8003 enum iwarp_fw_return_code { 8004 IWARP_CONN_ERROR_TCP_CONNECT_INVALID_PACKET = 6, 8005 IWARP_CONN_ERROR_TCP_CONNECTION_RST, 8006 IWARP_CONN_ERROR_TCP_CONNECT_TIMEOUT, 8007 IWARP_CONN_ERROR_MPA_ERROR_REJECT, 8008 IWARP_CONN_ERROR_MPA_NOT_SUPPORTED_VER, 8009 IWARP_CONN_ERROR_MPA_RST, 8010 IWARP_CONN_ERROR_MPA_FIN, 8011 IWARP_CONN_ERROR_MPA_RTR_MISMATCH, 8012 IWARP_CONN_ERROR_MPA_INSUF_IRD, 8013 IWARP_CONN_ERROR_MPA_INVALID_PACKET, 8014 IWARP_CONN_ERROR_MPA_LOCAL_ERROR, 8015 IWARP_CONN_ERROR_MPA_TIMEOUT, 8016 IWARP_CONN_ERROR_MPA_TERMINATE, 8017 IWARP_QP_IN_ERROR_GOOD_CLOSE, 8018 IWARP_QP_IN_ERROR_BAD_CLOSE, 8019 IWARP_EXCEPTION_DETECTED_LLP_CLOSED, 8020 IWARP_EXCEPTION_DETECTED_LLP_RESET, 8021 IWARP_EXCEPTION_DETECTED_IRQ_FULL, 8022 IWARP_EXCEPTION_DETECTED_RQ_EMPTY, 8023 IWARP_EXCEPTION_DETECTED_SRQ_EMPTY, 8024 IWARP_EXCEPTION_DETECTED_SRQ_LIMIT, 8025 IWARP_EXCEPTION_DETECTED_LLP_TIMEOUT, 8026 IWARP_EXCEPTION_DETECTED_REMOTE_PROTECTION_ERROR, 8027 IWARP_EXCEPTION_DETECTED_CQ_OVERFLOW, 8028 IWARP_EXCEPTION_DETECTED_LOCAL_CATASTROPHIC, 8029 IWARP_EXCEPTION_DETECTED_LOCAL_ACCESS_ERROR, 8030 IWARP_EXCEPTION_DETECTED_REMOTE_OPERATION_ERROR, 8031 IWARP_EXCEPTION_DETECTED_TERMINATE_RECEIVED, 8032 MAX_IWARP_FW_RETURN_CODE 8033 }; 8034 8035 /* unaligned opaque data received from LL2 */ 8036 struct iwarp_init_func_params { 8037 u8 ll2_ooo_q_index; 8038 u8 reserved1[7]; 8039 }; 8040 8041 /* iwarp func init ramrod data */ 8042 struct iwarp_init_func_ramrod_data { 8043 struct rdma_init_func_ramrod_data rdma; 8044 struct tcp_init_params tcp; 8045 struct iwarp_init_func_params iwarp; 8046 }; 8047 8048 /* iWARP QP - possible states to transition to */ 8049 enum iwarp_modify_qp_new_state_type { 8050 IWARP_MODIFY_QP_STATE_CLOSING = 1, 8051 IWARP_MODIFY_QP_STATE_ERROR = 2, 8052 MAX_IWARP_MODIFY_QP_NEW_STATE_TYPE 8053 }; 8054 8055 /* iwarp modify qp responder ramrod data */ 8056 struct iwarp_modify_qp_ramrod_data { 8057 __le16 transition_to_state; 8058 __le16 flags; 8059 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 8060 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 0 8061 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 8062 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 1 8063 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 8064 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 2 8065 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK 0x1 8066 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_SHIFT 3 8067 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1 8068 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 4 8069 #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK 0x1 8070 #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT 5 8071 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK 0x3FF 8072 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_SHIFT 6 8073 __le16 physical_q0; 8074 __le16 physical_q1; 8075 __le32 reserved1[10]; 8076 }; 8077 8078 /* MPA params for Enhanced mode */ 8079 struct mpa_rq_params { 8080 __le32 ird; 8081 __le32 ord; 8082 }; 8083 8084 /* MPA host Address-Len for private data */ 8085 struct mpa_ulp_buffer { 8086 struct regpair addr; 8087 __le16 len; 8088 __le16 reserved[3]; 8089 }; 8090 8091 /* iWARP MPA offload params common to Basic and Enhanced modes */ 8092 struct mpa_outgoing_params { 8093 u8 crc_needed; 8094 u8 reject; 8095 u8 reserved[6]; 8096 struct mpa_rq_params out_rq; 8097 struct mpa_ulp_buffer outgoing_ulp_buffer; 8098 }; 8099 8100 /* iWARP MPA offload params passed by driver to FW in MPA Offload Request 8101 * Ramrod. 8102 */ 8103 struct iwarp_mpa_offload_ramrod_data { 8104 struct mpa_outgoing_params common; 8105 __le32 tcp_cid; 8106 u8 mode; 8107 u8 tcp_connect_side; 8108 u8 rtr_pref; 8109 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_MASK 0x7 8110 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT 0 8111 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK 0x1F 8112 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_SHIFT 3 8113 u8 reserved2; 8114 struct mpa_ulp_buffer incoming_ulp_buffer; 8115 struct regpair async_eqe_output_buf; 8116 struct regpair handle_for_async; 8117 struct regpair shared_queue_addr; 8118 __le16 rcv_wnd; 8119 u8 stats_counter_id; 8120 u8 reserved3[13]; 8121 }; 8122 8123 /* iWARP TCP connection offload params passed by driver to FW */ 8124 struct iwarp_offload_params { 8125 struct mpa_ulp_buffer incoming_ulp_buffer; 8126 struct regpair async_eqe_output_buf; 8127 struct regpair handle_for_async; 8128 __le16 physical_q0; 8129 __le16 physical_q1; 8130 u8 stats_counter_id; 8131 u8 mpa_mode; 8132 u8 reserved[10]; 8133 }; 8134 8135 /* iWARP query QP output params */ 8136 struct iwarp_query_qp_output_params { 8137 __le32 flags; 8138 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1 8139 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0 8140 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF 8141 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_SHIFT 1 8142 u8 reserved1[4]; 8143 }; 8144 8145 /* iWARP query QP ramrod data */ 8146 struct iwarp_query_qp_ramrod_data { 8147 struct regpair output_params_addr; 8148 }; 8149 8150 /* iWARP Ramrod Command IDs */ 8151 enum iwarp_ramrod_cmd_id { 8152 IWARP_RAMROD_CMD_ID_TCP_OFFLOAD = 11, 8153 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD, 8154 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD_SEND_RTR, 8155 IWARP_RAMROD_CMD_ID_CREATE_QP, 8156 IWARP_RAMROD_CMD_ID_QUERY_QP, 8157 IWARP_RAMROD_CMD_ID_MODIFY_QP, 8158 IWARP_RAMROD_CMD_ID_DESTROY_QP, 8159 IWARP_RAMROD_CMD_ID_ABORT_TCP_OFFLOAD, 8160 MAX_IWARP_RAMROD_CMD_ID 8161 }; 8162 8163 /* Per PF iWARP retransmit path statistics */ 8164 struct iwarp_rxmit_stats_drv { 8165 struct regpair tx_go_to_slow_start_event_cnt; 8166 struct regpair tx_fast_retransmit_event_cnt; 8167 }; 8168 8169 /* iWARP and TCP connection offload params passed by driver to FW in iWARP 8170 * offload ramrod. 8171 */ 8172 struct iwarp_tcp_offload_ramrod_data { 8173 struct tcp_offload_params_opt2 tcp; 8174 struct iwarp_offload_params iwarp; 8175 }; 8176 8177 /* iWARP MPA negotiation types */ 8178 enum mpa_negotiation_mode { 8179 MPA_NEGOTIATION_TYPE_BASIC = 1, 8180 MPA_NEGOTIATION_TYPE_ENHANCED = 2, 8181 MAX_MPA_NEGOTIATION_MODE 8182 }; 8183 8184 /* iWARP MPA Enhanced mode RTR types */ 8185 enum mpa_rtr_type { 8186 MPA_RTR_TYPE_NONE = 0, 8187 MPA_RTR_TYPE_ZERO_SEND = 1, 8188 MPA_RTR_TYPE_ZERO_WRITE = 2, 8189 MPA_RTR_TYPE_ZERO_SEND_AND_WRITE = 3, 8190 MPA_RTR_TYPE_ZERO_READ = 4, 8191 MPA_RTR_TYPE_ZERO_SEND_AND_READ = 5, 8192 MPA_RTR_TYPE_ZERO_WRITE_AND_READ = 6, 8193 MPA_RTR_TYPE_ZERO_SEND_AND_WRITE_AND_READ = 7, 8194 MAX_MPA_RTR_TYPE 8195 }; 8196 8197 /* unaligned opaque data received from LL2 */ 8198 struct unaligned_opaque_data { 8199 __le16 first_mpa_offset; 8200 u8 tcp_payload_offset; 8201 u8 flags; 8202 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK 0x1 8203 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT 0 8204 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK 0x1 8205 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_SHIFT 1 8206 #define UNALIGNED_OPAQUE_DATA_RESERVED_MASK 0x3F 8207 #define UNALIGNED_OPAQUE_DATA_RESERVED_SHIFT 2 8208 __le32 cid; 8209 }; 8210 8211 struct mstorm_iwarp_conn_ag_ctx { 8212 u8 reserved; 8213 u8 state; 8214 u8 flags0; 8215 #define MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 8216 #define MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 8217 #define MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 8218 #define MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 8219 #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3 8220 #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT 2 8221 #define MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 8222 #define MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 8223 #define MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 8224 #define MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 8225 u8 flags1; 8226 #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1 8227 #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0 8228 #define MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 8229 #define MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 8230 #define MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 8231 #define MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 8232 #define MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 8233 #define MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3 8234 #define MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 8235 #define MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4 8236 #define MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 8237 #define MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5 8238 #define MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1 8239 #define MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT 6 8240 #define MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 8241 #define MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7 8242 __le16 rcq_cons; 8243 __le16 rcq_cons_th; 8244 __le32 reg0; 8245 __le32 reg1; 8246 }; 8247 8248 struct ustorm_iwarp_conn_ag_ctx { 8249 u8 reserved; 8250 u8 byte1; 8251 u8 flags0; 8252 #define USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 8253 #define USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 8254 #define USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 8255 #define USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 8256 #define USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 8257 #define USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2 8258 #define USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 8259 #define USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 8260 #define USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 8261 #define USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 8262 u8 flags1; 8263 #define USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3 8264 #define USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT 0 8265 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 8266 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 8267 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 8268 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 8269 #define USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 8270 #define USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 6 8271 u8 flags2; 8272 #define USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 8273 #define USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0 8274 #define USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 8275 #define USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 8276 #define USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 8277 #define USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 8278 #define USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1 8279 #define USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT 3 8280 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 8281 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 8282 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 8283 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 8284 #define USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 8285 #define USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 6 8286 #define USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 8287 #define USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 8288 u8 flags3; 8289 #define USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1 8290 #define USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT 0 8291 #define USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 8292 #define USTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1 8293 #define USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 8294 #define USTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2 8295 #define USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 8296 #define USTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3 8297 #define USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 8298 #define USTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4 8299 #define USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1 8300 #define USTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 5 8301 #define USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 8302 #define USTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6 8303 #define USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1 8304 #define USTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7 8305 u8 byte2; 8306 u8 byte3; 8307 __le16 word0; 8308 __le16 word1; 8309 __le32 cq_cons; 8310 __le32 cq_se_prod; 8311 __le32 cq_prod; 8312 __le32 reg3; 8313 __le16 word2; 8314 __le16 word3; 8315 }; 8316 8317 struct ystorm_iwarp_conn_ag_ctx { 8318 u8 byte0; 8319 u8 byte1; 8320 u8 flags0; 8321 #define YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK 0x1 8322 #define YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT 0 8323 #define YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 8324 #define YSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 8325 #define YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 8326 #define YSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2 8327 #define YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 8328 #define YSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 8329 #define YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 8330 #define YSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 8331 u8 flags1; 8332 #define YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 8333 #define YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0 8334 #define YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 8335 #define YSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 8336 #define YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 8337 #define YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 8338 #define YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 8339 #define YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3 8340 #define YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 8341 #define YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4 8342 #define YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 8343 #define YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5 8344 #define YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 8345 #define YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 6 8346 #define YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 8347 #define YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7 8348 u8 byte2; 8349 u8 byte3; 8350 __le16 word0; 8351 __le32 reg0; 8352 __le32 reg1; 8353 __le16 word1; 8354 __le16 word2; 8355 __le16 word3; 8356 __le16 word4; 8357 __le32 reg2; 8358 __le32 reg3; 8359 }; 8360 8361 /* The fcoe storm context of Ystorm */ 8362 struct ystorm_fcoe_conn_st_ctx { 8363 u8 func_mode; 8364 u8 cos; 8365 u8 conf_version; 8366 u8 eth_hdr_size; 8367 __le16 stat_ram_addr; 8368 __le16 mtu; 8369 __le16 max_fc_payload_len; 8370 __le16 tx_max_fc_pay_len; 8371 u8 fcp_cmd_size; 8372 u8 fcp_rsp_size; 8373 __le16 mss; 8374 struct regpair reserved; 8375 __le16 min_frame_size; 8376 u8 protection_info_flags; 8377 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1 8378 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 0 8379 #define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1 8380 #define YSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 1 8381 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK 0x3F 8382 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_SHIFT 2 8383 u8 dst_protection_per_mss; 8384 u8 src_protection_per_mss; 8385 u8 ptu_log_page_size; 8386 u8 flags; 8387 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 8388 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 0 8389 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1 8390 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 1 8391 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x3F 8392 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 2 8393 u8 fcp_xfer_size; 8394 }; 8395 8396 /* FCoE 16-bits vlan structure */ 8397 struct fcoe_vlan_fields { 8398 __le16 fields; 8399 #define FCOE_VLAN_FIELDS_VID_MASK 0xFFF 8400 #define FCOE_VLAN_FIELDS_VID_SHIFT 0 8401 #define FCOE_VLAN_FIELDS_CLI_MASK 0x1 8402 #define FCOE_VLAN_FIELDS_CLI_SHIFT 12 8403 #define FCOE_VLAN_FIELDS_PRI_MASK 0x7 8404 #define FCOE_VLAN_FIELDS_PRI_SHIFT 13 8405 }; 8406 8407 /* FCoE 16-bits vlan union */ 8408 union fcoe_vlan_field_union { 8409 struct fcoe_vlan_fields fields; 8410 __le16 val; 8411 }; 8412 8413 /* FCoE 16-bits vlan, vif union */ 8414 union fcoe_vlan_vif_field_union { 8415 union fcoe_vlan_field_union vlan; 8416 __le16 vif; 8417 }; 8418 8419 /* Ethernet context section */ 8420 struct pstorm_fcoe_eth_context_section { 8421 u8 remote_addr_3; 8422 u8 remote_addr_2; 8423 u8 remote_addr_1; 8424 u8 remote_addr_0; 8425 u8 local_addr_1; 8426 u8 local_addr_0; 8427 u8 remote_addr_5; 8428 u8 remote_addr_4; 8429 u8 local_addr_5; 8430 u8 local_addr_4; 8431 u8 local_addr_3; 8432 u8 local_addr_2; 8433 union fcoe_vlan_vif_field_union vif_outer_vlan; 8434 __le16 vif_outer_eth_type; 8435 union fcoe_vlan_vif_field_union inner_vlan; 8436 __le16 inner_eth_type; 8437 }; 8438 8439 /* The fcoe storm context of Pstorm */ 8440 struct pstorm_fcoe_conn_st_ctx { 8441 u8 func_mode; 8442 u8 cos; 8443 u8 conf_version; 8444 u8 rsrv; 8445 __le16 stat_ram_addr; 8446 __le16 mss; 8447 struct regpair abts_cleanup_addr; 8448 struct pstorm_fcoe_eth_context_section eth; 8449 u8 sid_2; 8450 u8 sid_1; 8451 u8 sid_0; 8452 u8 flags; 8453 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1 8454 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT 0 8455 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1 8456 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT 1 8457 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 8458 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 2 8459 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1 8460 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 3 8461 #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_MASK 0x1 8462 #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_SHIFT 4 8463 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x7 8464 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 5 8465 u8 did_2; 8466 u8 did_1; 8467 u8 did_0; 8468 u8 src_mac_index; 8469 __le16 rec_rr_tov_val; 8470 u8 q_relative_offset; 8471 u8 reserved1; 8472 }; 8473 8474 /* The fcoe storm context of Xstorm */ 8475 struct xstorm_fcoe_conn_st_ctx { 8476 u8 func_mode; 8477 u8 src_mac_index; 8478 u8 conf_version; 8479 u8 cached_wqes_avail; 8480 __le16 stat_ram_addr; 8481 u8 flags; 8482 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK 0x1 8483 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT 0 8484 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 8485 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 1 8486 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK 0x1 8487 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_SHIFT 2 8488 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3 8489 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT 3 8490 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x7 8491 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 5 8492 u8 cached_wqes_offset; 8493 u8 reserved2; 8494 u8 eth_hdr_size; 8495 u8 seq_id; 8496 u8 max_conc_seqs; 8497 __le16 num_pages_in_pbl; 8498 __le16 reserved; 8499 struct regpair sq_pbl_addr; 8500 struct regpair sq_curr_page_addr; 8501 struct regpair sq_next_page_addr; 8502 struct regpair xferq_pbl_addr; 8503 struct regpair xferq_curr_page_addr; 8504 struct regpair xferq_next_page_addr; 8505 struct regpair respq_pbl_addr; 8506 struct regpair respq_curr_page_addr; 8507 struct regpair respq_next_page_addr; 8508 __le16 mtu; 8509 __le16 tx_max_fc_pay_len; 8510 __le16 max_fc_payload_len; 8511 __le16 min_frame_size; 8512 __le16 sq_pbl_next_index; 8513 __le16 respq_pbl_next_index; 8514 u8 fcp_cmd_byte_credit; 8515 u8 fcp_rsp_byte_credit; 8516 __le16 protection_info; 8517 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK 0x1 8518 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT 0 8519 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1 8520 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 1 8521 #define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1 8522 #define XSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 2 8523 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK 0x1 8524 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT 3 8525 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK 0xF 8526 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_SHIFT 4 8527 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK 0xFF 8528 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_SHIFT 8 8529 __le16 xferq_pbl_next_index; 8530 __le16 page_size; 8531 u8 mid_seq; 8532 u8 fcp_xfer_byte_credit; 8533 u8 reserved1[2]; 8534 struct fcoe_wqe cached_wqes[16]; 8535 }; 8536 8537 struct xstorm_fcoe_conn_ag_ctx { 8538 u8 reserved0; 8539 u8 state; 8540 u8 flags0; 8541 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 8542 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 8543 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1 8544 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT 1 8545 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1 8546 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT 2 8547 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 8548 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 8549 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1 8550 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT 4 8551 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1 8552 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT 5 8553 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1 8554 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT 6 8555 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1 8556 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT 7 8557 u8 flags1; 8558 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1 8559 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0 8560 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1 8561 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT 1 8562 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1 8563 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT 2 8564 #define XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1 8565 #define XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT 3 8566 #define XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1 8567 #define XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT 4 8568 #define XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1 8569 #define XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT 5 8570 #define XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1 8571 #define XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT 6 8572 #define XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1 8573 #define XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT 7 8574 u8 flags2; 8575 #define XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 8576 #define XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0 8577 #define XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 8578 #define XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 2 8579 #define XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 8580 #define XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 4 8581 #define XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3 8582 #define XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 6 8583 u8 flags3; 8584 #define XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 8585 #define XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0 8586 #define XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 8587 #define XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 2 8588 #define XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 8589 #define XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 4 8590 #define XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3 8591 #define XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 6 8592 u8 flags4; 8593 #define XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3 8594 #define XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0 8595 #define XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3 8596 #define XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 2 8597 #define XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3 8598 #define XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 4 8599 #define XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3 8600 #define XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT 6 8601 u8 flags5; 8602 #define XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3 8603 #define XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0 8604 #define XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3 8605 #define XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT 2 8606 #define XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3 8607 #define XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT 4 8608 #define XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3 8609 #define XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT 6 8610 u8 flags6; 8611 #define XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3 8612 #define XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0 8613 #define XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3 8614 #define XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT 2 8615 #define XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3 8616 #define XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT 4 8617 #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3 8618 #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT 6 8619 u8 flags7; 8620 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 8621 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 8622 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3 8623 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT 2 8624 #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 8625 #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 8626 #define XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 8627 #define XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 6 8628 #define XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 8629 #define XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 7 8630 u8 flags8; 8631 #define XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 8632 #define XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0 8633 #define XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 8634 #define XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 1 8635 #define XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 8636 #define XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 2 8637 #define XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 8638 #define XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 3 8639 #define XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 8640 #define XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 4 8641 #define XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 8642 #define XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 5 8643 #define XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 8644 #define XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 6 8645 #define XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 8646 #define XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 7 8647 u8 flags9; 8648 #define XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 8649 #define XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0 8650 #define XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1 8651 #define XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT 1 8652 #define XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1 8653 #define XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT 2 8654 #define XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1 8655 #define XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT 3 8656 #define XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1 8657 #define XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT 4 8658 #define XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1 8659 #define XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT 5 8660 #define XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1 8661 #define XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT 6 8662 #define XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1 8663 #define XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT 7 8664 u8 flags10; 8665 #define XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1 8666 #define XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0 8667 #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 8668 #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT 1 8669 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 8670 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 8671 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1 8672 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT 3 8673 #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 8674 #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 8675 #define XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1 8676 #define XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT 5 8677 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1 8678 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT 6 8679 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1 8680 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT 7 8681 u8 flags11; 8682 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1 8683 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0 8684 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1 8685 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT 1 8686 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1 8687 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT 2 8688 #define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 8689 #define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 3 8690 #define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 8691 #define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 4 8692 #define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 8693 #define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 5 8694 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 8695 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 8696 #define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1 8697 #define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7 8698 u8 flags12; 8699 #define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1 8700 #define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0 8701 #define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1 8702 #define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT 1 8703 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 8704 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 8705 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 8706 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 8707 #define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1 8708 #define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT 4 8709 #define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1 8710 #define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT 5 8711 #define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1 8712 #define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT 6 8713 #define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1 8714 #define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT 7 8715 u8 flags13; 8716 #define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1 8717 #define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0 8718 #define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1 8719 #define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT 1 8720 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 8721 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 8722 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 8723 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 8724 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 8725 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 8726 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 8727 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 8728 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 8729 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 8730 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 8731 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 8732 u8 flags14; 8733 #define XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1 8734 #define XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0 8735 #define XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1 8736 #define XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT 1 8737 #define XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1 8738 #define XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT 2 8739 #define XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1 8740 #define XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT 3 8741 #define XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1 8742 #define XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT 4 8743 #define XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1 8744 #define XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT 5 8745 #define XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3 8746 #define XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT 6 8747 u8 byte2; 8748 __le16 physical_q0; 8749 __le16 word1; 8750 __le16 word2; 8751 __le16 sq_cons; 8752 __le16 sq_prod; 8753 __le16 xferq_prod; 8754 __le16 xferq_cons; 8755 u8 byte3; 8756 u8 byte4; 8757 u8 byte5; 8758 u8 byte6; 8759 __le32 remain_io; 8760 __le32 reg1; 8761 __le32 reg2; 8762 __le32 reg3; 8763 __le32 reg4; 8764 __le32 reg5; 8765 __le32 reg6; 8766 __le16 respq_prod; 8767 __le16 respq_cons; 8768 __le16 word9; 8769 __le16 word10; 8770 __le32 reg7; 8771 __le32 reg8; 8772 }; 8773 8774 /* The fcoe storm context of Ustorm */ 8775 struct ustorm_fcoe_conn_st_ctx { 8776 struct regpair respq_pbl_addr; 8777 __le16 num_pages_in_pbl; 8778 u8 ptu_log_page_size; 8779 u8 log_page_size; 8780 __le16 respq_prod; 8781 u8 reserved[2]; 8782 }; 8783 8784 struct tstorm_fcoe_conn_ag_ctx { 8785 u8 reserved0; 8786 u8 state; 8787 u8 flags0; 8788 #define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 8789 #define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 8790 #define TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 8791 #define TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 8792 #define TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1 8793 #define TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT 2 8794 #define TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1 8795 #define TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT 3 8796 #define TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1 8797 #define TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT 4 8798 #define TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1 8799 #define TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT 5 8800 #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3 8801 #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT 6 8802 u8 flags1; 8803 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 8804 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0 8805 #define TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 8806 #define TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 2 8807 #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 8808 #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 8809 #define TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 8810 #define TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 6 8811 u8 flags2; 8812 #define TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 8813 #define TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0 8814 #define TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 8815 #define TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 2 8816 #define TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3 8817 #define TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 4 8818 #define TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3 8819 #define TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 6 8820 u8 flags3; 8821 #define TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3 8822 #define TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0 8823 #define TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3 8824 #define TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 2 8825 #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1 8826 #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT 4 8827 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 8828 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 8829 #define TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 8830 #define TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 6 8831 #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 8832 #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 8833 u8 flags4; 8834 #define TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 8835 #define TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0 8836 #define TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 8837 #define TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 1 8838 #define TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 8839 #define TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 2 8840 #define TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 8841 #define TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 3 8842 #define TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 8843 #define TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 4 8844 #define TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 8845 #define TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 5 8846 #define TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 8847 #define TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 6 8848 #define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 8849 #define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7 8850 u8 flags5; 8851 #define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 8852 #define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0 8853 #define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 8854 #define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1 8855 #define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 8856 #define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2 8857 #define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 8858 #define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3 8859 #define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 8860 #define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4 8861 #define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 8862 #define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5 8863 #define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 8864 #define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6 8865 #define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 8866 #define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7 8867 __le32 reg0; 8868 __le32 reg1; 8869 }; 8870 8871 struct ustorm_fcoe_conn_ag_ctx { 8872 u8 byte0; 8873 u8 byte1; 8874 u8 flags0; 8875 #define USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 8876 #define USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 8877 #define USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 8878 #define USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 8879 #define USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 8880 #define USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 8881 #define USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 8882 #define USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 8883 #define USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 8884 #define USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 8885 u8 flags1; 8886 #define USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3 8887 #define USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0 8888 #define USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 8889 #define USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 2 8890 #define USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 8891 #define USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 4 8892 #define USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 8893 #define USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 6 8894 u8 flags2; 8895 #define USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 8896 #define USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 8897 #define USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 8898 #define USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 8899 #define USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 8900 #define USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 8901 #define USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 8902 #define USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 3 8903 #define USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 8904 #define USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 4 8905 #define USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 8906 #define USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 5 8907 #define USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 8908 #define USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 6 8909 #define USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 8910 #define USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7 8911 u8 flags3; 8912 #define USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 8913 #define USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0 8914 #define USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 8915 #define USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1 8916 #define USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 8917 #define USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2 8918 #define USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 8919 #define USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3 8920 #define USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 8921 #define USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4 8922 #define USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 8923 #define USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5 8924 #define USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 8925 #define USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6 8926 #define USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 8927 #define USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7 8928 u8 byte2; 8929 u8 byte3; 8930 __le16 word0; 8931 __le16 word1; 8932 __le32 reg0; 8933 __le32 reg1; 8934 __le32 reg2; 8935 __le32 reg3; 8936 __le16 word2; 8937 __le16 word3; 8938 }; 8939 8940 /* The fcoe storm context of Tstorm */ 8941 struct tstorm_fcoe_conn_st_ctx { 8942 __le16 stat_ram_addr; 8943 __le16 rx_max_fc_payload_len; 8944 __le16 e_d_tov_val; 8945 u8 flags; 8946 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK 0x1 8947 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT 0 8948 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK 0x1 8949 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT 1 8950 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK 0x3F 8951 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT 2 8952 u8 timers_cleanup_invocation_cnt; 8953 __le32 reserved1[2]; 8954 __le32 dst_mac_address_bytes_0_to_3; 8955 __le16 dst_mac_address_bytes_4_to_5; 8956 __le16 ramrod_echo; 8957 u8 flags1; 8958 #define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK 0x3 8959 #define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT 0 8960 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x3F 8961 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 2 8962 u8 cq_relative_offset; 8963 u8 cmdq_relative_offset; 8964 u8 bdq_resource_id; 8965 u8 reserved0[4]; 8966 }; 8967 8968 struct mstorm_fcoe_conn_ag_ctx { 8969 u8 byte0; 8970 u8 byte1; 8971 u8 flags0; 8972 #define MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 8973 #define MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 8974 #define MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 8975 #define MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 8976 #define MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 8977 #define MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 8978 #define MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 8979 #define MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 8980 #define MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 8981 #define MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 8982 u8 flags1; 8983 #define MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 8984 #define MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 8985 #define MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 8986 #define MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 8987 #define MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 8988 #define MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 8989 #define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 8990 #define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3 8991 #define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 8992 #define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4 8993 #define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 8994 #define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5 8995 #define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 8996 #define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6 8997 #define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 8998 #define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7 8999 __le16 word0; 9000 __le16 word1; 9001 __le32 reg0; 9002 __le32 reg1; 9003 }; 9004 9005 /* Fast path part of the fcoe storm context of Mstorm */ 9006 struct fcoe_mstorm_fcoe_conn_st_ctx_fp { 9007 __le16 xfer_prod; 9008 u8 num_cqs; 9009 u8 reserved1; 9010 u8 protection_info; 9011 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK 0x1 9012 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_SHIFT 0 9013 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK 0x1 9014 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_SHIFT 1 9015 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_MASK 0x3F 9016 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_SHIFT 2 9017 u8 q_relative_offset; 9018 u8 reserved2[2]; 9019 }; 9020 9021 /* Non fast path part of the fcoe storm context of Mstorm */ 9022 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp { 9023 __le16 conn_id; 9024 __le16 stat_ram_addr; 9025 __le16 num_pages_in_pbl; 9026 u8 ptu_log_page_size; 9027 u8 log_page_size; 9028 __le16 unsolicited_cq_count; 9029 __le16 cmdq_count; 9030 u8 bdq_resource_id; 9031 u8 reserved0[3]; 9032 struct regpair xferq_pbl_addr; 9033 struct regpair reserved1; 9034 struct regpair reserved2[3]; 9035 }; 9036 9037 /* The fcoe storm context of Mstorm */ 9038 struct mstorm_fcoe_conn_st_ctx { 9039 struct fcoe_mstorm_fcoe_conn_st_ctx_fp fp; 9040 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp non_fp; 9041 }; 9042 9043 /* fcoe connection context */ 9044 struct fcoe_conn_context { 9045 struct ystorm_fcoe_conn_st_ctx ystorm_st_context; 9046 struct pstorm_fcoe_conn_st_ctx pstorm_st_context; 9047 struct regpair pstorm_st_padding[2]; 9048 struct xstorm_fcoe_conn_st_ctx xstorm_st_context; 9049 struct xstorm_fcoe_conn_ag_ctx xstorm_ag_context; 9050 struct regpair xstorm_ag_padding[6]; 9051 struct ustorm_fcoe_conn_st_ctx ustorm_st_context; 9052 struct regpair ustorm_st_padding[2]; 9053 struct tstorm_fcoe_conn_ag_ctx tstorm_ag_context; 9054 struct regpair tstorm_ag_padding[2]; 9055 struct timers_context timer_context; 9056 struct ustorm_fcoe_conn_ag_ctx ustorm_ag_context; 9057 struct tstorm_fcoe_conn_st_ctx tstorm_st_context; 9058 struct mstorm_fcoe_conn_ag_ctx mstorm_ag_context; 9059 struct mstorm_fcoe_conn_st_ctx mstorm_st_context; 9060 }; 9061 9062 /* FCoE connection offload params passed by driver to FW in FCoE offload 9063 * ramrod. 9064 */ 9065 struct fcoe_conn_offload_ramrod_params { 9066 struct fcoe_conn_offload_ramrod_data offload_ramrod_data; 9067 }; 9068 9069 /* FCoE connection terminate params passed by driver to FW in FCoE terminate 9070 * conn ramrod. 9071 */ 9072 struct fcoe_conn_terminate_ramrod_params { 9073 struct fcoe_conn_terminate_ramrod_data terminate_ramrod_data; 9074 }; 9075 9076 /* FCoE event type */ 9077 enum fcoe_event_type { 9078 FCOE_EVENT_INIT_FUNC, 9079 FCOE_EVENT_DESTROY_FUNC, 9080 FCOE_EVENT_STAT_FUNC, 9081 FCOE_EVENT_OFFLOAD_CONN, 9082 FCOE_EVENT_TERMINATE_CONN, 9083 FCOE_EVENT_ERROR, 9084 MAX_FCOE_EVENT_TYPE 9085 }; 9086 9087 /* FCoE init params passed by driver to FW in FCoE init ramrod */ 9088 struct fcoe_init_ramrod_params { 9089 struct fcoe_init_func_ramrod_data init_ramrod_data; 9090 }; 9091 9092 /* FCoE ramrod Command IDs */ 9093 enum fcoe_ramrod_cmd_id { 9094 FCOE_RAMROD_CMD_ID_INIT_FUNC, 9095 FCOE_RAMROD_CMD_ID_DESTROY_FUNC, 9096 FCOE_RAMROD_CMD_ID_STAT_FUNC, 9097 FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, 9098 FCOE_RAMROD_CMD_ID_TERMINATE_CONN, 9099 MAX_FCOE_RAMROD_CMD_ID 9100 }; 9101 9102 /* FCoE statistics params buffer passed by driver to FW in FCoE statistics 9103 * ramrod. 9104 */ 9105 struct fcoe_stat_ramrod_params { 9106 struct fcoe_stat_ramrod_data stat_ramrod_data; 9107 }; 9108 9109 struct ystorm_fcoe_conn_ag_ctx { 9110 u8 byte0; 9111 u8 byte1; 9112 u8 flags0; 9113 #define YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 9114 #define YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 9115 #define YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 9116 #define YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 9117 #define YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 9118 #define YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 9119 #define YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 9120 #define YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 9121 #define YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 9122 #define YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 9123 u8 flags1; 9124 #define YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 9125 #define YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 9126 #define YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 9127 #define YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 9128 #define YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 9129 #define YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 9130 #define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 9131 #define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3 9132 #define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 9133 #define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4 9134 #define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 9135 #define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5 9136 #define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 9137 #define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6 9138 #define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 9139 #define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7 9140 u8 byte2; 9141 u8 byte3; 9142 __le16 word0; 9143 __le32 reg0; 9144 __le32 reg1; 9145 __le16 word1; 9146 __le16 word2; 9147 __le16 word3; 9148 __le16 word4; 9149 __le32 reg2; 9150 __le32 reg3; 9151 }; 9152 9153 /* The iscsi storm connection context of Ystorm */ 9154 struct ystorm_iscsi_conn_st_ctx { 9155 __le32 reserved[8]; 9156 }; 9157 9158 /* Combined iSCSI and TCP storm connection of Pstorm */ 9159 struct pstorm_iscsi_tcp_conn_st_ctx { 9160 __le32 tcp[32]; 9161 __le32 iscsi[4]; 9162 }; 9163 9164 /* The combined tcp and iscsi storm context of Xstorm */ 9165 struct xstorm_iscsi_tcp_conn_st_ctx { 9166 __le32 reserved_tcp[4]; 9167 __le32 reserved_iscsi[44]; 9168 }; 9169 9170 struct xstorm_iscsi_conn_ag_ctx { 9171 u8 cdu_validation; 9172 u8 state; 9173 u8 flags0; 9174 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 9175 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 9176 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1 9177 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1 9178 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1 9179 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_SHIFT 2 9180 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 9181 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 9182 #define XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1 9183 #define XSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4 9184 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1 9185 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_SHIFT 5 9186 #define XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1 9187 #define XSTORM_ISCSI_CONN_AG_CTX_BIT6_SHIFT 6 9188 #define XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1 9189 #define XSTORM_ISCSI_CONN_AG_CTX_BIT7_SHIFT 7 9190 u8 flags1; 9191 #define XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1 9192 #define XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT 0 9193 #define XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK 0x1 9194 #define XSTORM_ISCSI_CONN_AG_CTX_BIT9_SHIFT 1 9195 #define XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK 0x1 9196 #define XSTORM_ISCSI_CONN_AG_CTX_BIT10_SHIFT 2 9197 #define XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK 0x1 9198 #define XSTORM_ISCSI_CONN_AG_CTX_BIT11_SHIFT 3 9199 #define XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK 0x1 9200 #define XSTORM_ISCSI_CONN_AG_CTX_BIT12_SHIFT 4 9201 #define XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK 0x1 9202 #define XSTORM_ISCSI_CONN_AG_CTX_BIT13_SHIFT 5 9203 #define XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK 0x1 9204 #define XSTORM_ISCSI_CONN_AG_CTX_BIT14_SHIFT 6 9205 #define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK 0x1 9206 #define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_SHIFT 7 9207 u8 flags2; 9208 #define XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 9209 #define XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 0 9210 #define XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 9211 #define XSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 2 9212 #define XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 9213 #define XSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 4 9214 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 9215 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6 9216 u8 flags3; 9217 #define XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3 9218 #define XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 0 9219 #define XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3 9220 #define XSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 2 9221 #define XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3 9222 #define XSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 4 9223 #define XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3 9224 #define XSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 6 9225 u8 flags4; 9226 #define XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3 9227 #define XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 0 9228 #define XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3 9229 #define XSTORM_ISCSI_CONN_AG_CTX_CF9_SHIFT 2 9230 #define XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3 9231 #define XSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 4 9232 #define XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK 0x3 9233 #define XSTORM_ISCSI_CONN_AG_CTX_CF11_SHIFT 6 9234 u8 flags5; 9235 #define XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK 0x3 9236 #define XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT 0 9237 #define XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK 0x3 9238 #define XSTORM_ISCSI_CONN_AG_CTX_CF13_SHIFT 2 9239 #define XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK 0x3 9240 #define XSTORM_ISCSI_CONN_AG_CTX_CF14_SHIFT 4 9241 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK 0x3 9242 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_SHIFT 6 9243 u8 flags6; 9244 #define XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK 0x3 9245 #define XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT 0 9246 #define XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK 0x3 9247 #define XSTORM_ISCSI_CONN_AG_CTX_CF17_SHIFT 2 9248 #define XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK 0x3 9249 #define XSTORM_ISCSI_CONN_AG_CTX_CF18_SHIFT 4 9250 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 9251 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_SHIFT 6 9252 u8 flags7; 9253 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK 0x3 9254 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_SHIFT 0 9255 #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK 0x3 9256 #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_SHIFT 2 9257 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK 0x3 9258 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_SHIFT 4 9259 #define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 9260 #define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 6 9261 #define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 9262 #define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 7 9263 u8 flags8; 9264 #define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 9265 #define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 0 9266 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 9267 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1 9268 #define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1 9269 #define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 2 9270 #define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1 9271 #define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 3 9272 #define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1 9273 #define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 4 9274 #define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1 9275 #define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 5 9276 #define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1 9277 #define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 6 9278 #define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK 0x1 9279 #define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_SHIFT 7 9280 u8 flags9; 9281 #define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1 9282 #define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 0 9283 #define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK 0x1 9284 #define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_SHIFT 1 9285 #define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK 0x1 9286 #define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_SHIFT 2 9287 #define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK 0x1 9288 #define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_SHIFT 3 9289 #define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK 0x1 9290 #define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_SHIFT 4 9291 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK 0x1 9292 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_SHIFT 5 9293 #define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK 0x1 9294 #define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_SHIFT 6 9295 #define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK 0x1 9296 #define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_SHIFT 7 9297 u8 flags10; 9298 #define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK 0x1 9299 #define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT 0 9300 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1 9301 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1 9302 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK 0x1 9303 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_SHIFT 2 9304 #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK 0x1 9305 #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_SHIFT 3 9306 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 9307 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 9308 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK 0x1 9309 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_SHIFT 5 9310 #define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 9311 #define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 6 9312 #define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK 0x1 9313 #define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_SHIFT 7 9314 u8 flags11; 9315 #define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1 9316 #define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0 9317 #define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 9318 #define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 1 9319 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK 0x1 9320 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_SHIFT 2 9321 #define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1 9322 #define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 3 9323 #define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1 9324 #define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 4 9325 #define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1 9326 #define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 5 9327 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 9328 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 9329 #define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK 0x1 9330 #define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_SHIFT 7 9331 u8 flags12; 9332 #define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK 0x1 9333 #define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT 0 9334 #define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK 0x1 9335 #define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_SHIFT 1 9336 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 9337 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 9338 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 9339 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 9340 #define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK 0x1 9341 #define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_SHIFT 4 9342 #define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK 0x1 9343 #define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_SHIFT 5 9344 #define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK 0x1 9345 #define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_SHIFT 6 9346 #define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK 0x1 9347 #define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_SHIFT 7 9348 u8 flags13; 9349 #define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK 0x1 9350 #define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT 0 9351 #define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK 0x1 9352 #define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_SHIFT 1 9353 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 9354 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 9355 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 9356 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 9357 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 9358 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 9359 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 9360 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 9361 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 9362 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 9363 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 9364 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 9365 u8 flags14; 9366 #define XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK 0x1 9367 #define XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT 0 9368 #define XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK 0x1 9369 #define XSTORM_ISCSI_CONN_AG_CTX_BIT17_SHIFT 1 9370 #define XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK 0x1 9371 #define XSTORM_ISCSI_CONN_AG_CTX_BIT18_SHIFT 2 9372 #define XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK 0x1 9373 #define XSTORM_ISCSI_CONN_AG_CTX_BIT19_SHIFT 3 9374 #define XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK 0x1 9375 #define XSTORM_ISCSI_CONN_AG_CTX_BIT20_SHIFT 4 9376 #define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK 0x1 9377 #define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_SHIFT 5 9378 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK 0x3 9379 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_SHIFT 6 9380 u8 byte2; 9381 __le16 physical_q0; 9382 __le16 physical_q1; 9383 __le16 dummy_dorq_var; 9384 __le16 sq_cons; 9385 __le16 sq_prod; 9386 __le16 word5; 9387 __le16 slow_io_total_data_tx_update; 9388 u8 byte3; 9389 u8 byte4; 9390 u8 byte5; 9391 u8 byte6; 9392 __le32 reg0; 9393 __le32 reg1; 9394 __le32 reg2; 9395 __le32 more_to_send_seq; 9396 __le32 reg4; 9397 __le32 reg5; 9398 __le32 hq_scan_next_relevant_ack; 9399 __le16 r2tq_prod; 9400 __le16 r2tq_cons; 9401 __le16 hq_prod; 9402 __le16 hq_cons; 9403 __le32 remain_seq; 9404 __le32 bytes_to_next_pdu; 9405 __le32 hq_tcp_seq; 9406 u8 byte7; 9407 u8 byte8; 9408 u8 byte9; 9409 u8 byte10; 9410 u8 byte11; 9411 u8 byte12; 9412 u8 byte13; 9413 u8 byte14; 9414 u8 byte15; 9415 u8 e5_reserved; 9416 __le16 word11; 9417 __le32 reg10; 9418 __le32 reg11; 9419 __le32 exp_stat_sn; 9420 __le32 ongoing_fast_rxmit_seq; 9421 __le32 reg14; 9422 __le32 reg15; 9423 __le32 reg16; 9424 __le32 reg17; 9425 }; 9426 9427 struct tstorm_iscsi_conn_ag_ctx { 9428 u8 reserved0; 9429 u8 state; 9430 u8 flags0; 9431 #define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 9432 #define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 9433 #define TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 9434 #define TSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 9435 #define TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK 0x1 9436 #define TSTORM_ISCSI_CONN_AG_CTX_BIT2_SHIFT 2 9437 #define TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK 0x1 9438 #define TSTORM_ISCSI_CONN_AG_CTX_BIT3_SHIFT 3 9439 #define TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1 9440 #define TSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4 9441 #define TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK 0x1 9442 #define TSTORM_ISCSI_CONN_AG_CTX_BIT5_SHIFT 5 9443 #define TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 9444 #define TSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 6 9445 u8 flags1; 9446 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK 0x3 9447 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_SHIFT 0 9448 #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK 0x3 9449 #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_SHIFT 2 9450 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 9451 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4 9452 #define TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3 9453 #define TSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 6 9454 u8 flags2; 9455 #define TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3 9456 #define TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 0 9457 #define TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3 9458 #define TSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 2 9459 #define TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3 9460 #define TSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 4 9461 #define TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3 9462 #define TSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 6 9463 u8 flags3; 9464 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 9465 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 9466 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_MASK 0x3 9467 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_SHIFT 2 9468 #define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 9469 #define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 4 9470 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK 0x1 9471 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_SHIFT 5 9472 #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK 0x1 9473 #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_SHIFT 6 9474 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 9475 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7 9476 u8 flags4; 9477 #define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1 9478 #define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 0 9479 #define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1 9480 #define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 1 9481 #define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1 9482 #define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 2 9483 #define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1 9484 #define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 3 9485 #define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1 9486 #define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 4 9487 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 9488 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5 9489 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_EN_MASK 0x1 9490 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_EN_SHIFT 6 9491 #define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 9492 #define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7 9493 u8 flags5; 9494 #define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 9495 #define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0 9496 #define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 9497 #define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1 9498 #define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 9499 #define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2 9500 #define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 9501 #define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3 9502 #define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1 9503 #define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4 9504 #define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1 9505 #define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5 9506 #define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1 9507 #define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6 9508 #define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1 9509 #define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7 9510 __le32 reg0; 9511 __le32 reg1; 9512 __le32 rx_tcp_checksum_err_cnt; 9513 __le32 reg3; 9514 __le32 reg4; 9515 __le32 reg5; 9516 __le32 reg6; 9517 __le32 reg7; 9518 __le32 reg8; 9519 u8 cid_offload_cnt; 9520 u8 byte3; 9521 __le16 word0; 9522 }; 9523 9524 struct ustorm_iscsi_conn_ag_ctx { 9525 u8 byte0; 9526 u8 byte1; 9527 u8 flags0; 9528 #define USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1 9529 #define USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0 9530 #define USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 9531 #define USTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 9532 #define USTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 9533 #define USTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2 9534 #define USTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 9535 #define USTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4 9536 #define USTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 9537 #define USTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6 9538 u8 flags1; 9539 #define USTORM_ISCSI_CONN_AG_CTX_CF3_MASK 0x3 9540 #define USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT 0 9541 #define USTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3 9542 #define USTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 2 9543 #define USTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3 9544 #define USTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 4 9545 #define USTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3 9546 #define USTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 6 9547 u8 flags2; 9548 #define USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 9549 #define USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0 9550 #define USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 9551 #define USTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1 9552 #define USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 9553 #define USTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2 9554 #define USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK 0x1 9555 #define USTORM_ISCSI_CONN_AG_CTX_CF3EN_SHIFT 3 9556 #define USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1 9557 #define USTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 4 9558 #define USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1 9559 #define USTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 5 9560 #define USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1 9561 #define USTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 6 9562 #define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 9563 #define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7 9564 u8 flags3; 9565 #define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 9566 #define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0 9567 #define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 9568 #define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1 9569 #define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 9570 #define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2 9571 #define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 9572 #define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3 9573 #define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1 9574 #define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4 9575 #define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1 9576 #define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5 9577 #define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1 9578 #define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6 9579 #define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1 9580 #define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7 9581 u8 byte2; 9582 u8 byte3; 9583 __le16 word0; 9584 __le16 word1; 9585 __le32 reg0; 9586 __le32 reg1; 9587 __le32 reg2; 9588 __le32 reg3; 9589 __le16 word2; 9590 __le16 word3; 9591 }; 9592 9593 /* The iscsi storm connection context of Tstorm */ 9594 struct tstorm_iscsi_conn_st_ctx { 9595 __le32 reserved[44]; 9596 }; 9597 9598 struct mstorm_iscsi_conn_ag_ctx { 9599 u8 reserved; 9600 u8 state; 9601 u8 flags0; 9602 #define MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1 9603 #define MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0 9604 #define MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 9605 #define MSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 9606 #define MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 9607 #define MSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2 9608 #define MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 9609 #define MSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4 9610 #define MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 9611 #define MSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6 9612 u8 flags1; 9613 #define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 9614 #define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0 9615 #define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 9616 #define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1 9617 #define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 9618 #define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2 9619 #define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 9620 #define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3 9621 #define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 9622 #define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4 9623 #define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 9624 #define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5 9625 #define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 9626 #define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6 9627 #define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 9628 #define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7 9629 __le16 word0; 9630 __le16 word1; 9631 __le32 reg0; 9632 __le32 reg1; 9633 }; 9634 9635 /* Combined iSCSI and TCP storm connection of Mstorm */ 9636 struct mstorm_iscsi_tcp_conn_st_ctx { 9637 __le32 reserved_tcp[20]; 9638 __le32 reserved_iscsi[12]; 9639 }; 9640 9641 /* The iscsi storm context of Ustorm */ 9642 struct ustorm_iscsi_conn_st_ctx { 9643 __le32 reserved[52]; 9644 }; 9645 9646 /* iscsi connection context */ 9647 struct iscsi_conn_context { 9648 struct ystorm_iscsi_conn_st_ctx ystorm_st_context; 9649 struct pstorm_iscsi_tcp_conn_st_ctx pstorm_st_context; 9650 struct regpair pstorm_st_padding[2]; 9651 struct pb_context xpb2_context; 9652 struct xstorm_iscsi_tcp_conn_st_ctx xstorm_st_context; 9653 struct regpair xstorm_st_padding[2]; 9654 struct xstorm_iscsi_conn_ag_ctx xstorm_ag_context; 9655 struct tstorm_iscsi_conn_ag_ctx tstorm_ag_context; 9656 struct regpair tstorm_ag_padding[2]; 9657 struct timers_context timer_context; 9658 struct ustorm_iscsi_conn_ag_ctx ustorm_ag_context; 9659 struct pb_context upb_context; 9660 struct tstorm_iscsi_conn_st_ctx tstorm_st_context; 9661 struct regpair tstorm_st_padding[2]; 9662 struct mstorm_iscsi_conn_ag_ctx mstorm_ag_context; 9663 struct mstorm_iscsi_tcp_conn_st_ctx mstorm_st_context; 9664 struct ustorm_iscsi_conn_st_ctx ustorm_st_context; 9665 }; 9666 9667 /* iSCSI init params passed by driver to FW in iSCSI init ramrod */ 9668 struct iscsi_init_ramrod_params { 9669 struct iscsi_spe_func_init iscsi_init_spe; 9670 struct tcp_init_params tcp_init; 9671 }; 9672 9673 struct ystorm_iscsi_conn_ag_ctx { 9674 u8 byte0; 9675 u8 byte1; 9676 u8 flags0; 9677 #define YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1 9678 #define YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0 9679 #define YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 9680 #define YSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 9681 #define YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 9682 #define YSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2 9683 #define YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 9684 #define YSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4 9685 #define YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 9686 #define YSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6 9687 u8 flags1; 9688 #define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 9689 #define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0 9690 #define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 9691 #define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1 9692 #define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 9693 #define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2 9694 #define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 9695 #define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3 9696 #define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 9697 #define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4 9698 #define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 9699 #define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5 9700 #define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 9701 #define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6 9702 #define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 9703 #define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7 9704 u8 byte2; 9705 u8 byte3; 9706 __le16 word0; 9707 __le32 reg0; 9708 __le32 reg1; 9709 __le16 word1; 9710 __le16 word2; 9711 __le16 word3; 9712 __le16 word4; 9713 __le32 reg2; 9714 __le32 reg3; 9715 }; 9716 9717 #endif 9718