1 /* QLogic qed NIC Driver
2  * Copyright (c) 2015-2017  QLogic Corporation
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and /or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #ifndef _QED_HSI_H
34 #define _QED_HSI_H
35 
36 #include <linux/types.h>
37 #include <linux/io.h>
38 #include <linux/bitops.h>
39 #include <linux/delay.h>
40 #include <linux/kernel.h>
41 #include <linux/list.h>
42 #include <linux/slab.h>
43 #include <linux/qed/common_hsi.h>
44 #include <linux/qed/storage_common.h>
45 #include <linux/qed/tcp_common.h>
46 #include <linux/qed/fcoe_common.h>
47 #include <linux/qed/eth_common.h>
48 #include <linux/qed/iscsi_common.h>
49 #include <linux/qed/iwarp_common.h>
50 #include <linux/qed/rdma_common.h>
51 #include <linux/qed/roce_common.h>
52 #include <linux/qed/qed_fcoe_if.h>
53 
54 struct qed_hwfn;
55 struct qed_ptt;
56 
57 /* Opcodes for the event ring */
58 enum common_event_opcode {
59 	COMMON_EVENT_PF_START,
60 	COMMON_EVENT_PF_STOP,
61 	COMMON_EVENT_VF_START,
62 	COMMON_EVENT_VF_STOP,
63 	COMMON_EVENT_VF_PF_CHANNEL,
64 	COMMON_EVENT_VF_FLR,
65 	COMMON_EVENT_PF_UPDATE,
66 	COMMON_EVENT_MALICIOUS_VF,
67 	COMMON_EVENT_RL_UPDATE,
68 	COMMON_EVENT_EMPTY,
69 	MAX_COMMON_EVENT_OPCODE
70 };
71 
72 /* Common Ramrod Command IDs */
73 enum common_ramrod_cmd_id {
74 	COMMON_RAMROD_UNUSED,
75 	COMMON_RAMROD_PF_START,
76 	COMMON_RAMROD_PF_STOP,
77 	COMMON_RAMROD_VF_START,
78 	COMMON_RAMROD_VF_STOP,
79 	COMMON_RAMROD_PF_UPDATE,
80 	COMMON_RAMROD_RL_UPDATE,
81 	COMMON_RAMROD_EMPTY,
82 	MAX_COMMON_RAMROD_CMD_ID
83 };
84 
85 /* How ll2 should deal with packet upon errors */
86 enum core_error_handle {
87 	LL2_DROP_PACKET,
88 	LL2_DO_NOTHING,
89 	LL2_ASSERT,
90 	MAX_CORE_ERROR_HANDLE
91 };
92 
93 /* Opcodes for the event ring */
94 enum core_event_opcode {
95 	CORE_EVENT_TX_QUEUE_START,
96 	CORE_EVENT_TX_QUEUE_STOP,
97 	CORE_EVENT_RX_QUEUE_START,
98 	CORE_EVENT_RX_QUEUE_STOP,
99 	CORE_EVENT_RX_QUEUE_FLUSH,
100 	CORE_EVENT_TX_QUEUE_UPDATE,
101 	CORE_EVENT_QUEUE_STATS_QUERY,
102 	MAX_CORE_EVENT_OPCODE
103 };
104 
105 /* The L4 pseudo checksum mode for Core */
106 enum core_l4_pseudo_checksum_mode {
107 	CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH,
108 	CORE_L4_PSEUDO_CSUM_ZERO_LENGTH,
109 	MAX_CORE_L4_PSEUDO_CHECKSUM_MODE
110 };
111 
112 /* Light-L2 RX Producers in Tstorm RAM */
113 struct core_ll2_port_stats {
114 	struct regpair gsi_invalid_hdr;
115 	struct regpair gsi_invalid_pkt_length;
116 	struct regpair gsi_unsupported_pkt_typ;
117 	struct regpair gsi_crcchksm_error;
118 };
119 
120 /* LL2 TX Per Queue Stats */
121 struct core_ll2_pstorm_per_queue_stat {
122 	struct regpair sent_ucast_bytes;
123 	struct regpair sent_mcast_bytes;
124 	struct regpair sent_bcast_bytes;
125 	struct regpair sent_ucast_pkts;
126 	struct regpair sent_mcast_pkts;
127 	struct regpair sent_bcast_pkts;
128 	struct regpair error_drop_pkts;
129 };
130 
131 /* Light-L2 RX Producers in Tstorm RAM */
132 struct core_ll2_rx_prod {
133 	__le16 bd_prod;
134 	__le16 cqe_prod;
135 };
136 
137 struct core_ll2_tstorm_per_queue_stat {
138 	struct regpair packet_too_big_discard;
139 	struct regpair no_buff_discard;
140 };
141 
142 struct core_ll2_ustorm_per_queue_stat {
143 	struct regpair rcv_ucast_bytes;
144 	struct regpair rcv_mcast_bytes;
145 	struct regpair rcv_bcast_bytes;
146 	struct regpair rcv_ucast_pkts;
147 	struct regpair rcv_mcast_pkts;
148 	struct regpair rcv_bcast_pkts;
149 };
150 
151 /* Structure for doorbell data, in PWM mode, for RX producers update. */
152 struct core_pwm_prod_update_data {
153 	__le16 icid; /* internal CID */
154 	u8 reserved0;
155 	u8 params;
156 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_MASK	  0x3
157 #define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_SHIFT   0
158 #define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_MASK  0x3F	/* Set 0 */
159 #define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_SHIFT 2
160 	struct core_ll2_rx_prod prod; /* Producers */
161 };
162 
163 /* Core Ramrod Command IDs (light L2) */
164 enum core_ramrod_cmd_id {
165 	CORE_RAMROD_UNUSED,
166 	CORE_RAMROD_RX_QUEUE_START,
167 	CORE_RAMROD_TX_QUEUE_START,
168 	CORE_RAMROD_RX_QUEUE_STOP,
169 	CORE_RAMROD_TX_QUEUE_STOP,
170 	CORE_RAMROD_RX_QUEUE_FLUSH,
171 	CORE_RAMROD_TX_QUEUE_UPDATE,
172 	CORE_RAMROD_QUEUE_STATS_QUERY,
173 	MAX_CORE_RAMROD_CMD_ID
174 };
175 
176 /* Core RX CQE Type for Light L2 */
177 enum core_roce_flavor_type {
178 	CORE_ROCE,
179 	CORE_RROCE,
180 	MAX_CORE_ROCE_FLAVOR_TYPE
181 };
182 
183 /* Specifies how ll2 should deal with packets errors: packet_too_big and
184  * no_buff.
185  */
186 struct core_rx_action_on_error {
187 	u8 error_type;
188 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK	0x3
189 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT	0
190 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK		0x3
191 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT		2
192 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK		0xF
193 #define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT		4
194 };
195 
196 /* Core RX BD for Light L2 */
197 struct core_rx_bd {
198 	struct regpair addr;
199 	__le16 reserved[4];
200 };
201 
202 /* Core RX CM offload BD for Light L2 */
203 struct core_rx_bd_with_buff_len {
204 	struct regpair addr;
205 	__le16 buff_length;
206 	__le16 reserved[3];
207 };
208 
209 /* Core RX CM offload BD for Light L2 */
210 union core_rx_bd_union {
211 	struct core_rx_bd rx_bd;
212 	struct core_rx_bd_with_buff_len rx_bd_with_len;
213 };
214 
215 /* Opaque Data for Light L2 RX CQE */
216 struct core_rx_cqe_opaque_data {
217 	__le32 data[2];
218 };
219 
220 /* Core RX CQE Type for Light L2 */
221 enum core_rx_cqe_type {
222 	CORE_RX_CQE_ILLEGAL_TYPE,
223 	CORE_RX_CQE_TYPE_REGULAR,
224 	CORE_RX_CQE_TYPE_GSI_OFFLOAD,
225 	CORE_RX_CQE_TYPE_SLOW_PATH,
226 	MAX_CORE_RX_CQE_TYPE
227 };
228 
229 /* Core RX CQE for Light L2 */
230 struct core_rx_fast_path_cqe {
231 	u8 type;
232 	u8 placement_offset;
233 	struct parsing_and_err_flags parse_flags;
234 	__le16 packet_length;
235 	__le16 vlan;
236 	struct core_rx_cqe_opaque_data opaque_data;
237 	struct parsing_err_flags err_flags;
238 	__le16 reserved0;
239 	__le32 reserved1[3];
240 };
241 
242 /* Core Rx CM offload CQE */
243 struct core_rx_gsi_offload_cqe {
244 	u8 type;
245 	u8 data_length_error;
246 	struct parsing_and_err_flags parse_flags;
247 	__le16 data_length;
248 	__le16 vlan;
249 	__le32 src_mac_addrhi;
250 	__le16 src_mac_addrlo;
251 	__le16 qp_id;
252 	__le32 src_qp;
253 	struct core_rx_cqe_opaque_data opaque_data;
254 	__le32 reserved;
255 };
256 
257 /* Core RX CQE for Light L2 */
258 struct core_rx_slow_path_cqe {
259 	u8 type;
260 	u8 ramrod_cmd_id;
261 	__le16 echo;
262 	struct core_rx_cqe_opaque_data opaque_data;
263 	__le32 reserved1[5];
264 };
265 
266 /* Core RX CM offload BD for Light L2 */
267 union core_rx_cqe_union {
268 	struct core_rx_fast_path_cqe rx_cqe_fp;
269 	struct core_rx_gsi_offload_cqe rx_cqe_gsi;
270 	struct core_rx_slow_path_cqe rx_cqe_sp;
271 };
272 
273 /* Ramrod data for rx queue start ramrod */
274 struct core_rx_start_ramrod_data {
275 	struct regpair bd_base;
276 	struct regpair cqe_pbl_addr;
277 	__le16 mtu;
278 	__le16 sb_id;
279 	u8 sb_index;
280 	u8 complete_cqe_flg;
281 	u8 complete_event_flg;
282 	u8 drop_ttl0_flg;
283 	__le16 num_of_pbl_pages;
284 	u8 inner_vlan_stripping_en;
285 	u8 report_outer_vlan;
286 	u8 queue_id;
287 	u8 main_func_queue;
288 	u8 mf_si_bcast_accept_all;
289 	u8 mf_si_mcast_accept_all;
290 	struct core_rx_action_on_error action_on_error;
291 	u8 gsi_offload_flag;
292 	u8 vport_id_valid;
293 	u8 vport_id;
294 	u8 zero_prod_flg;
295 	u8 wipe_inner_vlan_pri_en;
296 	u8 reserved[2];
297 };
298 
299 /* Ramrod data for rx queue stop ramrod */
300 struct core_rx_stop_ramrod_data {
301 	u8 complete_cqe_flg;
302 	u8 complete_event_flg;
303 	u8 queue_id;
304 	u8 reserved1;
305 	__le16 reserved2[2];
306 };
307 
308 /* Flags for Core TX BD */
309 struct core_tx_bd_data {
310 	__le16 as_bitfield;
311 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK		0x1
312 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT		0
313 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK		0x1
314 #define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT		1
315 #define CORE_TX_BD_DATA_START_BD_MASK			0x1
316 #define CORE_TX_BD_DATA_START_BD_SHIFT			2
317 #define CORE_TX_BD_DATA_IP_CSUM_MASK			0x1
318 #define CORE_TX_BD_DATA_IP_CSUM_SHIFT			3
319 #define CORE_TX_BD_DATA_L4_CSUM_MASK			0x1
320 #define CORE_TX_BD_DATA_L4_CSUM_SHIFT			4
321 #define CORE_TX_BD_DATA_IPV6_EXT_MASK			0x1
322 #define CORE_TX_BD_DATA_IPV6_EXT_SHIFT			5
323 #define CORE_TX_BD_DATA_L4_PROTOCOL_MASK		0x1
324 #define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT		6
325 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK	0x1
326 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT	7
327 #define CORE_TX_BD_DATA_NBDS_MASK			0xF
328 #define CORE_TX_BD_DATA_NBDS_SHIFT			8
329 #define CORE_TX_BD_DATA_ROCE_FLAV_MASK			0x1
330 #define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT			12
331 #define CORE_TX_BD_DATA_IP_LEN_MASK			0x1
332 #define CORE_TX_BD_DATA_IP_LEN_SHIFT			13
333 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_MASK	0x1
334 #define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_SHIFT	14
335 #define CORE_TX_BD_DATA_RESERVED0_MASK			0x1
336 #define CORE_TX_BD_DATA_RESERVED0_SHIFT			15
337 };
338 
339 /* Core TX BD for Light L2 */
340 struct core_tx_bd {
341 	struct regpair addr;
342 	__le16 nbytes;
343 	__le16 nw_vlan_or_lb_echo;
344 	struct core_tx_bd_data bd_data;
345 	__le16 bitfield1;
346 #define CORE_TX_BD_L4_HDR_OFFSET_W_MASK		0x3FFF
347 #define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT	0
348 #define CORE_TX_BD_TX_DST_MASK			0x3
349 #define CORE_TX_BD_TX_DST_SHIFT			14
350 };
351 
352 /* Light L2 TX Destination */
353 enum core_tx_dest {
354 	CORE_TX_DEST_NW,
355 	CORE_TX_DEST_LB,
356 	CORE_TX_DEST_RESERVED,
357 	CORE_TX_DEST_DROP,
358 	MAX_CORE_TX_DEST
359 };
360 
361 /* Ramrod data for tx queue start ramrod */
362 struct core_tx_start_ramrod_data {
363 	struct regpair pbl_base_addr;
364 	__le16 mtu;
365 	__le16 sb_id;
366 	u8 sb_index;
367 	u8 stats_en;
368 	u8 stats_id;
369 	u8 conn_type;
370 	__le16 pbl_size;
371 	__le16 qm_pq_id;
372 	u8 gsi_offload_flag;
373 	u8 ctx_stats_en;
374 	u8 vport_id_valid;
375 	u8 vport_id;
376 	u8 enforce_security_flag;
377 	u8 reserved[7];
378 };
379 
380 /* Ramrod data for tx queue stop ramrod */
381 struct core_tx_stop_ramrod_data {
382 	__le32 reserved0[2];
383 };
384 
385 /* Ramrod data for tx queue update ramrod */
386 struct core_tx_update_ramrod_data {
387 	u8 update_qm_pq_id_flg;
388 	u8 reserved0;
389 	__le16 qm_pq_id;
390 	__le32 reserved1[1];
391 };
392 
393 /* Enum flag for what type of dcb data to update */
394 enum dcb_dscp_update_mode {
395 	DONT_UPDATE_DCB_DSCP,
396 	UPDATE_DCB,
397 	UPDATE_DSCP,
398 	UPDATE_DCB_DSCP,
399 	MAX_DCB_DSCP_UPDATE_MODE
400 };
401 
402 /* The core storm context for the Ystorm */
403 struct ystorm_core_conn_st_ctx {
404 	__le32 reserved[4];
405 };
406 
407 /* The core storm context for the Pstorm */
408 struct pstorm_core_conn_st_ctx {
409 	__le32 reserved[20];
410 };
411 
412 /* Core Slowpath Connection storm context of Xstorm */
413 struct xstorm_core_conn_st_ctx {
414 	__le32 spq_base_lo;
415 	__le32 spq_base_hi;
416 	struct regpair consolid_base_addr;
417 	__le16 spq_cons;
418 	__le16 consolid_cons;
419 	__le32 reserved0[55];
420 };
421 
422 struct e4_xstorm_core_conn_ag_ctx {
423 	u8 reserved0;
424 	u8 state;
425 	u8 flags0;
426 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
427 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
428 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK	0x1
429 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT	1
430 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK	0x1
431 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT	2
432 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
433 #define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT	3
434 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK	0x1
435 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT	4
436 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK	0x1
437 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT	5
438 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK	0x1
439 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT	6
440 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK	0x1
441 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT	7
442 	u8 flags1;
443 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK	0x1
444 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT	0
445 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK	0x1
446 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT	1
447 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK	0x1
448 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT	2
449 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_MASK		0x1
450 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT		3
451 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_MASK		0x1
452 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT		4
453 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_MASK		0x1
454 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT		5
455 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK	0x1
456 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT	6
457 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK	0x1
458 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT	7
459 	u8 flags2;
460 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_MASK	0x3
461 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT	0
462 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_MASK	0x3
463 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT	2
464 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_MASK	0x3
465 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT	4
466 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_MASK	0x3
467 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT	6
468 	u8 flags3;
469 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_MASK	0x3
470 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT	0
471 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_MASK	0x3
472 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT	2
473 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_MASK	0x3
474 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT	4
475 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_MASK	0x3
476 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT	6
477 	u8 flags4;
478 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_MASK	0x3
479 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT	0
480 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_MASK	0x3
481 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT	2
482 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_MASK	0x3
483 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT	4
484 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_MASK	0x3
485 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT	6
486 	u8 flags5;
487 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_MASK	0x3
488 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT	0
489 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_MASK	0x3
490 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT	2
491 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_MASK	0x3
492 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT	4
493 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_MASK	0x3
494 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT	6
495 	u8 flags6;
496 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK	0x3
497 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT	0
498 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_MASK			0x3
499 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT			2
500 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK			0x3
501 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT			4
502 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK		0x3
503 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT		6
504 	u8 flags7;
505 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK	0x3
506 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT	0
507 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK	0x3
508 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT	2
509 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK	0x3
510 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT	4
511 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK		0x1
512 #define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT		6
513 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK		0x1
514 #define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT		7
515 	u8 flags8;
516 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK	0x1
517 #define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT	0
518 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK	0x1
519 #define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT	1
520 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK	0x1
521 #define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT	2
522 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK	0x1
523 #define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT	3
524 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK	0x1
525 #define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT	4
526 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK	0x1
527 #define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT	5
528 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK	0x1
529 #define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT	6
530 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK	0x1
531 #define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT	7
532 	u8 flags9;
533 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK			0x1
534 #define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT			0
535 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK			0x1
536 #define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT			1
537 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK			0x1
538 #define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT			2
539 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK			0x1
540 #define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT			3
541 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK			0x1
542 #define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT			4
543 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK			0x1
544 #define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT			5
545 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK	0x1
546 #define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT	6
547 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK			0x1
548 #define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT			7
549 	u8 flags10;
550 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK		0x1
551 #define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT		0
552 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK		0x1
553 #define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT	1
554 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK		0x1
555 #define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT		2
556 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK		0x1
557 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT		3
558 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK		0x1
559 #define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT		4
560 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK			0x1
561 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT			5
562 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK		0x1
563 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT		6
564 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK		0x1
565 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT		7
566 	u8 flags11;
567 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK	0x1
568 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT	0
569 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK	0x1
570 #define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT	1
571 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK	0x1
572 #define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT	2
573 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK		0x1
574 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT	3
575 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK		0x1
576 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT	4
577 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK		0x1
578 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT	5
579 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK	0x1
580 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT	6
581 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK		0x1
582 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT	7
583 	u8 flags12;
584 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK	0x1
585 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT	0
586 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK	0x1
587 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT	1
588 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK	0x1
589 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT	2
590 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK	0x1
591 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT	3
592 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK	0x1
593 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT	4
594 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK	0x1
595 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT	5
596 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK	0x1
597 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT	6
598 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK	0x1
599 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT	7
600 	u8 flags13;
601 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK	0x1
602 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT	0
603 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK	0x1
604 #define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT	1
605 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK	0x1
606 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT	2
607 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK	0x1
608 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT	3
609 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK	0x1
610 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT	4
611 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK	0x1
612 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT	5
613 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK	0x1
614 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT	6
615 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK	0x1
616 #define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT	7
617 	u8 flags14;
618 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_MASK	0x1
619 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT	0
620 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_MASK	0x1
621 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT	1
622 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_MASK	0x1
623 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT	2
624 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_MASK	0x1
625 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT	3
626 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_MASK	0x1
627 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT	4
628 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_MASK	0x1
629 #define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT	5
630 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_MASK	0x3
631 #define E4_XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT	6
632 	u8 byte2;
633 	__le16 physical_q0;
634 	__le16 consolid_prod;
635 	__le16 reserved16;
636 	__le16 tx_bd_cons;
637 	__le16 tx_bd_or_spq_prod;
638 	__le16 updated_qm_pq_id;
639 	__le16 conn_dpi;
640 	u8 byte3;
641 	u8 byte4;
642 	u8 byte5;
643 	u8 byte6;
644 	__le32 reg0;
645 	__le32 reg1;
646 	__le32 reg2;
647 	__le32 reg3;
648 	__le32 reg4;
649 	__le32 reg5;
650 	__le32 reg6;
651 	__le16 word7;
652 	__le16 word8;
653 	__le16 word9;
654 	__le16 word10;
655 	__le32 reg7;
656 	__le32 reg8;
657 	__le32 reg9;
658 	u8 byte7;
659 	u8 byte8;
660 	u8 byte9;
661 	u8 byte10;
662 	u8 byte11;
663 	u8 byte12;
664 	u8 byte13;
665 	u8 byte14;
666 	u8 byte15;
667 	u8 e5_reserved;
668 	__le16 word11;
669 	__le32 reg10;
670 	__le32 reg11;
671 	__le32 reg12;
672 	__le32 reg13;
673 	__le32 reg14;
674 	__le32 reg15;
675 	__le32 reg16;
676 	__le32 reg17;
677 	__le32 reg18;
678 	__le32 reg19;
679 	__le16 word12;
680 	__le16 word13;
681 	__le16 word14;
682 	__le16 word15;
683 };
684 
685 struct e4_tstorm_core_conn_ag_ctx {
686 	u8 byte0;
687 	u8 byte1;
688 	u8 flags0;
689 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_MASK	0x1
690 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT	0
691 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_MASK	0x1
692 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT	1
693 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_MASK	0x1
694 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT	2
695 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_MASK	0x1
696 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT	3
697 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_MASK	0x1
698 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT	4
699 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_MASK	0x1
700 #define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT	5
701 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_MASK	0x3
702 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT	6
703 	u8 flags1;
704 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_MASK	0x3
705 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT	0
706 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_MASK	0x3
707 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT	2
708 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_MASK	0x3
709 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT	4
710 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_MASK	0x3
711 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT	6
712 	u8 flags2;
713 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_MASK	0x3
714 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT	0
715 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_MASK	0x3
716 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT	2
717 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_MASK	0x3
718 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT	4
719 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_MASK	0x3
720 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT	6
721 	u8 flags3;
722 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_MASK	0x3
723 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT	0
724 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_MASK	0x3
725 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT	2
726 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK	0x1
727 #define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT	4
728 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK	0x1
729 #define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT	5
730 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK	0x1
731 #define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT	6
732 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK	0x1
733 #define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT	7
734 	u8 flags4;
735 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK		0x1
736 #define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT		0
737 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK		0x1
738 #define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT		1
739 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK		0x1
740 #define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT		2
741 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK		0x1
742 #define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT		3
743 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK		0x1
744 #define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT		4
745 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK		0x1
746 #define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT		5
747 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK		0x1
748 #define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT		6
749 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK		0x1
750 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT	7
751 	u8 flags5;
752 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK		0x1
753 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT	0
754 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK		0x1
755 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT	1
756 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK		0x1
757 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT	2
758 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK		0x1
759 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT	3
760 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK		0x1
761 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT	4
762 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK		0x1
763 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT	5
764 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK		0x1
765 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT	6
766 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK		0x1
767 #define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT	7
768 	__le32 reg0;
769 	__le32 reg1;
770 	__le32 reg2;
771 	__le32 reg3;
772 	__le32 reg4;
773 	__le32 reg5;
774 	__le32 reg6;
775 	__le32 reg7;
776 	__le32 reg8;
777 	u8 byte2;
778 	u8 byte3;
779 	__le16 word0;
780 	u8 byte4;
781 	u8 byte5;
782 	__le16 word1;
783 	__le16 word2;
784 	__le16 word3;
785 	__le32 ll2_rx_prod;
786 	__le32 reg10;
787 };
788 
789 struct e4_ustorm_core_conn_ag_ctx {
790 	u8 reserved;
791 	u8 byte1;
792 	u8 flags0;
793 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_MASK	0x1
794 #define E4_USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT	0
795 #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_MASK	0x1
796 #define E4_USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT	1
797 #define E4_USTORM_CORE_CONN_AG_CTX_CF0_MASK	0x3
798 #define E4_USTORM_CORE_CONN_AG_CTX_CF0_SHIFT	2
799 #define E4_USTORM_CORE_CONN_AG_CTX_CF1_MASK	0x3
800 #define E4_USTORM_CORE_CONN_AG_CTX_CF1_SHIFT	4
801 #define E4_USTORM_CORE_CONN_AG_CTX_CF2_MASK	0x3
802 #define E4_USTORM_CORE_CONN_AG_CTX_CF2_SHIFT	6
803 	u8 flags1;
804 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_MASK	0x3
805 #define E4_USTORM_CORE_CONN_AG_CTX_CF3_SHIFT	0
806 #define E4_USTORM_CORE_CONN_AG_CTX_CF4_MASK	0x3
807 #define E4_USTORM_CORE_CONN_AG_CTX_CF4_SHIFT	2
808 #define E4_USTORM_CORE_CONN_AG_CTX_CF5_MASK	0x3
809 #define E4_USTORM_CORE_CONN_AG_CTX_CF5_SHIFT	4
810 #define E4_USTORM_CORE_CONN_AG_CTX_CF6_MASK	0x3
811 #define E4_USTORM_CORE_CONN_AG_CTX_CF6_SHIFT	6
812 	u8 flags2;
813 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_MASK		0x1
814 #define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT		0
815 #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_MASK		0x1
816 #define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT		1
817 #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_MASK		0x1
818 #define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT		2
819 #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_MASK		0x1
820 #define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT		3
821 #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_MASK		0x1
822 #define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT		4
823 #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_MASK		0x1
824 #define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT		5
825 #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_MASK		0x1
826 #define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT		6
827 #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK		0x1
828 #define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT	7
829 	u8 flags3;
830 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK		0x1
831 #define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT	0
832 #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK		0x1
833 #define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT	1
834 #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK		0x1
835 #define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT	2
836 #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK		0x1
837 #define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT	3
838 #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK		0x1
839 #define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT	4
840 #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK		0x1
841 #define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT	5
842 #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK		0x1
843 #define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT	6
844 #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK		0x1
845 #define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT	7
846 	u8 byte2;
847 	u8 byte3;
848 	__le16 word0;
849 	__le16 word1;
850 	__le32 rx_producers;
851 	__le32 reg1;
852 	__le32 reg2;
853 	__le32 reg3;
854 	__le16 word2;
855 	__le16 word3;
856 };
857 
858 /* The core storm context for the Mstorm */
859 struct mstorm_core_conn_st_ctx {
860 	__le32 reserved[40];
861 };
862 
863 /* The core storm context for the Ustorm */
864 struct ustorm_core_conn_st_ctx {
865 	__le32 reserved[20];
866 };
867 
868 /* The core storm context for the Tstorm */
869 struct tstorm_core_conn_st_ctx {
870 	__le32 reserved[4];
871 };
872 
873 /* core connection context */
874 struct e4_core_conn_context {
875 	struct ystorm_core_conn_st_ctx ystorm_st_context;
876 	struct regpair ystorm_st_padding[2];
877 	struct pstorm_core_conn_st_ctx pstorm_st_context;
878 	struct regpair pstorm_st_padding[2];
879 	struct xstorm_core_conn_st_ctx xstorm_st_context;
880 	struct e4_xstorm_core_conn_ag_ctx xstorm_ag_context;
881 	struct e4_tstorm_core_conn_ag_ctx tstorm_ag_context;
882 	struct e4_ustorm_core_conn_ag_ctx ustorm_ag_context;
883 	struct mstorm_core_conn_st_ctx mstorm_st_context;
884 	struct ustorm_core_conn_st_ctx ustorm_st_context;
885 	struct regpair ustorm_st_padding[2];
886 	struct tstorm_core_conn_st_ctx tstorm_st_context;
887 	struct regpair tstorm_st_padding[2];
888 };
889 
890 struct eth_mstorm_per_pf_stat {
891 	struct regpair gre_discard_pkts;
892 	struct regpair vxlan_discard_pkts;
893 	struct regpair geneve_discard_pkts;
894 	struct regpair lb_discard_pkts;
895 };
896 
897 struct eth_mstorm_per_queue_stat {
898 	struct regpair ttl0_discard;
899 	struct regpair packet_too_big_discard;
900 	struct regpair no_buff_discard;
901 	struct regpair not_active_discard;
902 	struct regpair tpa_coalesced_pkts;
903 	struct regpair tpa_coalesced_events;
904 	struct regpair tpa_aborts_num;
905 	struct regpair tpa_coalesced_bytes;
906 };
907 
908 /* Ethernet TX Per PF */
909 struct eth_pstorm_per_pf_stat {
910 	struct regpair sent_lb_ucast_bytes;
911 	struct regpair sent_lb_mcast_bytes;
912 	struct regpair sent_lb_bcast_bytes;
913 	struct regpair sent_lb_ucast_pkts;
914 	struct regpair sent_lb_mcast_pkts;
915 	struct regpair sent_lb_bcast_pkts;
916 	struct regpair sent_gre_bytes;
917 	struct regpair sent_vxlan_bytes;
918 	struct regpair sent_geneve_bytes;
919 	struct regpair sent_mpls_bytes;
920 	struct regpair sent_gre_mpls_bytes;
921 	struct regpair sent_udp_mpls_bytes;
922 	struct regpair sent_gre_pkts;
923 	struct regpair sent_vxlan_pkts;
924 	struct regpair sent_geneve_pkts;
925 	struct regpair sent_mpls_pkts;
926 	struct regpair sent_gre_mpls_pkts;
927 	struct regpair sent_udp_mpls_pkts;
928 	struct regpair gre_drop_pkts;
929 	struct regpair vxlan_drop_pkts;
930 	struct regpair geneve_drop_pkts;
931 	struct regpair mpls_drop_pkts;
932 	struct regpair gre_mpls_drop_pkts;
933 	struct regpair udp_mpls_drop_pkts;
934 };
935 
936 /* Ethernet TX Per Queue Stats */
937 struct eth_pstorm_per_queue_stat {
938 	struct regpair sent_ucast_bytes;
939 	struct regpair sent_mcast_bytes;
940 	struct regpair sent_bcast_bytes;
941 	struct regpair sent_ucast_pkts;
942 	struct regpair sent_mcast_pkts;
943 	struct regpair sent_bcast_pkts;
944 	struct regpair error_drop_pkts;
945 };
946 
947 /* ETH Rx producers data */
948 struct eth_rx_rate_limit {
949 	__le16 mult;
950 	__le16 cnst;
951 	u8 add_sub_cnst;
952 	u8 reserved0;
953 	__le16 reserved1;
954 };
955 
956 /* Update RSS indirection table entry command */
957 struct eth_tstorm_rss_update_data {
958 	u8 valid;
959 	u8 vport_id;
960 	u8 ind_table_index;
961 	u8 reserved;
962 	__le16 ind_table_value;
963 	__le16 reserved1;
964 };
965 
966 struct eth_ustorm_per_pf_stat {
967 	struct regpair rcv_lb_ucast_bytes;
968 	struct regpair rcv_lb_mcast_bytes;
969 	struct regpair rcv_lb_bcast_bytes;
970 	struct regpair rcv_lb_ucast_pkts;
971 	struct regpair rcv_lb_mcast_pkts;
972 	struct regpair rcv_lb_bcast_pkts;
973 	struct regpair rcv_gre_bytes;
974 	struct regpair rcv_vxlan_bytes;
975 	struct regpair rcv_geneve_bytes;
976 	struct regpair rcv_gre_pkts;
977 	struct regpair rcv_vxlan_pkts;
978 	struct regpair rcv_geneve_pkts;
979 };
980 
981 struct eth_ustorm_per_queue_stat {
982 	struct regpair rcv_ucast_bytes;
983 	struct regpair rcv_mcast_bytes;
984 	struct regpair rcv_bcast_bytes;
985 	struct regpair rcv_ucast_pkts;
986 	struct regpair rcv_mcast_pkts;
987 	struct regpair rcv_bcast_pkts;
988 };
989 
990 /* Event Ring VF-PF Channel data */
991 struct vf_pf_channel_eqe_data {
992 	struct regpair msg_addr;
993 };
994 
995 /* Event Ring malicious VF data */
996 struct malicious_vf_eqe_data {
997 	u8 vf_id;
998 	u8 err_id;
999 	__le16 reserved[3];
1000 };
1001 
1002 /* Event Ring initial cleanup data */
1003 struct initial_cleanup_eqe_data {
1004 	u8 vf_id;
1005 	u8 reserved[7];
1006 };
1007 
1008 /* Event Data Union */
1009 union event_ring_data {
1010 	u8 bytes[8];
1011 	struct vf_pf_channel_eqe_data vf_pf_channel;
1012 	struct iscsi_eqe_data iscsi_info;
1013 	struct iscsi_connect_done_results iscsi_conn_done_info;
1014 	union rdma_eqe_data rdma_data;
1015 	struct malicious_vf_eqe_data malicious_vf;
1016 	struct initial_cleanup_eqe_data vf_init_cleanup;
1017 };
1018 
1019 /* Event Ring Entry */
1020 struct event_ring_entry {
1021 	u8 protocol_id;
1022 	u8 opcode;
1023 	u8 reserved0;
1024 	u8 vf_id;
1025 	__le16 echo;
1026 	u8 fw_return_code;
1027 	u8 flags;
1028 #define EVENT_RING_ENTRY_ASYNC_MASK		0x1
1029 #define EVENT_RING_ENTRY_ASYNC_SHIFT		0
1030 #define EVENT_RING_ENTRY_RESERVED1_MASK		0x7F
1031 #define EVENT_RING_ENTRY_RESERVED1_SHIFT	1
1032 	union event_ring_data data;
1033 };
1034 
1035 /* Event Ring Next Page Address */
1036 struct event_ring_next_addr {
1037 	struct regpair addr;
1038 	__le32 reserved[2];
1039 };
1040 
1041 /* Event Ring Element */
1042 union event_ring_element {
1043 	struct event_ring_entry entry;
1044 	struct event_ring_next_addr next_addr;
1045 };
1046 
1047 /* Ports mode */
1048 enum fw_flow_ctrl_mode {
1049 	flow_ctrl_pause,
1050 	flow_ctrl_pfc,
1051 	MAX_FW_FLOW_CTRL_MODE
1052 };
1053 
1054 /* GFT profile type */
1055 enum gft_profile_type {
1056 	GFT_PROFILE_TYPE_4_TUPLE,
1057 	GFT_PROFILE_TYPE_L4_DST_PORT,
1058 	GFT_PROFILE_TYPE_IP_DST_ADDR,
1059 	GFT_PROFILE_TYPE_IP_SRC_ADDR,
1060 	GFT_PROFILE_TYPE_TUNNEL_TYPE,
1061 	MAX_GFT_PROFILE_TYPE
1062 };
1063 
1064 /* Major and Minor hsi Versions */
1065 struct hsi_fp_ver_struct {
1066 	u8 minor_ver_arr[2];
1067 	u8 major_ver_arr[2];
1068 };
1069 
1070 enum iwarp_ll2_tx_queues {
1071 	IWARP_LL2_IN_ORDER_TX_QUEUE = 1,
1072 	IWARP_LL2_ALIGNED_TX_QUEUE,
1073 	IWARP_LL2_ALIGNED_RIGHT_TRIMMED_TX_QUEUE,
1074 	IWARP_LL2_ERROR,
1075 	MAX_IWARP_LL2_TX_QUEUES
1076 };
1077 
1078 /* Malicious VF error ID */
1079 enum malicious_vf_error_id {
1080 	MALICIOUS_VF_NO_ERROR,
1081 	VF_PF_CHANNEL_NOT_READY,
1082 	VF_ZONE_MSG_NOT_VALID,
1083 	VF_ZONE_FUNC_NOT_ENABLED,
1084 	ETH_PACKET_TOO_SMALL,
1085 	ETH_ILLEGAL_VLAN_MODE,
1086 	ETH_MTU_VIOLATION,
1087 	ETH_ILLEGAL_INBAND_TAGS,
1088 	ETH_VLAN_INSERT_AND_INBAND_VLAN,
1089 	ETH_ILLEGAL_NBDS,
1090 	ETH_FIRST_BD_WO_SOP,
1091 	ETH_INSUFFICIENT_BDS,
1092 	ETH_ILLEGAL_LSO_HDR_NBDS,
1093 	ETH_ILLEGAL_LSO_MSS,
1094 	ETH_ZERO_SIZE_BD,
1095 	ETH_ILLEGAL_LSO_HDR_LEN,
1096 	ETH_INSUFFICIENT_PAYLOAD,
1097 	ETH_EDPM_OUT_OF_SYNC,
1098 	ETH_TUNN_IPV6_EXT_NBD_ERR,
1099 	ETH_CONTROL_PACKET_VIOLATION,
1100 	ETH_ANTI_SPOOFING_ERR,
1101 	ETH_PACKET_SIZE_TOO_LARGE,
1102 	CORE_ILLEGAL_VLAN_MODE,
1103 	CORE_ILLEGAL_NBDS,
1104 	CORE_FIRST_BD_WO_SOP,
1105 	CORE_INSUFFICIENT_BDS,
1106 	CORE_PACKET_TOO_SMALL,
1107 	CORE_ILLEGAL_INBAND_TAGS,
1108 	CORE_VLAN_INSERT_AND_INBAND_VLAN,
1109 	CORE_MTU_VIOLATION,
1110 	CORE_CONTROL_PACKET_VIOLATION,
1111 	CORE_ANTI_SPOOFING_ERR,
1112 	CORE_PACKET_SIZE_TOO_LARGE,
1113 	CORE_ILLEGAL_BD_FLAGS,
1114 	CORE_GSI_PACKET_VIOLATION,
1115 	MAX_MALICIOUS_VF_ERROR_ID,
1116 };
1117 
1118 /* Mstorm non-triggering VF zone */
1119 struct mstorm_non_trigger_vf_zone {
1120 	struct eth_mstorm_per_queue_stat eth_queue_stat;
1121 	struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD];
1122 };
1123 
1124 /* Mstorm VF zone */
1125 struct mstorm_vf_zone {
1126 	struct mstorm_non_trigger_vf_zone non_trigger;
1127 };
1128 
1129 /* vlan header including TPID and TCI fields */
1130 struct vlan_header {
1131 	__le16 tpid;
1132 	__le16 tci;
1133 };
1134 
1135 /* outer tag configurations */
1136 struct outer_tag_config_struct {
1137 	u8 enable_stag_pri_change;
1138 	u8 pri_map_valid;
1139 	u8 reserved[2];
1140 	struct vlan_header outer_tag;
1141 	u8 inner_to_outer_pri_map[8];
1142 };
1143 
1144 /* personality per PF */
1145 enum personality_type {
1146 	BAD_PERSONALITY_TYP,
1147 	PERSONALITY_ISCSI,
1148 	PERSONALITY_FCOE,
1149 	PERSONALITY_RDMA_AND_ETH,
1150 	PERSONALITY_RDMA,
1151 	PERSONALITY_CORE,
1152 	PERSONALITY_ETH,
1153 	PERSONALITY_RESERVED,
1154 	MAX_PERSONALITY_TYPE
1155 };
1156 
1157 /* tunnel configuration */
1158 struct pf_start_tunnel_config {
1159 	u8 set_vxlan_udp_port_flg;
1160 	u8 set_geneve_udp_port_flg;
1161 	u8 set_no_inner_l2_vxlan_udp_port_flg;
1162 	u8 tunnel_clss_vxlan;
1163 	u8 tunnel_clss_l2geneve;
1164 	u8 tunnel_clss_ipgeneve;
1165 	u8 tunnel_clss_l2gre;
1166 	u8 tunnel_clss_ipgre;
1167 	__le16 vxlan_udp_port;
1168 	__le16 geneve_udp_port;
1169 	__le16 no_inner_l2_vxlan_udp_port;
1170 	__le16 reserved[3];
1171 };
1172 
1173 /* Ramrod data for PF start ramrod */
1174 struct pf_start_ramrod_data {
1175 	struct regpair event_ring_pbl_addr;
1176 	struct regpair consolid_q_pbl_addr;
1177 	struct pf_start_tunnel_config tunnel_config;
1178 	__le16 event_ring_sb_id;
1179 	u8 base_vf_id;
1180 	u8 num_vfs;
1181 	u8 event_ring_num_pages;
1182 	u8 event_ring_sb_index;
1183 	u8 path_id;
1184 	u8 warning_as_error;
1185 	u8 dont_log_ramrods;
1186 	u8 personality;
1187 	__le16 log_type_mask;
1188 	u8 mf_mode;
1189 	u8 integ_phase;
1190 	u8 allow_npar_tx_switching;
1191 	u8 reserved0;
1192 	struct hsi_fp_ver_struct hsi_fp_ver;
1193 	struct outer_tag_config_struct outer_tag_config;
1194 };
1195 
1196 /* Data for port update ramrod */
1197 struct protocol_dcb_data {
1198 	u8 dcb_enable_flag;
1199 	u8 dscp_enable_flag;
1200 	u8 dcb_priority;
1201 	u8 dcb_tc;
1202 	u8 dscp_val;
1203 	u8 dcb_dont_add_vlan0;
1204 };
1205 
1206 /* Update tunnel configuration */
1207 struct pf_update_tunnel_config {
1208 	u8 update_rx_pf_clss;
1209 	u8 update_rx_def_ucast_clss;
1210 	u8 update_rx_def_non_ucast_clss;
1211 	u8 set_vxlan_udp_port_flg;
1212 	u8 set_geneve_udp_port_flg;
1213 	u8 set_no_inner_l2_vxlan_udp_port_flg;
1214 	u8 tunnel_clss_vxlan;
1215 	u8 tunnel_clss_l2geneve;
1216 	u8 tunnel_clss_ipgeneve;
1217 	u8 tunnel_clss_l2gre;
1218 	u8 tunnel_clss_ipgre;
1219 	u8 reserved;
1220 	__le16 vxlan_udp_port;
1221 	__le16 geneve_udp_port;
1222 	__le16 no_inner_l2_vxlan_udp_port;
1223 	__le16 reserved1[3];
1224 };
1225 
1226 /* Data for port update ramrod */
1227 struct pf_update_ramrod_data {
1228 	u8 update_eth_dcb_data_mode;
1229 	u8 update_fcoe_dcb_data_mode;
1230 	u8 update_iscsi_dcb_data_mode;
1231 	u8 update_roce_dcb_data_mode;
1232 	u8 update_rroce_dcb_data_mode;
1233 	u8 update_iwarp_dcb_data_mode;
1234 	u8 update_mf_vlan_flag;
1235 	u8 update_enable_stag_pri_change;
1236 	struct protocol_dcb_data eth_dcb_data;
1237 	struct protocol_dcb_data fcoe_dcb_data;
1238 	struct protocol_dcb_data iscsi_dcb_data;
1239 	struct protocol_dcb_data roce_dcb_data;
1240 	struct protocol_dcb_data rroce_dcb_data;
1241 	struct protocol_dcb_data iwarp_dcb_data;
1242 	__le16 mf_vlan;
1243 	u8 enable_stag_pri_change;
1244 	u8 reserved;
1245 	struct pf_update_tunnel_config tunnel_config;
1246 };
1247 
1248 /* Ports mode */
1249 enum ports_mode {
1250 	ENGX2_PORTX1,
1251 	ENGX2_PORTX2,
1252 	ENGX1_PORTX1,
1253 	ENGX1_PORTX2,
1254 	ENGX1_PORTX4,
1255 	MAX_PORTS_MODE
1256 };
1257 
1258 /* use to index in hsi_fp_[major|minor]_ver_arr per protocol */
1259 enum protocol_version_array_key {
1260 	ETH_VER_KEY = 0,
1261 	ROCE_VER_KEY,
1262 	MAX_PROTOCOL_VERSION_ARRAY_KEY
1263 };
1264 
1265 /* RDMA TX Stats */
1266 struct rdma_sent_stats {
1267 	struct regpair sent_bytes;
1268 	struct regpair sent_pkts;
1269 };
1270 
1271 /* Pstorm non-triggering VF zone */
1272 struct pstorm_non_trigger_vf_zone {
1273 	struct eth_pstorm_per_queue_stat eth_queue_stat;
1274 	struct rdma_sent_stats rdma_stats;
1275 };
1276 
1277 /* Pstorm VF zone */
1278 struct pstorm_vf_zone {
1279 	struct pstorm_non_trigger_vf_zone non_trigger;
1280 	struct regpair reserved[7];
1281 };
1282 
1283 /* Ramrod Header of SPQE */
1284 struct ramrod_header {
1285 	__le32 cid;
1286 	u8 cmd_id;
1287 	u8 protocol_id;
1288 	__le16 echo;
1289 };
1290 
1291 /* RDMA RX Stats */
1292 struct rdma_rcv_stats {
1293 	struct regpair rcv_bytes;
1294 	struct regpair rcv_pkts;
1295 };
1296 
1297 /* Data for update QCN/DCQCN RL ramrod */
1298 struct rl_update_ramrod_data {
1299 	u8 qcn_update_param_flg;
1300 	u8 dcqcn_update_param_flg;
1301 	u8 rl_init_flg;
1302 	u8 rl_start_flg;
1303 	u8 rl_stop_flg;
1304 	u8 rl_id_first;
1305 	u8 rl_id_last;
1306 	u8 rl_dc_qcn_flg;
1307 	u8 dcqcn_reset_alpha_on_idle;
1308 	u8 rl_bc_stage_th;
1309 	u8 rl_timer_stage_th;
1310 	u8 reserved1;
1311 	__le32 rl_bc_rate;
1312 	__le16 rl_max_rate;
1313 	__le16 rl_r_ai;
1314 	__le16 rl_r_hai;
1315 	__le16 dcqcn_g;
1316 	__le32 dcqcn_k_us;
1317 	__le32 dcqcn_timeuot_us;
1318 	__le32 qcn_timeuot_us;
1319 	__le32 reserved2;
1320 };
1321 
1322 /* Slowpath Element (SPQE) */
1323 struct slow_path_element {
1324 	struct ramrod_header hdr;
1325 	struct regpair data_ptr;
1326 };
1327 
1328 /* Tstorm non-triggering VF zone */
1329 struct tstorm_non_trigger_vf_zone {
1330 	struct rdma_rcv_stats rdma_stats;
1331 };
1332 
1333 struct tstorm_per_port_stat {
1334 	struct regpair trunc_error_discard;
1335 	struct regpair mac_error_discard;
1336 	struct regpair mftag_filter_discard;
1337 	struct regpair eth_mac_filter_discard;
1338 	struct regpair ll2_mac_filter_discard;
1339 	struct regpair ll2_conn_disabled_discard;
1340 	struct regpair iscsi_irregular_pkt;
1341 	struct regpair fcoe_irregular_pkt;
1342 	struct regpair roce_irregular_pkt;
1343 	struct regpair iwarp_irregular_pkt;
1344 	struct regpair eth_irregular_pkt;
1345 	struct regpair toe_irregular_pkt;
1346 	struct regpair preroce_irregular_pkt;
1347 	struct regpair eth_gre_tunn_filter_discard;
1348 	struct regpair eth_vxlan_tunn_filter_discard;
1349 	struct regpair eth_geneve_tunn_filter_discard;
1350 	struct regpair eth_gft_drop_pkt;
1351 };
1352 
1353 /* Tstorm VF zone */
1354 struct tstorm_vf_zone {
1355 	struct tstorm_non_trigger_vf_zone non_trigger;
1356 };
1357 
1358 /* Tunnel classification scheme */
1359 enum tunnel_clss {
1360 	TUNNEL_CLSS_MAC_VLAN = 0,
1361 	TUNNEL_CLSS_MAC_VNI,
1362 	TUNNEL_CLSS_INNER_MAC_VLAN,
1363 	TUNNEL_CLSS_INNER_MAC_VNI,
1364 	TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE,
1365 	MAX_TUNNEL_CLSS
1366 };
1367 
1368 /* Ustorm non-triggering VF zone */
1369 struct ustorm_non_trigger_vf_zone {
1370 	struct eth_ustorm_per_queue_stat eth_queue_stat;
1371 	struct regpair vf_pf_msg_addr;
1372 };
1373 
1374 /* Ustorm triggering VF zone */
1375 struct ustorm_trigger_vf_zone {
1376 	u8 vf_pf_msg_valid;
1377 	u8 reserved[7];
1378 };
1379 
1380 /* Ustorm VF zone */
1381 struct ustorm_vf_zone {
1382 	struct ustorm_non_trigger_vf_zone non_trigger;
1383 	struct ustorm_trigger_vf_zone trigger;
1384 };
1385 
1386 /* VF-PF channel data */
1387 struct vf_pf_channel_data {
1388 	__le32 ready;
1389 	u8 valid;
1390 	u8 reserved0;
1391 	__le16 reserved1;
1392 };
1393 
1394 /* Ramrod data for VF start ramrod */
1395 struct vf_start_ramrod_data {
1396 	u8 vf_id;
1397 	u8 enable_flr_ack;
1398 	__le16 opaque_fid;
1399 	u8 personality;
1400 	u8 reserved[7];
1401 	struct hsi_fp_ver_struct hsi_fp_ver;
1402 
1403 };
1404 
1405 /* Ramrod data for VF start ramrod */
1406 struct vf_stop_ramrod_data {
1407 	u8 vf_id;
1408 	u8 reserved0;
1409 	__le16 reserved1;
1410 	__le32 reserved2;
1411 };
1412 
1413 /* VF zone size mode */
1414 enum vf_zone_size_mode {
1415 	VF_ZONE_SIZE_MODE_DEFAULT,
1416 	VF_ZONE_SIZE_MODE_DOUBLE,
1417 	VF_ZONE_SIZE_MODE_QUAD,
1418 	MAX_VF_ZONE_SIZE_MODE
1419 };
1420 
1421 /* Xstorm non-triggering VF zone */
1422 struct xstorm_non_trigger_vf_zone {
1423 	struct regpair non_edpm_ack_pkts;
1424 };
1425 
1426 /* Tstorm VF zone */
1427 struct xstorm_vf_zone {
1428 	struct xstorm_non_trigger_vf_zone non_trigger;
1429 };
1430 
1431 /* Attentions status block */
1432 struct atten_status_block {
1433 	__le32 atten_bits;
1434 	__le32 atten_ack;
1435 	__le16 reserved0;
1436 	__le16 sb_index;
1437 	__le32 reserved1;
1438 };
1439 
1440 /* DMAE command */
1441 struct dmae_cmd {
1442 	__le32 opcode;
1443 #define DMAE_CMD_SRC_MASK		0x1
1444 #define DMAE_CMD_SRC_SHIFT		0
1445 #define DMAE_CMD_DST_MASK		0x3
1446 #define DMAE_CMD_DST_SHIFT		1
1447 #define DMAE_CMD_C_DST_MASK		0x1
1448 #define DMAE_CMD_C_DST_SHIFT		3
1449 #define DMAE_CMD_CRC_RESET_MASK		0x1
1450 #define DMAE_CMD_CRC_RESET_SHIFT	4
1451 #define DMAE_CMD_SRC_ADDR_RESET_MASK	0x1
1452 #define DMAE_CMD_SRC_ADDR_RESET_SHIFT	5
1453 #define DMAE_CMD_DST_ADDR_RESET_MASK	0x1
1454 #define DMAE_CMD_DST_ADDR_RESET_SHIFT	6
1455 #define DMAE_CMD_COMP_FUNC_MASK		0x1
1456 #define DMAE_CMD_COMP_FUNC_SHIFT	7
1457 #define DMAE_CMD_COMP_WORD_EN_MASK	0x1
1458 #define DMAE_CMD_COMP_WORD_EN_SHIFT	8
1459 #define DMAE_CMD_COMP_CRC_EN_MASK	0x1
1460 #define DMAE_CMD_COMP_CRC_EN_SHIFT	9
1461 #define DMAE_CMD_COMP_CRC_OFFSET_MASK	0x7
1462 #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
1463 #define DMAE_CMD_RESERVED1_MASK		0x1
1464 #define DMAE_CMD_RESERVED1_SHIFT	13
1465 #define DMAE_CMD_ENDIANITY_MODE_MASK	0x3
1466 #define DMAE_CMD_ENDIANITY_MODE_SHIFT	14
1467 #define DMAE_CMD_ERR_HANDLING_MASK	0x3
1468 #define DMAE_CMD_ERR_HANDLING_SHIFT	16
1469 #define DMAE_CMD_PORT_ID_MASK		0x3
1470 #define DMAE_CMD_PORT_ID_SHIFT		18
1471 #define DMAE_CMD_SRC_PF_ID_MASK		0xF
1472 #define DMAE_CMD_SRC_PF_ID_SHIFT	20
1473 #define DMAE_CMD_DST_PF_ID_MASK		0xF
1474 #define DMAE_CMD_DST_PF_ID_SHIFT	24
1475 #define DMAE_CMD_SRC_VF_ID_VALID_MASK	0x1
1476 #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
1477 #define DMAE_CMD_DST_VF_ID_VALID_MASK	0x1
1478 #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
1479 #define DMAE_CMD_RESERVED2_MASK		0x3
1480 #define DMAE_CMD_RESERVED2_SHIFT	30
1481 	__le32 src_addr_lo;
1482 	__le32 src_addr_hi;
1483 	__le32 dst_addr_lo;
1484 	__le32 dst_addr_hi;
1485 	__le16 length_dw;
1486 	__le16 opcode_b;
1487 #define DMAE_CMD_SRC_VF_ID_MASK		0xFF
1488 #define DMAE_CMD_SRC_VF_ID_SHIFT	0
1489 #define DMAE_CMD_DST_VF_ID_MASK		0xFF
1490 #define DMAE_CMD_DST_VF_ID_SHIFT	8
1491 	__le32 comp_addr_lo;
1492 	__le32 comp_addr_hi;
1493 	__le32 comp_val;
1494 	__le32 crc32;
1495 	__le32 crc_32_c;
1496 	__le16 crc16;
1497 	__le16 crc16_c;
1498 	__le16 crc10;
1499 	__le16 error_bit_reserved;
1500 #define DMAE_CMD_ERROR_BIT_MASK        0x1
1501 #define DMAE_CMD_ERROR_BIT_SHIFT       0
1502 #define DMAE_CMD_RESERVED_MASK	       0x7FFF
1503 #define DMAE_CMD_RESERVED_SHIFT        1
1504 	__le16 xsum16;
1505 	__le16 xsum8;
1506 };
1507 
1508 enum dmae_cmd_comp_crc_en_enum {
1509 	dmae_cmd_comp_crc_disabled,
1510 	dmae_cmd_comp_crc_enabled,
1511 	MAX_DMAE_CMD_COMP_CRC_EN_ENUM
1512 };
1513 
1514 enum dmae_cmd_comp_func_enum {
1515 	dmae_cmd_comp_func_to_src,
1516 	dmae_cmd_comp_func_to_dst,
1517 	MAX_DMAE_CMD_COMP_FUNC_ENUM
1518 };
1519 
1520 enum dmae_cmd_comp_word_en_enum {
1521 	dmae_cmd_comp_word_disabled,
1522 	dmae_cmd_comp_word_enabled,
1523 	MAX_DMAE_CMD_COMP_WORD_EN_ENUM
1524 };
1525 
1526 enum dmae_cmd_c_dst_enum {
1527 	dmae_cmd_c_dst_pcie,
1528 	dmae_cmd_c_dst_grc,
1529 	MAX_DMAE_CMD_C_DST_ENUM
1530 };
1531 
1532 enum dmae_cmd_dst_enum {
1533 	dmae_cmd_dst_none_0,
1534 	dmae_cmd_dst_pcie,
1535 	dmae_cmd_dst_grc,
1536 	dmae_cmd_dst_none_3,
1537 	MAX_DMAE_CMD_DST_ENUM
1538 };
1539 
1540 enum dmae_cmd_error_handling_enum {
1541 	dmae_cmd_error_handling_send_regular_comp,
1542 	dmae_cmd_error_handling_send_comp_with_err,
1543 	dmae_cmd_error_handling_dont_send_comp,
1544 	MAX_DMAE_CMD_ERROR_HANDLING_ENUM
1545 };
1546 
1547 enum dmae_cmd_src_enum {
1548 	dmae_cmd_src_pcie,
1549 	dmae_cmd_src_grc,
1550 	MAX_DMAE_CMD_SRC_ENUM
1551 };
1552 
1553 struct e4_mstorm_core_conn_ag_ctx {
1554 	u8 byte0;
1555 	u8 byte1;
1556 	u8 flags0;
1557 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_MASK	0x1
1558 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT	0
1559 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_MASK	0x1
1560 #define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT	1
1561 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_MASK	0x3
1562 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT	2
1563 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_MASK	0x3
1564 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT	4
1565 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_MASK	0x3
1566 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT	6
1567 	u8 flags1;
1568 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK		0x1
1569 #define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT		0
1570 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK		0x1
1571 #define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT		1
1572 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK		0x1
1573 #define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT		2
1574 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK		0x1
1575 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT	3
1576 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK		0x1
1577 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT	4
1578 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK		0x1
1579 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT	5
1580 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK		0x1
1581 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT	6
1582 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK		0x1
1583 #define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT	7
1584 	__le16 word0;
1585 	__le16 word1;
1586 	__le32 reg0;
1587 	__le32 reg1;
1588 };
1589 
1590 struct e4_ystorm_core_conn_ag_ctx {
1591 	u8 byte0;
1592 	u8 byte1;
1593 	u8 flags0;
1594 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_MASK	0x1
1595 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT	0
1596 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_MASK	0x1
1597 #define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT	1
1598 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_MASK	0x3
1599 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT	2
1600 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_MASK	0x3
1601 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT	4
1602 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_MASK	0x3
1603 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT	6
1604 	u8 flags1;
1605 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK		0x1
1606 #define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT		0
1607 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK		0x1
1608 #define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT		1
1609 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK		0x1
1610 #define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT		2
1611 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK		0x1
1612 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT	3
1613 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK		0x1
1614 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT	4
1615 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK		0x1
1616 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT	5
1617 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK		0x1
1618 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT	6
1619 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK		0x1
1620 #define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT	7
1621 	u8 byte2;
1622 	u8 byte3;
1623 	__le16 word0;
1624 	__le32 reg0;
1625 	__le32 reg1;
1626 	__le16 word1;
1627 	__le16 word2;
1628 	__le16 word3;
1629 	__le16 word4;
1630 	__le32 reg2;
1631 	__le32 reg3;
1632 };
1633 
1634 /* DMAE parameters */
1635 struct qed_dmae_params {
1636 	u32 flags;
1637 /* If QED_DMAE_PARAMS_RW_REPL_SRC flag is set and the
1638  * source is a block of length DMAE_MAX_RW_SIZE and the
1639  * destination is larger, the source block will be duplicated as
1640  * many times as required to fill the destination block. This is
1641  * used mostly to write a zeroed buffer to destination address
1642  * using DMA
1643  */
1644 #define QED_DMAE_PARAMS_RW_REPL_SRC_MASK	0x1
1645 #define QED_DMAE_PARAMS_RW_REPL_SRC_SHIFT	0
1646 #define QED_DMAE_PARAMS_SRC_VF_VALID_MASK	0x1
1647 #define QED_DMAE_PARAMS_SRC_VF_VALID_SHIFT	1
1648 #define QED_DMAE_PARAMS_DST_VF_VALID_MASK	0x1
1649 #define QED_DMAE_PARAMS_DST_VF_VALID_SHIFT	2
1650 #define QED_DMAE_PARAMS_COMPLETION_DST_MASK	0x1
1651 #define QED_DMAE_PARAMS_COMPLETION_DST_SHIFT	3
1652 #define QED_DMAE_PARAMS_PORT_VALID_MASK		0x1
1653 #define QED_DMAE_PARAMS_PORT_VALID_SHIFT	4
1654 #define QED_DMAE_PARAMS_SRC_PF_VALID_MASK	0x1
1655 #define QED_DMAE_PARAMS_SRC_PF_VALID_SHIFT	5
1656 #define QED_DMAE_PARAMS_DST_PF_VALID_MASK	0x1
1657 #define QED_DMAE_PARAMS_DST_PF_VALID_SHIFT	6
1658 #define QED_DMAE_PARAMS_RESERVED_MASK		0x1FFFFFF
1659 #define QED_DMAE_PARAMS_RESERVED_SHIFT		7
1660 	u8 src_vfid;
1661 	u8 dst_vfid;
1662 	u8 port_id;
1663 	u8 src_pfid;
1664 	u8 dst_pfid;
1665 	u8 reserved1;
1666 	__le16 reserved2;
1667 };
1668 
1669 /* IGU cleanup command */
1670 struct igu_cleanup {
1671 	__le32 sb_id_and_flags;
1672 #define IGU_CLEANUP_RESERVED0_MASK	0x7FFFFFF
1673 #define IGU_CLEANUP_RESERVED0_SHIFT	0
1674 #define IGU_CLEANUP_CLEANUP_SET_MASK	0x1
1675 #define IGU_CLEANUP_CLEANUP_SET_SHIFT	27
1676 #define IGU_CLEANUP_CLEANUP_TYPE_MASK	0x7
1677 #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT	28
1678 #define IGU_CLEANUP_COMMAND_TYPE_MASK	0x1
1679 #define IGU_CLEANUP_COMMAND_TYPE_SHIFT	31
1680 	__le32 reserved1;
1681 };
1682 
1683 /* IGU firmware driver command */
1684 union igu_command {
1685 	struct igu_prod_cons_update prod_cons_update;
1686 	struct igu_cleanup cleanup;
1687 };
1688 
1689 /* IGU firmware driver command */
1690 struct igu_command_reg_ctrl {
1691 	__le16 opaque_fid;
1692 	__le16 igu_command_reg_ctrl_fields;
1693 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK	0xFFF
1694 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT	0
1695 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK	0x7
1696 #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT	12
1697 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK	0x1
1698 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT	15
1699 };
1700 
1701 /* IGU mapping line structure */
1702 struct igu_mapping_line {
1703 	__le32 igu_mapping_line_fields;
1704 #define IGU_MAPPING_LINE_VALID_MASK		0x1
1705 #define IGU_MAPPING_LINE_VALID_SHIFT		0
1706 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK	0xFF
1707 #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT	1
1708 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK	0xFF
1709 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT	9
1710 #define IGU_MAPPING_LINE_PF_VALID_MASK		0x1
1711 #define IGU_MAPPING_LINE_PF_VALID_SHIFT		17
1712 #define IGU_MAPPING_LINE_IPS_GROUP_MASK		0x3F
1713 #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT	18
1714 #define IGU_MAPPING_LINE_RESERVED_MASK		0xFF
1715 #define IGU_MAPPING_LINE_RESERVED_SHIFT		24
1716 };
1717 
1718 /* IGU MSIX line structure */
1719 struct igu_msix_vector {
1720 	struct regpair address;
1721 	__le32 data;
1722 	__le32 msix_vector_fields;
1723 #define IGU_MSIX_VECTOR_MASK_BIT_MASK		0x1
1724 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT		0
1725 #define IGU_MSIX_VECTOR_RESERVED0_MASK		0x7FFF
1726 #define IGU_MSIX_VECTOR_RESERVED0_SHIFT		1
1727 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK	0xFF
1728 #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT	16
1729 #define IGU_MSIX_VECTOR_RESERVED1_MASK		0xFF
1730 #define IGU_MSIX_VECTOR_RESERVED1_SHIFT		24
1731 };
1732 /* per encapsulation type enabling flags */
1733 struct prs_reg_encapsulation_type_en {
1734 	u8 flags;
1735 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK		0x1
1736 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT		0
1737 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK		0x1
1738 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT		1
1739 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK			0x1
1740 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT		2
1741 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK			0x1
1742 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT		3
1743 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK	0x1
1744 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT	4
1745 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK	0x1
1746 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT	5
1747 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK			0x3
1748 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT			6
1749 };
1750 
1751 enum pxp_tph_st_hint {
1752 	TPH_ST_HINT_BIDIR,
1753 	TPH_ST_HINT_REQUESTER,
1754 	TPH_ST_HINT_TARGET,
1755 	TPH_ST_HINT_TARGET_PRIO,
1756 	MAX_PXP_TPH_ST_HINT
1757 };
1758 
1759 /* QM hardware structure of enable bypass credit mask */
1760 struct qm_rf_bypass_mask {
1761 	u8 flags;
1762 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK		0x1
1763 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT		0
1764 #define QM_RF_BYPASS_MASK_RESERVED0_MASK	0x1
1765 #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT	1
1766 #define QM_RF_BYPASS_MASK_PFWFQ_MASK		0x1
1767 #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT		2
1768 #define QM_RF_BYPASS_MASK_VPWFQ_MASK		0x1
1769 #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT		3
1770 #define QM_RF_BYPASS_MASK_PFRL_MASK		0x1
1771 #define QM_RF_BYPASS_MASK_PFRL_SHIFT		4
1772 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK		0x1
1773 #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT		5
1774 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK		0x1
1775 #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT		6
1776 #define QM_RF_BYPASS_MASK_RESERVED1_MASK	0x1
1777 #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT	7
1778 };
1779 
1780 /* QM hardware structure of opportunistic credit mask */
1781 struct qm_rf_opportunistic_mask {
1782 	__le16 flags;
1783 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK		0x1
1784 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT		0
1785 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK		0x1
1786 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT		1
1787 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK		0x1
1788 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT		2
1789 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK		0x1
1790 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT		3
1791 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK		0x1
1792 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT		4
1793 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK		0x1
1794 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT		5
1795 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK		0x1
1796 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT		6
1797 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK		0x1
1798 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT	7
1799 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK	0x1
1800 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT	8
1801 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK		0x7F
1802 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT	9
1803 };
1804 
1805 /* QM hardware structure of QM map memory */
1806 struct qm_rf_pq_map_e4 {
1807 	__le32 reg;
1808 #define QM_RF_PQ_MAP_E4_PQ_VALID_MASK		0x1
1809 #define QM_RF_PQ_MAP_E4_PQ_VALID_SHIFT		0
1810 #define QM_RF_PQ_MAP_E4_RL_ID_MASK		0xFF
1811 #define QM_RF_PQ_MAP_E4_RL_ID_SHIFT		1
1812 #define QM_RF_PQ_MAP_E4_VP_PQ_ID_MASK		0x1FF
1813 #define QM_RF_PQ_MAP_E4_VP_PQ_ID_SHIFT		9
1814 #define QM_RF_PQ_MAP_E4_VOQ_MASK		0x1F
1815 #define QM_RF_PQ_MAP_E4_VOQ_SHIFT		18
1816 #define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_MASK	0x3
1817 #define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_SHIFT	23
1818 #define QM_RF_PQ_MAP_E4_RL_VALID_MASK		0x1
1819 #define QM_RF_PQ_MAP_E4_RL_VALID_SHIFT		25
1820 #define QM_RF_PQ_MAP_E4_RESERVED_MASK		0x3F
1821 #define QM_RF_PQ_MAP_E4_RESERVED_SHIFT		26
1822 };
1823 
1824 /* Completion params for aggregated interrupt completion */
1825 struct sdm_agg_int_comp_params {
1826 	__le16 params;
1827 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK	0x3F
1828 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT	0
1829 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK	0x1
1830 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT	6
1831 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK	0x1FF
1832 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT	7
1833 };
1834 
1835 /* SDM operation gen command (generate aggregative interrupt) */
1836 struct sdm_op_gen {
1837 	__le32 command;
1838 #define SDM_OP_GEN_COMP_PARAM_MASK	0xFFFF
1839 #define SDM_OP_GEN_COMP_PARAM_SHIFT	0
1840 #define SDM_OP_GEN_COMP_TYPE_MASK	0xF
1841 #define SDM_OP_GEN_COMP_TYPE_SHIFT	16
1842 #define SDM_OP_GEN_RESERVED_MASK	0xFFF
1843 #define SDM_OP_GEN_RESERVED_SHIFT	20
1844 };
1845 
1846 /* Physical memory descriptor */
1847 struct phys_mem_desc {
1848 	dma_addr_t phys_addr;
1849 	void *virt_addr;
1850 	u32 size;		/* In bytes */
1851 };
1852 
1853 /* Virtual memory descriptor */
1854 struct virt_mem_desc {
1855 	void *ptr;
1856 	u32 size;		/* In bytes */
1857 };
1858 
1859 /****************************************/
1860 /* Debug Tools HSI constants and macros */
1861 /****************************************/
1862 
1863 enum block_id {
1864 	BLOCK_GRC,
1865 	BLOCK_MISCS,
1866 	BLOCK_MISC,
1867 	BLOCK_DBU,
1868 	BLOCK_PGLUE_B,
1869 	BLOCK_CNIG,
1870 	BLOCK_CPMU,
1871 	BLOCK_NCSI,
1872 	BLOCK_OPTE,
1873 	BLOCK_BMB,
1874 	BLOCK_PCIE,
1875 	BLOCK_MCP,
1876 	BLOCK_MCP2,
1877 	BLOCK_PSWHST,
1878 	BLOCK_PSWHST2,
1879 	BLOCK_PSWRD,
1880 	BLOCK_PSWRD2,
1881 	BLOCK_PSWWR,
1882 	BLOCK_PSWWR2,
1883 	BLOCK_PSWRQ,
1884 	BLOCK_PSWRQ2,
1885 	BLOCK_PGLCS,
1886 	BLOCK_DMAE,
1887 	BLOCK_PTU,
1888 	BLOCK_TCM,
1889 	BLOCK_MCM,
1890 	BLOCK_UCM,
1891 	BLOCK_XCM,
1892 	BLOCK_YCM,
1893 	BLOCK_PCM,
1894 	BLOCK_QM,
1895 	BLOCK_TM,
1896 	BLOCK_DORQ,
1897 	BLOCK_BRB,
1898 	BLOCK_SRC,
1899 	BLOCK_PRS,
1900 	BLOCK_TSDM,
1901 	BLOCK_MSDM,
1902 	BLOCK_USDM,
1903 	BLOCK_XSDM,
1904 	BLOCK_YSDM,
1905 	BLOCK_PSDM,
1906 	BLOCK_TSEM,
1907 	BLOCK_MSEM,
1908 	BLOCK_USEM,
1909 	BLOCK_XSEM,
1910 	BLOCK_YSEM,
1911 	BLOCK_PSEM,
1912 	BLOCK_RSS,
1913 	BLOCK_TMLD,
1914 	BLOCK_MULD,
1915 	BLOCK_YULD,
1916 	BLOCK_XYLD,
1917 	BLOCK_PRM,
1918 	BLOCK_PBF_PB1,
1919 	BLOCK_PBF_PB2,
1920 	BLOCK_RPB,
1921 	BLOCK_BTB,
1922 	BLOCK_PBF,
1923 	BLOCK_RDIF,
1924 	BLOCK_TDIF,
1925 	BLOCK_CDU,
1926 	BLOCK_CCFC,
1927 	BLOCK_TCFC,
1928 	BLOCK_IGU,
1929 	BLOCK_CAU,
1930 	BLOCK_UMAC,
1931 	BLOCK_XMAC,
1932 	BLOCK_MSTAT,
1933 	BLOCK_DBG,
1934 	BLOCK_NIG,
1935 	BLOCK_WOL,
1936 	BLOCK_BMBN,
1937 	BLOCK_IPC,
1938 	BLOCK_NWM,
1939 	BLOCK_NWS,
1940 	BLOCK_MS,
1941 	BLOCK_PHY_PCIE,
1942 	BLOCK_LED,
1943 	BLOCK_AVS_WRAP,
1944 	BLOCK_PXPREQBUS,
1945 	BLOCK_BAR0_MAP,
1946 	BLOCK_MCP_FIO,
1947 	BLOCK_LAST_INIT,
1948 	BLOCK_PRS_FC,
1949 	BLOCK_PBF_FC,
1950 	BLOCK_NIG_LB_FC,
1951 	BLOCK_NIG_LB_FC_PLLH,
1952 	BLOCK_NIG_TX_FC_PLLH,
1953 	BLOCK_NIG_TX_FC,
1954 	BLOCK_NIG_RX_FC_PLLH,
1955 	BLOCK_NIG_RX_FC,
1956 	MAX_BLOCK_ID
1957 };
1958 
1959 /* binary debug buffer types */
1960 enum bin_dbg_buffer_type {
1961 	BIN_BUF_DBG_MODE_TREE,
1962 	BIN_BUF_DBG_DUMP_REG,
1963 	BIN_BUF_DBG_DUMP_MEM,
1964 	BIN_BUF_DBG_IDLE_CHK_REGS,
1965 	BIN_BUF_DBG_IDLE_CHK_IMMS,
1966 	BIN_BUF_DBG_IDLE_CHK_RULES,
1967 	BIN_BUF_DBG_IDLE_CHK_PARSING_DATA,
1968 	BIN_BUF_DBG_ATTN_BLOCKS,
1969 	BIN_BUF_DBG_ATTN_REGS,
1970 	BIN_BUF_DBG_ATTN_INDEXES,
1971 	BIN_BUF_DBG_ATTN_NAME_OFFSETS,
1972 	BIN_BUF_DBG_BLOCKS,
1973 	BIN_BUF_DBG_BLOCKS_CHIP_DATA,
1974 	BIN_BUF_DBG_BUS_LINES,
1975 	BIN_BUF_DBG_BLOCKS_USER_DATA,
1976 	BIN_BUF_DBG_BLOCKS_CHIP_USER_DATA,
1977 	BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS,
1978 	BIN_BUF_DBG_RESET_REGS,
1979 	BIN_BUF_DBG_PARSING_STRINGS,
1980 	MAX_BIN_DBG_BUFFER_TYPE
1981 };
1982 
1983 
1984 /* Attention bit mapping */
1985 struct dbg_attn_bit_mapping {
1986 	u16 data;
1987 #define DBG_ATTN_BIT_MAPPING_VAL_MASK			0x7FFF
1988 #define DBG_ATTN_BIT_MAPPING_VAL_SHIFT			0
1989 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK	0x1
1990 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT	15
1991 };
1992 
1993 /* Attention block per-type data */
1994 struct dbg_attn_block_type_data {
1995 	u16 names_offset;
1996 	u16 reserved1;
1997 	u8 num_regs;
1998 	u8 reserved2;
1999 	u16 regs_offset;
2000 
2001 };
2002 
2003 /* Block attentions */
2004 struct dbg_attn_block {
2005 	struct dbg_attn_block_type_data per_type_data[2];
2006 };
2007 
2008 /* Attention register result */
2009 struct dbg_attn_reg_result {
2010 	u32 data;
2011 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK	0xFFFFFF
2012 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT	0
2013 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK	0xFF
2014 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_SHIFT	24
2015 	u16 block_attn_offset;
2016 	u16 reserved;
2017 	u32 sts_val;
2018 	u32 mask_val;
2019 };
2020 
2021 /* Attention block result */
2022 struct dbg_attn_block_result {
2023 	u8 block_id;
2024 	u8 data;
2025 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK	0x3
2026 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT	0
2027 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK	0x3F
2028 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT	2
2029 	u16 names_offset;
2030 	struct dbg_attn_reg_result reg_results[15];
2031 };
2032 
2033 /* Mode header */
2034 struct dbg_mode_hdr {
2035 	u16 data;
2036 #define DBG_MODE_HDR_EVAL_MODE_MASK		0x1
2037 #define DBG_MODE_HDR_EVAL_MODE_SHIFT		0
2038 #define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK	0x7FFF
2039 #define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT	1
2040 };
2041 
2042 /* Attention register */
2043 struct dbg_attn_reg {
2044 	struct dbg_mode_hdr mode;
2045 	u16 block_attn_offset;
2046 	u32 data;
2047 #define DBG_ATTN_REG_STS_ADDRESS_MASK	0xFFFFFF
2048 #define DBG_ATTN_REG_STS_ADDRESS_SHIFT	0
2049 #define DBG_ATTN_REG_NUM_REG_ATTN_MASK	0xFF
2050 #define DBG_ATTN_REG_NUM_REG_ATTN_SHIFT 24
2051 	u32 sts_clr_address;
2052 	u32 mask_address;
2053 };
2054 
2055 /* Attention types */
2056 enum dbg_attn_type {
2057 	ATTN_TYPE_INTERRUPT,
2058 	ATTN_TYPE_PARITY,
2059 	MAX_DBG_ATTN_TYPE
2060 };
2061 
2062 /* Block debug data */
2063 struct dbg_block {
2064 	u8 name[15];
2065 	u8 associated_storm_letter;
2066 };
2067 
2068 /* Chip-specific block debug data */
2069 struct dbg_block_chip {
2070 	u8 flags;
2071 #define DBG_BLOCK_CHIP_IS_REMOVED_MASK		 0x1
2072 #define DBG_BLOCK_CHIP_IS_REMOVED_SHIFT		 0
2073 #define DBG_BLOCK_CHIP_HAS_RESET_REG_MASK	 0x1
2074 #define DBG_BLOCK_CHIP_HAS_RESET_REG_SHIFT	 1
2075 #define DBG_BLOCK_CHIP_UNRESET_BEFORE_DUMP_MASK  0x1
2076 #define DBG_BLOCK_CHIP_UNRESET_BEFORE_DUMP_SHIFT 2
2077 #define DBG_BLOCK_CHIP_HAS_DBG_BUS_MASK		 0x1
2078 #define DBG_BLOCK_CHIP_HAS_DBG_BUS_SHIFT	 3
2079 #define DBG_BLOCK_CHIP_HAS_LATENCY_EVENTS_MASK	 0x1
2080 #define DBG_BLOCK_CHIP_HAS_LATENCY_EVENTS_SHIFT  4
2081 #define DBG_BLOCK_CHIP_RESERVED0_MASK		 0x7
2082 #define DBG_BLOCK_CHIP_RESERVED0_SHIFT		 5
2083 	u8 dbg_client_id;
2084 	u8 reset_reg_id;
2085 	u8 reset_reg_bit_offset;
2086 	struct dbg_mode_hdr dbg_bus_mode;
2087 	u16 reserved1;
2088 	u8 reserved2;
2089 	u8 num_of_dbg_bus_lines;
2090 	u16 dbg_bus_lines_offset;
2091 	u32 dbg_select_reg_addr;
2092 	u32 dbg_dword_enable_reg_addr;
2093 	u32 dbg_shift_reg_addr;
2094 	u32 dbg_force_valid_reg_addr;
2095 	u32 dbg_force_frame_reg_addr;
2096 };
2097 
2098 /* Chip-specific block user debug data */
2099 struct dbg_block_chip_user {
2100 	u8 num_of_dbg_bus_lines;
2101 	u8 has_latency_events;
2102 	u16 names_offset;
2103 };
2104 
2105 /* Block user debug data */
2106 struct dbg_block_user {
2107 	u8 name[16];
2108 };
2109 
2110 /* Block Debug line data */
2111 struct dbg_bus_line {
2112 	u8 data;
2113 #define DBG_BUS_LINE_NUM_OF_GROUPS_MASK		0xF
2114 #define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT	0
2115 #define DBG_BUS_LINE_IS_256B_MASK		0x1
2116 #define DBG_BUS_LINE_IS_256B_SHIFT		4
2117 #define DBG_BUS_LINE_RESERVED_MASK		0x7
2118 #define DBG_BUS_LINE_RESERVED_SHIFT		5
2119 	u8 group_sizes;
2120 };
2121 
2122 /* Condition header for registers dump */
2123 struct dbg_dump_cond_hdr {
2124 	struct dbg_mode_hdr mode; /* Mode header */
2125 	u8 block_id; /* block ID */
2126 	u8 data_size; /* size in dwords of the data following this header */
2127 };
2128 
2129 /* Memory data for registers dump */
2130 struct dbg_dump_mem {
2131 	u32 dword0;
2132 #define DBG_DUMP_MEM_ADDRESS_MASK	0xFFFFFF
2133 #define DBG_DUMP_MEM_ADDRESS_SHIFT	0
2134 #define DBG_DUMP_MEM_MEM_GROUP_ID_MASK	0xFF
2135 #define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT	24
2136 	u32 dword1;
2137 #define DBG_DUMP_MEM_LENGTH_MASK	0xFFFFFF
2138 #define DBG_DUMP_MEM_LENGTH_SHIFT	0
2139 #define DBG_DUMP_MEM_WIDE_BUS_MASK	0x1
2140 #define DBG_DUMP_MEM_WIDE_BUS_SHIFT	24
2141 #define DBG_DUMP_MEM_RESERVED_MASK	0x7F
2142 #define DBG_DUMP_MEM_RESERVED_SHIFT	25
2143 };
2144 
2145 /* Register data for registers dump */
2146 struct dbg_dump_reg {
2147 	u32 data;
2148 #define DBG_DUMP_REG_ADDRESS_MASK	0x7FFFFF
2149 #define DBG_DUMP_REG_ADDRESS_SHIFT	0
2150 #define DBG_DUMP_REG_WIDE_BUS_MASK	0x1
2151 #define DBG_DUMP_REG_WIDE_BUS_SHIFT	23
2152 #define DBG_DUMP_REG_LENGTH_MASK	0xFF
2153 #define DBG_DUMP_REG_LENGTH_SHIFT	24
2154 };
2155 
2156 /* Split header for registers dump */
2157 struct dbg_dump_split_hdr {
2158 	u32 hdr;
2159 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK	0xFFFFFF
2160 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT	0
2161 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK	0xFF
2162 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT	24
2163 };
2164 
2165 /* Condition header for idle check */
2166 struct dbg_idle_chk_cond_hdr {
2167 	struct dbg_mode_hdr mode; /* Mode header */
2168 	u16 data_size; /* size in dwords of the data following this header */
2169 };
2170 
2171 /* Idle Check condition register */
2172 struct dbg_idle_chk_cond_reg {
2173 	u32 data;
2174 #define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK	0x7FFFFF
2175 #define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT	0
2176 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK	0x1
2177 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT	23
2178 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK	0xFF
2179 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT	24
2180 	u16 num_entries;
2181 	u8 entry_size;
2182 	u8 start_entry;
2183 };
2184 
2185 /* Idle Check info register */
2186 struct dbg_idle_chk_info_reg {
2187 	u32 data;
2188 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK	0x7FFFFF
2189 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT	0
2190 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK	0x1
2191 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT	23
2192 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK	0xFF
2193 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT	24
2194 	u16 size; /* register size in dwords */
2195 	struct dbg_mode_hdr mode; /* Mode header */
2196 };
2197 
2198 /* Idle Check register */
2199 union dbg_idle_chk_reg {
2200 	struct dbg_idle_chk_cond_reg cond_reg; /* condition register */
2201 	struct dbg_idle_chk_info_reg info_reg; /* info register */
2202 };
2203 
2204 /* Idle Check result header */
2205 struct dbg_idle_chk_result_hdr {
2206 	u16 rule_id; /* Failing rule index */
2207 	u16 mem_entry_id; /* Failing memory entry index */
2208 	u8 num_dumped_cond_regs; /* number of dumped condition registers */
2209 	u8 num_dumped_info_regs; /* number of dumped condition registers */
2210 	u8 severity; /* from dbg_idle_chk_severity_types enum */
2211 	u8 reserved;
2212 };
2213 
2214 /* Idle Check result register header */
2215 struct dbg_idle_chk_result_reg_hdr {
2216 	u8 data;
2217 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK  0x1
2218 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0
2219 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK  0x7F
2220 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1
2221 	u8 start_entry; /* index of the first checked entry */
2222 	u16 size; /* register size in dwords */
2223 };
2224 
2225 /* Idle Check rule */
2226 struct dbg_idle_chk_rule {
2227 	u16 rule_id; /* Idle Check rule ID */
2228 	u8 severity; /* value from dbg_idle_chk_severity_types enum */
2229 	u8 cond_id; /* Condition ID */
2230 	u8 num_cond_regs; /* number of condition registers */
2231 	u8 num_info_regs; /* number of info registers */
2232 	u8 num_imms; /* number of immediates in the condition */
2233 	u8 reserved1;
2234 	u16 reg_offset; /* offset of this rules registers in the idle check
2235 			 * register array (in dbg_idle_chk_reg units).
2236 			 */
2237 	u16 imm_offset; /* offset of this rules immediate values in the
2238 			 * immediate values array (in dwords).
2239 			 */
2240 };
2241 
2242 /* Idle Check rule parsing data */
2243 struct dbg_idle_chk_rule_parsing_data {
2244 	u32 data;
2245 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK	0x1
2246 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT	0
2247 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK	0x7FFFFFFF
2248 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT	1
2249 };
2250 
2251 /* Idle check severity types */
2252 enum dbg_idle_chk_severity_types {
2253 	/* idle check failure should cause an error */
2254 	IDLE_CHK_SEVERITY_ERROR,
2255 	/* idle check failure should cause an error only if theres no traffic */
2256 	IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC,
2257 	/* idle check failure should cause a warning */
2258 	IDLE_CHK_SEVERITY_WARNING,
2259 	MAX_DBG_IDLE_CHK_SEVERITY_TYPES
2260 };
2261 
2262 /* Reset register */
2263 struct dbg_reset_reg {
2264 	u32 data;
2265 #define DBG_RESET_REG_ADDR_MASK        0xFFFFFF
2266 #define DBG_RESET_REG_ADDR_SHIFT       0
2267 #define DBG_RESET_REG_IS_REMOVED_MASK  0x1
2268 #define DBG_RESET_REG_IS_REMOVED_SHIFT 24
2269 #define DBG_RESET_REG_RESERVED_MASK    0x7F
2270 #define DBG_RESET_REG_RESERVED_SHIFT   25
2271 };
2272 
2273 /* Debug Bus block data */
2274 struct dbg_bus_block_data {
2275 	u8 enable_mask;
2276 	u8 right_shift;
2277 	u8 force_valid_mask;
2278 	u8 force_frame_mask;
2279 	u8 dword_mask;
2280 	u8 line_num;
2281 	u8 hw_id;
2282 	u8 flags;
2283 #define DBG_BUS_BLOCK_DATA_IS_256B_LINE_MASK  0x1
2284 #define DBG_BUS_BLOCK_DATA_IS_256B_LINE_SHIFT 0
2285 #define DBG_BUS_BLOCK_DATA_RESERVED_MASK      0x7F
2286 #define DBG_BUS_BLOCK_DATA_RESERVED_SHIFT     1
2287 };
2288 
2289 enum dbg_bus_clients {
2290 	DBG_BUS_CLIENT_RBCN,
2291 	DBG_BUS_CLIENT_RBCP,
2292 	DBG_BUS_CLIENT_RBCR,
2293 	DBG_BUS_CLIENT_RBCT,
2294 	DBG_BUS_CLIENT_RBCU,
2295 	DBG_BUS_CLIENT_RBCF,
2296 	DBG_BUS_CLIENT_RBCX,
2297 	DBG_BUS_CLIENT_RBCS,
2298 	DBG_BUS_CLIENT_RBCH,
2299 	DBG_BUS_CLIENT_RBCZ,
2300 	DBG_BUS_CLIENT_OTHER_ENGINE,
2301 	DBG_BUS_CLIENT_TIMESTAMP,
2302 	DBG_BUS_CLIENT_CPU,
2303 	DBG_BUS_CLIENT_RBCY,
2304 	DBG_BUS_CLIENT_RBCQ,
2305 	DBG_BUS_CLIENT_RBCM,
2306 	DBG_BUS_CLIENT_RBCB,
2307 	DBG_BUS_CLIENT_RBCW,
2308 	DBG_BUS_CLIENT_RBCV,
2309 	MAX_DBG_BUS_CLIENTS
2310 };
2311 
2312 /* Debug Bus constraint operation types */
2313 enum dbg_bus_constraint_ops {
2314 	DBG_BUS_CONSTRAINT_OP_EQ,
2315 	DBG_BUS_CONSTRAINT_OP_NE,
2316 	DBG_BUS_CONSTRAINT_OP_LT,
2317 	DBG_BUS_CONSTRAINT_OP_LTC,
2318 	DBG_BUS_CONSTRAINT_OP_LE,
2319 	DBG_BUS_CONSTRAINT_OP_LEC,
2320 	DBG_BUS_CONSTRAINT_OP_GT,
2321 	DBG_BUS_CONSTRAINT_OP_GTC,
2322 	DBG_BUS_CONSTRAINT_OP_GE,
2323 	DBG_BUS_CONSTRAINT_OP_GEC,
2324 	MAX_DBG_BUS_CONSTRAINT_OPS
2325 };
2326 
2327 /* Debug Bus trigger state data */
2328 struct dbg_bus_trigger_state_data {
2329 	u8 msg_len;
2330 	u8 constraint_dword_mask;
2331 	u8 storm_id;
2332 	u8 reserved;
2333 };
2334 
2335 /* Debug Bus memory address */
2336 struct dbg_bus_mem_addr {
2337 	u32 lo;
2338 	u32 hi;
2339 };
2340 
2341 /* Debug Bus PCI buffer data */
2342 struct dbg_bus_pci_buf_data {
2343 	struct dbg_bus_mem_addr phys_addr; /* PCI buffer physical address */
2344 	struct dbg_bus_mem_addr virt_addr; /* PCI buffer virtual address */
2345 	u32 size; /* PCI buffer size in bytes */
2346 };
2347 
2348 /* Debug Bus Storm EID range filter params */
2349 struct dbg_bus_storm_eid_range_params {
2350 	u8 min; /* Minimal event ID to filter on */
2351 	u8 max; /* Maximal event ID to filter on */
2352 };
2353 
2354 /* Debug Bus Storm EID mask filter params */
2355 struct dbg_bus_storm_eid_mask_params {
2356 	u8 val; /* Event ID value */
2357 	u8 mask; /* Event ID mask. 1s in the mask = dont care bits. */
2358 };
2359 
2360 /* Debug Bus Storm EID filter params */
2361 union dbg_bus_storm_eid_params {
2362 	struct dbg_bus_storm_eid_range_params range;
2363 	struct dbg_bus_storm_eid_mask_params mask;
2364 };
2365 
2366 /* Debug Bus Storm data */
2367 struct dbg_bus_storm_data {
2368 	u8 enabled;
2369 	u8 mode;
2370 	u8 hw_id;
2371 	u8 eid_filter_en;
2372 	u8 eid_range_not_mask;
2373 	u8 cid_filter_en;
2374 	union dbg_bus_storm_eid_params eid_filter_params;
2375 	u32 cid;
2376 };
2377 
2378 /* Debug Bus data */
2379 struct dbg_bus_data {
2380 	u32 app_version;
2381 	u8 state;
2382 	u8 mode_256b_en;
2383 	u8 num_enabled_blocks;
2384 	u8 num_enabled_storms;
2385 	u8 target;
2386 	u8 one_shot_en;
2387 	u8 grc_input_en;
2388 	u8 timestamp_input_en;
2389 	u8 filter_en;
2390 	u8 adding_filter;
2391 	u8 filter_pre_trigger;
2392 	u8 filter_post_trigger;
2393 	u8 trigger_en;
2394 	u8 filter_constraint_dword_mask;
2395 	u8 next_trigger_state;
2396 	u8 next_constraint_id;
2397 	struct dbg_bus_trigger_state_data trigger_states[3];
2398 	u8 filter_msg_len;
2399 	u8 rcv_from_other_engine;
2400 	u8 blocks_dword_mask;
2401 	u8 blocks_dword_overlap;
2402 	u32 hw_id_mask;
2403 	struct dbg_bus_pci_buf_data pci_buf;
2404 	struct dbg_bus_block_data blocks[132];
2405 	struct dbg_bus_storm_data storms[6];
2406 };
2407 
2408 /* Debug bus states */
2409 enum dbg_bus_states {
2410 	DBG_BUS_STATE_IDLE,
2411 	DBG_BUS_STATE_READY,
2412 	DBG_BUS_STATE_RECORDING,
2413 	DBG_BUS_STATE_STOPPED,
2414 	MAX_DBG_BUS_STATES
2415 };
2416 
2417 /* Debug Bus Storm modes */
2418 enum dbg_bus_storm_modes {
2419 	DBG_BUS_STORM_MODE_PRINTF,
2420 	DBG_BUS_STORM_MODE_PRAM_ADDR,
2421 	DBG_BUS_STORM_MODE_DRA_RW,
2422 	DBG_BUS_STORM_MODE_DRA_W,
2423 	DBG_BUS_STORM_MODE_LD_ST_ADDR,
2424 	DBG_BUS_STORM_MODE_DRA_FSM,
2425 	DBG_BUS_STORM_MODE_FAST_DBGMUX,
2426 	DBG_BUS_STORM_MODE_RH,
2427 	DBG_BUS_STORM_MODE_RH_WITH_STORE,
2428 	DBG_BUS_STORM_MODE_FOC,
2429 	DBG_BUS_STORM_MODE_EXT_STORE,
2430 	MAX_DBG_BUS_STORM_MODES
2431 };
2432 
2433 /* Debug bus target IDs */
2434 enum dbg_bus_targets {
2435 	DBG_BUS_TARGET_ID_INT_BUF,
2436 	DBG_BUS_TARGET_ID_NIG,
2437 	DBG_BUS_TARGET_ID_PCI,
2438 	MAX_DBG_BUS_TARGETS
2439 };
2440 
2441 /* GRC Dump data */
2442 struct dbg_grc_data {
2443 	u8 params_initialized;
2444 	u8 reserved1;
2445 	u16 reserved2;
2446 	u32 param_val[48];
2447 };
2448 
2449 /* Debug GRC params */
2450 enum dbg_grc_params {
2451 	DBG_GRC_PARAM_DUMP_TSTORM,
2452 	DBG_GRC_PARAM_DUMP_MSTORM,
2453 	DBG_GRC_PARAM_DUMP_USTORM,
2454 	DBG_GRC_PARAM_DUMP_XSTORM,
2455 	DBG_GRC_PARAM_DUMP_YSTORM,
2456 	DBG_GRC_PARAM_DUMP_PSTORM,
2457 	DBG_GRC_PARAM_DUMP_REGS,
2458 	DBG_GRC_PARAM_DUMP_RAM,
2459 	DBG_GRC_PARAM_DUMP_PBUF,
2460 	DBG_GRC_PARAM_DUMP_IOR,
2461 	DBG_GRC_PARAM_DUMP_VFC,
2462 	DBG_GRC_PARAM_DUMP_CM_CTX,
2463 	DBG_GRC_PARAM_DUMP_PXP,
2464 	DBG_GRC_PARAM_DUMP_RSS,
2465 	DBG_GRC_PARAM_DUMP_CAU,
2466 	DBG_GRC_PARAM_DUMP_QM,
2467 	DBG_GRC_PARAM_DUMP_MCP,
2468 	DBG_GRC_PARAM_DUMP_DORQ,
2469 	DBG_GRC_PARAM_DUMP_CFC,
2470 	DBG_GRC_PARAM_DUMP_IGU,
2471 	DBG_GRC_PARAM_DUMP_BRB,
2472 	DBG_GRC_PARAM_DUMP_BTB,
2473 	DBG_GRC_PARAM_DUMP_BMB,
2474 	DBG_GRC_PARAM_RESERVD1,
2475 	DBG_GRC_PARAM_DUMP_MULD,
2476 	DBG_GRC_PARAM_DUMP_PRS,
2477 	DBG_GRC_PARAM_DUMP_DMAE,
2478 	DBG_GRC_PARAM_DUMP_TM,
2479 	DBG_GRC_PARAM_DUMP_SDM,
2480 	DBG_GRC_PARAM_DUMP_DIF,
2481 	DBG_GRC_PARAM_DUMP_STATIC,
2482 	DBG_GRC_PARAM_UNSTALL,
2483 	DBG_GRC_PARAM_RESERVED2,
2484 	DBG_GRC_PARAM_MCP_TRACE_META_SIZE,
2485 	DBG_GRC_PARAM_EXCLUDE_ALL,
2486 	DBG_GRC_PARAM_CRASH,
2487 	DBG_GRC_PARAM_PARITY_SAFE,
2488 	DBG_GRC_PARAM_DUMP_CM,
2489 	DBG_GRC_PARAM_DUMP_PHY,
2490 	DBG_GRC_PARAM_NO_MCP,
2491 	DBG_GRC_PARAM_NO_FW_VER,
2492 	DBG_GRC_PARAM_RESERVED3,
2493 	DBG_GRC_PARAM_DUMP_MCP_HW_DUMP,
2494 	DBG_GRC_PARAM_DUMP_ILT_CDUC,
2495 	DBG_GRC_PARAM_DUMP_ILT_CDUT,
2496 	DBG_GRC_PARAM_DUMP_CAU_EXT,
2497 	MAX_DBG_GRC_PARAMS
2498 };
2499 
2500 /* Debug status codes */
2501 enum dbg_status {
2502 	DBG_STATUS_OK,
2503 	DBG_STATUS_APP_VERSION_NOT_SET,
2504 	DBG_STATUS_UNSUPPORTED_APP_VERSION,
2505 	DBG_STATUS_DBG_BLOCK_NOT_RESET,
2506 	DBG_STATUS_INVALID_ARGS,
2507 	DBG_STATUS_OUTPUT_ALREADY_SET,
2508 	DBG_STATUS_INVALID_PCI_BUF_SIZE,
2509 	DBG_STATUS_PCI_BUF_ALLOC_FAILED,
2510 	DBG_STATUS_PCI_BUF_NOT_ALLOCATED,
2511 	DBG_STATUS_INVALID_FILTER_TRIGGER_DWORDS,
2512 	DBG_STATUS_NO_MATCHING_FRAMING_MODE,
2513 	DBG_STATUS_VFC_READ_ERROR,
2514 	DBG_STATUS_STORM_ALREADY_ENABLED,
2515 	DBG_STATUS_STORM_NOT_ENABLED,
2516 	DBG_STATUS_BLOCK_ALREADY_ENABLED,
2517 	DBG_STATUS_BLOCK_NOT_ENABLED,
2518 	DBG_STATUS_NO_INPUT_ENABLED,
2519 	DBG_STATUS_NO_FILTER_TRIGGER_256B,
2520 	DBG_STATUS_FILTER_ALREADY_ENABLED,
2521 	DBG_STATUS_TRIGGER_ALREADY_ENABLED,
2522 	DBG_STATUS_TRIGGER_NOT_ENABLED,
2523 	DBG_STATUS_CANT_ADD_CONSTRAINT,
2524 	DBG_STATUS_TOO_MANY_TRIGGER_STATES,
2525 	DBG_STATUS_TOO_MANY_CONSTRAINTS,
2526 	DBG_STATUS_RECORDING_NOT_STARTED,
2527 	DBG_STATUS_DATA_DIDNT_TRIGGER,
2528 	DBG_STATUS_NO_DATA_RECORDED,
2529 	DBG_STATUS_DUMP_BUF_TOO_SMALL,
2530 	DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED,
2531 	DBG_STATUS_UNKNOWN_CHIP,
2532 	DBG_STATUS_VIRT_MEM_ALLOC_FAILED,
2533 	DBG_STATUS_BLOCK_IN_RESET,
2534 	DBG_STATUS_INVALID_TRACE_SIGNATURE,
2535 	DBG_STATUS_INVALID_NVRAM_BUNDLE,
2536 	DBG_STATUS_NVRAM_GET_IMAGE_FAILED,
2537 	DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE,
2538 	DBG_STATUS_NVRAM_READ_FAILED,
2539 	DBG_STATUS_IDLE_CHK_PARSE_FAILED,
2540 	DBG_STATUS_MCP_TRACE_BAD_DATA,
2541 	DBG_STATUS_MCP_TRACE_NO_META,
2542 	DBG_STATUS_MCP_COULD_NOT_HALT,
2543 	DBG_STATUS_MCP_COULD_NOT_RESUME,
2544 	DBG_STATUS_RESERVED0,
2545 	DBG_STATUS_SEMI_FIFO_NOT_EMPTY,
2546 	DBG_STATUS_IGU_FIFO_BAD_DATA,
2547 	DBG_STATUS_MCP_COULD_NOT_MASK_PRTY,
2548 	DBG_STATUS_FW_ASSERTS_PARSE_FAILED,
2549 	DBG_STATUS_REG_FIFO_BAD_DATA,
2550 	DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA,
2551 	DBG_STATUS_DBG_ARRAY_NOT_SET,
2552 	DBG_STATUS_RESERVED1,
2553 	DBG_STATUS_NON_MATCHING_LINES,
2554 	DBG_STATUS_INSUFFICIENT_HW_IDS,
2555 	DBG_STATUS_DBG_BUS_IN_USE,
2556 	DBG_STATUS_INVALID_STORM_DBG_MODE,
2557 	DBG_STATUS_OTHER_ENGINE_BB_ONLY,
2558 	DBG_STATUS_FILTER_SINGLE_HW_ID,
2559 	DBG_STATUS_TRIGGER_SINGLE_HW_ID,
2560 	DBG_STATUS_MISSING_TRIGGER_STATE_STORM,
2561 	MAX_DBG_STATUS
2562 };
2563 
2564 /* Debug Storms IDs */
2565 enum dbg_storms {
2566 	DBG_TSTORM_ID,
2567 	DBG_MSTORM_ID,
2568 	DBG_USTORM_ID,
2569 	DBG_XSTORM_ID,
2570 	DBG_YSTORM_ID,
2571 	DBG_PSTORM_ID,
2572 	MAX_DBG_STORMS
2573 };
2574 
2575 /* Idle Check data */
2576 struct idle_chk_data {
2577 	u32 buf_size;
2578 	u8 buf_size_set;
2579 	u8 reserved1;
2580 	u16 reserved2;
2581 };
2582 
2583 struct pretend_params {
2584 	u8 split_type;
2585 	u8 reserved;
2586 	u16 split_id;
2587 };
2588 
2589 /* Debug Tools data (per HW function)
2590  */
2591 struct dbg_tools_data {
2592 	struct dbg_grc_data grc;
2593 	struct dbg_bus_data bus;
2594 	struct idle_chk_data idle_chk;
2595 	u8 mode_enable[40];
2596 	u8 block_in_reset[132];
2597 	u8 chip_id;
2598 	u8 hw_type;
2599 	u8 num_ports;
2600 	u8 num_pfs_per_port;
2601 	u8 num_vfs;
2602 	u8 initialized;
2603 	u8 use_dmae;
2604 	u8 reserved;
2605 	struct pretend_params pretend;
2606 	u32 num_regs_read;
2607 };
2608 
2609 /* ILT Clients */
2610 enum ilt_clients {
2611 	ILT_CLI_CDUC,
2612 	ILT_CLI_CDUT,
2613 	ILT_CLI_QM,
2614 	ILT_CLI_TM,
2615 	ILT_CLI_SRC,
2616 	ILT_CLI_TSDM,
2617 	ILT_CLI_RGFS,
2618 	ILT_CLI_TGFS,
2619 	MAX_ILT_CLIENTS
2620 };
2621 
2622 /********************************/
2623 /* HSI Init Functions constants */
2624 /********************************/
2625 
2626 /* Number of VLAN priorities */
2627 #define NUM_OF_VLAN_PRIORITIES	8
2628 
2629 /* BRB RAM init requirements */
2630 struct init_brb_ram_req {
2631 	u32 guranteed_per_tc;
2632 	u32 headroom_per_tc;
2633 	u32 min_pkt_size;
2634 	u32 max_ports_per_engine;
2635 	u8 num_active_tcs[MAX_NUM_PORTS];
2636 };
2637 
2638 /* ETS per-TC init requirements */
2639 struct init_ets_tc_req {
2640 	u8 use_sp;
2641 	u8 use_wfq;
2642 	u16 weight;
2643 };
2644 
2645 /* ETS init requirements */
2646 struct init_ets_req {
2647 	u32 mtu;
2648 	struct init_ets_tc_req tc_req[NUM_OF_TCS];
2649 };
2650 
2651 /* NIG LB RL init requirements */
2652 struct init_nig_lb_rl_req {
2653 	u16 lb_mac_rate;
2654 	u16 lb_rate;
2655 	u32 mtu;
2656 	u16 tc_rate[NUM_OF_PHYS_TCS];
2657 };
2658 
2659 /* NIG TC mapping for each priority */
2660 struct init_nig_pri_tc_map_entry {
2661 	u8 tc_id;
2662 	u8 valid;
2663 };
2664 
2665 /* NIG priority to TC map init requirements */
2666 struct init_nig_pri_tc_map_req {
2667 	struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES];
2668 };
2669 
2670 /* QM per global RL init parameters */
2671 struct init_qm_global_rl_params {
2672 	u32 rate_limit;
2673 };
2674 
2675 /* QM per-port init parameters */
2676 struct init_qm_port_params {
2677 	u16 active_phys_tcs;
2678 	u16 num_pbf_cmd_lines;
2679 	u16 num_btb_blocks;
2680 	u8 active;
2681 	u8 reserved;
2682 };
2683 
2684 /* QM per-PQ init parameters */
2685 struct init_qm_pq_params {
2686 	u8 vport_id;
2687 	u8 tc_id;
2688 	u8 wrr_group;
2689 	u8 rl_valid;
2690 	u16 rl_id;
2691 	u8 port_id;
2692 	u8 reserved;
2693 };
2694 
2695 /* QM per-vport init parameters */
2696 struct init_qm_vport_params {
2697 	u16 wfq;
2698 	u16 first_tx_pq_id[NUM_OF_TCS];
2699 };
2700 
2701 /**************************************/
2702 /* Init Tool HSI constants and macros */
2703 /**************************************/
2704 
2705 /* Width of GRC address in bits (addresses are specified in dwords) */
2706 #define GRC_ADDR_BITS	23
2707 #define MAX_GRC_ADDR	(BIT(GRC_ADDR_BITS) - 1)
2708 
2709 /* indicates an init that should be applied to any phase ID */
2710 #define ANY_PHASE_ID	0xffff
2711 
2712 /* Max size in dwords of a zipped array */
2713 #define MAX_ZIPPED_SIZE	8192
2714 enum chip_ids {
2715 	CHIP_BB,
2716 	CHIP_K2,
2717 	MAX_CHIP_IDS
2718 };
2719 
2720 struct fw_asserts_ram_section {
2721 	__le16 section_ram_line_offset;
2722 	__le16 section_ram_line_size;
2723 	u8 list_dword_offset;
2724 	u8 list_element_dword_size;
2725 	u8 list_num_elements;
2726 	u8 list_next_index_dword_offset;
2727 };
2728 
2729 struct fw_ver_num {
2730 	u8 major;
2731 	u8 minor;
2732 	u8 rev;
2733 	u8 eng;
2734 };
2735 
2736 struct fw_ver_info {
2737 	__le16 tools_ver;
2738 	u8 image_id;
2739 	u8 reserved1;
2740 	struct fw_ver_num num;
2741 	__le32 timestamp;
2742 	__le32 reserved2;
2743 };
2744 
2745 struct fw_info {
2746 	struct fw_ver_info ver;
2747 	struct fw_asserts_ram_section fw_asserts_section;
2748 };
2749 
2750 struct fw_info_location {
2751 	__le32 grc_addr;
2752 	__le32 size;
2753 };
2754 
2755 enum init_modes {
2756 	MODE_RESERVED,
2757 	MODE_BB,
2758 	MODE_K2,
2759 	MODE_ASIC,
2760 	MODE_RESERVED2,
2761 	MODE_RESERVED3,
2762 	MODE_RESERVED4,
2763 	MODE_RESERVED5,
2764 	MODE_SF,
2765 	MODE_MF_SD,
2766 	MODE_MF_SI,
2767 	MODE_PORTS_PER_ENG_1,
2768 	MODE_PORTS_PER_ENG_2,
2769 	MODE_PORTS_PER_ENG_4,
2770 	MODE_100G,
2771 	MODE_RESERVED6,
2772 	MODE_RESERVED7,
2773 	MAX_INIT_MODES
2774 };
2775 
2776 enum init_phases {
2777 	PHASE_ENGINE,
2778 	PHASE_PORT,
2779 	PHASE_PF,
2780 	PHASE_VF,
2781 	PHASE_QM_PF,
2782 	MAX_INIT_PHASES
2783 };
2784 
2785 enum init_split_types {
2786 	SPLIT_TYPE_NONE,
2787 	SPLIT_TYPE_PORT,
2788 	SPLIT_TYPE_PF,
2789 	SPLIT_TYPE_PORT_PF,
2790 	SPLIT_TYPE_VF,
2791 	MAX_INIT_SPLIT_TYPES
2792 };
2793 
2794 /* Binary buffer header */
2795 struct bin_buffer_hdr {
2796 	u32 offset;
2797 	u32 length;
2798 };
2799 
2800 /* Binary init buffer types */
2801 enum bin_init_buffer_type {
2802 	BIN_BUF_INIT_FW_VER_INFO,
2803 	BIN_BUF_INIT_CMD,
2804 	BIN_BUF_INIT_VAL,
2805 	BIN_BUF_INIT_MODE_TREE,
2806 	BIN_BUF_INIT_IRO,
2807 	BIN_BUF_INIT_OVERLAYS,
2808 	MAX_BIN_INIT_BUFFER_TYPE
2809 };
2810 
2811 /* FW overlay buffer header */
2812 struct fw_overlay_buf_hdr {
2813 	u32 data;
2814 #define FW_OVERLAY_BUF_HDR_STORM_ID_MASK  0xFF
2815 #define FW_OVERLAY_BUF_HDR_STORM_ID_SHIFT 0
2816 #define FW_OVERLAY_BUF_HDR_BUF_SIZE_MASK  0xFFFFFF
2817 #define FW_OVERLAY_BUF_HDR_BUF_SIZE_SHIFT 8
2818 };
2819 
2820 /* init array header: raw */
2821 struct init_array_raw_hdr {
2822 	u32 data;
2823 #define INIT_ARRAY_RAW_HDR_TYPE_MASK	0xF
2824 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT	0
2825 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK	0xFFFFFFF
2826 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT	4
2827 };
2828 
2829 /* init array header: standard */
2830 struct init_array_standard_hdr {
2831 	u32 data;
2832 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK	0xF
2833 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT	0
2834 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK	0xFFFFFFF
2835 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT	4
2836 };
2837 
2838 /* init array header: zipped */
2839 struct init_array_zipped_hdr {
2840 	u32 data;
2841 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK		0xF
2842 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT	0
2843 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK	0xFFFFFFF
2844 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT	4
2845 };
2846 
2847 /* init array header: pattern */
2848 struct init_array_pattern_hdr {
2849 	u32 data;
2850 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK		0xF
2851 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT		0
2852 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK	0xF
2853 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT	4
2854 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK		0xFFFFFF
2855 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT	8
2856 };
2857 
2858 /* init array header union */
2859 union init_array_hdr {
2860 	struct init_array_raw_hdr raw;
2861 	struct init_array_standard_hdr standard;
2862 	struct init_array_zipped_hdr zipped;
2863 	struct init_array_pattern_hdr pattern;
2864 };
2865 
2866 /* init array types */
2867 enum init_array_types {
2868 	INIT_ARR_STANDARD,
2869 	INIT_ARR_ZIPPED,
2870 	INIT_ARR_PATTERN,
2871 	MAX_INIT_ARRAY_TYPES
2872 };
2873 
2874 /* init operation: callback */
2875 struct init_callback_op {
2876 	u32 op_data;
2877 #define INIT_CALLBACK_OP_OP_MASK	0xF
2878 #define INIT_CALLBACK_OP_OP_SHIFT	0
2879 #define INIT_CALLBACK_OP_RESERVED_MASK	0xFFFFFFF
2880 #define INIT_CALLBACK_OP_RESERVED_SHIFT	4
2881 	u16 callback_id;
2882 	u16 block_id;
2883 };
2884 
2885 /* init operation: delay */
2886 struct init_delay_op {
2887 	u32 op_data;
2888 #define INIT_DELAY_OP_OP_MASK		0xF
2889 #define INIT_DELAY_OP_OP_SHIFT		0
2890 #define INIT_DELAY_OP_RESERVED_MASK	0xFFFFFFF
2891 #define INIT_DELAY_OP_RESERVED_SHIFT	4
2892 	u32 delay;
2893 };
2894 
2895 /* init operation: if_mode */
2896 struct init_if_mode_op {
2897 	u32 op_data;
2898 #define INIT_IF_MODE_OP_OP_MASK			0xF
2899 #define INIT_IF_MODE_OP_OP_SHIFT		0
2900 #define INIT_IF_MODE_OP_RESERVED1_MASK		0xFFF
2901 #define INIT_IF_MODE_OP_RESERVED1_SHIFT		4
2902 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK		0xFFFF
2903 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT	16
2904 	u16 reserved2;
2905 	u16 modes_buf_offset;
2906 };
2907 
2908 /* init operation: if_phase */
2909 struct init_if_phase_op {
2910 	u32 op_data;
2911 #define INIT_IF_PHASE_OP_OP_MASK		0xF
2912 #define INIT_IF_PHASE_OP_OP_SHIFT		0
2913 #define INIT_IF_PHASE_OP_RESERVED1_MASK		0xFFF
2914 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT	4
2915 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK	0xFFFF
2916 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT	16
2917 	u32 phase_data;
2918 #define INIT_IF_PHASE_OP_PHASE_MASK		0xFF
2919 #define INIT_IF_PHASE_OP_PHASE_SHIFT		0
2920 #define INIT_IF_PHASE_OP_RESERVED2_MASK		0xFF
2921 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT	8
2922 #define INIT_IF_PHASE_OP_PHASE_ID_MASK		0xFFFF
2923 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT		16
2924 };
2925 
2926 /* init mode operators */
2927 enum init_mode_ops {
2928 	INIT_MODE_OP_NOT,
2929 	INIT_MODE_OP_OR,
2930 	INIT_MODE_OP_AND,
2931 	MAX_INIT_MODE_OPS
2932 };
2933 
2934 /* init operation: raw */
2935 struct init_raw_op {
2936 	u32 op_data;
2937 #define INIT_RAW_OP_OP_MASK		0xF
2938 #define INIT_RAW_OP_OP_SHIFT		0
2939 #define INIT_RAW_OP_PARAM1_MASK		0xFFFFFFF
2940 #define INIT_RAW_OP_PARAM1_SHIFT	4
2941 	u32 param2;
2942 };
2943 
2944 /* init array params */
2945 struct init_op_array_params {
2946 	u16 size;
2947 	u16 offset;
2948 };
2949 
2950 /* Write init operation arguments */
2951 union init_write_args {
2952 	u32 inline_val;
2953 	u32 zeros_count;
2954 	u32 array_offset;
2955 	struct init_op_array_params runtime;
2956 };
2957 
2958 /* init operation: write */
2959 struct init_write_op {
2960 	u32 data;
2961 #define INIT_WRITE_OP_OP_MASK		0xF
2962 #define INIT_WRITE_OP_OP_SHIFT		0
2963 #define INIT_WRITE_OP_SOURCE_MASK	0x7
2964 #define INIT_WRITE_OP_SOURCE_SHIFT	4
2965 #define INIT_WRITE_OP_RESERVED_MASK	0x1
2966 #define INIT_WRITE_OP_RESERVED_SHIFT	7
2967 #define INIT_WRITE_OP_WIDE_BUS_MASK	0x1
2968 #define INIT_WRITE_OP_WIDE_BUS_SHIFT	8
2969 #define INIT_WRITE_OP_ADDRESS_MASK	0x7FFFFF
2970 #define INIT_WRITE_OP_ADDRESS_SHIFT	9
2971 	union init_write_args args;
2972 };
2973 
2974 /* init operation: read */
2975 struct init_read_op {
2976 	u32 op_data;
2977 #define INIT_READ_OP_OP_MASK		0xF
2978 #define INIT_READ_OP_OP_SHIFT		0
2979 #define INIT_READ_OP_POLL_TYPE_MASK	0xF
2980 #define INIT_READ_OP_POLL_TYPE_SHIFT	4
2981 #define INIT_READ_OP_RESERVED_MASK	0x1
2982 #define INIT_READ_OP_RESERVED_SHIFT	8
2983 #define INIT_READ_OP_ADDRESS_MASK	0x7FFFFF
2984 #define INIT_READ_OP_ADDRESS_SHIFT	9
2985 	u32 expected_val;
2986 };
2987 
2988 /* Init operations union */
2989 union init_op {
2990 	struct init_raw_op raw;
2991 	struct init_write_op write;
2992 	struct init_read_op read;
2993 	struct init_if_mode_op if_mode;
2994 	struct init_if_phase_op if_phase;
2995 	struct init_callback_op callback;
2996 	struct init_delay_op delay;
2997 };
2998 
2999 /* Init command operation types */
3000 enum init_op_types {
3001 	INIT_OP_READ,
3002 	INIT_OP_WRITE,
3003 	INIT_OP_IF_MODE,
3004 	INIT_OP_IF_PHASE,
3005 	INIT_OP_DELAY,
3006 	INIT_OP_CALLBACK,
3007 	MAX_INIT_OP_TYPES
3008 };
3009 
3010 /* init polling types */
3011 enum init_poll_types {
3012 	INIT_POLL_NONE,
3013 	INIT_POLL_EQ,
3014 	INIT_POLL_OR,
3015 	INIT_POLL_AND,
3016 	MAX_INIT_POLL_TYPES
3017 };
3018 
3019 /* init source types */
3020 enum init_source_types {
3021 	INIT_SRC_INLINE,
3022 	INIT_SRC_ZEROS,
3023 	INIT_SRC_ARRAY,
3024 	INIT_SRC_RUNTIME,
3025 	MAX_INIT_SOURCE_TYPES
3026 };
3027 
3028 /* Internal RAM Offsets macro data */
3029 struct iro {
3030 	u32 base;
3031 	u16 m1;
3032 	u16 m2;
3033 	u16 m3;
3034 	u16 size;
3035 };
3036 
3037 /***************************** Public Functions *******************************/
3038 
3039 /**
3040  * @brief qed_dbg_set_bin_ptr - Sets a pointer to the binary data with debug
3041  *	arrays.
3042  *
3043  * @param p_hwfn -	    HW device data
3044  * @param bin_ptr - a pointer to the binary data with debug arrays.
3045  */
3046 enum dbg_status qed_dbg_set_bin_ptr(struct qed_hwfn *p_hwfn,
3047 				    const u8 * const bin_ptr);
3048 
3049 /**
3050  * @brief qed_read_regs - Reads registers into a buffer (using GRC).
3051  *
3052  * @param p_hwfn - HW device data
3053  * @param p_ptt - Ptt window used for writing the registers.
3054  * @param buf - Destination buffer.
3055  * @param addr - Source GRC address in dwords.
3056  * @param len - Number of registers to read.
3057  */
3058 void qed_read_regs(struct qed_hwfn *p_hwfn,
3059 		   struct qed_ptt *p_ptt, u32 *buf, u32 addr, u32 len);
3060 
3061 /**
3062  * @brief qed_read_fw_info - Reads FW info from the chip.
3063  *
3064  * The FW info contains FW-related information, such as the FW version,
3065  * FW image (main/L2B/kuku), FW timestamp, etc.
3066  * The FW info is read from the internal RAM of the first Storm that is not in
3067  * reset.
3068  *
3069  * @param p_hwfn -	    HW device data
3070  * @param p_ptt -	    Ptt window used for writing the registers.
3071  * @param fw_info -	Out: a pointer to write the FW info into.
3072  *
3073  * @return true if the FW info was read successfully from one of the Storms,
3074  * or false if all Storms are in reset.
3075  */
3076 bool qed_read_fw_info(struct qed_hwfn *p_hwfn,
3077 		      struct qed_ptt *p_ptt, struct fw_info *fw_info);
3078 /**
3079  * @brief qed_dbg_grc_config - Sets the value of a GRC parameter.
3080  *
3081  * @param p_hwfn -	HW device data
3082  * @param grc_param -	GRC parameter
3083  * @param val -		Value to set.
3084  *
3085  * @return error if one of the following holds:
3086  *	- the version wasn't set
3087  *	- grc_param is invalid
3088  *	- val is outside the allowed boundaries
3089  */
3090 enum dbg_status qed_dbg_grc_config(struct qed_hwfn *p_hwfn,
3091 				   enum dbg_grc_params grc_param, u32 val);
3092 
3093 /**
3094  * @brief qed_dbg_grc_set_params_default - Reverts all GRC parameters to their
3095  *	default value.
3096  *
3097  * @param p_hwfn		- HW device data
3098  */
3099 void qed_dbg_grc_set_params_default(struct qed_hwfn *p_hwfn);
3100 /**
3101  * @brief qed_dbg_grc_get_dump_buf_size - Returns the required buffer size for
3102  *	GRC Dump.
3103  *
3104  * @param p_hwfn - HW device data
3105  * @param p_ptt - Ptt window used for writing the registers.
3106  * @param buf_size - OUT: required buffer size (in dwords) for the GRC Dump
3107  *	data.
3108  *
3109  * @return error if one of the following holds:
3110  *	- the version wasn't set
3111  * Otherwise, returns ok.
3112  */
3113 enum dbg_status qed_dbg_grc_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3114 					      struct qed_ptt *p_ptt,
3115 					      u32 *buf_size);
3116 
3117 /**
3118  * @brief qed_dbg_grc_dump - Dumps GRC data into the specified buffer.
3119  *
3120  * @param p_hwfn - HW device data
3121  * @param p_ptt - Ptt window used for writing the registers.
3122  * @param dump_buf - Pointer to write the collected GRC data into.
3123  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3124  * @param num_dumped_dwords - OUT: number of dumped dwords.
3125  *
3126  * @return error if one of the following holds:
3127  *	- the version wasn't set
3128  *	- the specified dump buffer is too small
3129  * Otherwise, returns ok.
3130  */
3131 enum dbg_status qed_dbg_grc_dump(struct qed_hwfn *p_hwfn,
3132 				 struct qed_ptt *p_ptt,
3133 				 u32 *dump_buf,
3134 				 u32 buf_size_in_dwords,
3135 				 u32 *num_dumped_dwords);
3136 
3137 /**
3138  * @brief qed_dbg_idle_chk_get_dump_buf_size - Returns the required buffer size
3139  *	for idle check results.
3140  *
3141  * @param p_hwfn - HW device data
3142  * @param p_ptt - Ptt window used for writing the registers.
3143  * @param buf_size - OUT: required buffer size (in dwords) for the idle check
3144  *	data.
3145  *
3146  * @return error if one of the following holds:
3147  *	- the version wasn't set
3148  * Otherwise, returns ok.
3149  */
3150 enum dbg_status qed_dbg_idle_chk_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3151 						   struct qed_ptt *p_ptt,
3152 						   u32 *buf_size);
3153 
3154 /**
3155  * @brief qed_dbg_idle_chk_dump - Performs idle check and writes the results
3156  *	into the specified buffer.
3157  *
3158  * @param p_hwfn - HW device data
3159  * @param p_ptt - Ptt window used for writing the registers.
3160  * @param dump_buf - Pointer to write the idle check data into.
3161  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3162  * @param num_dumped_dwords - OUT: number of dumped dwords.
3163  *
3164  * @return error if one of the following holds:
3165  *	- the version wasn't set
3166  *	- the specified buffer is too small
3167  * Otherwise, returns ok.
3168  */
3169 enum dbg_status qed_dbg_idle_chk_dump(struct qed_hwfn *p_hwfn,
3170 				      struct qed_ptt *p_ptt,
3171 				      u32 *dump_buf,
3172 				      u32 buf_size_in_dwords,
3173 				      u32 *num_dumped_dwords);
3174 
3175 /**
3176  * @brief qed_dbg_mcp_trace_get_dump_buf_size - Returns the required buffer size
3177  *	for mcp trace results.
3178  *
3179  * @param p_hwfn - HW device data
3180  * @param p_ptt - Ptt window used for writing the registers.
3181  * @param buf_size - OUT: required buffer size (in dwords) for mcp trace data.
3182  *
3183  * @return error if one of the following holds:
3184  *	- the version wasn't set
3185  *	- the trace data in MCP scratchpad contain an invalid signature
3186  *	- the bundle ID in NVRAM is invalid
3187  *	- the trace meta data cannot be found (in NVRAM or image file)
3188  * Otherwise, returns ok.
3189  */
3190 enum dbg_status qed_dbg_mcp_trace_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3191 						    struct qed_ptt *p_ptt,
3192 						    u32 *buf_size);
3193 
3194 /**
3195  * @brief qed_dbg_mcp_trace_dump - Performs mcp trace and writes the results
3196  *	into the specified buffer.
3197  *
3198  * @param p_hwfn - HW device data
3199  * @param p_ptt - Ptt window used for writing the registers.
3200  * @param dump_buf - Pointer to write the mcp trace data into.
3201  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3202  * @param num_dumped_dwords - OUT: number of dumped dwords.
3203  *
3204  * @return error if one of the following holds:
3205  *	- the version wasn't set
3206  *	- the specified buffer is too small
3207  *	- the trace data in MCP scratchpad contain an invalid signature
3208  *	- the bundle ID in NVRAM is invalid
3209  *	- the trace meta data cannot be found (in NVRAM or image file)
3210  *	- the trace meta data cannot be read (from NVRAM or image file)
3211  * Otherwise, returns ok.
3212  */
3213 enum dbg_status qed_dbg_mcp_trace_dump(struct qed_hwfn *p_hwfn,
3214 				       struct qed_ptt *p_ptt,
3215 				       u32 *dump_buf,
3216 				       u32 buf_size_in_dwords,
3217 				       u32 *num_dumped_dwords);
3218 
3219 /**
3220  * @brief qed_dbg_reg_fifo_get_dump_buf_size - Returns the required buffer size
3221  *	for grc trace fifo results.
3222  *
3223  * @param p_hwfn - HW device data
3224  * @param p_ptt - Ptt window used for writing the registers.
3225  * @param buf_size - OUT: required buffer size (in dwords) for reg fifo data.
3226  *
3227  * @return error if one of the following holds:
3228  *	- the version wasn't set
3229  * Otherwise, returns ok.
3230  */
3231 enum dbg_status qed_dbg_reg_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3232 						   struct qed_ptt *p_ptt,
3233 						   u32 *buf_size);
3234 
3235 /**
3236  * @brief qed_dbg_reg_fifo_dump - Reads the reg fifo and writes the results into
3237  *	the specified buffer.
3238  *
3239  * @param p_hwfn - HW device data
3240  * @param p_ptt - Ptt window used for writing the registers.
3241  * @param dump_buf - Pointer to write the reg fifo data into.
3242  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3243  * @param num_dumped_dwords - OUT: number of dumped dwords.
3244  *
3245  * @return error if one of the following holds:
3246  *	- the version wasn't set
3247  *	- the specified buffer is too small
3248  *	- DMAE transaction failed
3249  * Otherwise, returns ok.
3250  */
3251 enum dbg_status qed_dbg_reg_fifo_dump(struct qed_hwfn *p_hwfn,
3252 				      struct qed_ptt *p_ptt,
3253 				      u32 *dump_buf,
3254 				      u32 buf_size_in_dwords,
3255 				      u32 *num_dumped_dwords);
3256 
3257 /**
3258  * @brief qed_dbg_igu_fifo_get_dump_buf_size - Returns the required buffer size
3259  *	for the IGU fifo results.
3260  *
3261  * @param p_hwfn - HW device data
3262  * @param p_ptt - Ptt window used for writing the registers.
3263  * @param buf_size - OUT: required buffer size (in dwords) for the IGU fifo
3264  *	data.
3265  *
3266  * @return error if one of the following holds:
3267  *	- the version wasn't set
3268  * Otherwise, returns ok.
3269  */
3270 enum dbg_status qed_dbg_igu_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3271 						   struct qed_ptt *p_ptt,
3272 						   u32 *buf_size);
3273 
3274 /**
3275  * @brief qed_dbg_igu_fifo_dump - Reads the IGU fifo and writes the results into
3276  *	the specified buffer.
3277  *
3278  * @param p_hwfn - HW device data
3279  * @param p_ptt - Ptt window used for writing the registers.
3280  * @param dump_buf - Pointer to write the IGU fifo data into.
3281  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3282  * @param num_dumped_dwords - OUT: number of dumped dwords.
3283  *
3284  * @return error if one of the following holds:
3285  *	- the version wasn't set
3286  *	- the specified buffer is too small
3287  *	- DMAE transaction failed
3288  * Otherwise, returns ok.
3289  */
3290 enum dbg_status qed_dbg_igu_fifo_dump(struct qed_hwfn *p_hwfn,
3291 				      struct qed_ptt *p_ptt,
3292 				      u32 *dump_buf,
3293 				      u32 buf_size_in_dwords,
3294 				      u32 *num_dumped_dwords);
3295 
3296 /**
3297  * @brief qed_dbg_protection_override_get_dump_buf_size - Returns the required
3298  *	buffer size for protection override window results.
3299  *
3300  * @param p_hwfn - HW device data
3301  * @param p_ptt - Ptt window used for writing the registers.
3302  * @param buf_size - OUT: required buffer size (in dwords) for protection
3303  *	override data.
3304  *
3305  * @return error if one of the following holds:
3306  *	- the version wasn't set
3307  * Otherwise, returns ok.
3308  */
3309 enum dbg_status
3310 qed_dbg_protection_override_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3311 					      struct qed_ptt *p_ptt,
3312 					      u32 *buf_size);
3313 /**
3314  * @brief qed_dbg_protection_override_dump - Reads protection override window
3315  *	entries and writes the results into the specified buffer.
3316  *
3317  * @param p_hwfn - HW device data
3318  * @param p_ptt - Ptt window used for writing the registers.
3319  * @param dump_buf - Pointer to write the protection override data into.
3320  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3321  * @param num_dumped_dwords - OUT: number of dumped dwords.
3322  *
3323  * @return error if one of the following holds:
3324  *	- the version wasn't set
3325  *	- the specified buffer is too small
3326  *	- DMAE transaction failed
3327  * Otherwise, returns ok.
3328  */
3329 enum dbg_status qed_dbg_protection_override_dump(struct qed_hwfn *p_hwfn,
3330 						 struct qed_ptt *p_ptt,
3331 						 u32 *dump_buf,
3332 						 u32 buf_size_in_dwords,
3333 						 u32 *num_dumped_dwords);
3334 /**
3335  * @brief qed_dbg_fw_asserts_get_dump_buf_size - Returns the required buffer
3336  *	size for FW Asserts results.
3337  *
3338  * @param p_hwfn - HW device data
3339  * @param p_ptt - Ptt window used for writing the registers.
3340  * @param buf_size - OUT: required buffer size (in dwords) for FW Asserts data.
3341  *
3342  * @return error if one of the following holds:
3343  *	- the version wasn't set
3344  * Otherwise, returns ok.
3345  */
3346 enum dbg_status qed_dbg_fw_asserts_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3347 						     struct qed_ptt *p_ptt,
3348 						     u32 *buf_size);
3349 /**
3350  * @brief qed_dbg_fw_asserts_dump - Reads the FW Asserts and writes the results
3351  *	into the specified buffer.
3352  *
3353  * @param p_hwfn - HW device data
3354  * @param p_ptt - Ptt window used for writing the registers.
3355  * @param dump_buf - Pointer to write the FW Asserts data into.
3356  * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3357  * @param num_dumped_dwords - OUT: number of dumped dwords.
3358  *
3359  * @return error if one of the following holds:
3360  *	- the version wasn't set
3361  *	- the specified buffer is too small
3362  * Otherwise, returns ok.
3363  */
3364 enum dbg_status qed_dbg_fw_asserts_dump(struct qed_hwfn *p_hwfn,
3365 					struct qed_ptt *p_ptt,
3366 					u32 *dump_buf,
3367 					u32 buf_size_in_dwords,
3368 					u32 *num_dumped_dwords);
3369 
3370 /**
3371  * @brief qed_dbg_read_attn - Reads the attention registers of the specified
3372  * block and type, and writes the results into the specified buffer.
3373  *
3374  * @param p_hwfn -	 HW device data
3375  * @param p_ptt -	 Ptt window used for writing the registers.
3376  * @param block -	 Block ID.
3377  * @param attn_type -	 Attention type.
3378  * @param clear_status - Indicates if the attention status should be cleared.
3379  * @param results -	 OUT: Pointer to write the read results into
3380  *
3381  * @return error if one of the following holds:
3382  *	- the version wasn't set
3383  * Otherwise, returns ok.
3384  */
3385 enum dbg_status qed_dbg_read_attn(struct qed_hwfn *p_hwfn,
3386 				  struct qed_ptt *p_ptt,
3387 				  enum block_id block,
3388 				  enum dbg_attn_type attn_type,
3389 				  bool clear_status,
3390 				  struct dbg_attn_block_result *results);
3391 
3392 /**
3393  * @brief qed_dbg_print_attn - Prints attention registers values in the
3394  *	specified results struct.
3395  *
3396  * @param p_hwfn
3397  * @param results - Pointer to the attention read results
3398  *
3399  * @return error if one of the following holds:
3400  *	- the version wasn't set
3401  * Otherwise, returns ok.
3402  */
3403 enum dbg_status qed_dbg_print_attn(struct qed_hwfn *p_hwfn,
3404 				   struct dbg_attn_block_result *results);
3405 
3406 /******************************* Data Types **********************************/
3407 
3408 struct mcp_trace_format {
3409 	u32 data;
3410 #define MCP_TRACE_FORMAT_MODULE_MASK	0x0000ffff
3411 #define MCP_TRACE_FORMAT_MODULE_OFFSET	0
3412 #define MCP_TRACE_FORMAT_LEVEL_MASK	0x00030000
3413 #define MCP_TRACE_FORMAT_LEVEL_OFFSET	16
3414 #define MCP_TRACE_FORMAT_P1_SIZE_MASK	0x000c0000
3415 #define MCP_TRACE_FORMAT_P1_SIZE_OFFSET 18
3416 #define MCP_TRACE_FORMAT_P2_SIZE_MASK	0x00300000
3417 #define MCP_TRACE_FORMAT_P2_SIZE_OFFSET 20
3418 #define MCP_TRACE_FORMAT_P3_SIZE_MASK	0x00c00000
3419 #define MCP_TRACE_FORMAT_P3_SIZE_OFFSET 22
3420 #define MCP_TRACE_FORMAT_LEN_MASK	0xff000000
3421 #define MCP_TRACE_FORMAT_LEN_OFFSET	24
3422 
3423 	char *format_str;
3424 };
3425 
3426 /* MCP Trace Meta data structure */
3427 struct mcp_trace_meta {
3428 	u32 modules_num;
3429 	char **modules;
3430 	u32 formats_num;
3431 	struct mcp_trace_format *formats;
3432 	bool is_allocated;
3433 };
3434 
3435 /* Debug Tools user data */
3436 struct dbg_tools_user_data {
3437 	struct mcp_trace_meta mcp_trace_meta;
3438 	const u32 *mcp_trace_user_meta_buf;
3439 };
3440 
3441 /******************************** Constants **********************************/
3442 
3443 #define MAX_NAME_LEN	16
3444 
3445 /***************************** Public Functions *******************************/
3446 
3447 /**
3448  * @brief qed_dbg_user_set_bin_ptr - Sets a pointer to the binary data with
3449  *	debug arrays.
3450  *
3451  * @param p_hwfn - HW device data
3452  * @param bin_ptr - a pointer to the binary data with debug arrays.
3453  */
3454 enum dbg_status qed_dbg_user_set_bin_ptr(struct qed_hwfn *p_hwfn,
3455 					 const u8 * const bin_ptr);
3456 
3457 /**
3458  * @brief qed_dbg_alloc_user_data - Allocates user debug data.
3459  *
3460  * @param p_hwfn -		 HW device data
3461  * @param user_data_ptr - OUT: a pointer to the allocated memory.
3462  */
3463 enum dbg_status qed_dbg_alloc_user_data(struct qed_hwfn *p_hwfn,
3464 					void **user_data_ptr);
3465 
3466 /**
3467  * @brief qed_dbg_get_status_str - Returns a string for the specified status.
3468  *
3469  * @param status - a debug status code.
3470  *
3471  * @return a string for the specified status
3472  */
3473 const char *qed_dbg_get_status_str(enum dbg_status status);
3474 
3475 /**
3476  * @brief qed_get_idle_chk_results_buf_size - Returns the required buffer size
3477  *	for idle check results (in bytes).
3478  *
3479  * @param p_hwfn - HW device data
3480  * @param dump_buf - idle check dump buffer.
3481  * @param num_dumped_dwords - number of dwords that were dumped.
3482  * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3483  *	results.
3484  *
3485  * @return error if the parsing fails, ok otherwise.
3486  */
3487 enum dbg_status qed_get_idle_chk_results_buf_size(struct qed_hwfn *p_hwfn,
3488 						  u32 *dump_buf,
3489 						  u32  num_dumped_dwords,
3490 						  u32 *results_buf_size);
3491 /**
3492  * @brief qed_print_idle_chk_results - Prints idle check results
3493  *
3494  * @param p_hwfn - HW device data
3495  * @param dump_buf - idle check dump buffer.
3496  * @param num_dumped_dwords - number of dwords that were dumped.
3497  * @param results_buf - buffer for printing the idle check results.
3498  * @param num_errors - OUT: number of errors found in idle check.
3499  * @param num_warnings - OUT: number of warnings found in idle check.
3500  *
3501  * @return error if the parsing fails, ok otherwise.
3502  */
3503 enum dbg_status qed_print_idle_chk_results(struct qed_hwfn *p_hwfn,
3504 					   u32 *dump_buf,
3505 					   u32 num_dumped_dwords,
3506 					   char *results_buf,
3507 					   u32 *num_errors,
3508 					   u32 *num_warnings);
3509 
3510 /**
3511  * @brief qed_dbg_mcp_trace_set_meta_data - Sets the MCP Trace meta data.
3512  *
3513  * Needed in case the MCP Trace dump doesn't contain the meta data (e.g. due to
3514  * no NVRAM access).
3515  *
3516  * @param data - pointer to MCP Trace meta data
3517  * @param size - size of MCP Trace meta data in dwords
3518  */
3519 void qed_dbg_mcp_trace_set_meta_data(struct qed_hwfn *p_hwfn,
3520 				     const u32 *meta_buf);
3521 
3522 /**
3523  * @brief qed_get_mcp_trace_results_buf_size - Returns the required buffer size
3524  *	for MCP Trace results (in bytes).
3525  *
3526  * @param p_hwfn - HW device data
3527  * @param dump_buf - MCP Trace dump buffer.
3528  * @param num_dumped_dwords - number of dwords that were dumped.
3529  * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3530  *	results.
3531  *
3532  * @return error if the parsing fails, ok otherwise.
3533  */
3534 enum dbg_status qed_get_mcp_trace_results_buf_size(struct qed_hwfn *p_hwfn,
3535 						   u32 *dump_buf,
3536 						   u32 num_dumped_dwords,
3537 						   u32 *results_buf_size);
3538 
3539 /**
3540  * @brief qed_print_mcp_trace_results - Prints MCP Trace results
3541  *
3542  * @param p_hwfn - HW device data
3543  * @param dump_buf - mcp trace dump buffer, starting from the header.
3544  * @param num_dumped_dwords - number of dwords that were dumped.
3545  * @param results_buf - buffer for printing the mcp trace results.
3546  *
3547  * @return error if the parsing fails, ok otherwise.
3548  */
3549 enum dbg_status qed_print_mcp_trace_results(struct qed_hwfn *p_hwfn,
3550 					    u32 *dump_buf,
3551 					    u32 num_dumped_dwords,
3552 					    char *results_buf);
3553 
3554 /**
3555  * @brief qed_print_mcp_trace_results_cont - Prints MCP Trace results, and
3556  * keeps the MCP trace meta data allocated, to support continuous MCP Trace
3557  * parsing. After the continuous parsing ends, mcp_trace_free_meta_data should
3558  * be called to free the meta data.
3559  *
3560  * @param p_hwfn -	      HW device data
3561  * @param dump_buf -	      mcp trace dump buffer, starting from the header.
3562  * @param results_buf -	      buffer for printing the mcp trace results.
3563  *
3564  * @return error if the parsing fails, ok otherwise.
3565  */
3566 enum dbg_status qed_print_mcp_trace_results_cont(struct qed_hwfn *p_hwfn,
3567 						 u32 *dump_buf,
3568 						 char *results_buf);
3569 
3570 /**
3571  * @brief print_mcp_trace_line - Prints MCP Trace results for a single line
3572  *
3573  * @param p_hwfn -	      HW device data
3574  * @param dump_buf -	      mcp trace dump buffer, starting from the header.
3575  * @param num_dumped_bytes -  number of bytes that were dumped.
3576  * @param results_buf -	      buffer for printing the mcp trace results.
3577  *
3578  * @return error if the parsing fails, ok otherwise.
3579  */
3580 enum dbg_status qed_print_mcp_trace_line(struct qed_hwfn *p_hwfn,
3581 					 u8 *dump_buf,
3582 					 u32 num_dumped_bytes,
3583 					 char *results_buf);
3584 
3585 /**
3586  * @brief mcp_trace_free_meta_data - Frees the MCP Trace meta data.
3587  * Should be called after continuous MCP Trace parsing.
3588  *
3589  * @param p_hwfn - HW device data
3590  */
3591 void qed_mcp_trace_free_meta_data(struct qed_hwfn *p_hwfn);
3592 
3593 /**
3594  * @brief qed_get_reg_fifo_results_buf_size - Returns the required buffer size
3595  *	for reg_fifo results (in bytes).
3596  *
3597  * @param p_hwfn - HW device data
3598  * @param dump_buf - reg fifo dump buffer.
3599  * @param num_dumped_dwords - number of dwords that were dumped.
3600  * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3601  *	results.
3602  *
3603  * @return error if the parsing fails, ok otherwise.
3604  */
3605 enum dbg_status qed_get_reg_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
3606 						  u32 *dump_buf,
3607 						  u32 num_dumped_dwords,
3608 						  u32 *results_buf_size);
3609 
3610 /**
3611  * @brief qed_print_reg_fifo_results - Prints reg fifo results
3612  *
3613  * @param p_hwfn - HW device data
3614  * @param dump_buf - reg fifo dump buffer, starting from the header.
3615  * @param num_dumped_dwords - number of dwords that were dumped.
3616  * @param results_buf - buffer for printing the reg fifo results.
3617  *
3618  * @return error if the parsing fails, ok otherwise.
3619  */
3620 enum dbg_status qed_print_reg_fifo_results(struct qed_hwfn *p_hwfn,
3621 					   u32 *dump_buf,
3622 					   u32 num_dumped_dwords,
3623 					   char *results_buf);
3624 
3625 /**
3626  * @brief qed_get_igu_fifo_results_buf_size - Returns the required buffer size
3627  *	for igu_fifo results (in bytes).
3628  *
3629  * @param p_hwfn - HW device data
3630  * @param dump_buf - IGU fifo dump buffer.
3631  * @param num_dumped_dwords - number of dwords that were dumped.
3632  * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3633  *	results.
3634  *
3635  * @return error if the parsing fails, ok otherwise.
3636  */
3637 enum dbg_status qed_get_igu_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
3638 						  u32 *dump_buf,
3639 						  u32 num_dumped_dwords,
3640 						  u32 *results_buf_size);
3641 
3642 /**
3643  * @brief qed_print_igu_fifo_results - Prints IGU fifo results
3644  *
3645  * @param p_hwfn - HW device data
3646  * @param dump_buf - IGU fifo dump buffer, starting from the header.
3647  * @param num_dumped_dwords - number of dwords that were dumped.
3648  * @param results_buf - buffer for printing the IGU fifo results.
3649  *
3650  * @return error if the parsing fails, ok otherwise.
3651  */
3652 enum dbg_status qed_print_igu_fifo_results(struct qed_hwfn *p_hwfn,
3653 					   u32 *dump_buf,
3654 					   u32 num_dumped_dwords,
3655 					   char *results_buf);
3656 
3657 /**
3658  * @brief qed_get_protection_override_results_buf_size - Returns the required
3659  *	buffer size for protection override results (in bytes).
3660  *
3661  * @param p_hwfn - HW device data
3662  * @param dump_buf - protection override dump buffer.
3663  * @param num_dumped_dwords - number of dwords that were dumped.
3664  * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3665  *	results.
3666  *
3667  * @return error if the parsing fails, ok otherwise.
3668  */
3669 enum dbg_status
3670 qed_get_protection_override_results_buf_size(struct qed_hwfn *p_hwfn,
3671 					     u32 *dump_buf,
3672 					     u32 num_dumped_dwords,
3673 					     u32 *results_buf_size);
3674 
3675 /**
3676  * @brief qed_print_protection_override_results - Prints protection override
3677  *	results.
3678  *
3679  * @param p_hwfn - HW device data
3680  * @param dump_buf - protection override dump buffer, starting from the header.
3681  * @param num_dumped_dwords - number of dwords that were dumped.
3682  * @param results_buf - buffer for printing the reg fifo results.
3683  *
3684  * @return error if the parsing fails, ok otherwise.
3685  */
3686 enum dbg_status qed_print_protection_override_results(struct qed_hwfn *p_hwfn,
3687 						      u32 *dump_buf,
3688 						      u32 num_dumped_dwords,
3689 						      char *results_buf);
3690 
3691 /**
3692  * @brief qed_get_fw_asserts_results_buf_size - Returns the required buffer size
3693  *	for FW Asserts results (in bytes).
3694  *
3695  * @param p_hwfn - HW device data
3696  * @param dump_buf - FW Asserts dump buffer.
3697  * @param num_dumped_dwords - number of dwords that were dumped.
3698  * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3699  *	results.
3700  *
3701  * @return error if the parsing fails, ok otherwise.
3702  */
3703 enum dbg_status qed_get_fw_asserts_results_buf_size(struct qed_hwfn *p_hwfn,
3704 						    u32 *dump_buf,
3705 						    u32 num_dumped_dwords,
3706 						    u32 *results_buf_size);
3707 
3708 /**
3709  * @brief qed_print_fw_asserts_results - Prints FW Asserts results
3710  *
3711  * @param p_hwfn - HW device data
3712  * @param dump_buf - FW Asserts dump buffer, starting from the header.
3713  * @param num_dumped_dwords - number of dwords that were dumped.
3714  * @param results_buf - buffer for printing the FW Asserts results.
3715  *
3716  * @return error if the parsing fails, ok otherwise.
3717  */
3718 enum dbg_status qed_print_fw_asserts_results(struct qed_hwfn *p_hwfn,
3719 					     u32 *dump_buf,
3720 					     u32 num_dumped_dwords,
3721 					     char *results_buf);
3722 
3723 /**
3724  * @brief qed_dbg_parse_attn - Parses and prints attention registers values in
3725  * the specified results struct.
3726  *
3727  * @param p_hwfn -  HW device data
3728  * @param results - Pointer to the attention read results
3729  *
3730  * @return error if one of the following holds:
3731  *	- the version wasn't set
3732  * Otherwise, returns ok.
3733  */
3734 enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn,
3735 				   struct dbg_attn_block_result *results);
3736 
3737 /* Win 2 */
3738 #define GTT_BAR0_MAP_REG_IGU_CMD	0x00f000UL
3739 
3740 /* Win 3 */
3741 #define GTT_BAR0_MAP_REG_TSDM_RAM	0x010000UL
3742 
3743 /* Win 4 */
3744 #define GTT_BAR0_MAP_REG_MSDM_RAM	0x011000UL
3745 
3746 /* Win 5 */
3747 #define GTT_BAR0_MAP_REG_MSDM_RAM_1024	0x012000UL
3748 
3749 /* Win 6 */
3750 #define GTT_BAR0_MAP_REG_MSDM_RAM_2048	0x013000UL
3751 
3752 /* Win 7 */
3753 #define GTT_BAR0_MAP_REG_USDM_RAM	0x014000UL
3754 
3755 /* Win 8 */
3756 #define GTT_BAR0_MAP_REG_USDM_RAM_1024	0x015000UL
3757 
3758 /* Win 9 */
3759 #define GTT_BAR0_MAP_REG_USDM_RAM_2048	0x016000UL
3760 
3761 /* Win 10 */
3762 #define GTT_BAR0_MAP_REG_XSDM_RAM	0x017000UL
3763 
3764 /* Win 11 */
3765 #define GTT_BAR0_MAP_REG_XSDM_RAM_1024	0x018000UL
3766 
3767 /* Win 12 */
3768 #define GTT_BAR0_MAP_REG_YSDM_RAM	0x019000UL
3769 
3770 /* Win 13 */
3771 #define GTT_BAR0_MAP_REG_PSDM_RAM	0x01a000UL
3772 
3773 /**
3774  * @brief qed_qm_pf_mem_size - prepare QM ILT sizes
3775  *
3776  * Returns the required host memory size in 4KB units.
3777  * Must be called before all QM init HSI functions.
3778  *
3779  * @param num_pf_cids - number of connections used by this PF
3780  * @param num_vf_cids - number of connections used by VFs of this PF
3781  * @param num_tids - number of tasks used by this PF
3782  * @param num_pf_pqs - number of PQs used by this PF
3783  * @param num_vf_pqs - number of PQs used by VFs of this PF
3784  *
3785  * @return The required host memory size in 4KB units.
3786  */
3787 u32 qed_qm_pf_mem_size(u32 num_pf_cids,
3788 		       u32 num_vf_cids,
3789 		       u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs);
3790 
3791 struct qed_qm_common_rt_init_params {
3792 	u8 max_ports_per_engine;
3793 	u8 max_phys_tcs_per_port;
3794 	bool pf_rl_en;
3795 	bool pf_wfq_en;
3796 	bool global_rl_en;
3797 	bool vport_wfq_en;
3798 	struct init_qm_port_params *port_params;
3799 };
3800 
3801 int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn,
3802 			  struct qed_qm_common_rt_init_params *p_params);
3803 
3804 struct qed_qm_pf_rt_init_params {
3805 	u8 port_id;
3806 	u8 pf_id;
3807 	u8 max_phys_tcs_per_port;
3808 	bool is_pf_loading;
3809 	u32 num_pf_cids;
3810 	u32 num_vf_cids;
3811 	u32 num_tids;
3812 	u16 start_pq;
3813 	u16 num_pf_pqs;
3814 	u16 num_vf_pqs;
3815 	u16 start_vport;
3816 	u16 num_vports;
3817 	u16 pf_wfq;
3818 	u32 pf_rl;
3819 	struct init_qm_pq_params *pq_params;
3820 	struct init_qm_vport_params *vport_params;
3821 };
3822 
3823 int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
3824 	struct qed_ptt *p_ptt,
3825 	struct qed_qm_pf_rt_init_params *p_params);
3826 
3827 /**
3828  * @brief qed_init_pf_wfq - Initializes the WFQ weight of the specified PF
3829  *
3830  * @param p_hwfn
3831  * @param p_ptt - ptt window used for writing the registers
3832  * @param pf_id - PF ID
3833  * @param pf_wfq - WFQ weight. Must be non-zero.
3834  *
3835  * @return 0 on success, -1 on error.
3836  */
3837 int qed_init_pf_wfq(struct qed_hwfn *p_hwfn,
3838 		    struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq);
3839 
3840 /**
3841  * @brief qed_init_pf_rl - Initializes the rate limit of the specified PF
3842  *
3843  * @param p_hwfn
3844  * @param p_ptt - ptt window used for writing the registers
3845  * @param pf_id - PF ID
3846  * @param pf_rl - rate limit in Mb/sec units
3847  *
3848  * @return 0 on success, -1 on error.
3849  */
3850 int qed_init_pf_rl(struct qed_hwfn *p_hwfn,
3851 		   struct qed_ptt *p_ptt, u8 pf_id, u32 pf_rl);
3852 
3853 /**
3854  * @brief qed_init_vport_wfq Initializes the WFQ weight of the specified VPORT
3855  *
3856  * @param p_hwfn
3857  * @param p_ptt - ptt window used for writing the registers
3858  * @param first_tx_pq_id- An array containing the first Tx PQ ID associated
3859  *	  with the VPORT for each TC. This array is filled by
3860  *	  qed_qm_pf_rt_init
3861  * @param vport_wfq - WFQ weight. Must be non-zero.
3862  *
3863  * @return 0 on success, -1 on error.
3864  */
3865 int qed_init_vport_wfq(struct qed_hwfn *p_hwfn,
3866 		       struct qed_ptt *p_ptt,
3867 		       u16 first_tx_pq_id[NUM_OF_TCS], u16 wfq);
3868 
3869 /**
3870  * @brief qed_init_global_rl - Initializes the rate limit of the specified
3871  * rate limiter
3872  *
3873  * @param p_hwfn
3874  * @param p_ptt - ptt window used for writing the registers
3875  * @param rl_id - RL ID
3876  * @param rate_limit - rate limit in Mb/sec units
3877  *
3878  * @return 0 on success, -1 on error.
3879  */
3880 int qed_init_global_rl(struct qed_hwfn *p_hwfn,
3881 		       struct qed_ptt *p_ptt,
3882 		       u16 rl_id, u32 rate_limit);
3883 
3884 /**
3885  * @brief qed_send_qm_stop_cmd  Sends a stop command to the QM
3886  *
3887  * @param p_hwfn
3888  * @param p_ptt
3889  * @param is_release_cmd - true for release, false for stop.
3890  * @param is_tx_pq - true for Tx PQs, false for Other PQs.
3891  * @param start_pq - first PQ ID to stop
3892  * @param num_pqs - Number of PQs to stop, starting from start_pq.
3893  *
3894  * @return bool, true if successful, false if timeout occurred while waiting for
3895  *	QM command done.
3896  */
3897 bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
3898 			  struct qed_ptt *p_ptt,
3899 			  bool is_release_cmd,
3900 			  bool is_tx_pq, u16 start_pq, u16 num_pqs);
3901 
3902 /**
3903  * @brief qed_set_vxlan_dest_port - initializes vxlan tunnel destination udp port
3904  *
3905  * @param p_hwfn
3906  * @param p_ptt - ptt window used for writing the registers.
3907  * @param dest_port - vxlan destination udp port.
3908  */
3909 void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn,
3910 			     struct qed_ptt *p_ptt, u16 dest_port);
3911 
3912 /**
3913  * @brief qed_set_vxlan_enable - enable or disable VXLAN tunnel in HW
3914  *
3915  * @param p_hwfn
3916  * @param p_ptt - ptt window used for writing the registers.
3917  * @param vxlan_enable - vxlan enable flag.
3918  */
3919 void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn,
3920 			  struct qed_ptt *p_ptt, bool vxlan_enable);
3921 
3922 /**
3923  * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
3924  *
3925  * @param p_hwfn
3926  * @param p_ptt - ptt window used for writing the registers.
3927  * @param eth_gre_enable - eth GRE enable enable flag.
3928  * @param ip_gre_enable - IP GRE enable enable flag.
3929  */
3930 void qed_set_gre_enable(struct qed_hwfn *p_hwfn,
3931 			struct qed_ptt *p_ptt,
3932 			bool eth_gre_enable, bool ip_gre_enable);
3933 
3934 /**
3935  * @brief qed_set_geneve_dest_port - initializes geneve tunnel destination udp port
3936  *
3937  * @param p_hwfn
3938  * @param p_ptt - ptt window used for writing the registers.
3939  * @param dest_port - geneve destination udp port.
3940  */
3941 void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn,
3942 			      struct qed_ptt *p_ptt, u16 dest_port);
3943 
3944 /**
3945  * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
3946  *
3947  * @param p_ptt - ptt window used for writing the registers.
3948  * @param eth_geneve_enable - eth GENEVE enable enable flag.
3949  * @param ip_geneve_enable - IP GENEVE enable enable flag.
3950  */
3951 void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
3952 			   struct qed_ptt *p_ptt,
3953 			   bool eth_geneve_enable, bool ip_geneve_enable);
3954 
3955 void qed_set_vxlan_no_l2_enable(struct qed_hwfn *p_hwfn,
3956 				struct qed_ptt *p_ptt, bool enable);
3957 
3958 /**
3959  * @brief qed_gft_disable - Disable GFT
3960  *
3961  * @param p_hwfn
3962  * @param p_ptt - ptt window used for writing the registers.
3963  * @param pf_id - pf on which to disable GFT.
3964  */
3965 void qed_gft_disable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 pf_id);
3966 
3967 /**
3968  * @brief qed_gft_config - Enable and configure HW for GFT
3969  *
3970  * @param p_hwfn - HW device data
3971  * @param p_ptt - ptt window used for writing the registers.
3972  * @param pf_id - pf on which to enable GFT.
3973  * @param tcp - set profile tcp packets.
3974  * @param udp - set profile udp  packet.
3975  * @param ipv4 - set profile ipv4 packet.
3976  * @param ipv6 - set profile ipv6 packet.
3977  * @param profile_type - define packet same fields. Use enum gft_profile_type.
3978  */
3979 void qed_gft_config(struct qed_hwfn *p_hwfn,
3980 		    struct qed_ptt *p_ptt,
3981 		    u16 pf_id,
3982 		    bool tcp,
3983 		    bool udp,
3984 		    bool ipv4, bool ipv6, enum gft_profile_type profile_type);
3985 
3986 /**
3987  * @brief qed_enable_context_validation - Enable and configure context
3988  *	validation.
3989  *
3990  * @param p_hwfn
3991  * @param p_ptt - ptt window used for writing the registers.
3992  */
3993 void qed_enable_context_validation(struct qed_hwfn *p_hwfn,
3994 				   struct qed_ptt *p_ptt);
3995 
3996 /**
3997  * @brief qed_calc_session_ctx_validation - Calcualte validation byte for
3998  *	session context.
3999  *
4000  * @param p_ctx_mem - pointer to context memory.
4001  * @param ctx_size - context size.
4002  * @param ctx_type - context type.
4003  * @param cid - context cid.
4004  */
4005 void qed_calc_session_ctx_validation(void *p_ctx_mem,
4006 				     u16 ctx_size, u8 ctx_type, u32 cid);
4007 
4008 /**
4009  * @brief qed_calc_task_ctx_validation - Calcualte validation byte for task
4010  *	context.
4011  *
4012  * @param p_ctx_mem - pointer to context memory.
4013  * @param ctx_size - context size.
4014  * @param ctx_type - context type.
4015  * @param tid - context tid.
4016  */
4017 void qed_calc_task_ctx_validation(void *p_ctx_mem,
4018 				  u16 ctx_size, u8 ctx_type, u32 tid);
4019 
4020 /**
4021  * @brief qed_memset_session_ctx - Memset session context to 0 while
4022  *	preserving validation bytes.
4023  *
4024  * @param p_hwfn -
4025  * @param p_ctx_mem - pointer to context memory.
4026  * @param ctx_size - size to initialzie.
4027  * @param ctx_type - context type.
4028  */
4029 void qed_memset_session_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type);
4030 
4031 /**
4032  * @brief qed_memset_task_ctx - Memset task context to 0 while preserving
4033  *	validation bytes.
4034  *
4035  * @param p_ctx_mem - pointer to context memory.
4036  * @param ctx_size - size to initialzie.
4037  * @param ctx_type - context type.
4038  */
4039 void qed_memset_task_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type);
4040 
4041 #define NUM_STORMS 6
4042 
4043 /**
4044  * @brief qed_set_rdma_error_level - Sets the RDMA assert level.
4045  *                                   If the severity of the error will be
4046  *                                   above the level, the FW will assert.
4047  * @param p_hwfn - HW device data
4048  * @param p_ptt - ptt window used for writing the registers
4049  * @param assert_level - An array of assert levels for each storm.
4050  *
4051  */
4052 void qed_set_rdma_error_level(struct qed_hwfn *p_hwfn,
4053 			      struct qed_ptt *p_ptt,
4054 			      u8 assert_level[NUM_STORMS]);
4055 /**
4056  * @brief qed_fw_overlay_mem_alloc - Allocates and fills the FW overlay memory.
4057  *
4058  * @param p_hwfn - HW device data
4059  * @param fw_overlay_in_buf - the input FW overlay buffer.
4060  * @param buf_size - the size of the input FW overlay buffer in bytes.
4061  *		     must be aligned to dwords.
4062  * @param fw_overlay_out_mem - OUT: a pointer to the allocated overlays memory.
4063  *
4064  * @return a pointer to the allocated overlays memory,
4065  * or NULL in case of failures.
4066  */
4067 struct phys_mem_desc *
4068 qed_fw_overlay_mem_alloc(struct qed_hwfn *p_hwfn,
4069 			 const u32 * const fw_overlay_in_buf,
4070 			 u32 buf_size_in_bytes);
4071 
4072 /**
4073  * @brief qed_fw_overlay_init_ram - Initializes the FW overlay RAM.
4074  *
4075  * @param p_hwfn - HW device data.
4076  * @param p_ptt - ptt window used for writing the registers.
4077  * @param fw_overlay_mem - the allocated FW overlay memory.
4078  */
4079 void qed_fw_overlay_init_ram(struct qed_hwfn *p_hwfn,
4080 			     struct qed_ptt *p_ptt,
4081 			     struct phys_mem_desc *fw_overlay_mem);
4082 
4083 /**
4084  * @brief qed_fw_overlay_mem_free - Frees the FW overlay memory.
4085  *
4086  * @param p_hwfn - HW device data.
4087  * @param fw_overlay_mem - the allocated FW overlay memory to free.
4088  */
4089 void qed_fw_overlay_mem_free(struct qed_hwfn *p_hwfn,
4090 			     struct phys_mem_desc *fw_overlay_mem);
4091 
4092 /* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */
4093 #define YSTORM_FLOW_CONTROL_MODE_OFFSET			(IRO[0].base)
4094 #define YSTORM_FLOW_CONTROL_MODE_SIZE			(IRO[0].size)
4095 
4096 /* Tstorm port statistics */
4097 #define TSTORM_PORT_STAT_OFFSET(port_id) \
4098 	(IRO[1].base + ((port_id) * IRO[1].m1))
4099 #define TSTORM_PORT_STAT_SIZE				(IRO[1].size)
4100 
4101 /* Tstorm ll2 port statistics */
4102 #define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \
4103 	(IRO[2].base + ((port_id) * IRO[2].m1))
4104 #define TSTORM_LL2_PORT_STAT_SIZE			(IRO[2].size)
4105 
4106 /* Ustorm VF-PF Channel ready flag */
4107 #define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \
4108 	(IRO[3].base + ((vf_id) * IRO[3].m1))
4109 #define USTORM_VF_PF_CHANNEL_READY_SIZE			(IRO[3].size)
4110 
4111 /* Ustorm Final flr cleanup ack */
4112 #define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) \
4113 	(IRO[4].base + ((pf_id) * IRO[4].m1))
4114 #define USTORM_FLR_FINAL_ACK_SIZE			(IRO[4].size)
4115 
4116 /* Ustorm Event ring consumer */
4117 #define USTORM_EQE_CONS_OFFSET(pf_id) \
4118 	(IRO[5].base + ((pf_id) * IRO[5].m1))
4119 #define USTORM_EQE_CONS_SIZE				(IRO[5].size)
4120 
4121 /* Ustorm eth queue zone */
4122 #define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) \
4123 	(IRO[6].base + ((queue_zone_id) * IRO[6].m1))
4124 #define USTORM_ETH_QUEUE_ZONE_SIZE			(IRO[6].size)
4125 
4126 /* Ustorm Common Queue ring consumer */
4127 #define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) \
4128 	(IRO[7].base + ((queue_zone_id) * IRO[7].m1))
4129 #define USTORM_COMMON_QUEUE_CONS_SIZE			(IRO[7].size)
4130 
4131 /* Xstorm common PQ info */
4132 #define XSTORM_PQ_INFO_OFFSET(pq_id) \
4133 	(IRO[8].base + ((pq_id) * IRO[8].m1))
4134 #define XSTORM_PQ_INFO_SIZE				(IRO[8].size)
4135 
4136 /* Xstorm Integration Test Data */
4137 #define XSTORM_INTEG_TEST_DATA_OFFSET			(IRO[9].base)
4138 #define XSTORM_INTEG_TEST_DATA_SIZE			(IRO[9].size)
4139 
4140 /* Ystorm Integration Test Data */
4141 #define YSTORM_INTEG_TEST_DATA_OFFSET			(IRO[10].base)
4142 #define YSTORM_INTEG_TEST_DATA_SIZE			(IRO[10].size)
4143 
4144 /* Pstorm Integration Test Data */
4145 #define PSTORM_INTEG_TEST_DATA_OFFSET			(IRO[11].base)
4146 #define PSTORM_INTEG_TEST_DATA_SIZE			(IRO[11].size)
4147 
4148 /* Tstorm Integration Test Data */
4149 #define TSTORM_INTEG_TEST_DATA_OFFSET			(IRO[12].base)
4150 #define TSTORM_INTEG_TEST_DATA_SIZE			(IRO[12].size)
4151 
4152 /* Mstorm Integration Test Data */
4153 #define MSTORM_INTEG_TEST_DATA_OFFSET			(IRO[13].base)
4154 #define MSTORM_INTEG_TEST_DATA_SIZE			(IRO[13].size)
4155 
4156 /* Ustorm Integration Test Data */
4157 #define USTORM_INTEG_TEST_DATA_OFFSET			(IRO[14].base)
4158 #define USTORM_INTEG_TEST_DATA_SIZE			(IRO[14].size)
4159 
4160 /* Xstorm overlay buffer host address */
4161 #define XSTORM_OVERLAY_BUF_ADDR_OFFSET			(IRO[15].base)
4162 #define XSTORM_OVERLAY_BUF_ADDR_SIZE			(IRO[15].size)
4163 
4164 /* Ystorm overlay buffer host address */
4165 #define YSTORM_OVERLAY_BUF_ADDR_OFFSET			(IRO[16].base)
4166 #define YSTORM_OVERLAY_BUF_ADDR_SIZE			(IRO[16].size)
4167 
4168 /* Pstorm overlay buffer host address */
4169 #define PSTORM_OVERLAY_BUF_ADDR_OFFSET			(IRO[17].base)
4170 #define PSTORM_OVERLAY_BUF_ADDR_SIZE			(IRO[17].size)
4171 
4172 /* Tstorm overlay buffer host address */
4173 #define TSTORM_OVERLAY_BUF_ADDR_OFFSET			(IRO[18].base)
4174 #define TSTORM_OVERLAY_BUF_ADDR_SIZE			(IRO[18].size)
4175 
4176 /* Mstorm overlay buffer host address */
4177 #define MSTORM_OVERLAY_BUF_ADDR_OFFSET			(IRO[19].base)
4178 #define MSTORM_OVERLAY_BUF_ADDR_SIZE			(IRO[19].size)
4179 
4180 /* Ustorm overlay buffer host address */
4181 #define USTORM_OVERLAY_BUF_ADDR_OFFSET			(IRO[20].base)
4182 #define USTORM_OVERLAY_BUF_ADDR_SIZE			(IRO[20].size)
4183 
4184 /* Tstorm producers */
4185 #define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \
4186 	(IRO[21].base + ((core_rx_queue_id) * IRO[21].m1))
4187 #define TSTORM_LL2_RX_PRODS_SIZE			(IRO[21].size)
4188 
4189 /* Tstorm LightL2 queue statistics */
4190 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
4191 	(IRO[22].base + ((core_rx_queue_id) * IRO[22].m1))
4192 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE		(IRO[22].size)
4193 
4194 /* Ustorm LiteL2 queue statistics */
4195 #define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
4196 	(IRO[23].base + ((core_rx_queue_id) * IRO[23].m1))
4197 #define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE		(IRO[23].size)
4198 
4199 /* Pstorm LiteL2 queue statistics */
4200 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
4201 	(IRO[24].base + ((core_tx_stats_id) * IRO[24].m1))
4202 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE		(IRO[24].size)
4203 
4204 /* Mstorm queue statistics */
4205 #define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
4206 	(IRO[25].base + ((stat_counter_id) * IRO[25].m1))
4207 #define MSTORM_QUEUE_STAT_SIZE				(IRO[25].size)
4208 
4209 /* TPA agregation timeout in us resolution (on ASIC) */
4210 #define MSTORM_TPA_TIMEOUT_US_OFFSET			(IRO[26].base)
4211 #define MSTORM_TPA_TIMEOUT_US_SIZE			(IRO[26].size)
4212 
4213 /* Mstorm ETH VF queues producers offset in RAM. Used in default VF zone size
4214  * mode
4215  */
4216 #define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \
4217 	(IRO[27].base + ((vf_id) * IRO[27].m1) + ((vf_queue_id) * IRO[27].m2))
4218 #define MSTORM_ETH_VF_PRODS_SIZE			(IRO[27].size)
4219 
4220 /* Mstorm ETH PF queues producers */
4221 #define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) \
4222 	(IRO[28].base + ((queue_id) * IRO[28].m1))
4223 #define MSTORM_ETH_PF_PRODS_SIZE			(IRO[28].size)
4224 
4225 /* Mstorm pf statistics */
4226 #define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \
4227 	(IRO[29].base + ((pf_id) * IRO[29].m1))
4228 #define MSTORM_ETH_PF_STAT_SIZE				(IRO[29].size)
4229 
4230 /* Ustorm queue statistics */
4231 #define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
4232 	(IRO[30].base + ((stat_counter_id) * IRO[30].m1))
4233 #define USTORM_QUEUE_STAT_SIZE				(IRO[30].size)
4234 
4235 /* Ustorm pf statistics */
4236 #define USTORM_ETH_PF_STAT_OFFSET(pf_id) \
4237 	(IRO[31].base + ((pf_id) * IRO[31].m1))
4238 #define USTORM_ETH_PF_STAT_SIZE				(IRO[31].size)
4239 
4240 /* Pstorm queue statistics */
4241 #define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id)	\
4242 	(IRO[32].base + ((stat_counter_id) * IRO[32].m1))
4243 #define PSTORM_QUEUE_STAT_SIZE				(IRO[32].size)
4244 
4245 /* Pstorm pf statistics */
4246 #define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \
4247 	(IRO[33].base + ((pf_id) * IRO[33].m1))
4248 #define PSTORM_ETH_PF_STAT_SIZE				(IRO[33].size)
4249 
4250 /* Control frame's EthType configuration for TX control frame security */
4251 #define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(eth_type_id)	\
4252 	(IRO[34].base + ((eth_type_id) * IRO[34].m1))
4253 #define PSTORM_CTL_FRAME_ETHTYPE_SIZE			(IRO[34].size)
4254 
4255 /* Tstorm last parser message */
4256 #define TSTORM_ETH_PRS_INPUT_OFFSET			(IRO[35].base)
4257 #define TSTORM_ETH_PRS_INPUT_SIZE			(IRO[35].size)
4258 
4259 /* Tstorm Eth limit Rx rate */
4260 #define ETH_RX_RATE_LIMIT_OFFSET(pf_id)	\
4261 	(IRO[36].base + ((pf_id) * IRO[36].m1))
4262 #define ETH_RX_RATE_LIMIT_SIZE				(IRO[36].size)
4263 
4264 /* RSS indirection table entry update command per PF offset in TSTORM PF BAR0.
4265  * Use eth_tstorm_rss_update_data for update
4266  */
4267 #define TSTORM_ETH_RSS_UPDATE_OFFSET(pf_id) \
4268 	(IRO[37].base + ((pf_id) * IRO[37].m1))
4269 #define TSTORM_ETH_RSS_UPDATE_SIZE			(IRO[37].size)
4270 
4271 /* Xstorm queue zone */
4272 #define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
4273 	(IRO[38].base + ((queue_id) * IRO[38].m1))
4274 #define XSTORM_ETH_QUEUE_ZONE_SIZE			(IRO[38].size)
4275 
4276 /* Ystorm cqe producer */
4277 #define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) \
4278 	(IRO[39].base + ((rss_id) * IRO[39].m1))
4279 #define YSTORM_TOE_CQ_PROD_SIZE				(IRO[39].size)
4280 
4281 /* Ustorm cqe producer */
4282 #define USTORM_TOE_CQ_PROD_OFFSET(rss_id) \
4283 	(IRO[40].base + ((rss_id) * IRO[40].m1))
4284 #define USTORM_TOE_CQ_PROD_SIZE				(IRO[40].size)
4285 
4286 /* Ustorm grq producer */
4287 #define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) \
4288 	(IRO[41].base + ((pf_id) * IRO[41].m1))
4289 #define USTORM_TOE_GRQ_PROD_SIZE			(IRO[41].size)
4290 
4291 /* Tstorm cmdq-cons of given command queue-id */
4292 #define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \
4293 	(IRO[42].base + ((cmdq_queue_id) * IRO[42].m1))
4294 #define TSTORM_SCSI_CMDQ_CONS_SIZE			(IRO[42].size)
4295 
4296 /* Tstorm (reflects M-Storm) bdq-external-producer of given function ID,
4297  * BDqueue-id
4298  */
4299 #define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(storage_func_id, bdq_id) \
4300 	(IRO[43].base + ((storage_func_id) * IRO[43].m1) + \
4301 	 ((bdq_id) * IRO[43].m2))
4302 #define TSTORM_SCSI_BDQ_EXT_PROD_SIZE			(IRO[43].size)
4303 
4304 /* Mstorm bdq-external-producer of given BDQ resource ID, BDqueue-id */
4305 #define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(storage_func_id, bdq_id) \
4306 	(IRO[44].base + ((storage_func_id) * IRO[44].m1) + \
4307 	 ((bdq_id) * IRO[44].m2))
4308 #define MSTORM_SCSI_BDQ_EXT_PROD_SIZE			(IRO[44].size)
4309 
4310 /* Tstorm iSCSI RX stats */
4311 #define TSTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \
4312 	(IRO[45].base + ((storage_func_id) * IRO[45].m1))
4313 #define TSTORM_ISCSI_RX_STATS_SIZE			(IRO[45].size)
4314 
4315 /* Mstorm iSCSI RX stats */
4316 #define MSTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \
4317 	(IRO[46].base + ((storage_func_id) * IRO[46].m1))
4318 #define MSTORM_ISCSI_RX_STATS_SIZE			(IRO[46].size)
4319 
4320 /* Ustorm iSCSI RX stats */
4321 #define USTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \
4322 	(IRO[47].base + ((storage_func_id) * IRO[47].m1))
4323 #define USTORM_ISCSI_RX_STATS_SIZE			(IRO[47].size)
4324 
4325 /* Xstorm iSCSI TX stats */
4326 #define XSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \
4327 	(IRO[48].base + ((storage_func_id) * IRO[48].m1))
4328 #define XSTORM_ISCSI_TX_STATS_SIZE			(IRO[48].size)
4329 
4330 /* Ystorm iSCSI TX stats */
4331 #define YSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \
4332 	(IRO[49].base + ((storage_func_id) * IRO[49].m1))
4333 #define YSTORM_ISCSI_TX_STATS_SIZE			(IRO[49].size)
4334 
4335 /* Pstorm iSCSI TX stats */
4336 #define PSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \
4337 	(IRO[50].base + ((storage_func_id) * IRO[50].m1))
4338 #define PSTORM_ISCSI_TX_STATS_SIZE			(IRO[50].size)
4339 
4340 /* Tstorm FCoE RX stats */
4341 #define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
4342 	(IRO[51].base + ((pf_id) * IRO[51].m1))
4343 #define TSTORM_FCOE_RX_STATS_SIZE			(IRO[51].size)
4344 
4345 /* Pstorm FCoE TX stats */
4346 #define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \
4347 	(IRO[52].base + ((pf_id) * IRO[52].m1))
4348 #define PSTORM_FCOE_TX_STATS_SIZE			(IRO[52].size)
4349 
4350 /* Pstorm RDMA queue statistics */
4351 #define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
4352 	(IRO[53].base + ((rdma_stat_counter_id) * IRO[53].m1))
4353 #define PSTORM_RDMA_QUEUE_STAT_SIZE			(IRO[53].size)
4354 
4355 /* Tstorm RDMA queue statistics */
4356 #define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
4357 	(IRO[54].base + ((rdma_stat_counter_id) * IRO[54].m1))
4358 #define TSTORM_RDMA_QUEUE_STAT_SIZE			(IRO[54].size)
4359 
4360 /* Xstorm error level for assert */
4361 #define XSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4362 	(IRO[55].base + ((pf_id) * IRO[55].m1))
4363 #define XSTORM_RDMA_ASSERT_LEVEL_SIZE			(IRO[55].size)
4364 
4365 /* Ystorm error level for assert */
4366 #define YSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4367 	(IRO[56].base + ((pf_id) * IRO[56].m1))
4368 #define YSTORM_RDMA_ASSERT_LEVEL_SIZE			(IRO[56].size)
4369 
4370 /* Pstorm error level for assert */
4371 #define PSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4372 	(IRO[57].base + ((pf_id) * IRO[57].m1))
4373 #define PSTORM_RDMA_ASSERT_LEVEL_SIZE			(IRO[57].size)
4374 
4375 /* Tstorm error level for assert */
4376 #define TSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4377 	(IRO[58].base + ((pf_id) * IRO[58].m1))
4378 #define TSTORM_RDMA_ASSERT_LEVEL_SIZE			(IRO[58].size)
4379 
4380 /* Mstorm error level for assert */
4381 #define MSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4382 	(IRO[59].base + ((pf_id) * IRO[59].m1))
4383 #define MSTORM_RDMA_ASSERT_LEVEL_SIZE			(IRO[59].size)
4384 
4385 /* Ustorm error level for assert */
4386 #define USTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
4387 	(IRO[60].base + ((pf_id) * IRO[60].m1))
4388 #define USTORM_RDMA_ASSERT_LEVEL_SIZE			(IRO[60].size)
4389 
4390 /* Xstorm iWARP rxmit stats */
4391 #define XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id) \
4392 	(IRO[61].base + ((pf_id) * IRO[61].m1))
4393 #define XSTORM_IWARP_RXMIT_STATS_SIZE			(IRO[61].size)
4394 
4395 /* Tstorm RoCE Event Statistics */
4396 #define TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id)	\
4397 	(IRO[62].base + ((roce_pf_id) * IRO[62].m1))
4398 #define TSTORM_ROCE_EVENTS_STAT_SIZE			(IRO[62].size)
4399 
4400 /* DCQCN Received Statistics */
4401 #define YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id)\
4402 	(IRO[63].base + ((roce_pf_id) * IRO[63].m1))
4403 #define YSTORM_ROCE_DCQCN_RECEIVED_STATS_SIZE		(IRO[63].size)
4404 
4405 /* RoCE Error Statistics */
4406 #define YSTORM_ROCE_ERROR_STATS_OFFSET(roce_pf_id)	\
4407 	(IRO[64].base + ((roce_pf_id) * IRO[64].m1))
4408 #define YSTORM_ROCE_ERROR_STATS_SIZE			(IRO[64].size)
4409 
4410 /* DCQCN Sent Statistics */
4411 #define PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id)	\
4412 	(IRO[65].base + ((roce_pf_id) * IRO[65].m1))
4413 #define PSTORM_ROCE_DCQCN_SENT_STATS_SIZE		(IRO[65].size)
4414 
4415 /* RoCE CQEs Statistics */
4416 #define USTORM_ROCE_CQE_STATS_OFFSET(roce_pf_id)	\
4417 	(IRO[66].base + ((roce_pf_id) * IRO[66].m1))
4418 #define USTORM_ROCE_CQE_STATS_SIZE			(IRO[66].size)
4419 
4420 /* IRO Array */
4421 static const u32 iro_arr[] = {
4422 	0x00000000, 0x00000000, 0x00080000,
4423 	0x00003288, 0x00000088, 0x00880000,
4424 	0x000058e8, 0x00000020, 0x00200000,
4425 	0x00000b00, 0x00000008, 0x00040000,
4426 	0x00000a80, 0x00000008, 0x00040000,
4427 	0x00000000, 0x00000008, 0x00020000,
4428 	0x00000080, 0x00000008, 0x00040000,
4429 	0x00000084, 0x00000008, 0x00020000,
4430 	0x00005718, 0x00000004, 0x00040000,
4431 	0x00004dd0, 0x00000000, 0x00780000,
4432 	0x00003e40, 0x00000000, 0x00780000,
4433 	0x00004480, 0x00000000, 0x00780000,
4434 	0x00003210, 0x00000000, 0x00780000,
4435 	0x00003b50, 0x00000000, 0x00780000,
4436 	0x00007f58, 0x00000000, 0x00780000,
4437 	0x00005f58, 0x00000000, 0x00080000,
4438 	0x00007100, 0x00000000, 0x00080000,
4439 	0x0000aea0, 0x00000000, 0x00080000,
4440 	0x00004398, 0x00000000, 0x00080000,
4441 	0x0000a5a0, 0x00000000, 0x00080000,
4442 	0x0000bde8, 0x00000000, 0x00080000,
4443 	0x00000020, 0x00000004, 0x00040000,
4444 	0x000056c8, 0x00000010, 0x00100000,
4445 	0x0000c210, 0x00000030, 0x00300000,
4446 	0x0000b088, 0x00000038, 0x00380000,
4447 	0x00003d20, 0x00000080, 0x00400000,
4448 	0x0000bf60, 0x00000000, 0x00040000,
4449 	0x00004560, 0x00040080, 0x00040000,
4450 	0x000001f8, 0x00000004, 0x00040000,
4451 	0x00003d60, 0x00000080, 0x00200000,
4452 	0x00008960, 0x00000040, 0x00300000,
4453 	0x0000e840, 0x00000060, 0x00600000,
4454 	0x00004618, 0x00000080, 0x00380000,
4455 	0x00010738, 0x000000c0, 0x00c00000,
4456 	0x000001f8, 0x00000002, 0x00020000,
4457 	0x0000a2a0, 0x00000000, 0x01080000,
4458 	0x0000a3a8, 0x00000008, 0x00080000,
4459 	0x000001c0, 0x00000008, 0x00080000,
4460 	0x000001f8, 0x00000008, 0x00080000,
4461 	0x00000ac0, 0x00000008, 0x00080000,
4462 	0x00002578, 0x00000008, 0x00080000,
4463 	0x000024f8, 0x00000008, 0x00080000,
4464 	0x00000280, 0x00000008, 0x00080000,
4465 	0x00000680, 0x00080018, 0x00080000,
4466 	0x00000b78, 0x00080018, 0x00020000,
4467 	0x0000c640, 0x00000050, 0x003c0000,
4468 	0x00012038, 0x00000018, 0x00100000,
4469 	0x00011b00, 0x00000040, 0x00180000,
4470 	0x000095d0, 0x00000050, 0x00200000,
4471 	0x00008b10, 0x00000040, 0x00280000,
4472 	0x00011640, 0x00000018, 0x00100000,
4473 	0x0000c828, 0x00000048, 0x00380000,
4474 	0x00011710, 0x00000020, 0x00200000,
4475 	0x00004650, 0x00000080, 0x00100000,
4476 	0x00003618, 0x00000010, 0x00100000,
4477 	0x0000a968, 0x00000008, 0x00010000,
4478 	0x000097a0, 0x00000008, 0x00010000,
4479 	0x00011990, 0x00000008, 0x00010000,
4480 	0x0000f018, 0x00000008, 0x00010000,
4481 	0x00012628, 0x00000008, 0x00010000,
4482 	0x00011da8, 0x00000008, 0x00010000,
4483 	0x0000aa78, 0x00000030, 0x00100000,
4484 	0x0000d768, 0x00000028, 0x00280000,
4485 	0x00009a58, 0x00000018, 0x00180000,
4486 	0x00009bd8, 0x00000008, 0x00080000,
4487 	0x00013a18, 0x00000008, 0x00080000,
4488 	0x000126e8, 0x00000018, 0x00180000,
4489 	0x0000e608, 0x00500288, 0x00100000,
4490 	0x00012970, 0x00000138, 0x00280000,
4491 };
4492 
4493 /* Runtime array offsets */
4494 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET				0
4495 #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET				1
4496 #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET				2
4497 #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET				3
4498 #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET				4
4499 #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET				5
4500 #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET				6
4501 #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET				7
4502 #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET				8
4503 #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET				9
4504 #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET				10
4505 #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET				11
4506 #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET				12
4507 #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET				13
4508 #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET				14
4509 #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET				15
4510 #define DORQ_REG_VF_ICID_BIT_SHIFT_NORM_RT_OFFSET			16
4511 #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET					17
4512 #define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET				18
4513 #define IGU_REG_PF_CONFIGURATION_RT_OFFSET				19
4514 #define IGU_REG_VF_CONFIGURATION_RT_OFFSET				20
4515 #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET				21
4516 #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET				22
4517 #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET				23
4518 #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET				24
4519 #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET				25
4520 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET					26
4521 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE					736
4522 #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET				762
4523 #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE					736
4524 #define CAU_REG_PI_MEMORY_RT_OFFSET					1498
4525 #define CAU_REG_PI_MEMORY_RT_SIZE					4416
4526 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET			5914
4527 #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET			5915
4528 #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET			5916
4529 #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET				5917
4530 #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET				5918
4531 #define PRS_REG_SEARCH_TCP_RT_OFFSET					5919
4532 #define PRS_REG_SEARCH_FCOE_RT_OFFSET					5920
4533 #define PRS_REG_SEARCH_ROCE_RT_OFFSET					5921
4534 #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET				5922
4535 #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET				5923
4536 #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET				5924
4537 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET			5925
4538 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET		5926
4539 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET			5927
4540 #define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET				5928
4541 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET				5929
4542 #define SRC_REG_FIRSTFREE_RT_OFFSET					5930
4543 #define SRC_REG_FIRSTFREE_RT_SIZE					2
4544 #define SRC_REG_LASTFREE_RT_OFFSET					5932
4545 #define SRC_REG_LASTFREE_RT_SIZE					2
4546 #define SRC_REG_COUNTFREE_RT_OFFSET					5934
4547 #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET				5935
4548 #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET				5936
4549 #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET				5937
4550 #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET					5938
4551 #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET					5939
4552 #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET					5940
4553 #define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET				5941
4554 #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET				5942
4555 #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET				5943
4556 #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET				5944
4557 #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET				5945
4558 #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET				5946
4559 #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET				5947
4560 #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET				5948
4561 #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET				5949
4562 #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET				5950
4563 #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET				5951
4564 #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET				5952
4565 #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET				5953
4566 #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET			5954
4567 #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET			5955
4568 #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET			5956
4569 #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET				5957
4570 #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET				5958
4571 #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET				5959
4572 #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET				5960
4573 #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET				5961
4574 #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET				5962
4575 #define PSWRQ2_REG_VF_BASE_RT_OFFSET					5963
4576 #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET				5964
4577 #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET				5965
4578 #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET				5966
4579 #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET					5967
4580 #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE					22000
4581 #define PGLUE_REG_B_VF_BASE_RT_OFFSET					27967
4582 #define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET			27968
4583 #define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET				27969
4584 #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET				27970
4585 #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET				27971
4586 #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET				27972
4587 #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET				27973
4588 #define TM_REG_VF_ENABLE_CONN_RT_OFFSET					27974
4589 #define TM_REG_PF_ENABLE_CONN_RT_OFFSET					27975
4590 #define TM_REG_PF_ENABLE_TASK_RT_OFFSET					27976
4591 #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET			27977
4592 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET			27978
4593 #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET				27979
4594 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE					416
4595 #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET				28395
4596 #define TM_REG_CONFIG_TASK_MEM_RT_SIZE					512
4597 #define QM_REG_MAXPQSIZE_0_RT_OFFSET					28907
4598 #define QM_REG_MAXPQSIZE_1_RT_OFFSET					28908
4599 #define QM_REG_MAXPQSIZE_2_RT_OFFSET					28909
4600 #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET				28910
4601 #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET				28911
4602 #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET				28912
4603 #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET				28913
4604 #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET				28914
4605 #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET				28915
4606 #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET				28916
4607 #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET				28917
4608 #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET				28918
4609 #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET				28919
4610 #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET				28920
4611 #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET				28921
4612 #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET				28922
4613 #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET				28923
4614 #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET				28924
4615 #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET				28925
4616 #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET				28926
4617 #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET				28927
4618 #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET				28928
4619 #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET				28929
4620 #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET				28930
4621 #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET				28931
4622 #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET				28932
4623 #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET				28933
4624 #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET				28934
4625 #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET				28935
4626 #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET				28936
4627 #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET				28937
4628 #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET				28938
4629 #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET				28939
4630 #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET				28940
4631 #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET				28941
4632 #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET				28942
4633 #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET				28943
4634 #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET				28944
4635 #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET				28945
4636 #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET				28946
4637 #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET				28947
4638 #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET				28948
4639 #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET				28949
4640 #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET				28950
4641 #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET				28951
4642 #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET				28952
4643 #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET				28953
4644 #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET				28954
4645 #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET				28955
4646 #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET				28956
4647 #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET				28957
4648 #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET				28958
4649 #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET				28959
4650 #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET				28960
4651 #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET				28961
4652 #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET				28962
4653 #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET				28963
4654 #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET				28964
4655 #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET				28965
4656 #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET				28966
4657 #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET				28967
4658 #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET				28968
4659 #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET				28969
4660 #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET				28970
4661 #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET				28971
4662 #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET				28972
4663 #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET				28973
4664 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET				28974
4665 #define QM_REG_BASEADDROTHERPQ_RT_SIZE					128
4666 #define QM_REG_PTRTBLOTHER_RT_OFFSET					29102
4667 #define QM_REG_PTRTBLOTHER_RT_SIZE					256
4668 #define QM_REG_VOQCRDLINE_RT_OFFSET					29358
4669 #define QM_REG_VOQCRDLINE_RT_SIZE					20
4670 #define QM_REG_VOQINITCRDLINE_RT_OFFSET					29378
4671 #define QM_REG_VOQINITCRDLINE_RT_SIZE					20
4672 #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET				29398
4673 #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET				29399
4674 #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET				29400
4675 #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET				29401
4676 #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET				29402
4677 #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET				29403
4678 #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET				29404
4679 #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET				29405
4680 #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET				29406
4681 #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET				29407
4682 #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET				29408
4683 #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET				29409
4684 #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET				29410
4685 #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET				29411
4686 #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET				29412
4687 #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET				29413
4688 #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET				29414
4689 #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET				29415
4690 #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET				29416
4691 #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET				29417
4692 #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET				29418
4693 #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET				29419
4694 #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET				29420
4695 #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET				29421
4696 #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET				29422
4697 #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET				29423
4698 #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET				29424
4699 #define QM_REG_PQTX2PF_0_RT_OFFSET					29425
4700 #define QM_REG_PQTX2PF_1_RT_OFFSET					29426
4701 #define QM_REG_PQTX2PF_2_RT_OFFSET					29427
4702 #define QM_REG_PQTX2PF_3_RT_OFFSET					29428
4703 #define QM_REG_PQTX2PF_4_RT_OFFSET					29429
4704 #define QM_REG_PQTX2PF_5_RT_OFFSET					29430
4705 #define QM_REG_PQTX2PF_6_RT_OFFSET					29431
4706 #define QM_REG_PQTX2PF_7_RT_OFFSET					29432
4707 #define QM_REG_PQTX2PF_8_RT_OFFSET					29433
4708 #define QM_REG_PQTX2PF_9_RT_OFFSET					29434
4709 #define QM_REG_PQTX2PF_10_RT_OFFSET					29435
4710 #define QM_REG_PQTX2PF_11_RT_OFFSET					29436
4711 #define QM_REG_PQTX2PF_12_RT_OFFSET					29437
4712 #define QM_REG_PQTX2PF_13_RT_OFFSET					29438
4713 #define QM_REG_PQTX2PF_14_RT_OFFSET					29439
4714 #define QM_REG_PQTX2PF_15_RT_OFFSET					29440
4715 #define QM_REG_PQTX2PF_16_RT_OFFSET					29441
4716 #define QM_REG_PQTX2PF_17_RT_OFFSET					29442
4717 #define QM_REG_PQTX2PF_18_RT_OFFSET					29443
4718 #define QM_REG_PQTX2PF_19_RT_OFFSET					29444
4719 #define QM_REG_PQTX2PF_20_RT_OFFSET					29445
4720 #define QM_REG_PQTX2PF_21_RT_OFFSET					29446
4721 #define QM_REG_PQTX2PF_22_RT_OFFSET					29447
4722 #define QM_REG_PQTX2PF_23_RT_OFFSET					29448
4723 #define QM_REG_PQTX2PF_24_RT_OFFSET					29449
4724 #define QM_REG_PQTX2PF_25_RT_OFFSET					29450
4725 #define QM_REG_PQTX2PF_26_RT_OFFSET					29451
4726 #define QM_REG_PQTX2PF_27_RT_OFFSET					29452
4727 #define QM_REG_PQTX2PF_28_RT_OFFSET					29453
4728 #define QM_REG_PQTX2PF_29_RT_OFFSET					29454
4729 #define QM_REG_PQTX2PF_30_RT_OFFSET					29455
4730 #define QM_REG_PQTX2PF_31_RT_OFFSET					29456
4731 #define QM_REG_PQTX2PF_32_RT_OFFSET					29457
4732 #define QM_REG_PQTX2PF_33_RT_OFFSET					29458
4733 #define QM_REG_PQTX2PF_34_RT_OFFSET					29459
4734 #define QM_REG_PQTX2PF_35_RT_OFFSET					29460
4735 #define QM_REG_PQTX2PF_36_RT_OFFSET					29461
4736 #define QM_REG_PQTX2PF_37_RT_OFFSET					29462
4737 #define QM_REG_PQTX2PF_38_RT_OFFSET					29463
4738 #define QM_REG_PQTX2PF_39_RT_OFFSET					29464
4739 #define QM_REG_PQTX2PF_40_RT_OFFSET					29465
4740 #define QM_REG_PQTX2PF_41_RT_OFFSET					29466
4741 #define QM_REG_PQTX2PF_42_RT_OFFSET					29467
4742 #define QM_REG_PQTX2PF_43_RT_OFFSET					29468
4743 #define QM_REG_PQTX2PF_44_RT_OFFSET					29469
4744 #define QM_REG_PQTX2PF_45_RT_OFFSET					29470
4745 #define QM_REG_PQTX2PF_46_RT_OFFSET					29471
4746 #define QM_REG_PQTX2PF_47_RT_OFFSET					29472
4747 #define QM_REG_PQTX2PF_48_RT_OFFSET					29473
4748 #define QM_REG_PQTX2PF_49_RT_OFFSET					29474
4749 #define QM_REG_PQTX2PF_50_RT_OFFSET					29475
4750 #define QM_REG_PQTX2PF_51_RT_OFFSET					29476
4751 #define QM_REG_PQTX2PF_52_RT_OFFSET					29477
4752 #define QM_REG_PQTX2PF_53_RT_OFFSET					29478
4753 #define QM_REG_PQTX2PF_54_RT_OFFSET					29479
4754 #define QM_REG_PQTX2PF_55_RT_OFFSET					29480
4755 #define QM_REG_PQTX2PF_56_RT_OFFSET					29481
4756 #define QM_REG_PQTX2PF_57_RT_OFFSET					29482
4757 #define QM_REG_PQTX2PF_58_RT_OFFSET					29483
4758 #define QM_REG_PQTX2PF_59_RT_OFFSET					29484
4759 #define QM_REG_PQTX2PF_60_RT_OFFSET					29485
4760 #define QM_REG_PQTX2PF_61_RT_OFFSET					29486
4761 #define QM_REG_PQTX2PF_62_RT_OFFSET					29487
4762 #define QM_REG_PQTX2PF_63_RT_OFFSET					29488
4763 #define QM_REG_PQOTHER2PF_0_RT_OFFSET					29489
4764 #define QM_REG_PQOTHER2PF_1_RT_OFFSET					29490
4765 #define QM_REG_PQOTHER2PF_2_RT_OFFSET					29491
4766 #define QM_REG_PQOTHER2PF_3_RT_OFFSET					29492
4767 #define QM_REG_PQOTHER2PF_4_RT_OFFSET					29493
4768 #define QM_REG_PQOTHER2PF_5_RT_OFFSET					29494
4769 #define QM_REG_PQOTHER2PF_6_RT_OFFSET					29495
4770 #define QM_REG_PQOTHER2PF_7_RT_OFFSET					29496
4771 #define QM_REG_PQOTHER2PF_8_RT_OFFSET					29497
4772 #define QM_REG_PQOTHER2PF_9_RT_OFFSET					29498
4773 #define QM_REG_PQOTHER2PF_10_RT_OFFSET					29499
4774 #define QM_REG_PQOTHER2PF_11_RT_OFFSET					29500
4775 #define QM_REG_PQOTHER2PF_12_RT_OFFSET					29501
4776 #define QM_REG_PQOTHER2PF_13_RT_OFFSET					29502
4777 #define QM_REG_PQOTHER2PF_14_RT_OFFSET					29503
4778 #define QM_REG_PQOTHER2PF_15_RT_OFFSET					29504
4779 #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET					29505
4780 #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET					29506
4781 #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET				29507
4782 #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET				29508
4783 #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET				29509
4784 #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET				29510
4785 #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET				29511
4786 #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET				29512
4787 #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET				29513
4788 #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET				29514
4789 #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET				29515
4790 #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET				29516
4791 #define QM_REG_RLGLBLINCVAL_RT_OFFSET					29517
4792 #define QM_REG_RLGLBLINCVAL_RT_SIZE					256
4793 #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET				29773
4794 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE					256
4795 #define QM_REG_RLGLBLCRD_RT_OFFSET					30029
4796 #define QM_REG_RLGLBLCRD_RT_SIZE					256
4797 #define QM_REG_RLGLBLENABLE_RT_OFFSET					30285
4798 #define QM_REG_RLPFPERIOD_RT_OFFSET					30286
4799 #define QM_REG_RLPFPERIODTIMER_RT_OFFSET				30287
4800 #define QM_REG_RLPFINCVAL_RT_OFFSET					30288
4801 #define QM_REG_RLPFINCVAL_RT_SIZE					16
4802 #define QM_REG_RLPFUPPERBOUND_RT_OFFSET					30304
4803 #define QM_REG_RLPFUPPERBOUND_RT_SIZE					16
4804 #define QM_REG_RLPFCRD_RT_OFFSET					30320
4805 #define QM_REG_RLPFCRD_RT_SIZE						16
4806 #define QM_REG_RLPFENABLE_RT_OFFSET					30336
4807 #define QM_REG_RLPFVOQENABLE_RT_OFFSET					30337
4808 #define QM_REG_WFQPFWEIGHT_RT_OFFSET					30338
4809 #define QM_REG_WFQPFWEIGHT_RT_SIZE					16
4810 #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET				30354
4811 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE					16
4812 #define QM_REG_WFQPFCRD_RT_OFFSET					30370
4813 #define QM_REG_WFQPFCRD_RT_SIZE						160
4814 #define QM_REG_WFQPFENABLE_RT_OFFSET					30530
4815 #define QM_REG_WFQVPENABLE_RT_OFFSET					30531
4816 #define QM_REG_BASEADDRTXPQ_RT_OFFSET					30532
4817 #define QM_REG_BASEADDRTXPQ_RT_SIZE					512
4818 #define QM_REG_TXPQMAP_RT_OFFSET					31044
4819 #define QM_REG_TXPQMAP_RT_SIZE						512
4820 #define QM_REG_WFQVPWEIGHT_RT_OFFSET					31556
4821 #define QM_REG_WFQVPWEIGHT_RT_SIZE					512
4822 #define QM_REG_WFQVPCRD_RT_OFFSET					32068
4823 #define QM_REG_WFQVPCRD_RT_SIZE						512
4824 #define QM_REG_WFQVPMAP_RT_OFFSET					32580
4825 #define QM_REG_WFQVPMAP_RT_SIZE						512
4826 #define QM_REG_PTRTBLTX_RT_OFFSET					33092
4827 #define QM_REG_PTRTBLTX_RT_SIZE						1024
4828 #define QM_REG_WFQPFCRD_MSB_RT_OFFSET					34116
4829 #define QM_REG_WFQPFCRD_MSB_RT_SIZE					160
4830 #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET				34276
4831 #define NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET				34277
4832 #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET				34278
4833 #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET				34279
4834 #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET				34280
4835 #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET				34281
4836 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET			34282
4837 #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET				34283
4838 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE					4
4839 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET				34287
4840 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE				4
4841 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET				34291
4842 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE				32
4843 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET				34323
4844 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE				16
4845 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET				34339
4846 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE				16
4847 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET			34355
4848 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE			16
4849 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET			34371
4850 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE				16
4851 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET					34387
4852 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_OFFSET				34388
4853 #define NIG_REG_PPF_TO_ENGINE_SEL_RT_SIZE				8
4854 #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET				34396
4855 #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET				34397
4856 #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET				34398
4857 #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET				34399
4858 #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET				34400
4859 #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET				34401
4860 #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET				34402
4861 #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET			34403
4862 #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET			34404
4863 #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET			34405
4864 #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET			34406
4865 #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET				34407
4866 #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET				34408
4867 #define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET				34409
4868 #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET				34410
4869 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET			34411
4870 #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET				34412
4871 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET			34413
4872 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET			34414
4873 #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET				34415
4874 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET			34416
4875 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET			34417
4876 #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET				34418
4877 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET			34419
4878 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET			34420
4879 #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET				34421
4880 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET			34422
4881 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET			34423
4882 #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET				34424
4883 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET			34425
4884 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET			34426
4885 #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET				34427
4886 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET			34428
4887 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET			34429
4888 #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET				34430
4889 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET			34431
4890 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET			34432
4891 #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET				34433
4892 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET			34434
4893 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET			34435
4894 #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET				34436
4895 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET			34437
4896 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET			34438
4897 #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET				34439
4898 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET			34440
4899 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET			34441
4900 #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET				34442
4901 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET			34443
4902 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET			34444
4903 #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET				34445
4904 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET			34446
4905 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET			34447
4906 #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET				34448
4907 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET			34449
4908 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET			34450
4909 #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET				34451
4910 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET			34452
4911 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET			34453
4912 #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET				34454
4913 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET			34455
4914 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET			34456
4915 #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET				34457
4916 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET			34458
4917 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET			34459
4918 #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET				34460
4919 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET			34461
4920 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET			34462
4921 #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET				34463
4922 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET			34464
4923 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET			34465
4924 #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET				34466
4925 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET			34467
4926 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET			34468
4927 #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET				34469
4928 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET			34470
4929 #define XCM_REG_CON_PHY_Q3_RT_OFFSET					34471
4930 
4931 #define RUNTIME_ARRAY_SIZE 34472
4932 
4933 /* Init Callbacks */
4934 #define DMAE_READY_CB	0
4935 
4936 /* The eth storm context for the Tstorm */
4937 struct tstorm_eth_conn_st_ctx {
4938 	__le32 reserved[4];
4939 };
4940 
4941 /* The eth storm context for the Pstorm */
4942 struct pstorm_eth_conn_st_ctx {
4943 	__le32 reserved[8];
4944 };
4945 
4946 /* The eth storm context for the Xstorm */
4947 struct xstorm_eth_conn_st_ctx {
4948 	__le32 reserved[60];
4949 };
4950 
4951 struct e4_xstorm_eth_conn_ag_ctx {
4952 	u8 reserved0;
4953 	u8 state;
4954 	u8 flags0;
4955 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
4956 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
4957 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK	0x1
4958 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT	1
4959 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK	0x1
4960 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT	2
4961 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
4962 #define E4_XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT	3
4963 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK	0x1
4964 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT	4
4965 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK	0x1
4966 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT	5
4967 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK	0x1
4968 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT	6
4969 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK	0x1
4970 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT	7
4971 		u8 flags1;
4972 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK	0x1
4973 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT	0
4974 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK	0x1
4975 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT	1
4976 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK	0x1
4977 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT	2
4978 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_MASK		0x1
4979 #define E4_XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT		3
4980 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_MASK	0x1
4981 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED2_SHIFT	4
4982 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_MASK	0x1
4983 #define E4_XSTORM_ETH_CONN_AG_CTX_E5_RESERVED3_SHIFT	5
4984 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK	0x1
4985 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT	6
4986 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK	0x1
4987 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT	7
4988 	u8 flags2;
4989 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_MASK	0x3
4990 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT	0
4991 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_MASK	0x3
4992 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT	2
4993 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_MASK	0x3
4994 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT	4
4995 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_MASK	0x3
4996 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT	6
4997 	u8 flags3;
4998 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_MASK	0x3
4999 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT	0
5000 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_MASK	0x3
5001 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT	2
5002 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_MASK	0x3
5003 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT	4
5004 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_MASK	0x3
5005 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT	6
5006 		u8 flags4;
5007 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_MASK	0x3
5008 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT	0
5009 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_MASK	0x3
5010 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT	2
5011 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_MASK	0x3
5012 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT	4
5013 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_MASK	0x3
5014 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT	6
5015 	u8 flags5;
5016 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_MASK	0x3
5017 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT	0
5018 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_MASK	0x3
5019 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT	2
5020 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_MASK	0x3
5021 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT	4
5022 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_MASK	0x3
5023 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT	6
5024 	u8 flags6;
5025 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK		0x3
5026 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT	0
5027 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK		0x3
5028 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT	2
5029 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK			0x3
5030 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT			4
5031 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK		0x3
5032 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT		6
5033 	u8 flags7;
5034 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK		0x3
5035 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT	0
5036 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK	0x3
5037 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT	2
5038 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK	0x3
5039 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT	4
5040 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK		0x1
5041 #define E4_XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT		6
5042 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK		0x1
5043 #define E4_XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT		7
5044 	u8 flags8;
5045 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK	0x1
5046 #define E4_XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT	0
5047 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK	0x1
5048 #define E4_XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT	1
5049 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK	0x1
5050 #define E4_XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT	2
5051 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK	0x1
5052 #define E4_XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT	3
5053 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK	0x1
5054 #define E4_XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT	4
5055 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK	0x1
5056 #define E4_XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT	5
5057 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK	0x1
5058 #define E4_XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT	6
5059 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK	0x1
5060 #define E4_XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT	7
5061 	u8 flags9;
5062 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK			0x1
5063 #define E4_XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT			0
5064 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK			0x1
5065 #define E4_XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT			1
5066 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK			0x1
5067 #define E4_XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT			2
5068 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK			0x1
5069 #define E4_XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT			3
5070 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK			0x1
5071 #define E4_XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT			4
5072 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK			0x1
5073 #define E4_XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT			5
5074 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK	0x1
5075 #define E4_XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT	6
5076 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK	0x1
5077 #define E4_XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT	7
5078 	u8 flags10;
5079 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK			0x1
5080 #define E4_XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT		0
5081 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK		0x1
5082 #define E4_XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT		1
5083 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK		0x1
5084 #define E4_XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT		2
5085 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK		0x1
5086 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT		3
5087 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK		0x1
5088 #define E4_XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT		4
5089 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK	0x1
5090 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT	5
5091 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK		0x1
5092 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT		6
5093 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK		0x1
5094 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT		7
5095 	u8 flags11;
5096 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK	0x1
5097 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT	0
5098 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK	0x1
5099 #define E4_XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT	1
5100 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK	0x1
5101 #define E4_XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT	2
5102 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK		0x1
5103 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT		3
5104 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK		0x1
5105 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT		4
5106 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK		0x1
5107 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT		5
5108 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK	0x1
5109 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT	6
5110 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK		0x1
5111 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT		7
5112 	u8 flags12;
5113 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK		0x1
5114 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT	0
5115 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK		0x1
5116 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT	1
5117 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK	0x1
5118 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT	2
5119 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK	0x1
5120 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT	3
5121 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK		0x1
5122 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT	4
5123 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK		0x1
5124 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT	5
5125 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK		0x1
5126 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT	6
5127 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK		0x1
5128 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT	7
5129 	u8 flags13;
5130 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK		0x1
5131 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT	0
5132 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK		0x1
5133 #define E4_XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT	1
5134 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK	0x1
5135 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT	2
5136 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK	0x1
5137 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT	3
5138 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK	0x1
5139 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT	4
5140 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK	0x1
5141 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT	5
5142 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK	0x1
5143 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT	6
5144 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK	0x1
5145 #define E4_XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT	7
5146 	u8 flags14;
5147 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK		0x1
5148 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT	0
5149 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK	0x1
5150 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT	1
5151 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK	0x1
5152 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT	2
5153 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK	0x1
5154 #define E4_XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT	3
5155 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK		0x1
5156 #define E4_XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT		4
5157 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK		0x1
5158 #define E4_XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT	5
5159 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK		0x3
5160 #define E4_XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT		6
5161 	u8 edpm_event_id;
5162 	__le16 physical_q0;
5163 	__le16 e5_reserved1;
5164 	__le16 edpm_num_bds;
5165 	__le16 tx_bd_cons;
5166 	__le16 tx_bd_prod;
5167 	__le16 updated_qm_pq_id;
5168 	__le16 conn_dpi;
5169 	u8 byte3;
5170 	u8 byte4;
5171 	u8 byte5;
5172 	u8 byte6;
5173 	__le32 reg0;
5174 	__le32 reg1;
5175 	__le32 reg2;
5176 	__le32 reg3;
5177 	__le32 reg4;
5178 	__le32 reg5;
5179 	__le32 reg6;
5180 	__le16 word7;
5181 	__le16 word8;
5182 	__le16 word9;
5183 	__le16 word10;
5184 	__le32 reg7;
5185 	__le32 reg8;
5186 	__le32 reg9;
5187 	u8 byte7;
5188 	u8 byte8;
5189 	u8 byte9;
5190 	u8 byte10;
5191 	u8 byte11;
5192 	u8 byte12;
5193 	u8 byte13;
5194 	u8 byte14;
5195 	u8 byte15;
5196 	u8 e5_reserved;
5197 	__le16 word11;
5198 	__le32 reg10;
5199 	__le32 reg11;
5200 	__le32 reg12;
5201 	__le32 reg13;
5202 	__le32 reg14;
5203 	__le32 reg15;
5204 	__le32 reg16;
5205 	__le32 reg17;
5206 	__le32 reg18;
5207 	__le32 reg19;
5208 	__le16 word12;
5209 	__le16 word13;
5210 	__le16 word14;
5211 	__le16 word15;
5212 };
5213 
5214 /* The eth storm context for the Ystorm */
5215 struct ystorm_eth_conn_st_ctx {
5216 	__le32 reserved[8];
5217 };
5218 
5219 struct e4_ystorm_eth_conn_ag_ctx {
5220 	u8 byte0;
5221 	u8 state;
5222 	u8 flags0;
5223 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_MASK			0x1
5224 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT			0
5225 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_MASK			0x1
5226 #define E4_YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT			1
5227 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK	0x3
5228 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT	2
5229 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK		0x3
5230 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT	4
5231 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_MASK			0x3
5232 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT			6
5233 	u8 flags1;
5234 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK	0x1
5235 #define E4_YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT	0
5236 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK	0x1
5237 #define E4_YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT	1
5238 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK			0x1
5239 #define E4_YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT			2
5240 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK			0x1
5241 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT			3
5242 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK			0x1
5243 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT			4
5244 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK			0x1
5245 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT			5
5246 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK			0x1
5247 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT			6
5248 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK			0x1
5249 #define E4_YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT			7
5250 	u8 tx_q0_int_coallecing_timeset;
5251 	u8 byte3;
5252 	__le16 word0;
5253 	__le32 terminate_spqe;
5254 	__le32 reg1;
5255 	__le16 tx_bd_cons_upd;
5256 	__le16 word2;
5257 	__le16 word3;
5258 	__le16 word4;
5259 	__le32 reg2;
5260 	__le32 reg3;
5261 };
5262 
5263 struct e4_tstorm_eth_conn_ag_ctx {
5264 	u8 byte0;
5265 	u8 byte1;
5266 	u8 flags0;
5267 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_MASK	0x1
5268 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT	0
5269 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_MASK	0x1
5270 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT	1
5271 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_MASK	0x1
5272 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT	2
5273 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_MASK	0x1
5274 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT	3
5275 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_MASK	0x1
5276 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT	4
5277 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_MASK	0x1
5278 #define E4_TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT	5
5279 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_MASK	0x3
5280 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT	6
5281 	u8 flags1;
5282 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_MASK	0x3
5283 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT	0
5284 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_MASK	0x3
5285 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT	2
5286 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_MASK	0x3
5287 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT	4
5288 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_MASK	0x3
5289 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT	6
5290 	u8 flags2;
5291 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_MASK	0x3
5292 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT	0
5293 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_MASK	0x3
5294 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT	2
5295 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_MASK	0x3
5296 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT	4
5297 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_MASK	0x3
5298 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT	6
5299 	u8 flags3;
5300 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_MASK	0x3
5301 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT	0
5302 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_MASK	0x3
5303 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT	2
5304 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK	0x1
5305 #define E4_TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT	4
5306 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK	0x1
5307 #define E4_TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT	5
5308 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK	0x1
5309 #define E4_TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT	6
5310 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK	0x1
5311 #define E4_TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT	7
5312 	u8 flags4;
5313 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK	0x1
5314 #define E4_TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT	0
5315 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK	0x1
5316 #define E4_TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT	1
5317 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK	0x1
5318 #define E4_TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT	2
5319 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK	0x1
5320 #define E4_TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT	3
5321 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK	0x1
5322 #define E4_TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT	4
5323 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK	0x1
5324 #define E4_TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT	5
5325 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK	0x1
5326 #define E4_TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT	6
5327 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK	0x1
5328 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT	7
5329 	u8 flags5;
5330 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK		0x1
5331 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT		0
5332 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK		0x1
5333 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT		1
5334 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK		0x1
5335 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT		2
5336 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK		0x1
5337 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT		3
5338 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK		0x1
5339 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT		4
5340 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK		0x1
5341 #define E4_TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT	5
5342 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK		0x1
5343 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT		6
5344 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK		0x1
5345 #define E4_TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT		7
5346 	__le32 reg0;
5347 	__le32 reg1;
5348 	__le32 reg2;
5349 	__le32 reg3;
5350 	__le32 reg4;
5351 	__le32 reg5;
5352 	__le32 reg6;
5353 	__le32 reg7;
5354 	__le32 reg8;
5355 	u8 byte2;
5356 	u8 byte3;
5357 	__le16 rx_bd_cons;
5358 	u8 byte4;
5359 	u8 byte5;
5360 	__le16 rx_bd_prod;
5361 	__le16 word2;
5362 	__le16 word3;
5363 	__le32 reg9;
5364 	__le32 reg10;
5365 };
5366 
5367 struct e4_ustorm_eth_conn_ag_ctx {
5368 	u8 byte0;
5369 	u8 byte1;
5370 	u8 flags0;
5371 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_MASK			0x1
5372 #define E4_USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT			0
5373 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_MASK			0x1
5374 #define E4_USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT			1
5375 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK	0x3
5376 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT	2
5377 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK	0x3
5378 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT	4
5379 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_MASK			0x3
5380 #define E4_USTORM_ETH_CONN_AG_CTX_CF2_SHIFT			6
5381 	u8 flags1;
5382 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_MASK			0x3
5383 #define E4_USTORM_ETH_CONN_AG_CTX_CF3_SHIFT			0
5384 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK		0x3
5385 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT		2
5386 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK		0x3
5387 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT		4
5388 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK	0x3
5389 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT	6
5390 	u8 flags2;
5391 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK	0x1
5392 #define E4_USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT	0
5393 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK	0x1
5394 #define E4_USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT	1
5395 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_MASK			0x1
5396 #define E4_USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT			2
5397 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_MASK			0x1
5398 #define E4_USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT			3
5399 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK		0x1
5400 #define E4_USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT		4
5401 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK		0x1
5402 #define E4_USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT		5
5403 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK	0x1
5404 #define E4_USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT	6
5405 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK			0x1
5406 #define E4_USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT			7
5407 	u8 flags3;
5408 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK	0x1
5409 #define E4_USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT	0
5410 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK	0x1
5411 #define E4_USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT	1
5412 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK	0x1
5413 #define E4_USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT	2
5414 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK	0x1
5415 #define E4_USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT	3
5416 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK	0x1
5417 #define E4_USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT	4
5418 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK	0x1
5419 #define E4_USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT	5
5420 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK	0x1
5421 #define E4_USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT	6
5422 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK	0x1
5423 #define E4_USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT	7
5424 	u8 byte2;
5425 	u8 byte3;
5426 	__le16 word0;
5427 	__le16 tx_bd_cons;
5428 	__le32 reg0;
5429 	__le32 reg1;
5430 	__le32 reg2;
5431 	__le32 tx_int_coallecing_timeset;
5432 	__le16 tx_drv_bd_cons;
5433 	__le16 rx_drv_cqe_cons;
5434 };
5435 
5436 /* The eth storm context for the Ustorm */
5437 struct ustorm_eth_conn_st_ctx {
5438 	__le32 reserved[40];
5439 };
5440 
5441 /* The eth storm context for the Mstorm */
5442 struct mstorm_eth_conn_st_ctx {
5443 	__le32 reserved[8];
5444 };
5445 
5446 /* eth connection context */
5447 struct e4_eth_conn_context {
5448 	struct tstorm_eth_conn_st_ctx tstorm_st_context;
5449 	struct regpair tstorm_st_padding[2];
5450 	struct pstorm_eth_conn_st_ctx pstorm_st_context;
5451 	struct xstorm_eth_conn_st_ctx xstorm_st_context;
5452 	struct e4_xstorm_eth_conn_ag_ctx xstorm_ag_context;
5453 	struct e4_tstorm_eth_conn_ag_ctx tstorm_ag_context;
5454 	struct ystorm_eth_conn_st_ctx ystorm_st_context;
5455 	struct e4_ystorm_eth_conn_ag_ctx ystorm_ag_context;
5456 	struct e4_ustorm_eth_conn_ag_ctx ustorm_ag_context;
5457 	struct ustorm_eth_conn_st_ctx ustorm_st_context;
5458 	struct mstorm_eth_conn_st_ctx mstorm_st_context;
5459 };
5460 
5461 /* Ethernet filter types: mac/vlan/pair */
5462 enum eth_error_code {
5463 	ETH_OK = 0x00,
5464 	ETH_FILTERS_MAC_ADD_FAIL_FULL,
5465 	ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2,
5466 	ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2,
5467 	ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2,
5468 	ETH_FILTERS_MAC_DEL_FAIL_NOF,
5469 	ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2,
5470 	ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2,
5471 	ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC,
5472 	ETH_FILTERS_VLAN_ADD_FAIL_FULL,
5473 	ETH_FILTERS_VLAN_ADD_FAIL_DUP,
5474 	ETH_FILTERS_VLAN_DEL_FAIL_NOF,
5475 	ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1,
5476 	ETH_FILTERS_PAIR_ADD_FAIL_DUP,
5477 	ETH_FILTERS_PAIR_ADD_FAIL_FULL,
5478 	ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC,
5479 	ETH_FILTERS_PAIR_DEL_FAIL_NOF,
5480 	ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1,
5481 	ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC,
5482 	ETH_FILTERS_VNI_ADD_FAIL_FULL,
5483 	ETH_FILTERS_VNI_ADD_FAIL_DUP,
5484 	ETH_FILTERS_GFT_UPDATE_FAIL,
5485 	ETH_RX_QUEUE_FAIL_LOAD_VF_DATA,
5486 	ETH_FILTERS_GFS_ADD_FILTER_FAIL_MAX_HOPS,
5487 	ETH_FILTERS_GFS_ADD_FILTER_FAIL_NO_FREE_ENRTY,
5488 	ETH_FILTERS_GFS_ADD_FILTER_FAIL_ALREADY_EXISTS,
5489 	ETH_FILTERS_GFS_ADD_FILTER_FAIL_PCI_ERROR,
5490 	ETH_FILTERS_GFS_ADD_FINLER_FAIL_MAGIC_NUM_ERROR,
5491 	ETH_FILTERS_GFS_DEL_FILTER_FAIL_MAX_HOPS,
5492 	ETH_FILTERS_GFS_DEL_FILTER_FAIL_NO_MATCH_ENRTY,
5493 	ETH_FILTERS_GFS_DEL_FILTER_FAIL_PCI_ERROR,
5494 	ETH_FILTERS_GFS_DEL_FILTER_FAIL_MAGIC_NUM_ERROR,
5495 	MAX_ETH_ERROR_CODE
5496 };
5497 
5498 /* Opcodes for the event ring */
5499 enum eth_event_opcode {
5500 	ETH_EVENT_UNUSED,
5501 	ETH_EVENT_VPORT_START,
5502 	ETH_EVENT_VPORT_UPDATE,
5503 	ETH_EVENT_VPORT_STOP,
5504 	ETH_EVENT_TX_QUEUE_START,
5505 	ETH_EVENT_TX_QUEUE_STOP,
5506 	ETH_EVENT_RX_QUEUE_START,
5507 	ETH_EVENT_RX_QUEUE_UPDATE,
5508 	ETH_EVENT_RX_QUEUE_STOP,
5509 	ETH_EVENT_FILTERS_UPDATE,
5510 	ETH_EVENT_RX_ADD_OPENFLOW_FILTER,
5511 	ETH_EVENT_RX_DELETE_OPENFLOW_FILTER,
5512 	ETH_EVENT_RX_CREATE_OPENFLOW_ACTION,
5513 	ETH_EVENT_RX_ADD_UDP_FILTER,
5514 	ETH_EVENT_RX_DELETE_UDP_FILTER,
5515 	ETH_EVENT_RX_CREATE_GFT_ACTION,
5516 	ETH_EVENT_RX_GFT_UPDATE_FILTER,
5517 	ETH_EVENT_TX_QUEUE_UPDATE,
5518 	ETH_EVENT_RGFS_ADD_FILTER,
5519 	ETH_EVENT_RGFS_DEL_FILTER,
5520 	ETH_EVENT_TGFS_ADD_FILTER,
5521 	ETH_EVENT_TGFS_DEL_FILTER,
5522 	ETH_EVENT_GFS_COUNTERS_REPORT_REQUEST,
5523 	MAX_ETH_EVENT_OPCODE
5524 };
5525 
5526 /* Classify rule types in E2/E3 */
5527 enum eth_filter_action {
5528 	ETH_FILTER_ACTION_UNUSED,
5529 	ETH_FILTER_ACTION_REMOVE,
5530 	ETH_FILTER_ACTION_ADD,
5531 	ETH_FILTER_ACTION_REMOVE_ALL,
5532 	MAX_ETH_FILTER_ACTION
5533 };
5534 
5535 /* Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$ */
5536 struct eth_filter_cmd {
5537 	u8 type;
5538 	u8 vport_id;
5539 	u8 action;
5540 	u8 reserved0;
5541 	__le32 vni;
5542 	__le16 mac_lsb;
5543 	__le16 mac_mid;
5544 	__le16 mac_msb;
5545 	__le16 vlan_id;
5546 };
5547 
5548 /*	$$KEEP_ENDIANNESS$$ */
5549 struct eth_filter_cmd_header {
5550 	u8 rx;
5551 	u8 tx;
5552 	u8 cmd_cnt;
5553 	u8 assert_on_error;
5554 	u8 reserved1[4];
5555 };
5556 
5557 /* Ethernet filter types: mac/vlan/pair */
5558 enum eth_filter_type {
5559 	ETH_FILTER_TYPE_UNUSED,
5560 	ETH_FILTER_TYPE_MAC,
5561 	ETH_FILTER_TYPE_VLAN,
5562 	ETH_FILTER_TYPE_PAIR,
5563 	ETH_FILTER_TYPE_INNER_MAC,
5564 	ETH_FILTER_TYPE_INNER_VLAN,
5565 	ETH_FILTER_TYPE_INNER_PAIR,
5566 	ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR,
5567 	ETH_FILTER_TYPE_MAC_VNI_PAIR,
5568 	ETH_FILTER_TYPE_VNI,
5569 	MAX_ETH_FILTER_TYPE
5570 };
5571 
5572 /* inner to inner vlan priority translation configurations */
5573 struct eth_in_to_in_pri_map_cfg {
5574 	u8 inner_vlan_pri_remap_en;
5575 	u8 reserved[7];
5576 	u8 non_rdma_in_to_in_pri_map[8];
5577 	u8 rdma_in_to_in_pri_map[8];
5578 };
5579 
5580 /* Eth IPv4 Fragment Type */
5581 enum eth_ipv4_frag_type {
5582 	ETH_IPV4_NOT_FRAG,
5583 	ETH_IPV4_FIRST_FRAG,
5584 	ETH_IPV4_NON_FIRST_FRAG,
5585 	MAX_ETH_IPV4_FRAG_TYPE
5586 };
5587 
5588 /* eth IPv4 Fragment Type */
5589 enum eth_ip_type {
5590 	ETH_IPV4,
5591 	ETH_IPV6,
5592 	MAX_ETH_IP_TYPE
5593 };
5594 
5595 /* Ethernet Ramrod Command IDs */
5596 enum eth_ramrod_cmd_id {
5597 	ETH_RAMROD_UNUSED,
5598 	ETH_RAMROD_VPORT_START,
5599 	ETH_RAMROD_VPORT_UPDATE,
5600 	ETH_RAMROD_VPORT_STOP,
5601 	ETH_RAMROD_RX_QUEUE_START,
5602 	ETH_RAMROD_RX_QUEUE_STOP,
5603 	ETH_RAMROD_TX_QUEUE_START,
5604 	ETH_RAMROD_TX_QUEUE_STOP,
5605 	ETH_RAMROD_FILTERS_UPDATE,
5606 	ETH_RAMROD_RX_QUEUE_UPDATE,
5607 	ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION,
5608 	ETH_RAMROD_RX_ADD_OPENFLOW_FILTER,
5609 	ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER,
5610 	ETH_RAMROD_RX_ADD_UDP_FILTER,
5611 	ETH_RAMROD_RX_DELETE_UDP_FILTER,
5612 	ETH_RAMROD_RX_CREATE_GFT_ACTION,
5613 	ETH_RAMROD_GFT_UPDATE_FILTER,
5614 	ETH_RAMROD_TX_QUEUE_UPDATE,
5615 	ETH_RAMROD_RGFS_FILTER_ADD,
5616 	ETH_RAMROD_RGFS_FILTER_DEL,
5617 	ETH_RAMROD_TGFS_FILTER_ADD,
5618 	ETH_RAMROD_TGFS_FILTER_DEL,
5619 	ETH_RAMROD_GFS_COUNTERS_REPORT_REQUEST,
5620 	MAX_ETH_RAMROD_CMD_ID
5621 };
5622 
5623 /* Return code from eth sp ramrods */
5624 struct eth_return_code {
5625 	u8 value;
5626 #define ETH_RETURN_CODE_ERR_CODE_MASK  0x3F
5627 #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0
5628 #define ETH_RETURN_CODE_RESERVED_MASK  0x1
5629 #define ETH_RETURN_CODE_RESERVED_SHIFT 6
5630 #define ETH_RETURN_CODE_RX_TX_MASK     0x1
5631 #define ETH_RETURN_CODE_RX_TX_SHIFT    7
5632 };
5633 
5634 /* tx destination enum */
5635 enum eth_tx_dst_mode_config_enum {
5636 	ETH_TX_DST_MODE_CONFIG_DISABLE,
5637 	ETH_TX_DST_MODE_CONFIG_FORWARD_DATA_IN_BD,
5638 	ETH_TX_DST_MODE_CONFIG_FORWARD_DATA_IN_VPORT,
5639 	MAX_ETH_TX_DST_MODE_CONFIG_ENUM
5640 };
5641 
5642 /* What to do in case an error occurs */
5643 enum eth_tx_err {
5644 	ETH_TX_ERR_DROP,
5645 	ETH_TX_ERR_ASSERT_MALICIOUS,
5646 	MAX_ETH_TX_ERR
5647 };
5648 
5649 /* Array of the different error type behaviors */
5650 struct eth_tx_err_vals {
5651 	__le16 values;
5652 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK			0x1
5653 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT			0
5654 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK			0x1
5655 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT			1
5656 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK			0x1
5657 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT			2
5658 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK		0x1
5659 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT		3
5660 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK	0x1
5661 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT	4
5662 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK			0x1
5663 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT			5
5664 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK		0x1
5665 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT		6
5666 #define ETH_TX_ERR_VALS_ILLEGAL_BD_FLAGS_MASK			0x1
5667 #define ETH_TX_ERR_VALS_ILLEGAL_BD_FLAGS_SHIFT			7
5668 #define ETH_TX_ERR_VALS_RESERVED_MASK				0xFF
5669 #define ETH_TX_ERR_VALS_RESERVED_SHIFT				8
5670 };
5671 
5672 /* vport rss configuration data */
5673 struct eth_vport_rss_config {
5674 	__le16 capabilities;
5675 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK		0x1
5676 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT		0
5677 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK		0x1
5678 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT		1
5679 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK		0x1
5680 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT		2
5681 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK		0x1
5682 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT		3
5683 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK		0x1
5684 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT		4
5685 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK		0x1
5686 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT		5
5687 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK		0x1
5688 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT	6
5689 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK			0x1FF
5690 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT			7
5691 	u8 rss_id;
5692 	u8 rss_mode;
5693 	u8 update_rss_key;
5694 	u8 update_rss_ind_table;
5695 	u8 update_rss_capabilities;
5696 	u8 tbl_size;
5697 	__le32 reserved2[2];
5698 	__le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM];
5699 	__le32 rss_key[ETH_RSS_KEY_SIZE_REGS];
5700 	__le32 reserved3[2];
5701 };
5702 
5703 /* eth vport RSS mode */
5704 enum eth_vport_rss_mode {
5705 	ETH_VPORT_RSS_MODE_DISABLED,
5706 	ETH_VPORT_RSS_MODE_REGULAR,
5707 	MAX_ETH_VPORT_RSS_MODE
5708 };
5709 
5710 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
5711 struct eth_vport_rx_mode {
5712 	__le16 state;
5713 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK		0x1
5714 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT		0
5715 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK		0x1
5716 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT	1
5717 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK	0x1
5718 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT	2
5719 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK		0x1
5720 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT		3
5721 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK		0x1
5722 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT	4
5723 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK		0x1
5724 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT	5
5725 #define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_MASK		0x1
5726 #define ETH_VPORT_RX_MODE_ACCEPT_ANY_VNI_SHIFT		6
5727 #define ETH_VPORT_RX_MODE_RESERVED1_MASK		0x1FF
5728 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT		7
5729 };
5730 
5731 /* Command for setting tpa parameters */
5732 struct eth_vport_tpa_param {
5733 	u8 tpa_ipv4_en_flg;
5734 	u8 tpa_ipv6_en_flg;
5735 	u8 tpa_ipv4_tunn_en_flg;
5736 	u8 tpa_ipv6_tunn_en_flg;
5737 	u8 tpa_pkt_split_flg;
5738 	u8 tpa_hdr_data_split_flg;
5739 	u8 tpa_gro_consistent_flg;
5740 
5741 	u8 tpa_max_aggs_num;
5742 
5743 	__le16 tpa_max_size;
5744 	__le16 tpa_min_size_to_start;
5745 
5746 	__le16 tpa_min_size_to_cont;
5747 	u8 max_buff_num;
5748 	u8 reserved;
5749 };
5750 
5751 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */
5752 struct eth_vport_tx_mode {
5753 	__le16 state;
5754 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK		0x1
5755 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT		0
5756 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK		0x1
5757 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT	1
5758 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK		0x1
5759 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT		2
5760 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK		0x1
5761 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT	3
5762 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK		0x1
5763 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT	4
5764 #define ETH_VPORT_TX_MODE_RESERVED1_MASK		0x7FF
5765 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT		5
5766 };
5767 
5768 /* GFT filter update action type */
5769 enum gft_filter_update_action {
5770 	GFT_ADD_FILTER,
5771 	GFT_DELETE_FILTER,
5772 	MAX_GFT_FILTER_UPDATE_ACTION
5773 };
5774 
5775 /* Ramrod data for rx add openflow filter */
5776 struct rx_add_openflow_filter_data {
5777 	__le16 action_icid;
5778 	u8 priority;
5779 	u8 reserved0;
5780 	__le32 tenant_id;
5781 	__le16 dst_mac_hi;
5782 	__le16 dst_mac_mid;
5783 	__le16 dst_mac_lo;
5784 	__le16 src_mac_hi;
5785 	__le16 src_mac_mid;
5786 	__le16 src_mac_lo;
5787 	__le16 vlan_id;
5788 	__le16 l2_eth_type;
5789 	u8 ipv4_dscp;
5790 	u8 ipv4_frag_type;
5791 	u8 ipv4_over_ip;
5792 	u8 tenant_id_exists;
5793 	__le32 ipv4_dst_addr;
5794 	__le32 ipv4_src_addr;
5795 	__le16 l4_dst_port;
5796 	__le16 l4_src_port;
5797 };
5798 
5799 /* Ramrod data for rx create gft action */
5800 struct rx_create_gft_action_data {
5801 	u8 vport_id;
5802 	u8 reserved[7];
5803 };
5804 
5805 /* Ramrod data for rx create openflow action */
5806 struct rx_create_openflow_action_data {
5807 	u8 vport_id;
5808 	u8 reserved[7];
5809 };
5810 
5811 /* Ramrod data for rx queue start ramrod */
5812 struct rx_queue_start_ramrod_data {
5813 	__le16 rx_queue_id;
5814 	__le16 num_of_pbl_pages;
5815 	__le16 bd_max_bytes;
5816 	__le16 sb_id;
5817 	u8 sb_index;
5818 	u8 vport_id;
5819 	u8 default_rss_queue_flg;
5820 	u8 complete_cqe_flg;
5821 	u8 complete_event_flg;
5822 	u8 stats_counter_id;
5823 	u8 pin_context;
5824 	u8 pxp_tph_valid_bd;
5825 	u8 pxp_tph_valid_pkt;
5826 	u8 pxp_st_hint;
5827 
5828 	__le16 pxp_st_index;
5829 	u8 pmd_mode;
5830 
5831 	u8 notify_en;
5832 	u8 toggle_val;
5833 
5834 	u8 vf_rx_prod_index;
5835 	u8 vf_rx_prod_use_zone_a;
5836 	u8 reserved[5];
5837 	__le16 reserved1;
5838 	struct regpair cqe_pbl_addr;
5839 	struct regpair bd_base;
5840 	struct regpair reserved2;
5841 };
5842 
5843 /* Ramrod data for rx queue stop ramrod */
5844 struct rx_queue_stop_ramrod_data {
5845 	__le16 rx_queue_id;
5846 	u8 complete_cqe_flg;
5847 	u8 complete_event_flg;
5848 	u8 vport_id;
5849 	u8 reserved[3];
5850 };
5851 
5852 /* Ramrod data for rx queue update ramrod */
5853 struct rx_queue_update_ramrod_data {
5854 	__le16 rx_queue_id;
5855 	u8 complete_cqe_flg;
5856 	u8 complete_event_flg;
5857 	u8 vport_id;
5858 	u8 set_default_rss_queue;
5859 	u8 reserved[3];
5860 	u8 reserved1;
5861 	u8 reserved2;
5862 	u8 reserved3;
5863 	__le16 reserved4;
5864 	__le16 reserved5;
5865 	struct regpair reserved6;
5866 };
5867 
5868 /* Ramrod data for rx Add UDP Filter */
5869 struct rx_udp_filter_data {
5870 	__le16 action_icid;
5871 	__le16 vlan_id;
5872 	u8 ip_type;
5873 	u8 tenant_id_exists;
5874 	__le16 reserved1;
5875 	__le32 ip_dst_addr[4];
5876 	__le32 ip_src_addr[4];
5877 	__le16 udp_dst_port;
5878 	__le16 udp_src_port;
5879 	__le32 tenant_id;
5880 };
5881 
5882 /* Add or delete GFT filter - filter is packet header of type of packet wished
5883  * to pass certain FW flow.
5884  */
5885 struct rx_update_gft_filter_data {
5886 	struct regpair pkt_hdr_addr;
5887 	__le16 pkt_hdr_length;
5888 	__le16 action_icid;
5889 	__le16 rx_qid;
5890 	__le16 flow_id;
5891 	__le16 vport_id;
5892 	u8 action_icid_valid;
5893 	u8 rx_qid_valid;
5894 	u8 flow_id_valid;
5895 	u8 filter_action;
5896 	u8 assert_on_error;
5897 	u8 inner_vlan_removal_en;
5898 };
5899 
5900 /* Ramrod data for tx queue start ramrod */
5901 struct tx_queue_start_ramrod_data {
5902 	__le16 sb_id;
5903 	u8 sb_index;
5904 	u8 vport_id;
5905 	u8 reserved0;
5906 	u8 stats_counter_id;
5907 	__le16 qm_pq_id;
5908 	u8 flags;
5909 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK	0x1
5910 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT	0
5911 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK	0x1
5912 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT	1
5913 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK		0x1
5914 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT		2
5915 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK		0x1
5916 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT		3
5917 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK		0x1
5918 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT		4
5919 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK		0x7
5920 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT		5
5921 	u8 pxp_st_hint;
5922 	u8 pxp_tph_valid_bd;
5923 	u8 pxp_tph_valid_pkt;
5924 	__le16 pxp_st_index;
5925 	__le16 comp_agg_size;
5926 	__le16 queue_zone_id;
5927 	__le16 reserved2;
5928 	__le16 pbl_size;
5929 	__le16 tx_queue_id;
5930 	__le16 same_as_last_id;
5931 	__le16 reserved[3];
5932 	struct regpair pbl_base_addr;
5933 	struct regpair bd_cons_address;
5934 };
5935 
5936 /* Ramrod data for tx queue stop ramrod */
5937 struct tx_queue_stop_ramrod_data {
5938 	__le16 reserved[4];
5939 };
5940 
5941 /* Ramrod data for tx queue update ramrod */
5942 struct tx_queue_update_ramrod_data {
5943 	__le16 update_qm_pq_id_flg;
5944 	__le16 qm_pq_id;
5945 	__le32 reserved0;
5946 	struct regpair reserved1[5];
5947 };
5948 
5949 /* Inner to Inner VLAN priority map update mode */
5950 enum update_in_to_in_pri_map_mode_enum {
5951 	ETH_IN_TO_IN_PRI_MAP_UPDATE_DISABLED,
5952 	ETH_IN_TO_IN_PRI_MAP_UPDATE_NON_RDMA_TBL,
5953 	ETH_IN_TO_IN_PRI_MAP_UPDATE_RDMA_TBL,
5954 	MAX_UPDATE_IN_TO_IN_PRI_MAP_MODE_ENUM
5955 };
5956 
5957 /* Ramrod data for vport update ramrod */
5958 struct vport_filter_update_ramrod_data {
5959 	struct eth_filter_cmd_header filter_cmd_hdr;
5960 	struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT];
5961 };
5962 
5963 /* Ramrod data for vport start ramrod */
5964 struct vport_start_ramrod_data {
5965 	u8 vport_id;
5966 	u8 sw_fid;
5967 	__le16 mtu;
5968 	u8 drop_ttl0_en;
5969 	u8 inner_vlan_removal_en;
5970 	struct eth_vport_rx_mode rx_mode;
5971 	struct eth_vport_tx_mode tx_mode;
5972 	struct eth_vport_tpa_param tpa_param;
5973 	__le16 default_vlan;
5974 	u8 tx_switching_en;
5975 	u8 anti_spoofing_en;
5976 	u8 default_vlan_en;
5977 	u8 handle_ptp_pkts;
5978 	u8 silent_vlan_removal_en;
5979 	u8 untagged;
5980 	struct eth_tx_err_vals tx_err_behav;
5981 	u8 zero_placement_offset;
5982 	u8 ctl_frame_mac_check_en;
5983 	u8 ctl_frame_ethtype_check_en;
5984 	u8 reserved0;
5985 	u8 reserved1;
5986 	u8 tx_dst_port_mode_config;
5987 	u8 dst_vport_id;
5988 	u8 tx_dst_port_mode;
5989 	u8 dst_vport_id_valid;
5990 	u8 wipe_inner_vlan_pri_en;
5991 	u8 reserved2[2];
5992 	struct eth_in_to_in_pri_map_cfg in_to_in_vlan_pri_map_cfg;
5993 };
5994 
5995 /* Ramrod data for vport stop ramrod */
5996 struct vport_stop_ramrod_data {
5997 	u8 vport_id;
5998 	u8 reserved[7];
5999 };
6000 
6001 /* Ramrod data for vport update ramrod */
6002 struct vport_update_ramrod_data_cmn {
6003 	u8 vport_id;
6004 	u8 update_rx_active_flg;
6005 	u8 rx_active_flg;
6006 	u8 update_tx_active_flg;
6007 	u8 tx_active_flg;
6008 	u8 update_rx_mode_flg;
6009 	u8 update_tx_mode_flg;
6010 	u8 update_approx_mcast_flg;
6011 
6012 	u8 update_rss_flg;
6013 	u8 update_inner_vlan_removal_en_flg;
6014 
6015 	u8 inner_vlan_removal_en;
6016 	u8 update_tpa_param_flg;
6017 	u8 update_tpa_en_flg;
6018 	u8 update_tx_switching_en_flg;
6019 
6020 	u8 tx_switching_en;
6021 	u8 update_anti_spoofing_en_flg;
6022 
6023 	u8 anti_spoofing_en;
6024 	u8 update_handle_ptp_pkts;
6025 
6026 	u8 handle_ptp_pkts;
6027 	u8 update_default_vlan_en_flg;
6028 
6029 	u8 default_vlan_en;
6030 
6031 	u8 update_default_vlan_flg;
6032 
6033 	__le16 default_vlan;
6034 	u8 update_accept_any_vlan_flg;
6035 
6036 	u8 accept_any_vlan;
6037 	u8 silent_vlan_removal_en;
6038 	u8 update_mtu_flg;
6039 
6040 	__le16 mtu;
6041 	u8 update_ctl_frame_checks_en_flg;
6042 	u8 ctl_frame_mac_check_en;
6043 	u8 ctl_frame_ethtype_check_en;
6044 	u8 update_in_to_in_pri_map_mode;
6045 	u8 in_to_in_pri_map[8];
6046 	u8 reserved[6];
6047 };
6048 
6049 struct vport_update_ramrod_mcast {
6050 	__le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS];
6051 };
6052 
6053 /* Ramrod data for vport update ramrod */
6054 struct vport_update_ramrod_data {
6055 	struct vport_update_ramrod_data_cmn common;
6056 
6057 	struct eth_vport_rx_mode rx_mode;
6058 	struct eth_vport_tx_mode tx_mode;
6059 	__le32 reserved[3];
6060 	struct eth_vport_tpa_param tpa_param;
6061 	struct vport_update_ramrod_mcast approx_mcast;
6062 	struct eth_vport_rss_config rss_config;
6063 };
6064 
6065 struct e4_xstorm_eth_conn_ag_ctx_dq_ext_ldpart {
6066 	u8 reserved0;
6067 	u8 state;
6068 	u8 flags0;
6069 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK	0x1
6070 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT	0
6071 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK		0x1
6072 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT		1
6073 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK		0x1
6074 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT		2
6075 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK	0x1
6076 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT	3
6077 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK		0x1
6078 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT		4
6079 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK		0x1
6080 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT		5
6081 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK		0x1
6082 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT		6
6083 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK		0x1
6084 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT		7
6085 	u8 flags1;
6086 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK		0x1
6087 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT		0
6088 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK		0x1
6089 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT		1
6090 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK		0x1
6091 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT		2
6092 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK		0x1
6093 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT		3
6094 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_MASK	0x1
6095 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED2_SHIFT	4
6096 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_MASK	0x1
6097 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_E5_RESERVED3_SHIFT	5
6098 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK	0x1
6099 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT	6
6100 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK	0x1
6101 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT	7
6102 	u8 flags2;
6103 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK	0x3
6104 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT	0
6105 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK	0x3
6106 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT	2
6107 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK	0x3
6108 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT	4
6109 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK	0x3
6110 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT	6
6111 	u8 flags3;
6112 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK	0x3
6113 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT	0
6114 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK	0x3
6115 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT	2
6116 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK	0x3
6117 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT	4
6118 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK	0x3
6119 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT	6
6120 	u8 flags4;
6121 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK	0x3
6122 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT	0
6123 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK	0x3
6124 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT	2
6125 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK	0x3
6126 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT	4
6127 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK	0x3
6128 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT	6
6129 	u8 flags5;
6130 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK	0x3
6131 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT	0
6132 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK	0x3
6133 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT	2
6134 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK	0x3
6135 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT	4
6136 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK	0x3
6137 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT	6
6138 	u8 flags6;
6139 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK	0x3
6140 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT	0
6141 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK	0x3
6142 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT	2
6143 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK		0x3
6144 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT		4
6145 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK	0x3
6146 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT	6
6147 	u8 flags7;
6148 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK		0x3
6149 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT		0
6150 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK		0x3
6151 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT	2
6152 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK		0x3
6153 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT		4
6154 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK		0x1
6155 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT		6
6156 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK		0x1
6157 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT		7
6158 	u8 flags8;
6159 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK	0x1
6160 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT	0
6161 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK	0x1
6162 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT	1
6163 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK	0x1
6164 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT	2
6165 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK	0x1
6166 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT	3
6167 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK	0x1
6168 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT	4
6169 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK	0x1
6170 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT	5
6171 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK	0x1
6172 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT	6
6173 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK	0x1
6174 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT	7
6175 	u8 flags9;
6176 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK			0x1
6177 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT			0
6178 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK			0x1
6179 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT			1
6180 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK			0x1
6181 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT			2
6182 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK			0x1
6183 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT			3
6184 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK			0x1
6185 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT			4
6186 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK			0x1
6187 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT			5
6188 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK	0x1
6189 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT	6
6190 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK	0x1
6191 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT	7
6192 	u8 flags10;
6193 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK			0x1
6194 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT			0
6195 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK		0x1
6196 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT		1
6197 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK		0x1
6198 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT		2
6199 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK			0x1
6200 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT		3
6201 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK		0x1
6202 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT		4
6203 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK	0x1
6204 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT	5
6205 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK			0x1
6206 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT		6
6207 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK			0x1
6208 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT		7
6209 	u8 flags11;
6210 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK		0x1
6211 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT	0
6212 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK		0x1
6213 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT	1
6214 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK	0x1
6215 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT	2
6216 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK		0x1
6217 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT		3
6218 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK		0x1
6219 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT		4
6220 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK		0x1
6221 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT		5
6222 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK	0x1
6223 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT	6
6224 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK		0x1
6225 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT		7
6226 	u8 flags12;
6227 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK		0x1
6228 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT		0
6229 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK		0x1
6230 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT		1
6231 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK	0x1
6232 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT	2
6233 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK	0x1
6234 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT	3
6235 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK		0x1
6236 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT		4
6237 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK		0x1
6238 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT		5
6239 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK		0x1
6240 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT		6
6241 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK		0x1
6242 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT		7
6243 	u8 flags13;
6244 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK		0x1
6245 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT		0
6246 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK		0x1
6247 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT		1
6248 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK	0x1
6249 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT	2
6250 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK	0x1
6251 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT	3
6252 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK	0x1
6253 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT	4
6254 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK	0x1
6255 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT	5
6256 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK	0x1
6257 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT	6
6258 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK	0x1
6259 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT	7
6260 	u8 flags14;
6261 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK		0x1
6262 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT		0
6263 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK		0x1
6264 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT	1
6265 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK	0x1
6266 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT	2
6267 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK	0x1
6268 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT	3
6269 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK		0x1
6270 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT		4
6271 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK		0x1
6272 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT		5
6273 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK			0x3
6274 #define E4XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT		6
6275 	u8 edpm_event_id;
6276 	__le16 physical_q0;
6277 	__le16 e5_reserved1;
6278 	__le16 edpm_num_bds;
6279 	__le16 tx_bd_cons;
6280 	__le16 tx_bd_prod;
6281 	__le16 updated_qm_pq_id;
6282 	__le16 conn_dpi;
6283 	u8 byte3;
6284 	u8 byte4;
6285 	u8 byte5;
6286 	u8 byte6;
6287 	__le32 reg0;
6288 	__le32 reg1;
6289 	__le32 reg2;
6290 	__le32 reg3;
6291 	__le32 reg4;
6292 };
6293 
6294 struct e4_mstorm_eth_conn_ag_ctx {
6295 	u8 byte0;
6296 	u8 byte1;
6297 	u8 flags0;
6298 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
6299 #define E4_MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	 0
6300 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_MASK		0x1
6301 #define E4_MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT		1
6302 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_MASK		0x3
6303 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT		2
6304 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_MASK		0x3
6305 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT		4
6306 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_MASK		0x3
6307 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT		6
6308 	u8 flags1;
6309 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK	0x1
6310 #define E4_MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT	0
6311 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK	0x1
6312 #define E4_MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT	1
6313 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK	0x1
6314 #define E4_MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT	2
6315 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK	0x1
6316 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT	3
6317 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK	0x1
6318 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT	4
6319 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK	0x1
6320 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT	5
6321 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK	0x1
6322 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT	6
6323 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK	0x1
6324 #define E4_MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT	7
6325 	__le16 word0;
6326 	__le16 word1;
6327 	__le32 reg0;
6328 	__le32 reg1;
6329 };
6330 
6331 struct e4_xstorm_eth_hw_conn_ag_ctx {
6332 	u8 reserved0;
6333 	u8 state;
6334 	u8 flags0;
6335 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
6336 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
6337 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK	0x1
6338 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT	1
6339 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK	0x1
6340 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT	2
6341 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
6342 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT	3
6343 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK	0x1
6344 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT	4
6345 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK	0x1
6346 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT	5
6347 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK	0x1
6348 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT	6
6349 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK	0x1
6350 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT	7
6351 	u8 flags1;
6352 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK		0x1
6353 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT		0
6354 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK		0x1
6355 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT		1
6356 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK		0x1
6357 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT		2
6358 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK			0x1
6359 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT		3
6360 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_MASK		0x1
6361 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED2_SHIFT		4
6362 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_MASK		0x1
6363 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_E5_RESERVED3_SHIFT		5
6364 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK	0x1
6365 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT	6
6366 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK		0x1
6367 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT		7
6368 	u8 flags2;
6369 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK	0x3
6370 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT	0
6371 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK	0x3
6372 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT	2
6373 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK	0x3
6374 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT	4
6375 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK	0x3
6376 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT	6
6377 	u8 flags3;
6378 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK	0x3
6379 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT	0
6380 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK	0x3
6381 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT	2
6382 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK	0x3
6383 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT	4
6384 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK	0x3
6385 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT	6
6386 	u8 flags4;
6387 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK	0x3
6388 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT	0
6389 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK	0x3
6390 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT	2
6391 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK	0x3
6392 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT	4
6393 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK	0x3
6394 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT	6
6395 	u8 flags5;
6396 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK	0x3
6397 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT	0
6398 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK	0x3
6399 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT	2
6400 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK	0x3
6401 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT	4
6402 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK	0x3
6403 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT	6
6404 	u8 flags6;
6405 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK	0x3
6406 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT	0
6407 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK	0x3
6408 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT	2
6409 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK			0x3
6410 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT		4
6411 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK		0x3
6412 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT		6
6413 	u8 flags7;
6414 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK	0x3
6415 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT	0
6416 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK	0x3
6417 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT	2
6418 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK	0x3
6419 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT	4
6420 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK		0x1
6421 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT	6
6422 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK		0x1
6423 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT	7
6424 	u8 flags8;
6425 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK		0x1
6426 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT	0
6427 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK		0x1
6428 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT	1
6429 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK		0x1
6430 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT	2
6431 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK		0x1
6432 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT	3
6433 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK		0x1
6434 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT	4
6435 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK		0x1
6436 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT	5
6437 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK		0x1
6438 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT	6
6439 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK		0x1
6440 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT	7
6441 	u8 flags9;
6442 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK		0x1
6443 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT		0
6444 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK		0x1
6445 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT		1
6446 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK		0x1
6447 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT		2
6448 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK		0x1
6449 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT		3
6450 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK		0x1
6451 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT		4
6452 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK		0x1
6453 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT		5
6454 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK	0x1
6455 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT	6
6456 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK	0x1
6457 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT	7
6458 	u8 flags10;
6459 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK			0x1
6460 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT			0
6461 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK		0x1
6462 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT		1
6463 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK			0x1
6464 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT			2
6465 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK			0x1
6466 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT			3
6467 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK			0x1
6468 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT			4
6469 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK	0x1
6470 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT	5
6471 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK			0x1
6472 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT			6
6473 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK			0x1
6474 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT			7
6475 	u8 flags11;
6476 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK		0x1
6477 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT		0
6478 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK		0x1
6479 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT		1
6480 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK	0x1
6481 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT	2
6482 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK		0x1
6483 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT		3
6484 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK		0x1
6485 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT		4
6486 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK		0x1
6487 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT		5
6488 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK		0x1
6489 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT		6
6490 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK		0x1
6491 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT		7
6492 	u8 flags12;
6493 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK	0x1
6494 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT	0
6495 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK	0x1
6496 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT	1
6497 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK	0x1
6498 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT	2
6499 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK	0x1
6500 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT	3
6501 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK	0x1
6502 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT	4
6503 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK	0x1
6504 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT	5
6505 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK	0x1
6506 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT	6
6507 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK	0x1
6508 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT	7
6509 	u8 flags13;
6510 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK	0x1
6511 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT	0
6512 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK	0x1
6513 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT	1
6514 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK	0x1
6515 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT	2
6516 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK	0x1
6517 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT	3
6518 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK	0x1
6519 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT	4
6520 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK	0x1
6521 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT	5
6522 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK	0x1
6523 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT	6
6524 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK	0x1
6525 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT	7
6526 	u8 flags14;
6527 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK	0x1
6528 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT	0
6529 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK	0x1
6530 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT	1
6531 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK	0x1
6532 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT	2
6533 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK	0x1
6534 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT	3
6535 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK	0x1
6536 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT	4
6537 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK	0x1
6538 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT	5
6539 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK		0x3
6540 #define E4_XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT		6
6541 	u8 edpm_event_id;
6542 	__le16 physical_q0;
6543 	__le16 e5_reserved1;
6544 	__le16 edpm_num_bds;
6545 	__le16 tx_bd_cons;
6546 	__le16 tx_bd_prod;
6547 	__le16 updated_qm_pq_id;
6548 	__le16 conn_dpi;
6549 };
6550 
6551 /* GFT CAM line struct with fields breakout */
6552 struct gft_cam_line_mapped {
6553 	__le32 camline;
6554 #define GFT_CAM_LINE_MAPPED_VALID_MASK				0x1
6555 #define GFT_CAM_LINE_MAPPED_VALID_SHIFT				0
6556 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK			0x1
6557 #define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT			1
6558 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK		0x1
6559 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT		2
6560 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK		0xF
6561 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT		3
6562 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK			0xF
6563 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT			7
6564 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK				0xF
6565 #define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT				11
6566 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK		0x1
6567 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT		15
6568 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK		0x1
6569 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT	16
6570 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK	0xF
6571 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT	17
6572 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK		0xF
6573 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT		21
6574 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK			0xF
6575 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT			25
6576 #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK			0x7
6577 #define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT			29
6578 };
6579 
6580 
6581 /* Used in gft_profile_key: Indication for ip version */
6582 enum gft_profile_ip_version {
6583 	GFT_PROFILE_IPV4 = 0,
6584 	GFT_PROFILE_IPV6 = 1,
6585 	MAX_GFT_PROFILE_IP_VERSION
6586 };
6587 
6588 /* Profile key stucr fot GFT logic in Prs */
6589 struct gft_profile_key {
6590 	__le16 profile_key;
6591 #define GFT_PROFILE_KEY_IP_VERSION_MASK			0x1
6592 #define GFT_PROFILE_KEY_IP_VERSION_SHIFT		0
6593 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK		0x1
6594 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT		1
6595 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK	0xF
6596 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT	2
6597 #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK		0xF
6598 #define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT		6
6599 #define GFT_PROFILE_KEY_PF_ID_MASK			0xF
6600 #define GFT_PROFILE_KEY_PF_ID_SHIFT			10
6601 #define GFT_PROFILE_KEY_RESERVED0_MASK			0x3
6602 #define GFT_PROFILE_KEY_RESERVED0_SHIFT			14
6603 };
6604 
6605 /* Used in gft_profile_key: Indication for tunnel type */
6606 enum gft_profile_tunnel_type {
6607 	GFT_PROFILE_NO_TUNNEL = 0,
6608 	GFT_PROFILE_VXLAN_TUNNEL = 1,
6609 	GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL = 2,
6610 	GFT_PROFILE_GRE_IP_TUNNEL = 3,
6611 	GFT_PROFILE_GENEVE_MAC_TUNNEL = 4,
6612 	GFT_PROFILE_GENEVE_IP_TUNNEL = 5,
6613 	MAX_GFT_PROFILE_TUNNEL_TYPE
6614 };
6615 
6616 /* Used in gft_profile_key: Indication for protocol type */
6617 enum gft_profile_upper_protocol_type {
6618 	GFT_PROFILE_ROCE_PROTOCOL = 0,
6619 	GFT_PROFILE_RROCE_PROTOCOL = 1,
6620 	GFT_PROFILE_FCOE_PROTOCOL = 2,
6621 	GFT_PROFILE_ICMP_PROTOCOL = 3,
6622 	GFT_PROFILE_ARP_PROTOCOL = 4,
6623 	GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER = 5,
6624 	GFT_PROFILE_USER_TCP_DST_PORT_1_INNER = 6,
6625 	GFT_PROFILE_TCP_PROTOCOL = 7,
6626 	GFT_PROFILE_USER_UDP_DST_PORT_1_INNER = 8,
6627 	GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER = 9,
6628 	GFT_PROFILE_UDP_PROTOCOL = 10,
6629 	GFT_PROFILE_USER_IP_1_INNER = 11,
6630 	GFT_PROFILE_USER_IP_2_OUTER = 12,
6631 	GFT_PROFILE_USER_ETH_1_INNER = 13,
6632 	GFT_PROFILE_USER_ETH_2_OUTER = 14,
6633 	GFT_PROFILE_RAW = 15,
6634 	MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE
6635 };
6636 
6637 /* GFT RAM line struct */
6638 struct gft_ram_line {
6639 	__le32 lo;
6640 #define GFT_RAM_LINE_VLAN_SELECT_MASK			0x3
6641 #define GFT_RAM_LINE_VLAN_SELECT_SHIFT			0
6642 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK		0x1
6643 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT		2
6644 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK		0x1
6645 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT		3
6646 #define GFT_RAM_LINE_TUNNEL_TTL_MASK			0x1
6647 #define GFT_RAM_LINE_TUNNEL_TTL_SHIFT			4
6648 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK		0x1
6649 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT		5
6650 #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK		0x1
6651 #define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT		6
6652 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK		0x1
6653 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT		7
6654 #define GFT_RAM_LINE_TUNNEL_DSCP_MASK			0x1
6655 #define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT			8
6656 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK	0x1
6657 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT	9
6658 #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK			0x1
6659 #define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT		10
6660 #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK			0x1
6661 #define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT		11
6662 #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK		0x1
6663 #define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT		12
6664 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK		0x1
6665 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT		13
6666 #define GFT_RAM_LINE_TUNNEL_VLAN_MASK			0x1
6667 #define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT			14
6668 #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK		0x1
6669 #define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT		15
6670 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK		0x1
6671 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT		16
6672 #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK			0x1
6673 #define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT		17
6674 #define GFT_RAM_LINE_TTL_MASK				0x1
6675 #define GFT_RAM_LINE_TTL_SHIFT				18
6676 #define GFT_RAM_LINE_ETHERTYPE_MASK			0x1
6677 #define GFT_RAM_LINE_ETHERTYPE_SHIFT			19
6678 #define GFT_RAM_LINE_RESERVED0_MASK			0x1
6679 #define GFT_RAM_LINE_RESERVED0_SHIFT			20
6680 #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK			0x1
6681 #define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT			21
6682 #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK			0x1
6683 #define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT			22
6684 #define GFT_RAM_LINE_TCP_FLAG_RST_MASK			0x1
6685 #define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT			23
6686 #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK			0x1
6687 #define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT			24
6688 #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK			0x1
6689 #define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT			25
6690 #define GFT_RAM_LINE_TCP_FLAG_URG_MASK			0x1
6691 #define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT			26
6692 #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK			0x1
6693 #define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT			27
6694 #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK			0x1
6695 #define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT			28
6696 #define GFT_RAM_LINE_TCP_FLAG_NS_MASK			0x1
6697 #define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT			29
6698 #define GFT_RAM_LINE_DST_PORT_MASK			0x1
6699 #define GFT_RAM_LINE_DST_PORT_SHIFT			30
6700 #define GFT_RAM_LINE_SRC_PORT_MASK			0x1
6701 #define GFT_RAM_LINE_SRC_PORT_SHIFT			31
6702 	__le32 hi;
6703 #define GFT_RAM_LINE_DSCP_MASK				0x1
6704 #define GFT_RAM_LINE_DSCP_SHIFT				0
6705 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK		0x1
6706 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT		1
6707 #define GFT_RAM_LINE_DST_IP_MASK			0x1
6708 #define GFT_RAM_LINE_DST_IP_SHIFT			2
6709 #define GFT_RAM_LINE_SRC_IP_MASK			0x1
6710 #define GFT_RAM_LINE_SRC_IP_SHIFT			3
6711 #define GFT_RAM_LINE_PRIORITY_MASK			0x1
6712 #define GFT_RAM_LINE_PRIORITY_SHIFT			4
6713 #define GFT_RAM_LINE_PROVIDER_VLAN_MASK			0x1
6714 #define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT		5
6715 #define GFT_RAM_LINE_VLAN_MASK				0x1
6716 #define GFT_RAM_LINE_VLAN_SHIFT				6
6717 #define GFT_RAM_LINE_DST_MAC_MASK			0x1
6718 #define GFT_RAM_LINE_DST_MAC_SHIFT			7
6719 #define GFT_RAM_LINE_SRC_MAC_MASK			0x1
6720 #define GFT_RAM_LINE_SRC_MAC_SHIFT			8
6721 #define GFT_RAM_LINE_TENANT_ID_MASK			0x1
6722 #define GFT_RAM_LINE_TENANT_ID_SHIFT			9
6723 #define GFT_RAM_LINE_RESERVED1_MASK			0x3FFFFF
6724 #define GFT_RAM_LINE_RESERVED1_SHIFT			10
6725 };
6726 
6727 /* Used in the first 2 bits for gft_ram_line: Indication for vlan mask */
6728 enum gft_vlan_select {
6729 	INNER_PROVIDER_VLAN = 0,
6730 	INNER_VLAN = 1,
6731 	OUTER_PROVIDER_VLAN = 2,
6732 	OUTER_VLAN = 3,
6733 	MAX_GFT_VLAN_SELECT
6734 };
6735 
6736 /* The rdma task context of Mstorm */
6737 struct ystorm_rdma_task_st_ctx {
6738 	struct regpair temp[4];
6739 };
6740 
6741 struct e4_ystorm_rdma_task_ag_ctx {
6742 	u8 reserved;
6743 	u8 byte1;
6744 	__le16 msem_ctx_upd_seq;
6745 	u8 flags0;
6746 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK		0xF
6747 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT	0
6748 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK		0x1
6749 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT		4
6750 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK			0x1
6751 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT			5
6752 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK			0x1
6753 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT			6
6754 #define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK		0x1
6755 #define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT		7
6756 	u8 flags1;
6757 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK		0x3
6758 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT		0
6759 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK		0x3
6760 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT		2
6761 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK	0x3
6762 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT	4
6763 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK		0x1
6764 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT		6
6765 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK		0x1
6766 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT		7
6767 	u8 flags2;
6768 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK		0x1
6769 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT		0
6770 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK		0x1
6771 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT	1
6772 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK		0x1
6773 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT	2
6774 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK		0x1
6775 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT	3
6776 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK		0x1
6777 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT	4
6778 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK		0x1
6779 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT	5
6780 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK		0x1
6781 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT	6
6782 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK		0x1
6783 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT	7
6784 	u8 key;
6785 	__le32 mw_cnt_or_qp_id;
6786 	u8 ref_cnt_seq;
6787 	u8 ctx_upd_seq;
6788 	__le16 dif_flags;
6789 	__le16 tx_ref_count;
6790 	__le16 last_used_ltid;
6791 	__le16 parent_mr_lo;
6792 	__le16 parent_mr_hi;
6793 	__le32 fbo_lo;
6794 	__le32 fbo_hi;
6795 };
6796 
6797 struct e4_mstorm_rdma_task_ag_ctx {
6798 	u8 reserved;
6799 	u8 byte1;
6800 	__le16 icid;
6801 	u8 flags0;
6802 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK		0xF
6803 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT	0
6804 #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK		0x1
6805 #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT		4
6806 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK			0x1
6807 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT			5
6808 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK			0x1
6809 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT			6
6810 #define E4_MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK		0x1
6811 #define E4_MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT		7
6812 	u8 flags1;
6813 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK	0x3
6814 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT	0
6815 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK	0x3
6816 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT	2
6817 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK	0x3
6818 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT	4
6819 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK	0x1
6820 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT	6
6821 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK	0x1
6822 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT	7
6823 	u8 flags2;
6824 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK		0x1
6825 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT		0
6826 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK		0x1
6827 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT	1
6828 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK		0x1
6829 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT	2
6830 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK		0x1
6831 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT	3
6832 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK		0x1
6833 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT	4
6834 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK		0x1
6835 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT	5
6836 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK		0x1
6837 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT	6
6838 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK		0x1
6839 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT	7
6840 	u8 key;
6841 	__le32 mw_cnt_or_qp_id;
6842 	u8 ref_cnt_seq;
6843 	u8 ctx_upd_seq;
6844 	__le16 dif_flags;
6845 	__le16 tx_ref_count;
6846 	__le16 last_used_ltid;
6847 	__le16 parent_mr_lo;
6848 	__le16 parent_mr_hi;
6849 	__le32 fbo_lo;
6850 	__le32 fbo_hi;
6851 };
6852 
6853 /* The roce task context of Mstorm */
6854 struct mstorm_rdma_task_st_ctx {
6855 	struct regpair temp[4];
6856 };
6857 
6858 /* The roce task context of Ustorm */
6859 struct ustorm_rdma_task_st_ctx {
6860 	struct regpair temp[6];
6861 };
6862 
6863 struct e4_ustorm_rdma_task_ag_ctx {
6864 	u8 reserved;
6865 	u8 state;
6866 	__le16 icid;
6867 	u8 flags0;
6868 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK		0xF
6869 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT	0
6870 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK		0x1
6871 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT		4
6872 #define E4_USTORM_RDMA_TASK_AG_CTX_BIT1_MASK			0x1
6873 #define E4_USTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT			5
6874 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK	0x3
6875 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT	6
6876 	u8 flags1;
6877 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK	0x3
6878 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT	0
6879 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK		0x3
6880 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT		2
6881 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_MASK          0x3
6882 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_BLOCK_SIZE_SHIFT         4
6883 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK		0x3
6884 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT		6
6885 	u8 flags2;
6886 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK	0x1
6887 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT	0
6888 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK		0x1
6889 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT		1
6890 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK		0x1
6891 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT		2
6892 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED4_MASK               0x1
6893 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED4_SHIFT              3
6894 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK		0x1
6895 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT	4
6896 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK			0x1
6897 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT		5
6898 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK			0x1
6899 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT		6
6900 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK			0x1
6901 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT		7
6902 	u8 flags3;
6903 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_MASK	0x1
6904 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RXMIT_PROD_CONS_EN_SHIFT	0
6905 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK			0x1
6906 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT		1
6907 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_PROD_CONS_EN_MASK	0x1
6908 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_PROD_CONS_EN_SHIFT	2
6909 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK			0x1
6910 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT		3
6911 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK		0xF
6912 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT		4
6913 	__le32 dif_err_intervals;
6914 	__le32 dif_error_1st_interval;
6915 	__le32 dif_rxmit_cons;
6916 	__le32 dif_rxmit_prod;
6917 	__le32 sge_index;
6918 	__le32 sq_cons;
6919 	u8 byte2;
6920 	u8 byte3;
6921 	__le16 dif_write_cons;
6922 	__le16 dif_write_prod;
6923 	__le16 word3;
6924 	__le32 dif_error_buffer_address_lo;
6925 	__le32 dif_error_buffer_address_hi;
6926 };
6927 
6928 /* RDMA task context */
6929 struct e4_rdma_task_context {
6930 	struct ystorm_rdma_task_st_ctx ystorm_st_context;
6931 	struct e4_ystorm_rdma_task_ag_ctx ystorm_ag_context;
6932 	struct tdif_task_context tdif_context;
6933 	struct e4_mstorm_rdma_task_ag_ctx mstorm_ag_context;
6934 	struct mstorm_rdma_task_st_ctx mstorm_st_context;
6935 	struct rdif_task_context rdif_context;
6936 	struct ustorm_rdma_task_st_ctx ustorm_st_context;
6937 	struct regpair ustorm_st_padding[2];
6938 	struct e4_ustorm_rdma_task_ag_ctx ustorm_ag_context;
6939 };
6940 
6941 /* rdma function init ramrod data */
6942 struct rdma_close_func_ramrod_data {
6943 	u8 cnq_start_offset;
6944 	u8 num_cnqs;
6945 	u8 vf_id;
6946 	u8 vf_valid;
6947 	u8 reserved[4];
6948 };
6949 
6950 /* rdma function init CNQ parameters */
6951 struct rdma_cnq_params {
6952 	__le16 sb_num;
6953 	u8 sb_index;
6954 	u8 num_pbl_pages;
6955 	__le32 reserved;
6956 	struct regpair pbl_base_addr;
6957 	__le16 queue_zone_num;
6958 	u8 reserved1[6];
6959 };
6960 
6961 /* rdma create cq ramrod data */
6962 struct rdma_create_cq_ramrod_data {
6963 	struct regpair cq_handle;
6964 	struct regpair pbl_addr;
6965 	__le32 max_cqes;
6966 	__le16 pbl_num_pages;
6967 	__le16 dpi;
6968 	u8 is_two_level_pbl;
6969 	u8 cnq_id;
6970 	u8 pbl_log_page_size;
6971 	u8 toggle_bit;
6972 	__le16 int_timeout;
6973 	u8 vf_id;
6974 	u8 flags;
6975 #define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_MASK  0x1
6976 #define RDMA_CREATE_CQ_RAMROD_DATA_VF_ID_VALID_SHIFT 0
6977 #define RDMA_CREATE_CQ_RAMROD_DATA_RESERVED1_MASK    0x7F
6978 #define RDMA_CREATE_CQ_RAMROD_DATA_RESERVED1_SHIFT   1
6979 };
6980 
6981 /* rdma deregister tid ramrod data */
6982 struct rdma_deregister_tid_ramrod_data {
6983 	__le32 itid;
6984 	__le32 reserved;
6985 };
6986 
6987 /* rdma destroy cq output params */
6988 struct rdma_destroy_cq_output_params {
6989 	__le16 cnq_num;
6990 	__le16 reserved0;
6991 	__le32 reserved1;
6992 };
6993 
6994 /* rdma destroy cq ramrod data */
6995 struct rdma_destroy_cq_ramrod_data {
6996 	struct regpair output_params_addr;
6997 };
6998 
6999 /* RDMA slow path EQ cmd IDs */
7000 enum rdma_event_opcode {
7001 	RDMA_EVENT_UNUSED,
7002 	RDMA_EVENT_FUNC_INIT,
7003 	RDMA_EVENT_FUNC_CLOSE,
7004 	RDMA_EVENT_REGISTER_MR,
7005 	RDMA_EVENT_DEREGISTER_MR,
7006 	RDMA_EVENT_CREATE_CQ,
7007 	RDMA_EVENT_RESIZE_CQ,
7008 	RDMA_EVENT_DESTROY_CQ,
7009 	RDMA_EVENT_CREATE_SRQ,
7010 	RDMA_EVENT_MODIFY_SRQ,
7011 	RDMA_EVENT_DESTROY_SRQ,
7012 	MAX_RDMA_EVENT_OPCODE
7013 };
7014 
7015 /* RDMA FW return code for slow path ramrods */
7016 enum rdma_fw_return_code {
7017 	RDMA_RETURN_OK = 0,
7018 	RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR,
7019 	RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR,
7020 	RDMA_RETURN_RESIZE_CQ_ERR,
7021 	RDMA_RETURN_NIG_DRAIN_REQ,
7022 	RDMA_RETURN_GENERAL_ERR,
7023 	MAX_RDMA_FW_RETURN_CODE
7024 };
7025 
7026 /* rdma function init header */
7027 struct rdma_init_func_hdr {
7028 	u8 cnq_start_offset;
7029 	u8 num_cnqs;
7030 	u8 cq_ring_mode;
7031 	u8 vf_id;
7032 	u8 vf_valid;
7033 	u8 relaxed_ordering;
7034 	__le16 first_reg_srq_id;
7035 	__le32 reg_srq_base_addr;
7036 	u8 searcher_mode;
7037 	u8 pvrdma_mode;
7038 	u8 max_num_ns_log;
7039 	u8 reserved;
7040 };
7041 
7042 /* rdma function init ramrod data */
7043 struct rdma_init_func_ramrod_data {
7044 	struct rdma_init_func_hdr params_header;
7045 	struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES];
7046 };
7047 
7048 /* RDMA ramrod command IDs */
7049 enum rdma_ramrod_cmd_id {
7050 	RDMA_RAMROD_UNUSED,
7051 	RDMA_RAMROD_FUNC_INIT,
7052 	RDMA_RAMROD_FUNC_CLOSE,
7053 	RDMA_RAMROD_REGISTER_MR,
7054 	RDMA_RAMROD_DEREGISTER_MR,
7055 	RDMA_RAMROD_CREATE_CQ,
7056 	RDMA_RAMROD_RESIZE_CQ,
7057 	RDMA_RAMROD_DESTROY_CQ,
7058 	RDMA_RAMROD_CREATE_SRQ,
7059 	RDMA_RAMROD_MODIFY_SRQ,
7060 	RDMA_RAMROD_DESTROY_SRQ,
7061 	MAX_RDMA_RAMROD_CMD_ID
7062 };
7063 
7064 /* rdma register tid ramrod data */
7065 struct rdma_register_tid_ramrod_data {
7066 	__le16 flags;
7067 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK	0x1F
7068 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT	0
7069 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK	0x1
7070 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT	5
7071 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK		0x1
7072 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT		6
7073 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK		0x1
7074 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT		7
7075 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK		0x1
7076 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT		8
7077 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK		0x1
7078 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT	9
7079 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK	0x1
7080 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT	10
7081 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK		0x1
7082 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT		11
7083 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK		0x1
7084 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT		12
7085 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK	0x1
7086 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT	13
7087 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK		0x3
7088 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_SHIFT		14
7089 	u8 flags1;
7090 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK	0x1F
7091 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT	0
7092 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK		0x7
7093 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT		5
7094 	u8 flags2;
7095 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK		0x1
7096 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT		0
7097 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK	0x1
7098 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT	1
7099 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK		0x3F
7100 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT		2
7101 	u8 key;
7102 	u8 length_hi;
7103 	u8 vf_id;
7104 	u8 vf_valid;
7105 	__le16 pd;
7106 	__le16 reserved2;
7107 	__le32 length_lo;
7108 	__le32 itid;
7109 	__le32 reserved3;
7110 	struct regpair va;
7111 	struct regpair pbl_base;
7112 	struct regpair dif_error_addr;
7113 	__le32 reserved4[4];
7114 };
7115 
7116 /* rdma resize cq output params */
7117 struct rdma_resize_cq_output_params {
7118 	__le32 old_cq_cons;
7119 	__le32 old_cq_prod;
7120 };
7121 
7122 /* rdma resize cq ramrod data */
7123 struct rdma_resize_cq_ramrod_data {
7124 	u8 flags;
7125 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK		0x1
7126 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT		0
7127 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK	0x1
7128 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT	1
7129 #define RDMA_RESIZE_CQ_RAMROD_DATA_VF_ID_VALID_MASK		0x1
7130 #define RDMA_RESIZE_CQ_RAMROD_DATA_VF_ID_VALID_SHIFT		2
7131 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK		0x1F
7132 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT		3
7133 	u8 pbl_log_page_size;
7134 	__le16 pbl_num_pages;
7135 	__le32 max_cqes;
7136 	struct regpair pbl_addr;
7137 	struct regpair output_params_addr;
7138 	u8 vf_id;
7139 	u8 reserved1[7];
7140 };
7141 
7142 /* The rdma SRQ context */
7143 struct rdma_srq_context {
7144 	struct regpair temp[8];
7145 };
7146 
7147 /* rdma create qp requester ramrod data */
7148 struct rdma_srq_create_ramrod_data {
7149 	u8 flags;
7150 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_MASK         0x1
7151 #define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_SHIFT        0
7152 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_MASK  0x1
7153 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 1
7154 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_MASK        0x3F
7155 #define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_SHIFT       2
7156 	u8 reserved2;
7157 	__le16 xrc_domain;
7158 	__le32 xrc_srq_cq_cid;
7159 	struct regpair pbl_base_addr;
7160 	__le16 pages_in_srq_pbl;
7161 	__le16 pd_id;
7162 	struct rdma_srq_id srq_id;
7163 	__le16 page_size;
7164 	__le16 reserved3;
7165 	__le32 reserved4;
7166 	struct regpair producers_addr;
7167 };
7168 
7169 /* rdma create qp requester ramrod data */
7170 struct rdma_srq_destroy_ramrod_data {
7171 	struct rdma_srq_id srq_id;
7172 	__le32 reserved;
7173 };
7174 
7175 /* rdma create qp requester ramrod data */
7176 struct rdma_srq_modify_ramrod_data {
7177 	struct rdma_srq_id srq_id;
7178 	__le32 wqe_limit;
7179 };
7180 
7181 /* RDMA Tid type enumeration (for register_tid ramrod) */
7182 enum rdma_tid_type {
7183 	RDMA_TID_REGISTERED_MR,
7184 	RDMA_TID_FMR,
7185 	RDMA_TID_MW,
7186 	MAX_RDMA_TID_TYPE
7187 };
7188 
7189 /* The rdma XRC SRQ context */
7190 struct rdma_xrc_srq_context {
7191 	struct regpair temp[9];
7192 };
7193 
7194 struct e4_tstorm_rdma_task_ag_ctx {
7195 	u8 byte0;
7196 	u8 byte1;
7197 	__le16 word0;
7198 	u8 flags0;
7199 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK		0xF
7200 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT	0
7201 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK		0x1
7202 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT		4
7203 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK		0x1
7204 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT		5
7205 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK		0x1
7206 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT		6
7207 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK		0x1
7208 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT		7
7209 	u8 flags1;
7210 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK	0x1
7211 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT	0
7212 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK	0x1
7213 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT	1
7214 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK	0x3
7215 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT	2
7216 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK	0x3
7217 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT	4
7218 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK	0x3
7219 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT	6
7220 	u8 flags2;
7221 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK	0x3
7222 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT	0
7223 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK	0x3
7224 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT	2
7225 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK	0x3
7226 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT	4
7227 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK	0x3
7228 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT	6
7229 	u8 flags3;
7230 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK	0x3
7231 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT	0
7232 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK	0x1
7233 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT	2
7234 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK	0x1
7235 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT	3
7236 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK	0x1
7237 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT	4
7238 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK	0x1
7239 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT	5
7240 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK	0x1
7241 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT	6
7242 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK	0x1
7243 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT	7
7244 	u8 flags4;
7245 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK		0x1
7246 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT		0
7247 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK		0x1
7248 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT		1
7249 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK		0x1
7250 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT	2
7251 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK		0x1
7252 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT	3
7253 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK		0x1
7254 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT	4
7255 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK		0x1
7256 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT	5
7257 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK		0x1
7258 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT	6
7259 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK		0x1
7260 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT	7
7261 	u8 byte2;
7262 	__le16 word1;
7263 	__le32 reg0;
7264 	u8 byte3;
7265 	u8 byte4;
7266 	__le16 word2;
7267 	__le16 word3;
7268 	__le16 word4;
7269 	__le32 reg1;
7270 	__le32 reg2;
7271 };
7272 
7273 struct e4_ustorm_rdma_conn_ag_ctx {
7274 	u8 reserved;
7275 	u8 byte1;
7276 	u8 flags0;
7277 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
7278 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
7279 #define E4_USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_MASK  0x1
7280 #define E4_USTORM_RDMA_CONN_AG_CTX_DIF_ERROR_REPORTED_SHIFT 1
7281 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK	0x3
7282 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT	2
7283 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_MASK		0x3
7284 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT		4
7285 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_MASK		0x3
7286 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT		6
7287 	u8 flags1;
7288 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_MASK		0x3
7289 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT		0
7290 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK	0x3
7291 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT	2
7292 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK	0x3
7293 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT	4
7294 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_MASK		0x3
7295 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT		6
7296 	u8 flags2;
7297 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK		0x1
7298 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT		0
7299 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK			0x1
7300 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT			1
7301 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK			0x1
7302 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT			2
7303 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK			0x1
7304 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT			3
7305 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK		0x1
7306 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT	4
7307 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK		0x1
7308 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT		5
7309 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK			0x1
7310 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT			6
7311 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK		0x1
7312 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT		7
7313 	u8 flags3;
7314 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK		0x1
7315 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT		0
7316 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK		0x1
7317 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT	1
7318 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK		0x1
7319 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT	2
7320 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK		0x1
7321 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT	3
7322 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK		0x1
7323 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT	4
7324 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK		0x1
7325 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT	5
7326 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK		0x1
7327 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT	6
7328 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK		0x1
7329 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT	7
7330 	u8 byte2;
7331 	u8 nvmf_only;
7332 	__le16 conn_dpi;
7333 	__le16 word1;
7334 	__le32 cq_cons;
7335 	__le32 cq_se_prod;
7336 	__le32 cq_prod;
7337 	__le32 reg3;
7338 	__le16 int_timeout;
7339 	__le16 word3;
7340 };
7341 
7342 struct e4_xstorm_roce_conn_ag_ctx {
7343 	u8 reserved0;
7344 	u8 state;
7345 	u8 flags0;
7346 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK      0x1
7347 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT     0
7348 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT1_MASK              0x1
7349 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT             1
7350 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT2_MASK              0x1
7351 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT2_SHIFT             2
7352 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_MASK      0x1
7353 #define E4_XSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT     3
7354 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT4_MASK              0x1
7355 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT4_SHIFT             4
7356 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT5_MASK              0x1
7357 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT5_SHIFT             5
7358 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT6_MASK              0x1
7359 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT6_SHIFT             6
7360 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT7_MASK              0x1
7361 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT7_SHIFT             7
7362 	u8 flags1;
7363 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT8_MASK              0x1
7364 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT8_SHIFT             0
7365 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT9_MASK              0x1
7366 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT9_SHIFT             1
7367 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT10_MASK             0x1
7368 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT10_SHIFT            2
7369 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT11_MASK             0x1
7370 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT11_SHIFT            3
7371 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_MASK        0x1
7372 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSDM_FLUSH_SHIFT       4
7373 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_MASK        0x1
7374 #define E4_XSTORM_ROCE_CONN_AG_CTX_MSEM_FLUSH_SHIFT       5
7375 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT14_MASK	       0x1
7376 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT14_SHIFT	       6
7377 #define E4_XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_MASK      0x1
7378 #define E4_XSTORM_ROCE_CONN_AG_CTX_YSTORM_FLUSH_SHIFT     7
7379 	u8 flags2;
7380 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0_MASK               0x3
7381 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT              0
7382 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1_MASK               0x3
7383 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT              2
7384 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2_MASK               0x3
7385 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT              4
7386 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3_MASK               0x3
7387 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3_SHIFT              6
7388 	u8 flags3;
7389 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4_MASK               0x3
7390 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4_SHIFT              0
7391 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5_MASK               0x3
7392 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT              2
7393 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6_MASK               0x3
7394 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6_SHIFT              4
7395 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK       0x3
7396 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT      6
7397 	u8 flags4;
7398 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8_MASK               0x3
7399 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT              0
7400 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9_MASK               0x3
7401 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT              2
7402 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10_MASK              0x3
7403 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10_SHIFT             4
7404 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11_MASK              0x3
7405 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11_SHIFT             6
7406 	u8 flags5;
7407 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12_MASK              0x3
7408 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12_SHIFT             0
7409 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13_MASK              0x3
7410 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13_SHIFT             2
7411 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14_MASK              0x3
7412 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14_SHIFT             4
7413 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15_MASK              0x3
7414 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15_SHIFT             6
7415 	u8 flags6;
7416 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16_MASK              0x3
7417 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16_SHIFT             0
7418 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17_MASK              0x3
7419 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17_SHIFT             2
7420 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18_MASK              0x3
7421 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18_SHIFT             4
7422 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19_MASK              0x3
7423 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19_SHIFT             6
7424 	u8 flags7;
7425 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20_MASK              0x3
7426 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20_SHIFT             0
7427 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21_MASK              0x3
7428 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21_SHIFT             2
7429 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_MASK         0x3
7430 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_SHIFT        4
7431 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK             0x1
7432 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT            6
7433 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK             0x1
7434 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT            7
7435 	u8 flags8;
7436 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK             0x1
7437 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT            0
7438 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3EN_MASK             0x1
7439 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF3EN_SHIFT            1
7440 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4EN_MASK             0x1
7441 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF4EN_SHIFT            2
7442 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK             0x1
7443 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF5EN_SHIFT            3
7444 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK             0x1
7445 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF6EN_SHIFT            4
7446 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK    0x1
7447 #define E4_XSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT   5
7448 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK             0x1
7449 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF8EN_SHIFT            6
7450 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK             0x1
7451 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF9EN_SHIFT            7
7452 	u8 flags9;
7453 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK            0x1
7454 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT           0
7455 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11EN_MASK            0x1
7456 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF11EN_SHIFT           1
7457 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12EN_MASK            0x1
7458 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF12EN_SHIFT           2
7459 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13EN_MASK            0x1
7460 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF13EN_SHIFT           3
7461 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14EN_MASK            0x1
7462 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF14EN_SHIFT           4
7463 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15EN_MASK            0x1
7464 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF15EN_SHIFT           5
7465 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16EN_MASK            0x1
7466 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF16EN_SHIFT           6
7467 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17EN_MASK            0x1
7468 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF17EN_SHIFT           7
7469 	u8 flags10;
7470 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18EN_MASK            0x1
7471 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF18EN_SHIFT           0
7472 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19EN_MASK            0x1
7473 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF19EN_SHIFT           1
7474 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20EN_MASK            0x1
7475 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF20EN_SHIFT           2
7476 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21EN_MASK            0x1
7477 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF21EN_SHIFT           3
7478 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_MASK      0x1
7479 #define E4_XSTORM_ROCE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT     4
7480 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23EN_MASK            0x1
7481 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23EN_SHIFT           5
7482 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK           0x1
7483 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT          6
7484 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK           0x1
7485 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT          7
7486 	u8 flags11;
7487 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK           0x1
7488 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT          0
7489 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK           0x1
7490 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT          1
7491 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK           0x1
7492 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT          2
7493 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK           0x1
7494 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE5EN_SHIFT          3
7495 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK           0x1
7496 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE6EN_SHIFT          4
7497 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK           0x1
7498 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE7EN_SHIFT          5
7499 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_MASK      0x1
7500 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED1_SHIFT     6
7501 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE9EN_MASK           0x1
7502 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE9EN_SHIFT          7
7503 	u8 flags12;
7504 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE10EN_MASK          0x1
7505 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE10EN_SHIFT         0
7506 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE11EN_MASK          0x1
7507 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE11EN_SHIFT         1
7508 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_MASK      0x1
7509 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED2_SHIFT     2
7510 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_MASK      0x1
7511 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED3_SHIFT     3
7512 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE14EN_MASK          0x1
7513 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE14EN_SHIFT         4
7514 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE15EN_MASK          0x1
7515 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE15EN_SHIFT         5
7516 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE16EN_MASK          0x1
7517 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE16EN_SHIFT         6
7518 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE17EN_MASK          0x1
7519 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE17EN_SHIFT         7
7520 	u8 flags13;
7521 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE18EN_MASK          0x1
7522 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE18EN_SHIFT         0
7523 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE19EN_MASK          0x1
7524 #define E4_XSTORM_ROCE_CONN_AG_CTX_RULE19EN_SHIFT         1
7525 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_MASK      0x1
7526 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED4_SHIFT     2
7527 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_MASK      0x1
7528 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED5_SHIFT     3
7529 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_MASK      0x1
7530 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED6_SHIFT     4
7531 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_MASK      0x1
7532 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED7_SHIFT     5
7533 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_MASK      0x1
7534 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED8_SHIFT     6
7535 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_MASK      0x1
7536 #define E4_XSTORM_ROCE_CONN_AG_CTX_A0_RESERVED9_SHIFT     7
7537 	u8 flags14;
7538 #define E4_XSTORM_ROCE_CONN_AG_CTX_MIGRATION_MASK         0x1
7539 #define E4_XSTORM_ROCE_CONN_AG_CTX_MIGRATION_SHIFT        0
7540 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT17_MASK             0x1
7541 #define E4_XSTORM_ROCE_CONN_AG_CTX_BIT17_SHIFT            1
7542 #define E4_XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_MASK      0x3
7543 #define E4_XSTORM_ROCE_CONN_AG_CTX_DPM_PORT_NUM_SHIFT     2
7544 #define E4_XSTORM_ROCE_CONN_AG_CTX_RESERVED_MASK          0x1
7545 #define E4_XSTORM_ROCE_CONN_AG_CTX_RESERVED_SHIFT         4
7546 #define E4_XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK  0x1
7547 #define E4_XSTORM_ROCE_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5
7548 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23_MASK              0x3
7549 #define E4_XSTORM_ROCE_CONN_AG_CTX_CF23_SHIFT             6
7550 	u8 byte2;
7551 	__le16 physical_q0;
7552 	__le16 word1;
7553 	__le16 word2;
7554 	__le16 word3;
7555 	__le16 word4;
7556 	__le16 word5;
7557 	__le16 conn_dpi;
7558 	u8 byte3;
7559 	u8 byte4;
7560 	u8 byte5;
7561 	u8 byte6;
7562 	__le32 reg0;
7563 	__le32 reg1;
7564 	__le32 reg2;
7565 	__le32 snd_nxt_psn;
7566 	__le32 reg4;
7567 	__le32 reg5;
7568 	__le32 reg6;
7569 };
7570 
7571 struct e4_tstorm_roce_conn_ag_ctx {
7572 	u8 reserved0;
7573 	u8 byte1;
7574 	u8 flags0;
7575 #define E4_TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_MASK          0x1
7576 #define E4_TSTORM_ROCE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT         0
7577 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT1_MASK                  0x1
7578 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT                 1
7579 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT2_MASK                  0x1
7580 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT2_SHIFT                 2
7581 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT3_MASK                  0x1
7582 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT3_SHIFT                 3
7583 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT4_MASK                  0x1
7584 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT4_SHIFT                 4
7585 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT5_MASK                  0x1
7586 #define E4_TSTORM_ROCE_CONN_AG_CTX_BIT5_SHIFT                 5
7587 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0_MASK                   0x3
7588 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT                  6
7589 	u8 flags1;
7590 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK       0x3
7591 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT      0
7592 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2_MASK                   0x3
7593 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT                  2
7594 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK     0x3
7595 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT    4
7596 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_MASK           0x3
7597 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT          6
7598 	u8 flags2;
7599 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5_MASK                   0x3
7600 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5_SHIFT                  0
7601 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6_MASK                   0x3
7602 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6_SHIFT                  2
7603 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7_MASK                   0x3
7604 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7_SHIFT                  4
7605 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8_MASK                   0x3
7606 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8_SHIFT                  6
7607 	u8 flags3;
7608 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9_MASK                   0x3
7609 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9_SHIFT                  0
7610 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10_MASK                  0x3
7611 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10_SHIFT                 2
7612 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK                 0x1
7613 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT                4
7614 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK    0x1
7615 #define E4_TSTORM_ROCE_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT   5
7616 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK                 0x1
7617 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT                6
7618 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK  0x1
7619 #define E4_TSTORM_ROCE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7
7620 	u8 flags4;
7621 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK        0x1
7622 #define E4_TSTORM_ROCE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT       0
7623 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5EN_MASK                 0x1
7624 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF5EN_SHIFT                1
7625 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6EN_MASK                 0x1
7626 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF6EN_SHIFT                2
7627 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7EN_MASK                 0x1
7628 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF7EN_SHIFT                3
7629 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8EN_MASK                 0x1
7630 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF8EN_SHIFT                4
7631 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9EN_MASK                 0x1
7632 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF9EN_SHIFT                5
7633 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10EN_MASK                0x1
7634 #define E4_TSTORM_ROCE_CONN_AG_CTX_CF10EN_SHIFT               6
7635 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK               0x1
7636 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT              7
7637 	u8 flags5;
7638 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK               0x1
7639 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT              0
7640 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK               0x1
7641 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT              1
7642 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK               0x1
7643 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT              2
7644 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK               0x1
7645 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT              3
7646 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE5EN_MASK               0x1
7647 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE5EN_SHIFT              4
7648 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE6EN_MASK               0x1
7649 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE6EN_SHIFT              5
7650 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE7EN_MASK               0x1
7651 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE7EN_SHIFT              6
7652 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE8EN_MASK               0x1
7653 #define E4_TSTORM_ROCE_CONN_AG_CTX_RULE8EN_SHIFT              7
7654 	__le32 reg0;
7655 	__le32 reg1;
7656 	__le32 reg2;
7657 	__le32 reg3;
7658 	__le32 reg4;
7659 	__le32 reg5;
7660 	__le32 reg6;
7661 	__le32 reg7;
7662 	__le32 reg8;
7663 	u8 byte2;
7664 	u8 byte3;
7665 	__le16 word0;
7666 	u8 byte4;
7667 	u8 byte5;
7668 	__le16 word1;
7669 	__le16 word2;
7670 	__le16 word3;
7671 	__le32 reg9;
7672 	__le32 reg10;
7673 };
7674 
7675 /* The roce storm context of Ystorm */
7676 struct ystorm_roce_conn_st_ctx {
7677 	struct regpair temp[2];
7678 };
7679 
7680 /* The roce storm context of Mstorm */
7681 struct pstorm_roce_conn_st_ctx {
7682 	struct regpair temp[16];
7683 };
7684 
7685 /* The roce storm context of Xstorm */
7686 struct xstorm_roce_conn_st_ctx {
7687 	struct regpair temp[24];
7688 };
7689 
7690 /* The roce storm context of Tstorm */
7691 struct tstorm_roce_conn_st_ctx {
7692 	struct regpair temp[30];
7693 };
7694 
7695 /* The roce storm context of Mstorm */
7696 struct mstorm_roce_conn_st_ctx {
7697 	struct regpair temp[6];
7698 };
7699 
7700 /* The roce storm context of Ustorm */
7701 struct ustorm_roce_conn_st_ctx {
7702 	struct regpair temp[14];
7703 };
7704 
7705 /* roce connection context */
7706 struct e4_roce_conn_context {
7707 	struct ystorm_roce_conn_st_ctx ystorm_st_context;
7708 	struct regpair ystorm_st_padding[2];
7709 	struct pstorm_roce_conn_st_ctx pstorm_st_context;
7710 	struct xstorm_roce_conn_st_ctx xstorm_st_context;
7711 	struct e4_xstorm_roce_conn_ag_ctx xstorm_ag_context;
7712 	struct e4_tstorm_roce_conn_ag_ctx tstorm_ag_context;
7713 	struct timers_context timer_context;
7714 	struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context;
7715 	struct tstorm_roce_conn_st_ctx tstorm_st_context;
7716 	struct regpair tstorm_st_padding[2];
7717 	struct mstorm_roce_conn_st_ctx mstorm_st_context;
7718 	struct regpair mstorm_st_padding[2];
7719 	struct ustorm_roce_conn_st_ctx ustorm_st_context;
7720 	struct regpair ustorm_st_padding[2];
7721 };
7722 
7723 /* roce cqes statistics */
7724 struct roce_cqe_stats {
7725 	__le32 req_cqe_error;
7726 	__le32 req_remote_access_errors;
7727 	__le32 req_remote_invalid_request;
7728 	__le32 resp_cqe_error;
7729 	__le32 resp_local_length_error;
7730 	__le32 reserved;
7731 };
7732 
7733 /* roce create qp requester ramrod data */
7734 struct roce_create_qp_req_ramrod_data {
7735 	__le16 flags;
7736 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK			0x3
7737 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT		0
7738 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK		0x1
7739 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT	2
7740 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK		0x1
7741 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT		3
7742 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK				0x7
7743 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT			4
7744 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_MASK			0x1
7745 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_XRC_FLAG_SHIFT			7
7746 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK		0xF
7747 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT		8
7748 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK			0xF
7749 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT		12
7750 	u8 max_ord;
7751 	u8 traffic_class;
7752 	u8 hop_limit;
7753 	u8 orq_num_pages;
7754 	__le16 p_key;
7755 	__le32 flow_label;
7756 	__le32 dst_qp_id;
7757 	__le32 ack_timeout_val;
7758 	__le32 initial_psn;
7759 	__le16 mtu;
7760 	__le16 pd;
7761 	__le16 sq_num_pages;
7762 	__le16 low_latency_phy_queue;
7763 	struct regpair sq_pbl_addr;
7764 	struct regpair orq_pbl_addr;
7765 	__le16 local_mac_addr[3];
7766 	__le16 remote_mac_addr[3];
7767 	__le16 vlan_id;
7768 	__le16 udp_src_port;
7769 	__le32 src_gid[4];
7770 	__le32 dst_gid[4];
7771 	__le32 cq_cid;
7772 	struct regpair qp_handle_for_cqe;
7773 	struct regpair qp_handle_for_async;
7774 	u8 stats_counter_id;
7775 	u8 vf_id;
7776 	u8 vport_id;
7777 	u8 flags2;
7778 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_MASK			0x1
7779 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_EDPM_MODE_SHIFT			0
7780 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_VF_ID_VALID_MASK			0x1
7781 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_VF_ID_VALID_SHIFT		1
7782 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK			0x3F
7783 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT			2
7784 	u8 name_space;
7785 	u8 reserved3[3];
7786 	__le16 regular_latency_phy_queue;
7787 	__le16 dpi;
7788 };
7789 
7790 /* roce create qp responder ramrod data */
7791 struct roce_create_qp_resp_ramrod_data {
7792 	__le32 flags;
7793 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK		0x3
7794 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT		0
7795 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK			0x1
7796 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT		2
7797 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK			0x1
7798 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT		3
7799 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK			0x1
7800 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT			4
7801 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK			0x1
7802 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT			5
7803 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK	0x1
7804 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT	6
7805 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK		0x1
7806 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT		7
7807 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK			0x7
7808 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT			8
7809 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK		0x1F
7810 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT		11
7811 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_MASK             0x1
7812 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_XRC_FLAG_SHIFT            16
7813 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_VF_ID_VALID_MASK	0x1
7814 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_VF_ID_VALID_SHIFT	17
7815 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_MASK		0x3FFF
7816 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_SHIFT		18
7817 	__le16 xrc_domain;
7818 	u8 max_ird;
7819 	u8 traffic_class;
7820 	u8 hop_limit;
7821 	u8 irq_num_pages;
7822 	__le16 p_key;
7823 	__le32 flow_label;
7824 	__le32 dst_qp_id;
7825 	u8 stats_counter_id;
7826 	u8 reserved1;
7827 	__le16 mtu;
7828 	__le32 initial_psn;
7829 	__le16 pd;
7830 	__le16 rq_num_pages;
7831 	struct rdma_srq_id srq_id;
7832 	struct regpair rq_pbl_addr;
7833 	struct regpair irq_pbl_addr;
7834 	__le16 local_mac_addr[3];
7835 	__le16 remote_mac_addr[3];
7836 	__le16 vlan_id;
7837 	__le16 udp_src_port;
7838 	__le32 src_gid[4];
7839 	__le32 dst_gid[4];
7840 	struct regpair qp_handle_for_cqe;
7841 	struct regpair qp_handle_for_async;
7842 	__le16 low_latency_phy_queue;
7843 	u8 vf_id;
7844 	u8 vport_id;
7845 	__le32 cq_cid;
7846 	__le16 regular_latency_phy_queue;
7847 	__le16 dpi;
7848 	__le32 src_qp_id;
7849 	u8 name_space;
7850 	u8 reserved3[3];
7851 };
7852 
7853 /* roce DCQCN received statistics */
7854 struct roce_dcqcn_received_stats {
7855 	struct regpair ecn_pkt_rcv;
7856 	struct regpair cnp_pkt_rcv;
7857 };
7858 
7859 /* roce DCQCN sent statistics */
7860 struct roce_dcqcn_sent_stats {
7861 	struct regpair cnp_pkt_sent;
7862 };
7863 
7864 /* RoCE destroy qp requester output params */
7865 struct roce_destroy_qp_req_output_params {
7866 	__le32 cq_prod;
7867 	__le32 reserved;
7868 };
7869 
7870 /* RoCE destroy qp requester ramrod data */
7871 struct roce_destroy_qp_req_ramrod_data {
7872 	struct regpair output_params_addr;
7873 };
7874 
7875 /* RoCE destroy qp responder output params */
7876 struct roce_destroy_qp_resp_output_params {
7877 	__le32 cq_prod;
7878 	__le32 reserved;
7879 };
7880 
7881 /* RoCE destroy qp responder ramrod data */
7882 struct roce_destroy_qp_resp_ramrod_data {
7883 	struct regpair output_params_addr;
7884 	__le32 src_qp_id;
7885 	__le32 reserved;
7886 };
7887 
7888 /* roce error statistics */
7889 struct roce_error_stats {
7890 	__le32 resp_remote_access_errors;
7891 	__le32 reserved;
7892 };
7893 
7894 /* roce special events statistics */
7895 struct roce_events_stats {
7896 	__le32 silent_drops;
7897 	__le32 rnr_naks_sent;
7898 	__le32 retransmit_count;
7899 	__le32 icrc_error_count;
7900 	__le32 implied_nak_seq_err;
7901 	__le32 duplicate_request;
7902 	__le32 local_ack_timeout_err;
7903 	__le32 out_of_sequence;
7904 	__le32 packet_seq_err;
7905 	__le32 rnr_nak_retry_err;
7906 };
7907 
7908 /* roce slow path EQ cmd IDs */
7909 enum roce_event_opcode {
7910 	ROCE_EVENT_CREATE_QP = 11,
7911 	ROCE_EVENT_MODIFY_QP,
7912 	ROCE_EVENT_QUERY_QP,
7913 	ROCE_EVENT_DESTROY_QP,
7914 	ROCE_EVENT_CREATE_UD_QP,
7915 	ROCE_EVENT_DESTROY_UD_QP,
7916 	ROCE_EVENT_FUNC_UPDATE,
7917 	MAX_ROCE_EVENT_OPCODE
7918 };
7919 
7920 /* roce func init ramrod data */
7921 struct roce_init_func_params {
7922 	u8 ll2_queue_id;
7923 	u8 cnp_vlan_priority;
7924 	u8 cnp_dscp;
7925 	u8 flags;
7926 #define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_MASK		0x1
7927 #define ROCE_INIT_FUNC_PARAMS_DCQCN_NP_EN_SHIFT		0
7928 #define ROCE_INIT_FUNC_PARAMS_DCQCN_RP_EN_MASK		0x1
7929 #define ROCE_INIT_FUNC_PARAMS_DCQCN_RP_EN_SHIFT		1
7930 #define ROCE_INIT_FUNC_PARAMS_RESERVED0_MASK		0x3F
7931 #define ROCE_INIT_FUNC_PARAMS_RESERVED0_SHIFT		2
7932 	__le32 cnp_send_timeout;
7933 	__le16 rl_offset;
7934 	u8 rl_count_log;
7935 	u8 reserved1[5];
7936 };
7937 
7938 /* roce func init ramrod data */
7939 struct roce_init_func_ramrod_data {
7940 	struct rdma_init_func_ramrod_data rdma;
7941 	struct roce_init_func_params roce;
7942 };
7943 
7944 /* roce modify qp requester ramrod data */
7945 struct roce_modify_qp_req_ramrod_data {
7946 	__le16 flags;
7947 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK		0x1
7948 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT		0
7949 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK		0x1
7950 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT		1
7951 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK		0x1
7952 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT	2
7953 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK			0x1
7954 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT			3
7955 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK		0x1
7956 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT		4
7957 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK			0x1
7958 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT		5
7959 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK		0x1
7960 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT		6
7961 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK		0x1
7962 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT		7
7963 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK		0x1
7964 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT		8
7965 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK			0x1
7966 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT			9
7967 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK				0x7
7968 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT			10
7969 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK		0x1
7970 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT		13
7971 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK			0x3
7972 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT			14
7973 	u8 fields;
7974 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK	0xF
7975 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT	0
7976 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK		0xF
7977 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT	4
7978 	u8 max_ord;
7979 	u8 traffic_class;
7980 	u8 hop_limit;
7981 	__le16 p_key;
7982 	__le32 flow_label;
7983 	__le32 ack_timeout_val;
7984 	__le16 mtu;
7985 	__le16 reserved2;
7986 	__le32 reserved3[2];
7987 	__le16 low_latency_phy_queue;
7988 	__le16 regular_latency_phy_queue;
7989 	__le32 src_gid[4];
7990 	__le32 dst_gid[4];
7991 };
7992 
7993 /* roce modify qp responder ramrod data */
7994 struct roce_modify_qp_resp_ramrod_data {
7995 	__le16 flags;
7996 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK		0x1
7997 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT		0
7998 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK			0x1
7999 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT		1
8000 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK			0x1
8001 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT		2
8002 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK			0x1
8003 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT			3
8004 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK			0x1
8005 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT			4
8006 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK		0x1
8007 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT	5
8008 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK		0x1
8009 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT		6
8010 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK			0x1
8011 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT			7
8012 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK	0x1
8013 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT	8
8014 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK		0x1
8015 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT		9
8016 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK		0x1
8017 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT	10
8018 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK			0x1F
8019 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT			11
8020 	u8 fields;
8021 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK		0x7
8022 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT		0
8023 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK	0x1F
8024 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT	3
8025 	u8 max_ird;
8026 	u8 traffic_class;
8027 	u8 hop_limit;
8028 	__le16 p_key;
8029 	__le32 flow_label;
8030 	__le16 mtu;
8031 	__le16 low_latency_phy_queue;
8032 	__le16 regular_latency_phy_queue;
8033 	u8 reserved2[6];
8034 	__le32 src_gid[4];
8035 	__le32 dst_gid[4];
8036 };
8037 
8038 /* RoCE query qp requester output params */
8039 struct roce_query_qp_req_output_params {
8040 	__le32 psn;
8041 	__le32 flags;
8042 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK		0x1
8043 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT		0
8044 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK	0x1
8045 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT	1
8046 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK		0x3FFFFFFF
8047 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT		2
8048 };
8049 
8050 /* RoCE query qp requester ramrod data */
8051 struct roce_query_qp_req_ramrod_data {
8052 	struct regpair output_params_addr;
8053 };
8054 
8055 /* RoCE query qp responder output params */
8056 struct roce_query_qp_resp_output_params {
8057 	__le32 psn;
8058 	__le32 flags;
8059 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK  0x1
8060 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0
8061 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK  0x7FFFFFFF
8062 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1
8063 };
8064 
8065 /* RoCE query qp responder ramrod data */
8066 struct roce_query_qp_resp_ramrod_data {
8067 	struct regpair output_params_addr;
8068 };
8069 
8070 /* ROCE ramrod command IDs */
8071 enum roce_ramrod_cmd_id {
8072 	ROCE_RAMROD_CREATE_QP = 11,
8073 	ROCE_RAMROD_MODIFY_QP,
8074 	ROCE_RAMROD_QUERY_QP,
8075 	ROCE_RAMROD_DESTROY_QP,
8076 	ROCE_RAMROD_CREATE_UD_QP,
8077 	ROCE_RAMROD_DESTROY_UD_QP,
8078 	ROCE_RAMROD_FUNC_UPDATE,
8079 	MAX_ROCE_RAMROD_CMD_ID
8080 };
8081 
8082 /* RoCE func init ramrod data */
8083 struct roce_update_func_params {
8084 	u8 cnp_vlan_priority;
8085 	u8 cnp_dscp;
8086 	__le16 flags;
8087 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_MASK	0x1
8088 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_NP_EN_SHIFT	0
8089 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_RP_EN_MASK	0x1
8090 #define ROCE_UPDATE_FUNC_PARAMS_DCQCN_RP_EN_SHIFT	1
8091 #define ROCE_UPDATE_FUNC_PARAMS_RESERVED0_MASK		0x3FFF
8092 #define ROCE_UPDATE_FUNC_PARAMS_RESERVED0_SHIFT		2
8093 	__le32 cnp_send_timeout;
8094 };
8095 
8096 struct e4_xstorm_roce_conn_ag_ctx_dq_ext_ld_part {
8097 	u8 reserved0;
8098 	u8 state;
8099 	u8 flags0;
8100 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK	0x1
8101 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT	0
8102 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK		0x1
8103 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT		1
8104 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK		0x1
8105 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT		2
8106 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK	0x1
8107 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT	3
8108 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK		0x1
8109 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT		4
8110 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK		0x1
8111 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT		5
8112 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK		0x1
8113 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT		6
8114 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK		0x1
8115 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT		7
8116 	u8 flags1;
8117 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK		0x1
8118 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT		0
8119 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK		0x1
8120 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT		1
8121 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK		0x1
8122 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT		2
8123 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK		0x1
8124 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT		3
8125 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_MASK	0x1
8126 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSDM_FLUSH_SHIFT	4
8127 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_MASK	0x1
8128 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSEM_FLUSH_SHIFT	5
8129 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK		0x1
8130 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT		6
8131 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK	0x1
8132 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT	7
8133 	u8 flags2;
8134 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK	0x3
8135 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT	0
8136 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK	0x3
8137 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT	2
8138 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK	0x3
8139 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT	4
8140 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK	0x3
8141 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT	6
8142 	u8 flags3;
8143 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK		0x3
8144 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT		0
8145 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK		0x3
8146 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT		2
8147 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK		0x3
8148 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT		4
8149 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK	0x3
8150 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT	6
8151 	u8 flags4;
8152 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK	0x3
8153 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT	0
8154 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK	0x3
8155 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT	2
8156 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK	0x3
8157 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT	4
8158 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK	0x3
8159 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT	6
8160 	u8 flags5;
8161 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK	0x3
8162 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT	0
8163 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK	0x3
8164 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT	2
8165 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK	0x3
8166 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT	4
8167 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK	0x3
8168 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT	6
8169 	u8 flags6;
8170 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK	0x3
8171 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT	0
8172 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK	0x3
8173 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT	2
8174 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK	0x3
8175 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT	4
8176 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK	0x3
8177 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT	6
8178 	u8 flags7;
8179 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK		0x3
8180 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT		0
8181 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK		0x3
8182 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT		2
8183 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK		0x3
8184 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT	4
8185 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK		0x1
8186 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT		6
8187 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK		0x1
8188 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT		7
8189 	u8 flags8;
8190 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK		0x1
8191 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT		0
8192 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK		0x1
8193 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT		1
8194 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK		0x1
8195 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT		2
8196 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK		0x1
8197 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT		3
8198 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK		0x1
8199 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT		4
8200 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK	0x1
8201 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT	5
8202 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK		0x1
8203 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT		6
8204 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK		0x1
8205 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT		7
8206 	u8 flags9;
8207 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK	0x1
8208 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT	0
8209 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK	0x1
8210 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT	1
8211 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK	0x1
8212 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT	2
8213 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK	0x1
8214 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT	3
8215 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK	0x1
8216 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT	4
8217 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK	0x1
8218 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT	5
8219 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK	0x1
8220 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT	6
8221 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK	0x1
8222 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT	7
8223 	u8 flags10;
8224 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK		0x1
8225 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT		0
8226 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK		0x1
8227 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT		1
8228 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK		0x1
8229 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT		2
8230 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK		0x1
8231 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT		3
8232 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK	0x1
8233 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT	4
8234 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK		0x1
8235 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT		5
8236 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK		0x1
8237 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT		6
8238 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK		0x1
8239 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT		7
8240 	u8 flags11;
8241 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK		0x1
8242 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT		0
8243 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK		0x1
8244 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT		1
8245 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK		0x1
8246 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT		2
8247 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK		0x1
8248 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT		3
8249 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK		0x1
8250 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT		4
8251 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK		0x1
8252 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT		5
8253 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK	0x1
8254 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT	6
8255 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK		0x1
8256 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT		7
8257 	u8 flags12;
8258 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK		0x1
8259 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT		0
8260 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK		0x1
8261 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT		1
8262 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK	0x1
8263 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT	2
8264 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK	0x1
8265 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT	3
8266 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK		0x1
8267 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT		4
8268 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK		0x1
8269 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT		5
8270 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK		0x1
8271 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT		6
8272 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK		0x1
8273 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT		7
8274 	u8 flags13;
8275 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK		0x1
8276 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT		0
8277 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK		0x1
8278 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT		1
8279 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK	0x1
8280 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT	2
8281 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK	0x1
8282 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT	3
8283 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK	0x1
8284 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT	4
8285 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK	0x1
8286 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT	5
8287 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK	0x1
8288 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT	6
8289 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK	0x1
8290 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT	7
8291 	u8 flags14;
8292 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK		0x1
8293 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT	0
8294 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK		0x1
8295 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT		1
8296 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK	0x3
8297 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT	2
8298 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK		0x1
8299 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT		4
8300 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK	0x1
8301 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT	5
8302 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK		0x3
8303 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT		6
8304 	u8 byte2;
8305 	__le16 physical_q0;
8306 	__le16 word1;
8307 	__le16 word2;
8308 	__le16 word3;
8309 	__le16 word4;
8310 	__le16 word5;
8311 	__le16 conn_dpi;
8312 	u8 byte3;
8313 	u8 byte4;
8314 	u8 byte5;
8315 	u8 byte6;
8316 	__le32 reg0;
8317 	__le32 reg1;
8318 	__le32 reg2;
8319 	__le32 snd_nxt_psn;
8320 	__le32 reg4;
8321 };
8322 
8323 struct e4_mstorm_roce_conn_ag_ctx {
8324 	u8 byte0;
8325 	u8 byte1;
8326 	u8 flags0;
8327 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT0_MASK     0x1
8328 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT    0
8329 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT1_MASK     0x1
8330 #define E4_MSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT    1
8331 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0_MASK      0x3
8332 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT     2
8333 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1_MASK      0x3
8334 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT     4
8335 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2_MASK      0x3
8336 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT     6
8337 	u8 flags1;
8338 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK    0x1
8339 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT   0
8340 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK    0x1
8341 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT   1
8342 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK    0x1
8343 #define E4_MSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT   2
8344 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK  0x1
8345 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3
8346 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK  0x1
8347 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4
8348 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK  0x1
8349 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5
8350 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK  0x1
8351 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 6
8352 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK  0x1
8353 #define E4_MSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7
8354 	__le16 word0;
8355 	__le16 word1;
8356 	__le32 reg0;
8357 	__le32 reg1;
8358 };
8359 
8360 struct e4_mstorm_roce_req_conn_ag_ctx {
8361 	u8 byte0;
8362 	u8 byte1;
8363 	u8 flags0;
8364 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK	0x1
8365 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT	0
8366 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK	0x1
8367 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT	1
8368 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK		0x3
8369 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT	2
8370 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK		0x3
8371 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT	4
8372 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK		0x3
8373 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT	6
8374 	u8 flags1;
8375 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK	0x1
8376 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT	0
8377 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK	0x1
8378 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT	1
8379 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK	0x1
8380 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT	2
8381 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK	0x1
8382 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT	3
8383 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK	0x1
8384 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT	4
8385 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK	0x1
8386 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT	5
8387 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK	0x1
8388 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT	6
8389 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK	0x1
8390 #define E4_MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT	7
8391 	__le16 word0;
8392 	__le16 word1;
8393 	__le32 reg0;
8394 	__le32 reg1;
8395 };
8396 
8397 struct e4_mstorm_roce_resp_conn_ag_ctx {
8398 	u8 byte0;
8399 	u8 byte1;
8400 	u8 flags0;
8401 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK	0x1
8402 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT	0
8403 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK	0x1
8404 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT	1
8405 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK	0x3
8406 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT	2
8407 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK	0x3
8408 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT	4
8409 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK	0x3
8410 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT	6
8411 	u8 flags1;
8412 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK	0x1
8413 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT	0
8414 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK	0x1
8415 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT	1
8416 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK	0x1
8417 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT	2
8418 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK	0x1
8419 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT	3
8420 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK	0x1
8421 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT	4
8422 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK	0x1
8423 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT	5
8424 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK	0x1
8425 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT	6
8426 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK	0x1
8427 #define E4_MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT	7
8428 	__le16 word0;
8429 	__le16 word1;
8430 	__le32 reg0;
8431 	__le32 reg1;
8432 };
8433 
8434 struct e4_tstorm_roce_req_conn_ag_ctx {
8435 	u8 reserved0;
8436 	u8 state;
8437 	u8 flags0;
8438 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK		0x1
8439 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT		0
8440 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_MASK		0x1
8441 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURRED_SHIFT		1
8442 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_MASK	0x1
8443 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURRED_SHIFT	2
8444 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK			0x1
8445 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT			3
8446 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK		0x1
8447 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT		4
8448 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK			0x1
8449 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT			5
8450 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK			0x3
8451 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT			6
8452 	u8 flags1;
8453 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK             0x3
8454 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT            0
8455 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK			0x3
8456 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT		2
8457 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK		0x3
8458 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT		4
8459 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK			0x3
8460 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT		6
8461 	u8 flags2;
8462 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_MASK               0x3
8463 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_SHIFT              0
8464 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK	0x3
8465 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT	2
8466 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK	0x3
8467 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT	4
8468 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK	0x3
8469 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT	6
8470 	u8 flags3;
8471 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK	0x3
8472 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT	0
8473 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK	0x3
8474 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT	2
8475 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK			0x1
8476 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT		4
8477 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK          0x1
8478 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT         5
8479 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK		0x1
8480 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT		6
8481 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK	0x1
8482 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT	7
8483 	u8 flags4;
8484 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK		0x1
8485 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT		0
8486 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_MASK            0x1
8487 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_FORCE_COMP_CF_EN_SHIFT           1
8488 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK		0x1
8489 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT		2
8490 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK	0x1
8491 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT	3
8492 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK		0x1
8493 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT		4
8494 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK	0x1
8495 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT	5
8496 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK	0x1
8497 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT	6
8498 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK			0x1
8499 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT			7
8500 	u8 flags5;
8501 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK		0x1
8502 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT		0
8503 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_DIF_CNT_EN_MASK		0x1
8504 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_DIF_CNT_EN_SHIFT		1
8505 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK		0x1
8506 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT		2
8507 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK		0x1
8508 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT		3
8509 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK		0x1
8510 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT		4
8511 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK	0x1
8512 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT	5
8513 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK		0x1
8514 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT		6
8515 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK		0x1
8516 #define E4_TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT		7
8517 	__le32 dif_rxmit_cnt;
8518 	__le32 snd_nxt_psn;
8519 	__le32 snd_max_psn;
8520 	__le32 orq_prod;
8521 	__le32 reg4;
8522 	__le32 dif_acked_cnt;
8523 	__le32 dif_cnt;
8524 	__le32 reg7;
8525 	__le32 reg8;
8526 	u8 tx_cqe_error_type;
8527 	u8 orq_cache_idx;
8528 	__le16 snd_sq_cons_th;
8529 	u8 byte4;
8530 	u8 byte5;
8531 	__le16 snd_sq_cons;
8532 	__le16 conn_dpi;
8533 	__le16 force_comp_cons;
8534 	__le32 dif_rxmit_acked_cnt;
8535 	__le32 reg10;
8536 };
8537 
8538 struct e4_tstorm_roce_resp_conn_ag_ctx {
8539 	u8 byte0;
8540 	u8 state;
8541 	u8 flags0;
8542 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK		0x1
8543 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT		0
8544 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK	0x1
8545 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT	1
8546 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK			0x1
8547 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT			2
8548 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK			0x1
8549 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT			3
8550 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK		0x1
8551 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT		4
8552 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK			0x1
8553 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT			5
8554 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK			0x3
8555 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT			6
8556 	u8 flags1;
8557 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK            0x3
8558 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT           0
8559 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK	0x3
8560 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT	2
8561 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK		0x3
8562 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT		4
8563 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK	0x3
8564 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT	6
8565 	u8 flags2;
8566 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK                0x3
8567 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT               0
8568 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK		0x3
8569 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT		2
8570 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK		0x3
8571 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT		4
8572 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK		0x3
8573 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT		6
8574 	u8 flags3;
8575 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK		0x3
8576 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT		0
8577 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK		0x3
8578 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT		2
8579 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK		0x1
8580 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT		4
8581 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK         0x1
8582 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT        5
8583 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK	0x1
8584 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT	6
8585 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK		0x1
8586 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT		7
8587 	u8 flags4;
8588 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK		0x1
8589 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT		0
8590 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK             0x1
8591 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT            1
8592 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK			0x1
8593 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT			2
8594 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK			0x1
8595 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT			3
8596 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK			0x1
8597 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT			4
8598 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK			0x1
8599 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT			5
8600 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK			0x1
8601 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT			6
8602 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK			0x1
8603 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT			7
8604 	u8 flags5;
8605 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK		0x1
8606 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT		0
8607 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK		0x1
8608 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT		1
8609 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK		0x1
8610 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT		2
8611 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK		0x1
8612 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT		3
8613 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK		0x1
8614 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT		4
8615 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK		0x1
8616 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT	5
8617 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK		0x1
8618 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT		6
8619 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK		0x1
8620 #define E4_TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT		7
8621 	__le32 psn_and_rxmit_id_echo;
8622 	__le32 reg1;
8623 	__le32 reg2;
8624 	__le32 reg3;
8625 	__le32 reg4;
8626 	__le32 reg5;
8627 	__le32 reg6;
8628 	__le32 reg7;
8629 	__le32 reg8;
8630 	u8 tx_async_error_type;
8631 	u8 byte3;
8632 	__le16 rq_cons;
8633 	u8 byte4;
8634 	u8 byte5;
8635 	__le16 rq_prod;
8636 	__le16 conn_dpi;
8637 	__le16 irq_cons;
8638 	__le32 reg9;
8639 	__le32 reg10;
8640 };
8641 
8642 struct e4_ustorm_roce_req_conn_ag_ctx {
8643 	u8 byte0;
8644 	u8 byte1;
8645 	u8 flags0;
8646 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK	0x1
8647 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT	0
8648 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK	0x1
8649 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT	1
8650 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK		0x3
8651 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT	2
8652 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK		0x3
8653 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT	4
8654 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK		0x3
8655 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT	6
8656 	u8 flags1;
8657 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK		0x3
8658 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT	0
8659 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK		0x3
8660 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT	2
8661 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK		0x3
8662 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT	4
8663 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK		0x3
8664 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT	6
8665 	u8 flags2;
8666 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK	0x1
8667 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT	0
8668 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK	0x1
8669 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT	1
8670 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK	0x1
8671 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT	2
8672 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK	0x1
8673 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT	3
8674 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK	0x1
8675 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT	4
8676 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK	0x1
8677 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT	5
8678 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK	0x1
8679 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT	6
8680 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK	0x1
8681 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT	7
8682 	u8 flags3;
8683 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK	0x1
8684 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT	0
8685 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK	0x1
8686 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT	1
8687 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK	0x1
8688 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT	2
8689 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK	0x1
8690 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT	3
8691 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK	0x1
8692 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT	4
8693 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK	0x1
8694 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT	5
8695 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK	0x1
8696 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT	6
8697 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK	0x1
8698 #define E4_USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT	7
8699 	u8 byte2;
8700 	u8 byte3;
8701 	__le16 word0;
8702 	__le16 word1;
8703 	__le32 reg0;
8704 	__le32 reg1;
8705 	__le32 reg2;
8706 	__le32 reg3;
8707 	__le16 word2;
8708 	__le16 word3;
8709 };
8710 
8711 struct e4_ustorm_roce_resp_conn_ag_ctx {
8712 	u8 byte0;
8713 	u8 byte1;
8714 	u8 flags0;
8715 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK	0x1
8716 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT	0
8717 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK	0x1
8718 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT	1
8719 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK	0x3
8720 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT	2
8721 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK	0x3
8722 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT	4
8723 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK	0x3
8724 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT	6
8725 	u8 flags1;
8726 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK	0x3
8727 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT	0
8728 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK	0x3
8729 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT	2
8730 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK	0x3
8731 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT	4
8732 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK	0x3
8733 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT	6
8734 	u8 flags2;
8735 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK	0x1
8736 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT	0
8737 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK	0x1
8738 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT	1
8739 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK	0x1
8740 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT	2
8741 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK	0x1
8742 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT	3
8743 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK	0x1
8744 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT	4
8745 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK	0x1
8746 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT	5
8747 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK	0x1
8748 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT	6
8749 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK	0x1
8750 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT	7
8751 	u8 flags3;
8752 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK	0x1
8753 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT	0
8754 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK	0x1
8755 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT	1
8756 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK	0x1
8757 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT	2
8758 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK	0x1
8759 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT	3
8760 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK	0x1
8761 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT	4
8762 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK	0x1
8763 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT	5
8764 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK	0x1
8765 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT	6
8766 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK	0x1
8767 #define E4_USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT	7
8768 	u8 byte2;
8769 	u8 byte3;
8770 	__le16 word0;
8771 	__le16 word1;
8772 	__le32 reg0;
8773 	__le32 reg1;
8774 	__le32 reg2;
8775 	__le32 reg3;
8776 	__le16 word2;
8777 	__le16 word3;
8778 };
8779 
8780 struct e4_xstorm_roce_req_conn_ag_ctx {
8781 	u8 reserved0;
8782 	u8 state;
8783 	u8 flags0;
8784 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
8785 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
8786 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK		0x1
8787 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT		1
8788 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK		0x1
8789 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT		2
8790 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
8791 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT	3
8792 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK		0x1
8793 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT		4
8794 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK		0x1
8795 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT		5
8796 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK		0x1
8797 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT		6
8798 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK		0x1
8799 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT		7
8800 	u8 flags1;
8801 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK		0x1
8802 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT		0
8803 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK		0x1
8804 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT		1
8805 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK		0x1
8806 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT		2
8807 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK		0x1
8808 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT		3
8809 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSDM_FLUSH_MASK		0x1
8810 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSDM_FLUSH_SHIFT		4
8811 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSEM_FLUSH_MASK		0x1
8812 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MSEM_FLUSH_SHIFT		5
8813 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK		0x1
8814 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT	6
8815 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK	0x1
8816 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT	7
8817 	u8 flags2;
8818 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK		0x3
8819 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT	0
8820 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK		0x3
8821 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT	2
8822 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK		0x3
8823 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT	4
8824 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK		0x3
8825 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT	6
8826 	u8 flags3;
8827 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK		0x3
8828 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT	0
8829 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK		0x3
8830 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT	2
8831 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK	0x3
8832 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT	4
8833 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK		0x3
8834 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT	6
8835 	u8 flags4;
8836 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_MASK        0x3
8837 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_SHIFT       0
8838 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_MASK     0x3
8839 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_SHIFT    2
8840 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK	0x3
8841 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT	4
8842 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK	0x3
8843 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT	6
8844 	u8 flags5;
8845 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK		0x3
8846 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT		0
8847 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK		0x3
8848 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT		2
8849 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK	0x3
8850 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT	4
8851 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK		0x3
8852 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT		6
8853 	u8 flags6;
8854 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK	0x3
8855 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT	0
8856 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK	0x3
8857 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT	2
8858 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK	0x3
8859 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT	4
8860 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK	0x3
8861 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT	6
8862 	u8 flags7;
8863 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK	0x3
8864 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT	0
8865 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK	0x3
8866 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT	2
8867 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK	0x3
8868 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT	4
8869 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK	0x1
8870 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT	6
8871 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK	0x1
8872 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT	7
8873 	u8 flags8;
8874 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK		0x1
8875 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT		0
8876 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK		0x1
8877 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT		1
8878 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK	0x1
8879 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT	2
8880 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK	0x1
8881 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT	3
8882 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK	0x1
8883 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT	4
8884 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK	0x1
8885 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT	5
8886 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_MASK     0x1
8887 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DIF_ERROR_CF_EN_SHIFT    6
8888 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_MASK  0x1
8889 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SCAN_SQ_FOR_COMP_CF_EN_SHIFT 7
8890 	u8 flags9;
8891 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK		0x1
8892 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT		0
8893 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK		0x1
8894 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT		1
8895 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK		0x1
8896 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT		2
8897 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK		0x1
8898 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT		3
8899 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK	0x1
8900 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT	4
8901 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK		0x1
8902 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT		5
8903 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK		0x1
8904 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT		6
8905 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK		0x1
8906 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT		7
8907 	u8 flags10;
8908 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK		0x1
8909 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT		0
8910 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK		0x1
8911 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT		1
8912 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK		0x1
8913 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT		2
8914 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK		0x1
8915 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT		3
8916 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK	0x1
8917 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT	4
8918 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK		0x1
8919 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT		5
8920 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK		0x1
8921 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT		6
8922 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK		0x1
8923 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT		7
8924 	u8 flags11;
8925 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK		0x1
8926 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT		0
8927 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK		0x1
8928 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT		1
8929 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK		0x1
8930 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT		2
8931 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK		0x1
8932 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT		3
8933 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK		0x1
8934 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT		4
8935 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK	0x1
8936 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT	5
8937 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK	0x1
8938 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT	6
8939 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK		0x1
8940 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT		7
8941 	u8 flags12;
8942 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK		0x1
8943 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT		0
8944 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK		0x1
8945 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT		1
8946 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK	0x1
8947 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT	2
8948 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK	0x1
8949 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT	3
8950 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK	0x1
8951 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT	4
8952 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK		0x1
8953 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT		5
8954 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK	0x1
8955 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT	6
8956 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK	0x1
8957 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT	7
8958 	u8 flags13;
8959 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK		0x1
8960 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT		0
8961 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK		0x1
8962 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT		1
8963 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK	0x1
8964 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT	2
8965 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK	0x1
8966 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT	3
8967 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK	0x1
8968 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT	4
8969 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK	0x1
8970 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT	5
8971 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK	0x1
8972 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT	6
8973 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK	0x1
8974 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT	7
8975 	u8 flags14;
8976 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK	0x1
8977 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT	0
8978 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK		0x1
8979 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT		1
8980 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK	0x3
8981 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT	2
8982 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK		0x1
8983 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT		4
8984 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK	0x1
8985 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT	5
8986 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK		0x3
8987 #define E4_XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT		6
8988 	u8 byte2;
8989 	__le16 physical_q0;
8990 	__le16 word1;
8991 	__le16 sq_cmp_cons;
8992 	__le16 sq_cons;
8993 	__le16 sq_prod;
8994 	__le16 dif_error_first_sq_cons;
8995 	__le16 conn_dpi;
8996 	u8 dif_error_sge_index;
8997 	u8 byte4;
8998 	u8 byte5;
8999 	u8 byte6;
9000 	__le32 lsn;
9001 	__le32 ssn;
9002 	__le32 snd_una_psn;
9003 	__le32 snd_nxt_psn;
9004 	__le32 dif_error_offset;
9005 	__le32 orq_cons_th;
9006 	__le32 orq_cons;
9007 };
9008 
9009 struct e4_xstorm_roce_resp_conn_ag_ctx {
9010 	u8 reserved0;
9011 	u8 state;
9012 	u8 flags0;
9013 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
9014 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
9015 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK		0x1
9016 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT		1
9017 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK		0x1
9018 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT		2
9019 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
9020 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT	3
9021 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK		0x1
9022 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT		4
9023 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK		0x1
9024 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT		5
9025 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK		0x1
9026 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT		6
9027 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK		0x1
9028 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT		7
9029 	u8 flags1;
9030 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK		0x1
9031 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT		0
9032 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK		0x1
9033 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT		1
9034 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK		0x1
9035 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT		2
9036 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK		0x1
9037 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT		3
9038 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSDM_FLUSH_MASK		0x1
9039 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSDM_FLUSH_SHIFT	4
9040 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSEM_FLUSH_MASK		0x1
9041 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_MSEM_FLUSH_SHIFT	5
9042 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK	0x1
9043 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT	6
9044 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK	0x1
9045 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT	7
9046 	u8 flags2;
9047 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK	0x3
9048 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT	0
9049 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK	0x3
9050 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT	2
9051 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK	0x3
9052 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT	4
9053 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK	0x3
9054 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT	6
9055 	u8 flags3;
9056 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK		0x3
9057 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT		0
9058 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK	0x3
9059 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT	2
9060 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK	0x3
9061 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT	4
9062 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK	0x3
9063 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT	6
9064 	u8 flags4;
9065 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK	0x3
9066 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT	0
9067 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK	0x3
9068 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT	2
9069 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK	0x3
9070 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT	4
9071 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK	0x3
9072 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT	6
9073 	u8 flags5;
9074 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK	0x3
9075 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT	0
9076 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK	0x3
9077 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT	2
9078 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK	0x3
9079 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT	4
9080 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK	0x3
9081 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT	6
9082 	u8 flags6;
9083 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK	0x3
9084 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT	0
9085 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK	0x3
9086 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT	2
9087 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK	0x3
9088 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT	4
9089 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK	0x3
9090 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT	6
9091 	u8 flags7;
9092 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK	0x3
9093 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT	0
9094 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK	0x3
9095 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT	2
9096 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK	0x3
9097 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT	4
9098 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK	0x1
9099 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT	6
9100 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK	0x1
9101 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT	7
9102 	u8 flags8;
9103 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK		0x1
9104 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT		0
9105 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK		0x1
9106 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT		1
9107 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK	0x1
9108 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT	2
9109 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK	0x1
9110 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT	3
9111 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK	0x1
9112 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT	4
9113 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK	0x1
9114 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT	5
9115 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK		0x1
9116 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT		6
9117 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK		0x1
9118 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT		7
9119 	u8 flags9;
9120 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK	0x1
9121 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT	0
9122 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK	0x1
9123 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT	1
9124 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK	0x1
9125 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT	2
9126 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK	0x1
9127 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT	3
9128 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK	0x1
9129 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT	4
9130 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK	0x1
9131 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT	5
9132 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK	0x1
9133 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT	6
9134 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK	0x1
9135 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT	7
9136 	u8 flags10;
9137 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK		0x1
9138 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT		0
9139 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK		0x1
9140 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT		1
9141 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK		0x1
9142 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT		2
9143 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK		0x1
9144 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT		3
9145 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK	0x1
9146 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT	4
9147 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK		0x1
9148 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT		5
9149 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK		0x1
9150 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT		6
9151 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK		0x1
9152 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT		7
9153 	u8 flags11;
9154 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK		0x1
9155 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT		0
9156 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK		0x1
9157 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT		1
9158 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK		0x1
9159 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT		2
9160 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK		0x1
9161 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT		3
9162 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK		0x1
9163 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT		4
9164 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK		0x1
9165 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT		5
9166 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK	0x1
9167 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT	6
9168 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK		0x1
9169 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT		7
9170 	u8 flags12;
9171 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK	0x1
9172 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT	0
9173 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_MASK		0x1
9174 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE11EN_SHIFT		1
9175 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK	0x1
9176 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT	2
9177 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK	0x1
9178 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT	3
9179 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK		0x1
9180 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT		4
9181 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK		0x1
9182 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT		5
9183 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK		0x1
9184 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT		6
9185 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK		0x1
9186 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT		7
9187 	u8 flags13;
9188 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK		0x1
9189 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT		0
9190 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK		0x1
9191 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT		1
9192 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK	0x1
9193 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT	2
9194 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK	0x1
9195 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT	3
9196 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK	0x1
9197 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT	4
9198 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK	0x1
9199 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT	5
9200 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK	0x1
9201 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT	6
9202 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK	0x1
9203 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT	7
9204 	u8 flags14;
9205 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK	0x1
9206 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT	0
9207 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK	0x1
9208 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT	1
9209 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK	0x1
9210 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT	2
9211 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK	0x1
9212 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT	3
9213 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK	0x1
9214 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT	4
9215 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK	0x1
9216 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT	5
9217 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK	0x3
9218 #define E4_XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT	6
9219 	u8 byte2;
9220 	__le16 physical_q0;
9221 	__le16 irq_prod_shadow;
9222 	__le16 word2;
9223 	__le16 irq_cons;
9224 	__le16 irq_prod;
9225 	__le16 e5_reserved1;
9226 	__le16 conn_dpi;
9227 	u8 rxmit_opcode;
9228 	u8 byte4;
9229 	u8 byte5;
9230 	u8 byte6;
9231 	__le32 rxmit_psn_and_id;
9232 	__le32 rxmit_bytes_length;
9233 	__le32 psn;
9234 	__le32 reg3;
9235 	__le32 reg4;
9236 	__le32 reg5;
9237 	__le32 msn_and_syndrome;
9238 };
9239 
9240 struct e4_ystorm_roce_conn_ag_ctx {
9241 	u8 byte0;
9242 	u8 byte1;
9243 	u8 flags0;
9244 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT0_MASK     0x1
9245 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT0_SHIFT    0
9246 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT1_MASK     0x1
9247 #define E4_YSTORM_ROCE_CONN_AG_CTX_BIT1_SHIFT    1
9248 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0_MASK      0x3
9249 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0_SHIFT     2
9250 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1_MASK      0x3
9251 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1_SHIFT     4
9252 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2_MASK      0x3
9253 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2_SHIFT     6
9254 	u8 flags1;
9255 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0EN_MASK    0x1
9256 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF0EN_SHIFT   0
9257 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1EN_MASK    0x1
9258 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF1EN_SHIFT   1
9259 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2EN_MASK    0x1
9260 #define E4_YSTORM_ROCE_CONN_AG_CTX_CF2EN_SHIFT   2
9261 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE0EN_MASK  0x1
9262 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE0EN_SHIFT 3
9263 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE1EN_MASK  0x1
9264 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE1EN_SHIFT 4
9265 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE2EN_MASK  0x1
9266 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE2EN_SHIFT 5
9267 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE3EN_MASK  0x1
9268 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE3EN_SHIFT 6
9269 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE4EN_MASK  0x1
9270 #define E4_YSTORM_ROCE_CONN_AG_CTX_RULE4EN_SHIFT 7
9271 	u8 byte2;
9272 	u8 byte3;
9273 	__le16 word0;
9274 	__le32 reg0;
9275 	__le32 reg1;
9276 	__le16 word1;
9277 	__le16 word2;
9278 	__le16 word3;
9279 	__le16 word4;
9280 	__le32 reg2;
9281 	__le32 reg3;
9282 };
9283 
9284 struct e4_ystorm_roce_req_conn_ag_ctx {
9285 	u8 byte0;
9286 	u8 byte1;
9287 	u8 flags0;
9288 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK	0x1
9289 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT	0
9290 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK	0x1
9291 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT	1
9292 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK		0x3
9293 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT	2
9294 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK		0x3
9295 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT	4
9296 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK		0x3
9297 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT	6
9298 	u8 flags1;
9299 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK	0x1
9300 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT	0
9301 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK	0x1
9302 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT	1
9303 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK	0x1
9304 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT	2
9305 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK	0x1
9306 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT	3
9307 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK	0x1
9308 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT	4
9309 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK	0x1
9310 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT	5
9311 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK	0x1
9312 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT	6
9313 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK	0x1
9314 #define E4_YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT	7
9315 	u8 byte2;
9316 	u8 byte3;
9317 	__le16 word0;
9318 	__le32 reg0;
9319 	__le32 reg1;
9320 	__le16 word1;
9321 	__le16 word2;
9322 	__le16 word3;
9323 	__le16 word4;
9324 	__le32 reg2;
9325 	__le32 reg3;
9326 };
9327 
9328 struct e4_ystorm_roce_resp_conn_ag_ctx {
9329 	u8 byte0;
9330 	u8 byte1;
9331 	u8 flags0;
9332 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK	0x1
9333 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT	0
9334 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK	0x1
9335 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT	1
9336 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK	0x3
9337 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT	2
9338 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK	0x3
9339 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT	4
9340 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK	0x3
9341 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT	6
9342 	u8 flags1;
9343 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK	0x1
9344 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT	0
9345 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK	0x1
9346 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT	1
9347 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK	0x1
9348 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT	2
9349 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK	0x1
9350 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT	3
9351 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK	0x1
9352 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT	4
9353 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK	0x1
9354 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT	5
9355 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK	0x1
9356 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT	6
9357 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK	0x1
9358 #define E4_YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT	7
9359 	u8 byte2;
9360 	u8 byte3;
9361 	__le16 word0;
9362 	__le32 reg0;
9363 	__le32 reg1;
9364 	__le16 word1;
9365 	__le16 word2;
9366 	__le16 word3;
9367 	__le16 word4;
9368 	__le32 reg2;
9369 	__le32 reg3;
9370 };
9371 
9372 /* Roce doorbell data */
9373 enum roce_flavor {
9374 	PLAIN_ROCE,
9375 	RROCE_IPV4,
9376 	RROCE_IPV6,
9377 	MAX_ROCE_FLAVOR
9378 };
9379 
9380 /* The iwarp storm context of Ystorm */
9381 struct ystorm_iwarp_conn_st_ctx {
9382 	__le32 reserved[4];
9383 };
9384 
9385 /* The iwarp storm context of Pstorm */
9386 struct pstorm_iwarp_conn_st_ctx {
9387 	__le32 reserved[36];
9388 };
9389 
9390 /* The iwarp storm context of Xstorm */
9391 struct xstorm_iwarp_conn_st_ctx {
9392 	__le32 reserved[48];
9393 };
9394 
9395 struct e4_xstorm_iwarp_conn_ag_ctx {
9396 	u8 reserved0;
9397 	u8 state;
9398 	u8 flags0;
9399 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
9400 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
9401 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK	0x1
9402 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_SHIFT	1
9403 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK	0x1
9404 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_SHIFT	2
9405 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
9406 #define E4_XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT	3
9407 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK		0x1
9408 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT		4
9409 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK	0x1
9410 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT	5
9411 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK		0x1
9412 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT		6
9413 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK		0x1
9414 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT		7
9415 	u8 flags1;
9416 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK				0x1
9417 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT				0
9418 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK				0x1
9419 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT				1
9420 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK				0x1
9421 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT				2
9422 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK				0x1
9423 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT				3
9424 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK				0x1
9425 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT				4
9426 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK				0x1
9427 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT				5
9428 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK				0x1
9429 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT				6
9430 #define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK	0x1
9431 #define E4_XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7
9432 	u8 flags2;
9433 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_MASK			0x3
9434 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT			0
9435 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_MASK			0x3
9436 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT			2
9437 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_MASK			0x3
9438 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT			4
9439 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK		0x3
9440 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT	6
9441 	u8 flags3;
9442 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_MASK	0x3
9443 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT	0
9444 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_MASK	0x3
9445 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT	2
9446 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_MASK	0x3
9447 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT	4
9448 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_MASK	0x3
9449 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT	6
9450 	u8 flags4;
9451 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_MASK	0x3
9452 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT	0
9453 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_MASK	0x3
9454 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9_SHIFT	2
9455 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_MASK	0x3
9456 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT	4
9457 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_MASK	0x3
9458 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT	6
9459 	u8 flags5;
9460 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_MASK		0x3
9461 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT		0
9462 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_MASK		0x3
9463 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT		2
9464 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK	0x3
9465 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT	4
9466 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_MASK		0x3
9467 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT		6
9468 	u8 flags6;
9469 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK	0x3
9470 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0
9471 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_MASK				0x3
9472 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT				2
9473 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_MASK				0x3
9474 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT				4
9475 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK			0x3
9476 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT			6
9477 	u8 flags7;
9478 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK	0x3
9479 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT	0
9480 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK	0x3
9481 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT	2
9482 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK	0x3
9483 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT	4
9484 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK		0x1
9485 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT		6
9486 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK		0x1
9487 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT		7
9488 	u8 flags8;
9489 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK			0x1
9490 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT			0
9491 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK	0x1
9492 #define E4_XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT	1
9493 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK			0x1
9494 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT			2
9495 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK			0x1
9496 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT			3
9497 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK			0x1
9498 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT			4
9499 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK			0x1
9500 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT			5
9501 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK			0x1
9502 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT			6
9503 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK			0x1
9504 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT			7
9505 	u8 flags9;
9506 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK				0x1
9507 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT			0
9508 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK				0x1
9509 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT			1
9510 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK				0x1
9511 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT			2
9512 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK				0x1
9513 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT			3
9514 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK			0x1
9515 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT		4
9516 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK				0x1
9517 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT			5
9518 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1
9519 #define E4_XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6
9520 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK				0x1
9521 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT			7
9522 	u8 flags10;
9523 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK			0x1
9524 #define E4_XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT		0
9525 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK		0x1
9526 #define E4_XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT		1
9527 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK		0x1
9528 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT		2
9529 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK		0x1
9530 #define E4_XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT		3
9531 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK		0x1
9532 #define E4_XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT		4
9533 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_MASK               0x1
9534 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_EN_SHIFT              5
9535 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK		0x1
9536 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT		6
9537 #define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK	0x1
9538 #define E4_XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT	7
9539 	u8 flags11;
9540 #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK	0x1
9541 #define E4_XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT	0
9542 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK	0x1
9543 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT	1
9544 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK	0x1
9545 #define E4_XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT	2
9546 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK	0x1
9547 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT	3
9548 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK	0x1
9549 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT	4
9550 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK	0x1
9551 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT	5
9552 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK	0x1
9553 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT	6
9554 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK	0x1
9555 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT	7
9556 	u8 flags12;
9557 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK	0x1
9558 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT	0
9559 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK		0x1
9560 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT		1
9561 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK		0x1
9562 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT		2
9563 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK		0x1
9564 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT		3
9565 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK	0x1
9566 #define E4_XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT	4
9567 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK		0x1
9568 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT		5
9569 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK		0x1
9570 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT		6
9571 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK		0x1
9572 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT		7
9573 	u8 flags13;
9574 #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK	0x1
9575 #define E4_XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT	0
9576 #define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK	0x1
9577 #define E4_XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT	1
9578 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK	0x1
9579 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT	2
9580 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK		0x1
9581 #define E4_XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT		3
9582 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK		0x1
9583 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT		4
9584 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK	0x1
9585 #define E4_XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT	5
9586 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK		0x1
9587 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT		6
9588 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK		0x1
9589 #define E4_XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT		7
9590 	u8 flags14;
9591 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK		0x1
9592 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT		0
9593 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK		0x1
9594 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT		1
9595 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK		0x1
9596 #define E4_XSTORM_IWARP_CONN_AG_CTX_BIT18_SHIFT		2
9597 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK	0x1
9598 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_SHIFT	3
9599 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK	0x1
9600 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_SHIFT	4
9601 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK	0x1
9602 #define E4_XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_SHIFT	5
9603 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_MASK	0x3
9604 #define E4_XSTORM_IWARP_CONN_AG_CTX_SEND_TERMINATE_CF_SHIFT	6
9605 	u8 byte2;
9606 	__le16 physical_q0;
9607 	__le16 physical_q1;
9608 	__le16 sq_comp_cons;
9609 	__le16 sq_tx_cons;
9610 	__le16 sq_prod;
9611 	__le16 word5;
9612 	__le16 conn_dpi;
9613 	u8 byte3;
9614 	u8 byte4;
9615 	u8 byte5;
9616 	u8 byte6;
9617 	__le32 reg0;
9618 	__le32 reg1;
9619 	__le32 reg2;
9620 	__le32 more_to_send_seq;
9621 	__le32 reg4;
9622 	__le32 rewinded_snd_max_or_term_opcode;
9623 	__le32 rd_msn;
9624 	__le16 irq_prod_via_msdm;
9625 	__le16 irq_cons;
9626 	__le16 hq_cons_th_or_mpa_data;
9627 	__le16 hq_cons;
9628 	__le32 atom_msn;
9629 	__le32 orq_cons;
9630 	__le32 orq_cons_th;
9631 	u8 byte7;
9632 	u8 wqe_data_pad_bytes;
9633 	u8 max_ord;
9634 	u8 former_hq_prod;
9635 	u8 irq_prod_via_msem;
9636 	u8 byte12;
9637 	u8 max_pkt_pdu_size_lo;
9638 	u8 max_pkt_pdu_size_hi;
9639 	u8 byte15;
9640 	u8 e5_reserved;
9641 	__le16 e5_reserved4;
9642 	__le32 reg10;
9643 	__le32 reg11;
9644 	__le32 shared_queue_page_addr_lo;
9645 	__le32 shared_queue_page_addr_hi;
9646 	__le32 reg14;
9647 	__le32 reg15;
9648 	__le32 reg16;
9649 	__le32 reg17;
9650 };
9651 
9652 struct e4_tstorm_iwarp_conn_ag_ctx {
9653 	u8 reserved0;
9654 	u8 state;
9655 	u8 flags0;
9656 #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
9657 #define E4_TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
9658 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK		0x1
9659 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT		1
9660 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK		0x1
9661 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT		2
9662 #define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_MASK  0x1
9663 #define E4_TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_OR_TERMINATE_SENT_SHIFT 3
9664 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK		0x1
9665 #define E4_TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT		4
9666 #define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK	0x1
9667 #define E4_TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT	5
9668 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_MASK		0x3
9669 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT		6
9670 	u8 flags1;
9671 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK		0x3
9672 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT		0
9673 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK		0x3
9674 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_SHIFT	2
9675 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK		0x3
9676 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT	4
9677 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_MASK			0x3
9678 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT			6
9679 	u8 flags2;
9680 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_MASK	0x3
9681 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT	0
9682 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_MASK	0x3
9683 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT	2
9684 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_MASK	0x3
9685 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT	4
9686 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_MASK	0x3
9687 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT	6
9688 	u8 flags3;
9689 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_MASK 0x3
9690 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPLETE_SHIFT 0
9691 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK	0x3
9692 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT	2
9693 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK				0x1
9694 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT				4
9695 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK			0x1
9696 #define E4_TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT			5
9697 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK		0x1
9698 #define E4_TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_SHIFT		6
9699 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK		0x1
9700 #define E4_TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT		7
9701 	u8 flags4;
9702 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK				0x1
9703 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT				0
9704 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK				0x1
9705 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT				1
9706 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK				0x1
9707 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT				2
9708 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK				0x1
9709 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT				3
9710 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK				0x1
9711 #define E4_TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT				4
9712 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_MASK 0x1
9713 #define	E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_AND_TCP_HANDSHAKE_COMPL_EN_SHIFT 5
9714 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK	0x1
9715 #define E4_TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT	6
9716 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK			0x1
9717 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT			7
9718 	u8 flags5;
9719 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK		0x1
9720 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT		0
9721 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK		0x1
9722 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT		1
9723 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK		0x1
9724 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT		2
9725 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK		0x1
9726 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT		3
9727 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK		0x1
9728 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT		4
9729 #define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK	0x1
9730 #define E4_TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT	5
9731 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK		0x1
9732 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT		6
9733 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK		0x1
9734 #define E4_TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT		7
9735 	__le32 reg0;
9736 	__le32 reg1;
9737 	__le32 unaligned_nxt_seq;
9738 	__le32 reg3;
9739 	__le32 reg4;
9740 	__le32 reg5;
9741 	__le32 reg6;
9742 	__le32 reg7;
9743 	__le32 reg8;
9744 	u8 orq_cache_idx;
9745 	u8 hq_prod;
9746 	__le16 sq_tx_cons_th;
9747 	u8 orq_prod;
9748 	u8 irq_cons;
9749 	__le16 sq_tx_cons;
9750 	__le16 conn_dpi;
9751 	__le16 rq_prod;
9752 	__le32 snd_seq;
9753 	__le32 last_hq_sequence;
9754 };
9755 
9756 /* The iwarp storm context of Tstorm */
9757 struct tstorm_iwarp_conn_st_ctx {
9758 	__le32 reserved[60];
9759 };
9760 
9761 /* The iwarp storm context of Mstorm */
9762 struct mstorm_iwarp_conn_st_ctx {
9763 	__le32 reserved[32];
9764 };
9765 
9766 /* The iwarp storm context of Ustorm */
9767 struct ustorm_iwarp_conn_st_ctx {
9768 	struct regpair reserved[14];
9769 };
9770 
9771 /* iwarp connection context */
9772 struct e4_iwarp_conn_context {
9773 	struct ystorm_iwarp_conn_st_ctx ystorm_st_context;
9774 	struct regpair ystorm_st_padding[2];
9775 	struct pstorm_iwarp_conn_st_ctx pstorm_st_context;
9776 	struct regpair pstorm_st_padding[2];
9777 	struct xstorm_iwarp_conn_st_ctx xstorm_st_context;
9778 	struct e4_xstorm_iwarp_conn_ag_ctx xstorm_ag_context;
9779 	struct e4_tstorm_iwarp_conn_ag_ctx tstorm_ag_context;
9780 	struct timers_context timer_context;
9781 	struct e4_ustorm_rdma_conn_ag_ctx ustorm_ag_context;
9782 	struct tstorm_iwarp_conn_st_ctx tstorm_st_context;
9783 	struct regpair tstorm_st_padding[2];
9784 	struct mstorm_iwarp_conn_st_ctx mstorm_st_context;
9785 	struct ustorm_iwarp_conn_st_ctx ustorm_st_context;
9786 	struct regpair ustorm_st_padding[2];
9787 };
9788 
9789 /* iWARP create QP params passed by driver to FW in CreateQP Request Ramrod */
9790 struct iwarp_create_qp_ramrod_data {
9791 	u8 flags;
9792 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK	0x1
9793 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT	0
9794 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK		0x1
9795 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_SHIFT		1
9796 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK		0x1
9797 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT		2
9798 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK		0x1
9799 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT		3
9800 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK		0x1
9801 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_SHIFT		4
9802 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK		0x1
9803 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_SHIFT		5
9804 #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_MASK	0x1
9805 #define IWARP_CREATE_QP_RAMROD_DATA_LOW_LATENCY_QUEUE_EN_SHIFT	6
9806 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK		0x1
9807 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_SHIFT		7
9808 	u8 reserved1;
9809 	__le16 pd;
9810 	__le16 sq_num_pages;
9811 	__le16 rq_num_pages;
9812 	__le32 reserved3[2];
9813 	struct regpair qp_handle_for_cqe;
9814 	struct rdma_srq_id srq_id;
9815 	__le32 cq_cid_for_sq;
9816 	__le32 cq_cid_for_rq;
9817 	__le16 dpi;
9818 	__le16 physical_q0;
9819 	__le16 physical_q1;
9820 	u8 reserved2[6];
9821 };
9822 
9823 /* iWARP completion queue types */
9824 enum iwarp_eqe_async_opcode {
9825 	IWARP_EVENT_TYPE_ASYNC_CONNECT_COMPLETE,
9826 	IWARP_EVENT_TYPE_ASYNC_ENHANCED_MPA_REPLY_ARRIVED,
9827 	IWARP_EVENT_TYPE_ASYNC_MPA_HANDSHAKE_COMPLETE,
9828 	IWARP_EVENT_TYPE_ASYNC_CID_CLEANED,
9829 	IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED,
9830 	IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE,
9831 	IWARP_EVENT_TYPE_ASYNC_CQ_OVERFLOW,
9832 	IWARP_EVENT_TYPE_ASYNC_SRQ_EMPTY,
9833 	IWARP_EVENT_TYPE_ASYNC_SRQ_LIMIT,
9834 	MAX_IWARP_EQE_ASYNC_OPCODE
9835 };
9836 
9837 struct iwarp_eqe_data_mpa_async_completion {
9838 	__le16 ulp_data_len;
9839 	u8 rtr_type_sent;
9840 	u8 reserved[5];
9841 };
9842 
9843 struct iwarp_eqe_data_tcp_async_completion {
9844 	__le16 ulp_data_len;
9845 	u8 mpa_handshake_mode;
9846 	u8 reserved[5];
9847 };
9848 
9849 /* iWARP completion queue types */
9850 enum iwarp_eqe_sync_opcode {
9851 	IWARP_EVENT_TYPE_TCP_OFFLOAD =
9852 	11,
9853 	IWARP_EVENT_TYPE_MPA_OFFLOAD,
9854 	IWARP_EVENT_TYPE_MPA_OFFLOAD_SEND_RTR,
9855 	IWARP_EVENT_TYPE_CREATE_QP,
9856 	IWARP_EVENT_TYPE_QUERY_QP,
9857 	IWARP_EVENT_TYPE_MODIFY_QP,
9858 	IWARP_EVENT_TYPE_DESTROY_QP,
9859 	IWARP_EVENT_TYPE_ABORT_TCP_OFFLOAD,
9860 	MAX_IWARP_EQE_SYNC_OPCODE
9861 };
9862 
9863 /* iWARP EQE completion status */
9864 enum iwarp_fw_return_code {
9865 	IWARP_CONN_ERROR_TCP_CONNECT_INVALID_PACKET = 6,
9866 	IWARP_CONN_ERROR_TCP_CONNECTION_RST,
9867 	IWARP_CONN_ERROR_TCP_CONNECT_TIMEOUT,
9868 	IWARP_CONN_ERROR_MPA_ERROR_REJECT,
9869 	IWARP_CONN_ERROR_MPA_NOT_SUPPORTED_VER,
9870 	IWARP_CONN_ERROR_MPA_RST,
9871 	IWARP_CONN_ERROR_MPA_FIN,
9872 	IWARP_CONN_ERROR_MPA_RTR_MISMATCH,
9873 	IWARP_CONN_ERROR_MPA_INSUF_IRD,
9874 	IWARP_CONN_ERROR_MPA_INVALID_PACKET,
9875 	IWARP_CONN_ERROR_MPA_LOCAL_ERROR,
9876 	IWARP_CONN_ERROR_MPA_TIMEOUT,
9877 	IWARP_CONN_ERROR_MPA_TERMINATE,
9878 	IWARP_QP_IN_ERROR_GOOD_CLOSE,
9879 	IWARP_QP_IN_ERROR_BAD_CLOSE,
9880 	IWARP_EXCEPTION_DETECTED_LLP_CLOSED,
9881 	IWARP_EXCEPTION_DETECTED_LLP_RESET,
9882 	IWARP_EXCEPTION_DETECTED_IRQ_FULL,
9883 	IWARP_EXCEPTION_DETECTED_RQ_EMPTY,
9884 	IWARP_EXCEPTION_DETECTED_SRQ_EMPTY,
9885 	IWARP_EXCEPTION_DETECTED_SRQ_LIMIT,
9886 	IWARP_EXCEPTION_DETECTED_LLP_TIMEOUT,
9887 	IWARP_EXCEPTION_DETECTED_REMOTE_PROTECTION_ERROR,
9888 	IWARP_EXCEPTION_DETECTED_CQ_OVERFLOW,
9889 	IWARP_EXCEPTION_DETECTED_LOCAL_CATASTROPHIC,
9890 	IWARP_EXCEPTION_DETECTED_LOCAL_ACCESS_ERROR,
9891 	IWARP_EXCEPTION_DETECTED_REMOTE_OPERATION_ERROR,
9892 	IWARP_EXCEPTION_DETECTED_TERMINATE_RECEIVED,
9893 	MAX_IWARP_FW_RETURN_CODE
9894 };
9895 
9896 /* unaligned opaque data received from LL2 */
9897 struct iwarp_init_func_params {
9898 	u8 ll2_ooo_q_index;
9899 	u8 reserved1[7];
9900 };
9901 
9902 /* iwarp func init ramrod data */
9903 struct iwarp_init_func_ramrod_data {
9904 	struct rdma_init_func_ramrod_data rdma;
9905 	struct tcp_init_params tcp;
9906 	struct iwarp_init_func_params iwarp;
9907 };
9908 
9909 /* iWARP QP - possible states to transition to */
9910 enum iwarp_modify_qp_new_state_type {
9911 	IWARP_MODIFY_QP_STATE_CLOSING = 1,
9912 	IWARP_MODIFY_QP_STATE_ERROR = 2,
9913 	MAX_IWARP_MODIFY_QP_NEW_STATE_TYPE
9914 };
9915 
9916 /* iwarp modify qp responder ramrod data */
9917 struct iwarp_modify_qp_ramrod_data {
9918 	__le16 transition_to_state;
9919 	__le16 flags;
9920 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK		0x1
9921 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT		0
9922 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK		0x1
9923 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT		1
9924 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK		0x1
9925 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_SHIFT		2
9926 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK		0x1
9927 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_SHIFT	3
9928 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK	0x1
9929 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT	4
9930 #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_MASK	0x1
9931 #define IWARP_MODIFY_QP_RAMROD_DATA_PHYSICAL_QUEUE_FLG_SHIFT	5
9932 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK		0x3FF
9933 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_SHIFT		6
9934 	__le16 physical_q0;
9935 	__le16 physical_q1;
9936 	__le32 reserved1[10];
9937 };
9938 
9939 /* MPA params for Enhanced mode */
9940 struct mpa_rq_params {
9941 	__le32 ird;
9942 	__le32 ord;
9943 };
9944 
9945 /* MPA host Address-Len for private data */
9946 struct mpa_ulp_buffer {
9947 	struct regpair addr;
9948 	__le16 len;
9949 	__le16 reserved[3];
9950 };
9951 
9952 /* iWARP MPA offload params common to Basic and Enhanced modes */
9953 struct mpa_outgoing_params {
9954 	u8 crc_needed;
9955 	u8 reject;
9956 	u8 reserved[6];
9957 	struct mpa_rq_params out_rq;
9958 	struct mpa_ulp_buffer outgoing_ulp_buffer;
9959 };
9960 
9961 /* iWARP MPA offload params passed by driver to FW in MPA Offload Request
9962  * Ramrod.
9963  */
9964 struct iwarp_mpa_offload_ramrod_data {
9965 	struct mpa_outgoing_params common;
9966 	__le32 tcp_cid;
9967 	u8 mode;
9968 	u8 tcp_connect_side;
9969 	u8 rtr_pref;
9970 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_MASK	0x7
9971 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT	0
9972 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK		0x1F
9973 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_SHIFT		3
9974 	u8 reserved2;
9975 	struct mpa_ulp_buffer incoming_ulp_buffer;
9976 	struct regpair async_eqe_output_buf;
9977 	struct regpair handle_for_async;
9978 	struct regpair shared_queue_addr;
9979 	__le16 rcv_wnd;
9980 	u8 stats_counter_id;
9981 	u8 reserved3[13];
9982 };
9983 
9984 /* iWARP TCP connection offload params passed by driver to FW */
9985 struct iwarp_offload_params {
9986 	struct mpa_ulp_buffer incoming_ulp_buffer;
9987 	struct regpair async_eqe_output_buf;
9988 	struct regpair handle_for_async;
9989 	__le16 physical_q0;
9990 	__le16 physical_q1;
9991 	u8 stats_counter_id;
9992 	u8 mpa_mode;
9993 	u8 reserved[10];
9994 };
9995 
9996 /* iWARP query QP output params */
9997 struct iwarp_query_qp_output_params {
9998 	__le32 flags;
9999 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK	0x1
10000 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT	0
10001 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_MASK	0x7FFFFFFF
10002 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_SHIFT	1
10003 	u8 reserved1[4];
10004 };
10005 
10006 /* iWARP query QP ramrod data */
10007 struct iwarp_query_qp_ramrod_data {
10008 	struct regpair output_params_addr;
10009 };
10010 
10011 /* iWARP Ramrod Command IDs */
10012 enum iwarp_ramrod_cmd_id {
10013 	IWARP_RAMROD_CMD_ID_TCP_OFFLOAD = 11,
10014 	IWARP_RAMROD_CMD_ID_MPA_OFFLOAD,
10015 	IWARP_RAMROD_CMD_ID_MPA_OFFLOAD_SEND_RTR,
10016 	IWARP_RAMROD_CMD_ID_CREATE_QP,
10017 	IWARP_RAMROD_CMD_ID_QUERY_QP,
10018 	IWARP_RAMROD_CMD_ID_MODIFY_QP,
10019 	IWARP_RAMROD_CMD_ID_DESTROY_QP,
10020 	IWARP_RAMROD_CMD_ID_ABORT_TCP_OFFLOAD,
10021 	MAX_IWARP_RAMROD_CMD_ID
10022 };
10023 
10024 /* Per PF iWARP retransmit path statistics */
10025 struct iwarp_rxmit_stats_drv {
10026 	struct regpair tx_go_to_slow_start_event_cnt;
10027 	struct regpair tx_fast_retransmit_event_cnt;
10028 };
10029 
10030 /* iWARP and TCP connection offload params passed by driver to FW in iWARP
10031  * offload ramrod.
10032  */
10033 struct iwarp_tcp_offload_ramrod_data {
10034 	struct tcp_offload_params_opt2 tcp;
10035 	struct iwarp_offload_params iwarp;
10036 };
10037 
10038 /* iWARP MPA negotiation types */
10039 enum mpa_negotiation_mode {
10040 	MPA_NEGOTIATION_TYPE_BASIC = 1,
10041 	MPA_NEGOTIATION_TYPE_ENHANCED = 2,
10042 	MAX_MPA_NEGOTIATION_MODE
10043 };
10044 
10045 /* iWARP MPA Enhanced mode RTR types */
10046 enum mpa_rtr_type {
10047 	MPA_RTR_TYPE_NONE = 0,
10048 	MPA_RTR_TYPE_ZERO_SEND = 1,
10049 	MPA_RTR_TYPE_ZERO_WRITE = 2,
10050 	MPA_RTR_TYPE_ZERO_SEND_AND_WRITE = 3,
10051 	MPA_RTR_TYPE_ZERO_READ = 4,
10052 	MPA_RTR_TYPE_ZERO_SEND_AND_READ = 5,
10053 	MPA_RTR_TYPE_ZERO_WRITE_AND_READ = 6,
10054 	MPA_RTR_TYPE_ZERO_SEND_AND_WRITE_AND_READ = 7,
10055 	MAX_MPA_RTR_TYPE
10056 };
10057 
10058 /* unaligned opaque data received from LL2 */
10059 struct unaligned_opaque_data {
10060 	__le16 first_mpa_offset;
10061 	u8 tcp_payload_offset;
10062 	u8 flags;
10063 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK	0x1
10064 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT	0
10065 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK		0x1
10066 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_SHIFT		1
10067 #define UNALIGNED_OPAQUE_DATA_RESERVED_MASK			0x3F
10068 #define UNALIGNED_OPAQUE_DATA_RESERVED_SHIFT			2
10069 	__le32 cid;
10070 };
10071 
10072 struct e4_mstorm_iwarp_conn_ag_ctx {
10073 	u8 reserved;
10074 	u8 state;
10075 	u8 flags0;
10076 #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK		0x1
10077 #define E4_MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT		0
10078 #define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK			0x1
10079 #define E4_MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT			1
10080 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK	0x3
10081 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT	2
10082 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_MASK			0x3
10083 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT			4
10084 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_MASK			0x3
10085 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT			6
10086 	u8 flags1;
10087 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK	0x1
10088 #define E4_MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT	0
10089 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK			0x1
10090 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT			1
10091 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK			0x1
10092 #define E4_MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT			2
10093 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK		0x1
10094 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT		3
10095 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK		0x1
10096 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT		4
10097 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK		0x1
10098 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT		5
10099 #define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK		0x1
10100 #define E4_MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT		6
10101 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK		0x1
10102 #define E4_MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT		7
10103 	__le16 rcq_cons;
10104 	__le16 rcq_cons_th;
10105 	__le32 reg0;
10106 	__le32 reg1;
10107 };
10108 
10109 struct e4_ustorm_iwarp_conn_ag_ctx {
10110 	u8 reserved;
10111 	u8 byte1;
10112 	u8 flags0;
10113 #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
10114 #define E4_USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
10115 #define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_MASK		0x1
10116 #define E4_USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT		1
10117 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0_MASK		0x3
10118 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT		2
10119 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1_MASK		0x3
10120 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT		4
10121 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2_MASK		0x3
10122 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT		6
10123 	u8 flags1;
10124 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_MASK		0x3
10125 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT		0
10126 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK	0x3
10127 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT	2
10128 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK	0x3
10129 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT	4
10130 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6_MASK		0x3
10131 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT		6
10132 	u8 flags2;
10133 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK			0x1
10134 #define E4_USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT			0
10135 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK			0x1
10136 #define E4_USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT			1
10137 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK			0x1
10138 #define E4_USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT			2
10139 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK			0x1
10140 #define E4_USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT			3
10141 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK	0x1
10142 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT	4
10143 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK		0x1
10144 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT		5
10145 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK			0x1
10146 #define E4_USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT			6
10147 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK		0x1
10148 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT		7
10149 	u8 flags3;
10150 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK		0x1
10151 #define E4_USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT		0
10152 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK	0x1
10153 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT	1
10154 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK	0x1
10155 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT	2
10156 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK	0x1
10157 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT	3
10158 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK	0x1
10159 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT	4
10160 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK	0x1
10161 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT	5
10162 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK	0x1
10163 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT	6
10164 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK	0x1
10165 #define E4_USTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT	7
10166 	u8 byte2;
10167 	u8 byte3;
10168 	__le16 word0;
10169 	__le16 word1;
10170 	__le32 cq_cons;
10171 	__le32 cq_se_prod;
10172 	__le32 cq_prod;
10173 	__le32 reg3;
10174 	__le16 word2;
10175 	__le16 word3;
10176 };
10177 
10178 struct e4_ystorm_iwarp_conn_ag_ctx {
10179 	u8 byte0;
10180 	u8 byte1;
10181 	u8 flags0;
10182 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK	0x1
10183 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT	0
10184 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK	0x1
10185 #define E4_YSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT	1
10186 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_MASK	0x3
10187 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT	2
10188 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_MASK	0x3
10189 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT	4
10190 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_MASK	0x3
10191 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT	6
10192 	u8 flags1;
10193 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK		0x1
10194 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT		0
10195 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK		0x1
10196 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT		1
10197 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK		0x1
10198 #define E4_YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT		2
10199 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK	0x1
10200 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT	3
10201 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK	0x1
10202 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT	4
10203 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK	0x1
10204 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT	5
10205 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK	0x1
10206 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT	6
10207 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK	0x1
10208 #define E4_YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT	7
10209 	u8 byte2;
10210 	u8 byte3;
10211 	__le16 word0;
10212 	__le32 reg0;
10213 	__le32 reg1;
10214 	__le16 word1;
10215 	__le16 word2;
10216 	__le16 word3;
10217 	__le16 word4;
10218 	__le32 reg2;
10219 	__le32 reg3;
10220 };
10221 
10222 /* The fcoe storm context of Ystorm */
10223 struct ystorm_fcoe_conn_st_ctx {
10224 	u8 func_mode;
10225 	u8 cos;
10226 	u8 conf_version;
10227 	u8 eth_hdr_size;
10228 	__le16 stat_ram_addr;
10229 	__le16 mtu;
10230 	__le16 max_fc_payload_len;
10231 	__le16 tx_max_fc_pay_len;
10232 	u8 fcp_cmd_size;
10233 	u8 fcp_rsp_size;
10234 	__le16 mss;
10235 	struct regpair reserved;
10236 	__le16 min_frame_size;
10237 	u8 protection_info_flags;
10238 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK		0x1
10239 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT	0
10240 #define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK			0x1
10241 #define YSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT			1
10242 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK			0x3F
10243 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_SHIFT			2
10244 	u8 dst_protection_per_mss;
10245 	u8 src_protection_per_mss;
10246 	u8 ptu_log_page_size;
10247 	u8 flags;
10248 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK	0x1
10249 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT	0
10250 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK	0x1
10251 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT	1
10252 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK		0x3F
10253 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT		2
10254 	u8 fcp_xfer_size;
10255 };
10256 
10257 /* FCoE 16-bits vlan structure */
10258 struct fcoe_vlan_fields {
10259 	__le16 fields;
10260 #define FCOE_VLAN_FIELDS_VID_MASK	0xFFF
10261 #define FCOE_VLAN_FIELDS_VID_SHIFT	0
10262 #define FCOE_VLAN_FIELDS_CLI_MASK	0x1
10263 #define FCOE_VLAN_FIELDS_CLI_SHIFT	12
10264 #define FCOE_VLAN_FIELDS_PRI_MASK	0x7
10265 #define FCOE_VLAN_FIELDS_PRI_SHIFT	13
10266 };
10267 
10268 /* FCoE 16-bits vlan union */
10269 union fcoe_vlan_field_union {
10270 	struct fcoe_vlan_fields fields;
10271 	__le16 val;
10272 };
10273 
10274 /* FCoE 16-bits vlan, vif union */
10275 union fcoe_vlan_vif_field_union {
10276 	union fcoe_vlan_field_union vlan;
10277 	__le16 vif;
10278 };
10279 
10280 /* Ethernet context section */
10281 struct pstorm_fcoe_eth_context_section {
10282 	u8 remote_addr_3;
10283 	u8 remote_addr_2;
10284 	u8 remote_addr_1;
10285 	u8 remote_addr_0;
10286 	u8 local_addr_1;
10287 	u8 local_addr_0;
10288 	u8 remote_addr_5;
10289 	u8 remote_addr_4;
10290 	u8 local_addr_5;
10291 	u8 local_addr_4;
10292 	u8 local_addr_3;
10293 	u8 local_addr_2;
10294 	union fcoe_vlan_vif_field_union vif_outer_vlan;
10295 	__le16 vif_outer_eth_type;
10296 	union fcoe_vlan_vif_field_union inner_vlan;
10297 	__le16 inner_eth_type;
10298 };
10299 
10300 /* The fcoe storm context of Pstorm */
10301 struct pstorm_fcoe_conn_st_ctx {
10302 	u8 func_mode;
10303 	u8 cos;
10304 	u8 conf_version;
10305 	u8 rsrv;
10306 	__le16 stat_ram_addr;
10307 	__le16 mss;
10308 	struct regpair abts_cleanup_addr;
10309 	struct pstorm_fcoe_eth_context_section eth;
10310 	u8 sid_2;
10311 	u8 sid_1;
10312 	u8 sid_0;
10313 	u8 flags;
10314 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK			0x1
10315 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT		0
10316 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK		0x1
10317 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT	1
10318 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK		0x1
10319 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT		2
10320 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK		0x1
10321 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT		3
10322 #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_MASK		0x1
10323 #define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_SHIFT		4
10324 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK			0x7
10325 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT			5
10326 	u8 did_2;
10327 	u8 did_1;
10328 	u8 did_0;
10329 	u8 src_mac_index;
10330 	__le16 rec_rr_tov_val;
10331 	u8 q_relative_offset;
10332 	u8 reserved1;
10333 };
10334 
10335 /* The fcoe storm context of Xstorm */
10336 struct xstorm_fcoe_conn_st_ctx {
10337 	u8 func_mode;
10338 	u8 src_mac_index;
10339 	u8 conf_version;
10340 	u8 cached_wqes_avail;
10341 	__le16 stat_ram_addr;
10342 	u8 flags;
10343 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK		0x1
10344 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT		0
10345 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK		0x1
10346 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT		1
10347 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK	0x1
10348 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_SHIFT	2
10349 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK		0x3
10350 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT	3
10351 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK			0x7
10352 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT			5
10353 	u8 cached_wqes_offset;
10354 	u8 reserved2;
10355 	u8 eth_hdr_size;
10356 	u8 seq_id;
10357 	u8 max_conc_seqs;
10358 	__le16 num_pages_in_pbl;
10359 	__le16 reserved;
10360 	struct regpair sq_pbl_addr;
10361 	struct regpair sq_curr_page_addr;
10362 	struct regpair sq_next_page_addr;
10363 	struct regpair xferq_pbl_addr;
10364 	struct regpair xferq_curr_page_addr;
10365 	struct regpair xferq_next_page_addr;
10366 	struct regpair respq_pbl_addr;
10367 	struct regpair respq_curr_page_addr;
10368 	struct regpair respq_next_page_addr;
10369 	__le16 mtu;
10370 	__le16 tx_max_fc_pay_len;
10371 	__le16 max_fc_payload_len;
10372 	__le16 min_frame_size;
10373 	__le16 sq_pbl_next_index;
10374 	__le16 respq_pbl_next_index;
10375 	u8 fcp_cmd_byte_credit;
10376 	u8 fcp_rsp_byte_credit;
10377 	__le16 protection_info;
10378 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK		0x1
10379 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT		0
10380 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK		0x1
10381 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT	1
10382 #define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK			0x1
10383 #define XSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT			2
10384 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK		0x1
10385 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT	3
10386 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK			0xF
10387 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_SHIFT			4
10388 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK	0xFF
10389 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_SHIFT	8
10390 	__le16 xferq_pbl_next_index;
10391 	__le16 page_size;
10392 	u8 mid_seq;
10393 	u8 fcp_xfer_byte_credit;
10394 	u8 reserved1[2];
10395 	struct fcoe_wqe cached_wqes[16];
10396 };
10397 
10398 struct e4_xstorm_fcoe_conn_ag_ctx {
10399 	u8 reserved0;
10400 	u8 state;
10401 	u8 flags0;
10402 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
10403 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
10404 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK	0x1
10405 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT	1
10406 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK	0x1
10407 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT	2
10408 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
10409 #define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT	3
10410 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK	0x1
10411 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT	4
10412 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK	0x1
10413 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT	5
10414 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK	0x1
10415 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT	6
10416 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK	0x1
10417 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT	7
10418 	u8 flags1;
10419 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK	0x1
10420 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT	0
10421 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK	0x1
10422 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT	1
10423 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK	0x1
10424 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT	2
10425 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK		0x1
10426 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT		3
10427 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK		0x1
10428 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT		4
10429 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK		0x1
10430 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT		5
10431 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK		0x1
10432 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT		6
10433 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK		0x1
10434 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT		7
10435 	u8 flags2;
10436 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_MASK	0x3
10437 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT	0
10438 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_MASK	0x3
10439 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT	2
10440 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_MASK	0x3
10441 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT	4
10442 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_MASK	0x3
10443 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT	6
10444 	u8 flags3;
10445 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_MASK	0x3
10446 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT	0
10447 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_MASK	0x3
10448 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT	2
10449 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_MASK	0x3
10450 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT	4
10451 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_MASK	0x3
10452 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT	6
10453 	u8 flags4;
10454 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_MASK	0x3
10455 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT	0
10456 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_MASK	0x3
10457 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT	2
10458 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_MASK	0x3
10459 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT	4
10460 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_MASK	0x3
10461 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT	6
10462 	u8 flags5;
10463 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_MASK	0x3
10464 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT	0
10465 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_MASK	0x3
10466 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT	2
10467 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_MASK	0x3
10468 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT	4
10469 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_MASK	0x3
10470 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT	6
10471 	u8 flags6;
10472 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_MASK	0x3
10473 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT	0
10474 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_MASK	0x3
10475 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT	2
10476 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_MASK	0x3
10477 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT	4
10478 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK	0x3
10479 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT	6
10480 	u8 flags7;
10481 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK	0x3
10482 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT	0
10483 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK	0x3
10484 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT	2
10485 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK	0x3
10486 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT	4
10487 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK		0x1
10488 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT		6
10489 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK		0x1
10490 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT		7
10491 	u8 flags8;
10492 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK	0x1
10493 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT	0
10494 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK	0x1
10495 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT	1
10496 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK	0x1
10497 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT	2
10498 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK	0x1
10499 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT	3
10500 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK	0x1
10501 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT	4
10502 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK	0x1
10503 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT	5
10504 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK	0x1
10505 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT	6
10506 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK	0x1
10507 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT	7
10508 	u8 flags9;
10509 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK	0x1
10510 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT	0
10511 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK	0x1
10512 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT	1
10513 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK	0x1
10514 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT	2
10515 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK	0x1
10516 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT	3
10517 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK	0x1
10518 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT	4
10519 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK	0x1
10520 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT	5
10521 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK	0x1
10522 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT	6
10523 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK	0x1
10524 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT	7
10525 	u8 flags10;
10526 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK		0x1
10527 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT		0
10528 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK	0x1
10529 #define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT	1
10530 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK	0x1
10531 #define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT	2
10532 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK	0x1
10533 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT	3
10534 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK	0x1
10535 #define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT	4
10536 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK		0x1
10537 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT		5
10538 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK	0x1
10539 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT	6
10540 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK	0x1
10541 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT	7
10542 	u8 flags11;
10543 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK		0x1
10544 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT		0
10545 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK		0x1
10546 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT		1
10547 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK		0x1
10548 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT		2
10549 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK			0x1
10550 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT		3
10551 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK			0x1
10552 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT		4
10553 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK			0x1
10554 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT		5
10555 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK		0x1
10556 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT		6
10557 #define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK	0x1
10558 #define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT	7
10559 	u8 flags12;
10560 #define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK	0x1
10561 #define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT	0
10562 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK	0x1
10563 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT	1
10564 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK	0x1
10565 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT	2
10566 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK	0x1
10567 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT	3
10568 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK	0x1
10569 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT	4
10570 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK	0x1
10571 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT	5
10572 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK	0x1
10573 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT	6
10574 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK	0x1
10575 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT	7
10576 	u8 flags13;
10577 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK	0x1
10578 #define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT	0
10579 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK		0x1
10580 #define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT		1
10581 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK		0x1
10582 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT		2
10583 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK		0x1
10584 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT		3
10585 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK		0x1
10586 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT		4
10587 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK		0x1
10588 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT		5
10589 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK		0x1
10590 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT		6
10591 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK		0x1
10592 #define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT		7
10593 	u8 flags14;
10594 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK	0x1
10595 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT	0
10596 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK	0x1
10597 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT	1
10598 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK	0x1
10599 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT	2
10600 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK	0x1
10601 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT	3
10602 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK	0x1
10603 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT	4
10604 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK	0x1
10605 #define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT	5
10606 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_MASK	0x3
10607 #define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT	6
10608 	u8 byte2;
10609 	__le16 physical_q0;
10610 	__le16 word1;
10611 	__le16 word2;
10612 	__le16 sq_cons;
10613 	__le16 sq_prod;
10614 	__le16 xferq_prod;
10615 	__le16 xferq_cons;
10616 	u8 byte3;
10617 	u8 byte4;
10618 	u8 byte5;
10619 	u8 byte6;
10620 	__le32 remain_io;
10621 	__le32 reg1;
10622 	__le32 reg2;
10623 	__le32 reg3;
10624 	__le32 reg4;
10625 	__le32 reg5;
10626 	__le32 reg6;
10627 	__le16 respq_prod;
10628 	__le16 respq_cons;
10629 	__le16 word9;
10630 	__le16 word10;
10631 	__le32 reg7;
10632 	__le32 reg8;
10633 };
10634 
10635 /* The fcoe storm context of Ustorm */
10636 struct ustorm_fcoe_conn_st_ctx {
10637 	struct regpair respq_pbl_addr;
10638 	__le16 num_pages_in_pbl;
10639 	u8 ptu_log_page_size;
10640 	u8 log_page_size;
10641 	__le16 respq_prod;
10642 	u8 reserved[2];
10643 };
10644 
10645 struct e4_tstorm_fcoe_conn_ag_ctx {
10646 	u8 reserved0;
10647 	u8 state;
10648 	u8 flags0;
10649 #define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
10650 #define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
10651 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK		0x1
10652 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT		1
10653 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK		0x1
10654 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT		2
10655 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK		0x1
10656 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT		3
10657 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK		0x1
10658 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT		4
10659 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK		0x1
10660 #define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT		5
10661 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK	0x3
10662 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT	6
10663 	u8 flags1;
10664 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK		0x3
10665 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT		0
10666 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_MASK			0x3
10667 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT			2
10668 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK	0x3
10669 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT	4
10670 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_MASK			0x3
10671 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT			6
10672 	u8 flags2;
10673 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_MASK	0x3
10674 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT	0
10675 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_MASK	0x3
10676 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT	2
10677 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_MASK	0x3
10678 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT	4
10679 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_MASK	0x3
10680 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT	6
10681 	u8 flags3;
10682 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_MASK			0x3
10683 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT			0
10684 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_MASK			0x3
10685 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT			2
10686 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK	0x1
10687 #define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT	4
10688 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK		0x1
10689 #define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT		5
10690 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK			0x1
10691 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT			6
10692 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK	0x1
10693 #define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT	7
10694 	u8 flags4;
10695 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK		0x1
10696 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT		0
10697 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK		0x1
10698 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT		1
10699 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK		0x1
10700 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT		2
10701 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK		0x1
10702 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT		3
10703 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK		0x1
10704 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT		4
10705 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK		0x1
10706 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT		5
10707 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK		0x1
10708 #define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT		6
10709 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK		0x1
10710 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT	7
10711 	u8 flags5;
10712 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK		0x1
10713 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT	0
10714 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK		0x1
10715 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT	1
10716 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK		0x1
10717 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT	2
10718 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK		0x1
10719 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT	3
10720 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK		0x1
10721 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT	4
10722 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK		0x1
10723 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT	5
10724 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK		0x1
10725 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT	6
10726 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK		0x1
10727 #define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT	7
10728 	__le32 reg0;
10729 	__le32 reg1;
10730 };
10731 
10732 struct e4_ustorm_fcoe_conn_ag_ctx {
10733 	u8 byte0;
10734 	u8 byte1;
10735 	u8 flags0;
10736 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_MASK	0x1
10737 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT	0
10738 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_MASK	0x1
10739 #define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT	1
10740 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0_MASK	0x3
10741 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT	2
10742 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1_MASK	0x3
10743 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT	4
10744 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2_MASK	0x3
10745 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT	6
10746 	u8 flags1;
10747 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3_MASK	0x3
10748 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT	0
10749 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4_MASK	0x3
10750 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT	2
10751 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5_MASK	0x3
10752 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT	4
10753 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6_MASK	0x3
10754 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT	6
10755 	u8 flags2;
10756 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK		0x1
10757 #define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT		0
10758 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK		0x1
10759 #define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT		1
10760 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK		0x1
10761 #define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT		2
10762 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK		0x1
10763 #define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT		3
10764 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK		0x1
10765 #define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT		4
10766 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK		0x1
10767 #define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT		5
10768 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK		0x1
10769 #define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT		6
10770 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK		0x1
10771 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT	7
10772 	u8 flags3;
10773 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK		0x1
10774 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT	0
10775 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK		0x1
10776 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT	1
10777 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK		0x1
10778 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT	2
10779 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK		0x1
10780 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT	3
10781 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK		0x1
10782 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT	4
10783 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK		0x1
10784 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT	5
10785 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK		0x1
10786 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT	6
10787 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK		0x1
10788 #define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT	7
10789 	u8 byte2;
10790 	u8 byte3;
10791 	__le16 word0;
10792 	__le16 word1;
10793 	__le32 reg0;
10794 	__le32 reg1;
10795 	__le32 reg2;
10796 	__le32 reg3;
10797 	__le16 word2;
10798 	__le16 word3;
10799 };
10800 
10801 /* The fcoe storm context of Tstorm */
10802 struct tstorm_fcoe_conn_st_ctx {
10803 	__le16 stat_ram_addr;
10804 	__le16 rx_max_fc_payload_len;
10805 	__le16 e_d_tov_val;
10806 	u8 flags;
10807 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK	0x1
10808 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT	0
10809 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK	0x1
10810 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT	1
10811 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK		0x3F
10812 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT		2
10813 	u8 timers_cleanup_invocation_cnt;
10814 	__le32 reserved1[2];
10815 	__le32 dst_mac_address_bytes_0_to_3;
10816 	__le16 dst_mac_address_bytes_4_to_5;
10817 	__le16 ramrod_echo;
10818 	u8 flags1;
10819 #define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK	0x3
10820 #define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT	0
10821 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK	0x3F
10822 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT	2
10823 	u8 cq_relative_offset;
10824 	u8 cmdq_relative_offset;
10825 	u8 bdq_resource_id;
10826 	u8 reserved0[4];
10827 };
10828 
10829 struct e4_mstorm_fcoe_conn_ag_ctx {
10830 	u8 byte0;
10831 	u8 byte1;
10832 	u8 flags0;
10833 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK	0x1
10834 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT	0
10835 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK	0x1
10836 #define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT	1
10837 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_MASK	0x3
10838 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT	2
10839 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_MASK	0x3
10840 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT	4
10841 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_MASK	0x3
10842 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT	6
10843 	u8 flags1;
10844 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK		0x1
10845 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT		0
10846 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK		0x1
10847 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT		1
10848 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK		0x1
10849 #define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT		2
10850 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK		0x1
10851 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT	3
10852 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK		0x1
10853 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT	4
10854 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK		0x1
10855 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT	5
10856 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK		0x1
10857 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT	6
10858 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK		0x1
10859 #define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT	7
10860 	__le16 word0;
10861 	__le16 word1;
10862 	__le32 reg0;
10863 	__le32 reg1;
10864 };
10865 
10866 /* Fast path part of the fcoe storm context of Mstorm */
10867 struct fcoe_mstorm_fcoe_conn_st_ctx_fp {
10868 	__le16 xfer_prod;
10869 	u8 num_cqs;
10870 	u8 reserved1;
10871 	u8 protection_info;
10872 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK  0x1
10873 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_SHIFT 0
10874 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK               0x1
10875 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_SHIFT              1
10876 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_MASK           0x3F
10877 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_SHIFT          2
10878 	u8 q_relative_offset;
10879 	u8 reserved2[2];
10880 };
10881 
10882 /* Non fast path part of the fcoe storm context of Mstorm */
10883 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp {
10884 	__le16 conn_id;
10885 	__le16 stat_ram_addr;
10886 	__le16 num_pages_in_pbl;
10887 	u8 ptu_log_page_size;
10888 	u8 log_page_size;
10889 	__le16 unsolicited_cq_count;
10890 	__le16 cmdq_count;
10891 	u8 bdq_resource_id;
10892 	u8 reserved0[3];
10893 	struct regpair xferq_pbl_addr;
10894 	struct regpair reserved1;
10895 	struct regpair reserved2[3];
10896 };
10897 
10898 /* The fcoe storm context of Mstorm */
10899 struct mstorm_fcoe_conn_st_ctx {
10900 	struct fcoe_mstorm_fcoe_conn_st_ctx_fp fp;
10901 	struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp non_fp;
10902 };
10903 
10904 /* fcoe connection context */
10905 struct e4_fcoe_conn_context {
10906 	struct ystorm_fcoe_conn_st_ctx ystorm_st_context;
10907 	struct pstorm_fcoe_conn_st_ctx pstorm_st_context;
10908 	struct regpair pstorm_st_padding[2];
10909 	struct xstorm_fcoe_conn_st_ctx xstorm_st_context;
10910 	struct e4_xstorm_fcoe_conn_ag_ctx xstorm_ag_context;
10911 	struct regpair xstorm_ag_padding[6];
10912 	struct ustorm_fcoe_conn_st_ctx ustorm_st_context;
10913 	struct regpair ustorm_st_padding[2];
10914 	struct e4_tstorm_fcoe_conn_ag_ctx tstorm_ag_context;
10915 	struct regpair tstorm_ag_padding[2];
10916 	struct timers_context timer_context;
10917 	struct e4_ustorm_fcoe_conn_ag_ctx ustorm_ag_context;
10918 	struct tstorm_fcoe_conn_st_ctx tstorm_st_context;
10919 	struct e4_mstorm_fcoe_conn_ag_ctx mstorm_ag_context;
10920 	struct mstorm_fcoe_conn_st_ctx mstorm_st_context;
10921 };
10922 
10923 /* FCoE connection offload params passed by driver to FW in FCoE offload
10924  * ramrod.
10925  */
10926 struct fcoe_conn_offload_ramrod_params {
10927 	struct fcoe_conn_offload_ramrod_data offload_ramrod_data;
10928 };
10929 
10930 /* FCoE connection terminate params passed by driver to FW in FCoE terminate
10931  * conn ramrod.
10932  */
10933 struct fcoe_conn_terminate_ramrod_params {
10934 	struct fcoe_conn_terminate_ramrod_data terminate_ramrod_data;
10935 };
10936 
10937 /* FCoE event type */
10938 enum fcoe_event_type {
10939 	FCOE_EVENT_INIT_FUNC,
10940 	FCOE_EVENT_DESTROY_FUNC,
10941 	FCOE_EVENT_STAT_FUNC,
10942 	FCOE_EVENT_OFFLOAD_CONN,
10943 	FCOE_EVENT_TERMINATE_CONN,
10944 	FCOE_EVENT_ERROR,
10945 	MAX_FCOE_EVENT_TYPE
10946 };
10947 
10948 /* FCoE init params passed by driver to FW in FCoE init ramrod */
10949 struct fcoe_init_ramrod_params {
10950 	struct fcoe_init_func_ramrod_data init_ramrod_data;
10951 };
10952 
10953 /* FCoE ramrod Command IDs */
10954 enum fcoe_ramrod_cmd_id {
10955 	FCOE_RAMROD_CMD_ID_INIT_FUNC,
10956 	FCOE_RAMROD_CMD_ID_DESTROY_FUNC,
10957 	FCOE_RAMROD_CMD_ID_STAT_FUNC,
10958 	FCOE_RAMROD_CMD_ID_OFFLOAD_CONN,
10959 	FCOE_RAMROD_CMD_ID_TERMINATE_CONN,
10960 	MAX_FCOE_RAMROD_CMD_ID
10961 };
10962 
10963 /* FCoE statistics params buffer passed by driver to FW in FCoE statistics
10964  * ramrod.
10965  */
10966 struct fcoe_stat_ramrod_params {
10967 	struct fcoe_stat_ramrod_data stat_ramrod_data;
10968 };
10969 
10970 struct e4_ystorm_fcoe_conn_ag_ctx {
10971 	u8 byte0;
10972 	u8 byte1;
10973 	u8 flags0;
10974 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK	0x1
10975 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT	0
10976 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK	0x1
10977 #define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT	1
10978 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_MASK	0x3
10979 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT	2
10980 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_MASK	0x3
10981 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT	4
10982 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_MASK	0x3
10983 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT	6
10984 	u8 flags1;
10985 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK		0x1
10986 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT		0
10987 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK		0x1
10988 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT		1
10989 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK		0x1
10990 #define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT		2
10991 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK		0x1
10992 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT	3
10993 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK		0x1
10994 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT	4
10995 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK		0x1
10996 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT	5
10997 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK		0x1
10998 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT	6
10999 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK		0x1
11000 #define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT	7
11001 	u8 byte2;
11002 	u8 byte3;
11003 	__le16 word0;
11004 	__le32 reg0;
11005 	__le32 reg1;
11006 	__le16 word1;
11007 	__le16 word2;
11008 	__le16 word3;
11009 	__le16 word4;
11010 	__le32 reg2;
11011 	__le32 reg3;
11012 };
11013 
11014 /* The iscsi storm connection context of Ystorm */
11015 struct ystorm_iscsi_conn_st_ctx {
11016 	__le32 reserved[8];
11017 };
11018 
11019 /* Combined iSCSI and TCP storm connection of Pstorm */
11020 struct pstorm_iscsi_tcp_conn_st_ctx {
11021 	__le32 tcp[32];
11022 	__le32 iscsi[4];
11023 };
11024 
11025 /* The combined tcp and iscsi storm context of Xstorm */
11026 struct xstorm_iscsi_tcp_conn_st_ctx {
11027 	__le32 reserved_tcp[4];
11028 	__le32 reserved_iscsi[44];
11029 };
11030 
11031 struct e4_xstorm_iscsi_conn_ag_ctx {
11032 	u8 cdu_validation;
11033 	u8 state;
11034 	u8 flags0;
11035 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
11036 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
11037 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK	0x1
11038 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_SHIFT	1
11039 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK	0x1
11040 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_SHIFT	2
11041 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK	0x1
11042 #define E4_XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_SHIFT	3
11043 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK		0x1
11044 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT		4
11045 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK	0x1
11046 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_SHIFT	5
11047 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK		0x1
11048 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT6_SHIFT		6
11049 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK		0x1
11050 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT7_SHIFT		7
11051 	u8 flags1;
11052 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK		0x1
11053 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT		0
11054 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK		0x1
11055 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT9_SHIFT		1
11056 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK		0x1
11057 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT10_SHIFT		2
11058 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK		0x1
11059 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT11_SHIFT		3
11060 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK		0x1
11061 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT12_SHIFT		4
11062 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK		0x1
11063 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT13_SHIFT		5
11064 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK		0x1
11065 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT14_SHIFT		6
11066 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK	0x1
11067 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_SHIFT	7
11068 	u8 flags2;
11069 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK			0x3
11070 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT			0
11071 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK			0x3
11072 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT			2
11073 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK			0x3
11074 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT			4
11075 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK		0x3
11076 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT	6
11077 	u8 flags3;
11078 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK	0x3
11079 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT	0
11080 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK	0x3
11081 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT	2
11082 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK	0x3
11083 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT	4
11084 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK	0x3
11085 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT	6
11086 	u8 flags4;
11087 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK	0x3
11088 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT	0
11089 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK	0x3
11090 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9_SHIFT	2
11091 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK	0x3
11092 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT	4
11093 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK	0x3
11094 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11_SHIFT	6
11095 	u8 flags5;
11096 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK				0x3
11097 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT				0
11098 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK				0x3
11099 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13_SHIFT				2
11100 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK				0x3
11101 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14_SHIFT				4
11102 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK	0x3
11103 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_SHIFT	6
11104 	u8 flags6;
11105 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK		0x3
11106 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT		0
11107 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK		0x3
11108 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17_SHIFT		2
11109 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK		0x3
11110 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18_SHIFT		4
11111 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK	0x3
11112 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_SHIFT	6
11113 	u8 flags7;
11114 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK	0x3
11115 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_SHIFT	0
11116 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK	0x3
11117 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_SHIFT	2
11118 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK		0x3
11119 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_SHIFT		4
11120 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK			0x1
11121 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT			6
11122 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK			0x1
11123 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT			7
11124 	u8 flags8;
11125 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK			0x1
11126 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT			0
11127 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK	0x1
11128 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT	1
11129 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK			0x1
11130 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT			2
11131 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK			0x1
11132 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT			3
11133 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK			0x1
11134 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT			4
11135 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK			0x1
11136 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT			5
11137 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK			0x1
11138 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT			6
11139 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK			0x1
11140 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF9EN_SHIFT			7
11141 	u8 flags9;
11142 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK				0x1
11143 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT			0
11144 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK				0x1
11145 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF11EN_SHIFT			1
11146 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK				0x1
11147 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF12EN_SHIFT			2
11148 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK				0x1
11149 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF13EN_SHIFT			3
11150 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK				0x1
11151 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF14EN_SHIFT			4
11152 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK	0x1
11153 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_SHIFT	5
11154 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK				0x1
11155 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF16EN_SHIFT			6
11156 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK				0x1
11157 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF17EN_SHIFT			7
11158 	u8 flags10;
11159 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK				0x1
11160 #define E4_XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT			0
11161 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK			0x1
11162 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT			1
11163 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK		0x1
11164 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_SHIFT	2
11165 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK		0x1
11166 #define E4_XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_SHIFT	3
11167 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK			0x1
11168 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_SHIFT			4
11169 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK		0x1
11170 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_SHIFT		5
11171 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK			0x1
11172 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT			6
11173 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK	0x1
11174 #define E4_XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_SHIFT	7
11175 	u8 flags11;
11176 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK	0x1
11177 #define E4_XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT	0
11178 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK	0x1
11179 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT	1
11180 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK	0x1
11181 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_SHIFT	2
11182 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK	0x1
11183 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT	3
11184 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK	0x1
11185 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT	4
11186 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK	0x1
11187 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT	5
11188 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK	0x1
11189 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_SHIFT	6
11190 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK	0x1
11191 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_SHIFT	7
11192 	u8 flags12;
11193 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK		0x1
11194 #define E4_XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT	0
11195 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK		0x1
11196 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_SHIFT		1
11197 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK		0x1
11198 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_SHIFT		2
11199 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK		0x1
11200 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_SHIFT		3
11201 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK		0x1
11202 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_SHIFT		4
11203 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK		0x1
11204 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_SHIFT		5
11205 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK		0x1
11206 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_SHIFT		6
11207 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK		0x1
11208 #define E4_XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_SHIFT		7
11209 	u8 flags13;
11210 #define E4_XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK	0x1
11211 #define E4_XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT	0
11212 #define E4_XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK		0x1
11213 #define E4_XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_SHIFT	1
11214 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK		0x1
11215 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_SHIFT		2
11216 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK		0x1
11217 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_SHIFT		3
11218 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK		0x1
11219 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_SHIFT		4
11220 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK		0x1
11221 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_SHIFT		5
11222 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK		0x1
11223 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_SHIFT		6
11224 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK		0x1
11225 #define E4_XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_SHIFT		7
11226 	u8 flags14;
11227 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK			0x1
11228 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT			0
11229 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK			0x1
11230 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT17_SHIFT			1
11231 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK			0x1
11232 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT18_SHIFT			2
11233 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK			0x1
11234 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT19_SHIFT			3
11235 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK			0x1
11236 #define E4_XSTORM_ISCSI_CONN_AG_CTX_BIT20_SHIFT			4
11237 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK	0x1
11238 #define E4_XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_SHIFT	5
11239 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK	0x3
11240 #define E4_XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_SHIFT	6
11241 	u8 byte2;
11242 	__le16 physical_q0;
11243 	__le16 physical_q1;
11244 	__le16 dummy_dorq_var;
11245 	__le16 sq_cons;
11246 	__le16 sq_prod;
11247 	__le16 word5;
11248 	__le16 slow_io_total_data_tx_update;
11249 	u8 byte3;
11250 	u8 byte4;
11251 	u8 byte5;
11252 	u8 byte6;
11253 	__le32 reg0;
11254 	__le32 reg1;
11255 	__le32 reg2;
11256 	__le32 more_to_send_seq;
11257 	__le32 reg4;
11258 	__le32 reg5;
11259 	__le32 hq_scan_next_relevant_ack;
11260 	__le16 r2tq_prod;
11261 	__le16 r2tq_cons;
11262 	__le16 hq_prod;
11263 	__le16 hq_cons;
11264 	__le32 remain_seq;
11265 	__le32 bytes_to_next_pdu;
11266 	__le32 hq_tcp_seq;
11267 	u8 byte7;
11268 	u8 byte8;
11269 	u8 byte9;
11270 	u8 byte10;
11271 	u8 byte11;
11272 	u8 byte12;
11273 	u8 byte13;
11274 	u8 byte14;
11275 	u8 byte15;
11276 	u8 e5_reserved;
11277 	__le16 word11;
11278 	__le32 reg10;
11279 	__le32 reg11;
11280 	__le32 exp_stat_sn;
11281 	__le32 ongoing_fast_rxmit_seq;
11282 	__le32 reg14;
11283 	__le32 reg15;
11284 	__le32 reg16;
11285 	__le32 reg17;
11286 };
11287 
11288 struct e4_tstorm_iscsi_conn_ag_ctx {
11289 	u8 reserved0;
11290 	u8 state;
11291 	u8 flags0;
11292 #define E4_TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK	0x1
11293 #define E4_TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT	0
11294 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK		0x1
11295 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT		1
11296 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK		0x1
11297 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT2_SHIFT		2
11298 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK		0x1
11299 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT3_SHIFT		3
11300 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK		0x1
11301 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT		4
11302 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK		0x1
11303 #define E4_TSTORM_ISCSI_CONN_AG_CTX_BIT5_SHIFT		5
11304 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK		0x3
11305 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT		6
11306 	u8 flags1;
11307 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK		0x3
11308 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_SHIFT		0
11309 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK		0x3
11310 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_SHIFT		2
11311 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK		0x3
11312 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT	4
11313 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK			0x3
11314 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT			6
11315 	u8 flags2;
11316 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK	0x3
11317 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT	0
11318 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK	0x3
11319 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT	2
11320 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK	0x3
11321 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT	4
11322 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK	0x3
11323 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT	6
11324 	u8 flags3;
11325 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK		0x3
11326 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT		0
11327 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_MASK	0x3
11328 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_SHIFT	2
11329 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK			0x1
11330 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT			4
11331 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK	0x1
11332 #define E4_TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_SHIFT	5
11333 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK	0x1
11334 #define E4_TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_SHIFT	6
11335 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK	0x1
11336 #define E4_TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT	7
11337 	u8 flags4;
11338 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK		0x1
11339 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT		0
11340 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK		0x1
11341 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT		1
11342 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK		0x1
11343 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT		2
11344 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK		0x1
11345 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT		3
11346 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK		0x1
11347 #define E4_TSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT		4
11348 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK	0x1
11349 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT	5
11350 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_EN_MASK	0x1
11351 #define E4_TSTORM_ISCSI_CONN_AG_CTX_FLUSH_OOO_ISLES_CF_EN_SHIFT	6
11352 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK	0x1
11353 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT	7
11354 	u8 flags5;
11355 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK	0x1
11356 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT	0
11357 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK	0x1
11358 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT	1
11359 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK	0x1
11360 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT	2
11361 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK	0x1
11362 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT	3
11363 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK	0x1
11364 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT	4
11365 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK	0x1
11366 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT	5
11367 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK	0x1
11368 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT	6
11369 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK	0x1
11370 #define E4_TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT	7
11371 	__le32 reg0;
11372 	__le32 reg1;
11373 	__le32 rx_tcp_checksum_err_cnt;
11374 	__le32 reg3;
11375 	__le32 reg4;
11376 	__le32 reg5;
11377 	__le32 reg6;
11378 	__le32 reg7;
11379 	__le32 reg8;
11380 	u8 cid_offload_cnt;
11381 	u8 byte3;
11382 	__le16 word0;
11383 };
11384 
11385 struct e4_ustorm_iscsi_conn_ag_ctx {
11386 	u8 byte0;
11387 	u8 byte1;
11388 	u8 flags0;
11389 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK	0x1
11390 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT	0
11391 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK	0x1
11392 #define E4_USTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT	1
11393 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0_MASK	0x3
11394 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT	2
11395 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1_MASK	0x3
11396 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT	4
11397 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2_MASK	0x3
11398 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT	6
11399 	u8 flags1;
11400 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3_MASK	0x3
11401 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT	0
11402 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4_MASK	0x3
11403 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT	2
11404 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5_MASK	0x3
11405 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT	4
11406 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6_MASK	0x3
11407 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT	6
11408 	u8 flags2;
11409 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK		0x1
11410 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT		0
11411 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK		0x1
11412 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT		1
11413 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK		0x1
11414 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT		2
11415 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK		0x1
11416 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF3EN_SHIFT		3
11417 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK		0x1
11418 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT		4
11419 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK		0x1
11420 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT		5
11421 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK		0x1
11422 #define E4_USTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT		6
11423 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK	0x1
11424 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT	7
11425 	u8 flags3;
11426 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK	0x1
11427 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT	0
11428 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK	0x1
11429 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT	1
11430 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK	0x1
11431 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT	2
11432 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK	0x1
11433 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT	3
11434 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK	0x1
11435 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT	4
11436 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK	0x1
11437 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT	5
11438 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK	0x1
11439 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT	6
11440 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK	0x1
11441 #define E4_USTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT	7
11442 	u8 byte2;
11443 	u8 byte3;
11444 	__le16 word0;
11445 	__le16 word1;
11446 	__le32 reg0;
11447 	__le32 reg1;
11448 	__le32 reg2;
11449 	__le32 reg3;
11450 	__le16 word2;
11451 	__le16 word3;
11452 };
11453 
11454 /* The iscsi storm connection context of Tstorm */
11455 struct tstorm_iscsi_conn_st_ctx {
11456 	__le32 reserved[44];
11457 };
11458 
11459 struct e4_mstorm_iscsi_conn_ag_ctx {
11460 	u8 reserved;
11461 	u8 state;
11462 	u8 flags0;
11463 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK	0x1
11464 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT	0
11465 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK	0x1
11466 #define E4_MSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT	1
11467 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK	0x3
11468 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT	2
11469 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK	0x3
11470 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT	4
11471 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK	0x3
11472 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT	6
11473 	u8 flags1;
11474 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK		0x1
11475 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT		0
11476 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK		0x1
11477 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT		1
11478 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK		0x1
11479 #define E4_MSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT		2
11480 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK	0x1
11481 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT	3
11482 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK	0x1
11483 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT	4
11484 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK	0x1
11485 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT	5
11486 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK	0x1
11487 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT	6
11488 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK	0x1
11489 #define E4_MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT	7
11490 	__le16 word0;
11491 	__le16 word1;
11492 	__le32 reg0;
11493 	__le32 reg1;
11494 };
11495 
11496 /* Combined iSCSI and TCP storm connection of Mstorm */
11497 struct mstorm_iscsi_tcp_conn_st_ctx {
11498 	__le32 reserved_tcp[20];
11499 	__le32 reserved_iscsi[12];
11500 };
11501 
11502 /* The iscsi storm context of Ustorm */
11503 struct ustorm_iscsi_conn_st_ctx {
11504 	__le32 reserved[52];
11505 };
11506 
11507 /* iscsi connection context */
11508 struct e4_iscsi_conn_context {
11509 	struct ystorm_iscsi_conn_st_ctx ystorm_st_context;
11510 	struct pstorm_iscsi_tcp_conn_st_ctx pstorm_st_context;
11511 	struct regpair pstorm_st_padding[2];
11512 	struct pb_context xpb2_context;
11513 	struct xstorm_iscsi_tcp_conn_st_ctx xstorm_st_context;
11514 	struct regpair xstorm_st_padding[2];
11515 	struct e4_xstorm_iscsi_conn_ag_ctx xstorm_ag_context;
11516 	struct e4_tstorm_iscsi_conn_ag_ctx tstorm_ag_context;
11517 	struct regpair tstorm_ag_padding[2];
11518 	struct timers_context timer_context;
11519 	struct e4_ustorm_iscsi_conn_ag_ctx ustorm_ag_context;
11520 	struct pb_context upb_context;
11521 	struct tstorm_iscsi_conn_st_ctx tstorm_st_context;
11522 	struct regpair tstorm_st_padding[2];
11523 	struct e4_mstorm_iscsi_conn_ag_ctx mstorm_ag_context;
11524 	struct mstorm_iscsi_tcp_conn_st_ctx mstorm_st_context;
11525 	struct ustorm_iscsi_conn_st_ctx ustorm_st_context;
11526 };
11527 
11528 /* iSCSI init params passed by driver to FW in iSCSI init ramrod */
11529 struct iscsi_init_ramrod_params {
11530 	struct iscsi_spe_func_init iscsi_init_spe;
11531 	struct tcp_init_params tcp_init;
11532 };
11533 
11534 struct e4_ystorm_iscsi_conn_ag_ctx {
11535 	u8 byte0;
11536 	u8 byte1;
11537 	u8 flags0;
11538 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK	0x1
11539 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT	0
11540 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK	0x1
11541 #define E4_YSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT	1
11542 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK	0x3
11543 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT	2
11544 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK	0x3
11545 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT	4
11546 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK	0x3
11547 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT	6
11548 	u8 flags1;
11549 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK		0x1
11550 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT		0
11551 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK		0x1
11552 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT		1
11553 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK		0x1
11554 #define E4_YSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT		2
11555 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK	0x1
11556 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT	3
11557 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK	0x1
11558 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT	4
11559 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK	0x1
11560 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT	5
11561 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK	0x1
11562 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT	6
11563 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK	0x1
11564 #define E4_YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT	7
11565 	u8 byte2;
11566 	u8 byte3;
11567 	__le16 word0;
11568 	__le32 reg0;
11569 	__le32 reg1;
11570 	__le16 word1;
11571 	__le16 word2;
11572 	__le16 word3;
11573 	__le16 word4;
11574 	__le32 reg2;
11575 	__le32 reg3;
11576 };
11577 
11578 #define MFW_TRACE_SIGNATURE     0x25071946
11579 
11580 /* The trace in the buffer */
11581 #define MFW_TRACE_EVENTID_MASK          0x00ffff
11582 #define MFW_TRACE_PRM_SIZE_MASK         0x0f0000
11583 #define MFW_TRACE_PRM_SIZE_OFFSET	16
11584 #define MFW_TRACE_ENTRY_SIZE            3
11585 
11586 struct mcp_trace {
11587 	u32 signature;		/* Help to identify that the trace is valid */
11588 	u32 size;		/* the size of the trace buffer in bytes */
11589 	u32 curr_level;		/* 2 - all will be written to the buffer
11590 				 * 1 - debug trace will not be written
11591 				 * 0 - just errors will be written to the buffer
11592 				 */
11593 	u32 modules_mask[2];	/* a bit per module, 1 means write it, 0 means
11594 				 * mask it.
11595 				 */
11596 
11597 	/* Warning: the following pointers are assumed to be 32bits as they are
11598 	 * used only in the MFW.
11599 	 */
11600 	u32 trace_prod; /* The next trace will be written to this offset */
11601 	u32 trace_oldest; /* The oldest valid trace starts at this offset
11602 			   * (usually very close after the current producer).
11603 			   */
11604 };
11605 
11606 #define VF_MAX_STATIC 192
11607 
11608 #define MCP_GLOB_PATH_MAX	2
11609 #define MCP_PORT_MAX		2
11610 #define MCP_GLOB_PORT_MAX	4
11611 #define MCP_GLOB_FUNC_MAX	16
11612 
11613 typedef u32 offsize_t;		/* In DWORDS !!! */
11614 /* Offset from the beginning of the MCP scratchpad */
11615 #define OFFSIZE_OFFSET_SHIFT	0
11616 #define OFFSIZE_OFFSET_MASK	0x0000ffff
11617 /* Size of specific element (not the whole array if any) */
11618 #define OFFSIZE_SIZE_SHIFT	16
11619 #define OFFSIZE_SIZE_MASK	0xffff0000
11620 
11621 #define SECTION_OFFSET(_offsize) ((((_offsize &			\
11622 				     OFFSIZE_OFFSET_MASK) >>	\
11623 				    OFFSIZE_OFFSET_SHIFT) << 2))
11624 
11625 #define QED_SECTION_SIZE(_offsize) (((_offsize &		\
11626 				      OFFSIZE_SIZE_MASK) >>	\
11627 				     OFFSIZE_SIZE_SHIFT) << 2)
11628 
11629 #define SECTION_ADDR(_offsize, idx) (MCP_REG_SCRATCH +			\
11630 				     SECTION_OFFSET(_offsize) +		\
11631 				     (QED_SECTION_SIZE(_offsize) * idx))
11632 
11633 #define SECTION_OFFSIZE_ADDR(_pub_base, _section)	\
11634 	(_pub_base + offsetof(struct mcp_public_data, sections[_section]))
11635 
11636 /* PHY configuration */
11637 struct eth_phy_cfg {
11638 	u32 speed;
11639 #define ETH_SPEED_AUTONEG	0
11640 #define ETH_SPEED_SMARTLINQ	0x8
11641 
11642 	u32 pause;
11643 #define ETH_PAUSE_NONE		0x0
11644 #define ETH_PAUSE_AUTONEG	0x1
11645 #define ETH_PAUSE_RX		0x2
11646 #define ETH_PAUSE_TX		0x4
11647 
11648 	u32 adv_speed;
11649 	u32 loopback_mode;
11650 #define ETH_LOOPBACK_NONE		(0)
11651 #define ETH_LOOPBACK_INT_PHY		(1)
11652 #define ETH_LOOPBACK_EXT_PHY		(2)
11653 #define ETH_LOOPBACK_EXT		(3)
11654 #define ETH_LOOPBACK_MAC		(4)
11655 
11656 	u32 eee_cfg;
11657 #define EEE_CFG_EEE_ENABLED			BIT(0)
11658 #define EEE_CFG_TX_LPI				BIT(1)
11659 #define EEE_CFG_ADV_SPEED_1G			BIT(2)
11660 #define EEE_CFG_ADV_SPEED_10G			BIT(3)
11661 #define EEE_TX_TIMER_USEC_MASK			(0xfffffff0)
11662 #define EEE_TX_TIMER_USEC_OFFSET		4
11663 #define EEE_TX_TIMER_USEC_BALANCED_TIME		(0xa00)
11664 #define EEE_TX_TIMER_USEC_AGGRESSIVE_TIME	(0x100)
11665 #define EEE_TX_TIMER_USEC_LATENCY_TIME		(0x6000)
11666 
11667 	u32 feature_config_flags;
11668 #define ETH_EEE_MODE_ADV_LPI		(1 << 0)
11669 };
11670 
11671 struct port_mf_cfg {
11672 	u32 dynamic_cfg;
11673 #define PORT_MF_CFG_OV_TAG_MASK		0x0000ffff
11674 #define PORT_MF_CFG_OV_TAG_SHIFT	0
11675 #define PORT_MF_CFG_OV_TAG_DEFAULT	PORT_MF_CFG_OV_TAG_MASK
11676 
11677 	u32 reserved[1];
11678 };
11679 
11680 struct eth_stats {
11681 	u64 r64;
11682 	u64 r127;
11683 	u64 r255;
11684 	u64 r511;
11685 	u64 r1023;
11686 	u64 r1518;
11687 
11688 	union {
11689 		struct {
11690 			u64 r1522;
11691 			u64 r2047;
11692 			u64 r4095;
11693 			u64 r9216;
11694 			u64 r16383;
11695 		} bb0;
11696 		struct {
11697 			u64 unused1;
11698 			u64 r1519_to_max;
11699 			u64 unused2;
11700 			u64 unused3;
11701 			u64 unused4;
11702 		} ah0;
11703 	} u0;
11704 
11705 	u64 rfcs;
11706 	u64 rxcf;
11707 	u64 rxpf;
11708 	u64 rxpp;
11709 	u64 raln;
11710 	u64 rfcr;
11711 	u64 rovr;
11712 	u64 rjbr;
11713 	u64 rund;
11714 	u64 rfrg;
11715 	u64 t64;
11716 	u64 t127;
11717 	u64 t255;
11718 	u64 t511;
11719 	u64 t1023;
11720 	u64 t1518;
11721 
11722 	union {
11723 		struct {
11724 			u64 t2047;
11725 			u64 t4095;
11726 			u64 t9216;
11727 			u64 t16383;
11728 		} bb1;
11729 		struct {
11730 			u64 t1519_to_max;
11731 			u64 unused6;
11732 			u64 unused7;
11733 			u64 unused8;
11734 		} ah1;
11735 	} u1;
11736 
11737 	u64 txpf;
11738 	u64 txpp;
11739 
11740 	union {
11741 		struct {
11742 			u64 tlpiec;
11743 			u64 tncl;
11744 		} bb2;
11745 		struct {
11746 			u64 unused9;
11747 			u64 unused10;
11748 		} ah2;
11749 	} u2;
11750 
11751 	u64 rbyte;
11752 	u64 rxuca;
11753 	u64 rxmca;
11754 	u64 rxbca;
11755 	u64 rxpok;
11756 	u64 tbyte;
11757 	u64 txuca;
11758 	u64 txmca;
11759 	u64 txbca;
11760 	u64 txcf;
11761 };
11762 
11763 struct brb_stats {
11764 	u64 brb_truncate[8];
11765 	u64 brb_discard[8];
11766 };
11767 
11768 struct port_stats {
11769 	struct brb_stats brb;
11770 	struct eth_stats eth;
11771 };
11772 
11773 struct couple_mode_teaming {
11774 	u8 port_cmt[MCP_GLOB_PORT_MAX];
11775 #define PORT_CMT_IN_TEAM	(1 << 0)
11776 
11777 #define PORT_CMT_PORT_ROLE	(1 << 1)
11778 #define PORT_CMT_PORT_INACTIVE	(0 << 1)
11779 #define PORT_CMT_PORT_ACTIVE	(1 << 1)
11780 
11781 #define PORT_CMT_TEAM_MASK	(1 << 2)
11782 #define PORT_CMT_TEAM0		(0 << 2)
11783 #define PORT_CMT_TEAM1		(1 << 2)
11784 };
11785 
11786 #define LLDP_CHASSIS_ID_STAT_LEN	4
11787 #define LLDP_PORT_ID_STAT_LEN		4
11788 #define DCBX_MAX_APP_PROTOCOL		32
11789 #define MAX_SYSTEM_LLDP_TLV_DATA	32
11790 
11791 enum _lldp_agent {
11792 	LLDP_NEAREST_BRIDGE = 0,
11793 	LLDP_NEAREST_NON_TPMR_BRIDGE,
11794 	LLDP_NEAREST_CUSTOMER_BRIDGE,
11795 	LLDP_MAX_LLDP_AGENTS
11796 };
11797 
11798 struct lldp_config_params_s {
11799 	u32 config;
11800 #define LLDP_CONFIG_TX_INTERVAL_MASK	0x000000ff
11801 #define LLDP_CONFIG_TX_INTERVAL_SHIFT	0
11802 #define LLDP_CONFIG_HOLD_MASK		0x00000f00
11803 #define LLDP_CONFIG_HOLD_SHIFT		8
11804 #define LLDP_CONFIG_MAX_CREDIT_MASK	0x0000f000
11805 #define LLDP_CONFIG_MAX_CREDIT_SHIFT	12
11806 #define LLDP_CONFIG_ENABLE_RX_MASK	0x40000000
11807 #define LLDP_CONFIG_ENABLE_RX_SHIFT	30
11808 #define LLDP_CONFIG_ENABLE_TX_MASK	0x80000000
11809 #define LLDP_CONFIG_ENABLE_TX_SHIFT	31
11810 	u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
11811 	u32 local_port_id[LLDP_PORT_ID_STAT_LEN];
11812 };
11813 
11814 struct lldp_status_params_s {
11815 	u32 prefix_seq_num;
11816 	u32 status;
11817 	u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN];
11818 	u32 peer_port_id[LLDP_PORT_ID_STAT_LEN];
11819 	u32 suffix_seq_num;
11820 };
11821 
11822 struct dcbx_ets_feature {
11823 	u32 flags;
11824 #define DCBX_ETS_ENABLED_MASK	0x00000001
11825 #define DCBX_ETS_ENABLED_SHIFT	0
11826 #define DCBX_ETS_WILLING_MASK	0x00000002
11827 #define DCBX_ETS_WILLING_SHIFT	1
11828 #define DCBX_ETS_ERROR_MASK	0x00000004
11829 #define DCBX_ETS_ERROR_SHIFT	2
11830 #define DCBX_ETS_CBS_MASK	0x00000008
11831 #define DCBX_ETS_CBS_SHIFT	3
11832 #define DCBX_ETS_MAX_TCS_MASK	0x000000f0
11833 #define DCBX_ETS_MAX_TCS_SHIFT	4
11834 #define DCBX_OOO_TC_MASK	0x00000f00
11835 #define DCBX_OOO_TC_SHIFT	8
11836 	u32 pri_tc_tbl[1];
11837 #define DCBX_TCP_OOO_TC		(4)
11838 
11839 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET	(DCBX_TCP_OOO_TC + 1)
11840 #define DCBX_CEE_STRICT_PRIORITY	0xf
11841 	u32 tc_bw_tbl[2];
11842 	u32 tc_tsa_tbl[2];
11843 #define DCBX_ETS_TSA_STRICT	0
11844 #define DCBX_ETS_TSA_CBS	1
11845 #define DCBX_ETS_TSA_ETS	2
11846 };
11847 
11848 #define DCBX_TCP_OOO_TC			(4)
11849 #define DCBX_TCP_OOO_K2_4PORT_TC	(3)
11850 
11851 struct dcbx_app_priority_entry {
11852 	u32 entry;
11853 #define DCBX_APP_PRI_MAP_MASK		0x000000ff
11854 #define DCBX_APP_PRI_MAP_SHIFT		0
11855 #define DCBX_APP_PRI_0			0x01
11856 #define DCBX_APP_PRI_1			0x02
11857 #define DCBX_APP_PRI_2			0x04
11858 #define DCBX_APP_PRI_3			0x08
11859 #define DCBX_APP_PRI_4			0x10
11860 #define DCBX_APP_PRI_5			0x20
11861 #define DCBX_APP_PRI_6			0x40
11862 #define DCBX_APP_PRI_7			0x80
11863 #define DCBX_APP_SF_MASK		0x00000300
11864 #define DCBX_APP_SF_SHIFT		8
11865 #define DCBX_APP_SF_ETHTYPE		0
11866 #define DCBX_APP_SF_PORT		1
11867 #define DCBX_APP_SF_IEEE_MASK		0x0000f000
11868 #define DCBX_APP_SF_IEEE_SHIFT		12
11869 #define DCBX_APP_SF_IEEE_RESERVED	0
11870 #define DCBX_APP_SF_IEEE_ETHTYPE	1
11871 #define DCBX_APP_SF_IEEE_TCP_PORT	2
11872 #define DCBX_APP_SF_IEEE_UDP_PORT	3
11873 #define DCBX_APP_SF_IEEE_TCP_UDP_PORT	4
11874 
11875 #define DCBX_APP_PROTOCOL_ID_MASK	0xffff0000
11876 #define DCBX_APP_PROTOCOL_ID_SHIFT	16
11877 };
11878 
11879 struct dcbx_app_priority_feature {
11880 	u32 flags;
11881 #define DCBX_APP_ENABLED_MASK		0x00000001
11882 #define DCBX_APP_ENABLED_SHIFT		0
11883 #define DCBX_APP_WILLING_MASK		0x00000002
11884 #define DCBX_APP_WILLING_SHIFT		1
11885 #define DCBX_APP_ERROR_MASK		0x00000004
11886 #define DCBX_APP_ERROR_SHIFT		2
11887 #define DCBX_APP_MAX_TCS_MASK		0x0000f000
11888 #define DCBX_APP_MAX_TCS_SHIFT		12
11889 #define DCBX_APP_NUM_ENTRIES_MASK	0x00ff0000
11890 #define DCBX_APP_NUM_ENTRIES_SHIFT	16
11891 	struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
11892 };
11893 
11894 struct dcbx_features {
11895 	struct dcbx_ets_feature ets;
11896 	u32 pfc;
11897 #define DCBX_PFC_PRI_EN_BITMAP_MASK	0x000000ff
11898 #define DCBX_PFC_PRI_EN_BITMAP_SHIFT	0
11899 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0	0x01
11900 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1	0x02
11901 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2	0x04
11902 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3	0x08
11903 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4	0x10
11904 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5	0x20
11905 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6	0x40
11906 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7	0x80
11907 
11908 #define DCBX_PFC_FLAGS_MASK		0x0000ff00
11909 #define DCBX_PFC_FLAGS_SHIFT		8
11910 #define DCBX_PFC_CAPS_MASK		0x00000f00
11911 #define DCBX_PFC_CAPS_SHIFT		8
11912 #define DCBX_PFC_MBC_MASK		0x00004000
11913 #define DCBX_PFC_MBC_SHIFT		14
11914 #define DCBX_PFC_WILLING_MASK		0x00008000
11915 #define DCBX_PFC_WILLING_SHIFT		15
11916 #define DCBX_PFC_ENABLED_MASK		0x00010000
11917 #define DCBX_PFC_ENABLED_SHIFT		16
11918 #define DCBX_PFC_ERROR_MASK		0x00020000
11919 #define DCBX_PFC_ERROR_SHIFT		17
11920 
11921 	struct dcbx_app_priority_feature app;
11922 };
11923 
11924 struct dcbx_local_params {
11925 	u32 config;
11926 #define DCBX_CONFIG_VERSION_MASK	0x00000007
11927 #define DCBX_CONFIG_VERSION_SHIFT	0
11928 #define DCBX_CONFIG_VERSION_DISABLED	0
11929 #define DCBX_CONFIG_VERSION_IEEE	1
11930 #define DCBX_CONFIG_VERSION_CEE		2
11931 #define DCBX_CONFIG_VERSION_STATIC	4
11932 
11933 	u32 flags;
11934 	struct dcbx_features features;
11935 };
11936 
11937 struct dcbx_mib {
11938 	u32 prefix_seq_num;
11939 	u32 flags;
11940 	struct dcbx_features features;
11941 	u32 suffix_seq_num;
11942 };
11943 
11944 struct lldp_system_tlvs_buffer_s {
11945 	u16 valid;
11946 	u16 length;
11947 	u32 data[MAX_SYSTEM_LLDP_TLV_DATA];
11948 };
11949 
11950 struct dcb_dscp_map {
11951 	u32 flags;
11952 #define DCB_DSCP_ENABLE_MASK	0x1
11953 #define DCB_DSCP_ENABLE_SHIFT	0
11954 #define DCB_DSCP_ENABLE	1
11955 	u32 dscp_pri_map[8];
11956 };
11957 
11958 struct public_global {
11959 	u32 max_path;
11960 	u32 max_ports;
11961 #define MODE_1P 1
11962 #define MODE_2P 2
11963 #define MODE_3P 3
11964 #define MODE_4P 4
11965 	u32 debug_mb_offset;
11966 	u32 phymod_dbg_mb_offset;
11967 	struct couple_mode_teaming cmt;
11968 	s32 internal_temperature;
11969 	u32 mfw_ver;
11970 	u32 running_bundle_id;
11971 	s32 external_temperature;
11972 	u32 mdump_reason;
11973 	u64 reserved;
11974 	u32 data_ptr;
11975 	u32 data_size;
11976 };
11977 
11978 struct fw_flr_mb {
11979 	u32 aggint;
11980 	u32 opgen_addr;
11981 	u32 accum_ack;
11982 };
11983 
11984 struct public_path {
11985 	struct fw_flr_mb flr_mb;
11986 	u32 mcp_vf_disabled[VF_MAX_STATIC / 32];
11987 
11988 	u32 process_kill;
11989 #define PROCESS_KILL_COUNTER_MASK	0x0000ffff
11990 #define PROCESS_KILL_COUNTER_SHIFT	0
11991 #define PROCESS_KILL_GLOB_AEU_BIT_MASK	0xffff0000
11992 #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT	16
11993 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit)
11994 };
11995 
11996 struct public_port {
11997 	u32 validity_map;
11998 
11999 	u32 link_status;
12000 #define LINK_STATUS_LINK_UP			0x00000001
12001 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK	0x0000001e
12002 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD	(1 << 1)
12003 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD	(2 << 1)
12004 #define LINK_STATUS_SPEED_AND_DUPLEX_10G	(3 << 1)
12005 #define LINK_STATUS_SPEED_AND_DUPLEX_20G	(4 << 1)
12006 #define LINK_STATUS_SPEED_AND_DUPLEX_40G	(5 << 1)
12007 #define LINK_STATUS_SPEED_AND_DUPLEX_50G	(6 << 1)
12008 #define LINK_STATUS_SPEED_AND_DUPLEX_100G	(7 << 1)
12009 #define LINK_STATUS_SPEED_AND_DUPLEX_25G	(8 << 1)
12010 
12011 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED	0x00000020
12012 
12013 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE	0x00000040
12014 #define LINK_STATUS_PARALLEL_DETECTION_USED	0x00000080
12015 
12016 #define LINK_STATUS_PFC_ENABLED				0x00000100
12017 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
12018 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
12019 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE		0x00000800
12020 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE		0x00001000
12021 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE		0x00002000
12022 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE		0x00004000
12023 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE		0x00008000
12024 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE		0x00010000
12025 
12026 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK	0x000C0000
12027 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE	(0 << 18)
12028 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE	(1 << 18)
12029 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE	(2 << 18)
12030 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE		(3 << 18)
12031 
12032 #define LINK_STATUS_SFP_TX_FAULT			0x00100000
12033 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED		0x00200000
12034 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED		0x00400000
12035 #define LINK_STATUS_RX_SIGNAL_PRESENT			0x00800000
12036 #define LINK_STATUS_MAC_LOCAL_FAULT			0x01000000
12037 #define LINK_STATUS_MAC_REMOTE_FAULT			0x02000000
12038 #define LINK_STATUS_UNSUPPORTED_SPD_REQ			0x04000000
12039 
12040 	u32 link_status1;
12041 	u32 ext_phy_fw_version;
12042 	u32 drv_phy_cfg_addr;
12043 
12044 	u32 port_stx;
12045 
12046 	u32 stat_nig_timer;
12047 
12048 	struct port_mf_cfg port_mf_config;
12049 	struct port_stats stats;
12050 
12051 	u32 media_type;
12052 #define MEDIA_UNSPECIFIED	0x0
12053 #define MEDIA_SFPP_10G_FIBER	0x1
12054 #define MEDIA_XFP_FIBER		0x2
12055 #define MEDIA_DA_TWINAX		0x3
12056 #define MEDIA_BASE_T		0x4
12057 #define MEDIA_SFP_1G_FIBER	0x5
12058 #define MEDIA_MODULE_FIBER	0x6
12059 #define MEDIA_KR		0xf0
12060 #define MEDIA_NOT_PRESENT	0xff
12061 
12062 	u32 lfa_status;
12063 	u32 link_change_count;
12064 
12065 	struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS];
12066 	struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS];
12067 	struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf;
12068 
12069 	/* DCBX related MIB */
12070 	struct dcbx_local_params local_admin_dcbx_mib;
12071 	struct dcbx_mib remote_dcbx_mib;
12072 	struct dcbx_mib operational_dcbx_mib;
12073 
12074 	u32 reserved[2];
12075 	u32 transceiver_data;
12076 #define ETH_TRANSCEIVER_STATE_MASK	0x000000FF
12077 #define ETH_TRANSCEIVER_STATE_SHIFT	0x00000000
12078 #define ETH_TRANSCEIVER_STATE_OFFSET	0x00000000
12079 #define ETH_TRANSCEIVER_STATE_UNPLUGGED	0x00000000
12080 #define ETH_TRANSCEIVER_STATE_PRESENT	0x00000001
12081 #define ETH_TRANSCEIVER_STATE_VALID	0x00000003
12082 #define ETH_TRANSCEIVER_STATE_UPDATING	0x00000008
12083 #define ETH_TRANSCEIVER_TYPE_MASK       0x0000FF00
12084 #define ETH_TRANSCEIVER_TYPE_OFFSET     0x8
12085 #define ETH_TRANSCEIVER_TYPE_NONE                       0x00
12086 #define ETH_TRANSCEIVER_TYPE_UNKNOWN                    0xFF
12087 #define ETH_TRANSCEIVER_TYPE_1G_PCC                     0x01
12088 #define ETH_TRANSCEIVER_TYPE_1G_ACC                     0x02
12089 #define ETH_TRANSCEIVER_TYPE_1G_LX                      0x03
12090 #define ETH_TRANSCEIVER_TYPE_1G_SX                      0x04
12091 #define ETH_TRANSCEIVER_TYPE_10G_SR                     0x05
12092 #define ETH_TRANSCEIVER_TYPE_10G_LR                     0x06
12093 #define ETH_TRANSCEIVER_TYPE_10G_LRM                    0x07
12094 #define ETH_TRANSCEIVER_TYPE_10G_ER                     0x08
12095 #define ETH_TRANSCEIVER_TYPE_10G_PCC                    0x09
12096 #define ETH_TRANSCEIVER_TYPE_10G_ACC                    0x0a
12097 #define ETH_TRANSCEIVER_TYPE_XLPPI                      0x0b
12098 #define ETH_TRANSCEIVER_TYPE_40G_LR4                    0x0c
12099 #define ETH_TRANSCEIVER_TYPE_40G_SR4                    0x0d
12100 #define ETH_TRANSCEIVER_TYPE_40G_CR4                    0x0e
12101 #define ETH_TRANSCEIVER_TYPE_100G_AOC                   0x0f
12102 #define ETH_TRANSCEIVER_TYPE_100G_SR4                   0x10
12103 #define ETH_TRANSCEIVER_TYPE_100G_LR4                   0x11
12104 #define ETH_TRANSCEIVER_TYPE_100G_ER4                   0x12
12105 #define ETH_TRANSCEIVER_TYPE_100G_ACC                   0x13
12106 #define ETH_TRANSCEIVER_TYPE_100G_CR4                   0x14
12107 #define ETH_TRANSCEIVER_TYPE_4x10G_SR                   0x15
12108 #define ETH_TRANSCEIVER_TYPE_25G_CA_N                   0x16
12109 #define ETH_TRANSCEIVER_TYPE_25G_ACC_S                  0x17
12110 #define ETH_TRANSCEIVER_TYPE_25G_CA_S                   0x18
12111 #define ETH_TRANSCEIVER_TYPE_25G_ACC_M                  0x19
12112 #define ETH_TRANSCEIVER_TYPE_25G_CA_L                   0x1a
12113 #define ETH_TRANSCEIVER_TYPE_25G_ACC_L                  0x1b
12114 #define ETH_TRANSCEIVER_TYPE_25G_SR                     0x1c
12115 #define ETH_TRANSCEIVER_TYPE_25G_LR                     0x1d
12116 #define ETH_TRANSCEIVER_TYPE_25G_AOC                    0x1e
12117 #define ETH_TRANSCEIVER_TYPE_4x10G                      0x1f
12118 #define ETH_TRANSCEIVER_TYPE_4x25G_CR                   0x20
12119 #define ETH_TRANSCEIVER_TYPE_1000BASET                  0x21
12120 #define ETH_TRANSCEIVER_TYPE_10G_BASET                  0x22
12121 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_SR      0x30
12122 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_CR      0x31
12123 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_10G_40G_LR      0x32
12124 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_SR     0x33
12125 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_CR     0x34
12126 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_LR     0x35
12127 #define ETH_TRANSCEIVER_TYPE_MULTI_RATE_40G_100G_AOC    0x36
12128 	u32 wol_info;
12129 	u32 wol_pkt_len;
12130 	u32 wol_pkt_details;
12131 	struct dcb_dscp_map dcb_dscp_map;
12132 
12133 	u32 eee_status;
12134 #define EEE_ACTIVE_BIT			BIT(0)
12135 #define EEE_LD_ADV_STATUS_MASK		0x000000f0
12136 #define EEE_LD_ADV_STATUS_OFFSET	4
12137 #define EEE_1G_ADV			BIT(1)
12138 #define EEE_10G_ADV			BIT(2)
12139 #define EEE_LP_ADV_STATUS_MASK		0x00000f00
12140 #define EEE_LP_ADV_STATUS_OFFSET	8
12141 #define EEE_SUPPORTED_SPEED_MASK	0x0000f000
12142 #define EEE_SUPPORTED_SPEED_OFFSET	12
12143 #define EEE_1G_SUPPORTED		BIT(1)
12144 #define EEE_10G_SUPPORTED		BIT(2)
12145 
12146 	u32 eee_remote;
12147 #define EEE_REMOTE_TW_TX_MASK   0x0000ffff
12148 #define EEE_REMOTE_TW_TX_OFFSET 0
12149 #define EEE_REMOTE_TW_RX_MASK   0xffff0000
12150 #define EEE_REMOTE_TW_RX_OFFSET 16
12151 
12152 	u32 reserved1;
12153 	u32 oem_cfg_port;
12154 #define OEM_CFG_CHANNEL_TYPE_MASK                       0x00000003
12155 #define OEM_CFG_CHANNEL_TYPE_OFFSET                     0
12156 #define OEM_CFG_CHANNEL_TYPE_VLAN_PARTITION             0x1
12157 #define OEM_CFG_CHANNEL_TYPE_STAGGED                    0x2
12158 #define OEM_CFG_SCHED_TYPE_MASK                         0x0000000C
12159 #define OEM_CFG_SCHED_TYPE_OFFSET                       2
12160 #define OEM_CFG_SCHED_TYPE_ETS                          0x1
12161 #define OEM_CFG_SCHED_TYPE_VNIC_BW                      0x2
12162 };
12163 
12164 struct public_func {
12165 	u32 reserved0[2];
12166 
12167 	u32 mtu_size;
12168 
12169 	u32 reserved[7];
12170 
12171 	u32 config;
12172 #define FUNC_MF_CFG_FUNC_HIDE			0x00000001
12173 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING		0x00000002
12174 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT	0x00000001
12175 
12176 #define FUNC_MF_CFG_PROTOCOL_MASK	0x000000f0
12177 #define FUNC_MF_CFG_PROTOCOL_SHIFT	4
12178 #define FUNC_MF_CFG_PROTOCOL_ETHERNET	0x00000000
12179 #define FUNC_MF_CFG_PROTOCOL_ISCSI              0x00000010
12180 #define FUNC_MF_CFG_PROTOCOL_FCOE               0x00000020
12181 #define FUNC_MF_CFG_PROTOCOL_ROCE               0x00000030
12182 #define FUNC_MF_CFG_PROTOCOL_MAX	0x00000030
12183 
12184 #define FUNC_MF_CFG_MIN_BW_MASK		0x0000ff00
12185 #define FUNC_MF_CFG_MIN_BW_SHIFT	8
12186 #define FUNC_MF_CFG_MIN_BW_DEFAULT	0x00000000
12187 #define FUNC_MF_CFG_MAX_BW_MASK		0x00ff0000
12188 #define FUNC_MF_CFG_MAX_BW_SHIFT	16
12189 #define FUNC_MF_CFG_MAX_BW_DEFAULT	0x00640000
12190 
12191 	u32 status;
12192 #define FUNC_STATUS_VIRTUAL_LINK_UP	0x00000001
12193 
12194 	u32 mac_upper;
12195 #define FUNC_MF_CFG_UPPERMAC_MASK	0x0000ffff
12196 #define FUNC_MF_CFG_UPPERMAC_SHIFT	0
12197 #define FUNC_MF_CFG_UPPERMAC_DEFAULT	FUNC_MF_CFG_UPPERMAC_MASK
12198 	u32 mac_lower;
12199 #define FUNC_MF_CFG_LOWERMAC_DEFAULT	0xffffffff
12200 
12201 	u32 fcoe_wwn_port_name_upper;
12202 	u32 fcoe_wwn_port_name_lower;
12203 
12204 	u32 fcoe_wwn_node_name_upper;
12205 	u32 fcoe_wwn_node_name_lower;
12206 
12207 	u32 ovlan_stag;
12208 #define FUNC_MF_CFG_OV_STAG_MASK	0x0000ffff
12209 #define FUNC_MF_CFG_OV_STAG_SHIFT	0
12210 #define FUNC_MF_CFG_OV_STAG_DEFAULT	FUNC_MF_CFG_OV_STAG_MASK
12211 
12212 	u32 pf_allocation;
12213 
12214 	u32 preserve_data;
12215 
12216 	u32 driver_last_activity_ts;
12217 
12218 	u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32];
12219 
12220 	u32 drv_id;
12221 #define DRV_ID_PDA_COMP_VER_MASK	0x0000ffff
12222 #define DRV_ID_PDA_COMP_VER_SHIFT	0
12223 
12224 #define LOAD_REQ_HSI_VERSION		2
12225 #define DRV_ID_MCP_HSI_VER_MASK		0x00ff0000
12226 #define DRV_ID_MCP_HSI_VER_SHIFT	16
12227 #define DRV_ID_MCP_HSI_VER_CURRENT	(LOAD_REQ_HSI_VERSION << \
12228 					 DRV_ID_MCP_HSI_VER_SHIFT)
12229 
12230 #define DRV_ID_DRV_TYPE_MASK		0x7f000000
12231 #define DRV_ID_DRV_TYPE_SHIFT		24
12232 #define DRV_ID_DRV_TYPE_UNKNOWN		(0 << DRV_ID_DRV_TYPE_SHIFT)
12233 #define DRV_ID_DRV_TYPE_LINUX		(1 << DRV_ID_DRV_TYPE_SHIFT)
12234 
12235 #define DRV_ID_DRV_INIT_HW_MASK		0x80000000
12236 #define DRV_ID_DRV_INIT_HW_SHIFT	31
12237 #define DRV_ID_DRV_INIT_HW_FLAG		(1 << DRV_ID_DRV_INIT_HW_SHIFT)
12238 
12239 	u32 oem_cfg_func;
12240 #define OEM_CFG_FUNC_TC_MASK                    0x0000000F
12241 #define OEM_CFG_FUNC_TC_OFFSET                  0
12242 #define OEM_CFG_FUNC_TC_0                       0x0
12243 #define OEM_CFG_FUNC_TC_1                       0x1
12244 #define OEM_CFG_FUNC_TC_2                       0x2
12245 #define OEM_CFG_FUNC_TC_3                       0x3
12246 #define OEM_CFG_FUNC_TC_4                       0x4
12247 #define OEM_CFG_FUNC_TC_5                       0x5
12248 #define OEM_CFG_FUNC_TC_6                       0x6
12249 #define OEM_CFG_FUNC_TC_7                       0x7
12250 
12251 #define OEM_CFG_FUNC_HOST_PRI_CTRL_MASK         0x00000030
12252 #define OEM_CFG_FUNC_HOST_PRI_CTRL_OFFSET       4
12253 #define OEM_CFG_FUNC_HOST_PRI_CTRL_VNIC         0x1
12254 #define OEM_CFG_FUNC_HOST_PRI_CTRL_OS           0x2
12255 };
12256 
12257 struct mcp_mac {
12258 	u32 mac_upper;
12259 	u32 mac_lower;
12260 };
12261 
12262 struct mcp_val64 {
12263 	u32 lo;
12264 	u32 hi;
12265 };
12266 
12267 struct mcp_file_att {
12268 	u32 nvm_start_addr;
12269 	u32 len;
12270 };
12271 
12272 struct bist_nvm_image_att {
12273 	u32 return_code;
12274 	u32 image_type;
12275 	u32 nvm_start_addr;
12276 	u32 len;
12277 };
12278 
12279 #define MCP_DRV_VER_STR_SIZE 16
12280 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32))
12281 #define MCP_DRV_NVM_BUF_LEN 32
12282 struct drv_version_stc {
12283 	u32 version;
12284 	u8 name[MCP_DRV_VER_STR_SIZE - 4];
12285 };
12286 
12287 struct lan_stats_stc {
12288 	u64 ucast_rx_pkts;
12289 	u64 ucast_tx_pkts;
12290 	u32 fcs_err;
12291 	u32 rserved;
12292 };
12293 
12294 struct fcoe_stats_stc {
12295 	u64 rx_pkts;
12296 	u64 tx_pkts;
12297 	u32 fcs_err;
12298 	u32 login_failure;
12299 };
12300 
12301 struct ocbb_data_stc {
12302 	u32 ocbb_host_addr;
12303 	u32 ocsd_host_addr;
12304 	u32 ocsd_req_update_interval;
12305 };
12306 
12307 #define MAX_NUM_OF_SENSORS 7
12308 struct temperature_status_stc {
12309 	u32 num_of_sensors;
12310 	u32 sensor[MAX_NUM_OF_SENSORS];
12311 };
12312 
12313 /* crash dump configuration header */
12314 struct mdump_config_stc {
12315 	u32 version;
12316 	u32 config;
12317 	u32 epoc;
12318 	u32 num_of_logs;
12319 	u32 valid_logs;
12320 };
12321 
12322 enum resource_id_enum {
12323 	RESOURCE_NUM_SB_E = 0,
12324 	RESOURCE_NUM_L2_QUEUE_E = 1,
12325 	RESOURCE_NUM_VPORT_E = 2,
12326 	RESOURCE_NUM_VMQ_E = 3,
12327 	RESOURCE_FACTOR_NUM_RSS_PF_E = 4,
12328 	RESOURCE_FACTOR_RSS_PER_VF_E = 5,
12329 	RESOURCE_NUM_RL_E = 6,
12330 	RESOURCE_NUM_PQ_E = 7,
12331 	RESOURCE_NUM_VF_E = 8,
12332 	RESOURCE_VFC_FILTER_E = 9,
12333 	RESOURCE_ILT_E = 10,
12334 	RESOURCE_CQS_E = 11,
12335 	RESOURCE_GFT_PROFILES_E = 12,
12336 	RESOURCE_NUM_TC_E = 13,
12337 	RESOURCE_NUM_RSS_ENGINES_E = 14,
12338 	RESOURCE_LL2_QUEUE_E = 15,
12339 	RESOURCE_RDMA_STATS_QUEUE_E = 16,
12340 	RESOURCE_BDQ_E = 17,
12341 	RESOURCE_QCN_E = 18,
12342 	RESOURCE_LLH_FILTER_E = 19,
12343 	RESOURCE_VF_MAC_ADDR = 20,
12344 	RESOURCE_LL2_CQS_E = 21,
12345 	RESOURCE_VF_CNQS = 22,
12346 	RESOURCE_MAX_NUM,
12347 	RESOURCE_NUM_INVALID = 0xFFFFFFFF
12348 };
12349 
12350 /* Resource ID is to be filled by the driver in the MB request
12351  * Size, offset & flags to be filled by the MFW in the MB response
12352  */
12353 struct resource_info {
12354 	enum resource_id_enum res_id;
12355 	u32 size;		/* number of allocated resources */
12356 	u32 offset;		/* Offset of the 1st resource */
12357 	u32 vf_size;
12358 	u32 vf_offset;
12359 	u32 flags;
12360 #define RESOURCE_ELEMENT_STRICT (1 << 0)
12361 };
12362 
12363 #define DRV_ROLE_NONE           0
12364 #define DRV_ROLE_PREBOOT        1
12365 #define DRV_ROLE_OS             2
12366 #define DRV_ROLE_KDUMP          3
12367 
12368 struct load_req_stc {
12369 	u32 drv_ver_0;
12370 	u32 drv_ver_1;
12371 	u32 fw_ver;
12372 	u32 misc0;
12373 #define LOAD_REQ_ROLE_MASK              0x000000FF
12374 #define LOAD_REQ_ROLE_SHIFT             0
12375 #define LOAD_REQ_LOCK_TO_MASK           0x0000FF00
12376 #define LOAD_REQ_LOCK_TO_SHIFT          8
12377 #define LOAD_REQ_LOCK_TO_DEFAULT        0
12378 #define LOAD_REQ_LOCK_TO_NONE           255
12379 #define LOAD_REQ_FORCE_MASK             0x000F0000
12380 #define LOAD_REQ_FORCE_SHIFT            16
12381 #define LOAD_REQ_FORCE_NONE             0
12382 #define LOAD_REQ_FORCE_PF               1
12383 #define LOAD_REQ_FORCE_ALL              2
12384 #define LOAD_REQ_FLAGS0_MASK            0x00F00000
12385 #define LOAD_REQ_FLAGS0_SHIFT           20
12386 #define LOAD_REQ_FLAGS0_AVOID_RESET     (0x1 << 0)
12387 };
12388 
12389 struct load_rsp_stc {
12390 	u32 drv_ver_0;
12391 	u32 drv_ver_1;
12392 	u32 fw_ver;
12393 	u32 misc0;
12394 #define LOAD_RSP_ROLE_MASK              0x000000FF
12395 #define LOAD_RSP_ROLE_SHIFT             0
12396 #define LOAD_RSP_HSI_MASK               0x0000FF00
12397 #define LOAD_RSP_HSI_SHIFT              8
12398 #define LOAD_RSP_FLAGS0_MASK            0x000F0000
12399 #define LOAD_RSP_FLAGS0_SHIFT           16
12400 #define LOAD_RSP_FLAGS0_DRV_EXISTS      (0x1 << 0)
12401 };
12402 
12403 union drv_union_data {
12404 	u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD];
12405 	struct mcp_mac wol_mac;
12406 
12407 	struct eth_phy_cfg drv_phy_cfg;
12408 
12409 	struct mcp_val64 val64;
12410 
12411 	u8 raw_data[MCP_DRV_NVM_BUF_LEN];
12412 
12413 	struct mcp_file_att file_att;
12414 
12415 	u32 ack_vf_disabled[VF_MAX_STATIC / 32];
12416 
12417 	struct drv_version_stc drv_version;
12418 
12419 	struct lan_stats_stc lan_stats;
12420 	struct fcoe_stats_stc fcoe_stats;
12421 	struct ocbb_data_stc ocbb_info;
12422 	struct temperature_status_stc temp_info;
12423 	struct resource_info resource;
12424 	struct bist_nvm_image_att nvm_image_att;
12425 	struct mdump_config_stc mdump_config;
12426 };
12427 
12428 struct public_drv_mb {
12429 	u32 drv_mb_header;
12430 #define DRV_MSG_CODE_MASK			0xffff0000
12431 #define DRV_MSG_CODE_LOAD_REQ			0x10000000
12432 #define DRV_MSG_CODE_LOAD_DONE			0x11000000
12433 #define DRV_MSG_CODE_INIT_HW			0x12000000
12434 #define DRV_MSG_CODE_CANCEL_LOAD_REQ            0x13000000
12435 #define DRV_MSG_CODE_UNLOAD_REQ			0x20000000
12436 #define DRV_MSG_CODE_UNLOAD_DONE		0x21000000
12437 #define DRV_MSG_CODE_INIT_PHY			0x22000000
12438 #define DRV_MSG_CODE_LINK_RESET			0x23000000
12439 #define DRV_MSG_CODE_SET_DCBX			0x25000000
12440 #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG         0x26000000
12441 #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM          0x27000000
12442 #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS    0x28000000
12443 #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER     0x29000000
12444 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE     0x31000000
12445 #define DRV_MSG_CODE_BW_UPDATE_ACK              0x32000000
12446 #define DRV_MSG_CODE_OV_UPDATE_MTU              0x33000000
12447 #define DRV_MSG_GET_RESOURCE_ALLOC_MSG		0x34000000
12448 #define DRV_MSG_SET_RESOURCE_VALUE_MSG		0x35000000
12449 #define DRV_MSG_CODE_OV_UPDATE_WOL              0x38000000
12450 #define DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE     0x39000000
12451 #define DRV_MSG_CODE_GET_OEM_UPDATES            0x41000000
12452 
12453 #define DRV_MSG_CODE_BW_UPDATE_ACK		0x32000000
12454 #define DRV_MSG_CODE_NIG_DRAIN			0x30000000
12455 #define DRV_MSG_CODE_S_TAG_UPDATE_ACK		0x3b000000
12456 #define DRV_MSG_CODE_GET_NVM_CFG_OPTION		0x003e0000
12457 #define DRV_MSG_CODE_SET_NVM_CFG_OPTION		0x003f0000
12458 #define DRV_MSG_CODE_INITIATE_PF_FLR            0x02010000
12459 #define DRV_MSG_CODE_VF_DISABLED_DONE		0xc0000000
12460 #define DRV_MSG_CODE_CFG_VF_MSIX		0xc0010000
12461 #define DRV_MSG_CODE_CFG_PF_VFS_MSIX		0xc0020000
12462 #define DRV_MSG_CODE_NVM_PUT_FILE_BEGIN		0x00010000
12463 #define DRV_MSG_CODE_NVM_PUT_FILE_DATA		0x00020000
12464 #define DRV_MSG_CODE_NVM_GET_FILE_ATT		0x00030000
12465 #define DRV_MSG_CODE_NVM_READ_NVRAM		0x00050000
12466 #define DRV_MSG_CODE_NVM_WRITE_NVRAM		0x00060000
12467 #define DRV_MSG_CODE_MCP_RESET			0x00090000
12468 #define DRV_MSG_CODE_SET_VERSION		0x000f0000
12469 #define DRV_MSG_CODE_MCP_HALT                   0x00100000
12470 #define DRV_MSG_CODE_SET_VMAC                   0x00110000
12471 #define DRV_MSG_CODE_GET_VMAC                   0x00120000
12472 #define DRV_MSG_CODE_VMAC_TYPE_SHIFT            4
12473 #define DRV_MSG_CODE_VMAC_TYPE_MASK             0x30
12474 #define DRV_MSG_CODE_VMAC_TYPE_MAC              1
12475 #define DRV_MSG_CODE_VMAC_TYPE_WWNN             2
12476 #define DRV_MSG_CODE_VMAC_TYPE_WWPN             3
12477 
12478 #define DRV_MSG_CODE_GET_STATS                  0x00130000
12479 #define DRV_MSG_CODE_STATS_TYPE_LAN             1
12480 #define DRV_MSG_CODE_STATS_TYPE_FCOE            2
12481 #define DRV_MSG_CODE_STATS_TYPE_ISCSI           3
12482 #define DRV_MSG_CODE_STATS_TYPE_RDMA            4
12483 
12484 #define DRV_MSG_CODE_TRANSCEIVER_READ           0x00160000
12485 
12486 #define DRV_MSG_CODE_MASK_PARITIES              0x001a0000
12487 
12488 #define DRV_MSG_CODE_BIST_TEST			0x001e0000
12489 #define DRV_MSG_CODE_SET_LED_MODE		0x00200000
12490 #define DRV_MSG_CODE_RESOURCE_CMD		0x00230000
12491 #define DRV_MSG_CODE_GET_TLV_DONE		0x002f0000
12492 #define DRV_MSG_CODE_GET_ENGINE_CONFIG		0x00370000
12493 #define DRV_MSG_CODE_GET_PPFID_BITMAP		0x43000000
12494 
12495 #define RESOURCE_CMD_REQ_RESC_MASK		0x0000001F
12496 #define RESOURCE_CMD_REQ_RESC_SHIFT		0
12497 #define RESOURCE_CMD_REQ_OPCODE_MASK		0x000000E0
12498 #define RESOURCE_CMD_REQ_OPCODE_SHIFT		5
12499 #define RESOURCE_OPCODE_REQ			1
12500 #define RESOURCE_OPCODE_REQ_WO_AGING		2
12501 #define RESOURCE_OPCODE_REQ_W_AGING		3
12502 #define RESOURCE_OPCODE_RELEASE			4
12503 #define RESOURCE_OPCODE_FORCE_RELEASE		5
12504 #define RESOURCE_CMD_REQ_AGE_MASK		0x0000FF00
12505 #define RESOURCE_CMD_REQ_AGE_SHIFT		8
12506 
12507 #define RESOURCE_CMD_RSP_OWNER_MASK		0x000000FF
12508 #define RESOURCE_CMD_RSP_OWNER_SHIFT		0
12509 #define RESOURCE_CMD_RSP_OPCODE_MASK		0x00000700
12510 #define RESOURCE_CMD_RSP_OPCODE_SHIFT		8
12511 #define RESOURCE_OPCODE_GNT			1
12512 #define RESOURCE_OPCODE_BUSY			2
12513 #define RESOURCE_OPCODE_RELEASED		3
12514 #define RESOURCE_OPCODE_RELEASED_PREVIOUS	4
12515 #define RESOURCE_OPCODE_WRONG_OWNER		5
12516 #define RESOURCE_OPCODE_UNKNOWN_CMD		255
12517 
12518 #define RESOURCE_DUMP				0
12519 
12520 #define DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL	0x002b0000
12521 #define DRV_MSG_CODE_OS_WOL			0x002e0000
12522 
12523 #define DRV_MSG_CODE_FEATURE_SUPPORT		0x00300000
12524 #define DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT	0x00310000
12525 #define DRV_MSG_SEQ_NUMBER_MASK			0x0000ffff
12526 
12527 	u32 drv_mb_param;
12528 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN         0x00000000
12529 #define DRV_MB_PARAM_UNLOAD_WOL_MCP             0x00000001
12530 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED        0x00000002
12531 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED         0x00000003
12532 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK		0x000000FF
12533 #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT		3
12534 
12535 #define DRV_MB_PARAM_NVM_PUT_FILE_BEGIN_MBI     0x3
12536 #define DRV_MB_PARAM_NVM_OFFSET_OFFSET          0
12537 #define DRV_MB_PARAM_NVM_OFFSET_MASK            0x00FFFFFF
12538 #define DRV_MB_PARAM_NVM_LEN_OFFSET		24
12539 #define DRV_MB_PARAM_NVM_LEN_MASK               0xFF000000
12540 
12541 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT	0
12542 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK	0x000000FF
12543 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT	8
12544 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK	0x0000FF00
12545 #define DRV_MB_PARAM_LLDP_SEND_MASK		0x00000001
12546 #define DRV_MB_PARAM_LLDP_SEND_SHIFT		0
12547 
12548 #define DRV_MB_PARAM_OV_CURR_CFG_SHIFT		0
12549 #define DRV_MB_PARAM_OV_CURR_CFG_MASK		0x0000000F
12550 #define DRV_MB_PARAM_OV_CURR_CFG_NONE		0
12551 #define DRV_MB_PARAM_OV_CURR_CFG_OS		1
12552 #define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC	2
12553 #define DRV_MB_PARAM_OV_CURR_CFG_OTHER		3
12554 
12555 #define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT	0
12556 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK	0xFFFFFFFF
12557 #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK	0xFF000000
12558 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK	0x00FF0000
12559 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK	0x0000FF00
12560 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK	0x000000FF
12561 
12562 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT	0
12563 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK	0xF
12564 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN	0x1
12565 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED	0x2
12566 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING	0x3
12567 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED	0x4
12568 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE	0x5
12569 
12570 #define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT	0
12571 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK	0xFFFFFFFF
12572 
12573 #define DRV_MB_PARAM_WOL_MASK	(DRV_MB_PARAM_WOL_DEFAULT | \
12574 				 DRV_MB_PARAM_WOL_DISABLED | \
12575 				 DRV_MB_PARAM_WOL_ENABLED)
12576 #define DRV_MB_PARAM_WOL_DEFAULT	DRV_MB_PARAM_UNLOAD_WOL_MCP
12577 #define DRV_MB_PARAM_WOL_DISABLED	DRV_MB_PARAM_UNLOAD_WOL_DISABLED
12578 #define DRV_MB_PARAM_WOL_ENABLED	DRV_MB_PARAM_UNLOAD_WOL_ENABLED
12579 
12580 #define DRV_MB_PARAM_ESWITCH_MODE_MASK	(DRV_MB_PARAM_ESWITCH_MODE_NONE | \
12581 					 DRV_MB_PARAM_ESWITCH_MODE_VEB | \
12582 					 DRV_MB_PARAM_ESWITCH_MODE_VEPA)
12583 #define DRV_MB_PARAM_ESWITCH_MODE_NONE	0x0
12584 #define DRV_MB_PARAM_ESWITCH_MODE_VEB	0x1
12585 #define DRV_MB_PARAM_ESWITCH_MODE_VEPA	0x2
12586 
12587 #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_MASK	0x1
12588 #define DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET	0
12589 
12590 #define DRV_MB_PARAM_SET_LED_MODE_OPER		0x0
12591 #define DRV_MB_PARAM_SET_LED_MODE_ON		0x1
12592 #define DRV_MB_PARAM_SET_LED_MODE_OFF		0x2
12593 
12594 #define DRV_MB_PARAM_TRANSCEIVER_PORT_OFFSET		0
12595 #define DRV_MB_PARAM_TRANSCEIVER_PORT_MASK		0x00000003
12596 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_OFFSET		2
12597 #define DRV_MB_PARAM_TRANSCEIVER_SIZE_MASK		0x000000FC
12598 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_OFFSET	8
12599 #define DRV_MB_PARAM_TRANSCEIVER_I2C_ADDRESS_MASK	0x0000FF00
12600 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_OFFSET		16
12601 #define DRV_MB_PARAM_TRANSCEIVER_OFFSET_MASK		0xFFFF0000
12602 
12603 	/* Resource Allocation params - Driver version support */
12604 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK	0xFFFF0000
12605 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT	16
12606 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK	0x0000FFFF
12607 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT	0
12608 
12609 #define DRV_MB_PARAM_BIST_REGISTER_TEST		1
12610 #define DRV_MB_PARAM_BIST_CLOCK_TEST		2
12611 #define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES	3
12612 #define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX	4
12613 
12614 #define DRV_MB_PARAM_BIST_RC_UNKNOWN		0
12615 #define DRV_MB_PARAM_BIST_RC_PASSED		1
12616 #define DRV_MB_PARAM_BIST_RC_FAILED		2
12617 #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER	3
12618 
12619 #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT	0
12620 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK	0x000000FF
12621 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT	8
12622 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK		0x0000FF00
12623 
12624 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_MASK		0x0000FFFF
12625 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_OFFSET	0
12626 #define DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE		0x00000002
12627 #define DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_VLINK		0x00010000
12628 
12629 #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_SHIFT		0
12630 #define DRV_MB_PARAM_NVM_CFG_OPTION_ID_MASK		0x0000FFFF
12631 #define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_SHIFT		16
12632 #define DRV_MB_PARAM_NVM_CFG_OPTION_ALL_MASK		0x00010000
12633 #define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_SHIFT		17
12634 #define DRV_MB_PARAM_NVM_CFG_OPTION_INIT_MASK		0x00020000
12635 #define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_SHIFT	18
12636 #define DRV_MB_PARAM_NVM_CFG_OPTION_COMMIT_MASK		0x00040000
12637 #define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_SHIFT		19
12638 #define DRV_MB_PARAM_NVM_CFG_OPTION_FREE_MASK		0x00080000
12639 #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_SHIFT	20
12640 #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_SEL_MASK	0x00100000
12641 #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_SHIFT	24
12642 #define DRV_MB_PARAM_NVM_CFG_OPTION_ENTITY_ID_MASK	0x0f000000
12643 
12644 	u32 fw_mb_header;
12645 #define FW_MSG_CODE_MASK			0xffff0000
12646 #define FW_MSG_CODE_UNSUPPORTED                 0x00000000
12647 #define FW_MSG_CODE_DRV_LOAD_ENGINE		0x10100000
12648 #define FW_MSG_CODE_DRV_LOAD_PORT		0x10110000
12649 #define FW_MSG_CODE_DRV_LOAD_FUNCTION		0x10120000
12650 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA	0x10200000
12651 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1	0x10210000
12652 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG	0x10220000
12653 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI        0x10230000
12654 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE 0x10300000
12655 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT     0x10310000
12656 #define FW_MSG_CODE_DRV_LOAD_DONE		0x11100000
12657 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE		0x20110000
12658 #define FW_MSG_CODE_DRV_UNLOAD_PORT		0x20120000
12659 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION		0x20130000
12660 #define FW_MSG_CODE_DRV_UNLOAD_DONE		0x21100000
12661 #define FW_MSG_CODE_RESOURCE_ALLOC_OK           0x34000000
12662 #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN      0x35000000
12663 #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED   0x36000000
12664 #define FW_MSG_CODE_S_TAG_UPDATE_ACK_DONE	0x3b000000
12665 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE	0xb0010000
12666 
12667 #define FW_MSG_CODE_NVM_OK			0x00010000
12668 #define FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK	0x00400000
12669 #define FW_MSG_CODE_PHY_OK			0x00110000
12670 #define FW_MSG_CODE_OK				0x00160000
12671 #define FW_MSG_CODE_ERROR			0x00170000
12672 #define FW_MSG_CODE_TRANSCEIVER_DIAG_OK		0x00160000
12673 #define FW_MSG_CODE_TRANSCEIVER_DIAG_ERROR	0x00170000
12674 #define FW_MSG_CODE_TRANSCEIVER_NOT_PRESENT	0x00020000
12675 
12676 #define FW_MSG_CODE_OS_WOL_SUPPORTED            0x00800000
12677 #define FW_MSG_CODE_OS_WOL_NOT_SUPPORTED        0x00810000
12678 #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE	0x00870000
12679 #define FW_MSG_SEQ_NUMBER_MASK			0x0000ffff
12680 
12681 	u32 fw_mb_param;
12682 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK	0xFFFF0000
12683 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT	16
12684 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK	0x0000FFFF
12685 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT	0
12686 
12687 	/* get pf rdma protocol command responce */
12688 #define FW_MB_PARAM_GET_PF_RDMA_NONE		0x0
12689 #define FW_MB_PARAM_GET_PF_RDMA_ROCE		0x1
12690 #define FW_MB_PARAM_GET_PF_RDMA_IWARP		0x2
12691 #define FW_MB_PARAM_GET_PF_RDMA_BOTH		0x3
12692 
12693 /* get MFW feature support response */
12694 #define FW_MB_PARAM_FEATURE_SUPPORT_SMARTLINQ	0x00000001
12695 #define FW_MB_PARAM_FEATURE_SUPPORT_EEE		0x00000002
12696 #define FW_MB_PARAM_FEATURE_SUPPORT_VLINK	0x00010000
12697 
12698 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR	(1 << 0)
12699 
12700 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_MASK   0x00000001
12701 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALID_SHIFT 0
12702 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_MASK   0x00000002
12703 #define FW_MB_PARAM_ENG_CFG_FIR_AFFIN_VALUE_SHIFT 1
12704 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_MASK    0x00000004
12705 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALID_SHIFT  2
12706 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_MASK    0x00000008
12707 #define FW_MB_PARAM_ENG_CFG_L2_AFFIN_VALUE_SHIFT  3
12708 
12709 #define FW_MB_PARAM_PPFID_BITMAP_MASK	0xFF
12710 #define FW_MB_PARAM_PPFID_BITMAP_SHIFT	0
12711 
12712 	u32 drv_pulse_mb;
12713 #define DRV_PULSE_SEQ_MASK			0x00007fff
12714 #define DRV_PULSE_SYSTEM_TIME_MASK		0xffff0000
12715 #define DRV_PULSE_ALWAYS_ALIVE			0x00008000
12716 
12717 	u32 mcp_pulse_mb;
12718 #define MCP_PULSE_SEQ_MASK			0x00007fff
12719 #define MCP_PULSE_ALWAYS_ALIVE			0x00008000
12720 #define MCP_EVENT_MASK				0xffff0000
12721 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ	0x00010000
12722 
12723 	union drv_union_data union_data;
12724 };
12725 
12726 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_MASK	0x00ffffff
12727 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_OFFSET_SHIFT	0
12728 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE_MASK		0xff000000
12729 #define FW_MB_PARAM_NVM_PUT_FILE_REQ_SIZE_SHIFT		24
12730 
12731 enum MFW_DRV_MSG_TYPE {
12732 	MFW_DRV_MSG_LINK_CHANGE,
12733 	MFW_DRV_MSG_FLR_FW_ACK_FAILED,
12734 	MFW_DRV_MSG_VF_DISABLED,
12735 	MFW_DRV_MSG_LLDP_DATA_UPDATED,
12736 	MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED,
12737 	MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED,
12738 	MFW_DRV_MSG_ERROR_RECOVERY,
12739 	MFW_DRV_MSG_BW_UPDATE,
12740 	MFW_DRV_MSG_S_TAG_UPDATE,
12741 	MFW_DRV_MSG_GET_LAN_STATS,
12742 	MFW_DRV_MSG_GET_FCOE_STATS,
12743 	MFW_DRV_MSG_GET_ISCSI_STATS,
12744 	MFW_DRV_MSG_GET_RDMA_STATS,
12745 	MFW_DRV_MSG_BW_UPDATE10,
12746 	MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE,
12747 	MFW_DRV_MSG_BW_UPDATE11,
12748 	MFW_DRV_MSG_RESERVED,
12749 	MFW_DRV_MSG_GET_TLV_REQ,
12750 	MFW_DRV_MSG_OEM_CFG_UPDATE,
12751 	MFW_DRV_MSG_MAX
12752 };
12753 
12754 #define MFW_DRV_MSG_MAX_DWORDS(msgs)	(((msgs - 1) >> 2) + 1)
12755 #define MFW_DRV_MSG_DWORD(msg_id)	(msg_id >> 2)
12756 #define MFW_DRV_MSG_OFFSET(msg_id)	((msg_id & 0x3) << 3)
12757 #define MFW_DRV_MSG_MASK(msg_id)	(0xff << MFW_DRV_MSG_OFFSET(msg_id))
12758 
12759 struct public_mfw_mb {
12760 	u32 sup_msgs;
12761 	u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
12762 	u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)];
12763 };
12764 
12765 enum public_sections {
12766 	PUBLIC_DRV_MB,
12767 	PUBLIC_MFW_MB,
12768 	PUBLIC_GLOBAL,
12769 	PUBLIC_PATH,
12770 	PUBLIC_PORT,
12771 	PUBLIC_FUNC,
12772 	PUBLIC_MAX_SECTIONS
12773 };
12774 
12775 struct mcp_public_data {
12776 	u32 num_sections;
12777 	u32 sections[PUBLIC_MAX_SECTIONS];
12778 	struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX];
12779 	struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX];
12780 	struct public_global global;
12781 	struct public_path path[MCP_GLOB_PATH_MAX];
12782 	struct public_port port[MCP_GLOB_PORT_MAX];
12783 	struct public_func func[MCP_GLOB_FUNC_MAX];
12784 };
12785 
12786 #define MAX_I2C_TRANSACTION_SIZE	16
12787 
12788 /* OCBB definitions */
12789 enum tlvs {
12790 	/* Category 1: Device Properties */
12791 	DRV_TLV_CLP_STR,
12792 	DRV_TLV_CLP_STR_CTD,
12793 	/* Category 6: Device Configuration */
12794 	DRV_TLV_SCSI_TO,
12795 	DRV_TLV_R_T_TOV,
12796 	DRV_TLV_R_A_TOV,
12797 	DRV_TLV_E_D_TOV,
12798 	DRV_TLV_CR_TOV,
12799 	DRV_TLV_BOOT_TYPE,
12800 	/* Category 8: Port Configuration */
12801 	DRV_TLV_NPIV_ENABLED,
12802 	/* Category 10: Function Configuration */
12803 	DRV_TLV_FEATURE_FLAGS,
12804 	DRV_TLV_LOCAL_ADMIN_ADDR,
12805 	DRV_TLV_ADDITIONAL_MAC_ADDR_1,
12806 	DRV_TLV_ADDITIONAL_MAC_ADDR_2,
12807 	DRV_TLV_LSO_MAX_OFFLOAD_SIZE,
12808 	DRV_TLV_LSO_MIN_SEGMENT_COUNT,
12809 	DRV_TLV_PROMISCUOUS_MODE,
12810 	DRV_TLV_TX_DESCRIPTORS_QUEUE_SIZE,
12811 	DRV_TLV_RX_DESCRIPTORS_QUEUE_SIZE,
12812 	DRV_TLV_NUM_OF_NET_QUEUE_VMQ_CFG,
12813 	DRV_TLV_FLEX_NIC_OUTER_VLAN_ID,
12814 	DRV_TLV_OS_DRIVER_STATES,
12815 	DRV_TLV_PXE_BOOT_PROGRESS,
12816 	/* Category 12: FC/FCoE Configuration */
12817 	DRV_TLV_NPIV_STATE,
12818 	DRV_TLV_NUM_OF_NPIV_IDS,
12819 	DRV_TLV_SWITCH_NAME,
12820 	DRV_TLV_SWITCH_PORT_NUM,
12821 	DRV_TLV_SWITCH_PORT_ID,
12822 	DRV_TLV_VENDOR_NAME,
12823 	DRV_TLV_SWITCH_MODEL,
12824 	DRV_TLV_SWITCH_FW_VER,
12825 	DRV_TLV_QOS_PRIORITY_PER_802_1P,
12826 	DRV_TLV_PORT_ALIAS,
12827 	DRV_TLV_PORT_STATE,
12828 	DRV_TLV_FIP_TX_DESCRIPTORS_QUEUE_SIZE,
12829 	DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_SIZE,
12830 	DRV_TLV_LINK_FAILURE_COUNT,
12831 	DRV_TLV_FCOE_BOOT_PROGRESS,
12832 	/* Category 13: iSCSI Configuration */
12833 	DRV_TLV_TARGET_LLMNR_ENABLED,
12834 	DRV_TLV_HEADER_DIGEST_FLAG_ENABLED,
12835 	DRV_TLV_DATA_DIGEST_FLAG_ENABLED,
12836 	DRV_TLV_AUTHENTICATION_METHOD,
12837 	DRV_TLV_ISCSI_BOOT_TARGET_PORTAL,
12838 	DRV_TLV_MAX_FRAME_SIZE,
12839 	DRV_TLV_PDU_TX_DESCRIPTORS_QUEUE_SIZE,
12840 	DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_SIZE,
12841 	DRV_TLV_ISCSI_BOOT_PROGRESS,
12842 	/* Category 20: Device Data */
12843 	DRV_TLV_PCIE_BUS_RX_UTILIZATION,
12844 	DRV_TLV_PCIE_BUS_TX_UTILIZATION,
12845 	DRV_TLV_DEVICE_CPU_CORES_UTILIZATION,
12846 	DRV_TLV_LAST_VALID_DCC_TLV_RECEIVED,
12847 	DRV_TLV_NCSI_RX_BYTES_RECEIVED,
12848 	DRV_TLV_NCSI_TX_BYTES_SENT,
12849 	/* Category 22: Base Port Data */
12850 	DRV_TLV_RX_DISCARDS,
12851 	DRV_TLV_RX_ERRORS,
12852 	DRV_TLV_TX_ERRORS,
12853 	DRV_TLV_TX_DISCARDS,
12854 	DRV_TLV_RX_FRAMES_RECEIVED,
12855 	DRV_TLV_TX_FRAMES_SENT,
12856 	/* Category 23: FC/FCoE Port Data */
12857 	DRV_TLV_RX_BROADCAST_PACKETS,
12858 	DRV_TLV_TX_BROADCAST_PACKETS,
12859 	/* Category 28: Base Function Data */
12860 	DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV4,
12861 	DRV_TLV_NUM_OFFLOADED_CONNECTIONS_TCP_IPV6,
12862 	DRV_TLV_TX_DESCRIPTOR_QUEUE_AVG_DEPTH,
12863 	DRV_TLV_RX_DESCRIPTORS_QUEUE_AVG_DEPTH,
12864 	DRV_TLV_PF_RX_FRAMES_RECEIVED,
12865 	DRV_TLV_RX_BYTES_RECEIVED,
12866 	DRV_TLV_PF_TX_FRAMES_SENT,
12867 	DRV_TLV_TX_BYTES_SENT,
12868 	DRV_TLV_IOV_OFFLOAD,
12869 	DRV_TLV_PCI_ERRORS_CAP_ID,
12870 	DRV_TLV_UNCORRECTABLE_ERROR_STATUS,
12871 	DRV_TLV_UNCORRECTABLE_ERROR_MASK,
12872 	DRV_TLV_CORRECTABLE_ERROR_STATUS,
12873 	DRV_TLV_CORRECTABLE_ERROR_MASK,
12874 	DRV_TLV_PCI_ERRORS_AECC_REGISTER,
12875 	DRV_TLV_TX_QUEUES_EMPTY,
12876 	DRV_TLV_RX_QUEUES_EMPTY,
12877 	DRV_TLV_TX_QUEUES_FULL,
12878 	DRV_TLV_RX_QUEUES_FULL,
12879 	/* Category 29: FC/FCoE Function Data */
12880 	DRV_TLV_FCOE_TX_DESCRIPTOR_QUEUE_AVG_DEPTH,
12881 	DRV_TLV_FCOE_RX_DESCRIPTORS_QUEUE_AVG_DEPTH,
12882 	DRV_TLV_FCOE_RX_FRAMES_RECEIVED,
12883 	DRV_TLV_FCOE_RX_BYTES_RECEIVED,
12884 	DRV_TLV_FCOE_TX_FRAMES_SENT,
12885 	DRV_TLV_FCOE_TX_BYTES_SENT,
12886 	DRV_TLV_CRC_ERROR_COUNT,
12887 	DRV_TLV_CRC_ERROR_1_RECEIVED_SOURCE_FC_ID,
12888 	DRV_TLV_CRC_ERROR_1_TIMESTAMP,
12889 	DRV_TLV_CRC_ERROR_2_RECEIVED_SOURCE_FC_ID,
12890 	DRV_TLV_CRC_ERROR_2_TIMESTAMP,
12891 	DRV_TLV_CRC_ERROR_3_RECEIVED_SOURCE_FC_ID,
12892 	DRV_TLV_CRC_ERROR_3_TIMESTAMP,
12893 	DRV_TLV_CRC_ERROR_4_RECEIVED_SOURCE_FC_ID,
12894 	DRV_TLV_CRC_ERROR_4_TIMESTAMP,
12895 	DRV_TLV_CRC_ERROR_5_RECEIVED_SOURCE_FC_ID,
12896 	DRV_TLV_CRC_ERROR_5_TIMESTAMP,
12897 	DRV_TLV_LOSS_OF_SYNC_ERROR_COUNT,
12898 	DRV_TLV_LOSS_OF_SIGNAL_ERRORS,
12899 	DRV_TLV_PRIMITIVE_SEQUENCE_PROTOCOL_ERROR_COUNT,
12900 	DRV_TLV_DISPARITY_ERROR_COUNT,
12901 	DRV_TLV_CODE_VIOLATION_ERROR_COUNT,
12902 	DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_1,
12903 	DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_2,
12904 	DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_3,
12905 	DRV_TLV_LAST_FLOGI_ISSUED_COMMON_PARAMETERS_WORD_4,
12906 	DRV_TLV_LAST_FLOGI_TIMESTAMP,
12907 	DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_1,
12908 	DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_2,
12909 	DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_3,
12910 	DRV_TLV_LAST_FLOGI_ACC_COMMON_PARAMETERS_WORD_4,
12911 	DRV_TLV_LAST_FLOGI_ACC_TIMESTAMP,
12912 	DRV_TLV_LAST_FLOGI_RJT,
12913 	DRV_TLV_LAST_FLOGI_RJT_TIMESTAMP,
12914 	DRV_TLV_FDISCS_SENT_COUNT,
12915 	DRV_TLV_FDISC_ACCS_RECEIVED,
12916 	DRV_TLV_FDISC_RJTS_RECEIVED,
12917 	DRV_TLV_PLOGI_SENT_COUNT,
12918 	DRV_TLV_PLOGI_ACCS_RECEIVED,
12919 	DRV_TLV_PLOGI_RJTS_RECEIVED,
12920 	DRV_TLV_PLOGI_1_SENT_DESTINATION_FC_ID,
12921 	DRV_TLV_PLOGI_1_TIMESTAMP,
12922 	DRV_TLV_PLOGI_2_SENT_DESTINATION_FC_ID,
12923 	DRV_TLV_PLOGI_2_TIMESTAMP,
12924 	DRV_TLV_PLOGI_3_SENT_DESTINATION_FC_ID,
12925 	DRV_TLV_PLOGI_3_TIMESTAMP,
12926 	DRV_TLV_PLOGI_4_SENT_DESTINATION_FC_ID,
12927 	DRV_TLV_PLOGI_4_TIMESTAMP,
12928 	DRV_TLV_PLOGI_5_SENT_DESTINATION_FC_ID,
12929 	DRV_TLV_PLOGI_5_TIMESTAMP,
12930 	DRV_TLV_PLOGI_1_ACC_RECEIVED_SOURCE_FC_ID,
12931 	DRV_TLV_PLOGI_1_ACC_TIMESTAMP,
12932 	DRV_TLV_PLOGI_2_ACC_RECEIVED_SOURCE_FC_ID,
12933 	DRV_TLV_PLOGI_2_ACC_TIMESTAMP,
12934 	DRV_TLV_PLOGI_3_ACC_RECEIVED_SOURCE_FC_ID,
12935 	DRV_TLV_PLOGI_3_ACC_TIMESTAMP,
12936 	DRV_TLV_PLOGI_4_ACC_RECEIVED_SOURCE_FC_ID,
12937 	DRV_TLV_PLOGI_4_ACC_TIMESTAMP,
12938 	DRV_TLV_PLOGI_5_ACC_RECEIVED_SOURCE_FC_ID,
12939 	DRV_TLV_PLOGI_5_ACC_TIMESTAMP,
12940 	DRV_TLV_LOGOS_ISSUED,
12941 	DRV_TLV_LOGO_ACCS_RECEIVED,
12942 	DRV_TLV_LOGO_RJTS_RECEIVED,
12943 	DRV_TLV_LOGO_1_RECEIVED_SOURCE_FC_ID,
12944 	DRV_TLV_LOGO_1_TIMESTAMP,
12945 	DRV_TLV_LOGO_2_RECEIVED_SOURCE_FC_ID,
12946 	DRV_TLV_LOGO_2_TIMESTAMP,
12947 	DRV_TLV_LOGO_3_RECEIVED_SOURCE_FC_ID,
12948 	DRV_TLV_LOGO_3_TIMESTAMP,
12949 	DRV_TLV_LOGO_4_RECEIVED_SOURCE_FC_ID,
12950 	DRV_TLV_LOGO_4_TIMESTAMP,
12951 	DRV_TLV_LOGO_5_RECEIVED_SOURCE_FC_ID,
12952 	DRV_TLV_LOGO_5_TIMESTAMP,
12953 	DRV_TLV_LOGOS_RECEIVED,
12954 	DRV_TLV_ACCS_ISSUED,
12955 	DRV_TLV_PRLIS_ISSUED,
12956 	DRV_TLV_ACCS_RECEIVED,
12957 	DRV_TLV_ABTS_SENT_COUNT,
12958 	DRV_TLV_ABTS_ACCS_RECEIVED,
12959 	DRV_TLV_ABTS_RJTS_RECEIVED,
12960 	DRV_TLV_ABTS_1_SENT_DESTINATION_FC_ID,
12961 	DRV_TLV_ABTS_1_TIMESTAMP,
12962 	DRV_TLV_ABTS_2_SENT_DESTINATION_FC_ID,
12963 	DRV_TLV_ABTS_2_TIMESTAMP,
12964 	DRV_TLV_ABTS_3_SENT_DESTINATION_FC_ID,
12965 	DRV_TLV_ABTS_3_TIMESTAMP,
12966 	DRV_TLV_ABTS_4_SENT_DESTINATION_FC_ID,
12967 	DRV_TLV_ABTS_4_TIMESTAMP,
12968 	DRV_TLV_ABTS_5_SENT_DESTINATION_FC_ID,
12969 	DRV_TLV_ABTS_5_TIMESTAMP,
12970 	DRV_TLV_RSCNS_RECEIVED,
12971 	DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_1,
12972 	DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_2,
12973 	DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_3,
12974 	DRV_TLV_LAST_RSCN_RECEIVED_N_PORT_4,
12975 	DRV_TLV_LUN_RESETS_ISSUED,
12976 	DRV_TLV_ABORT_TASK_SETS_ISSUED,
12977 	DRV_TLV_TPRLOS_SENT,
12978 	DRV_TLV_NOS_SENT_COUNT,
12979 	DRV_TLV_NOS_RECEIVED_COUNT,
12980 	DRV_TLV_OLS_COUNT,
12981 	DRV_TLV_LR_COUNT,
12982 	DRV_TLV_LRR_COUNT,
12983 	DRV_TLV_LIP_SENT_COUNT,
12984 	DRV_TLV_LIP_RECEIVED_COUNT,
12985 	DRV_TLV_EOFA_COUNT,
12986 	DRV_TLV_EOFNI_COUNT,
12987 	DRV_TLV_SCSI_STATUS_CHECK_CONDITION_COUNT,
12988 	DRV_TLV_SCSI_STATUS_CONDITION_MET_COUNT,
12989 	DRV_TLV_SCSI_STATUS_BUSY_COUNT,
12990 	DRV_TLV_SCSI_STATUS_INTERMEDIATE_COUNT,
12991 	DRV_TLV_SCSI_STATUS_INTERMEDIATE_CONDITION_MET_COUNT,
12992 	DRV_TLV_SCSI_STATUS_RESERVATION_CONFLICT_COUNT,
12993 	DRV_TLV_SCSI_STATUS_TASK_SET_FULL_COUNT,
12994 	DRV_TLV_SCSI_STATUS_ACA_ACTIVE_COUNT,
12995 	DRV_TLV_SCSI_STATUS_TASK_ABORTED_COUNT,
12996 	DRV_TLV_SCSI_CHECK_CONDITION_1_RECEIVED_SK_ASC_ASCQ,
12997 	DRV_TLV_SCSI_CHECK_1_TIMESTAMP,
12998 	DRV_TLV_SCSI_CHECK_CONDITION_2_RECEIVED_SK_ASC_ASCQ,
12999 	DRV_TLV_SCSI_CHECK_2_TIMESTAMP,
13000 	DRV_TLV_SCSI_CHECK_CONDITION_3_RECEIVED_SK_ASC_ASCQ,
13001 	DRV_TLV_SCSI_CHECK_3_TIMESTAMP,
13002 	DRV_TLV_SCSI_CHECK_CONDITION_4_RECEIVED_SK_ASC_ASCQ,
13003 	DRV_TLV_SCSI_CHECK_4_TIMESTAMP,
13004 	DRV_TLV_SCSI_CHECK_CONDITION_5_RECEIVED_SK_ASC_ASCQ,
13005 	DRV_TLV_SCSI_CHECK_5_TIMESTAMP,
13006 	/* Category 30: iSCSI Function Data */
13007 	DRV_TLV_PDU_TX_DESCRIPTOR_QUEUE_AVG_DEPTH,
13008 	DRV_TLV_PDU_RX_DESCRIPTORS_QUEUE_AVG_DEPTH,
13009 	DRV_TLV_ISCSI_PDU_RX_FRAMES_RECEIVED,
13010 	DRV_TLV_ISCSI_PDU_RX_BYTES_RECEIVED,
13011 	DRV_TLV_ISCSI_PDU_TX_FRAMES_SENT,
13012 	DRV_TLV_ISCSI_PDU_TX_BYTES_SENT
13013 };
13014 
13015 struct nvm_cfg_mac_address {
13016 	u32 mac_addr_hi;
13017 #define NVM_CFG_MAC_ADDRESS_HI_MASK	0x0000FFFF
13018 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET	0
13019 	u32 mac_addr_lo;
13020 };
13021 
13022 struct nvm_cfg1_glob {
13023 	u32 generic_cont0;
13024 #define NVM_CFG1_GLOB_MF_MODE_MASK		0x00000FF0
13025 #define NVM_CFG1_GLOB_MF_MODE_OFFSET		4
13026 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED	0x0
13027 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT		0x1
13028 #define NVM_CFG1_GLOB_MF_MODE_SPIO4		0x2
13029 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0		0x3
13030 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5		0x4
13031 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0		0x5
13032 #define NVM_CFG1_GLOB_MF_MODE_BD		0x6
13033 #define NVM_CFG1_GLOB_MF_MODE_UFP		0x7
13034 	u32 engineering_change[3];
13035 	u32 manufacturing_id;
13036 	u32 serial_number[4];
13037 	u32 pcie_cfg;
13038 	u32 mgmt_traffic;
13039 	u32 core_cfg;
13040 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK		0x000000FF
13041 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET		0
13042 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G	0x0
13043 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G		0x1
13044 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G	0x2
13045 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F		0x3
13046 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E	0x4
13047 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G	0x5
13048 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G		0xB
13049 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G		0xC
13050 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G		0xD
13051 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G		0xE
13052 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G		0xF
13053 
13054 	u32 e_lane_cfg1;
13055 	u32 e_lane_cfg2;
13056 	u32 f_lane_cfg1;
13057 	u32 f_lane_cfg2;
13058 	u32 mps10_preemphasis;
13059 	u32 mps10_driver_current;
13060 	u32 mps25_preemphasis;
13061 	u32 mps25_driver_current;
13062 	u32 pci_id;
13063 	u32 pci_subsys_id;
13064 	u32 bar;
13065 	u32 mps10_txfir_main;
13066 	u32 mps10_txfir_post;
13067 	u32 mps25_txfir_main;
13068 	u32 mps25_txfir_post;
13069 	u32 manufacture_ver;
13070 	u32 manufacture_time;
13071 	u32 led_global_settings;
13072 	u32 generic_cont1;
13073 	u32 mbi_version;
13074 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK		0x000000FF
13075 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET		0
13076 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK		0x0000FF00
13077 #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET		8
13078 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK		0x00FF0000
13079 #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET		16
13080 	u32 mbi_date;
13081 	u32 misc_sig;
13082 	u32 device_capabilities;
13083 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET	0x1
13084 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE		0x2
13085 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI		0x4
13086 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE		0x8
13087 	u32 power_dissipated;
13088 	u32 power_consumed;
13089 	u32 efi_version;
13090 	u32 multi_network_modes_capability;
13091 	u32 reserved[41];
13092 };
13093 
13094 struct nvm_cfg1_path {
13095 	u32 reserved[30];
13096 };
13097 
13098 struct nvm_cfg1_port {
13099 	u32 reserved__m_relocated_to_option_123;
13100 	u32 reserved__m_relocated_to_option_124;
13101 	u32 generic_cont0;
13102 #define NVM_CFG1_PORT_DCBX_MODE_MASK				0x000F0000
13103 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET				16
13104 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED			0x0
13105 #define NVM_CFG1_PORT_DCBX_MODE_IEEE				0x1
13106 #define NVM_CFG1_PORT_DCBX_MODE_CEE				0x2
13107 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC				0x3
13108 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK		0x00F00000
13109 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET		20
13110 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET	0x1
13111 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE		0x2
13112 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI		0x4
13113 	u32 pcie_cfg;
13114 	u32 features;
13115 	u32 speed_cap_mask;
13116 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK		0x0000FFFF
13117 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET		0
13118 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G		0x1
13119 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G		0x2
13120 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_20G             0x4
13121 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G		0x8
13122 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G		0x10
13123 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G		0x20
13124 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G		0x40
13125 	u32 link_settings;
13126 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK			0x0000000F
13127 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET			0
13128 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG			0x0
13129 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G				0x1
13130 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G			0x2
13131 #define NVM_CFG1_PORT_DRV_LINK_SPEED_20G                        0x3
13132 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G			0x4
13133 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G			0x5
13134 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G			0x6
13135 #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G			0x7
13136 #define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ			0x8
13137 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK			0x00000070
13138 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET			4
13139 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG			0x1
13140 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX			0x2
13141 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX			0x4
13142 	u32 phy_cfg;
13143 	u32 mgmt_traffic;
13144 
13145 	u32 ext_phy;
13146 	/* EEE power saving mode */
13147 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK		0x00FF0000
13148 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET		16
13149 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED		0x0
13150 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED		0x1
13151 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE		0x2
13152 #define NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY		0x3
13153 
13154 	u32 mba_cfg1;
13155 	u32 mba_cfg2;
13156 	u32 vf_cfg;
13157 	struct nvm_cfg_mac_address lldp_mac_address;
13158 	u32 led_port_settings;
13159 	u32 transceiver_00;
13160 	u32 device_ids;
13161 	u32 board_cfg;
13162 #define NVM_CFG1_PORT_PORT_TYPE_MASK                            0x000000FF
13163 #define NVM_CFG1_PORT_PORT_TYPE_OFFSET                          0
13164 #define NVM_CFG1_PORT_PORT_TYPE_UNDEFINED                       0x0
13165 #define NVM_CFG1_PORT_PORT_TYPE_MODULE                          0x1
13166 #define NVM_CFG1_PORT_PORT_TYPE_BACKPLANE                       0x2
13167 #define NVM_CFG1_PORT_PORT_TYPE_EXT_PHY                         0x3
13168 #define NVM_CFG1_PORT_PORT_TYPE_MODULE_SLAVE                    0x4
13169 	u32 mnm_10g_cap;
13170 	u32 mnm_10g_ctrl;
13171 	u32 mnm_10g_misc;
13172 	u32 mnm_25g_cap;
13173 	u32 mnm_25g_ctrl;
13174 	u32 mnm_25g_misc;
13175 	u32 mnm_40g_cap;
13176 	u32 mnm_40g_ctrl;
13177 	u32 mnm_40g_misc;
13178 	u32 mnm_50g_cap;
13179 	u32 mnm_50g_ctrl;
13180 	u32 mnm_50g_misc;
13181 	u32 mnm_100g_cap;
13182 	u32 mnm_100g_ctrl;
13183 	u32 mnm_100g_misc;
13184 	u32 reserved[116];
13185 };
13186 
13187 struct nvm_cfg1_func {
13188 	struct nvm_cfg_mac_address mac_address;
13189 	u32 rsrv1;
13190 	u32 rsrv2;
13191 	u32 device_id;
13192 	u32 cmn_cfg;
13193 	u32 pci_cfg;
13194 	struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr;
13195 	struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr;
13196 	u32 preboot_generic_cfg;
13197 	u32 reserved[8];
13198 };
13199 
13200 struct nvm_cfg1 {
13201 	struct nvm_cfg1_glob glob;
13202 	struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX];
13203 	struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX];
13204 	struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX];
13205 };
13206 
13207 enum spad_sections {
13208 	SPAD_SECTION_TRACE,
13209 	SPAD_SECTION_NVM_CFG,
13210 	SPAD_SECTION_PUBLIC,
13211 	SPAD_SECTION_PRIVATE,
13212 	SPAD_SECTION_MAX
13213 };
13214 
13215 #define MCP_TRACE_SIZE          2048	/* 2kb */
13216 
13217 /* This section is located at a fixed location in the beginning of the
13218  * scratchpad, to ensure that the MCP trace is not run over during MFW upgrade.
13219  * All the rest of data has a floating location which differs from version to
13220  * version, and is pointed by the mcp_meta_data below.
13221  * Moreover, the spad_layout section is part of the MFW firmware, and is loaded
13222  * with it from nvram in order to clear this portion.
13223  */
13224 struct static_init {
13225 	u32 num_sections;
13226 	offsize_t sections[SPAD_SECTION_MAX];
13227 #define SECTION(_sec_) (*((offsize_t *)(STRUCT_OFFSET(sections[_sec_]))))
13228 
13229 	struct mcp_trace trace;
13230 #define MCP_TRACE_P ((struct mcp_trace *)(STRUCT_OFFSET(trace)))
13231 	u8 trace_buffer[MCP_TRACE_SIZE];
13232 #define MCP_TRACE_BUF ((u8 *)(STRUCT_OFFSET(trace_buffer)))
13233 	/* running_mfw has the same definition as in nvm_map.h.
13234 	 * This bit indicate both the running dir, and the running bundle.
13235 	 * It is set once when the LIM is loaded.
13236 	 */
13237 	u32 running_mfw;
13238 #define RUNNING_MFW (*((u32 *)(STRUCT_OFFSET(running_mfw))))
13239 	u32 build_time;
13240 #define MFW_BUILD_TIME (*((u32 *)(STRUCT_OFFSET(build_time))))
13241 	u32 reset_type;
13242 #define RESET_TYPE (*((u32 *)(STRUCT_OFFSET(reset_type))))
13243 	u32 mfw_secure_mode;
13244 #define MFW_SECURE_MODE (*((u32 *)(STRUCT_OFFSET(mfw_secure_mode))))
13245 	u16 pme_status_pf_bitmap;
13246 #define PME_STATUS_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_status_pf_bitmap))))
13247 	u16 pme_enable_pf_bitmap;
13248 #define PME_ENABLE_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_enable_pf_bitmap))))
13249 	u32 mim_nvm_addr;
13250 	u32 mim_start_addr;
13251 	u32 ah_pcie_link_params;
13252 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_MASK     (0x000000ff)
13253 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_SHIFT    (0)
13254 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_MASK     (0x0000ff00)
13255 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_SHIFT    (8)
13256 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_MASK      (0x00ff0000)
13257 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_SHIFT     (16)
13258 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_MASK       (0xff000000)
13259 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_SHIFT      (24)
13260 #define AH_PCIE_LINK_PARAMS (*((u32 *)(STRUCT_OFFSET(ah_pcie_link_params))))
13261 
13262 	u32 rsrv_persist[5];	/* Persist reserved for MFW upgrades */
13263 };
13264 
13265 #define NVM_MAGIC_VALUE		0x669955aa
13266 
13267 enum nvm_image_type {
13268 	NVM_TYPE_TIM1 = 0x01,
13269 	NVM_TYPE_TIM2 = 0x02,
13270 	NVM_TYPE_MIM1 = 0x03,
13271 	NVM_TYPE_MIM2 = 0x04,
13272 	NVM_TYPE_MBA = 0x05,
13273 	NVM_TYPE_MODULES_PN = 0x06,
13274 	NVM_TYPE_VPD = 0x07,
13275 	NVM_TYPE_MFW_TRACE1 = 0x08,
13276 	NVM_TYPE_MFW_TRACE2 = 0x09,
13277 	NVM_TYPE_NVM_CFG1 = 0x0a,
13278 	NVM_TYPE_L2B = 0x0b,
13279 	NVM_TYPE_DIR1 = 0x0c,
13280 	NVM_TYPE_EAGLE_FW1 = 0x0d,
13281 	NVM_TYPE_FALCON_FW1 = 0x0e,
13282 	NVM_TYPE_PCIE_FW1 = 0x0f,
13283 	NVM_TYPE_HW_SET = 0x10,
13284 	NVM_TYPE_LIM = 0x11,
13285 	NVM_TYPE_AVS_FW1 = 0x12,
13286 	NVM_TYPE_DIR2 = 0x13,
13287 	NVM_TYPE_CCM = 0x14,
13288 	NVM_TYPE_EAGLE_FW2 = 0x15,
13289 	NVM_TYPE_FALCON_FW2 = 0x16,
13290 	NVM_TYPE_PCIE_FW2 = 0x17,
13291 	NVM_TYPE_AVS_FW2 = 0x18,
13292 	NVM_TYPE_INIT_HW = 0x19,
13293 	NVM_TYPE_DEFAULT_CFG = 0x1a,
13294 	NVM_TYPE_MDUMP = 0x1b,
13295 	NVM_TYPE_META = 0x1c,
13296 	NVM_TYPE_ISCSI_CFG = 0x1d,
13297 	NVM_TYPE_FCOE_CFG = 0x1f,
13298 	NVM_TYPE_ETH_PHY_FW1 = 0x20,
13299 	NVM_TYPE_ETH_PHY_FW2 = 0x21,
13300 	NVM_TYPE_BDN = 0x22,
13301 	NVM_TYPE_8485X_PHY_FW = 0x23,
13302 	NVM_TYPE_PUB_KEY = 0x24,
13303 	NVM_TYPE_RECOVERY = 0x25,
13304 	NVM_TYPE_PLDM = 0x26,
13305 	NVM_TYPE_UPK1 = 0x27,
13306 	NVM_TYPE_UPK2 = 0x28,
13307 	NVM_TYPE_MASTER_KC = 0x29,
13308 	NVM_TYPE_BACKUP_KC = 0x2a,
13309 	NVM_TYPE_HW_DUMP = 0x2b,
13310 	NVM_TYPE_HW_DUMP_OUT = 0x2c,
13311 	NVM_TYPE_BIN_NVM_META = 0x30,
13312 	NVM_TYPE_ROM_TEST = 0xf0,
13313 	NVM_TYPE_88X33X0_PHY_FW = 0x31,
13314 	NVM_TYPE_88X33X0_PHY_SLAVE_FW = 0x32,
13315 	NVM_TYPE_MAX,
13316 };
13317 
13318 #define DIR_ID_1    (0)
13319 
13320 #endif
13321