1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _QED_HSI_H 34 #define _QED_HSI_H 35 36 #include <linux/types.h> 37 #include <linux/io.h> 38 #include <linux/bitops.h> 39 #include <linux/delay.h> 40 #include <linux/kernel.h> 41 #include <linux/list.h> 42 #include <linux/slab.h> 43 #include <linux/qed/common_hsi.h> 44 #include <linux/qed/storage_common.h> 45 #include <linux/qed/tcp_common.h> 46 #include <linux/qed/fcoe_common.h> 47 #include <linux/qed/eth_common.h> 48 #include <linux/qed/iscsi_common.h> 49 #include <linux/qed/rdma_common.h> 50 #include <linux/qed/roce_common.h> 51 #include <linux/qed/qed_fcoe_if.h> 52 53 struct qed_hwfn; 54 struct qed_ptt; 55 56 /* opcodes for the event ring */ 57 enum common_event_opcode { 58 COMMON_EVENT_PF_START, 59 COMMON_EVENT_PF_STOP, 60 COMMON_EVENT_VF_START, 61 COMMON_EVENT_VF_STOP, 62 COMMON_EVENT_VF_PF_CHANNEL, 63 COMMON_EVENT_VF_FLR, 64 COMMON_EVENT_PF_UPDATE, 65 COMMON_EVENT_MALICIOUS_VF, 66 COMMON_EVENT_RL_UPDATE, 67 COMMON_EVENT_EMPTY, 68 MAX_COMMON_EVENT_OPCODE 69 }; 70 71 /* Common Ramrod Command IDs */ 72 enum common_ramrod_cmd_id { 73 COMMON_RAMROD_UNUSED, 74 COMMON_RAMROD_PF_START, 75 COMMON_RAMROD_PF_STOP, 76 COMMON_RAMROD_VF_START, 77 COMMON_RAMROD_VF_STOP, 78 COMMON_RAMROD_PF_UPDATE, 79 COMMON_RAMROD_RL_UPDATE, 80 COMMON_RAMROD_EMPTY, 81 MAX_COMMON_RAMROD_CMD_ID 82 }; 83 84 /* The core storm context for the Ystorm */ 85 struct ystorm_core_conn_st_ctx { 86 __le32 reserved[4]; 87 }; 88 89 /* The core storm context for the Pstorm */ 90 struct pstorm_core_conn_st_ctx { 91 __le32 reserved[4]; 92 }; 93 94 /* Core Slowpath Connection storm context of Xstorm */ 95 struct xstorm_core_conn_st_ctx { 96 __le32 spq_base_lo; 97 __le32 spq_base_hi; 98 struct regpair consolid_base_addr; 99 __le16 spq_cons; 100 __le16 consolid_cons; 101 __le32 reserved0[55]; 102 }; 103 104 struct xstorm_core_conn_ag_ctx { 105 u8 reserved0; 106 u8 core_state; 107 u8 flags0; 108 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 109 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 110 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1 111 #define XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1 112 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1 113 #define XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2 114 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 115 #define XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 116 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1 117 #define XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4 118 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1 119 #define XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5 120 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1 121 #define XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6 122 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1 123 #define XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7 124 u8 flags1; 125 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1 126 #define XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0 127 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1 128 #define XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1 129 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1 130 #define XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2 131 #define XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1 132 #define XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3 133 #define XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1 134 #define XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4 135 #define XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1 136 #define XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5 137 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 138 #define XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 139 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 140 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 141 u8 flags2; 142 #define XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 143 #define XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0 144 #define XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 145 #define XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2 146 #define XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 147 #define XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4 148 #define XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 149 #define XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6 150 u8 flags3; 151 #define XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 152 #define XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0 153 #define XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 154 #define XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2 155 #define XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 156 #define XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4 157 #define XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 158 #define XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6 159 u8 flags4; 160 #define XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 161 #define XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0 162 #define XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 163 #define XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2 164 #define XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 165 #define XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4 166 #define XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3 167 #define XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6 168 u8 flags5; 169 #define XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3 170 #define XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0 171 #define XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3 172 #define XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2 173 #define XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3 174 #define XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4 175 #define XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3 176 #define XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6 177 u8 flags6; 178 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3 179 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0 180 #define XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3 181 #define XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2 182 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3 183 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4 184 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 185 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 186 u8 flags7; 187 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 188 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 189 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3 190 #define XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2 191 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 192 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 193 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 194 #define XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6 195 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 196 #define XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7 197 u8 flags8; 198 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 199 #define XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0 200 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 201 #define XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1 202 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 203 #define XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2 204 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 205 #define XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3 206 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 207 #define XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4 208 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 209 #define XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5 210 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 211 #define XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6 212 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 213 #define XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7 214 u8 flags9; 215 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 216 #define XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0 217 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1 218 #define XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1 219 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1 220 #define XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2 221 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1 222 #define XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3 223 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1 224 #define XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4 225 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1 226 #define XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5 227 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1 228 #define XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6 229 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1 230 #define XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7 231 u8 flags10; 232 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 233 #define XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 234 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 235 #define XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 236 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 237 #define XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 238 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1 239 #define XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3 240 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 241 #define XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 242 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1 243 #define XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5 244 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1 245 #define XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6 246 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1 247 #define XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7 248 u8 flags11; 249 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1 250 #define XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0 251 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1 252 #define XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1 253 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 254 #define XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 255 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 256 #define XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3 257 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 258 #define XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4 259 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 260 #define XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5 261 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 262 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 263 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1 264 #define XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7 265 u8 flags12; 266 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1 267 #define XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0 268 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1 269 #define XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1 270 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 271 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 272 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 273 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 274 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1 275 #define XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4 276 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1 277 #define XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5 278 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1 279 #define XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6 280 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1 281 #define XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7 282 u8 flags13; 283 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1 284 #define XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0 285 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1 286 #define XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1 287 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 288 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 289 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 290 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 291 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 292 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 293 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 294 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 295 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 296 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 297 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 298 #define XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 299 u8 flags14; 300 #define XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1 301 #define XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0 302 #define XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1 303 #define XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1 304 #define XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1 305 #define XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2 306 #define XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1 307 #define XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3 308 #define XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1 309 #define XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4 310 #define XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1 311 #define XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5 312 #define XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3 313 #define XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6 314 u8 byte2; 315 __le16 physical_q0; 316 __le16 consolid_prod; 317 __le16 reserved16; 318 __le16 tx_bd_cons; 319 __le16 tx_bd_or_spq_prod; 320 __le16 word5; 321 __le16 conn_dpi; 322 u8 byte3; 323 u8 byte4; 324 u8 byte5; 325 u8 byte6; 326 __le32 reg0; 327 __le32 reg1; 328 __le32 reg2; 329 __le32 reg3; 330 __le32 reg4; 331 __le32 reg5; 332 __le32 reg6; 333 __le16 word7; 334 __le16 word8; 335 __le16 word9; 336 __le16 word10; 337 __le32 reg7; 338 __le32 reg8; 339 __le32 reg9; 340 u8 byte7; 341 u8 byte8; 342 u8 byte9; 343 u8 byte10; 344 u8 byte11; 345 u8 byte12; 346 u8 byte13; 347 u8 byte14; 348 u8 byte15; 349 u8 e5_reserved; 350 __le16 word11; 351 __le32 reg10; 352 __le32 reg11; 353 __le32 reg12; 354 __le32 reg13; 355 __le32 reg14; 356 __le32 reg15; 357 __le32 reg16; 358 __le32 reg17; 359 __le32 reg18; 360 __le32 reg19; 361 __le16 word12; 362 __le16 word13; 363 __le16 word14; 364 __le16 word15; 365 }; 366 367 struct tstorm_core_conn_ag_ctx { 368 u8 byte0; 369 u8 byte1; 370 u8 flags0; 371 #define TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 372 #define TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 373 #define TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 374 #define TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 375 #define TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 376 #define TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2 377 #define TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 378 #define TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3 379 #define TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 380 #define TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4 381 #define TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 382 #define TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5 383 #define TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 384 #define TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6 385 u8 flags1; 386 #define TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 387 #define TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0 388 #define TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 389 #define TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2 390 #define TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 391 #define TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4 392 #define TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 393 #define TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6 394 u8 flags2; 395 #define TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 396 #define TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0 397 #define TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 398 #define TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2 399 #define TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 400 #define TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4 401 #define TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 402 #define TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6 403 u8 flags3; 404 #define TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 405 #define TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0 406 #define TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 407 #define TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2 408 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 409 #define TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4 410 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 411 #define TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5 412 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 413 #define TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6 414 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 415 #define TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7 416 u8 flags4; 417 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 418 #define TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0 419 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 420 #define TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1 421 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 422 #define TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2 423 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 424 #define TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3 425 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 426 #define TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4 427 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 428 #define TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5 429 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 430 #define TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6 431 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 432 #define TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7 433 u8 flags5; 434 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 435 #define TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0 436 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 437 #define TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1 438 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 439 #define TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2 440 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 441 #define TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3 442 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 443 #define TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4 444 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 445 #define TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5 446 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 447 #define TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6 448 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 449 #define TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7 450 __le32 reg0; 451 __le32 reg1; 452 __le32 reg2; 453 __le32 reg3; 454 __le32 reg4; 455 __le32 reg5; 456 __le32 reg6; 457 __le32 reg7; 458 __le32 reg8; 459 u8 byte2; 460 u8 byte3; 461 __le16 word0; 462 u8 byte4; 463 u8 byte5; 464 __le16 word1; 465 __le16 word2; 466 __le16 word3; 467 __le32 reg9; 468 __le32 reg10; 469 }; 470 471 struct ustorm_core_conn_ag_ctx { 472 u8 reserved; 473 u8 byte1; 474 u8 flags0; 475 #define USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 476 #define USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 477 #define USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 478 #define USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 479 #define USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 480 #define USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 481 #define USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 482 #define USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 483 #define USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 484 #define USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 485 u8 flags1; 486 #define USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 487 #define USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0 488 #define USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 489 #define USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2 490 #define USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 491 #define USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4 492 #define USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 493 #define USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6 494 u8 flags2; 495 #define USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 496 #define USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 497 #define USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 498 #define USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 499 #define USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 500 #define USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 501 #define USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 502 #define USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3 503 #define USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 504 #define USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4 505 #define USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 506 #define USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5 507 #define USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 508 #define USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6 509 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 510 #define USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7 511 u8 flags3; 512 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 513 #define USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0 514 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 515 #define USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1 516 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 517 #define USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2 518 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 519 #define USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3 520 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 521 #define USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4 522 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 523 #define USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5 524 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 525 #define USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6 526 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 527 #define USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7 528 u8 byte2; 529 u8 byte3; 530 __le16 word0; 531 __le16 word1; 532 __le32 rx_producers; 533 __le32 reg1; 534 __le32 reg2; 535 __le32 reg3; 536 __le16 word2; 537 __le16 word3; 538 }; 539 540 /* The core storm context for the Mstorm */ 541 struct mstorm_core_conn_st_ctx { 542 __le32 reserved[24]; 543 }; 544 545 /* The core storm context for the Ustorm */ 546 struct ustorm_core_conn_st_ctx { 547 __le32 reserved[4]; 548 }; 549 550 /* core connection context */ 551 struct core_conn_context { 552 struct ystorm_core_conn_st_ctx ystorm_st_context; 553 struct regpair ystorm_st_padding[2]; 554 struct pstorm_core_conn_st_ctx pstorm_st_context; 555 struct regpair pstorm_st_padding[2]; 556 struct xstorm_core_conn_st_ctx xstorm_st_context; 557 struct xstorm_core_conn_ag_ctx xstorm_ag_context; 558 struct tstorm_core_conn_ag_ctx tstorm_ag_context; 559 struct ustorm_core_conn_ag_ctx ustorm_ag_context; 560 struct mstorm_core_conn_st_ctx mstorm_st_context; 561 struct ustorm_core_conn_st_ctx ustorm_st_context; 562 struct regpair ustorm_st_padding[2]; 563 }; 564 565 enum core_error_handle { 566 LL2_DROP_PACKET, 567 LL2_DO_NOTHING, 568 LL2_ASSERT, 569 MAX_CORE_ERROR_HANDLE 570 }; 571 572 enum core_event_opcode { 573 CORE_EVENT_TX_QUEUE_START, 574 CORE_EVENT_TX_QUEUE_STOP, 575 CORE_EVENT_RX_QUEUE_START, 576 CORE_EVENT_RX_QUEUE_STOP, 577 CORE_EVENT_RX_QUEUE_FLUSH, 578 MAX_CORE_EVENT_OPCODE 579 }; 580 581 enum core_l4_pseudo_checksum_mode { 582 CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH, 583 CORE_L4_PSEUDO_CSUM_ZERO_LENGTH, 584 MAX_CORE_L4_PSEUDO_CHECKSUM_MODE 585 }; 586 587 struct core_ll2_port_stats { 588 struct regpair gsi_invalid_hdr; 589 struct regpair gsi_invalid_pkt_length; 590 struct regpair gsi_unsupported_pkt_typ; 591 struct regpair gsi_crcchksm_error; 592 }; 593 594 struct core_ll2_pstorm_per_queue_stat { 595 struct regpair sent_ucast_bytes; 596 struct regpair sent_mcast_bytes; 597 struct regpair sent_bcast_bytes; 598 struct regpair sent_ucast_pkts; 599 struct regpair sent_mcast_pkts; 600 struct regpair sent_bcast_pkts; 601 }; 602 603 struct core_ll2_rx_prod { 604 __le16 bd_prod; 605 __le16 cqe_prod; 606 __le32 reserved; 607 }; 608 609 struct core_ll2_tstorm_per_queue_stat { 610 struct regpair packet_too_big_discard; 611 struct regpair no_buff_discard; 612 }; 613 614 struct core_ll2_ustorm_per_queue_stat { 615 struct regpair rcv_ucast_bytes; 616 struct regpair rcv_mcast_bytes; 617 struct regpair rcv_bcast_bytes; 618 struct regpair rcv_ucast_pkts; 619 struct regpair rcv_mcast_pkts; 620 struct regpair rcv_bcast_pkts; 621 }; 622 623 enum core_ramrod_cmd_id { 624 CORE_RAMROD_UNUSED, 625 CORE_RAMROD_RX_QUEUE_START, 626 CORE_RAMROD_TX_QUEUE_START, 627 CORE_RAMROD_RX_QUEUE_STOP, 628 CORE_RAMROD_TX_QUEUE_STOP, 629 CORE_RAMROD_RX_QUEUE_FLUSH, 630 MAX_CORE_RAMROD_CMD_ID 631 }; 632 633 enum core_roce_flavor_type { 634 CORE_ROCE, 635 CORE_RROCE, 636 MAX_CORE_ROCE_FLAVOR_TYPE 637 }; 638 639 struct core_rx_action_on_error { 640 u8 error_type; 641 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3 642 #define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0 643 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3 644 #define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT 2 645 #define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF 646 #define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT 4 647 }; 648 649 struct core_rx_bd { 650 struct regpair addr; 651 __le16 reserved[4]; 652 }; 653 654 struct core_rx_bd_with_buff_len { 655 struct regpair addr; 656 __le16 buff_length; 657 __le16 reserved[3]; 658 }; 659 660 union core_rx_bd_union { 661 struct core_rx_bd rx_bd; 662 struct core_rx_bd_with_buff_len rx_bd_with_len; 663 }; 664 665 struct core_rx_cqe_opaque_data { 666 __le32 data[2]; 667 }; 668 669 enum core_rx_cqe_type { 670 CORE_RX_CQE_ILLIGAL_TYPE, 671 CORE_RX_CQE_TYPE_REGULAR, 672 CORE_RX_CQE_TYPE_GSI_OFFLOAD, 673 CORE_RX_CQE_TYPE_SLOW_PATH, 674 MAX_CORE_RX_CQE_TYPE 675 }; 676 677 struct core_rx_fast_path_cqe { 678 u8 type; 679 u8 placement_offset; 680 struct parsing_and_err_flags parse_flags; 681 __le16 packet_length; 682 __le16 vlan; 683 struct core_rx_cqe_opaque_data opaque_data; 684 struct parsing_err_flags err_flags; 685 __le16 reserved0; 686 __le32 reserved1[3]; 687 }; 688 689 struct core_rx_gsi_offload_cqe { 690 u8 type; 691 u8 data_length_error; 692 struct parsing_and_err_flags parse_flags; 693 __le16 data_length; 694 __le16 vlan; 695 __le32 src_mac_addrhi; 696 __le16 src_mac_addrlo; 697 __le16 qp_id; 698 __le32 gid_dst[4]; 699 }; 700 701 struct core_rx_slow_path_cqe { 702 u8 type; 703 u8 ramrod_cmd_id; 704 __le16 echo; 705 struct core_rx_cqe_opaque_data opaque_data; 706 __le32 reserved1[5]; 707 }; 708 709 union core_rx_cqe_union { 710 struct core_rx_fast_path_cqe rx_cqe_fp; 711 struct core_rx_gsi_offload_cqe rx_cqe_gsi; 712 struct core_rx_slow_path_cqe rx_cqe_sp; 713 }; 714 715 struct core_rx_start_ramrod_data { 716 struct regpair bd_base; 717 struct regpair cqe_pbl_addr; 718 __le16 mtu; 719 __le16 sb_id; 720 u8 sb_index; 721 u8 complete_cqe_flg; 722 u8 complete_event_flg; 723 u8 drop_ttl0_flg; 724 __le16 num_of_pbl_pages; 725 u8 inner_vlan_removal_en; 726 u8 queue_id; 727 u8 main_func_queue; 728 u8 mf_si_bcast_accept_all; 729 u8 mf_si_mcast_accept_all; 730 struct core_rx_action_on_error action_on_error; 731 u8 gsi_offload_flag; 732 u8 reserved[7]; 733 }; 734 735 struct core_rx_stop_ramrod_data { 736 u8 complete_cqe_flg; 737 u8 complete_event_flg; 738 u8 queue_id; 739 u8 reserved1; 740 __le16 reserved2[2]; 741 }; 742 743 struct core_tx_bd_data { 744 __le16 as_bitfield; 745 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1 746 #define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0 747 #define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1 748 #define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT 1 749 #define CORE_TX_BD_DATA_START_BD_MASK 0x1 750 #define CORE_TX_BD_DATA_START_BD_SHIFT 2 751 #define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1 752 #define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3 753 #define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1 754 #define CORE_TX_BD_DATA_L4_CSUM_SHIFT 4 755 #define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1 756 #define CORE_TX_BD_DATA_IPV6_EXT_SHIFT 5 757 #define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1 758 #define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT 6 759 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1 760 #define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT 7 761 #define CORE_TX_BD_DATA_NBDS_MASK 0xF 762 #define CORE_TX_BD_DATA_NBDS_SHIFT 8 763 #define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1 764 #define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT 12 765 #define CORE_TX_BD_DATA_IP_LEN_MASK 0x1 766 #define CORE_TX_BD_DATA_IP_LEN_SHIFT 13 767 #define CORE_TX_BD_DATA_RESERVED0_MASK 0x3 768 #define CORE_TX_BD_DATA_RESERVED0_SHIFT 14 769 }; 770 771 struct core_tx_bd { 772 struct regpair addr; 773 __le16 nbytes; 774 __le16 nw_vlan_or_lb_echo; 775 struct core_tx_bd_data bd_data; 776 __le16 bitfield1; 777 #define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF 778 #define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0 779 #define CORE_TX_BD_TX_DST_MASK 0x3 780 #define CORE_TX_BD_TX_DST_SHIFT 14 781 }; 782 783 enum core_tx_dest { 784 CORE_TX_DEST_NW, 785 CORE_TX_DEST_LB, 786 CORE_TX_DEST_RESERVED, 787 CORE_TX_DEST_DROP, 788 MAX_CORE_TX_DEST 789 }; 790 791 struct core_tx_start_ramrod_data { 792 struct regpair pbl_base_addr; 793 __le16 mtu; 794 __le16 sb_id; 795 u8 sb_index; 796 u8 stats_en; 797 u8 stats_id; 798 u8 conn_type; 799 __le16 pbl_size; 800 __le16 qm_pq_id; 801 u8 gsi_offload_flag; 802 u8 resrved[3]; 803 }; 804 805 struct core_tx_stop_ramrod_data { 806 __le32 reserved0[2]; 807 }; 808 809 enum dcb_dscp_update_mode { 810 DONT_UPDATE_DCB_DSCP, 811 UPDATE_DCB, 812 UPDATE_DSCP, 813 UPDATE_DCB_DSCP, 814 MAX_DCB_DSCP_UPDATE_MODE 815 }; 816 817 struct eth_mstorm_per_pf_stat { 818 struct regpair gre_discard_pkts; 819 struct regpair vxlan_discard_pkts; 820 struct regpair geneve_discard_pkts; 821 struct regpair lb_discard_pkts; 822 }; 823 824 struct eth_mstorm_per_queue_stat { 825 struct regpair ttl0_discard; 826 struct regpair packet_too_big_discard; 827 struct regpair no_buff_discard; 828 struct regpair not_active_discard; 829 struct regpair tpa_coalesced_pkts; 830 struct regpair tpa_coalesced_events; 831 struct regpair tpa_aborts_num; 832 struct regpair tpa_coalesced_bytes; 833 }; 834 835 /* Ethernet TX Per PF */ 836 struct eth_pstorm_per_pf_stat { 837 struct regpair sent_lb_ucast_bytes; 838 struct regpair sent_lb_mcast_bytes; 839 struct regpair sent_lb_bcast_bytes; 840 struct regpair sent_lb_ucast_pkts; 841 struct regpair sent_lb_mcast_pkts; 842 struct regpair sent_lb_bcast_pkts; 843 struct regpair sent_gre_bytes; 844 struct regpair sent_vxlan_bytes; 845 struct regpair sent_geneve_bytes; 846 struct regpair sent_gre_pkts; 847 struct regpair sent_vxlan_pkts; 848 struct regpair sent_geneve_pkts; 849 struct regpair gre_drop_pkts; 850 struct regpair vxlan_drop_pkts; 851 struct regpair geneve_drop_pkts; 852 }; 853 854 /* Ethernet TX Per Queue Stats */ 855 struct eth_pstorm_per_queue_stat { 856 struct regpair sent_ucast_bytes; 857 struct regpair sent_mcast_bytes; 858 struct regpair sent_bcast_bytes; 859 struct regpair sent_ucast_pkts; 860 struct regpair sent_mcast_pkts; 861 struct regpair sent_bcast_pkts; 862 struct regpair error_drop_pkts; 863 }; 864 865 /* ETH Rx producers data */ 866 struct eth_rx_rate_limit { 867 __le16 mult; 868 __le16 cnst; 869 u8 add_sub_cnst; 870 u8 reserved0; 871 __le16 reserved1; 872 }; 873 874 struct eth_ustorm_per_pf_stat { 875 struct regpair rcv_lb_ucast_bytes; 876 struct regpair rcv_lb_mcast_bytes; 877 struct regpair rcv_lb_bcast_bytes; 878 struct regpair rcv_lb_ucast_pkts; 879 struct regpair rcv_lb_mcast_pkts; 880 struct regpair rcv_lb_bcast_pkts; 881 struct regpair rcv_gre_bytes; 882 struct regpair rcv_vxlan_bytes; 883 struct regpair rcv_geneve_bytes; 884 struct regpair rcv_gre_pkts; 885 struct regpair rcv_vxlan_pkts; 886 struct regpair rcv_geneve_pkts; 887 }; 888 889 struct eth_ustorm_per_queue_stat { 890 struct regpair rcv_ucast_bytes; 891 struct regpair rcv_mcast_bytes; 892 struct regpair rcv_bcast_bytes; 893 struct regpair rcv_ucast_pkts; 894 struct regpair rcv_mcast_pkts; 895 struct regpair rcv_bcast_pkts; 896 }; 897 898 /* Event Ring Next Page Address */ 899 struct event_ring_next_addr { 900 struct regpair addr; 901 __le32 reserved[2]; 902 }; 903 904 /* Event Ring Element */ 905 union event_ring_element { 906 struct event_ring_entry entry; 907 struct event_ring_next_addr next_addr; 908 }; 909 910 enum fw_flow_ctrl_mode { 911 flow_ctrl_pause, 912 flow_ctrl_pfc, 913 MAX_FW_FLOW_CTRL_MODE 914 }; 915 916 /* Major and Minor hsi Versions */ 917 struct hsi_fp_ver_struct { 918 u8 minor_ver_arr[2]; 919 u8 major_ver_arr[2]; 920 }; 921 922 enum iwarp_ll2_tx_queues { 923 IWARP_LL2_IN_ORDER_TX_QUEUE = 1, 924 IWARP_LL2_ALIGNED_TX_QUEUE, 925 IWARP_LL2_ALIGNED_RIGHT_TRIMMED_TX_QUEUE, 926 IWARP_LL2_ERROR, 927 MAX_IWARP_LL2_TX_QUEUES 928 }; 929 930 /* Mstorm non-triggering VF zone */ 931 enum malicious_vf_error_id { 932 MALICIOUS_VF_NO_ERROR, 933 VF_PF_CHANNEL_NOT_READY, 934 VF_ZONE_MSG_NOT_VALID, 935 VF_ZONE_FUNC_NOT_ENABLED, 936 ETH_PACKET_TOO_SMALL, 937 ETH_ILLEGAL_VLAN_MODE, 938 ETH_MTU_VIOLATION, 939 ETH_ILLEGAL_INBAND_TAGS, 940 ETH_VLAN_INSERT_AND_INBAND_VLAN, 941 ETH_ILLEGAL_NBDS, 942 ETH_FIRST_BD_WO_SOP, 943 ETH_INSUFFICIENT_BDS, 944 ETH_ILLEGAL_LSO_HDR_NBDS, 945 ETH_ILLEGAL_LSO_MSS, 946 ETH_ZERO_SIZE_BD, 947 ETH_ILLEGAL_LSO_HDR_LEN, 948 ETH_INSUFFICIENT_PAYLOAD, 949 ETH_EDPM_OUT_OF_SYNC, 950 ETH_TUNN_IPV6_EXT_NBD_ERR, 951 ETH_CONTROL_PACKET_VIOLATION, 952 ETH_ANTI_SPOOFING_ERR, 953 MAX_MALICIOUS_VF_ERROR_ID 954 }; 955 956 struct mstorm_non_trigger_vf_zone { 957 struct eth_mstorm_per_queue_stat eth_queue_stat; 958 struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD]; 959 }; 960 961 /* Mstorm VF zone */ 962 struct mstorm_vf_zone { 963 struct mstorm_non_trigger_vf_zone non_trigger; 964 965 }; 966 967 /* personality per PF */ 968 enum personality_type { 969 BAD_PERSONALITY_TYP, 970 PERSONALITY_ISCSI, 971 PERSONALITY_FCOE, 972 PERSONALITY_RDMA_AND_ETH, 973 PERSONALITY_RDMA, 974 PERSONALITY_CORE, 975 PERSONALITY_ETH, 976 PERSONALITY_RESERVED4, 977 MAX_PERSONALITY_TYPE 978 }; 979 980 /* tunnel configuration */ 981 struct pf_start_tunnel_config { 982 u8 set_vxlan_udp_port_flg; 983 u8 set_geneve_udp_port_flg; 984 u8 tunnel_clss_vxlan; 985 u8 tunnel_clss_l2geneve; 986 u8 tunnel_clss_ipgeneve; 987 u8 tunnel_clss_l2gre; 988 u8 tunnel_clss_ipgre; 989 u8 reserved; 990 __le16 vxlan_udp_port; 991 __le16 geneve_udp_port; 992 }; 993 994 /* Ramrod data for PF start ramrod */ 995 struct pf_start_ramrod_data { 996 struct regpair event_ring_pbl_addr; 997 struct regpair consolid_q_pbl_addr; 998 struct pf_start_tunnel_config tunnel_config; 999 __le32 reserved; 1000 __le16 event_ring_sb_id; 1001 u8 base_vf_id; 1002 u8 num_vfs; 1003 u8 event_ring_num_pages; 1004 u8 event_ring_sb_index; 1005 u8 path_id; 1006 u8 warning_as_error; 1007 u8 dont_log_ramrods; 1008 u8 personality; 1009 __le16 log_type_mask; 1010 u8 mf_mode; 1011 u8 integ_phase; 1012 u8 allow_npar_tx_switching; 1013 u8 inner_to_outer_pri_map[8]; 1014 u8 pri_map_valid; 1015 __le32 outer_tag; 1016 struct hsi_fp_ver_struct hsi_fp_ver; 1017 }; 1018 1019 struct protocol_dcb_data { 1020 u8 dcb_enable_flag; 1021 u8 reserved_a; 1022 u8 dcb_priority; 1023 u8 dcb_tc; 1024 u8 reserved_b; 1025 u8 reserved0; 1026 }; 1027 1028 struct pf_update_tunnel_config { 1029 u8 update_rx_pf_clss; 1030 u8 update_rx_def_ucast_clss; 1031 u8 update_rx_def_non_ucast_clss; 1032 u8 set_vxlan_udp_port_flg; 1033 u8 set_geneve_udp_port_flg; 1034 u8 tunnel_clss_vxlan; 1035 u8 tunnel_clss_l2geneve; 1036 u8 tunnel_clss_ipgeneve; 1037 u8 tunnel_clss_l2gre; 1038 u8 tunnel_clss_ipgre; 1039 __le16 vxlan_udp_port; 1040 __le16 geneve_udp_port; 1041 __le16 reserved; 1042 }; 1043 1044 struct pf_update_ramrod_data { 1045 u8 pf_id; 1046 u8 update_eth_dcb_data_mode; 1047 u8 update_fcoe_dcb_data_mode; 1048 u8 update_iscsi_dcb_data_mode; 1049 u8 update_roce_dcb_data_mode; 1050 u8 update_rroce_dcb_data_mode; 1051 u8 update_iwarp_dcb_data_mode; 1052 u8 update_mf_vlan_flag; 1053 struct protocol_dcb_data eth_dcb_data; 1054 struct protocol_dcb_data fcoe_dcb_data; 1055 struct protocol_dcb_data iscsi_dcb_data; 1056 struct protocol_dcb_data roce_dcb_data; 1057 struct protocol_dcb_data rroce_dcb_data; 1058 struct protocol_dcb_data iwarp_dcb_data; 1059 __le16 mf_vlan; 1060 __le16 reserved; 1061 struct pf_update_tunnel_config tunnel_config; 1062 }; 1063 1064 /* Ports mode */ 1065 enum ports_mode { 1066 ENGX2_PORTX1, 1067 ENGX2_PORTX2, 1068 ENGX1_PORTX1, 1069 ENGX1_PORTX2, 1070 ENGX1_PORTX4, 1071 MAX_PORTS_MODE 1072 }; 1073 1074 /* use to index in hsi_fp_[major|minor]_ver_arr per protocol */ 1075 enum protocol_version_array_key { 1076 ETH_VER_KEY = 0, 1077 ROCE_VER_KEY, 1078 MAX_PROTOCOL_VERSION_ARRAY_KEY 1079 }; 1080 1081 struct rdma_sent_stats { 1082 struct regpair sent_bytes; 1083 struct regpair sent_pkts; 1084 }; 1085 1086 struct pstorm_non_trigger_vf_zone { 1087 struct eth_pstorm_per_queue_stat eth_queue_stat; 1088 struct rdma_sent_stats rdma_stats; 1089 }; 1090 1091 /* Pstorm VF zone */ 1092 struct pstorm_vf_zone { 1093 struct pstorm_non_trigger_vf_zone non_trigger; 1094 struct regpair reserved[7]; 1095 }; 1096 1097 /* Ramrod Header of SPQE */ 1098 struct ramrod_header { 1099 __le32 cid; 1100 u8 cmd_id; 1101 u8 protocol_id; 1102 __le16 echo; 1103 }; 1104 1105 struct rdma_rcv_stats { 1106 struct regpair rcv_bytes; 1107 struct regpair rcv_pkts; 1108 }; 1109 1110 struct slow_path_element { 1111 struct ramrod_header hdr; 1112 struct regpair data_ptr; 1113 }; 1114 1115 /* Tstorm non-triggering VF zone */ 1116 struct tstorm_non_trigger_vf_zone { 1117 struct rdma_rcv_stats rdma_stats; 1118 }; 1119 1120 struct tstorm_per_port_stat { 1121 struct regpair trunc_error_discard; 1122 struct regpair mac_error_discard; 1123 struct regpair mftag_filter_discard; 1124 struct regpair eth_mac_filter_discard; 1125 struct regpair ll2_mac_filter_discard; 1126 struct regpair ll2_conn_disabled_discard; 1127 struct regpair iscsi_irregular_pkt; 1128 struct regpair fcoe_irregular_pkt; 1129 struct regpair roce_irregular_pkt; 1130 struct regpair iwarp_irregular_pkt; 1131 struct regpair eth_irregular_pkt; 1132 struct regpair reserved1; 1133 struct regpair preroce_irregular_pkt; 1134 struct regpair eth_gre_tunn_filter_discard; 1135 struct regpair eth_vxlan_tunn_filter_discard; 1136 struct regpair eth_geneve_tunn_filter_discard; 1137 }; 1138 1139 /* Tstorm VF zone */ 1140 struct tstorm_vf_zone { 1141 struct tstorm_non_trigger_vf_zone non_trigger; 1142 }; 1143 1144 /* Tunnel classification scheme */ 1145 enum tunnel_clss { 1146 TUNNEL_CLSS_MAC_VLAN = 0, 1147 TUNNEL_CLSS_MAC_VNI, 1148 TUNNEL_CLSS_INNER_MAC_VLAN, 1149 TUNNEL_CLSS_INNER_MAC_VNI, 1150 TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE, 1151 MAX_TUNNEL_CLSS 1152 }; 1153 1154 /* Ustorm non-triggering VF zone */ 1155 struct ustorm_non_trigger_vf_zone { 1156 struct eth_ustorm_per_queue_stat eth_queue_stat; 1157 struct regpair vf_pf_msg_addr; 1158 }; 1159 1160 /* Ustorm triggering VF zone */ 1161 struct ustorm_trigger_vf_zone { 1162 u8 vf_pf_msg_valid; 1163 u8 reserved[7]; 1164 }; 1165 1166 /* Ustorm VF zone */ 1167 struct ustorm_vf_zone { 1168 struct ustorm_non_trigger_vf_zone non_trigger; 1169 struct ustorm_trigger_vf_zone trigger; 1170 }; 1171 1172 /* VF-PF channel data */ 1173 struct vf_pf_channel_data { 1174 __le32 ready; 1175 u8 valid; 1176 u8 reserved0; 1177 __le16 reserved1; 1178 }; 1179 1180 /* Ramrod data for VF start ramrod */ 1181 struct vf_start_ramrod_data { 1182 u8 vf_id; 1183 u8 enable_flr_ack; 1184 __le16 opaque_fid; 1185 u8 personality; 1186 u8 reserved[7]; 1187 struct hsi_fp_ver_struct hsi_fp_ver; 1188 1189 }; 1190 1191 /* Ramrod data for VF start ramrod */ 1192 struct vf_stop_ramrod_data { 1193 u8 vf_id; 1194 u8 reserved0; 1195 __le16 reserved1; 1196 __le32 reserved2; 1197 }; 1198 1199 enum vf_zone_size_mode { 1200 VF_ZONE_SIZE_MODE_DEFAULT, 1201 VF_ZONE_SIZE_MODE_DOUBLE, 1202 VF_ZONE_SIZE_MODE_QUAD, 1203 MAX_VF_ZONE_SIZE_MODE 1204 }; 1205 1206 struct atten_status_block { 1207 __le32 atten_bits; 1208 __le32 atten_ack; 1209 __le16 reserved0; 1210 __le16 sb_index; 1211 __le32 reserved1; 1212 }; 1213 1214 enum command_type_bit { 1215 IGU_COMMAND_TYPE_NOP = 0, 1216 IGU_COMMAND_TYPE_SET = 1, 1217 MAX_COMMAND_TYPE_BIT 1218 }; 1219 1220 /* DMAE command */ 1221 struct dmae_cmd { 1222 __le32 opcode; 1223 #define DMAE_CMD_SRC_MASK 0x1 1224 #define DMAE_CMD_SRC_SHIFT 0 1225 #define DMAE_CMD_DST_MASK 0x3 1226 #define DMAE_CMD_DST_SHIFT 1 1227 #define DMAE_CMD_C_DST_MASK 0x1 1228 #define DMAE_CMD_C_DST_SHIFT 3 1229 #define DMAE_CMD_CRC_RESET_MASK 0x1 1230 #define DMAE_CMD_CRC_RESET_SHIFT 4 1231 #define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1 1232 #define DMAE_CMD_SRC_ADDR_RESET_SHIFT 5 1233 #define DMAE_CMD_DST_ADDR_RESET_MASK 0x1 1234 #define DMAE_CMD_DST_ADDR_RESET_SHIFT 6 1235 #define DMAE_CMD_COMP_FUNC_MASK 0x1 1236 #define DMAE_CMD_COMP_FUNC_SHIFT 7 1237 #define DMAE_CMD_COMP_WORD_EN_MASK 0x1 1238 #define DMAE_CMD_COMP_WORD_EN_SHIFT 8 1239 #define DMAE_CMD_COMP_CRC_EN_MASK 0x1 1240 #define DMAE_CMD_COMP_CRC_EN_SHIFT 9 1241 #define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7 1242 #define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10 1243 #define DMAE_CMD_RESERVED1_MASK 0x1 1244 #define DMAE_CMD_RESERVED1_SHIFT 13 1245 #define DMAE_CMD_ENDIANITY_MODE_MASK 0x3 1246 #define DMAE_CMD_ENDIANITY_MODE_SHIFT 14 1247 #define DMAE_CMD_ERR_HANDLING_MASK 0x3 1248 #define DMAE_CMD_ERR_HANDLING_SHIFT 16 1249 #define DMAE_CMD_PORT_ID_MASK 0x3 1250 #define DMAE_CMD_PORT_ID_SHIFT 18 1251 #define DMAE_CMD_SRC_PF_ID_MASK 0xF 1252 #define DMAE_CMD_SRC_PF_ID_SHIFT 20 1253 #define DMAE_CMD_DST_PF_ID_MASK 0xF 1254 #define DMAE_CMD_DST_PF_ID_SHIFT 24 1255 #define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1 1256 #define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28 1257 #define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1 1258 #define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29 1259 #define DMAE_CMD_RESERVED2_MASK 0x3 1260 #define DMAE_CMD_RESERVED2_SHIFT 30 1261 __le32 src_addr_lo; 1262 __le32 src_addr_hi; 1263 __le32 dst_addr_lo; 1264 __le32 dst_addr_hi; 1265 __le16 length_dw; 1266 __le16 opcode_b; 1267 #define DMAE_CMD_SRC_VF_ID_MASK 0xFF 1268 #define DMAE_CMD_SRC_VF_ID_SHIFT 0 1269 #define DMAE_CMD_DST_VF_ID_MASK 0xFF 1270 #define DMAE_CMD_DST_VF_ID_SHIFT 8 1271 __le32 comp_addr_lo; 1272 __le32 comp_addr_hi; 1273 __le32 comp_val; 1274 __le32 crc32; 1275 __le32 crc_32_c; 1276 __le16 crc16; 1277 __le16 crc16_c; 1278 __le16 crc10; 1279 __le16 reserved; 1280 __le16 xsum16; 1281 __le16 xsum8; 1282 }; 1283 1284 enum dmae_cmd_comp_crc_en_enum { 1285 dmae_cmd_comp_crc_disabled, 1286 dmae_cmd_comp_crc_enabled, 1287 MAX_DMAE_CMD_COMP_CRC_EN_ENUM 1288 }; 1289 1290 enum dmae_cmd_comp_func_enum { 1291 dmae_cmd_comp_func_to_src, 1292 dmae_cmd_comp_func_to_dst, 1293 MAX_DMAE_CMD_COMP_FUNC_ENUM 1294 }; 1295 1296 enum dmae_cmd_comp_word_en_enum { 1297 dmae_cmd_comp_word_disabled, 1298 dmae_cmd_comp_word_enabled, 1299 MAX_DMAE_CMD_COMP_WORD_EN_ENUM 1300 }; 1301 1302 enum dmae_cmd_c_dst_enum { 1303 dmae_cmd_c_dst_pcie, 1304 dmae_cmd_c_dst_grc, 1305 MAX_DMAE_CMD_C_DST_ENUM 1306 }; 1307 1308 enum dmae_cmd_dst_enum { 1309 dmae_cmd_dst_none_0, 1310 dmae_cmd_dst_pcie, 1311 dmae_cmd_dst_grc, 1312 dmae_cmd_dst_none_3, 1313 MAX_DMAE_CMD_DST_ENUM 1314 }; 1315 1316 enum dmae_cmd_error_handling_enum { 1317 dmae_cmd_error_handling_send_regular_comp, 1318 dmae_cmd_error_handling_send_comp_with_err, 1319 dmae_cmd_error_handling_dont_send_comp, 1320 MAX_DMAE_CMD_ERROR_HANDLING_ENUM 1321 }; 1322 1323 enum dmae_cmd_src_enum { 1324 dmae_cmd_src_pcie, 1325 dmae_cmd_src_grc, 1326 MAX_DMAE_CMD_SRC_ENUM 1327 }; 1328 1329 struct mstorm_core_conn_ag_ctx { 1330 u8 byte0; 1331 u8 byte1; 1332 u8 flags0; 1333 #define MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 1334 #define MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 1335 #define MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 1336 #define MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 1337 #define MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 1338 #define MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 1339 #define MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 1340 #define MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 1341 #define MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 1342 #define MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 1343 u8 flags1; 1344 #define MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 1345 #define MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 1346 #define MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 1347 #define MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 1348 #define MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 1349 #define MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 1350 #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 1351 #define MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3 1352 #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 1353 #define MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4 1354 #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 1355 #define MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5 1356 #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 1357 #define MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6 1358 #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 1359 #define MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7 1360 __le16 word0; 1361 __le16 word1; 1362 __le32 reg0; 1363 __le32 reg1; 1364 }; 1365 1366 struct ystorm_core_conn_ag_ctx { 1367 u8 byte0; 1368 u8 byte1; 1369 u8 flags0; 1370 #define YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 1371 #define YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 1372 #define YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 1373 #define YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 1374 #define YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 1375 #define YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 1376 #define YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 1377 #define YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 1378 #define YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 1379 #define YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 1380 u8 flags1; 1381 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 1382 #define YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 1383 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 1384 #define YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 1385 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 1386 #define YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 1387 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 1388 #define YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3 1389 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 1390 #define YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4 1391 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 1392 #define YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5 1393 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 1394 #define YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6 1395 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 1396 #define YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7 1397 u8 byte2; 1398 u8 byte3; 1399 __le16 word0; 1400 __le32 reg0; 1401 __le32 reg1; 1402 __le16 word1; 1403 __le16 word2; 1404 __le16 word3; 1405 __le16 word4; 1406 __le32 reg2; 1407 __le32 reg3; 1408 }; 1409 1410 /* IGU cleanup command */ 1411 struct igu_cleanup { 1412 __le32 sb_id_and_flags; 1413 #define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF 1414 #define IGU_CLEANUP_RESERVED0_SHIFT 0 1415 #define IGU_CLEANUP_CLEANUP_SET_MASK 0x1 1416 #define IGU_CLEANUP_CLEANUP_SET_SHIFT 27 1417 #define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7 1418 #define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28 1419 #define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1 1420 #define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31 1421 __le32 reserved1; 1422 }; 1423 1424 /* IGU firmware driver command */ 1425 union igu_command { 1426 struct igu_prod_cons_update prod_cons_update; 1427 struct igu_cleanup cleanup; 1428 }; 1429 1430 /* IGU firmware driver command */ 1431 struct igu_command_reg_ctrl { 1432 __le16 opaque_fid; 1433 __le16 igu_command_reg_ctrl_fields; 1434 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF 1435 #define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0 1436 #define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7 1437 #define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT 12 1438 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1 1439 #define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15 1440 }; 1441 1442 /* IGU mapping line structure */ 1443 struct igu_mapping_line { 1444 __le32 igu_mapping_line_fields; 1445 #define IGU_MAPPING_LINE_VALID_MASK 0x1 1446 #define IGU_MAPPING_LINE_VALID_SHIFT 0 1447 #define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF 1448 #define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT 1 1449 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF 1450 #define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9 1451 #define IGU_MAPPING_LINE_PF_VALID_MASK 0x1 1452 #define IGU_MAPPING_LINE_PF_VALID_SHIFT 17 1453 #define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F 1454 #define IGU_MAPPING_LINE_IPS_GROUP_SHIFT 18 1455 #define IGU_MAPPING_LINE_RESERVED_MASK 0xFF 1456 #define IGU_MAPPING_LINE_RESERVED_SHIFT 24 1457 }; 1458 1459 /* IGU MSIX line structure */ 1460 struct igu_msix_vector { 1461 struct regpair address; 1462 __le32 data; 1463 __le32 msix_vector_fields; 1464 #define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1 1465 #define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0 1466 #define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF 1467 #define IGU_MSIX_VECTOR_RESERVED0_SHIFT 1 1468 #define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF 1469 #define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16 1470 #define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF 1471 #define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24 1472 }; 1473 /* per encapsulation type enabling flags */ 1474 struct prs_reg_encapsulation_type_en { 1475 u8 flags; 1476 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1 1477 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0 1478 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1 1479 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT 1 1480 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1 1481 #define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT 2 1482 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1 1483 #define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT 3 1484 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1 1485 #define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4 1486 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1 1487 #define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT 5 1488 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3 1489 #define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT 6 1490 }; 1491 1492 enum pxp_tph_st_hint { 1493 TPH_ST_HINT_BIDIR, 1494 TPH_ST_HINT_REQUESTER, 1495 TPH_ST_HINT_TARGET, 1496 TPH_ST_HINT_TARGET_PRIO, 1497 MAX_PXP_TPH_ST_HINT 1498 }; 1499 1500 /* QM hardware structure of enable bypass credit mask */ 1501 struct qm_rf_bypass_mask { 1502 u8 flags; 1503 #define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1 1504 #define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0 1505 #define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1 1506 #define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1 1507 #define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1 1508 #define QM_RF_BYPASS_MASK_PFWFQ_SHIFT 2 1509 #define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1 1510 #define QM_RF_BYPASS_MASK_VPWFQ_SHIFT 3 1511 #define QM_RF_BYPASS_MASK_PFRL_MASK 0x1 1512 #define QM_RF_BYPASS_MASK_PFRL_SHIFT 4 1513 #define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1 1514 #define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT 5 1515 #define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1 1516 #define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT 6 1517 #define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1 1518 #define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7 1519 }; 1520 1521 /* QM hardware structure of opportunistic credit mask */ 1522 struct qm_rf_opportunistic_mask { 1523 __le16 flags; 1524 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1 1525 #define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0 1526 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1 1527 #define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT 1 1528 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1 1529 #define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT 2 1530 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1 1531 #define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT 3 1532 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1 1533 #define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT 4 1534 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1 1535 #define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT 5 1536 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1 1537 #define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT 6 1538 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1 1539 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT 7 1540 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1 1541 #define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8 1542 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F 1543 #define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT 9 1544 }; 1545 1546 /* QM hardware structure of QM map memory */ 1547 struct qm_rf_pq_map { 1548 __le32 reg; 1549 #define QM_RF_PQ_MAP_PQ_VALID_MASK 0x1 1550 #define QM_RF_PQ_MAP_PQ_VALID_SHIFT 0 1551 #define QM_RF_PQ_MAP_RL_ID_MASK 0xFF 1552 #define QM_RF_PQ_MAP_RL_ID_SHIFT 1 1553 #define QM_RF_PQ_MAP_VP_PQ_ID_MASK 0x1FF 1554 #define QM_RF_PQ_MAP_VP_PQ_ID_SHIFT 9 1555 #define QM_RF_PQ_MAP_VOQ_MASK 0x1F 1556 #define QM_RF_PQ_MAP_VOQ_SHIFT 18 1557 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_MASK 0x3 1558 #define QM_RF_PQ_MAP_WRR_WEIGHT_GROUP_SHIFT 23 1559 #define QM_RF_PQ_MAP_RL_VALID_MASK 0x1 1560 #define QM_RF_PQ_MAP_RL_VALID_SHIFT 25 1561 #define QM_RF_PQ_MAP_RESERVED_MASK 0x3F 1562 #define QM_RF_PQ_MAP_RESERVED_SHIFT 26 1563 }; 1564 1565 /* Completion params for aggregated interrupt completion */ 1566 struct sdm_agg_int_comp_params { 1567 __le16 params; 1568 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F 1569 #define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0 1570 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1 1571 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6 1572 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF 1573 #define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT 7 1574 }; 1575 1576 /* SDM operation gen command (generate aggregative interrupt) */ 1577 struct sdm_op_gen { 1578 __le32 command; 1579 #define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF 1580 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0 1581 #define SDM_OP_GEN_COMP_TYPE_MASK 0xF 1582 #define SDM_OP_GEN_COMP_TYPE_SHIFT 16 1583 #define SDM_OP_GEN_RESERVED_MASK 0xFFF 1584 #define SDM_OP_GEN_RESERVED_SHIFT 20 1585 }; 1586 1587 /****************************************/ 1588 /* Debug Tools HSI constants and macros */ 1589 /****************************************/ 1590 1591 enum block_addr { 1592 GRCBASE_GRC = 0x50000, 1593 GRCBASE_MISCS = 0x9000, 1594 GRCBASE_MISC = 0x8000, 1595 GRCBASE_DBU = 0xa000, 1596 GRCBASE_PGLUE_B = 0x2a8000, 1597 GRCBASE_CNIG = 0x218000, 1598 GRCBASE_CPMU = 0x30000, 1599 GRCBASE_NCSI = 0x40000, 1600 GRCBASE_OPTE = 0x53000, 1601 GRCBASE_BMB = 0x540000, 1602 GRCBASE_PCIE = 0x54000, 1603 GRCBASE_MCP = 0xe00000, 1604 GRCBASE_MCP2 = 0x52000, 1605 GRCBASE_PSWHST = 0x2a0000, 1606 GRCBASE_PSWHST2 = 0x29e000, 1607 GRCBASE_PSWRD = 0x29c000, 1608 GRCBASE_PSWRD2 = 0x29d000, 1609 GRCBASE_PSWWR = 0x29a000, 1610 GRCBASE_PSWWR2 = 0x29b000, 1611 GRCBASE_PSWRQ = 0x280000, 1612 GRCBASE_PSWRQ2 = 0x240000, 1613 GRCBASE_PGLCS = 0x0, 1614 GRCBASE_DMAE = 0xc000, 1615 GRCBASE_PTU = 0x560000, 1616 GRCBASE_TCM = 0x1180000, 1617 GRCBASE_MCM = 0x1200000, 1618 GRCBASE_UCM = 0x1280000, 1619 GRCBASE_XCM = 0x1000000, 1620 GRCBASE_YCM = 0x1080000, 1621 GRCBASE_PCM = 0x1100000, 1622 GRCBASE_QM = 0x2f0000, 1623 GRCBASE_TM = 0x2c0000, 1624 GRCBASE_DORQ = 0x100000, 1625 GRCBASE_BRB = 0x340000, 1626 GRCBASE_SRC = 0x238000, 1627 GRCBASE_PRS = 0x1f0000, 1628 GRCBASE_TSDM = 0xfb0000, 1629 GRCBASE_MSDM = 0xfc0000, 1630 GRCBASE_USDM = 0xfd0000, 1631 GRCBASE_XSDM = 0xf80000, 1632 GRCBASE_YSDM = 0xf90000, 1633 GRCBASE_PSDM = 0xfa0000, 1634 GRCBASE_TSEM = 0x1700000, 1635 GRCBASE_MSEM = 0x1800000, 1636 GRCBASE_USEM = 0x1900000, 1637 GRCBASE_XSEM = 0x1400000, 1638 GRCBASE_YSEM = 0x1500000, 1639 GRCBASE_PSEM = 0x1600000, 1640 GRCBASE_RSS = 0x238800, 1641 GRCBASE_TMLD = 0x4d0000, 1642 GRCBASE_MULD = 0x4e0000, 1643 GRCBASE_YULD = 0x4c8000, 1644 GRCBASE_XYLD = 0x4c0000, 1645 GRCBASE_PTLD = 0x590000, 1646 GRCBASE_YPLD = 0x5b0000, 1647 GRCBASE_PRM = 0x230000, 1648 GRCBASE_PBF_PB1 = 0xda0000, 1649 GRCBASE_PBF_PB2 = 0xda4000, 1650 GRCBASE_RPB = 0x23c000, 1651 GRCBASE_BTB = 0xdb0000, 1652 GRCBASE_PBF = 0xd80000, 1653 GRCBASE_RDIF = 0x300000, 1654 GRCBASE_TDIF = 0x310000, 1655 GRCBASE_CDU = 0x580000, 1656 GRCBASE_CCFC = 0x2e0000, 1657 GRCBASE_TCFC = 0x2d0000, 1658 GRCBASE_IGU = 0x180000, 1659 GRCBASE_CAU = 0x1c0000, 1660 GRCBASE_RGFS = 0xf00000, 1661 GRCBASE_RGSRC = 0x320000, 1662 GRCBASE_TGFS = 0xd00000, 1663 GRCBASE_TGSRC = 0x322000, 1664 GRCBASE_UMAC = 0x51000, 1665 GRCBASE_XMAC = 0x210000, 1666 GRCBASE_DBG = 0x10000, 1667 GRCBASE_NIG = 0x500000, 1668 GRCBASE_WOL = 0x600000, 1669 GRCBASE_BMBN = 0x610000, 1670 GRCBASE_IPC = 0x20000, 1671 GRCBASE_NWM = 0x800000, 1672 GRCBASE_NWS = 0x700000, 1673 GRCBASE_MS = 0x6a0000, 1674 GRCBASE_PHY_PCIE = 0x620000, 1675 GRCBASE_LED = 0x6b8000, 1676 GRCBASE_AVS_WRAP = 0x6b0000, 1677 GRCBASE_MISC_AEU = 0x8000, 1678 GRCBASE_BAR0_MAP = 0x1c00000, 1679 MAX_BLOCK_ADDR 1680 }; 1681 1682 enum block_id { 1683 BLOCK_GRC, 1684 BLOCK_MISCS, 1685 BLOCK_MISC, 1686 BLOCK_DBU, 1687 BLOCK_PGLUE_B, 1688 BLOCK_CNIG, 1689 BLOCK_CPMU, 1690 BLOCK_NCSI, 1691 BLOCK_OPTE, 1692 BLOCK_BMB, 1693 BLOCK_PCIE, 1694 BLOCK_MCP, 1695 BLOCK_MCP2, 1696 BLOCK_PSWHST, 1697 BLOCK_PSWHST2, 1698 BLOCK_PSWRD, 1699 BLOCK_PSWRD2, 1700 BLOCK_PSWWR, 1701 BLOCK_PSWWR2, 1702 BLOCK_PSWRQ, 1703 BLOCK_PSWRQ2, 1704 BLOCK_PGLCS, 1705 BLOCK_DMAE, 1706 BLOCK_PTU, 1707 BLOCK_TCM, 1708 BLOCK_MCM, 1709 BLOCK_UCM, 1710 BLOCK_XCM, 1711 BLOCK_YCM, 1712 BLOCK_PCM, 1713 BLOCK_QM, 1714 BLOCK_TM, 1715 BLOCK_DORQ, 1716 BLOCK_BRB, 1717 BLOCK_SRC, 1718 BLOCK_PRS, 1719 BLOCK_TSDM, 1720 BLOCK_MSDM, 1721 BLOCK_USDM, 1722 BLOCK_XSDM, 1723 BLOCK_YSDM, 1724 BLOCK_PSDM, 1725 BLOCK_TSEM, 1726 BLOCK_MSEM, 1727 BLOCK_USEM, 1728 BLOCK_XSEM, 1729 BLOCK_YSEM, 1730 BLOCK_PSEM, 1731 BLOCK_RSS, 1732 BLOCK_TMLD, 1733 BLOCK_MULD, 1734 BLOCK_YULD, 1735 BLOCK_XYLD, 1736 BLOCK_PTLD, 1737 BLOCK_YPLD, 1738 BLOCK_PRM, 1739 BLOCK_PBF_PB1, 1740 BLOCK_PBF_PB2, 1741 BLOCK_RPB, 1742 BLOCK_BTB, 1743 BLOCK_PBF, 1744 BLOCK_RDIF, 1745 BLOCK_TDIF, 1746 BLOCK_CDU, 1747 BLOCK_CCFC, 1748 BLOCK_TCFC, 1749 BLOCK_IGU, 1750 BLOCK_CAU, 1751 BLOCK_RGFS, 1752 BLOCK_RGSRC, 1753 BLOCK_TGFS, 1754 BLOCK_TGSRC, 1755 BLOCK_UMAC, 1756 BLOCK_XMAC, 1757 BLOCK_DBG, 1758 BLOCK_NIG, 1759 BLOCK_WOL, 1760 BLOCK_BMBN, 1761 BLOCK_IPC, 1762 BLOCK_NWM, 1763 BLOCK_NWS, 1764 BLOCK_MS, 1765 BLOCK_PHY_PCIE, 1766 BLOCK_LED, 1767 BLOCK_AVS_WRAP, 1768 BLOCK_MISC_AEU, 1769 BLOCK_BAR0_MAP, 1770 MAX_BLOCK_ID 1771 }; 1772 1773 /* binary debug buffer types */ 1774 enum bin_dbg_buffer_type { 1775 BIN_BUF_DBG_MODE_TREE, 1776 BIN_BUF_DBG_DUMP_REG, 1777 BIN_BUF_DBG_DUMP_MEM, 1778 BIN_BUF_DBG_IDLE_CHK_REGS, 1779 BIN_BUF_DBG_IDLE_CHK_IMMS, 1780 BIN_BUF_DBG_IDLE_CHK_RULES, 1781 BIN_BUF_DBG_IDLE_CHK_PARSING_DATA, 1782 BIN_BUF_DBG_ATTN_BLOCKS, 1783 BIN_BUF_DBG_ATTN_REGS, 1784 BIN_BUF_DBG_ATTN_INDEXES, 1785 BIN_BUF_DBG_ATTN_NAME_OFFSETS, 1786 BIN_BUF_DBG_BUS_BLOCKS, 1787 BIN_BUF_DBG_BUS_LINES, 1788 BIN_BUF_DBG_BUS_BLOCKS_USER_DATA, 1789 BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS, 1790 BIN_BUF_DBG_PARSING_STRINGS, 1791 MAX_BIN_DBG_BUFFER_TYPE 1792 }; 1793 1794 1795 /* Attention bit mapping */ 1796 struct dbg_attn_bit_mapping { 1797 __le16 data; 1798 #define DBG_ATTN_BIT_MAPPING_VAL_MASK 0x7FFF 1799 #define DBG_ATTN_BIT_MAPPING_VAL_SHIFT 0 1800 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK 0x1 1801 #define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT 15 1802 }; 1803 1804 /* Attention block per-type data */ 1805 struct dbg_attn_block_type_data { 1806 __le16 names_offset; 1807 __le16 reserved1; 1808 u8 num_regs; 1809 u8 reserved2; 1810 __le16 regs_offset; 1811 }; 1812 1813 /* Block attentions */ 1814 struct dbg_attn_block { 1815 struct dbg_attn_block_type_data per_type_data[2]; 1816 }; 1817 1818 /* Attention register result */ 1819 struct dbg_attn_reg_result { 1820 __le32 data; 1821 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK 0xFFFFFF 1822 #define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT 0 1823 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK 0xFF 1824 #define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_SHIFT 24 1825 __le16 block_attn_offset; 1826 __le16 reserved; 1827 __le32 sts_val; 1828 __le32 mask_val; 1829 }; 1830 1831 /* Attention block result */ 1832 struct dbg_attn_block_result { 1833 u8 block_id; 1834 u8 data; 1835 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK 0x3 1836 #define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT 0 1837 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK 0x3F 1838 #define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT 2 1839 __le16 names_offset; 1840 struct dbg_attn_reg_result reg_results[15]; 1841 }; 1842 1843 /* mode header */ 1844 struct dbg_mode_hdr { 1845 __le16 data; 1846 #define DBG_MODE_HDR_EVAL_MODE_MASK 0x1 1847 #define DBG_MODE_HDR_EVAL_MODE_SHIFT 0 1848 #define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK 0x7FFF 1849 #define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT 1 1850 }; 1851 1852 /* Attention register */ 1853 struct dbg_attn_reg { 1854 struct dbg_mode_hdr mode; 1855 __le16 block_attn_offset; 1856 __le32 data; 1857 #define DBG_ATTN_REG_STS_ADDRESS_MASK 0xFFFFFF 1858 #define DBG_ATTN_REG_STS_ADDRESS_SHIFT 0 1859 #define DBG_ATTN_REG_NUM_REG_ATTN_MASK 0xFF 1860 #define DBG_ATTN_REG_NUM_REG_ATTN_SHIFT 24 1861 __le32 sts_clr_address; 1862 __le32 mask_address; 1863 }; 1864 1865 /* attention types */ 1866 enum dbg_attn_type { 1867 ATTN_TYPE_INTERRUPT, 1868 ATTN_TYPE_PARITY, 1869 MAX_DBG_ATTN_TYPE 1870 }; 1871 1872 struct dbg_bus_block { 1873 u8 num_of_lines; 1874 u8 has_latency_events; 1875 __le16 lines_offset; 1876 }; 1877 1878 struct dbg_bus_block_user_data { 1879 u8 num_of_lines; 1880 u8 has_latency_events; 1881 __le16 names_offset; 1882 }; 1883 1884 struct dbg_bus_line { 1885 u8 data; 1886 #define DBG_BUS_LINE_NUM_OF_GROUPS_MASK 0xF 1887 #define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT 0 1888 #define DBG_BUS_LINE_IS_256B_MASK 0x1 1889 #define DBG_BUS_LINE_IS_256B_SHIFT 4 1890 #define DBG_BUS_LINE_RESERVED_MASK 0x7 1891 #define DBG_BUS_LINE_RESERVED_SHIFT 5 1892 u8 group_sizes; 1893 }; 1894 1895 /* condition header for registers dump */ 1896 struct dbg_dump_cond_hdr { 1897 struct dbg_mode_hdr mode; /* Mode header */ 1898 u8 block_id; /* block ID */ 1899 u8 data_size; /* size in dwords of the data following this header */ 1900 }; 1901 1902 /* memory data for registers dump */ 1903 struct dbg_dump_mem { 1904 __le32 dword0; 1905 #define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF 1906 #define DBG_DUMP_MEM_ADDRESS_SHIFT 0 1907 #define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF 1908 #define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24 1909 __le32 dword1; 1910 #define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF 1911 #define DBG_DUMP_MEM_LENGTH_SHIFT 0 1912 #define DBG_DUMP_MEM_WIDE_BUS_MASK 0x1 1913 #define DBG_DUMP_MEM_WIDE_BUS_SHIFT 24 1914 #define DBG_DUMP_MEM_RESERVED_MASK 0x7F 1915 #define DBG_DUMP_MEM_RESERVED_SHIFT 25 1916 }; 1917 1918 /* register data for registers dump */ 1919 struct dbg_dump_reg { 1920 __le32 data; 1921 #define DBG_DUMP_REG_ADDRESS_MASK 0x7FFFFF /* register address (in dwords) */ 1922 #define DBG_DUMP_REG_ADDRESS_SHIFT 0 1923 #define DBG_DUMP_REG_WIDE_BUS_MASK 0x1 /* indicates register is wide-bus */ 1924 #define DBG_DUMP_REG_WIDE_BUS_SHIFT 23 1925 #define DBG_DUMP_REG_LENGTH_MASK 0xFF /* register size (in dwords) */ 1926 #define DBG_DUMP_REG_LENGTH_SHIFT 24 1927 }; 1928 1929 /* split header for registers dump */ 1930 struct dbg_dump_split_hdr { 1931 __le32 hdr; 1932 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF 1933 #define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0 1934 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF 1935 #define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24 1936 }; 1937 1938 /* condition header for idle check */ 1939 struct dbg_idle_chk_cond_hdr { 1940 struct dbg_mode_hdr mode; /* Mode header */ 1941 __le16 data_size; /* size in dwords of the data following this header */ 1942 }; 1943 1944 /* Idle Check condition register */ 1945 struct dbg_idle_chk_cond_reg { 1946 __le32 data; 1947 #define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0x7FFFFF 1948 #define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0 1949 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK 0x1 1950 #define DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT 23 1951 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF 1952 #define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24 1953 __le16 num_entries; 1954 u8 entry_size; 1955 u8 start_entry; 1956 }; 1957 1958 /* Idle Check info register */ 1959 struct dbg_idle_chk_info_reg { 1960 __le32 data; 1961 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0x7FFFFF 1962 #define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0 1963 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK 0x1 1964 #define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT 23 1965 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF 1966 #define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24 1967 __le16 size; /* register size in dwords */ 1968 struct dbg_mode_hdr mode; /* Mode header */ 1969 }; 1970 1971 /* Idle Check register */ 1972 union dbg_idle_chk_reg { 1973 struct dbg_idle_chk_cond_reg cond_reg; /* condition register */ 1974 struct dbg_idle_chk_info_reg info_reg; /* info register */ 1975 }; 1976 1977 /* Idle Check result header */ 1978 struct dbg_idle_chk_result_hdr { 1979 __le16 rule_id; /* Failing rule index */ 1980 __le16 mem_entry_id; /* Failing memory entry index */ 1981 u8 num_dumped_cond_regs; /* number of dumped condition registers */ 1982 u8 num_dumped_info_regs; /* number of dumped condition registers */ 1983 u8 severity; /* from dbg_idle_chk_severity_types enum */ 1984 u8 reserved; 1985 }; 1986 1987 /* Idle Check result register header */ 1988 struct dbg_idle_chk_result_reg_hdr { 1989 u8 data; 1990 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK 0x1 1991 #define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0 1992 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK 0x7F 1993 #define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1 1994 u8 start_entry; /* index of the first checked entry */ 1995 __le16 size; /* register size in dwords */ 1996 }; 1997 1998 /* Idle Check rule */ 1999 struct dbg_idle_chk_rule { 2000 __le16 rule_id; /* Idle Check rule ID */ 2001 u8 severity; /* value from dbg_idle_chk_severity_types enum */ 2002 u8 cond_id; /* Condition ID */ 2003 u8 num_cond_regs; /* number of condition registers */ 2004 u8 num_info_regs; /* number of info registers */ 2005 u8 num_imms; /* number of immediates in the condition */ 2006 u8 reserved1; 2007 __le16 reg_offset; /* offset of this rules registers in the idle check 2008 * register array (in dbg_idle_chk_reg units). 2009 */ 2010 __le16 imm_offset; /* offset of this rules immediate values in the 2011 * immediate values array (in dwords). 2012 */ 2013 }; 2014 2015 /* Idle Check rule parsing data */ 2016 struct dbg_idle_chk_rule_parsing_data { 2017 __le32 data; 2018 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1 2019 #define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0 2020 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF 2021 #define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1 2022 }; 2023 2024 /* idle check severity types */ 2025 enum dbg_idle_chk_severity_types { 2026 /* idle check failure should cause an error */ 2027 IDLE_CHK_SEVERITY_ERROR, 2028 /* idle check failure should cause an error only if theres no traffic */ 2029 IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC, 2030 /* idle check failure should cause a warning */ 2031 IDLE_CHK_SEVERITY_WARNING, 2032 MAX_DBG_IDLE_CHK_SEVERITY_TYPES 2033 }; 2034 2035 /* Debug Bus block data */ 2036 struct dbg_bus_block_data { 2037 __le16 data; 2038 #define DBG_BUS_BLOCK_DATA_ENABLE_MASK_MASK 0xF 2039 #define DBG_BUS_BLOCK_DATA_ENABLE_MASK_SHIFT 0 2040 #define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_MASK 0xF 2041 #define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_SHIFT 4 2042 #define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_MASK 0xF 2043 #define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_SHIFT 8 2044 #define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_MASK 0xF 2045 #define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_SHIFT 12 2046 u8 line_num; 2047 u8 hw_id; 2048 }; 2049 2050 /* Debug Bus Clients */ 2051 enum dbg_bus_clients { 2052 DBG_BUS_CLIENT_RBCN, 2053 DBG_BUS_CLIENT_RBCP, 2054 DBG_BUS_CLIENT_RBCR, 2055 DBG_BUS_CLIENT_RBCT, 2056 DBG_BUS_CLIENT_RBCU, 2057 DBG_BUS_CLIENT_RBCF, 2058 DBG_BUS_CLIENT_RBCX, 2059 DBG_BUS_CLIENT_RBCS, 2060 DBG_BUS_CLIENT_RBCH, 2061 DBG_BUS_CLIENT_RBCZ, 2062 DBG_BUS_CLIENT_OTHER_ENGINE, 2063 DBG_BUS_CLIENT_TIMESTAMP, 2064 DBG_BUS_CLIENT_CPU, 2065 DBG_BUS_CLIENT_RBCY, 2066 DBG_BUS_CLIENT_RBCQ, 2067 DBG_BUS_CLIENT_RBCM, 2068 DBG_BUS_CLIENT_RBCB, 2069 DBG_BUS_CLIENT_RBCW, 2070 DBG_BUS_CLIENT_RBCV, 2071 MAX_DBG_BUS_CLIENTS 2072 }; 2073 2074 enum dbg_bus_constraint_ops { 2075 DBG_BUS_CONSTRAINT_OP_EQ, 2076 DBG_BUS_CONSTRAINT_OP_NE, 2077 DBG_BUS_CONSTRAINT_OP_LT, 2078 DBG_BUS_CONSTRAINT_OP_LTC, 2079 DBG_BUS_CONSTRAINT_OP_LE, 2080 DBG_BUS_CONSTRAINT_OP_LEC, 2081 DBG_BUS_CONSTRAINT_OP_GT, 2082 DBG_BUS_CONSTRAINT_OP_GTC, 2083 DBG_BUS_CONSTRAINT_OP_GE, 2084 DBG_BUS_CONSTRAINT_OP_GEC, 2085 MAX_DBG_BUS_CONSTRAINT_OPS 2086 }; 2087 2088 struct dbg_bus_trigger_state_data { 2089 u8 data; 2090 #define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_MASK 0xF 2091 #define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_SHIFT 0 2092 #define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_MASK 0xF 2093 #define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_SHIFT 4 2094 }; 2095 2096 /* Debug Bus memory address */ 2097 struct dbg_bus_mem_addr { 2098 __le32 lo; 2099 __le32 hi; 2100 }; 2101 2102 /* Debug Bus PCI buffer data */ 2103 struct dbg_bus_pci_buf_data { 2104 struct dbg_bus_mem_addr phys_addr; /* PCI buffer physical address */ 2105 struct dbg_bus_mem_addr virt_addr; /* PCI buffer virtual address */ 2106 __le32 size; /* PCI buffer size in bytes */ 2107 }; 2108 2109 /* Debug Bus Storm EID range filter params */ 2110 struct dbg_bus_storm_eid_range_params { 2111 u8 min; /* Minimal event ID to filter on */ 2112 u8 max; /* Maximal event ID to filter on */ 2113 }; 2114 2115 /* Debug Bus Storm EID mask filter params */ 2116 struct dbg_bus_storm_eid_mask_params { 2117 u8 val; /* Event ID value */ 2118 u8 mask; /* Event ID mask. 1s in the mask = dont care bits. */ 2119 }; 2120 2121 /* Debug Bus Storm EID filter params */ 2122 union dbg_bus_storm_eid_params { 2123 struct dbg_bus_storm_eid_range_params range; 2124 struct dbg_bus_storm_eid_mask_params mask; 2125 }; 2126 2127 /* Debug Bus Storm data */ 2128 struct dbg_bus_storm_data { 2129 u8 enabled; 2130 u8 mode; 2131 u8 hw_id; 2132 u8 eid_filter_en; 2133 u8 eid_range_not_mask; 2134 u8 cid_filter_en; 2135 union dbg_bus_storm_eid_params eid_filter_params; 2136 __le32 cid; 2137 }; 2138 2139 /* Debug Bus data */ 2140 struct dbg_bus_data { 2141 __le32 app_version; 2142 u8 state; 2143 u8 hw_dwords; 2144 __le16 hw_id_mask; 2145 u8 num_enabled_blocks; 2146 u8 num_enabled_storms; 2147 u8 target; 2148 u8 one_shot_en; 2149 u8 grc_input_en; 2150 u8 timestamp_input_en; 2151 u8 filter_en; 2152 u8 adding_filter; 2153 u8 filter_pre_trigger; 2154 u8 filter_post_trigger; 2155 __le16 reserved; 2156 u8 trigger_en; 2157 struct dbg_bus_trigger_state_data trigger_states[3]; 2158 u8 next_trigger_state; 2159 u8 next_constraint_id; 2160 u8 unify_inputs; 2161 u8 rcv_from_other_engine; 2162 struct dbg_bus_pci_buf_data pci_buf; 2163 struct dbg_bus_block_data blocks[88]; 2164 struct dbg_bus_storm_data storms[6]; 2165 }; 2166 2167 enum dbg_bus_filter_types { 2168 DBG_BUS_FILTER_TYPE_OFF, 2169 DBG_BUS_FILTER_TYPE_PRE, 2170 DBG_BUS_FILTER_TYPE_POST, 2171 DBG_BUS_FILTER_TYPE_ON, 2172 MAX_DBG_BUS_FILTER_TYPES 2173 }; 2174 2175 /* Debug bus frame modes */ 2176 enum dbg_bus_frame_modes { 2177 DBG_BUS_FRAME_MODE_0HW_4ST = 0, /* 0 HW dwords, 4 Storm dwords */ 2178 DBG_BUS_FRAME_MODE_4HW_0ST = 3, /* 4 HW dwords, 0 Storm dwords */ 2179 DBG_BUS_FRAME_MODE_8HW_0ST = 4, /* 8 HW dwords, 0 Storm dwords */ 2180 MAX_DBG_BUS_FRAME_MODES 2181 }; 2182 2183 enum dbg_bus_other_engine_modes { 2184 DBG_BUS_OTHER_ENGINE_MODE_NONE, 2185 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX, 2186 DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_RX, 2187 DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX, 2188 DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX, 2189 MAX_DBG_BUS_OTHER_ENGINE_MODES 2190 }; 2191 2192 enum dbg_bus_post_trigger_types { 2193 DBG_BUS_POST_TRIGGER_RECORD, 2194 DBG_BUS_POST_TRIGGER_DROP, 2195 MAX_DBG_BUS_POST_TRIGGER_TYPES 2196 }; 2197 2198 enum dbg_bus_pre_trigger_types { 2199 DBG_BUS_PRE_TRIGGER_START_FROM_ZERO, 2200 DBG_BUS_PRE_TRIGGER_NUM_CHUNKS, 2201 DBG_BUS_PRE_TRIGGER_DROP, 2202 MAX_DBG_BUS_PRE_TRIGGER_TYPES 2203 }; 2204 2205 enum dbg_bus_semi_frame_modes { 2206 DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST = 2207 0, 2208 DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST = 2209 3, 2210 MAX_DBG_BUS_SEMI_FRAME_MODES 2211 }; 2212 2213 /* Debug bus states */ 2214 enum dbg_bus_states { 2215 DBG_BUS_STATE_IDLE, 2216 DBG_BUS_STATE_READY, 2217 DBG_BUS_STATE_RECORDING, 2218 DBG_BUS_STATE_STOPPED, 2219 MAX_DBG_BUS_STATES 2220 }; 2221 2222 enum dbg_bus_storm_modes { 2223 DBG_BUS_STORM_MODE_PRINTF, 2224 DBG_BUS_STORM_MODE_PRAM_ADDR, 2225 DBG_BUS_STORM_MODE_DRA_RW, 2226 DBG_BUS_STORM_MODE_DRA_W, 2227 DBG_BUS_STORM_MODE_LD_ST_ADDR, 2228 DBG_BUS_STORM_MODE_DRA_FSM, 2229 DBG_BUS_STORM_MODE_RH, 2230 DBG_BUS_STORM_MODE_FOC, 2231 DBG_BUS_STORM_MODE_EXT_STORE, 2232 MAX_DBG_BUS_STORM_MODES 2233 }; 2234 2235 /* Debug bus target IDs */ 2236 enum dbg_bus_targets { 2237 DBG_BUS_TARGET_ID_INT_BUF, 2238 DBG_BUS_TARGET_ID_NIG, 2239 DBG_BUS_TARGET_ID_PCI, 2240 MAX_DBG_BUS_TARGETS 2241 }; 2242 2243 /* GRC Dump data */ 2244 struct dbg_grc_data { 2245 u8 params_initialized; 2246 u8 reserved1; 2247 __le16 reserved2; 2248 __le32 param_val[48]; 2249 }; 2250 2251 /* Debug GRC params */ 2252 enum dbg_grc_params { 2253 DBG_GRC_PARAM_DUMP_TSTORM, 2254 DBG_GRC_PARAM_DUMP_MSTORM, 2255 DBG_GRC_PARAM_DUMP_USTORM, 2256 DBG_GRC_PARAM_DUMP_XSTORM, 2257 DBG_GRC_PARAM_DUMP_YSTORM, 2258 DBG_GRC_PARAM_DUMP_PSTORM, 2259 DBG_GRC_PARAM_DUMP_REGS, 2260 DBG_GRC_PARAM_DUMP_RAM, 2261 DBG_GRC_PARAM_DUMP_PBUF, 2262 DBG_GRC_PARAM_DUMP_IOR, 2263 DBG_GRC_PARAM_DUMP_VFC, 2264 DBG_GRC_PARAM_DUMP_CM_CTX, 2265 DBG_GRC_PARAM_DUMP_PXP, 2266 DBG_GRC_PARAM_DUMP_RSS, 2267 DBG_GRC_PARAM_DUMP_CAU, 2268 DBG_GRC_PARAM_DUMP_QM, 2269 DBG_GRC_PARAM_DUMP_MCP, 2270 DBG_GRC_PARAM_RESERVED, 2271 DBG_GRC_PARAM_DUMP_CFC, 2272 DBG_GRC_PARAM_DUMP_IGU, 2273 DBG_GRC_PARAM_DUMP_BRB, 2274 DBG_GRC_PARAM_DUMP_BTB, 2275 DBG_GRC_PARAM_DUMP_BMB, 2276 DBG_GRC_PARAM_DUMP_NIG, 2277 DBG_GRC_PARAM_DUMP_MULD, 2278 DBG_GRC_PARAM_DUMP_PRS, 2279 DBG_GRC_PARAM_DUMP_DMAE, 2280 DBG_GRC_PARAM_DUMP_TM, 2281 DBG_GRC_PARAM_DUMP_SDM, 2282 DBG_GRC_PARAM_DUMP_DIF, 2283 DBG_GRC_PARAM_DUMP_STATIC, 2284 DBG_GRC_PARAM_UNSTALL, 2285 DBG_GRC_PARAM_NUM_LCIDS, 2286 DBG_GRC_PARAM_NUM_LTIDS, 2287 DBG_GRC_PARAM_EXCLUDE_ALL, 2288 DBG_GRC_PARAM_CRASH, 2289 DBG_GRC_PARAM_PARITY_SAFE, 2290 DBG_GRC_PARAM_DUMP_CM, 2291 DBG_GRC_PARAM_DUMP_PHY, 2292 DBG_GRC_PARAM_NO_MCP, 2293 DBG_GRC_PARAM_NO_FW_VER, 2294 MAX_DBG_GRC_PARAMS 2295 }; 2296 2297 /* Debug reset registers */ 2298 enum dbg_reset_regs { 2299 DBG_RESET_REG_MISCS_PL_UA, 2300 DBG_RESET_REG_MISCS_PL_HV, 2301 DBG_RESET_REG_MISCS_PL_HV_2, 2302 DBG_RESET_REG_MISC_PL_UA, 2303 DBG_RESET_REG_MISC_PL_HV, 2304 DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 2305 DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 2306 DBG_RESET_REG_MISC_PL_PDA_VAUX, 2307 MAX_DBG_RESET_REGS 2308 }; 2309 2310 /* Debug status codes */ 2311 enum dbg_status { 2312 DBG_STATUS_OK, 2313 DBG_STATUS_APP_VERSION_NOT_SET, 2314 DBG_STATUS_UNSUPPORTED_APP_VERSION, 2315 DBG_STATUS_DBG_BLOCK_NOT_RESET, 2316 DBG_STATUS_INVALID_ARGS, 2317 DBG_STATUS_OUTPUT_ALREADY_SET, 2318 DBG_STATUS_INVALID_PCI_BUF_SIZE, 2319 DBG_STATUS_PCI_BUF_ALLOC_FAILED, 2320 DBG_STATUS_PCI_BUF_NOT_ALLOCATED, 2321 DBG_STATUS_TOO_MANY_INPUTS, 2322 DBG_STATUS_INPUT_OVERLAP, 2323 DBG_STATUS_HW_ONLY_RECORDING, 2324 DBG_STATUS_STORM_ALREADY_ENABLED, 2325 DBG_STATUS_STORM_NOT_ENABLED, 2326 DBG_STATUS_BLOCK_ALREADY_ENABLED, 2327 DBG_STATUS_BLOCK_NOT_ENABLED, 2328 DBG_STATUS_NO_INPUT_ENABLED, 2329 DBG_STATUS_NO_FILTER_TRIGGER_64B, 2330 DBG_STATUS_FILTER_ALREADY_ENABLED, 2331 DBG_STATUS_TRIGGER_ALREADY_ENABLED, 2332 DBG_STATUS_TRIGGER_NOT_ENABLED, 2333 DBG_STATUS_CANT_ADD_CONSTRAINT, 2334 DBG_STATUS_TOO_MANY_TRIGGER_STATES, 2335 DBG_STATUS_TOO_MANY_CONSTRAINTS, 2336 DBG_STATUS_RECORDING_NOT_STARTED, 2337 DBG_STATUS_DATA_DIDNT_TRIGGER, 2338 DBG_STATUS_NO_DATA_RECORDED, 2339 DBG_STATUS_DUMP_BUF_TOO_SMALL, 2340 DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED, 2341 DBG_STATUS_UNKNOWN_CHIP, 2342 DBG_STATUS_VIRT_MEM_ALLOC_FAILED, 2343 DBG_STATUS_BLOCK_IN_RESET, 2344 DBG_STATUS_INVALID_TRACE_SIGNATURE, 2345 DBG_STATUS_INVALID_NVRAM_BUNDLE, 2346 DBG_STATUS_NVRAM_GET_IMAGE_FAILED, 2347 DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE, 2348 DBG_STATUS_NVRAM_READ_FAILED, 2349 DBG_STATUS_IDLE_CHK_PARSE_FAILED, 2350 DBG_STATUS_MCP_TRACE_BAD_DATA, 2351 DBG_STATUS_MCP_TRACE_NO_META, 2352 DBG_STATUS_MCP_COULD_NOT_HALT, 2353 DBG_STATUS_MCP_COULD_NOT_RESUME, 2354 DBG_STATUS_DMAE_FAILED, 2355 DBG_STATUS_SEMI_FIFO_NOT_EMPTY, 2356 DBG_STATUS_IGU_FIFO_BAD_DATA, 2357 DBG_STATUS_MCP_COULD_NOT_MASK_PRTY, 2358 DBG_STATUS_FW_ASSERTS_PARSE_FAILED, 2359 DBG_STATUS_REG_FIFO_BAD_DATA, 2360 DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA, 2361 DBG_STATUS_DBG_ARRAY_NOT_SET, 2362 DBG_STATUS_FILTER_BUG, 2363 DBG_STATUS_NON_MATCHING_LINES, 2364 DBG_STATUS_INVALID_TRIGGER_DWORD_OFFSET, 2365 DBG_STATUS_DBG_BUS_IN_USE, 2366 MAX_DBG_STATUS 2367 }; 2368 2369 /* Debug Storms IDs */ 2370 enum dbg_storms { 2371 DBG_TSTORM_ID, 2372 DBG_MSTORM_ID, 2373 DBG_USTORM_ID, 2374 DBG_XSTORM_ID, 2375 DBG_YSTORM_ID, 2376 DBG_PSTORM_ID, 2377 MAX_DBG_STORMS 2378 }; 2379 2380 /* Idle Check data */ 2381 struct idle_chk_data { 2382 __le32 buf_size; 2383 u8 buf_size_set; 2384 u8 reserved1; 2385 __le16 reserved2; 2386 }; 2387 2388 /* Debug Tools data (per HW function) */ 2389 struct dbg_tools_data { 2390 struct dbg_grc_data grc; 2391 struct dbg_bus_data bus; 2392 struct idle_chk_data idle_chk; 2393 u8 mode_enable[40]; 2394 u8 block_in_reset[88]; 2395 u8 chip_id; 2396 u8 platform_id; 2397 u8 initialized; 2398 u8 reserved; 2399 }; 2400 2401 /********************************/ 2402 /* HSI Init Functions constants */ 2403 /********************************/ 2404 2405 /* Number of VLAN priorities */ 2406 #define NUM_OF_VLAN_PRIORITIES 8 2407 2408 struct init_brb_ram_req { 2409 __le32 guranteed_per_tc; 2410 __le32 headroom_per_tc; 2411 __le32 min_pkt_size; 2412 __le32 max_ports_per_engine; 2413 u8 num_active_tcs[MAX_NUM_PORTS]; 2414 }; 2415 2416 struct init_ets_tc_req { 2417 u8 use_sp; 2418 u8 use_wfq; 2419 __le16 weight; 2420 }; 2421 2422 struct init_ets_req { 2423 __le32 mtu; 2424 struct init_ets_tc_req tc_req[NUM_OF_TCS]; 2425 }; 2426 2427 struct init_nig_lb_rl_req { 2428 __le16 lb_mac_rate; 2429 __le16 lb_rate; 2430 __le32 mtu; 2431 __le16 tc_rate[NUM_OF_PHYS_TCS]; 2432 }; 2433 2434 struct init_nig_pri_tc_map_entry { 2435 u8 tc_id; 2436 u8 valid; 2437 }; 2438 2439 struct init_nig_pri_tc_map_req { 2440 struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES]; 2441 }; 2442 2443 struct init_qm_port_params { 2444 u8 active; 2445 u8 active_phys_tcs; 2446 __le16 num_pbf_cmd_lines; 2447 __le16 num_btb_blocks; 2448 __le16 reserved; 2449 }; 2450 2451 /* QM per-PQ init parameters */ 2452 struct init_qm_pq_params { 2453 u8 vport_id; 2454 u8 tc_id; 2455 u8 wrr_group; 2456 u8 rl_valid; 2457 }; 2458 2459 /* QM per-vport init parameters */ 2460 struct init_qm_vport_params { 2461 __le32 vport_rl; 2462 __le16 vport_wfq; 2463 __le16 first_tx_pq_id[NUM_OF_TCS]; 2464 }; 2465 2466 /**************************************/ 2467 /* Init Tool HSI constants and macros */ 2468 /**************************************/ 2469 2470 /* Width of GRC address in bits (addresses are specified in dwords) */ 2471 #define GRC_ADDR_BITS 23 2472 #define MAX_GRC_ADDR (BIT(GRC_ADDR_BITS) - 1) 2473 2474 /* indicates an init that should be applied to any phase ID */ 2475 #define ANY_PHASE_ID 0xffff 2476 2477 /* Max size in dwords of a zipped array */ 2478 #define MAX_ZIPPED_SIZE 8192 2479 enum chip_ids { 2480 CHIP_BB, 2481 CHIP_K2, 2482 CHIP_RESERVED, 2483 MAX_CHIP_IDS 2484 }; 2485 2486 struct fw_asserts_ram_section { 2487 __le16 section_ram_line_offset; 2488 __le16 section_ram_line_size; 2489 u8 list_dword_offset; 2490 u8 list_element_dword_size; 2491 u8 list_num_elements; 2492 u8 list_next_index_dword_offset; 2493 }; 2494 2495 struct fw_ver_num { 2496 u8 major; 2497 u8 minor; 2498 u8 rev; 2499 u8 eng; 2500 }; 2501 2502 struct fw_ver_info { 2503 __le16 tools_ver; 2504 u8 image_id; 2505 u8 reserved1; 2506 struct fw_ver_num num; 2507 __le32 timestamp; 2508 __le32 reserved2; 2509 }; 2510 2511 struct fw_info { 2512 struct fw_ver_info ver; 2513 struct fw_asserts_ram_section fw_asserts_section; 2514 }; 2515 2516 struct fw_info_location { 2517 __le32 grc_addr; 2518 __le32 size; 2519 }; 2520 2521 enum init_modes { 2522 MODE_RESERVED, 2523 MODE_BB, 2524 MODE_K2, 2525 MODE_ASIC, 2526 MODE_RESERVED2, 2527 MODE_RESERVED3, 2528 MODE_RESERVED4, 2529 MODE_RESERVED5, 2530 MODE_SF, 2531 MODE_MF_SD, 2532 MODE_MF_SI, 2533 MODE_PORTS_PER_ENG_1, 2534 MODE_PORTS_PER_ENG_2, 2535 MODE_PORTS_PER_ENG_4, 2536 MODE_100G, 2537 MODE_RESERVED6, 2538 MAX_INIT_MODES 2539 }; 2540 2541 enum init_phases { 2542 PHASE_ENGINE, 2543 PHASE_PORT, 2544 PHASE_PF, 2545 PHASE_VF, 2546 PHASE_QM_PF, 2547 MAX_INIT_PHASES 2548 }; 2549 2550 enum init_split_types { 2551 SPLIT_TYPE_NONE, 2552 SPLIT_TYPE_PORT, 2553 SPLIT_TYPE_PF, 2554 SPLIT_TYPE_PORT_PF, 2555 SPLIT_TYPE_VF, 2556 MAX_INIT_SPLIT_TYPES 2557 }; 2558 2559 /* Binary buffer header */ 2560 struct bin_buffer_hdr { 2561 __le32 offset; 2562 __le32 length; 2563 }; 2564 2565 /* binary init buffer types */ 2566 enum bin_init_buffer_type { 2567 BIN_BUF_INIT_FW_VER_INFO, 2568 BIN_BUF_INIT_CMD, 2569 BIN_BUF_INIT_VAL, 2570 BIN_BUF_INIT_MODE_TREE, 2571 BIN_BUF_INIT_IRO, 2572 MAX_BIN_INIT_BUFFER_TYPE 2573 }; 2574 2575 /* init array header: raw */ 2576 struct init_array_raw_hdr { 2577 __le32 data; 2578 #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF 2579 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0 2580 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF 2581 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4 2582 }; 2583 2584 /* init array header: standard */ 2585 struct init_array_standard_hdr { 2586 __le32 data; 2587 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF 2588 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0 2589 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF 2590 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4 2591 }; 2592 2593 /* init array header: zipped */ 2594 struct init_array_zipped_hdr { 2595 __le32 data; 2596 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF 2597 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0 2598 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF 2599 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4 2600 }; 2601 2602 /* init array header: pattern */ 2603 struct init_array_pattern_hdr { 2604 __le32 data; 2605 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF 2606 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0 2607 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF 2608 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4 2609 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF 2610 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8 2611 }; 2612 2613 /* init array header union */ 2614 union init_array_hdr { 2615 struct init_array_raw_hdr raw; 2616 struct init_array_standard_hdr standard; 2617 struct init_array_zipped_hdr zipped; 2618 struct init_array_pattern_hdr pattern; 2619 }; 2620 2621 /* init array types */ 2622 enum init_array_types { 2623 INIT_ARR_STANDARD, 2624 INIT_ARR_ZIPPED, 2625 INIT_ARR_PATTERN, 2626 MAX_INIT_ARRAY_TYPES 2627 }; 2628 2629 /* init operation: callback */ 2630 struct init_callback_op { 2631 __le32 op_data; 2632 #define INIT_CALLBACK_OP_OP_MASK 0xF 2633 #define INIT_CALLBACK_OP_OP_SHIFT 0 2634 #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF 2635 #define INIT_CALLBACK_OP_RESERVED_SHIFT 4 2636 __le16 callback_id; 2637 __le16 block_id; 2638 }; 2639 2640 /* init operation: delay */ 2641 struct init_delay_op { 2642 __le32 op_data; 2643 #define INIT_DELAY_OP_OP_MASK 0xF 2644 #define INIT_DELAY_OP_OP_SHIFT 0 2645 #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF 2646 #define INIT_DELAY_OP_RESERVED_SHIFT 4 2647 __le32 delay; 2648 }; 2649 2650 /* init operation: if_mode */ 2651 struct init_if_mode_op { 2652 __le32 op_data; 2653 #define INIT_IF_MODE_OP_OP_MASK 0xF 2654 #define INIT_IF_MODE_OP_OP_SHIFT 0 2655 #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF 2656 #define INIT_IF_MODE_OP_RESERVED1_SHIFT 4 2657 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF 2658 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16 2659 __le16 reserved2; 2660 __le16 modes_buf_offset; 2661 }; 2662 2663 /* init operation: if_phase */ 2664 struct init_if_phase_op { 2665 __le32 op_data; 2666 #define INIT_IF_PHASE_OP_OP_MASK 0xF 2667 #define INIT_IF_PHASE_OP_OP_SHIFT 0 2668 #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1 2669 #define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4 2670 #define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF 2671 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5 2672 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF 2673 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16 2674 __le32 phase_data; 2675 #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF 2676 #define INIT_IF_PHASE_OP_PHASE_SHIFT 0 2677 #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF 2678 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8 2679 #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF 2680 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16 2681 }; 2682 2683 /* init mode operators */ 2684 enum init_mode_ops { 2685 INIT_MODE_OP_NOT, 2686 INIT_MODE_OP_OR, 2687 INIT_MODE_OP_AND, 2688 MAX_INIT_MODE_OPS 2689 }; 2690 2691 /* init operation: raw */ 2692 struct init_raw_op { 2693 __le32 op_data; 2694 #define INIT_RAW_OP_OP_MASK 0xF 2695 #define INIT_RAW_OP_OP_SHIFT 0 2696 #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF 2697 #define INIT_RAW_OP_PARAM1_SHIFT 4 2698 __le32 param2; 2699 }; 2700 2701 /* init array params */ 2702 struct init_op_array_params { 2703 __le16 size; 2704 __le16 offset; 2705 }; 2706 2707 /* Write init operation arguments */ 2708 union init_write_args { 2709 __le32 inline_val; 2710 __le32 zeros_count; 2711 __le32 array_offset; 2712 struct init_op_array_params runtime; 2713 }; 2714 2715 /* init operation: write */ 2716 struct init_write_op { 2717 __le32 data; 2718 #define INIT_WRITE_OP_OP_MASK 0xF 2719 #define INIT_WRITE_OP_OP_SHIFT 0 2720 #define INIT_WRITE_OP_SOURCE_MASK 0x7 2721 #define INIT_WRITE_OP_SOURCE_SHIFT 4 2722 #define INIT_WRITE_OP_RESERVED_MASK 0x1 2723 #define INIT_WRITE_OP_RESERVED_SHIFT 7 2724 #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1 2725 #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8 2726 #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF 2727 #define INIT_WRITE_OP_ADDRESS_SHIFT 9 2728 union init_write_args args; 2729 }; 2730 2731 /* init operation: read */ 2732 struct init_read_op { 2733 __le32 op_data; 2734 #define INIT_READ_OP_OP_MASK 0xF 2735 #define INIT_READ_OP_OP_SHIFT 0 2736 #define INIT_READ_OP_POLL_TYPE_MASK 0xF 2737 #define INIT_READ_OP_POLL_TYPE_SHIFT 4 2738 #define INIT_READ_OP_RESERVED_MASK 0x1 2739 #define INIT_READ_OP_RESERVED_SHIFT 8 2740 #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF 2741 #define INIT_READ_OP_ADDRESS_SHIFT 9 2742 __le32 expected_val; 2743 }; 2744 2745 /* Init operations union */ 2746 union init_op { 2747 struct init_raw_op raw; 2748 struct init_write_op write; 2749 struct init_read_op read; 2750 struct init_if_mode_op if_mode; 2751 struct init_if_phase_op if_phase; 2752 struct init_callback_op callback; 2753 struct init_delay_op delay; 2754 }; 2755 2756 /* Init command operation types */ 2757 enum init_op_types { 2758 INIT_OP_READ, 2759 INIT_OP_WRITE, 2760 INIT_OP_IF_MODE, 2761 INIT_OP_IF_PHASE, 2762 INIT_OP_DELAY, 2763 INIT_OP_CALLBACK, 2764 MAX_INIT_OP_TYPES 2765 }; 2766 2767 /* init polling types */ 2768 enum init_poll_types { 2769 INIT_POLL_NONE, 2770 INIT_POLL_EQ, 2771 INIT_POLL_OR, 2772 INIT_POLL_AND, 2773 MAX_INIT_POLL_TYPES 2774 }; 2775 2776 /* init source types */ 2777 enum init_source_types { 2778 INIT_SRC_INLINE, 2779 INIT_SRC_ZEROS, 2780 INIT_SRC_ARRAY, 2781 INIT_SRC_RUNTIME, 2782 MAX_INIT_SOURCE_TYPES 2783 }; 2784 2785 /* Internal RAM Offsets macro data */ 2786 struct iro { 2787 __le32 base; 2788 __le16 m1; 2789 __le16 m2; 2790 __le16 m3; 2791 __le16 size; 2792 }; 2793 2794 /***************************** Public Functions *******************************/ 2795 /** 2796 * @brief qed_dbg_set_bin_ptr - Sets a pointer to the binary data with debug 2797 * arrays. 2798 * 2799 * @param bin_ptr - a pointer to the binary data with debug arrays. 2800 */ 2801 enum dbg_status qed_dbg_set_bin_ptr(const u8 * const bin_ptr); 2802 2803 /** 2804 * @brief qed_dbg_grc_set_params_default - Reverts all GRC parameters to their 2805 * default value. 2806 * 2807 * @param p_hwfn - HW device data 2808 */ 2809 void qed_dbg_grc_set_params_default(struct qed_hwfn *p_hwfn); 2810 /** 2811 * @brief qed_dbg_grc_get_dump_buf_size - Returns the required buffer size for 2812 * GRC Dump. 2813 * 2814 * @param p_hwfn - HW device data 2815 * @param p_ptt - Ptt window used for writing the registers. 2816 * @param buf_size - OUT: required buffer size (in dwords) for the GRC Dump 2817 * data. 2818 * 2819 * @return error if one of the following holds: 2820 * - the version wasn't set 2821 * Otherwise, returns ok. 2822 */ 2823 enum dbg_status qed_dbg_grc_get_dump_buf_size(struct qed_hwfn *p_hwfn, 2824 struct qed_ptt *p_ptt, 2825 u32 *buf_size); 2826 2827 /** 2828 * @brief qed_dbg_grc_dump - Dumps GRC data into the specified buffer. 2829 * 2830 * @param p_hwfn - HW device data 2831 * @param p_ptt - Ptt window used for writing the registers. 2832 * @param dump_buf - Pointer to write the collected GRC data into. 2833 * @param buf_size_in_dwords - Size of the specified buffer in dwords. 2834 * @param num_dumped_dwords - OUT: number of dumped dwords. 2835 * 2836 * @return error if one of the following holds: 2837 * - the version wasn't set 2838 * - the specified dump buffer is too small 2839 * Otherwise, returns ok. 2840 */ 2841 enum dbg_status qed_dbg_grc_dump(struct qed_hwfn *p_hwfn, 2842 struct qed_ptt *p_ptt, 2843 u32 *dump_buf, 2844 u32 buf_size_in_dwords, 2845 u32 *num_dumped_dwords); 2846 2847 /** 2848 * @brief qed_dbg_idle_chk_get_dump_buf_size - Returns the required buffer size 2849 * for idle check results. 2850 * 2851 * @param p_hwfn - HW device data 2852 * @param p_ptt - Ptt window used for writing the registers. 2853 * @param buf_size - OUT: required buffer size (in dwords) for the idle check 2854 * data. 2855 * 2856 * @return error if one of the following holds: 2857 * - the version wasn't set 2858 * Otherwise, returns ok. 2859 */ 2860 enum dbg_status qed_dbg_idle_chk_get_dump_buf_size(struct qed_hwfn *p_hwfn, 2861 struct qed_ptt *p_ptt, 2862 u32 *buf_size); 2863 2864 /** 2865 * @brief qed_dbg_idle_chk_dump - Performs idle check and writes the results 2866 * into the specified buffer. 2867 * 2868 * @param p_hwfn - HW device data 2869 * @param p_ptt - Ptt window used for writing the registers. 2870 * @param dump_buf - Pointer to write the idle check data into. 2871 * @param buf_size_in_dwords - Size of the specified buffer in dwords. 2872 * @param num_dumped_dwords - OUT: number of dumped dwords. 2873 * 2874 * @return error if one of the following holds: 2875 * - the version wasn't set 2876 * - the specified buffer is too small 2877 * Otherwise, returns ok. 2878 */ 2879 enum dbg_status qed_dbg_idle_chk_dump(struct qed_hwfn *p_hwfn, 2880 struct qed_ptt *p_ptt, 2881 u32 *dump_buf, 2882 u32 buf_size_in_dwords, 2883 u32 *num_dumped_dwords); 2884 2885 /** 2886 * @brief qed_dbg_mcp_trace_get_dump_buf_size - Returns the required buffer size 2887 * for mcp trace results. 2888 * 2889 * @param p_hwfn - HW device data 2890 * @param p_ptt - Ptt window used for writing the registers. 2891 * @param buf_size - OUT: required buffer size (in dwords) for mcp trace data. 2892 * 2893 * @return error if one of the following holds: 2894 * - the version wasn't set 2895 * - the trace data in MCP scratchpad contain an invalid signature 2896 * - the bundle ID in NVRAM is invalid 2897 * - the trace meta data cannot be found (in NVRAM or image file) 2898 * Otherwise, returns ok. 2899 */ 2900 enum dbg_status qed_dbg_mcp_trace_get_dump_buf_size(struct qed_hwfn *p_hwfn, 2901 struct qed_ptt *p_ptt, 2902 u32 *buf_size); 2903 2904 /** 2905 * @brief qed_dbg_mcp_trace_dump - Performs mcp trace and writes the results 2906 * into the specified buffer. 2907 * 2908 * @param p_hwfn - HW device data 2909 * @param p_ptt - Ptt window used for writing the registers. 2910 * @param dump_buf - Pointer to write the mcp trace data into. 2911 * @param buf_size_in_dwords - Size of the specified buffer in dwords. 2912 * @param num_dumped_dwords - OUT: number of dumped dwords. 2913 * 2914 * @return error if one of the following holds: 2915 * - the version wasn't set 2916 * - the specified buffer is too small 2917 * - the trace data in MCP scratchpad contain an invalid signature 2918 * - the bundle ID in NVRAM is invalid 2919 * - the trace meta data cannot be found (in NVRAM or image file) 2920 * - the trace meta data cannot be read (from NVRAM or image file) 2921 * Otherwise, returns ok. 2922 */ 2923 enum dbg_status qed_dbg_mcp_trace_dump(struct qed_hwfn *p_hwfn, 2924 struct qed_ptt *p_ptt, 2925 u32 *dump_buf, 2926 u32 buf_size_in_dwords, 2927 u32 *num_dumped_dwords); 2928 2929 /** 2930 * @brief qed_dbg_reg_fifo_get_dump_buf_size - Returns the required buffer size 2931 * for grc trace fifo results. 2932 * 2933 * @param p_hwfn - HW device data 2934 * @param p_ptt - Ptt window used for writing the registers. 2935 * @param buf_size - OUT: required buffer size (in dwords) for reg fifo data. 2936 * 2937 * @return error if one of the following holds: 2938 * - the version wasn't set 2939 * Otherwise, returns ok. 2940 */ 2941 enum dbg_status qed_dbg_reg_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn, 2942 struct qed_ptt *p_ptt, 2943 u32 *buf_size); 2944 2945 /** 2946 * @brief qed_dbg_reg_fifo_dump - Reads the reg fifo and writes the results into 2947 * the specified buffer. 2948 * 2949 * @param p_hwfn - HW device data 2950 * @param p_ptt - Ptt window used for writing the registers. 2951 * @param dump_buf - Pointer to write the reg fifo data into. 2952 * @param buf_size_in_dwords - Size of the specified buffer in dwords. 2953 * @param num_dumped_dwords - OUT: number of dumped dwords. 2954 * 2955 * @return error if one of the following holds: 2956 * - the version wasn't set 2957 * - the specified buffer is too small 2958 * - DMAE transaction failed 2959 * Otherwise, returns ok. 2960 */ 2961 enum dbg_status qed_dbg_reg_fifo_dump(struct qed_hwfn *p_hwfn, 2962 struct qed_ptt *p_ptt, 2963 u32 *dump_buf, 2964 u32 buf_size_in_dwords, 2965 u32 *num_dumped_dwords); 2966 2967 /** 2968 * @brief qed_dbg_igu_fifo_get_dump_buf_size - Returns the required buffer size 2969 * for the IGU fifo results. 2970 * 2971 * @param p_hwfn - HW device data 2972 * @param p_ptt - Ptt window used for writing the registers. 2973 * @param buf_size - OUT: required buffer size (in dwords) for the IGU fifo 2974 * data. 2975 * 2976 * @return error if one of the following holds: 2977 * - the version wasn't set 2978 * Otherwise, returns ok. 2979 */ 2980 enum dbg_status qed_dbg_igu_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn, 2981 struct qed_ptt *p_ptt, 2982 u32 *buf_size); 2983 2984 /** 2985 * @brief qed_dbg_igu_fifo_dump - Reads the IGU fifo and writes the results into 2986 * the specified buffer. 2987 * 2988 * @param p_hwfn - HW device data 2989 * @param p_ptt - Ptt window used for writing the registers. 2990 * @param dump_buf - Pointer to write the IGU fifo data into. 2991 * @param buf_size_in_dwords - Size of the specified buffer in dwords. 2992 * @param num_dumped_dwords - OUT: number of dumped dwords. 2993 * 2994 * @return error if one of the following holds: 2995 * - the version wasn't set 2996 * - the specified buffer is too small 2997 * - DMAE transaction failed 2998 * Otherwise, returns ok. 2999 */ 3000 enum dbg_status qed_dbg_igu_fifo_dump(struct qed_hwfn *p_hwfn, 3001 struct qed_ptt *p_ptt, 3002 u32 *dump_buf, 3003 u32 buf_size_in_dwords, 3004 u32 *num_dumped_dwords); 3005 3006 /** 3007 * @brief qed_dbg_protection_override_get_dump_buf_size - Returns the required 3008 * buffer size for protection override window results. 3009 * 3010 * @param p_hwfn - HW device data 3011 * @param p_ptt - Ptt window used for writing the registers. 3012 * @param buf_size - OUT: required buffer size (in dwords) for protection 3013 * override data. 3014 * 3015 * @return error if one of the following holds: 3016 * - the version wasn't set 3017 * Otherwise, returns ok. 3018 */ 3019 enum dbg_status 3020 qed_dbg_protection_override_get_dump_buf_size(struct qed_hwfn *p_hwfn, 3021 struct qed_ptt *p_ptt, 3022 u32 *buf_size); 3023 /** 3024 * @brief qed_dbg_protection_override_dump - Reads protection override window 3025 * entries and writes the results into the specified buffer. 3026 * 3027 * @param p_hwfn - HW device data 3028 * @param p_ptt - Ptt window used for writing the registers. 3029 * @param dump_buf - Pointer to write the protection override data into. 3030 * @param buf_size_in_dwords - Size of the specified buffer in dwords. 3031 * @param num_dumped_dwords - OUT: number of dumped dwords. 3032 * 3033 * @return error if one of the following holds: 3034 * - the version wasn't set 3035 * - the specified buffer is too small 3036 * - DMAE transaction failed 3037 * Otherwise, returns ok. 3038 */ 3039 enum dbg_status qed_dbg_protection_override_dump(struct qed_hwfn *p_hwfn, 3040 struct qed_ptt *p_ptt, 3041 u32 *dump_buf, 3042 u32 buf_size_in_dwords, 3043 u32 *num_dumped_dwords); 3044 /** 3045 * @brief qed_dbg_fw_asserts_get_dump_buf_size - Returns the required buffer 3046 * size for FW Asserts results. 3047 * 3048 * @param p_hwfn - HW device data 3049 * @param p_ptt - Ptt window used for writing the registers. 3050 * @param buf_size - OUT: required buffer size (in dwords) for FW Asserts data. 3051 * 3052 * @return error if one of the following holds: 3053 * - the version wasn't set 3054 * Otherwise, returns ok. 3055 */ 3056 enum dbg_status qed_dbg_fw_asserts_get_dump_buf_size(struct qed_hwfn *p_hwfn, 3057 struct qed_ptt *p_ptt, 3058 u32 *buf_size); 3059 /** 3060 * @brief qed_dbg_fw_asserts_dump - Reads the FW Asserts and writes the results 3061 * into the specified buffer. 3062 * 3063 * @param p_hwfn - HW device data 3064 * @param p_ptt - Ptt window used for writing the registers. 3065 * @param dump_buf - Pointer to write the FW Asserts data into. 3066 * @param buf_size_in_dwords - Size of the specified buffer in dwords. 3067 * @param num_dumped_dwords - OUT: number of dumped dwords. 3068 * 3069 * @return error if one of the following holds: 3070 * - the version wasn't set 3071 * - the specified buffer is too small 3072 * Otherwise, returns ok. 3073 */ 3074 enum dbg_status qed_dbg_fw_asserts_dump(struct qed_hwfn *p_hwfn, 3075 struct qed_ptt *p_ptt, 3076 u32 *dump_buf, 3077 u32 buf_size_in_dwords, 3078 u32 *num_dumped_dwords); 3079 /** 3080 * @brief qed_dbg_print_attn - Prints attention registers values in the 3081 * specified results struct. 3082 * 3083 * @param p_hwfn 3084 * @param results - Pointer to the attention read results 3085 * 3086 * @return error if one of the following holds: 3087 * - the version wasn't set 3088 * Otherwise, returns ok. 3089 */ 3090 enum dbg_status qed_dbg_print_attn(struct qed_hwfn *p_hwfn, 3091 struct dbg_attn_block_result *results); 3092 3093 /******************************** Constants **********************************/ 3094 3095 #define MAX_NAME_LEN 16 3096 3097 /***************************** Public Functions *******************************/ 3098 /** 3099 * @brief qed_dbg_user_set_bin_ptr - Sets a pointer to the binary data with 3100 * debug arrays. 3101 * 3102 * @param bin_ptr - a pointer to the binary data with debug arrays. 3103 */ 3104 enum dbg_status qed_dbg_user_set_bin_ptr(const u8 * const bin_ptr); 3105 3106 /** 3107 * @brief qed_dbg_get_status_str - Returns a string for the specified status. 3108 * 3109 * @param status - a debug status code. 3110 * 3111 * @return a string for the specified status 3112 */ 3113 const char *qed_dbg_get_status_str(enum dbg_status status); 3114 3115 /** 3116 * @brief qed_get_idle_chk_results_buf_size - Returns the required buffer size 3117 * for idle check results (in bytes). 3118 * 3119 * @param p_hwfn - HW device data 3120 * @param dump_buf - idle check dump buffer. 3121 * @param num_dumped_dwords - number of dwords that were dumped. 3122 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed 3123 * results. 3124 * 3125 * @return error if the parsing fails, ok otherwise. 3126 */ 3127 enum dbg_status qed_get_idle_chk_results_buf_size(struct qed_hwfn *p_hwfn, 3128 u32 *dump_buf, 3129 u32 num_dumped_dwords, 3130 u32 *results_buf_size); 3131 /** 3132 * @brief qed_print_idle_chk_results - Prints idle check results 3133 * 3134 * @param p_hwfn - HW device data 3135 * @param dump_buf - idle check dump buffer. 3136 * @param num_dumped_dwords - number of dwords that were dumped. 3137 * @param results_buf - buffer for printing the idle check results. 3138 * @param num_errors - OUT: number of errors found in idle check. 3139 * @param num_warnings - OUT: number of warnings found in idle check. 3140 * 3141 * @return error if the parsing fails, ok otherwise. 3142 */ 3143 enum dbg_status qed_print_idle_chk_results(struct qed_hwfn *p_hwfn, 3144 u32 *dump_buf, 3145 u32 num_dumped_dwords, 3146 char *results_buf, 3147 u32 *num_errors, 3148 u32 *num_warnings); 3149 3150 /** 3151 * @brief qed_get_mcp_trace_results_buf_size - Returns the required buffer size 3152 * for MCP Trace results (in bytes). 3153 * 3154 * @param p_hwfn - HW device data 3155 * @param dump_buf - MCP Trace dump buffer. 3156 * @param num_dumped_dwords - number of dwords that were dumped. 3157 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed 3158 * results. 3159 * 3160 * @return error if the parsing fails, ok otherwise. 3161 */ 3162 enum dbg_status qed_get_mcp_trace_results_buf_size(struct qed_hwfn *p_hwfn, 3163 u32 *dump_buf, 3164 u32 num_dumped_dwords, 3165 u32 *results_buf_size); 3166 3167 /** 3168 * @brief qed_print_mcp_trace_results - Prints MCP Trace results 3169 * 3170 * @param p_hwfn - HW device data 3171 * @param dump_buf - mcp trace dump buffer, starting from the header. 3172 * @param num_dumped_dwords - number of dwords that were dumped. 3173 * @param results_buf - buffer for printing the mcp trace results. 3174 * 3175 * @return error if the parsing fails, ok otherwise. 3176 */ 3177 enum dbg_status qed_print_mcp_trace_results(struct qed_hwfn *p_hwfn, 3178 u32 *dump_buf, 3179 u32 num_dumped_dwords, 3180 char *results_buf); 3181 3182 /** 3183 * @brief qed_get_reg_fifo_results_buf_size - Returns the required buffer size 3184 * for reg_fifo results (in bytes). 3185 * 3186 * @param p_hwfn - HW device data 3187 * @param dump_buf - reg fifo dump buffer. 3188 * @param num_dumped_dwords - number of dwords that were dumped. 3189 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed 3190 * results. 3191 * 3192 * @return error if the parsing fails, ok otherwise. 3193 */ 3194 enum dbg_status qed_get_reg_fifo_results_buf_size(struct qed_hwfn *p_hwfn, 3195 u32 *dump_buf, 3196 u32 num_dumped_dwords, 3197 u32 *results_buf_size); 3198 3199 /** 3200 * @brief qed_print_reg_fifo_results - Prints reg fifo results 3201 * 3202 * @param p_hwfn - HW device data 3203 * @param dump_buf - reg fifo dump buffer, starting from the header. 3204 * @param num_dumped_dwords - number of dwords that were dumped. 3205 * @param results_buf - buffer for printing the reg fifo results. 3206 * 3207 * @return error if the parsing fails, ok otherwise. 3208 */ 3209 enum dbg_status qed_print_reg_fifo_results(struct qed_hwfn *p_hwfn, 3210 u32 *dump_buf, 3211 u32 num_dumped_dwords, 3212 char *results_buf); 3213 3214 /** 3215 * @brief qed_get_igu_fifo_results_buf_size - Returns the required buffer size 3216 * for igu_fifo results (in bytes). 3217 * 3218 * @param p_hwfn - HW device data 3219 * @param dump_buf - IGU fifo dump buffer. 3220 * @param num_dumped_dwords - number of dwords that were dumped. 3221 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed 3222 * results. 3223 * 3224 * @return error if the parsing fails, ok otherwise. 3225 */ 3226 enum dbg_status qed_get_igu_fifo_results_buf_size(struct qed_hwfn *p_hwfn, 3227 u32 *dump_buf, 3228 u32 num_dumped_dwords, 3229 u32 *results_buf_size); 3230 3231 /** 3232 * @brief qed_print_igu_fifo_results - Prints IGU fifo results 3233 * 3234 * @param p_hwfn - HW device data 3235 * @param dump_buf - IGU fifo dump buffer, starting from the header. 3236 * @param num_dumped_dwords - number of dwords that were dumped. 3237 * @param results_buf - buffer for printing the IGU fifo results. 3238 * 3239 * @return error if the parsing fails, ok otherwise. 3240 */ 3241 enum dbg_status qed_print_igu_fifo_results(struct qed_hwfn *p_hwfn, 3242 u32 *dump_buf, 3243 u32 num_dumped_dwords, 3244 char *results_buf); 3245 3246 /** 3247 * @brief qed_get_protection_override_results_buf_size - Returns the required 3248 * buffer size for protection override results (in bytes). 3249 * 3250 * @param p_hwfn - HW device data 3251 * @param dump_buf - protection override dump buffer. 3252 * @param num_dumped_dwords - number of dwords that were dumped. 3253 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed 3254 * results. 3255 * 3256 * @return error if the parsing fails, ok otherwise. 3257 */ 3258 enum dbg_status 3259 qed_get_protection_override_results_buf_size(struct qed_hwfn *p_hwfn, 3260 u32 *dump_buf, 3261 u32 num_dumped_dwords, 3262 u32 *results_buf_size); 3263 3264 /** 3265 * @brief qed_print_protection_override_results - Prints protection override 3266 * results. 3267 * 3268 * @param p_hwfn - HW device data 3269 * @param dump_buf - protection override dump buffer, starting from the header. 3270 * @param num_dumped_dwords - number of dwords that were dumped. 3271 * @param results_buf - buffer for printing the reg fifo results. 3272 * 3273 * @return error if the parsing fails, ok otherwise. 3274 */ 3275 enum dbg_status qed_print_protection_override_results(struct qed_hwfn *p_hwfn, 3276 u32 *dump_buf, 3277 u32 num_dumped_dwords, 3278 char *results_buf); 3279 3280 /** 3281 * @brief qed_get_fw_asserts_results_buf_size - Returns the required buffer size 3282 * for FW Asserts results (in bytes). 3283 * 3284 * @param p_hwfn - HW device data 3285 * @param dump_buf - FW Asserts dump buffer. 3286 * @param num_dumped_dwords - number of dwords that were dumped. 3287 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed 3288 * results. 3289 * 3290 * @return error if the parsing fails, ok otherwise. 3291 */ 3292 enum dbg_status qed_get_fw_asserts_results_buf_size(struct qed_hwfn *p_hwfn, 3293 u32 *dump_buf, 3294 u32 num_dumped_dwords, 3295 u32 *results_buf_size); 3296 3297 /** 3298 * @brief qed_print_fw_asserts_results - Prints FW Asserts results 3299 * 3300 * @param p_hwfn - HW device data 3301 * @param dump_buf - FW Asserts dump buffer, starting from the header. 3302 * @param num_dumped_dwords - number of dwords that were dumped. 3303 * @param results_buf - buffer for printing the FW Asserts results. 3304 * 3305 * @return error if the parsing fails, ok otherwise. 3306 */ 3307 enum dbg_status qed_print_fw_asserts_results(struct qed_hwfn *p_hwfn, 3308 u32 *dump_buf, 3309 u32 num_dumped_dwords, 3310 char *results_buf); 3311 3312 /* Debug Bus blocks */ 3313 static const u32 dbg_bus_blocks[] = { 3314 0x0000000f, /* grc, bb, 15 lines */ 3315 0x0000000f, /* grc, k2, 15 lines */ 3316 0x00000000, 3317 0x00000000, /* miscs, bb, 0 lines */ 3318 0x00000000, /* miscs, k2, 0 lines */ 3319 0x00000000, 3320 0x00000000, /* misc, bb, 0 lines */ 3321 0x00000000, /* misc, k2, 0 lines */ 3322 0x00000000, 3323 0x00000000, /* dbu, bb, 0 lines */ 3324 0x00000000, /* dbu, k2, 0 lines */ 3325 0x00000000, 3326 0x000f0127, /* pglue_b, bb, 39 lines */ 3327 0x0036012a, /* pglue_b, k2, 42 lines */ 3328 0x00000000, 3329 0x00000000, /* cnig, bb, 0 lines */ 3330 0x00120102, /* cnig, k2, 2 lines */ 3331 0x00000000, 3332 0x00000000, /* cpmu, bb, 0 lines */ 3333 0x00000000, /* cpmu, k2, 0 lines */ 3334 0x00000000, 3335 0x00000001, /* ncsi, bb, 1 lines */ 3336 0x00000001, /* ncsi, k2, 1 lines */ 3337 0x00000000, 3338 0x00000000, /* opte, bb, 0 lines */ 3339 0x00000000, /* opte, k2, 0 lines */ 3340 0x00000000, 3341 0x00600085, /* bmb, bb, 133 lines */ 3342 0x00600085, /* bmb, k2, 133 lines */ 3343 0x00000000, 3344 0x00000000, /* pcie, bb, 0 lines */ 3345 0x00e50033, /* pcie, k2, 51 lines */ 3346 0x00000000, 3347 0x00000000, /* mcp, bb, 0 lines */ 3348 0x00000000, /* mcp, k2, 0 lines */ 3349 0x00000000, 3350 0x01180009, /* mcp2, bb, 9 lines */ 3351 0x01180009, /* mcp2, k2, 9 lines */ 3352 0x00000000, 3353 0x01210104, /* pswhst, bb, 4 lines */ 3354 0x01210104, /* pswhst, k2, 4 lines */ 3355 0x00000000, 3356 0x01250103, /* pswhst2, bb, 3 lines */ 3357 0x01250103, /* pswhst2, k2, 3 lines */ 3358 0x00000000, 3359 0x00340101, /* pswrd, bb, 1 lines */ 3360 0x00340101, /* pswrd, k2, 1 lines */ 3361 0x00000000, 3362 0x01280119, /* pswrd2, bb, 25 lines */ 3363 0x01280119, /* pswrd2, k2, 25 lines */ 3364 0x00000000, 3365 0x01410109, /* pswwr, bb, 9 lines */ 3366 0x01410109, /* pswwr, k2, 9 lines */ 3367 0x00000000, 3368 0x00000000, /* pswwr2, bb, 0 lines */ 3369 0x00000000, /* pswwr2, k2, 0 lines */ 3370 0x00000000, 3371 0x001c0001, /* pswrq, bb, 1 lines */ 3372 0x001c0001, /* pswrq, k2, 1 lines */ 3373 0x00000000, 3374 0x014a0015, /* pswrq2, bb, 21 lines */ 3375 0x014a0015, /* pswrq2, k2, 21 lines */ 3376 0x00000000, 3377 0x00000000, /* pglcs, bb, 0 lines */ 3378 0x00120006, /* pglcs, k2, 6 lines */ 3379 0x00000000, 3380 0x00100001, /* dmae, bb, 1 lines */ 3381 0x00100001, /* dmae, k2, 1 lines */ 3382 0x00000000, 3383 0x015f0105, /* ptu, bb, 5 lines */ 3384 0x015f0105, /* ptu, k2, 5 lines */ 3385 0x00000000, 3386 0x01640120, /* tcm, bb, 32 lines */ 3387 0x01640120, /* tcm, k2, 32 lines */ 3388 0x00000000, 3389 0x01640120, /* mcm, bb, 32 lines */ 3390 0x01640120, /* mcm, k2, 32 lines */ 3391 0x00000000, 3392 0x01640120, /* ucm, bb, 32 lines */ 3393 0x01640120, /* ucm, k2, 32 lines */ 3394 0x00000000, 3395 0x01640120, /* xcm, bb, 32 lines */ 3396 0x01640120, /* xcm, k2, 32 lines */ 3397 0x00000000, 3398 0x01640120, /* ycm, bb, 32 lines */ 3399 0x01640120, /* ycm, k2, 32 lines */ 3400 0x00000000, 3401 0x01640120, /* pcm, bb, 32 lines */ 3402 0x01640120, /* pcm, k2, 32 lines */ 3403 0x00000000, 3404 0x01840062, /* qm, bb, 98 lines */ 3405 0x01840062, /* qm, k2, 98 lines */ 3406 0x00000000, 3407 0x01e60021, /* tm, bb, 33 lines */ 3408 0x01e60021, /* tm, k2, 33 lines */ 3409 0x00000000, 3410 0x02070107, /* dorq, bb, 7 lines */ 3411 0x02070107, /* dorq, k2, 7 lines */ 3412 0x00000000, 3413 0x00600185, /* brb, bb, 133 lines */ 3414 0x00600185, /* brb, k2, 133 lines */ 3415 0x00000000, 3416 0x020e0019, /* src, bb, 25 lines */ 3417 0x020c001a, /* src, k2, 26 lines */ 3418 0x00000000, 3419 0x02270104, /* prs, bb, 4 lines */ 3420 0x02270104, /* prs, k2, 4 lines */ 3421 0x00000000, 3422 0x022b0133, /* tsdm, bb, 51 lines */ 3423 0x022b0133, /* tsdm, k2, 51 lines */ 3424 0x00000000, 3425 0x022b0133, /* msdm, bb, 51 lines */ 3426 0x022b0133, /* msdm, k2, 51 lines */ 3427 0x00000000, 3428 0x022b0133, /* usdm, bb, 51 lines */ 3429 0x022b0133, /* usdm, k2, 51 lines */ 3430 0x00000000, 3431 0x022b0133, /* xsdm, bb, 51 lines */ 3432 0x022b0133, /* xsdm, k2, 51 lines */ 3433 0x00000000, 3434 0x022b0133, /* ysdm, bb, 51 lines */ 3435 0x022b0133, /* ysdm, k2, 51 lines */ 3436 0x00000000, 3437 0x022b0133, /* psdm, bb, 51 lines */ 3438 0x022b0133, /* psdm, k2, 51 lines */ 3439 0x00000000, 3440 0x025e010c, /* tsem, bb, 12 lines */ 3441 0x025e010c, /* tsem, k2, 12 lines */ 3442 0x00000000, 3443 0x025e010c, /* msem, bb, 12 lines */ 3444 0x025e010c, /* msem, k2, 12 lines */ 3445 0x00000000, 3446 0x025e010c, /* usem, bb, 12 lines */ 3447 0x025e010c, /* usem, k2, 12 lines */ 3448 0x00000000, 3449 0x025e010c, /* xsem, bb, 12 lines */ 3450 0x025e010c, /* xsem, k2, 12 lines */ 3451 0x00000000, 3452 0x025e010c, /* ysem, bb, 12 lines */ 3453 0x025e010c, /* ysem, k2, 12 lines */ 3454 0x00000000, 3455 0x025e010c, /* psem, bb, 12 lines */ 3456 0x025e010c, /* psem, k2, 12 lines */ 3457 0x00000000, 3458 0x026a000d, /* rss, bb, 13 lines */ 3459 0x026a000d, /* rss, k2, 13 lines */ 3460 0x00000000, 3461 0x02770106, /* tmld, bb, 6 lines */ 3462 0x02770106, /* tmld, k2, 6 lines */ 3463 0x00000000, 3464 0x027d0106, /* muld, bb, 6 lines */ 3465 0x027d0106, /* muld, k2, 6 lines */ 3466 0x00000000, 3467 0x02770005, /* yuld, bb, 5 lines */ 3468 0x02770005, /* yuld, k2, 5 lines */ 3469 0x00000000, 3470 0x02830107, /* xyld, bb, 7 lines */ 3471 0x027d0107, /* xyld, k2, 7 lines */ 3472 0x00000000, 3473 0x00000000, /* ptld, bb, 0 lines */ 3474 0x00000000, /* ptld, k2, 0 lines */ 3475 0x00000000, 3476 0x00000000, /* ypld, bb, 0 lines */ 3477 0x00000000, /* ypld, k2, 0 lines */ 3478 0x00000000, 3479 0x028a010e, /* prm, bb, 14 lines */ 3480 0x02980110, /* prm, k2, 16 lines */ 3481 0x00000000, 3482 0x02a8000d, /* pbf_pb1, bb, 13 lines */ 3483 0x02a8000d, /* pbf_pb1, k2, 13 lines */ 3484 0x00000000, 3485 0x02a8000d, /* pbf_pb2, bb, 13 lines */ 3486 0x02a8000d, /* pbf_pb2, k2, 13 lines */ 3487 0x00000000, 3488 0x02a8000d, /* rpb, bb, 13 lines */ 3489 0x02a8000d, /* rpb, k2, 13 lines */ 3490 0x00000000, 3491 0x00600185, /* btb, bb, 133 lines */ 3492 0x00600185, /* btb, k2, 133 lines */ 3493 0x00000000, 3494 0x02b50117, /* pbf, bb, 23 lines */ 3495 0x02b50117, /* pbf, k2, 23 lines */ 3496 0x00000000, 3497 0x02cc0006, /* rdif, bb, 6 lines */ 3498 0x02cc0006, /* rdif, k2, 6 lines */ 3499 0x00000000, 3500 0x02d20006, /* tdif, bb, 6 lines */ 3501 0x02d20006, /* tdif, k2, 6 lines */ 3502 0x00000000, 3503 0x02d80003, /* cdu, bb, 3 lines */ 3504 0x02db000e, /* cdu, k2, 14 lines */ 3505 0x00000000, 3506 0x02e9010d, /* ccfc, bb, 13 lines */ 3507 0x02f60117, /* ccfc, k2, 23 lines */ 3508 0x00000000, 3509 0x02e9010d, /* tcfc, bb, 13 lines */ 3510 0x02f60117, /* tcfc, k2, 23 lines */ 3511 0x00000000, 3512 0x030d0133, /* igu, bb, 51 lines */ 3513 0x030d0133, /* igu, k2, 51 lines */ 3514 0x00000000, 3515 0x03400106, /* cau, bb, 6 lines */ 3516 0x03400106, /* cau, k2, 6 lines */ 3517 0x00000000, 3518 0x00000000, /* rgfs, bb, 0 lines */ 3519 0x00000000, /* rgfs, k2, 0 lines */ 3520 0x00000000, 3521 0x00000000, /* rgsrc, bb, 0 lines */ 3522 0x00000000, /* rgsrc, k2, 0 lines */ 3523 0x00000000, 3524 0x00000000, /* tgfs, bb, 0 lines */ 3525 0x00000000, /* tgfs, k2, 0 lines */ 3526 0x00000000, 3527 0x00000000, /* tgsrc, bb, 0 lines */ 3528 0x00000000, /* tgsrc, k2, 0 lines */ 3529 0x00000000, 3530 0x00000000, /* umac, bb, 0 lines */ 3531 0x00120006, /* umac, k2, 6 lines */ 3532 0x00000000, 3533 0x00000000, /* xmac, bb, 0 lines */ 3534 0x00000000, /* xmac, k2, 0 lines */ 3535 0x00000000, 3536 0x00000000, /* dbg, bb, 0 lines */ 3537 0x00000000, /* dbg, k2, 0 lines */ 3538 0x00000000, 3539 0x0346012b, /* nig, bb, 43 lines */ 3540 0x0346011d, /* nig, k2, 29 lines */ 3541 0x00000000, 3542 0x00000000, /* wol, bb, 0 lines */ 3543 0x001c0002, /* wol, k2, 2 lines */ 3544 0x00000000, 3545 0x00000000, /* bmbn, bb, 0 lines */ 3546 0x00210008, /* bmbn, k2, 8 lines */ 3547 0x00000000, 3548 0x00000000, /* ipc, bb, 0 lines */ 3549 0x00000000, /* ipc, k2, 0 lines */ 3550 0x00000000, 3551 0x00000000, /* nwm, bb, 0 lines */ 3552 0x0371000b, /* nwm, k2, 11 lines */ 3553 0x00000000, 3554 0x00000000, /* nws, bb, 0 lines */ 3555 0x037c0009, /* nws, k2, 9 lines */ 3556 0x00000000, 3557 0x00000000, /* ms, bb, 0 lines */ 3558 0x00120004, /* ms, k2, 4 lines */ 3559 0x00000000, 3560 0x00000000, /* phy_pcie, bb, 0 lines */ 3561 0x00e5001a, /* phy_pcie, k2, 26 lines */ 3562 0x00000000, 3563 0x00000000, /* led, bb, 0 lines */ 3564 0x00000000, /* led, k2, 0 lines */ 3565 0x00000000, 3566 0x00000000, /* avs_wrap, bb, 0 lines */ 3567 0x00000000, /* avs_wrap, k2, 0 lines */ 3568 0x00000000, 3569 0x00000000, /* bar0_map, bb, 0 lines */ 3570 0x00000000, /* bar0_map, k2, 0 lines */ 3571 0x00000000, 3572 }; 3573 3574 /* Win 2 */ 3575 #define GTT_BAR0_MAP_REG_IGU_CMD 0x00f000UL 3576 3577 /* Win 3 */ 3578 #define GTT_BAR0_MAP_REG_TSDM_RAM 0x010000UL 3579 3580 /* Win 4 */ 3581 #define GTT_BAR0_MAP_REG_MSDM_RAM 0x011000UL 3582 3583 /* Win 5 */ 3584 #define GTT_BAR0_MAP_REG_MSDM_RAM_1024 0x012000UL 3585 3586 /* Win 6 */ 3587 #define GTT_BAR0_MAP_REG_USDM_RAM 0x013000UL 3588 3589 /* Win 7 */ 3590 #define GTT_BAR0_MAP_REG_USDM_RAM_1024 0x014000UL 3591 3592 /* Win 8 */ 3593 #define GTT_BAR0_MAP_REG_USDM_RAM_2048 0x015000UL 3594 3595 /* Win 9 */ 3596 #define GTT_BAR0_MAP_REG_XSDM_RAM 0x016000UL 3597 3598 /* Win 10 */ 3599 #define GTT_BAR0_MAP_REG_YSDM_RAM 0x017000UL 3600 3601 /* Win 11 */ 3602 #define GTT_BAR0_MAP_REG_PSDM_RAM 0x018000UL 3603 3604 /** 3605 * @brief qed_qm_pf_mem_size - prepare QM ILT sizes 3606 * 3607 * Returns the required host memory size in 4KB units. 3608 * Must be called before all QM init HSI functions. 3609 * 3610 * @param pf_id - physical function ID 3611 * @param num_pf_cids - number of connections used by this PF 3612 * @param num_vf_cids - number of connections used by VFs of this PF 3613 * @param num_tids - number of tasks used by this PF 3614 * @param num_pf_pqs - number of PQs used by this PF 3615 * @param num_vf_pqs - number of PQs used by VFs of this PF 3616 * 3617 * @return The required host memory size in 4KB units. 3618 */ 3619 u32 qed_qm_pf_mem_size(u8 pf_id, 3620 u32 num_pf_cids, 3621 u32 num_vf_cids, 3622 u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs); 3623 3624 struct qed_qm_common_rt_init_params { 3625 u8 max_ports_per_engine; 3626 u8 max_phys_tcs_per_port; 3627 bool pf_rl_en; 3628 bool pf_wfq_en; 3629 bool vport_rl_en; 3630 bool vport_wfq_en; 3631 struct init_qm_port_params *port_params; 3632 }; 3633 3634 int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn, 3635 struct qed_qm_common_rt_init_params *p_params); 3636 3637 struct qed_qm_pf_rt_init_params { 3638 u8 port_id; 3639 u8 pf_id; 3640 u8 max_phys_tcs_per_port; 3641 bool is_first_pf; 3642 u32 num_pf_cids; 3643 u32 num_vf_cids; 3644 u32 num_tids; 3645 u16 start_pq; 3646 u16 num_pf_pqs; 3647 u16 num_vf_pqs; 3648 u8 start_vport; 3649 u8 num_vports; 3650 u16 pf_wfq; 3651 u32 pf_rl; 3652 struct init_qm_pq_params *pq_params; 3653 struct init_qm_vport_params *vport_params; 3654 }; 3655 3656 int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn, 3657 struct qed_ptt *p_ptt, 3658 struct qed_qm_pf_rt_init_params *p_params); 3659 3660 /** 3661 * @brief qed_init_pf_wfq - Initializes the WFQ weight of the specified PF 3662 * 3663 * @param p_hwfn 3664 * @param p_ptt - ptt window used for writing the registers 3665 * @param pf_id - PF ID 3666 * @param pf_wfq - WFQ weight. Must be non-zero. 3667 * 3668 * @return 0 on success, -1 on error. 3669 */ 3670 int qed_init_pf_wfq(struct qed_hwfn *p_hwfn, 3671 struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq); 3672 3673 /** 3674 * @brief qed_init_pf_rl - Initializes the rate limit of the specified PF 3675 * 3676 * @param p_hwfn 3677 * @param p_ptt - ptt window used for writing the registers 3678 * @param pf_id - PF ID 3679 * @param pf_rl - rate limit in Mb/sec units 3680 * 3681 * @return 0 on success, -1 on error. 3682 */ 3683 int qed_init_pf_rl(struct qed_hwfn *p_hwfn, 3684 struct qed_ptt *p_ptt, u8 pf_id, u32 pf_rl); 3685 3686 /** 3687 * @brief qed_init_vport_wfq Initializes the WFQ weight of the specified VPORT 3688 * 3689 * @param p_hwfn 3690 * @param p_ptt - ptt window used for writing the registers 3691 * @param first_tx_pq_id- An array containing the first Tx PQ ID associated 3692 * with the VPORT for each TC. This array is filled by 3693 * qed_qm_pf_rt_init 3694 * @param vport_wfq - WFQ weight. Must be non-zero. 3695 * 3696 * @return 0 on success, -1 on error. 3697 */ 3698 int qed_init_vport_wfq(struct qed_hwfn *p_hwfn, 3699 struct qed_ptt *p_ptt, 3700 u16 first_tx_pq_id[NUM_OF_TCS], u16 vport_wfq); 3701 3702 /** 3703 * @brief qed_init_vport_rl - Initializes the rate limit of the specified VPORT 3704 * 3705 * @param p_hwfn 3706 * @param p_ptt - ptt window used for writing the registers 3707 * @param vport_id - VPORT ID 3708 * @param vport_rl - rate limit in Mb/sec units 3709 * 3710 * @return 0 on success, -1 on error. 3711 */ 3712 int qed_init_vport_rl(struct qed_hwfn *p_hwfn, 3713 struct qed_ptt *p_ptt, u8 vport_id, u32 vport_rl); 3714 /** 3715 * @brief qed_send_qm_stop_cmd Sends a stop command to the QM 3716 * 3717 * @param p_hwfn 3718 * @param p_ptt 3719 * @param is_release_cmd - true for release, false for stop. 3720 * @param is_tx_pq - true for Tx PQs, false for Other PQs. 3721 * @param start_pq - first PQ ID to stop 3722 * @param num_pqs - Number of PQs to stop, starting from start_pq. 3723 * 3724 * @return bool, true if successful, false if timeout occured while waiting for QM command done. 3725 */ 3726 bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn, 3727 struct qed_ptt *p_ptt, 3728 bool is_release_cmd, 3729 bool is_tx_pq, u16 start_pq, u16 num_pqs); 3730 3731 /** 3732 * @brief qed_set_vxlan_dest_port - initializes vxlan tunnel destination udp port 3733 * 3734 * @param p_ptt - ptt window used for writing the registers. 3735 * @param dest_port - vxlan destination udp port. 3736 */ 3737 void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn, 3738 struct qed_ptt *p_ptt, u16 dest_port); 3739 3740 /** 3741 * @brief qed_set_vxlan_enable - enable or disable VXLAN tunnel in HW 3742 * 3743 * @param p_ptt - ptt window used for writing the registers. 3744 * @param vxlan_enable - vxlan enable flag. 3745 */ 3746 void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn, 3747 struct qed_ptt *p_ptt, bool vxlan_enable); 3748 3749 /** 3750 * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW 3751 * 3752 * @param p_ptt - ptt window used for writing the registers. 3753 * @param eth_gre_enable - eth GRE enable enable flag. 3754 * @param ip_gre_enable - IP GRE enable enable flag. 3755 */ 3756 void qed_set_gre_enable(struct qed_hwfn *p_hwfn, 3757 struct qed_ptt *p_ptt, 3758 bool eth_gre_enable, bool ip_gre_enable); 3759 3760 /** 3761 * @brief qed_set_geneve_dest_port - initializes geneve tunnel destination udp port 3762 * 3763 * @param p_ptt - ptt window used for writing the registers. 3764 * @param dest_port - geneve destination udp port. 3765 */ 3766 void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn, 3767 struct qed_ptt *p_ptt, u16 dest_port); 3768 3769 /** 3770 * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW 3771 * 3772 * @param p_ptt - ptt window used for writing the registers. 3773 * @param eth_geneve_enable - eth GENEVE enable enable flag. 3774 * @param ip_geneve_enable - IP GENEVE enable enable flag. 3775 */ 3776 void qed_set_geneve_enable(struct qed_hwfn *p_hwfn, 3777 struct qed_ptt *p_ptt, 3778 bool eth_geneve_enable, bool ip_geneve_enable); 3779 void qed_set_rfs_mode_disable(struct qed_hwfn *p_hwfn, 3780 struct qed_ptt *p_ptt, u16 pf_id); 3781 void qed_set_rfs_mode_enable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 3782 u16 pf_id, bool tcp, bool udp, 3783 bool ipv4, bool ipv6); 3784 3785 #define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base) 3786 #define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size) 3787 #define TSTORM_PORT_STAT_OFFSET(port_id) \ 3788 (IRO[1].base + ((port_id) * IRO[1].m1)) 3789 #define TSTORM_PORT_STAT_SIZE (IRO[1].size) 3790 #define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \ 3791 (IRO[2].base + ((port_id) * IRO[2].m1)) 3792 #define TSTORM_LL2_PORT_STAT_SIZE (IRO[2].size) 3793 #define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \ 3794 (IRO[3].base + ((vf_id) * IRO[3].m1)) 3795 #define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size) 3796 #define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) \ 3797 (IRO[4].base + (pf_id) * IRO[4].m1) 3798 #define USTORM_FLR_FINAL_ACK_SIZE (IRO[4].size) 3799 #define USTORM_EQE_CONS_OFFSET(pf_id) \ 3800 (IRO[5].base + ((pf_id) * IRO[5].m1)) 3801 #define USTORM_EQE_CONS_SIZE (IRO[5].size) 3802 #define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) \ 3803 (IRO[6].base + ((queue_zone_id) * IRO[6].m1)) 3804 #define USTORM_ETH_QUEUE_ZONE_SIZE (IRO[6].size) 3805 #define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) \ 3806 (IRO[7].base + ((queue_zone_id) * IRO[7].m1)) 3807 #define USTORM_COMMON_QUEUE_CONS_SIZE (IRO[7].size) 3808 #define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \ 3809 (IRO[14].base + ((core_rx_queue_id) * IRO[14].m1)) 3810 #define TSTORM_LL2_RX_PRODS_SIZE (IRO[14].size) 3811 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \ 3812 (IRO[15].base + ((core_rx_queue_id) * IRO[15].m1)) 3813 #define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE (IRO[15].size) 3814 #define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \ 3815 (IRO[16].base + ((core_rx_queue_id) * IRO[16].m1)) 3816 #define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE (IRO[16].size) 3817 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \ 3818 (IRO[17].base + ((core_tx_stats_id) * IRO[17].m1)) 3819 #define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE (IRO[17]. size) 3820 #define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \ 3821 (IRO[18].base + ((stat_counter_id) * IRO[18].m1)) 3822 #define MSTORM_QUEUE_STAT_SIZE (IRO[18].size) 3823 #define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) \ 3824 (IRO[19].base + ((queue_id) * IRO[19].m1)) 3825 #define MSTORM_ETH_PF_PRODS_SIZE (IRO[19].size) 3826 #define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \ 3827 (IRO[20].base + ((vf_id) * IRO[20].m1) + ((vf_queue_id) * IRO[20].m2)) 3828 #define MSTORM_ETH_VF_PRODS_SIZE (IRO[20].size) 3829 #define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[21].base) 3830 #define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[21].size) 3831 #define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \ 3832 (IRO[22].base + ((pf_id) * IRO[22].m1)) 3833 #define MSTORM_ETH_PF_STAT_SIZE (IRO[22].size) 3834 #define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \ 3835 (IRO[23].base + ((stat_counter_id) * IRO[23].m1)) 3836 #define USTORM_QUEUE_STAT_SIZE (IRO[23].size) 3837 #define USTORM_ETH_PF_STAT_OFFSET(pf_id) \ 3838 (IRO[24].base + ((pf_id) * IRO[24].m1)) 3839 #define USTORM_ETH_PF_STAT_SIZE (IRO[24].size) 3840 #define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \ 3841 (IRO[25].base + ((stat_counter_id) * IRO[25].m1)) 3842 #define PSTORM_QUEUE_STAT_SIZE (IRO[25].size) 3843 #define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \ 3844 (IRO[26].base + ((pf_id) * IRO[26].m1)) 3845 #define PSTORM_ETH_PF_STAT_SIZE (IRO[26].size) 3846 #define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(ethtype) \ 3847 (IRO[27].base + ((ethtype) * IRO[27].m1)) 3848 #define PSTORM_CTL_FRAME_ETHTYPE_SIZE (IRO[27].size) 3849 #define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[28].base) 3850 #define TSTORM_ETH_PRS_INPUT_SIZE (IRO[28].size) 3851 #define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \ 3852 (IRO[29].base + ((pf_id) * IRO[29].m1)) 3853 #define ETH_RX_RATE_LIMIT_SIZE (IRO[29].size) 3854 #define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \ 3855 (IRO[30].base + ((queue_id) * IRO[30].m1)) 3856 #define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[30].size) 3857 #define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \ 3858 (IRO[34].base + ((cmdq_queue_id) * IRO[34].m1)) 3859 #define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[34].size) 3860 #define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \ 3861 (IRO[35].base + ((func_id) * IRO[35].m1) + ((bdq_id) * IRO[35].m2)) 3862 #define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[35].size) 3863 #define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(func_id, bdq_id) \ 3864 (IRO[36].base + ((func_id) * IRO[36].m1) + ((bdq_id) * IRO[36].m2)) 3865 #define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[36].size) 3866 #define TSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \ 3867 (IRO[37].base + ((pf_id) * IRO[37].m1)) 3868 #define TSTORM_ISCSI_RX_STATS_SIZE (IRO[37].size) 3869 #define MSTORM_ISCSI_RX_STATS_OFFSET(pf_id) \ 3870 (IRO[38].base + ((pf_id) * IRO[38].m1)) 3871 #define MSTORM_ISCSI_RX_STATS_SIZE (IRO[38].size) 3872 #define USTORM_ISCSI_RX_STATS_OFFSET(pf_id) \ 3873 (IRO[39].base + ((pf_id) * IRO[39].m1)) 3874 #define USTORM_ISCSI_RX_STATS_SIZE (IRO[39].size) 3875 #define XSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \ 3876 (IRO[40].base + ((pf_id) * IRO[40].m1)) 3877 #define XSTORM_ISCSI_TX_STATS_SIZE (IRO[40].size) 3878 #define YSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \ 3879 (IRO[41].base + ((pf_id) * IRO[41].m1)) 3880 #define YSTORM_ISCSI_TX_STATS_SIZE (IRO[41].size) 3881 #define PSTORM_ISCSI_TX_STATS_OFFSET(pf_id) \ 3882 (IRO[42].base + ((pf_id) * IRO[42].m1)) 3883 #define PSTORM_ISCSI_TX_STATS_SIZE (IRO[42].size) 3884 #define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \ 3885 (IRO[45].base + ((rdma_stat_counter_id) * IRO[45].m1)) 3886 #define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[45].size) 3887 #define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \ 3888 (IRO[46].base + ((rdma_stat_counter_id) * IRO[46].m1)) 3889 #define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[46].size) 3890 #define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \ 3891 (IRO[43].base + ((pf_id) * IRO[43].m1)) 3892 #define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \ 3893 (IRO[44].base + ((pf_id) * IRO[44].m1)) 3894 3895 static const struct iro iro_arr[49] = { 3896 {0x0, 0x0, 0x0, 0x0, 0x8}, 3897 {0x4cb0, 0x80, 0x0, 0x0, 0x80}, 3898 {0x6518, 0x20, 0x0, 0x0, 0x20}, 3899 {0xb00, 0x8, 0x0, 0x0, 0x4}, 3900 {0xa80, 0x8, 0x0, 0x0, 0x4}, 3901 {0x0, 0x8, 0x0, 0x0, 0x2}, 3902 {0x80, 0x8, 0x0, 0x0, 0x4}, 3903 {0x84, 0x8, 0x0, 0x0, 0x2}, 3904 {0x4c40, 0x0, 0x0, 0x0, 0x78}, 3905 {0x3df0, 0x0, 0x0, 0x0, 0x78}, 3906 {0x29b0, 0x0, 0x0, 0x0, 0x78}, 3907 {0x4c38, 0x0, 0x0, 0x0, 0x78}, 3908 {0x4990, 0x0, 0x0, 0x0, 0x78}, 3909 {0x7f48, 0x0, 0x0, 0x0, 0x78}, 3910 {0xa28, 0x8, 0x0, 0x0, 0x8}, 3911 {0x61f8, 0x10, 0x0, 0x0, 0x10}, 3912 {0xbd20, 0x30, 0x0, 0x0, 0x30}, 3913 {0x95b8, 0x30, 0x0, 0x0, 0x30}, 3914 {0x4b60, 0x80, 0x0, 0x0, 0x40}, 3915 {0x1f8, 0x4, 0x0, 0x0, 0x4}, 3916 {0x53a0, 0x80, 0x4, 0x0, 0x4}, 3917 {0xc7c8, 0x0, 0x0, 0x0, 0x4}, 3918 {0x4ba0, 0x80, 0x0, 0x0, 0x20}, 3919 {0x8150, 0x40, 0x0, 0x0, 0x30}, 3920 {0xec70, 0x60, 0x0, 0x0, 0x60}, 3921 {0x2b48, 0x80, 0x0, 0x0, 0x38}, 3922 {0xf1b0, 0x78, 0x0, 0x0, 0x78}, 3923 {0x1f8, 0x4, 0x0, 0x0, 0x4}, 3924 {0xaef8, 0x0, 0x0, 0x0, 0xf0}, 3925 {0xafe8, 0x8, 0x0, 0x0, 0x8}, 3926 {0x1f8, 0x8, 0x0, 0x0, 0x8}, 3927 {0xac0, 0x8, 0x0, 0x0, 0x8}, 3928 {0x2578, 0x8, 0x0, 0x0, 0x8}, 3929 {0x24f8, 0x8, 0x0, 0x0, 0x8}, 3930 {0x0, 0x8, 0x0, 0x0, 0x8}, 3931 {0x200, 0x10, 0x8, 0x0, 0x8}, 3932 {0xb78, 0x10, 0x8, 0x0, 0x2}, 3933 {0xd9a8, 0x38, 0x0, 0x0, 0x24}, 3934 {0x12988, 0x10, 0x0, 0x0, 0x8}, 3935 {0x11fa0, 0x38, 0x0, 0x0, 0x18}, 3936 {0xa580, 0x38, 0x0, 0x0, 0x10}, 3937 {0x86f8, 0x30, 0x0, 0x0, 0x18}, 3938 {0x101f8, 0x10, 0x0, 0x0, 0x10}, 3939 {0xde28, 0x48, 0x0, 0x0, 0x38}, 3940 {0x10660, 0x20, 0x0, 0x0, 0x20}, 3941 {0x2b80, 0x80, 0x0, 0x0, 0x10}, 3942 {0x5020, 0x10, 0x0, 0x0, 0x10}, 3943 {0xc9b0, 0x30, 0x0, 0x0, 0x10}, 3944 {0xeec0, 0x10, 0x0, 0x0, 0x10}, 3945 }; 3946 3947 /* Runtime array offsets */ 3948 #define DORQ_REG_PF_MAX_ICID_0_RT_OFFSET 0 3949 #define DORQ_REG_PF_MAX_ICID_1_RT_OFFSET 1 3950 #define DORQ_REG_PF_MAX_ICID_2_RT_OFFSET 2 3951 #define DORQ_REG_PF_MAX_ICID_3_RT_OFFSET 3 3952 #define DORQ_REG_PF_MAX_ICID_4_RT_OFFSET 4 3953 #define DORQ_REG_PF_MAX_ICID_5_RT_OFFSET 5 3954 #define DORQ_REG_PF_MAX_ICID_6_RT_OFFSET 6 3955 #define DORQ_REG_PF_MAX_ICID_7_RT_OFFSET 7 3956 #define DORQ_REG_VF_MAX_ICID_0_RT_OFFSET 8 3957 #define DORQ_REG_VF_MAX_ICID_1_RT_OFFSET 9 3958 #define DORQ_REG_VF_MAX_ICID_2_RT_OFFSET 10 3959 #define DORQ_REG_VF_MAX_ICID_3_RT_OFFSET 11 3960 #define DORQ_REG_VF_MAX_ICID_4_RT_OFFSET 12 3961 #define DORQ_REG_VF_MAX_ICID_5_RT_OFFSET 13 3962 #define DORQ_REG_VF_MAX_ICID_6_RT_OFFSET 14 3963 #define DORQ_REG_VF_MAX_ICID_7_RT_OFFSET 15 3964 #define DORQ_REG_PF_WAKE_ALL_RT_OFFSET 16 3965 #define DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET 17 3966 #define IGU_REG_PF_CONFIGURATION_RT_OFFSET 18 3967 #define IGU_REG_VF_CONFIGURATION_RT_OFFSET 19 3968 #define IGU_REG_ATTN_MSG_ADDR_L_RT_OFFSET 20 3969 #define IGU_REG_ATTN_MSG_ADDR_H_RT_OFFSET 21 3970 #define IGU_REG_LEADING_EDGE_LATCH_RT_OFFSET 22 3971 #define IGU_REG_TRAILING_EDGE_LATCH_RT_OFFSET 23 3972 #define CAU_REG_CQE_AGG_UNIT_SIZE_RT_OFFSET 24 3973 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761 3974 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736 3975 #define CAU_REG_SB_VAR_MEMORY_RT_OFFSET 761 3976 #define CAU_REG_SB_VAR_MEMORY_RT_SIZE 736 3977 #define CAU_REG_SB_ADDR_MEMORY_RT_OFFSET 1497 3978 #define CAU_REG_SB_ADDR_MEMORY_RT_SIZE 736 3979 #define CAU_REG_PI_MEMORY_RT_OFFSET 2233 3980 #define CAU_REG_PI_MEMORY_RT_SIZE 4416 3981 #define PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET 6649 3982 #define PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET 6650 3983 #define PRS_REG_TASK_ID_MAX_INITIATOR_VF_RT_OFFSET 6651 3984 #define PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET 6652 3985 #define PRS_REG_TASK_ID_MAX_TARGET_VF_RT_OFFSET 6653 3986 #define PRS_REG_SEARCH_TCP_RT_OFFSET 6654 3987 #define PRS_REG_SEARCH_FCOE_RT_OFFSET 6655 3988 #define PRS_REG_SEARCH_ROCE_RT_OFFSET 6656 3989 #define PRS_REG_ROCE_DEST_QP_MAX_VF_RT_OFFSET 6657 3990 #define PRS_REG_ROCE_DEST_QP_MAX_PF_RT_OFFSET 6658 3991 #define PRS_REG_SEARCH_OPENFLOW_RT_OFFSET 6659 3992 #define PRS_REG_SEARCH_NON_IP_AS_OPENFLOW_RT_OFFSET 6660 3993 #define PRS_REG_OPENFLOW_SUPPORT_ONLY_KNOWN_OVER_IP_RT_OFFSET 6661 3994 #define PRS_REG_OPENFLOW_SEARCH_KEY_MASK_RT_OFFSET 6662 3995 #define PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET 6663 3996 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN_RT_OFFSET 6664 3997 #define SRC_REG_FIRSTFREE_RT_OFFSET 6665 3998 #define SRC_REG_FIRSTFREE_RT_SIZE 2 3999 #define SRC_REG_LASTFREE_RT_OFFSET 6667 4000 #define SRC_REG_LASTFREE_RT_SIZE 2 4001 #define SRC_REG_COUNTFREE_RT_OFFSET 6669 4002 #define SRC_REG_NUMBER_HASH_BITS_RT_OFFSET 6670 4003 #define PSWRQ2_REG_CDUT_P_SIZE_RT_OFFSET 6671 4004 #define PSWRQ2_REG_CDUC_P_SIZE_RT_OFFSET 6672 4005 #define PSWRQ2_REG_TM_P_SIZE_RT_OFFSET 6673 4006 #define PSWRQ2_REG_QM_P_SIZE_RT_OFFSET 6674 4007 #define PSWRQ2_REG_SRC_P_SIZE_RT_OFFSET 6675 4008 #define PSWRQ2_REG_TSDM_P_SIZE_RT_OFFSET 6676 4009 #define PSWRQ2_REG_TM_FIRST_ILT_RT_OFFSET 6677 4010 #define PSWRQ2_REG_TM_LAST_ILT_RT_OFFSET 6678 4011 #define PSWRQ2_REG_QM_FIRST_ILT_RT_OFFSET 6679 4012 #define PSWRQ2_REG_QM_LAST_ILT_RT_OFFSET 6680 4013 #define PSWRQ2_REG_SRC_FIRST_ILT_RT_OFFSET 6681 4014 #define PSWRQ2_REG_SRC_LAST_ILT_RT_OFFSET 6682 4015 #define PSWRQ2_REG_CDUC_FIRST_ILT_RT_OFFSET 6683 4016 #define PSWRQ2_REG_CDUC_LAST_ILT_RT_OFFSET 6684 4017 #define PSWRQ2_REG_CDUT_FIRST_ILT_RT_OFFSET 6685 4018 #define PSWRQ2_REG_CDUT_LAST_ILT_RT_OFFSET 6686 4019 #define PSWRQ2_REG_TSDM_FIRST_ILT_RT_OFFSET 6687 4020 #define PSWRQ2_REG_TSDM_LAST_ILT_RT_OFFSET 6688 4021 #define PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6689 4022 #define PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6690 4023 #define PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET 6691 4024 #define PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET 6692 4025 #define PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET 6693 4026 #define PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET 6694 4027 #define PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET 6695 4028 #define PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET 6696 4029 #define PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET 6697 4030 #define PSWRQ2_REG_VF_BASE_RT_OFFSET 6698 4031 #define PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET 6699 4032 #define PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET 6700 4033 #define PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET 6701 4034 #define PSWRQ2_REG_ILT_MEMORY_RT_OFFSET 6702 4035 #define PSWRQ2_REG_ILT_MEMORY_RT_SIZE 22000 4036 #define PGLUE_REG_B_VF_BASE_RT_OFFSET 28702 4037 #define PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET 28703 4038 #define PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET 28704 4039 #define PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET 28705 4040 #define PGLUE_REG_B_PF_BAR0_SIZE_RT_OFFSET 28706 4041 #define PGLUE_REG_B_PF_BAR1_SIZE_RT_OFFSET 28707 4042 #define PGLUE_REG_B_VF_BAR1_SIZE_RT_OFFSET 28708 4043 #define TM_REG_VF_ENABLE_CONN_RT_OFFSET 28709 4044 #define TM_REG_PF_ENABLE_CONN_RT_OFFSET 28710 4045 #define TM_REG_PF_ENABLE_TASK_RT_OFFSET 28711 4046 #define TM_REG_GROUP_SIZE_RESOLUTION_CONN_RT_OFFSET 28712 4047 #define TM_REG_GROUP_SIZE_RESOLUTION_TASK_RT_OFFSET 28713 4048 #define TM_REG_CONFIG_CONN_MEM_RT_OFFSET 28714 4049 #define TM_REG_CONFIG_CONN_MEM_RT_SIZE 416 4050 #define TM_REG_CONFIG_TASK_MEM_RT_OFFSET 29130 4051 #define TM_REG_CONFIG_TASK_MEM_RT_SIZE 608 4052 #define QM_REG_MAXPQSIZE_0_RT_OFFSET 29738 4053 #define QM_REG_MAXPQSIZE_1_RT_OFFSET 29739 4054 #define QM_REG_MAXPQSIZE_2_RT_OFFSET 29740 4055 #define QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET 29741 4056 #define QM_REG_MAXPQSIZETXSEL_1_RT_OFFSET 29742 4057 #define QM_REG_MAXPQSIZETXSEL_2_RT_OFFSET 29743 4058 #define QM_REG_MAXPQSIZETXSEL_3_RT_OFFSET 29744 4059 #define QM_REG_MAXPQSIZETXSEL_4_RT_OFFSET 29745 4060 #define QM_REG_MAXPQSIZETXSEL_5_RT_OFFSET 29746 4061 #define QM_REG_MAXPQSIZETXSEL_6_RT_OFFSET 29747 4062 #define QM_REG_MAXPQSIZETXSEL_7_RT_OFFSET 29748 4063 #define QM_REG_MAXPQSIZETXSEL_8_RT_OFFSET 29749 4064 #define QM_REG_MAXPQSIZETXSEL_9_RT_OFFSET 29750 4065 #define QM_REG_MAXPQSIZETXSEL_10_RT_OFFSET 29751 4066 #define QM_REG_MAXPQSIZETXSEL_11_RT_OFFSET 29752 4067 #define QM_REG_MAXPQSIZETXSEL_12_RT_OFFSET 29753 4068 #define QM_REG_MAXPQSIZETXSEL_13_RT_OFFSET 29754 4069 #define QM_REG_MAXPQSIZETXSEL_14_RT_OFFSET 29755 4070 #define QM_REG_MAXPQSIZETXSEL_15_RT_OFFSET 29756 4071 #define QM_REG_MAXPQSIZETXSEL_16_RT_OFFSET 29757 4072 #define QM_REG_MAXPQSIZETXSEL_17_RT_OFFSET 29758 4073 #define QM_REG_MAXPQSIZETXSEL_18_RT_OFFSET 29759 4074 #define QM_REG_MAXPQSIZETXSEL_19_RT_OFFSET 29760 4075 #define QM_REG_MAXPQSIZETXSEL_20_RT_OFFSET 29761 4076 #define QM_REG_MAXPQSIZETXSEL_21_RT_OFFSET 29762 4077 #define QM_REG_MAXPQSIZETXSEL_22_RT_OFFSET 29763 4078 #define QM_REG_MAXPQSIZETXSEL_23_RT_OFFSET 29764 4079 #define QM_REG_MAXPQSIZETXSEL_24_RT_OFFSET 29765 4080 #define QM_REG_MAXPQSIZETXSEL_25_RT_OFFSET 29766 4081 #define QM_REG_MAXPQSIZETXSEL_26_RT_OFFSET 29767 4082 #define QM_REG_MAXPQSIZETXSEL_27_RT_OFFSET 29768 4083 #define QM_REG_MAXPQSIZETXSEL_28_RT_OFFSET 29769 4084 #define QM_REG_MAXPQSIZETXSEL_29_RT_OFFSET 29770 4085 #define QM_REG_MAXPQSIZETXSEL_30_RT_OFFSET 29771 4086 #define QM_REG_MAXPQSIZETXSEL_31_RT_OFFSET 29772 4087 #define QM_REG_MAXPQSIZETXSEL_32_RT_OFFSET 29773 4088 #define QM_REG_MAXPQSIZETXSEL_33_RT_OFFSET 29774 4089 #define QM_REG_MAXPQSIZETXSEL_34_RT_OFFSET 29775 4090 #define QM_REG_MAXPQSIZETXSEL_35_RT_OFFSET 29776 4091 #define QM_REG_MAXPQSIZETXSEL_36_RT_OFFSET 29777 4092 #define QM_REG_MAXPQSIZETXSEL_37_RT_OFFSET 29778 4093 #define QM_REG_MAXPQSIZETXSEL_38_RT_OFFSET 29779 4094 #define QM_REG_MAXPQSIZETXSEL_39_RT_OFFSET 29780 4095 #define QM_REG_MAXPQSIZETXSEL_40_RT_OFFSET 29781 4096 #define QM_REG_MAXPQSIZETXSEL_41_RT_OFFSET 29782 4097 #define QM_REG_MAXPQSIZETXSEL_42_RT_OFFSET 29783 4098 #define QM_REG_MAXPQSIZETXSEL_43_RT_OFFSET 29784 4099 #define QM_REG_MAXPQSIZETXSEL_44_RT_OFFSET 29785 4100 #define QM_REG_MAXPQSIZETXSEL_45_RT_OFFSET 29786 4101 #define QM_REG_MAXPQSIZETXSEL_46_RT_OFFSET 29787 4102 #define QM_REG_MAXPQSIZETXSEL_47_RT_OFFSET 29788 4103 #define QM_REG_MAXPQSIZETXSEL_48_RT_OFFSET 29789 4104 #define QM_REG_MAXPQSIZETXSEL_49_RT_OFFSET 29790 4105 #define QM_REG_MAXPQSIZETXSEL_50_RT_OFFSET 29791 4106 #define QM_REG_MAXPQSIZETXSEL_51_RT_OFFSET 29792 4107 #define QM_REG_MAXPQSIZETXSEL_52_RT_OFFSET 29793 4108 #define QM_REG_MAXPQSIZETXSEL_53_RT_OFFSET 29794 4109 #define QM_REG_MAXPQSIZETXSEL_54_RT_OFFSET 29795 4110 #define QM_REG_MAXPQSIZETXSEL_55_RT_OFFSET 29796 4111 #define QM_REG_MAXPQSIZETXSEL_56_RT_OFFSET 29797 4112 #define QM_REG_MAXPQSIZETXSEL_57_RT_OFFSET 29798 4113 #define QM_REG_MAXPQSIZETXSEL_58_RT_OFFSET 29799 4114 #define QM_REG_MAXPQSIZETXSEL_59_RT_OFFSET 29800 4115 #define QM_REG_MAXPQSIZETXSEL_60_RT_OFFSET 29801 4116 #define QM_REG_MAXPQSIZETXSEL_61_RT_OFFSET 29802 4117 #define QM_REG_MAXPQSIZETXSEL_62_RT_OFFSET 29803 4118 #define QM_REG_MAXPQSIZETXSEL_63_RT_OFFSET 29804 4119 #define QM_REG_BASEADDROTHERPQ_RT_OFFSET 29805 4120 #define QM_REG_BASEADDROTHERPQ_RT_SIZE 128 4121 #define QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET 29933 4122 #define QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET 29934 4123 #define QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET 29935 4124 #define QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET 29936 4125 #define QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET 29937 4126 #define QM_REG_WRROTHERPQGRP_0_RT_OFFSET 29938 4127 #define QM_REG_WRROTHERPQGRP_1_RT_OFFSET 29939 4128 #define QM_REG_WRROTHERPQGRP_2_RT_OFFSET 29940 4129 #define QM_REG_WRROTHERPQGRP_3_RT_OFFSET 29941 4130 #define QM_REG_WRROTHERPQGRP_4_RT_OFFSET 29942 4131 #define QM_REG_WRROTHERPQGRP_5_RT_OFFSET 29943 4132 #define QM_REG_WRROTHERPQGRP_6_RT_OFFSET 29944 4133 #define QM_REG_WRROTHERPQGRP_7_RT_OFFSET 29945 4134 #define QM_REG_WRROTHERPQGRP_8_RT_OFFSET 29946 4135 #define QM_REG_WRROTHERPQGRP_9_RT_OFFSET 29947 4136 #define QM_REG_WRROTHERPQGRP_10_RT_OFFSET 29948 4137 #define QM_REG_WRROTHERPQGRP_11_RT_OFFSET 29949 4138 #define QM_REG_WRROTHERPQGRP_12_RT_OFFSET 29950 4139 #define QM_REG_WRROTHERPQGRP_13_RT_OFFSET 29951 4140 #define QM_REG_WRROTHERPQGRP_14_RT_OFFSET 29952 4141 #define QM_REG_WRROTHERPQGRP_15_RT_OFFSET 29953 4142 #define QM_REG_WRROTHERGRPWEIGHT_0_RT_OFFSET 29954 4143 #define QM_REG_WRROTHERGRPWEIGHT_1_RT_OFFSET 29955 4144 #define QM_REG_WRROTHERGRPWEIGHT_2_RT_OFFSET 29956 4145 #define QM_REG_WRROTHERGRPWEIGHT_3_RT_OFFSET 29957 4146 #define QM_REG_WRRTXGRPWEIGHT_0_RT_OFFSET 29958 4147 #define QM_REG_WRRTXGRPWEIGHT_1_RT_OFFSET 29959 4148 #define QM_REG_PQTX2PF_0_RT_OFFSET 29960 4149 #define QM_REG_PQTX2PF_1_RT_OFFSET 29961 4150 #define QM_REG_PQTX2PF_2_RT_OFFSET 29962 4151 #define QM_REG_PQTX2PF_3_RT_OFFSET 29963 4152 #define QM_REG_PQTX2PF_4_RT_OFFSET 29964 4153 #define QM_REG_PQTX2PF_5_RT_OFFSET 29965 4154 #define QM_REG_PQTX2PF_6_RT_OFFSET 29966 4155 #define QM_REG_PQTX2PF_7_RT_OFFSET 29967 4156 #define QM_REG_PQTX2PF_8_RT_OFFSET 29968 4157 #define QM_REG_PQTX2PF_9_RT_OFFSET 29969 4158 #define QM_REG_PQTX2PF_10_RT_OFFSET 29970 4159 #define QM_REG_PQTX2PF_11_RT_OFFSET 29971 4160 #define QM_REG_PQTX2PF_12_RT_OFFSET 29972 4161 #define QM_REG_PQTX2PF_13_RT_OFFSET 29973 4162 #define QM_REG_PQTX2PF_14_RT_OFFSET 29974 4163 #define QM_REG_PQTX2PF_15_RT_OFFSET 29975 4164 #define QM_REG_PQTX2PF_16_RT_OFFSET 29976 4165 #define QM_REG_PQTX2PF_17_RT_OFFSET 29977 4166 #define QM_REG_PQTX2PF_18_RT_OFFSET 29978 4167 #define QM_REG_PQTX2PF_19_RT_OFFSET 29979 4168 #define QM_REG_PQTX2PF_20_RT_OFFSET 29980 4169 #define QM_REG_PQTX2PF_21_RT_OFFSET 29981 4170 #define QM_REG_PQTX2PF_22_RT_OFFSET 29982 4171 #define QM_REG_PQTX2PF_23_RT_OFFSET 29983 4172 #define QM_REG_PQTX2PF_24_RT_OFFSET 29984 4173 #define QM_REG_PQTX2PF_25_RT_OFFSET 29985 4174 #define QM_REG_PQTX2PF_26_RT_OFFSET 29986 4175 #define QM_REG_PQTX2PF_27_RT_OFFSET 29987 4176 #define QM_REG_PQTX2PF_28_RT_OFFSET 29988 4177 #define QM_REG_PQTX2PF_29_RT_OFFSET 29989 4178 #define QM_REG_PQTX2PF_30_RT_OFFSET 29990 4179 #define QM_REG_PQTX2PF_31_RT_OFFSET 29991 4180 #define QM_REG_PQTX2PF_32_RT_OFFSET 29992 4181 #define QM_REG_PQTX2PF_33_RT_OFFSET 29993 4182 #define QM_REG_PQTX2PF_34_RT_OFFSET 29994 4183 #define QM_REG_PQTX2PF_35_RT_OFFSET 29995 4184 #define QM_REG_PQTX2PF_36_RT_OFFSET 29996 4185 #define QM_REG_PQTX2PF_37_RT_OFFSET 29997 4186 #define QM_REG_PQTX2PF_38_RT_OFFSET 29998 4187 #define QM_REG_PQTX2PF_39_RT_OFFSET 29999 4188 #define QM_REG_PQTX2PF_40_RT_OFFSET 30000 4189 #define QM_REG_PQTX2PF_41_RT_OFFSET 30001 4190 #define QM_REG_PQTX2PF_42_RT_OFFSET 30002 4191 #define QM_REG_PQTX2PF_43_RT_OFFSET 30003 4192 #define QM_REG_PQTX2PF_44_RT_OFFSET 30004 4193 #define QM_REG_PQTX2PF_45_RT_OFFSET 30005 4194 #define QM_REG_PQTX2PF_46_RT_OFFSET 30006 4195 #define QM_REG_PQTX2PF_47_RT_OFFSET 30007 4196 #define QM_REG_PQTX2PF_48_RT_OFFSET 30008 4197 #define QM_REG_PQTX2PF_49_RT_OFFSET 30009 4198 #define QM_REG_PQTX2PF_50_RT_OFFSET 30010 4199 #define QM_REG_PQTX2PF_51_RT_OFFSET 30011 4200 #define QM_REG_PQTX2PF_52_RT_OFFSET 30012 4201 #define QM_REG_PQTX2PF_53_RT_OFFSET 30013 4202 #define QM_REG_PQTX2PF_54_RT_OFFSET 30014 4203 #define QM_REG_PQTX2PF_55_RT_OFFSET 30015 4204 #define QM_REG_PQTX2PF_56_RT_OFFSET 30016 4205 #define QM_REG_PQTX2PF_57_RT_OFFSET 30017 4206 #define QM_REG_PQTX2PF_58_RT_OFFSET 30018 4207 #define QM_REG_PQTX2PF_59_RT_OFFSET 30019 4208 #define QM_REG_PQTX2PF_60_RT_OFFSET 30020 4209 #define QM_REG_PQTX2PF_61_RT_OFFSET 30021 4210 #define QM_REG_PQTX2PF_62_RT_OFFSET 30022 4211 #define QM_REG_PQTX2PF_63_RT_OFFSET 30023 4212 #define QM_REG_PQOTHER2PF_0_RT_OFFSET 30024 4213 #define QM_REG_PQOTHER2PF_1_RT_OFFSET 30025 4214 #define QM_REG_PQOTHER2PF_2_RT_OFFSET 30026 4215 #define QM_REG_PQOTHER2PF_3_RT_OFFSET 30027 4216 #define QM_REG_PQOTHER2PF_4_RT_OFFSET 30028 4217 #define QM_REG_PQOTHER2PF_5_RT_OFFSET 30029 4218 #define QM_REG_PQOTHER2PF_6_RT_OFFSET 30030 4219 #define QM_REG_PQOTHER2PF_7_RT_OFFSET 30031 4220 #define QM_REG_PQOTHER2PF_8_RT_OFFSET 30032 4221 #define QM_REG_PQOTHER2PF_9_RT_OFFSET 30033 4222 #define QM_REG_PQOTHER2PF_10_RT_OFFSET 30034 4223 #define QM_REG_PQOTHER2PF_11_RT_OFFSET 30035 4224 #define QM_REG_PQOTHER2PF_12_RT_OFFSET 30036 4225 #define QM_REG_PQOTHER2PF_13_RT_OFFSET 30037 4226 #define QM_REG_PQOTHER2PF_14_RT_OFFSET 30038 4227 #define QM_REG_PQOTHER2PF_15_RT_OFFSET 30039 4228 #define QM_REG_RLGLBLPERIOD_0_RT_OFFSET 30040 4229 #define QM_REG_RLGLBLPERIOD_1_RT_OFFSET 30041 4230 #define QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET 30042 4231 #define QM_REG_RLGLBLPERIODTIMER_1_RT_OFFSET 30043 4232 #define QM_REG_RLGLBLPERIODSEL_0_RT_OFFSET 30044 4233 #define QM_REG_RLGLBLPERIODSEL_1_RT_OFFSET 30045 4234 #define QM_REG_RLGLBLPERIODSEL_2_RT_OFFSET 30046 4235 #define QM_REG_RLGLBLPERIODSEL_3_RT_OFFSET 30047 4236 #define QM_REG_RLGLBLPERIODSEL_4_RT_OFFSET 30048 4237 #define QM_REG_RLGLBLPERIODSEL_5_RT_OFFSET 30049 4238 #define QM_REG_RLGLBLPERIODSEL_6_RT_OFFSET 30050 4239 #define QM_REG_RLGLBLPERIODSEL_7_RT_OFFSET 30051 4240 #define QM_REG_RLGLBLINCVAL_RT_OFFSET 30052 4241 #define QM_REG_RLGLBLINCVAL_RT_SIZE 256 4242 #define QM_REG_RLGLBLUPPERBOUND_RT_OFFSET 30308 4243 #define QM_REG_RLGLBLUPPERBOUND_RT_SIZE 256 4244 #define QM_REG_RLGLBLCRD_RT_OFFSET 30564 4245 #define QM_REG_RLGLBLCRD_RT_SIZE 256 4246 #define QM_REG_RLGLBLENABLE_RT_OFFSET 30820 4247 #define QM_REG_RLPFPERIOD_RT_OFFSET 30821 4248 #define QM_REG_RLPFPERIODTIMER_RT_OFFSET 30822 4249 #define QM_REG_RLPFINCVAL_RT_OFFSET 30823 4250 #define QM_REG_RLPFINCVAL_RT_SIZE 16 4251 #define QM_REG_RLPFUPPERBOUND_RT_OFFSET 30839 4252 #define QM_REG_RLPFUPPERBOUND_RT_SIZE 16 4253 #define QM_REG_RLPFCRD_RT_OFFSET 30855 4254 #define QM_REG_RLPFCRD_RT_SIZE 16 4255 #define QM_REG_RLPFENABLE_RT_OFFSET 30871 4256 #define QM_REG_RLPFVOQENABLE_RT_OFFSET 30872 4257 #define QM_REG_WFQPFWEIGHT_RT_OFFSET 30873 4258 #define QM_REG_WFQPFWEIGHT_RT_SIZE 16 4259 #define QM_REG_WFQPFUPPERBOUND_RT_OFFSET 30889 4260 #define QM_REG_WFQPFUPPERBOUND_RT_SIZE 16 4261 #define QM_REG_WFQPFCRD_RT_OFFSET 30905 4262 #define QM_REG_WFQPFCRD_RT_SIZE 256 4263 #define QM_REG_WFQPFENABLE_RT_OFFSET 31161 4264 #define QM_REG_WFQVPENABLE_RT_OFFSET 31162 4265 #define QM_REG_BASEADDRTXPQ_RT_OFFSET 31163 4266 #define QM_REG_BASEADDRTXPQ_RT_SIZE 512 4267 #define QM_REG_TXPQMAP_RT_OFFSET 31675 4268 #define QM_REG_TXPQMAP_RT_SIZE 512 4269 #define QM_REG_WFQVPWEIGHT_RT_OFFSET 32187 4270 #define QM_REG_WFQVPWEIGHT_RT_SIZE 512 4271 #define QM_REG_WFQVPCRD_RT_OFFSET 32699 4272 #define QM_REG_WFQVPCRD_RT_SIZE 512 4273 #define QM_REG_WFQVPMAP_RT_OFFSET 33211 4274 #define QM_REG_WFQVPMAP_RT_SIZE 512 4275 #define QM_REG_WFQPFCRD_MSB_RT_OFFSET 33723 4276 #define QM_REG_WFQPFCRD_MSB_RT_SIZE 320 4277 #define QM_REG_VOQCRDLINE_RT_OFFSET 34043 4278 #define QM_REG_VOQCRDLINE_RT_SIZE 36 4279 #define QM_REG_VOQINITCRDLINE_RT_OFFSET 34079 4280 #define QM_REG_VOQINITCRDLINE_RT_SIZE 36 4281 #define NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET 34115 4282 #define NIG_REG_OUTER_TAG_VALUE_LIST0_RT_OFFSET 34116 4283 #define NIG_REG_OUTER_TAG_VALUE_LIST1_RT_OFFSET 34117 4284 #define NIG_REG_OUTER_TAG_VALUE_LIST2_RT_OFFSET 34118 4285 #define NIG_REG_OUTER_TAG_VALUE_LIST3_RT_OFFSET 34119 4286 #define NIG_REG_OUTER_TAG_VALUE_MASK_RT_OFFSET 34120 4287 #define NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET 34121 4288 #define NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET 34122 4289 #define NIG_REG_LLH_FUNC_TAG_EN_RT_SIZE 4 4290 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_OFFSET 34126 4291 #define NIG_REG_LLH_FUNC_TAG_HDR_SEL_RT_SIZE 4 4292 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET 34130 4293 #define NIG_REG_LLH_FUNC_TAG_VALUE_RT_SIZE 4 4294 #define NIG_REG_LLH_FUNC_NO_TAG_RT_OFFSET 34134 4295 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_OFFSET 34135 4296 #define NIG_REG_LLH_FUNC_FILTER_VALUE_RT_SIZE 32 4297 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_OFFSET 34167 4298 #define NIG_REG_LLH_FUNC_FILTER_EN_RT_SIZE 16 4299 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_OFFSET 34183 4300 #define NIG_REG_LLH_FUNC_FILTER_MODE_RT_SIZE 16 4301 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_OFFSET 34199 4302 #define NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE_RT_SIZE 16 4303 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET 34215 4304 #define NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_SIZE 16 4305 #define NIG_REG_TX_EDPM_CTRL_RT_OFFSET 34231 4306 #define NIG_REG_ROCE_DUPLICATE_TO_HOST_RT_OFFSET 34232 4307 #define CDU_REG_CID_ADDR_PARAMS_RT_OFFSET 34233 4308 #define CDU_REG_SEGMENT0_PARAMS_RT_OFFSET 34234 4309 #define CDU_REG_SEGMENT1_PARAMS_RT_OFFSET 34235 4310 #define CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET 34236 4311 #define CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET 34237 4312 #define CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET 34238 4313 #define CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 34239 4314 #define CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET 34240 4315 #define CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET 34241 4316 #define CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET 34242 4317 #define CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 34243 4318 #define CDU_REG_VF_SEG_TYPE_OFFSET_RT_OFFSET 34244 4319 #define CDU_REG_VF_FL_SEG_TYPE_OFFSET_RT_OFFSET 34245 4320 #define PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET 34246 4321 #define PBF_REG_BTB_SHARED_AREA_SIZE_RT_OFFSET 34247 4322 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET 34248 4323 #define PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET 34249 4324 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ0_RT_OFFSET 34250 4325 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET 34251 4326 #define PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET 34252 4327 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ1_RT_OFFSET 34253 4328 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ2_RT_OFFSET 34254 4329 #define PBF_REG_BTB_GUARANTEED_VOQ2_RT_OFFSET 34255 4330 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ2_RT_OFFSET 34256 4331 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ3_RT_OFFSET 34257 4332 #define PBF_REG_BTB_GUARANTEED_VOQ3_RT_OFFSET 34258 4333 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ3_RT_OFFSET 34259 4334 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ4_RT_OFFSET 34260 4335 #define PBF_REG_BTB_GUARANTEED_VOQ4_RT_OFFSET 34261 4336 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ4_RT_OFFSET 34262 4337 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ5_RT_OFFSET 34263 4338 #define PBF_REG_BTB_GUARANTEED_VOQ5_RT_OFFSET 34264 4339 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ5_RT_OFFSET 34265 4340 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ6_RT_OFFSET 34266 4341 #define PBF_REG_BTB_GUARANTEED_VOQ6_RT_OFFSET 34267 4342 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ6_RT_OFFSET 34268 4343 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ7_RT_OFFSET 34269 4344 #define PBF_REG_BTB_GUARANTEED_VOQ7_RT_OFFSET 34270 4345 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ7_RT_OFFSET 34271 4346 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ8_RT_OFFSET 34272 4347 #define PBF_REG_BTB_GUARANTEED_VOQ8_RT_OFFSET 34273 4348 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ8_RT_OFFSET 34274 4349 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ9_RT_OFFSET 34275 4350 #define PBF_REG_BTB_GUARANTEED_VOQ9_RT_OFFSET 34276 4351 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ9_RT_OFFSET 34277 4352 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ10_RT_OFFSET 34278 4353 #define PBF_REG_BTB_GUARANTEED_VOQ10_RT_OFFSET 34279 4354 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ10_RT_OFFSET 34280 4355 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ11_RT_OFFSET 34281 4356 #define PBF_REG_BTB_GUARANTEED_VOQ11_RT_OFFSET 34282 4357 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ11_RT_OFFSET 34283 4358 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ12_RT_OFFSET 34284 4359 #define PBF_REG_BTB_GUARANTEED_VOQ12_RT_OFFSET 34285 4360 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ12_RT_OFFSET 34286 4361 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ13_RT_OFFSET 34287 4362 #define PBF_REG_BTB_GUARANTEED_VOQ13_RT_OFFSET 34288 4363 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ13_RT_OFFSET 34289 4364 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ14_RT_OFFSET 34290 4365 #define PBF_REG_BTB_GUARANTEED_VOQ14_RT_OFFSET 34291 4366 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ14_RT_OFFSET 34292 4367 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ15_RT_OFFSET 34293 4368 #define PBF_REG_BTB_GUARANTEED_VOQ15_RT_OFFSET 34294 4369 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ15_RT_OFFSET 34295 4370 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ16_RT_OFFSET 34296 4371 #define PBF_REG_BTB_GUARANTEED_VOQ16_RT_OFFSET 34297 4372 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ16_RT_OFFSET 34298 4373 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ17_RT_OFFSET 34299 4374 #define PBF_REG_BTB_GUARANTEED_VOQ17_RT_OFFSET 34300 4375 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ17_RT_OFFSET 34301 4376 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ18_RT_OFFSET 34302 4377 #define PBF_REG_BTB_GUARANTEED_VOQ18_RT_OFFSET 34303 4378 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ18_RT_OFFSET 34304 4379 #define PBF_REG_YCMD_QS_NUM_LINES_VOQ19_RT_OFFSET 34305 4380 #define PBF_REG_BTB_GUARANTEED_VOQ19_RT_OFFSET 34306 4381 #define PBF_REG_BTB_SHARED_AREA_SETUP_VOQ19_RT_OFFSET 34307 4382 #define XCM_REG_CON_PHY_Q3_RT_OFFSET 34308 4383 4384 #define RUNTIME_ARRAY_SIZE 34309 4385 4386 /* The eth storm context for the Tstorm */ 4387 struct tstorm_eth_conn_st_ctx { 4388 __le32 reserved[4]; 4389 }; 4390 4391 /* The eth storm context for the Pstorm */ 4392 struct pstorm_eth_conn_st_ctx { 4393 __le32 reserved[8]; 4394 }; 4395 4396 /* The eth storm context for the Xstorm */ 4397 struct xstorm_eth_conn_st_ctx { 4398 __le32 reserved[60]; 4399 }; 4400 4401 struct xstorm_eth_conn_ag_ctx { 4402 u8 reserved0; 4403 u8 eth_state; 4404 u8 flags0; 4405 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 4406 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 4407 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_MASK 0x1 4408 #define XSTORM_ETH_CONN_AG_CTX_RESERVED1_SHIFT 1 4409 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_MASK 0x1 4410 #define XSTORM_ETH_CONN_AG_CTX_RESERVED2_SHIFT 2 4411 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 4412 #define XSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 4413 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_MASK 0x1 4414 #define XSTORM_ETH_CONN_AG_CTX_RESERVED3_SHIFT 4 4415 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_MASK 0x1 4416 #define XSTORM_ETH_CONN_AG_CTX_RESERVED4_SHIFT 5 4417 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_MASK 0x1 4418 #define XSTORM_ETH_CONN_AG_CTX_RESERVED5_SHIFT 6 4419 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_MASK 0x1 4420 #define XSTORM_ETH_CONN_AG_CTX_RESERVED6_SHIFT 7 4421 u8 flags1; 4422 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_MASK 0x1 4423 #define XSTORM_ETH_CONN_AG_CTX_RESERVED7_SHIFT 0 4424 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_MASK 0x1 4425 #define XSTORM_ETH_CONN_AG_CTX_RESERVED8_SHIFT 1 4426 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_MASK 0x1 4427 #define XSTORM_ETH_CONN_AG_CTX_RESERVED9_SHIFT 2 4428 #define XSTORM_ETH_CONN_AG_CTX_BIT11_MASK 0x1 4429 #define XSTORM_ETH_CONN_AG_CTX_BIT11_SHIFT 3 4430 #define XSTORM_ETH_CONN_AG_CTX_BIT12_MASK 0x1 4431 #define XSTORM_ETH_CONN_AG_CTX_BIT12_SHIFT 4 4432 #define XSTORM_ETH_CONN_AG_CTX_BIT13_MASK 0x1 4433 #define XSTORM_ETH_CONN_AG_CTX_BIT13_SHIFT 5 4434 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 4435 #define XSTORM_ETH_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 4436 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 4437 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 4438 u8 flags2; 4439 #define XSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 4440 #define XSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 0 4441 #define XSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 4442 #define XSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 2 4443 #define XSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 4444 #define XSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 4 4445 #define XSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 4446 #define XSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 6 4447 u8 flags3; 4448 #define XSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 4449 #define XSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 0 4450 #define XSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 4451 #define XSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 2 4452 #define XSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 4453 #define XSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 4 4454 #define XSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 4455 #define XSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 6 4456 u8 flags4; 4457 #define XSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 4458 #define XSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 0 4459 #define XSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 4460 #define XSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 2 4461 #define XSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 4462 #define XSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 4 4463 #define XSTORM_ETH_CONN_AG_CTX_CF11_MASK 0x3 4464 #define XSTORM_ETH_CONN_AG_CTX_CF11_SHIFT 6 4465 u8 flags5; 4466 #define XSTORM_ETH_CONN_AG_CTX_CF12_MASK 0x3 4467 #define XSTORM_ETH_CONN_AG_CTX_CF12_SHIFT 0 4468 #define XSTORM_ETH_CONN_AG_CTX_CF13_MASK 0x3 4469 #define XSTORM_ETH_CONN_AG_CTX_CF13_SHIFT 2 4470 #define XSTORM_ETH_CONN_AG_CTX_CF14_MASK 0x3 4471 #define XSTORM_ETH_CONN_AG_CTX_CF14_SHIFT 4 4472 #define XSTORM_ETH_CONN_AG_CTX_CF15_MASK 0x3 4473 #define XSTORM_ETH_CONN_AG_CTX_CF15_SHIFT 6 4474 u8 flags6; 4475 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 4476 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 4477 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 4478 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 4479 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_MASK 0x3 4480 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_SHIFT 4 4481 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 4482 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 4483 u8 flags7; 4484 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 4485 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 4486 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_MASK 0x3 4487 #define XSTORM_ETH_CONN_AG_CTX_RESERVED10_SHIFT 2 4488 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_MASK 0x3 4489 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_SHIFT 4 4490 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 4491 #define XSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 6 4492 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 4493 #define XSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 7 4494 u8 flags8; 4495 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 4496 #define XSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 0 4497 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 4498 #define XSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 1 4499 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 4500 #define XSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 2 4501 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 4502 #define XSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 3 4503 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 4504 #define XSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 4 4505 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 4506 #define XSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 5 4507 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 4508 #define XSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 6 4509 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 4510 #define XSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 7 4511 u8 flags9; 4512 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 4513 #define XSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 0 4514 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_MASK 0x1 4515 #define XSTORM_ETH_CONN_AG_CTX_CF11EN_SHIFT 1 4516 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_MASK 0x1 4517 #define XSTORM_ETH_CONN_AG_CTX_CF12EN_SHIFT 2 4518 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_MASK 0x1 4519 #define XSTORM_ETH_CONN_AG_CTX_CF13EN_SHIFT 3 4520 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_MASK 0x1 4521 #define XSTORM_ETH_CONN_AG_CTX_CF14EN_SHIFT 4 4522 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_MASK 0x1 4523 #define XSTORM_ETH_CONN_AG_CTX_CF15EN_SHIFT 5 4524 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 4525 #define XSTORM_ETH_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 4526 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 4527 #define XSTORM_ETH_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 4528 u8 flags10; 4529 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 4530 #define XSTORM_ETH_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 4531 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 4532 #define XSTORM_ETH_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 4533 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 4534 #define XSTORM_ETH_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 4535 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_MASK 0x1 4536 #define XSTORM_ETH_CONN_AG_CTX_RESERVED11_SHIFT 3 4537 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 4538 #define XSTORM_ETH_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 4539 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 4540 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 4541 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_MASK 0x1 4542 #define XSTORM_ETH_CONN_AG_CTX_RESERVED12_SHIFT 6 4543 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_MASK 0x1 4544 #define XSTORM_ETH_CONN_AG_CTX_RESERVED13_SHIFT 7 4545 u8 flags11; 4546 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_MASK 0x1 4547 #define XSTORM_ETH_CONN_AG_CTX_RESERVED14_SHIFT 0 4548 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_MASK 0x1 4549 #define XSTORM_ETH_CONN_AG_CTX_RESERVED15_SHIFT 1 4550 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 4551 #define XSTORM_ETH_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 4552 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 4553 #define XSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 3 4554 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 4555 #define XSTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 4 4556 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 4557 #define XSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 5 4558 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 4559 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 4560 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_MASK 0x1 4561 #define XSTORM_ETH_CONN_AG_CTX_RULE9EN_SHIFT 7 4562 u8 flags12; 4563 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_MASK 0x1 4564 #define XSTORM_ETH_CONN_AG_CTX_RULE10EN_SHIFT 0 4565 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_MASK 0x1 4566 #define XSTORM_ETH_CONN_AG_CTX_RULE11EN_SHIFT 1 4567 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 4568 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 4569 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 4570 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 4571 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_MASK 0x1 4572 #define XSTORM_ETH_CONN_AG_CTX_RULE14EN_SHIFT 4 4573 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_MASK 0x1 4574 #define XSTORM_ETH_CONN_AG_CTX_RULE15EN_SHIFT 5 4575 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_MASK 0x1 4576 #define XSTORM_ETH_CONN_AG_CTX_RULE16EN_SHIFT 6 4577 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_MASK 0x1 4578 #define XSTORM_ETH_CONN_AG_CTX_RULE17EN_SHIFT 7 4579 u8 flags13; 4580 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_MASK 0x1 4581 #define XSTORM_ETH_CONN_AG_CTX_RULE18EN_SHIFT 0 4582 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_MASK 0x1 4583 #define XSTORM_ETH_CONN_AG_CTX_RULE19EN_SHIFT 1 4584 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 4585 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 4586 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 4587 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 4588 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 4589 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 4590 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 4591 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 4592 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 4593 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 4594 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 4595 #define XSTORM_ETH_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 4596 u8 flags14; 4597 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 4598 #define XSTORM_ETH_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 4599 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 4600 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 4601 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 4602 #define XSTORM_ETH_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 4603 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 4604 #define XSTORM_ETH_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 4605 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 4606 #define XSTORM_ETH_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 4607 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 4608 #define XSTORM_ETH_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 4609 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 4610 #define XSTORM_ETH_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 4611 u8 edpm_event_id; 4612 __le16 physical_q0; 4613 __le16 ereserved1; 4614 __le16 edpm_num_bds; 4615 __le16 tx_bd_cons; 4616 __le16 tx_bd_prod; 4617 __le16 tx_class; 4618 __le16 conn_dpi; 4619 u8 byte3; 4620 u8 byte4; 4621 u8 byte5; 4622 u8 byte6; 4623 __le32 reg0; 4624 __le32 reg1; 4625 __le32 reg2; 4626 __le32 reg3; 4627 __le32 reg4; 4628 __le32 reg5; 4629 __le32 reg6; 4630 __le16 word7; 4631 __le16 word8; 4632 __le16 word9; 4633 __le16 word10; 4634 __le32 reg7; 4635 __le32 reg8; 4636 __le32 reg9; 4637 u8 byte7; 4638 u8 byte8; 4639 u8 byte9; 4640 u8 byte10; 4641 u8 byte11; 4642 u8 byte12; 4643 u8 byte13; 4644 u8 byte14; 4645 u8 byte15; 4646 u8 ereserved; 4647 __le16 word11; 4648 __le32 reg10; 4649 __le32 reg11; 4650 __le32 reg12; 4651 __le32 reg13; 4652 __le32 reg14; 4653 __le32 reg15; 4654 __le32 reg16; 4655 __le32 reg17; 4656 __le32 reg18; 4657 __le32 reg19; 4658 __le16 word12; 4659 __le16 word13; 4660 __le16 word14; 4661 __le16 word15; 4662 }; 4663 4664 /* The eth storm context for the Ystorm */ 4665 struct ystorm_eth_conn_st_ctx { 4666 __le32 reserved[8]; 4667 }; 4668 4669 struct ystorm_eth_conn_ag_ctx { 4670 u8 byte0; 4671 u8 state; 4672 u8 flags0; 4673 #define YSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 4674 #define YSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 4675 #define YSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 4676 #define YSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 4677 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 4678 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 2 4679 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_MASK 0x3 4680 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_SHIFT 4 4681 #define YSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 4682 #define YSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 4683 u8 flags1; 4684 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 4685 #define YSTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 0 4686 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_MASK 0x1 4687 #define YSTORM_ETH_CONN_AG_CTX_PMD_TERMINATE_CF_EN_SHIFT 1 4688 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 4689 #define YSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 4690 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 4691 #define YSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 4692 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 4693 #define YSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 4694 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 4695 #define YSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 4696 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 4697 #define YSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 4698 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 4699 #define YSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 4700 u8 tx_q0_int_coallecing_timeset; 4701 u8 byte3; 4702 __le16 word0; 4703 __le32 terminate_spqe; 4704 __le32 reg1; 4705 __le16 tx_bd_cons_upd; 4706 __le16 word2; 4707 __le16 word3; 4708 __le16 word4; 4709 __le32 reg2; 4710 __le32 reg3; 4711 }; 4712 4713 struct tstorm_eth_conn_ag_ctx { 4714 u8 byte0; 4715 u8 byte1; 4716 u8 flags0; 4717 #define TSTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 4718 #define TSTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 4719 #define TSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 4720 #define TSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 4721 #define TSTORM_ETH_CONN_AG_CTX_BIT2_MASK 0x1 4722 #define TSTORM_ETH_CONN_AG_CTX_BIT2_SHIFT 2 4723 #define TSTORM_ETH_CONN_AG_CTX_BIT3_MASK 0x1 4724 #define TSTORM_ETH_CONN_AG_CTX_BIT3_SHIFT 3 4725 #define TSTORM_ETH_CONN_AG_CTX_BIT4_MASK 0x1 4726 #define TSTORM_ETH_CONN_AG_CTX_BIT4_SHIFT 4 4727 #define TSTORM_ETH_CONN_AG_CTX_BIT5_MASK 0x1 4728 #define TSTORM_ETH_CONN_AG_CTX_BIT5_SHIFT 5 4729 #define TSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 4730 #define TSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 6 4731 u8 flags1; 4732 #define TSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 4733 #define TSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 0 4734 #define TSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 4735 #define TSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 2 4736 #define TSTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 4737 #define TSTORM_ETH_CONN_AG_CTX_CF3_SHIFT 4 4738 #define TSTORM_ETH_CONN_AG_CTX_CF4_MASK 0x3 4739 #define TSTORM_ETH_CONN_AG_CTX_CF4_SHIFT 6 4740 u8 flags2; 4741 #define TSTORM_ETH_CONN_AG_CTX_CF5_MASK 0x3 4742 #define TSTORM_ETH_CONN_AG_CTX_CF5_SHIFT 0 4743 #define TSTORM_ETH_CONN_AG_CTX_CF6_MASK 0x3 4744 #define TSTORM_ETH_CONN_AG_CTX_CF6_SHIFT 2 4745 #define TSTORM_ETH_CONN_AG_CTX_CF7_MASK 0x3 4746 #define TSTORM_ETH_CONN_AG_CTX_CF7_SHIFT 4 4747 #define TSTORM_ETH_CONN_AG_CTX_CF8_MASK 0x3 4748 #define TSTORM_ETH_CONN_AG_CTX_CF8_SHIFT 6 4749 u8 flags3; 4750 #define TSTORM_ETH_CONN_AG_CTX_CF9_MASK 0x3 4751 #define TSTORM_ETH_CONN_AG_CTX_CF9_SHIFT 0 4752 #define TSTORM_ETH_CONN_AG_CTX_CF10_MASK 0x3 4753 #define TSTORM_ETH_CONN_AG_CTX_CF10_SHIFT 2 4754 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 4755 #define TSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 4 4756 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 4757 #define TSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 5 4758 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 4759 #define TSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 6 4760 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 4761 #define TSTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 7 4762 u8 flags4; 4763 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_MASK 0x1 4764 #define TSTORM_ETH_CONN_AG_CTX_CF4EN_SHIFT 0 4765 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_MASK 0x1 4766 #define TSTORM_ETH_CONN_AG_CTX_CF5EN_SHIFT 1 4767 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_MASK 0x1 4768 #define TSTORM_ETH_CONN_AG_CTX_CF6EN_SHIFT 2 4769 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_MASK 0x1 4770 #define TSTORM_ETH_CONN_AG_CTX_CF7EN_SHIFT 3 4771 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_MASK 0x1 4772 #define TSTORM_ETH_CONN_AG_CTX_CF8EN_SHIFT 4 4773 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_MASK 0x1 4774 #define TSTORM_ETH_CONN_AG_CTX_CF9EN_SHIFT 5 4775 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_MASK 0x1 4776 #define TSTORM_ETH_CONN_AG_CTX_CF10EN_SHIFT 6 4777 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 4778 #define TSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 4779 u8 flags5; 4780 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 4781 #define TSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 4782 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 4783 #define TSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 4784 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 4785 #define TSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 4786 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 4787 #define TSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 4788 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 4789 #define TSTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 4790 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_MASK 0x1 4791 #define TSTORM_ETH_CONN_AG_CTX_RX_BD_EN_SHIFT 5 4792 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 4793 #define TSTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 4794 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 4795 #define TSTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 4796 __le32 reg0; 4797 __le32 reg1; 4798 __le32 reg2; 4799 __le32 reg3; 4800 __le32 reg4; 4801 __le32 reg5; 4802 __le32 reg6; 4803 __le32 reg7; 4804 __le32 reg8; 4805 u8 byte2; 4806 u8 byte3; 4807 __le16 rx_bd_cons; 4808 u8 byte4; 4809 u8 byte5; 4810 __le16 rx_bd_prod; 4811 __le16 word2; 4812 __le16 word3; 4813 __le32 reg9; 4814 __le32 reg10; 4815 }; 4816 4817 struct ustorm_eth_conn_ag_ctx { 4818 u8 byte0; 4819 u8 byte1; 4820 u8 flags0; 4821 #define USTORM_ETH_CONN_AG_CTX_BIT0_MASK 0x1 4822 #define USTORM_ETH_CONN_AG_CTX_BIT0_SHIFT 0 4823 #define USTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 4824 #define USTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 4825 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_MASK 0x3 4826 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_SHIFT 2 4827 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_MASK 0x3 4828 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_SHIFT 4 4829 #define USTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 4830 #define USTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 4831 u8 flags1; 4832 #define USTORM_ETH_CONN_AG_CTX_CF3_MASK 0x3 4833 #define USTORM_ETH_CONN_AG_CTX_CF3_SHIFT 0 4834 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_MASK 0x3 4835 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_SHIFT 2 4836 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_MASK 0x3 4837 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_SHIFT 4 4838 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_MASK 0x3 4839 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_SHIFT 6 4840 u8 flags2; 4841 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_MASK 0x1 4842 #define USTORM_ETH_CONN_AG_CTX_TX_PMD_TERMINATE_CF_EN_SHIFT 0 4843 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_MASK 0x1 4844 #define USTORM_ETH_CONN_AG_CTX_RX_PMD_TERMINATE_CF_EN_SHIFT 1 4845 #define USTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 4846 #define USTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 4847 #define USTORM_ETH_CONN_AG_CTX_CF3EN_MASK 0x1 4848 #define USTORM_ETH_CONN_AG_CTX_CF3EN_SHIFT 3 4849 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_MASK 0x1 4850 #define USTORM_ETH_CONN_AG_CTX_TX_ARM_CF_EN_SHIFT 4 4851 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_MASK 0x1 4852 #define USTORM_ETH_CONN_AG_CTX_RX_ARM_CF_EN_SHIFT 5 4853 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_MASK 0x1 4854 #define USTORM_ETH_CONN_AG_CTX_TX_BD_CONS_UPD_CF_EN_SHIFT 6 4855 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 4856 #define USTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 7 4857 u8 flags3; 4858 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 4859 #define USTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 0 4860 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 4861 #define USTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 1 4862 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 4863 #define USTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 2 4864 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 4865 #define USTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 3 4866 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_MASK 0x1 4867 #define USTORM_ETH_CONN_AG_CTX_RULE5EN_SHIFT 4 4868 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_MASK 0x1 4869 #define USTORM_ETH_CONN_AG_CTX_RULE6EN_SHIFT 5 4870 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_MASK 0x1 4871 #define USTORM_ETH_CONN_AG_CTX_RULE7EN_SHIFT 6 4872 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_MASK 0x1 4873 #define USTORM_ETH_CONN_AG_CTX_RULE8EN_SHIFT 7 4874 u8 byte2; 4875 u8 byte3; 4876 __le16 word0; 4877 __le16 tx_bd_cons; 4878 __le32 reg0; 4879 __le32 reg1; 4880 __le32 reg2; 4881 __le32 tx_int_coallecing_timeset; 4882 __le16 tx_drv_bd_cons; 4883 __le16 rx_drv_cqe_cons; 4884 }; 4885 4886 /* The eth storm context for the Ustorm */ 4887 struct ustorm_eth_conn_st_ctx { 4888 __le32 reserved[40]; 4889 }; 4890 4891 /* The eth storm context for the Mstorm */ 4892 struct mstorm_eth_conn_st_ctx { 4893 __le32 reserved[8]; 4894 }; 4895 4896 /* eth connection context */ 4897 struct eth_conn_context { 4898 struct tstorm_eth_conn_st_ctx tstorm_st_context; 4899 struct regpair tstorm_st_padding[2]; 4900 struct pstorm_eth_conn_st_ctx pstorm_st_context; 4901 struct xstorm_eth_conn_st_ctx xstorm_st_context; 4902 struct xstorm_eth_conn_ag_ctx xstorm_ag_context; 4903 struct ystorm_eth_conn_st_ctx ystorm_st_context; 4904 struct ystorm_eth_conn_ag_ctx ystorm_ag_context; 4905 struct tstorm_eth_conn_ag_ctx tstorm_ag_context; 4906 struct ustorm_eth_conn_ag_ctx ustorm_ag_context; 4907 struct ustorm_eth_conn_st_ctx ustorm_st_context; 4908 struct mstorm_eth_conn_st_ctx mstorm_st_context; 4909 }; 4910 4911 enum eth_error_code { 4912 ETH_OK = 0x00, 4913 ETH_FILTERS_MAC_ADD_FAIL_FULL, 4914 ETH_FILTERS_MAC_ADD_FAIL_FULL_MTT2, 4915 ETH_FILTERS_MAC_ADD_FAIL_DUP_MTT2, 4916 ETH_FILTERS_MAC_ADD_FAIL_DUP_STT2, 4917 ETH_FILTERS_MAC_DEL_FAIL_NOF, 4918 ETH_FILTERS_MAC_DEL_FAIL_NOF_MTT2, 4919 ETH_FILTERS_MAC_DEL_FAIL_NOF_STT2, 4920 ETH_FILTERS_MAC_ADD_FAIL_ZERO_MAC, 4921 ETH_FILTERS_VLAN_ADD_FAIL_FULL, 4922 ETH_FILTERS_VLAN_ADD_FAIL_DUP, 4923 ETH_FILTERS_VLAN_DEL_FAIL_NOF, 4924 ETH_FILTERS_VLAN_DEL_FAIL_NOF_TT1, 4925 ETH_FILTERS_PAIR_ADD_FAIL_DUP, 4926 ETH_FILTERS_PAIR_ADD_FAIL_FULL, 4927 ETH_FILTERS_PAIR_ADD_FAIL_FULL_MAC, 4928 ETH_FILTERS_PAIR_DEL_FAIL_NOF, 4929 ETH_FILTERS_PAIR_DEL_FAIL_NOF_TT1, 4930 ETH_FILTERS_PAIR_ADD_FAIL_ZERO_MAC, 4931 ETH_FILTERS_VNI_ADD_FAIL_FULL, 4932 ETH_FILTERS_VNI_ADD_FAIL_DUP, 4933 ETH_FILTERS_GFT_UPDATE_FAIL, 4934 MAX_ETH_ERROR_CODE 4935 }; 4936 4937 enum eth_event_opcode { 4938 ETH_EVENT_UNUSED, 4939 ETH_EVENT_VPORT_START, 4940 ETH_EVENT_VPORT_UPDATE, 4941 ETH_EVENT_VPORT_STOP, 4942 ETH_EVENT_TX_QUEUE_START, 4943 ETH_EVENT_TX_QUEUE_STOP, 4944 ETH_EVENT_RX_QUEUE_START, 4945 ETH_EVENT_RX_QUEUE_UPDATE, 4946 ETH_EVENT_RX_QUEUE_STOP, 4947 ETH_EVENT_FILTERS_UPDATE, 4948 ETH_EVENT_RESERVED, 4949 ETH_EVENT_RESERVED2, 4950 ETH_EVENT_RESERVED3, 4951 ETH_EVENT_RX_ADD_UDP_FILTER, 4952 ETH_EVENT_RX_DELETE_UDP_FILTER, 4953 ETH_EVENT_RESERVED4, 4954 ETH_EVENT_RESERVED5, 4955 MAX_ETH_EVENT_OPCODE 4956 }; 4957 4958 /* Classify rule types in E2/E3 */ 4959 enum eth_filter_action { 4960 ETH_FILTER_ACTION_UNUSED, 4961 ETH_FILTER_ACTION_REMOVE, 4962 ETH_FILTER_ACTION_ADD, 4963 ETH_FILTER_ACTION_REMOVE_ALL, 4964 MAX_ETH_FILTER_ACTION 4965 }; 4966 4967 /* Command for adding/removing a classification rule $$KEEP_ENDIANNESS$$ */ 4968 struct eth_filter_cmd { 4969 u8 type; 4970 u8 vport_id; 4971 u8 action; 4972 u8 reserved0; 4973 __le32 vni; 4974 __le16 mac_lsb; 4975 __le16 mac_mid; 4976 __le16 mac_msb; 4977 __le16 vlan_id; 4978 }; 4979 4980 /* $$KEEP_ENDIANNESS$$ */ 4981 struct eth_filter_cmd_header { 4982 u8 rx; 4983 u8 tx; 4984 u8 cmd_cnt; 4985 u8 assert_on_error; 4986 u8 reserved1[4]; 4987 }; 4988 4989 /* Ethernet filter types: mac/vlan/pair */ 4990 enum eth_filter_type { 4991 ETH_FILTER_TYPE_UNUSED, 4992 ETH_FILTER_TYPE_MAC, 4993 ETH_FILTER_TYPE_VLAN, 4994 ETH_FILTER_TYPE_PAIR, 4995 ETH_FILTER_TYPE_INNER_MAC, 4996 ETH_FILTER_TYPE_INNER_VLAN, 4997 ETH_FILTER_TYPE_INNER_PAIR, 4998 ETH_FILTER_TYPE_INNER_MAC_VNI_PAIR, 4999 ETH_FILTER_TYPE_MAC_VNI_PAIR, 5000 ETH_FILTER_TYPE_VNI, 5001 MAX_ETH_FILTER_TYPE 5002 }; 5003 5004 enum eth_ipv4_frag_type { 5005 ETH_IPV4_NOT_FRAG, 5006 ETH_IPV4_FIRST_FRAG, 5007 ETH_IPV4_NON_FIRST_FRAG, 5008 MAX_ETH_IPV4_FRAG_TYPE 5009 }; 5010 5011 enum eth_ip_type { 5012 ETH_IPV4, 5013 ETH_IPV6, 5014 MAX_ETH_IP_TYPE 5015 }; 5016 5017 enum eth_ramrod_cmd_id { 5018 ETH_RAMROD_UNUSED, 5019 ETH_RAMROD_VPORT_START, 5020 ETH_RAMROD_VPORT_UPDATE, 5021 ETH_RAMROD_VPORT_STOP, 5022 ETH_RAMROD_RX_QUEUE_START, 5023 ETH_RAMROD_RX_QUEUE_STOP, 5024 ETH_RAMROD_TX_QUEUE_START, 5025 ETH_RAMROD_TX_QUEUE_STOP, 5026 ETH_RAMROD_FILTERS_UPDATE, 5027 ETH_RAMROD_RX_QUEUE_UPDATE, 5028 ETH_RAMROD_RX_CREATE_OPENFLOW_ACTION, 5029 ETH_RAMROD_RX_ADD_OPENFLOW_FILTER, 5030 ETH_RAMROD_RX_DELETE_OPENFLOW_FILTER, 5031 ETH_RAMROD_RX_ADD_UDP_FILTER, 5032 ETH_RAMROD_RX_DELETE_UDP_FILTER, 5033 ETH_RAMROD_RX_CREATE_GFT_ACTION, 5034 ETH_RAMROD_GFT_UPDATE_FILTER, 5035 MAX_ETH_RAMROD_CMD_ID 5036 }; 5037 5038 /* return code from eth sp ramrods */ 5039 struct eth_return_code { 5040 u8 value; 5041 #define ETH_RETURN_CODE_ERR_CODE_MASK 0x1F 5042 #define ETH_RETURN_CODE_ERR_CODE_SHIFT 0 5043 #define ETH_RETURN_CODE_RESERVED_MASK 0x3 5044 #define ETH_RETURN_CODE_RESERVED_SHIFT 5 5045 #define ETH_RETURN_CODE_RX_TX_MASK 0x1 5046 #define ETH_RETURN_CODE_RX_TX_SHIFT 7 5047 }; 5048 5049 /* What to do in case an error occurs */ 5050 enum eth_tx_err { 5051 ETH_TX_ERR_DROP, 5052 ETH_TX_ERR_ASSERT_MALICIOUS, 5053 MAX_ETH_TX_ERR 5054 }; 5055 5056 /* Array of the different error type behaviors */ 5057 struct eth_tx_err_vals { 5058 __le16 values; 5059 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_MASK 0x1 5060 #define ETH_TX_ERR_VALS_ILLEGAL_VLAN_MODE_SHIFT 0 5061 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_MASK 0x1 5062 #define ETH_TX_ERR_VALS_PACKET_TOO_SMALL_SHIFT 1 5063 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_MASK 0x1 5064 #define ETH_TX_ERR_VALS_ANTI_SPOOFING_ERR_SHIFT 2 5065 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_MASK 0x1 5066 #define ETH_TX_ERR_VALS_ILLEGAL_INBAND_TAGS_SHIFT 3 5067 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_MASK 0x1 5068 #define ETH_TX_ERR_VALS_VLAN_INSERTION_W_INBAND_TAG_SHIFT 4 5069 #define ETH_TX_ERR_VALS_MTU_VIOLATION_MASK 0x1 5070 #define ETH_TX_ERR_VALS_MTU_VIOLATION_SHIFT 5 5071 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_MASK 0x1 5072 #define ETH_TX_ERR_VALS_ILLEGAL_CONTROL_FRAME_SHIFT 6 5073 #define ETH_TX_ERR_VALS_RESERVED_MASK 0x1FF 5074 #define ETH_TX_ERR_VALS_RESERVED_SHIFT 7 5075 }; 5076 5077 /* vport rss configuration data */ 5078 struct eth_vport_rss_config { 5079 __le16 capabilities; 5080 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_MASK 0x1 5081 #define ETH_VPORT_RSS_CONFIG_IPV4_CAPABILITY_SHIFT 0 5082 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_MASK 0x1 5083 #define ETH_VPORT_RSS_CONFIG_IPV6_CAPABILITY_SHIFT 1 5084 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_MASK 0x1 5085 #define ETH_VPORT_RSS_CONFIG_IPV4_TCP_CAPABILITY_SHIFT 2 5086 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_MASK 0x1 5087 #define ETH_VPORT_RSS_CONFIG_IPV6_TCP_CAPABILITY_SHIFT 3 5088 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_MASK 0x1 5089 #define ETH_VPORT_RSS_CONFIG_IPV4_UDP_CAPABILITY_SHIFT 4 5090 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_MASK 0x1 5091 #define ETH_VPORT_RSS_CONFIG_IPV6_UDP_CAPABILITY_SHIFT 5 5092 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_MASK 0x1 5093 #define ETH_VPORT_RSS_CONFIG_EN_5_TUPLE_CAPABILITY_SHIFT 6 5094 #define ETH_VPORT_RSS_CONFIG_RESERVED0_MASK 0x1FF 5095 #define ETH_VPORT_RSS_CONFIG_RESERVED0_SHIFT 7 5096 u8 rss_id; 5097 u8 rss_mode; 5098 u8 update_rss_key; 5099 u8 update_rss_ind_table; 5100 u8 update_rss_capabilities; 5101 u8 tbl_size; 5102 __le32 reserved2[2]; 5103 __le16 indirection_table[ETH_RSS_IND_TABLE_ENTRIES_NUM]; 5104 5105 __le32 rss_key[ETH_RSS_KEY_SIZE_REGS]; 5106 __le32 reserved3[2]; 5107 }; 5108 5109 /* eth vport RSS mode */ 5110 enum eth_vport_rss_mode { 5111 ETH_VPORT_RSS_MODE_DISABLED, 5112 ETH_VPORT_RSS_MODE_REGULAR, 5113 MAX_ETH_VPORT_RSS_MODE 5114 }; 5115 5116 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */ 5117 struct eth_vport_rx_mode { 5118 __le16 state; 5119 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_MASK 0x1 5120 #define ETH_VPORT_RX_MODE_UCAST_DROP_ALL_SHIFT 0 5121 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_MASK 0x1 5122 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_ALL_SHIFT 1 5123 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_MASK 0x1 5124 #define ETH_VPORT_RX_MODE_UCAST_ACCEPT_UNMATCHED_SHIFT 2 5125 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_MASK 0x1 5126 #define ETH_VPORT_RX_MODE_MCAST_DROP_ALL_SHIFT 3 5127 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_MASK 0x1 5128 #define ETH_VPORT_RX_MODE_MCAST_ACCEPT_ALL_SHIFT 4 5129 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_MASK 0x1 5130 #define ETH_VPORT_RX_MODE_BCAST_ACCEPT_ALL_SHIFT 5 5131 #define ETH_VPORT_RX_MODE_RESERVED1_MASK 0x3FF 5132 #define ETH_VPORT_RX_MODE_RESERVED1_SHIFT 6 5133 __le16 reserved2[3]; 5134 }; 5135 5136 /* Command for setting tpa parameters */ 5137 struct eth_vport_tpa_param { 5138 u8 tpa_ipv4_en_flg; 5139 u8 tpa_ipv6_en_flg; 5140 u8 tpa_ipv4_tunn_en_flg; 5141 u8 tpa_ipv6_tunn_en_flg; 5142 u8 tpa_pkt_split_flg; 5143 u8 tpa_hdr_data_split_flg; 5144 u8 tpa_gro_consistent_flg; 5145 5146 u8 tpa_max_aggs_num; 5147 5148 __le16 tpa_max_size; 5149 __le16 tpa_min_size_to_start; 5150 5151 __le16 tpa_min_size_to_cont; 5152 u8 max_buff_num; 5153 u8 reserved; 5154 }; 5155 5156 /* Command for setting classification flags for a vport $$KEEP_ENDIANNESS$$ */ 5157 struct eth_vport_tx_mode { 5158 __le16 state; 5159 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_MASK 0x1 5160 #define ETH_VPORT_TX_MODE_UCAST_DROP_ALL_SHIFT 0 5161 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_MASK 0x1 5162 #define ETH_VPORT_TX_MODE_UCAST_ACCEPT_ALL_SHIFT 1 5163 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_MASK 0x1 5164 #define ETH_VPORT_TX_MODE_MCAST_DROP_ALL_SHIFT 2 5165 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_MASK 0x1 5166 #define ETH_VPORT_TX_MODE_MCAST_ACCEPT_ALL_SHIFT 3 5167 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_MASK 0x1 5168 #define ETH_VPORT_TX_MODE_BCAST_ACCEPT_ALL_SHIFT 4 5169 #define ETH_VPORT_TX_MODE_RESERVED1_MASK 0x7FF 5170 #define ETH_VPORT_TX_MODE_RESERVED1_SHIFT 5 5171 __le16 reserved2[3]; 5172 }; 5173 5174 enum gft_filter_update_action { 5175 GFT_ADD_FILTER, 5176 GFT_DELETE_FILTER, 5177 MAX_GFT_FILTER_UPDATE_ACTION 5178 }; 5179 5180 enum gft_logic_filter_type { 5181 GFT_FILTER_TYPE, 5182 RFS_FILTER_TYPE, 5183 MAX_GFT_LOGIC_FILTER_TYPE 5184 }; 5185 5186 struct rx_add_openflow_filter_data { 5187 __le16 action_icid; 5188 u8 priority; 5189 u8 reserved0; 5190 __le32 tenant_id; 5191 __le16 dst_mac_hi; 5192 __le16 dst_mac_mid; 5193 __le16 dst_mac_lo; 5194 __le16 src_mac_hi; 5195 __le16 src_mac_mid; 5196 __le16 src_mac_lo; 5197 __le16 vlan_id; 5198 __le16 l2_eth_type; 5199 u8 ipv4_dscp; 5200 u8 ipv4_frag_type; 5201 u8 ipv4_over_ip; 5202 u8 tenant_id_exists; 5203 __le32 ipv4_dst_addr; 5204 __le32 ipv4_src_addr; 5205 __le16 l4_dst_port; 5206 __le16 l4_src_port; 5207 }; 5208 5209 struct rx_create_gft_action_data { 5210 u8 vport_id; 5211 u8 reserved[7]; 5212 }; 5213 5214 struct rx_create_openflow_action_data { 5215 u8 vport_id; 5216 u8 reserved[7]; 5217 }; 5218 5219 /* Ramrod data for rx queue start ramrod */ 5220 struct rx_queue_start_ramrod_data { 5221 __le16 rx_queue_id; 5222 __le16 num_of_pbl_pages; 5223 __le16 bd_max_bytes; 5224 __le16 sb_id; 5225 u8 sb_index; 5226 u8 vport_id; 5227 u8 default_rss_queue_flg; 5228 u8 complete_cqe_flg; 5229 u8 complete_event_flg; 5230 u8 stats_counter_id; 5231 u8 pin_context; 5232 u8 pxp_tph_valid_bd; 5233 u8 pxp_tph_valid_pkt; 5234 u8 pxp_st_hint; 5235 5236 __le16 pxp_st_index; 5237 u8 pmd_mode; 5238 5239 u8 notify_en; 5240 u8 toggle_val; 5241 5242 u8 vf_rx_prod_index; 5243 u8 vf_rx_prod_use_zone_a; 5244 u8 reserved[5]; 5245 __le16 reserved1; 5246 struct regpair cqe_pbl_addr; 5247 struct regpair bd_base; 5248 struct regpair reserved2; 5249 }; 5250 5251 /* Ramrod data for rx queue start ramrod */ 5252 struct rx_queue_stop_ramrod_data { 5253 __le16 rx_queue_id; 5254 u8 complete_cqe_flg; 5255 u8 complete_event_flg; 5256 u8 vport_id; 5257 u8 reserved[3]; 5258 }; 5259 5260 /* Ramrod data for rx queue update ramrod */ 5261 struct rx_queue_update_ramrod_data { 5262 __le16 rx_queue_id; 5263 u8 complete_cqe_flg; 5264 u8 complete_event_flg; 5265 u8 vport_id; 5266 u8 reserved[4]; 5267 u8 reserved1; 5268 u8 reserved2; 5269 u8 reserved3; 5270 __le16 reserved4; 5271 __le16 reserved5; 5272 struct regpair reserved6; 5273 }; 5274 5275 /* Ramrod data for rx Add UDP Filter */ 5276 struct rx_udp_filter_data { 5277 __le16 action_icid; 5278 __le16 vlan_id; 5279 u8 ip_type; 5280 u8 tenant_id_exists; 5281 __le16 reserved1; 5282 __le32 ip_dst_addr[4]; 5283 __le32 ip_src_addr[4]; 5284 __le16 udp_dst_port; 5285 __le16 udp_src_port; 5286 __le32 tenant_id; 5287 }; 5288 5289 struct rx_update_gft_filter_data { 5290 struct regpair pkt_hdr_addr; 5291 __le16 pkt_hdr_length; 5292 __le16 rx_qid_or_action_icid; 5293 u8 vport_id; 5294 u8 filter_type; 5295 u8 filter_action; 5296 u8 assert_on_error; 5297 }; 5298 5299 /* Ramrod data for rx queue start ramrod */ 5300 struct tx_queue_start_ramrod_data { 5301 __le16 sb_id; 5302 u8 sb_index; 5303 u8 vport_id; 5304 u8 reserved0; 5305 u8 stats_counter_id; 5306 __le16 qm_pq_id; 5307 u8 flags; 5308 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_MASK 0x1 5309 #define TX_QUEUE_START_RAMROD_DATA_DISABLE_OPPORTUNISTIC_SHIFT 0 5310 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_MASK 0x1 5311 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_PKT_DUP_SHIFT 1 5312 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_MASK 0x1 5313 #define TX_QUEUE_START_RAMROD_DATA_TEST_MODE_TX_DEST_SHIFT 2 5314 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_MASK 0x1 5315 #define TX_QUEUE_START_RAMROD_DATA_PMD_MODE_SHIFT 3 5316 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_MASK 0x1 5317 #define TX_QUEUE_START_RAMROD_DATA_NOTIFY_EN_SHIFT 4 5318 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_MASK 0x1 5319 #define TX_QUEUE_START_RAMROD_DATA_PIN_CONTEXT_SHIFT 5 5320 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_MASK 0x3 5321 #define TX_QUEUE_START_RAMROD_DATA_RESERVED1_SHIFT 6 5322 u8 pxp_st_hint; 5323 u8 pxp_tph_valid_bd; 5324 u8 pxp_tph_valid_pkt; 5325 __le16 pxp_st_index; 5326 __le16 comp_agg_size; 5327 __le16 queue_zone_id; 5328 __le16 reserved2; 5329 __le16 pbl_size; 5330 __le16 tx_queue_id; 5331 __le16 same_as_last_id; 5332 __le16 reserved[3]; 5333 struct regpair pbl_base_addr; 5334 struct regpair bd_cons_address; 5335 }; 5336 5337 /* Ramrod data for tx queue stop ramrod */ 5338 struct tx_queue_stop_ramrod_data { 5339 __le16 reserved[4]; 5340 }; 5341 5342 /* Ramrod data for vport update ramrod */ 5343 struct vport_filter_update_ramrod_data { 5344 struct eth_filter_cmd_header filter_cmd_hdr; 5345 struct eth_filter_cmd filter_cmds[ETH_FILTER_RULES_COUNT]; 5346 }; 5347 5348 /* Ramrod data for vport start ramrod */ 5349 struct vport_start_ramrod_data { 5350 u8 vport_id; 5351 u8 sw_fid; 5352 __le16 mtu; 5353 u8 drop_ttl0_en; 5354 u8 inner_vlan_removal_en; 5355 struct eth_vport_rx_mode rx_mode; 5356 struct eth_vport_tx_mode tx_mode; 5357 struct eth_vport_tpa_param tpa_param; 5358 __le16 default_vlan; 5359 u8 tx_switching_en; 5360 u8 anti_spoofing_en; 5361 5362 u8 default_vlan_en; 5363 5364 u8 handle_ptp_pkts; 5365 u8 silent_vlan_removal_en; 5366 u8 untagged; 5367 struct eth_tx_err_vals tx_err_behav; 5368 5369 u8 zero_placement_offset; 5370 u8 ctl_frame_mac_check_en; 5371 u8 ctl_frame_ethtype_check_en; 5372 u8 reserved[5]; 5373 }; 5374 5375 /* Ramrod data for vport stop ramrod */ 5376 struct vport_stop_ramrod_data { 5377 u8 vport_id; 5378 u8 reserved[7]; 5379 }; 5380 5381 /* Ramrod data for vport update ramrod */ 5382 struct vport_update_ramrod_data_cmn { 5383 u8 vport_id; 5384 u8 update_rx_active_flg; 5385 u8 rx_active_flg; 5386 u8 update_tx_active_flg; 5387 u8 tx_active_flg; 5388 u8 update_rx_mode_flg; 5389 u8 update_tx_mode_flg; 5390 u8 update_approx_mcast_flg; 5391 5392 u8 update_rss_flg; 5393 u8 update_inner_vlan_removal_en_flg; 5394 5395 u8 inner_vlan_removal_en; 5396 u8 update_tpa_param_flg; 5397 u8 update_tpa_en_flg; 5398 u8 update_tx_switching_en_flg; 5399 5400 u8 tx_switching_en; 5401 u8 update_anti_spoofing_en_flg; 5402 5403 u8 anti_spoofing_en; 5404 u8 update_handle_ptp_pkts; 5405 5406 u8 handle_ptp_pkts; 5407 u8 update_default_vlan_en_flg; 5408 5409 u8 default_vlan_en; 5410 5411 u8 update_default_vlan_flg; 5412 5413 __le16 default_vlan; 5414 u8 update_accept_any_vlan_flg; 5415 5416 u8 accept_any_vlan; 5417 u8 silent_vlan_removal_en; 5418 u8 update_mtu_flg; 5419 5420 __le16 mtu; 5421 u8 update_ctl_frame_checks_en_flg; 5422 u8 ctl_frame_mac_check_en; 5423 u8 ctl_frame_ethtype_check_en; 5424 u8 reserved[15]; 5425 }; 5426 5427 struct vport_update_ramrod_mcast { 5428 __le32 bins[ETH_MULTICAST_MAC_BINS_IN_REGS]; 5429 }; 5430 5431 /* Ramrod data for vport update ramrod */ 5432 struct vport_update_ramrod_data { 5433 struct vport_update_ramrod_data_cmn common; 5434 5435 struct eth_vport_rx_mode rx_mode; 5436 struct eth_vport_tx_mode tx_mode; 5437 struct eth_vport_tpa_param tpa_param; 5438 struct vport_update_ramrod_mcast approx_mcast; 5439 struct eth_vport_rss_config rss_config; 5440 }; 5441 5442 struct xstorm_eth_conn_agctxdq_ext_ldpart { 5443 u8 reserved0; 5444 u8 eth_state; 5445 u8 flags0; 5446 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 5447 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 5448 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_MASK 0x1 5449 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED1_SHIFT 1 5450 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_MASK 0x1 5451 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED2_SHIFT 2 5452 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 5453 #define XSTORMETHCONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 5454 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_MASK 0x1 5455 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED3_SHIFT 4 5456 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_MASK 0x1 5457 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED4_SHIFT 5 5458 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_MASK 0x1 5459 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED5_SHIFT 6 5460 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_MASK 0x1 5461 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED6_SHIFT 7 5462 u8 flags1; 5463 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_MASK 0x1 5464 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED7_SHIFT 0 5465 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_MASK 0x1 5466 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED8_SHIFT 1 5467 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_MASK 0x1 5468 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED9_SHIFT 2 5469 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 5470 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 5471 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_MASK 0x1 5472 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT12_SHIFT 4 5473 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_MASK 0x1 5474 #define XSTORMETHCONNAGCTXDQEXTLDPART_BIT13_SHIFT 5 5475 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_MASK 0x1 5476 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_RULE_ACTIVE_SHIFT 6 5477 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_MASK 0x1 5478 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_ACTIVE_SHIFT 7 5479 u8 flags2; 5480 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0_MASK 0x3 5481 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0_SHIFT 0 5482 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1_MASK 0x3 5483 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1_SHIFT 2 5484 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2_MASK 0x3 5485 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2_SHIFT 4 5486 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3_MASK 0x3 5487 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3_SHIFT 6 5488 u8 flags3; 5489 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4_MASK 0x3 5490 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4_SHIFT 0 5491 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5_MASK 0x3 5492 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5_SHIFT 2 5493 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6_MASK 0x3 5494 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6_SHIFT 4 5495 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7_MASK 0x3 5496 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7_SHIFT 6 5497 u8 flags4; 5498 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8_MASK 0x3 5499 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8_SHIFT 0 5500 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9_MASK 0x3 5501 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9_SHIFT 2 5502 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10_MASK 0x3 5503 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10_SHIFT 4 5504 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11_MASK 0x3 5505 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11_SHIFT 6 5506 u8 flags5; 5507 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12_MASK 0x3 5508 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12_SHIFT 0 5509 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13_MASK 0x3 5510 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13_SHIFT 2 5511 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14_MASK 0x3 5512 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14_SHIFT 4 5513 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15_MASK 0x3 5514 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15_SHIFT 6 5515 u8 flags6; 5516 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_MASK 0x3 5517 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_SHIFT 0 5518 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_MASK 0x3 5519 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_SHIFT 2 5520 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_MASK 0x3 5521 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_SHIFT 4 5522 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_MASK 0x3 5523 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_SHIFT 6 5524 u8 flags7; 5525 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_MASK 0x3 5526 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_SHIFT 0 5527 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_MASK 0x3 5528 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED10_SHIFT 2 5529 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 5530 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 5531 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 5532 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 5533 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 5534 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 5535 u8 flags8; 5536 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 5537 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 5538 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 5539 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 5540 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 5541 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 5542 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 5543 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 5544 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 5545 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 5546 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_MASK 0x1 5547 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF7EN_SHIFT 5 5548 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 5549 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 5550 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 5551 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 5552 u8 flags9; 5553 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 5554 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 5555 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 5556 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 5557 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 5558 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 5559 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 5560 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 5561 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 5562 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 5563 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 5564 #define XSTORMETHCONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 5565 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_MASK 0x1 5566 #define XSTORMETHCONNAGCTXDQEXTLDPART_GO_TO_BD_CONS_CF_EN_SHIFT 6 5567 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_MASK 0x1 5568 #define XSTORMETHCONNAGCTXDQEXTLDPART_MULTI_UNICAST_CF_EN_SHIFT 7 5569 u8 flags10; 5570 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_MASK 0x1 5571 #define XSTORMETHCONNAGCTXDQEXTLDPART_DQ_CF_EN_SHIFT 0 5572 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_MASK 0x1 5573 #define XSTORMETHCONNAGCTXDQEXTLDPART_TERMINATE_CF_EN_SHIFT 1 5574 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_MASK 0x1 5575 #define XSTORMETHCONNAGCTXDQEXTLDPART_FLUSH_Q0_EN_SHIFT 2 5576 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_MASK 0x1 5577 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED11_SHIFT 3 5578 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 5579 #define XSTORMETHCONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 5580 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_MASK 0x1 5581 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_EN_RESERVED_SHIFT 5 5582 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_MASK 0x1 5583 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED12_SHIFT 6 5584 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_MASK 0x1 5585 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED13_SHIFT 7 5586 u8 flags11; 5587 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_MASK 0x1 5588 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED14_SHIFT 0 5589 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_MASK 0x1 5590 #define XSTORMETHCONNAGCTXDQEXTLDPART_RESERVED15_SHIFT 1 5591 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_MASK 0x1 5592 #define XSTORMETHCONNAGCTXDQEXTLDPART_TX_DEC_RULE_EN_SHIFT 2 5593 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 5594 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 5595 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 5596 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 5597 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 5598 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 5599 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 5600 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 5601 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 5602 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 5603 u8 flags12; 5604 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 5605 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 5606 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 5607 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 5608 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 5609 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 5610 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 5611 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 5612 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 5613 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 5614 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 5615 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 5616 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 5617 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 5618 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 5619 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 5620 u8 flags13; 5621 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 5622 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 5623 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 5624 #define XSTORMETHCONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 5625 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 5626 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 5627 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 5628 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 5629 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 5630 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 5631 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 5632 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 5633 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 5634 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 5635 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 5636 #define XSTORMETHCONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 5637 u8 flags14; 5638 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_MASK 0x1 5639 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_USE_EXT_HDR_SHIFT 0 5640 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_MASK 0x1 5641 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_RAW_L3L4_SHIFT 1 5642 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_MASK 0x1 5643 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_INBAND_PROP_HDR_SHIFT 2 5644 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_MASK 0x1 5645 #define XSTORMETHCONNAGCTXDQEXTLDPART_EDPM_SEND_EXT_TUNNEL_SHIFT 3 5646 #define XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_MASK 0x1 5647 #define XSTORMETHCONNAGCTXDQEXTLDPART_L2_EDPM_ENABLE_SHIFT 4 5648 #define XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 5649 #define XSTORMETHCONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 5650 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_MASK 0x3 5651 #define XSTORMETHCONNAGCTXDQEXTLDPART_TPH_ENABLE_SHIFT 6 5652 u8 edpm_event_id; 5653 __le16 physical_q0; 5654 __le16 ereserved1; 5655 __le16 edpm_num_bds; 5656 __le16 tx_bd_cons; 5657 __le16 tx_bd_prod; 5658 __le16 tx_class; 5659 __le16 conn_dpi; 5660 u8 byte3; 5661 u8 byte4; 5662 u8 byte5; 5663 u8 byte6; 5664 __le32 reg0; 5665 __le32 reg1; 5666 __le32 reg2; 5667 __le32 reg3; 5668 __le32 reg4; 5669 }; 5670 5671 struct mstorm_eth_conn_ag_ctx { 5672 u8 byte0; 5673 u8 byte1; 5674 u8 flags0; 5675 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 5676 #define MSTORM_ETH_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 5677 #define MSTORM_ETH_CONN_AG_CTX_BIT1_MASK 0x1 5678 #define MSTORM_ETH_CONN_AG_CTX_BIT1_SHIFT 1 5679 #define MSTORM_ETH_CONN_AG_CTX_CF0_MASK 0x3 5680 #define MSTORM_ETH_CONN_AG_CTX_CF0_SHIFT 2 5681 #define MSTORM_ETH_CONN_AG_CTX_CF1_MASK 0x3 5682 #define MSTORM_ETH_CONN_AG_CTX_CF1_SHIFT 4 5683 #define MSTORM_ETH_CONN_AG_CTX_CF2_MASK 0x3 5684 #define MSTORM_ETH_CONN_AG_CTX_CF2_SHIFT 6 5685 u8 flags1; 5686 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_MASK 0x1 5687 #define MSTORM_ETH_CONN_AG_CTX_CF0EN_SHIFT 0 5688 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_MASK 0x1 5689 #define MSTORM_ETH_CONN_AG_CTX_CF1EN_SHIFT 1 5690 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_MASK 0x1 5691 #define MSTORM_ETH_CONN_AG_CTX_CF2EN_SHIFT 2 5692 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_MASK 0x1 5693 #define MSTORM_ETH_CONN_AG_CTX_RULE0EN_SHIFT 3 5694 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_MASK 0x1 5695 #define MSTORM_ETH_CONN_AG_CTX_RULE1EN_SHIFT 4 5696 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_MASK 0x1 5697 #define MSTORM_ETH_CONN_AG_CTX_RULE2EN_SHIFT 5 5698 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_MASK 0x1 5699 #define MSTORM_ETH_CONN_AG_CTX_RULE3EN_SHIFT 6 5700 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_MASK 0x1 5701 #define MSTORM_ETH_CONN_AG_CTX_RULE4EN_SHIFT 7 5702 __le16 word0; 5703 __le16 word1; 5704 __le32 reg0; 5705 __le32 reg1; 5706 }; 5707 5708 struct xstorm_eth_hw_conn_ag_ctx { 5709 u8 reserved0; 5710 u8 eth_state; 5711 u8 flags0; 5712 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 5713 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 5714 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_MASK 0x1 5715 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED1_SHIFT 1 5716 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_MASK 0x1 5717 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED2_SHIFT 2 5718 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 5719 #define XSTORM_ETH_HW_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 5720 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_MASK 0x1 5721 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED3_SHIFT 4 5722 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_MASK 0x1 5723 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED4_SHIFT 5 5724 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_MASK 0x1 5725 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED5_SHIFT 6 5726 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_MASK 0x1 5727 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED6_SHIFT 7 5728 u8 flags1; 5729 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_MASK 0x1 5730 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED7_SHIFT 0 5731 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_MASK 0x1 5732 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED8_SHIFT 1 5733 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_MASK 0x1 5734 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED9_SHIFT 2 5735 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_MASK 0x1 5736 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT11_SHIFT 3 5737 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_MASK 0x1 5738 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT12_SHIFT 4 5739 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_MASK 0x1 5740 #define XSTORM_ETH_HW_CONN_AG_CTX_BIT13_SHIFT 5 5741 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 5742 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 5743 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 5744 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 5745 u8 flags2; 5746 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_MASK 0x3 5747 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0_SHIFT 0 5748 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_MASK 0x3 5749 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1_SHIFT 2 5750 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_MASK 0x3 5751 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2_SHIFT 4 5752 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_MASK 0x3 5753 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3_SHIFT 6 5754 u8 flags3; 5755 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_MASK 0x3 5756 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4_SHIFT 0 5757 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_MASK 0x3 5758 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5_SHIFT 2 5759 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_MASK 0x3 5760 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6_SHIFT 4 5761 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_MASK 0x3 5762 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7_SHIFT 6 5763 u8 flags4; 5764 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_MASK 0x3 5765 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8_SHIFT 0 5766 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_MASK 0x3 5767 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9_SHIFT 2 5768 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_MASK 0x3 5769 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10_SHIFT 4 5770 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_MASK 0x3 5771 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11_SHIFT 6 5772 u8 flags5; 5773 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_MASK 0x3 5774 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12_SHIFT 0 5775 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_MASK 0x3 5776 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13_SHIFT 2 5777 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_MASK 0x3 5778 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14_SHIFT 4 5779 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_MASK 0x3 5780 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15_SHIFT 6 5781 u8 flags6; 5782 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_MASK 0x3 5783 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_SHIFT 0 5784 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_MASK 0x3 5785 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_SHIFT 2 5786 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_MASK 0x3 5787 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_SHIFT 4 5788 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 5789 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 5790 u8 flags7; 5791 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 5792 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 5793 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_MASK 0x3 5794 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED10_SHIFT 2 5795 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_MASK 0x3 5796 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_SHIFT 4 5797 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_MASK 0x1 5798 #define XSTORM_ETH_HW_CONN_AG_CTX_CF0EN_SHIFT 6 5799 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_MASK 0x1 5800 #define XSTORM_ETH_HW_CONN_AG_CTX_CF1EN_SHIFT 7 5801 u8 flags8; 5802 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_MASK 0x1 5803 #define XSTORM_ETH_HW_CONN_AG_CTX_CF2EN_SHIFT 0 5804 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_MASK 0x1 5805 #define XSTORM_ETH_HW_CONN_AG_CTX_CF3EN_SHIFT 1 5806 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_MASK 0x1 5807 #define XSTORM_ETH_HW_CONN_AG_CTX_CF4EN_SHIFT 2 5808 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_MASK 0x1 5809 #define XSTORM_ETH_HW_CONN_AG_CTX_CF5EN_SHIFT 3 5810 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_MASK 0x1 5811 #define XSTORM_ETH_HW_CONN_AG_CTX_CF6EN_SHIFT 4 5812 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_MASK 0x1 5813 #define XSTORM_ETH_HW_CONN_AG_CTX_CF7EN_SHIFT 5 5814 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_MASK 0x1 5815 #define XSTORM_ETH_HW_CONN_AG_CTX_CF8EN_SHIFT 6 5816 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_MASK 0x1 5817 #define XSTORM_ETH_HW_CONN_AG_CTX_CF9EN_SHIFT 7 5818 u8 flags9; 5819 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_MASK 0x1 5820 #define XSTORM_ETH_HW_CONN_AG_CTX_CF10EN_SHIFT 0 5821 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_MASK 0x1 5822 #define XSTORM_ETH_HW_CONN_AG_CTX_CF11EN_SHIFT 1 5823 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_MASK 0x1 5824 #define XSTORM_ETH_HW_CONN_AG_CTX_CF12EN_SHIFT 2 5825 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_MASK 0x1 5826 #define XSTORM_ETH_HW_CONN_AG_CTX_CF13EN_SHIFT 3 5827 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_MASK 0x1 5828 #define XSTORM_ETH_HW_CONN_AG_CTX_CF14EN_SHIFT 4 5829 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_MASK 0x1 5830 #define XSTORM_ETH_HW_CONN_AG_CTX_CF15EN_SHIFT 5 5831 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_MASK 0x1 5832 #define XSTORM_ETH_HW_CONN_AG_CTX_GO_TO_BD_CONS_CF_EN_SHIFT 6 5833 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_MASK 0x1 5834 #define XSTORM_ETH_HW_CONN_AG_CTX_MULTI_UNICAST_CF_EN_SHIFT 7 5835 u8 flags10; 5836 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 5837 #define XSTORM_ETH_HW_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 5838 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 5839 #define XSTORM_ETH_HW_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 5840 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 5841 #define XSTORM_ETH_HW_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 5842 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_MASK 0x1 5843 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED11_SHIFT 3 5844 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 5845 #define XSTORM_ETH_HW_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 5846 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_MASK 0x1 5847 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_EN_RESERVED_SHIFT 5 5848 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_MASK 0x1 5849 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED12_SHIFT 6 5850 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_MASK 0x1 5851 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED13_SHIFT 7 5852 u8 flags11; 5853 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_MASK 0x1 5854 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED14_SHIFT 0 5855 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_MASK 0x1 5856 #define XSTORM_ETH_HW_CONN_AG_CTX_RESERVED15_SHIFT 1 5857 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 5858 #define XSTORM_ETH_HW_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 5859 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_MASK 0x1 5860 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE5EN_SHIFT 3 5861 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_MASK 0x1 5862 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE6EN_SHIFT 4 5863 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_MASK 0x1 5864 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE7EN_SHIFT 5 5865 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 5866 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 5867 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_MASK 0x1 5868 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE9EN_SHIFT 7 5869 u8 flags12; 5870 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_MASK 0x1 5871 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE10EN_SHIFT 0 5872 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_MASK 0x1 5873 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE11EN_SHIFT 1 5874 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 5875 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 5876 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 5877 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 5878 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_MASK 0x1 5879 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE14EN_SHIFT 4 5880 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_MASK 0x1 5881 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE15EN_SHIFT 5 5882 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_MASK 0x1 5883 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE16EN_SHIFT 6 5884 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_MASK 0x1 5885 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE17EN_SHIFT 7 5886 u8 flags13; 5887 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_MASK 0x1 5888 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE18EN_SHIFT 0 5889 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_MASK 0x1 5890 #define XSTORM_ETH_HW_CONN_AG_CTX_RULE19EN_SHIFT 1 5891 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 5892 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 5893 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 5894 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 5895 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 5896 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 5897 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 5898 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 5899 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 5900 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 5901 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 5902 #define XSTORM_ETH_HW_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 5903 u8 flags14; 5904 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_MASK 0x1 5905 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_USE_EXT_HDR_SHIFT 0 5906 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_MASK 0x1 5907 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_RAW_L3L4_SHIFT 1 5908 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_MASK 0x1 5909 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_INBAND_PROP_HDR_SHIFT 2 5910 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_MASK 0x1 5911 #define XSTORM_ETH_HW_CONN_AG_CTX_EDPM_SEND_EXT_TUNNEL_SHIFT 3 5912 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_MASK 0x1 5913 #define XSTORM_ETH_HW_CONN_AG_CTX_L2_EDPM_ENABLE_SHIFT 4 5914 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 5915 #define XSTORM_ETH_HW_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 5916 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_MASK 0x3 5917 #define XSTORM_ETH_HW_CONN_AG_CTX_TPH_ENABLE_SHIFT 6 5918 u8 edpm_event_id; 5919 __le16 physical_q0; 5920 __le16 ereserved1; 5921 __le16 edpm_num_bds; 5922 __le16 tx_bd_cons; 5923 __le16 tx_bd_prod; 5924 __le16 tx_class; 5925 __le16 conn_dpi; 5926 }; 5927 5928 struct gft_cam_line { 5929 __le32 camline; 5930 #define GFT_CAM_LINE_VALID_MASK 0x1 5931 #define GFT_CAM_LINE_VALID_SHIFT 0 5932 #define GFT_CAM_LINE_DATA_MASK 0x3FFF 5933 #define GFT_CAM_LINE_DATA_SHIFT 1 5934 #define GFT_CAM_LINE_MASK_BITS_MASK 0x3FFF 5935 #define GFT_CAM_LINE_MASK_BITS_SHIFT 15 5936 #define GFT_CAM_LINE_RESERVED1_MASK 0x7 5937 #define GFT_CAM_LINE_RESERVED1_SHIFT 29 5938 }; 5939 5940 struct gft_cam_line_mapped { 5941 __le32 camline; 5942 #define GFT_CAM_LINE_MAPPED_VALID_MASK 0x1 5943 #define GFT_CAM_LINE_MAPPED_VALID_SHIFT 0 5944 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK 0x1 5945 #define GFT_CAM_LINE_MAPPED_IP_VERSION_SHIFT 1 5946 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK 0x1 5947 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_SHIFT 2 5948 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK 0xF 5949 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_SHIFT 3 5950 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK 0xF 5951 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_SHIFT 7 5952 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK 0xF 5953 #define GFT_CAM_LINE_MAPPED_PF_ID_SHIFT 11 5954 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_MASK 0x1 5955 #define GFT_CAM_LINE_MAPPED_IP_VERSION_MASK_SHIFT 15 5956 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_MASK 0x1 5957 #define GFT_CAM_LINE_MAPPED_TUNNEL_IP_VERSION_MASK_SHIFT 16 5958 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK 0xF 5959 #define GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_SHIFT 17 5960 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_MASK 0xF 5961 #define GFT_CAM_LINE_MAPPED_TUNNEL_TYPE_MASK_SHIFT 21 5962 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK 0xF 5963 #define GFT_CAM_LINE_MAPPED_PF_ID_MASK_SHIFT 25 5964 #define GFT_CAM_LINE_MAPPED_RESERVED1_MASK 0x7 5965 #define GFT_CAM_LINE_MAPPED_RESERVED1_SHIFT 29 5966 }; 5967 5968 union gft_cam_line_union { 5969 struct gft_cam_line cam_line; 5970 struct gft_cam_line_mapped cam_line_mapped; 5971 }; 5972 5973 enum gft_profile_ip_version { 5974 GFT_PROFILE_IPV4 = 0, 5975 GFT_PROFILE_IPV6 = 1, 5976 MAX_GFT_PROFILE_IP_VERSION 5977 }; 5978 5979 struct gft_profile_key { 5980 __le16 profile_key; 5981 #define GFT_PROFILE_KEY_IP_VERSION_MASK 0x1 5982 #define GFT_PROFILE_KEY_IP_VERSION_SHIFT 0 5983 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_MASK 0x1 5984 #define GFT_PROFILE_KEY_TUNNEL_IP_VERSION_SHIFT 1 5985 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_MASK 0xF 5986 #define GFT_PROFILE_KEY_UPPER_PROTOCOL_TYPE_SHIFT 2 5987 #define GFT_PROFILE_KEY_TUNNEL_TYPE_MASK 0xF 5988 #define GFT_PROFILE_KEY_TUNNEL_TYPE_SHIFT 6 5989 #define GFT_PROFILE_KEY_PF_ID_MASK 0xF 5990 #define GFT_PROFILE_KEY_PF_ID_SHIFT 10 5991 #define GFT_PROFILE_KEY_RESERVED0_MASK 0x3 5992 #define GFT_PROFILE_KEY_RESERVED0_SHIFT 14 5993 }; 5994 5995 enum gft_profile_tunnel_type { 5996 GFT_PROFILE_NO_TUNNEL = 0, 5997 GFT_PROFILE_VXLAN_TUNNEL = 1, 5998 GFT_PROFILE_GRE_MAC_OR_NVGRE_TUNNEL = 2, 5999 GFT_PROFILE_GRE_IP_TUNNEL = 3, 6000 GFT_PROFILE_GENEVE_MAC_TUNNEL = 4, 6001 GFT_PROFILE_GENEVE_IP_TUNNEL = 5, 6002 MAX_GFT_PROFILE_TUNNEL_TYPE 6003 }; 6004 6005 enum gft_profile_upper_protocol_type { 6006 GFT_PROFILE_ROCE_PROTOCOL = 0, 6007 GFT_PROFILE_RROCE_PROTOCOL = 1, 6008 GFT_PROFILE_FCOE_PROTOCOL = 2, 6009 GFT_PROFILE_ICMP_PROTOCOL = 3, 6010 GFT_PROFILE_ARP_PROTOCOL = 4, 6011 GFT_PROFILE_USER_TCP_SRC_PORT_1_INNER = 5, 6012 GFT_PROFILE_USER_TCP_DST_PORT_1_INNER = 6, 6013 GFT_PROFILE_TCP_PROTOCOL = 7, 6014 GFT_PROFILE_USER_UDP_DST_PORT_1_INNER = 8, 6015 GFT_PROFILE_USER_UDP_DST_PORT_2_OUTER = 9, 6016 GFT_PROFILE_UDP_PROTOCOL = 10, 6017 GFT_PROFILE_USER_IP_1_INNER = 11, 6018 GFT_PROFILE_USER_IP_2_OUTER = 12, 6019 GFT_PROFILE_USER_ETH_1_INNER = 13, 6020 GFT_PROFILE_USER_ETH_2_OUTER = 14, 6021 GFT_PROFILE_RAW = 15, 6022 MAX_GFT_PROFILE_UPPER_PROTOCOL_TYPE 6023 }; 6024 6025 struct gft_ram_line { 6026 __le32 lo; 6027 #define GFT_RAM_LINE_VLAN_SELECT_MASK 0x3 6028 #define GFT_RAM_LINE_VLAN_SELECT_SHIFT 0 6029 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_MASK 0x1 6030 #define GFT_RAM_LINE_TUNNEL_ENTROPHY_SHIFT 2 6031 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_MASK 0x1 6032 #define GFT_RAM_LINE_TUNNEL_TTL_EQUAL_ONE_SHIFT 3 6033 #define GFT_RAM_LINE_TUNNEL_TTL_MASK 0x1 6034 #define GFT_RAM_LINE_TUNNEL_TTL_SHIFT 4 6035 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_MASK 0x1 6036 #define GFT_RAM_LINE_TUNNEL_ETHERTYPE_SHIFT 5 6037 #define GFT_RAM_LINE_TUNNEL_DST_PORT_MASK 0x1 6038 #define GFT_RAM_LINE_TUNNEL_DST_PORT_SHIFT 6 6039 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_MASK 0x1 6040 #define GFT_RAM_LINE_TUNNEL_SRC_PORT_SHIFT 7 6041 #define GFT_RAM_LINE_TUNNEL_DSCP_MASK 0x1 6042 #define GFT_RAM_LINE_TUNNEL_DSCP_SHIFT 8 6043 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_MASK 0x1 6044 #define GFT_RAM_LINE_TUNNEL_OVER_IP_PROTOCOL_SHIFT 9 6045 #define GFT_RAM_LINE_TUNNEL_DST_IP_MASK 0x1 6046 #define GFT_RAM_LINE_TUNNEL_DST_IP_SHIFT 10 6047 #define GFT_RAM_LINE_TUNNEL_SRC_IP_MASK 0x1 6048 #define GFT_RAM_LINE_TUNNEL_SRC_IP_SHIFT 11 6049 #define GFT_RAM_LINE_TUNNEL_PRIORITY_MASK 0x1 6050 #define GFT_RAM_LINE_TUNNEL_PRIORITY_SHIFT 12 6051 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_MASK 0x1 6052 #define GFT_RAM_LINE_TUNNEL_PROVIDER_VLAN_SHIFT 13 6053 #define GFT_RAM_LINE_TUNNEL_VLAN_MASK 0x1 6054 #define GFT_RAM_LINE_TUNNEL_VLAN_SHIFT 14 6055 #define GFT_RAM_LINE_TUNNEL_DST_MAC_MASK 0x1 6056 #define GFT_RAM_LINE_TUNNEL_DST_MAC_SHIFT 15 6057 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_MASK 0x1 6058 #define GFT_RAM_LINE_TUNNEL_SRC_MAC_SHIFT 16 6059 #define GFT_RAM_LINE_TTL_EQUAL_ONE_MASK 0x1 6060 #define GFT_RAM_LINE_TTL_EQUAL_ONE_SHIFT 17 6061 #define GFT_RAM_LINE_TTL_MASK 0x1 6062 #define GFT_RAM_LINE_TTL_SHIFT 18 6063 #define GFT_RAM_LINE_ETHERTYPE_MASK 0x1 6064 #define GFT_RAM_LINE_ETHERTYPE_SHIFT 19 6065 #define GFT_RAM_LINE_RESERVED0_MASK 0x1 6066 #define GFT_RAM_LINE_RESERVED0_SHIFT 20 6067 #define GFT_RAM_LINE_TCP_FLAG_FIN_MASK 0x1 6068 #define GFT_RAM_LINE_TCP_FLAG_FIN_SHIFT 21 6069 #define GFT_RAM_LINE_TCP_FLAG_SYN_MASK 0x1 6070 #define GFT_RAM_LINE_TCP_FLAG_SYN_SHIFT 22 6071 #define GFT_RAM_LINE_TCP_FLAG_RST_MASK 0x1 6072 #define GFT_RAM_LINE_TCP_FLAG_RST_SHIFT 23 6073 #define GFT_RAM_LINE_TCP_FLAG_PSH_MASK 0x1 6074 #define GFT_RAM_LINE_TCP_FLAG_PSH_SHIFT 24 6075 #define GFT_RAM_LINE_TCP_FLAG_ACK_MASK 0x1 6076 #define GFT_RAM_LINE_TCP_FLAG_ACK_SHIFT 25 6077 #define GFT_RAM_LINE_TCP_FLAG_URG_MASK 0x1 6078 #define GFT_RAM_LINE_TCP_FLAG_URG_SHIFT 26 6079 #define GFT_RAM_LINE_TCP_FLAG_ECE_MASK 0x1 6080 #define GFT_RAM_LINE_TCP_FLAG_ECE_SHIFT 27 6081 #define GFT_RAM_LINE_TCP_FLAG_CWR_MASK 0x1 6082 #define GFT_RAM_LINE_TCP_FLAG_CWR_SHIFT 28 6083 #define GFT_RAM_LINE_TCP_FLAG_NS_MASK 0x1 6084 #define GFT_RAM_LINE_TCP_FLAG_NS_SHIFT 29 6085 #define GFT_RAM_LINE_DST_PORT_MASK 0x1 6086 #define GFT_RAM_LINE_DST_PORT_SHIFT 30 6087 #define GFT_RAM_LINE_SRC_PORT_MASK 0x1 6088 #define GFT_RAM_LINE_SRC_PORT_SHIFT 31 6089 __le32 hi; 6090 #define GFT_RAM_LINE_DSCP_MASK 0x1 6091 #define GFT_RAM_LINE_DSCP_SHIFT 0 6092 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_MASK 0x1 6093 #define GFT_RAM_LINE_OVER_IP_PROTOCOL_SHIFT 1 6094 #define GFT_RAM_LINE_DST_IP_MASK 0x1 6095 #define GFT_RAM_LINE_DST_IP_SHIFT 2 6096 #define GFT_RAM_LINE_SRC_IP_MASK 0x1 6097 #define GFT_RAM_LINE_SRC_IP_SHIFT 3 6098 #define GFT_RAM_LINE_PRIORITY_MASK 0x1 6099 #define GFT_RAM_LINE_PRIORITY_SHIFT 4 6100 #define GFT_RAM_LINE_PROVIDER_VLAN_MASK 0x1 6101 #define GFT_RAM_LINE_PROVIDER_VLAN_SHIFT 5 6102 #define GFT_RAM_LINE_VLAN_MASK 0x1 6103 #define GFT_RAM_LINE_VLAN_SHIFT 6 6104 #define GFT_RAM_LINE_DST_MAC_MASK 0x1 6105 #define GFT_RAM_LINE_DST_MAC_SHIFT 7 6106 #define GFT_RAM_LINE_SRC_MAC_MASK 0x1 6107 #define GFT_RAM_LINE_SRC_MAC_SHIFT 8 6108 #define GFT_RAM_LINE_TENANT_ID_MASK 0x1 6109 #define GFT_RAM_LINE_TENANT_ID_SHIFT 9 6110 #define GFT_RAM_LINE_RESERVED1_MASK 0x3FFFFF 6111 #define GFT_RAM_LINE_RESERVED1_SHIFT 10 6112 }; 6113 6114 enum gft_vlan_select { 6115 INNER_PROVIDER_VLAN = 0, 6116 INNER_VLAN = 1, 6117 OUTER_PROVIDER_VLAN = 2, 6118 OUTER_VLAN = 3, 6119 MAX_GFT_VLAN_SELECT 6120 }; 6121 6122 struct mstorm_rdma_task_st_ctx { 6123 struct regpair temp[4]; 6124 }; 6125 6126 struct rdma_close_func_ramrod_data { 6127 u8 cnq_start_offset; 6128 u8 num_cnqs; 6129 u8 vf_id; 6130 u8 vf_valid; 6131 u8 reserved[4]; 6132 }; 6133 6134 struct rdma_cnq_params { 6135 __le16 sb_num; 6136 u8 sb_index; 6137 u8 num_pbl_pages; 6138 __le32 reserved; 6139 struct regpair pbl_base_addr; 6140 __le16 queue_zone_num; 6141 u8 reserved1[6]; 6142 }; 6143 6144 struct rdma_create_cq_ramrod_data { 6145 struct regpair cq_handle; 6146 struct regpair pbl_addr; 6147 __le32 max_cqes; 6148 __le16 pbl_num_pages; 6149 __le16 dpi; 6150 u8 is_two_level_pbl; 6151 u8 cnq_id; 6152 u8 pbl_log_page_size; 6153 u8 toggle_bit; 6154 __le16 int_timeout; 6155 __le16 reserved1; 6156 }; 6157 6158 struct rdma_deregister_tid_ramrod_data { 6159 __le32 itid; 6160 __le32 reserved; 6161 }; 6162 6163 struct rdma_destroy_cq_output_params { 6164 __le16 cnq_num; 6165 __le16 reserved0; 6166 __le32 reserved1; 6167 }; 6168 6169 struct rdma_destroy_cq_ramrod_data { 6170 struct regpair output_params_addr; 6171 }; 6172 6173 enum rdma_event_opcode { 6174 RDMA_EVENT_UNUSED, 6175 RDMA_EVENT_FUNC_INIT, 6176 RDMA_EVENT_FUNC_CLOSE, 6177 RDMA_EVENT_REGISTER_MR, 6178 RDMA_EVENT_DEREGISTER_MR, 6179 RDMA_EVENT_CREATE_CQ, 6180 RDMA_EVENT_RESIZE_CQ, 6181 RDMA_EVENT_DESTROY_CQ, 6182 RDMA_EVENT_CREATE_SRQ, 6183 RDMA_EVENT_MODIFY_SRQ, 6184 RDMA_EVENT_DESTROY_SRQ, 6185 MAX_RDMA_EVENT_OPCODE 6186 }; 6187 6188 enum rdma_fw_return_code { 6189 RDMA_RETURN_OK = 0, 6190 RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR, 6191 RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR, 6192 RDMA_RETURN_RESIZE_CQ_ERR, 6193 RDMA_RETURN_NIG_DRAIN_REQ, 6194 MAX_RDMA_FW_RETURN_CODE 6195 }; 6196 6197 struct rdma_init_func_hdr { 6198 u8 cnq_start_offset; 6199 u8 num_cnqs; 6200 u8 cq_ring_mode; 6201 u8 vf_id; 6202 u8 vf_valid; 6203 u8 reserved[3]; 6204 }; 6205 6206 struct rdma_init_func_ramrod_data { 6207 struct rdma_init_func_hdr params_header; 6208 struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES]; 6209 }; 6210 6211 enum rdma_ramrod_cmd_id { 6212 RDMA_RAMROD_UNUSED, 6213 RDMA_RAMROD_FUNC_INIT, 6214 RDMA_RAMROD_FUNC_CLOSE, 6215 RDMA_RAMROD_REGISTER_MR, 6216 RDMA_RAMROD_DEREGISTER_MR, 6217 RDMA_RAMROD_CREATE_CQ, 6218 RDMA_RAMROD_RESIZE_CQ, 6219 RDMA_RAMROD_DESTROY_CQ, 6220 RDMA_RAMROD_CREATE_SRQ, 6221 RDMA_RAMROD_MODIFY_SRQ, 6222 RDMA_RAMROD_DESTROY_SRQ, 6223 MAX_RDMA_RAMROD_CMD_ID 6224 }; 6225 6226 struct rdma_register_tid_ramrod_data { 6227 __le16 flags; 6228 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK 0x1F 6229 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT 0 6230 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1 6231 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT 5 6232 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1 6233 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT 6 6234 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1 6235 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT 7 6236 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1 6237 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT 8 6238 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1 6239 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT 9 6240 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1 6241 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT 10 6242 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1 6243 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT 11 6244 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1 6245 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT 12 6246 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1 6247 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT 13 6248 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK 0x3 6249 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_SHIFT 14 6250 u8 flags1; 6251 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK 0x1F 6252 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0 6253 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK 0x7 6254 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT 5 6255 u8 flags2; 6256 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1 6257 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT 0 6258 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK 0x1 6259 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT 1 6260 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK 0x3F 6261 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT 2 6262 u8 key; 6263 u8 length_hi; 6264 u8 vf_id; 6265 u8 vf_valid; 6266 __le16 pd; 6267 __le16 reserved2; 6268 __le32 length_lo; 6269 __le32 itid; 6270 __le32 reserved3; 6271 struct regpair va; 6272 struct regpair pbl_base; 6273 struct regpair dif_error_addr; 6274 struct regpair dif_runt_addr; 6275 __le32 reserved4[2]; 6276 }; 6277 6278 struct rdma_resize_cq_output_params { 6279 __le32 old_cq_cons; 6280 __le32 old_cq_prod; 6281 }; 6282 6283 struct rdma_resize_cq_ramrod_data { 6284 u8 flags; 6285 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1 6286 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0 6287 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1 6288 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1 6289 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x3F 6290 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 2 6291 u8 pbl_log_page_size; 6292 __le16 pbl_num_pages; 6293 __le32 max_cqes; 6294 struct regpair pbl_addr; 6295 struct regpair output_params_addr; 6296 }; 6297 6298 struct rdma_srq_context { 6299 struct regpair temp[8]; 6300 }; 6301 6302 struct rdma_srq_create_ramrod_data { 6303 struct regpair pbl_base_addr; 6304 __le16 pages_in_srq_pbl; 6305 __le16 pd_id; 6306 struct rdma_srq_id srq_id; 6307 __le16 page_size; 6308 __le16 reserved1; 6309 __le32 reserved2; 6310 struct regpair producers_addr; 6311 }; 6312 6313 struct rdma_srq_destroy_ramrod_data { 6314 struct rdma_srq_id srq_id; 6315 __le32 reserved; 6316 }; 6317 6318 struct rdma_srq_modify_ramrod_data { 6319 struct rdma_srq_id srq_id; 6320 __le32 wqe_limit; 6321 }; 6322 6323 struct ystorm_rdma_task_st_ctx { 6324 struct regpair temp[4]; 6325 }; 6326 6327 struct ystorm_rdma_task_ag_ctx { 6328 u8 reserved; 6329 u8 byte1; 6330 __le16 msem_ctx_upd_seq; 6331 u8 flags0; 6332 #define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF 6333 #define YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 6334 #define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 6335 #define YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 6336 #define YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 6337 #define YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 6338 #define YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1 6339 #define YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6 6340 #define YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 6341 #define YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 6342 u8 flags1; 6343 #define YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 6344 #define YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 6345 #define YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 6346 #define YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 6347 #define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 6348 #define YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4 6349 #define YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 6350 #define YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 6351 #define YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 6352 #define YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 6353 u8 flags2; 6354 #define YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 6355 #define YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 6356 #define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 6357 #define YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 6358 #define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 6359 #define YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 6360 #define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 6361 #define YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 6362 #define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 6363 #define YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 6364 #define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 6365 #define YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 6366 #define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 6367 #define YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 6368 #define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 6369 #define YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 6370 u8 key; 6371 __le32 mw_cnt; 6372 u8 ref_cnt_seq; 6373 u8 ctx_upd_seq; 6374 __le16 dif_flags; 6375 __le16 tx_ref_count; 6376 __le16 last_used_ltid; 6377 __le16 parent_mr_lo; 6378 __le16 parent_mr_hi; 6379 __le32 fbo_lo; 6380 __le32 fbo_hi; 6381 }; 6382 6383 struct mstorm_rdma_task_ag_ctx { 6384 u8 reserved; 6385 u8 byte1; 6386 __le16 icid; 6387 u8 flags0; 6388 #define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF 6389 #define MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 6390 #define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 6391 #define MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 6392 #define MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 6393 #define MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 6394 #define MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 6395 #define MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 6396 #define MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 6397 #define MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 6398 u8 flags1; 6399 #define MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 6400 #define MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 6401 #define MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 6402 #define MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 6403 #define MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 6404 #define MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4 6405 #define MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 6406 #define MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 6407 #define MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 6408 #define MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 6409 u8 flags2; 6410 #define MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 6411 #define MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0 6412 #define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 6413 #define MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 6414 #define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 6415 #define MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 6416 #define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 6417 #define MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 6418 #define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 6419 #define MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 6420 #define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 6421 #define MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 6422 #define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 6423 #define MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 6424 #define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 6425 #define MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 6426 u8 key; 6427 __le32 mw_cnt; 6428 u8 ref_cnt_seq; 6429 u8 ctx_upd_seq; 6430 __le16 dif_flags; 6431 __le16 tx_ref_count; 6432 __le16 last_used_ltid; 6433 __le16 parent_mr_lo; 6434 __le16 parent_mr_hi; 6435 __le32 fbo_lo; 6436 __le32 fbo_hi; 6437 }; 6438 6439 struct ustorm_rdma_task_st_ctx { 6440 struct regpair temp[2]; 6441 }; 6442 6443 struct ustorm_rdma_task_ag_ctx { 6444 u8 reserved; 6445 u8 byte1; 6446 __le16 icid; 6447 u8 flags0; 6448 #define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF 6449 #define USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 6450 #define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 6451 #define USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 6452 #define USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1 6453 #define USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5 6454 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3 6455 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6 6456 u8 flags1; 6457 #define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3 6458 #define USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0 6459 #define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3 6460 #define USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2 6461 #define USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 6462 #define USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 4 6463 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 6464 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6 6465 u8 flags2; 6466 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1 6467 #define USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0 6468 #define USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1 6469 #define USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1 6470 #define USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1 6471 #define USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2 6472 #define USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 6473 #define USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 3 6474 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 6475 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4 6476 #define USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 6477 #define USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5 6478 #define USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 6479 #define USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6 6480 #define USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 6481 #define USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7 6482 u8 flags3; 6483 #define USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 6484 #define USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0 6485 #define USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 6486 #define USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1 6487 #define USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 6488 #define USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2 6489 #define USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 6490 #define USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3 6491 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF 6492 #define USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4 6493 __le32 dif_err_intervals; 6494 __le32 dif_error_1st_interval; 6495 __le32 reg2; 6496 __le32 dif_runt_value; 6497 __le32 reg4; 6498 __le32 reg5; 6499 }; 6500 6501 struct rdma_task_context { 6502 struct ystorm_rdma_task_st_ctx ystorm_st_context; 6503 struct ystorm_rdma_task_ag_ctx ystorm_ag_context; 6504 struct tdif_task_context tdif_context; 6505 struct mstorm_rdma_task_ag_ctx mstorm_ag_context; 6506 struct mstorm_rdma_task_st_ctx mstorm_st_context; 6507 struct rdif_task_context rdif_context; 6508 struct ustorm_rdma_task_st_ctx ustorm_st_context; 6509 struct regpair ustorm_st_padding[2]; 6510 struct ustorm_rdma_task_ag_ctx ustorm_ag_context; 6511 }; 6512 6513 enum rdma_tid_type { 6514 RDMA_TID_REGISTERED_MR, 6515 RDMA_TID_FMR, 6516 RDMA_TID_MW_TYPE1, 6517 RDMA_TID_MW_TYPE2A, 6518 MAX_RDMA_TID_TYPE 6519 }; 6520 6521 struct xstorm_roce_conn_ag_ctx_dq_ext_ld_part { 6522 u8 reserved0; 6523 u8 state; 6524 u8 flags0; 6525 #define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 6526 #define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 6527 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1 6528 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1 6529 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1 6530 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2 6531 #define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 6532 #define XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 6533 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1 6534 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4 6535 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1 6536 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5 6537 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1 6538 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6 6539 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1 6540 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7 6541 u8 flags1; 6542 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1 6543 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0 6544 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1 6545 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1 6546 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1 6547 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2 6548 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 6549 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 6550 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1 6551 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4 6552 #define XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_MASK 0x1 6553 #define XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_SHIFT 5 6554 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1 6555 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6 6556 #define XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1 6557 #define XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7 6558 u8 flags2; 6559 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3 6560 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0 6561 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3 6562 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2 6563 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3 6564 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4 6565 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3 6566 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6 6567 u8 flags3; 6568 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3 6569 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0 6570 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3 6571 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2 6572 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3 6573 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4 6574 #define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3 6575 #define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6 6576 u8 flags4; 6577 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3 6578 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0 6579 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3 6580 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2 6581 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3 6582 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4 6583 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3 6584 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6 6585 u8 flags5; 6586 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3 6587 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0 6588 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3 6589 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2 6590 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3 6591 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4 6592 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3 6593 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6 6594 u8 flags6; 6595 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3 6596 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0 6597 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3 6598 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2 6599 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3 6600 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4 6601 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3 6602 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6 6603 u8 flags7; 6604 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3 6605 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0 6606 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3 6607 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2 6608 #define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 6609 #define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 6610 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 6611 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 6612 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 6613 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 6614 u8 flags8; 6615 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 6616 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 6617 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 6618 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 6619 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 6620 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 6621 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 6622 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 6623 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 6624 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 6625 #define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1 6626 #define XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5 6627 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 6628 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 6629 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 6630 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 6631 u8 flags9; 6632 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 6633 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 6634 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 6635 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 6636 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 6637 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 6638 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 6639 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 6640 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 6641 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 6642 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 6643 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 6644 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1 6645 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6 6646 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1 6647 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7 6648 u8 flags10; 6649 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1 6650 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0 6651 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1 6652 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1 6653 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1 6654 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2 6655 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1 6656 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3 6657 #define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 6658 #define XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 6659 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1 6660 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5 6661 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1 6662 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6 6663 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1 6664 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7 6665 u8 flags11; 6666 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1 6667 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0 6668 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1 6669 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1 6670 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1 6671 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2 6672 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 6673 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 6674 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 6675 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 6676 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 6677 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 6678 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 6679 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 6680 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 6681 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 6682 u8 flags12; 6683 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 6684 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 6685 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 6686 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 6687 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 6688 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 6689 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 6690 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 6691 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 6692 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 6693 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 6694 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 6695 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 6696 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 6697 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 6698 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 6699 u8 flags13; 6700 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 6701 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 6702 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 6703 #define XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 6704 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 6705 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 6706 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 6707 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 6708 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 6709 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 6710 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 6711 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 6712 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 6713 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 6714 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 6715 #define XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 6716 u8 flags14; 6717 #define XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1 6718 #define XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0 6719 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1 6720 #define XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1 6721 #define XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3 6722 #define XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2 6723 #define XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1 6724 #define XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4 6725 #define XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 6726 #define XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 6727 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3 6728 #define XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6 6729 u8 byte2; 6730 __le16 physical_q0; 6731 __le16 word1; 6732 __le16 word2; 6733 __le16 word3; 6734 __le16 word4; 6735 __le16 word5; 6736 __le16 conn_dpi; 6737 u8 byte3; 6738 u8 byte4; 6739 u8 byte5; 6740 u8 byte6; 6741 __le32 reg0; 6742 __le32 reg1; 6743 __le32 reg2; 6744 __le32 snd_nxt_psn; 6745 __le32 reg4; 6746 }; 6747 6748 struct mstorm_rdma_conn_ag_ctx { 6749 u8 byte0; 6750 u8 byte1; 6751 u8 flags0; 6752 #define MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 6753 #define MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0 6754 #define MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 6755 #define MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 6756 #define MSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 6757 #define MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2 6758 #define MSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 6759 #define MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 6760 #define MSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 6761 #define MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 6762 u8 flags1; 6763 #define MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 6764 #define MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0 6765 #define MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 6766 #define MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 6767 #define MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 6768 #define MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 6769 #define MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 6770 #define MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3 6771 #define MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 6772 #define MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4 6773 #define MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 6774 #define MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5 6775 #define MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 6776 #define MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6 6777 #define MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 6778 #define MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7 6779 __le16 word0; 6780 __le16 word1; 6781 __le32 reg0; 6782 __le32 reg1; 6783 }; 6784 6785 struct tstorm_rdma_conn_ag_ctx { 6786 u8 reserved0; 6787 u8 byte1; 6788 u8 flags0; 6789 #define TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 6790 #define TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 6791 #define TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 6792 #define TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 6793 #define TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 6794 #define TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2 6795 #define TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK 0x1 6796 #define TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT 3 6797 #define TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 6798 #define TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4 6799 #define TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 6800 #define TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5 6801 #define TSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 6802 #define TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 6 6803 u8 flags1; 6804 #define TSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 6805 #define TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 0 6806 #define TSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 6807 #define TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 2 6808 #define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 6809 #define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 6810 #define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 6811 #define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 6812 u8 flags2; 6813 #define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 6814 #define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 6815 #define TSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 6816 #define TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 2 6817 #define TSTORM_RDMA_CONN_AG_CTX_CF7_MASK 0x3 6818 #define TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT 4 6819 #define TSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 6820 #define TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 6 6821 u8 flags3; 6822 #define TSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 6823 #define TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 0 6824 #define TSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 6825 #define TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 2 6826 #define TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 6827 #define TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 4 6828 #define TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 6829 #define TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 5 6830 #define TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 6831 #define TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 6 6832 #define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 6833 #define TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 6834 u8 flags4; 6835 #define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 6836 #define TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 6837 #define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 6838 #define TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 6839 #define TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 6840 #define TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 2 6841 #define TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK 0x1 6842 #define TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT 3 6843 #define TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 6844 #define TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 4 6845 #define TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 6846 #define TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 5 6847 #define TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 6848 #define TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 6 6849 #define TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 6850 #define TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 7 6851 u8 flags5; 6852 #define TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 6853 #define TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 0 6854 #define TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 6855 #define TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 6856 #define TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 6857 #define TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 6858 #define TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 6859 #define TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 6860 #define TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 6861 #define TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 6862 #define TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 6863 #define TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 6864 #define TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 6865 #define TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 6866 #define TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 6867 #define TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 6868 __le32 reg0; 6869 __le32 reg1; 6870 __le32 reg2; 6871 __le32 reg3; 6872 __le32 reg4; 6873 __le32 reg5; 6874 __le32 reg6; 6875 __le32 reg7; 6876 __le32 reg8; 6877 u8 byte2; 6878 u8 byte3; 6879 __le16 word0; 6880 u8 byte4; 6881 u8 byte5; 6882 __le16 word1; 6883 __le16 word2; 6884 __le16 word3; 6885 __le32 reg9; 6886 __le32 reg10; 6887 }; 6888 6889 struct tstorm_rdma_task_ag_ctx { 6890 u8 byte0; 6891 u8 byte1; 6892 __le16 word0; 6893 u8 flags0; 6894 #define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF 6895 #define TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0 6896 #define TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1 6897 #define TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4 6898 #define TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 6899 #define TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 6900 #define TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 6901 #define TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 6902 #define TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 6903 #define TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 6904 u8 flags1; 6905 #define TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 6906 #define TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 6907 #define TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1 6908 #define TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1 6909 #define TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 6910 #define TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2 6911 #define TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 6912 #define TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4 6913 #define TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 6914 #define TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6 6915 u8 flags2; 6916 #define TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 6917 #define TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0 6918 #define TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3 6919 #define TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2 6920 #define TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3 6921 #define TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4 6922 #define TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3 6923 #define TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6 6924 u8 flags3; 6925 #define TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3 6926 #define TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0 6927 #define TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 6928 #define TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2 6929 #define TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 6930 #define TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3 6931 #define TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 6932 #define TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4 6933 #define TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 6934 #define TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5 6935 #define TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1 6936 #define TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6 6937 #define TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1 6938 #define TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7 6939 u8 flags4; 6940 #define TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1 6941 #define TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0 6942 #define TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1 6943 #define TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1 6944 #define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 6945 #define TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2 6946 #define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 6947 #define TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3 6948 #define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 6949 #define TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4 6950 #define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 6951 #define TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5 6952 #define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 6953 #define TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6 6954 #define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 6955 #define TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7 6956 u8 byte2; 6957 __le16 word1; 6958 __le32 reg0; 6959 u8 byte3; 6960 u8 byte4; 6961 __le16 word2; 6962 __le16 word3; 6963 __le16 word4; 6964 __le32 reg1; 6965 __le32 reg2; 6966 }; 6967 6968 struct ustorm_rdma_conn_ag_ctx { 6969 u8 reserved; 6970 u8 byte1; 6971 u8 flags0; 6972 #define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 6973 #define USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 6974 #define USTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 6975 #define USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 6976 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 6977 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2 6978 #define USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 6979 #define USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 6980 #define USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 6981 #define USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 6982 u8 flags1; 6983 #define USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 6984 #define USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0 6985 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 6986 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 6987 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 6988 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 6989 #define USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 6990 #define USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6 6991 u8 flags2; 6992 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 6993 #define USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 6994 #define USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 6995 #define USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 6996 #define USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 6997 #define USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 6998 #define USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 6999 #define USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3 7000 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 7001 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 7002 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 7003 #define USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 7004 #define USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 7005 #define USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6 7006 #define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 7007 #define USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 7008 u8 flags3; 7009 #define USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1 7010 #define USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0 7011 #define USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 7012 #define USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 7013 #define USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 7014 #define USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 7015 #define USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 7016 #define USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 7017 #define USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 7018 #define USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 7019 #define USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 7020 #define USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 7021 #define USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 7022 #define USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 7023 #define USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 7024 #define USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 7025 u8 byte2; 7026 u8 byte3; 7027 __le16 conn_dpi; 7028 __le16 word1; 7029 __le32 cq_cons; 7030 __le32 cq_se_prod; 7031 __le32 cq_prod; 7032 __le32 reg3; 7033 __le16 int_timeout; 7034 __le16 word3; 7035 }; 7036 7037 struct xstorm_rdma_conn_ag_ctx { 7038 u8 reserved0; 7039 u8 state; 7040 u8 flags0; 7041 #define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 7042 #define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 7043 #define XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 7044 #define XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 7045 #define XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 7046 #define XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2 7047 #define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 7048 #define XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 7049 #define XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 7050 #define XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4 7051 #define XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 7052 #define XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5 7053 #define XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK 0x1 7054 #define XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT 6 7055 #define XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK 0x1 7056 #define XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT 7 7057 u8 flags1; 7058 #define XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK 0x1 7059 #define XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT 0 7060 #define XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK 0x1 7061 #define XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT 1 7062 #define XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK 0x1 7063 #define XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT 2 7064 #define XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK 0x1 7065 #define XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT 3 7066 #define XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK 0x1 7067 #define XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT 4 7068 #define XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 7069 #define XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 5 7070 #define XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK 0x1 7071 #define XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT 6 7072 #define XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 7073 #define XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 7074 u8 flags2; 7075 #define XSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 7076 #define XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 0 7077 #define XSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 7078 #define XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 2 7079 #define XSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 7080 #define XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 4 7081 #define XSTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 7082 #define XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 6 7083 u8 flags3; 7084 #define XSTORM_RDMA_CONN_AG_CTX_CF4_MASK 0x3 7085 #define XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT 0 7086 #define XSTORM_RDMA_CONN_AG_CTX_CF5_MASK 0x3 7087 #define XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT 2 7088 #define XSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 7089 #define XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 4 7090 #define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 7091 #define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 7092 u8 flags4; 7093 #define XSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 7094 #define XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 0 7095 #define XSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 7096 #define XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 2 7097 #define XSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 7098 #define XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 4 7099 #define XSTORM_RDMA_CONN_AG_CTX_CF11_MASK 0x3 7100 #define XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT 6 7101 u8 flags5; 7102 #define XSTORM_RDMA_CONN_AG_CTX_CF12_MASK 0x3 7103 #define XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT 0 7104 #define XSTORM_RDMA_CONN_AG_CTX_CF13_MASK 0x3 7105 #define XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT 2 7106 #define XSTORM_RDMA_CONN_AG_CTX_CF14_MASK 0x3 7107 #define XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT 4 7108 #define XSTORM_RDMA_CONN_AG_CTX_CF15_MASK 0x3 7109 #define XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT 6 7110 u8 flags6; 7111 #define XSTORM_RDMA_CONN_AG_CTX_CF16_MASK 0x3 7112 #define XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT 0 7113 #define XSTORM_RDMA_CONN_AG_CTX_CF17_MASK 0x3 7114 #define XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT 2 7115 #define XSTORM_RDMA_CONN_AG_CTX_CF18_MASK 0x3 7116 #define XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT 4 7117 #define XSTORM_RDMA_CONN_AG_CTX_CF19_MASK 0x3 7118 #define XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT 6 7119 u8 flags7; 7120 #define XSTORM_RDMA_CONN_AG_CTX_CF20_MASK 0x3 7121 #define XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT 0 7122 #define XSTORM_RDMA_CONN_AG_CTX_CF21_MASK 0x3 7123 #define XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT 2 7124 #define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK 0x3 7125 #define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT 4 7126 #define XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 7127 #define XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 6 7128 #define XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 7129 #define XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 7 7130 u8 flags8; 7131 #define XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 7132 #define XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 0 7133 #define XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 7134 #define XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 1 7135 #define XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK 0x1 7136 #define XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT 2 7137 #define XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK 0x1 7138 #define XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT 3 7139 #define XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 7140 #define XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 4 7141 #define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 7142 #define XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 7143 #define XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 7144 #define XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 6 7145 #define XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 7146 #define XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 7 7147 u8 flags9; 7148 #define XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 7149 #define XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 0 7150 #define XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK 0x1 7151 #define XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT 1 7152 #define XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK 0x1 7153 #define XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT 2 7154 #define XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK 0x1 7155 #define XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT 3 7156 #define XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK 0x1 7157 #define XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT 4 7158 #define XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK 0x1 7159 #define XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT 5 7160 #define XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK 0x1 7161 #define XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT 6 7162 #define XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK 0x1 7163 #define XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT 7 7164 u8 flags10; 7165 #define XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK 0x1 7166 #define XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT 0 7167 #define XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK 0x1 7168 #define XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT 1 7169 #define XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK 0x1 7170 #define XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT 2 7171 #define XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK 0x1 7172 #define XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT 3 7173 #define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 7174 #define XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 7175 #define XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK 0x1 7176 #define XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT 5 7177 #define XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 7178 #define XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 6 7179 #define XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 7180 #define XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 7 7181 u8 flags11; 7182 #define XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 7183 #define XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 0 7184 #define XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 7185 #define XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 1 7186 #define XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 7187 #define XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 2 7188 #define XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 7189 #define XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 3 7190 #define XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 7191 #define XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 4 7192 #define XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 7193 #define XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 5 7194 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 7195 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 7196 #define XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK 0x1 7197 #define XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT 7 7198 u8 flags12; 7199 #define XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK 0x1 7200 #define XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT 0 7201 #define XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK 0x1 7202 #define XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT 1 7203 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 7204 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 7205 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 7206 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 7207 #define XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK 0x1 7208 #define XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT 4 7209 #define XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK 0x1 7210 #define XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT 5 7211 #define XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK 0x1 7212 #define XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT 6 7213 #define XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK 0x1 7214 #define XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT 7 7215 u8 flags13; 7216 #define XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK 0x1 7217 #define XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT 0 7218 #define XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK 0x1 7219 #define XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT 1 7220 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 7221 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 7222 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 7223 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 7224 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 7225 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 7226 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 7227 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 7228 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 7229 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 7230 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 7231 #define XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 7232 u8 flags14; 7233 #define XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK 0x1 7234 #define XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT 0 7235 #define XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK 0x1 7236 #define XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT 1 7237 #define XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 7238 #define XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 7239 #define XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK 0x1 7240 #define XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT 4 7241 #define XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 7242 #define XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 7243 #define XSTORM_RDMA_CONN_AG_CTX_CF23_MASK 0x3 7244 #define XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT 6 7245 u8 byte2; 7246 __le16 physical_q0; 7247 __le16 word1; 7248 __le16 word2; 7249 __le16 word3; 7250 __le16 word4; 7251 __le16 word5; 7252 __le16 conn_dpi; 7253 u8 byte3; 7254 u8 byte4; 7255 u8 byte5; 7256 u8 byte6; 7257 __le32 reg0; 7258 __le32 reg1; 7259 __le32 reg2; 7260 __le32 snd_nxt_psn; 7261 __le32 reg4; 7262 __le32 reg5; 7263 __le32 reg6; 7264 }; 7265 7266 struct ystorm_rdma_conn_ag_ctx { 7267 u8 byte0; 7268 u8 byte1; 7269 u8 flags0; 7270 #define YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 7271 #define YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0 7272 #define YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 7273 #define YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 7274 #define YSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 7275 #define YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2 7276 #define YSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 7277 #define YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 7278 #define YSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 7279 #define YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 7280 u8 flags1; 7281 #define YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 7282 #define YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0 7283 #define YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 7284 #define YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 7285 #define YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 7286 #define YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 7287 #define YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 7288 #define YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3 7289 #define YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 7290 #define YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4 7291 #define YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 7292 #define YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5 7293 #define YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 7294 #define YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6 7295 #define YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 7296 #define YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7 7297 u8 byte2; 7298 u8 byte3; 7299 __le16 word0; 7300 __le32 reg0; 7301 __le32 reg1; 7302 __le16 word1; 7303 __le16 word2; 7304 __le16 word3; 7305 __le16 word4; 7306 __le32 reg2; 7307 __le32 reg3; 7308 }; 7309 7310 struct mstorm_roce_conn_st_ctx { 7311 struct regpair temp[6]; 7312 }; 7313 7314 struct pstorm_roce_conn_st_ctx { 7315 struct regpair temp[16]; 7316 }; 7317 7318 struct ystorm_roce_conn_st_ctx { 7319 struct regpair temp[2]; 7320 }; 7321 7322 struct xstorm_roce_conn_st_ctx { 7323 struct regpair temp[24]; 7324 }; 7325 7326 struct tstorm_roce_conn_st_ctx { 7327 struct regpair temp[30]; 7328 }; 7329 7330 struct ustorm_roce_conn_st_ctx { 7331 struct regpair temp[12]; 7332 }; 7333 7334 struct roce_conn_context { 7335 struct ystorm_roce_conn_st_ctx ystorm_st_context; 7336 struct regpair ystorm_st_padding[2]; 7337 struct pstorm_roce_conn_st_ctx pstorm_st_context; 7338 struct xstorm_roce_conn_st_ctx xstorm_st_context; 7339 struct regpair xstorm_st_padding[2]; 7340 struct xstorm_rdma_conn_ag_ctx xstorm_ag_context; 7341 struct tstorm_rdma_conn_ag_ctx tstorm_ag_context; 7342 struct timers_context timer_context; 7343 struct ustorm_rdma_conn_ag_ctx ustorm_ag_context; 7344 struct tstorm_roce_conn_st_ctx tstorm_st_context; 7345 struct mstorm_roce_conn_st_ctx mstorm_st_context; 7346 struct ustorm_roce_conn_st_ctx ustorm_st_context; 7347 struct regpair ustorm_st_padding[2]; 7348 }; 7349 7350 struct roce_create_qp_req_ramrod_data { 7351 __le16 flags; 7352 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 7353 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0 7354 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1 7355 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 2 7356 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_MASK 0x1 7357 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_SIGNALED_COMP_SHIFT 3 7358 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_MASK 0x7 7359 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_PRI_SHIFT 4 7360 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_MASK 0x1 7361 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RESERVED_SHIFT 7 7362 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF 7363 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 8 7364 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF 7365 #define ROCE_CREATE_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 12 7366 u8 max_ord; 7367 u8 traffic_class; 7368 u8 hop_limit; 7369 u8 orq_num_pages; 7370 __le16 p_key; 7371 __le32 flow_label; 7372 __le32 dst_qp_id; 7373 __le32 ack_timeout_val; 7374 __le32 initial_psn; 7375 __le16 mtu; 7376 __le16 pd; 7377 __le16 sq_num_pages; 7378 __le16 low_latency_phy_queue; 7379 struct regpair sq_pbl_addr; 7380 struct regpair orq_pbl_addr; 7381 __le16 local_mac_addr[3]; 7382 __le16 remote_mac_addr[3]; 7383 __le16 vlan_id; 7384 __le16 udp_src_port; 7385 __le32 src_gid[4]; 7386 __le32 dst_gid[4]; 7387 struct regpair qp_handle_for_cqe; 7388 struct regpair qp_handle_for_async; 7389 u8 stats_counter_id; 7390 u8 reserved3[7]; 7391 __le32 cq_cid; 7392 __le16 regular_latency_phy_queue; 7393 __le16 dpi; 7394 }; 7395 7396 struct roce_create_qp_resp_ramrod_data { 7397 __le16 flags; 7398 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_MASK 0x3 7399 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ROCE_FLAVOR_SHIFT 0 7400 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 7401 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2 7402 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 7403 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3 7404 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 7405 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 4 7406 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_MASK 0x1 7407 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_SRQ_FLG_SHIFT 5 7408 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_MASK 0x1 7409 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_E2E_FLOW_CONTROL_EN_SHIFT 6 7410 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1 7411 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 7 7412 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_MASK 0x7 7413 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_PRI_SHIFT 8 7414 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F 7415 #define ROCE_CREATE_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 11 7416 u8 max_ird; 7417 u8 traffic_class; 7418 u8 hop_limit; 7419 u8 irq_num_pages; 7420 __le16 p_key; 7421 __le32 flow_label; 7422 __le32 dst_qp_id; 7423 u8 stats_counter_id; 7424 u8 reserved1; 7425 __le16 mtu; 7426 __le32 initial_psn; 7427 __le16 pd; 7428 __le16 rq_num_pages; 7429 struct rdma_srq_id srq_id; 7430 struct regpair rq_pbl_addr; 7431 struct regpair irq_pbl_addr; 7432 __le16 local_mac_addr[3]; 7433 __le16 remote_mac_addr[3]; 7434 __le16 vlan_id; 7435 __le16 udp_src_port; 7436 __le32 src_gid[4]; 7437 __le32 dst_gid[4]; 7438 struct regpair qp_handle_for_cqe; 7439 struct regpair qp_handle_for_async; 7440 __le16 low_latency_phy_queue; 7441 u8 reserved2[6]; 7442 __le32 cq_cid; 7443 __le16 regular_latency_phy_queue; 7444 __le16 dpi; 7445 }; 7446 7447 struct roce_destroy_qp_req_output_params { 7448 __le32 num_bound_mw; 7449 __le32 cq_prod; 7450 }; 7451 7452 struct roce_destroy_qp_req_ramrod_data { 7453 struct regpair output_params_addr; 7454 }; 7455 7456 struct roce_destroy_qp_resp_output_params { 7457 __le32 num_invalidated_mw; 7458 __le32 cq_prod; 7459 }; 7460 7461 struct roce_destroy_qp_resp_ramrod_data { 7462 struct regpair output_params_addr; 7463 }; 7464 7465 struct roce_events_stats { 7466 __le16 silent_drops; 7467 __le16 rnr_naks_sent; 7468 __le32 retransmit_count; 7469 __le32 icrc_error_count; 7470 __le32 reserved; 7471 }; 7472 7473 enum roce_event_opcode { 7474 ROCE_EVENT_CREATE_QP = 11, 7475 ROCE_EVENT_MODIFY_QP, 7476 ROCE_EVENT_QUERY_QP, 7477 ROCE_EVENT_DESTROY_QP, 7478 ROCE_EVENT_CREATE_UD_QP, 7479 ROCE_EVENT_DESTROY_UD_QP, 7480 MAX_ROCE_EVENT_OPCODE 7481 }; 7482 7483 struct roce_init_func_params { 7484 u8 ll2_queue_id; 7485 u8 cnp_vlan_priority; 7486 u8 cnp_dscp; 7487 u8 reserved; 7488 __le32 cnp_send_timeout; 7489 }; 7490 7491 struct roce_init_func_ramrod_data { 7492 struct rdma_init_func_ramrod_data rdma; 7493 struct roce_init_func_params roce; 7494 }; 7495 7496 struct roce_modify_qp_req_ramrod_data { 7497 __le16 flags; 7498 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1 7499 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0 7500 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_MASK 0x1 7501 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MOVE_TO_SQD_FLG_SHIFT 1 7502 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_MASK 0x1 7503 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_EN_SQD_ASYNC_NOTIFY_SHIFT 2 7504 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_MASK 0x1 7505 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_P_KEY_FLG_SHIFT 3 7506 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1 7507 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 4 7508 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_MASK 0x1 7509 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_MAX_ORD_FLG_SHIFT 5 7510 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_MASK 0x1 7511 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_FLG_SHIFT 6 7512 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_MASK 0x1 7513 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_FLG_SHIFT 7 7514 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_MASK 0x1 7515 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ACK_TIMEOUT_FLG_SHIFT 8 7516 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_MASK 0x1 7517 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_FLG_SHIFT 9 7518 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_MASK 0x7 7519 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_PRI_SHIFT 10 7520 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_MASK 0x7 7521 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RESERVED1_SHIFT 13 7522 u8 fields; 7523 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_MASK 0xF 7524 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_ERR_RETRY_CNT_SHIFT 0 7525 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_MASK 0xF 7526 #define ROCE_MODIFY_QP_REQ_RAMROD_DATA_RNR_NAK_CNT_SHIFT 4 7527 u8 max_ord; 7528 u8 traffic_class; 7529 u8 hop_limit; 7530 __le16 p_key; 7531 __le32 flow_label; 7532 __le32 ack_timeout_val; 7533 __le16 mtu; 7534 __le16 reserved2; 7535 __le32 reserved3[3]; 7536 __le32 src_gid[4]; 7537 __le32 dst_gid[4]; 7538 }; 7539 7540 struct roce_modify_qp_resp_ramrod_data { 7541 __le16 flags; 7542 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_MASK 0x1 7543 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MOVE_TO_ERR_FLG_SHIFT 0 7544 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 7545 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_RD_EN_SHIFT 1 7546 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 7547 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_WR_EN_SHIFT 2 7548 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 7549 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ATOMIC_EN_SHIFT 3 7550 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_MASK 0x1 7551 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_P_KEY_FLG_SHIFT 4 7552 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_MASK 0x1 7553 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_ADDRESS_VECTOR_FLG_SHIFT 5 7554 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_MASK 0x1 7555 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MAX_IRD_FLG_SHIFT 6 7556 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_MASK 0x1 7557 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_FLG_SHIFT 7 7558 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_MASK 0x1 7559 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_FLG_SHIFT 8 7560 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1 7561 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 9 7562 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_MASK 0x3F 7563 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_RESERVED1_SHIFT 10 7564 u8 fields; 7565 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_MASK 0x7 7566 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_PRI_SHIFT 0 7567 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_MASK 0x1F 7568 #define ROCE_MODIFY_QP_RESP_RAMROD_DATA_MIN_RNR_NAK_TIMER_SHIFT 3 7569 u8 max_ird; 7570 u8 traffic_class; 7571 u8 hop_limit; 7572 __le16 p_key; 7573 __le32 flow_label; 7574 __le16 mtu; 7575 __le16 reserved2; 7576 __le32 src_gid[4]; 7577 __le32 dst_gid[4]; 7578 }; 7579 7580 struct roce_query_qp_req_output_params { 7581 __le32 psn; 7582 __le32 flags; 7583 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_MASK 0x1 7584 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_ERR_FLG_SHIFT 0 7585 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_MASK 0x1 7586 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_SQ_DRAINING_FLG_SHIFT 1 7587 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_MASK 0x3FFFFFFF 7588 #define ROCE_QUERY_QP_REQ_OUTPUT_PARAMS_RESERVED0_SHIFT 2 7589 }; 7590 7591 struct roce_query_qp_req_ramrod_data { 7592 struct regpair output_params_addr; 7593 }; 7594 7595 struct roce_query_qp_resp_output_params { 7596 __le32 psn; 7597 __le32 err_flag; 7598 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1 7599 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0 7600 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF 7601 #define ROCE_QUERY_QP_RESP_OUTPUT_PARAMS_RESERVED0_SHIFT 1 7602 }; 7603 7604 struct roce_query_qp_resp_ramrod_data { 7605 struct regpair output_params_addr; 7606 }; 7607 7608 enum roce_ramrod_cmd_id { 7609 ROCE_RAMROD_CREATE_QP = 11, 7610 ROCE_RAMROD_MODIFY_QP, 7611 ROCE_RAMROD_QUERY_QP, 7612 ROCE_RAMROD_DESTROY_QP, 7613 ROCE_RAMROD_CREATE_UD_QP, 7614 ROCE_RAMROD_DESTROY_UD_QP, 7615 MAX_ROCE_RAMROD_CMD_ID 7616 }; 7617 7618 struct mstorm_roce_req_conn_ag_ctx { 7619 u8 byte0; 7620 u8 byte1; 7621 u8 flags0; 7622 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 7623 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 7624 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 7625 #define MSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 7626 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 7627 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 7628 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 7629 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 7630 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 7631 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 7632 u8 flags1; 7633 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 7634 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 7635 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 7636 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 7637 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 7638 #define MSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 7639 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 7640 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 7641 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 7642 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 7643 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 7644 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 7645 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 7646 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 7647 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 7648 #define MSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 7649 __le16 word0; 7650 __le16 word1; 7651 __le32 reg0; 7652 __le32 reg1; 7653 }; 7654 7655 struct mstorm_roce_resp_conn_ag_ctx { 7656 u8 byte0; 7657 u8 byte1; 7658 u8 flags0; 7659 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 7660 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 7661 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 7662 #define MSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 7663 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 7664 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 7665 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 7666 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 7667 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 7668 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 7669 u8 flags1; 7670 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 7671 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 7672 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 7673 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 7674 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 7675 #define MSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 7676 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 7677 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 7678 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 7679 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 7680 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 7681 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 7682 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 7683 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 7684 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 7685 #define MSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 7686 __le16 word0; 7687 __le16 word1; 7688 __le32 reg0; 7689 __le32 reg1; 7690 }; 7691 7692 struct tstorm_roce_req_conn_ag_ctx { 7693 u8 reserved0; 7694 u8 state; 7695 u8 flags0; 7696 #define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 7697 #define TSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 7698 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_MASK 0x1 7699 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_OCCURED_SHIFT 1 7700 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_MASK 0x1 7701 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_CQE_ERROR_OCCURED_SHIFT 2 7702 #define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_MASK 0x1 7703 #define TSTORM_ROCE_REQ_CONN_AG_CTX_BIT3_SHIFT 3 7704 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 7705 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 7706 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 7707 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CACHED_ORQ_SHIFT 5 7708 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_MASK 0x3 7709 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_SHIFT 6 7710 u8 flags1; 7711 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 7712 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 0 7713 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_MASK 0x3 7714 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_SHIFT 2 7715 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 7716 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 7717 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 7718 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 7719 u8 flags2; 7720 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 7721 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 7722 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_MASK 0x3 7723 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_SHIFT 2 7724 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_MASK 0x3 7725 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_SHIFT 4 7726 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_MASK 0x3 7727 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_SHIFT 6 7728 u8 flags3; 7729 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_MASK 0x3 7730 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_SHIFT 0 7731 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_MASK 0x3 7732 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_SHIFT 2 7733 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_MASK 0x1 7734 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_CF_EN_SHIFT 4 7735 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 7736 #define TSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 5 7737 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_MASK 0x1 7738 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_SQ_CF_EN_SHIFT 6 7739 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 7740 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 7741 u8 flags4; 7742 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 7743 #define TSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 7744 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 7745 #define TSTORM_ROCE_REQ_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 7746 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_MASK 0x1 7747 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SET_TIMER_CF_EN_SHIFT 2 7748 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_MASK 0x1 7749 #define TSTORM_ROCE_REQ_CONN_AG_CTX_TX_ASYNC_ERROR_CF_EN_SHIFT 3 7750 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_MASK 0x1 7751 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RXMIT_DONE_CF_EN_SHIFT 4 7752 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_MASK 0x1 7753 #define TSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_SCAN_COMPLETED_CF_EN_SHIFT 5 7754 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_MASK 0x1 7755 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SQ_DRAIN_COMPLETED_CF_EN_SHIFT 6 7756 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 7757 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 7758 u8 flags5; 7759 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 7760 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 7761 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 7762 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1 7763 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 7764 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 7765 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 7766 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 7767 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 7768 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 7769 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_MASK 0x1 7770 #define TSTORM_ROCE_REQ_CONN_AG_CTX_SND_SQ_CONS_EN_SHIFT 5 7771 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 7772 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 7773 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 7774 #define TSTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 7775 __le32 reg0; 7776 __le32 snd_nxt_psn; 7777 __le32 snd_max_psn; 7778 __le32 orq_prod; 7779 __le32 reg4; 7780 __le32 reg5; 7781 __le32 reg6; 7782 __le32 reg7; 7783 __le32 reg8; 7784 u8 tx_cqe_error_type; 7785 u8 orq_cache_idx; 7786 __le16 snd_sq_cons_th; 7787 u8 byte4; 7788 u8 byte5; 7789 __le16 snd_sq_cons; 7790 __le16 word2; 7791 __le16 word3; 7792 __le32 reg9; 7793 __le32 reg10; 7794 }; 7795 7796 struct tstorm_roce_resp_conn_ag_ctx { 7797 u8 byte0; 7798 u8 state; 7799 u8 flags0; 7800 #define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 7801 #define TSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 7802 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_MASK 0x1 7803 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_NOTIFY_REQUESTER_SHIFT 1 7804 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_MASK 0x1 7805 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT2_SHIFT 2 7806 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_MASK 0x1 7807 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT3_SHIFT 3 7808 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 7809 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 4 7810 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_MASK 0x1 7811 #define TSTORM_ROCE_RESP_CONN_AG_CTX_BIT5_SHIFT 5 7812 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 7813 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 6 7814 u8 flags1; 7815 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 7816 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 0 7817 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_MASK 0x3 7818 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_SHIFT 2 7819 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 7820 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 4 7821 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 7822 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 7823 u8 flags2; 7824 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 7825 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 7826 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 7827 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 2 7828 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_MASK 0x3 7829 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7_SHIFT 4 7830 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 7831 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 6 7832 u8 flags3; 7833 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 7834 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 0 7835 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 7836 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 2 7837 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 7838 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 4 7839 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 7840 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 5 7841 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_MASK 0x1 7842 #define TSTORM_ROCE_RESP_CONN_AG_CTX_TX_ERROR_CF_EN_SHIFT 6 7843 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 7844 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 7 7845 u8 flags4; 7846 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 7847 #define TSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 7848 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 7849 #define TSTORM_ROCE_RESP_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 7850 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 7851 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 2 7852 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_MASK 0x1 7853 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF7EN_SHIFT 3 7854 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 7855 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 4 7856 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 7857 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 5 7858 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 7859 #define TSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 6 7860 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 7861 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 7862 u8 flags5; 7863 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 7864 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 7865 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 7866 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 7867 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 7868 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 7869 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 7870 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 7871 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 7872 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 7873 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_MASK 0x1 7874 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RQ_RULE_EN_SHIFT 5 7875 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 7876 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 7877 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 7878 #define TSTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 7879 __le32 psn_and_rxmit_id_echo; 7880 __le32 reg1; 7881 __le32 reg2; 7882 __le32 reg3; 7883 __le32 reg4; 7884 __le32 reg5; 7885 __le32 reg6; 7886 __le32 reg7; 7887 __le32 reg8; 7888 u8 tx_async_error_type; 7889 u8 byte3; 7890 __le16 rq_cons; 7891 u8 byte4; 7892 u8 byte5; 7893 __le16 rq_prod; 7894 __le16 conn_dpi; 7895 __le16 irq_cons; 7896 __le32 num_invlidated_mw; 7897 __le32 reg10; 7898 }; 7899 7900 struct ustorm_roce_req_conn_ag_ctx { 7901 u8 byte0; 7902 u8 byte1; 7903 u8 flags0; 7904 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 7905 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 7906 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 7907 #define USTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 7908 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 7909 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 7910 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 7911 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 7912 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 7913 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 7914 u8 flags1; 7915 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 7916 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 0 7917 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_MASK 0x3 7918 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4_SHIFT 2 7919 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_MASK 0x3 7920 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5_SHIFT 4 7921 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_MASK 0x3 7922 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6_SHIFT 6 7923 u8 flags2; 7924 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 7925 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 7926 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 7927 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 7928 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 7929 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 7930 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 7931 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 3 7932 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_MASK 0x1 7933 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF4EN_SHIFT 4 7934 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_MASK 0x1 7935 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF5EN_SHIFT 5 7936 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_MASK 0x1 7937 #define USTORM_ROCE_REQ_CONN_AG_CTX_CF6EN_SHIFT 6 7938 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 7939 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 7 7940 u8 flags3; 7941 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 7942 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 0 7943 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 7944 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 1 7945 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 7946 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 2 7947 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 7948 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 3 7949 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 7950 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 4 7951 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 7952 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 5 7953 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_MASK 0x1 7954 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE7EN_SHIFT 6 7955 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_MASK 0x1 7956 #define USTORM_ROCE_REQ_CONN_AG_CTX_RULE8EN_SHIFT 7 7957 u8 byte2; 7958 u8 byte3; 7959 __le16 word0; 7960 __le16 word1; 7961 __le32 reg0; 7962 __le32 reg1; 7963 __le32 reg2; 7964 __le32 reg3; 7965 __le16 word2; 7966 __le16 word3; 7967 }; 7968 7969 struct ustorm_roce_resp_conn_ag_ctx { 7970 u8 byte0; 7971 u8 byte1; 7972 u8 flags0; 7973 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 7974 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 7975 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 7976 #define USTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 7977 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 7978 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 7979 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 7980 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 7981 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 7982 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 7983 u8 flags1; 7984 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 7985 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 0 7986 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_MASK 0x3 7987 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4_SHIFT 2 7988 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_MASK 0x3 7989 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5_SHIFT 4 7990 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_MASK 0x3 7991 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6_SHIFT 6 7992 u8 flags2; 7993 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 7994 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 7995 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 7996 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 7997 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 7998 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 7999 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 8000 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 3 8001 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_MASK 0x1 8002 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF4EN_SHIFT 4 8003 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_MASK 0x1 8004 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF5EN_SHIFT 5 8005 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_MASK 0x1 8006 #define USTORM_ROCE_RESP_CONN_AG_CTX_CF6EN_SHIFT 6 8007 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 8008 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 7 8009 u8 flags3; 8010 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 8011 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 0 8012 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 8013 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 1 8014 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 8015 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 2 8016 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 8017 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 3 8018 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 8019 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 4 8020 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 8021 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 5 8022 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 8023 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 6 8024 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_MASK 0x1 8025 #define USTORM_ROCE_RESP_CONN_AG_CTX_RULE8EN_SHIFT 7 8026 u8 byte2; 8027 u8 byte3; 8028 __le16 word0; 8029 __le16 word1; 8030 __le32 reg0; 8031 __le32 reg1; 8032 __le32 reg2; 8033 __le32 reg3; 8034 __le16 word2; 8035 __le16 word3; 8036 }; 8037 8038 struct xstorm_roce_req_conn_ag_ctx { 8039 u8 reserved0; 8040 u8 state; 8041 u8 flags0; 8042 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 8043 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 8044 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_MASK 0x1 8045 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED1_SHIFT 1 8046 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_MASK 0x1 8047 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED2_SHIFT 2 8048 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 8049 #define XSTORM_ROCE_REQ_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 8050 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_MASK 0x1 8051 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED3_SHIFT 4 8052 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_MASK 0x1 8053 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED4_SHIFT 5 8054 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_MASK 0x1 8055 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED5_SHIFT 6 8056 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_MASK 0x1 8057 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED6_SHIFT 7 8058 u8 flags1; 8059 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_MASK 0x1 8060 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED7_SHIFT 0 8061 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_MASK 0x1 8062 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED8_SHIFT 1 8063 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_MASK 0x1 8064 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT10_SHIFT 2 8065 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_MASK 0x1 8066 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT11_SHIFT 3 8067 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_MASK 0x1 8068 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT12_SHIFT 4 8069 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_MASK 0x1 8070 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT13_SHIFT 5 8071 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_MASK 0x1 8072 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ERROR_STATE_SHIFT 6 8073 #define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 8074 #define XSTORM_ROCE_REQ_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 8075 u8 flags2; 8076 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 8077 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 0 8078 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 8079 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 2 8080 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 8081 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 4 8082 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_MASK 0x3 8083 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3_SHIFT 6 8084 u8 flags3; 8085 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 8086 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 0 8087 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 8088 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 8089 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_MASK 0x3 8090 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_SHIFT 4 8091 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 8092 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 8093 u8 flags4; 8094 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_MASK 0x3 8095 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8_SHIFT 0 8096 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_MASK 0x3 8097 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9_SHIFT 2 8098 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_MASK 0x3 8099 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10_SHIFT 4 8100 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_MASK 0x3 8101 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11_SHIFT 6 8102 u8 flags5; 8103 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_MASK 0x3 8104 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12_SHIFT 0 8105 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_MASK 0x3 8106 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13_SHIFT 2 8107 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_MASK 0x3 8108 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FMR_ENDED_CF_SHIFT 4 8109 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_MASK 0x3 8110 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15_SHIFT 6 8111 u8 flags6; 8112 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_MASK 0x3 8113 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16_SHIFT 0 8114 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_MASK 0x3 8115 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17_SHIFT 2 8116 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_MASK 0x3 8117 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18_SHIFT 4 8118 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_MASK 0x3 8119 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19_SHIFT 6 8120 u8 flags7; 8121 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_MASK 0x3 8122 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20_SHIFT 0 8123 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_MASK 0x3 8124 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21_SHIFT 2 8125 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_MASK 0x3 8126 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_SHIFT 4 8127 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 8128 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 6 8129 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 8130 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 7 8131 u8 flags8; 8132 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 8133 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 0 8134 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_MASK 0x1 8135 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF3EN_SHIFT 1 8136 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 8137 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 2 8138 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 8139 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 8140 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_MASK 0x1 8141 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SND_RXMIT_CF_EN_SHIFT 4 8142 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 8143 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 8144 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_MASK 0x1 8145 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF8EN_SHIFT 6 8146 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_MASK 0x1 8147 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF9EN_SHIFT 7 8148 u8 flags9; 8149 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_MASK 0x1 8150 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF10EN_SHIFT 0 8151 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_MASK 0x1 8152 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF11EN_SHIFT 1 8153 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_MASK 0x1 8154 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF12EN_SHIFT 2 8155 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_MASK 0x1 8156 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF13EN_SHIFT 3 8157 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_MASK 0x1 8158 #define XSTORM_ROCE_REQ_CONN_AG_CTX_FME_ENDED_CF_EN_SHIFT 4 8159 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_MASK 0x1 8160 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF15EN_SHIFT 5 8161 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_MASK 0x1 8162 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF16EN_SHIFT 6 8163 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_MASK 0x1 8164 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF17EN_SHIFT 7 8165 u8 flags10; 8166 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_MASK 0x1 8167 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF18EN_SHIFT 0 8168 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_MASK 0x1 8169 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF19EN_SHIFT 1 8170 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_MASK 0x1 8171 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF20EN_SHIFT 2 8172 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_MASK 0x1 8173 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF21EN_SHIFT 3 8174 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 8175 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 8176 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_MASK 0x1 8177 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23EN_SHIFT 5 8178 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 8179 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 6 8180 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 8181 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 7 8182 u8 flags11; 8183 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 8184 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 0 8185 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 8186 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 1 8187 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 8188 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 2 8189 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_MASK 0x1 8190 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE5EN_SHIFT 3 8191 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_MASK 0x1 8192 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE6EN_SHIFT 4 8193 #define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_MASK 0x1 8194 #define XSTORM_ROCE_REQ_CONN_AG_CTX_E2E_CREDIT_RULE_EN_SHIFT 5 8195 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 8196 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 8197 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_MASK 0x1 8198 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE9EN_SHIFT 7 8199 u8 flags12; 8200 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_MASK 0x1 8201 #define XSTORM_ROCE_REQ_CONN_AG_CTX_SQ_PROD_EN_SHIFT 0 8202 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_MASK 0x1 8203 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE11EN_SHIFT 1 8204 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 8205 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 8206 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 8207 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 8208 #define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_MASK 0x1 8209 #define XSTORM_ROCE_REQ_CONN_AG_CTX_INV_FENCE_RULE_EN_SHIFT 4 8210 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_MASK 0x1 8211 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE15EN_SHIFT 5 8212 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_MASK 0x1 8213 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ORQ_FENCE_RULE_EN_SHIFT 6 8214 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_MASK 0x1 8215 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MAX_ORD_RULE_EN_SHIFT 7 8216 u8 flags13; 8217 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_MASK 0x1 8218 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE18EN_SHIFT 0 8219 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_MASK 0x1 8220 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RULE19EN_SHIFT 1 8221 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 8222 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 8223 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 8224 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 8225 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 8226 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 8227 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 8228 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 8229 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 8230 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 8231 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 8232 #define XSTORM_ROCE_REQ_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 8233 u8 flags14; 8234 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_MASK 0x1 8235 #define XSTORM_ROCE_REQ_CONN_AG_CTX_MIGRATION_FLAG_SHIFT 0 8236 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_MASK 0x1 8237 #define XSTORM_ROCE_REQ_CONN_AG_CTX_BIT17_SHIFT 1 8238 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 8239 #define XSTORM_ROCE_REQ_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 8240 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_MASK 0x1 8241 #define XSTORM_ROCE_REQ_CONN_AG_CTX_RESERVED_SHIFT 4 8242 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 8243 #define XSTORM_ROCE_REQ_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 8244 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_MASK 0x3 8245 #define XSTORM_ROCE_REQ_CONN_AG_CTX_CF23_SHIFT 6 8246 u8 byte2; 8247 __le16 physical_q0; 8248 __le16 word1; 8249 __le16 sq_cmp_cons; 8250 __le16 sq_cons; 8251 __le16 sq_prod; 8252 __le16 word5; 8253 __le16 conn_dpi; 8254 u8 byte3; 8255 u8 byte4; 8256 u8 byte5; 8257 u8 byte6; 8258 __le32 lsn; 8259 __le32 ssn; 8260 __le32 snd_una_psn; 8261 __le32 snd_nxt_psn; 8262 __le32 reg4; 8263 __le32 orq_cons_th; 8264 __le32 orq_cons; 8265 }; 8266 8267 struct xstorm_roce_resp_conn_ag_ctx { 8268 u8 reserved0; 8269 u8 state; 8270 u8 flags0; 8271 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 8272 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 8273 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_MASK 0x1 8274 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED1_SHIFT 1 8275 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_MASK 0x1 8276 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED2_SHIFT 2 8277 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 8278 #define XSTORM_ROCE_RESP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 8279 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_MASK 0x1 8280 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED3_SHIFT 4 8281 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_MASK 0x1 8282 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED4_SHIFT 5 8283 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_MASK 0x1 8284 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED5_SHIFT 6 8285 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_MASK 0x1 8286 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED6_SHIFT 7 8287 u8 flags1; 8288 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_MASK 0x1 8289 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED7_SHIFT 0 8290 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_MASK 0x1 8291 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RESERVED8_SHIFT 1 8292 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_MASK 0x1 8293 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT10_SHIFT 2 8294 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_MASK 0x1 8295 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT11_SHIFT 3 8296 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_MASK 0x1 8297 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT12_SHIFT 4 8298 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_MASK 0x1 8299 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT13_SHIFT 5 8300 #define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_MASK 0x1 8301 #define XSTORM_ROCE_RESP_CONN_AG_CTX_ERROR_STATE_SHIFT 6 8302 #define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 8303 #define XSTORM_ROCE_RESP_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 8304 u8 flags2; 8305 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 8306 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 0 8307 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 8308 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 2 8309 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 8310 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 4 8311 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_MASK 0x3 8312 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3_SHIFT 6 8313 u8 flags3; 8314 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_MASK 0x3 8315 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_SHIFT 0 8316 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_MASK 0x3 8317 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_SHIFT 2 8318 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_MASK 0x3 8319 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_SHIFT 4 8320 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 8321 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 8322 u8 flags4; 8323 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_MASK 0x3 8324 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8_SHIFT 0 8325 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_MASK 0x3 8326 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9_SHIFT 2 8327 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_MASK 0x3 8328 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10_SHIFT 4 8329 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_MASK 0x3 8330 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11_SHIFT 6 8331 u8 flags5; 8332 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_MASK 0x3 8333 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12_SHIFT 0 8334 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_MASK 0x3 8335 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13_SHIFT 2 8336 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_MASK 0x3 8337 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14_SHIFT 4 8338 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_MASK 0x3 8339 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15_SHIFT 6 8340 u8 flags6; 8341 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_MASK 0x3 8342 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16_SHIFT 0 8343 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_MASK 0x3 8344 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17_SHIFT 2 8345 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_MASK 0x3 8346 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18_SHIFT 4 8347 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_MASK 0x3 8348 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19_SHIFT 6 8349 u8 flags7; 8350 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_MASK 0x3 8351 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20_SHIFT 0 8352 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_MASK 0x3 8353 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21_SHIFT 2 8354 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 8355 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_SHIFT 4 8356 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 8357 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 6 8358 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 8359 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 7 8360 u8 flags8; 8361 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 8362 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 0 8363 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_MASK 0x1 8364 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF3EN_SHIFT 1 8365 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_MASK 0x1 8366 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RXMIT_CF_EN_SHIFT 2 8367 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_MASK 0x1 8368 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RX_ERROR_CF_EN_SHIFT 3 8369 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_MASK 0x1 8370 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FORCE_ACK_CF_EN_SHIFT 4 8371 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 8372 #define XSTORM_ROCE_RESP_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 8373 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_MASK 0x1 8374 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF8EN_SHIFT 6 8375 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_MASK 0x1 8376 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF9EN_SHIFT 7 8377 u8 flags9; 8378 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_MASK 0x1 8379 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF10EN_SHIFT 0 8380 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_MASK 0x1 8381 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF11EN_SHIFT 1 8382 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_MASK 0x1 8383 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF12EN_SHIFT 2 8384 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_MASK 0x1 8385 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF13EN_SHIFT 3 8386 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_MASK 0x1 8387 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF14EN_SHIFT 4 8388 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_MASK 0x1 8389 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF15EN_SHIFT 5 8390 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_MASK 0x1 8391 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF16EN_SHIFT 6 8392 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_MASK 0x1 8393 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF17EN_SHIFT 7 8394 u8 flags10; 8395 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_MASK 0x1 8396 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF18EN_SHIFT 0 8397 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_MASK 0x1 8398 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF19EN_SHIFT 1 8399 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_MASK 0x1 8400 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF20EN_SHIFT 2 8401 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_MASK 0x1 8402 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF21EN_SHIFT 3 8403 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 8404 #define XSTORM_ROCE_RESP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 8405 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_MASK 0x1 8406 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23EN_SHIFT 5 8407 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 8408 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 6 8409 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 8410 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 7 8411 u8 flags11; 8412 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 8413 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 0 8414 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 8415 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 1 8416 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 8417 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 2 8418 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_MASK 0x1 8419 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE5EN_SHIFT 3 8420 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_MASK 0x1 8421 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE6EN_SHIFT 4 8422 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_MASK 0x1 8423 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE7EN_SHIFT 5 8424 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 8425 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 8426 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_MASK 0x1 8427 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE9EN_SHIFT 7 8428 u8 flags12; 8429 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_MASK 0x1 8430 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE10EN_SHIFT 0 8431 #define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_MASK 0x1 8432 #define XSTORM_ROCE_RESP_CONN_AG_CTX_IRQ_PROD_RULE_EN_SHIFT 1 8433 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 8434 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 8435 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 8436 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 8437 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_MASK 0x1 8438 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE14EN_SHIFT 4 8439 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_MASK 0x1 8440 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE15EN_SHIFT 5 8441 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_MASK 0x1 8442 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE16EN_SHIFT 6 8443 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_MASK 0x1 8444 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE17EN_SHIFT 7 8445 u8 flags13; 8446 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_MASK 0x1 8447 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE18EN_SHIFT 0 8448 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_MASK 0x1 8449 #define XSTORM_ROCE_RESP_CONN_AG_CTX_RULE19EN_SHIFT 1 8450 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 8451 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 8452 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 8453 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 8454 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 8455 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 8456 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 8457 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 8458 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 8459 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 8460 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 8461 #define XSTORM_ROCE_RESP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 8462 u8 flags14; 8463 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_MASK 0x1 8464 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT16_SHIFT 0 8465 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_MASK 0x1 8466 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT17_SHIFT 1 8467 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_MASK 0x1 8468 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT18_SHIFT 2 8469 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_MASK 0x1 8470 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT19_SHIFT 3 8471 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_MASK 0x1 8472 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT20_SHIFT 4 8473 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_MASK 0x1 8474 #define XSTORM_ROCE_RESP_CONN_AG_CTX_BIT21_SHIFT 5 8475 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_MASK 0x3 8476 #define XSTORM_ROCE_RESP_CONN_AG_CTX_CF23_SHIFT 6 8477 u8 byte2; 8478 __le16 physical_q0; 8479 __le16 word1; 8480 __le16 irq_prod; 8481 __le16 word3; 8482 __le16 word4; 8483 __le16 ereserved1; 8484 __le16 irq_cons; 8485 u8 rxmit_opcode; 8486 u8 byte4; 8487 u8 byte5; 8488 u8 byte6; 8489 __le32 rxmit_psn_and_id; 8490 __le32 rxmit_bytes_length; 8491 __le32 psn; 8492 __le32 reg3; 8493 __le32 reg4; 8494 __le32 reg5; 8495 __le32 msn_and_syndrome; 8496 }; 8497 8498 struct ystorm_roce_req_conn_ag_ctx { 8499 u8 byte0; 8500 u8 byte1; 8501 u8 flags0; 8502 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_MASK 0x1 8503 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT0_SHIFT 0 8504 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_MASK 0x1 8505 #define YSTORM_ROCE_REQ_CONN_AG_CTX_BIT1_SHIFT 1 8506 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_MASK 0x3 8507 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0_SHIFT 2 8508 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_MASK 0x3 8509 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1_SHIFT 4 8510 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_MASK 0x3 8511 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2_SHIFT 6 8512 u8 flags1; 8513 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_MASK 0x1 8514 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF0EN_SHIFT 0 8515 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_MASK 0x1 8516 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF1EN_SHIFT 1 8517 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_MASK 0x1 8518 #define YSTORM_ROCE_REQ_CONN_AG_CTX_CF2EN_SHIFT 2 8519 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_MASK 0x1 8520 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE0EN_SHIFT 3 8521 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_MASK 0x1 8522 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE1EN_SHIFT 4 8523 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_MASK 0x1 8524 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE2EN_SHIFT 5 8525 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_MASK 0x1 8526 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE3EN_SHIFT 6 8527 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_MASK 0x1 8528 #define YSTORM_ROCE_REQ_CONN_AG_CTX_RULE4EN_SHIFT 7 8529 u8 byte2; 8530 u8 byte3; 8531 __le16 word0; 8532 __le32 reg0; 8533 __le32 reg1; 8534 __le16 word1; 8535 __le16 word2; 8536 __le16 word3; 8537 __le16 word4; 8538 __le32 reg2; 8539 __le32 reg3; 8540 }; 8541 8542 struct ystorm_roce_resp_conn_ag_ctx { 8543 u8 byte0; 8544 u8 byte1; 8545 u8 flags0; 8546 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_MASK 0x1 8547 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT0_SHIFT 0 8548 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_MASK 0x1 8549 #define YSTORM_ROCE_RESP_CONN_AG_CTX_BIT1_SHIFT 1 8550 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_MASK 0x3 8551 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0_SHIFT 2 8552 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_MASK 0x3 8553 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1_SHIFT 4 8554 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_MASK 0x3 8555 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2_SHIFT 6 8556 u8 flags1; 8557 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_MASK 0x1 8558 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF0EN_SHIFT 0 8559 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_MASK 0x1 8560 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF1EN_SHIFT 1 8561 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_MASK 0x1 8562 #define YSTORM_ROCE_RESP_CONN_AG_CTX_CF2EN_SHIFT 2 8563 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_MASK 0x1 8564 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE0EN_SHIFT 3 8565 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_MASK 0x1 8566 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE1EN_SHIFT 4 8567 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_MASK 0x1 8568 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE2EN_SHIFT 5 8569 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_MASK 0x1 8570 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE3EN_SHIFT 6 8571 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_MASK 0x1 8572 #define YSTORM_ROCE_RESP_CONN_AG_CTX_RULE4EN_SHIFT 7 8573 u8 byte2; 8574 u8 byte3; 8575 __le16 word0; 8576 __le32 reg0; 8577 __le32 reg1; 8578 __le16 word1; 8579 __le16 word2; 8580 __le16 word3; 8581 __le16 word4; 8582 __le32 reg2; 8583 __le32 reg3; 8584 }; 8585 8586 enum roce_flavor { 8587 PLAIN_ROCE, 8588 RROCE_IPV4, 8589 RROCE_IPV6, 8590 MAX_ROCE_FLAVOR 8591 }; 8592 8593 struct ystorm_iwarp_conn_st_ctx { 8594 __le32 reserved[4]; 8595 }; 8596 8597 struct pstorm_iwarp_conn_st_ctx { 8598 __le32 reserved[36]; 8599 }; 8600 8601 struct xstorm_iwarp_conn_st_ctx { 8602 __le32 reserved[44]; 8603 }; 8604 8605 struct xstorm_iwarp_conn_ag_ctx { 8606 u8 reserved0; 8607 u8 state; 8608 u8 flags0; 8609 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 8610 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 8611 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1 8612 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1 8613 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_MASK 0x1 8614 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM2_SHIFT 2 8615 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 8616 #define XSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 8617 #define XSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 8618 #define XSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4 8619 #define XSTORM_IWARP_CONN_AG_CTX_RESERVED2_MASK 0x1 8620 #define XSTORM_IWARP_CONN_AG_CTX_RESERVED2_SHIFT 5 8621 #define XSTORM_IWARP_CONN_AG_CTX_BIT6_MASK 0x1 8622 #define XSTORM_IWARP_CONN_AG_CTX_BIT6_SHIFT 6 8623 #define XSTORM_IWARP_CONN_AG_CTX_BIT7_MASK 0x1 8624 #define XSTORM_IWARP_CONN_AG_CTX_BIT7_SHIFT 7 8625 u8 flags1; 8626 #define XSTORM_IWARP_CONN_AG_CTX_BIT8_MASK 0x1 8627 #define XSTORM_IWARP_CONN_AG_CTX_BIT8_SHIFT 0 8628 #define XSTORM_IWARP_CONN_AG_CTX_BIT9_MASK 0x1 8629 #define XSTORM_IWARP_CONN_AG_CTX_BIT9_SHIFT 1 8630 #define XSTORM_IWARP_CONN_AG_CTX_BIT10_MASK 0x1 8631 #define XSTORM_IWARP_CONN_AG_CTX_BIT10_SHIFT 2 8632 #define XSTORM_IWARP_CONN_AG_CTX_BIT11_MASK 0x1 8633 #define XSTORM_IWARP_CONN_AG_CTX_BIT11_SHIFT 3 8634 #define XSTORM_IWARP_CONN_AG_CTX_BIT12_MASK 0x1 8635 #define XSTORM_IWARP_CONN_AG_CTX_BIT12_SHIFT 4 8636 #define XSTORM_IWARP_CONN_AG_CTX_BIT13_MASK 0x1 8637 #define XSTORM_IWARP_CONN_AG_CTX_BIT13_SHIFT 5 8638 #define XSTORM_IWARP_CONN_AG_CTX_BIT14_MASK 0x1 8639 #define XSTORM_IWARP_CONN_AG_CTX_BIT14_SHIFT 6 8640 #define XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_MASK 0x1 8641 #define XSTORM_IWARP_CONN_AG_CTX_YSTORM_FLUSH_OR_REWIND_SND_MAX_SHIFT 7 8642 u8 flags2; 8643 #define XSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 8644 #define XSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 0 8645 #define XSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 8646 #define XSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 2 8647 #define XSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 8648 #define XSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 4 8649 #define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 8650 #define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6 8651 u8 flags3; 8652 #define XSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 8653 #define XSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 0 8654 #define XSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 8655 #define XSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 2 8656 #define XSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 8657 #define XSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 4 8658 #define XSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 8659 #define XSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 6 8660 u8 flags4; 8661 #define XSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 8662 #define XSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 0 8663 #define XSTORM_IWARP_CONN_AG_CTX_CF9_MASK 0x3 8664 #define XSTORM_IWARP_CONN_AG_CTX_CF9_SHIFT 2 8665 #define XSTORM_IWARP_CONN_AG_CTX_CF10_MASK 0x3 8666 #define XSTORM_IWARP_CONN_AG_CTX_CF10_SHIFT 4 8667 #define XSTORM_IWARP_CONN_AG_CTX_CF11_MASK 0x3 8668 #define XSTORM_IWARP_CONN_AG_CTX_CF11_SHIFT 6 8669 u8 flags5; 8670 #define XSTORM_IWARP_CONN_AG_CTX_CF12_MASK 0x3 8671 #define XSTORM_IWARP_CONN_AG_CTX_CF12_SHIFT 0 8672 #define XSTORM_IWARP_CONN_AG_CTX_CF13_MASK 0x3 8673 #define XSTORM_IWARP_CONN_AG_CTX_CF13_SHIFT 2 8674 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_MASK 0x3 8675 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_SHIFT 4 8676 #define XSTORM_IWARP_CONN_AG_CTX_CF15_MASK 0x3 8677 #define XSTORM_IWARP_CONN_AG_CTX_CF15_SHIFT 6 8678 u8 flags6; 8679 #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_MASK 0x3 8680 #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_SHIFT 0 8681 #define XSTORM_IWARP_CONN_AG_CTX_CF17_MASK 0x3 8682 #define XSTORM_IWARP_CONN_AG_CTX_CF17_SHIFT 2 8683 #define XSTORM_IWARP_CONN_AG_CTX_CF18_MASK 0x3 8684 #define XSTORM_IWARP_CONN_AG_CTX_CF18_SHIFT 4 8685 #define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 8686 #define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_SHIFT 6 8687 u8 flags7; 8688 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 8689 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 8690 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_MASK 0x3 8691 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_SHIFT 2 8692 #define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_MASK 0x3 8693 #define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_SHIFT 4 8694 #define XSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 8695 #define XSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 6 8696 #define XSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 8697 #define XSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 7 8698 u8 flags8; 8699 #define XSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 8700 #define XSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 0 8701 #define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 8702 #define XSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1 8703 #define XSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 8704 #define XSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 2 8705 #define XSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 8706 #define XSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 3 8707 #define XSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 8708 #define XSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 4 8709 #define XSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 8710 #define XSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 5 8711 #define XSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 8712 #define XSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 6 8713 #define XSTORM_IWARP_CONN_AG_CTX_CF9EN_MASK 0x1 8714 #define XSTORM_IWARP_CONN_AG_CTX_CF9EN_SHIFT 7 8715 u8 flags9; 8716 #define XSTORM_IWARP_CONN_AG_CTX_CF10EN_MASK 0x1 8717 #define XSTORM_IWARP_CONN_AG_CTX_CF10EN_SHIFT 0 8718 #define XSTORM_IWARP_CONN_AG_CTX_CF11EN_MASK 0x1 8719 #define XSTORM_IWARP_CONN_AG_CTX_CF11EN_SHIFT 1 8720 #define XSTORM_IWARP_CONN_AG_CTX_CF12EN_MASK 0x1 8721 #define XSTORM_IWARP_CONN_AG_CTX_CF12EN_SHIFT 2 8722 #define XSTORM_IWARP_CONN_AG_CTX_CF13EN_MASK 0x1 8723 #define XSTORM_IWARP_CONN_AG_CTX_CF13EN_SHIFT 3 8724 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_MASK 0x1 8725 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FLUSH_CF_EN_SHIFT 4 8726 #define XSTORM_IWARP_CONN_AG_CTX_CF15EN_MASK 0x1 8727 #define XSTORM_IWARP_CONN_AG_CTX_CF15EN_SHIFT 5 8728 #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_MASK 0x1 8729 #define XSTORM_IWARP_CONN_AG_CTX_MPA_OR_ERROR_WAKEUP_TRIGGER_CF_EN_SHIFT 6 8730 #define XSTORM_IWARP_CONN_AG_CTX_CF17EN_MASK 0x1 8731 #define XSTORM_IWARP_CONN_AG_CTX_CF17EN_SHIFT 7 8732 u8 flags10; 8733 #define XSTORM_IWARP_CONN_AG_CTX_CF18EN_MASK 0x1 8734 #define XSTORM_IWARP_CONN_AG_CTX_CF18EN_SHIFT 0 8735 #define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1 8736 #define XSTORM_IWARP_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1 8737 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 8738 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 8739 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_MASK 0x1 8740 #define XSTORM_IWARP_CONN_AG_CTX_FLUSH_Q1_EN_SHIFT 3 8741 #define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 8742 #define XSTORM_IWARP_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 8743 #define XSTORM_IWARP_CONN_AG_CTX_CF23EN_MASK 0x1 8744 #define XSTORM_IWARP_CONN_AG_CTX_CF23EN_SHIFT 5 8745 #define XSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 8746 #define XSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 6 8747 #define XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_MASK 0x1 8748 #define XSTORM_IWARP_CONN_AG_CTX_MORE_TO_SEND_RULE_EN_SHIFT 7 8749 u8 flags11; 8750 #define XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1 8751 #define XSTORM_IWARP_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0 8752 #define XSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 8753 #define XSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 1 8754 #define XSTORM_IWARP_CONN_AG_CTX_RESERVED3_MASK 0x1 8755 #define XSTORM_IWARP_CONN_AG_CTX_RESERVED3_SHIFT 2 8756 #define XSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 8757 #define XSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 3 8758 #define XSTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1 8759 #define XSTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 4 8760 #define XSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 8761 #define XSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 5 8762 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 8763 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 8764 #define XSTORM_IWARP_CONN_AG_CTX_RULE9EN_MASK 0x1 8765 #define XSTORM_IWARP_CONN_AG_CTX_RULE9EN_SHIFT 7 8766 u8 flags12; 8767 #define XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_MASK 0x1 8768 #define XSTORM_IWARP_CONN_AG_CTX_SQ_NOT_EMPTY_RULE_EN_SHIFT 0 8769 #define XSTORM_IWARP_CONN_AG_CTX_RULE11EN_MASK 0x1 8770 #define XSTORM_IWARP_CONN_AG_CTX_RULE11EN_SHIFT 1 8771 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 8772 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 8773 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 8774 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 8775 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_MASK 0x1 8776 #define XSTORM_IWARP_CONN_AG_CTX_SQ_FENCE_RULE_EN_SHIFT 4 8777 #define XSTORM_IWARP_CONN_AG_CTX_RULE15EN_MASK 0x1 8778 #define XSTORM_IWARP_CONN_AG_CTX_RULE15EN_SHIFT 5 8779 #define XSTORM_IWARP_CONN_AG_CTX_RULE16EN_MASK 0x1 8780 #define XSTORM_IWARP_CONN_AG_CTX_RULE16EN_SHIFT 6 8781 #define XSTORM_IWARP_CONN_AG_CTX_RULE17EN_MASK 0x1 8782 #define XSTORM_IWARP_CONN_AG_CTX_RULE17EN_SHIFT 7 8783 u8 flags13; 8784 #define XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_MASK 0x1 8785 #define XSTORM_IWARP_CONN_AG_CTX_IRQ_NOT_EMPTY_RULE_EN_SHIFT 0 8786 #define XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_MASK 0x1 8787 #define XSTORM_IWARP_CONN_AG_CTX_HQ_NOT_FULL_RULE_EN_SHIFT 1 8788 #define XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_MASK 0x1 8789 #define XSTORM_IWARP_CONN_AG_CTX_ORQ_RD_FENCE_RULE_EN_SHIFT 2 8790 #define XSTORM_IWARP_CONN_AG_CTX_RULE21EN_MASK 0x1 8791 #define XSTORM_IWARP_CONN_AG_CTX_RULE21EN_SHIFT 3 8792 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 8793 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 8794 #define XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_MASK 0x1 8795 #define XSTORM_IWARP_CONN_AG_CTX_ORQ_NOT_FULL_RULE_EN_SHIFT 5 8796 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 8797 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 8798 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 8799 #define XSTORM_IWARP_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 8800 u8 flags14; 8801 #define XSTORM_IWARP_CONN_AG_CTX_BIT16_MASK 0x1 8802 #define XSTORM_IWARP_CONN_AG_CTX_BIT16_SHIFT 0 8803 #define XSTORM_IWARP_CONN_AG_CTX_BIT17_MASK 0x1 8804 #define XSTORM_IWARP_CONN_AG_CTX_BIT17_SHIFT 1 8805 #define XSTORM_IWARP_CONN_AG_CTX_BIT18_MASK 0x1 8806 #define XSTORM_IWARP_CONN_AG_CTX_BIT18_SHIFT 2 8807 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_MASK 0x1 8808 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED1_SHIFT 3 8809 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_MASK 0x1 8810 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED2_SHIFT 4 8811 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_MASK 0x1 8812 #define XSTORM_IWARP_CONN_AG_CTX_E5_RESERVED3_SHIFT 5 8813 #define XSTORM_IWARP_CONN_AG_CTX_CF23_MASK 0x3 8814 #define XSTORM_IWARP_CONN_AG_CTX_CF23_SHIFT 6 8815 u8 byte2; 8816 __le16 physical_q0; 8817 __le16 physical_q1; 8818 __le16 sq_comp_cons; 8819 __le16 sq_tx_cons; 8820 __le16 sq_prod; 8821 __le16 word5; 8822 __le16 conn_dpi; 8823 u8 byte3; 8824 u8 byte4; 8825 u8 byte5; 8826 u8 byte6; 8827 __le32 reg0; 8828 __le32 reg1; 8829 __le32 reg2; 8830 __le32 more_to_send_seq; 8831 __le32 reg4; 8832 __le32 rewinded_snd_max; 8833 __le32 rd_msn; 8834 __le16 irq_prod_via_msdm; 8835 __le16 irq_cons; 8836 __le16 hq_cons_th_or_mpa_data; 8837 __le16 hq_cons; 8838 __le32 atom_msn; 8839 __le32 orq_cons; 8840 __le32 orq_cons_th; 8841 u8 byte7; 8842 u8 max_ord; 8843 u8 wqe_data_pad_bytes; 8844 u8 former_hq_prod; 8845 u8 irq_prod_via_msem; 8846 u8 byte12; 8847 u8 max_pkt_pdu_size_lo; 8848 u8 max_pkt_pdu_size_hi; 8849 u8 byte15; 8850 u8 e5_reserved; 8851 __le16 e5_reserved4; 8852 __le32 reg10; 8853 __le32 reg11; 8854 __le32 shared_queue_page_addr_lo; 8855 __le32 shared_queue_page_addr_hi; 8856 __le32 reg14; 8857 __le32 reg15; 8858 __le32 reg16; 8859 __le32 reg17; 8860 }; 8861 8862 struct tstorm_iwarp_conn_ag_ctx { 8863 u8 reserved0; 8864 u8 state; 8865 u8 flags0; 8866 #define TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 8867 #define TSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 8868 #define TSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 8869 #define TSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 8870 #define TSTORM_IWARP_CONN_AG_CTX_BIT2_MASK 0x1 8871 #define TSTORM_IWARP_CONN_AG_CTX_BIT2_SHIFT 2 8872 #define TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 8873 #define TSTORM_IWARP_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 3 8874 #define TSTORM_IWARP_CONN_AG_CTX_BIT4_MASK 0x1 8875 #define TSTORM_IWARP_CONN_AG_CTX_BIT4_SHIFT 4 8876 #define TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_MASK 0x1 8877 #define TSTORM_IWARP_CONN_AG_CTX_CACHED_ORQ_SHIFT 5 8878 #define TSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 8879 #define TSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 6 8880 u8 flags1; 8881 #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_MASK 0x3 8882 #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_SHIFT 0 8883 #define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_MASK 0x3 8884 #define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_SHIFT 2 8885 #define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 8886 #define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4 8887 #define TSTORM_IWARP_CONN_AG_CTX_CF4_MASK 0x3 8888 #define TSTORM_IWARP_CONN_AG_CTX_CF4_SHIFT 6 8889 u8 flags2; 8890 #define TSTORM_IWARP_CONN_AG_CTX_CF5_MASK 0x3 8891 #define TSTORM_IWARP_CONN_AG_CTX_CF5_SHIFT 0 8892 #define TSTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 8893 #define TSTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 2 8894 #define TSTORM_IWARP_CONN_AG_CTX_CF7_MASK 0x3 8895 #define TSTORM_IWARP_CONN_AG_CTX_CF7_SHIFT 4 8896 #define TSTORM_IWARP_CONN_AG_CTX_CF8_MASK 0x3 8897 #define TSTORM_IWARP_CONN_AG_CTX_CF8_SHIFT 6 8898 u8 flags3; 8899 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 8900 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 8901 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_MASK 0x3 8902 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_SHIFT 2 8903 #define TSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 8904 #define TSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 4 8905 #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_MASK 0x1 8906 #define TSTORM_IWARP_CONN_AG_CTX_RQ_POST_CF_EN_SHIFT 5 8907 #define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_MASK 0x1 8908 #define TSTORM_IWARP_CONN_AG_CTX_MPA_TIMEOUT_CF_EN_SHIFT 6 8909 #define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 8910 #define TSTORM_IWARP_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7 8911 u8 flags4; 8912 #define TSTORM_IWARP_CONN_AG_CTX_CF4EN_MASK 0x1 8913 #define TSTORM_IWARP_CONN_AG_CTX_CF4EN_SHIFT 0 8914 #define TSTORM_IWARP_CONN_AG_CTX_CF5EN_MASK 0x1 8915 #define TSTORM_IWARP_CONN_AG_CTX_CF5EN_SHIFT 1 8916 #define TSTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 8917 #define TSTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 2 8918 #define TSTORM_IWARP_CONN_AG_CTX_CF7EN_MASK 0x1 8919 #define TSTORM_IWARP_CONN_AG_CTX_CF7EN_SHIFT 3 8920 #define TSTORM_IWARP_CONN_AG_CTX_CF8EN_MASK 0x1 8921 #define TSTORM_IWARP_CONN_AG_CTX_CF8EN_SHIFT 4 8922 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 8923 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5 8924 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_MASK 0x1 8925 #define TSTORM_IWARP_CONN_AG_CTX_FLUSH_OR_ERROR_DETECTED_EN_SHIFT 6 8926 #define TSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 8927 #define TSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 7 8928 u8 flags5; 8929 #define TSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 8930 #define TSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 0 8931 #define TSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 8932 #define TSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1 8933 #define TSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 8934 #define TSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2 8935 #define TSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 8936 #define TSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3 8937 #define TSTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 8938 #define TSTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4 8939 #define TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_MASK 0x1 8940 #define TSTORM_IWARP_CONN_AG_CTX_SND_SQ_CONS_RULE_SHIFT 5 8941 #define TSTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 8942 #define TSTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6 8943 #define TSTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1 8944 #define TSTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7 8945 __le32 reg0; 8946 __le32 reg1; 8947 __le32 unaligned_nxt_seq; 8948 __le32 reg3; 8949 __le32 reg4; 8950 __le32 reg5; 8951 __le32 reg6; 8952 __le32 reg7; 8953 __le32 reg8; 8954 u8 orq_cache_idx; 8955 u8 hq_prod; 8956 __le16 sq_tx_cons_th; 8957 u8 orq_prod; 8958 u8 irq_cons; 8959 __le16 sq_tx_cons; 8960 __le16 conn_dpi; 8961 __le16 rq_prod; 8962 __le32 snd_seq; 8963 __le32 last_hq_sequence; 8964 }; 8965 8966 struct tstorm_iwarp_conn_st_ctx { 8967 __le32 reserved[60]; 8968 }; 8969 8970 struct mstorm_iwarp_conn_st_ctx { 8971 __le32 reserved[32]; 8972 }; 8973 8974 struct ustorm_iwarp_conn_st_ctx { 8975 __le32 reserved[24]; 8976 }; 8977 8978 struct iwarp_conn_context { 8979 struct ystorm_iwarp_conn_st_ctx ystorm_st_context; 8980 struct regpair ystorm_st_padding[2]; 8981 struct pstorm_iwarp_conn_st_ctx pstorm_st_context; 8982 struct regpair pstorm_st_padding[2]; 8983 struct xstorm_iwarp_conn_st_ctx xstorm_st_context; 8984 struct regpair xstorm_st_padding[2]; 8985 struct xstorm_iwarp_conn_ag_ctx xstorm_ag_context; 8986 struct tstorm_iwarp_conn_ag_ctx tstorm_ag_context; 8987 struct timers_context timer_context; 8988 struct ustorm_rdma_conn_ag_ctx ustorm_ag_context; 8989 struct tstorm_iwarp_conn_st_ctx tstorm_st_context; 8990 struct regpair tstorm_st_padding[2]; 8991 struct mstorm_iwarp_conn_st_ctx mstorm_st_context; 8992 struct ustorm_iwarp_conn_st_ctx ustorm_st_context; 8993 }; 8994 8995 struct iwarp_create_qp_ramrod_data { 8996 u8 flags; 8997 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_MASK 0x1 8998 #define IWARP_CREATE_QP_RAMROD_DATA_FMR_AND_RESERVED_EN_SHIFT 0 8999 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_MASK 0x1 9000 #define IWARP_CREATE_QP_RAMROD_DATA_SIGNALED_COMP_SHIFT 1 9001 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 9002 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 2 9003 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 9004 #define IWARP_CREATE_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 3 9005 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 9006 #define IWARP_CREATE_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 4 9007 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_MASK 0x1 9008 #define IWARP_CREATE_QP_RAMROD_DATA_SRQ_FLG_SHIFT 5 9009 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_MASK 0x3 9010 #define IWARP_CREATE_QP_RAMROD_DATA_RESERVED0_SHIFT 6 9011 u8 reserved1; 9012 __le16 pd; 9013 __le16 sq_num_pages; 9014 __le16 rq_num_pages; 9015 __le32 reserved3[2]; 9016 struct regpair qp_handle_for_cqe; 9017 struct rdma_srq_id srq_id; 9018 __le32 cq_cid_for_sq; 9019 __le32 cq_cid_for_rq; 9020 __le16 dpi; 9021 __le16 physical_q0; 9022 __le16 physical_q1; 9023 u8 reserved2[6]; 9024 }; 9025 9026 enum iwarp_eqe_async_opcode { 9027 IWARP_EVENT_TYPE_ASYNC_CONNECT_COMPLETE, 9028 IWARP_EVENT_TYPE_ASYNC_ENHANCED_MPA_REPLY_ARRIVED, 9029 IWARP_EVENT_TYPE_ASYNC_MPA_HANDSHAKE_COMPLETE, 9030 IWARP_EVENT_TYPE_ASYNC_CID_CLEANED, 9031 IWARP_EVENT_TYPE_ASYNC_EXCEPTION_DETECTED, 9032 IWARP_EVENT_TYPE_ASYNC_QP_IN_ERROR_STATE, 9033 IWARP_EVENT_TYPE_ASYNC_CQ_OVERFLOW, 9034 MAX_IWARP_EQE_ASYNC_OPCODE 9035 }; 9036 9037 struct iwarp_eqe_data_mpa_async_completion { 9038 __le16 ulp_data_len; 9039 u8 reserved[6]; 9040 }; 9041 9042 struct iwarp_eqe_data_tcp_async_completion { 9043 __le16 ulp_data_len; 9044 u8 mpa_handshake_mode; 9045 u8 reserved[5]; 9046 }; 9047 9048 enum iwarp_eqe_sync_opcode { 9049 IWARP_EVENT_TYPE_TCP_OFFLOAD = 9050 11, 9051 IWARP_EVENT_TYPE_MPA_OFFLOAD, 9052 IWARP_EVENT_TYPE_MPA_OFFLOAD_SEND_RTR, 9053 IWARP_EVENT_TYPE_CREATE_QP, 9054 IWARP_EVENT_TYPE_QUERY_QP, 9055 IWARP_EVENT_TYPE_MODIFY_QP, 9056 IWARP_EVENT_TYPE_DESTROY_QP, 9057 MAX_IWARP_EQE_SYNC_OPCODE 9058 }; 9059 9060 enum iwarp_fw_return_code { 9061 IWARP_CONN_ERROR_TCP_CONNECT_INVALID_PACKET = 5, 9062 IWARP_CONN_ERROR_TCP_CONNECTION_RST, 9063 IWARP_CONN_ERROR_TCP_CONNECT_TIMEOUT, 9064 IWARP_CONN_ERROR_MPA_ERROR_REJECT, 9065 IWARP_CONN_ERROR_MPA_NOT_SUPPORTED_VER, 9066 IWARP_CONN_ERROR_MPA_RST, 9067 IWARP_CONN_ERROR_MPA_FIN, 9068 IWARP_CONN_ERROR_MPA_RTR_MISMATCH, 9069 IWARP_CONN_ERROR_MPA_INSUF_IRD, 9070 IWARP_CONN_ERROR_MPA_INVALID_PACKET, 9071 IWARP_CONN_ERROR_MPA_LOCAL_ERROR, 9072 IWARP_CONN_ERROR_MPA_TIMEOUT, 9073 IWARP_CONN_ERROR_MPA_TERMINATE, 9074 IWARP_QP_IN_ERROR_GOOD_CLOSE, 9075 IWARP_QP_IN_ERROR_BAD_CLOSE, 9076 IWARP_EXCEPTION_DETECTED_LLP_CLOSED, 9077 IWARP_EXCEPTION_DETECTED_LLP_RESET, 9078 IWARP_EXCEPTION_DETECTED_IRQ_FULL, 9079 IWARP_EXCEPTION_DETECTED_RQ_EMPTY, 9080 IWARP_EXCEPTION_DETECTED_LLP_TIMEOUT, 9081 IWARP_EXCEPTION_DETECTED_REMOTE_PROTECTION_ERROR, 9082 IWARP_EXCEPTION_DETECTED_CQ_OVERFLOW, 9083 IWARP_EXCEPTION_DETECTED_LOCAL_CATASTROPHIC, 9084 IWARP_EXCEPTION_DETECTED_LOCAL_ACCESS_ERROR, 9085 IWARP_EXCEPTION_DETECTED_REMOTE_OPERATION_ERROR, 9086 IWARP_EXCEPTION_DETECTED_TERMINATE_RECEIVED, 9087 MAX_IWARP_FW_RETURN_CODE 9088 }; 9089 9090 struct iwarp_init_func_params { 9091 u8 ll2_ooo_q_index; 9092 u8 reserved1[7]; 9093 }; 9094 9095 struct iwarp_init_func_ramrod_data { 9096 struct rdma_init_func_ramrod_data rdma; 9097 struct tcp_init_params tcp; 9098 struct iwarp_init_func_params iwarp; 9099 }; 9100 9101 enum iwarp_modify_qp_new_state_type { 9102 IWARP_MODIFY_QP_STATE_CLOSING = 1, 9103 IWARP_MODIFY_QP_STATE_ERROR = 9104 2, 9105 MAX_IWARP_MODIFY_QP_NEW_STATE_TYPE 9106 }; 9107 9108 struct iwarp_modify_qp_ramrod_data { 9109 __le16 transition_to_state; 9110 __le16 flags; 9111 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_MASK 0x1 9112 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_RD_EN_SHIFT 0 9113 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_MASK 0x1 9114 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_WR_EN_SHIFT 1 9115 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_MASK 0x1 9116 #define IWARP_MODIFY_QP_RAMROD_DATA_ATOMIC_EN_SHIFT 2 9117 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_MASK 0x1 9118 #define IWARP_MODIFY_QP_RAMROD_DATA_STATE_TRANS_EN_SHIFT 3 9119 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_MASK 0x1 9120 #define IWARP_MODIFY_QP_RAMROD_DATA_RDMA_OPS_EN_FLG_SHIFT 4 9121 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_MASK 0x7FF 9122 #define IWARP_MODIFY_QP_RAMROD_DATA_RESERVED_SHIFT 5 9123 __le32 reserved3[3]; 9124 __le32 reserved4[8]; 9125 }; 9126 9127 struct mpa_rq_params { 9128 __le32 ird; 9129 __le32 ord; 9130 }; 9131 9132 struct mpa_ulp_buffer { 9133 struct regpair addr; 9134 __le16 len; 9135 __le16 reserved[3]; 9136 }; 9137 9138 struct mpa_outgoing_params { 9139 u8 crc_needed; 9140 u8 reject; 9141 u8 reserved[6]; 9142 struct mpa_rq_params out_rq; 9143 struct mpa_ulp_buffer outgoing_ulp_buffer; 9144 }; 9145 9146 struct iwarp_mpa_offload_ramrod_data { 9147 struct mpa_outgoing_params common; 9148 __le32 tcp_cid; 9149 u8 mode; 9150 u8 tcp_connect_side; 9151 u8 rtr_pref; 9152 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_MASK 0x7 9153 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RTR_SUPPORTED_SHIFT 0 9154 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_MASK 0x1F 9155 #define IWARP_MPA_OFFLOAD_RAMROD_DATA_RESERVED1_SHIFT 3 9156 u8 reserved2; 9157 struct mpa_ulp_buffer incoming_ulp_buffer; 9158 struct regpair async_eqe_output_buf; 9159 struct regpair handle_for_async; 9160 struct regpair shared_queue_addr; 9161 u8 stats_counter_id; 9162 u8 reserved3[15]; 9163 }; 9164 9165 struct iwarp_offload_params { 9166 struct mpa_ulp_buffer incoming_ulp_buffer; 9167 struct regpair async_eqe_output_buf; 9168 struct regpair handle_for_async; 9169 __le16 physical_q0; 9170 __le16 physical_q1; 9171 u8 stats_counter_id; 9172 u8 mpa_mode; 9173 u8 reserved[10]; 9174 }; 9175 9176 struct iwarp_query_qp_output_params { 9177 __le32 flags; 9178 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_MASK 0x1 9179 #define IWARP_QUERY_QP_OUTPUT_PARAMS_ERROR_FLG_SHIFT 0 9180 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_MASK 0x7FFFFFFF 9181 #define IWARP_QUERY_QP_OUTPUT_PARAMS_RESERVED0_SHIFT 1 9182 u8 reserved1[4]; 9183 }; 9184 9185 struct iwarp_query_qp_ramrod_data { 9186 struct regpair output_params_addr; 9187 }; 9188 9189 enum iwarp_ramrod_cmd_id { 9190 IWARP_RAMROD_CMD_ID_TCP_OFFLOAD = 9191 11, 9192 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD, 9193 IWARP_RAMROD_CMD_ID_MPA_OFFLOAD_SEND_RTR, 9194 IWARP_RAMROD_CMD_ID_CREATE_QP, 9195 IWARP_RAMROD_CMD_ID_QUERY_QP, 9196 IWARP_RAMROD_CMD_ID_MODIFY_QP, 9197 IWARP_RAMROD_CMD_ID_DESTROY_QP, 9198 MAX_IWARP_RAMROD_CMD_ID 9199 }; 9200 9201 struct iwarp_rxmit_stats_drv { 9202 struct regpair tx_go_to_slow_start_event_cnt; 9203 struct regpair tx_fast_retransmit_event_cnt; 9204 }; 9205 9206 struct iwarp_tcp_offload_ramrod_data { 9207 struct iwarp_offload_params iwarp; 9208 struct tcp_offload_params_opt2 tcp; 9209 }; 9210 9211 enum mpa_negotiation_mode { 9212 MPA_NEGOTIATION_TYPE_BASIC = 1, 9213 MPA_NEGOTIATION_TYPE_ENHANCED = 2, 9214 MAX_MPA_NEGOTIATION_MODE 9215 }; 9216 9217 enum mpa_rtr_type { 9218 MPA_RTR_TYPE_NONE = 0, 9219 MPA_RTR_TYPE_ZERO_SEND = 1, 9220 MPA_RTR_TYPE_ZERO_WRITE = 2, 9221 MPA_RTR_TYPE_ZERO_SEND_AND_WRITE = 3, 9222 MPA_RTR_TYPE_ZERO_READ = 4, 9223 MPA_RTR_TYPE_ZERO_SEND_AND_READ = 5, 9224 MPA_RTR_TYPE_ZERO_WRITE_AND_READ = 6, 9225 MPA_RTR_TYPE_ZERO_SEND_AND_WRITE_AND_READ = 7, 9226 MAX_MPA_RTR_TYPE 9227 }; 9228 9229 struct unaligned_opaque_data { 9230 __le16 first_mpa_offset; 9231 u8 tcp_payload_offset; 9232 u8 flags; 9233 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_MASK 0x1 9234 #define UNALIGNED_OPAQUE_DATA_PKT_REACHED_WIN_RIGHT_EDGE_SHIFT 0 9235 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_MASK 0x1 9236 #define UNALIGNED_OPAQUE_DATA_CONNECTION_CLOSED_SHIFT 1 9237 #define UNALIGNED_OPAQUE_DATA_RESERVED_MASK 0x3F 9238 #define UNALIGNED_OPAQUE_DATA_RESERVED_SHIFT 2 9239 __le32 cid; 9240 }; 9241 9242 struct mstorm_iwarp_conn_ag_ctx { 9243 u8 reserved; 9244 u8 state; 9245 u8 flags0; 9246 #define MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 9247 #define MSTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 9248 #define MSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 9249 #define MSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 9250 #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_MASK 0x3 9251 #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_SHIFT 2 9252 #define MSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 9253 #define MSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 9254 #define MSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 9255 #define MSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 9256 u8 flags1; 9257 #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_MASK 0x1 9258 #define MSTORM_IWARP_CONN_AG_CTX_INV_STAG_DONE_CF_EN_SHIFT 0 9259 #define MSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 9260 #define MSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 9261 #define MSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 9262 #define MSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 9263 #define MSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 9264 #define MSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3 9265 #define MSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 9266 #define MSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4 9267 #define MSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 9268 #define MSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5 9269 #define MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_MASK 0x1 9270 #define MSTORM_IWARP_CONN_AG_CTX_RCQ_CONS_EN_SHIFT 6 9271 #define MSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 9272 #define MSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7 9273 __le16 rcq_cons; 9274 __le16 rcq_cons_th; 9275 __le32 reg0; 9276 __le32 reg1; 9277 }; 9278 9279 struct ustorm_iwarp_conn_ag_ctx { 9280 u8 reserved; 9281 u8 byte1; 9282 u8 flags0; 9283 #define USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 9284 #define USTORM_IWARP_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 9285 #define USTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 9286 #define USTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 9287 #define USTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 9288 #define USTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2 9289 #define USTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 9290 #define USTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 9291 #define USTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 9292 #define USTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 9293 u8 flags1; 9294 #define USTORM_IWARP_CONN_AG_CTX_CF3_MASK 0x3 9295 #define USTORM_IWARP_CONN_AG_CTX_CF3_SHIFT 0 9296 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 9297 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 9298 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 9299 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 9300 #define USTORM_IWARP_CONN_AG_CTX_CF6_MASK 0x3 9301 #define USTORM_IWARP_CONN_AG_CTX_CF6_SHIFT 6 9302 u8 flags2; 9303 #define USTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 9304 #define USTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0 9305 #define USTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 9306 #define USTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 9307 #define USTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 9308 #define USTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 9309 #define USTORM_IWARP_CONN_AG_CTX_CF3EN_MASK 0x1 9310 #define USTORM_IWARP_CONN_AG_CTX_CF3EN_SHIFT 3 9311 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 9312 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 9313 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 9314 #define USTORM_IWARP_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 9315 #define USTORM_IWARP_CONN_AG_CTX_CF6EN_MASK 0x1 9316 #define USTORM_IWARP_CONN_AG_CTX_CF6EN_SHIFT 6 9317 #define USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 9318 #define USTORM_IWARP_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 9319 u8 flags3; 9320 #define USTORM_IWARP_CONN_AG_CTX_CQ_EN_MASK 0x1 9321 #define USTORM_IWARP_CONN_AG_CTX_CQ_EN_SHIFT 0 9322 #define USTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 9323 #define USTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 1 9324 #define USTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 9325 #define USTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 2 9326 #define USTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 9327 #define USTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 3 9328 #define USTORM_IWARP_CONN_AG_CTX_RULE5EN_MASK 0x1 9329 #define USTORM_IWARP_CONN_AG_CTX_RULE5EN_SHIFT 4 9330 #define USTORM_IWARP_CONN_AG_CTX_RULE6EN_MASK 0x1 9331 #define USTORM_IWARP_CONN_AG_CTX_RULE6EN_SHIFT 5 9332 #define USTORM_IWARP_CONN_AG_CTX_RULE7EN_MASK 0x1 9333 #define USTORM_IWARP_CONN_AG_CTX_RULE7EN_SHIFT 6 9334 #define USTORM_IWARP_CONN_AG_CTX_RULE8EN_MASK 0x1 9335 #define USTORM_IWARP_CONN_AG_CTX_RULE8EN_SHIFT 7 9336 u8 byte2; 9337 u8 byte3; 9338 __le16 word0; 9339 __le16 word1; 9340 __le32 cq_cons; 9341 __le32 cq_se_prod; 9342 __le32 cq_prod; 9343 __le32 reg3; 9344 __le16 word2; 9345 __le16 word3; 9346 }; 9347 9348 struct ystorm_iwarp_conn_ag_ctx { 9349 u8 byte0; 9350 u8 byte1; 9351 u8 flags0; 9352 #define YSTORM_IWARP_CONN_AG_CTX_BIT0_MASK 0x1 9353 #define YSTORM_IWARP_CONN_AG_CTX_BIT0_SHIFT 0 9354 #define YSTORM_IWARP_CONN_AG_CTX_BIT1_MASK 0x1 9355 #define YSTORM_IWARP_CONN_AG_CTX_BIT1_SHIFT 1 9356 #define YSTORM_IWARP_CONN_AG_CTX_CF0_MASK 0x3 9357 #define YSTORM_IWARP_CONN_AG_CTX_CF0_SHIFT 2 9358 #define YSTORM_IWARP_CONN_AG_CTX_CF1_MASK 0x3 9359 #define YSTORM_IWARP_CONN_AG_CTX_CF1_SHIFT 4 9360 #define YSTORM_IWARP_CONN_AG_CTX_CF2_MASK 0x3 9361 #define YSTORM_IWARP_CONN_AG_CTX_CF2_SHIFT 6 9362 u8 flags1; 9363 #define YSTORM_IWARP_CONN_AG_CTX_CF0EN_MASK 0x1 9364 #define YSTORM_IWARP_CONN_AG_CTX_CF0EN_SHIFT 0 9365 #define YSTORM_IWARP_CONN_AG_CTX_CF1EN_MASK 0x1 9366 #define YSTORM_IWARP_CONN_AG_CTX_CF1EN_SHIFT 1 9367 #define YSTORM_IWARP_CONN_AG_CTX_CF2EN_MASK 0x1 9368 #define YSTORM_IWARP_CONN_AG_CTX_CF2EN_SHIFT 2 9369 #define YSTORM_IWARP_CONN_AG_CTX_RULE0EN_MASK 0x1 9370 #define YSTORM_IWARP_CONN_AG_CTX_RULE0EN_SHIFT 3 9371 #define YSTORM_IWARP_CONN_AG_CTX_RULE1EN_MASK 0x1 9372 #define YSTORM_IWARP_CONN_AG_CTX_RULE1EN_SHIFT 4 9373 #define YSTORM_IWARP_CONN_AG_CTX_RULE2EN_MASK 0x1 9374 #define YSTORM_IWARP_CONN_AG_CTX_RULE2EN_SHIFT 5 9375 #define YSTORM_IWARP_CONN_AG_CTX_RULE3EN_MASK 0x1 9376 #define YSTORM_IWARP_CONN_AG_CTX_RULE3EN_SHIFT 6 9377 #define YSTORM_IWARP_CONN_AG_CTX_RULE4EN_MASK 0x1 9378 #define YSTORM_IWARP_CONN_AG_CTX_RULE4EN_SHIFT 7 9379 u8 byte2; 9380 u8 byte3; 9381 __le16 word0; 9382 __le32 reg0; 9383 __le32 reg1; 9384 __le16 word1; 9385 __le16 word2; 9386 __le16 word3; 9387 __le16 word4; 9388 __le32 reg2; 9389 __le32 reg3; 9390 }; 9391 9392 struct ystorm_fcoe_conn_st_ctx { 9393 u8 func_mode; 9394 u8 cos; 9395 u8 conf_version; 9396 u8 eth_hdr_size; 9397 __le16 stat_ram_addr; 9398 __le16 mtu; 9399 __le16 max_fc_payload_len; 9400 __le16 tx_max_fc_pay_len; 9401 u8 fcp_cmd_size; 9402 u8 fcp_rsp_size; 9403 __le16 mss; 9404 struct regpair reserved; 9405 __le16 min_frame_size; 9406 u8 protection_info_flags; 9407 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1 9408 #define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 0 9409 #define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1 9410 #define YSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 1 9411 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK 0x3F 9412 #define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_SHIFT 2 9413 u8 dst_protection_per_mss; 9414 u8 src_protection_per_mss; 9415 u8 ptu_log_page_size; 9416 u8 flags; 9417 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 9418 #define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 0 9419 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1 9420 #define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 1 9421 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x3F 9422 #define YSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 2 9423 u8 fcp_xfer_size; 9424 }; 9425 9426 struct fcoe_vlan_fields { 9427 __le16 fields; 9428 #define FCOE_VLAN_FIELDS_VID_MASK 0xFFF 9429 #define FCOE_VLAN_FIELDS_VID_SHIFT 0 9430 #define FCOE_VLAN_FIELDS_CLI_MASK 0x1 9431 #define FCOE_VLAN_FIELDS_CLI_SHIFT 12 9432 #define FCOE_VLAN_FIELDS_PRI_MASK 0x7 9433 #define FCOE_VLAN_FIELDS_PRI_SHIFT 13 9434 }; 9435 9436 union fcoe_vlan_field_union { 9437 struct fcoe_vlan_fields fields; 9438 __le16 val; 9439 }; 9440 9441 union fcoe_vlan_vif_field_union { 9442 union fcoe_vlan_field_union vlan; 9443 __le16 vif; 9444 }; 9445 9446 struct pstorm_fcoe_eth_context_section { 9447 u8 remote_addr_3; 9448 u8 remote_addr_2; 9449 u8 remote_addr_1; 9450 u8 remote_addr_0; 9451 u8 local_addr_1; 9452 u8 local_addr_0; 9453 u8 remote_addr_5; 9454 u8 remote_addr_4; 9455 u8 local_addr_5; 9456 u8 local_addr_4; 9457 u8 local_addr_3; 9458 u8 local_addr_2; 9459 union fcoe_vlan_vif_field_union vif_outer_vlan; 9460 __le16 vif_outer_eth_type; 9461 union fcoe_vlan_vif_field_union inner_vlan; 9462 __le16 inner_eth_type; 9463 }; 9464 9465 struct pstorm_fcoe_conn_st_ctx { 9466 u8 func_mode; 9467 u8 cos; 9468 u8 conf_version; 9469 u8 rsrv; 9470 __le16 stat_ram_addr; 9471 __le16 mss; 9472 struct regpair abts_cleanup_addr; 9473 struct pstorm_fcoe_eth_context_section eth; 9474 u8 sid_2; 9475 u8 sid_1; 9476 u8 sid_0; 9477 u8 flags; 9478 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1 9479 #define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT 0 9480 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1 9481 #define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT 1 9482 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 9483 #define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 2 9484 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1 9485 #define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 3 9486 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0xF 9487 #define PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 4 9488 u8 did_2; 9489 u8 did_1; 9490 u8 did_0; 9491 u8 src_mac_index; 9492 __le16 rec_rr_tov_val; 9493 u8 q_relative_offset; 9494 u8 reserved1; 9495 }; 9496 9497 struct xstorm_fcoe_conn_st_ctx { 9498 u8 func_mode; 9499 u8 src_mac_index; 9500 u8 conf_version; 9501 u8 cached_wqes_avail; 9502 __le16 stat_ram_addr; 9503 u8 flags; 9504 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK 0x1 9505 #define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT 0 9506 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 9507 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 1 9508 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK 0x1 9509 #define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_SHIFT 2 9510 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3 9511 #define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT 3 9512 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x7 9513 #define XSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 5 9514 u8 cached_wqes_offset; 9515 u8 reserved2; 9516 u8 eth_hdr_size; 9517 u8 seq_id; 9518 u8 max_conc_seqs; 9519 __le16 num_pages_in_pbl; 9520 __le16 reserved; 9521 struct regpair sq_pbl_addr; 9522 struct regpair sq_curr_page_addr; 9523 struct regpair sq_next_page_addr; 9524 struct regpair xferq_pbl_addr; 9525 struct regpair xferq_curr_page_addr; 9526 struct regpair xferq_next_page_addr; 9527 struct regpair respq_pbl_addr; 9528 struct regpair respq_curr_page_addr; 9529 struct regpair respq_next_page_addr; 9530 __le16 mtu; 9531 __le16 tx_max_fc_pay_len; 9532 __le16 max_fc_payload_len; 9533 __le16 min_frame_size; 9534 __le16 sq_pbl_next_index; 9535 __le16 respq_pbl_next_index; 9536 u8 fcp_cmd_byte_credit; 9537 u8 fcp_rsp_byte_credit; 9538 __le16 protection_info; 9539 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK 0x1 9540 #define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT 0 9541 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1 9542 #define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 1 9543 #define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1 9544 #define XSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 2 9545 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK 0x1 9546 #define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT 3 9547 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK 0xF 9548 #define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_SHIFT 4 9549 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK 0xFF 9550 #define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_SHIFT 8 9551 __le16 xferq_pbl_next_index; 9552 __le16 page_size; 9553 u8 mid_seq; 9554 u8 fcp_xfer_byte_credit; 9555 u8 reserved1[2]; 9556 struct fcoe_wqe cached_wqes[16]; 9557 }; 9558 9559 struct xstorm_fcoe_conn_ag_ctx { 9560 u8 reserved0; 9561 u8 fcoe_state; 9562 u8 flags0; 9563 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 9564 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 9565 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1 9566 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT 1 9567 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1 9568 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT 2 9569 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 9570 #define XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 9571 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1 9572 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT 4 9573 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1 9574 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT 5 9575 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1 9576 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT 6 9577 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1 9578 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT 7 9579 u8 flags1; 9580 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1 9581 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0 9582 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1 9583 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT 1 9584 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1 9585 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT 2 9586 #define XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1 9587 #define XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT 3 9588 #define XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1 9589 #define XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT 4 9590 #define XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1 9591 #define XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT 5 9592 #define XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1 9593 #define XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT 6 9594 #define XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1 9595 #define XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT 7 9596 u8 flags2; 9597 #define XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 9598 #define XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0 9599 #define XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 9600 #define XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 2 9601 #define XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 9602 #define XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 4 9603 #define XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3 9604 #define XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 6 9605 u8 flags3; 9606 #define XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 9607 #define XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0 9608 #define XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 9609 #define XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 2 9610 #define XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 9611 #define XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 4 9612 #define XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3 9613 #define XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 6 9614 u8 flags4; 9615 #define XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3 9616 #define XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0 9617 #define XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3 9618 #define XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 2 9619 #define XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3 9620 #define XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 4 9621 #define XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3 9622 #define XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT 6 9623 u8 flags5; 9624 #define XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3 9625 #define XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0 9626 #define XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3 9627 #define XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT 2 9628 #define XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3 9629 #define XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT 4 9630 #define XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3 9631 #define XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT 6 9632 u8 flags6; 9633 #define XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3 9634 #define XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0 9635 #define XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3 9636 #define XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT 2 9637 #define XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3 9638 #define XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT 4 9639 #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3 9640 #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT 6 9641 u8 flags7; 9642 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 9643 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 9644 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3 9645 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT 2 9646 #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 9647 #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 9648 #define XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 9649 #define XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 6 9650 #define XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 9651 #define XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 7 9652 u8 flags8; 9653 #define XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 9654 #define XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0 9655 #define XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 9656 #define XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 1 9657 #define XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 9658 #define XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 2 9659 #define XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 9660 #define XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 3 9661 #define XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 9662 #define XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 4 9663 #define XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 9664 #define XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 5 9665 #define XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 9666 #define XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 6 9667 #define XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 9668 #define XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 7 9669 u8 flags9; 9670 #define XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 9671 #define XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0 9672 #define XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1 9673 #define XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT 1 9674 #define XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1 9675 #define XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT 2 9676 #define XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1 9677 #define XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT 3 9678 #define XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1 9679 #define XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT 4 9680 #define XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1 9681 #define XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT 5 9682 #define XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1 9683 #define XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT 6 9684 #define XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1 9685 #define XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT 7 9686 u8 flags10; 9687 #define XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1 9688 #define XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0 9689 #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 9690 #define XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT 1 9691 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 9692 #define XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 9693 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1 9694 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT 3 9695 #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 9696 #define XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 9697 #define XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1 9698 #define XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT 5 9699 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1 9700 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT 6 9701 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1 9702 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT 7 9703 u8 flags11; 9704 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1 9705 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0 9706 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1 9707 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT 1 9708 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1 9709 #define XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT 2 9710 #define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 9711 #define XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 3 9712 #define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 9713 #define XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 4 9714 #define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 9715 #define XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 5 9716 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 9717 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 9718 #define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1 9719 #define XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7 9720 u8 flags12; 9721 #define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1 9722 #define XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0 9723 #define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1 9724 #define XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT 1 9725 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 9726 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 9727 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 9728 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 9729 #define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1 9730 #define XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT 4 9731 #define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1 9732 #define XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT 5 9733 #define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1 9734 #define XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT 6 9735 #define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1 9736 #define XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT 7 9737 u8 flags13; 9738 #define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1 9739 #define XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0 9740 #define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1 9741 #define XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT 1 9742 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 9743 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 9744 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 9745 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 9746 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 9747 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 9748 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 9749 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 9750 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 9751 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 9752 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 9753 #define XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 9754 u8 flags14; 9755 #define XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1 9756 #define XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0 9757 #define XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1 9758 #define XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT 1 9759 #define XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1 9760 #define XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT 2 9761 #define XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1 9762 #define XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT 3 9763 #define XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1 9764 #define XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT 4 9765 #define XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1 9766 #define XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT 5 9767 #define XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3 9768 #define XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT 6 9769 u8 byte2; 9770 __le16 physical_q0; 9771 __le16 word1; 9772 __le16 word2; 9773 __le16 sq_cons; 9774 __le16 sq_prod; 9775 __le16 xferq_prod; 9776 __le16 xferq_cons; 9777 u8 byte3; 9778 u8 byte4; 9779 u8 byte5; 9780 u8 byte6; 9781 __le32 remain_io; 9782 __le32 reg1; 9783 __le32 reg2; 9784 __le32 reg3; 9785 __le32 reg4; 9786 __le32 reg5; 9787 __le32 reg6; 9788 __le16 respq_prod; 9789 __le16 respq_cons; 9790 __le16 word9; 9791 __le16 word10; 9792 __le32 reg7; 9793 __le32 reg8; 9794 }; 9795 9796 struct ustorm_fcoe_conn_st_ctx { 9797 struct regpair respq_pbl_addr; 9798 __le16 num_pages_in_pbl; 9799 u8 ptu_log_page_size; 9800 u8 log_page_size; 9801 __le16 respq_prod; 9802 u8 reserved[2]; 9803 }; 9804 9805 struct tstorm_fcoe_conn_ag_ctx { 9806 u8 reserved0; 9807 u8 fcoe_state; 9808 u8 flags0; 9809 #define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 9810 #define TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 9811 #define TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 9812 #define TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 9813 #define TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1 9814 #define TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT 2 9815 #define TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1 9816 #define TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT 3 9817 #define TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1 9818 #define TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT 4 9819 #define TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1 9820 #define TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT 5 9821 #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3 9822 #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT 6 9823 u8 flags1; 9824 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 9825 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0 9826 #define TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 9827 #define TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 2 9828 #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 9829 #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 9830 #define TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 9831 #define TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 6 9832 u8 flags2; 9833 #define TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 9834 #define TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0 9835 #define TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 9836 #define TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 2 9837 #define TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3 9838 #define TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 4 9839 #define TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3 9840 #define TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 6 9841 u8 flags3; 9842 #define TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3 9843 #define TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0 9844 #define TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3 9845 #define TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 2 9846 #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1 9847 #define TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT 4 9848 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 9849 #define TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 9850 #define TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 9851 #define TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 6 9852 #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 9853 #define TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 9854 u8 flags4; 9855 #define TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 9856 #define TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0 9857 #define TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 9858 #define TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 1 9859 #define TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 9860 #define TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 2 9861 #define TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 9862 #define TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 3 9863 #define TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 9864 #define TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 4 9865 #define TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 9866 #define TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 5 9867 #define TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 9868 #define TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 6 9869 #define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 9870 #define TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7 9871 u8 flags5; 9872 #define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 9873 #define TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0 9874 #define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 9875 #define TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1 9876 #define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 9877 #define TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2 9878 #define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 9879 #define TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3 9880 #define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 9881 #define TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4 9882 #define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 9883 #define TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5 9884 #define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 9885 #define TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6 9886 #define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 9887 #define TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7 9888 __le32 reg0; 9889 __le32 reg1; 9890 }; 9891 9892 struct ustorm_fcoe_conn_ag_ctx { 9893 u8 byte0; 9894 u8 byte1; 9895 u8 flags0; 9896 #define USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 9897 #define USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 9898 #define USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 9899 #define USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 9900 #define USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 9901 #define USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 9902 #define USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 9903 #define USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 9904 #define USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 9905 #define USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 9906 u8 flags1; 9907 #define USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3 9908 #define USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0 9909 #define USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 9910 #define USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 2 9911 #define USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 9912 #define USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 4 9913 #define USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 9914 #define USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 6 9915 u8 flags2; 9916 #define USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 9917 #define USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 9918 #define USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 9919 #define USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 9920 #define USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 9921 #define USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 9922 #define USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 9923 #define USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 3 9924 #define USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 9925 #define USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 4 9926 #define USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 9927 #define USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 5 9928 #define USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 9929 #define USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 6 9930 #define USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 9931 #define USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7 9932 u8 flags3; 9933 #define USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 9934 #define USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0 9935 #define USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 9936 #define USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1 9937 #define USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 9938 #define USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2 9939 #define USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 9940 #define USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3 9941 #define USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 9942 #define USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4 9943 #define USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 9944 #define USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5 9945 #define USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 9946 #define USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6 9947 #define USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 9948 #define USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7 9949 u8 byte2; 9950 u8 byte3; 9951 __le16 word0; 9952 __le16 word1; 9953 __le32 reg0; 9954 __le32 reg1; 9955 __le32 reg2; 9956 __le32 reg3; 9957 __le16 word2; 9958 __le16 word3; 9959 }; 9960 9961 struct tstorm_fcoe_conn_st_ctx { 9962 __le16 stat_ram_addr; 9963 __le16 rx_max_fc_payload_len; 9964 __le16 e_d_tov_val; 9965 u8 flags; 9966 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK 0x1 9967 #define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT 0 9968 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK 0x1 9969 #define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT 1 9970 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK 0x3F 9971 #define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT 2 9972 u8 timers_cleanup_invocation_cnt; 9973 __le32 reserved1[2]; 9974 __le32 dst_mac_address_bytes0to3; 9975 __le16 dst_mac_address_bytes4to5; 9976 __le16 ramrod_echo; 9977 u8 flags1; 9978 #define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK 0x3 9979 #define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT 0 9980 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x3F 9981 #define TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 2 9982 u8 q_relative_offset; 9983 u8 bdq_resource_id; 9984 u8 reserved0[5]; 9985 }; 9986 9987 struct mstorm_fcoe_conn_ag_ctx { 9988 u8 byte0; 9989 u8 byte1; 9990 u8 flags0; 9991 #define MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 9992 #define MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 9993 #define MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 9994 #define MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 9995 #define MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 9996 #define MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 9997 #define MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 9998 #define MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 9999 #define MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 10000 #define MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 10001 u8 flags1; 10002 #define MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 10003 #define MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 10004 #define MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 10005 #define MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 10006 #define MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 10007 #define MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 10008 #define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 10009 #define MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3 10010 #define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 10011 #define MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4 10012 #define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 10013 #define MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5 10014 #define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 10015 #define MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6 10016 #define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 10017 #define MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7 10018 __le16 word0; 10019 __le16 word1; 10020 __le32 reg0; 10021 __le32 reg1; 10022 }; 10023 10024 struct fcoe_mstorm_fcoe_conn_st_ctx_fp { 10025 __le16 xfer_prod; 10026 __le16 reserved1; 10027 u8 protection_info; 10028 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK 0x1 10029 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_SHIFT 0 10030 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK 0x1 10031 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_SHIFT 1 10032 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_MASK 0x3F 10033 #define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_SHIFT 2 10034 u8 q_relative_offset; 10035 u8 reserved2[2]; 10036 }; 10037 10038 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp { 10039 __le16 conn_id; 10040 __le16 stat_ram_addr; 10041 __le16 num_pages_in_pbl; 10042 u8 ptu_log_page_size; 10043 u8 log_page_size; 10044 __le16 unsolicited_cq_count; 10045 __le16 cmdq_count; 10046 u8 bdq_resource_id; 10047 u8 reserved0[3]; 10048 struct regpair xferq_pbl_addr; 10049 struct regpair reserved1; 10050 struct regpair reserved2[3]; 10051 }; 10052 10053 struct mstorm_fcoe_conn_st_ctx { 10054 struct fcoe_mstorm_fcoe_conn_st_ctx_fp fp; 10055 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp non_fp; 10056 }; 10057 10058 struct fcoe_conn_context { 10059 struct ystorm_fcoe_conn_st_ctx ystorm_st_context; 10060 struct pstorm_fcoe_conn_st_ctx pstorm_st_context; 10061 struct regpair pstorm_st_padding[2]; 10062 struct xstorm_fcoe_conn_st_ctx xstorm_st_context; 10063 struct xstorm_fcoe_conn_ag_ctx xstorm_ag_context; 10064 struct regpair xstorm_ag_padding[6]; 10065 struct ustorm_fcoe_conn_st_ctx ustorm_st_context; 10066 struct regpair ustorm_st_padding[2]; 10067 struct tstorm_fcoe_conn_ag_ctx tstorm_ag_context; 10068 struct regpair tstorm_ag_padding[2]; 10069 struct timers_context timer_context; 10070 struct ustorm_fcoe_conn_ag_ctx ustorm_ag_context; 10071 struct tstorm_fcoe_conn_st_ctx tstorm_st_context; 10072 struct mstorm_fcoe_conn_ag_ctx mstorm_ag_context; 10073 struct mstorm_fcoe_conn_st_ctx mstorm_st_context; 10074 }; 10075 10076 struct fcoe_conn_offload_ramrod_params { 10077 struct fcoe_conn_offload_ramrod_data offload_ramrod_data; 10078 }; 10079 10080 struct fcoe_conn_terminate_ramrod_params { 10081 struct fcoe_conn_terminate_ramrod_data terminate_ramrod_data; 10082 }; 10083 10084 enum fcoe_event_type { 10085 FCOE_EVENT_INIT_FUNC, 10086 FCOE_EVENT_DESTROY_FUNC, 10087 FCOE_EVENT_STAT_FUNC, 10088 FCOE_EVENT_OFFLOAD_CONN, 10089 FCOE_EVENT_TERMINATE_CONN, 10090 FCOE_EVENT_ERROR, 10091 MAX_FCOE_EVENT_TYPE 10092 }; 10093 10094 struct fcoe_init_ramrod_params { 10095 struct fcoe_init_func_ramrod_data init_ramrod_data; 10096 }; 10097 10098 enum fcoe_ramrod_cmd_id { 10099 FCOE_RAMROD_CMD_ID_INIT_FUNC, 10100 FCOE_RAMROD_CMD_ID_DESTROY_FUNC, 10101 FCOE_RAMROD_CMD_ID_STAT_FUNC, 10102 FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, 10103 FCOE_RAMROD_CMD_ID_TERMINATE_CONN, 10104 MAX_FCOE_RAMROD_CMD_ID 10105 }; 10106 10107 struct fcoe_stat_ramrod_params { 10108 struct fcoe_stat_ramrod_data stat_ramrod_data; 10109 }; 10110 10111 struct ystorm_fcoe_conn_ag_ctx { 10112 u8 byte0; 10113 u8 byte1; 10114 u8 flags0; 10115 #define YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 10116 #define YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 10117 #define YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 10118 #define YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 10119 #define YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 10120 #define YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 10121 #define YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 10122 #define YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 10123 #define YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 10124 #define YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 10125 u8 flags1; 10126 #define YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 10127 #define YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 10128 #define YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 10129 #define YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 10130 #define YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 10131 #define YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 10132 #define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 10133 #define YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3 10134 #define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 10135 #define YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4 10136 #define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 10137 #define YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5 10138 #define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 10139 #define YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6 10140 #define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 10141 #define YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7 10142 u8 byte2; 10143 u8 byte3; 10144 __le16 word0; 10145 __le32 reg0; 10146 __le32 reg1; 10147 __le16 word1; 10148 __le16 word2; 10149 __le16 word3; 10150 __le16 word4; 10151 __le32 reg2; 10152 __le32 reg3; 10153 }; 10154 10155 struct ystorm_iscsi_conn_st_ctx { 10156 __le32 reserved[4]; 10157 }; 10158 10159 struct pstorm_iscsi_tcp_conn_st_ctx { 10160 __le32 tcp[32]; 10161 __le32 iscsi[4]; 10162 }; 10163 10164 struct xstorm_iscsi_tcp_conn_st_ctx { 10165 __le32 reserved_iscsi[40]; 10166 __le32 reserved_tcp[4]; 10167 }; 10168 10169 struct xstorm_iscsi_conn_ag_ctx { 10170 u8 cdu_validation; 10171 u8 state; 10172 u8 flags0; 10173 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 10174 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 10175 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_MASK 0x1 10176 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM1_SHIFT 1 10177 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_MASK 0x1 10178 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED1_SHIFT 2 10179 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 10180 #define XSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 10181 #define XSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1 10182 #define XSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4 10183 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_MASK 0x1 10184 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED2_SHIFT 5 10185 #define XSTORM_ISCSI_CONN_AG_CTX_BIT6_MASK 0x1 10186 #define XSTORM_ISCSI_CONN_AG_CTX_BIT6_SHIFT 6 10187 #define XSTORM_ISCSI_CONN_AG_CTX_BIT7_MASK 0x1 10188 #define XSTORM_ISCSI_CONN_AG_CTX_BIT7_SHIFT 7 10189 u8 flags1; 10190 #define XSTORM_ISCSI_CONN_AG_CTX_BIT8_MASK 0x1 10191 #define XSTORM_ISCSI_CONN_AG_CTX_BIT8_SHIFT 0 10192 #define XSTORM_ISCSI_CONN_AG_CTX_BIT9_MASK 0x1 10193 #define XSTORM_ISCSI_CONN_AG_CTX_BIT9_SHIFT 1 10194 #define XSTORM_ISCSI_CONN_AG_CTX_BIT10_MASK 0x1 10195 #define XSTORM_ISCSI_CONN_AG_CTX_BIT10_SHIFT 2 10196 #define XSTORM_ISCSI_CONN_AG_CTX_BIT11_MASK 0x1 10197 #define XSTORM_ISCSI_CONN_AG_CTX_BIT11_SHIFT 3 10198 #define XSTORM_ISCSI_CONN_AG_CTX_BIT12_MASK 0x1 10199 #define XSTORM_ISCSI_CONN_AG_CTX_BIT12_SHIFT 4 10200 #define XSTORM_ISCSI_CONN_AG_CTX_BIT13_MASK 0x1 10201 #define XSTORM_ISCSI_CONN_AG_CTX_BIT13_SHIFT 5 10202 #define XSTORM_ISCSI_CONN_AG_CTX_BIT14_MASK 0x1 10203 #define XSTORM_ISCSI_CONN_AG_CTX_BIT14_SHIFT 6 10204 #define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_MASK 0x1 10205 #define XSTORM_ISCSI_CONN_AG_CTX_TX_TRUNCATE_SHIFT 7 10206 u8 flags2; 10207 #define XSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 10208 #define XSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 0 10209 #define XSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 10210 #define XSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 2 10211 #define XSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 10212 #define XSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 4 10213 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 10214 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 6 10215 u8 flags3; 10216 #define XSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3 10217 #define XSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 0 10218 #define XSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3 10219 #define XSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 2 10220 #define XSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3 10221 #define XSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 4 10222 #define XSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3 10223 #define XSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 6 10224 u8 flags4; 10225 #define XSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3 10226 #define XSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 0 10227 #define XSTORM_ISCSI_CONN_AG_CTX_CF9_MASK 0x3 10228 #define XSTORM_ISCSI_CONN_AG_CTX_CF9_SHIFT 2 10229 #define XSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3 10230 #define XSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 4 10231 #define XSTORM_ISCSI_CONN_AG_CTX_CF11_MASK 0x3 10232 #define XSTORM_ISCSI_CONN_AG_CTX_CF11_SHIFT 6 10233 u8 flags5; 10234 #define XSTORM_ISCSI_CONN_AG_CTX_CF12_MASK 0x3 10235 #define XSTORM_ISCSI_CONN_AG_CTX_CF12_SHIFT 0 10236 #define XSTORM_ISCSI_CONN_AG_CTX_CF13_MASK 0x3 10237 #define XSTORM_ISCSI_CONN_AG_CTX_CF13_SHIFT 2 10238 #define XSTORM_ISCSI_CONN_AG_CTX_CF14_MASK 0x3 10239 #define XSTORM_ISCSI_CONN_AG_CTX_CF14_SHIFT 4 10240 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_MASK 0x3 10241 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_SHIFT 6 10242 u8 flags6; 10243 #define XSTORM_ISCSI_CONN_AG_CTX_CF16_MASK 0x3 10244 #define XSTORM_ISCSI_CONN_AG_CTX_CF16_SHIFT 0 10245 #define XSTORM_ISCSI_CONN_AG_CTX_CF17_MASK 0x3 10246 #define XSTORM_ISCSI_CONN_AG_CTX_CF17_SHIFT 2 10247 #define XSTORM_ISCSI_CONN_AG_CTX_CF18_MASK 0x3 10248 #define XSTORM_ISCSI_CONN_AG_CTX_CF18_SHIFT 4 10249 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_MASK 0x3 10250 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_SHIFT 6 10251 u8 flags7; 10252 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_MASK 0x3 10253 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_SHIFT 0 10254 #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_MASK 0x3 10255 #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_SHIFT 2 10256 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_MASK 0x3 10257 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_SHIFT 4 10258 #define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 10259 #define XSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 6 10260 #define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 10261 #define XSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 7 10262 u8 flags8; 10263 #define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 10264 #define XSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 0 10265 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 10266 #define XSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 1 10267 #define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1 10268 #define XSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 2 10269 #define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1 10270 #define XSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 3 10271 #define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1 10272 #define XSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 4 10273 #define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1 10274 #define XSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 5 10275 #define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1 10276 #define XSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 6 10277 #define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_MASK 0x1 10278 #define XSTORM_ISCSI_CONN_AG_CTX_CF9EN_SHIFT 7 10279 u8 flags9; 10280 #define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1 10281 #define XSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 0 10282 #define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_MASK 0x1 10283 #define XSTORM_ISCSI_CONN_AG_CTX_CF11EN_SHIFT 1 10284 #define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_MASK 0x1 10285 #define XSTORM_ISCSI_CONN_AG_CTX_CF12EN_SHIFT 2 10286 #define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_MASK 0x1 10287 #define XSTORM_ISCSI_CONN_AG_CTX_CF13EN_SHIFT 3 10288 #define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_MASK 0x1 10289 #define XSTORM_ISCSI_CONN_AG_CTX_CF14EN_SHIFT 4 10290 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_MASK 0x1 10291 #define XSTORM_ISCSI_CONN_AG_CTX_UPDATE_STATE_TO_BASE_CF_EN_SHIFT 5 10292 #define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_MASK 0x1 10293 #define XSTORM_ISCSI_CONN_AG_CTX_CF16EN_SHIFT 6 10294 #define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_MASK 0x1 10295 #define XSTORM_ISCSI_CONN_AG_CTX_CF17EN_SHIFT 7 10296 u8 flags10; 10297 #define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_MASK 0x1 10298 #define XSTORM_ISCSI_CONN_AG_CTX_CF18EN_SHIFT 0 10299 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_MASK 0x1 10300 #define XSTORM_ISCSI_CONN_AG_CTX_DQ_FLUSH_EN_SHIFT 1 10301 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_MASK 0x1 10302 #define XSTORM_ISCSI_CONN_AG_CTX_MST_XCM_Q0_FLUSH_CF_EN_SHIFT 2 10303 #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_MASK 0x1 10304 #define XSTORM_ISCSI_CONN_AG_CTX_UST_XCM_Q1_FLUSH_CF_EN_SHIFT 3 10305 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 10306 #define XSTORM_ISCSI_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 10307 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_MASK 0x1 10308 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_EN_SHIFT 5 10309 #define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 10310 #define XSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 6 10311 #define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_MASK 0x1 10312 #define XSTORM_ISCSI_CONN_AG_CTX_MORE_TO_SEND_DEC_RULE_EN_SHIFT 7 10313 u8 flags11; 10314 #define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_MASK 0x1 10315 #define XSTORM_ISCSI_CONN_AG_CTX_TX_BLOCKED_EN_SHIFT 0 10316 #define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 10317 #define XSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 1 10318 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_MASK 0x1 10319 #define XSTORM_ISCSI_CONN_AG_CTX_RESERVED3_SHIFT 2 10320 #define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1 10321 #define XSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 3 10322 #define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1 10323 #define XSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 4 10324 #define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1 10325 #define XSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 5 10326 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 10327 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 10328 #define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_MASK 0x1 10329 #define XSTORM_ISCSI_CONN_AG_CTX_RULE9EN_SHIFT 7 10330 u8 flags12; 10331 #define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_MASK 0x1 10332 #define XSTORM_ISCSI_CONN_AG_CTX_SQ_DEC_RULE_EN_SHIFT 0 10333 #define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_MASK 0x1 10334 #define XSTORM_ISCSI_CONN_AG_CTX_RULE11EN_SHIFT 1 10335 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 10336 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 10337 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 10338 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 10339 #define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_MASK 0x1 10340 #define XSTORM_ISCSI_CONN_AG_CTX_RULE14EN_SHIFT 4 10341 #define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_MASK 0x1 10342 #define XSTORM_ISCSI_CONN_AG_CTX_RULE15EN_SHIFT 5 10343 #define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_MASK 0x1 10344 #define XSTORM_ISCSI_CONN_AG_CTX_RULE16EN_SHIFT 6 10345 #define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_MASK 0x1 10346 #define XSTORM_ISCSI_CONN_AG_CTX_RULE17EN_SHIFT 7 10347 u8 flags13; 10348 #define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_MASK 0x1 10349 #define XSTORM_ISCSI_CONN_AG_CTX_R2TQ_DEC_RULE_EN_SHIFT 0 10350 #define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_MASK 0x1 10351 #define XSTORM_ISCSI_CONN_AG_CTX_HQ_DEC_RULE_EN_SHIFT 1 10352 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 10353 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 10354 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 10355 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 10356 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 10357 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 10358 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 10359 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 10360 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 10361 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 10362 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 10363 #define XSTORM_ISCSI_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 10364 u8 flags14; 10365 #define XSTORM_ISCSI_CONN_AG_CTX_BIT16_MASK 0x1 10366 #define XSTORM_ISCSI_CONN_AG_CTX_BIT16_SHIFT 0 10367 #define XSTORM_ISCSI_CONN_AG_CTX_BIT17_MASK 0x1 10368 #define XSTORM_ISCSI_CONN_AG_CTX_BIT17_SHIFT 1 10369 #define XSTORM_ISCSI_CONN_AG_CTX_BIT18_MASK 0x1 10370 #define XSTORM_ISCSI_CONN_AG_CTX_BIT18_SHIFT 2 10371 #define XSTORM_ISCSI_CONN_AG_CTX_BIT19_MASK 0x1 10372 #define XSTORM_ISCSI_CONN_AG_CTX_BIT19_SHIFT 3 10373 #define XSTORM_ISCSI_CONN_AG_CTX_BIT20_MASK 0x1 10374 #define XSTORM_ISCSI_CONN_AG_CTX_BIT20_SHIFT 4 10375 #define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_MASK 0x1 10376 #define XSTORM_ISCSI_CONN_AG_CTX_DUMMY_READ_DONE_SHIFT 5 10377 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_MASK 0x3 10378 #define XSTORM_ISCSI_CONN_AG_CTX_PROC_ONLY_CLEANUP_SHIFT 6 10379 u8 byte2; 10380 __le16 physical_q0; 10381 __le16 physical_q1; 10382 __le16 dummy_dorq_var; 10383 __le16 sq_cons; 10384 __le16 sq_prod; 10385 __le16 word5; 10386 __le16 slow_io_total_data_tx_update; 10387 u8 byte3; 10388 u8 byte4; 10389 u8 byte5; 10390 u8 byte6; 10391 __le32 reg0; 10392 __le32 reg1; 10393 __le32 reg2; 10394 __le32 more_to_send_seq; 10395 __le32 reg4; 10396 __le32 reg5; 10397 __le32 hq_scan_next_relevant_ack; 10398 __le16 r2tq_prod; 10399 __le16 r2tq_cons; 10400 __le16 hq_prod; 10401 __le16 hq_cons; 10402 __le32 remain_seq; 10403 __le32 bytes_to_next_pdu; 10404 __le32 hq_tcp_seq; 10405 u8 byte7; 10406 u8 byte8; 10407 u8 byte9; 10408 u8 byte10; 10409 u8 byte11; 10410 u8 byte12; 10411 u8 byte13; 10412 u8 byte14; 10413 u8 byte15; 10414 u8 ereserved; 10415 __le16 word11; 10416 __le32 reg10; 10417 __le32 reg11; 10418 __le32 exp_stat_sn; 10419 __le32 ongoing_fast_rxmit_seq; 10420 __le32 reg14; 10421 __le32 reg15; 10422 __le32 reg16; 10423 __le32 reg17; 10424 }; 10425 10426 struct tstorm_iscsi_conn_ag_ctx { 10427 u8 reserved0; 10428 u8 state; 10429 u8 flags0; 10430 #define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 10431 #define TSTORM_ISCSI_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 10432 #define TSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 10433 #define TSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 10434 #define TSTORM_ISCSI_CONN_AG_CTX_BIT2_MASK 0x1 10435 #define TSTORM_ISCSI_CONN_AG_CTX_BIT2_SHIFT 2 10436 #define TSTORM_ISCSI_CONN_AG_CTX_BIT3_MASK 0x1 10437 #define TSTORM_ISCSI_CONN_AG_CTX_BIT3_SHIFT 3 10438 #define TSTORM_ISCSI_CONN_AG_CTX_BIT4_MASK 0x1 10439 #define TSTORM_ISCSI_CONN_AG_CTX_BIT4_SHIFT 4 10440 #define TSTORM_ISCSI_CONN_AG_CTX_BIT5_MASK 0x1 10441 #define TSTORM_ISCSI_CONN_AG_CTX_BIT5_SHIFT 5 10442 #define TSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 10443 #define TSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 6 10444 u8 flags1; 10445 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_MASK 0x3 10446 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_SHIFT 0 10447 #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_MASK 0x3 10448 #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_SHIFT 2 10449 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_MASK 0x3 10450 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_SHIFT 4 10451 #define TSTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3 10452 #define TSTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 6 10453 u8 flags2; 10454 #define TSTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3 10455 #define TSTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 0 10456 #define TSTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3 10457 #define TSTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 2 10458 #define TSTORM_ISCSI_CONN_AG_CTX_CF7_MASK 0x3 10459 #define TSTORM_ISCSI_CONN_AG_CTX_CF7_SHIFT 4 10460 #define TSTORM_ISCSI_CONN_AG_CTX_CF8_MASK 0x3 10461 #define TSTORM_ISCSI_CONN_AG_CTX_CF8_SHIFT 6 10462 u8 flags3; 10463 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 10464 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 10465 #define TSTORM_ISCSI_CONN_AG_CTX_CF10_MASK 0x3 10466 #define TSTORM_ISCSI_CONN_AG_CTX_CF10_SHIFT 2 10467 #define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 10468 #define TSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 4 10469 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_MASK 0x1 10470 #define TSTORM_ISCSI_CONN_AG_CTX_P2T_FLUSH_CF_EN_SHIFT 5 10471 #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_MASK 0x1 10472 #define TSTORM_ISCSI_CONN_AG_CTX_M2T_FLUSH_CF_EN_SHIFT 6 10473 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 10474 #define TSTORM_ISCSI_CONN_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 7 10475 u8 flags4; 10476 #define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1 10477 #define TSTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 0 10478 #define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1 10479 #define TSTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 1 10480 #define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1 10481 #define TSTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 2 10482 #define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_MASK 0x1 10483 #define TSTORM_ISCSI_CONN_AG_CTX_CF7EN_SHIFT 3 10484 #define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_MASK 0x1 10485 #define TSTORM_ISCSI_CONN_AG_CTX_CF8EN_SHIFT 4 10486 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 10487 #define TSTORM_ISCSI_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 5 10488 #define TSTORM_ISCSI_CONN_AG_CTX_CF10EN_MASK 0x1 10489 #define TSTORM_ISCSI_CONN_AG_CTX_CF10EN_SHIFT 6 10490 #define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 10491 #define TSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7 10492 u8 flags5; 10493 #define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 10494 #define TSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0 10495 #define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 10496 #define TSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1 10497 #define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 10498 #define TSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2 10499 #define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 10500 #define TSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3 10501 #define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1 10502 #define TSTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4 10503 #define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1 10504 #define TSTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5 10505 #define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1 10506 #define TSTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6 10507 #define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1 10508 #define TSTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7 10509 __le32 reg0; 10510 __le32 reg1; 10511 __le32 reg2; 10512 __le32 reg3; 10513 __le32 reg4; 10514 __le32 reg5; 10515 __le32 reg6; 10516 __le32 reg7; 10517 __le32 reg8; 10518 u8 cid_offload_cnt; 10519 u8 byte3; 10520 __le16 word0; 10521 }; 10522 10523 struct ustorm_iscsi_conn_ag_ctx { 10524 u8 byte0; 10525 u8 byte1; 10526 u8 flags0; 10527 #define USTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1 10528 #define USTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0 10529 #define USTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 10530 #define USTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 10531 #define USTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 10532 #define USTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2 10533 #define USTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 10534 #define USTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4 10535 #define USTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 10536 #define USTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6 10537 u8 flags1; 10538 #define USTORM_ISCSI_CONN_AG_CTX_CF3_MASK 0x3 10539 #define USTORM_ISCSI_CONN_AG_CTX_CF3_SHIFT 0 10540 #define USTORM_ISCSI_CONN_AG_CTX_CF4_MASK 0x3 10541 #define USTORM_ISCSI_CONN_AG_CTX_CF4_SHIFT 2 10542 #define USTORM_ISCSI_CONN_AG_CTX_CF5_MASK 0x3 10543 #define USTORM_ISCSI_CONN_AG_CTX_CF5_SHIFT 4 10544 #define USTORM_ISCSI_CONN_AG_CTX_CF6_MASK 0x3 10545 #define USTORM_ISCSI_CONN_AG_CTX_CF6_SHIFT 6 10546 u8 flags2; 10547 #define USTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 10548 #define USTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0 10549 #define USTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 10550 #define USTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1 10551 #define USTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 10552 #define USTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2 10553 #define USTORM_ISCSI_CONN_AG_CTX_CF3EN_MASK 0x1 10554 #define USTORM_ISCSI_CONN_AG_CTX_CF3EN_SHIFT 3 10555 #define USTORM_ISCSI_CONN_AG_CTX_CF4EN_MASK 0x1 10556 #define USTORM_ISCSI_CONN_AG_CTX_CF4EN_SHIFT 4 10557 #define USTORM_ISCSI_CONN_AG_CTX_CF5EN_MASK 0x1 10558 #define USTORM_ISCSI_CONN_AG_CTX_CF5EN_SHIFT 5 10559 #define USTORM_ISCSI_CONN_AG_CTX_CF6EN_MASK 0x1 10560 #define USTORM_ISCSI_CONN_AG_CTX_CF6EN_SHIFT 6 10561 #define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 10562 #define USTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 7 10563 u8 flags3; 10564 #define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 10565 #define USTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 0 10566 #define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 10567 #define USTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 1 10568 #define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 10569 #define USTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 2 10570 #define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 10571 #define USTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 3 10572 #define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_MASK 0x1 10573 #define USTORM_ISCSI_CONN_AG_CTX_RULE5EN_SHIFT 4 10574 #define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_MASK 0x1 10575 #define USTORM_ISCSI_CONN_AG_CTX_RULE6EN_SHIFT 5 10576 #define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_MASK 0x1 10577 #define USTORM_ISCSI_CONN_AG_CTX_RULE7EN_SHIFT 6 10578 #define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_MASK 0x1 10579 #define USTORM_ISCSI_CONN_AG_CTX_RULE8EN_SHIFT 7 10580 u8 byte2; 10581 u8 byte3; 10582 __le16 word0; 10583 __le16 word1; 10584 __le32 reg0; 10585 __le32 reg1; 10586 __le32 reg2; 10587 __le32 reg3; 10588 __le16 word2; 10589 __le16 word3; 10590 }; 10591 10592 struct tstorm_iscsi_conn_st_ctx { 10593 __le32 reserved[40]; 10594 }; 10595 10596 struct mstorm_iscsi_conn_ag_ctx { 10597 u8 reserved; 10598 u8 state; 10599 u8 flags0; 10600 #define MSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1 10601 #define MSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0 10602 #define MSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 10603 #define MSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 10604 #define MSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 10605 #define MSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2 10606 #define MSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 10607 #define MSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4 10608 #define MSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 10609 #define MSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6 10610 u8 flags1; 10611 #define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 10612 #define MSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0 10613 #define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 10614 #define MSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1 10615 #define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 10616 #define MSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2 10617 #define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 10618 #define MSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3 10619 #define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 10620 #define MSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4 10621 #define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 10622 #define MSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5 10623 #define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 10624 #define MSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6 10625 #define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 10626 #define MSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7 10627 __le16 word0; 10628 __le16 word1; 10629 __le32 reg0; 10630 __le32 reg1; 10631 }; 10632 10633 struct mstorm_iscsi_tcp_conn_st_ctx { 10634 __le32 reserved_tcp[20]; 10635 __le32 reserved_iscsi[8]; 10636 }; 10637 10638 struct ustorm_iscsi_conn_st_ctx { 10639 __le32 reserved[52]; 10640 }; 10641 10642 struct iscsi_conn_context { 10643 struct ystorm_iscsi_conn_st_ctx ystorm_st_context; 10644 struct regpair ystorm_st_padding[2]; 10645 struct pstorm_iscsi_tcp_conn_st_ctx pstorm_st_context; 10646 struct regpair pstorm_st_padding[2]; 10647 struct pb_context xpb2_context; 10648 struct xstorm_iscsi_tcp_conn_st_ctx xstorm_st_context; 10649 struct regpair xstorm_st_padding[2]; 10650 struct xstorm_iscsi_conn_ag_ctx xstorm_ag_context; 10651 struct tstorm_iscsi_conn_ag_ctx tstorm_ag_context; 10652 struct regpair tstorm_ag_padding[2]; 10653 struct timers_context timer_context; 10654 struct ustorm_iscsi_conn_ag_ctx ustorm_ag_context; 10655 struct pb_context upb_context; 10656 struct tstorm_iscsi_conn_st_ctx tstorm_st_context; 10657 struct regpair tstorm_st_padding[2]; 10658 struct mstorm_iscsi_conn_ag_ctx mstorm_ag_context; 10659 struct mstorm_iscsi_tcp_conn_st_ctx mstorm_st_context; 10660 struct ustorm_iscsi_conn_st_ctx ustorm_st_context; 10661 }; 10662 10663 struct iscsi_init_ramrod_params { 10664 struct iscsi_spe_func_init iscsi_init_spe; 10665 struct tcp_init_params tcp_init; 10666 }; 10667 10668 struct ystorm_iscsi_conn_ag_ctx { 10669 u8 byte0; 10670 u8 byte1; 10671 u8 flags0; 10672 #define YSTORM_ISCSI_CONN_AG_CTX_BIT0_MASK 0x1 10673 #define YSTORM_ISCSI_CONN_AG_CTX_BIT0_SHIFT 0 10674 #define YSTORM_ISCSI_CONN_AG_CTX_BIT1_MASK 0x1 10675 #define YSTORM_ISCSI_CONN_AG_CTX_BIT1_SHIFT 1 10676 #define YSTORM_ISCSI_CONN_AG_CTX_CF0_MASK 0x3 10677 #define YSTORM_ISCSI_CONN_AG_CTX_CF0_SHIFT 2 10678 #define YSTORM_ISCSI_CONN_AG_CTX_CF1_MASK 0x3 10679 #define YSTORM_ISCSI_CONN_AG_CTX_CF1_SHIFT 4 10680 #define YSTORM_ISCSI_CONN_AG_CTX_CF2_MASK 0x3 10681 #define YSTORM_ISCSI_CONN_AG_CTX_CF2_SHIFT 6 10682 u8 flags1; 10683 #define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_MASK 0x1 10684 #define YSTORM_ISCSI_CONN_AG_CTX_CF0EN_SHIFT 0 10685 #define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_MASK 0x1 10686 #define YSTORM_ISCSI_CONN_AG_CTX_CF1EN_SHIFT 1 10687 #define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_MASK 0x1 10688 #define YSTORM_ISCSI_CONN_AG_CTX_CF2EN_SHIFT 2 10689 #define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_MASK 0x1 10690 #define YSTORM_ISCSI_CONN_AG_CTX_RULE0EN_SHIFT 3 10691 #define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_MASK 0x1 10692 #define YSTORM_ISCSI_CONN_AG_CTX_RULE1EN_SHIFT 4 10693 #define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_MASK 0x1 10694 #define YSTORM_ISCSI_CONN_AG_CTX_RULE2EN_SHIFT 5 10695 #define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_MASK 0x1 10696 #define YSTORM_ISCSI_CONN_AG_CTX_RULE3EN_SHIFT 6 10697 #define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_MASK 0x1 10698 #define YSTORM_ISCSI_CONN_AG_CTX_RULE4EN_SHIFT 7 10699 u8 byte2; 10700 u8 byte3; 10701 __le16 word0; 10702 __le32 reg0; 10703 __le32 reg1; 10704 __le16 word1; 10705 __le16 word2; 10706 __le16 word3; 10707 __le16 word4; 10708 __le32 reg2; 10709 __le32 reg3; 10710 }; 10711 10712 #define MFW_TRACE_SIGNATURE 0x25071946 10713 10714 /* The trace in the buffer */ 10715 #define MFW_TRACE_EVENTID_MASK 0x00ffff 10716 #define MFW_TRACE_PRM_SIZE_MASK 0x0f0000 10717 #define MFW_TRACE_PRM_SIZE_SHIFT 16 10718 #define MFW_TRACE_ENTRY_SIZE 3 10719 10720 struct mcp_trace { 10721 u32 signature; /* Help to identify that the trace is valid */ 10722 u32 size; /* the size of the trace buffer in bytes */ 10723 u32 curr_level; /* 2 - all will be written to the buffer 10724 * 1 - debug trace will not be written 10725 * 0 - just errors will be written to the buffer 10726 */ 10727 u32 modules_mask[2]; /* a bit per module, 1 means write it, 0 means 10728 * mask it. 10729 */ 10730 10731 /* Warning: the following pointers are assumed to be 32bits as they are 10732 * used only in the MFW. 10733 */ 10734 u32 trace_prod; /* The next trace will be written to this offset */ 10735 u32 trace_oldest; /* The oldest valid trace starts at this offset 10736 * (usually very close after the current producer). 10737 */ 10738 }; 10739 10740 #define VF_MAX_STATIC 192 10741 10742 #define MCP_GLOB_PATH_MAX 2 10743 #define MCP_PORT_MAX 2 10744 #define MCP_GLOB_PORT_MAX 4 10745 #define MCP_GLOB_FUNC_MAX 16 10746 10747 typedef u32 offsize_t; /* In DWORDS !!! */ 10748 /* Offset from the beginning of the MCP scratchpad */ 10749 #define OFFSIZE_OFFSET_SHIFT 0 10750 #define OFFSIZE_OFFSET_MASK 0x0000ffff 10751 /* Size of specific element (not the whole array if any) */ 10752 #define OFFSIZE_SIZE_SHIFT 16 10753 #define OFFSIZE_SIZE_MASK 0xffff0000 10754 10755 #define SECTION_OFFSET(_offsize) ((((_offsize & \ 10756 OFFSIZE_OFFSET_MASK) >> \ 10757 OFFSIZE_OFFSET_SHIFT) << 2)) 10758 10759 #define QED_SECTION_SIZE(_offsize) (((_offsize & \ 10760 OFFSIZE_SIZE_MASK) >> \ 10761 OFFSIZE_SIZE_SHIFT) << 2) 10762 10763 #define SECTION_ADDR(_offsize, idx) (MCP_REG_SCRATCH + \ 10764 SECTION_OFFSET(_offsize) + \ 10765 (QED_SECTION_SIZE(_offsize) * idx)) 10766 10767 #define SECTION_OFFSIZE_ADDR(_pub_base, _section) \ 10768 (_pub_base + offsetof(struct mcp_public_data, sections[_section])) 10769 10770 /* PHY configuration */ 10771 struct eth_phy_cfg { 10772 u32 speed; 10773 #define ETH_SPEED_AUTONEG 0 10774 #define ETH_SPEED_SMARTLINQ 0x8 10775 10776 u32 pause; 10777 #define ETH_PAUSE_NONE 0x0 10778 #define ETH_PAUSE_AUTONEG 0x1 10779 #define ETH_PAUSE_RX 0x2 10780 #define ETH_PAUSE_TX 0x4 10781 10782 u32 adv_speed; 10783 u32 loopback_mode; 10784 #define ETH_LOOPBACK_NONE (0) 10785 #define ETH_LOOPBACK_INT_PHY (1) 10786 #define ETH_LOOPBACK_EXT_PHY (2) 10787 #define ETH_LOOPBACK_EXT (3) 10788 #define ETH_LOOPBACK_MAC (4) 10789 10790 u32 feature_config_flags; 10791 #define ETH_EEE_MODE_ADV_LPI (1 << 0) 10792 }; 10793 10794 struct port_mf_cfg { 10795 u32 dynamic_cfg; 10796 #define PORT_MF_CFG_OV_TAG_MASK 0x0000ffff 10797 #define PORT_MF_CFG_OV_TAG_SHIFT 0 10798 #define PORT_MF_CFG_OV_TAG_DEFAULT PORT_MF_CFG_OV_TAG_MASK 10799 10800 u32 reserved[1]; 10801 }; 10802 10803 struct eth_stats { 10804 u64 r64; 10805 u64 r127; 10806 u64 r255; 10807 u64 r511; 10808 u64 r1023; 10809 u64 r1518; 10810 10811 union { 10812 struct { 10813 u64 r1522; 10814 u64 r2047; 10815 u64 r4095; 10816 u64 r9216; 10817 u64 r16383; 10818 } bb0; 10819 struct { 10820 u64 unused1; 10821 u64 r1519_to_max; 10822 u64 unused2; 10823 u64 unused3; 10824 u64 unused4; 10825 } ah0; 10826 } u0; 10827 10828 u64 rfcs; 10829 u64 rxcf; 10830 u64 rxpf; 10831 u64 rxpp; 10832 u64 raln; 10833 u64 rfcr; 10834 u64 rovr; 10835 u64 rjbr; 10836 u64 rund; 10837 u64 rfrg; 10838 u64 t64; 10839 u64 t127; 10840 u64 t255; 10841 u64 t511; 10842 u64 t1023; 10843 u64 t1518; 10844 10845 union { 10846 struct { 10847 u64 t2047; 10848 u64 t4095; 10849 u64 t9216; 10850 u64 t16383; 10851 } bb1; 10852 struct { 10853 u64 t1519_to_max; 10854 u64 unused6; 10855 u64 unused7; 10856 u64 unused8; 10857 } ah1; 10858 } u1; 10859 10860 u64 txpf; 10861 u64 txpp; 10862 10863 union { 10864 struct { 10865 u64 tlpiec; 10866 u64 tncl; 10867 } bb2; 10868 struct { 10869 u64 unused9; 10870 u64 unused10; 10871 } ah2; 10872 } u2; 10873 10874 u64 rbyte; 10875 u64 rxuca; 10876 u64 rxmca; 10877 u64 rxbca; 10878 u64 rxpok; 10879 u64 tbyte; 10880 u64 txuca; 10881 u64 txmca; 10882 u64 txbca; 10883 u64 txcf; 10884 }; 10885 10886 struct brb_stats { 10887 u64 brb_truncate[8]; 10888 u64 brb_discard[8]; 10889 }; 10890 10891 struct port_stats { 10892 struct brb_stats brb; 10893 struct eth_stats eth; 10894 }; 10895 10896 struct couple_mode_teaming { 10897 u8 port_cmt[MCP_GLOB_PORT_MAX]; 10898 #define PORT_CMT_IN_TEAM (1 << 0) 10899 10900 #define PORT_CMT_PORT_ROLE (1 << 1) 10901 #define PORT_CMT_PORT_INACTIVE (0 << 1) 10902 #define PORT_CMT_PORT_ACTIVE (1 << 1) 10903 10904 #define PORT_CMT_TEAM_MASK (1 << 2) 10905 #define PORT_CMT_TEAM0 (0 << 2) 10906 #define PORT_CMT_TEAM1 (1 << 2) 10907 }; 10908 10909 #define LLDP_CHASSIS_ID_STAT_LEN 4 10910 #define LLDP_PORT_ID_STAT_LEN 4 10911 #define DCBX_MAX_APP_PROTOCOL 32 10912 #define MAX_SYSTEM_LLDP_TLV_DATA 32 10913 10914 enum _lldp_agent { 10915 LLDP_NEAREST_BRIDGE = 0, 10916 LLDP_NEAREST_NON_TPMR_BRIDGE, 10917 LLDP_NEAREST_CUSTOMER_BRIDGE, 10918 LLDP_MAX_LLDP_AGENTS 10919 }; 10920 10921 struct lldp_config_params_s { 10922 u32 config; 10923 #define LLDP_CONFIG_TX_INTERVAL_MASK 0x000000ff 10924 #define LLDP_CONFIG_TX_INTERVAL_SHIFT 0 10925 #define LLDP_CONFIG_HOLD_MASK 0x00000f00 10926 #define LLDP_CONFIG_HOLD_SHIFT 8 10927 #define LLDP_CONFIG_MAX_CREDIT_MASK 0x0000f000 10928 #define LLDP_CONFIG_MAX_CREDIT_SHIFT 12 10929 #define LLDP_CONFIG_ENABLE_RX_MASK 0x40000000 10930 #define LLDP_CONFIG_ENABLE_RX_SHIFT 30 10931 #define LLDP_CONFIG_ENABLE_TX_MASK 0x80000000 10932 #define LLDP_CONFIG_ENABLE_TX_SHIFT 31 10933 u32 local_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; 10934 u32 local_port_id[LLDP_PORT_ID_STAT_LEN]; 10935 }; 10936 10937 struct lldp_status_params_s { 10938 u32 prefix_seq_num; 10939 u32 status; 10940 u32 peer_chassis_id[LLDP_CHASSIS_ID_STAT_LEN]; 10941 u32 peer_port_id[LLDP_PORT_ID_STAT_LEN]; 10942 u32 suffix_seq_num; 10943 }; 10944 10945 struct dcbx_ets_feature { 10946 u32 flags; 10947 #define DCBX_ETS_ENABLED_MASK 0x00000001 10948 #define DCBX_ETS_ENABLED_SHIFT 0 10949 #define DCBX_ETS_WILLING_MASK 0x00000002 10950 #define DCBX_ETS_WILLING_SHIFT 1 10951 #define DCBX_ETS_ERROR_MASK 0x00000004 10952 #define DCBX_ETS_ERROR_SHIFT 2 10953 #define DCBX_ETS_CBS_MASK 0x00000008 10954 #define DCBX_ETS_CBS_SHIFT 3 10955 #define DCBX_ETS_MAX_TCS_MASK 0x000000f0 10956 #define DCBX_ETS_MAX_TCS_SHIFT 4 10957 #define DCBX_OOO_TC_MASK 0x00000f00 10958 #define DCBX_OOO_TC_SHIFT 8 10959 u32 pri_tc_tbl[1]; 10960 #define DCBX_TCP_OOO_TC (4) 10961 10962 #define NIG_ETS_ISCSI_OOO_CLIENT_OFFSET (DCBX_TCP_OOO_TC + 1) 10963 #define DCBX_CEE_STRICT_PRIORITY 0xf 10964 u32 tc_bw_tbl[2]; 10965 u32 tc_tsa_tbl[2]; 10966 #define DCBX_ETS_TSA_STRICT 0 10967 #define DCBX_ETS_TSA_CBS 1 10968 #define DCBX_ETS_TSA_ETS 2 10969 }; 10970 10971 #define DCBX_TCP_OOO_TC (4) 10972 #define DCBX_TCP_OOO_K2_4PORT_TC (3) 10973 10974 struct dcbx_app_priority_entry { 10975 u32 entry; 10976 #define DCBX_APP_PRI_MAP_MASK 0x000000ff 10977 #define DCBX_APP_PRI_MAP_SHIFT 0 10978 #define DCBX_APP_PRI_0 0x01 10979 #define DCBX_APP_PRI_1 0x02 10980 #define DCBX_APP_PRI_2 0x04 10981 #define DCBX_APP_PRI_3 0x08 10982 #define DCBX_APP_PRI_4 0x10 10983 #define DCBX_APP_PRI_5 0x20 10984 #define DCBX_APP_PRI_6 0x40 10985 #define DCBX_APP_PRI_7 0x80 10986 #define DCBX_APP_SF_MASK 0x00000300 10987 #define DCBX_APP_SF_SHIFT 8 10988 #define DCBX_APP_SF_ETHTYPE 0 10989 #define DCBX_APP_SF_PORT 1 10990 #define DCBX_APP_SF_IEEE_MASK 0x0000f000 10991 #define DCBX_APP_SF_IEEE_SHIFT 12 10992 #define DCBX_APP_SF_IEEE_RESERVED 0 10993 #define DCBX_APP_SF_IEEE_ETHTYPE 1 10994 #define DCBX_APP_SF_IEEE_TCP_PORT 2 10995 #define DCBX_APP_SF_IEEE_UDP_PORT 3 10996 #define DCBX_APP_SF_IEEE_TCP_UDP_PORT 4 10997 10998 #define DCBX_APP_PROTOCOL_ID_MASK 0xffff0000 10999 #define DCBX_APP_PROTOCOL_ID_SHIFT 16 11000 }; 11001 11002 struct dcbx_app_priority_feature { 11003 u32 flags; 11004 #define DCBX_APP_ENABLED_MASK 0x00000001 11005 #define DCBX_APP_ENABLED_SHIFT 0 11006 #define DCBX_APP_WILLING_MASK 0x00000002 11007 #define DCBX_APP_WILLING_SHIFT 1 11008 #define DCBX_APP_ERROR_MASK 0x00000004 11009 #define DCBX_APP_ERROR_SHIFT 2 11010 #define DCBX_APP_MAX_TCS_MASK 0x0000f000 11011 #define DCBX_APP_MAX_TCS_SHIFT 12 11012 #define DCBX_APP_NUM_ENTRIES_MASK 0x00ff0000 11013 #define DCBX_APP_NUM_ENTRIES_SHIFT 16 11014 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 11015 }; 11016 11017 struct dcbx_features { 11018 struct dcbx_ets_feature ets; 11019 u32 pfc; 11020 #define DCBX_PFC_PRI_EN_BITMAP_MASK 0x000000ff 11021 #define DCBX_PFC_PRI_EN_BITMAP_SHIFT 0 11022 #define DCBX_PFC_PRI_EN_BITMAP_PRI_0 0x01 11023 #define DCBX_PFC_PRI_EN_BITMAP_PRI_1 0x02 11024 #define DCBX_PFC_PRI_EN_BITMAP_PRI_2 0x04 11025 #define DCBX_PFC_PRI_EN_BITMAP_PRI_3 0x08 11026 #define DCBX_PFC_PRI_EN_BITMAP_PRI_4 0x10 11027 #define DCBX_PFC_PRI_EN_BITMAP_PRI_5 0x20 11028 #define DCBX_PFC_PRI_EN_BITMAP_PRI_6 0x40 11029 #define DCBX_PFC_PRI_EN_BITMAP_PRI_7 0x80 11030 11031 #define DCBX_PFC_FLAGS_MASK 0x0000ff00 11032 #define DCBX_PFC_FLAGS_SHIFT 8 11033 #define DCBX_PFC_CAPS_MASK 0x00000f00 11034 #define DCBX_PFC_CAPS_SHIFT 8 11035 #define DCBX_PFC_MBC_MASK 0x00004000 11036 #define DCBX_PFC_MBC_SHIFT 14 11037 #define DCBX_PFC_WILLING_MASK 0x00008000 11038 #define DCBX_PFC_WILLING_SHIFT 15 11039 #define DCBX_PFC_ENABLED_MASK 0x00010000 11040 #define DCBX_PFC_ENABLED_SHIFT 16 11041 #define DCBX_PFC_ERROR_MASK 0x00020000 11042 #define DCBX_PFC_ERROR_SHIFT 17 11043 11044 struct dcbx_app_priority_feature app; 11045 }; 11046 11047 struct dcbx_local_params { 11048 u32 config; 11049 #define DCBX_CONFIG_VERSION_MASK 0x00000007 11050 #define DCBX_CONFIG_VERSION_SHIFT 0 11051 #define DCBX_CONFIG_VERSION_DISABLED 0 11052 #define DCBX_CONFIG_VERSION_IEEE 1 11053 #define DCBX_CONFIG_VERSION_CEE 2 11054 #define DCBX_CONFIG_VERSION_STATIC 4 11055 11056 u32 flags; 11057 struct dcbx_features features; 11058 }; 11059 11060 struct dcbx_mib { 11061 u32 prefix_seq_num; 11062 u32 flags; 11063 struct dcbx_features features; 11064 u32 suffix_seq_num; 11065 }; 11066 11067 struct lldp_system_tlvs_buffer_s { 11068 u16 valid; 11069 u16 length; 11070 u32 data[MAX_SYSTEM_LLDP_TLV_DATA]; 11071 }; 11072 11073 struct dcb_dscp_map { 11074 u32 flags; 11075 #define DCB_DSCP_ENABLE_MASK 0x1 11076 #define DCB_DSCP_ENABLE_SHIFT 0 11077 #define DCB_DSCP_ENABLE 1 11078 u32 dscp_pri_map[8]; 11079 }; 11080 11081 struct public_global { 11082 u32 max_path; 11083 u32 max_ports; 11084 #define MODE_1P 1 11085 #define MODE_2P 2 11086 #define MODE_3P 3 11087 #define MODE_4P 4 11088 u32 debug_mb_offset; 11089 u32 phymod_dbg_mb_offset; 11090 struct couple_mode_teaming cmt; 11091 s32 internal_temperature; 11092 u32 mfw_ver; 11093 u32 running_bundle_id; 11094 s32 external_temperature; 11095 u32 mdump_reason; 11096 }; 11097 11098 struct fw_flr_mb { 11099 u32 aggint; 11100 u32 opgen_addr; 11101 u32 accum_ack; 11102 }; 11103 11104 struct public_path { 11105 struct fw_flr_mb flr_mb; 11106 u32 mcp_vf_disabled[VF_MAX_STATIC / 32]; 11107 11108 u32 process_kill; 11109 #define PROCESS_KILL_COUNTER_MASK 0x0000ffff 11110 #define PROCESS_KILL_COUNTER_SHIFT 0 11111 #define PROCESS_KILL_GLOB_AEU_BIT_MASK 0xffff0000 11112 #define PROCESS_KILL_GLOB_AEU_BIT_SHIFT 16 11113 #define GLOBAL_AEU_BIT(aeu_reg_id, aeu_bit) (aeu_reg_id * 32 + aeu_bit) 11114 }; 11115 11116 struct public_port { 11117 u32 validity_map; 11118 11119 u32 link_status; 11120 #define LINK_STATUS_LINK_UP 0x00000001 11121 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001e 11122 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (1 << 1) 11123 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (2 << 1) 11124 #define LINK_STATUS_SPEED_AND_DUPLEX_10G (3 << 1) 11125 #define LINK_STATUS_SPEED_AND_DUPLEX_20G (4 << 1) 11126 #define LINK_STATUS_SPEED_AND_DUPLEX_40G (5 << 1) 11127 #define LINK_STATUS_SPEED_AND_DUPLEX_50G (6 << 1) 11128 #define LINK_STATUS_SPEED_AND_DUPLEX_100G (7 << 1) 11129 #define LINK_STATUS_SPEED_AND_DUPLEX_25G (8 << 1) 11130 11131 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 11132 11133 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 11134 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 11135 11136 #define LINK_STATUS_PFC_ENABLED 0x00000100 11137 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 11138 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 11139 #define LINK_STATUS_LINK_PARTNER_10G_CAPABLE 0x00000800 11140 #define LINK_STATUS_LINK_PARTNER_20G_CAPABLE 0x00001000 11141 #define LINK_STATUS_LINK_PARTNER_40G_CAPABLE 0x00002000 11142 #define LINK_STATUS_LINK_PARTNER_50G_CAPABLE 0x00004000 11143 #define LINK_STATUS_LINK_PARTNER_100G_CAPABLE 0x00008000 11144 #define LINK_STATUS_LINK_PARTNER_25G_CAPABLE 0x00010000 11145 11146 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 11147 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0 << 18) 11148 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1 << 18) 11149 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2 << 18) 11150 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3 << 18) 11151 11152 #define LINK_STATUS_SFP_TX_FAULT 0x00100000 11153 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00200000 11154 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00400000 11155 #define LINK_STATUS_RX_SIGNAL_PRESENT 0x00800000 11156 #define LINK_STATUS_MAC_LOCAL_FAULT 0x01000000 11157 #define LINK_STATUS_MAC_REMOTE_FAULT 0x02000000 11158 #define LINK_STATUS_UNSUPPORTED_SPD_REQ 0x04000000 11159 11160 u32 link_status1; 11161 u32 ext_phy_fw_version; 11162 u32 drv_phy_cfg_addr; 11163 11164 u32 port_stx; 11165 11166 u32 stat_nig_timer; 11167 11168 struct port_mf_cfg port_mf_config; 11169 struct port_stats stats; 11170 11171 u32 media_type; 11172 #define MEDIA_UNSPECIFIED 0x0 11173 #define MEDIA_SFPP_10G_FIBER 0x1 11174 #define MEDIA_XFP_FIBER 0x2 11175 #define MEDIA_DA_TWINAX 0x3 11176 #define MEDIA_BASE_T 0x4 11177 #define MEDIA_SFP_1G_FIBER 0x5 11178 #define MEDIA_MODULE_FIBER 0x6 11179 #define MEDIA_KR 0xf0 11180 #define MEDIA_NOT_PRESENT 0xff 11181 11182 u32 lfa_status; 11183 u32 link_change_count; 11184 11185 struct lldp_config_params_s lldp_config_params[LLDP_MAX_LLDP_AGENTS]; 11186 struct lldp_status_params_s lldp_status_params[LLDP_MAX_LLDP_AGENTS]; 11187 struct lldp_system_tlvs_buffer_s system_lldp_tlvs_buf; 11188 11189 /* DCBX related MIB */ 11190 struct dcbx_local_params local_admin_dcbx_mib; 11191 struct dcbx_mib remote_dcbx_mib; 11192 struct dcbx_mib operational_dcbx_mib; 11193 11194 u32 reserved[2]; 11195 u32 transceiver_data; 11196 #define ETH_TRANSCEIVER_STATE_MASK 0x000000FF 11197 #define ETH_TRANSCEIVER_STATE_SHIFT 0x00000000 11198 #define ETH_TRANSCEIVER_STATE_UNPLUGGED 0x00000000 11199 #define ETH_TRANSCEIVER_STATE_PRESENT 0x00000001 11200 #define ETH_TRANSCEIVER_STATE_VALID 0x00000003 11201 #define ETH_TRANSCEIVER_STATE_UPDATING 0x00000008 11202 11203 u32 wol_info; 11204 u32 wol_pkt_len; 11205 u32 wol_pkt_details; 11206 struct dcb_dscp_map dcb_dscp_map; 11207 }; 11208 11209 struct public_func { 11210 u32 reserved0[2]; 11211 11212 u32 mtu_size; 11213 11214 u32 reserved[7]; 11215 11216 u32 config; 11217 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 11218 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING 0x00000002 11219 #define FUNC_MF_CFG_PAUSE_ON_HOST_RING_SHIFT 0x00000001 11220 11221 #define FUNC_MF_CFG_PROTOCOL_MASK 0x000000f0 11222 #define FUNC_MF_CFG_PROTOCOL_SHIFT 4 11223 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000000 11224 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000010 11225 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000020 11226 #define FUNC_MF_CFG_PROTOCOL_ROCE 0x00000030 11227 #define FUNC_MF_CFG_PROTOCOL_MAX 0x00000030 11228 11229 #define FUNC_MF_CFG_MIN_BW_MASK 0x0000ff00 11230 #define FUNC_MF_CFG_MIN_BW_SHIFT 8 11231 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 11232 #define FUNC_MF_CFG_MAX_BW_MASK 0x00ff0000 11233 #define FUNC_MF_CFG_MAX_BW_SHIFT 16 11234 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x00640000 11235 11236 u32 status; 11237 #define FUNC_STATUS_VLINK_DOWN 0x00000001 11238 11239 u32 mac_upper; 11240 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 11241 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 11242 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 11243 u32 mac_lower; 11244 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 11245 11246 u32 fcoe_wwn_port_name_upper; 11247 u32 fcoe_wwn_port_name_lower; 11248 11249 u32 fcoe_wwn_node_name_upper; 11250 u32 fcoe_wwn_node_name_lower; 11251 11252 u32 ovlan_stag; 11253 #define FUNC_MF_CFG_OV_STAG_MASK 0x0000ffff 11254 #define FUNC_MF_CFG_OV_STAG_SHIFT 0 11255 #define FUNC_MF_CFG_OV_STAG_DEFAULT FUNC_MF_CFG_OV_STAG_MASK 11256 11257 u32 pf_allocation; 11258 11259 u32 preserve_data; 11260 11261 u32 driver_last_activity_ts; 11262 11263 u32 drv_ack_vf_disabled[VF_MAX_STATIC / 32]; 11264 11265 u32 drv_id; 11266 #define DRV_ID_PDA_COMP_VER_MASK 0x0000ffff 11267 #define DRV_ID_PDA_COMP_VER_SHIFT 0 11268 11269 #define LOAD_REQ_HSI_VERSION 2 11270 #define DRV_ID_MCP_HSI_VER_MASK 0x00ff0000 11271 #define DRV_ID_MCP_HSI_VER_SHIFT 16 11272 #define DRV_ID_MCP_HSI_VER_CURRENT (LOAD_REQ_HSI_VERSION << \ 11273 DRV_ID_MCP_HSI_VER_SHIFT) 11274 11275 #define DRV_ID_DRV_TYPE_MASK 0x7f000000 11276 #define DRV_ID_DRV_TYPE_SHIFT 24 11277 #define DRV_ID_DRV_TYPE_UNKNOWN (0 << DRV_ID_DRV_TYPE_SHIFT) 11278 #define DRV_ID_DRV_TYPE_LINUX (1 << DRV_ID_DRV_TYPE_SHIFT) 11279 11280 #define DRV_ID_DRV_INIT_HW_MASK 0x80000000 11281 #define DRV_ID_DRV_INIT_HW_SHIFT 31 11282 #define DRV_ID_DRV_INIT_HW_FLAG (1 << DRV_ID_DRV_INIT_HW_SHIFT) 11283 }; 11284 11285 struct mcp_mac { 11286 u32 mac_upper; 11287 u32 mac_lower; 11288 }; 11289 11290 struct mcp_val64 { 11291 u32 lo; 11292 u32 hi; 11293 }; 11294 11295 struct mcp_file_att { 11296 u32 nvm_start_addr; 11297 u32 len; 11298 }; 11299 11300 struct bist_nvm_image_att { 11301 u32 return_code; 11302 u32 image_type; 11303 u32 nvm_start_addr; 11304 u32 len; 11305 }; 11306 11307 #define MCP_DRV_VER_STR_SIZE 16 11308 #define MCP_DRV_VER_STR_SIZE_DWORD (MCP_DRV_VER_STR_SIZE / sizeof(u32)) 11309 #define MCP_DRV_NVM_BUF_LEN 32 11310 struct drv_version_stc { 11311 u32 version; 11312 u8 name[MCP_DRV_VER_STR_SIZE - 4]; 11313 }; 11314 11315 struct lan_stats_stc { 11316 u64 ucast_rx_pkts; 11317 u64 ucast_tx_pkts; 11318 u32 fcs_err; 11319 u32 rserved; 11320 }; 11321 11322 struct fcoe_stats_stc { 11323 u64 rx_pkts; 11324 u64 tx_pkts; 11325 u32 fcs_err; 11326 u32 login_failure; 11327 }; 11328 11329 struct ocbb_data_stc { 11330 u32 ocbb_host_addr; 11331 u32 ocsd_host_addr; 11332 u32 ocsd_req_update_interval; 11333 }; 11334 11335 #define MAX_NUM_OF_SENSORS 7 11336 struct temperature_status_stc { 11337 u32 num_of_sensors; 11338 u32 sensor[MAX_NUM_OF_SENSORS]; 11339 }; 11340 11341 /* crash dump configuration header */ 11342 struct mdump_config_stc { 11343 u32 version; 11344 u32 config; 11345 u32 epoc; 11346 u32 num_of_logs; 11347 u32 valid_logs; 11348 }; 11349 11350 enum resource_id_enum { 11351 RESOURCE_NUM_SB_E = 0, 11352 RESOURCE_NUM_L2_QUEUE_E = 1, 11353 RESOURCE_NUM_VPORT_E = 2, 11354 RESOURCE_NUM_VMQ_E = 3, 11355 RESOURCE_FACTOR_NUM_RSS_PF_E = 4, 11356 RESOURCE_FACTOR_RSS_PER_VF_E = 5, 11357 RESOURCE_NUM_RL_E = 6, 11358 RESOURCE_NUM_PQ_E = 7, 11359 RESOURCE_NUM_VF_E = 8, 11360 RESOURCE_VFC_FILTER_E = 9, 11361 RESOURCE_ILT_E = 10, 11362 RESOURCE_CQS_E = 11, 11363 RESOURCE_GFT_PROFILES_E = 12, 11364 RESOURCE_NUM_TC_E = 13, 11365 RESOURCE_NUM_RSS_ENGINES_E = 14, 11366 RESOURCE_LL2_QUEUE_E = 15, 11367 RESOURCE_RDMA_STATS_QUEUE_E = 16, 11368 RESOURCE_BDQ_E = 17, 11369 RESOURCE_MAX_NUM, 11370 RESOURCE_NUM_INVALID = 0xFFFFFFFF 11371 }; 11372 11373 /* Resource ID is to be filled by the driver in the MB request 11374 * Size, offset & flags to be filled by the MFW in the MB response 11375 */ 11376 struct resource_info { 11377 enum resource_id_enum res_id; 11378 u32 size; /* number of allocated resources */ 11379 u32 offset; /* Offset of the 1st resource */ 11380 u32 vf_size; 11381 u32 vf_offset; 11382 u32 flags; 11383 #define RESOURCE_ELEMENT_STRICT (1 << 0) 11384 }; 11385 11386 #define DRV_ROLE_NONE 0 11387 #define DRV_ROLE_PREBOOT 1 11388 #define DRV_ROLE_OS 2 11389 #define DRV_ROLE_KDUMP 3 11390 11391 struct load_req_stc { 11392 u32 drv_ver_0; 11393 u32 drv_ver_1; 11394 u32 fw_ver; 11395 u32 misc0; 11396 #define LOAD_REQ_ROLE_MASK 0x000000FF 11397 #define LOAD_REQ_ROLE_SHIFT 0 11398 #define LOAD_REQ_LOCK_TO_MASK 0x0000FF00 11399 #define LOAD_REQ_LOCK_TO_SHIFT 8 11400 #define LOAD_REQ_LOCK_TO_DEFAULT 0 11401 #define LOAD_REQ_LOCK_TO_NONE 255 11402 #define LOAD_REQ_FORCE_MASK 0x000F0000 11403 #define LOAD_REQ_FORCE_SHIFT 16 11404 #define LOAD_REQ_FORCE_NONE 0 11405 #define LOAD_REQ_FORCE_PF 1 11406 #define LOAD_REQ_FORCE_ALL 2 11407 #define LOAD_REQ_FLAGS0_MASK 0x00F00000 11408 #define LOAD_REQ_FLAGS0_SHIFT 20 11409 #define LOAD_REQ_FLAGS0_AVOID_RESET (0x1 << 0) 11410 }; 11411 11412 struct load_rsp_stc { 11413 u32 drv_ver_0; 11414 u32 drv_ver_1; 11415 u32 fw_ver; 11416 u32 misc0; 11417 #define LOAD_RSP_ROLE_MASK 0x000000FF 11418 #define LOAD_RSP_ROLE_SHIFT 0 11419 #define LOAD_RSP_HSI_MASK 0x0000FF00 11420 #define LOAD_RSP_HSI_SHIFT 8 11421 #define LOAD_RSP_FLAGS0_MASK 0x000F0000 11422 #define LOAD_RSP_FLAGS0_SHIFT 16 11423 #define LOAD_RSP_FLAGS0_DRV_EXISTS (0x1 << 0) 11424 }; 11425 11426 union drv_union_data { 11427 u32 ver_str[MCP_DRV_VER_STR_SIZE_DWORD]; 11428 struct mcp_mac wol_mac; 11429 11430 struct eth_phy_cfg drv_phy_cfg; 11431 11432 struct mcp_val64 val64; 11433 11434 u8 raw_data[MCP_DRV_NVM_BUF_LEN]; 11435 11436 struct mcp_file_att file_att; 11437 11438 u32 ack_vf_disabled[VF_MAX_STATIC / 32]; 11439 11440 struct drv_version_stc drv_version; 11441 11442 struct lan_stats_stc lan_stats; 11443 struct fcoe_stats_stc fcoe_stats; 11444 struct ocbb_data_stc ocbb_info; 11445 struct temperature_status_stc temp_info; 11446 struct resource_info resource; 11447 struct bist_nvm_image_att nvm_image_att; 11448 struct mdump_config_stc mdump_config; 11449 }; 11450 11451 struct public_drv_mb { 11452 u32 drv_mb_header; 11453 #define DRV_MSG_CODE_MASK 0xffff0000 11454 #define DRV_MSG_CODE_LOAD_REQ 0x10000000 11455 #define DRV_MSG_CODE_LOAD_DONE 0x11000000 11456 #define DRV_MSG_CODE_INIT_HW 0x12000000 11457 #define DRV_MSG_CODE_CANCEL_LOAD_REQ 0x13000000 11458 #define DRV_MSG_CODE_UNLOAD_REQ 0x20000000 11459 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 11460 #define DRV_MSG_CODE_INIT_PHY 0x22000000 11461 #define DRV_MSG_CODE_LINK_RESET 0x23000000 11462 #define DRV_MSG_CODE_SET_DCBX 0x25000000 11463 #define DRV_MSG_CODE_OV_UPDATE_CURR_CFG 0x26000000 11464 #define DRV_MSG_CODE_OV_UPDATE_BUS_NUM 0x27000000 11465 #define DRV_MSG_CODE_OV_UPDATE_BOOT_PROGRESS 0x28000000 11466 #define DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER 0x29000000 11467 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE 0x31000000 11468 #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000 11469 #define DRV_MSG_CODE_OV_UPDATE_MTU 0x33000000 11470 #define DRV_MSG_GET_RESOURCE_ALLOC_MSG 0x34000000 11471 #define DRV_MSG_SET_RESOURCE_VALUE_MSG 0x35000000 11472 #define DRV_MSG_CODE_OV_UPDATE_WOL 0x38000000 11473 #define DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE 0x39000000 11474 11475 #define DRV_MSG_CODE_BW_UPDATE_ACK 0x32000000 11476 #define DRV_MSG_CODE_NIG_DRAIN 0x30000000 11477 #define DRV_MSG_CODE_S_TAG_UPDATE_ACK 0x3b000000 11478 #define DRV_MSG_CODE_INITIATE_PF_FLR 0x02010000 11479 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 11480 #define DRV_MSG_CODE_CFG_VF_MSIX 0xc0010000 11481 #define DRV_MSG_CODE_CFG_PF_VFS_MSIX 0xc0020000 11482 #define DRV_MSG_CODE_NVM_GET_FILE_ATT 0x00030000 11483 #define DRV_MSG_CODE_NVM_READ_NVRAM 0x00050000 11484 #define DRV_MSG_CODE_MCP_RESET 0x00090000 11485 #define DRV_MSG_CODE_SET_VERSION 0x000f0000 11486 #define DRV_MSG_CODE_MCP_HALT 0x00100000 11487 #define DRV_MSG_CODE_SET_VMAC 0x00110000 11488 #define DRV_MSG_CODE_GET_VMAC 0x00120000 11489 #define DRV_MSG_CODE_VMAC_TYPE_SHIFT 4 11490 #define DRV_MSG_CODE_VMAC_TYPE_MASK 0x30 11491 #define DRV_MSG_CODE_VMAC_TYPE_MAC 1 11492 #define DRV_MSG_CODE_VMAC_TYPE_WWNN 2 11493 #define DRV_MSG_CODE_VMAC_TYPE_WWPN 3 11494 11495 #define DRV_MSG_CODE_GET_STATS 0x00130000 11496 #define DRV_MSG_CODE_STATS_TYPE_LAN 1 11497 #define DRV_MSG_CODE_STATS_TYPE_FCOE 2 11498 #define DRV_MSG_CODE_STATS_TYPE_ISCSI 3 11499 #define DRV_MSG_CODE_STATS_TYPE_RDMA 4 11500 11501 #define DRV_MSG_CODE_MASK_PARITIES 0x001a0000 11502 11503 #define DRV_MSG_CODE_BIST_TEST 0x001e0000 11504 #define DRV_MSG_CODE_SET_LED_MODE 0x00200000 11505 #define DRV_MSG_CODE_RESOURCE_CMD 0x00230000 11506 11507 #define RESOURCE_CMD_REQ_RESC_MASK 0x0000001F 11508 #define RESOURCE_CMD_REQ_RESC_SHIFT 0 11509 #define RESOURCE_CMD_REQ_OPCODE_MASK 0x000000E0 11510 #define RESOURCE_CMD_REQ_OPCODE_SHIFT 5 11511 #define RESOURCE_OPCODE_REQ 1 11512 #define RESOURCE_OPCODE_REQ_WO_AGING 2 11513 #define RESOURCE_OPCODE_REQ_W_AGING 3 11514 #define RESOURCE_OPCODE_RELEASE 4 11515 #define RESOURCE_OPCODE_FORCE_RELEASE 5 11516 #define RESOURCE_CMD_REQ_AGE_MASK 0x0000FF00 11517 #define RESOURCE_CMD_REQ_AGE_SHIFT 8 11518 11519 #define RESOURCE_CMD_RSP_OWNER_MASK 0x000000FF 11520 #define RESOURCE_CMD_RSP_OWNER_SHIFT 0 11521 #define RESOURCE_CMD_RSP_OPCODE_MASK 0x00000700 11522 #define RESOURCE_CMD_RSP_OPCODE_SHIFT 8 11523 #define RESOURCE_OPCODE_GNT 1 11524 #define RESOURCE_OPCODE_BUSY 2 11525 #define RESOURCE_OPCODE_RELEASED 3 11526 #define RESOURCE_OPCODE_RELEASED_PREVIOUS 4 11527 #define RESOURCE_OPCODE_WRONG_OWNER 5 11528 #define RESOURCE_OPCODE_UNKNOWN_CMD 255 11529 11530 #define RESOURCE_DUMP 0 11531 11532 #define DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL 0x002b0000 11533 #define DRV_MSG_CODE_OS_WOL 0x002e0000 11534 11535 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 11536 11537 u32 drv_mb_param; 11538 #define DRV_MB_PARAM_UNLOAD_WOL_UNKNOWN 0x00000000 11539 #define DRV_MB_PARAM_UNLOAD_WOL_MCP 0x00000001 11540 #define DRV_MB_PARAM_UNLOAD_WOL_DISABLED 0x00000002 11541 #define DRV_MB_PARAM_UNLOAD_WOL_ENABLED 0x00000003 11542 #define DRV_MB_PARAM_DCBX_NOTIFY_MASK 0x000000FF 11543 #define DRV_MB_PARAM_DCBX_NOTIFY_SHIFT 3 11544 11545 #define DRV_MB_PARAM_NVM_LEN_SHIFT 24 11546 11547 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT 0 11548 #define DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK 0x000000FF 11549 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT 8 11550 #define DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK 0x0000FF00 11551 #define DRV_MB_PARAM_LLDP_SEND_MASK 0x00000001 11552 #define DRV_MB_PARAM_LLDP_SEND_SHIFT 0 11553 11554 #define DRV_MB_PARAM_OV_CURR_CFG_SHIFT 0 11555 #define DRV_MB_PARAM_OV_CURR_CFG_MASK 0x0000000F 11556 #define DRV_MB_PARAM_OV_CURR_CFG_NONE 0 11557 #define DRV_MB_PARAM_OV_CURR_CFG_OS 1 11558 #define DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC 2 11559 #define DRV_MB_PARAM_OV_CURR_CFG_OTHER 3 11560 11561 #define DRV_MB_PARAM_OV_STORM_FW_VER_SHIFT 0 11562 #define DRV_MB_PARAM_OV_STORM_FW_VER_MASK 0xFFFFFFFF 11563 #define DRV_MB_PARAM_OV_STORM_FW_VER_MAJOR_MASK 0xFF000000 11564 #define DRV_MB_PARAM_OV_STORM_FW_VER_MINOR_MASK 0x00FF0000 11565 #define DRV_MB_PARAM_OV_STORM_FW_VER_BUILD_MASK 0x0000FF00 11566 #define DRV_MB_PARAM_OV_STORM_FW_VER_DROP_MASK 0x000000FF 11567 11568 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_SHIFT 0 11569 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_MASK 0xF 11570 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_UNKNOWN 0x1 11571 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED 0x2 11572 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_LOADING 0x3 11573 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED 0x4 11574 #define DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE 0x5 11575 11576 #define DRV_MB_PARAM_OV_MTU_SIZE_SHIFT 0 11577 #define DRV_MB_PARAM_OV_MTU_SIZE_MASK 0xFFFFFFFF 11578 11579 #define DRV_MB_PARAM_WOL_MASK (DRV_MB_PARAM_WOL_DEFAULT | \ 11580 DRV_MB_PARAM_WOL_DISABLED | \ 11581 DRV_MB_PARAM_WOL_ENABLED) 11582 #define DRV_MB_PARAM_WOL_DEFAULT DRV_MB_PARAM_UNLOAD_WOL_MCP 11583 #define DRV_MB_PARAM_WOL_DISABLED DRV_MB_PARAM_UNLOAD_WOL_DISABLED 11584 #define DRV_MB_PARAM_WOL_ENABLED DRV_MB_PARAM_UNLOAD_WOL_ENABLED 11585 11586 #define DRV_MB_PARAM_ESWITCH_MODE_MASK (DRV_MB_PARAM_ESWITCH_MODE_NONE | \ 11587 DRV_MB_PARAM_ESWITCH_MODE_VEB | \ 11588 DRV_MB_PARAM_ESWITCH_MODE_VEPA) 11589 #define DRV_MB_PARAM_ESWITCH_MODE_NONE 0x0 11590 #define DRV_MB_PARAM_ESWITCH_MODE_VEB 0x1 11591 #define DRV_MB_PARAM_ESWITCH_MODE_VEPA 0x2 11592 11593 #define DRV_MB_PARAM_SET_LED_MODE_OPER 0x0 11594 #define DRV_MB_PARAM_SET_LED_MODE_ON 0x1 11595 #define DRV_MB_PARAM_SET_LED_MODE_OFF 0x2 11596 11597 /* Resource Allocation params - Driver version support */ 11598 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 11599 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16 11600 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF 11601 #define DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0 11602 11603 #define DRV_MB_PARAM_BIST_REGISTER_TEST 1 11604 #define DRV_MB_PARAM_BIST_CLOCK_TEST 2 11605 #define DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES 3 11606 #define DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX 4 11607 11608 #define DRV_MB_PARAM_BIST_RC_UNKNOWN 0 11609 #define DRV_MB_PARAM_BIST_RC_PASSED 1 11610 #define DRV_MB_PARAM_BIST_RC_FAILED 2 11611 #define DRV_MB_PARAM_BIST_RC_INVALID_PARAMETER 3 11612 11613 #define DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT 0 11614 #define DRV_MB_PARAM_BIST_TEST_INDEX_MASK 0x000000FF 11615 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT 8 11616 #define DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_MASK 0x0000FF00 11617 11618 u32 fw_mb_header; 11619 #define FW_MSG_CODE_MASK 0xffff0000 11620 #define FW_MSG_CODE_UNSUPPORTED 0x00000000 11621 #define FW_MSG_CODE_DRV_LOAD_ENGINE 0x10100000 11622 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 11623 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 11624 #define FW_MSG_CODE_DRV_LOAD_REFUSED_PDA 0x10200000 11625 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1 0x10210000 11626 #define FW_MSG_CODE_DRV_LOAD_REFUSED_DIAG 0x10220000 11627 #define FW_MSG_CODE_DRV_LOAD_REFUSED_HSI 0x10230000 11628 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE 0x10300000 11629 #define FW_MSG_CODE_DRV_LOAD_REFUSED_REJECT 0x10310000 11630 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 11631 #define FW_MSG_CODE_DRV_UNLOAD_ENGINE 0x20110000 11632 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20120000 11633 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20130000 11634 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 11635 #define FW_MSG_CODE_RESOURCE_ALLOC_OK 0x34000000 11636 #define FW_MSG_CODE_RESOURCE_ALLOC_UNKNOWN 0x35000000 11637 #define FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED 0x36000000 11638 #define FW_MSG_CODE_S_TAG_UPDATE_ACK_DONE 0x3b000000 11639 #define FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE 0xb0010000 11640 11641 #define FW_MSG_CODE_NVM_OK 0x00010000 11642 #define FW_MSG_CODE_OK 0x00160000 11643 11644 #define FW_MSG_CODE_OS_WOL_SUPPORTED 0x00800000 11645 #define FW_MSG_CODE_OS_WOL_NOT_SUPPORTED 0x00810000 11646 #define FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE 0x00870000 11647 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 11648 11649 u32 fw_mb_param; 11650 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_MASK 0xFFFF0000 11651 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT 16 11652 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_MASK 0x0000FFFF 11653 #define FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT 0 11654 11655 /* get pf rdma protocol command responce */ 11656 #define FW_MB_PARAM_GET_PF_RDMA_NONE 0x0 11657 #define FW_MB_PARAM_GET_PF_RDMA_ROCE 0x1 11658 #define FW_MB_PARAM_GET_PF_RDMA_IWARP 0x2 11659 #define FW_MB_PARAM_GET_PF_RDMA_BOTH 0x3 11660 11661 #define FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR (1 << 0) 11662 11663 u32 drv_pulse_mb; 11664 #define DRV_PULSE_SEQ_MASK 0x00007fff 11665 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 11666 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 11667 11668 u32 mcp_pulse_mb; 11669 #define MCP_PULSE_SEQ_MASK 0x00007fff 11670 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 11671 #define MCP_EVENT_MASK 0xffff0000 11672 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 11673 11674 union drv_union_data union_data; 11675 }; 11676 11677 enum MFW_DRV_MSG_TYPE { 11678 MFW_DRV_MSG_LINK_CHANGE, 11679 MFW_DRV_MSG_FLR_FW_ACK_FAILED, 11680 MFW_DRV_MSG_VF_DISABLED, 11681 MFW_DRV_MSG_LLDP_DATA_UPDATED, 11682 MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED, 11683 MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED, 11684 MFW_DRV_MSG_RESERVED4, 11685 MFW_DRV_MSG_BW_UPDATE, 11686 MFW_DRV_MSG_S_TAG_UPDATE, 11687 MFW_DRV_MSG_GET_LAN_STATS, 11688 MFW_DRV_MSG_GET_FCOE_STATS, 11689 MFW_DRV_MSG_GET_ISCSI_STATS, 11690 MFW_DRV_MSG_GET_RDMA_STATS, 11691 MFW_DRV_MSG_BW_UPDATE10, 11692 MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE, 11693 MFW_DRV_MSG_BW_UPDATE11, 11694 MFW_DRV_MSG_MAX 11695 }; 11696 11697 #define MFW_DRV_MSG_MAX_DWORDS(msgs) (((msgs - 1) >> 2) + 1) 11698 #define MFW_DRV_MSG_DWORD(msg_id) (msg_id >> 2) 11699 #define MFW_DRV_MSG_OFFSET(msg_id) ((msg_id & 0x3) << 3) 11700 #define MFW_DRV_MSG_MASK(msg_id) (0xff << MFW_DRV_MSG_OFFSET(msg_id)) 11701 11702 struct public_mfw_mb { 11703 u32 sup_msgs; 11704 u32 msg[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; 11705 u32 ack[MFW_DRV_MSG_MAX_DWORDS(MFW_DRV_MSG_MAX)]; 11706 }; 11707 11708 enum public_sections { 11709 PUBLIC_DRV_MB, 11710 PUBLIC_MFW_MB, 11711 PUBLIC_GLOBAL, 11712 PUBLIC_PATH, 11713 PUBLIC_PORT, 11714 PUBLIC_FUNC, 11715 PUBLIC_MAX_SECTIONS 11716 }; 11717 11718 struct mcp_public_data { 11719 u32 num_sections; 11720 u32 sections[PUBLIC_MAX_SECTIONS]; 11721 struct public_drv_mb drv_mb[MCP_GLOB_FUNC_MAX]; 11722 struct public_mfw_mb mfw_mb[MCP_GLOB_FUNC_MAX]; 11723 struct public_global global; 11724 struct public_path path[MCP_GLOB_PATH_MAX]; 11725 struct public_port port[MCP_GLOB_PORT_MAX]; 11726 struct public_func func[MCP_GLOB_FUNC_MAX]; 11727 }; 11728 11729 struct nvm_cfg_mac_address { 11730 u32 mac_addr_hi; 11731 #define NVM_CFG_MAC_ADDRESS_HI_MASK 0x0000FFFF 11732 #define NVM_CFG_MAC_ADDRESS_HI_OFFSET 0 11733 u32 mac_addr_lo; 11734 }; 11735 11736 struct nvm_cfg1_glob { 11737 u32 generic_cont0; 11738 #define NVM_CFG1_GLOB_MF_MODE_MASK 0x00000FF0 11739 #define NVM_CFG1_GLOB_MF_MODE_OFFSET 4 11740 #define NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED 0x0 11741 #define NVM_CFG1_GLOB_MF_MODE_DEFAULT 0x1 11742 #define NVM_CFG1_GLOB_MF_MODE_SPIO4 0x2 11743 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_0 0x3 11744 #define NVM_CFG1_GLOB_MF_MODE_NPAR1_5 0x4 11745 #define NVM_CFG1_GLOB_MF_MODE_NPAR2_0 0x5 11746 #define NVM_CFG1_GLOB_MF_MODE_BD 0x6 11747 #define NVM_CFG1_GLOB_MF_MODE_UFP 0x7 11748 u32 engineering_change[3]; 11749 u32 manufacturing_id; 11750 u32 serial_number[4]; 11751 u32 pcie_cfg; 11752 u32 mgmt_traffic; 11753 u32 core_cfg; 11754 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK 0x000000FF 11755 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET 0 11756 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G 0x0 11757 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G 0x1 11758 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G 0x2 11759 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F 0x3 11760 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E 0x4 11761 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G 0x5 11762 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G 0xB 11763 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G 0xC 11764 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G 0xD 11765 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G 0xE 11766 #define NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G 0xF 11767 11768 u32 e_lane_cfg1; 11769 u32 e_lane_cfg2; 11770 u32 f_lane_cfg1; 11771 u32 f_lane_cfg2; 11772 u32 mps10_preemphasis; 11773 u32 mps10_driver_current; 11774 u32 mps25_preemphasis; 11775 u32 mps25_driver_current; 11776 u32 pci_id; 11777 u32 pci_subsys_id; 11778 u32 bar; 11779 u32 mps10_txfir_main; 11780 u32 mps10_txfir_post; 11781 u32 mps25_txfir_main; 11782 u32 mps25_txfir_post; 11783 u32 manufacture_ver; 11784 u32 manufacture_time; 11785 u32 led_global_settings; 11786 u32 generic_cont1; 11787 u32 mbi_version; 11788 #define NVM_CFG1_GLOB_MBI_VERSION_0_MASK 0x000000FF 11789 #define NVM_CFG1_GLOB_MBI_VERSION_0_OFFSET 0 11790 #define NVM_CFG1_GLOB_MBI_VERSION_1_MASK 0x0000FF00 11791 #define NVM_CFG1_GLOB_MBI_VERSION_1_OFFSET 8 11792 #define NVM_CFG1_GLOB_MBI_VERSION_2_MASK 0x00FF0000 11793 #define NVM_CFG1_GLOB_MBI_VERSION_2_OFFSET 16 11794 u32 mbi_date; 11795 u32 misc_sig; 11796 u32 device_capabilities; 11797 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET 0x1 11798 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE 0x2 11799 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI 0x4 11800 #define NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE 0x8 11801 u32 power_dissipated; 11802 u32 power_consumed; 11803 u32 efi_version; 11804 u32 multi_network_modes_capability; 11805 u32 reserved[41]; 11806 }; 11807 11808 struct nvm_cfg1_path { 11809 u32 reserved[30]; 11810 }; 11811 11812 struct nvm_cfg1_port { 11813 u32 reserved__m_relocated_to_option_123; 11814 u32 reserved__m_relocated_to_option_124; 11815 u32 generic_cont0; 11816 #define NVM_CFG1_PORT_DCBX_MODE_MASK 0x000F0000 11817 #define NVM_CFG1_PORT_DCBX_MODE_OFFSET 16 11818 #define NVM_CFG1_PORT_DCBX_MODE_DISABLED 0x0 11819 #define NVM_CFG1_PORT_DCBX_MODE_IEEE 0x1 11820 #define NVM_CFG1_PORT_DCBX_MODE_CEE 0x2 11821 #define NVM_CFG1_PORT_DCBX_MODE_DYNAMIC 0x3 11822 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_MASK 0x00F00000 11823 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_OFFSET 20 11824 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ETHERNET 0x1 11825 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_FCOE 0x2 11826 #define NVM_CFG1_PORT_DEFAULT_ENABLED_PROTOCOLS_ISCSI 0x4 11827 u32 pcie_cfg; 11828 u32 features; 11829 u32 speed_cap_mask; 11830 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK 0x0000FFFF 11831 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_OFFSET 0 11832 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_1G 0x1 11833 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_10G 0x2 11834 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_25G 0x8 11835 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_40G 0x10 11836 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_50G 0x20 11837 #define NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_BB_100G 0x40 11838 u32 link_settings; 11839 #define NVM_CFG1_PORT_DRV_LINK_SPEED_MASK 0x0000000F 11840 #define NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET 0 11841 #define NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG 0x0 11842 #define NVM_CFG1_PORT_DRV_LINK_SPEED_1G 0x1 11843 #define NVM_CFG1_PORT_DRV_LINK_SPEED_10G 0x2 11844 #define NVM_CFG1_PORT_DRV_LINK_SPEED_25G 0x4 11845 #define NVM_CFG1_PORT_DRV_LINK_SPEED_40G 0x5 11846 #define NVM_CFG1_PORT_DRV_LINK_SPEED_50G 0x6 11847 #define NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G 0x7 11848 #define NVM_CFG1_PORT_DRV_LINK_SPEED_SMARTLINQ 0x8 11849 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK 0x00000070 11850 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET 4 11851 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG 0x1 11852 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX 0x2 11853 #define NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX 0x4 11854 u32 phy_cfg; 11855 u32 mgmt_traffic; 11856 u32 ext_phy; 11857 u32 mba_cfg1; 11858 u32 mba_cfg2; 11859 u32 vf_cfg; 11860 struct nvm_cfg_mac_address lldp_mac_address; 11861 u32 led_port_settings; 11862 u32 transceiver_00; 11863 u32 device_ids; 11864 u32 board_cfg; 11865 u32 mnm_10g_cap; 11866 u32 mnm_10g_ctrl; 11867 u32 mnm_10g_misc; 11868 u32 mnm_25g_cap; 11869 u32 mnm_25g_ctrl; 11870 u32 mnm_25g_misc; 11871 u32 mnm_40g_cap; 11872 u32 mnm_40g_ctrl; 11873 u32 mnm_40g_misc; 11874 u32 mnm_50g_cap; 11875 u32 mnm_50g_ctrl; 11876 u32 mnm_50g_misc; 11877 u32 mnm_100g_cap; 11878 u32 mnm_100g_ctrl; 11879 u32 mnm_100g_misc; 11880 u32 reserved[116]; 11881 }; 11882 11883 struct nvm_cfg1_func { 11884 struct nvm_cfg_mac_address mac_address; 11885 u32 rsrv1; 11886 u32 rsrv2; 11887 u32 device_id; 11888 u32 cmn_cfg; 11889 u32 pci_cfg; 11890 struct nvm_cfg_mac_address fcoe_node_wwn_mac_addr; 11891 struct nvm_cfg_mac_address fcoe_port_wwn_mac_addr; 11892 u32 preboot_generic_cfg; 11893 u32 reserved[8]; 11894 }; 11895 11896 struct nvm_cfg1 { 11897 struct nvm_cfg1_glob glob; 11898 struct nvm_cfg1_path path[MCP_GLOB_PATH_MAX]; 11899 struct nvm_cfg1_port port[MCP_GLOB_PORT_MAX]; 11900 struct nvm_cfg1_func func[MCP_GLOB_FUNC_MAX]; 11901 }; 11902 11903 enum spad_sections { 11904 SPAD_SECTION_TRACE, 11905 SPAD_SECTION_NVM_CFG, 11906 SPAD_SECTION_PUBLIC, 11907 SPAD_SECTION_PRIVATE, 11908 SPAD_SECTION_MAX 11909 }; 11910 11911 #define MCP_TRACE_SIZE 2048 /* 2kb */ 11912 11913 /* This section is located at a fixed location in the beginning of the 11914 * scratchpad, to ensure that the MCP trace is not run over during MFW upgrade. 11915 * All the rest of data has a floating location which differs from version to 11916 * version, and is pointed by the mcp_meta_data below. 11917 * Moreover, the spad_layout section is part of the MFW firmware, and is loaded 11918 * with it from nvram in order to clear this portion. 11919 */ 11920 struct static_init { 11921 u32 num_sections; 11922 offsize_t sections[SPAD_SECTION_MAX]; 11923 #define SECTION(_sec_) (*((offsize_t *)(STRUCT_OFFSET(sections[_sec_])))) 11924 11925 struct mcp_trace trace; 11926 #define MCP_TRACE_P ((struct mcp_trace *)(STRUCT_OFFSET(trace))) 11927 u8 trace_buffer[MCP_TRACE_SIZE]; 11928 #define MCP_TRACE_BUF ((u8 *)(STRUCT_OFFSET(trace_buffer))) 11929 /* running_mfw has the same definition as in nvm_map.h. 11930 * This bit indicate both the running dir, and the running bundle. 11931 * It is set once when the LIM is loaded. 11932 */ 11933 u32 running_mfw; 11934 #define RUNNING_MFW (*((u32 *)(STRUCT_OFFSET(running_mfw)))) 11935 u32 build_time; 11936 #define MFW_BUILD_TIME (*((u32 *)(STRUCT_OFFSET(build_time)))) 11937 u32 reset_type; 11938 #define RESET_TYPE (*((u32 *)(STRUCT_OFFSET(reset_type)))) 11939 u32 mfw_secure_mode; 11940 #define MFW_SECURE_MODE (*((u32 *)(STRUCT_OFFSET(mfw_secure_mode)))) 11941 u16 pme_status_pf_bitmap; 11942 #define PME_STATUS_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_status_pf_bitmap)))) 11943 u16 pme_enable_pf_bitmap; 11944 #define PME_ENABLE_PF_BITMAP (*((u16 *)(STRUCT_OFFSET(pme_enable_pf_bitmap)))) 11945 u32 mim_nvm_addr; 11946 u32 mim_start_addr; 11947 u32 ah_pcie_link_params; 11948 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_MASK (0x000000ff) 11949 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_SHIFT (0) 11950 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_MASK (0x0000ff00) 11951 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_SHIFT (8) 11952 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_MASK (0x00ff0000) 11953 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_SHIFT (16) 11954 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_MASK (0xff000000) 11955 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_SHIFT (24) 11956 #define AH_PCIE_LINK_PARAMS (*((u32 *)(STRUCT_OFFSET(ah_pcie_link_params)))) 11957 11958 u32 rsrv_persist[5]; /* Persist reserved for MFW upgrades */ 11959 }; 11960 11961 #define NVM_MAGIC_VALUE 0x669955aa 11962 11963 enum nvm_image_type { 11964 NVM_TYPE_TIM1 = 0x01, 11965 NVM_TYPE_TIM2 = 0x02, 11966 NVM_TYPE_MIM1 = 0x03, 11967 NVM_TYPE_MIM2 = 0x04, 11968 NVM_TYPE_MBA = 0x05, 11969 NVM_TYPE_MODULES_PN = 0x06, 11970 NVM_TYPE_VPD = 0x07, 11971 NVM_TYPE_MFW_TRACE1 = 0x08, 11972 NVM_TYPE_MFW_TRACE2 = 0x09, 11973 NVM_TYPE_NVM_CFG1 = 0x0a, 11974 NVM_TYPE_L2B = 0x0b, 11975 NVM_TYPE_DIR1 = 0x0c, 11976 NVM_TYPE_EAGLE_FW1 = 0x0d, 11977 NVM_TYPE_FALCON_FW1 = 0x0e, 11978 NVM_TYPE_PCIE_FW1 = 0x0f, 11979 NVM_TYPE_HW_SET = 0x10, 11980 NVM_TYPE_LIM = 0x11, 11981 NVM_TYPE_AVS_FW1 = 0x12, 11982 NVM_TYPE_DIR2 = 0x13, 11983 NVM_TYPE_CCM = 0x14, 11984 NVM_TYPE_EAGLE_FW2 = 0x15, 11985 NVM_TYPE_FALCON_FW2 = 0x16, 11986 NVM_TYPE_PCIE_FW2 = 0x17, 11987 NVM_TYPE_AVS_FW2 = 0x18, 11988 NVM_TYPE_INIT_HW = 0x19, 11989 NVM_TYPE_DEFAULT_CFG = 0x1a, 11990 NVM_TYPE_MDUMP = 0x1b, 11991 NVM_TYPE_META = 0x1c, 11992 NVM_TYPE_ISCSI_CFG = 0x1d, 11993 NVM_TYPE_FCOE_CFG = 0x1f, 11994 NVM_TYPE_ETH_PHY_FW1 = 0x20, 11995 NVM_TYPE_ETH_PHY_FW2 = 0x21, 11996 NVM_TYPE_MAX, 11997 }; 11998 11999 #define DIR_ID_1 (0) 12000 12001 #endif 12002