1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015 QLogic Corporation 3 * 4 * This software is available under the terms of the GNU General Public License 5 * (GPL) Version 2, available from the file COPYING in the main directory of 6 * this source tree. 7 */ 8 9 #include <linux/types.h> 10 #include <asm/byteorder.h> 11 #include <linux/io.h> 12 #include <linux/delay.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/errno.h> 15 #include <linux/kernel.h> 16 #include <linux/mutex.h> 17 #include <linux/pci.h> 18 #include <linux/slab.h> 19 #include <linux/string.h> 20 #include <linux/vmalloc.h> 21 #include <linux/etherdevice.h> 22 #include <linux/qed/qed_chain.h> 23 #include <linux/qed/qed_if.h> 24 #include "qed.h" 25 #include "qed_cxt.h" 26 #include "qed_dcbx.h" 27 #include "qed_dev_api.h" 28 #include "qed_hsi.h" 29 #include "qed_hw.h" 30 #include "qed_init_ops.h" 31 #include "qed_int.h" 32 #include "qed_ll2.h" 33 #include "qed_mcp.h" 34 #include "qed_reg_addr.h" 35 #include "qed_sp.h" 36 #include "qed_sriov.h" 37 #include "qed_vf.h" 38 #include "qed_roce.h" 39 40 static DEFINE_SPINLOCK(qm_lock); 41 42 #define QED_MIN_DPIS (4) 43 #define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS) 44 45 /* API common to all protocols */ 46 enum BAR_ID { 47 BAR_ID_0, /* used for GRC */ 48 BAR_ID_1 /* Used for doorbells */ 49 }; 50 51 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, enum BAR_ID bar_id) 52 { 53 u32 bar_reg = (bar_id == BAR_ID_0 ? 54 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE); 55 u32 val; 56 57 if (IS_VF(p_hwfn->cdev)) 58 return 1 << 17; 59 60 val = qed_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg); 61 if (val) 62 return 1 << (val + 15); 63 64 /* Old MFW initialized above registered only conditionally */ 65 if (p_hwfn->cdev->num_hwfns > 1) { 66 DP_INFO(p_hwfn, 67 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n"); 68 return BAR_ID_0 ? 256 * 1024 : 512 * 1024; 69 } else { 70 DP_INFO(p_hwfn, 71 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n"); 72 return 512 * 1024; 73 } 74 } 75 76 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level) 77 { 78 u32 i; 79 80 cdev->dp_level = dp_level; 81 cdev->dp_module = dp_module; 82 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 83 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 84 85 p_hwfn->dp_level = dp_level; 86 p_hwfn->dp_module = dp_module; 87 } 88 } 89 90 void qed_init_struct(struct qed_dev *cdev) 91 { 92 u8 i; 93 94 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 95 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 96 97 p_hwfn->cdev = cdev; 98 p_hwfn->my_id = i; 99 p_hwfn->b_active = false; 100 101 mutex_init(&p_hwfn->dmae_info.mutex); 102 } 103 104 /* hwfn 0 is always active */ 105 cdev->hwfns[0].b_active = true; 106 107 /* set the default cache alignment to 128 */ 108 cdev->cache_shift = 7; 109 } 110 111 static void qed_qm_info_free(struct qed_hwfn *p_hwfn) 112 { 113 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 114 115 kfree(qm_info->qm_pq_params); 116 qm_info->qm_pq_params = NULL; 117 kfree(qm_info->qm_vport_params); 118 qm_info->qm_vport_params = NULL; 119 kfree(qm_info->qm_port_params); 120 qm_info->qm_port_params = NULL; 121 kfree(qm_info->wfq_data); 122 qm_info->wfq_data = NULL; 123 } 124 125 void qed_resc_free(struct qed_dev *cdev) 126 { 127 int i; 128 129 if (IS_VF(cdev)) 130 return; 131 132 kfree(cdev->fw_data); 133 cdev->fw_data = NULL; 134 135 kfree(cdev->reset_stats); 136 137 for_each_hwfn(cdev, i) { 138 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 139 140 kfree(p_hwfn->p_tx_cids); 141 p_hwfn->p_tx_cids = NULL; 142 kfree(p_hwfn->p_rx_cids); 143 p_hwfn->p_rx_cids = NULL; 144 } 145 146 for_each_hwfn(cdev, i) { 147 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 148 149 qed_cxt_mngr_free(p_hwfn); 150 qed_qm_info_free(p_hwfn); 151 qed_spq_free(p_hwfn); 152 qed_eq_free(p_hwfn, p_hwfn->p_eq); 153 qed_consq_free(p_hwfn, p_hwfn->p_consq); 154 qed_int_free(p_hwfn); 155 #ifdef CONFIG_QED_LL2 156 qed_ll2_free(p_hwfn, p_hwfn->p_ll2_info); 157 #endif 158 qed_iov_free(p_hwfn); 159 qed_dmae_info_free(p_hwfn); 160 qed_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info); 161 } 162 } 163 164 static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable) 165 { 166 u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue = 0; 167 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 168 struct init_qm_port_params *p_qm_port; 169 bool init_rdma_offload_pq = false; 170 bool init_pure_ack_pq = false; 171 bool init_ooo_pq = false; 172 u16 num_pqs, multi_cos_tcs = 1; 173 u8 pf_wfq = qm_info->pf_wfq; 174 u32 pf_rl = qm_info->pf_rl; 175 u16 num_pf_rls = 0; 176 u16 num_vfs = 0; 177 178 #ifdef CONFIG_QED_SRIOV 179 if (p_hwfn->cdev->p_iov_info) 180 num_vfs = p_hwfn->cdev->p_iov_info->total_vfs; 181 #endif 182 memset(qm_info, 0, sizeof(*qm_info)); 183 184 num_pqs = multi_cos_tcs + num_vfs + 1; /* The '1' is for pure-LB */ 185 num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT); 186 187 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) { 188 num_pqs++; /* for RoCE queue */ 189 init_rdma_offload_pq = true; 190 /* we subtract num_vfs because each require a rate limiter, 191 * and one default rate limiter 192 */ 193 if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn) 194 num_pf_rls = RESC_NUM(p_hwfn, QED_RL) - num_vfs - 1; 195 196 num_pqs += num_pf_rls; 197 qm_info->num_pf_rls = (u8) num_pf_rls; 198 } 199 200 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 201 num_pqs += 2; /* for iSCSI pure-ACK / OOO queue */ 202 init_pure_ack_pq = true; 203 init_ooo_pq = true; 204 } 205 206 /* Sanity checking that setup requires legal number of resources */ 207 if (num_pqs > RESC_NUM(p_hwfn, QED_PQ)) { 208 DP_ERR(p_hwfn, 209 "Need too many Physical queues - 0x%04x when only %04x are available\n", 210 num_pqs, RESC_NUM(p_hwfn, QED_PQ)); 211 return -EINVAL; 212 } 213 214 /* PQs will be arranged as follows: First per-TC PQ then pure-LB quete. 215 */ 216 qm_info->qm_pq_params = kcalloc(num_pqs, 217 sizeof(struct init_qm_pq_params), 218 b_sleepable ? GFP_KERNEL : GFP_ATOMIC); 219 if (!qm_info->qm_pq_params) 220 goto alloc_err; 221 222 qm_info->qm_vport_params = kcalloc(num_vports, 223 sizeof(struct init_qm_vport_params), 224 b_sleepable ? GFP_KERNEL 225 : GFP_ATOMIC); 226 if (!qm_info->qm_vport_params) 227 goto alloc_err; 228 229 qm_info->qm_port_params = kcalloc(MAX_NUM_PORTS, 230 sizeof(struct init_qm_port_params), 231 b_sleepable ? GFP_KERNEL 232 : GFP_ATOMIC); 233 if (!qm_info->qm_port_params) 234 goto alloc_err; 235 236 qm_info->wfq_data = kcalloc(num_vports, sizeof(struct qed_wfq_data), 237 b_sleepable ? GFP_KERNEL : GFP_ATOMIC); 238 if (!qm_info->wfq_data) 239 goto alloc_err; 240 241 vport_id = (u8)RESC_START(p_hwfn, QED_VPORT); 242 243 /* First init rate limited queues */ 244 for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) { 245 qm_info->qm_pq_params[curr_queue].vport_id = vport_id++; 246 qm_info->qm_pq_params[curr_queue].tc_id = 247 p_hwfn->hw_info.non_offload_tc; 248 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 249 qm_info->qm_pq_params[curr_queue].rl_valid = 1; 250 } 251 252 /* First init per-TC PQs */ 253 for (i = 0; i < multi_cos_tcs; i++) { 254 struct init_qm_pq_params *params = 255 &qm_info->qm_pq_params[curr_queue++]; 256 257 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE || 258 p_hwfn->hw_info.personality == QED_PCI_ETH) { 259 params->vport_id = vport_id; 260 params->tc_id = p_hwfn->hw_info.non_offload_tc; 261 params->wrr_group = 1; 262 } else { 263 params->vport_id = vport_id; 264 params->tc_id = p_hwfn->hw_info.offload_tc; 265 params->wrr_group = 1; 266 } 267 } 268 269 /* Then init pure-LB PQ */ 270 qm_info->pure_lb_pq = curr_queue; 271 qm_info->qm_pq_params[curr_queue].vport_id = 272 (u8) RESC_START(p_hwfn, QED_VPORT); 273 qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC; 274 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 275 curr_queue++; 276 277 qm_info->offload_pq = 0; 278 if (init_rdma_offload_pq) { 279 qm_info->offload_pq = curr_queue; 280 qm_info->qm_pq_params[curr_queue].vport_id = vport_id; 281 qm_info->qm_pq_params[curr_queue].tc_id = 282 p_hwfn->hw_info.offload_tc; 283 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 284 curr_queue++; 285 } 286 287 if (init_pure_ack_pq) { 288 qm_info->pure_ack_pq = curr_queue; 289 qm_info->qm_pq_params[curr_queue].vport_id = vport_id; 290 qm_info->qm_pq_params[curr_queue].tc_id = 291 p_hwfn->hw_info.offload_tc; 292 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 293 curr_queue++; 294 } 295 296 if (init_ooo_pq) { 297 qm_info->ooo_pq = curr_queue; 298 qm_info->qm_pq_params[curr_queue].vport_id = vport_id; 299 qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC; 300 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 301 curr_queue++; 302 } 303 304 /* Then init per-VF PQs */ 305 vf_offset = curr_queue; 306 for (i = 0; i < num_vfs; i++) { 307 /* First vport is used by the PF */ 308 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1; 309 qm_info->qm_pq_params[curr_queue].tc_id = 310 p_hwfn->hw_info.non_offload_tc; 311 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 312 qm_info->qm_pq_params[curr_queue].rl_valid = 1; 313 curr_queue++; 314 } 315 316 qm_info->vf_queues_offset = vf_offset; 317 qm_info->num_pqs = num_pqs; 318 qm_info->num_vports = num_vports; 319 320 /* Initialize qm port parameters */ 321 num_ports = p_hwfn->cdev->num_ports_in_engines; 322 for (i = 0; i < num_ports; i++) { 323 p_qm_port = &qm_info->qm_port_params[i]; 324 p_qm_port->active = 1; 325 if (num_ports == 4) 326 p_qm_port->active_phys_tcs = 0x7; 327 else 328 p_qm_port->active_phys_tcs = 0x9f; 329 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports; 330 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports; 331 } 332 333 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS; 334 335 qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ); 336 337 qm_info->num_vf_pqs = num_vfs; 338 qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT); 339 340 for (i = 0; i < qm_info->num_vports; i++) 341 qm_info->qm_vport_params[i].vport_wfq = 1; 342 343 qm_info->vport_rl_en = 1; 344 qm_info->vport_wfq_en = 1; 345 qm_info->pf_rl = pf_rl; 346 qm_info->pf_wfq = pf_wfq; 347 348 return 0; 349 350 alloc_err: 351 qed_qm_info_free(p_hwfn); 352 return -ENOMEM; 353 } 354 355 /* This function reconfigures the QM pf on the fly. 356 * For this purpose we: 357 * 1. reconfigure the QM database 358 * 2. set new values to runtime arrat 359 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM 360 * 4. activate init tool in QM_PF stage 361 * 5. send an sdm_qm_cmd through rbc interface to release the QM 362 */ 363 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 364 { 365 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 366 bool b_rc; 367 int rc; 368 369 /* qm_info is allocated in qed_init_qm_info() which is already called 370 * from qed_resc_alloc() or previous call of qed_qm_reconf(). 371 * The allocated size may change each init, so we free it before next 372 * allocation. 373 */ 374 qed_qm_info_free(p_hwfn); 375 376 /* initialize qed's qm data structure */ 377 rc = qed_init_qm_info(p_hwfn, false); 378 if (rc) 379 return rc; 380 381 /* stop PF's qm queues */ 382 spin_lock_bh(&qm_lock); 383 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true, 384 qm_info->start_pq, qm_info->num_pqs); 385 spin_unlock_bh(&qm_lock); 386 if (!b_rc) 387 return -EINVAL; 388 389 /* clear the QM_PF runtime phase leftovers from previous init */ 390 qed_init_clear_rt_data(p_hwfn); 391 392 /* prepare QM portion of runtime array */ 393 qed_qm_init_pf(p_hwfn); 394 395 /* activate init tool on runtime array */ 396 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id, 397 p_hwfn->hw_info.hw_mode); 398 if (rc) 399 return rc; 400 401 /* start PF's qm queues */ 402 spin_lock_bh(&qm_lock); 403 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true, 404 qm_info->start_pq, qm_info->num_pqs); 405 spin_unlock_bh(&qm_lock); 406 if (!b_rc) 407 return -EINVAL; 408 409 return 0; 410 } 411 412 int qed_resc_alloc(struct qed_dev *cdev) 413 { 414 #ifdef CONFIG_QED_LL2 415 struct qed_ll2_info *p_ll2_info; 416 #endif 417 struct qed_consq *p_consq; 418 struct qed_eq *p_eq; 419 int i, rc = 0; 420 421 if (IS_VF(cdev)) 422 return rc; 423 424 cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL); 425 if (!cdev->fw_data) 426 return -ENOMEM; 427 428 /* Allocate Memory for the Queue->CID mapping */ 429 for_each_hwfn(cdev, i) { 430 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 431 int tx_size = sizeof(struct qed_hw_cid_data) * 432 RESC_NUM(p_hwfn, QED_L2_QUEUE); 433 int rx_size = sizeof(struct qed_hw_cid_data) * 434 RESC_NUM(p_hwfn, QED_L2_QUEUE); 435 436 p_hwfn->p_tx_cids = kzalloc(tx_size, GFP_KERNEL); 437 if (!p_hwfn->p_tx_cids) 438 goto alloc_no_mem; 439 440 p_hwfn->p_rx_cids = kzalloc(rx_size, GFP_KERNEL); 441 if (!p_hwfn->p_rx_cids) 442 goto alloc_no_mem; 443 } 444 445 for_each_hwfn(cdev, i) { 446 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 447 u32 n_eqes, num_cons; 448 449 /* First allocate the context manager structure */ 450 rc = qed_cxt_mngr_alloc(p_hwfn); 451 if (rc) 452 goto alloc_err; 453 454 /* Set the HW cid/tid numbers (in the contest manager) 455 * Must be done prior to any further computations. 456 */ 457 rc = qed_cxt_set_pf_params(p_hwfn); 458 if (rc) 459 goto alloc_err; 460 461 /* Prepare and process QM requirements */ 462 rc = qed_init_qm_info(p_hwfn, true); 463 if (rc) 464 goto alloc_err; 465 466 /* Compute the ILT client partition */ 467 rc = qed_cxt_cfg_ilt_compute(p_hwfn); 468 if (rc) 469 goto alloc_err; 470 471 /* CID map / ILT shadow table / T2 472 * The talbes sizes are determined by the computations above 473 */ 474 rc = qed_cxt_tables_alloc(p_hwfn); 475 if (rc) 476 goto alloc_err; 477 478 /* SPQ, must follow ILT because initializes SPQ context */ 479 rc = qed_spq_alloc(p_hwfn); 480 if (rc) 481 goto alloc_err; 482 483 /* SP status block allocation */ 484 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn, 485 RESERVED_PTT_DPC); 486 487 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt); 488 if (rc) 489 goto alloc_err; 490 491 rc = qed_iov_alloc(p_hwfn); 492 if (rc) 493 goto alloc_err; 494 495 /* EQ */ 496 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain); 497 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) { 498 num_cons = qed_cxt_get_proto_cid_count(p_hwfn, 499 PROTOCOLID_ROCE, 500 NULL) * 2; 501 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB; 502 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 503 num_cons = 504 qed_cxt_get_proto_cid_count(p_hwfn, 505 PROTOCOLID_ISCSI, 506 NULL); 507 n_eqes += 2 * num_cons; 508 } 509 510 if (n_eqes > 0xFFFF) { 511 DP_ERR(p_hwfn, 512 "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n", 513 n_eqes, 0xFFFF); 514 rc = -EINVAL; 515 goto alloc_err; 516 } 517 518 p_eq = qed_eq_alloc(p_hwfn, (u16) n_eqes); 519 if (!p_eq) 520 goto alloc_no_mem; 521 p_hwfn->p_eq = p_eq; 522 523 p_consq = qed_consq_alloc(p_hwfn); 524 if (!p_consq) 525 goto alloc_no_mem; 526 p_hwfn->p_consq = p_consq; 527 528 #ifdef CONFIG_QED_LL2 529 if (p_hwfn->using_ll2) { 530 p_ll2_info = qed_ll2_alloc(p_hwfn); 531 if (!p_ll2_info) 532 goto alloc_no_mem; 533 p_hwfn->p_ll2_info = p_ll2_info; 534 } 535 #endif 536 537 /* DMA info initialization */ 538 rc = qed_dmae_info_alloc(p_hwfn); 539 if (rc) 540 goto alloc_err; 541 542 /* DCBX initialization */ 543 rc = qed_dcbx_info_alloc(p_hwfn); 544 if (rc) 545 goto alloc_err; 546 } 547 548 cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL); 549 if (!cdev->reset_stats) 550 goto alloc_no_mem; 551 552 return 0; 553 554 alloc_no_mem: 555 rc = -ENOMEM; 556 alloc_err: 557 qed_resc_free(cdev); 558 return rc; 559 } 560 561 void qed_resc_setup(struct qed_dev *cdev) 562 { 563 int i; 564 565 if (IS_VF(cdev)) 566 return; 567 568 for_each_hwfn(cdev, i) { 569 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 570 571 qed_cxt_mngr_setup(p_hwfn); 572 qed_spq_setup(p_hwfn); 573 qed_eq_setup(p_hwfn, p_hwfn->p_eq); 574 qed_consq_setup(p_hwfn, p_hwfn->p_consq); 575 576 /* Read shadow of current MFW mailbox */ 577 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt); 578 memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 579 p_hwfn->mcp_info->mfw_mb_cur, 580 p_hwfn->mcp_info->mfw_mb_length); 581 582 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt); 583 584 qed_iov_setup(p_hwfn, p_hwfn->p_main_ptt); 585 #ifdef CONFIG_QED_LL2 586 if (p_hwfn->using_ll2) 587 qed_ll2_setup(p_hwfn, p_hwfn->p_ll2_info); 588 #endif 589 } 590 } 591 592 #define FINAL_CLEANUP_POLL_CNT (100) 593 #define FINAL_CLEANUP_POLL_TIME (10) 594 int qed_final_cleanup(struct qed_hwfn *p_hwfn, 595 struct qed_ptt *p_ptt, u16 id, bool is_vf) 596 { 597 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT; 598 int rc = -EBUSY; 599 600 addr = GTT_BAR0_MAP_REG_USDM_RAM + 601 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id); 602 603 if (is_vf) 604 id += 0x10; 605 606 command |= X_FINAL_CLEANUP_AGG_INT << 607 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT; 608 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT; 609 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT; 610 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT; 611 612 /* Make sure notification is not set before initiating final cleanup */ 613 if (REG_RD(p_hwfn, addr)) { 614 DP_NOTICE(p_hwfn, 615 "Unexpected; Found final cleanup notification before initiating final cleanup\n"); 616 REG_WR(p_hwfn, addr, 0); 617 } 618 619 DP_VERBOSE(p_hwfn, QED_MSG_IOV, 620 "Sending final cleanup for PFVF[%d] [Command %08x\n]", 621 id, command); 622 623 qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command); 624 625 /* Poll until completion */ 626 while (!REG_RD(p_hwfn, addr) && count--) 627 msleep(FINAL_CLEANUP_POLL_TIME); 628 629 if (REG_RD(p_hwfn, addr)) 630 rc = 0; 631 else 632 DP_NOTICE(p_hwfn, 633 "Failed to receive FW final cleanup notification\n"); 634 635 /* Cleanup afterwards */ 636 REG_WR(p_hwfn, addr, 0); 637 638 return rc; 639 } 640 641 static void qed_calc_hw_mode(struct qed_hwfn *p_hwfn) 642 { 643 int hw_mode = 0; 644 645 hw_mode = (1 << MODE_BB_B0); 646 647 switch (p_hwfn->cdev->num_ports_in_engines) { 648 case 1: 649 hw_mode |= 1 << MODE_PORTS_PER_ENG_1; 650 break; 651 case 2: 652 hw_mode |= 1 << MODE_PORTS_PER_ENG_2; 653 break; 654 case 4: 655 hw_mode |= 1 << MODE_PORTS_PER_ENG_4; 656 break; 657 default: 658 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n", 659 p_hwfn->cdev->num_ports_in_engines); 660 return; 661 } 662 663 switch (p_hwfn->cdev->mf_mode) { 664 case QED_MF_DEFAULT: 665 case QED_MF_NPAR: 666 hw_mode |= 1 << MODE_MF_SI; 667 break; 668 case QED_MF_OVLAN: 669 hw_mode |= 1 << MODE_MF_SD; 670 break; 671 default: 672 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n"); 673 hw_mode |= 1 << MODE_MF_SI; 674 } 675 676 hw_mode |= 1 << MODE_ASIC; 677 678 if (p_hwfn->cdev->num_hwfns > 1) 679 hw_mode |= 1 << MODE_100G; 680 681 p_hwfn->hw_info.hw_mode = hw_mode; 682 683 DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP), 684 "Configuring function for hw_mode: 0x%08x\n", 685 p_hwfn->hw_info.hw_mode); 686 } 687 688 /* Init run time data for all PFs on an engine. */ 689 static void qed_init_cau_rt_data(struct qed_dev *cdev) 690 { 691 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET; 692 int i, sb_id; 693 694 for_each_hwfn(cdev, i) { 695 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 696 struct qed_igu_info *p_igu_info; 697 struct qed_igu_block *p_block; 698 struct cau_sb_entry sb_entry; 699 700 p_igu_info = p_hwfn->hw_info.p_igu_info; 701 702 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev); 703 sb_id++) { 704 p_block = &p_igu_info->igu_map.igu_blocks[sb_id]; 705 if (!p_block->is_pf) 706 continue; 707 708 qed_init_cau_sb_entry(p_hwfn, &sb_entry, 709 p_block->function_id, 0, 0); 710 STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry); 711 } 712 } 713 } 714 715 static int qed_hw_init_common(struct qed_hwfn *p_hwfn, 716 struct qed_ptt *p_ptt, int hw_mode) 717 { 718 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 719 struct qed_qm_common_rt_init_params params; 720 struct qed_dev *cdev = p_hwfn->cdev; 721 u16 num_pfs, pf_id; 722 u32 concrete_fid; 723 int rc = 0; 724 u8 vf_id; 725 726 qed_init_cau_rt_data(cdev); 727 728 /* Program GTT windows */ 729 qed_gtt_init(p_hwfn); 730 731 if (p_hwfn->mcp_info) { 732 if (p_hwfn->mcp_info->func_info.bandwidth_max) 733 qm_info->pf_rl_en = 1; 734 if (p_hwfn->mcp_info->func_info.bandwidth_min) 735 qm_info->pf_wfq_en = 1; 736 } 737 738 memset(¶ms, 0, sizeof(params)); 739 params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engines; 740 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port; 741 params.pf_rl_en = qm_info->pf_rl_en; 742 params.pf_wfq_en = qm_info->pf_wfq_en; 743 params.vport_rl_en = qm_info->vport_rl_en; 744 params.vport_wfq_en = qm_info->vport_wfq_en; 745 params.port_params = qm_info->qm_port_params; 746 747 qed_qm_common_rt_init(p_hwfn, ¶ms); 748 749 qed_cxt_hw_init_common(p_hwfn); 750 751 /* Close gate from NIG to BRB/Storm; By default they are open, but 752 * we close them to prevent NIG from passing data to reset blocks. 753 * Should have been done in the ENGINE phase, but init-tool lacks 754 * proper port-pretend capabilities. 755 */ 756 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0); 757 qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0); 758 qed_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1); 759 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0); 760 qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0); 761 qed_port_unpretend(p_hwfn, p_ptt); 762 763 rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode); 764 if (rc) 765 return rc; 766 767 qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0); 768 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1); 769 770 if (QED_IS_BB(p_hwfn->cdev)) { 771 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev); 772 for (pf_id = 0; pf_id < num_pfs; pf_id++) { 773 qed_fid_pretend(p_hwfn, p_ptt, pf_id); 774 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 775 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 776 } 777 /* pretend to original PF */ 778 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 779 } 780 781 for (vf_id = 0; vf_id < MAX_NUM_VFS_BB; vf_id++) { 782 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id); 783 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid); 784 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1); 785 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0); 786 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1); 787 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0); 788 } 789 /* pretend to original PF */ 790 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 791 792 return rc; 793 } 794 795 static int 796 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn, 797 struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus) 798 { 799 u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size; 800 u32 dpi_bit_shift, dpi_count; 801 u32 min_dpis; 802 803 /* Calculate DPI size */ 804 dpi_page_size_1 = QED_WID_SIZE * n_cpus; 805 dpi_page_size_2 = max_t(u32, QED_WID_SIZE, PAGE_SIZE); 806 dpi_page_size = max_t(u32, dpi_page_size_1, dpi_page_size_2); 807 dpi_page_size = roundup_pow_of_two(dpi_page_size); 808 dpi_bit_shift = ilog2(dpi_page_size / 4096); 809 810 dpi_count = pwm_region_size / dpi_page_size; 811 812 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis; 813 min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis); 814 815 p_hwfn->dpi_size = dpi_page_size; 816 p_hwfn->dpi_count = dpi_count; 817 818 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift); 819 820 if (dpi_count < min_dpis) 821 return -EINVAL; 822 823 return 0; 824 } 825 826 enum QED_ROCE_EDPM_MODE { 827 QED_ROCE_EDPM_MODE_ENABLE = 0, 828 QED_ROCE_EDPM_MODE_FORCE_ON = 1, 829 QED_ROCE_EDPM_MODE_DISABLE = 2, 830 }; 831 832 static int 833 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 834 { 835 u32 pwm_regsize, norm_regsize; 836 u32 non_pwm_conn, min_addr_reg1; 837 u32 db_bar_size, n_cpus; 838 u32 roce_edpm_mode; 839 u32 pf_dems_shift; 840 int rc = 0; 841 u8 cond; 842 843 db_bar_size = qed_hw_bar_size(p_hwfn, BAR_ID_1); 844 if (p_hwfn->cdev->num_hwfns > 1) 845 db_bar_size /= 2; 846 847 /* Calculate doorbell regions */ 848 non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) + 849 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE, 850 NULL) + 851 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, 852 NULL); 853 norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, 4096); 854 min_addr_reg1 = norm_regsize / 4096; 855 pwm_regsize = db_bar_size - norm_regsize; 856 857 /* Check that the normal and PWM sizes are valid */ 858 if (db_bar_size < norm_regsize) { 859 DP_ERR(p_hwfn->cdev, 860 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n", 861 db_bar_size, norm_regsize); 862 return -EINVAL; 863 } 864 865 if (pwm_regsize < QED_MIN_PWM_REGION) { 866 DP_ERR(p_hwfn->cdev, 867 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n", 868 pwm_regsize, 869 QED_MIN_PWM_REGION, db_bar_size, norm_regsize); 870 return -EINVAL; 871 } 872 873 /* Calculate number of DPIs */ 874 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode; 875 if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) || 876 ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) { 877 /* Either EDPM is mandatory, or we are attempting to allocate a 878 * WID per CPU. 879 */ 880 n_cpus = num_active_cpus(); 881 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 882 } 883 884 cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) || 885 (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE); 886 if (cond || p_hwfn->dcbx_no_edpm) { 887 /* Either EDPM is disabled from user configuration, or it is 888 * disabled via DCBx, or it is not mandatory and we failed to 889 * allocated a WID per CPU. 890 */ 891 n_cpus = 1; 892 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 893 894 if (cond) 895 qed_rdma_dpm_bar(p_hwfn, p_ptt); 896 } 897 898 DP_INFO(p_hwfn, 899 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n", 900 norm_regsize, 901 pwm_regsize, 902 p_hwfn->dpi_size, 903 p_hwfn->dpi_count, 904 ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ? 905 "disabled" : "enabled"); 906 907 if (rc) { 908 DP_ERR(p_hwfn, 909 "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n", 910 p_hwfn->dpi_count, 911 p_hwfn->pf_params.rdma_pf_params.min_dpis); 912 return -EINVAL; 913 } 914 915 p_hwfn->dpi_start_offset = norm_regsize; 916 917 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */ 918 pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4); 919 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift); 920 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1); 921 922 return 0; 923 } 924 925 static int qed_hw_init_port(struct qed_hwfn *p_hwfn, 926 struct qed_ptt *p_ptt, int hw_mode) 927 { 928 return qed_init_run(p_hwfn, p_ptt, PHASE_PORT, 929 p_hwfn->port_id, hw_mode); 930 } 931 932 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn, 933 struct qed_ptt *p_ptt, 934 struct qed_tunn_start_params *p_tunn, 935 int hw_mode, 936 bool b_hw_start, 937 enum qed_int_mode int_mode, 938 bool allow_npar_tx_switch) 939 { 940 u8 rel_pf_id = p_hwfn->rel_pf_id; 941 int rc = 0; 942 943 if (p_hwfn->mcp_info) { 944 struct qed_mcp_function_info *p_info; 945 946 p_info = &p_hwfn->mcp_info->func_info; 947 if (p_info->bandwidth_min) 948 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min; 949 950 /* Update rate limit once we'll actually have a link */ 951 p_hwfn->qm_info.pf_rl = 100000; 952 } 953 954 qed_cxt_hw_init_pf(p_hwfn); 955 956 qed_int_igu_init_rt(p_hwfn); 957 958 /* Set VLAN in NIG if needed */ 959 if (hw_mode & BIT(MODE_MF_SD)) { 960 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n"); 961 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1); 962 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET, 963 p_hwfn->hw_info.ovlan); 964 } 965 966 /* Enable classification by MAC if needed */ 967 if (hw_mode & BIT(MODE_MF_SI)) { 968 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 969 "Configuring TAGMAC_CLS_TYPE\n"); 970 STORE_RT_REG(p_hwfn, 971 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1); 972 } 973 974 /* Protocl Configuration */ 975 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 976 (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0); 977 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 0); 978 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0); 979 980 /* Cleanup chip from previous driver if such remains exist */ 981 rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false); 982 if (rc) 983 return rc; 984 985 /* PF Init sequence */ 986 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode); 987 if (rc) 988 return rc; 989 990 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */ 991 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode); 992 if (rc) 993 return rc; 994 995 /* Pure runtime initializations - directly to the HW */ 996 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true); 997 998 rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt); 999 if (rc) 1000 return rc; 1001 1002 if (b_hw_start) { 1003 /* enable interrupts */ 1004 qed_int_igu_enable(p_hwfn, p_ptt, int_mode); 1005 1006 /* send function start command */ 1007 rc = qed_sp_pf_start(p_hwfn, p_tunn, p_hwfn->cdev->mf_mode, 1008 allow_npar_tx_switch); 1009 if (rc) 1010 DP_NOTICE(p_hwfn, "Function start ramrod failed\n"); 1011 } 1012 return rc; 1013 } 1014 1015 static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn, 1016 struct qed_ptt *p_ptt, 1017 u8 enable) 1018 { 1019 u32 delay_idx = 0, val, set_val = enable ? 1 : 0; 1020 1021 /* Change PF in PXP */ 1022 qed_wr(p_hwfn, p_ptt, 1023 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val); 1024 1025 /* wait until value is set - try for 1 second every 50us */ 1026 for (delay_idx = 0; delay_idx < 20000; delay_idx++) { 1027 val = qed_rd(p_hwfn, p_ptt, 1028 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1029 if (val == set_val) 1030 break; 1031 1032 usleep_range(50, 60); 1033 } 1034 1035 if (val != set_val) { 1036 DP_NOTICE(p_hwfn, 1037 "PFID_ENABLE_MASTER wasn't changed after a second\n"); 1038 return -EAGAIN; 1039 } 1040 1041 return 0; 1042 } 1043 1044 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn, 1045 struct qed_ptt *p_main_ptt) 1046 { 1047 /* Read shadow of current MFW mailbox */ 1048 qed_mcp_read_mb(p_hwfn, p_main_ptt); 1049 memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 1050 p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length); 1051 } 1052 1053 int qed_hw_init(struct qed_dev *cdev, 1054 struct qed_tunn_start_params *p_tunn, 1055 bool b_hw_start, 1056 enum qed_int_mode int_mode, 1057 bool allow_npar_tx_switch, 1058 const u8 *bin_fw_data) 1059 { 1060 u32 load_code, param; 1061 int rc, mfw_rc, i; 1062 1063 if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) { 1064 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n"); 1065 return -EINVAL; 1066 } 1067 1068 if (IS_PF(cdev)) { 1069 rc = qed_init_fw_data(cdev, bin_fw_data); 1070 if (rc) 1071 return rc; 1072 } 1073 1074 for_each_hwfn(cdev, i) { 1075 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1076 1077 if (IS_VF(cdev)) { 1078 p_hwfn->b_int_enabled = 1; 1079 continue; 1080 } 1081 1082 /* Enable DMAE in PXP */ 1083 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true); 1084 1085 qed_calc_hw_mode(p_hwfn); 1086 1087 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code); 1088 if (rc) { 1089 DP_NOTICE(p_hwfn, "Failed sending LOAD_REQ command\n"); 1090 return rc; 1091 } 1092 1093 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt); 1094 1095 DP_VERBOSE(p_hwfn, QED_MSG_SP, 1096 "Load request was sent. Resp:0x%x, Load code: 0x%x\n", 1097 rc, load_code); 1098 1099 p_hwfn->first_on_engine = (load_code == 1100 FW_MSG_CODE_DRV_LOAD_ENGINE); 1101 1102 switch (load_code) { 1103 case FW_MSG_CODE_DRV_LOAD_ENGINE: 1104 rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt, 1105 p_hwfn->hw_info.hw_mode); 1106 if (rc) 1107 break; 1108 /* Fall into */ 1109 case FW_MSG_CODE_DRV_LOAD_PORT: 1110 rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt, 1111 p_hwfn->hw_info.hw_mode); 1112 if (rc) 1113 break; 1114 1115 /* Fall into */ 1116 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 1117 rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt, 1118 p_tunn, p_hwfn->hw_info.hw_mode, 1119 b_hw_start, int_mode, 1120 allow_npar_tx_switch); 1121 break; 1122 default: 1123 rc = -EINVAL; 1124 break; 1125 } 1126 1127 if (rc) 1128 DP_NOTICE(p_hwfn, 1129 "init phase failed for loadcode 0x%x (rc %d)\n", 1130 load_code, rc); 1131 1132 /* ACK mfw regardless of success or failure of initialization */ 1133 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1134 DRV_MSG_CODE_LOAD_DONE, 1135 0, &load_code, ¶m); 1136 if (rc) 1137 return rc; 1138 if (mfw_rc) { 1139 DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n"); 1140 return mfw_rc; 1141 } 1142 1143 /* send DCBX attention request command */ 1144 DP_VERBOSE(p_hwfn, 1145 QED_MSG_DCB, 1146 "sending phony dcbx set command to trigger DCBx attention handling\n"); 1147 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1148 DRV_MSG_CODE_SET_DCBX, 1149 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT, 1150 &load_code, ¶m); 1151 if (mfw_rc) { 1152 DP_NOTICE(p_hwfn, 1153 "Failed to send DCBX attention request\n"); 1154 return mfw_rc; 1155 } 1156 1157 p_hwfn->hw_init_done = true; 1158 } 1159 1160 return 0; 1161 } 1162 1163 #define QED_HW_STOP_RETRY_LIMIT (10) 1164 static void qed_hw_timers_stop(struct qed_dev *cdev, 1165 struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1166 { 1167 int i; 1168 1169 /* close timers */ 1170 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0); 1171 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0); 1172 1173 for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) { 1174 if ((!qed_rd(p_hwfn, p_ptt, 1175 TM_REG_PF_SCAN_ACTIVE_CONN)) && 1176 (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK))) 1177 break; 1178 1179 /* Dependent on number of connection/tasks, possibly 1180 * 1ms sleep is required between polls 1181 */ 1182 usleep_range(1000, 2000); 1183 } 1184 1185 if (i < QED_HW_STOP_RETRY_LIMIT) 1186 return; 1187 1188 DP_NOTICE(p_hwfn, 1189 "Timers linear scans are not over [Connection %02x Tasks %02x]\n", 1190 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN), 1191 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)); 1192 } 1193 1194 void qed_hw_timers_stop_all(struct qed_dev *cdev) 1195 { 1196 int j; 1197 1198 for_each_hwfn(cdev, j) { 1199 struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 1200 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 1201 1202 qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 1203 } 1204 } 1205 1206 int qed_hw_stop(struct qed_dev *cdev) 1207 { 1208 int rc = 0, t_rc; 1209 int j; 1210 1211 for_each_hwfn(cdev, j) { 1212 struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 1213 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 1214 1215 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n"); 1216 1217 if (IS_VF(cdev)) { 1218 qed_vf_pf_int_cleanup(p_hwfn); 1219 continue; 1220 } 1221 1222 /* mark the hw as uninitialized... */ 1223 p_hwfn->hw_init_done = false; 1224 1225 rc = qed_sp_pf_stop(p_hwfn); 1226 if (rc) 1227 DP_NOTICE(p_hwfn, 1228 "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n"); 1229 1230 qed_wr(p_hwfn, p_ptt, 1231 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 1232 1233 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1234 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 1235 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 1236 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1237 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 1238 1239 qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 1240 1241 /* Disable Attention Generation */ 1242 qed_int_igu_disable_int(p_hwfn, p_ptt); 1243 1244 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0); 1245 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0); 1246 1247 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true); 1248 1249 /* Need to wait 1ms to guarantee SBs are cleared */ 1250 usleep_range(1000, 2000); 1251 } 1252 1253 if (IS_PF(cdev)) { 1254 /* Disable DMAE in PXP - in CMT, this should only be done for 1255 * first hw-function, and only after all transactions have 1256 * stopped for all active hw-functions. 1257 */ 1258 t_rc = qed_change_pci_hwfn(&cdev->hwfns[0], 1259 cdev->hwfns[0].p_main_ptt, false); 1260 if (t_rc != 0) 1261 rc = t_rc; 1262 } 1263 1264 return rc; 1265 } 1266 1267 void qed_hw_stop_fastpath(struct qed_dev *cdev) 1268 { 1269 int j; 1270 1271 for_each_hwfn(cdev, j) { 1272 struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 1273 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 1274 1275 if (IS_VF(cdev)) { 1276 qed_vf_pf_int_cleanup(p_hwfn); 1277 continue; 1278 } 1279 1280 DP_VERBOSE(p_hwfn, 1281 NETIF_MSG_IFDOWN, "Shutting down the fastpath\n"); 1282 1283 qed_wr(p_hwfn, p_ptt, 1284 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 1285 1286 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1287 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 1288 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 1289 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1290 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 1291 1292 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false); 1293 1294 /* Need to wait 1ms to guarantee SBs are cleared */ 1295 usleep_range(1000, 2000); 1296 } 1297 } 1298 1299 void qed_hw_start_fastpath(struct qed_hwfn *p_hwfn) 1300 { 1301 if (IS_VF(p_hwfn->cdev)) 1302 return; 1303 1304 /* Re-open incoming traffic */ 1305 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1306 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0); 1307 } 1308 1309 static int qed_reg_assert(struct qed_hwfn *p_hwfn, 1310 struct qed_ptt *p_ptt, u32 reg, bool expected) 1311 { 1312 u32 assert_val = qed_rd(p_hwfn, p_ptt, reg); 1313 1314 if (assert_val != expected) { 1315 DP_NOTICE(p_hwfn, "Value at address 0x%08x != 0x%08x\n", 1316 reg, expected); 1317 return -EINVAL; 1318 } 1319 1320 return 0; 1321 } 1322 1323 int qed_hw_reset(struct qed_dev *cdev) 1324 { 1325 int rc = 0; 1326 u32 unload_resp, unload_param; 1327 int i; 1328 1329 for_each_hwfn(cdev, i) { 1330 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1331 1332 if (IS_VF(cdev)) { 1333 rc = qed_vf_pf_reset(p_hwfn); 1334 if (rc) 1335 return rc; 1336 continue; 1337 } 1338 1339 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Resetting hw/fw\n"); 1340 1341 /* Check for incorrect states */ 1342 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt, 1343 QM_REG_USG_CNT_PF_TX, 0); 1344 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt, 1345 QM_REG_USG_CNT_PF_OTHER, 0); 1346 1347 /* Disable PF in HW blocks */ 1348 qed_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0); 1349 qed_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0); 1350 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1351 TCFC_REG_STRONG_ENABLE_PF, 0); 1352 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1353 CCFC_REG_STRONG_ENABLE_PF, 0); 1354 1355 /* Send unload command to MCP */ 1356 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1357 DRV_MSG_CODE_UNLOAD_REQ, 1358 DRV_MB_PARAM_UNLOAD_WOL_MCP, 1359 &unload_resp, &unload_param); 1360 if (rc) { 1361 DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_REQ failed\n"); 1362 unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE; 1363 } 1364 1365 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1366 DRV_MSG_CODE_UNLOAD_DONE, 1367 0, &unload_resp, &unload_param); 1368 if (rc) { 1369 DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_DONE failed\n"); 1370 return rc; 1371 } 1372 } 1373 1374 return rc; 1375 } 1376 1377 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */ 1378 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn) 1379 { 1380 qed_ptt_pool_free(p_hwfn); 1381 kfree(p_hwfn->hw_info.p_igu_info); 1382 } 1383 1384 /* Setup bar access */ 1385 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn) 1386 { 1387 /* clear indirect access */ 1388 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0); 1389 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0); 1390 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0); 1391 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0); 1392 1393 /* Clean Previous errors if such exist */ 1394 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1395 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id); 1396 1397 /* enable internal target-read */ 1398 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1399 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 1400 } 1401 1402 static void get_function_id(struct qed_hwfn *p_hwfn) 1403 { 1404 /* ME Register */ 1405 p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn, 1406 PXP_PF_ME_OPAQUE_ADDR); 1407 1408 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); 1409 1410 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf; 1411 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 1412 PXP_CONCRETE_FID_PFID); 1413 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 1414 PXP_CONCRETE_FID_PORT); 1415 1416 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, 1417 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n", 1418 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid); 1419 } 1420 1421 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn) 1422 { 1423 u32 *feat_num = p_hwfn->hw_info.feat_num; 1424 int num_features = 1; 1425 1426 if (IS_ENABLED(CONFIG_QED_RDMA) && 1427 p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) { 1428 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide 1429 * the status blocks equally between L2 / RoCE but with 1430 * consideration as to how many l2 queues / cnqs we have. 1431 */ 1432 num_features++; 1433 1434 feat_num[QED_RDMA_CNQ] = 1435 min_t(u32, RESC_NUM(p_hwfn, QED_SB) / num_features, 1436 RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM)); 1437 } 1438 1439 feat_num[QED_PF_L2_QUE] = min_t(u32, RESC_NUM(p_hwfn, QED_SB) / 1440 num_features, 1441 RESC_NUM(p_hwfn, QED_L2_QUEUE)); 1442 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, 1443 "#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n", 1444 feat_num[QED_PF_L2_QUE], RESC_NUM(p_hwfn, QED_SB), 1445 num_features); 1446 } 1447 1448 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn) 1449 { 1450 u8 enabled_func_idx = p_hwfn->enabled_func_idx; 1451 u32 *resc_start = p_hwfn->hw_info.resc_start; 1452 u8 num_funcs = p_hwfn->num_funcs_on_engine; 1453 u32 *resc_num = p_hwfn->hw_info.resc_num; 1454 struct qed_sb_cnt_info sb_cnt_info; 1455 int i, max_vf_vlan_filters; 1456 1457 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info)); 1458 1459 #ifdef CONFIG_QED_SRIOV 1460 max_vf_vlan_filters = QED_ETH_MAX_VF_NUM_VLAN_FILTERS; 1461 #else 1462 max_vf_vlan_filters = 0; 1463 #endif 1464 1465 qed_int_get_num_sbs(p_hwfn, &sb_cnt_info); 1466 1467 resc_num[QED_SB] = min_t(u32, 1468 (MAX_SB_PER_PATH_BB / num_funcs), 1469 sb_cnt_info.sb_cnt); 1470 resc_num[QED_L2_QUEUE] = MAX_NUM_L2_QUEUES_BB / num_funcs; 1471 resc_num[QED_VPORT] = MAX_NUM_VPORTS_BB / num_funcs; 1472 resc_num[QED_RSS_ENG] = ETH_RSS_ENGINE_NUM_BB / num_funcs; 1473 resc_num[QED_PQ] = MAX_QM_TX_QUEUES_BB / num_funcs; 1474 resc_num[QED_RL] = min_t(u32, 64, resc_num[QED_VPORT]); 1475 resc_num[QED_MAC] = ETH_NUM_MAC_FILTERS / num_funcs; 1476 resc_num[QED_VLAN] = (ETH_NUM_VLAN_FILTERS - 1 /*For vlan0*/) / 1477 num_funcs; 1478 resc_num[QED_ILT] = PXP_NUM_ILT_RECORDS_BB / num_funcs; 1479 resc_num[QED_LL2_QUEUE] = MAX_NUM_LL2_RX_QUEUES / num_funcs; 1480 resc_num[QED_RDMA_CNQ_RAM] = NUM_OF_CMDQS_CQS / num_funcs; 1481 resc_num[QED_RDMA_STATS_QUEUE] = RDMA_NUM_STATISTIC_COUNTERS_BB / 1482 num_funcs; 1483 1484 for (i = 0; i < QED_MAX_RESC; i++) 1485 resc_start[i] = resc_num[i] * enabled_func_idx; 1486 1487 /* Sanity for ILT */ 1488 if (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB) { 1489 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n", 1490 RESC_START(p_hwfn, QED_ILT), 1491 RESC_END(p_hwfn, QED_ILT) - 1); 1492 return -EINVAL; 1493 } 1494 1495 qed_hw_set_feat(p_hwfn); 1496 1497 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, 1498 "The numbers for each resource are:\n" 1499 "SB = %d start = %d\n" 1500 "L2_QUEUE = %d start = %d\n" 1501 "VPORT = %d start = %d\n" 1502 "PQ = %d start = %d\n" 1503 "RL = %d start = %d\n" 1504 "MAC = %d start = %d\n" 1505 "VLAN = %d start = %d\n" 1506 "ILT = %d start = %d\n" 1507 "LL2_QUEUE = %d start = %d\n", 1508 p_hwfn->hw_info.resc_num[QED_SB], 1509 p_hwfn->hw_info.resc_start[QED_SB], 1510 p_hwfn->hw_info.resc_num[QED_L2_QUEUE], 1511 p_hwfn->hw_info.resc_start[QED_L2_QUEUE], 1512 p_hwfn->hw_info.resc_num[QED_VPORT], 1513 p_hwfn->hw_info.resc_start[QED_VPORT], 1514 p_hwfn->hw_info.resc_num[QED_PQ], 1515 p_hwfn->hw_info.resc_start[QED_PQ], 1516 p_hwfn->hw_info.resc_num[QED_RL], 1517 p_hwfn->hw_info.resc_start[QED_RL], 1518 p_hwfn->hw_info.resc_num[QED_MAC], 1519 p_hwfn->hw_info.resc_start[QED_MAC], 1520 p_hwfn->hw_info.resc_num[QED_VLAN], 1521 p_hwfn->hw_info.resc_start[QED_VLAN], 1522 p_hwfn->hw_info.resc_num[QED_ILT], 1523 p_hwfn->hw_info.resc_start[QED_ILT], 1524 RESC_NUM(p_hwfn, QED_LL2_QUEUE), 1525 RESC_START(p_hwfn, QED_LL2_QUEUE)); 1526 1527 return 0; 1528 } 1529 1530 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1531 { 1532 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg; 1533 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities; 1534 struct qed_mcp_link_params *link; 1535 1536 /* Read global nvm_cfg address */ 1537 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 1538 1539 /* Verify MCP has initialized it */ 1540 if (!nvm_cfg_addr) { 1541 DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 1542 return -EINVAL; 1543 } 1544 1545 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */ 1546 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 1547 1548 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1549 offsetof(struct nvm_cfg1, glob) + 1550 offsetof(struct nvm_cfg1_glob, core_cfg); 1551 1552 core_cfg = qed_rd(p_hwfn, p_ptt, addr); 1553 1554 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >> 1555 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) { 1556 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G: 1557 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G; 1558 break; 1559 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G: 1560 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G; 1561 break; 1562 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G: 1563 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G; 1564 break; 1565 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F: 1566 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F; 1567 break; 1568 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E: 1569 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E; 1570 break; 1571 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G: 1572 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G; 1573 break; 1574 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G: 1575 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G; 1576 break; 1577 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G: 1578 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G; 1579 break; 1580 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G: 1581 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G; 1582 break; 1583 default: 1584 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg); 1585 break; 1586 } 1587 1588 /* Read default link configuration */ 1589 link = &p_hwfn->mcp_info->link_input; 1590 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1591 offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 1592 link_temp = qed_rd(p_hwfn, p_ptt, 1593 port_cfg_addr + 1594 offsetof(struct nvm_cfg1_port, speed_cap_mask)); 1595 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK; 1596 link->speed.advertised_speeds = link_temp; 1597 1598 link_temp = link->speed.advertised_speeds; 1599 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp; 1600 1601 link_temp = qed_rd(p_hwfn, p_ptt, 1602 port_cfg_addr + 1603 offsetof(struct nvm_cfg1_port, link_settings)); 1604 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >> 1605 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) { 1606 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG: 1607 link->speed.autoneg = true; 1608 break; 1609 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G: 1610 link->speed.forced_speed = 1000; 1611 break; 1612 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G: 1613 link->speed.forced_speed = 10000; 1614 break; 1615 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G: 1616 link->speed.forced_speed = 25000; 1617 break; 1618 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G: 1619 link->speed.forced_speed = 40000; 1620 break; 1621 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G: 1622 link->speed.forced_speed = 50000; 1623 break; 1624 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G: 1625 link->speed.forced_speed = 100000; 1626 break; 1627 default: 1628 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp); 1629 } 1630 1631 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK; 1632 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET; 1633 link->pause.autoneg = !!(link_temp & 1634 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG); 1635 link->pause.forced_rx = !!(link_temp & 1636 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX); 1637 link->pause.forced_tx = !!(link_temp & 1638 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX); 1639 link->loopback_mode = 0; 1640 1641 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1642 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n", 1643 link->speed.forced_speed, link->speed.advertised_speeds, 1644 link->speed.autoneg, link->pause.autoneg); 1645 1646 /* Read Multi-function information from shmem */ 1647 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1648 offsetof(struct nvm_cfg1, glob) + 1649 offsetof(struct nvm_cfg1_glob, generic_cont0); 1650 1651 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr); 1652 1653 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >> 1654 NVM_CFG1_GLOB_MF_MODE_OFFSET; 1655 1656 switch (mf_mode) { 1657 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED: 1658 p_hwfn->cdev->mf_mode = QED_MF_OVLAN; 1659 break; 1660 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0: 1661 p_hwfn->cdev->mf_mode = QED_MF_NPAR; 1662 break; 1663 case NVM_CFG1_GLOB_MF_MODE_DEFAULT: 1664 p_hwfn->cdev->mf_mode = QED_MF_DEFAULT; 1665 break; 1666 } 1667 DP_INFO(p_hwfn, "Multi function mode is %08x\n", 1668 p_hwfn->cdev->mf_mode); 1669 1670 /* Read Multi-function information from shmem */ 1671 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1672 offsetof(struct nvm_cfg1, glob) + 1673 offsetof(struct nvm_cfg1_glob, device_capabilities); 1674 1675 device_capabilities = qed_rd(p_hwfn, p_ptt, addr); 1676 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET) 1677 __set_bit(QED_DEV_CAP_ETH, 1678 &p_hwfn->hw_info.device_capabilities); 1679 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI) 1680 __set_bit(QED_DEV_CAP_ISCSI, 1681 &p_hwfn->hw_info.device_capabilities); 1682 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE) 1683 __set_bit(QED_DEV_CAP_ROCE, 1684 &p_hwfn->hw_info.device_capabilities); 1685 1686 return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt); 1687 } 1688 1689 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1690 { 1691 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id; 1692 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask; 1693 1694 num_funcs = MAX_NUM_PFS_BB; 1695 1696 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values 1697 * in the other bits are selected. 1698 * Bits 1-15 are for functions 1-15, respectively, and their value is 1699 * '0' only for enabled functions (function 0 always exists and 1700 * enabled). 1701 * In case of CMT, only the "even" functions are enabled, and thus the 1702 * number of functions for both hwfns is learnt from the same bits. 1703 */ 1704 reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE); 1705 1706 if (reg_function_hide & 0x1) { 1707 if (QED_PATH_ID(p_hwfn) && p_hwfn->cdev->num_hwfns == 1) { 1708 num_funcs = 0; 1709 eng_mask = 0xaaaa; 1710 } else { 1711 num_funcs = 1; 1712 eng_mask = 0x5554; 1713 } 1714 1715 /* Get the number of the enabled functions on the engine */ 1716 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask; 1717 while (tmp) { 1718 if (tmp & 0x1) 1719 num_funcs++; 1720 tmp >>= 0x1; 1721 } 1722 1723 /* Get the PF index within the enabled functions */ 1724 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1; 1725 tmp = reg_function_hide & eng_mask & low_pfs_mask; 1726 while (tmp) { 1727 if (tmp & 0x1) 1728 enabled_func_idx--; 1729 tmp >>= 0x1; 1730 } 1731 } 1732 1733 p_hwfn->num_funcs_on_engine = num_funcs; 1734 p_hwfn->enabled_func_idx = enabled_func_idx; 1735 1736 DP_VERBOSE(p_hwfn, 1737 NETIF_MSG_PROBE, 1738 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n", 1739 p_hwfn->rel_pf_id, 1740 p_hwfn->abs_pf_id, 1741 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine); 1742 } 1743 1744 static int 1745 qed_get_hw_info(struct qed_hwfn *p_hwfn, 1746 struct qed_ptt *p_ptt, 1747 enum qed_pci_personality personality) 1748 { 1749 u32 port_mode; 1750 int rc; 1751 1752 /* Since all information is common, only first hwfns should do this */ 1753 if (IS_LEAD_HWFN(p_hwfn)) { 1754 rc = qed_iov_hw_info(p_hwfn); 1755 if (rc) 1756 return rc; 1757 } 1758 1759 /* Read the port mode */ 1760 port_mode = qed_rd(p_hwfn, p_ptt, 1761 CNIG_REG_NW_PORT_MODE_BB_B0); 1762 1763 if (port_mode < 3) { 1764 p_hwfn->cdev->num_ports_in_engines = 1; 1765 } else if (port_mode <= 5) { 1766 p_hwfn->cdev->num_ports_in_engines = 2; 1767 } else { 1768 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n", 1769 p_hwfn->cdev->num_ports_in_engines); 1770 1771 /* Default num_ports_in_engines to something */ 1772 p_hwfn->cdev->num_ports_in_engines = 1; 1773 } 1774 1775 qed_hw_get_nvm_info(p_hwfn, p_ptt); 1776 1777 rc = qed_int_igu_read_cam(p_hwfn, p_ptt); 1778 if (rc) 1779 return rc; 1780 1781 if (qed_mcp_is_init(p_hwfn)) 1782 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr, 1783 p_hwfn->mcp_info->func_info.mac); 1784 else 1785 eth_random_addr(p_hwfn->hw_info.hw_mac_addr); 1786 1787 if (qed_mcp_is_init(p_hwfn)) { 1788 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET) 1789 p_hwfn->hw_info.ovlan = 1790 p_hwfn->mcp_info->func_info.ovlan; 1791 1792 qed_mcp_cmd_port_init(p_hwfn, p_ptt); 1793 } 1794 1795 if (qed_mcp_is_init(p_hwfn)) { 1796 enum qed_pci_personality protocol; 1797 1798 protocol = p_hwfn->mcp_info->func_info.protocol; 1799 p_hwfn->hw_info.personality = protocol; 1800 } 1801 1802 qed_get_num_funcs(p_hwfn, p_ptt); 1803 1804 return qed_hw_get_resc(p_hwfn); 1805 } 1806 1807 static int qed_get_dev_info(struct qed_dev *cdev) 1808 { 1809 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 1810 u32 tmp; 1811 1812 /* Read Vendor Id / Device Id */ 1813 pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id); 1814 pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id); 1815 1816 cdev->chip_num = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, 1817 MISCS_REG_CHIP_NUM); 1818 cdev->chip_rev = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, 1819 MISCS_REG_CHIP_REV); 1820 MASK_FIELD(CHIP_REV, cdev->chip_rev); 1821 1822 cdev->type = QED_DEV_TYPE_BB; 1823 /* Learn number of HW-functions */ 1824 tmp = qed_rd(p_hwfn, p_hwfn->p_main_ptt, 1825 MISCS_REG_CMT_ENABLED_FOR_PAIR); 1826 1827 if (tmp & (1 << p_hwfn->rel_pf_id)) { 1828 DP_NOTICE(cdev->hwfns, "device in CMT mode\n"); 1829 cdev->num_hwfns = 2; 1830 } else { 1831 cdev->num_hwfns = 1; 1832 } 1833 1834 cdev->chip_bond_id = qed_rd(p_hwfn, p_hwfn->p_main_ptt, 1835 MISCS_REG_CHIP_TEST_REG) >> 4; 1836 MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id); 1837 cdev->chip_metal = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, 1838 MISCS_REG_CHIP_METAL); 1839 MASK_FIELD(CHIP_METAL, cdev->chip_metal); 1840 1841 DP_INFO(cdev->hwfns, 1842 "Chip details - Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n", 1843 cdev->chip_num, cdev->chip_rev, 1844 cdev->chip_bond_id, cdev->chip_metal); 1845 1846 if (QED_IS_BB(cdev) && CHIP_REV_IS_A0(cdev)) { 1847 DP_NOTICE(cdev->hwfns, 1848 "The chip type/rev (BB A0) is not supported!\n"); 1849 return -EINVAL; 1850 } 1851 1852 return 0; 1853 } 1854 1855 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn, 1856 void __iomem *p_regview, 1857 void __iomem *p_doorbells, 1858 enum qed_pci_personality personality) 1859 { 1860 int rc = 0; 1861 1862 /* Split PCI bars evenly between hwfns */ 1863 p_hwfn->regview = p_regview; 1864 p_hwfn->doorbells = p_doorbells; 1865 1866 if (IS_VF(p_hwfn->cdev)) 1867 return qed_vf_hw_prepare(p_hwfn); 1868 1869 /* Validate that chip access is feasible */ 1870 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) { 1871 DP_ERR(p_hwfn, 1872 "Reading the ME register returns all Fs; Preventing further chip access\n"); 1873 return -EINVAL; 1874 } 1875 1876 get_function_id(p_hwfn); 1877 1878 /* Allocate PTT pool */ 1879 rc = qed_ptt_pool_alloc(p_hwfn); 1880 if (rc) 1881 goto err0; 1882 1883 /* Allocate the main PTT */ 1884 p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN); 1885 1886 /* First hwfn learns basic information, e.g., number of hwfns */ 1887 if (!p_hwfn->my_id) { 1888 rc = qed_get_dev_info(p_hwfn->cdev); 1889 if (rc) 1890 goto err1; 1891 } 1892 1893 qed_hw_hwfn_prepare(p_hwfn); 1894 1895 /* Initialize MCP structure */ 1896 rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt); 1897 if (rc) { 1898 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n"); 1899 goto err1; 1900 } 1901 1902 /* Read the device configuration information from the HW and SHMEM */ 1903 rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality); 1904 if (rc) { 1905 DP_NOTICE(p_hwfn, "Failed to get HW information\n"); 1906 goto err2; 1907 } 1908 1909 /* Allocate the init RT array and initialize the init-ops engine */ 1910 rc = qed_init_alloc(p_hwfn); 1911 if (rc) 1912 goto err2; 1913 1914 return rc; 1915 err2: 1916 if (IS_LEAD_HWFN(p_hwfn)) 1917 qed_iov_free_hw_info(p_hwfn->cdev); 1918 qed_mcp_free(p_hwfn); 1919 err1: 1920 qed_hw_hwfn_free(p_hwfn); 1921 err0: 1922 return rc; 1923 } 1924 1925 int qed_hw_prepare(struct qed_dev *cdev, 1926 int personality) 1927 { 1928 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 1929 int rc; 1930 1931 /* Store the precompiled init data ptrs */ 1932 if (IS_PF(cdev)) 1933 qed_init_iro_array(cdev); 1934 1935 /* Initialize the first hwfn - will learn number of hwfns */ 1936 rc = qed_hw_prepare_single(p_hwfn, 1937 cdev->regview, 1938 cdev->doorbells, personality); 1939 if (rc) 1940 return rc; 1941 1942 personality = p_hwfn->hw_info.personality; 1943 1944 /* Initialize the rest of the hwfns */ 1945 if (cdev->num_hwfns > 1) { 1946 void __iomem *p_regview, *p_doorbell; 1947 u8 __iomem *addr; 1948 1949 /* adjust bar offset for second engine */ 1950 addr = cdev->regview + qed_hw_bar_size(p_hwfn, BAR_ID_0) / 2; 1951 p_regview = addr; 1952 1953 /* adjust doorbell bar offset for second engine */ 1954 addr = cdev->doorbells + qed_hw_bar_size(p_hwfn, BAR_ID_1) / 2; 1955 p_doorbell = addr; 1956 1957 /* prepare second hw function */ 1958 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview, 1959 p_doorbell, personality); 1960 1961 /* in case of error, need to free the previously 1962 * initiliazed hwfn 0. 1963 */ 1964 if (rc) { 1965 if (IS_PF(cdev)) { 1966 qed_init_free(p_hwfn); 1967 qed_mcp_free(p_hwfn); 1968 qed_hw_hwfn_free(p_hwfn); 1969 } 1970 } 1971 } 1972 1973 return rc; 1974 } 1975 1976 void qed_hw_remove(struct qed_dev *cdev) 1977 { 1978 int i; 1979 1980 for_each_hwfn(cdev, i) { 1981 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1982 1983 if (IS_VF(cdev)) { 1984 qed_vf_pf_release(p_hwfn); 1985 continue; 1986 } 1987 1988 qed_init_free(p_hwfn); 1989 qed_hw_hwfn_free(p_hwfn); 1990 qed_mcp_free(p_hwfn); 1991 } 1992 1993 qed_iov_free_hw_info(cdev); 1994 } 1995 1996 static void qed_chain_free_next_ptr(struct qed_dev *cdev, 1997 struct qed_chain *p_chain) 1998 { 1999 void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL; 2000 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0; 2001 struct qed_chain_next *p_next; 2002 u32 size, i; 2003 2004 if (!p_virt) 2005 return; 2006 2007 size = p_chain->elem_size * p_chain->usable_per_page; 2008 2009 for (i = 0; i < p_chain->page_cnt; i++) { 2010 if (!p_virt) 2011 break; 2012 2013 p_next = (struct qed_chain_next *)((u8 *)p_virt + size); 2014 p_virt_next = p_next->next_virt; 2015 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys); 2016 2017 dma_free_coherent(&cdev->pdev->dev, 2018 QED_CHAIN_PAGE_SIZE, p_virt, p_phys); 2019 2020 p_virt = p_virt_next; 2021 p_phys = p_phys_next; 2022 } 2023 } 2024 2025 static void qed_chain_free_single(struct qed_dev *cdev, 2026 struct qed_chain *p_chain) 2027 { 2028 if (!p_chain->p_virt_addr) 2029 return; 2030 2031 dma_free_coherent(&cdev->pdev->dev, 2032 QED_CHAIN_PAGE_SIZE, 2033 p_chain->p_virt_addr, p_chain->p_phys_addr); 2034 } 2035 2036 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain) 2037 { 2038 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl; 2039 u32 page_cnt = p_chain->page_cnt, i, pbl_size; 2040 u8 *p_pbl_virt = p_chain->pbl.p_virt_table; 2041 2042 if (!pp_virt_addr_tbl) 2043 return; 2044 2045 if (!p_chain->pbl.p_virt_table) 2046 goto out; 2047 2048 for (i = 0; i < page_cnt; i++) { 2049 if (!pp_virt_addr_tbl[i]) 2050 break; 2051 2052 dma_free_coherent(&cdev->pdev->dev, 2053 QED_CHAIN_PAGE_SIZE, 2054 pp_virt_addr_tbl[i], 2055 *(dma_addr_t *)p_pbl_virt); 2056 2057 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE; 2058 } 2059 2060 pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; 2061 dma_free_coherent(&cdev->pdev->dev, 2062 pbl_size, 2063 p_chain->pbl.p_virt_table, p_chain->pbl.p_phys_table); 2064 out: 2065 vfree(p_chain->pbl.pp_virt_addr_tbl); 2066 } 2067 2068 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain) 2069 { 2070 switch (p_chain->mode) { 2071 case QED_CHAIN_MODE_NEXT_PTR: 2072 qed_chain_free_next_ptr(cdev, p_chain); 2073 break; 2074 case QED_CHAIN_MODE_SINGLE: 2075 qed_chain_free_single(cdev, p_chain); 2076 break; 2077 case QED_CHAIN_MODE_PBL: 2078 qed_chain_free_pbl(cdev, p_chain); 2079 break; 2080 } 2081 } 2082 2083 static int 2084 qed_chain_alloc_sanity_check(struct qed_dev *cdev, 2085 enum qed_chain_cnt_type cnt_type, 2086 size_t elem_size, u32 page_cnt) 2087 { 2088 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt; 2089 2090 /* The actual chain size can be larger than the maximal possible value 2091 * after rounding up the requested elements number to pages, and after 2092 * taking into acount the unusuable elements (next-ptr elements). 2093 * The size of a "u16" chain can be (U16_MAX + 1) since the chain 2094 * size/capacity fields are of a u32 type. 2095 */ 2096 if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 && 2097 chain_size > 0x10000) || 2098 (cnt_type == QED_CHAIN_CNT_TYPE_U32 && 2099 chain_size > 0x100000000ULL)) { 2100 DP_NOTICE(cdev, 2101 "The actual chain size (0x%llx) is larger than the maximal possible value\n", 2102 chain_size); 2103 return -EINVAL; 2104 } 2105 2106 return 0; 2107 } 2108 2109 static int 2110 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain) 2111 { 2112 void *p_virt = NULL, *p_virt_prev = NULL; 2113 dma_addr_t p_phys = 0; 2114 u32 i; 2115 2116 for (i = 0; i < p_chain->page_cnt; i++) { 2117 p_virt = dma_alloc_coherent(&cdev->pdev->dev, 2118 QED_CHAIN_PAGE_SIZE, 2119 &p_phys, GFP_KERNEL); 2120 if (!p_virt) 2121 return -ENOMEM; 2122 2123 if (i == 0) { 2124 qed_chain_init_mem(p_chain, p_virt, p_phys); 2125 qed_chain_reset(p_chain); 2126 } else { 2127 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, 2128 p_virt, p_phys); 2129 } 2130 2131 p_virt_prev = p_virt; 2132 } 2133 /* Last page's next element should point to the beginning of the 2134 * chain. 2135 */ 2136 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, 2137 p_chain->p_virt_addr, 2138 p_chain->p_phys_addr); 2139 2140 return 0; 2141 } 2142 2143 static int 2144 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain) 2145 { 2146 dma_addr_t p_phys = 0; 2147 void *p_virt = NULL; 2148 2149 p_virt = dma_alloc_coherent(&cdev->pdev->dev, 2150 QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL); 2151 if (!p_virt) 2152 return -ENOMEM; 2153 2154 qed_chain_init_mem(p_chain, p_virt, p_phys); 2155 qed_chain_reset(p_chain); 2156 2157 return 0; 2158 } 2159 2160 static int qed_chain_alloc_pbl(struct qed_dev *cdev, struct qed_chain *p_chain) 2161 { 2162 u32 page_cnt = p_chain->page_cnt, size, i; 2163 dma_addr_t p_phys = 0, p_pbl_phys = 0; 2164 void **pp_virt_addr_tbl = NULL; 2165 u8 *p_pbl_virt = NULL; 2166 void *p_virt = NULL; 2167 2168 size = page_cnt * sizeof(*pp_virt_addr_tbl); 2169 pp_virt_addr_tbl = vzalloc(size); 2170 if (!pp_virt_addr_tbl) 2171 return -ENOMEM; 2172 2173 /* The allocation of the PBL table is done with its full size, since it 2174 * is expected to be successive. 2175 * qed_chain_init_pbl_mem() is called even in a case of an allocation 2176 * failure, since pp_virt_addr_tbl was previously allocated, and it 2177 * should be saved to allow its freeing during the error flow. 2178 */ 2179 size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; 2180 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev, 2181 size, &p_pbl_phys, GFP_KERNEL); 2182 qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys, 2183 pp_virt_addr_tbl); 2184 if (!p_pbl_virt) 2185 return -ENOMEM; 2186 2187 for (i = 0; i < page_cnt; i++) { 2188 p_virt = dma_alloc_coherent(&cdev->pdev->dev, 2189 QED_CHAIN_PAGE_SIZE, 2190 &p_phys, GFP_KERNEL); 2191 if (!p_virt) 2192 return -ENOMEM; 2193 2194 if (i == 0) { 2195 qed_chain_init_mem(p_chain, p_virt, p_phys); 2196 qed_chain_reset(p_chain); 2197 } 2198 2199 /* Fill the PBL table with the physical address of the page */ 2200 *(dma_addr_t *)p_pbl_virt = p_phys; 2201 /* Keep the virtual address of the page */ 2202 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt; 2203 2204 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE; 2205 } 2206 2207 return 0; 2208 } 2209 2210 int qed_chain_alloc(struct qed_dev *cdev, 2211 enum qed_chain_use_mode intended_use, 2212 enum qed_chain_mode mode, 2213 enum qed_chain_cnt_type cnt_type, 2214 u32 num_elems, size_t elem_size, struct qed_chain *p_chain) 2215 { 2216 u32 page_cnt; 2217 int rc = 0; 2218 2219 if (mode == QED_CHAIN_MODE_SINGLE) 2220 page_cnt = 1; 2221 else 2222 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode); 2223 2224 rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt); 2225 if (rc) { 2226 DP_NOTICE(cdev, 2227 "Cannot allocate a chain with the given arguments:\n"); 2228 DP_NOTICE(cdev, 2229 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n", 2230 intended_use, mode, cnt_type, num_elems, elem_size); 2231 return rc; 2232 } 2233 2234 qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use, 2235 mode, cnt_type); 2236 2237 switch (mode) { 2238 case QED_CHAIN_MODE_NEXT_PTR: 2239 rc = qed_chain_alloc_next_ptr(cdev, p_chain); 2240 break; 2241 case QED_CHAIN_MODE_SINGLE: 2242 rc = qed_chain_alloc_single(cdev, p_chain); 2243 break; 2244 case QED_CHAIN_MODE_PBL: 2245 rc = qed_chain_alloc_pbl(cdev, p_chain); 2246 break; 2247 } 2248 if (rc) 2249 goto nomem; 2250 2251 return 0; 2252 2253 nomem: 2254 qed_chain_free(cdev, p_chain); 2255 return rc; 2256 } 2257 2258 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id) 2259 { 2260 if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) { 2261 u16 min, max; 2262 2263 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE); 2264 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE); 2265 DP_NOTICE(p_hwfn, 2266 "l2_queue id [%d] is not valid, available indices [%d - %d]\n", 2267 src_id, min, max); 2268 2269 return -EINVAL; 2270 } 2271 2272 *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id; 2273 2274 return 0; 2275 } 2276 2277 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id) 2278 { 2279 if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) { 2280 u8 min, max; 2281 2282 min = (u8)RESC_START(p_hwfn, QED_VPORT); 2283 max = min + RESC_NUM(p_hwfn, QED_VPORT); 2284 DP_NOTICE(p_hwfn, 2285 "vport id [%d] is not valid, available indices [%d - %d]\n", 2286 src_id, min, max); 2287 2288 return -EINVAL; 2289 } 2290 2291 *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id; 2292 2293 return 0; 2294 } 2295 2296 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id) 2297 { 2298 if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) { 2299 u8 min, max; 2300 2301 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG); 2302 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG); 2303 DP_NOTICE(p_hwfn, 2304 "rss_eng id [%d] is not valid, available indices [%d - %d]\n", 2305 src_id, min, max); 2306 2307 return -EINVAL; 2308 } 2309 2310 *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id; 2311 2312 return 0; 2313 } 2314 2315 static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low, 2316 u8 *p_filter) 2317 { 2318 *p_high = p_filter[1] | (p_filter[0] << 8); 2319 *p_low = p_filter[5] | (p_filter[4] << 8) | 2320 (p_filter[3] << 16) | (p_filter[2] << 24); 2321 } 2322 2323 int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn, 2324 struct qed_ptt *p_ptt, u8 *p_filter) 2325 { 2326 u32 high = 0, low = 0, en; 2327 int i; 2328 2329 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 2330 return 0; 2331 2332 qed_llh_mac_to_filter(&high, &low, p_filter); 2333 2334 /* Find a free entry and utilize it */ 2335 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 2336 en = qed_rd(p_hwfn, p_ptt, 2337 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)); 2338 if (en) 2339 continue; 2340 qed_wr(p_hwfn, p_ptt, 2341 NIG_REG_LLH_FUNC_FILTER_VALUE + 2342 2 * i * sizeof(u32), low); 2343 qed_wr(p_hwfn, p_ptt, 2344 NIG_REG_LLH_FUNC_FILTER_VALUE + 2345 (2 * i + 1) * sizeof(u32), high); 2346 qed_wr(p_hwfn, p_ptt, 2347 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0); 2348 qed_wr(p_hwfn, p_ptt, 2349 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 2350 i * sizeof(u32), 0); 2351 qed_wr(p_hwfn, p_ptt, 2352 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1); 2353 break; 2354 } 2355 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) { 2356 DP_NOTICE(p_hwfn, 2357 "Failed to find an empty LLH filter to utilize\n"); 2358 return -EINVAL; 2359 } 2360 2361 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 2362 "mac: %pM is added at %d\n", 2363 p_filter, i); 2364 2365 return 0; 2366 } 2367 2368 void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn, 2369 struct qed_ptt *p_ptt, u8 *p_filter) 2370 { 2371 u32 high = 0, low = 0; 2372 int i; 2373 2374 if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 2375 return; 2376 2377 qed_llh_mac_to_filter(&high, &low, p_filter); 2378 2379 /* Find the entry and clean it */ 2380 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 2381 if (qed_rd(p_hwfn, p_ptt, 2382 NIG_REG_LLH_FUNC_FILTER_VALUE + 2383 2 * i * sizeof(u32)) != low) 2384 continue; 2385 if (qed_rd(p_hwfn, p_ptt, 2386 NIG_REG_LLH_FUNC_FILTER_VALUE + 2387 (2 * i + 1) * sizeof(u32)) != high) 2388 continue; 2389 2390 qed_wr(p_hwfn, p_ptt, 2391 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0); 2392 qed_wr(p_hwfn, p_ptt, 2393 NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0); 2394 qed_wr(p_hwfn, p_ptt, 2395 NIG_REG_LLH_FUNC_FILTER_VALUE + 2396 (2 * i + 1) * sizeof(u32), 0); 2397 2398 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 2399 "mac: %pM is removed from %d\n", 2400 p_filter, i); 2401 break; 2402 } 2403 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) 2404 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n"); 2405 } 2406 2407 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2408 u32 hw_addr, void *p_eth_qzone, 2409 size_t eth_qzone_size, u8 timeset) 2410 { 2411 struct coalescing_timeset *p_coal_timeset; 2412 2413 if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) { 2414 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n"); 2415 return -EINVAL; 2416 } 2417 2418 p_coal_timeset = p_eth_qzone; 2419 memset(p_coal_timeset, 0, eth_qzone_size); 2420 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset); 2421 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1); 2422 qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size); 2423 2424 return 0; 2425 } 2426 2427 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2428 u16 coalesce, u8 qid, u16 sb_id) 2429 { 2430 struct ustorm_eth_queue_zone eth_qzone; 2431 u8 timeset, timer_res; 2432 u16 fw_qid = 0; 2433 u32 address; 2434 int rc; 2435 2436 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 2437 if (coalesce <= 0x7F) { 2438 timer_res = 0; 2439 } else if (coalesce <= 0xFF) { 2440 timer_res = 1; 2441 } else if (coalesce <= 0x1FF) { 2442 timer_res = 2; 2443 } else { 2444 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 2445 return -EINVAL; 2446 } 2447 timeset = (u8)(coalesce >> timer_res); 2448 2449 rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid); 2450 if (rc) 2451 return rc; 2452 2453 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false); 2454 if (rc) 2455 goto out; 2456 2457 address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid); 2458 2459 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 2460 sizeof(struct ustorm_eth_queue_zone), timeset); 2461 if (rc) 2462 goto out; 2463 2464 p_hwfn->cdev->rx_coalesce_usecs = coalesce; 2465 out: 2466 return rc; 2467 } 2468 2469 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2470 u16 coalesce, u8 qid, u16 sb_id) 2471 { 2472 struct xstorm_eth_queue_zone eth_qzone; 2473 u8 timeset, timer_res; 2474 u16 fw_qid = 0; 2475 u32 address; 2476 int rc; 2477 2478 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 2479 if (coalesce <= 0x7F) { 2480 timer_res = 0; 2481 } else if (coalesce <= 0xFF) { 2482 timer_res = 1; 2483 } else if (coalesce <= 0x1FF) { 2484 timer_res = 2; 2485 } else { 2486 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 2487 return -EINVAL; 2488 } 2489 timeset = (u8)(coalesce >> timer_res); 2490 2491 rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid); 2492 if (rc) 2493 return rc; 2494 2495 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true); 2496 if (rc) 2497 goto out; 2498 2499 address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid); 2500 2501 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 2502 sizeof(struct xstorm_eth_queue_zone), timeset); 2503 if (rc) 2504 goto out; 2505 2506 p_hwfn->cdev->tx_coalesce_usecs = coalesce; 2507 out: 2508 return rc; 2509 } 2510 2511 /* Calculate final WFQ values for all vports and configure them. 2512 * After this configuration each vport will have 2513 * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT) 2514 */ 2515 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 2516 struct qed_ptt *p_ptt, 2517 u32 min_pf_rate) 2518 { 2519 struct init_qm_vport_params *vport_params; 2520 int i; 2521 2522 vport_params = p_hwfn->qm_info.qm_vport_params; 2523 2524 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 2525 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 2526 2527 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) / 2528 min_pf_rate; 2529 qed_init_vport_wfq(p_hwfn, p_ptt, 2530 vport_params[i].first_tx_pq_id, 2531 vport_params[i].vport_wfq); 2532 } 2533 } 2534 2535 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn, 2536 u32 min_pf_rate) 2537 2538 { 2539 int i; 2540 2541 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) 2542 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1; 2543 } 2544 2545 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 2546 struct qed_ptt *p_ptt, 2547 u32 min_pf_rate) 2548 { 2549 struct init_qm_vport_params *vport_params; 2550 int i; 2551 2552 vport_params = p_hwfn->qm_info.qm_vport_params; 2553 2554 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 2555 qed_init_wfq_default_param(p_hwfn, min_pf_rate); 2556 qed_init_vport_wfq(p_hwfn, p_ptt, 2557 vport_params[i].first_tx_pq_id, 2558 vport_params[i].vport_wfq); 2559 } 2560 } 2561 2562 /* This function performs several validations for WFQ 2563 * configuration and required min rate for a given vport 2564 * 1. req_rate must be greater than one percent of min_pf_rate. 2565 * 2. req_rate should not cause other vports [not configured for WFQ explicitly] 2566 * rates to get less than one percent of min_pf_rate. 2567 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate. 2568 */ 2569 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn, 2570 u16 vport_id, u32 req_rate, u32 min_pf_rate) 2571 { 2572 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0; 2573 int non_requested_count = 0, req_count = 0, i, num_vports; 2574 2575 num_vports = p_hwfn->qm_info.num_vports; 2576 2577 /* Accounting for the vports which are configured for WFQ explicitly */ 2578 for (i = 0; i < num_vports; i++) { 2579 u32 tmp_speed; 2580 2581 if ((i != vport_id) && 2582 p_hwfn->qm_info.wfq_data[i].configured) { 2583 req_count++; 2584 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 2585 total_req_min_rate += tmp_speed; 2586 } 2587 } 2588 2589 /* Include current vport data as well */ 2590 req_count++; 2591 total_req_min_rate += req_rate; 2592 non_requested_count = num_vports - req_count; 2593 2594 if (req_rate < min_pf_rate / QED_WFQ_UNIT) { 2595 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2596 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 2597 vport_id, req_rate, min_pf_rate); 2598 return -EINVAL; 2599 } 2600 2601 if (num_vports > QED_WFQ_UNIT) { 2602 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2603 "Number of vports is greater than %d\n", 2604 QED_WFQ_UNIT); 2605 return -EINVAL; 2606 } 2607 2608 if (total_req_min_rate > min_pf_rate) { 2609 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2610 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n", 2611 total_req_min_rate, min_pf_rate); 2612 return -EINVAL; 2613 } 2614 2615 total_left_rate = min_pf_rate - total_req_min_rate; 2616 2617 left_rate_per_vp = total_left_rate / non_requested_count; 2618 if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) { 2619 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2620 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 2621 left_rate_per_vp, min_pf_rate); 2622 return -EINVAL; 2623 } 2624 2625 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate; 2626 p_hwfn->qm_info.wfq_data[vport_id].configured = true; 2627 2628 for (i = 0; i < num_vports; i++) { 2629 if (p_hwfn->qm_info.wfq_data[i].configured) 2630 continue; 2631 2632 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp; 2633 } 2634 2635 return 0; 2636 } 2637 2638 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn, 2639 struct qed_ptt *p_ptt, u16 vp_id, u32 rate) 2640 { 2641 struct qed_mcp_link_state *p_link; 2642 int rc = 0; 2643 2644 p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output; 2645 2646 if (!p_link->min_pf_rate) { 2647 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate; 2648 p_hwfn->qm_info.wfq_data[vp_id].configured = true; 2649 return rc; 2650 } 2651 2652 rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate); 2653 2654 if (!rc) 2655 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, 2656 p_link->min_pf_rate); 2657 else 2658 DP_NOTICE(p_hwfn, 2659 "Validation failed while configuring min rate\n"); 2660 2661 return rc; 2662 } 2663 2664 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn, 2665 struct qed_ptt *p_ptt, 2666 u32 min_pf_rate) 2667 { 2668 bool use_wfq = false; 2669 int rc = 0; 2670 u16 i; 2671 2672 /* Validate all pre configured vports for wfq */ 2673 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 2674 u32 rate; 2675 2676 if (!p_hwfn->qm_info.wfq_data[i].configured) 2677 continue; 2678 2679 rate = p_hwfn->qm_info.wfq_data[i].min_speed; 2680 use_wfq = true; 2681 2682 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate); 2683 if (rc) { 2684 DP_NOTICE(p_hwfn, 2685 "WFQ validation failed while configuring min rate\n"); 2686 break; 2687 } 2688 } 2689 2690 if (!rc && use_wfq) 2691 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 2692 else 2693 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 2694 2695 return rc; 2696 } 2697 2698 /* Main API for qed clients to configure vport min rate. 2699 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)] 2700 * rate - Speed in Mbps needs to be assigned to a given vport. 2701 */ 2702 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate) 2703 { 2704 int i, rc = -EINVAL; 2705 2706 /* Currently not supported; Might change in future */ 2707 if (cdev->num_hwfns > 1) { 2708 DP_NOTICE(cdev, 2709 "WFQ configuration is not supported for this device\n"); 2710 return rc; 2711 } 2712 2713 for_each_hwfn(cdev, i) { 2714 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2715 struct qed_ptt *p_ptt; 2716 2717 p_ptt = qed_ptt_acquire(p_hwfn); 2718 if (!p_ptt) 2719 return -EBUSY; 2720 2721 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate); 2722 2723 if (rc) { 2724 qed_ptt_release(p_hwfn, p_ptt); 2725 return rc; 2726 } 2727 2728 qed_ptt_release(p_hwfn, p_ptt); 2729 } 2730 2731 return rc; 2732 } 2733 2734 /* API to configure WFQ from mcp link change */ 2735 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate) 2736 { 2737 int i; 2738 2739 if (cdev->num_hwfns > 1) { 2740 DP_VERBOSE(cdev, 2741 NETIF_MSG_LINK, 2742 "WFQ configuration is not supported for this device\n"); 2743 return; 2744 } 2745 2746 for_each_hwfn(cdev, i) { 2747 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2748 2749 __qed_configure_vp_wfq_on_link_change(p_hwfn, 2750 p_hwfn->p_dpc_ptt, 2751 min_pf_rate); 2752 } 2753 } 2754 2755 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn, 2756 struct qed_ptt *p_ptt, 2757 struct qed_mcp_link_state *p_link, 2758 u8 max_bw) 2759 { 2760 int rc = 0; 2761 2762 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw; 2763 2764 if (!p_link->line_speed && (max_bw != 100)) 2765 return rc; 2766 2767 p_link->speed = (p_link->line_speed * max_bw) / 100; 2768 p_hwfn->qm_info.pf_rl = p_link->speed; 2769 2770 /* Since the limiter also affects Tx-switched traffic, we don't want it 2771 * to limit such traffic in case there's no actual limit. 2772 * In that case, set limit to imaginary high boundary. 2773 */ 2774 if (max_bw == 100) 2775 p_hwfn->qm_info.pf_rl = 100000; 2776 2777 rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, 2778 p_hwfn->qm_info.pf_rl); 2779 2780 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2781 "Configured MAX bandwidth to be %08x Mb/sec\n", 2782 p_link->speed); 2783 2784 return rc; 2785 } 2786 2787 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */ 2788 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw) 2789 { 2790 int i, rc = -EINVAL; 2791 2792 if (max_bw < 1 || max_bw > 100) { 2793 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n"); 2794 return rc; 2795 } 2796 2797 for_each_hwfn(cdev, i) { 2798 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2799 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 2800 struct qed_mcp_link_state *p_link; 2801 struct qed_ptt *p_ptt; 2802 2803 p_link = &p_lead->mcp_info->link_output; 2804 2805 p_ptt = qed_ptt_acquire(p_hwfn); 2806 if (!p_ptt) 2807 return -EBUSY; 2808 2809 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, 2810 p_link, max_bw); 2811 2812 qed_ptt_release(p_hwfn, p_ptt); 2813 2814 if (rc) 2815 break; 2816 } 2817 2818 return rc; 2819 } 2820 2821 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn, 2822 struct qed_ptt *p_ptt, 2823 struct qed_mcp_link_state *p_link, 2824 u8 min_bw) 2825 { 2826 int rc = 0; 2827 2828 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw; 2829 p_hwfn->qm_info.pf_wfq = min_bw; 2830 2831 if (!p_link->line_speed) 2832 return rc; 2833 2834 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100; 2835 2836 rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw); 2837 2838 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2839 "Configured MIN bandwidth to be %d Mb/sec\n", 2840 p_link->min_pf_rate); 2841 2842 return rc; 2843 } 2844 2845 /* Main API to configure PF min bandwidth where bw range is [1-100] */ 2846 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw) 2847 { 2848 int i, rc = -EINVAL; 2849 2850 if (min_bw < 1 || min_bw > 100) { 2851 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n"); 2852 return rc; 2853 } 2854 2855 for_each_hwfn(cdev, i) { 2856 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2857 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 2858 struct qed_mcp_link_state *p_link; 2859 struct qed_ptt *p_ptt; 2860 2861 p_link = &p_lead->mcp_info->link_output; 2862 2863 p_ptt = qed_ptt_acquire(p_hwfn); 2864 if (!p_ptt) 2865 return -EBUSY; 2866 2867 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, 2868 p_link, min_bw); 2869 if (rc) { 2870 qed_ptt_release(p_hwfn, p_ptt); 2871 return rc; 2872 } 2873 2874 if (p_link->min_pf_rate) { 2875 u32 min_rate = p_link->min_pf_rate; 2876 2877 rc = __qed_configure_vp_wfq_on_link_change(p_hwfn, 2878 p_ptt, 2879 min_rate); 2880 } 2881 2882 qed_ptt_release(p_hwfn, p_ptt); 2883 } 2884 2885 return rc; 2886 } 2887 2888 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2889 { 2890 struct qed_mcp_link_state *p_link; 2891 2892 p_link = &p_hwfn->mcp_info->link_output; 2893 2894 if (p_link->min_pf_rate) 2895 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, 2896 p_link->min_pf_rate); 2897 2898 memset(p_hwfn->qm_info.wfq_data, 0, 2899 sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports); 2900 } 2901