1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015 QLogic Corporation 3 * 4 * This software is available under the terms of the GNU General Public License 5 * (GPL) Version 2, available from the file COPYING in the main directory of 6 * this source tree. 7 */ 8 9 #include <linux/types.h> 10 #include <asm/byteorder.h> 11 #include <linux/io.h> 12 #include <linux/delay.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/errno.h> 15 #include <linux/kernel.h> 16 #include <linux/mutex.h> 17 #include <linux/pci.h> 18 #include <linux/slab.h> 19 #include <linux/string.h> 20 #include <linux/vmalloc.h> 21 #include <linux/etherdevice.h> 22 #include <linux/qed/qed_chain.h> 23 #include <linux/qed/qed_if.h> 24 #include "qed.h" 25 #include "qed_cxt.h" 26 #include "qed_dcbx.h" 27 #include "qed_dev_api.h" 28 #include "qed_hsi.h" 29 #include "qed_hw.h" 30 #include "qed_init_ops.h" 31 #include "qed_int.h" 32 #include "qed_mcp.h" 33 #include "qed_reg_addr.h" 34 #include "qed_sp.h" 35 #include "qed_sriov.h" 36 #include "qed_vf.h" 37 38 static spinlock_t qm_lock; 39 static bool qm_lock_init = false; 40 41 /* API common to all protocols */ 42 enum BAR_ID { 43 BAR_ID_0, /* used for GRC */ 44 BAR_ID_1 /* Used for doorbells */ 45 }; 46 47 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, 48 enum BAR_ID bar_id) 49 { 50 u32 bar_reg = (bar_id == BAR_ID_0 ? 51 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE); 52 u32 val; 53 54 if (IS_VF(p_hwfn->cdev)) 55 return 1 << 17; 56 57 val = qed_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg); 58 if (val) 59 return 1 << (val + 15); 60 61 /* Old MFW initialized above registered only conditionally */ 62 if (p_hwfn->cdev->num_hwfns > 1) { 63 DP_INFO(p_hwfn, 64 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n"); 65 return BAR_ID_0 ? 256 * 1024 : 512 * 1024; 66 } else { 67 DP_INFO(p_hwfn, 68 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n"); 69 return 512 * 1024; 70 } 71 } 72 73 void qed_init_dp(struct qed_dev *cdev, 74 u32 dp_module, u8 dp_level) 75 { 76 u32 i; 77 78 cdev->dp_level = dp_level; 79 cdev->dp_module = dp_module; 80 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 81 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 82 83 p_hwfn->dp_level = dp_level; 84 p_hwfn->dp_module = dp_module; 85 } 86 } 87 88 void qed_init_struct(struct qed_dev *cdev) 89 { 90 u8 i; 91 92 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 93 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 94 95 p_hwfn->cdev = cdev; 96 p_hwfn->my_id = i; 97 p_hwfn->b_active = false; 98 99 mutex_init(&p_hwfn->dmae_info.mutex); 100 } 101 102 /* hwfn 0 is always active */ 103 cdev->hwfns[0].b_active = true; 104 105 /* set the default cache alignment to 128 */ 106 cdev->cache_shift = 7; 107 } 108 109 static void qed_qm_info_free(struct qed_hwfn *p_hwfn) 110 { 111 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 112 113 kfree(qm_info->qm_pq_params); 114 qm_info->qm_pq_params = NULL; 115 kfree(qm_info->qm_vport_params); 116 qm_info->qm_vport_params = NULL; 117 kfree(qm_info->qm_port_params); 118 qm_info->qm_port_params = NULL; 119 kfree(qm_info->wfq_data); 120 qm_info->wfq_data = NULL; 121 } 122 123 void qed_resc_free(struct qed_dev *cdev) 124 { 125 int i; 126 127 if (IS_VF(cdev)) 128 return; 129 130 kfree(cdev->fw_data); 131 cdev->fw_data = NULL; 132 133 kfree(cdev->reset_stats); 134 135 for_each_hwfn(cdev, i) { 136 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 137 138 kfree(p_hwfn->p_tx_cids); 139 p_hwfn->p_tx_cids = NULL; 140 kfree(p_hwfn->p_rx_cids); 141 p_hwfn->p_rx_cids = NULL; 142 } 143 144 for_each_hwfn(cdev, i) { 145 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 146 147 qed_cxt_mngr_free(p_hwfn); 148 qed_qm_info_free(p_hwfn); 149 qed_spq_free(p_hwfn); 150 qed_eq_free(p_hwfn, p_hwfn->p_eq); 151 qed_consq_free(p_hwfn, p_hwfn->p_consq); 152 qed_int_free(p_hwfn); 153 qed_iov_free(p_hwfn); 154 qed_dmae_info_free(p_hwfn); 155 qed_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info); 156 } 157 } 158 159 static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable) 160 { 161 u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue = 0; 162 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 163 struct init_qm_port_params *p_qm_port; 164 bool init_rdma_offload_pq = false; 165 bool init_pure_ack_pq = false; 166 bool init_ooo_pq = false; 167 u16 num_pqs, multi_cos_tcs = 1; 168 u8 pf_wfq = qm_info->pf_wfq; 169 u32 pf_rl = qm_info->pf_rl; 170 u16 num_pf_rls = 0; 171 u16 num_vfs = 0; 172 173 #ifdef CONFIG_QED_SRIOV 174 if (p_hwfn->cdev->p_iov_info) 175 num_vfs = p_hwfn->cdev->p_iov_info->total_vfs; 176 #endif 177 memset(qm_info, 0, sizeof(*qm_info)); 178 179 num_pqs = multi_cos_tcs + num_vfs + 1; /* The '1' is for pure-LB */ 180 num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT); 181 182 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) { 183 num_pqs++; /* for RoCE queue */ 184 init_rdma_offload_pq = true; 185 /* we subtract num_vfs because each require a rate limiter, 186 * and one default rate limiter 187 */ 188 if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn) 189 num_pf_rls = RESC_NUM(p_hwfn, QED_RL) - num_vfs - 1; 190 191 num_pqs += num_pf_rls; 192 qm_info->num_pf_rls = (u8) num_pf_rls; 193 } 194 195 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 196 num_pqs += 2; /* for iSCSI pure-ACK / OOO queue */ 197 init_pure_ack_pq = true; 198 init_ooo_pq = true; 199 } 200 201 /* Sanity checking that setup requires legal number of resources */ 202 if (num_pqs > RESC_NUM(p_hwfn, QED_PQ)) { 203 DP_ERR(p_hwfn, 204 "Need too many Physical queues - 0x%04x when only %04x are available\n", 205 num_pqs, RESC_NUM(p_hwfn, QED_PQ)); 206 return -EINVAL; 207 } 208 209 /* PQs will be arranged as follows: First per-TC PQ then pure-LB quete. 210 */ 211 qm_info->qm_pq_params = kcalloc(num_pqs, 212 sizeof(struct init_qm_pq_params), 213 b_sleepable ? GFP_KERNEL : GFP_ATOMIC); 214 if (!qm_info->qm_pq_params) 215 goto alloc_err; 216 217 qm_info->qm_vport_params = kcalloc(num_vports, 218 sizeof(struct init_qm_vport_params), 219 b_sleepable ? GFP_KERNEL 220 : GFP_ATOMIC); 221 if (!qm_info->qm_vport_params) 222 goto alloc_err; 223 224 qm_info->qm_port_params = kcalloc(MAX_NUM_PORTS, 225 sizeof(struct init_qm_port_params), 226 b_sleepable ? GFP_KERNEL 227 : GFP_ATOMIC); 228 if (!qm_info->qm_port_params) 229 goto alloc_err; 230 231 qm_info->wfq_data = kcalloc(num_vports, sizeof(struct qed_wfq_data), 232 b_sleepable ? GFP_KERNEL : GFP_ATOMIC); 233 if (!qm_info->wfq_data) 234 goto alloc_err; 235 236 vport_id = (u8)RESC_START(p_hwfn, QED_VPORT); 237 238 /* First init rate limited queues */ 239 for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) { 240 qm_info->qm_pq_params[curr_queue].vport_id = vport_id++; 241 qm_info->qm_pq_params[curr_queue].tc_id = 242 p_hwfn->hw_info.non_offload_tc; 243 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 244 qm_info->qm_pq_params[curr_queue].rl_valid = 1; 245 } 246 247 /* First init per-TC PQs */ 248 for (i = 0; i < multi_cos_tcs; i++) { 249 struct init_qm_pq_params *params = 250 &qm_info->qm_pq_params[curr_queue++]; 251 252 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE || 253 p_hwfn->hw_info.personality == QED_PCI_ETH) { 254 params->vport_id = vport_id; 255 params->tc_id = p_hwfn->hw_info.non_offload_tc; 256 params->wrr_group = 1; 257 } else { 258 params->vport_id = vport_id; 259 params->tc_id = p_hwfn->hw_info.offload_tc; 260 params->wrr_group = 1; 261 } 262 } 263 264 /* Then init pure-LB PQ */ 265 qm_info->pure_lb_pq = curr_queue; 266 qm_info->qm_pq_params[curr_queue].vport_id = 267 (u8) RESC_START(p_hwfn, QED_VPORT); 268 qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC; 269 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 270 curr_queue++; 271 272 qm_info->offload_pq = 0; 273 if (init_rdma_offload_pq) { 274 qm_info->offload_pq = curr_queue; 275 qm_info->qm_pq_params[curr_queue].vport_id = vport_id; 276 qm_info->qm_pq_params[curr_queue].tc_id = 277 p_hwfn->hw_info.offload_tc; 278 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 279 curr_queue++; 280 } 281 282 if (init_pure_ack_pq) { 283 qm_info->pure_ack_pq = curr_queue; 284 qm_info->qm_pq_params[curr_queue].vport_id = vport_id; 285 qm_info->qm_pq_params[curr_queue].tc_id = 286 p_hwfn->hw_info.offload_tc; 287 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 288 curr_queue++; 289 } 290 291 if (init_ooo_pq) { 292 qm_info->ooo_pq = curr_queue; 293 qm_info->qm_pq_params[curr_queue].vport_id = vport_id; 294 qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC; 295 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 296 curr_queue++; 297 } 298 299 /* Then init per-VF PQs */ 300 vf_offset = curr_queue; 301 for (i = 0; i < num_vfs; i++) { 302 /* First vport is used by the PF */ 303 qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1; 304 qm_info->qm_pq_params[curr_queue].tc_id = 305 p_hwfn->hw_info.non_offload_tc; 306 qm_info->qm_pq_params[curr_queue].wrr_group = 1; 307 qm_info->qm_pq_params[curr_queue].rl_valid = 1; 308 curr_queue++; 309 } 310 311 qm_info->vf_queues_offset = vf_offset; 312 qm_info->num_pqs = num_pqs; 313 qm_info->num_vports = num_vports; 314 315 /* Initialize qm port parameters */ 316 num_ports = p_hwfn->cdev->num_ports_in_engines; 317 for (i = 0; i < num_ports; i++) { 318 p_qm_port = &qm_info->qm_port_params[i]; 319 p_qm_port->active = 1; 320 if (num_ports == 4) 321 p_qm_port->active_phys_tcs = 0x7; 322 else 323 p_qm_port->active_phys_tcs = 0x9f; 324 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports; 325 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports; 326 } 327 328 qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS; 329 330 qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ); 331 332 qm_info->num_vf_pqs = num_vfs; 333 qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT); 334 335 for (i = 0; i < qm_info->num_vports; i++) 336 qm_info->qm_vport_params[i].vport_wfq = 1; 337 338 qm_info->vport_rl_en = 1; 339 qm_info->vport_wfq_en = 1; 340 qm_info->pf_rl = pf_rl; 341 qm_info->pf_wfq = pf_wfq; 342 343 return 0; 344 345 alloc_err: 346 DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n"); 347 qed_qm_info_free(p_hwfn); 348 return -ENOMEM; 349 } 350 351 /* This function reconfigures the QM pf on the fly. 352 * For this purpose we: 353 * 1. reconfigure the QM database 354 * 2. set new values to runtime arrat 355 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM 356 * 4. activate init tool in QM_PF stage 357 * 5. send an sdm_qm_cmd through rbc interface to release the QM 358 */ 359 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 360 { 361 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 362 bool b_rc; 363 int rc; 364 365 /* qm_info is allocated in qed_init_qm_info() which is already called 366 * from qed_resc_alloc() or previous call of qed_qm_reconf(). 367 * The allocated size may change each init, so we free it before next 368 * allocation. 369 */ 370 qed_qm_info_free(p_hwfn); 371 372 /* initialize qed's qm data structure */ 373 rc = qed_init_qm_info(p_hwfn, false); 374 if (rc) 375 return rc; 376 377 /* stop PF's qm queues */ 378 spin_lock_bh(&qm_lock); 379 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true, 380 qm_info->start_pq, qm_info->num_pqs); 381 spin_unlock_bh(&qm_lock); 382 if (!b_rc) 383 return -EINVAL; 384 385 /* clear the QM_PF runtime phase leftovers from previous init */ 386 qed_init_clear_rt_data(p_hwfn); 387 388 /* prepare QM portion of runtime array */ 389 qed_qm_init_pf(p_hwfn); 390 391 /* activate init tool on runtime array */ 392 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id, 393 p_hwfn->hw_info.hw_mode); 394 if (rc) 395 return rc; 396 397 /* start PF's qm queues */ 398 spin_lock_bh(&qm_lock); 399 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true, 400 qm_info->start_pq, qm_info->num_pqs); 401 spin_unlock_bh(&qm_lock); 402 if (!b_rc) 403 return -EINVAL; 404 405 return 0; 406 } 407 408 int qed_resc_alloc(struct qed_dev *cdev) 409 { 410 struct qed_consq *p_consq; 411 struct qed_eq *p_eq; 412 int i, rc = 0; 413 414 if (IS_VF(cdev)) 415 return rc; 416 417 cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL); 418 if (!cdev->fw_data) 419 return -ENOMEM; 420 421 /* Allocate Memory for the Queue->CID mapping */ 422 for_each_hwfn(cdev, i) { 423 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 424 int tx_size = sizeof(struct qed_hw_cid_data) * 425 RESC_NUM(p_hwfn, QED_L2_QUEUE); 426 int rx_size = sizeof(struct qed_hw_cid_data) * 427 RESC_NUM(p_hwfn, QED_L2_QUEUE); 428 429 p_hwfn->p_tx_cids = kzalloc(tx_size, GFP_KERNEL); 430 if (!p_hwfn->p_tx_cids) { 431 DP_NOTICE(p_hwfn, 432 "Failed to allocate memory for Tx Cids\n"); 433 goto alloc_no_mem; 434 } 435 436 p_hwfn->p_rx_cids = kzalloc(rx_size, GFP_KERNEL); 437 if (!p_hwfn->p_rx_cids) { 438 DP_NOTICE(p_hwfn, 439 "Failed to allocate memory for Rx Cids\n"); 440 goto alloc_no_mem; 441 } 442 } 443 444 for_each_hwfn(cdev, i) { 445 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 446 u32 n_eqes, num_cons; 447 448 /* First allocate the context manager structure */ 449 rc = qed_cxt_mngr_alloc(p_hwfn); 450 if (rc) 451 goto alloc_err; 452 453 /* Set the HW cid/tid numbers (in the contest manager) 454 * Must be done prior to any further computations. 455 */ 456 rc = qed_cxt_set_pf_params(p_hwfn); 457 if (rc) 458 goto alloc_err; 459 460 /* Prepare and process QM requirements */ 461 rc = qed_init_qm_info(p_hwfn, true); 462 if (rc) 463 goto alloc_err; 464 465 /* Compute the ILT client partition */ 466 rc = qed_cxt_cfg_ilt_compute(p_hwfn); 467 if (rc) 468 goto alloc_err; 469 470 /* CID map / ILT shadow table / T2 471 * The talbes sizes are determined by the computations above 472 */ 473 rc = qed_cxt_tables_alloc(p_hwfn); 474 if (rc) 475 goto alloc_err; 476 477 /* SPQ, must follow ILT because initializes SPQ context */ 478 rc = qed_spq_alloc(p_hwfn); 479 if (rc) 480 goto alloc_err; 481 482 /* SP status block allocation */ 483 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn, 484 RESERVED_PTT_DPC); 485 486 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt); 487 if (rc) 488 goto alloc_err; 489 490 rc = qed_iov_alloc(p_hwfn); 491 if (rc) 492 goto alloc_err; 493 494 /* EQ */ 495 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain); 496 if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) { 497 num_cons = qed_cxt_get_proto_cid_count(p_hwfn, 498 PROTOCOLID_ROCE, 499 0) * 2; 500 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB; 501 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 502 num_cons = 503 qed_cxt_get_proto_cid_count(p_hwfn, 504 PROTOCOLID_ISCSI, 0); 505 n_eqes += 2 * num_cons; 506 } 507 508 if (n_eqes > 0xFFFF) { 509 DP_ERR(p_hwfn, 510 "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n", 511 n_eqes, 0xFFFF); 512 goto alloc_err; 513 } 514 515 p_eq = qed_eq_alloc(p_hwfn, (u16) n_eqes); 516 if (!p_eq) 517 goto alloc_no_mem; 518 p_hwfn->p_eq = p_eq; 519 520 p_consq = qed_consq_alloc(p_hwfn); 521 if (!p_consq) 522 goto alloc_no_mem; 523 p_hwfn->p_consq = p_consq; 524 525 /* DMA info initialization */ 526 rc = qed_dmae_info_alloc(p_hwfn); 527 if (rc) { 528 DP_NOTICE(p_hwfn, 529 "Failed to allocate memory for dmae_info structure\n"); 530 goto alloc_err; 531 } 532 533 /* DCBX initialization */ 534 rc = qed_dcbx_info_alloc(p_hwfn); 535 if (rc) { 536 DP_NOTICE(p_hwfn, 537 "Failed to allocate memory for dcbx structure\n"); 538 goto alloc_err; 539 } 540 } 541 542 cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL); 543 if (!cdev->reset_stats) { 544 DP_NOTICE(cdev, "Failed to allocate reset statistics\n"); 545 rc = -ENOMEM; 546 goto alloc_err; 547 } 548 549 return 0; 550 551 alloc_no_mem: 552 rc = -ENOMEM; 553 alloc_err: 554 qed_resc_free(cdev); 555 return rc; 556 } 557 558 void qed_resc_setup(struct qed_dev *cdev) 559 { 560 int i; 561 562 if (IS_VF(cdev)) 563 return; 564 565 for_each_hwfn(cdev, i) { 566 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 567 568 qed_cxt_mngr_setup(p_hwfn); 569 qed_spq_setup(p_hwfn); 570 qed_eq_setup(p_hwfn, p_hwfn->p_eq); 571 qed_consq_setup(p_hwfn, p_hwfn->p_consq); 572 573 /* Read shadow of current MFW mailbox */ 574 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt); 575 memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 576 p_hwfn->mcp_info->mfw_mb_cur, 577 p_hwfn->mcp_info->mfw_mb_length); 578 579 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt); 580 581 qed_iov_setup(p_hwfn, p_hwfn->p_main_ptt); 582 } 583 } 584 585 #define FINAL_CLEANUP_POLL_CNT (100) 586 #define FINAL_CLEANUP_POLL_TIME (10) 587 int qed_final_cleanup(struct qed_hwfn *p_hwfn, 588 struct qed_ptt *p_ptt, u16 id, bool is_vf) 589 { 590 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT; 591 int rc = -EBUSY; 592 593 addr = GTT_BAR0_MAP_REG_USDM_RAM + 594 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id); 595 596 if (is_vf) 597 id += 0x10; 598 599 command |= X_FINAL_CLEANUP_AGG_INT << 600 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT; 601 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT; 602 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT; 603 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT; 604 605 /* Make sure notification is not set before initiating final cleanup */ 606 if (REG_RD(p_hwfn, addr)) { 607 DP_NOTICE( 608 p_hwfn, 609 "Unexpected; Found final cleanup notification before initiating final cleanup\n"); 610 REG_WR(p_hwfn, addr, 0); 611 } 612 613 DP_VERBOSE(p_hwfn, QED_MSG_IOV, 614 "Sending final cleanup for PFVF[%d] [Command %08x\n]", 615 id, command); 616 617 qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command); 618 619 /* Poll until completion */ 620 while (!REG_RD(p_hwfn, addr) && count--) 621 msleep(FINAL_CLEANUP_POLL_TIME); 622 623 if (REG_RD(p_hwfn, addr)) 624 rc = 0; 625 else 626 DP_NOTICE(p_hwfn, 627 "Failed to receive FW final cleanup notification\n"); 628 629 /* Cleanup afterwards */ 630 REG_WR(p_hwfn, addr, 0); 631 632 return rc; 633 } 634 635 static void qed_calc_hw_mode(struct qed_hwfn *p_hwfn) 636 { 637 int hw_mode = 0; 638 639 hw_mode = (1 << MODE_BB_B0); 640 641 switch (p_hwfn->cdev->num_ports_in_engines) { 642 case 1: 643 hw_mode |= 1 << MODE_PORTS_PER_ENG_1; 644 break; 645 case 2: 646 hw_mode |= 1 << MODE_PORTS_PER_ENG_2; 647 break; 648 case 4: 649 hw_mode |= 1 << MODE_PORTS_PER_ENG_4; 650 break; 651 default: 652 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n", 653 p_hwfn->cdev->num_ports_in_engines); 654 return; 655 } 656 657 switch (p_hwfn->cdev->mf_mode) { 658 case QED_MF_DEFAULT: 659 case QED_MF_NPAR: 660 hw_mode |= 1 << MODE_MF_SI; 661 break; 662 case QED_MF_OVLAN: 663 hw_mode |= 1 << MODE_MF_SD; 664 break; 665 default: 666 DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n"); 667 hw_mode |= 1 << MODE_MF_SI; 668 } 669 670 hw_mode |= 1 << MODE_ASIC; 671 672 if (p_hwfn->cdev->num_hwfns > 1) 673 hw_mode |= 1 << MODE_100G; 674 675 p_hwfn->hw_info.hw_mode = hw_mode; 676 677 DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP), 678 "Configuring function for hw_mode: 0x%08x\n", 679 p_hwfn->hw_info.hw_mode); 680 } 681 682 /* Init run time data for all PFs on an engine. */ 683 static void qed_init_cau_rt_data(struct qed_dev *cdev) 684 { 685 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET; 686 int i, sb_id; 687 688 for_each_hwfn(cdev, i) { 689 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 690 struct qed_igu_info *p_igu_info; 691 struct qed_igu_block *p_block; 692 struct cau_sb_entry sb_entry; 693 694 p_igu_info = p_hwfn->hw_info.p_igu_info; 695 696 for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev); 697 sb_id++) { 698 p_block = &p_igu_info->igu_map.igu_blocks[sb_id]; 699 if (!p_block->is_pf) 700 continue; 701 702 qed_init_cau_sb_entry(p_hwfn, &sb_entry, 703 p_block->function_id, 704 0, 0); 705 STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, 706 sb_entry); 707 } 708 } 709 } 710 711 static int qed_hw_init_common(struct qed_hwfn *p_hwfn, 712 struct qed_ptt *p_ptt, 713 int hw_mode) 714 { 715 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 716 struct qed_qm_common_rt_init_params params; 717 struct qed_dev *cdev = p_hwfn->cdev; 718 u16 num_pfs, pf_id; 719 u32 concrete_fid; 720 int rc = 0; 721 u8 vf_id; 722 723 qed_init_cau_rt_data(cdev); 724 725 /* Program GTT windows */ 726 qed_gtt_init(p_hwfn); 727 728 if (p_hwfn->mcp_info) { 729 if (p_hwfn->mcp_info->func_info.bandwidth_max) 730 qm_info->pf_rl_en = 1; 731 if (p_hwfn->mcp_info->func_info.bandwidth_min) 732 qm_info->pf_wfq_en = 1; 733 } 734 735 memset(¶ms, 0, sizeof(params)); 736 params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engines; 737 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port; 738 params.pf_rl_en = qm_info->pf_rl_en; 739 params.pf_wfq_en = qm_info->pf_wfq_en; 740 params.vport_rl_en = qm_info->vport_rl_en; 741 params.vport_wfq_en = qm_info->vport_wfq_en; 742 params.port_params = qm_info->qm_port_params; 743 744 qed_qm_common_rt_init(p_hwfn, ¶ms); 745 746 qed_cxt_hw_init_common(p_hwfn); 747 748 /* Close gate from NIG to BRB/Storm; By default they are open, but 749 * we close them to prevent NIG from passing data to reset blocks. 750 * Should have been done in the ENGINE phase, but init-tool lacks 751 * proper port-pretend capabilities. 752 */ 753 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0); 754 qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0); 755 qed_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1); 756 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0); 757 qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0); 758 qed_port_unpretend(p_hwfn, p_ptt); 759 760 rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode); 761 if (rc != 0) 762 return rc; 763 764 qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0); 765 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1); 766 767 if (QED_IS_BB(p_hwfn->cdev)) { 768 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev); 769 for (pf_id = 0; pf_id < num_pfs; pf_id++) { 770 qed_fid_pretend(p_hwfn, p_ptt, pf_id); 771 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 772 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 773 } 774 /* pretend to original PF */ 775 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 776 } 777 778 for (vf_id = 0; vf_id < MAX_NUM_VFS_BB; vf_id++) { 779 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id); 780 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid); 781 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1); 782 } 783 /* pretend to original PF */ 784 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 785 786 return rc; 787 } 788 789 static int qed_hw_init_port(struct qed_hwfn *p_hwfn, 790 struct qed_ptt *p_ptt, 791 int hw_mode) 792 { 793 int rc = 0; 794 795 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode); 796 if (rc != 0) 797 return rc; 798 799 if (hw_mode & (1 << MODE_MF_SI)) { 800 u8 pf_id = 0; 801 802 if (!qed_hw_init_first_eth(p_hwfn, p_ptt, &pf_id)) { 803 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 804 "PF[%08x] is first eth on engine\n", pf_id); 805 806 /* We should have configured BIT for ppfid, i.e., the 807 * relative function number in the port. But there's a 808 * bug in LLH in BB where the ppfid is actually engine 809 * based, so we need to take this into account. 810 */ 811 qed_wr(p_hwfn, p_ptt, 812 NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR, 1 << pf_id); 813 } 814 815 /* Take the protocol-based hit vector if there is a hit, 816 * otherwise take the other vector. 817 */ 818 qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_CLS_TYPE_DUALMODE, 0x2); 819 } 820 return rc; 821 } 822 823 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn, 824 struct qed_ptt *p_ptt, 825 struct qed_tunn_start_params *p_tunn, 826 int hw_mode, 827 bool b_hw_start, 828 enum qed_int_mode int_mode, 829 bool allow_npar_tx_switch) 830 { 831 u8 rel_pf_id = p_hwfn->rel_pf_id; 832 int rc = 0; 833 834 if (p_hwfn->mcp_info) { 835 struct qed_mcp_function_info *p_info; 836 837 p_info = &p_hwfn->mcp_info->func_info; 838 if (p_info->bandwidth_min) 839 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min; 840 841 /* Update rate limit once we'll actually have a link */ 842 p_hwfn->qm_info.pf_rl = 100000; 843 } 844 845 qed_cxt_hw_init_pf(p_hwfn); 846 847 qed_int_igu_init_rt(p_hwfn); 848 849 /* Set VLAN in NIG if needed */ 850 if (hw_mode & (1 << MODE_MF_SD)) { 851 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n"); 852 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1); 853 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET, 854 p_hwfn->hw_info.ovlan); 855 } 856 857 /* Enable classification by MAC if needed */ 858 if (hw_mode & (1 << MODE_MF_SI)) { 859 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 860 "Configuring TAGMAC_CLS_TYPE\n"); 861 STORE_RT_REG(p_hwfn, 862 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1); 863 } 864 865 /* Protocl Configuration */ 866 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 867 (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0); 868 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 0); 869 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0); 870 871 /* Cleanup chip from previous driver if such remains exist */ 872 rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false); 873 if (rc != 0) 874 return rc; 875 876 /* PF Init sequence */ 877 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode); 878 if (rc) 879 return rc; 880 881 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */ 882 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode); 883 if (rc) 884 return rc; 885 886 /* Pure runtime initializations - directly to the HW */ 887 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true); 888 889 if (hw_mode & (1 << MODE_MF_SI)) { 890 u8 pf_id = 0; 891 u32 val; 892 893 if (!qed_hw_init_first_eth(p_hwfn, p_ptt, &pf_id)) { 894 if (p_hwfn->rel_pf_id == pf_id) { 895 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 896 "PF[%d] is first ETH on engine\n", 897 pf_id); 898 val = 1; 899 } 900 qed_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, val); 901 } 902 } 903 904 if (b_hw_start) { 905 /* enable interrupts */ 906 qed_int_igu_enable(p_hwfn, p_ptt, int_mode); 907 908 /* send function start command */ 909 rc = qed_sp_pf_start(p_hwfn, p_tunn, p_hwfn->cdev->mf_mode, 910 allow_npar_tx_switch); 911 if (rc) 912 DP_NOTICE(p_hwfn, "Function start ramrod failed\n"); 913 } 914 return rc; 915 } 916 917 static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn, 918 struct qed_ptt *p_ptt, 919 u8 enable) 920 { 921 u32 delay_idx = 0, val, set_val = enable ? 1 : 0; 922 923 /* Change PF in PXP */ 924 qed_wr(p_hwfn, p_ptt, 925 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val); 926 927 /* wait until value is set - try for 1 second every 50us */ 928 for (delay_idx = 0; delay_idx < 20000; delay_idx++) { 929 val = qed_rd(p_hwfn, p_ptt, 930 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 931 if (val == set_val) 932 break; 933 934 usleep_range(50, 60); 935 } 936 937 if (val != set_val) { 938 DP_NOTICE(p_hwfn, 939 "PFID_ENABLE_MASTER wasn't changed after a second\n"); 940 return -EAGAIN; 941 } 942 943 return 0; 944 } 945 946 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn, 947 struct qed_ptt *p_main_ptt) 948 { 949 /* Read shadow of current MFW mailbox */ 950 qed_mcp_read_mb(p_hwfn, p_main_ptt); 951 memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 952 p_hwfn->mcp_info->mfw_mb_cur, 953 p_hwfn->mcp_info->mfw_mb_length); 954 } 955 956 int qed_hw_init(struct qed_dev *cdev, 957 struct qed_tunn_start_params *p_tunn, 958 bool b_hw_start, 959 enum qed_int_mode int_mode, 960 bool allow_npar_tx_switch, 961 const u8 *bin_fw_data) 962 { 963 u32 load_code, param; 964 int rc, mfw_rc, i; 965 966 if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) { 967 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n"); 968 return -EINVAL; 969 } 970 971 if (IS_PF(cdev)) { 972 rc = qed_init_fw_data(cdev, bin_fw_data); 973 if (rc != 0) 974 return rc; 975 } 976 977 for_each_hwfn(cdev, i) { 978 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 979 980 if (IS_VF(cdev)) { 981 p_hwfn->b_int_enabled = 1; 982 continue; 983 } 984 985 /* Enable DMAE in PXP */ 986 rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true); 987 988 qed_calc_hw_mode(p_hwfn); 989 990 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, 991 &load_code); 992 if (rc) { 993 DP_NOTICE(p_hwfn, "Failed sending LOAD_REQ command\n"); 994 return rc; 995 } 996 997 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt); 998 999 DP_VERBOSE(p_hwfn, QED_MSG_SP, 1000 "Load request was sent. Resp:0x%x, Load code: 0x%x\n", 1001 rc, load_code); 1002 1003 p_hwfn->first_on_engine = (load_code == 1004 FW_MSG_CODE_DRV_LOAD_ENGINE); 1005 1006 if (!qm_lock_init) { 1007 spin_lock_init(&qm_lock); 1008 qm_lock_init = true; 1009 } 1010 1011 switch (load_code) { 1012 case FW_MSG_CODE_DRV_LOAD_ENGINE: 1013 rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt, 1014 p_hwfn->hw_info.hw_mode); 1015 if (rc) 1016 break; 1017 /* Fall into */ 1018 case FW_MSG_CODE_DRV_LOAD_PORT: 1019 rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt, 1020 p_hwfn->hw_info.hw_mode); 1021 if (rc) 1022 break; 1023 1024 /* Fall into */ 1025 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 1026 rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt, 1027 p_tunn, p_hwfn->hw_info.hw_mode, 1028 b_hw_start, int_mode, 1029 allow_npar_tx_switch); 1030 break; 1031 default: 1032 rc = -EINVAL; 1033 break; 1034 } 1035 1036 if (rc) 1037 DP_NOTICE(p_hwfn, 1038 "init phase failed for loadcode 0x%x (rc %d)\n", 1039 load_code, rc); 1040 1041 /* ACK mfw regardless of success or failure of initialization */ 1042 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1043 DRV_MSG_CODE_LOAD_DONE, 1044 0, &load_code, ¶m); 1045 if (rc) 1046 return rc; 1047 if (mfw_rc) { 1048 DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n"); 1049 return mfw_rc; 1050 } 1051 1052 /* send DCBX attention request command */ 1053 DP_VERBOSE(p_hwfn, 1054 QED_MSG_DCB, 1055 "sending phony dcbx set command to trigger DCBx attention handling\n"); 1056 mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1057 DRV_MSG_CODE_SET_DCBX, 1058 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT, 1059 &load_code, ¶m); 1060 if (mfw_rc) { 1061 DP_NOTICE(p_hwfn, 1062 "Failed to send DCBX attention request\n"); 1063 return mfw_rc; 1064 } 1065 1066 p_hwfn->hw_init_done = true; 1067 } 1068 1069 return 0; 1070 } 1071 1072 #define QED_HW_STOP_RETRY_LIMIT (10) 1073 static inline void qed_hw_timers_stop(struct qed_dev *cdev, 1074 struct qed_hwfn *p_hwfn, 1075 struct qed_ptt *p_ptt) 1076 { 1077 int i; 1078 1079 /* close timers */ 1080 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0); 1081 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0); 1082 1083 for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) { 1084 if ((!qed_rd(p_hwfn, p_ptt, 1085 TM_REG_PF_SCAN_ACTIVE_CONN)) && 1086 (!qed_rd(p_hwfn, p_ptt, 1087 TM_REG_PF_SCAN_ACTIVE_TASK))) 1088 break; 1089 1090 /* Dependent on number of connection/tasks, possibly 1091 * 1ms sleep is required between polls 1092 */ 1093 usleep_range(1000, 2000); 1094 } 1095 1096 if (i < QED_HW_STOP_RETRY_LIMIT) 1097 return; 1098 1099 DP_NOTICE(p_hwfn, 1100 "Timers linear scans are not over [Connection %02x Tasks %02x]\n", 1101 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN), 1102 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)); 1103 } 1104 1105 void qed_hw_timers_stop_all(struct qed_dev *cdev) 1106 { 1107 int j; 1108 1109 for_each_hwfn(cdev, j) { 1110 struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 1111 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 1112 1113 qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 1114 } 1115 } 1116 1117 int qed_hw_stop(struct qed_dev *cdev) 1118 { 1119 int rc = 0, t_rc; 1120 int j; 1121 1122 for_each_hwfn(cdev, j) { 1123 struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 1124 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 1125 1126 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n"); 1127 1128 if (IS_VF(cdev)) { 1129 qed_vf_pf_int_cleanup(p_hwfn); 1130 continue; 1131 } 1132 1133 /* mark the hw as uninitialized... */ 1134 p_hwfn->hw_init_done = false; 1135 1136 rc = qed_sp_pf_stop(p_hwfn); 1137 if (rc) 1138 DP_NOTICE(p_hwfn, 1139 "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n"); 1140 1141 qed_wr(p_hwfn, p_ptt, 1142 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 1143 1144 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1145 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 1146 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 1147 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1148 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 1149 1150 qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 1151 1152 /* Disable Attention Generation */ 1153 qed_int_igu_disable_int(p_hwfn, p_ptt); 1154 1155 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0); 1156 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0); 1157 1158 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true); 1159 1160 /* Need to wait 1ms to guarantee SBs are cleared */ 1161 usleep_range(1000, 2000); 1162 } 1163 1164 if (IS_PF(cdev)) { 1165 /* Disable DMAE in PXP - in CMT, this should only be done for 1166 * first hw-function, and only after all transactions have 1167 * stopped for all active hw-functions. 1168 */ 1169 t_rc = qed_change_pci_hwfn(&cdev->hwfns[0], 1170 cdev->hwfns[0].p_main_ptt, false); 1171 if (t_rc != 0) 1172 rc = t_rc; 1173 } 1174 1175 return rc; 1176 } 1177 1178 void qed_hw_stop_fastpath(struct qed_dev *cdev) 1179 { 1180 int j; 1181 1182 for_each_hwfn(cdev, j) { 1183 struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 1184 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 1185 1186 if (IS_VF(cdev)) { 1187 qed_vf_pf_int_cleanup(p_hwfn); 1188 continue; 1189 } 1190 1191 DP_VERBOSE(p_hwfn, 1192 NETIF_MSG_IFDOWN, 1193 "Shutting down the fastpath\n"); 1194 1195 qed_wr(p_hwfn, p_ptt, 1196 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 1197 1198 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1199 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 1200 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 1201 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1202 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 1203 1204 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false); 1205 1206 /* Need to wait 1ms to guarantee SBs are cleared */ 1207 usleep_range(1000, 2000); 1208 } 1209 } 1210 1211 void qed_hw_start_fastpath(struct qed_hwfn *p_hwfn) 1212 { 1213 if (IS_VF(p_hwfn->cdev)) 1214 return; 1215 1216 /* Re-open incoming traffic */ 1217 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1218 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0); 1219 } 1220 1221 static int qed_reg_assert(struct qed_hwfn *hwfn, 1222 struct qed_ptt *ptt, u32 reg, 1223 bool expected) 1224 { 1225 u32 assert_val = qed_rd(hwfn, ptt, reg); 1226 1227 if (assert_val != expected) { 1228 DP_NOTICE(hwfn, "Value at address 0x%x != 0x%08x\n", 1229 reg, expected); 1230 return -EINVAL; 1231 } 1232 1233 return 0; 1234 } 1235 1236 int qed_hw_reset(struct qed_dev *cdev) 1237 { 1238 int rc = 0; 1239 u32 unload_resp, unload_param; 1240 int i; 1241 1242 for_each_hwfn(cdev, i) { 1243 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1244 1245 if (IS_VF(cdev)) { 1246 rc = qed_vf_pf_reset(p_hwfn); 1247 if (rc) 1248 return rc; 1249 continue; 1250 } 1251 1252 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Resetting hw/fw\n"); 1253 1254 /* Check for incorrect states */ 1255 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt, 1256 QM_REG_USG_CNT_PF_TX, 0); 1257 qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt, 1258 QM_REG_USG_CNT_PF_OTHER, 0); 1259 1260 /* Disable PF in HW blocks */ 1261 qed_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0); 1262 qed_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0); 1263 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1264 TCFC_REG_STRONG_ENABLE_PF, 0); 1265 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1266 CCFC_REG_STRONG_ENABLE_PF, 0); 1267 1268 /* Send unload command to MCP */ 1269 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1270 DRV_MSG_CODE_UNLOAD_REQ, 1271 DRV_MB_PARAM_UNLOAD_WOL_MCP, 1272 &unload_resp, &unload_param); 1273 if (rc) { 1274 DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_REQ failed\n"); 1275 unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE; 1276 } 1277 1278 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1279 DRV_MSG_CODE_UNLOAD_DONE, 1280 0, &unload_resp, &unload_param); 1281 if (rc) { 1282 DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_DONE failed\n"); 1283 return rc; 1284 } 1285 } 1286 1287 return rc; 1288 } 1289 1290 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */ 1291 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn) 1292 { 1293 qed_ptt_pool_free(p_hwfn); 1294 kfree(p_hwfn->hw_info.p_igu_info); 1295 } 1296 1297 /* Setup bar access */ 1298 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn) 1299 { 1300 /* clear indirect access */ 1301 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0); 1302 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0); 1303 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0); 1304 qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0); 1305 1306 /* Clean Previous errors if such exist */ 1307 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1308 PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1309 1 << p_hwfn->abs_pf_id); 1310 1311 /* enable internal target-read */ 1312 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1313 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 1314 } 1315 1316 static void get_function_id(struct qed_hwfn *p_hwfn) 1317 { 1318 /* ME Register */ 1319 p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR); 1320 1321 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); 1322 1323 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf; 1324 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 1325 PXP_CONCRETE_FID_PFID); 1326 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 1327 PXP_CONCRETE_FID_PORT); 1328 } 1329 1330 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn) 1331 { 1332 u32 *feat_num = p_hwfn->hw_info.feat_num; 1333 int num_features = 1; 1334 1335 feat_num[QED_PF_L2_QUE] = min_t(u32, RESC_NUM(p_hwfn, QED_SB) / 1336 num_features, 1337 RESC_NUM(p_hwfn, QED_L2_QUEUE)); 1338 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, 1339 "#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n", 1340 feat_num[QED_PF_L2_QUE], RESC_NUM(p_hwfn, QED_SB), 1341 num_features); 1342 } 1343 1344 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn) 1345 { 1346 u8 enabled_func_idx = p_hwfn->enabled_func_idx; 1347 u32 *resc_start = p_hwfn->hw_info.resc_start; 1348 u8 num_funcs = p_hwfn->num_funcs_on_engine; 1349 u32 *resc_num = p_hwfn->hw_info.resc_num; 1350 struct qed_sb_cnt_info sb_cnt_info; 1351 int i, max_vf_vlan_filters; 1352 1353 memset(&sb_cnt_info, 0, sizeof(sb_cnt_info)); 1354 1355 #ifdef CONFIG_QED_SRIOV 1356 max_vf_vlan_filters = QED_ETH_MAX_VF_NUM_VLAN_FILTERS; 1357 #else 1358 max_vf_vlan_filters = 0; 1359 #endif 1360 1361 qed_int_get_num_sbs(p_hwfn, &sb_cnt_info); 1362 1363 resc_num[QED_SB] = min_t(u32, 1364 (MAX_SB_PER_PATH_BB / num_funcs), 1365 sb_cnt_info.sb_cnt); 1366 resc_num[QED_L2_QUEUE] = MAX_NUM_L2_QUEUES_BB / num_funcs; 1367 resc_num[QED_VPORT] = MAX_NUM_VPORTS_BB / num_funcs; 1368 resc_num[QED_RSS_ENG] = ETH_RSS_ENGINE_NUM_BB / num_funcs; 1369 resc_num[QED_PQ] = MAX_QM_TX_QUEUES_BB / num_funcs; 1370 resc_num[QED_RL] = min_t(u32, 64, resc_num[QED_VPORT]); 1371 resc_num[QED_MAC] = ETH_NUM_MAC_FILTERS / num_funcs; 1372 resc_num[QED_VLAN] = (ETH_NUM_VLAN_FILTERS - 1 /*For vlan0*/) / 1373 num_funcs; 1374 resc_num[QED_ILT] = PXP_NUM_ILT_RECORDS_BB / num_funcs; 1375 1376 for (i = 0; i < QED_MAX_RESC; i++) 1377 resc_start[i] = resc_num[i] * enabled_func_idx; 1378 1379 /* Sanity for ILT */ 1380 if (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB) { 1381 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n", 1382 RESC_START(p_hwfn, QED_ILT), 1383 RESC_END(p_hwfn, QED_ILT) - 1); 1384 return -EINVAL; 1385 } 1386 1387 qed_hw_set_feat(p_hwfn); 1388 1389 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, 1390 "The numbers for each resource are:\n" 1391 "SB = %d start = %d\n" 1392 "L2_QUEUE = %d start = %d\n" 1393 "VPORT = %d start = %d\n" 1394 "PQ = %d start = %d\n" 1395 "RL = %d start = %d\n" 1396 "MAC = %d start = %d\n" 1397 "VLAN = %d start = %d\n" 1398 "ILT = %d start = %d\n", 1399 p_hwfn->hw_info.resc_num[QED_SB], 1400 p_hwfn->hw_info.resc_start[QED_SB], 1401 p_hwfn->hw_info.resc_num[QED_L2_QUEUE], 1402 p_hwfn->hw_info.resc_start[QED_L2_QUEUE], 1403 p_hwfn->hw_info.resc_num[QED_VPORT], 1404 p_hwfn->hw_info.resc_start[QED_VPORT], 1405 p_hwfn->hw_info.resc_num[QED_PQ], 1406 p_hwfn->hw_info.resc_start[QED_PQ], 1407 p_hwfn->hw_info.resc_num[QED_RL], 1408 p_hwfn->hw_info.resc_start[QED_RL], 1409 p_hwfn->hw_info.resc_num[QED_MAC], 1410 p_hwfn->hw_info.resc_start[QED_MAC], 1411 p_hwfn->hw_info.resc_num[QED_VLAN], 1412 p_hwfn->hw_info.resc_start[QED_VLAN], 1413 p_hwfn->hw_info.resc_num[QED_ILT], 1414 p_hwfn->hw_info.resc_start[QED_ILT]); 1415 1416 return 0; 1417 } 1418 1419 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, 1420 struct qed_ptt *p_ptt) 1421 { 1422 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg; 1423 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities; 1424 struct qed_mcp_link_params *link; 1425 1426 /* Read global nvm_cfg address */ 1427 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 1428 1429 /* Verify MCP has initialized it */ 1430 if (!nvm_cfg_addr) { 1431 DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 1432 return -EINVAL; 1433 } 1434 1435 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */ 1436 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 1437 1438 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1439 offsetof(struct nvm_cfg1, glob) + 1440 offsetof(struct nvm_cfg1_glob, core_cfg); 1441 1442 core_cfg = qed_rd(p_hwfn, p_ptt, addr); 1443 1444 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >> 1445 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) { 1446 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G: 1447 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G; 1448 break; 1449 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G: 1450 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G; 1451 break; 1452 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G: 1453 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G; 1454 break; 1455 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F: 1456 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F; 1457 break; 1458 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E: 1459 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E; 1460 break; 1461 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G: 1462 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G; 1463 break; 1464 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G: 1465 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G; 1466 break; 1467 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G: 1468 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G; 1469 break; 1470 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G: 1471 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G; 1472 break; 1473 default: 1474 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", 1475 core_cfg); 1476 break; 1477 } 1478 1479 /* Read default link configuration */ 1480 link = &p_hwfn->mcp_info->link_input; 1481 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1482 offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 1483 link_temp = qed_rd(p_hwfn, p_ptt, 1484 port_cfg_addr + 1485 offsetof(struct nvm_cfg1_port, speed_cap_mask)); 1486 link->speed.advertised_speeds = 1487 link_temp & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK; 1488 1489 p_hwfn->mcp_info->link_capabilities.speed_capabilities = 1490 link->speed.advertised_speeds; 1491 1492 link_temp = qed_rd(p_hwfn, p_ptt, 1493 port_cfg_addr + 1494 offsetof(struct nvm_cfg1_port, link_settings)); 1495 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >> 1496 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) { 1497 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG: 1498 link->speed.autoneg = true; 1499 break; 1500 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G: 1501 link->speed.forced_speed = 1000; 1502 break; 1503 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G: 1504 link->speed.forced_speed = 10000; 1505 break; 1506 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G: 1507 link->speed.forced_speed = 25000; 1508 break; 1509 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G: 1510 link->speed.forced_speed = 40000; 1511 break; 1512 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G: 1513 link->speed.forced_speed = 50000; 1514 break; 1515 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G: 1516 link->speed.forced_speed = 100000; 1517 break; 1518 default: 1519 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", 1520 link_temp); 1521 } 1522 1523 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK; 1524 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET; 1525 link->pause.autoneg = !!(link_temp & 1526 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG); 1527 link->pause.forced_rx = !!(link_temp & 1528 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX); 1529 link->pause.forced_tx = !!(link_temp & 1530 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX); 1531 link->loopback_mode = 0; 1532 1533 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1534 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n", 1535 link->speed.forced_speed, link->speed.advertised_speeds, 1536 link->speed.autoneg, link->pause.autoneg); 1537 1538 /* Read Multi-function information from shmem */ 1539 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1540 offsetof(struct nvm_cfg1, glob) + 1541 offsetof(struct nvm_cfg1_glob, generic_cont0); 1542 1543 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr); 1544 1545 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >> 1546 NVM_CFG1_GLOB_MF_MODE_OFFSET; 1547 1548 switch (mf_mode) { 1549 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED: 1550 p_hwfn->cdev->mf_mode = QED_MF_OVLAN; 1551 break; 1552 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0: 1553 p_hwfn->cdev->mf_mode = QED_MF_NPAR; 1554 break; 1555 case NVM_CFG1_GLOB_MF_MODE_DEFAULT: 1556 p_hwfn->cdev->mf_mode = QED_MF_DEFAULT; 1557 break; 1558 } 1559 DP_INFO(p_hwfn, "Multi function mode is %08x\n", 1560 p_hwfn->cdev->mf_mode); 1561 1562 /* Read Multi-function information from shmem */ 1563 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1564 offsetof(struct nvm_cfg1, glob) + 1565 offsetof(struct nvm_cfg1_glob, device_capabilities); 1566 1567 device_capabilities = qed_rd(p_hwfn, p_ptt, addr); 1568 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET) 1569 __set_bit(QED_DEV_CAP_ETH, 1570 &p_hwfn->hw_info.device_capabilities); 1571 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI) 1572 __set_bit(QED_DEV_CAP_ISCSI, 1573 &p_hwfn->hw_info.device_capabilities); 1574 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE) 1575 __set_bit(QED_DEV_CAP_ROCE, 1576 &p_hwfn->hw_info.device_capabilities); 1577 1578 return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt); 1579 } 1580 1581 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1582 { 1583 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id; 1584 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask; 1585 1586 num_funcs = MAX_NUM_PFS_BB; 1587 1588 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values 1589 * in the other bits are selected. 1590 * Bits 1-15 are for functions 1-15, respectively, and their value is 1591 * '0' only for enabled functions (function 0 always exists and 1592 * enabled). 1593 * In case of CMT, only the "even" functions are enabled, and thus the 1594 * number of functions for both hwfns is learnt from the same bits. 1595 */ 1596 reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE); 1597 1598 if (reg_function_hide & 0x1) { 1599 if (QED_PATH_ID(p_hwfn) && p_hwfn->cdev->num_hwfns == 1) { 1600 num_funcs = 0; 1601 eng_mask = 0xaaaa; 1602 } else { 1603 num_funcs = 1; 1604 eng_mask = 0x5554; 1605 } 1606 1607 /* Get the number of the enabled functions on the engine */ 1608 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask; 1609 while (tmp) { 1610 if (tmp & 0x1) 1611 num_funcs++; 1612 tmp >>= 0x1; 1613 } 1614 1615 /* Get the PF index within the enabled functions */ 1616 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1; 1617 tmp = reg_function_hide & eng_mask & low_pfs_mask; 1618 while (tmp) { 1619 if (tmp & 0x1) 1620 enabled_func_idx--; 1621 tmp >>= 0x1; 1622 } 1623 } 1624 1625 p_hwfn->num_funcs_on_engine = num_funcs; 1626 p_hwfn->enabled_func_idx = enabled_func_idx; 1627 1628 DP_VERBOSE(p_hwfn, 1629 NETIF_MSG_PROBE, 1630 "PF [rel_id %d, abs_id %d] within the %d enabled functions on the engine\n", 1631 p_hwfn->rel_pf_id, 1632 p_hwfn->abs_pf_id, 1633 p_hwfn->num_funcs_on_engine); 1634 } 1635 1636 static int 1637 qed_get_hw_info(struct qed_hwfn *p_hwfn, 1638 struct qed_ptt *p_ptt, 1639 enum qed_pci_personality personality) 1640 { 1641 u32 port_mode; 1642 int rc; 1643 1644 /* Since all information is common, only first hwfns should do this */ 1645 if (IS_LEAD_HWFN(p_hwfn)) { 1646 rc = qed_iov_hw_info(p_hwfn); 1647 if (rc) 1648 return rc; 1649 } 1650 1651 /* Read the port mode */ 1652 port_mode = qed_rd(p_hwfn, p_ptt, 1653 CNIG_REG_NW_PORT_MODE_BB_B0); 1654 1655 if (port_mode < 3) { 1656 p_hwfn->cdev->num_ports_in_engines = 1; 1657 } else if (port_mode <= 5) { 1658 p_hwfn->cdev->num_ports_in_engines = 2; 1659 } else { 1660 DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n", 1661 p_hwfn->cdev->num_ports_in_engines); 1662 1663 /* Default num_ports_in_engines to something */ 1664 p_hwfn->cdev->num_ports_in_engines = 1; 1665 } 1666 1667 qed_hw_get_nvm_info(p_hwfn, p_ptt); 1668 1669 rc = qed_int_igu_read_cam(p_hwfn, p_ptt); 1670 if (rc) 1671 return rc; 1672 1673 if (qed_mcp_is_init(p_hwfn)) 1674 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr, 1675 p_hwfn->mcp_info->func_info.mac); 1676 else 1677 eth_random_addr(p_hwfn->hw_info.hw_mac_addr); 1678 1679 if (qed_mcp_is_init(p_hwfn)) { 1680 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET) 1681 p_hwfn->hw_info.ovlan = 1682 p_hwfn->mcp_info->func_info.ovlan; 1683 1684 qed_mcp_cmd_port_init(p_hwfn, p_ptt); 1685 } 1686 1687 if (qed_mcp_is_init(p_hwfn)) { 1688 enum qed_pci_personality protocol; 1689 1690 protocol = p_hwfn->mcp_info->func_info.protocol; 1691 p_hwfn->hw_info.personality = protocol; 1692 } 1693 1694 qed_get_num_funcs(p_hwfn, p_ptt); 1695 1696 return qed_hw_get_resc(p_hwfn); 1697 } 1698 1699 static int qed_get_dev_info(struct qed_dev *cdev) 1700 { 1701 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 1702 u32 tmp; 1703 1704 /* Read Vendor Id / Device Id */ 1705 pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, 1706 &cdev->vendor_id); 1707 pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, 1708 &cdev->device_id); 1709 cdev->chip_num = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, 1710 MISCS_REG_CHIP_NUM); 1711 cdev->chip_rev = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, 1712 MISCS_REG_CHIP_REV); 1713 MASK_FIELD(CHIP_REV, cdev->chip_rev); 1714 1715 cdev->type = QED_DEV_TYPE_BB; 1716 /* Learn number of HW-functions */ 1717 tmp = qed_rd(p_hwfn, p_hwfn->p_main_ptt, 1718 MISCS_REG_CMT_ENABLED_FOR_PAIR); 1719 1720 if (tmp & (1 << p_hwfn->rel_pf_id)) { 1721 DP_NOTICE(cdev->hwfns, "device in CMT mode\n"); 1722 cdev->num_hwfns = 2; 1723 } else { 1724 cdev->num_hwfns = 1; 1725 } 1726 1727 cdev->chip_bond_id = qed_rd(p_hwfn, p_hwfn->p_main_ptt, 1728 MISCS_REG_CHIP_TEST_REG) >> 4; 1729 MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id); 1730 cdev->chip_metal = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, 1731 MISCS_REG_CHIP_METAL); 1732 MASK_FIELD(CHIP_METAL, cdev->chip_metal); 1733 1734 DP_INFO(cdev->hwfns, 1735 "Chip details - Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n", 1736 cdev->chip_num, cdev->chip_rev, 1737 cdev->chip_bond_id, cdev->chip_metal); 1738 1739 if (QED_IS_BB(cdev) && CHIP_REV_IS_A0(cdev)) { 1740 DP_NOTICE(cdev->hwfns, 1741 "The chip type/rev (BB A0) is not supported!\n"); 1742 return -EINVAL; 1743 } 1744 1745 return 0; 1746 } 1747 1748 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn, 1749 void __iomem *p_regview, 1750 void __iomem *p_doorbells, 1751 enum qed_pci_personality personality) 1752 { 1753 int rc = 0; 1754 1755 /* Split PCI bars evenly between hwfns */ 1756 p_hwfn->regview = p_regview; 1757 p_hwfn->doorbells = p_doorbells; 1758 1759 if (IS_VF(p_hwfn->cdev)) 1760 return qed_vf_hw_prepare(p_hwfn); 1761 1762 /* Validate that chip access is feasible */ 1763 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) { 1764 DP_ERR(p_hwfn, 1765 "Reading the ME register returns all Fs; Preventing further chip access\n"); 1766 return -EINVAL; 1767 } 1768 1769 get_function_id(p_hwfn); 1770 1771 /* Allocate PTT pool */ 1772 rc = qed_ptt_pool_alloc(p_hwfn); 1773 if (rc) { 1774 DP_NOTICE(p_hwfn, "Failed to prepare hwfn's hw\n"); 1775 goto err0; 1776 } 1777 1778 /* Allocate the main PTT */ 1779 p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN); 1780 1781 /* First hwfn learns basic information, e.g., number of hwfns */ 1782 if (!p_hwfn->my_id) { 1783 rc = qed_get_dev_info(p_hwfn->cdev); 1784 if (rc != 0) 1785 goto err1; 1786 } 1787 1788 qed_hw_hwfn_prepare(p_hwfn); 1789 1790 /* Initialize MCP structure */ 1791 rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt); 1792 if (rc) { 1793 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n"); 1794 goto err1; 1795 } 1796 1797 /* Read the device configuration information from the HW and SHMEM */ 1798 rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality); 1799 if (rc) { 1800 DP_NOTICE(p_hwfn, "Failed to get HW information\n"); 1801 goto err2; 1802 } 1803 1804 /* Allocate the init RT array and initialize the init-ops engine */ 1805 rc = qed_init_alloc(p_hwfn); 1806 if (rc) { 1807 DP_NOTICE(p_hwfn, "Failed to allocate the init array\n"); 1808 goto err2; 1809 } 1810 1811 return rc; 1812 err2: 1813 if (IS_LEAD_HWFN(p_hwfn)) 1814 qed_iov_free_hw_info(p_hwfn->cdev); 1815 qed_mcp_free(p_hwfn); 1816 err1: 1817 qed_hw_hwfn_free(p_hwfn); 1818 err0: 1819 return rc; 1820 } 1821 1822 int qed_hw_prepare(struct qed_dev *cdev, 1823 int personality) 1824 { 1825 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 1826 int rc; 1827 1828 /* Store the precompiled init data ptrs */ 1829 if (IS_PF(cdev)) 1830 qed_init_iro_array(cdev); 1831 1832 /* Initialize the first hwfn - will learn number of hwfns */ 1833 rc = qed_hw_prepare_single(p_hwfn, 1834 cdev->regview, 1835 cdev->doorbells, personality); 1836 if (rc) 1837 return rc; 1838 1839 personality = p_hwfn->hw_info.personality; 1840 1841 /* Initialize the rest of the hwfns */ 1842 if (cdev->num_hwfns > 1) { 1843 void __iomem *p_regview, *p_doorbell; 1844 u8 __iomem *addr; 1845 1846 /* adjust bar offset for second engine */ 1847 addr = cdev->regview + qed_hw_bar_size(p_hwfn, BAR_ID_0) / 2; 1848 p_regview = addr; 1849 1850 /* adjust doorbell bar offset for second engine */ 1851 addr = cdev->doorbells + qed_hw_bar_size(p_hwfn, BAR_ID_1) / 2; 1852 p_doorbell = addr; 1853 1854 /* prepare second hw function */ 1855 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview, 1856 p_doorbell, personality); 1857 1858 /* in case of error, need to free the previously 1859 * initiliazed hwfn 0. 1860 */ 1861 if (rc) { 1862 if (IS_PF(cdev)) { 1863 qed_init_free(p_hwfn); 1864 qed_mcp_free(p_hwfn); 1865 qed_hw_hwfn_free(p_hwfn); 1866 } 1867 } 1868 } 1869 1870 return rc; 1871 } 1872 1873 void qed_hw_remove(struct qed_dev *cdev) 1874 { 1875 int i; 1876 1877 for_each_hwfn(cdev, i) { 1878 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1879 1880 if (IS_VF(cdev)) { 1881 qed_vf_pf_release(p_hwfn); 1882 continue; 1883 } 1884 1885 qed_init_free(p_hwfn); 1886 qed_hw_hwfn_free(p_hwfn); 1887 qed_mcp_free(p_hwfn); 1888 } 1889 1890 qed_iov_free_hw_info(cdev); 1891 } 1892 1893 static void qed_chain_free_next_ptr(struct qed_dev *cdev, 1894 struct qed_chain *p_chain) 1895 { 1896 void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL; 1897 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0; 1898 struct qed_chain_next *p_next; 1899 u32 size, i; 1900 1901 if (!p_virt) 1902 return; 1903 1904 size = p_chain->elem_size * p_chain->usable_per_page; 1905 1906 for (i = 0; i < p_chain->page_cnt; i++) { 1907 if (!p_virt) 1908 break; 1909 1910 p_next = (struct qed_chain_next *)((u8 *)p_virt + size); 1911 p_virt_next = p_next->next_virt; 1912 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys); 1913 1914 dma_free_coherent(&cdev->pdev->dev, 1915 QED_CHAIN_PAGE_SIZE, p_virt, p_phys); 1916 1917 p_virt = p_virt_next; 1918 p_phys = p_phys_next; 1919 } 1920 } 1921 1922 static void qed_chain_free_single(struct qed_dev *cdev, 1923 struct qed_chain *p_chain) 1924 { 1925 if (!p_chain->p_virt_addr) 1926 return; 1927 1928 dma_free_coherent(&cdev->pdev->dev, 1929 QED_CHAIN_PAGE_SIZE, 1930 p_chain->p_virt_addr, p_chain->p_phys_addr); 1931 } 1932 1933 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain) 1934 { 1935 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl; 1936 u32 page_cnt = p_chain->page_cnt, i, pbl_size; 1937 u8 *p_pbl_virt = p_chain->pbl.p_virt_table; 1938 1939 if (!pp_virt_addr_tbl) 1940 return; 1941 1942 if (!p_chain->pbl.p_virt_table) 1943 goto out; 1944 1945 for (i = 0; i < page_cnt; i++) { 1946 if (!pp_virt_addr_tbl[i]) 1947 break; 1948 1949 dma_free_coherent(&cdev->pdev->dev, 1950 QED_CHAIN_PAGE_SIZE, 1951 pp_virt_addr_tbl[i], 1952 *(dma_addr_t *)p_pbl_virt); 1953 1954 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE; 1955 } 1956 1957 pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; 1958 dma_free_coherent(&cdev->pdev->dev, 1959 pbl_size, 1960 p_chain->pbl.p_virt_table, p_chain->pbl.p_phys_table); 1961 out: 1962 vfree(p_chain->pbl.pp_virt_addr_tbl); 1963 } 1964 1965 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain) 1966 { 1967 switch (p_chain->mode) { 1968 case QED_CHAIN_MODE_NEXT_PTR: 1969 qed_chain_free_next_ptr(cdev, p_chain); 1970 break; 1971 case QED_CHAIN_MODE_SINGLE: 1972 qed_chain_free_single(cdev, p_chain); 1973 break; 1974 case QED_CHAIN_MODE_PBL: 1975 qed_chain_free_pbl(cdev, p_chain); 1976 break; 1977 } 1978 } 1979 1980 static int 1981 qed_chain_alloc_sanity_check(struct qed_dev *cdev, 1982 enum qed_chain_cnt_type cnt_type, 1983 size_t elem_size, u32 page_cnt) 1984 { 1985 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt; 1986 1987 /* The actual chain size can be larger than the maximal possible value 1988 * after rounding up the requested elements number to pages, and after 1989 * taking into acount the unusuable elements (next-ptr elements). 1990 * The size of a "u16" chain can be (U16_MAX + 1) since the chain 1991 * size/capacity fields are of a u32 type. 1992 */ 1993 if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 && 1994 chain_size > 0x10000) || 1995 (cnt_type == QED_CHAIN_CNT_TYPE_U32 && 1996 chain_size > 0x100000000ULL)) { 1997 DP_NOTICE(cdev, 1998 "The actual chain size (0x%llx) is larger than the maximal possible value\n", 1999 chain_size); 2000 return -EINVAL; 2001 } 2002 2003 return 0; 2004 } 2005 2006 static int 2007 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain) 2008 { 2009 void *p_virt = NULL, *p_virt_prev = NULL; 2010 dma_addr_t p_phys = 0; 2011 u32 i; 2012 2013 for (i = 0; i < p_chain->page_cnt; i++) { 2014 p_virt = dma_alloc_coherent(&cdev->pdev->dev, 2015 QED_CHAIN_PAGE_SIZE, 2016 &p_phys, GFP_KERNEL); 2017 if (!p_virt) { 2018 DP_NOTICE(cdev, "Failed to allocate chain memory\n"); 2019 return -ENOMEM; 2020 } 2021 2022 if (i == 0) { 2023 qed_chain_init_mem(p_chain, p_virt, p_phys); 2024 qed_chain_reset(p_chain); 2025 } else { 2026 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, 2027 p_virt, p_phys); 2028 } 2029 2030 p_virt_prev = p_virt; 2031 } 2032 /* Last page's next element should point to the beginning of the 2033 * chain. 2034 */ 2035 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, 2036 p_chain->p_virt_addr, 2037 p_chain->p_phys_addr); 2038 2039 return 0; 2040 } 2041 2042 static int 2043 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain) 2044 { 2045 dma_addr_t p_phys = 0; 2046 void *p_virt = NULL; 2047 2048 p_virt = dma_alloc_coherent(&cdev->pdev->dev, 2049 QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL); 2050 if (!p_virt) { 2051 DP_NOTICE(cdev, "Failed to allocate chain memory\n"); 2052 return -ENOMEM; 2053 } 2054 2055 qed_chain_init_mem(p_chain, p_virt, p_phys); 2056 qed_chain_reset(p_chain); 2057 2058 return 0; 2059 } 2060 2061 static int qed_chain_alloc_pbl(struct qed_dev *cdev, struct qed_chain *p_chain) 2062 { 2063 u32 page_cnt = p_chain->page_cnt, size, i; 2064 dma_addr_t p_phys = 0, p_pbl_phys = 0; 2065 void **pp_virt_addr_tbl = NULL; 2066 u8 *p_pbl_virt = NULL; 2067 void *p_virt = NULL; 2068 2069 size = page_cnt * sizeof(*pp_virt_addr_tbl); 2070 pp_virt_addr_tbl = vmalloc(size); 2071 if (!pp_virt_addr_tbl) { 2072 DP_NOTICE(cdev, 2073 "Failed to allocate memory for the chain virtual addresses table\n"); 2074 return -ENOMEM; 2075 } 2076 memset(pp_virt_addr_tbl, 0, size); 2077 2078 /* The allocation of the PBL table is done with its full size, since it 2079 * is expected to be successive. 2080 * qed_chain_init_pbl_mem() is called even in a case of an allocation 2081 * failure, since pp_virt_addr_tbl was previously allocated, and it 2082 * should be saved to allow its freeing during the error flow. 2083 */ 2084 size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; 2085 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev, 2086 size, &p_pbl_phys, GFP_KERNEL); 2087 qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys, 2088 pp_virt_addr_tbl); 2089 if (!p_pbl_virt) { 2090 DP_NOTICE(cdev, "Failed to allocate chain pbl memory\n"); 2091 return -ENOMEM; 2092 } 2093 2094 for (i = 0; i < page_cnt; i++) { 2095 p_virt = dma_alloc_coherent(&cdev->pdev->dev, 2096 QED_CHAIN_PAGE_SIZE, 2097 &p_phys, GFP_KERNEL); 2098 if (!p_virt) { 2099 DP_NOTICE(cdev, "Failed to allocate chain memory\n"); 2100 return -ENOMEM; 2101 } 2102 2103 if (i == 0) { 2104 qed_chain_init_mem(p_chain, p_virt, p_phys); 2105 qed_chain_reset(p_chain); 2106 } 2107 2108 /* Fill the PBL table with the physical address of the page */ 2109 *(dma_addr_t *)p_pbl_virt = p_phys; 2110 /* Keep the virtual address of the page */ 2111 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt; 2112 2113 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE; 2114 } 2115 2116 return 0; 2117 } 2118 2119 int qed_chain_alloc(struct qed_dev *cdev, 2120 enum qed_chain_use_mode intended_use, 2121 enum qed_chain_mode mode, 2122 enum qed_chain_cnt_type cnt_type, 2123 u32 num_elems, size_t elem_size, struct qed_chain *p_chain) 2124 { 2125 u32 page_cnt; 2126 int rc = 0; 2127 2128 if (mode == QED_CHAIN_MODE_SINGLE) 2129 page_cnt = 1; 2130 else 2131 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode); 2132 2133 rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt); 2134 if (rc) { 2135 DP_NOTICE(cdev, 2136 "Cannot allocate a chain with the given arguments:\n" 2137 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n", 2138 intended_use, mode, cnt_type, num_elems, elem_size); 2139 return rc; 2140 } 2141 2142 qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use, 2143 mode, cnt_type); 2144 2145 switch (mode) { 2146 case QED_CHAIN_MODE_NEXT_PTR: 2147 rc = qed_chain_alloc_next_ptr(cdev, p_chain); 2148 break; 2149 case QED_CHAIN_MODE_SINGLE: 2150 rc = qed_chain_alloc_single(cdev, p_chain); 2151 break; 2152 case QED_CHAIN_MODE_PBL: 2153 rc = qed_chain_alloc_pbl(cdev, p_chain); 2154 break; 2155 } 2156 if (rc) 2157 goto nomem; 2158 2159 return 0; 2160 2161 nomem: 2162 qed_chain_free(cdev, p_chain); 2163 return rc; 2164 } 2165 2166 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id) 2167 { 2168 if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) { 2169 u16 min, max; 2170 2171 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE); 2172 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE); 2173 DP_NOTICE(p_hwfn, 2174 "l2_queue id [%d] is not valid, available indices [%d - %d]\n", 2175 src_id, min, max); 2176 2177 return -EINVAL; 2178 } 2179 2180 *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id; 2181 2182 return 0; 2183 } 2184 2185 int qed_fw_vport(struct qed_hwfn *p_hwfn, 2186 u8 src_id, u8 *dst_id) 2187 { 2188 if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) { 2189 u8 min, max; 2190 2191 min = (u8)RESC_START(p_hwfn, QED_VPORT); 2192 max = min + RESC_NUM(p_hwfn, QED_VPORT); 2193 DP_NOTICE(p_hwfn, 2194 "vport id [%d] is not valid, available indices [%d - %d]\n", 2195 src_id, min, max); 2196 2197 return -EINVAL; 2198 } 2199 2200 *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id; 2201 2202 return 0; 2203 } 2204 2205 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, 2206 u8 src_id, u8 *dst_id) 2207 { 2208 if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) { 2209 u8 min, max; 2210 2211 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG); 2212 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG); 2213 DP_NOTICE(p_hwfn, 2214 "rss_eng id [%d] is not valid, available indices [%d - %d]\n", 2215 src_id, min, max); 2216 2217 return -EINVAL; 2218 } 2219 2220 *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id; 2221 2222 return 0; 2223 } 2224 2225 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2226 u32 hw_addr, void *p_eth_qzone, 2227 size_t eth_qzone_size, u8 timeset) 2228 { 2229 struct coalescing_timeset *p_coal_timeset; 2230 2231 if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) { 2232 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n"); 2233 return -EINVAL; 2234 } 2235 2236 p_coal_timeset = p_eth_qzone; 2237 memset(p_coal_timeset, 0, eth_qzone_size); 2238 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset); 2239 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1); 2240 qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size); 2241 2242 return 0; 2243 } 2244 2245 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2246 u16 coalesce, u8 qid, u16 sb_id) 2247 { 2248 struct ustorm_eth_queue_zone eth_qzone; 2249 u8 timeset, timer_res; 2250 u16 fw_qid = 0; 2251 u32 address; 2252 int rc; 2253 2254 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 2255 if (coalesce <= 0x7F) { 2256 timer_res = 0; 2257 } else if (coalesce <= 0xFF) { 2258 timer_res = 1; 2259 } else if (coalesce <= 0x1FF) { 2260 timer_res = 2; 2261 } else { 2262 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 2263 return -EINVAL; 2264 } 2265 timeset = (u8)(coalesce >> timer_res); 2266 2267 rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid); 2268 if (rc) 2269 return rc; 2270 2271 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false); 2272 if (rc) 2273 goto out; 2274 2275 address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid); 2276 2277 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 2278 sizeof(struct ustorm_eth_queue_zone), timeset); 2279 if (rc) 2280 goto out; 2281 2282 p_hwfn->cdev->rx_coalesce_usecs = coalesce; 2283 out: 2284 return rc; 2285 } 2286 2287 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2288 u16 coalesce, u8 qid, u16 sb_id) 2289 { 2290 struct xstorm_eth_queue_zone eth_qzone; 2291 u8 timeset, timer_res; 2292 u16 fw_qid = 0; 2293 u32 address; 2294 int rc; 2295 2296 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 2297 if (coalesce <= 0x7F) { 2298 timer_res = 0; 2299 } else if (coalesce <= 0xFF) { 2300 timer_res = 1; 2301 } else if (coalesce <= 0x1FF) { 2302 timer_res = 2; 2303 } else { 2304 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 2305 return -EINVAL; 2306 } 2307 timeset = (u8)(coalesce >> timer_res); 2308 2309 rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid); 2310 if (rc) 2311 return rc; 2312 2313 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true); 2314 if (rc) 2315 goto out; 2316 2317 address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid); 2318 2319 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 2320 sizeof(struct xstorm_eth_queue_zone), timeset); 2321 if (rc) 2322 goto out; 2323 2324 p_hwfn->cdev->tx_coalesce_usecs = coalesce; 2325 out: 2326 return rc; 2327 } 2328 2329 /* Calculate final WFQ values for all vports and configure them. 2330 * After this configuration each vport will have 2331 * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT) 2332 */ 2333 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 2334 struct qed_ptt *p_ptt, 2335 u32 min_pf_rate) 2336 { 2337 struct init_qm_vport_params *vport_params; 2338 int i; 2339 2340 vport_params = p_hwfn->qm_info.qm_vport_params; 2341 2342 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 2343 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 2344 2345 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) / 2346 min_pf_rate; 2347 qed_init_vport_wfq(p_hwfn, p_ptt, 2348 vport_params[i].first_tx_pq_id, 2349 vport_params[i].vport_wfq); 2350 } 2351 } 2352 2353 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn, 2354 u32 min_pf_rate) 2355 2356 { 2357 int i; 2358 2359 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) 2360 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1; 2361 } 2362 2363 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 2364 struct qed_ptt *p_ptt, 2365 u32 min_pf_rate) 2366 { 2367 struct init_qm_vport_params *vport_params; 2368 int i; 2369 2370 vport_params = p_hwfn->qm_info.qm_vport_params; 2371 2372 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 2373 qed_init_wfq_default_param(p_hwfn, min_pf_rate); 2374 qed_init_vport_wfq(p_hwfn, p_ptt, 2375 vport_params[i].first_tx_pq_id, 2376 vport_params[i].vport_wfq); 2377 } 2378 } 2379 2380 /* This function performs several validations for WFQ 2381 * configuration and required min rate for a given vport 2382 * 1. req_rate must be greater than one percent of min_pf_rate. 2383 * 2. req_rate should not cause other vports [not configured for WFQ explicitly] 2384 * rates to get less than one percent of min_pf_rate. 2385 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate. 2386 */ 2387 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn, 2388 u16 vport_id, u32 req_rate, 2389 u32 min_pf_rate) 2390 { 2391 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0; 2392 int non_requested_count = 0, req_count = 0, i, num_vports; 2393 2394 num_vports = p_hwfn->qm_info.num_vports; 2395 2396 /* Accounting for the vports which are configured for WFQ explicitly */ 2397 for (i = 0; i < num_vports; i++) { 2398 u32 tmp_speed; 2399 2400 if ((i != vport_id) && 2401 p_hwfn->qm_info.wfq_data[i].configured) { 2402 req_count++; 2403 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 2404 total_req_min_rate += tmp_speed; 2405 } 2406 } 2407 2408 /* Include current vport data as well */ 2409 req_count++; 2410 total_req_min_rate += req_rate; 2411 non_requested_count = num_vports - req_count; 2412 2413 if (req_rate < min_pf_rate / QED_WFQ_UNIT) { 2414 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2415 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 2416 vport_id, req_rate, min_pf_rate); 2417 return -EINVAL; 2418 } 2419 2420 if (num_vports > QED_WFQ_UNIT) { 2421 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2422 "Number of vports is greater than %d\n", 2423 QED_WFQ_UNIT); 2424 return -EINVAL; 2425 } 2426 2427 if (total_req_min_rate > min_pf_rate) { 2428 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2429 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n", 2430 total_req_min_rate, min_pf_rate); 2431 return -EINVAL; 2432 } 2433 2434 total_left_rate = min_pf_rate - total_req_min_rate; 2435 2436 left_rate_per_vp = total_left_rate / non_requested_count; 2437 if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) { 2438 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2439 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 2440 left_rate_per_vp, min_pf_rate); 2441 return -EINVAL; 2442 } 2443 2444 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate; 2445 p_hwfn->qm_info.wfq_data[vport_id].configured = true; 2446 2447 for (i = 0; i < num_vports; i++) { 2448 if (p_hwfn->qm_info.wfq_data[i].configured) 2449 continue; 2450 2451 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp; 2452 } 2453 2454 return 0; 2455 } 2456 2457 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn, 2458 struct qed_ptt *p_ptt, u16 vp_id, u32 rate) 2459 { 2460 struct qed_mcp_link_state *p_link; 2461 int rc = 0; 2462 2463 p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output; 2464 2465 if (!p_link->min_pf_rate) { 2466 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate; 2467 p_hwfn->qm_info.wfq_data[vp_id].configured = true; 2468 return rc; 2469 } 2470 2471 rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate); 2472 2473 if (rc == 0) 2474 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, 2475 p_link->min_pf_rate); 2476 else 2477 DP_NOTICE(p_hwfn, 2478 "Validation failed while configuring min rate\n"); 2479 2480 return rc; 2481 } 2482 2483 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn, 2484 struct qed_ptt *p_ptt, 2485 u32 min_pf_rate) 2486 { 2487 bool use_wfq = false; 2488 int rc = 0; 2489 u16 i; 2490 2491 /* Validate all pre configured vports for wfq */ 2492 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 2493 u32 rate; 2494 2495 if (!p_hwfn->qm_info.wfq_data[i].configured) 2496 continue; 2497 2498 rate = p_hwfn->qm_info.wfq_data[i].min_speed; 2499 use_wfq = true; 2500 2501 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate); 2502 if (rc) { 2503 DP_NOTICE(p_hwfn, 2504 "WFQ validation failed while configuring min rate\n"); 2505 break; 2506 } 2507 } 2508 2509 if (!rc && use_wfq) 2510 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 2511 else 2512 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 2513 2514 return rc; 2515 } 2516 2517 /* Main API for qed clients to configure vport min rate. 2518 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)] 2519 * rate - Speed in Mbps needs to be assigned to a given vport. 2520 */ 2521 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate) 2522 { 2523 int i, rc = -EINVAL; 2524 2525 /* Currently not supported; Might change in future */ 2526 if (cdev->num_hwfns > 1) { 2527 DP_NOTICE(cdev, 2528 "WFQ configuration is not supported for this device\n"); 2529 return rc; 2530 } 2531 2532 for_each_hwfn(cdev, i) { 2533 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2534 struct qed_ptt *p_ptt; 2535 2536 p_ptt = qed_ptt_acquire(p_hwfn); 2537 if (!p_ptt) 2538 return -EBUSY; 2539 2540 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate); 2541 2542 if (!rc) { 2543 qed_ptt_release(p_hwfn, p_ptt); 2544 return rc; 2545 } 2546 2547 qed_ptt_release(p_hwfn, p_ptt); 2548 } 2549 2550 return rc; 2551 } 2552 2553 /* API to configure WFQ from mcp link change */ 2554 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate) 2555 { 2556 int i; 2557 2558 if (cdev->num_hwfns > 1) { 2559 DP_VERBOSE(cdev, 2560 NETIF_MSG_LINK, 2561 "WFQ configuration is not supported for this device\n"); 2562 return; 2563 } 2564 2565 for_each_hwfn(cdev, i) { 2566 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2567 2568 __qed_configure_vp_wfq_on_link_change(p_hwfn, 2569 p_hwfn->p_dpc_ptt, 2570 min_pf_rate); 2571 } 2572 } 2573 2574 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn, 2575 struct qed_ptt *p_ptt, 2576 struct qed_mcp_link_state *p_link, 2577 u8 max_bw) 2578 { 2579 int rc = 0; 2580 2581 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw; 2582 2583 if (!p_link->line_speed && (max_bw != 100)) 2584 return rc; 2585 2586 p_link->speed = (p_link->line_speed * max_bw) / 100; 2587 p_hwfn->qm_info.pf_rl = p_link->speed; 2588 2589 /* Since the limiter also affects Tx-switched traffic, we don't want it 2590 * to limit such traffic in case there's no actual limit. 2591 * In that case, set limit to imaginary high boundary. 2592 */ 2593 if (max_bw == 100) 2594 p_hwfn->qm_info.pf_rl = 100000; 2595 2596 rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, 2597 p_hwfn->qm_info.pf_rl); 2598 2599 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2600 "Configured MAX bandwidth to be %08x Mb/sec\n", 2601 p_link->speed); 2602 2603 return rc; 2604 } 2605 2606 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */ 2607 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw) 2608 { 2609 int i, rc = -EINVAL; 2610 2611 if (max_bw < 1 || max_bw > 100) { 2612 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n"); 2613 return rc; 2614 } 2615 2616 for_each_hwfn(cdev, i) { 2617 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2618 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 2619 struct qed_mcp_link_state *p_link; 2620 struct qed_ptt *p_ptt; 2621 2622 p_link = &p_lead->mcp_info->link_output; 2623 2624 p_ptt = qed_ptt_acquire(p_hwfn); 2625 if (!p_ptt) 2626 return -EBUSY; 2627 2628 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, 2629 p_link, max_bw); 2630 2631 qed_ptt_release(p_hwfn, p_ptt); 2632 2633 if (rc) 2634 break; 2635 } 2636 2637 return rc; 2638 } 2639 2640 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn, 2641 struct qed_ptt *p_ptt, 2642 struct qed_mcp_link_state *p_link, 2643 u8 min_bw) 2644 { 2645 int rc = 0; 2646 2647 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw; 2648 p_hwfn->qm_info.pf_wfq = min_bw; 2649 2650 if (!p_link->line_speed) 2651 return rc; 2652 2653 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100; 2654 2655 rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw); 2656 2657 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2658 "Configured MIN bandwidth to be %d Mb/sec\n", 2659 p_link->min_pf_rate); 2660 2661 return rc; 2662 } 2663 2664 /* Main API to configure PF min bandwidth where bw range is [1-100] */ 2665 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw) 2666 { 2667 int i, rc = -EINVAL; 2668 2669 if (min_bw < 1 || min_bw > 100) { 2670 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n"); 2671 return rc; 2672 } 2673 2674 for_each_hwfn(cdev, i) { 2675 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2676 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 2677 struct qed_mcp_link_state *p_link; 2678 struct qed_ptt *p_ptt; 2679 2680 p_link = &p_lead->mcp_info->link_output; 2681 2682 p_ptt = qed_ptt_acquire(p_hwfn); 2683 if (!p_ptt) 2684 return -EBUSY; 2685 2686 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, 2687 p_link, min_bw); 2688 if (rc) { 2689 qed_ptt_release(p_hwfn, p_ptt); 2690 return rc; 2691 } 2692 2693 if (p_link->min_pf_rate) { 2694 u32 min_rate = p_link->min_pf_rate; 2695 2696 rc = __qed_configure_vp_wfq_on_link_change(p_hwfn, 2697 p_ptt, 2698 min_rate); 2699 } 2700 2701 qed_ptt_release(p_hwfn, p_ptt); 2702 } 2703 2704 return rc; 2705 } 2706 2707 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2708 { 2709 struct qed_mcp_link_state *p_link; 2710 2711 p_link = &p_hwfn->mcp_info->link_output; 2712 2713 if (p_link->min_pf_rate) 2714 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, 2715 p_link->min_pf_rate); 2716 2717 memset(p_hwfn->qm_info.wfq_data, 0, 2718 sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports); 2719 } 2720