1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/types.h> 34 #include <asm/byteorder.h> 35 #include <linux/io.h> 36 #include <linux/delay.h> 37 #include <linux/dma-mapping.h> 38 #include <linux/errno.h> 39 #include <linux/kernel.h> 40 #include <linux/mutex.h> 41 #include <linux/pci.h> 42 #include <linux/slab.h> 43 #include <linux/string.h> 44 #include <linux/vmalloc.h> 45 #include <linux/etherdevice.h> 46 #include <linux/qed/qed_chain.h> 47 #include <linux/qed/qed_if.h> 48 #include "qed.h" 49 #include "qed_cxt.h" 50 #include "qed_dcbx.h" 51 #include "qed_dev_api.h" 52 #include "qed_fcoe.h" 53 #include "qed_hsi.h" 54 #include "qed_hw.h" 55 #include "qed_init_ops.h" 56 #include "qed_int.h" 57 #include "qed_iscsi.h" 58 #include "qed_ll2.h" 59 #include "qed_mcp.h" 60 #include "qed_ooo.h" 61 #include "qed_reg_addr.h" 62 #include "qed_sp.h" 63 #include "qed_sriov.h" 64 #include "qed_vf.h" 65 #include "qed_rdma.h" 66 67 static DEFINE_SPINLOCK(qm_lock); 68 69 /******************** Doorbell Recovery *******************/ 70 /* The doorbell recovery mechanism consists of a list of entries which represent 71 * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each 72 * entity needs to register with the mechanism and provide the parameters 73 * describing it's doorbell, including a location where last used doorbell data 74 * can be found. The doorbell execute function will traverse the list and 75 * doorbell all of the registered entries. 76 */ 77 struct qed_db_recovery_entry { 78 struct list_head list_entry; 79 void __iomem *db_addr; 80 void *db_data; 81 enum qed_db_rec_width db_width; 82 enum qed_db_rec_space db_space; 83 u8 hwfn_idx; 84 }; 85 86 /* Display a single doorbell recovery entry */ 87 static void qed_db_recovery_dp_entry(struct qed_hwfn *p_hwfn, 88 struct qed_db_recovery_entry *db_entry, 89 char *action) 90 { 91 DP_VERBOSE(p_hwfn, 92 QED_MSG_SPQ, 93 "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n", 94 action, 95 db_entry, 96 db_entry->db_addr, 97 db_entry->db_data, 98 db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b", 99 db_entry->db_space == DB_REC_USER ? "user" : "kernel", 100 db_entry->hwfn_idx); 101 } 102 103 /* Doorbell address sanity (address within doorbell bar range) */ 104 static bool qed_db_rec_sanity(struct qed_dev *cdev, 105 void __iomem *db_addr, 106 enum qed_db_rec_width db_width, 107 void *db_data) 108 { 109 u32 width = (db_width == DB_REC_WIDTH_32B) ? 32 : 64; 110 111 /* Make sure doorbell address is within the doorbell bar */ 112 if (db_addr < cdev->doorbells || 113 (u8 __iomem *)db_addr + width > 114 (u8 __iomem *)cdev->doorbells + cdev->db_size) { 115 WARN(true, 116 "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n", 117 db_addr, 118 cdev->doorbells, 119 (u8 __iomem *)cdev->doorbells + cdev->db_size); 120 return false; 121 } 122 123 /* ake sure doorbell data pointer is not null */ 124 if (!db_data) { 125 WARN(true, "Illegal doorbell data pointer: %p", db_data); 126 return false; 127 } 128 129 return true; 130 } 131 132 /* Find hwfn according to the doorbell address */ 133 static struct qed_hwfn *qed_db_rec_find_hwfn(struct qed_dev *cdev, 134 void __iomem *db_addr) 135 { 136 struct qed_hwfn *p_hwfn; 137 138 /* In CMT doorbell bar is split down the middle between engine 0 and enigne 1 */ 139 if (cdev->num_hwfns > 1) 140 p_hwfn = db_addr < cdev->hwfns[1].doorbells ? 141 &cdev->hwfns[0] : &cdev->hwfns[1]; 142 else 143 p_hwfn = QED_LEADING_HWFN(cdev); 144 145 return p_hwfn; 146 } 147 148 /* Add a new entry to the doorbell recovery mechanism */ 149 int qed_db_recovery_add(struct qed_dev *cdev, 150 void __iomem *db_addr, 151 void *db_data, 152 enum qed_db_rec_width db_width, 153 enum qed_db_rec_space db_space) 154 { 155 struct qed_db_recovery_entry *db_entry; 156 struct qed_hwfn *p_hwfn; 157 158 /* Shortcircuit VFs, for now */ 159 if (IS_VF(cdev)) { 160 DP_VERBOSE(cdev, 161 QED_MSG_IOV, "db recovery - skipping VF doorbell\n"); 162 return 0; 163 } 164 165 /* Sanitize doorbell address */ 166 if (!qed_db_rec_sanity(cdev, db_addr, db_width, db_data)) 167 return -EINVAL; 168 169 /* Obtain hwfn from doorbell address */ 170 p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr); 171 172 /* Create entry */ 173 db_entry = kzalloc(sizeof(*db_entry), GFP_KERNEL); 174 if (!db_entry) { 175 DP_NOTICE(cdev, "Failed to allocate a db recovery entry\n"); 176 return -ENOMEM; 177 } 178 179 /* Populate entry */ 180 db_entry->db_addr = db_addr; 181 db_entry->db_data = db_data; 182 db_entry->db_width = db_width; 183 db_entry->db_space = db_space; 184 db_entry->hwfn_idx = p_hwfn->my_id; 185 186 /* Display */ 187 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Adding"); 188 189 /* Protect the list */ 190 spin_lock_bh(&p_hwfn->db_recovery_info.lock); 191 list_add_tail(&db_entry->list_entry, &p_hwfn->db_recovery_info.list); 192 spin_unlock_bh(&p_hwfn->db_recovery_info.lock); 193 194 return 0; 195 } 196 197 /* Remove an entry from the doorbell recovery mechanism */ 198 int qed_db_recovery_del(struct qed_dev *cdev, 199 void __iomem *db_addr, void *db_data) 200 { 201 struct qed_db_recovery_entry *db_entry = NULL; 202 struct qed_hwfn *p_hwfn; 203 int rc = -EINVAL; 204 205 /* Shortcircuit VFs, for now */ 206 if (IS_VF(cdev)) { 207 DP_VERBOSE(cdev, 208 QED_MSG_IOV, "db recovery - skipping VF doorbell\n"); 209 return 0; 210 } 211 212 /* Obtain hwfn from doorbell address */ 213 p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr); 214 215 /* Protect the list */ 216 spin_lock_bh(&p_hwfn->db_recovery_info.lock); 217 list_for_each_entry(db_entry, 218 &p_hwfn->db_recovery_info.list, list_entry) { 219 /* search according to db_data addr since db_addr is not unique (roce) */ 220 if (db_entry->db_data == db_data) { 221 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Deleting"); 222 list_del(&db_entry->list_entry); 223 rc = 0; 224 break; 225 } 226 } 227 228 spin_unlock_bh(&p_hwfn->db_recovery_info.lock); 229 230 if (rc == -EINVAL) 231 232 DP_NOTICE(p_hwfn, 233 "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n", 234 db_data, db_addr); 235 else 236 kfree(db_entry); 237 238 return rc; 239 } 240 241 /* Initialize the doorbell recovery mechanism */ 242 static int qed_db_recovery_setup(struct qed_hwfn *p_hwfn) 243 { 244 DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Setting up db recovery\n"); 245 246 /* Make sure db_size was set in cdev */ 247 if (!p_hwfn->cdev->db_size) { 248 DP_ERR(p_hwfn->cdev, "db_size not set\n"); 249 return -EINVAL; 250 } 251 252 INIT_LIST_HEAD(&p_hwfn->db_recovery_info.list); 253 spin_lock_init(&p_hwfn->db_recovery_info.lock); 254 p_hwfn->db_recovery_info.db_recovery_counter = 0; 255 256 return 0; 257 } 258 259 /* Destroy the doorbell recovery mechanism */ 260 static void qed_db_recovery_teardown(struct qed_hwfn *p_hwfn) 261 { 262 struct qed_db_recovery_entry *db_entry = NULL; 263 264 DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Tearing down db recovery\n"); 265 if (!list_empty(&p_hwfn->db_recovery_info.list)) { 266 DP_VERBOSE(p_hwfn, 267 QED_MSG_SPQ, 268 "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n"); 269 while (!list_empty(&p_hwfn->db_recovery_info.list)) { 270 db_entry = 271 list_first_entry(&p_hwfn->db_recovery_info.list, 272 struct qed_db_recovery_entry, 273 list_entry); 274 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Purging"); 275 list_del(&db_entry->list_entry); 276 kfree(db_entry); 277 } 278 } 279 p_hwfn->db_recovery_info.db_recovery_counter = 0; 280 } 281 282 /* Print the content of the doorbell recovery mechanism */ 283 void qed_db_recovery_dp(struct qed_hwfn *p_hwfn) 284 { 285 struct qed_db_recovery_entry *db_entry = NULL; 286 287 DP_NOTICE(p_hwfn, 288 "Displaying doorbell recovery database. Counter was %d\n", 289 p_hwfn->db_recovery_info.db_recovery_counter); 290 291 /* Protect the list */ 292 spin_lock_bh(&p_hwfn->db_recovery_info.lock); 293 list_for_each_entry(db_entry, 294 &p_hwfn->db_recovery_info.list, list_entry) { 295 qed_db_recovery_dp_entry(p_hwfn, db_entry, "Printing"); 296 } 297 298 spin_unlock_bh(&p_hwfn->db_recovery_info.lock); 299 } 300 301 /* Ring the doorbell of a single doorbell recovery entry */ 302 static void qed_db_recovery_ring(struct qed_hwfn *p_hwfn, 303 struct qed_db_recovery_entry *db_entry) 304 { 305 /* Print according to width */ 306 if (db_entry->db_width == DB_REC_WIDTH_32B) { 307 DP_VERBOSE(p_hwfn, QED_MSG_SPQ, 308 "ringing doorbell address %p data %x\n", 309 db_entry->db_addr, 310 *(u32 *)db_entry->db_data); 311 } else { 312 DP_VERBOSE(p_hwfn, QED_MSG_SPQ, 313 "ringing doorbell address %p data %llx\n", 314 db_entry->db_addr, 315 *(u64 *)(db_entry->db_data)); 316 } 317 318 /* Sanity */ 319 if (!qed_db_rec_sanity(p_hwfn->cdev, db_entry->db_addr, 320 db_entry->db_width, db_entry->db_data)) 321 return; 322 323 /* Flush the write combined buffer. Since there are multiple doorbelling 324 * entities using the same address, if we don't flush, a transaction 325 * could be lost. 326 */ 327 wmb(); 328 329 /* Ring the doorbell */ 330 if (db_entry->db_width == DB_REC_WIDTH_32B) 331 DIRECT_REG_WR(db_entry->db_addr, 332 *(u32 *)(db_entry->db_data)); 333 else 334 DIRECT_REG_WR64(db_entry->db_addr, 335 *(u64 *)(db_entry->db_data)); 336 337 /* Flush the write combined buffer. Next doorbell may come from a 338 * different entity to the same address... 339 */ 340 wmb(); 341 } 342 343 /* Traverse the doorbell recovery entry list and ring all the doorbells */ 344 void qed_db_recovery_execute(struct qed_hwfn *p_hwfn) 345 { 346 struct qed_db_recovery_entry *db_entry = NULL; 347 348 DP_NOTICE(p_hwfn, "Executing doorbell recovery. Counter was %d\n", 349 p_hwfn->db_recovery_info.db_recovery_counter); 350 351 /* Track amount of times recovery was executed */ 352 p_hwfn->db_recovery_info.db_recovery_counter++; 353 354 /* Protect the list */ 355 spin_lock_bh(&p_hwfn->db_recovery_info.lock); 356 list_for_each_entry(db_entry, 357 &p_hwfn->db_recovery_info.list, list_entry) 358 qed_db_recovery_ring(p_hwfn, db_entry); 359 spin_unlock_bh(&p_hwfn->db_recovery_info.lock); 360 } 361 362 /******************** Doorbell Recovery end ****************/ 363 364 #define QED_MIN_DPIS (4) 365 #define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS) 366 367 static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, 368 struct qed_ptt *p_ptt, enum BAR_ID bar_id) 369 { 370 u32 bar_reg = (bar_id == BAR_ID_0 ? 371 PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE); 372 u32 val; 373 374 if (IS_VF(p_hwfn->cdev)) 375 return qed_vf_hw_bar_size(p_hwfn, bar_id); 376 377 val = qed_rd(p_hwfn, p_ptt, bar_reg); 378 if (val) 379 return 1 << (val + 15); 380 381 /* Old MFW initialized above registered only conditionally */ 382 if (p_hwfn->cdev->num_hwfns > 1) { 383 DP_INFO(p_hwfn, 384 "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n"); 385 return BAR_ID_0 ? 256 * 1024 : 512 * 1024; 386 } else { 387 DP_INFO(p_hwfn, 388 "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n"); 389 return 512 * 1024; 390 } 391 } 392 393 void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level) 394 { 395 u32 i; 396 397 cdev->dp_level = dp_level; 398 cdev->dp_module = dp_module; 399 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 400 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 401 402 p_hwfn->dp_level = dp_level; 403 p_hwfn->dp_module = dp_module; 404 } 405 } 406 407 void qed_init_struct(struct qed_dev *cdev) 408 { 409 u8 i; 410 411 for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 412 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 413 414 p_hwfn->cdev = cdev; 415 p_hwfn->my_id = i; 416 p_hwfn->b_active = false; 417 418 mutex_init(&p_hwfn->dmae_info.mutex); 419 } 420 421 /* hwfn 0 is always active */ 422 cdev->hwfns[0].b_active = true; 423 424 /* set the default cache alignment to 128 */ 425 cdev->cache_shift = 7; 426 } 427 428 static void qed_qm_info_free(struct qed_hwfn *p_hwfn) 429 { 430 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 431 432 kfree(qm_info->qm_pq_params); 433 qm_info->qm_pq_params = NULL; 434 kfree(qm_info->qm_vport_params); 435 qm_info->qm_vport_params = NULL; 436 kfree(qm_info->qm_port_params); 437 qm_info->qm_port_params = NULL; 438 kfree(qm_info->wfq_data); 439 qm_info->wfq_data = NULL; 440 } 441 442 static void qed_dbg_user_data_free(struct qed_hwfn *p_hwfn) 443 { 444 kfree(p_hwfn->dbg_user_info); 445 p_hwfn->dbg_user_info = NULL; 446 } 447 448 void qed_resc_free(struct qed_dev *cdev) 449 { 450 int i; 451 452 if (IS_VF(cdev)) { 453 for_each_hwfn(cdev, i) 454 qed_l2_free(&cdev->hwfns[i]); 455 return; 456 } 457 458 kfree(cdev->fw_data); 459 cdev->fw_data = NULL; 460 461 kfree(cdev->reset_stats); 462 cdev->reset_stats = NULL; 463 464 for_each_hwfn(cdev, i) { 465 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 466 467 qed_cxt_mngr_free(p_hwfn); 468 qed_qm_info_free(p_hwfn); 469 qed_spq_free(p_hwfn); 470 qed_eq_free(p_hwfn); 471 qed_consq_free(p_hwfn); 472 qed_int_free(p_hwfn); 473 #ifdef CONFIG_QED_LL2 474 qed_ll2_free(p_hwfn); 475 #endif 476 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) 477 qed_fcoe_free(p_hwfn); 478 479 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 480 qed_iscsi_free(p_hwfn); 481 qed_ooo_free(p_hwfn); 482 } 483 484 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) 485 qed_rdma_info_free(p_hwfn); 486 487 qed_iov_free(p_hwfn); 488 qed_l2_free(p_hwfn); 489 qed_dmae_info_free(p_hwfn); 490 qed_dcbx_info_free(p_hwfn); 491 qed_dbg_user_data_free(p_hwfn); 492 493 /* Destroy doorbell recovery mechanism */ 494 qed_db_recovery_teardown(p_hwfn); 495 } 496 } 497 498 /******************** QM initialization *******************/ 499 #define ACTIVE_TCS_BMAP 0x9f 500 #define ACTIVE_TCS_BMAP_4PORT_K2 0xf 501 502 /* determines the physical queue flags for a given PF. */ 503 static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn) 504 { 505 u32 flags; 506 507 /* common flags */ 508 flags = PQ_FLAGS_LB; 509 510 /* feature flags */ 511 if (IS_QED_SRIOV(p_hwfn->cdev)) 512 flags |= PQ_FLAGS_VFS; 513 514 /* protocol flags */ 515 switch (p_hwfn->hw_info.personality) { 516 case QED_PCI_ETH: 517 flags |= PQ_FLAGS_MCOS; 518 break; 519 case QED_PCI_FCOE: 520 flags |= PQ_FLAGS_OFLD; 521 break; 522 case QED_PCI_ISCSI: 523 flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD; 524 break; 525 case QED_PCI_ETH_ROCE: 526 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT; 527 if (IS_QED_MULTI_TC_ROCE(p_hwfn)) 528 flags |= PQ_FLAGS_MTC; 529 break; 530 case QED_PCI_ETH_IWARP: 531 flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO | 532 PQ_FLAGS_OFLD; 533 break; 534 default: 535 DP_ERR(p_hwfn, 536 "unknown personality %d\n", p_hwfn->hw_info.personality); 537 return 0; 538 } 539 540 return flags; 541 } 542 543 /* Getters for resource amounts necessary for qm initialization */ 544 static u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn) 545 { 546 return p_hwfn->hw_info.num_hw_tc; 547 } 548 549 static u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn) 550 { 551 return IS_QED_SRIOV(p_hwfn->cdev) ? 552 p_hwfn->cdev->p_iov_info->total_vfs : 0; 553 } 554 555 static u8 qed_init_qm_get_num_mtc_tcs(struct qed_hwfn *p_hwfn) 556 { 557 u32 pq_flags = qed_get_pq_flags(p_hwfn); 558 559 if (!(PQ_FLAGS_MTC & pq_flags)) 560 return 1; 561 562 return qed_init_qm_get_num_tcs(p_hwfn); 563 } 564 565 #define NUM_DEFAULT_RLS 1 566 567 static u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn) 568 { 569 u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn); 570 571 /* num RLs can't exceed resource amount of rls or vports */ 572 num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL), 573 RESC_NUM(p_hwfn, QED_VPORT)); 574 575 /* Make sure after we reserve there's something left */ 576 if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) 577 return 0; 578 579 /* subtract rls necessary for VFs and one default one for the PF */ 580 num_pf_rls -= num_vfs + NUM_DEFAULT_RLS; 581 582 return num_pf_rls; 583 } 584 585 static u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn) 586 { 587 u32 pq_flags = qed_get_pq_flags(p_hwfn); 588 589 /* all pqs share the same vport, except for vfs and pf_rl pqs */ 590 return (!!(PQ_FLAGS_RLS & pq_flags)) * 591 qed_init_qm_get_num_pf_rls(p_hwfn) + 592 (!!(PQ_FLAGS_VFS & pq_flags)) * 593 qed_init_qm_get_num_vfs(p_hwfn) + 1; 594 } 595 596 /* calc amount of PQs according to the requested flags */ 597 static u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn) 598 { 599 u32 pq_flags = qed_get_pq_flags(p_hwfn); 600 601 return (!!(PQ_FLAGS_RLS & pq_flags)) * 602 qed_init_qm_get_num_pf_rls(p_hwfn) + 603 (!!(PQ_FLAGS_MCOS & pq_flags)) * 604 qed_init_qm_get_num_tcs(p_hwfn) + 605 (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) + 606 (!!(PQ_FLAGS_ACK & pq_flags)) + 607 (!!(PQ_FLAGS_OFLD & pq_flags)) * 608 qed_init_qm_get_num_mtc_tcs(p_hwfn) + 609 (!!(PQ_FLAGS_LLT & pq_flags)) * 610 qed_init_qm_get_num_mtc_tcs(p_hwfn) + 611 (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn); 612 } 613 614 /* initialize the top level QM params */ 615 static void qed_init_qm_params(struct qed_hwfn *p_hwfn) 616 { 617 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 618 bool four_port; 619 620 /* pq and vport bases for this PF */ 621 qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ); 622 qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT); 623 624 /* rate limiting and weighted fair queueing are always enabled */ 625 qm_info->vport_rl_en = true; 626 qm_info->vport_wfq_en = true; 627 628 /* TC config is different for AH 4 port */ 629 four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2; 630 631 /* in AH 4 port we have fewer TCs per port */ 632 qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 : 633 NUM_OF_PHYS_TCS; 634 635 /* unless MFW indicated otherwise, ooo_tc == 3 for 636 * AH 4-port and 4 otherwise. 637 */ 638 if (!qm_info->ooo_tc) 639 qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC : 640 DCBX_TCP_OOO_TC; 641 } 642 643 /* initialize qm vport params */ 644 static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn) 645 { 646 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 647 u8 i; 648 649 /* all vports participate in weighted fair queueing */ 650 for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++) 651 qm_info->qm_vport_params[i].vport_wfq = 1; 652 } 653 654 /* initialize qm port params */ 655 static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn) 656 { 657 /* Initialize qm port parameters */ 658 u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine; 659 660 /* indicate how ooo and high pri traffic is dealt with */ 661 active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ? 662 ACTIVE_TCS_BMAP_4PORT_K2 : 663 ACTIVE_TCS_BMAP; 664 665 for (i = 0; i < num_ports; i++) { 666 struct init_qm_port_params *p_qm_port = 667 &p_hwfn->qm_info.qm_port_params[i]; 668 669 p_qm_port->active = 1; 670 p_qm_port->active_phys_tcs = active_phys_tcs; 671 p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports; 672 p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports; 673 } 674 } 675 676 /* Reset the params which must be reset for qm init. QM init may be called as 677 * a result of flows other than driver load (e.g. dcbx renegotiation). Other 678 * params may be affected by the init but would simply recalculate to the same 679 * values. The allocations made for QM init, ports, vports, pqs and vfqs are not 680 * affected as these amounts stay the same. 681 */ 682 static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn) 683 { 684 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 685 686 qm_info->num_pqs = 0; 687 qm_info->num_vports = 0; 688 qm_info->num_pf_rls = 0; 689 qm_info->num_vf_pqs = 0; 690 qm_info->first_vf_pq = 0; 691 qm_info->first_mcos_pq = 0; 692 qm_info->first_rl_pq = 0; 693 } 694 695 static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn) 696 { 697 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 698 699 qm_info->num_vports++; 700 701 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn)) 702 DP_ERR(p_hwfn, 703 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n", 704 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn)); 705 } 706 707 /* initialize a single pq and manage qm_info resources accounting. 708 * The pq_init_flags param determines whether the PQ is rate limited 709 * (for VF or PF) and whether a new vport is allocated to the pq or not 710 * (i.e. vport will be shared). 711 */ 712 713 /* flags for pq init */ 714 #define PQ_INIT_SHARE_VPORT (1 << 0) 715 #define PQ_INIT_PF_RL (1 << 1) 716 #define PQ_INIT_VF_RL (1 << 2) 717 718 /* defines for pq init */ 719 #define PQ_INIT_DEFAULT_WRR_GROUP 1 720 #define PQ_INIT_DEFAULT_TC 0 721 722 void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc) 723 { 724 p_info->offload_tc = tc; 725 p_info->offload_tc_set = true; 726 } 727 728 static bool qed_is_offload_tc_set(struct qed_hwfn *p_hwfn) 729 { 730 return p_hwfn->hw_info.offload_tc_set; 731 } 732 733 static u32 qed_get_offload_tc(struct qed_hwfn *p_hwfn) 734 { 735 if (qed_is_offload_tc_set(p_hwfn)) 736 return p_hwfn->hw_info.offload_tc; 737 738 return PQ_INIT_DEFAULT_TC; 739 } 740 741 static void qed_init_qm_pq(struct qed_hwfn *p_hwfn, 742 struct qed_qm_info *qm_info, 743 u8 tc, u32 pq_init_flags) 744 { 745 u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn); 746 747 if (pq_idx > max_pq) 748 DP_ERR(p_hwfn, 749 "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq); 750 751 /* init pq params */ 752 qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id; 753 qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport + 754 qm_info->num_vports; 755 qm_info->qm_pq_params[pq_idx].tc_id = tc; 756 qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP; 757 qm_info->qm_pq_params[pq_idx].rl_valid = 758 (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL); 759 760 /* qm params accounting */ 761 qm_info->num_pqs++; 762 if (!(pq_init_flags & PQ_INIT_SHARE_VPORT)) 763 qm_info->num_vports++; 764 765 if (pq_init_flags & PQ_INIT_PF_RL) 766 qm_info->num_pf_rls++; 767 768 if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn)) 769 DP_ERR(p_hwfn, 770 "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n", 771 qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn)); 772 773 if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn)) 774 DP_ERR(p_hwfn, 775 "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n", 776 qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn)); 777 } 778 779 /* get pq index according to PQ_FLAGS */ 780 static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn, 781 unsigned long pq_flags) 782 { 783 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 784 785 /* Can't have multiple flags set here */ 786 if (bitmap_weight(&pq_flags, 787 sizeof(pq_flags) * BITS_PER_BYTE) > 1) { 788 DP_ERR(p_hwfn, "requested multiple pq flags 0x%lx\n", pq_flags); 789 goto err; 790 } 791 792 if (!(qed_get_pq_flags(p_hwfn) & pq_flags)) { 793 DP_ERR(p_hwfn, "pq flag 0x%lx is not set\n", pq_flags); 794 goto err; 795 } 796 797 switch (pq_flags) { 798 case PQ_FLAGS_RLS: 799 return &qm_info->first_rl_pq; 800 case PQ_FLAGS_MCOS: 801 return &qm_info->first_mcos_pq; 802 case PQ_FLAGS_LB: 803 return &qm_info->pure_lb_pq; 804 case PQ_FLAGS_OOO: 805 return &qm_info->ooo_pq; 806 case PQ_FLAGS_ACK: 807 return &qm_info->pure_ack_pq; 808 case PQ_FLAGS_OFLD: 809 return &qm_info->first_ofld_pq; 810 case PQ_FLAGS_LLT: 811 return &qm_info->first_llt_pq; 812 case PQ_FLAGS_VFS: 813 return &qm_info->first_vf_pq; 814 default: 815 goto err; 816 } 817 818 err: 819 return &qm_info->start_pq; 820 } 821 822 /* save pq index in qm info */ 823 static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn, 824 u32 pq_flags, u16 pq_val) 825 { 826 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags); 827 828 *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val; 829 } 830 831 /* get tx pq index, with the PQ TX base already set (ready for context init) */ 832 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags) 833 { 834 u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags); 835 836 return *base_pq_idx + CM_TX_PQ_BASE; 837 } 838 839 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc) 840 { 841 u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn); 842 843 if (max_tc == 0) { 844 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n", 845 PQ_FLAGS_MCOS); 846 return p_hwfn->qm_info.start_pq; 847 } 848 849 if (tc > max_tc) 850 DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc); 851 852 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc); 853 } 854 855 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf) 856 { 857 u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn); 858 859 if (max_vf == 0) { 860 DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n", 861 PQ_FLAGS_VFS); 862 return p_hwfn->qm_info.start_pq; 863 } 864 865 if (vf > max_vf) 866 DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf); 867 868 return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf); 869 } 870 871 u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc) 872 { 873 u16 first_ofld_pq, pq_offset; 874 875 first_ofld_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD); 876 pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ? 877 tc : PQ_INIT_DEFAULT_TC; 878 879 return first_ofld_pq + pq_offset; 880 } 881 882 u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc) 883 { 884 u16 first_llt_pq, pq_offset; 885 886 first_llt_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LLT); 887 pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ? 888 tc : PQ_INIT_DEFAULT_TC; 889 890 return first_llt_pq + pq_offset; 891 } 892 893 /* Functions for creating specific types of pqs */ 894 static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn) 895 { 896 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 897 898 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB)) 899 return; 900 901 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs); 902 qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT); 903 } 904 905 static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn) 906 { 907 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 908 909 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO)) 910 return; 911 912 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs); 913 qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT); 914 } 915 916 static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn) 917 { 918 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 919 920 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK)) 921 return; 922 923 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs); 924 qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn), 925 PQ_INIT_SHARE_VPORT); 926 } 927 928 static void qed_init_qm_mtc_pqs(struct qed_hwfn *p_hwfn) 929 { 930 u8 num_tcs = qed_init_qm_get_num_mtc_tcs(p_hwfn); 931 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 932 u8 tc; 933 934 /* override pq's TC if offload TC is set */ 935 for (tc = 0; tc < num_tcs; tc++) 936 qed_init_qm_pq(p_hwfn, qm_info, 937 qed_is_offload_tc_set(p_hwfn) ? 938 p_hwfn->hw_info.offload_tc : tc, 939 PQ_INIT_SHARE_VPORT); 940 } 941 942 static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn) 943 { 944 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 945 946 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD)) 947 return; 948 949 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs); 950 qed_init_qm_mtc_pqs(p_hwfn); 951 } 952 953 static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn) 954 { 955 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 956 957 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT)) 958 return; 959 960 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs); 961 qed_init_qm_mtc_pqs(p_hwfn); 962 } 963 964 static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn) 965 { 966 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 967 u8 tc_idx; 968 969 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS)) 970 return; 971 972 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs); 973 for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++) 974 qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT); 975 } 976 977 static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn) 978 { 979 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 980 u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn); 981 982 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS)) 983 return; 984 985 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs); 986 qm_info->num_vf_pqs = num_vfs; 987 for (vf_idx = 0; vf_idx < num_vfs; vf_idx++) 988 qed_init_qm_pq(p_hwfn, 989 qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL); 990 } 991 992 static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn) 993 { 994 u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn); 995 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 996 997 if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS)) 998 return; 999 1000 qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs); 1001 for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++) 1002 qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn), 1003 PQ_INIT_PF_RL); 1004 } 1005 1006 static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn) 1007 { 1008 /* rate limited pqs, must come first (FW assumption) */ 1009 qed_init_qm_rl_pqs(p_hwfn); 1010 1011 /* pqs for multi cos */ 1012 qed_init_qm_mcos_pqs(p_hwfn); 1013 1014 /* pure loopback pq */ 1015 qed_init_qm_lb_pq(p_hwfn); 1016 1017 /* out of order pq */ 1018 qed_init_qm_ooo_pq(p_hwfn); 1019 1020 /* pure ack pq */ 1021 qed_init_qm_pure_ack_pq(p_hwfn); 1022 1023 /* pq for offloaded protocol */ 1024 qed_init_qm_offload_pq(p_hwfn); 1025 1026 /* low latency pq */ 1027 qed_init_qm_low_latency_pq(p_hwfn); 1028 1029 /* done sharing vports */ 1030 qed_init_qm_advance_vport(p_hwfn); 1031 1032 /* pqs for vfs */ 1033 qed_init_qm_vf_pqs(p_hwfn); 1034 } 1035 1036 /* compare values of getters against resources amounts */ 1037 static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn) 1038 { 1039 if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) { 1040 DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n"); 1041 return -EINVAL; 1042 } 1043 1044 if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ)) 1045 return 0; 1046 1047 if (QED_IS_ROCE_PERSONALITY(p_hwfn)) { 1048 p_hwfn->hw_info.multi_tc_roce_en = 0; 1049 DP_NOTICE(p_hwfn, 1050 "multi-tc roce was disabled to reduce requested amount of pqs\n"); 1051 if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ)) 1052 return 0; 1053 } 1054 1055 DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n"); 1056 return -EINVAL; 1057 } 1058 1059 static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn) 1060 { 1061 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1062 struct init_qm_vport_params *vport; 1063 struct init_qm_port_params *port; 1064 struct init_qm_pq_params *pq; 1065 int i, tc; 1066 1067 /* top level params */ 1068 DP_VERBOSE(p_hwfn, 1069 NETIF_MSG_HW, 1070 "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, llt_pq %d, pure_ack_pq %d\n", 1071 qm_info->start_pq, 1072 qm_info->start_vport, 1073 qm_info->pure_lb_pq, 1074 qm_info->first_ofld_pq, 1075 qm_info->first_llt_pq, 1076 qm_info->pure_ack_pq); 1077 DP_VERBOSE(p_hwfn, 1078 NETIF_MSG_HW, 1079 "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n", 1080 qm_info->ooo_pq, 1081 qm_info->first_vf_pq, 1082 qm_info->num_pqs, 1083 qm_info->num_vf_pqs, 1084 qm_info->num_vports, qm_info->max_phys_tcs_per_port); 1085 DP_VERBOSE(p_hwfn, 1086 NETIF_MSG_HW, 1087 "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n", 1088 qm_info->pf_rl_en, 1089 qm_info->pf_wfq_en, 1090 qm_info->vport_rl_en, 1091 qm_info->vport_wfq_en, 1092 qm_info->pf_wfq, 1093 qm_info->pf_rl, 1094 qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn)); 1095 1096 /* port table */ 1097 for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) { 1098 port = &(qm_info->qm_port_params[i]); 1099 DP_VERBOSE(p_hwfn, 1100 NETIF_MSG_HW, 1101 "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n", 1102 i, 1103 port->active, 1104 port->active_phys_tcs, 1105 port->num_pbf_cmd_lines, 1106 port->num_btb_blocks, port->reserved); 1107 } 1108 1109 /* vport table */ 1110 for (i = 0; i < qm_info->num_vports; i++) { 1111 vport = &(qm_info->qm_vport_params[i]); 1112 DP_VERBOSE(p_hwfn, 1113 NETIF_MSG_HW, 1114 "vport idx %d, vport_rl %d, wfq %d, first_tx_pq_id [ ", 1115 qm_info->start_vport + i, 1116 vport->vport_rl, vport->vport_wfq); 1117 for (tc = 0; tc < NUM_OF_TCS; tc++) 1118 DP_VERBOSE(p_hwfn, 1119 NETIF_MSG_HW, 1120 "%d ", vport->first_tx_pq_id[tc]); 1121 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n"); 1122 } 1123 1124 /* pq table */ 1125 for (i = 0; i < qm_info->num_pqs; i++) { 1126 pq = &(qm_info->qm_pq_params[i]); 1127 DP_VERBOSE(p_hwfn, 1128 NETIF_MSG_HW, 1129 "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n", 1130 qm_info->start_pq + i, 1131 pq->port_id, 1132 pq->vport_id, 1133 pq->tc_id, pq->wrr_group, pq->rl_valid); 1134 } 1135 } 1136 1137 static void qed_init_qm_info(struct qed_hwfn *p_hwfn) 1138 { 1139 /* reset params required for init run */ 1140 qed_init_qm_reset_params(p_hwfn); 1141 1142 /* init QM top level params */ 1143 qed_init_qm_params(p_hwfn); 1144 1145 /* init QM port params */ 1146 qed_init_qm_port_params(p_hwfn); 1147 1148 /* init QM vport params */ 1149 qed_init_qm_vport_params(p_hwfn); 1150 1151 /* init QM physical queue params */ 1152 qed_init_qm_pq_params(p_hwfn); 1153 1154 /* display all that init */ 1155 qed_dp_init_qm_params(p_hwfn); 1156 } 1157 1158 /* This function reconfigures the QM pf on the fly. 1159 * For this purpose we: 1160 * 1. reconfigure the QM database 1161 * 2. set new values to runtime array 1162 * 3. send an sdm_qm_cmd through the rbc interface to stop the QM 1163 * 4. activate init tool in QM_PF stage 1164 * 5. send an sdm_qm_cmd through rbc interface to release the QM 1165 */ 1166 int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1167 { 1168 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1169 bool b_rc; 1170 int rc; 1171 1172 /* initialize qed's qm data structure */ 1173 qed_init_qm_info(p_hwfn); 1174 1175 /* stop PF's qm queues */ 1176 spin_lock_bh(&qm_lock); 1177 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true, 1178 qm_info->start_pq, qm_info->num_pqs); 1179 spin_unlock_bh(&qm_lock); 1180 if (!b_rc) 1181 return -EINVAL; 1182 1183 /* clear the QM_PF runtime phase leftovers from previous init */ 1184 qed_init_clear_rt_data(p_hwfn); 1185 1186 /* prepare QM portion of runtime array */ 1187 qed_qm_init_pf(p_hwfn, p_ptt, false); 1188 1189 /* activate init tool on runtime array */ 1190 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id, 1191 p_hwfn->hw_info.hw_mode); 1192 if (rc) 1193 return rc; 1194 1195 /* start PF's qm queues */ 1196 spin_lock_bh(&qm_lock); 1197 b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true, 1198 qm_info->start_pq, qm_info->num_pqs); 1199 spin_unlock_bh(&qm_lock); 1200 if (!b_rc) 1201 return -EINVAL; 1202 1203 return 0; 1204 } 1205 1206 static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn) 1207 { 1208 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1209 int rc; 1210 1211 rc = qed_init_qm_sanity(p_hwfn); 1212 if (rc) 1213 goto alloc_err; 1214 1215 qm_info->qm_pq_params = kcalloc(qed_init_qm_get_num_pqs(p_hwfn), 1216 sizeof(*qm_info->qm_pq_params), 1217 GFP_KERNEL); 1218 if (!qm_info->qm_pq_params) 1219 goto alloc_err; 1220 1221 qm_info->qm_vport_params = kcalloc(qed_init_qm_get_num_vports(p_hwfn), 1222 sizeof(*qm_info->qm_vport_params), 1223 GFP_KERNEL); 1224 if (!qm_info->qm_vport_params) 1225 goto alloc_err; 1226 1227 qm_info->qm_port_params = kcalloc(p_hwfn->cdev->num_ports_in_engine, 1228 sizeof(*qm_info->qm_port_params), 1229 GFP_KERNEL); 1230 if (!qm_info->qm_port_params) 1231 goto alloc_err; 1232 1233 qm_info->wfq_data = kcalloc(qed_init_qm_get_num_vports(p_hwfn), 1234 sizeof(*qm_info->wfq_data), 1235 GFP_KERNEL); 1236 if (!qm_info->wfq_data) 1237 goto alloc_err; 1238 1239 return 0; 1240 1241 alloc_err: 1242 DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n"); 1243 qed_qm_info_free(p_hwfn); 1244 return -ENOMEM; 1245 } 1246 1247 int qed_resc_alloc(struct qed_dev *cdev) 1248 { 1249 u32 rdma_tasks, excess_tasks; 1250 u32 line_count; 1251 int i, rc = 0; 1252 1253 if (IS_VF(cdev)) { 1254 for_each_hwfn(cdev, i) { 1255 rc = qed_l2_alloc(&cdev->hwfns[i]); 1256 if (rc) 1257 return rc; 1258 } 1259 return rc; 1260 } 1261 1262 cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL); 1263 if (!cdev->fw_data) 1264 return -ENOMEM; 1265 1266 for_each_hwfn(cdev, i) { 1267 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1268 u32 n_eqes, num_cons; 1269 1270 /* Initialize the doorbell recovery mechanism */ 1271 rc = qed_db_recovery_setup(p_hwfn); 1272 if (rc) 1273 goto alloc_err; 1274 1275 /* First allocate the context manager structure */ 1276 rc = qed_cxt_mngr_alloc(p_hwfn); 1277 if (rc) 1278 goto alloc_err; 1279 1280 /* Set the HW cid/tid numbers (in the contest manager) 1281 * Must be done prior to any further computations. 1282 */ 1283 rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS); 1284 if (rc) 1285 goto alloc_err; 1286 1287 rc = qed_alloc_qm_data(p_hwfn); 1288 if (rc) 1289 goto alloc_err; 1290 1291 /* init qm info */ 1292 qed_init_qm_info(p_hwfn); 1293 1294 /* Compute the ILT client partition */ 1295 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count); 1296 if (rc) { 1297 DP_NOTICE(p_hwfn, 1298 "too many ILT lines; re-computing with less lines\n"); 1299 /* In case there are not enough ILT lines we reduce the 1300 * number of RDMA tasks and re-compute. 1301 */ 1302 excess_tasks = 1303 qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count); 1304 if (!excess_tasks) 1305 goto alloc_err; 1306 1307 rdma_tasks = RDMA_MAX_TIDS - excess_tasks; 1308 rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks); 1309 if (rc) 1310 goto alloc_err; 1311 1312 rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count); 1313 if (rc) { 1314 DP_ERR(p_hwfn, 1315 "failed ILT compute. Requested too many lines: %u\n", 1316 line_count); 1317 1318 goto alloc_err; 1319 } 1320 } 1321 1322 /* CID map / ILT shadow table / T2 1323 * The talbes sizes are determined by the computations above 1324 */ 1325 rc = qed_cxt_tables_alloc(p_hwfn); 1326 if (rc) 1327 goto alloc_err; 1328 1329 /* SPQ, must follow ILT because initializes SPQ context */ 1330 rc = qed_spq_alloc(p_hwfn); 1331 if (rc) 1332 goto alloc_err; 1333 1334 /* SP status block allocation */ 1335 p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn, 1336 RESERVED_PTT_DPC); 1337 1338 rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt); 1339 if (rc) 1340 goto alloc_err; 1341 1342 rc = qed_iov_alloc(p_hwfn); 1343 if (rc) 1344 goto alloc_err; 1345 1346 /* EQ */ 1347 n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain); 1348 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) { 1349 enum protocol_type rdma_proto; 1350 1351 if (QED_IS_ROCE_PERSONALITY(p_hwfn)) 1352 rdma_proto = PROTOCOLID_ROCE; 1353 else 1354 rdma_proto = PROTOCOLID_IWARP; 1355 1356 num_cons = qed_cxt_get_proto_cid_count(p_hwfn, 1357 rdma_proto, 1358 NULL) * 2; 1359 n_eqes += num_cons + 2 * MAX_NUM_VFS_BB; 1360 } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 1361 num_cons = 1362 qed_cxt_get_proto_cid_count(p_hwfn, 1363 PROTOCOLID_ISCSI, 1364 NULL); 1365 n_eqes += 2 * num_cons; 1366 } 1367 1368 if (n_eqes > 0xFFFF) { 1369 DP_ERR(p_hwfn, 1370 "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n", 1371 n_eqes, 0xFFFF); 1372 goto alloc_no_mem; 1373 } 1374 1375 rc = qed_eq_alloc(p_hwfn, (u16) n_eqes); 1376 if (rc) 1377 goto alloc_err; 1378 1379 rc = qed_consq_alloc(p_hwfn); 1380 if (rc) 1381 goto alloc_err; 1382 1383 rc = qed_l2_alloc(p_hwfn); 1384 if (rc) 1385 goto alloc_err; 1386 1387 #ifdef CONFIG_QED_LL2 1388 if (p_hwfn->using_ll2) { 1389 rc = qed_ll2_alloc(p_hwfn); 1390 if (rc) 1391 goto alloc_err; 1392 } 1393 #endif 1394 1395 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) { 1396 rc = qed_fcoe_alloc(p_hwfn); 1397 if (rc) 1398 goto alloc_err; 1399 } 1400 1401 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 1402 rc = qed_iscsi_alloc(p_hwfn); 1403 if (rc) 1404 goto alloc_err; 1405 rc = qed_ooo_alloc(p_hwfn); 1406 if (rc) 1407 goto alloc_err; 1408 } 1409 1410 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) { 1411 rc = qed_rdma_info_alloc(p_hwfn); 1412 if (rc) 1413 goto alloc_err; 1414 } 1415 1416 /* DMA info initialization */ 1417 rc = qed_dmae_info_alloc(p_hwfn); 1418 if (rc) 1419 goto alloc_err; 1420 1421 /* DCBX initialization */ 1422 rc = qed_dcbx_info_alloc(p_hwfn); 1423 if (rc) 1424 goto alloc_err; 1425 1426 rc = qed_dbg_alloc_user_data(p_hwfn); 1427 if (rc) 1428 goto alloc_err; 1429 } 1430 1431 cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL); 1432 if (!cdev->reset_stats) 1433 goto alloc_no_mem; 1434 1435 return 0; 1436 1437 alloc_no_mem: 1438 rc = -ENOMEM; 1439 alloc_err: 1440 qed_resc_free(cdev); 1441 return rc; 1442 } 1443 1444 void qed_resc_setup(struct qed_dev *cdev) 1445 { 1446 int i; 1447 1448 if (IS_VF(cdev)) { 1449 for_each_hwfn(cdev, i) 1450 qed_l2_setup(&cdev->hwfns[i]); 1451 return; 1452 } 1453 1454 for_each_hwfn(cdev, i) { 1455 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1456 1457 qed_cxt_mngr_setup(p_hwfn); 1458 qed_spq_setup(p_hwfn); 1459 qed_eq_setup(p_hwfn); 1460 qed_consq_setup(p_hwfn); 1461 1462 /* Read shadow of current MFW mailbox */ 1463 qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt); 1464 memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 1465 p_hwfn->mcp_info->mfw_mb_cur, 1466 p_hwfn->mcp_info->mfw_mb_length); 1467 1468 qed_int_setup(p_hwfn, p_hwfn->p_main_ptt); 1469 1470 qed_l2_setup(p_hwfn); 1471 qed_iov_setup(p_hwfn); 1472 #ifdef CONFIG_QED_LL2 1473 if (p_hwfn->using_ll2) 1474 qed_ll2_setup(p_hwfn); 1475 #endif 1476 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) 1477 qed_fcoe_setup(p_hwfn); 1478 1479 if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 1480 qed_iscsi_setup(p_hwfn); 1481 qed_ooo_setup(p_hwfn); 1482 } 1483 } 1484 } 1485 1486 #define FINAL_CLEANUP_POLL_CNT (100) 1487 #define FINAL_CLEANUP_POLL_TIME (10) 1488 int qed_final_cleanup(struct qed_hwfn *p_hwfn, 1489 struct qed_ptt *p_ptt, u16 id, bool is_vf) 1490 { 1491 u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT; 1492 int rc = -EBUSY; 1493 1494 addr = GTT_BAR0_MAP_REG_USDM_RAM + 1495 USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id); 1496 1497 if (is_vf) 1498 id += 0x10; 1499 1500 command |= X_FINAL_CLEANUP_AGG_INT << 1501 SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT; 1502 command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT; 1503 command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT; 1504 command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT; 1505 1506 /* Make sure notification is not set before initiating final cleanup */ 1507 if (REG_RD(p_hwfn, addr)) { 1508 DP_NOTICE(p_hwfn, 1509 "Unexpected; Found final cleanup notification before initiating final cleanup\n"); 1510 REG_WR(p_hwfn, addr, 0); 1511 } 1512 1513 DP_VERBOSE(p_hwfn, QED_MSG_IOV, 1514 "Sending final cleanup for PFVF[%d] [Command %08x]\n", 1515 id, command); 1516 1517 qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command); 1518 1519 /* Poll until completion */ 1520 while (!REG_RD(p_hwfn, addr) && count--) 1521 msleep(FINAL_CLEANUP_POLL_TIME); 1522 1523 if (REG_RD(p_hwfn, addr)) 1524 rc = 0; 1525 else 1526 DP_NOTICE(p_hwfn, 1527 "Failed to receive FW final cleanup notification\n"); 1528 1529 /* Cleanup afterwards */ 1530 REG_WR(p_hwfn, addr, 0); 1531 1532 return rc; 1533 } 1534 1535 static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn) 1536 { 1537 int hw_mode = 0; 1538 1539 if (QED_IS_BB_B0(p_hwfn->cdev)) { 1540 hw_mode |= 1 << MODE_BB; 1541 } else if (QED_IS_AH(p_hwfn->cdev)) { 1542 hw_mode |= 1 << MODE_K2; 1543 } else { 1544 DP_NOTICE(p_hwfn, "Unknown chip type %#x\n", 1545 p_hwfn->cdev->type); 1546 return -EINVAL; 1547 } 1548 1549 switch (p_hwfn->cdev->num_ports_in_engine) { 1550 case 1: 1551 hw_mode |= 1 << MODE_PORTS_PER_ENG_1; 1552 break; 1553 case 2: 1554 hw_mode |= 1 << MODE_PORTS_PER_ENG_2; 1555 break; 1556 case 4: 1557 hw_mode |= 1 << MODE_PORTS_PER_ENG_4; 1558 break; 1559 default: 1560 DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n", 1561 p_hwfn->cdev->num_ports_in_engine); 1562 return -EINVAL; 1563 } 1564 1565 if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits)) 1566 hw_mode |= 1 << MODE_MF_SD; 1567 else 1568 hw_mode |= 1 << MODE_MF_SI; 1569 1570 hw_mode |= 1 << MODE_ASIC; 1571 1572 if (p_hwfn->cdev->num_hwfns > 1) 1573 hw_mode |= 1 << MODE_100G; 1574 1575 p_hwfn->hw_info.hw_mode = hw_mode; 1576 1577 DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP), 1578 "Configuring function for hw_mode: 0x%08x\n", 1579 p_hwfn->hw_info.hw_mode); 1580 1581 return 0; 1582 } 1583 1584 /* Init run time data for all PFs on an engine. */ 1585 static void qed_init_cau_rt_data(struct qed_dev *cdev) 1586 { 1587 u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET; 1588 int i, igu_sb_id; 1589 1590 for_each_hwfn(cdev, i) { 1591 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1592 struct qed_igu_info *p_igu_info; 1593 struct qed_igu_block *p_block; 1594 struct cau_sb_entry sb_entry; 1595 1596 p_igu_info = p_hwfn->hw_info.p_igu_info; 1597 1598 for (igu_sb_id = 0; 1599 igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) { 1600 p_block = &p_igu_info->entry[igu_sb_id]; 1601 1602 if (!p_block->is_pf) 1603 continue; 1604 1605 qed_init_cau_sb_entry(p_hwfn, &sb_entry, 1606 p_block->function_id, 0, 0); 1607 STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2, 1608 sb_entry); 1609 } 1610 } 1611 } 1612 1613 static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn, 1614 struct qed_ptt *p_ptt) 1615 { 1616 u32 val, wr_mbs, cache_line_size; 1617 1618 val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0); 1619 switch (val) { 1620 case 0: 1621 wr_mbs = 128; 1622 break; 1623 case 1: 1624 wr_mbs = 256; 1625 break; 1626 case 2: 1627 wr_mbs = 512; 1628 break; 1629 default: 1630 DP_INFO(p_hwfn, 1631 "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n", 1632 val); 1633 return; 1634 } 1635 1636 cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs); 1637 switch (cache_line_size) { 1638 case 32: 1639 val = 0; 1640 break; 1641 case 64: 1642 val = 1; 1643 break; 1644 case 128: 1645 val = 2; 1646 break; 1647 case 256: 1648 val = 3; 1649 break; 1650 default: 1651 DP_INFO(p_hwfn, 1652 "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n", 1653 cache_line_size); 1654 } 1655 1656 if (L1_CACHE_BYTES > wr_mbs) 1657 DP_INFO(p_hwfn, 1658 "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n", 1659 L1_CACHE_BYTES, wr_mbs); 1660 1661 STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val); 1662 if (val > 0) { 1663 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val); 1664 STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val); 1665 } 1666 } 1667 1668 static int qed_hw_init_common(struct qed_hwfn *p_hwfn, 1669 struct qed_ptt *p_ptt, int hw_mode) 1670 { 1671 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1672 struct qed_qm_common_rt_init_params params; 1673 struct qed_dev *cdev = p_hwfn->cdev; 1674 u8 vf_id, max_num_vfs; 1675 u16 num_pfs, pf_id; 1676 u32 concrete_fid; 1677 int rc = 0; 1678 1679 qed_init_cau_rt_data(cdev); 1680 1681 /* Program GTT windows */ 1682 qed_gtt_init(p_hwfn); 1683 1684 if (p_hwfn->mcp_info) { 1685 if (p_hwfn->mcp_info->func_info.bandwidth_max) 1686 qm_info->pf_rl_en = true; 1687 if (p_hwfn->mcp_info->func_info.bandwidth_min) 1688 qm_info->pf_wfq_en = true; 1689 } 1690 1691 memset(¶ms, 0, sizeof(params)); 1692 params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine; 1693 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port; 1694 params.pf_rl_en = qm_info->pf_rl_en; 1695 params.pf_wfq_en = qm_info->pf_wfq_en; 1696 params.vport_rl_en = qm_info->vport_rl_en; 1697 params.vport_wfq_en = qm_info->vport_wfq_en; 1698 params.port_params = qm_info->qm_port_params; 1699 1700 qed_qm_common_rt_init(p_hwfn, ¶ms); 1701 1702 qed_cxt_hw_init_common(p_hwfn); 1703 1704 qed_init_cache_line_size(p_hwfn, p_ptt); 1705 1706 rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode); 1707 if (rc) 1708 return rc; 1709 1710 qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0); 1711 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1); 1712 1713 if (QED_IS_BB(p_hwfn->cdev)) { 1714 num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev); 1715 for (pf_id = 0; pf_id < num_pfs; pf_id++) { 1716 qed_fid_pretend(p_hwfn, p_ptt, pf_id); 1717 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1718 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1719 } 1720 /* pretend to original PF */ 1721 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 1722 } 1723 1724 max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB; 1725 for (vf_id = 0; vf_id < max_num_vfs; vf_id++) { 1726 concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id); 1727 qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid); 1728 qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1); 1729 qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0); 1730 qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1); 1731 qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0); 1732 } 1733 /* pretend to original PF */ 1734 qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 1735 1736 return rc; 1737 } 1738 1739 static int 1740 qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn, 1741 struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus) 1742 { 1743 u32 dpi_bit_shift, dpi_count, dpi_page_size; 1744 u32 min_dpis; 1745 u32 n_wids; 1746 1747 /* Calculate DPI size */ 1748 n_wids = max_t(u32, QED_MIN_WIDS, n_cpus); 1749 dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids); 1750 dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1); 1751 dpi_bit_shift = ilog2(dpi_page_size / 4096); 1752 dpi_count = pwm_region_size / dpi_page_size; 1753 1754 min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis; 1755 min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis); 1756 1757 p_hwfn->dpi_size = dpi_page_size; 1758 p_hwfn->dpi_count = dpi_count; 1759 1760 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift); 1761 1762 if (dpi_count < min_dpis) 1763 return -EINVAL; 1764 1765 return 0; 1766 } 1767 1768 enum QED_ROCE_EDPM_MODE { 1769 QED_ROCE_EDPM_MODE_ENABLE = 0, 1770 QED_ROCE_EDPM_MODE_FORCE_ON = 1, 1771 QED_ROCE_EDPM_MODE_DISABLE = 2, 1772 }; 1773 1774 bool qed_edpm_enabled(struct qed_hwfn *p_hwfn) 1775 { 1776 if (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm) 1777 return false; 1778 1779 return true; 1780 } 1781 1782 static int 1783 qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1784 { 1785 u32 pwm_regsize, norm_regsize; 1786 u32 non_pwm_conn, min_addr_reg1; 1787 u32 db_bar_size, n_cpus = 1; 1788 u32 roce_edpm_mode; 1789 u32 pf_dems_shift; 1790 int rc = 0; 1791 u8 cond; 1792 1793 db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1); 1794 if (p_hwfn->cdev->num_hwfns > 1) 1795 db_bar_size /= 2; 1796 1797 /* Calculate doorbell regions */ 1798 non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) + 1799 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE, 1800 NULL) + 1801 qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, 1802 NULL); 1803 norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE); 1804 min_addr_reg1 = norm_regsize / 4096; 1805 pwm_regsize = db_bar_size - norm_regsize; 1806 1807 /* Check that the normal and PWM sizes are valid */ 1808 if (db_bar_size < norm_regsize) { 1809 DP_ERR(p_hwfn->cdev, 1810 "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n", 1811 db_bar_size, norm_regsize); 1812 return -EINVAL; 1813 } 1814 1815 if (pwm_regsize < QED_MIN_PWM_REGION) { 1816 DP_ERR(p_hwfn->cdev, 1817 "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n", 1818 pwm_regsize, 1819 QED_MIN_PWM_REGION, db_bar_size, norm_regsize); 1820 return -EINVAL; 1821 } 1822 1823 /* Calculate number of DPIs */ 1824 roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode; 1825 if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) || 1826 ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) { 1827 /* Either EDPM is mandatory, or we are attempting to allocate a 1828 * WID per CPU. 1829 */ 1830 n_cpus = num_present_cpus(); 1831 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 1832 } 1833 1834 cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) || 1835 (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE); 1836 if (cond || p_hwfn->dcbx_no_edpm) { 1837 /* Either EDPM is disabled from user configuration, or it is 1838 * disabled via DCBx, or it is not mandatory and we failed to 1839 * allocated a WID per CPU. 1840 */ 1841 n_cpus = 1; 1842 rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 1843 1844 if (cond) 1845 qed_rdma_dpm_bar(p_hwfn, p_ptt); 1846 } 1847 1848 p_hwfn->wid_count = (u16) n_cpus; 1849 1850 DP_INFO(p_hwfn, 1851 "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s, page_size=%lu\n", 1852 norm_regsize, 1853 pwm_regsize, 1854 p_hwfn->dpi_size, 1855 p_hwfn->dpi_count, 1856 (!qed_edpm_enabled(p_hwfn)) ? 1857 "disabled" : "enabled", PAGE_SIZE); 1858 1859 if (rc) { 1860 DP_ERR(p_hwfn, 1861 "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n", 1862 p_hwfn->dpi_count, 1863 p_hwfn->pf_params.rdma_pf_params.min_dpis); 1864 return -EINVAL; 1865 } 1866 1867 p_hwfn->dpi_start_offset = norm_regsize; 1868 1869 /* DEMS size is configured log2 of DWORDs, hence the division by 4 */ 1870 pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4); 1871 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift); 1872 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1); 1873 1874 return 0; 1875 } 1876 1877 static int qed_hw_init_port(struct qed_hwfn *p_hwfn, 1878 struct qed_ptt *p_ptt, int hw_mode) 1879 { 1880 int rc = 0; 1881 1882 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode); 1883 if (rc) 1884 return rc; 1885 1886 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0); 1887 1888 return 0; 1889 } 1890 1891 static int qed_hw_init_pf(struct qed_hwfn *p_hwfn, 1892 struct qed_ptt *p_ptt, 1893 struct qed_tunnel_info *p_tunn, 1894 int hw_mode, 1895 bool b_hw_start, 1896 enum qed_int_mode int_mode, 1897 bool allow_npar_tx_switch) 1898 { 1899 u8 rel_pf_id = p_hwfn->rel_pf_id; 1900 int rc = 0; 1901 1902 if (p_hwfn->mcp_info) { 1903 struct qed_mcp_function_info *p_info; 1904 1905 p_info = &p_hwfn->mcp_info->func_info; 1906 if (p_info->bandwidth_min) 1907 p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min; 1908 1909 /* Update rate limit once we'll actually have a link */ 1910 p_hwfn->qm_info.pf_rl = 100000; 1911 } 1912 1913 qed_cxt_hw_init_pf(p_hwfn, p_ptt); 1914 1915 qed_int_igu_init_rt(p_hwfn); 1916 1917 /* Set VLAN in NIG if needed */ 1918 if (hw_mode & BIT(MODE_MF_SD)) { 1919 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n"); 1920 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1); 1921 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET, 1922 p_hwfn->hw_info.ovlan); 1923 1924 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 1925 "Configuring LLH_FUNC_FILTER_HDR_SEL\n"); 1926 STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET, 1927 1); 1928 } 1929 1930 /* Enable classification by MAC if needed */ 1931 if (hw_mode & BIT(MODE_MF_SI)) { 1932 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 1933 "Configuring TAGMAC_CLS_TYPE\n"); 1934 STORE_RT_REG(p_hwfn, 1935 NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1); 1936 } 1937 1938 /* Protocol Configuration */ 1939 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 1940 (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0); 1941 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 1942 (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0); 1943 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0); 1944 1945 /* Sanity check before the PF init sequence that uses DMAE */ 1946 rc = qed_dmae_sanity(p_hwfn, p_ptt, "pf_phase"); 1947 if (rc) 1948 return rc; 1949 1950 /* PF Init sequence */ 1951 rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode); 1952 if (rc) 1953 return rc; 1954 1955 /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */ 1956 rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode); 1957 if (rc) 1958 return rc; 1959 1960 /* Pure runtime initializations - directly to the HW */ 1961 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true); 1962 1963 rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt); 1964 if (rc) 1965 return rc; 1966 1967 if (b_hw_start) { 1968 /* enable interrupts */ 1969 qed_int_igu_enable(p_hwfn, p_ptt, int_mode); 1970 1971 /* send function start command */ 1972 rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn, 1973 allow_npar_tx_switch); 1974 if (rc) { 1975 DP_NOTICE(p_hwfn, "Function start ramrod failed\n"); 1976 return rc; 1977 } 1978 if (p_hwfn->hw_info.personality == QED_PCI_FCOE) { 1979 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2)); 1980 qed_wr(p_hwfn, p_ptt, 1981 PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST, 1982 0x100); 1983 } 1984 } 1985 return rc; 1986 } 1987 1988 int qed_pglueb_set_pfid_enable(struct qed_hwfn *p_hwfn, 1989 struct qed_ptt *p_ptt, bool b_enable) 1990 { 1991 u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0; 1992 1993 /* Configure the PF's internal FID_enable for master transactions */ 1994 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val); 1995 1996 /* Wait until value is set - try for 1 second every 50us */ 1997 for (delay_idx = 0; delay_idx < 20000; delay_idx++) { 1998 val = qed_rd(p_hwfn, p_ptt, 1999 PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 2000 if (val == set_val) 2001 break; 2002 2003 usleep_range(50, 60); 2004 } 2005 2006 if (val != set_val) { 2007 DP_NOTICE(p_hwfn, 2008 "PFID_ENABLE_MASTER wasn't changed after a second\n"); 2009 return -EAGAIN; 2010 } 2011 2012 return 0; 2013 } 2014 2015 static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn, 2016 struct qed_ptt *p_main_ptt) 2017 { 2018 /* Read shadow of current MFW mailbox */ 2019 qed_mcp_read_mb(p_hwfn, p_main_ptt); 2020 memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 2021 p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length); 2022 } 2023 2024 static void 2025 qed_fill_load_req_params(struct qed_load_req_params *p_load_req, 2026 struct qed_drv_load_params *p_drv_load) 2027 { 2028 memset(p_load_req, 0, sizeof(*p_load_req)); 2029 2030 p_load_req->drv_role = p_drv_load->is_crash_kernel ? 2031 QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS; 2032 p_load_req->timeout_val = p_drv_load->mfw_timeout_val; 2033 p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset; 2034 p_load_req->override_force_load = p_drv_load->override_force_load; 2035 } 2036 2037 static int qed_vf_start(struct qed_hwfn *p_hwfn, 2038 struct qed_hw_init_params *p_params) 2039 { 2040 if (p_params->p_tunn) { 2041 qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn); 2042 qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn); 2043 } 2044 2045 p_hwfn->b_int_enabled = true; 2046 2047 return 0; 2048 } 2049 2050 static void qed_pglueb_clear_err(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2051 { 2052 qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 2053 BIT(p_hwfn->abs_pf_id)); 2054 } 2055 2056 int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params) 2057 { 2058 struct qed_load_req_params load_req_params; 2059 u32 load_code, resp, param, drv_mb_param; 2060 bool b_default_mtu = true; 2061 struct qed_hwfn *p_hwfn; 2062 int rc = 0, i; 2063 u16 ether_type; 2064 2065 if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) { 2066 DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n"); 2067 return -EINVAL; 2068 } 2069 2070 if (IS_PF(cdev)) { 2071 rc = qed_init_fw_data(cdev, p_params->bin_fw_data); 2072 if (rc) 2073 return rc; 2074 } 2075 2076 for_each_hwfn(cdev, i) { 2077 p_hwfn = &cdev->hwfns[i]; 2078 2079 /* If management didn't provide a default, set one of our own */ 2080 if (!p_hwfn->hw_info.mtu) { 2081 p_hwfn->hw_info.mtu = 1500; 2082 b_default_mtu = false; 2083 } 2084 2085 if (IS_VF(cdev)) { 2086 qed_vf_start(p_hwfn, p_params); 2087 continue; 2088 } 2089 2090 rc = qed_calc_hw_mode(p_hwfn); 2091 if (rc) 2092 return rc; 2093 2094 if (IS_PF(cdev) && (test_bit(QED_MF_8021Q_TAGGING, 2095 &cdev->mf_bits) || 2096 test_bit(QED_MF_8021AD_TAGGING, 2097 &cdev->mf_bits))) { 2098 if (test_bit(QED_MF_8021Q_TAGGING, &cdev->mf_bits)) 2099 ether_type = ETH_P_8021Q; 2100 else 2101 ether_type = ETH_P_8021AD; 2102 STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET, 2103 ether_type); 2104 STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET, 2105 ether_type); 2106 STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET, 2107 ether_type); 2108 STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET, 2109 ether_type); 2110 } 2111 2112 qed_fill_load_req_params(&load_req_params, 2113 p_params->p_drv_load_params); 2114 rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, 2115 &load_req_params); 2116 if (rc) { 2117 DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n"); 2118 return rc; 2119 } 2120 2121 load_code = load_req_params.load_code; 2122 DP_VERBOSE(p_hwfn, QED_MSG_SP, 2123 "Load request was sent. Load code: 0x%x\n", 2124 load_code); 2125 2126 /* Only relevant for recovery: 2127 * Clear the indication after LOAD_REQ is responded by the MFW. 2128 */ 2129 cdev->recov_in_prog = false; 2130 2131 qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt); 2132 2133 qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt); 2134 2135 /* Clean up chip from previous driver if such remains exist. 2136 * This is not needed when the PF is the first one on the 2137 * engine, since afterwards we are going to init the FW. 2138 */ 2139 if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) { 2140 rc = qed_final_cleanup(p_hwfn, p_hwfn->p_main_ptt, 2141 p_hwfn->rel_pf_id, false); 2142 if (rc) { 2143 DP_NOTICE(p_hwfn, "Final cleanup failed\n"); 2144 goto load_err; 2145 } 2146 } 2147 2148 /* Log and clear previous pglue_b errors if such exist */ 2149 qed_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt); 2150 2151 /* Enable the PF's internal FID_enable in the PXP */ 2152 rc = qed_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt, 2153 true); 2154 if (rc) 2155 goto load_err; 2156 2157 /* Clear the pglue_b was_error indication. 2158 * In E4 it must be done after the BME and the internal 2159 * FID_enable for the PF are set, since VDMs may cause the 2160 * indication to be set again. 2161 */ 2162 qed_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt); 2163 2164 switch (load_code) { 2165 case FW_MSG_CODE_DRV_LOAD_ENGINE: 2166 rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt, 2167 p_hwfn->hw_info.hw_mode); 2168 if (rc) 2169 break; 2170 /* Fall through */ 2171 case FW_MSG_CODE_DRV_LOAD_PORT: 2172 rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt, 2173 p_hwfn->hw_info.hw_mode); 2174 if (rc) 2175 break; 2176 2177 /* Fall through */ 2178 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 2179 rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt, 2180 p_params->p_tunn, 2181 p_hwfn->hw_info.hw_mode, 2182 p_params->b_hw_start, 2183 p_params->int_mode, 2184 p_params->allow_npar_tx_switch); 2185 break; 2186 default: 2187 DP_NOTICE(p_hwfn, 2188 "Unexpected load code [0x%08x]", load_code); 2189 rc = -EINVAL; 2190 break; 2191 } 2192 2193 if (rc) { 2194 DP_NOTICE(p_hwfn, 2195 "init phase failed for loadcode 0x%x (rc %d)\n", 2196 load_code, rc); 2197 goto load_err; 2198 } 2199 2200 rc = qed_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt); 2201 if (rc) 2202 return rc; 2203 2204 /* send DCBX attention request command */ 2205 DP_VERBOSE(p_hwfn, 2206 QED_MSG_DCB, 2207 "sending phony dcbx set command to trigger DCBx attention handling\n"); 2208 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 2209 DRV_MSG_CODE_SET_DCBX, 2210 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT, 2211 &resp, ¶m); 2212 if (rc) { 2213 DP_NOTICE(p_hwfn, 2214 "Failed to send DCBX attention request\n"); 2215 return rc; 2216 } 2217 2218 p_hwfn->hw_init_done = true; 2219 } 2220 2221 if (IS_PF(cdev)) { 2222 p_hwfn = QED_LEADING_HWFN(cdev); 2223 2224 /* Get pre-negotiated values for stag, bandwidth etc. */ 2225 DP_VERBOSE(p_hwfn, 2226 QED_MSG_SPQ, 2227 "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n"); 2228 drv_mb_param = 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET; 2229 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 2230 DRV_MSG_CODE_GET_OEM_UPDATES, 2231 drv_mb_param, &resp, ¶m); 2232 if (rc) 2233 DP_NOTICE(p_hwfn, 2234 "Failed to send GET_OEM_UPDATES attention request\n"); 2235 2236 drv_mb_param = STORM_FW_VERSION; 2237 rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 2238 DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER, 2239 drv_mb_param, &load_code, ¶m); 2240 if (rc) 2241 DP_INFO(p_hwfn, "Failed to update firmware version\n"); 2242 2243 if (!b_default_mtu) { 2244 rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt, 2245 p_hwfn->hw_info.mtu); 2246 if (rc) 2247 DP_INFO(p_hwfn, 2248 "Failed to update default mtu\n"); 2249 } 2250 2251 rc = qed_mcp_ov_update_driver_state(p_hwfn, 2252 p_hwfn->p_main_ptt, 2253 QED_OV_DRIVER_STATE_DISABLED); 2254 if (rc) 2255 DP_INFO(p_hwfn, "Failed to update driver state\n"); 2256 2257 rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt, 2258 QED_OV_ESWITCH_NONE); 2259 if (rc) 2260 DP_INFO(p_hwfn, "Failed to update eswitch mode\n"); 2261 } 2262 2263 return 0; 2264 2265 load_err: 2266 /* The MFW load lock should be released also when initialization fails. 2267 */ 2268 qed_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt); 2269 return rc; 2270 } 2271 2272 #define QED_HW_STOP_RETRY_LIMIT (10) 2273 static void qed_hw_timers_stop(struct qed_dev *cdev, 2274 struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2275 { 2276 int i; 2277 2278 /* close timers */ 2279 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0); 2280 qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0); 2281 2282 if (cdev->recov_in_prog) 2283 return; 2284 2285 for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) { 2286 if ((!qed_rd(p_hwfn, p_ptt, 2287 TM_REG_PF_SCAN_ACTIVE_CONN)) && 2288 (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK))) 2289 break; 2290 2291 /* Dependent on number of connection/tasks, possibly 2292 * 1ms sleep is required between polls 2293 */ 2294 usleep_range(1000, 2000); 2295 } 2296 2297 if (i < QED_HW_STOP_RETRY_LIMIT) 2298 return; 2299 2300 DP_NOTICE(p_hwfn, 2301 "Timers linear scans are not over [Connection %02x Tasks %02x]\n", 2302 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN), 2303 (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)); 2304 } 2305 2306 void qed_hw_timers_stop_all(struct qed_dev *cdev) 2307 { 2308 int j; 2309 2310 for_each_hwfn(cdev, j) { 2311 struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 2312 struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 2313 2314 qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 2315 } 2316 } 2317 2318 int qed_hw_stop(struct qed_dev *cdev) 2319 { 2320 struct qed_hwfn *p_hwfn; 2321 struct qed_ptt *p_ptt; 2322 int rc, rc2 = 0; 2323 int j; 2324 2325 for_each_hwfn(cdev, j) { 2326 p_hwfn = &cdev->hwfns[j]; 2327 p_ptt = p_hwfn->p_main_ptt; 2328 2329 DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n"); 2330 2331 if (IS_VF(cdev)) { 2332 qed_vf_pf_int_cleanup(p_hwfn); 2333 rc = qed_vf_pf_reset(p_hwfn); 2334 if (rc) { 2335 DP_NOTICE(p_hwfn, 2336 "qed_vf_pf_reset failed. rc = %d.\n", 2337 rc); 2338 rc2 = -EINVAL; 2339 } 2340 continue; 2341 } 2342 2343 /* mark the hw as uninitialized... */ 2344 p_hwfn->hw_init_done = false; 2345 2346 /* Send unload command to MCP */ 2347 if (!cdev->recov_in_prog) { 2348 rc = qed_mcp_unload_req(p_hwfn, p_ptt); 2349 if (rc) { 2350 DP_NOTICE(p_hwfn, 2351 "Failed sending a UNLOAD_REQ command. rc = %d.\n", 2352 rc); 2353 rc2 = -EINVAL; 2354 } 2355 } 2356 2357 qed_slowpath_irq_sync(p_hwfn); 2358 2359 /* After this point no MFW attentions are expected, e.g. prevent 2360 * race between pf stop and dcbx pf update. 2361 */ 2362 rc = qed_sp_pf_stop(p_hwfn); 2363 if (rc) { 2364 DP_NOTICE(p_hwfn, 2365 "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n", 2366 rc); 2367 rc2 = -EINVAL; 2368 } 2369 2370 qed_wr(p_hwfn, p_ptt, 2371 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 2372 2373 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 2374 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 2375 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 2376 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 2377 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 2378 2379 qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 2380 2381 /* Disable Attention Generation */ 2382 qed_int_igu_disable_int(p_hwfn, p_ptt); 2383 2384 qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0); 2385 qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0); 2386 2387 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true); 2388 2389 /* Need to wait 1ms to guarantee SBs are cleared */ 2390 usleep_range(1000, 2000); 2391 2392 /* Disable PF in HW blocks */ 2393 qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0); 2394 qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0); 2395 2396 if (!cdev->recov_in_prog) { 2397 rc = qed_mcp_unload_done(p_hwfn, p_ptt); 2398 if (rc) { 2399 DP_NOTICE(p_hwfn, 2400 "Failed sending a UNLOAD_DONE command. rc = %d.\n", 2401 rc); 2402 rc2 = -EINVAL; 2403 } 2404 } 2405 } 2406 2407 if (IS_PF(cdev) && !cdev->recov_in_prog) { 2408 p_hwfn = QED_LEADING_HWFN(cdev); 2409 p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt; 2410 2411 /* Clear the PF's internal FID_enable in the PXP. 2412 * In CMT this should only be done for first hw-function, and 2413 * only after all transactions have stopped for all active 2414 * hw-functions. 2415 */ 2416 rc = qed_pglueb_set_pfid_enable(p_hwfn, p_ptt, false); 2417 if (rc) { 2418 DP_NOTICE(p_hwfn, 2419 "qed_pglueb_set_pfid_enable() failed. rc = %d.\n", 2420 rc); 2421 rc2 = -EINVAL; 2422 } 2423 } 2424 2425 return rc2; 2426 } 2427 2428 int qed_hw_stop_fastpath(struct qed_dev *cdev) 2429 { 2430 int j; 2431 2432 for_each_hwfn(cdev, j) { 2433 struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 2434 struct qed_ptt *p_ptt; 2435 2436 if (IS_VF(cdev)) { 2437 qed_vf_pf_int_cleanup(p_hwfn); 2438 continue; 2439 } 2440 p_ptt = qed_ptt_acquire(p_hwfn); 2441 if (!p_ptt) 2442 return -EAGAIN; 2443 2444 DP_VERBOSE(p_hwfn, 2445 NETIF_MSG_IFDOWN, "Shutting down the fastpath\n"); 2446 2447 qed_wr(p_hwfn, p_ptt, 2448 NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 2449 2450 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 2451 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 2452 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 2453 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 2454 qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 2455 2456 qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false); 2457 2458 /* Need to wait 1ms to guarantee SBs are cleared */ 2459 usleep_range(1000, 2000); 2460 qed_ptt_release(p_hwfn, p_ptt); 2461 } 2462 2463 return 0; 2464 } 2465 2466 int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn) 2467 { 2468 struct qed_ptt *p_ptt; 2469 2470 if (IS_VF(p_hwfn->cdev)) 2471 return 0; 2472 2473 p_ptt = qed_ptt_acquire(p_hwfn); 2474 if (!p_ptt) 2475 return -EAGAIN; 2476 2477 if (p_hwfn->p_rdma_info && 2478 p_hwfn->p_rdma_info->active && p_hwfn->b_rdma_enabled_in_prs) 2479 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1); 2480 2481 /* Re-open incoming traffic */ 2482 qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0); 2483 qed_ptt_release(p_hwfn, p_ptt); 2484 2485 return 0; 2486 } 2487 2488 /* Free hwfn memory and resources acquired in hw_hwfn_prepare */ 2489 static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn) 2490 { 2491 qed_ptt_pool_free(p_hwfn); 2492 kfree(p_hwfn->hw_info.p_igu_info); 2493 p_hwfn->hw_info.p_igu_info = NULL; 2494 } 2495 2496 /* Setup bar access */ 2497 static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn) 2498 { 2499 /* clear indirect access */ 2500 if (QED_IS_AH(p_hwfn->cdev)) { 2501 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 2502 PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0); 2503 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 2504 PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0); 2505 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 2506 PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0); 2507 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 2508 PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0); 2509 } else { 2510 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 2511 PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0); 2512 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 2513 PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0); 2514 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 2515 PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0); 2516 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 2517 PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0); 2518 } 2519 2520 /* Clean previous pglue_b errors if such exist */ 2521 qed_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt); 2522 2523 /* enable internal target-read */ 2524 qed_wr(p_hwfn, p_hwfn->p_main_ptt, 2525 PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 2526 } 2527 2528 static void get_function_id(struct qed_hwfn *p_hwfn) 2529 { 2530 /* ME Register */ 2531 p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn, 2532 PXP_PF_ME_OPAQUE_ADDR); 2533 2534 p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); 2535 2536 p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf; 2537 p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 2538 PXP_CONCRETE_FID_PFID); 2539 p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 2540 PXP_CONCRETE_FID_PORT); 2541 2542 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, 2543 "Read ME register: Concrete 0x%08x Opaque 0x%04x\n", 2544 p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid); 2545 } 2546 2547 static void qed_hw_set_feat(struct qed_hwfn *p_hwfn) 2548 { 2549 u32 *feat_num = p_hwfn->hw_info.feat_num; 2550 struct qed_sb_cnt_info sb_cnt; 2551 u32 non_l2_sbs = 0; 2552 2553 memset(&sb_cnt, 0, sizeof(sb_cnt)); 2554 qed_int_get_num_sbs(p_hwfn, &sb_cnt); 2555 2556 if (IS_ENABLED(CONFIG_QED_RDMA) && 2557 QED_IS_RDMA_PERSONALITY(p_hwfn)) { 2558 /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide 2559 * the status blocks equally between L2 / RoCE but with 2560 * consideration as to how many l2 queues / cnqs we have. 2561 */ 2562 feat_num[QED_RDMA_CNQ] = 2563 min_t(u32, sb_cnt.cnt / 2, 2564 RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM)); 2565 2566 non_l2_sbs = feat_num[QED_RDMA_CNQ]; 2567 } 2568 if (QED_IS_L2_PERSONALITY(p_hwfn)) { 2569 /* Start by allocating VF queues, then PF's */ 2570 feat_num[QED_VF_L2_QUE] = min_t(u32, 2571 RESC_NUM(p_hwfn, QED_L2_QUEUE), 2572 sb_cnt.iov_cnt); 2573 feat_num[QED_PF_L2_QUE] = min_t(u32, 2574 sb_cnt.cnt - non_l2_sbs, 2575 RESC_NUM(p_hwfn, 2576 QED_L2_QUEUE) - 2577 FEAT_NUM(p_hwfn, 2578 QED_VF_L2_QUE)); 2579 } 2580 2581 if (QED_IS_FCOE_PERSONALITY(p_hwfn)) 2582 feat_num[QED_FCOE_CQ] = min_t(u32, sb_cnt.cnt, 2583 RESC_NUM(p_hwfn, 2584 QED_CMDQS_CQS)); 2585 2586 if (QED_IS_ISCSI_PERSONALITY(p_hwfn)) 2587 feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt, 2588 RESC_NUM(p_hwfn, 2589 QED_CMDQS_CQS)); 2590 DP_VERBOSE(p_hwfn, 2591 NETIF_MSG_PROBE, 2592 "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d #SBS=%d\n", 2593 (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE), 2594 (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE), 2595 (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ), 2596 (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ), 2597 (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ), 2598 (int)sb_cnt.cnt); 2599 } 2600 2601 const char *qed_hw_get_resc_name(enum qed_resources res_id) 2602 { 2603 switch (res_id) { 2604 case QED_L2_QUEUE: 2605 return "L2_QUEUE"; 2606 case QED_VPORT: 2607 return "VPORT"; 2608 case QED_RSS_ENG: 2609 return "RSS_ENG"; 2610 case QED_PQ: 2611 return "PQ"; 2612 case QED_RL: 2613 return "RL"; 2614 case QED_MAC: 2615 return "MAC"; 2616 case QED_VLAN: 2617 return "VLAN"; 2618 case QED_RDMA_CNQ_RAM: 2619 return "RDMA_CNQ_RAM"; 2620 case QED_ILT: 2621 return "ILT"; 2622 case QED_LL2_QUEUE: 2623 return "LL2_QUEUE"; 2624 case QED_CMDQS_CQS: 2625 return "CMDQS_CQS"; 2626 case QED_RDMA_STATS_QUEUE: 2627 return "RDMA_STATS_QUEUE"; 2628 case QED_BDQ: 2629 return "BDQ"; 2630 case QED_SB: 2631 return "SB"; 2632 default: 2633 return "UNKNOWN_RESOURCE"; 2634 } 2635 } 2636 2637 static int 2638 __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, 2639 struct qed_ptt *p_ptt, 2640 enum qed_resources res_id, 2641 u32 resc_max_val, u32 *p_mcp_resp) 2642 { 2643 int rc; 2644 2645 rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id, 2646 resc_max_val, p_mcp_resp); 2647 if (rc) { 2648 DP_NOTICE(p_hwfn, 2649 "MFW response failure for a max value setting of resource %d [%s]\n", 2650 res_id, qed_hw_get_resc_name(res_id)); 2651 return rc; 2652 } 2653 2654 if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) 2655 DP_INFO(p_hwfn, 2656 "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n", 2657 res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp); 2658 2659 return 0; 2660 } 2661 2662 static int 2663 qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2664 { 2665 bool b_ah = QED_IS_AH(p_hwfn->cdev); 2666 u32 resc_max_val, mcp_resp; 2667 u8 res_id; 2668 int rc; 2669 2670 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) { 2671 switch (res_id) { 2672 case QED_LL2_QUEUE: 2673 resc_max_val = MAX_NUM_LL2_RX_QUEUES; 2674 break; 2675 case QED_RDMA_CNQ_RAM: 2676 /* No need for a case for QED_CMDQS_CQS since 2677 * CNQ/CMDQS are the same resource. 2678 */ 2679 resc_max_val = NUM_OF_GLOBAL_QUEUES; 2680 break; 2681 case QED_RDMA_STATS_QUEUE: 2682 resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 2683 : RDMA_NUM_STATISTIC_COUNTERS_BB; 2684 break; 2685 case QED_BDQ: 2686 resc_max_val = BDQ_NUM_RESOURCES; 2687 break; 2688 default: 2689 continue; 2690 } 2691 2692 rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id, 2693 resc_max_val, &mcp_resp); 2694 if (rc) 2695 return rc; 2696 2697 /* There's no point to continue to the next resource if the 2698 * command is not supported by the MFW. 2699 * We do continue if the command is supported but the resource 2700 * is unknown to the MFW. Such a resource will be later 2701 * configured with the default allocation values. 2702 */ 2703 if (mcp_resp == FW_MSG_CODE_UNSUPPORTED) 2704 return -EINVAL; 2705 } 2706 2707 return 0; 2708 } 2709 2710 static 2711 int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn, 2712 enum qed_resources res_id, 2713 u32 *p_resc_num, u32 *p_resc_start) 2714 { 2715 u8 num_funcs = p_hwfn->num_funcs_on_engine; 2716 bool b_ah = QED_IS_AH(p_hwfn->cdev); 2717 2718 switch (res_id) { 2719 case QED_L2_QUEUE: 2720 *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 : 2721 MAX_NUM_L2_QUEUES_BB) / num_funcs; 2722 break; 2723 case QED_VPORT: 2724 *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 : 2725 MAX_NUM_VPORTS_BB) / num_funcs; 2726 break; 2727 case QED_RSS_ENG: 2728 *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 : 2729 ETH_RSS_ENGINE_NUM_BB) / num_funcs; 2730 break; 2731 case QED_PQ: 2732 *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 : 2733 MAX_QM_TX_QUEUES_BB) / num_funcs; 2734 *p_resc_num &= ~0x7; /* The granularity of the PQs is 8 */ 2735 break; 2736 case QED_RL: 2737 *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs; 2738 break; 2739 case QED_MAC: 2740 case QED_VLAN: 2741 /* Each VFC resource can accommodate both a MAC and a VLAN */ 2742 *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs; 2743 break; 2744 case QED_ILT: 2745 *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 : 2746 PXP_NUM_ILT_RECORDS_BB) / num_funcs; 2747 break; 2748 case QED_LL2_QUEUE: 2749 *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs; 2750 break; 2751 case QED_RDMA_CNQ_RAM: 2752 case QED_CMDQS_CQS: 2753 /* CNQ/CMDQS are the same resource */ 2754 *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs; 2755 break; 2756 case QED_RDMA_STATS_QUEUE: 2757 *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 : 2758 RDMA_NUM_STATISTIC_COUNTERS_BB) / num_funcs; 2759 break; 2760 case QED_BDQ: 2761 if (p_hwfn->hw_info.personality != QED_PCI_ISCSI && 2762 p_hwfn->hw_info.personality != QED_PCI_FCOE) 2763 *p_resc_num = 0; 2764 else 2765 *p_resc_num = 1; 2766 break; 2767 case QED_SB: 2768 /* Since we want its value to reflect whether MFW supports 2769 * the new scheme, have a default of 0. 2770 */ 2771 *p_resc_num = 0; 2772 break; 2773 default: 2774 return -EINVAL; 2775 } 2776 2777 switch (res_id) { 2778 case QED_BDQ: 2779 if (!*p_resc_num) 2780 *p_resc_start = 0; 2781 else if (p_hwfn->cdev->num_ports_in_engine == 4) 2782 *p_resc_start = p_hwfn->port_id; 2783 else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) 2784 *p_resc_start = p_hwfn->port_id; 2785 else if (p_hwfn->hw_info.personality == QED_PCI_FCOE) 2786 *p_resc_start = p_hwfn->port_id + 2; 2787 break; 2788 default: 2789 *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx; 2790 break; 2791 } 2792 2793 return 0; 2794 } 2795 2796 static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn, 2797 enum qed_resources res_id) 2798 { 2799 u32 dflt_resc_num = 0, dflt_resc_start = 0; 2800 u32 mcp_resp, *p_resc_num, *p_resc_start; 2801 int rc; 2802 2803 p_resc_num = &RESC_NUM(p_hwfn, res_id); 2804 p_resc_start = &RESC_START(p_hwfn, res_id); 2805 2806 rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num, 2807 &dflt_resc_start); 2808 if (rc) { 2809 DP_ERR(p_hwfn, 2810 "Failed to get default amount for resource %d [%s]\n", 2811 res_id, qed_hw_get_resc_name(res_id)); 2812 return rc; 2813 } 2814 2815 rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id, 2816 &mcp_resp, p_resc_num, p_resc_start); 2817 if (rc) { 2818 DP_NOTICE(p_hwfn, 2819 "MFW response failure for an allocation request for resource %d [%s]\n", 2820 res_id, qed_hw_get_resc_name(res_id)); 2821 return rc; 2822 } 2823 2824 /* Default driver values are applied in the following cases: 2825 * - The resource allocation MB command is not supported by the MFW 2826 * - There is an internal error in the MFW while processing the request 2827 * - The resource ID is unknown to the MFW 2828 */ 2829 if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) { 2830 DP_INFO(p_hwfn, 2831 "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n", 2832 res_id, 2833 qed_hw_get_resc_name(res_id), 2834 mcp_resp, dflt_resc_num, dflt_resc_start); 2835 *p_resc_num = dflt_resc_num; 2836 *p_resc_start = dflt_resc_start; 2837 goto out; 2838 } 2839 2840 out: 2841 /* PQs have to divide by 8 [that's the HW granularity]. 2842 * Reduce number so it would fit. 2843 */ 2844 if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) { 2845 DP_INFO(p_hwfn, 2846 "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n", 2847 *p_resc_num, 2848 (*p_resc_num) & ~0x7, 2849 *p_resc_start, (*p_resc_start) & ~0x7); 2850 *p_resc_num &= ~0x7; 2851 *p_resc_start &= ~0x7; 2852 } 2853 2854 return 0; 2855 } 2856 2857 static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn) 2858 { 2859 int rc; 2860 u8 res_id; 2861 2862 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) { 2863 rc = __qed_hw_set_resc_info(p_hwfn, res_id); 2864 if (rc) 2865 return rc; 2866 } 2867 2868 return 0; 2869 } 2870 2871 static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2872 { 2873 struct qed_resc_unlock_params resc_unlock_params; 2874 struct qed_resc_lock_params resc_lock_params; 2875 bool b_ah = QED_IS_AH(p_hwfn->cdev); 2876 u8 res_id; 2877 int rc; 2878 2879 /* Setting the max values of the soft resources and the following 2880 * resources allocation queries should be atomic. Since several PFs can 2881 * run in parallel - a resource lock is needed. 2882 * If either the resource lock or resource set value commands are not 2883 * supported - skip the the max values setting, release the lock if 2884 * needed, and proceed to the queries. Other failures, including a 2885 * failure to acquire the lock, will cause this function to fail. 2886 */ 2887 qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params, 2888 QED_RESC_LOCK_RESC_ALLOC, false); 2889 2890 rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params); 2891 if (rc && rc != -EINVAL) { 2892 return rc; 2893 } else if (rc == -EINVAL) { 2894 DP_INFO(p_hwfn, 2895 "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n"); 2896 } else if (!rc && !resc_lock_params.b_granted) { 2897 DP_NOTICE(p_hwfn, 2898 "Failed to acquire the resource lock for the resource allocation commands\n"); 2899 return -EBUSY; 2900 } else { 2901 rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt); 2902 if (rc && rc != -EINVAL) { 2903 DP_NOTICE(p_hwfn, 2904 "Failed to set the max values of the soft resources\n"); 2905 goto unlock_and_exit; 2906 } else if (rc == -EINVAL) { 2907 DP_INFO(p_hwfn, 2908 "Skip the max values setting of the soft resources since it is not supported by the MFW\n"); 2909 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, 2910 &resc_unlock_params); 2911 if (rc) 2912 DP_INFO(p_hwfn, 2913 "Failed to release the resource lock for the resource allocation commands\n"); 2914 } 2915 } 2916 2917 rc = qed_hw_set_resc_info(p_hwfn); 2918 if (rc) 2919 goto unlock_and_exit; 2920 2921 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) { 2922 rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params); 2923 if (rc) 2924 DP_INFO(p_hwfn, 2925 "Failed to release the resource lock for the resource allocation commands\n"); 2926 } 2927 2928 /* Sanity for ILT */ 2929 if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) || 2930 (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) { 2931 DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n", 2932 RESC_START(p_hwfn, QED_ILT), 2933 RESC_END(p_hwfn, QED_ILT) - 1); 2934 return -EINVAL; 2935 } 2936 2937 /* This will also learn the number of SBs from MFW */ 2938 if (qed_int_igu_reset_cam(p_hwfn, p_ptt)) 2939 return -EINVAL; 2940 2941 qed_hw_set_feat(p_hwfn); 2942 2943 for (res_id = 0; res_id < QED_MAX_RESC; res_id++) 2944 DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n", 2945 qed_hw_get_resc_name(res_id), 2946 RESC_NUM(p_hwfn, res_id), 2947 RESC_START(p_hwfn, res_id)); 2948 2949 return 0; 2950 2951 unlock_and_exit: 2952 if (resc_lock_params.b_granted && !resc_unlock_params.b_released) 2953 qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params); 2954 return rc; 2955 } 2956 2957 static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2958 { 2959 u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities; 2960 u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg; 2961 struct qed_mcp_link_capabilities *p_caps; 2962 struct qed_mcp_link_params *link; 2963 2964 /* Read global nvm_cfg address */ 2965 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 2966 2967 /* Verify MCP has initialized it */ 2968 if (!nvm_cfg_addr) { 2969 DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 2970 return -EINVAL; 2971 } 2972 2973 /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */ 2974 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 2975 2976 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2977 offsetof(struct nvm_cfg1, glob) + 2978 offsetof(struct nvm_cfg1_glob, core_cfg); 2979 2980 core_cfg = qed_rd(p_hwfn, p_ptt, addr); 2981 2982 switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >> 2983 NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) { 2984 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G: 2985 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G; 2986 break; 2987 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G: 2988 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G; 2989 break; 2990 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G: 2991 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G; 2992 break; 2993 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F: 2994 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F; 2995 break; 2996 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E: 2997 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E; 2998 break; 2999 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G: 3000 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G; 3001 break; 3002 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G: 3003 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G; 3004 break; 3005 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G: 3006 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G; 3007 break; 3008 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G: 3009 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G; 3010 break; 3011 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G: 3012 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G; 3013 break; 3014 case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G: 3015 p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G; 3016 break; 3017 default: 3018 DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg); 3019 break; 3020 } 3021 3022 /* Read default link configuration */ 3023 link = &p_hwfn->mcp_info->link_input; 3024 p_caps = &p_hwfn->mcp_info->link_capabilities; 3025 port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 3026 offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 3027 link_temp = qed_rd(p_hwfn, p_ptt, 3028 port_cfg_addr + 3029 offsetof(struct nvm_cfg1_port, speed_cap_mask)); 3030 link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK; 3031 link->speed.advertised_speeds = link_temp; 3032 3033 link_temp = link->speed.advertised_speeds; 3034 p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp; 3035 3036 link_temp = qed_rd(p_hwfn, p_ptt, 3037 port_cfg_addr + 3038 offsetof(struct nvm_cfg1_port, link_settings)); 3039 switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >> 3040 NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) { 3041 case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG: 3042 link->speed.autoneg = true; 3043 break; 3044 case NVM_CFG1_PORT_DRV_LINK_SPEED_1G: 3045 link->speed.forced_speed = 1000; 3046 break; 3047 case NVM_CFG1_PORT_DRV_LINK_SPEED_10G: 3048 link->speed.forced_speed = 10000; 3049 break; 3050 case NVM_CFG1_PORT_DRV_LINK_SPEED_20G: 3051 link->speed.forced_speed = 20000; 3052 break; 3053 case NVM_CFG1_PORT_DRV_LINK_SPEED_25G: 3054 link->speed.forced_speed = 25000; 3055 break; 3056 case NVM_CFG1_PORT_DRV_LINK_SPEED_40G: 3057 link->speed.forced_speed = 40000; 3058 break; 3059 case NVM_CFG1_PORT_DRV_LINK_SPEED_50G: 3060 link->speed.forced_speed = 50000; 3061 break; 3062 case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G: 3063 link->speed.forced_speed = 100000; 3064 break; 3065 default: 3066 DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp); 3067 } 3068 3069 p_hwfn->mcp_info->link_capabilities.default_speed_autoneg = 3070 link->speed.autoneg; 3071 3072 link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK; 3073 link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET; 3074 link->pause.autoneg = !!(link_temp & 3075 NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG); 3076 link->pause.forced_rx = !!(link_temp & 3077 NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX); 3078 link->pause.forced_tx = !!(link_temp & 3079 NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX); 3080 link->loopback_mode = 0; 3081 3082 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) { 3083 link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr + 3084 offsetof(struct nvm_cfg1_port, ext_phy)); 3085 link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK; 3086 link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET; 3087 p_caps->default_eee = QED_MCP_EEE_ENABLED; 3088 link->eee.enable = true; 3089 switch (link_temp) { 3090 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED: 3091 p_caps->default_eee = QED_MCP_EEE_DISABLED; 3092 link->eee.enable = false; 3093 break; 3094 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED: 3095 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME; 3096 break; 3097 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE: 3098 p_caps->eee_lpi_timer = 3099 EEE_TX_TIMER_USEC_AGGRESSIVE_TIME; 3100 break; 3101 case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY: 3102 p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME; 3103 break; 3104 } 3105 3106 link->eee.tx_lpi_timer = p_caps->eee_lpi_timer; 3107 link->eee.tx_lpi_enable = link->eee.enable; 3108 link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV; 3109 } else { 3110 p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED; 3111 } 3112 3113 DP_VERBOSE(p_hwfn, 3114 NETIF_MSG_LINK, 3115 "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x EEE: %02x [%08x usec]\n", 3116 link->speed.forced_speed, 3117 link->speed.advertised_speeds, 3118 link->speed.autoneg, 3119 link->pause.autoneg, 3120 p_caps->default_eee, p_caps->eee_lpi_timer); 3121 3122 if (IS_LEAD_HWFN(p_hwfn)) { 3123 struct qed_dev *cdev = p_hwfn->cdev; 3124 3125 /* Read Multi-function information from shmem */ 3126 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 3127 offsetof(struct nvm_cfg1, glob) + 3128 offsetof(struct nvm_cfg1_glob, generic_cont0); 3129 3130 generic_cont0 = qed_rd(p_hwfn, p_ptt, addr); 3131 3132 mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >> 3133 NVM_CFG1_GLOB_MF_MODE_OFFSET; 3134 3135 switch (mf_mode) { 3136 case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED: 3137 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS); 3138 break; 3139 case NVM_CFG1_GLOB_MF_MODE_UFP: 3140 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) | 3141 BIT(QED_MF_LLH_PROTO_CLSS) | 3142 BIT(QED_MF_UFP_SPECIFIC) | 3143 BIT(QED_MF_8021Q_TAGGING); 3144 break; 3145 case NVM_CFG1_GLOB_MF_MODE_BD: 3146 cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) | 3147 BIT(QED_MF_LLH_PROTO_CLSS) | 3148 BIT(QED_MF_8021AD_TAGGING); 3149 break; 3150 case NVM_CFG1_GLOB_MF_MODE_NPAR1_0: 3151 cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) | 3152 BIT(QED_MF_LLH_PROTO_CLSS) | 3153 BIT(QED_MF_LL2_NON_UNICAST) | 3154 BIT(QED_MF_INTER_PF_SWITCH); 3155 break; 3156 case NVM_CFG1_GLOB_MF_MODE_DEFAULT: 3157 cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) | 3158 BIT(QED_MF_LLH_PROTO_CLSS) | 3159 BIT(QED_MF_LL2_NON_UNICAST); 3160 if (QED_IS_BB(p_hwfn->cdev)) 3161 cdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF); 3162 break; 3163 } 3164 3165 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n", 3166 cdev->mf_bits); 3167 } 3168 3169 DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n", 3170 p_hwfn->cdev->mf_bits); 3171 3172 /* Read device capabilities information from shmem */ 3173 addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 3174 offsetof(struct nvm_cfg1, glob) + 3175 offsetof(struct nvm_cfg1_glob, device_capabilities); 3176 3177 device_capabilities = qed_rd(p_hwfn, p_ptt, addr); 3178 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET) 3179 __set_bit(QED_DEV_CAP_ETH, 3180 &p_hwfn->hw_info.device_capabilities); 3181 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE) 3182 __set_bit(QED_DEV_CAP_FCOE, 3183 &p_hwfn->hw_info.device_capabilities); 3184 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI) 3185 __set_bit(QED_DEV_CAP_ISCSI, 3186 &p_hwfn->hw_info.device_capabilities); 3187 if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE) 3188 __set_bit(QED_DEV_CAP_ROCE, 3189 &p_hwfn->hw_info.device_capabilities); 3190 3191 return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt); 3192 } 3193 3194 static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3195 { 3196 u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id; 3197 u32 reg_function_hide, tmp, eng_mask, low_pfs_mask; 3198 struct qed_dev *cdev = p_hwfn->cdev; 3199 3200 num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB; 3201 3202 /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values 3203 * in the other bits are selected. 3204 * Bits 1-15 are for functions 1-15, respectively, and their value is 3205 * '0' only for enabled functions (function 0 always exists and 3206 * enabled). 3207 * In case of CMT, only the "even" functions are enabled, and thus the 3208 * number of functions for both hwfns is learnt from the same bits. 3209 */ 3210 reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE); 3211 3212 if (reg_function_hide & 0x1) { 3213 if (QED_IS_BB(cdev)) { 3214 if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) { 3215 num_funcs = 0; 3216 eng_mask = 0xaaaa; 3217 } else { 3218 num_funcs = 1; 3219 eng_mask = 0x5554; 3220 } 3221 } else { 3222 num_funcs = 1; 3223 eng_mask = 0xfffe; 3224 } 3225 3226 /* Get the number of the enabled functions on the engine */ 3227 tmp = (reg_function_hide ^ 0xffffffff) & eng_mask; 3228 while (tmp) { 3229 if (tmp & 0x1) 3230 num_funcs++; 3231 tmp >>= 0x1; 3232 } 3233 3234 /* Get the PF index within the enabled functions */ 3235 low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1; 3236 tmp = reg_function_hide & eng_mask & low_pfs_mask; 3237 while (tmp) { 3238 if (tmp & 0x1) 3239 enabled_func_idx--; 3240 tmp >>= 0x1; 3241 } 3242 } 3243 3244 p_hwfn->num_funcs_on_engine = num_funcs; 3245 p_hwfn->enabled_func_idx = enabled_func_idx; 3246 3247 DP_VERBOSE(p_hwfn, 3248 NETIF_MSG_PROBE, 3249 "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n", 3250 p_hwfn->rel_pf_id, 3251 p_hwfn->abs_pf_id, 3252 p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine); 3253 } 3254 3255 static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3256 { 3257 u32 addr, global_offsize, global_addr, port_mode; 3258 struct qed_dev *cdev = p_hwfn->cdev; 3259 3260 /* In CMT there is always only one port */ 3261 if (cdev->num_hwfns > 1) { 3262 cdev->num_ports_in_engine = 1; 3263 cdev->num_ports = 1; 3264 return; 3265 } 3266 3267 /* Determine the number of ports per engine */ 3268 port_mode = qed_rd(p_hwfn, p_ptt, MISC_REG_PORT_MODE); 3269 switch (port_mode) { 3270 case 0x0: 3271 cdev->num_ports_in_engine = 1; 3272 break; 3273 case 0x1: 3274 cdev->num_ports_in_engine = 2; 3275 break; 3276 case 0x2: 3277 cdev->num_ports_in_engine = 4; 3278 break; 3279 default: 3280 DP_NOTICE(p_hwfn, "Unknown port mode 0x%08x\n", port_mode); 3281 cdev->num_ports_in_engine = 1; /* Default to something */ 3282 break; 3283 } 3284 3285 /* Get the total number of ports of the device */ 3286 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 3287 PUBLIC_GLOBAL); 3288 global_offsize = qed_rd(p_hwfn, p_ptt, addr); 3289 global_addr = SECTION_ADDR(global_offsize, 0); 3290 addr = global_addr + offsetof(struct public_global, max_ports); 3291 cdev->num_ports = (u8)qed_rd(p_hwfn, p_ptt, addr); 3292 } 3293 3294 static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3295 { 3296 struct qed_mcp_link_capabilities *p_caps; 3297 u32 eee_status; 3298 3299 p_caps = &p_hwfn->mcp_info->link_capabilities; 3300 if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED) 3301 return; 3302 3303 p_caps->eee_speed_caps = 0; 3304 eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 3305 offsetof(struct public_port, eee_status)); 3306 eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >> 3307 EEE_SUPPORTED_SPEED_OFFSET; 3308 3309 if (eee_status & EEE_1G_SUPPORTED) 3310 p_caps->eee_speed_caps |= QED_EEE_1G_ADV; 3311 if (eee_status & EEE_10G_ADV) 3312 p_caps->eee_speed_caps |= QED_EEE_10G_ADV; 3313 } 3314 3315 static int 3316 qed_get_hw_info(struct qed_hwfn *p_hwfn, 3317 struct qed_ptt *p_ptt, 3318 enum qed_pci_personality personality) 3319 { 3320 int rc; 3321 3322 /* Since all information is common, only first hwfns should do this */ 3323 if (IS_LEAD_HWFN(p_hwfn)) { 3324 rc = qed_iov_hw_info(p_hwfn); 3325 if (rc) 3326 return rc; 3327 } 3328 3329 if (IS_LEAD_HWFN(p_hwfn)) 3330 qed_hw_info_port_num(p_hwfn, p_ptt); 3331 3332 qed_mcp_get_capabilities(p_hwfn, p_ptt); 3333 3334 qed_hw_get_nvm_info(p_hwfn, p_ptt); 3335 3336 rc = qed_int_igu_read_cam(p_hwfn, p_ptt); 3337 if (rc) 3338 return rc; 3339 3340 if (qed_mcp_is_init(p_hwfn)) 3341 ether_addr_copy(p_hwfn->hw_info.hw_mac_addr, 3342 p_hwfn->mcp_info->func_info.mac); 3343 else 3344 eth_random_addr(p_hwfn->hw_info.hw_mac_addr); 3345 3346 if (qed_mcp_is_init(p_hwfn)) { 3347 if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET) 3348 p_hwfn->hw_info.ovlan = 3349 p_hwfn->mcp_info->func_info.ovlan; 3350 3351 qed_mcp_cmd_port_init(p_hwfn, p_ptt); 3352 3353 qed_get_eee_caps(p_hwfn, p_ptt); 3354 3355 qed_mcp_read_ufp_config(p_hwfn, p_ptt); 3356 } 3357 3358 if (qed_mcp_is_init(p_hwfn)) { 3359 enum qed_pci_personality protocol; 3360 3361 protocol = p_hwfn->mcp_info->func_info.protocol; 3362 p_hwfn->hw_info.personality = protocol; 3363 } 3364 3365 if (QED_IS_ROCE_PERSONALITY(p_hwfn)) 3366 p_hwfn->hw_info.multi_tc_roce_en = 1; 3367 3368 p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2; 3369 p_hwfn->hw_info.num_active_tc = 1; 3370 3371 qed_get_num_funcs(p_hwfn, p_ptt); 3372 3373 if (qed_mcp_is_init(p_hwfn)) 3374 p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu; 3375 3376 return qed_hw_get_resc(p_hwfn, p_ptt); 3377 } 3378 3379 static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3380 { 3381 struct qed_dev *cdev = p_hwfn->cdev; 3382 u16 device_id_mask; 3383 u32 tmp; 3384 3385 /* Read Vendor Id / Device Id */ 3386 pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id); 3387 pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id); 3388 3389 /* Determine type */ 3390 device_id_mask = cdev->device_id & QED_DEV_ID_MASK; 3391 switch (device_id_mask) { 3392 case QED_DEV_ID_MASK_BB: 3393 cdev->type = QED_DEV_TYPE_BB; 3394 break; 3395 case QED_DEV_ID_MASK_AH: 3396 cdev->type = QED_DEV_TYPE_AH; 3397 break; 3398 default: 3399 DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id); 3400 return -EBUSY; 3401 } 3402 3403 cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM); 3404 cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV); 3405 3406 MASK_FIELD(CHIP_REV, cdev->chip_rev); 3407 3408 /* Learn number of HW-functions */ 3409 tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR); 3410 3411 if (tmp & (1 << p_hwfn->rel_pf_id)) { 3412 DP_NOTICE(cdev->hwfns, "device in CMT mode\n"); 3413 cdev->num_hwfns = 2; 3414 } else { 3415 cdev->num_hwfns = 1; 3416 } 3417 3418 cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt, 3419 MISCS_REG_CHIP_TEST_REG) >> 4; 3420 MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id); 3421 cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL); 3422 MASK_FIELD(CHIP_METAL, cdev->chip_metal); 3423 3424 DP_INFO(cdev->hwfns, 3425 "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n", 3426 QED_IS_BB(cdev) ? "BB" : "AH", 3427 'A' + cdev->chip_rev, 3428 (int)cdev->chip_metal, 3429 cdev->chip_num, cdev->chip_rev, 3430 cdev->chip_bond_id, cdev->chip_metal); 3431 3432 return 0; 3433 } 3434 3435 static void qed_nvm_info_free(struct qed_hwfn *p_hwfn) 3436 { 3437 kfree(p_hwfn->nvm_info.image_att); 3438 p_hwfn->nvm_info.image_att = NULL; 3439 } 3440 3441 static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn, 3442 void __iomem *p_regview, 3443 void __iomem *p_doorbells, 3444 enum qed_pci_personality personality) 3445 { 3446 struct qed_dev *cdev = p_hwfn->cdev; 3447 int rc = 0; 3448 3449 /* Split PCI bars evenly between hwfns */ 3450 p_hwfn->regview = p_regview; 3451 p_hwfn->doorbells = p_doorbells; 3452 3453 if (IS_VF(p_hwfn->cdev)) 3454 return qed_vf_hw_prepare(p_hwfn); 3455 3456 /* Validate that chip access is feasible */ 3457 if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) { 3458 DP_ERR(p_hwfn, 3459 "Reading the ME register returns all Fs; Preventing further chip access\n"); 3460 return -EINVAL; 3461 } 3462 3463 get_function_id(p_hwfn); 3464 3465 /* Allocate PTT pool */ 3466 rc = qed_ptt_pool_alloc(p_hwfn); 3467 if (rc) 3468 goto err0; 3469 3470 /* Allocate the main PTT */ 3471 p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN); 3472 3473 /* First hwfn learns basic information, e.g., number of hwfns */ 3474 if (!p_hwfn->my_id) { 3475 rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt); 3476 if (rc) 3477 goto err1; 3478 } 3479 3480 qed_hw_hwfn_prepare(p_hwfn); 3481 3482 /* Initialize MCP structure */ 3483 rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt); 3484 if (rc) { 3485 DP_NOTICE(p_hwfn, "Failed initializing mcp command\n"); 3486 goto err1; 3487 } 3488 3489 /* Read the device configuration information from the HW and SHMEM */ 3490 rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality); 3491 if (rc) { 3492 DP_NOTICE(p_hwfn, "Failed to get HW information\n"); 3493 goto err2; 3494 } 3495 3496 /* Sending a mailbox to the MFW should be done after qed_get_hw_info() 3497 * is called as it sets the ports number in an engine. 3498 */ 3499 if (IS_LEAD_HWFN(p_hwfn) && !cdev->recov_in_prog) { 3500 rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt); 3501 if (rc) 3502 DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n"); 3503 } 3504 3505 /* NVRAM info initialization and population */ 3506 if (IS_LEAD_HWFN(p_hwfn)) { 3507 rc = qed_mcp_nvm_info_populate(p_hwfn); 3508 if (rc) { 3509 DP_NOTICE(p_hwfn, 3510 "Failed to populate nvm info shadow\n"); 3511 goto err2; 3512 } 3513 } 3514 3515 /* Allocate the init RT array and initialize the init-ops engine */ 3516 rc = qed_init_alloc(p_hwfn); 3517 if (rc) 3518 goto err3; 3519 3520 return rc; 3521 err3: 3522 if (IS_LEAD_HWFN(p_hwfn)) 3523 qed_nvm_info_free(p_hwfn); 3524 err2: 3525 if (IS_LEAD_HWFN(p_hwfn)) 3526 qed_iov_free_hw_info(p_hwfn->cdev); 3527 qed_mcp_free(p_hwfn); 3528 err1: 3529 qed_hw_hwfn_free(p_hwfn); 3530 err0: 3531 return rc; 3532 } 3533 3534 int qed_hw_prepare(struct qed_dev *cdev, 3535 int personality) 3536 { 3537 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 3538 int rc; 3539 3540 /* Store the precompiled init data ptrs */ 3541 if (IS_PF(cdev)) 3542 qed_init_iro_array(cdev); 3543 3544 /* Initialize the first hwfn - will learn number of hwfns */ 3545 rc = qed_hw_prepare_single(p_hwfn, 3546 cdev->regview, 3547 cdev->doorbells, personality); 3548 if (rc) 3549 return rc; 3550 3551 personality = p_hwfn->hw_info.personality; 3552 3553 /* Initialize the rest of the hwfns */ 3554 if (cdev->num_hwfns > 1) { 3555 void __iomem *p_regview, *p_doorbell; 3556 u8 __iomem *addr; 3557 3558 /* adjust bar offset for second engine */ 3559 addr = cdev->regview + 3560 qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt, 3561 BAR_ID_0) / 2; 3562 p_regview = addr; 3563 3564 addr = cdev->doorbells + 3565 qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt, 3566 BAR_ID_1) / 2; 3567 p_doorbell = addr; 3568 3569 /* prepare second hw function */ 3570 rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview, 3571 p_doorbell, personality); 3572 3573 /* in case of error, need to free the previously 3574 * initiliazed hwfn 0. 3575 */ 3576 if (rc) { 3577 if (IS_PF(cdev)) { 3578 qed_init_free(p_hwfn); 3579 qed_nvm_info_free(p_hwfn); 3580 qed_mcp_free(p_hwfn); 3581 qed_hw_hwfn_free(p_hwfn); 3582 } 3583 } 3584 } 3585 3586 return rc; 3587 } 3588 3589 void qed_hw_remove(struct qed_dev *cdev) 3590 { 3591 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 3592 int i; 3593 3594 if (IS_PF(cdev)) 3595 qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt, 3596 QED_OV_DRIVER_STATE_NOT_LOADED); 3597 3598 for_each_hwfn(cdev, i) { 3599 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 3600 3601 if (IS_VF(cdev)) { 3602 qed_vf_pf_release(p_hwfn); 3603 continue; 3604 } 3605 3606 qed_init_free(p_hwfn); 3607 qed_hw_hwfn_free(p_hwfn); 3608 qed_mcp_free(p_hwfn); 3609 } 3610 3611 qed_iov_free_hw_info(cdev); 3612 3613 qed_nvm_info_free(p_hwfn); 3614 } 3615 3616 static void qed_chain_free_next_ptr(struct qed_dev *cdev, 3617 struct qed_chain *p_chain) 3618 { 3619 void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL; 3620 dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0; 3621 struct qed_chain_next *p_next; 3622 u32 size, i; 3623 3624 if (!p_virt) 3625 return; 3626 3627 size = p_chain->elem_size * p_chain->usable_per_page; 3628 3629 for (i = 0; i < p_chain->page_cnt; i++) { 3630 if (!p_virt) 3631 break; 3632 3633 p_next = (struct qed_chain_next *)((u8 *)p_virt + size); 3634 p_virt_next = p_next->next_virt; 3635 p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys); 3636 3637 dma_free_coherent(&cdev->pdev->dev, 3638 QED_CHAIN_PAGE_SIZE, p_virt, p_phys); 3639 3640 p_virt = p_virt_next; 3641 p_phys = p_phys_next; 3642 } 3643 } 3644 3645 static void qed_chain_free_single(struct qed_dev *cdev, 3646 struct qed_chain *p_chain) 3647 { 3648 if (!p_chain->p_virt_addr) 3649 return; 3650 3651 dma_free_coherent(&cdev->pdev->dev, 3652 QED_CHAIN_PAGE_SIZE, 3653 p_chain->p_virt_addr, p_chain->p_phys_addr); 3654 } 3655 3656 static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain) 3657 { 3658 void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl; 3659 u32 page_cnt = p_chain->page_cnt, i, pbl_size; 3660 u8 *p_pbl_virt = p_chain->pbl_sp.p_virt_table; 3661 3662 if (!pp_virt_addr_tbl) 3663 return; 3664 3665 if (!p_pbl_virt) 3666 goto out; 3667 3668 for (i = 0; i < page_cnt; i++) { 3669 if (!pp_virt_addr_tbl[i]) 3670 break; 3671 3672 dma_free_coherent(&cdev->pdev->dev, 3673 QED_CHAIN_PAGE_SIZE, 3674 pp_virt_addr_tbl[i], 3675 *(dma_addr_t *)p_pbl_virt); 3676 3677 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE; 3678 } 3679 3680 pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; 3681 3682 if (!p_chain->b_external_pbl) 3683 dma_free_coherent(&cdev->pdev->dev, 3684 pbl_size, 3685 p_chain->pbl_sp.p_virt_table, 3686 p_chain->pbl_sp.p_phys_table); 3687 out: 3688 vfree(p_chain->pbl.pp_virt_addr_tbl); 3689 p_chain->pbl.pp_virt_addr_tbl = NULL; 3690 } 3691 3692 void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain) 3693 { 3694 switch (p_chain->mode) { 3695 case QED_CHAIN_MODE_NEXT_PTR: 3696 qed_chain_free_next_ptr(cdev, p_chain); 3697 break; 3698 case QED_CHAIN_MODE_SINGLE: 3699 qed_chain_free_single(cdev, p_chain); 3700 break; 3701 case QED_CHAIN_MODE_PBL: 3702 qed_chain_free_pbl(cdev, p_chain); 3703 break; 3704 } 3705 } 3706 3707 static int 3708 qed_chain_alloc_sanity_check(struct qed_dev *cdev, 3709 enum qed_chain_cnt_type cnt_type, 3710 size_t elem_size, u32 page_cnt) 3711 { 3712 u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt; 3713 3714 /* The actual chain size can be larger than the maximal possible value 3715 * after rounding up the requested elements number to pages, and after 3716 * taking into acount the unusuable elements (next-ptr elements). 3717 * The size of a "u16" chain can be (U16_MAX + 1) since the chain 3718 * size/capacity fields are of a u32 type. 3719 */ 3720 if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 && 3721 chain_size > ((u32)U16_MAX + 1)) || 3722 (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) { 3723 DP_NOTICE(cdev, 3724 "The actual chain size (0x%llx) is larger than the maximal possible value\n", 3725 chain_size); 3726 return -EINVAL; 3727 } 3728 3729 return 0; 3730 } 3731 3732 static int 3733 qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain) 3734 { 3735 void *p_virt = NULL, *p_virt_prev = NULL; 3736 dma_addr_t p_phys = 0; 3737 u32 i; 3738 3739 for (i = 0; i < p_chain->page_cnt; i++) { 3740 p_virt = dma_alloc_coherent(&cdev->pdev->dev, 3741 QED_CHAIN_PAGE_SIZE, 3742 &p_phys, GFP_KERNEL); 3743 if (!p_virt) 3744 return -ENOMEM; 3745 3746 if (i == 0) { 3747 qed_chain_init_mem(p_chain, p_virt, p_phys); 3748 qed_chain_reset(p_chain); 3749 } else { 3750 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, 3751 p_virt, p_phys); 3752 } 3753 3754 p_virt_prev = p_virt; 3755 } 3756 /* Last page's next element should point to the beginning of the 3757 * chain. 3758 */ 3759 qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, 3760 p_chain->p_virt_addr, 3761 p_chain->p_phys_addr); 3762 3763 return 0; 3764 } 3765 3766 static int 3767 qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain) 3768 { 3769 dma_addr_t p_phys = 0; 3770 void *p_virt = NULL; 3771 3772 p_virt = dma_alloc_coherent(&cdev->pdev->dev, 3773 QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL); 3774 if (!p_virt) 3775 return -ENOMEM; 3776 3777 qed_chain_init_mem(p_chain, p_virt, p_phys); 3778 qed_chain_reset(p_chain); 3779 3780 return 0; 3781 } 3782 3783 static int 3784 qed_chain_alloc_pbl(struct qed_dev *cdev, 3785 struct qed_chain *p_chain, 3786 struct qed_chain_ext_pbl *ext_pbl) 3787 { 3788 u32 page_cnt = p_chain->page_cnt, size, i; 3789 dma_addr_t p_phys = 0, p_pbl_phys = 0; 3790 void **pp_virt_addr_tbl = NULL; 3791 u8 *p_pbl_virt = NULL; 3792 void *p_virt = NULL; 3793 3794 size = page_cnt * sizeof(*pp_virt_addr_tbl); 3795 pp_virt_addr_tbl = vzalloc(size); 3796 if (!pp_virt_addr_tbl) 3797 return -ENOMEM; 3798 3799 /* The allocation of the PBL table is done with its full size, since it 3800 * is expected to be successive. 3801 * qed_chain_init_pbl_mem() is called even in a case of an allocation 3802 * failure, since pp_virt_addr_tbl was previously allocated, and it 3803 * should be saved to allow its freeing during the error flow. 3804 */ 3805 size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; 3806 3807 if (!ext_pbl) { 3808 p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev, 3809 size, &p_pbl_phys, GFP_KERNEL); 3810 } else { 3811 p_pbl_virt = ext_pbl->p_pbl_virt; 3812 p_pbl_phys = ext_pbl->p_pbl_phys; 3813 p_chain->b_external_pbl = true; 3814 } 3815 3816 qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys, 3817 pp_virt_addr_tbl); 3818 if (!p_pbl_virt) 3819 return -ENOMEM; 3820 3821 for (i = 0; i < page_cnt; i++) { 3822 p_virt = dma_alloc_coherent(&cdev->pdev->dev, 3823 QED_CHAIN_PAGE_SIZE, 3824 &p_phys, GFP_KERNEL); 3825 if (!p_virt) 3826 return -ENOMEM; 3827 3828 if (i == 0) { 3829 qed_chain_init_mem(p_chain, p_virt, p_phys); 3830 qed_chain_reset(p_chain); 3831 } 3832 3833 /* Fill the PBL table with the physical address of the page */ 3834 *(dma_addr_t *)p_pbl_virt = p_phys; 3835 /* Keep the virtual address of the page */ 3836 p_chain->pbl.pp_virt_addr_tbl[i] = p_virt; 3837 3838 p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE; 3839 } 3840 3841 return 0; 3842 } 3843 3844 int qed_chain_alloc(struct qed_dev *cdev, 3845 enum qed_chain_use_mode intended_use, 3846 enum qed_chain_mode mode, 3847 enum qed_chain_cnt_type cnt_type, 3848 u32 num_elems, 3849 size_t elem_size, 3850 struct qed_chain *p_chain, 3851 struct qed_chain_ext_pbl *ext_pbl) 3852 { 3853 u32 page_cnt; 3854 int rc = 0; 3855 3856 if (mode == QED_CHAIN_MODE_SINGLE) 3857 page_cnt = 1; 3858 else 3859 page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode); 3860 3861 rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt); 3862 if (rc) { 3863 DP_NOTICE(cdev, 3864 "Cannot allocate a chain with the given arguments:\n"); 3865 DP_NOTICE(cdev, 3866 "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n", 3867 intended_use, mode, cnt_type, num_elems, elem_size); 3868 return rc; 3869 } 3870 3871 qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use, 3872 mode, cnt_type); 3873 3874 switch (mode) { 3875 case QED_CHAIN_MODE_NEXT_PTR: 3876 rc = qed_chain_alloc_next_ptr(cdev, p_chain); 3877 break; 3878 case QED_CHAIN_MODE_SINGLE: 3879 rc = qed_chain_alloc_single(cdev, p_chain); 3880 break; 3881 case QED_CHAIN_MODE_PBL: 3882 rc = qed_chain_alloc_pbl(cdev, p_chain, ext_pbl); 3883 break; 3884 } 3885 if (rc) 3886 goto nomem; 3887 3888 return 0; 3889 3890 nomem: 3891 qed_chain_free(cdev, p_chain); 3892 return rc; 3893 } 3894 3895 int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id) 3896 { 3897 if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) { 3898 u16 min, max; 3899 3900 min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE); 3901 max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE); 3902 DP_NOTICE(p_hwfn, 3903 "l2_queue id [%d] is not valid, available indices [%d - %d]\n", 3904 src_id, min, max); 3905 3906 return -EINVAL; 3907 } 3908 3909 *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id; 3910 3911 return 0; 3912 } 3913 3914 int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id) 3915 { 3916 if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) { 3917 u8 min, max; 3918 3919 min = (u8)RESC_START(p_hwfn, QED_VPORT); 3920 max = min + RESC_NUM(p_hwfn, QED_VPORT); 3921 DP_NOTICE(p_hwfn, 3922 "vport id [%d] is not valid, available indices [%d - %d]\n", 3923 src_id, min, max); 3924 3925 return -EINVAL; 3926 } 3927 3928 *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id; 3929 3930 return 0; 3931 } 3932 3933 int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id) 3934 { 3935 if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) { 3936 u8 min, max; 3937 3938 min = (u8)RESC_START(p_hwfn, QED_RSS_ENG); 3939 max = min + RESC_NUM(p_hwfn, QED_RSS_ENG); 3940 DP_NOTICE(p_hwfn, 3941 "rss_eng id [%d] is not valid, available indices [%d - %d]\n", 3942 src_id, min, max); 3943 3944 return -EINVAL; 3945 } 3946 3947 *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id; 3948 3949 return 0; 3950 } 3951 3952 static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low, 3953 u8 *p_filter) 3954 { 3955 *p_high = p_filter[1] | (p_filter[0] << 8); 3956 *p_low = p_filter[5] | (p_filter[4] << 8) | 3957 (p_filter[3] << 16) | (p_filter[2] << 24); 3958 } 3959 3960 int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn, 3961 struct qed_ptt *p_ptt, u8 *p_filter) 3962 { 3963 u32 high = 0, low = 0, en; 3964 int i; 3965 3966 if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits)) 3967 return 0; 3968 3969 qed_llh_mac_to_filter(&high, &low, p_filter); 3970 3971 /* Find a free entry and utilize it */ 3972 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 3973 en = qed_rd(p_hwfn, p_ptt, 3974 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)); 3975 if (en) 3976 continue; 3977 qed_wr(p_hwfn, p_ptt, 3978 NIG_REG_LLH_FUNC_FILTER_VALUE + 3979 2 * i * sizeof(u32), low); 3980 qed_wr(p_hwfn, p_ptt, 3981 NIG_REG_LLH_FUNC_FILTER_VALUE + 3982 (2 * i + 1) * sizeof(u32), high); 3983 qed_wr(p_hwfn, p_ptt, 3984 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0); 3985 qed_wr(p_hwfn, p_ptt, 3986 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 3987 i * sizeof(u32), 0); 3988 qed_wr(p_hwfn, p_ptt, 3989 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1); 3990 break; 3991 } 3992 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) { 3993 DP_NOTICE(p_hwfn, 3994 "Failed to find an empty LLH filter to utilize\n"); 3995 return -EINVAL; 3996 } 3997 3998 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 3999 "mac: %pM is added at %d\n", 4000 p_filter, i); 4001 4002 return 0; 4003 } 4004 4005 void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn, 4006 struct qed_ptt *p_ptt, u8 *p_filter) 4007 { 4008 u32 high = 0, low = 0; 4009 int i; 4010 4011 if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits)) 4012 return; 4013 4014 qed_llh_mac_to_filter(&high, &low, p_filter); 4015 4016 /* Find the entry and clean it */ 4017 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 4018 if (qed_rd(p_hwfn, p_ptt, 4019 NIG_REG_LLH_FUNC_FILTER_VALUE + 4020 2 * i * sizeof(u32)) != low) 4021 continue; 4022 if (qed_rd(p_hwfn, p_ptt, 4023 NIG_REG_LLH_FUNC_FILTER_VALUE + 4024 (2 * i + 1) * sizeof(u32)) != high) 4025 continue; 4026 4027 qed_wr(p_hwfn, p_ptt, 4028 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0); 4029 qed_wr(p_hwfn, p_ptt, 4030 NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0); 4031 qed_wr(p_hwfn, p_ptt, 4032 NIG_REG_LLH_FUNC_FILTER_VALUE + 4033 (2 * i + 1) * sizeof(u32), 0); 4034 4035 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 4036 "mac: %pM is removed from %d\n", 4037 p_filter, i); 4038 break; 4039 } 4040 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) 4041 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n"); 4042 } 4043 4044 int 4045 qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn, 4046 struct qed_ptt *p_ptt, 4047 u16 source_port_or_eth_type, 4048 u16 dest_port, enum qed_llh_port_filter_type_t type) 4049 { 4050 u32 high = 0, low = 0, en; 4051 int i; 4052 4053 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits)) 4054 return 0; 4055 4056 switch (type) { 4057 case QED_LLH_FILTER_ETHERTYPE: 4058 high = source_port_or_eth_type; 4059 break; 4060 case QED_LLH_FILTER_TCP_SRC_PORT: 4061 case QED_LLH_FILTER_UDP_SRC_PORT: 4062 low = source_port_or_eth_type << 16; 4063 break; 4064 case QED_LLH_FILTER_TCP_DEST_PORT: 4065 case QED_LLH_FILTER_UDP_DEST_PORT: 4066 low = dest_port; 4067 break; 4068 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 4069 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 4070 low = (source_port_or_eth_type << 16) | dest_port; 4071 break; 4072 default: 4073 DP_NOTICE(p_hwfn, 4074 "Non valid LLH protocol filter type %d\n", type); 4075 return -EINVAL; 4076 } 4077 /* Find a free entry and utilize it */ 4078 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 4079 en = qed_rd(p_hwfn, p_ptt, 4080 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)); 4081 if (en) 4082 continue; 4083 qed_wr(p_hwfn, p_ptt, 4084 NIG_REG_LLH_FUNC_FILTER_VALUE + 4085 2 * i * sizeof(u32), low); 4086 qed_wr(p_hwfn, p_ptt, 4087 NIG_REG_LLH_FUNC_FILTER_VALUE + 4088 (2 * i + 1) * sizeof(u32), high); 4089 qed_wr(p_hwfn, p_ptt, 4090 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1); 4091 qed_wr(p_hwfn, p_ptt, 4092 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 4093 i * sizeof(u32), 1 << type); 4094 qed_wr(p_hwfn, p_ptt, 4095 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1); 4096 break; 4097 } 4098 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) { 4099 DP_NOTICE(p_hwfn, 4100 "Failed to find an empty LLH filter to utilize\n"); 4101 return -EINVAL; 4102 } 4103 switch (type) { 4104 case QED_LLH_FILTER_ETHERTYPE: 4105 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 4106 "ETH type %x is added at %d\n", 4107 source_port_or_eth_type, i); 4108 break; 4109 case QED_LLH_FILTER_TCP_SRC_PORT: 4110 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 4111 "TCP src port %x is added at %d\n", 4112 source_port_or_eth_type, i); 4113 break; 4114 case QED_LLH_FILTER_UDP_SRC_PORT: 4115 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 4116 "UDP src port %x is added at %d\n", 4117 source_port_or_eth_type, i); 4118 break; 4119 case QED_LLH_FILTER_TCP_DEST_PORT: 4120 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 4121 "TCP dst port %x is added at %d\n", dest_port, i); 4122 break; 4123 case QED_LLH_FILTER_UDP_DEST_PORT: 4124 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 4125 "UDP dst port %x is added at %d\n", dest_port, i); 4126 break; 4127 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 4128 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 4129 "TCP src/dst ports %x/%x are added at %d\n", 4130 source_port_or_eth_type, dest_port, i); 4131 break; 4132 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 4133 DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 4134 "UDP src/dst ports %x/%x are added at %d\n", 4135 source_port_or_eth_type, dest_port, i); 4136 break; 4137 } 4138 return 0; 4139 } 4140 4141 void 4142 qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn, 4143 struct qed_ptt *p_ptt, 4144 u16 source_port_or_eth_type, 4145 u16 dest_port, 4146 enum qed_llh_port_filter_type_t type) 4147 { 4148 u32 high = 0, low = 0; 4149 int i; 4150 4151 if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits)) 4152 return; 4153 4154 switch (type) { 4155 case QED_LLH_FILTER_ETHERTYPE: 4156 high = source_port_or_eth_type; 4157 break; 4158 case QED_LLH_FILTER_TCP_SRC_PORT: 4159 case QED_LLH_FILTER_UDP_SRC_PORT: 4160 low = source_port_or_eth_type << 16; 4161 break; 4162 case QED_LLH_FILTER_TCP_DEST_PORT: 4163 case QED_LLH_FILTER_UDP_DEST_PORT: 4164 low = dest_port; 4165 break; 4166 case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 4167 case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 4168 low = (source_port_or_eth_type << 16) | dest_port; 4169 break; 4170 default: 4171 DP_NOTICE(p_hwfn, 4172 "Non valid LLH protocol filter type %d\n", type); 4173 return; 4174 } 4175 4176 for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 4177 if (!qed_rd(p_hwfn, p_ptt, 4178 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32))) 4179 continue; 4180 if (!qed_rd(p_hwfn, p_ptt, 4181 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32))) 4182 continue; 4183 if (!(qed_rd(p_hwfn, p_ptt, 4184 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 4185 i * sizeof(u32)) & BIT(type))) 4186 continue; 4187 if (qed_rd(p_hwfn, p_ptt, 4188 NIG_REG_LLH_FUNC_FILTER_VALUE + 4189 2 * i * sizeof(u32)) != low) 4190 continue; 4191 if (qed_rd(p_hwfn, p_ptt, 4192 NIG_REG_LLH_FUNC_FILTER_VALUE + 4193 (2 * i + 1) * sizeof(u32)) != high) 4194 continue; 4195 4196 qed_wr(p_hwfn, p_ptt, 4197 NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0); 4198 qed_wr(p_hwfn, p_ptt, 4199 NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0); 4200 qed_wr(p_hwfn, p_ptt, 4201 NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 4202 i * sizeof(u32), 0); 4203 qed_wr(p_hwfn, p_ptt, 4204 NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0); 4205 qed_wr(p_hwfn, p_ptt, 4206 NIG_REG_LLH_FUNC_FILTER_VALUE + 4207 (2 * i + 1) * sizeof(u32), 0); 4208 break; 4209 } 4210 4211 if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) 4212 DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n"); 4213 } 4214 4215 static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 4216 u32 hw_addr, void *p_eth_qzone, 4217 size_t eth_qzone_size, u8 timeset) 4218 { 4219 struct coalescing_timeset *p_coal_timeset; 4220 4221 if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) { 4222 DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n"); 4223 return -EINVAL; 4224 } 4225 4226 p_coal_timeset = p_eth_qzone; 4227 memset(p_eth_qzone, 0, eth_qzone_size); 4228 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset); 4229 SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1); 4230 qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size); 4231 4232 return 0; 4233 } 4234 4235 int qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle) 4236 { 4237 struct qed_queue_cid *p_cid = p_handle; 4238 struct qed_hwfn *p_hwfn; 4239 struct qed_ptt *p_ptt; 4240 int rc = 0; 4241 4242 p_hwfn = p_cid->p_owner; 4243 4244 if (IS_VF(p_hwfn->cdev)) 4245 return qed_vf_pf_set_coalesce(p_hwfn, rx_coal, tx_coal, p_cid); 4246 4247 p_ptt = qed_ptt_acquire(p_hwfn); 4248 if (!p_ptt) 4249 return -EAGAIN; 4250 4251 if (rx_coal) { 4252 rc = qed_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid); 4253 if (rc) 4254 goto out; 4255 p_hwfn->cdev->rx_coalesce_usecs = rx_coal; 4256 } 4257 4258 if (tx_coal) { 4259 rc = qed_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid); 4260 if (rc) 4261 goto out; 4262 p_hwfn->cdev->tx_coalesce_usecs = tx_coal; 4263 } 4264 out: 4265 qed_ptt_release(p_hwfn, p_ptt); 4266 return rc; 4267 } 4268 4269 int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, 4270 struct qed_ptt *p_ptt, 4271 u16 coalesce, struct qed_queue_cid *p_cid) 4272 { 4273 struct ustorm_eth_queue_zone eth_qzone; 4274 u8 timeset, timer_res; 4275 u32 address; 4276 int rc; 4277 4278 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 4279 if (coalesce <= 0x7F) { 4280 timer_res = 0; 4281 } else if (coalesce <= 0xFF) { 4282 timer_res = 1; 4283 } else if (coalesce <= 0x1FF) { 4284 timer_res = 2; 4285 } else { 4286 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 4287 return -EINVAL; 4288 } 4289 timeset = (u8)(coalesce >> timer_res); 4290 4291 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, 4292 p_cid->sb_igu_id, false); 4293 if (rc) 4294 goto out; 4295 4296 address = BAR0_MAP_REG_USDM_RAM + 4297 USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id); 4298 4299 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 4300 sizeof(struct ustorm_eth_queue_zone), timeset); 4301 if (rc) 4302 goto out; 4303 4304 out: 4305 return rc; 4306 } 4307 4308 int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, 4309 struct qed_ptt *p_ptt, 4310 u16 coalesce, struct qed_queue_cid *p_cid) 4311 { 4312 struct xstorm_eth_queue_zone eth_qzone; 4313 u8 timeset, timer_res; 4314 u32 address; 4315 int rc; 4316 4317 /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 4318 if (coalesce <= 0x7F) { 4319 timer_res = 0; 4320 } else if (coalesce <= 0xFF) { 4321 timer_res = 1; 4322 } else if (coalesce <= 0x1FF) { 4323 timer_res = 2; 4324 } else { 4325 DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 4326 return -EINVAL; 4327 } 4328 timeset = (u8)(coalesce >> timer_res); 4329 4330 rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, 4331 p_cid->sb_igu_id, true); 4332 if (rc) 4333 goto out; 4334 4335 address = BAR0_MAP_REG_XSDM_RAM + 4336 XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id); 4337 4338 rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 4339 sizeof(struct xstorm_eth_queue_zone), timeset); 4340 out: 4341 return rc; 4342 } 4343 4344 /* Calculate final WFQ values for all vports and configure them. 4345 * After this configuration each vport will have 4346 * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT) 4347 */ 4348 static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 4349 struct qed_ptt *p_ptt, 4350 u32 min_pf_rate) 4351 { 4352 struct init_qm_vport_params *vport_params; 4353 int i; 4354 4355 vport_params = p_hwfn->qm_info.qm_vport_params; 4356 4357 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 4358 u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 4359 4360 vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) / 4361 min_pf_rate; 4362 qed_init_vport_wfq(p_hwfn, p_ptt, 4363 vport_params[i].first_tx_pq_id, 4364 vport_params[i].vport_wfq); 4365 } 4366 } 4367 4368 static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn, 4369 u32 min_pf_rate) 4370 4371 { 4372 int i; 4373 4374 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) 4375 p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1; 4376 } 4377 4378 static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 4379 struct qed_ptt *p_ptt, 4380 u32 min_pf_rate) 4381 { 4382 struct init_qm_vport_params *vport_params; 4383 int i; 4384 4385 vport_params = p_hwfn->qm_info.qm_vport_params; 4386 4387 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 4388 qed_init_wfq_default_param(p_hwfn, min_pf_rate); 4389 qed_init_vport_wfq(p_hwfn, p_ptt, 4390 vport_params[i].first_tx_pq_id, 4391 vport_params[i].vport_wfq); 4392 } 4393 } 4394 4395 /* This function performs several validations for WFQ 4396 * configuration and required min rate for a given vport 4397 * 1. req_rate must be greater than one percent of min_pf_rate. 4398 * 2. req_rate should not cause other vports [not configured for WFQ explicitly] 4399 * rates to get less than one percent of min_pf_rate. 4400 * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate. 4401 */ 4402 static int qed_init_wfq_param(struct qed_hwfn *p_hwfn, 4403 u16 vport_id, u32 req_rate, u32 min_pf_rate) 4404 { 4405 u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0; 4406 int non_requested_count = 0, req_count = 0, i, num_vports; 4407 4408 num_vports = p_hwfn->qm_info.num_vports; 4409 4410 /* Accounting for the vports which are configured for WFQ explicitly */ 4411 for (i = 0; i < num_vports; i++) { 4412 u32 tmp_speed; 4413 4414 if ((i != vport_id) && 4415 p_hwfn->qm_info.wfq_data[i].configured) { 4416 req_count++; 4417 tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 4418 total_req_min_rate += tmp_speed; 4419 } 4420 } 4421 4422 /* Include current vport data as well */ 4423 req_count++; 4424 total_req_min_rate += req_rate; 4425 non_requested_count = num_vports - req_count; 4426 4427 if (req_rate < min_pf_rate / QED_WFQ_UNIT) { 4428 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 4429 "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 4430 vport_id, req_rate, min_pf_rate); 4431 return -EINVAL; 4432 } 4433 4434 if (num_vports > QED_WFQ_UNIT) { 4435 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 4436 "Number of vports is greater than %d\n", 4437 QED_WFQ_UNIT); 4438 return -EINVAL; 4439 } 4440 4441 if (total_req_min_rate > min_pf_rate) { 4442 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 4443 "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n", 4444 total_req_min_rate, min_pf_rate); 4445 return -EINVAL; 4446 } 4447 4448 total_left_rate = min_pf_rate - total_req_min_rate; 4449 4450 left_rate_per_vp = total_left_rate / non_requested_count; 4451 if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) { 4452 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 4453 "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 4454 left_rate_per_vp, min_pf_rate); 4455 return -EINVAL; 4456 } 4457 4458 p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate; 4459 p_hwfn->qm_info.wfq_data[vport_id].configured = true; 4460 4461 for (i = 0; i < num_vports; i++) { 4462 if (p_hwfn->qm_info.wfq_data[i].configured) 4463 continue; 4464 4465 p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp; 4466 } 4467 4468 return 0; 4469 } 4470 4471 static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn, 4472 struct qed_ptt *p_ptt, u16 vp_id, u32 rate) 4473 { 4474 struct qed_mcp_link_state *p_link; 4475 int rc = 0; 4476 4477 p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output; 4478 4479 if (!p_link->min_pf_rate) { 4480 p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate; 4481 p_hwfn->qm_info.wfq_data[vp_id].configured = true; 4482 return rc; 4483 } 4484 4485 rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate); 4486 4487 if (!rc) 4488 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, 4489 p_link->min_pf_rate); 4490 else 4491 DP_NOTICE(p_hwfn, 4492 "Validation failed while configuring min rate\n"); 4493 4494 return rc; 4495 } 4496 4497 static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn, 4498 struct qed_ptt *p_ptt, 4499 u32 min_pf_rate) 4500 { 4501 bool use_wfq = false; 4502 int rc = 0; 4503 u16 i; 4504 4505 /* Validate all pre configured vports for wfq */ 4506 for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 4507 u32 rate; 4508 4509 if (!p_hwfn->qm_info.wfq_data[i].configured) 4510 continue; 4511 4512 rate = p_hwfn->qm_info.wfq_data[i].min_speed; 4513 use_wfq = true; 4514 4515 rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate); 4516 if (rc) { 4517 DP_NOTICE(p_hwfn, 4518 "WFQ validation failed while configuring min rate\n"); 4519 break; 4520 } 4521 } 4522 4523 if (!rc && use_wfq) 4524 qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 4525 else 4526 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 4527 4528 return rc; 4529 } 4530 4531 /* Main API for qed clients to configure vport min rate. 4532 * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)] 4533 * rate - Speed in Mbps needs to be assigned to a given vport. 4534 */ 4535 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate) 4536 { 4537 int i, rc = -EINVAL; 4538 4539 /* Currently not supported; Might change in future */ 4540 if (cdev->num_hwfns > 1) { 4541 DP_NOTICE(cdev, 4542 "WFQ configuration is not supported for this device\n"); 4543 return rc; 4544 } 4545 4546 for_each_hwfn(cdev, i) { 4547 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 4548 struct qed_ptt *p_ptt; 4549 4550 p_ptt = qed_ptt_acquire(p_hwfn); 4551 if (!p_ptt) 4552 return -EBUSY; 4553 4554 rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate); 4555 4556 if (rc) { 4557 qed_ptt_release(p_hwfn, p_ptt); 4558 return rc; 4559 } 4560 4561 qed_ptt_release(p_hwfn, p_ptt); 4562 } 4563 4564 return rc; 4565 } 4566 4567 /* API to configure WFQ from mcp link change */ 4568 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, 4569 struct qed_ptt *p_ptt, u32 min_pf_rate) 4570 { 4571 int i; 4572 4573 if (cdev->num_hwfns > 1) { 4574 DP_VERBOSE(cdev, 4575 NETIF_MSG_LINK, 4576 "WFQ configuration is not supported for this device\n"); 4577 return; 4578 } 4579 4580 for_each_hwfn(cdev, i) { 4581 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 4582 4583 __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt, 4584 min_pf_rate); 4585 } 4586 } 4587 4588 int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn, 4589 struct qed_ptt *p_ptt, 4590 struct qed_mcp_link_state *p_link, 4591 u8 max_bw) 4592 { 4593 int rc = 0; 4594 4595 p_hwfn->mcp_info->func_info.bandwidth_max = max_bw; 4596 4597 if (!p_link->line_speed && (max_bw != 100)) 4598 return rc; 4599 4600 p_link->speed = (p_link->line_speed * max_bw) / 100; 4601 p_hwfn->qm_info.pf_rl = p_link->speed; 4602 4603 /* Since the limiter also affects Tx-switched traffic, we don't want it 4604 * to limit such traffic in case there's no actual limit. 4605 * In that case, set limit to imaginary high boundary. 4606 */ 4607 if (max_bw == 100) 4608 p_hwfn->qm_info.pf_rl = 100000; 4609 4610 rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, 4611 p_hwfn->qm_info.pf_rl); 4612 4613 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 4614 "Configured MAX bandwidth to be %08x Mb/sec\n", 4615 p_link->speed); 4616 4617 return rc; 4618 } 4619 4620 /* Main API to configure PF max bandwidth where bw range is [1 - 100] */ 4621 int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw) 4622 { 4623 int i, rc = -EINVAL; 4624 4625 if (max_bw < 1 || max_bw > 100) { 4626 DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n"); 4627 return rc; 4628 } 4629 4630 for_each_hwfn(cdev, i) { 4631 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 4632 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 4633 struct qed_mcp_link_state *p_link; 4634 struct qed_ptt *p_ptt; 4635 4636 p_link = &p_lead->mcp_info->link_output; 4637 4638 p_ptt = qed_ptt_acquire(p_hwfn); 4639 if (!p_ptt) 4640 return -EBUSY; 4641 4642 rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, 4643 p_link, max_bw); 4644 4645 qed_ptt_release(p_hwfn, p_ptt); 4646 4647 if (rc) 4648 break; 4649 } 4650 4651 return rc; 4652 } 4653 4654 int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn, 4655 struct qed_ptt *p_ptt, 4656 struct qed_mcp_link_state *p_link, 4657 u8 min_bw) 4658 { 4659 int rc = 0; 4660 4661 p_hwfn->mcp_info->func_info.bandwidth_min = min_bw; 4662 p_hwfn->qm_info.pf_wfq = min_bw; 4663 4664 if (!p_link->line_speed) 4665 return rc; 4666 4667 p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100; 4668 4669 rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw); 4670 4671 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 4672 "Configured MIN bandwidth to be %d Mb/sec\n", 4673 p_link->min_pf_rate); 4674 4675 return rc; 4676 } 4677 4678 /* Main API to configure PF min bandwidth where bw range is [1-100] */ 4679 int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw) 4680 { 4681 int i, rc = -EINVAL; 4682 4683 if (min_bw < 1 || min_bw > 100) { 4684 DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n"); 4685 return rc; 4686 } 4687 4688 for_each_hwfn(cdev, i) { 4689 struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 4690 struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 4691 struct qed_mcp_link_state *p_link; 4692 struct qed_ptt *p_ptt; 4693 4694 p_link = &p_lead->mcp_info->link_output; 4695 4696 p_ptt = qed_ptt_acquire(p_hwfn); 4697 if (!p_ptt) 4698 return -EBUSY; 4699 4700 rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, 4701 p_link, min_bw); 4702 if (rc) { 4703 qed_ptt_release(p_hwfn, p_ptt); 4704 return rc; 4705 } 4706 4707 if (p_link->min_pf_rate) { 4708 u32 min_rate = p_link->min_pf_rate; 4709 4710 rc = __qed_configure_vp_wfq_on_link_change(p_hwfn, 4711 p_ptt, 4712 min_rate); 4713 } 4714 4715 qed_ptt_release(p_hwfn, p_ptt); 4716 } 4717 4718 return rc; 4719 } 4720 4721 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 4722 { 4723 struct qed_mcp_link_state *p_link; 4724 4725 p_link = &p_hwfn->mcp_info->link_output; 4726 4727 if (p_link->min_pf_rate) 4728 qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, 4729 p_link->min_pf_rate); 4730 4731 memset(p_hwfn->qm_info.wfq_data, 0, 4732 sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports); 4733 } 4734 4735 int qed_device_num_ports(struct qed_dev *cdev) 4736 { 4737 return cdev->num_ports; 4738 } 4739 4740 void qed_set_fw_mac_addr(__le16 *fw_msb, 4741 __le16 *fw_mid, __le16 *fw_lsb, u8 *mac) 4742 { 4743 ((u8 *)fw_msb)[0] = mac[1]; 4744 ((u8 *)fw_msb)[1] = mac[0]; 4745 ((u8 *)fw_mid)[0] = mac[3]; 4746 ((u8 *)fw_mid)[1] = mac[2]; 4747 ((u8 *)fw_lsb)[0] = mac[5]; 4748 ((u8 *)fw_lsb)[1] = mac[4]; 4749 } 4750