1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2fe56b9e6SYuval Mintz * Copyright (c) 2015 QLogic Corporation 3fe56b9e6SYuval Mintz * 4fe56b9e6SYuval Mintz * This software is available under the terms of the GNU General Public License 5fe56b9e6SYuval Mintz * (GPL) Version 2, available from the file COPYING in the main directory of 6fe56b9e6SYuval Mintz * this source tree. 7fe56b9e6SYuval Mintz */ 8fe56b9e6SYuval Mintz 9fe56b9e6SYuval Mintz #include <linux/types.h> 10fe56b9e6SYuval Mintz #include <asm/byteorder.h> 11fe56b9e6SYuval Mintz #include <linux/io.h> 12fe56b9e6SYuval Mintz #include <linux/delay.h> 13fe56b9e6SYuval Mintz #include <linux/dma-mapping.h> 14fe56b9e6SYuval Mintz #include <linux/errno.h> 15fe56b9e6SYuval Mintz #include <linux/kernel.h> 16fe56b9e6SYuval Mintz #include <linux/mutex.h> 17fe56b9e6SYuval Mintz #include <linux/pci.h> 18fe56b9e6SYuval Mintz #include <linux/slab.h> 19fe56b9e6SYuval Mintz #include <linux/string.h> 20a91eb52aSYuval Mintz #include <linux/vmalloc.h> 21fe56b9e6SYuval Mintz #include <linux/etherdevice.h> 22fe56b9e6SYuval Mintz #include <linux/qed/qed_chain.h> 23fe56b9e6SYuval Mintz #include <linux/qed/qed_if.h> 24fe56b9e6SYuval Mintz #include "qed.h" 25fe56b9e6SYuval Mintz #include "qed_cxt.h" 2639651abdSSudarsana Reddy Kalluru #include "qed_dcbx.h" 27fe56b9e6SYuval Mintz #include "qed_dev_api.h" 28fe56b9e6SYuval Mintz #include "qed_hsi.h" 29fe56b9e6SYuval Mintz #include "qed_hw.h" 30fe56b9e6SYuval Mintz #include "qed_init_ops.h" 31fe56b9e6SYuval Mintz #include "qed_int.h" 32fe56b9e6SYuval Mintz #include "qed_mcp.h" 33fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 34fe56b9e6SYuval Mintz #include "qed_sp.h" 3532a47e72SYuval Mintz #include "qed_sriov.h" 360b55e27dSYuval Mintz #include "qed_vf.h" 37fe56b9e6SYuval Mintz 3839651abdSSudarsana Reddy Kalluru static spinlock_t qm_lock; 3939651abdSSudarsana Reddy Kalluru static bool qm_lock_init = false; 4039651abdSSudarsana Reddy Kalluru 41fe56b9e6SYuval Mintz /* API common to all protocols */ 42c2035eeaSRam Amrani enum BAR_ID { 43c2035eeaSRam Amrani BAR_ID_0, /* used for GRC */ 44c2035eeaSRam Amrani BAR_ID_1 /* Used for doorbells */ 45c2035eeaSRam Amrani }; 46c2035eeaSRam Amrani 47c2035eeaSRam Amrani static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, 48c2035eeaSRam Amrani enum BAR_ID bar_id) 49c2035eeaSRam Amrani { 50c2035eeaSRam Amrani u32 bar_reg = (bar_id == BAR_ID_0 ? 51c2035eeaSRam Amrani PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE); 521408cc1fSYuval Mintz u32 val; 53c2035eeaSRam Amrani 541408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 551408cc1fSYuval Mintz return 1 << 17; 561408cc1fSYuval Mintz 571408cc1fSYuval Mintz val = qed_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg); 58c2035eeaSRam Amrani if (val) 59c2035eeaSRam Amrani return 1 << (val + 15); 60c2035eeaSRam Amrani 61c2035eeaSRam Amrani /* Old MFW initialized above registered only conditionally */ 62c2035eeaSRam Amrani if (p_hwfn->cdev->num_hwfns > 1) { 63c2035eeaSRam Amrani DP_INFO(p_hwfn, 64c2035eeaSRam Amrani "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n"); 65c2035eeaSRam Amrani return BAR_ID_0 ? 256 * 1024 : 512 * 1024; 66c2035eeaSRam Amrani } else { 67c2035eeaSRam Amrani DP_INFO(p_hwfn, 68c2035eeaSRam Amrani "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n"); 69c2035eeaSRam Amrani return 512 * 1024; 70c2035eeaSRam Amrani } 71c2035eeaSRam Amrani } 72c2035eeaSRam Amrani 73fe56b9e6SYuval Mintz void qed_init_dp(struct qed_dev *cdev, 74fe56b9e6SYuval Mintz u32 dp_module, u8 dp_level) 75fe56b9e6SYuval Mintz { 76fe56b9e6SYuval Mintz u32 i; 77fe56b9e6SYuval Mintz 78fe56b9e6SYuval Mintz cdev->dp_level = dp_level; 79fe56b9e6SYuval Mintz cdev->dp_module = dp_module; 80fe56b9e6SYuval Mintz for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 81fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 82fe56b9e6SYuval Mintz 83fe56b9e6SYuval Mintz p_hwfn->dp_level = dp_level; 84fe56b9e6SYuval Mintz p_hwfn->dp_module = dp_module; 85fe56b9e6SYuval Mintz } 86fe56b9e6SYuval Mintz } 87fe56b9e6SYuval Mintz 88fe56b9e6SYuval Mintz void qed_init_struct(struct qed_dev *cdev) 89fe56b9e6SYuval Mintz { 90fe56b9e6SYuval Mintz u8 i; 91fe56b9e6SYuval Mintz 92fe56b9e6SYuval Mintz for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 93fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 94fe56b9e6SYuval Mintz 95fe56b9e6SYuval Mintz p_hwfn->cdev = cdev; 96fe56b9e6SYuval Mintz p_hwfn->my_id = i; 97fe56b9e6SYuval Mintz p_hwfn->b_active = false; 98fe56b9e6SYuval Mintz 99fe56b9e6SYuval Mintz mutex_init(&p_hwfn->dmae_info.mutex); 100fe56b9e6SYuval Mintz } 101fe56b9e6SYuval Mintz 102fe56b9e6SYuval Mintz /* hwfn 0 is always active */ 103fe56b9e6SYuval Mintz cdev->hwfns[0].b_active = true; 104fe56b9e6SYuval Mintz 105fe56b9e6SYuval Mintz /* set the default cache alignment to 128 */ 106fe56b9e6SYuval Mintz cdev->cache_shift = 7; 107fe56b9e6SYuval Mintz } 108fe56b9e6SYuval Mintz 109fe56b9e6SYuval Mintz static void qed_qm_info_free(struct qed_hwfn *p_hwfn) 110fe56b9e6SYuval Mintz { 111fe56b9e6SYuval Mintz struct qed_qm_info *qm_info = &p_hwfn->qm_info; 112fe56b9e6SYuval Mintz 113fe56b9e6SYuval Mintz kfree(qm_info->qm_pq_params); 114fe56b9e6SYuval Mintz qm_info->qm_pq_params = NULL; 115fe56b9e6SYuval Mintz kfree(qm_info->qm_vport_params); 116fe56b9e6SYuval Mintz qm_info->qm_vport_params = NULL; 117fe56b9e6SYuval Mintz kfree(qm_info->qm_port_params); 118fe56b9e6SYuval Mintz qm_info->qm_port_params = NULL; 119bcd197c8SManish Chopra kfree(qm_info->wfq_data); 120bcd197c8SManish Chopra qm_info->wfq_data = NULL; 121fe56b9e6SYuval Mintz } 122fe56b9e6SYuval Mintz 123fe56b9e6SYuval Mintz void qed_resc_free(struct qed_dev *cdev) 124fe56b9e6SYuval Mintz { 125fe56b9e6SYuval Mintz int i; 126fe56b9e6SYuval Mintz 1271408cc1fSYuval Mintz if (IS_VF(cdev)) 1281408cc1fSYuval Mintz return; 1291408cc1fSYuval Mintz 130fe56b9e6SYuval Mintz kfree(cdev->fw_data); 131fe56b9e6SYuval Mintz cdev->fw_data = NULL; 132fe56b9e6SYuval Mintz 133fe56b9e6SYuval Mintz kfree(cdev->reset_stats); 134fe56b9e6SYuval Mintz 135fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 136fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 137fe56b9e6SYuval Mintz 13825c089d7SYuval Mintz kfree(p_hwfn->p_tx_cids); 13925c089d7SYuval Mintz p_hwfn->p_tx_cids = NULL; 14025c089d7SYuval Mintz kfree(p_hwfn->p_rx_cids); 14125c089d7SYuval Mintz p_hwfn->p_rx_cids = NULL; 14225c089d7SYuval Mintz } 14325c089d7SYuval Mintz 14425c089d7SYuval Mintz for_each_hwfn(cdev, i) { 14525c089d7SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 14625c089d7SYuval Mintz 147fe56b9e6SYuval Mintz qed_cxt_mngr_free(p_hwfn); 148fe56b9e6SYuval Mintz qed_qm_info_free(p_hwfn); 149fe56b9e6SYuval Mintz qed_spq_free(p_hwfn); 150fe56b9e6SYuval Mintz qed_eq_free(p_hwfn, p_hwfn->p_eq); 151fe56b9e6SYuval Mintz qed_consq_free(p_hwfn, p_hwfn->p_consq); 152fe56b9e6SYuval Mintz qed_int_free(p_hwfn); 15332a47e72SYuval Mintz qed_iov_free(p_hwfn); 154fe56b9e6SYuval Mintz qed_dmae_info_free(p_hwfn); 15539651abdSSudarsana Reddy Kalluru qed_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info); 156fe56b9e6SYuval Mintz } 157fe56b9e6SYuval Mintz } 158fe56b9e6SYuval Mintz 15979529291SSudarsana Reddy Kalluru static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable) 160fe56b9e6SYuval Mintz { 1611408cc1fSYuval Mintz u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue = 0; 162fe56b9e6SYuval Mintz struct qed_qm_info *qm_info = &p_hwfn->qm_info; 163fe56b9e6SYuval Mintz struct init_qm_port_params *p_qm_port; 164fe56b9e6SYuval Mintz u16 num_pqs, multi_cos_tcs = 1; 165cc3d5eb0SYuval Mintz u8 pf_wfq = qm_info->pf_wfq; 166cc3d5eb0SYuval Mintz u32 pf_rl = qm_info->pf_rl; 1671408cc1fSYuval Mintz u16 num_vfs = 0; 168fe56b9e6SYuval Mintz 1691408cc1fSYuval Mintz #ifdef CONFIG_QED_SRIOV 1701408cc1fSYuval Mintz if (p_hwfn->cdev->p_iov_info) 1711408cc1fSYuval Mintz num_vfs = p_hwfn->cdev->p_iov_info->total_vfs; 1721408cc1fSYuval Mintz #endif 173fe56b9e6SYuval Mintz memset(qm_info, 0, sizeof(*qm_info)); 174fe56b9e6SYuval Mintz 1751408cc1fSYuval Mintz num_pqs = multi_cos_tcs + num_vfs + 1; /* The '1' is for pure-LB */ 176fe56b9e6SYuval Mintz num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT); 177fe56b9e6SYuval Mintz 178fe56b9e6SYuval Mintz /* Sanity checking that setup requires legal number of resources */ 179fe56b9e6SYuval Mintz if (num_pqs > RESC_NUM(p_hwfn, QED_PQ)) { 180fe56b9e6SYuval Mintz DP_ERR(p_hwfn, 181fe56b9e6SYuval Mintz "Need too many Physical queues - 0x%04x when only %04x are available\n", 182fe56b9e6SYuval Mintz num_pqs, RESC_NUM(p_hwfn, QED_PQ)); 183fe56b9e6SYuval Mintz return -EINVAL; 184fe56b9e6SYuval Mintz } 185fe56b9e6SYuval Mintz 186fe56b9e6SYuval Mintz /* PQs will be arranged as follows: First per-TC PQ then pure-LB quete. 187fe56b9e6SYuval Mintz */ 18879529291SSudarsana Reddy Kalluru qm_info->qm_pq_params = kcalloc(num_pqs, 18979529291SSudarsana Reddy Kalluru sizeof(struct init_qm_pq_params), 19079529291SSudarsana Reddy Kalluru b_sleepable ? GFP_KERNEL : GFP_ATOMIC); 191fe56b9e6SYuval Mintz if (!qm_info->qm_pq_params) 192fe56b9e6SYuval Mintz goto alloc_err; 193fe56b9e6SYuval Mintz 19479529291SSudarsana Reddy Kalluru qm_info->qm_vport_params = kcalloc(num_vports, 19579529291SSudarsana Reddy Kalluru sizeof(struct init_qm_vport_params), 19679529291SSudarsana Reddy Kalluru b_sleepable ? GFP_KERNEL 19779529291SSudarsana Reddy Kalluru : GFP_ATOMIC); 198fe56b9e6SYuval Mintz if (!qm_info->qm_vport_params) 199fe56b9e6SYuval Mintz goto alloc_err; 200fe56b9e6SYuval Mintz 20179529291SSudarsana Reddy Kalluru qm_info->qm_port_params = kcalloc(MAX_NUM_PORTS, 20279529291SSudarsana Reddy Kalluru sizeof(struct init_qm_port_params), 20379529291SSudarsana Reddy Kalluru b_sleepable ? GFP_KERNEL 20479529291SSudarsana Reddy Kalluru : GFP_ATOMIC); 205fe56b9e6SYuval Mintz if (!qm_info->qm_port_params) 206fe56b9e6SYuval Mintz goto alloc_err; 207fe56b9e6SYuval Mintz 20879529291SSudarsana Reddy Kalluru qm_info->wfq_data = kcalloc(num_vports, sizeof(struct qed_wfq_data), 20979529291SSudarsana Reddy Kalluru b_sleepable ? GFP_KERNEL : GFP_ATOMIC); 210bcd197c8SManish Chopra if (!qm_info->wfq_data) 211bcd197c8SManish Chopra goto alloc_err; 212bcd197c8SManish Chopra 213fe56b9e6SYuval Mintz vport_id = (u8)RESC_START(p_hwfn, QED_VPORT); 214fe56b9e6SYuval Mintz 215fe56b9e6SYuval Mintz /* First init per-TC PQs */ 21639651abdSSudarsana Reddy Kalluru for (i = 0; i < multi_cos_tcs; i++) { 2171408cc1fSYuval Mintz struct init_qm_pq_params *params = 21839651abdSSudarsana Reddy Kalluru &qm_info->qm_pq_params[curr_queue++]; 219fe56b9e6SYuval Mintz 22039651abdSSudarsana Reddy Kalluru if (p_hwfn->hw_info.personality == QED_PCI_ETH) { 221fe56b9e6SYuval Mintz params->vport_id = vport_id; 222fe56b9e6SYuval Mintz params->tc_id = p_hwfn->hw_info.non_offload_tc; 223fe56b9e6SYuval Mintz params->wrr_group = 1; 22439651abdSSudarsana Reddy Kalluru } else { 22539651abdSSudarsana Reddy Kalluru params->vport_id = vport_id; 22639651abdSSudarsana Reddy Kalluru params->tc_id = p_hwfn->hw_info.offload_tc; 22739651abdSSudarsana Reddy Kalluru params->wrr_group = 1; 22839651abdSSudarsana Reddy Kalluru } 229fe56b9e6SYuval Mintz } 230fe56b9e6SYuval Mintz 231fe56b9e6SYuval Mintz /* Then init pure-LB PQ */ 2321408cc1fSYuval Mintz qm_info->pure_lb_pq = curr_queue; 2331408cc1fSYuval Mintz qm_info->qm_pq_params[curr_queue].vport_id = 2341408cc1fSYuval Mintz (u8) RESC_START(p_hwfn, QED_VPORT); 2351408cc1fSYuval Mintz qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC; 2361408cc1fSYuval Mintz qm_info->qm_pq_params[curr_queue].wrr_group = 1; 2371408cc1fSYuval Mintz curr_queue++; 238fe56b9e6SYuval Mintz 239fe56b9e6SYuval Mintz qm_info->offload_pq = 0; 2401408cc1fSYuval Mintz /* Then init per-VF PQs */ 2411408cc1fSYuval Mintz vf_offset = curr_queue; 2421408cc1fSYuval Mintz for (i = 0; i < num_vfs; i++) { 2431408cc1fSYuval Mintz /* First vport is used by the PF */ 2441408cc1fSYuval Mintz qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1; 2451408cc1fSYuval Mintz qm_info->qm_pq_params[curr_queue].tc_id = 2461408cc1fSYuval Mintz p_hwfn->hw_info.non_offload_tc; 2471408cc1fSYuval Mintz qm_info->qm_pq_params[curr_queue].wrr_group = 1; 248351a4dedSYuval Mintz qm_info->qm_pq_params[curr_queue].rl_valid = 1; 2491408cc1fSYuval Mintz curr_queue++; 2501408cc1fSYuval Mintz } 2511408cc1fSYuval Mintz 2521408cc1fSYuval Mintz qm_info->vf_queues_offset = vf_offset; 253fe56b9e6SYuval Mintz qm_info->num_pqs = num_pqs; 254fe56b9e6SYuval Mintz qm_info->num_vports = num_vports; 255fe56b9e6SYuval Mintz 256fe56b9e6SYuval Mintz /* Initialize qm port parameters */ 257fe56b9e6SYuval Mintz num_ports = p_hwfn->cdev->num_ports_in_engines; 258fe56b9e6SYuval Mintz for (i = 0; i < num_ports; i++) { 259fe56b9e6SYuval Mintz p_qm_port = &qm_info->qm_port_params[i]; 260fe56b9e6SYuval Mintz p_qm_port->active = 1; 261351a4dedSYuval Mintz if (num_ports == 4) 262351a4dedSYuval Mintz p_qm_port->active_phys_tcs = 0x7; 263351a4dedSYuval Mintz else 264351a4dedSYuval Mintz p_qm_port->active_phys_tcs = 0x9f; 265fe56b9e6SYuval Mintz p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports; 266fe56b9e6SYuval Mintz p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports; 267fe56b9e6SYuval Mintz } 268fe56b9e6SYuval Mintz 269fe56b9e6SYuval Mintz qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS; 270fe56b9e6SYuval Mintz 271fe56b9e6SYuval Mintz qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ); 272fe56b9e6SYuval Mintz 2731408cc1fSYuval Mintz qm_info->num_vf_pqs = num_vfs; 274fe56b9e6SYuval Mintz qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT); 275fe56b9e6SYuval Mintz 276a64b02d5SManish Chopra for (i = 0; i < qm_info->num_vports; i++) 277a64b02d5SManish Chopra qm_info->qm_vport_params[i].vport_wfq = 1; 278a64b02d5SManish Chopra 279fe56b9e6SYuval Mintz qm_info->vport_rl_en = 1; 280a64b02d5SManish Chopra qm_info->vport_wfq_en = 1; 281cc3d5eb0SYuval Mintz qm_info->pf_rl = pf_rl; 282cc3d5eb0SYuval Mintz qm_info->pf_wfq = pf_wfq; 283fe56b9e6SYuval Mintz 284fe56b9e6SYuval Mintz return 0; 285fe56b9e6SYuval Mintz 286fe56b9e6SYuval Mintz alloc_err: 287fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n"); 288bcd197c8SManish Chopra qed_qm_info_free(p_hwfn); 289fe56b9e6SYuval Mintz return -ENOMEM; 290fe56b9e6SYuval Mintz } 291fe56b9e6SYuval Mintz 29239651abdSSudarsana Reddy Kalluru /* This function reconfigures the QM pf on the fly. 29339651abdSSudarsana Reddy Kalluru * For this purpose we: 29439651abdSSudarsana Reddy Kalluru * 1. reconfigure the QM database 29539651abdSSudarsana Reddy Kalluru * 2. set new values to runtime arrat 29639651abdSSudarsana Reddy Kalluru * 3. send an sdm_qm_cmd through the rbc interface to stop the QM 29739651abdSSudarsana Reddy Kalluru * 4. activate init tool in QM_PF stage 29839651abdSSudarsana Reddy Kalluru * 5. send an sdm_qm_cmd through rbc interface to release the QM 29939651abdSSudarsana Reddy Kalluru */ 30039651abdSSudarsana Reddy Kalluru int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 30139651abdSSudarsana Reddy Kalluru { 30239651abdSSudarsana Reddy Kalluru struct qed_qm_info *qm_info = &p_hwfn->qm_info; 30339651abdSSudarsana Reddy Kalluru bool b_rc; 30439651abdSSudarsana Reddy Kalluru int rc; 30539651abdSSudarsana Reddy Kalluru 30639651abdSSudarsana Reddy Kalluru /* qm_info is allocated in qed_init_qm_info() which is already called 30739651abdSSudarsana Reddy Kalluru * from qed_resc_alloc() or previous call of qed_qm_reconf(). 30839651abdSSudarsana Reddy Kalluru * The allocated size may change each init, so we free it before next 30939651abdSSudarsana Reddy Kalluru * allocation. 31039651abdSSudarsana Reddy Kalluru */ 31139651abdSSudarsana Reddy Kalluru qed_qm_info_free(p_hwfn); 31239651abdSSudarsana Reddy Kalluru 31339651abdSSudarsana Reddy Kalluru /* initialize qed's qm data structure */ 31479529291SSudarsana Reddy Kalluru rc = qed_init_qm_info(p_hwfn, false); 31539651abdSSudarsana Reddy Kalluru if (rc) 31639651abdSSudarsana Reddy Kalluru return rc; 31739651abdSSudarsana Reddy Kalluru 31839651abdSSudarsana Reddy Kalluru /* stop PF's qm queues */ 31939651abdSSudarsana Reddy Kalluru spin_lock_bh(&qm_lock); 32039651abdSSudarsana Reddy Kalluru b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true, 32139651abdSSudarsana Reddy Kalluru qm_info->start_pq, qm_info->num_pqs); 32239651abdSSudarsana Reddy Kalluru spin_unlock_bh(&qm_lock); 32339651abdSSudarsana Reddy Kalluru if (!b_rc) 32439651abdSSudarsana Reddy Kalluru return -EINVAL; 32539651abdSSudarsana Reddy Kalluru 32639651abdSSudarsana Reddy Kalluru /* clear the QM_PF runtime phase leftovers from previous init */ 32739651abdSSudarsana Reddy Kalluru qed_init_clear_rt_data(p_hwfn); 32839651abdSSudarsana Reddy Kalluru 32939651abdSSudarsana Reddy Kalluru /* prepare QM portion of runtime array */ 33039651abdSSudarsana Reddy Kalluru qed_qm_init_pf(p_hwfn); 33139651abdSSudarsana Reddy Kalluru 33239651abdSSudarsana Reddy Kalluru /* activate init tool on runtime array */ 33339651abdSSudarsana Reddy Kalluru rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id, 33439651abdSSudarsana Reddy Kalluru p_hwfn->hw_info.hw_mode); 33539651abdSSudarsana Reddy Kalluru if (rc) 33639651abdSSudarsana Reddy Kalluru return rc; 33739651abdSSudarsana Reddy Kalluru 33839651abdSSudarsana Reddy Kalluru /* start PF's qm queues */ 33939651abdSSudarsana Reddy Kalluru spin_lock_bh(&qm_lock); 34039651abdSSudarsana Reddy Kalluru b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true, 34139651abdSSudarsana Reddy Kalluru qm_info->start_pq, qm_info->num_pqs); 34239651abdSSudarsana Reddy Kalluru spin_unlock_bh(&qm_lock); 34339651abdSSudarsana Reddy Kalluru if (!b_rc) 34439651abdSSudarsana Reddy Kalluru return -EINVAL; 34539651abdSSudarsana Reddy Kalluru 34639651abdSSudarsana Reddy Kalluru return 0; 34739651abdSSudarsana Reddy Kalluru } 34839651abdSSudarsana Reddy Kalluru 349fe56b9e6SYuval Mintz int qed_resc_alloc(struct qed_dev *cdev) 350fe56b9e6SYuval Mintz { 351fe56b9e6SYuval Mintz struct qed_consq *p_consq; 352fe56b9e6SYuval Mintz struct qed_eq *p_eq; 353fe56b9e6SYuval Mintz int i, rc = 0; 354fe56b9e6SYuval Mintz 3551408cc1fSYuval Mintz if (IS_VF(cdev)) 3561408cc1fSYuval Mintz return rc; 3571408cc1fSYuval Mintz 358fe56b9e6SYuval Mintz cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL); 359fe56b9e6SYuval Mintz if (!cdev->fw_data) 360fe56b9e6SYuval Mintz return -ENOMEM; 361fe56b9e6SYuval Mintz 36225c089d7SYuval Mintz /* Allocate Memory for the Queue->CID mapping */ 36325c089d7SYuval Mintz for_each_hwfn(cdev, i) { 36425c089d7SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 36525c089d7SYuval Mintz int tx_size = sizeof(struct qed_hw_cid_data) * 36625c089d7SYuval Mintz RESC_NUM(p_hwfn, QED_L2_QUEUE); 36725c089d7SYuval Mintz int rx_size = sizeof(struct qed_hw_cid_data) * 36825c089d7SYuval Mintz RESC_NUM(p_hwfn, QED_L2_QUEUE); 36925c089d7SYuval Mintz 37025c089d7SYuval Mintz p_hwfn->p_tx_cids = kzalloc(tx_size, GFP_KERNEL); 37125c089d7SYuval Mintz if (!p_hwfn->p_tx_cids) { 37225c089d7SYuval Mintz DP_NOTICE(p_hwfn, 37325c089d7SYuval Mintz "Failed to allocate memory for Tx Cids\n"); 3749b15acbfSDan Carpenter rc = -ENOMEM; 37525c089d7SYuval Mintz goto alloc_err; 37625c089d7SYuval Mintz } 37725c089d7SYuval Mintz 37825c089d7SYuval Mintz p_hwfn->p_rx_cids = kzalloc(rx_size, GFP_KERNEL); 37925c089d7SYuval Mintz if (!p_hwfn->p_rx_cids) { 38025c089d7SYuval Mintz DP_NOTICE(p_hwfn, 38125c089d7SYuval Mintz "Failed to allocate memory for Rx Cids\n"); 3829b15acbfSDan Carpenter rc = -ENOMEM; 38325c089d7SYuval Mintz goto alloc_err; 38425c089d7SYuval Mintz } 38525c089d7SYuval Mintz } 38625c089d7SYuval Mintz 387fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 388fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 389fe56b9e6SYuval Mintz 390fe56b9e6SYuval Mintz /* First allocate the context manager structure */ 391fe56b9e6SYuval Mintz rc = qed_cxt_mngr_alloc(p_hwfn); 392fe56b9e6SYuval Mintz if (rc) 393fe56b9e6SYuval Mintz goto alloc_err; 394fe56b9e6SYuval Mintz 395fe56b9e6SYuval Mintz /* Set the HW cid/tid numbers (in the contest manager) 396fe56b9e6SYuval Mintz * Must be done prior to any further computations. 397fe56b9e6SYuval Mintz */ 398fe56b9e6SYuval Mintz rc = qed_cxt_set_pf_params(p_hwfn); 399fe56b9e6SYuval Mintz if (rc) 400fe56b9e6SYuval Mintz goto alloc_err; 401fe56b9e6SYuval Mintz 402fe56b9e6SYuval Mintz /* Prepare and process QM requirements */ 40379529291SSudarsana Reddy Kalluru rc = qed_init_qm_info(p_hwfn, true); 404fe56b9e6SYuval Mintz if (rc) 405fe56b9e6SYuval Mintz goto alloc_err; 406fe56b9e6SYuval Mintz 407fe56b9e6SYuval Mintz /* Compute the ILT client partition */ 408fe56b9e6SYuval Mintz rc = qed_cxt_cfg_ilt_compute(p_hwfn); 409fe56b9e6SYuval Mintz if (rc) 410fe56b9e6SYuval Mintz goto alloc_err; 411fe56b9e6SYuval Mintz 412fe56b9e6SYuval Mintz /* CID map / ILT shadow table / T2 413fe56b9e6SYuval Mintz * The talbes sizes are determined by the computations above 414fe56b9e6SYuval Mintz */ 415fe56b9e6SYuval Mintz rc = qed_cxt_tables_alloc(p_hwfn); 416fe56b9e6SYuval Mintz if (rc) 417fe56b9e6SYuval Mintz goto alloc_err; 418fe56b9e6SYuval Mintz 419fe56b9e6SYuval Mintz /* SPQ, must follow ILT because initializes SPQ context */ 420fe56b9e6SYuval Mintz rc = qed_spq_alloc(p_hwfn); 421fe56b9e6SYuval Mintz if (rc) 422fe56b9e6SYuval Mintz goto alloc_err; 423fe56b9e6SYuval Mintz 424fe56b9e6SYuval Mintz /* SP status block allocation */ 425fe56b9e6SYuval Mintz p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn, 426fe56b9e6SYuval Mintz RESERVED_PTT_DPC); 427fe56b9e6SYuval Mintz 428fe56b9e6SYuval Mintz rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt); 429fe56b9e6SYuval Mintz if (rc) 430fe56b9e6SYuval Mintz goto alloc_err; 431fe56b9e6SYuval Mintz 43232a47e72SYuval Mintz rc = qed_iov_alloc(p_hwfn); 43332a47e72SYuval Mintz if (rc) 43432a47e72SYuval Mintz goto alloc_err; 43532a47e72SYuval Mintz 436fe56b9e6SYuval Mintz /* EQ */ 437fe56b9e6SYuval Mintz p_eq = qed_eq_alloc(p_hwfn, 256); 4389b15acbfSDan Carpenter if (!p_eq) { 4399b15acbfSDan Carpenter rc = -ENOMEM; 440fe56b9e6SYuval Mintz goto alloc_err; 4419b15acbfSDan Carpenter } 442fe56b9e6SYuval Mintz p_hwfn->p_eq = p_eq; 443fe56b9e6SYuval Mintz 444fe56b9e6SYuval Mintz p_consq = qed_consq_alloc(p_hwfn); 4459b15acbfSDan Carpenter if (!p_consq) { 4469b15acbfSDan Carpenter rc = -ENOMEM; 447fe56b9e6SYuval Mintz goto alloc_err; 4489b15acbfSDan Carpenter } 449fe56b9e6SYuval Mintz p_hwfn->p_consq = p_consq; 450fe56b9e6SYuval Mintz 451fe56b9e6SYuval Mintz /* DMA info initialization */ 452fe56b9e6SYuval Mintz rc = qed_dmae_info_alloc(p_hwfn); 453fe56b9e6SYuval Mintz if (rc) { 454fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 455fe56b9e6SYuval Mintz "Failed to allocate memory for dmae_info structure\n"); 456fe56b9e6SYuval Mintz goto alloc_err; 457fe56b9e6SYuval Mintz } 45839651abdSSudarsana Reddy Kalluru 45939651abdSSudarsana Reddy Kalluru /* DCBX initialization */ 46039651abdSSudarsana Reddy Kalluru rc = qed_dcbx_info_alloc(p_hwfn); 46139651abdSSudarsana Reddy Kalluru if (rc) { 46239651abdSSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 46339651abdSSudarsana Reddy Kalluru "Failed to allocate memory for dcbx structure\n"); 46439651abdSSudarsana Reddy Kalluru goto alloc_err; 46539651abdSSudarsana Reddy Kalluru } 466fe56b9e6SYuval Mintz } 467fe56b9e6SYuval Mintz 468fe56b9e6SYuval Mintz cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL); 469fe56b9e6SYuval Mintz if (!cdev->reset_stats) { 470fe56b9e6SYuval Mintz DP_NOTICE(cdev, "Failed to allocate reset statistics\n"); 4719b15acbfSDan Carpenter rc = -ENOMEM; 472fe56b9e6SYuval Mintz goto alloc_err; 473fe56b9e6SYuval Mintz } 474fe56b9e6SYuval Mintz 475fe56b9e6SYuval Mintz return 0; 476fe56b9e6SYuval Mintz 477fe56b9e6SYuval Mintz alloc_err: 478fe56b9e6SYuval Mintz qed_resc_free(cdev); 479fe56b9e6SYuval Mintz return rc; 480fe56b9e6SYuval Mintz } 481fe56b9e6SYuval Mintz 482fe56b9e6SYuval Mintz void qed_resc_setup(struct qed_dev *cdev) 483fe56b9e6SYuval Mintz { 484fe56b9e6SYuval Mintz int i; 485fe56b9e6SYuval Mintz 4861408cc1fSYuval Mintz if (IS_VF(cdev)) 4871408cc1fSYuval Mintz return; 4881408cc1fSYuval Mintz 489fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 490fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 491fe56b9e6SYuval Mintz 492fe56b9e6SYuval Mintz qed_cxt_mngr_setup(p_hwfn); 493fe56b9e6SYuval Mintz qed_spq_setup(p_hwfn); 494fe56b9e6SYuval Mintz qed_eq_setup(p_hwfn, p_hwfn->p_eq); 495fe56b9e6SYuval Mintz qed_consq_setup(p_hwfn, p_hwfn->p_consq); 496fe56b9e6SYuval Mintz 497fe56b9e6SYuval Mintz /* Read shadow of current MFW mailbox */ 498fe56b9e6SYuval Mintz qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt); 499fe56b9e6SYuval Mintz memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 500fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_cur, 501fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_length); 502fe56b9e6SYuval Mintz 503fe56b9e6SYuval Mintz qed_int_setup(p_hwfn, p_hwfn->p_main_ptt); 50432a47e72SYuval Mintz 50532a47e72SYuval Mintz qed_iov_setup(p_hwfn, p_hwfn->p_main_ptt); 506fe56b9e6SYuval Mintz } 507fe56b9e6SYuval Mintz } 508fe56b9e6SYuval Mintz 509fe56b9e6SYuval Mintz #define FINAL_CLEANUP_POLL_CNT (100) 510fe56b9e6SYuval Mintz #define FINAL_CLEANUP_POLL_TIME (10) 511fe56b9e6SYuval Mintz int qed_final_cleanup(struct qed_hwfn *p_hwfn, 5120b55e27dSYuval Mintz struct qed_ptt *p_ptt, u16 id, bool is_vf) 513fe56b9e6SYuval Mintz { 514fe56b9e6SYuval Mintz u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT; 515fe56b9e6SYuval Mintz int rc = -EBUSY; 516fe56b9e6SYuval Mintz 517fc48b7a6SYuval Mintz addr = GTT_BAR0_MAP_REG_USDM_RAM + 518fc48b7a6SYuval Mintz USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id); 519fe56b9e6SYuval Mintz 5200b55e27dSYuval Mintz if (is_vf) 5210b55e27dSYuval Mintz id += 0x10; 5220b55e27dSYuval Mintz 523fc48b7a6SYuval Mintz command |= X_FINAL_CLEANUP_AGG_INT << 524fc48b7a6SYuval Mintz SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT; 525fc48b7a6SYuval Mintz command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT; 526fc48b7a6SYuval Mintz command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT; 527fc48b7a6SYuval Mintz command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT; 528fe56b9e6SYuval Mintz 529fe56b9e6SYuval Mintz /* Make sure notification is not set before initiating final cleanup */ 530fe56b9e6SYuval Mintz if (REG_RD(p_hwfn, addr)) { 531fe56b9e6SYuval Mintz DP_NOTICE( 532fe56b9e6SYuval Mintz p_hwfn, 533fe56b9e6SYuval Mintz "Unexpected; Found final cleanup notification before initiating final cleanup\n"); 534fe56b9e6SYuval Mintz REG_WR(p_hwfn, addr, 0); 535fe56b9e6SYuval Mintz } 536fe56b9e6SYuval Mintz 537fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_IOV, 538fe56b9e6SYuval Mintz "Sending final cleanup for PFVF[%d] [Command %08x\n]", 539fe56b9e6SYuval Mintz id, command); 540fe56b9e6SYuval Mintz 541fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command); 542fe56b9e6SYuval Mintz 543fe56b9e6SYuval Mintz /* Poll until completion */ 544fe56b9e6SYuval Mintz while (!REG_RD(p_hwfn, addr) && count--) 545fe56b9e6SYuval Mintz msleep(FINAL_CLEANUP_POLL_TIME); 546fe56b9e6SYuval Mintz 547fe56b9e6SYuval Mintz if (REG_RD(p_hwfn, addr)) 548fe56b9e6SYuval Mintz rc = 0; 549fe56b9e6SYuval Mintz else 550fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 551fe56b9e6SYuval Mintz "Failed to receive FW final cleanup notification\n"); 552fe56b9e6SYuval Mintz 553fe56b9e6SYuval Mintz /* Cleanup afterwards */ 554fe56b9e6SYuval Mintz REG_WR(p_hwfn, addr, 0); 555fe56b9e6SYuval Mintz 556fe56b9e6SYuval Mintz return rc; 557fe56b9e6SYuval Mintz } 558fe56b9e6SYuval Mintz 559fe56b9e6SYuval Mintz static void qed_calc_hw_mode(struct qed_hwfn *p_hwfn) 560fe56b9e6SYuval Mintz { 561fe56b9e6SYuval Mintz int hw_mode = 0; 562fe56b9e6SYuval Mintz 56312e09c69SYuval Mintz hw_mode = (1 << MODE_BB_B0); 564fe56b9e6SYuval Mintz 565fe56b9e6SYuval Mintz switch (p_hwfn->cdev->num_ports_in_engines) { 566fe56b9e6SYuval Mintz case 1: 567fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_PORTS_PER_ENG_1; 568fe56b9e6SYuval Mintz break; 569fe56b9e6SYuval Mintz case 2: 570fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_PORTS_PER_ENG_2; 571fe56b9e6SYuval Mintz break; 572fe56b9e6SYuval Mintz case 4: 573fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_PORTS_PER_ENG_4; 574fe56b9e6SYuval Mintz break; 575fe56b9e6SYuval Mintz default: 576fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n", 577fe56b9e6SYuval Mintz p_hwfn->cdev->num_ports_in_engines); 578fe56b9e6SYuval Mintz return; 579fe56b9e6SYuval Mintz } 580fe56b9e6SYuval Mintz 581fe56b9e6SYuval Mintz switch (p_hwfn->cdev->mf_mode) { 582fc48b7a6SYuval Mintz case QED_MF_DEFAULT: 583fc48b7a6SYuval Mintz case QED_MF_NPAR: 584fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_MF_SI; 585fe56b9e6SYuval Mintz break; 586fc48b7a6SYuval Mintz case QED_MF_OVLAN: 587fc48b7a6SYuval Mintz hw_mode |= 1 << MODE_MF_SD; 588fc48b7a6SYuval Mintz break; 589fe56b9e6SYuval Mintz default: 590fc48b7a6SYuval Mintz DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n"); 591fc48b7a6SYuval Mintz hw_mode |= 1 << MODE_MF_SI; 592fe56b9e6SYuval Mintz } 593fe56b9e6SYuval Mintz 594fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_ASIC; 595fe56b9e6SYuval Mintz 5961af9dcf7SYuval Mintz if (p_hwfn->cdev->num_hwfns > 1) 5971af9dcf7SYuval Mintz hw_mode |= 1 << MODE_100G; 5981af9dcf7SYuval Mintz 599fe56b9e6SYuval Mintz p_hwfn->hw_info.hw_mode = hw_mode; 6001af9dcf7SYuval Mintz 6011af9dcf7SYuval Mintz DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP), 6021af9dcf7SYuval Mintz "Configuring function for hw_mode: 0x%08x\n", 6031af9dcf7SYuval Mintz p_hwfn->hw_info.hw_mode); 604fe56b9e6SYuval Mintz } 605fe56b9e6SYuval Mintz 606fe56b9e6SYuval Mintz /* Init run time data for all PFs on an engine. */ 607fe56b9e6SYuval Mintz static void qed_init_cau_rt_data(struct qed_dev *cdev) 608fe56b9e6SYuval Mintz { 609fe56b9e6SYuval Mintz u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET; 610fe56b9e6SYuval Mintz int i, sb_id; 611fe56b9e6SYuval Mintz 612fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 613fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 614fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 615fe56b9e6SYuval Mintz struct qed_igu_block *p_block; 616fe56b9e6SYuval Mintz struct cau_sb_entry sb_entry; 617fe56b9e6SYuval Mintz 618fe56b9e6SYuval Mintz p_igu_info = p_hwfn->hw_info.p_igu_info; 619fe56b9e6SYuval Mintz 620fe56b9e6SYuval Mintz for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev); 621fe56b9e6SYuval Mintz sb_id++) { 622fe56b9e6SYuval Mintz p_block = &p_igu_info->igu_map.igu_blocks[sb_id]; 623fe56b9e6SYuval Mintz if (!p_block->is_pf) 624fe56b9e6SYuval Mintz continue; 625fe56b9e6SYuval Mintz 626fe56b9e6SYuval Mintz qed_init_cau_sb_entry(p_hwfn, &sb_entry, 627fe56b9e6SYuval Mintz p_block->function_id, 628fe56b9e6SYuval Mintz 0, 0); 629fe56b9e6SYuval Mintz STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, 630fe56b9e6SYuval Mintz sb_entry); 631fe56b9e6SYuval Mintz } 632fe56b9e6SYuval Mintz } 633fe56b9e6SYuval Mintz } 634fe56b9e6SYuval Mintz 635fe56b9e6SYuval Mintz static int qed_hw_init_common(struct qed_hwfn *p_hwfn, 636fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 637fe56b9e6SYuval Mintz int hw_mode) 638fe56b9e6SYuval Mintz { 639fe56b9e6SYuval Mintz struct qed_qm_info *qm_info = &p_hwfn->qm_info; 640fe56b9e6SYuval Mintz struct qed_qm_common_rt_init_params params; 641fe56b9e6SYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 6421408cc1fSYuval Mintz u32 concrete_fid; 643fe56b9e6SYuval Mintz int rc = 0; 6441408cc1fSYuval Mintz u8 vf_id; 645fe56b9e6SYuval Mintz 646fe56b9e6SYuval Mintz qed_init_cau_rt_data(cdev); 647fe56b9e6SYuval Mintz 648fe56b9e6SYuval Mintz /* Program GTT windows */ 649fe56b9e6SYuval Mintz qed_gtt_init(p_hwfn); 650fe56b9e6SYuval Mintz 651fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 652fe56b9e6SYuval Mintz if (p_hwfn->mcp_info->func_info.bandwidth_max) 653fe56b9e6SYuval Mintz qm_info->pf_rl_en = 1; 654fe56b9e6SYuval Mintz if (p_hwfn->mcp_info->func_info.bandwidth_min) 655fe56b9e6SYuval Mintz qm_info->pf_wfq_en = 1; 656fe56b9e6SYuval Mintz } 657fe56b9e6SYuval Mintz 658fe56b9e6SYuval Mintz memset(¶ms, 0, sizeof(params)); 659fe56b9e6SYuval Mintz params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engines; 660fe56b9e6SYuval Mintz params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port; 661fe56b9e6SYuval Mintz params.pf_rl_en = qm_info->pf_rl_en; 662fe56b9e6SYuval Mintz params.pf_wfq_en = qm_info->pf_wfq_en; 663fe56b9e6SYuval Mintz params.vport_rl_en = qm_info->vport_rl_en; 664fe56b9e6SYuval Mintz params.vport_wfq_en = qm_info->vport_wfq_en; 665fe56b9e6SYuval Mintz params.port_params = qm_info->qm_port_params; 666fe56b9e6SYuval Mintz 667fe56b9e6SYuval Mintz qed_qm_common_rt_init(p_hwfn, ¶ms); 668fe56b9e6SYuval Mintz 669fe56b9e6SYuval Mintz qed_cxt_hw_init_common(p_hwfn); 670fe56b9e6SYuval Mintz 671fe56b9e6SYuval Mintz /* Close gate from NIG to BRB/Storm; By default they are open, but 672fe56b9e6SYuval Mintz * we close them to prevent NIG from passing data to reset blocks. 673fe56b9e6SYuval Mintz * Should have been done in the ENGINE phase, but init-tool lacks 674fe56b9e6SYuval Mintz * proper port-pretend capabilities. 675fe56b9e6SYuval Mintz */ 676fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0); 677fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0); 678fe56b9e6SYuval Mintz qed_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1); 679fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0); 680fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0); 681fe56b9e6SYuval Mintz qed_port_unpretend(p_hwfn, p_ptt); 682fe56b9e6SYuval Mintz 683fe56b9e6SYuval Mintz rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode); 684fe56b9e6SYuval Mintz if (rc != 0) 685fe56b9e6SYuval Mintz return rc; 686fe56b9e6SYuval Mintz 687fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0); 688fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1); 689fe56b9e6SYuval Mintz 690fe56b9e6SYuval Mintz /* Disable relaxed ordering in the PCI config space */ 691fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 0x20b4, 692fe56b9e6SYuval Mintz qed_rd(p_hwfn, p_ptt, 0x20b4) & ~0x10); 693fe56b9e6SYuval Mintz 6941408cc1fSYuval Mintz for (vf_id = 0; vf_id < MAX_NUM_VFS_BB; vf_id++) { 6951408cc1fSYuval Mintz concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id); 6961408cc1fSYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid); 6971408cc1fSYuval Mintz qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1); 6981408cc1fSYuval Mintz } 6991408cc1fSYuval Mintz /* pretend to original PF */ 7001408cc1fSYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 7011408cc1fSYuval Mintz 702fe56b9e6SYuval Mintz return rc; 703fe56b9e6SYuval Mintz } 704fe56b9e6SYuval Mintz 705fe56b9e6SYuval Mintz static int qed_hw_init_port(struct qed_hwfn *p_hwfn, 706fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 707fe56b9e6SYuval Mintz int hw_mode) 708fe56b9e6SYuval Mintz { 709fe56b9e6SYuval Mintz int rc = 0; 710fe56b9e6SYuval Mintz 711351a4dedSYuval Mintz rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode); 712351a4dedSYuval Mintz if (rc != 0) 713351a4dedSYuval Mintz return rc; 714351a4dedSYuval Mintz 715351a4dedSYuval Mintz if (hw_mode & (1 << MODE_MF_SI)) { 716351a4dedSYuval Mintz u8 pf_id = 0; 717351a4dedSYuval Mintz 718351a4dedSYuval Mintz if (!qed_hw_init_first_eth(p_hwfn, p_ptt, &pf_id)) { 719351a4dedSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 720351a4dedSYuval Mintz "PF[%08x] is first eth on engine\n", pf_id); 721351a4dedSYuval Mintz 722351a4dedSYuval Mintz /* We should have configured BIT for ppfid, i.e., the 723351a4dedSYuval Mintz * relative function number in the port. But there's a 724351a4dedSYuval Mintz * bug in LLH in BB where the ppfid is actually engine 725351a4dedSYuval Mintz * based, so we need to take this into account. 726351a4dedSYuval Mintz */ 727351a4dedSYuval Mintz qed_wr(p_hwfn, p_ptt, 728351a4dedSYuval Mintz NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR, 1 << pf_id); 729351a4dedSYuval Mintz } 730351a4dedSYuval Mintz 731351a4dedSYuval Mintz /* Take the protocol-based hit vector if there is a hit, 732351a4dedSYuval Mintz * otherwise take the other vector. 733351a4dedSYuval Mintz */ 734351a4dedSYuval Mintz qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_CLS_TYPE_DUALMODE, 0x2); 735351a4dedSYuval Mintz } 736fe56b9e6SYuval Mintz return rc; 737fe56b9e6SYuval Mintz } 738fe56b9e6SYuval Mintz 739fe56b9e6SYuval Mintz static int qed_hw_init_pf(struct qed_hwfn *p_hwfn, 740fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 741464f6645SManish Chopra struct qed_tunn_start_params *p_tunn, 742fe56b9e6SYuval Mintz int hw_mode, 743fe56b9e6SYuval Mintz bool b_hw_start, 744fe56b9e6SYuval Mintz enum qed_int_mode int_mode, 745fe56b9e6SYuval Mintz bool allow_npar_tx_switch) 746fe56b9e6SYuval Mintz { 747fe56b9e6SYuval Mintz u8 rel_pf_id = p_hwfn->rel_pf_id; 748fe56b9e6SYuval Mintz int rc = 0; 749fe56b9e6SYuval Mintz 750fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 751fe56b9e6SYuval Mintz struct qed_mcp_function_info *p_info; 752fe56b9e6SYuval Mintz 753fe56b9e6SYuval Mintz p_info = &p_hwfn->mcp_info->func_info; 754fe56b9e6SYuval Mintz if (p_info->bandwidth_min) 755fe56b9e6SYuval Mintz p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min; 756fe56b9e6SYuval Mintz 757fe56b9e6SYuval Mintz /* Update rate limit once we'll actually have a link */ 7584b01e519SManish Chopra p_hwfn->qm_info.pf_rl = 100000; 759fe56b9e6SYuval Mintz } 760fe56b9e6SYuval Mintz 761fe56b9e6SYuval Mintz qed_cxt_hw_init_pf(p_hwfn); 762fe56b9e6SYuval Mintz 763fe56b9e6SYuval Mintz qed_int_igu_init_rt(p_hwfn); 764fe56b9e6SYuval Mintz 765fe56b9e6SYuval Mintz /* Set VLAN in NIG if needed */ 766fe56b9e6SYuval Mintz if (hw_mode & (1 << MODE_MF_SD)) { 767fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n"); 768fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1); 769fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET, 770fe56b9e6SYuval Mintz p_hwfn->hw_info.ovlan); 771fe56b9e6SYuval Mintz } 772fe56b9e6SYuval Mintz 773fe56b9e6SYuval Mintz /* Enable classification by MAC if needed */ 77487aec47dSDan Carpenter if (hw_mode & (1 << MODE_MF_SI)) { 775fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 776fe56b9e6SYuval Mintz "Configuring TAGMAC_CLS_TYPE\n"); 777fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, 778fe56b9e6SYuval Mintz NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1); 779fe56b9e6SYuval Mintz } 780fe56b9e6SYuval Mintz 781fe56b9e6SYuval Mintz /* Protocl Configuration */ 782fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 0); 783fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 0); 784fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0); 785fe56b9e6SYuval Mintz 786fe56b9e6SYuval Mintz /* Cleanup chip from previous driver if such remains exist */ 7870b55e27dSYuval Mintz rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false); 788fe56b9e6SYuval Mintz if (rc != 0) 789fe56b9e6SYuval Mintz return rc; 790fe56b9e6SYuval Mintz 791fe56b9e6SYuval Mintz /* PF Init sequence */ 792fe56b9e6SYuval Mintz rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode); 793fe56b9e6SYuval Mintz if (rc) 794fe56b9e6SYuval Mintz return rc; 795fe56b9e6SYuval Mintz 796fe56b9e6SYuval Mintz /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */ 797fe56b9e6SYuval Mintz rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode); 798fe56b9e6SYuval Mintz if (rc) 799fe56b9e6SYuval Mintz return rc; 800fe56b9e6SYuval Mintz 801fe56b9e6SYuval Mintz /* Pure runtime initializations - directly to the HW */ 802fe56b9e6SYuval Mintz qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true); 803fe56b9e6SYuval Mintz 804351a4dedSYuval Mintz if (hw_mode & (1 << MODE_MF_SI)) { 805351a4dedSYuval Mintz u8 pf_id = 0; 806351a4dedSYuval Mintz u32 val; 807351a4dedSYuval Mintz 808351a4dedSYuval Mintz if (!qed_hw_init_first_eth(p_hwfn, p_ptt, &pf_id)) { 809351a4dedSYuval Mintz if (p_hwfn->rel_pf_id == pf_id) { 810351a4dedSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP, 811351a4dedSYuval Mintz "PF[%d] is first ETH on engine\n", 812351a4dedSYuval Mintz pf_id); 813351a4dedSYuval Mintz val = 1; 814351a4dedSYuval Mintz } 815351a4dedSYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_MSG_INFO, val); 816351a4dedSYuval Mintz } 817351a4dedSYuval Mintz } 818351a4dedSYuval Mintz 819fe56b9e6SYuval Mintz if (b_hw_start) { 820fe56b9e6SYuval Mintz /* enable interrupts */ 821fe56b9e6SYuval Mintz qed_int_igu_enable(p_hwfn, p_ptt, int_mode); 822fe56b9e6SYuval Mintz 823fe56b9e6SYuval Mintz /* send function start command */ 824831bfb0eSYuval Mintz rc = qed_sp_pf_start(p_hwfn, p_tunn, p_hwfn->cdev->mf_mode, 825831bfb0eSYuval Mintz allow_npar_tx_switch); 826fe56b9e6SYuval Mintz if (rc) 827fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Function start ramrod failed\n"); 828fe56b9e6SYuval Mintz } 829fe56b9e6SYuval Mintz return rc; 830fe56b9e6SYuval Mintz } 831fe56b9e6SYuval Mintz 832fe56b9e6SYuval Mintz static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn, 833fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 834fe56b9e6SYuval Mintz u8 enable) 835fe56b9e6SYuval Mintz { 836fe56b9e6SYuval Mintz u32 delay_idx = 0, val, set_val = enable ? 1 : 0; 837fe56b9e6SYuval Mintz 838fe56b9e6SYuval Mintz /* Change PF in PXP */ 839fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 840fe56b9e6SYuval Mintz PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val); 841fe56b9e6SYuval Mintz 842fe56b9e6SYuval Mintz /* wait until value is set - try for 1 second every 50us */ 843fe56b9e6SYuval Mintz for (delay_idx = 0; delay_idx < 20000; delay_idx++) { 844fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, 845fe56b9e6SYuval Mintz PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 846fe56b9e6SYuval Mintz if (val == set_val) 847fe56b9e6SYuval Mintz break; 848fe56b9e6SYuval Mintz 849fe56b9e6SYuval Mintz usleep_range(50, 60); 850fe56b9e6SYuval Mintz } 851fe56b9e6SYuval Mintz 852fe56b9e6SYuval Mintz if (val != set_val) { 853fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 854fe56b9e6SYuval Mintz "PFID_ENABLE_MASTER wasn't changed after a second\n"); 855fe56b9e6SYuval Mintz return -EAGAIN; 856fe56b9e6SYuval Mintz } 857fe56b9e6SYuval Mintz 858fe56b9e6SYuval Mintz return 0; 859fe56b9e6SYuval Mintz } 860fe56b9e6SYuval Mintz 861fe56b9e6SYuval Mintz static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn, 862fe56b9e6SYuval Mintz struct qed_ptt *p_main_ptt) 863fe56b9e6SYuval Mintz { 864fe56b9e6SYuval Mintz /* Read shadow of current MFW mailbox */ 865fe56b9e6SYuval Mintz qed_mcp_read_mb(p_hwfn, p_main_ptt); 866fe56b9e6SYuval Mintz memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 867fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_cur, 868fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_length); 869fe56b9e6SYuval Mintz } 870fe56b9e6SYuval Mintz 871fe56b9e6SYuval Mintz int qed_hw_init(struct qed_dev *cdev, 872464f6645SManish Chopra struct qed_tunn_start_params *p_tunn, 873fe56b9e6SYuval Mintz bool b_hw_start, 874fe56b9e6SYuval Mintz enum qed_int_mode int_mode, 875fe56b9e6SYuval Mintz bool allow_npar_tx_switch, 876fe56b9e6SYuval Mintz const u8 *bin_fw_data) 877fe56b9e6SYuval Mintz { 87886622ee7SYuval Mintz u32 load_code, param; 879fe56b9e6SYuval Mintz int rc, mfw_rc, i; 880fe56b9e6SYuval Mintz 881bb13ace7SSudarsana Reddy Kalluru if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) { 882bb13ace7SSudarsana Reddy Kalluru DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n"); 883bb13ace7SSudarsana Reddy Kalluru return -EINVAL; 884bb13ace7SSudarsana Reddy Kalluru } 885bb13ace7SSudarsana Reddy Kalluru 8861408cc1fSYuval Mintz if (IS_PF(cdev)) { 887fe56b9e6SYuval Mintz rc = qed_init_fw_data(cdev, bin_fw_data); 888fe56b9e6SYuval Mintz if (rc != 0) 889fe56b9e6SYuval Mintz return rc; 8901408cc1fSYuval Mintz } 891fe56b9e6SYuval Mintz 892fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 893fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 894fe56b9e6SYuval Mintz 8951408cc1fSYuval Mintz if (IS_VF(cdev)) { 8961408cc1fSYuval Mintz p_hwfn->b_int_enabled = 1; 8971408cc1fSYuval Mintz continue; 8981408cc1fSYuval Mintz } 8991408cc1fSYuval Mintz 900fe56b9e6SYuval Mintz /* Enable DMAE in PXP */ 901fe56b9e6SYuval Mintz rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true); 902fe56b9e6SYuval Mintz 903fe56b9e6SYuval Mintz qed_calc_hw_mode(p_hwfn); 904fe56b9e6SYuval Mintz 905fe56b9e6SYuval Mintz rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, 906fe56b9e6SYuval Mintz &load_code); 907fe56b9e6SYuval Mintz if (rc) { 908fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed sending LOAD_REQ command\n"); 909fe56b9e6SYuval Mintz return rc; 910fe56b9e6SYuval Mintz } 911fe56b9e6SYuval Mintz 912fe56b9e6SYuval Mintz qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt); 913fe56b9e6SYuval Mintz 914fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 915fe56b9e6SYuval Mintz "Load request was sent. Resp:0x%x, Load code: 0x%x\n", 916fe56b9e6SYuval Mintz rc, load_code); 917fe56b9e6SYuval Mintz 918fe56b9e6SYuval Mintz p_hwfn->first_on_engine = (load_code == 919fe56b9e6SYuval Mintz FW_MSG_CODE_DRV_LOAD_ENGINE); 920fe56b9e6SYuval Mintz 92139651abdSSudarsana Reddy Kalluru if (!qm_lock_init) { 92239651abdSSudarsana Reddy Kalluru spin_lock_init(&qm_lock); 92339651abdSSudarsana Reddy Kalluru qm_lock_init = true; 92439651abdSSudarsana Reddy Kalluru } 92539651abdSSudarsana Reddy Kalluru 926fe56b9e6SYuval Mintz switch (load_code) { 927fe56b9e6SYuval Mintz case FW_MSG_CODE_DRV_LOAD_ENGINE: 928fe56b9e6SYuval Mintz rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt, 929fe56b9e6SYuval Mintz p_hwfn->hw_info.hw_mode); 930fe56b9e6SYuval Mintz if (rc) 931fe56b9e6SYuval Mintz break; 932fe56b9e6SYuval Mintz /* Fall into */ 933fe56b9e6SYuval Mintz case FW_MSG_CODE_DRV_LOAD_PORT: 934fe56b9e6SYuval Mintz rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt, 935fe56b9e6SYuval Mintz p_hwfn->hw_info.hw_mode); 936fe56b9e6SYuval Mintz if (rc) 937fe56b9e6SYuval Mintz break; 938fe56b9e6SYuval Mintz 939fe56b9e6SYuval Mintz /* Fall into */ 940fe56b9e6SYuval Mintz case FW_MSG_CODE_DRV_LOAD_FUNCTION: 941fe56b9e6SYuval Mintz rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt, 942464f6645SManish Chopra p_tunn, p_hwfn->hw_info.hw_mode, 943fe56b9e6SYuval Mintz b_hw_start, int_mode, 944fe56b9e6SYuval Mintz allow_npar_tx_switch); 945fe56b9e6SYuval Mintz break; 946fe56b9e6SYuval Mintz default: 947fe56b9e6SYuval Mintz rc = -EINVAL; 948fe56b9e6SYuval Mintz break; 949fe56b9e6SYuval Mintz } 950fe56b9e6SYuval Mintz 951fe56b9e6SYuval Mintz if (rc) 952fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 953fe56b9e6SYuval Mintz "init phase failed for loadcode 0x%x (rc %d)\n", 954fe56b9e6SYuval Mintz load_code, rc); 955fe56b9e6SYuval Mintz 956fe56b9e6SYuval Mintz /* ACK mfw regardless of success or failure of initialization */ 957fe56b9e6SYuval Mintz mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 958fe56b9e6SYuval Mintz DRV_MSG_CODE_LOAD_DONE, 959fe56b9e6SYuval Mintz 0, &load_code, ¶m); 960fe56b9e6SYuval Mintz if (rc) 961fe56b9e6SYuval Mintz return rc; 962fe56b9e6SYuval Mintz if (mfw_rc) { 963fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n"); 964fe56b9e6SYuval Mintz return mfw_rc; 965fe56b9e6SYuval Mintz } 966fe56b9e6SYuval Mintz 96739651abdSSudarsana Reddy Kalluru /* send DCBX attention request command */ 96839651abdSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, 96939651abdSSudarsana Reddy Kalluru QED_MSG_DCB, 97039651abdSSudarsana Reddy Kalluru "sending phony dcbx set command to trigger DCBx attention handling\n"); 97139651abdSSudarsana Reddy Kalluru mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 97239651abdSSudarsana Reddy Kalluru DRV_MSG_CODE_SET_DCBX, 97339651abdSSudarsana Reddy Kalluru 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT, 97439651abdSSudarsana Reddy Kalluru &load_code, ¶m); 97539651abdSSudarsana Reddy Kalluru if (mfw_rc) { 97639651abdSSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 97739651abdSSudarsana Reddy Kalluru "Failed to send DCBX attention request\n"); 97839651abdSSudarsana Reddy Kalluru return mfw_rc; 97939651abdSSudarsana Reddy Kalluru } 98039651abdSSudarsana Reddy Kalluru 981fe56b9e6SYuval Mintz p_hwfn->hw_init_done = true; 982fe56b9e6SYuval Mintz } 983fe56b9e6SYuval Mintz 984fe56b9e6SYuval Mintz return 0; 985fe56b9e6SYuval Mintz } 986fe56b9e6SYuval Mintz 987fe56b9e6SYuval Mintz #define QED_HW_STOP_RETRY_LIMIT (10) 9888c925c44SYuval Mintz static inline void qed_hw_timers_stop(struct qed_dev *cdev, 9898c925c44SYuval Mintz struct qed_hwfn *p_hwfn, 9908c925c44SYuval Mintz struct qed_ptt *p_ptt) 9918c925c44SYuval Mintz { 9928c925c44SYuval Mintz int i; 9938c925c44SYuval Mintz 9948c925c44SYuval Mintz /* close timers */ 9958c925c44SYuval Mintz qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0); 9968c925c44SYuval Mintz qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0); 9978c925c44SYuval Mintz 9988c925c44SYuval Mintz for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) { 9998c925c44SYuval Mintz if ((!qed_rd(p_hwfn, p_ptt, 10008c925c44SYuval Mintz TM_REG_PF_SCAN_ACTIVE_CONN)) && 10018c925c44SYuval Mintz (!qed_rd(p_hwfn, p_ptt, 10028c925c44SYuval Mintz TM_REG_PF_SCAN_ACTIVE_TASK))) 10038c925c44SYuval Mintz break; 10048c925c44SYuval Mintz 10058c925c44SYuval Mintz /* Dependent on number of connection/tasks, possibly 10068c925c44SYuval Mintz * 1ms sleep is required between polls 10078c925c44SYuval Mintz */ 10088c925c44SYuval Mintz usleep_range(1000, 2000); 10098c925c44SYuval Mintz } 10108c925c44SYuval Mintz 10118c925c44SYuval Mintz if (i < QED_HW_STOP_RETRY_LIMIT) 10128c925c44SYuval Mintz return; 10138c925c44SYuval Mintz 10148c925c44SYuval Mintz DP_NOTICE(p_hwfn, 10158c925c44SYuval Mintz "Timers linear scans are not over [Connection %02x Tasks %02x]\n", 10168c925c44SYuval Mintz (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN), 10178c925c44SYuval Mintz (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)); 10188c925c44SYuval Mintz } 10198c925c44SYuval Mintz 10208c925c44SYuval Mintz void qed_hw_timers_stop_all(struct qed_dev *cdev) 10218c925c44SYuval Mintz { 10228c925c44SYuval Mintz int j; 10238c925c44SYuval Mintz 10248c925c44SYuval Mintz for_each_hwfn(cdev, j) { 10258c925c44SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 10268c925c44SYuval Mintz struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 10278c925c44SYuval Mintz 10288c925c44SYuval Mintz qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 10298c925c44SYuval Mintz } 10308c925c44SYuval Mintz } 10318c925c44SYuval Mintz 1032fe56b9e6SYuval Mintz int qed_hw_stop(struct qed_dev *cdev) 1033fe56b9e6SYuval Mintz { 1034fe56b9e6SYuval Mintz int rc = 0, t_rc; 10358c925c44SYuval Mintz int j; 1036fe56b9e6SYuval Mintz 1037fe56b9e6SYuval Mintz for_each_hwfn(cdev, j) { 1038fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 1039fe56b9e6SYuval Mintz struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 1040fe56b9e6SYuval Mintz 1041fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n"); 1042fe56b9e6SYuval Mintz 10431408cc1fSYuval Mintz if (IS_VF(cdev)) { 10440b55e27dSYuval Mintz qed_vf_pf_int_cleanup(p_hwfn); 10451408cc1fSYuval Mintz continue; 10461408cc1fSYuval Mintz } 10471408cc1fSYuval Mintz 1048fe56b9e6SYuval Mintz /* mark the hw as uninitialized... */ 1049fe56b9e6SYuval Mintz p_hwfn->hw_init_done = false; 1050fe56b9e6SYuval Mintz 1051fe56b9e6SYuval Mintz rc = qed_sp_pf_stop(p_hwfn); 1052fe56b9e6SYuval Mintz if (rc) 10538c925c44SYuval Mintz DP_NOTICE(p_hwfn, 10548c925c44SYuval Mintz "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n"); 1055fe56b9e6SYuval Mintz 1056fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 1057fe56b9e6SYuval Mintz NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 1058fe56b9e6SYuval Mintz 1059fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1060fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 1061fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 1062fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1063fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 1064fe56b9e6SYuval Mintz 10658c925c44SYuval Mintz qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 1066fe56b9e6SYuval Mintz 1067fe56b9e6SYuval Mintz /* Disable Attention Generation */ 1068fe56b9e6SYuval Mintz qed_int_igu_disable_int(p_hwfn, p_ptt); 1069fe56b9e6SYuval Mintz 1070fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0); 1071fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0); 1072fe56b9e6SYuval Mintz 1073fe56b9e6SYuval Mintz qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true); 1074fe56b9e6SYuval Mintz 1075fe56b9e6SYuval Mintz /* Need to wait 1ms to guarantee SBs are cleared */ 1076fe56b9e6SYuval Mintz usleep_range(1000, 2000); 1077fe56b9e6SYuval Mintz } 1078fe56b9e6SYuval Mintz 10791408cc1fSYuval Mintz if (IS_PF(cdev)) { 1080fe56b9e6SYuval Mintz /* Disable DMAE in PXP - in CMT, this should only be done for 1081fe56b9e6SYuval Mintz * first hw-function, and only after all transactions have 1082fe56b9e6SYuval Mintz * stopped for all active hw-functions. 1083fe56b9e6SYuval Mintz */ 1084fe56b9e6SYuval Mintz t_rc = qed_change_pci_hwfn(&cdev->hwfns[0], 10851408cc1fSYuval Mintz cdev->hwfns[0].p_main_ptt, false); 1086fe56b9e6SYuval Mintz if (t_rc != 0) 1087fe56b9e6SYuval Mintz rc = t_rc; 10881408cc1fSYuval Mintz } 1089fe56b9e6SYuval Mintz 1090fe56b9e6SYuval Mintz return rc; 1091fe56b9e6SYuval Mintz } 1092fe56b9e6SYuval Mintz 1093cee4d264SManish Chopra void qed_hw_stop_fastpath(struct qed_dev *cdev) 1094cee4d264SManish Chopra { 10958c925c44SYuval Mintz int j; 1096cee4d264SManish Chopra 1097cee4d264SManish Chopra for_each_hwfn(cdev, j) { 1098cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 1099cee4d264SManish Chopra struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 1100cee4d264SManish Chopra 1101dacd88d6SYuval Mintz if (IS_VF(cdev)) { 1102dacd88d6SYuval Mintz qed_vf_pf_int_cleanup(p_hwfn); 1103dacd88d6SYuval Mintz continue; 1104dacd88d6SYuval Mintz } 1105dacd88d6SYuval Mintz 1106cee4d264SManish Chopra DP_VERBOSE(p_hwfn, 1107cee4d264SManish Chopra NETIF_MSG_IFDOWN, 1108cee4d264SManish Chopra "Shutting down the fastpath\n"); 1109cee4d264SManish Chopra 1110cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, 1111cee4d264SManish Chopra NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 1112cee4d264SManish Chopra 1113cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1114cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 1115cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 1116cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1117cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 1118cee4d264SManish Chopra 1119cee4d264SManish Chopra qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false); 1120cee4d264SManish Chopra 1121cee4d264SManish Chopra /* Need to wait 1ms to guarantee SBs are cleared */ 1122cee4d264SManish Chopra usleep_range(1000, 2000); 1123cee4d264SManish Chopra } 1124cee4d264SManish Chopra } 1125cee4d264SManish Chopra 1126cee4d264SManish Chopra void qed_hw_start_fastpath(struct qed_hwfn *p_hwfn) 1127cee4d264SManish Chopra { 1128dacd88d6SYuval Mintz if (IS_VF(p_hwfn->cdev)) 1129dacd88d6SYuval Mintz return; 1130dacd88d6SYuval Mintz 1131cee4d264SManish Chopra /* Re-open incoming traffic */ 1132cee4d264SManish Chopra qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1133cee4d264SManish Chopra NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0); 1134cee4d264SManish Chopra } 1135cee4d264SManish Chopra 1136fe56b9e6SYuval Mintz static int qed_reg_assert(struct qed_hwfn *hwfn, 1137fe56b9e6SYuval Mintz struct qed_ptt *ptt, u32 reg, 1138fe56b9e6SYuval Mintz bool expected) 1139fe56b9e6SYuval Mintz { 1140fe56b9e6SYuval Mintz u32 assert_val = qed_rd(hwfn, ptt, reg); 1141fe56b9e6SYuval Mintz 1142fe56b9e6SYuval Mintz if (assert_val != expected) { 1143fe56b9e6SYuval Mintz DP_NOTICE(hwfn, "Value at address 0x%x != 0x%08x\n", 1144fe56b9e6SYuval Mintz reg, expected); 1145fe56b9e6SYuval Mintz return -EINVAL; 1146fe56b9e6SYuval Mintz } 1147fe56b9e6SYuval Mintz 1148fe56b9e6SYuval Mintz return 0; 1149fe56b9e6SYuval Mintz } 1150fe56b9e6SYuval Mintz 1151fe56b9e6SYuval Mintz int qed_hw_reset(struct qed_dev *cdev) 1152fe56b9e6SYuval Mintz { 1153fe56b9e6SYuval Mintz int rc = 0; 1154fe56b9e6SYuval Mintz u32 unload_resp, unload_param; 1155fe56b9e6SYuval Mintz int i; 1156fe56b9e6SYuval Mintz 1157fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 1158fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1159fe56b9e6SYuval Mintz 11601408cc1fSYuval Mintz if (IS_VF(cdev)) { 11610b55e27dSYuval Mintz rc = qed_vf_pf_reset(p_hwfn); 11620b55e27dSYuval Mintz if (rc) 11630b55e27dSYuval Mintz return rc; 11641408cc1fSYuval Mintz continue; 11651408cc1fSYuval Mintz } 11661408cc1fSYuval Mintz 1167fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Resetting hw/fw\n"); 1168fe56b9e6SYuval Mintz 1169fe56b9e6SYuval Mintz /* Check for incorrect states */ 1170fe56b9e6SYuval Mintz qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt, 1171fe56b9e6SYuval Mintz QM_REG_USG_CNT_PF_TX, 0); 1172fe56b9e6SYuval Mintz qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt, 1173fe56b9e6SYuval Mintz QM_REG_USG_CNT_PF_OTHER, 0); 1174fe56b9e6SYuval Mintz 1175fe56b9e6SYuval Mintz /* Disable PF in HW blocks */ 1176fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0); 1177fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0); 1178fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1179fe56b9e6SYuval Mintz TCFC_REG_STRONG_ENABLE_PF, 0); 1180fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1181fe56b9e6SYuval Mintz CCFC_REG_STRONG_ENABLE_PF, 0); 1182fe56b9e6SYuval Mintz 1183fe56b9e6SYuval Mintz /* Send unload command to MCP */ 1184fe56b9e6SYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1185fe56b9e6SYuval Mintz DRV_MSG_CODE_UNLOAD_REQ, 1186fe56b9e6SYuval Mintz DRV_MB_PARAM_UNLOAD_WOL_MCP, 1187fe56b9e6SYuval Mintz &unload_resp, &unload_param); 1188fe56b9e6SYuval Mintz if (rc) { 1189fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_REQ failed\n"); 1190fe56b9e6SYuval Mintz unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE; 1191fe56b9e6SYuval Mintz } 1192fe56b9e6SYuval Mintz 1193fe56b9e6SYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1194fe56b9e6SYuval Mintz DRV_MSG_CODE_UNLOAD_DONE, 1195fe56b9e6SYuval Mintz 0, &unload_resp, &unload_param); 1196fe56b9e6SYuval Mintz if (rc) { 1197fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_DONE failed\n"); 1198fe56b9e6SYuval Mintz return rc; 1199fe56b9e6SYuval Mintz } 1200fe56b9e6SYuval Mintz } 1201fe56b9e6SYuval Mintz 1202fe56b9e6SYuval Mintz return rc; 1203fe56b9e6SYuval Mintz } 1204fe56b9e6SYuval Mintz 1205fe56b9e6SYuval Mintz /* Free hwfn memory and resources acquired in hw_hwfn_prepare */ 1206fe56b9e6SYuval Mintz static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn) 1207fe56b9e6SYuval Mintz { 1208fe56b9e6SYuval Mintz qed_ptt_pool_free(p_hwfn); 1209fe56b9e6SYuval Mintz kfree(p_hwfn->hw_info.p_igu_info); 1210fe56b9e6SYuval Mintz } 1211fe56b9e6SYuval Mintz 1212fe56b9e6SYuval Mintz /* Setup bar access */ 121312e09c69SYuval Mintz static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn) 1214fe56b9e6SYuval Mintz { 1215fe56b9e6SYuval Mintz /* clear indirect access */ 1216fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0); 1217fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0); 1218fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0); 1219fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0); 1220fe56b9e6SYuval Mintz 1221fe56b9e6SYuval Mintz /* Clean Previous errors if such exist */ 1222fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1223fe56b9e6SYuval Mintz PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1224fe56b9e6SYuval Mintz 1 << p_hwfn->abs_pf_id); 1225fe56b9e6SYuval Mintz 1226fe56b9e6SYuval Mintz /* enable internal target-read */ 1227fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1228fe56b9e6SYuval Mintz PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 1229fe56b9e6SYuval Mintz } 1230fe56b9e6SYuval Mintz 1231fe56b9e6SYuval Mintz static void get_function_id(struct qed_hwfn *p_hwfn) 1232fe56b9e6SYuval Mintz { 1233fe56b9e6SYuval Mintz /* ME Register */ 1234fe56b9e6SYuval Mintz p_hwfn->hw_info.opaque_fid = (u16)REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR); 1235fe56b9e6SYuval Mintz 1236fe56b9e6SYuval Mintz p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); 1237fe56b9e6SYuval Mintz 1238fe56b9e6SYuval Mintz p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf; 1239fe56b9e6SYuval Mintz p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 1240fe56b9e6SYuval Mintz PXP_CONCRETE_FID_PFID); 1241fe56b9e6SYuval Mintz p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 1242fe56b9e6SYuval Mintz PXP_CONCRETE_FID_PORT); 1243fe56b9e6SYuval Mintz } 1244fe56b9e6SYuval Mintz 124525c089d7SYuval Mintz static void qed_hw_set_feat(struct qed_hwfn *p_hwfn) 124625c089d7SYuval Mintz { 124725c089d7SYuval Mintz u32 *feat_num = p_hwfn->hw_info.feat_num; 124825c089d7SYuval Mintz int num_features = 1; 124925c089d7SYuval Mintz 125025c089d7SYuval Mintz feat_num[QED_PF_L2_QUE] = min_t(u32, RESC_NUM(p_hwfn, QED_SB) / 125125c089d7SYuval Mintz num_features, 125225c089d7SYuval Mintz RESC_NUM(p_hwfn, QED_L2_QUEUE)); 125325c089d7SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, 125425c089d7SYuval Mintz "#PF_L2_QUEUES=%d #SBS=%d num_features=%d\n", 125525c089d7SYuval Mintz feat_num[QED_PF_L2_QUE], RESC_NUM(p_hwfn, QED_SB), 125625c089d7SYuval Mintz num_features); 125725c089d7SYuval Mintz } 125825c089d7SYuval Mintz 1259fe56b9e6SYuval Mintz static void qed_hw_get_resc(struct qed_hwfn *p_hwfn) 1260fe56b9e6SYuval Mintz { 1261fe56b9e6SYuval Mintz u32 *resc_start = p_hwfn->hw_info.resc_start; 12621408cc1fSYuval Mintz u8 num_funcs = p_hwfn->num_funcs_on_engine; 1263fe56b9e6SYuval Mintz u32 *resc_num = p_hwfn->hw_info.resc_num; 12644ac801b7SYuval Mintz struct qed_sb_cnt_info sb_cnt_info; 126508feecd7SYuval Mintz int i, max_vf_vlan_filters; 1266fe56b9e6SYuval Mintz 12674ac801b7SYuval Mintz memset(&sb_cnt_info, 0, sizeof(sb_cnt_info)); 126808feecd7SYuval Mintz 126908feecd7SYuval Mintz #ifdef CONFIG_QED_SRIOV 127008feecd7SYuval Mintz max_vf_vlan_filters = QED_ETH_MAX_VF_NUM_VLAN_FILTERS; 127108feecd7SYuval Mintz #else 127208feecd7SYuval Mintz max_vf_vlan_filters = 0; 127308feecd7SYuval Mintz #endif 127408feecd7SYuval Mintz 12754ac801b7SYuval Mintz qed_int_get_num_sbs(p_hwfn, &sb_cnt_info); 12764ac801b7SYuval Mintz 1277fe56b9e6SYuval Mintz resc_num[QED_SB] = min_t(u32, 1278fe56b9e6SYuval Mintz (MAX_SB_PER_PATH_BB / num_funcs), 12794ac801b7SYuval Mintz sb_cnt_info.sb_cnt); 128025c089d7SYuval Mintz resc_num[QED_L2_QUEUE] = MAX_NUM_L2_QUEUES_BB / num_funcs; 1281fe56b9e6SYuval Mintz resc_num[QED_VPORT] = MAX_NUM_VPORTS_BB / num_funcs; 128225c089d7SYuval Mintz resc_num[QED_RSS_ENG] = ETH_RSS_ENGINE_NUM_BB / num_funcs; 1283fe56b9e6SYuval Mintz resc_num[QED_PQ] = MAX_QM_TX_QUEUES_BB / num_funcs; 1284fe56b9e6SYuval Mintz resc_num[QED_RL] = 8; 128525c089d7SYuval Mintz resc_num[QED_MAC] = ETH_NUM_MAC_FILTERS / num_funcs; 128625c089d7SYuval Mintz resc_num[QED_VLAN] = (ETH_NUM_VLAN_FILTERS - 1 /*For vlan0*/) / 128725c089d7SYuval Mintz num_funcs; 1288fe56b9e6SYuval Mintz resc_num[QED_ILT] = 950; 1289fe56b9e6SYuval Mintz 1290fe56b9e6SYuval Mintz for (i = 0; i < QED_MAX_RESC; i++) 1291fe56b9e6SYuval Mintz resc_start[i] = resc_num[i] * p_hwfn->rel_pf_id; 1292fe56b9e6SYuval Mintz 129325c089d7SYuval Mintz qed_hw_set_feat(p_hwfn); 129425c089d7SYuval Mintz 1295fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, 1296fe56b9e6SYuval Mintz "The numbers for each resource are:\n" 1297fe56b9e6SYuval Mintz "SB = %d start = %d\n" 129825c089d7SYuval Mintz "L2_QUEUE = %d start = %d\n" 1299fe56b9e6SYuval Mintz "VPORT = %d start = %d\n" 1300fe56b9e6SYuval Mintz "PQ = %d start = %d\n" 1301fe56b9e6SYuval Mintz "RL = %d start = %d\n" 130225c089d7SYuval Mintz "MAC = %d start = %d\n" 130325c089d7SYuval Mintz "VLAN = %d start = %d\n" 1304fe56b9e6SYuval Mintz "ILT = %d start = %d\n", 1305fe56b9e6SYuval Mintz p_hwfn->hw_info.resc_num[QED_SB], 1306fe56b9e6SYuval Mintz p_hwfn->hw_info.resc_start[QED_SB], 130725c089d7SYuval Mintz p_hwfn->hw_info.resc_num[QED_L2_QUEUE], 130825c089d7SYuval Mintz p_hwfn->hw_info.resc_start[QED_L2_QUEUE], 1309fe56b9e6SYuval Mintz p_hwfn->hw_info.resc_num[QED_VPORT], 1310fe56b9e6SYuval Mintz p_hwfn->hw_info.resc_start[QED_VPORT], 1311fe56b9e6SYuval Mintz p_hwfn->hw_info.resc_num[QED_PQ], 1312fe56b9e6SYuval Mintz p_hwfn->hw_info.resc_start[QED_PQ], 1313fe56b9e6SYuval Mintz p_hwfn->hw_info.resc_num[QED_RL], 1314fe56b9e6SYuval Mintz p_hwfn->hw_info.resc_start[QED_RL], 131525c089d7SYuval Mintz p_hwfn->hw_info.resc_num[QED_MAC], 131625c089d7SYuval Mintz p_hwfn->hw_info.resc_start[QED_MAC], 131725c089d7SYuval Mintz p_hwfn->hw_info.resc_num[QED_VLAN], 131825c089d7SYuval Mintz p_hwfn->hw_info.resc_start[QED_VLAN], 1319fe56b9e6SYuval Mintz p_hwfn->hw_info.resc_num[QED_ILT], 1320fe56b9e6SYuval Mintz p_hwfn->hw_info.resc_start[QED_ILT]); 1321fe56b9e6SYuval Mintz } 1322fe56b9e6SYuval Mintz 1323fe56b9e6SYuval Mintz static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, 1324fe56b9e6SYuval Mintz struct qed_ptt *p_ptt) 1325fe56b9e6SYuval Mintz { 1326cc875c2eSYuval Mintz u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg; 1327fc48b7a6SYuval Mintz u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities; 1328cc875c2eSYuval Mintz struct qed_mcp_link_params *link; 1329fe56b9e6SYuval Mintz 1330fe56b9e6SYuval Mintz /* Read global nvm_cfg address */ 1331fe56b9e6SYuval Mintz nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 1332fe56b9e6SYuval Mintz 1333fe56b9e6SYuval Mintz /* Verify MCP has initialized it */ 1334fe56b9e6SYuval Mintz if (!nvm_cfg_addr) { 1335fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 1336fe56b9e6SYuval Mintz return -EINVAL; 1337fe56b9e6SYuval Mintz } 1338fe56b9e6SYuval Mintz 1339fe56b9e6SYuval Mintz /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */ 1340fe56b9e6SYuval Mintz nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 1341fe56b9e6SYuval Mintz 1342cc875c2eSYuval Mintz addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1343cc875c2eSYuval Mintz offsetof(struct nvm_cfg1, glob) + 1344cc875c2eSYuval Mintz offsetof(struct nvm_cfg1_glob, core_cfg); 1345cc875c2eSYuval Mintz 1346cc875c2eSYuval Mintz core_cfg = qed_rd(p_hwfn, p_ptt, addr); 1347cc875c2eSYuval Mintz 1348cc875c2eSYuval Mintz switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >> 1349cc875c2eSYuval Mintz NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) { 1350351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G: 1351cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G; 1352cc875c2eSYuval Mintz break; 1353351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G: 1354cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G; 1355cc875c2eSYuval Mintz break; 1356351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G: 1357cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G; 1358cc875c2eSYuval Mintz break; 1359351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F: 1360cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F; 1361cc875c2eSYuval Mintz break; 1362351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E: 1363cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E; 1364cc875c2eSYuval Mintz break; 1365351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G: 1366cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G; 1367cc875c2eSYuval Mintz break; 1368351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G: 1369cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G; 1370cc875c2eSYuval Mintz break; 1371351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G: 1372cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G; 1373cc875c2eSYuval Mintz break; 1374351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G: 1375cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G; 1376cc875c2eSYuval Mintz break; 1377cc875c2eSYuval Mintz default: 1378cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", 1379cc875c2eSYuval Mintz core_cfg); 1380cc875c2eSYuval Mintz break; 1381cc875c2eSYuval Mintz } 1382cc875c2eSYuval Mintz 1383cc875c2eSYuval Mintz /* Read default link configuration */ 1384cc875c2eSYuval Mintz link = &p_hwfn->mcp_info->link_input; 1385cc875c2eSYuval Mintz port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1386cc875c2eSYuval Mintz offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 1387cc875c2eSYuval Mintz link_temp = qed_rd(p_hwfn, p_ptt, 1388cc875c2eSYuval Mintz port_cfg_addr + 1389cc875c2eSYuval Mintz offsetof(struct nvm_cfg1_port, speed_cap_mask)); 1390cc875c2eSYuval Mintz link->speed.advertised_speeds = 1391cc875c2eSYuval Mintz link_temp & NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK; 1392cc875c2eSYuval Mintz 1393cc875c2eSYuval Mintz p_hwfn->mcp_info->link_capabilities.speed_capabilities = 1394cc875c2eSYuval Mintz link->speed.advertised_speeds; 1395cc875c2eSYuval Mintz 1396cc875c2eSYuval Mintz link_temp = qed_rd(p_hwfn, p_ptt, 1397cc875c2eSYuval Mintz port_cfg_addr + 1398cc875c2eSYuval Mintz offsetof(struct nvm_cfg1_port, link_settings)); 1399cc875c2eSYuval Mintz switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >> 1400cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) { 1401cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG: 1402cc875c2eSYuval Mintz link->speed.autoneg = true; 1403cc875c2eSYuval Mintz break; 1404cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_1G: 1405cc875c2eSYuval Mintz link->speed.forced_speed = 1000; 1406cc875c2eSYuval Mintz break; 1407cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_10G: 1408cc875c2eSYuval Mintz link->speed.forced_speed = 10000; 1409cc875c2eSYuval Mintz break; 1410cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_25G: 1411cc875c2eSYuval Mintz link->speed.forced_speed = 25000; 1412cc875c2eSYuval Mintz break; 1413cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_40G: 1414cc875c2eSYuval Mintz link->speed.forced_speed = 40000; 1415cc875c2eSYuval Mintz break; 1416cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_50G: 1417cc875c2eSYuval Mintz link->speed.forced_speed = 50000; 1418cc875c2eSYuval Mintz break; 1419351a4dedSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G: 1420cc875c2eSYuval Mintz link->speed.forced_speed = 100000; 1421cc875c2eSYuval Mintz break; 1422cc875c2eSYuval Mintz default: 1423cc875c2eSYuval Mintz DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", 1424cc875c2eSYuval Mintz link_temp); 1425cc875c2eSYuval Mintz } 1426cc875c2eSYuval Mintz 1427cc875c2eSYuval Mintz link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK; 1428cc875c2eSYuval Mintz link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET; 1429cc875c2eSYuval Mintz link->pause.autoneg = !!(link_temp & 1430cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG); 1431cc875c2eSYuval Mintz link->pause.forced_rx = !!(link_temp & 1432cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX); 1433cc875c2eSYuval Mintz link->pause.forced_tx = !!(link_temp & 1434cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX); 1435cc875c2eSYuval Mintz link->loopback_mode = 0; 1436cc875c2eSYuval Mintz 1437cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1438cc875c2eSYuval Mintz "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n", 1439cc875c2eSYuval Mintz link->speed.forced_speed, link->speed.advertised_speeds, 1440cc875c2eSYuval Mintz link->speed.autoneg, link->pause.autoneg); 1441cc875c2eSYuval Mintz 1442fe56b9e6SYuval Mintz /* Read Multi-function information from shmem */ 1443fe56b9e6SYuval Mintz addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1444fe56b9e6SYuval Mintz offsetof(struct nvm_cfg1, glob) + 1445fe56b9e6SYuval Mintz offsetof(struct nvm_cfg1_glob, generic_cont0); 1446fe56b9e6SYuval Mintz 1447fe56b9e6SYuval Mintz generic_cont0 = qed_rd(p_hwfn, p_ptt, addr); 1448fe56b9e6SYuval Mintz 1449fe56b9e6SYuval Mintz mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >> 1450fe56b9e6SYuval Mintz NVM_CFG1_GLOB_MF_MODE_OFFSET; 1451fe56b9e6SYuval Mintz 1452fe56b9e6SYuval Mintz switch (mf_mode) { 1453fe56b9e6SYuval Mintz case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED: 1454fc48b7a6SYuval Mintz p_hwfn->cdev->mf_mode = QED_MF_OVLAN; 1455fe56b9e6SYuval Mintz break; 1456fe56b9e6SYuval Mintz case NVM_CFG1_GLOB_MF_MODE_NPAR1_0: 1457fc48b7a6SYuval Mintz p_hwfn->cdev->mf_mode = QED_MF_NPAR; 1458fe56b9e6SYuval Mintz break; 1459fc48b7a6SYuval Mintz case NVM_CFG1_GLOB_MF_MODE_DEFAULT: 1460fc48b7a6SYuval Mintz p_hwfn->cdev->mf_mode = QED_MF_DEFAULT; 1461fe56b9e6SYuval Mintz break; 1462fe56b9e6SYuval Mintz } 1463fe56b9e6SYuval Mintz DP_INFO(p_hwfn, "Multi function mode is %08x\n", 1464fe56b9e6SYuval Mintz p_hwfn->cdev->mf_mode); 1465fe56b9e6SYuval Mintz 1466fc48b7a6SYuval Mintz /* Read Multi-function information from shmem */ 1467fc48b7a6SYuval Mintz addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1468fc48b7a6SYuval Mintz offsetof(struct nvm_cfg1, glob) + 1469fc48b7a6SYuval Mintz offsetof(struct nvm_cfg1_glob, device_capabilities); 1470fc48b7a6SYuval Mintz 1471fc48b7a6SYuval Mintz device_capabilities = qed_rd(p_hwfn, p_ptt, addr); 1472fc48b7a6SYuval Mintz if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET) 1473fc48b7a6SYuval Mintz __set_bit(QED_DEV_CAP_ETH, 1474fc48b7a6SYuval Mintz &p_hwfn->hw_info.device_capabilities); 1475c5ac9319SYuval Mintz if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI) 1476c5ac9319SYuval Mintz __set_bit(QED_DEV_CAP_ISCSI, 1477c5ac9319SYuval Mintz &p_hwfn->hw_info.device_capabilities); 1478c5ac9319SYuval Mintz if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE) 1479c5ac9319SYuval Mintz __set_bit(QED_DEV_CAP_ROCE, 1480c5ac9319SYuval Mintz &p_hwfn->hw_info.device_capabilities); 1481fc48b7a6SYuval Mintz 1482fe56b9e6SYuval Mintz return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt); 1483fe56b9e6SYuval Mintz } 1484fe56b9e6SYuval Mintz 14851408cc1fSYuval Mintz static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 14861408cc1fSYuval Mintz { 14871408cc1fSYuval Mintz u32 reg_function_hide, tmp, eng_mask; 14881408cc1fSYuval Mintz u8 num_funcs; 14891408cc1fSYuval Mintz 14901408cc1fSYuval Mintz num_funcs = MAX_NUM_PFS_BB; 14911408cc1fSYuval Mintz 14921408cc1fSYuval Mintz /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values 14931408cc1fSYuval Mintz * in the other bits are selected. 14941408cc1fSYuval Mintz * Bits 1-15 are for functions 1-15, respectively, and their value is 14951408cc1fSYuval Mintz * '0' only for enabled functions (function 0 always exists and 14961408cc1fSYuval Mintz * enabled). 14971408cc1fSYuval Mintz * In case of CMT, only the "even" functions are enabled, and thus the 14981408cc1fSYuval Mintz * number of functions for both hwfns is learnt from the same bits. 14991408cc1fSYuval Mintz */ 15001408cc1fSYuval Mintz reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE); 15011408cc1fSYuval Mintz 15021408cc1fSYuval Mintz if (reg_function_hide & 0x1) { 15031408cc1fSYuval Mintz if (QED_PATH_ID(p_hwfn) && p_hwfn->cdev->num_hwfns == 1) { 15041408cc1fSYuval Mintz num_funcs = 0; 15051408cc1fSYuval Mintz eng_mask = 0xaaaa; 15061408cc1fSYuval Mintz } else { 15071408cc1fSYuval Mintz num_funcs = 1; 15081408cc1fSYuval Mintz eng_mask = 0x5554; 15091408cc1fSYuval Mintz } 15101408cc1fSYuval Mintz 15111408cc1fSYuval Mintz /* Get the number of the enabled functions on the engine */ 15121408cc1fSYuval Mintz tmp = (reg_function_hide ^ 0xffffffff) & eng_mask; 15131408cc1fSYuval Mintz while (tmp) { 15141408cc1fSYuval Mintz if (tmp & 0x1) 15151408cc1fSYuval Mintz num_funcs++; 15161408cc1fSYuval Mintz tmp >>= 0x1; 15171408cc1fSYuval Mintz } 15181408cc1fSYuval Mintz } 15191408cc1fSYuval Mintz 15201408cc1fSYuval Mintz p_hwfn->num_funcs_on_engine = num_funcs; 15211408cc1fSYuval Mintz 15221408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, 15231408cc1fSYuval Mintz NETIF_MSG_PROBE, 15241408cc1fSYuval Mintz "PF [rel_id %d, abs_id %d] within the %d enabled functions on the engine\n", 15251408cc1fSYuval Mintz p_hwfn->rel_pf_id, 15261408cc1fSYuval Mintz p_hwfn->abs_pf_id, 15271408cc1fSYuval Mintz p_hwfn->num_funcs_on_engine); 15281408cc1fSYuval Mintz } 15291408cc1fSYuval Mintz 1530fe56b9e6SYuval Mintz static int 1531fe56b9e6SYuval Mintz qed_get_hw_info(struct qed_hwfn *p_hwfn, 1532fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1533fe56b9e6SYuval Mintz enum qed_pci_personality personality) 1534fe56b9e6SYuval Mintz { 1535fe56b9e6SYuval Mintz u32 port_mode; 1536fe56b9e6SYuval Mintz int rc; 1537fe56b9e6SYuval Mintz 153832a47e72SYuval Mintz /* Since all information is common, only first hwfns should do this */ 153932a47e72SYuval Mintz if (IS_LEAD_HWFN(p_hwfn)) { 154032a47e72SYuval Mintz rc = qed_iov_hw_info(p_hwfn); 154132a47e72SYuval Mintz if (rc) 154232a47e72SYuval Mintz return rc; 154332a47e72SYuval Mintz } 154432a47e72SYuval Mintz 1545fe56b9e6SYuval Mintz /* Read the port mode */ 1546fe56b9e6SYuval Mintz port_mode = qed_rd(p_hwfn, p_ptt, 1547fe56b9e6SYuval Mintz CNIG_REG_NW_PORT_MODE_BB_B0); 1548fe56b9e6SYuval Mintz 1549fe56b9e6SYuval Mintz if (port_mode < 3) { 1550fe56b9e6SYuval Mintz p_hwfn->cdev->num_ports_in_engines = 1; 1551fe56b9e6SYuval Mintz } else if (port_mode <= 5) { 1552fe56b9e6SYuval Mintz p_hwfn->cdev->num_ports_in_engines = 2; 1553fe56b9e6SYuval Mintz } else { 1554fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n", 1555fe56b9e6SYuval Mintz p_hwfn->cdev->num_ports_in_engines); 1556fe56b9e6SYuval Mintz 1557fe56b9e6SYuval Mintz /* Default num_ports_in_engines to something */ 1558fe56b9e6SYuval Mintz p_hwfn->cdev->num_ports_in_engines = 1; 1559fe56b9e6SYuval Mintz } 1560fe56b9e6SYuval Mintz 1561fe56b9e6SYuval Mintz qed_hw_get_nvm_info(p_hwfn, p_ptt); 1562fe56b9e6SYuval Mintz 1563fe56b9e6SYuval Mintz rc = qed_int_igu_read_cam(p_hwfn, p_ptt); 1564fe56b9e6SYuval Mintz if (rc) 1565fe56b9e6SYuval Mintz return rc; 1566fe56b9e6SYuval Mintz 1567fe56b9e6SYuval Mintz if (qed_mcp_is_init(p_hwfn)) 1568fe56b9e6SYuval Mintz ether_addr_copy(p_hwfn->hw_info.hw_mac_addr, 1569fe56b9e6SYuval Mintz p_hwfn->mcp_info->func_info.mac); 1570fe56b9e6SYuval Mintz else 1571fe56b9e6SYuval Mintz eth_random_addr(p_hwfn->hw_info.hw_mac_addr); 1572fe56b9e6SYuval Mintz 1573fe56b9e6SYuval Mintz if (qed_mcp_is_init(p_hwfn)) { 1574fe56b9e6SYuval Mintz if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET) 1575fe56b9e6SYuval Mintz p_hwfn->hw_info.ovlan = 1576fe56b9e6SYuval Mintz p_hwfn->mcp_info->func_info.ovlan; 1577fe56b9e6SYuval Mintz 1578fe56b9e6SYuval Mintz qed_mcp_cmd_port_init(p_hwfn, p_ptt); 1579fe56b9e6SYuval Mintz } 1580fe56b9e6SYuval Mintz 1581fe56b9e6SYuval Mintz if (qed_mcp_is_init(p_hwfn)) { 1582fe56b9e6SYuval Mintz enum qed_pci_personality protocol; 1583fe56b9e6SYuval Mintz 1584fe56b9e6SYuval Mintz protocol = p_hwfn->mcp_info->func_info.protocol; 1585fe56b9e6SYuval Mintz p_hwfn->hw_info.personality = protocol; 1586fe56b9e6SYuval Mintz } 1587fe56b9e6SYuval Mintz 15881408cc1fSYuval Mintz qed_get_num_funcs(p_hwfn, p_ptt); 15891408cc1fSYuval Mintz 1590fe56b9e6SYuval Mintz qed_hw_get_resc(p_hwfn); 1591fe56b9e6SYuval Mintz 1592fe56b9e6SYuval Mintz return rc; 1593fe56b9e6SYuval Mintz } 1594fe56b9e6SYuval Mintz 159512e09c69SYuval Mintz static int qed_get_dev_info(struct qed_dev *cdev) 1596fe56b9e6SYuval Mintz { 1597fc48b7a6SYuval Mintz struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 1598fe56b9e6SYuval Mintz u32 tmp; 1599fe56b9e6SYuval Mintz 1600fc48b7a6SYuval Mintz /* Read Vendor Id / Device Id */ 1601fc48b7a6SYuval Mintz pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, 1602fc48b7a6SYuval Mintz &cdev->vendor_id); 1603fc48b7a6SYuval Mintz pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, 1604fc48b7a6SYuval Mintz &cdev->device_id); 1605fc48b7a6SYuval Mintz cdev->chip_num = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, 1606fe56b9e6SYuval Mintz MISCS_REG_CHIP_NUM); 1607fc48b7a6SYuval Mintz cdev->chip_rev = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, 1608fe56b9e6SYuval Mintz MISCS_REG_CHIP_REV); 1609fe56b9e6SYuval Mintz MASK_FIELD(CHIP_REV, cdev->chip_rev); 1610fe56b9e6SYuval Mintz 1611fc48b7a6SYuval Mintz cdev->type = QED_DEV_TYPE_BB; 1612fe56b9e6SYuval Mintz /* Learn number of HW-functions */ 1613fc48b7a6SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_main_ptt, 1614fe56b9e6SYuval Mintz MISCS_REG_CMT_ENABLED_FOR_PAIR); 1615fe56b9e6SYuval Mintz 1616fc48b7a6SYuval Mintz if (tmp & (1 << p_hwfn->rel_pf_id)) { 1617fe56b9e6SYuval Mintz DP_NOTICE(cdev->hwfns, "device in CMT mode\n"); 1618fe56b9e6SYuval Mintz cdev->num_hwfns = 2; 1619fe56b9e6SYuval Mintz } else { 1620fe56b9e6SYuval Mintz cdev->num_hwfns = 1; 1621fe56b9e6SYuval Mintz } 1622fe56b9e6SYuval Mintz 1623fc48b7a6SYuval Mintz cdev->chip_bond_id = qed_rd(p_hwfn, p_hwfn->p_main_ptt, 1624fe56b9e6SYuval Mintz MISCS_REG_CHIP_TEST_REG) >> 4; 1625fe56b9e6SYuval Mintz MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id); 1626fc48b7a6SYuval Mintz cdev->chip_metal = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, 1627fe56b9e6SYuval Mintz MISCS_REG_CHIP_METAL); 1628fe56b9e6SYuval Mintz MASK_FIELD(CHIP_METAL, cdev->chip_metal); 1629fe56b9e6SYuval Mintz 1630fe56b9e6SYuval Mintz DP_INFO(cdev->hwfns, 1631fe56b9e6SYuval Mintz "Chip details - Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n", 1632fe56b9e6SYuval Mintz cdev->chip_num, cdev->chip_rev, 1633fe56b9e6SYuval Mintz cdev->chip_bond_id, cdev->chip_metal); 163412e09c69SYuval Mintz 163512e09c69SYuval Mintz if (QED_IS_BB(cdev) && CHIP_REV_IS_A0(cdev)) { 163612e09c69SYuval Mintz DP_NOTICE(cdev->hwfns, 163712e09c69SYuval Mintz "The chip type/rev (BB A0) is not supported!\n"); 163812e09c69SYuval Mintz return -EINVAL; 163912e09c69SYuval Mintz } 164012e09c69SYuval Mintz 164112e09c69SYuval Mintz return 0; 1642fe56b9e6SYuval Mintz } 1643fe56b9e6SYuval Mintz 1644fe56b9e6SYuval Mintz static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn, 1645fe56b9e6SYuval Mintz void __iomem *p_regview, 1646fe56b9e6SYuval Mintz void __iomem *p_doorbells, 1647fe56b9e6SYuval Mintz enum qed_pci_personality personality) 1648fe56b9e6SYuval Mintz { 1649fe56b9e6SYuval Mintz int rc = 0; 1650fe56b9e6SYuval Mintz 1651fe56b9e6SYuval Mintz /* Split PCI bars evenly between hwfns */ 1652fe56b9e6SYuval Mintz p_hwfn->regview = p_regview; 1653fe56b9e6SYuval Mintz p_hwfn->doorbells = p_doorbells; 1654fe56b9e6SYuval Mintz 16551408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 16561408cc1fSYuval Mintz return qed_vf_hw_prepare(p_hwfn); 16571408cc1fSYuval Mintz 1658fe56b9e6SYuval Mintz /* Validate that chip access is feasible */ 1659fe56b9e6SYuval Mintz if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) { 1660fe56b9e6SYuval Mintz DP_ERR(p_hwfn, 1661fe56b9e6SYuval Mintz "Reading the ME register returns all Fs; Preventing further chip access\n"); 1662fe56b9e6SYuval Mintz return -EINVAL; 1663fe56b9e6SYuval Mintz } 1664fe56b9e6SYuval Mintz 1665fe56b9e6SYuval Mintz get_function_id(p_hwfn); 1666fe56b9e6SYuval Mintz 166712e09c69SYuval Mintz /* Allocate PTT pool */ 166812e09c69SYuval Mintz rc = qed_ptt_pool_alloc(p_hwfn); 1669fe56b9e6SYuval Mintz if (rc) { 1670fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed to prepare hwfn's hw\n"); 1671fe56b9e6SYuval Mintz goto err0; 1672fe56b9e6SYuval Mintz } 1673fe56b9e6SYuval Mintz 167412e09c69SYuval Mintz /* Allocate the main PTT */ 167512e09c69SYuval Mintz p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN); 167612e09c69SYuval Mintz 1677fe56b9e6SYuval Mintz /* First hwfn learns basic information, e.g., number of hwfns */ 167812e09c69SYuval Mintz if (!p_hwfn->my_id) { 167912e09c69SYuval Mintz rc = qed_get_dev_info(p_hwfn->cdev); 168012e09c69SYuval Mintz if (rc != 0) 168112e09c69SYuval Mintz goto err1; 168212e09c69SYuval Mintz } 168312e09c69SYuval Mintz 168412e09c69SYuval Mintz qed_hw_hwfn_prepare(p_hwfn); 1685fe56b9e6SYuval Mintz 1686fe56b9e6SYuval Mintz /* Initialize MCP structure */ 1687fe56b9e6SYuval Mintz rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt); 1688fe56b9e6SYuval Mintz if (rc) { 1689fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed initializing mcp command\n"); 1690fe56b9e6SYuval Mintz goto err1; 1691fe56b9e6SYuval Mintz } 1692fe56b9e6SYuval Mintz 1693fe56b9e6SYuval Mintz /* Read the device configuration information from the HW and SHMEM */ 1694fe56b9e6SYuval Mintz rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality); 1695fe56b9e6SYuval Mintz if (rc) { 1696fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed to get HW information\n"); 1697fe56b9e6SYuval Mintz goto err2; 1698fe56b9e6SYuval Mintz } 1699fe56b9e6SYuval Mintz 1700fe56b9e6SYuval Mintz /* Allocate the init RT array and initialize the init-ops engine */ 1701fe56b9e6SYuval Mintz rc = qed_init_alloc(p_hwfn); 1702fe56b9e6SYuval Mintz if (rc) { 1703fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed to allocate the init array\n"); 1704fe56b9e6SYuval Mintz goto err2; 1705fe56b9e6SYuval Mintz } 1706fe56b9e6SYuval Mintz 1707fe56b9e6SYuval Mintz return rc; 1708fe56b9e6SYuval Mintz err2: 170932a47e72SYuval Mintz if (IS_LEAD_HWFN(p_hwfn)) 171032a47e72SYuval Mintz qed_iov_free_hw_info(p_hwfn->cdev); 1711fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 1712fe56b9e6SYuval Mintz err1: 1713fe56b9e6SYuval Mintz qed_hw_hwfn_free(p_hwfn); 1714fe56b9e6SYuval Mintz err0: 1715fe56b9e6SYuval Mintz return rc; 1716fe56b9e6SYuval Mintz } 1717fe56b9e6SYuval Mintz 1718fe56b9e6SYuval Mintz int qed_hw_prepare(struct qed_dev *cdev, 1719fe56b9e6SYuval Mintz int personality) 1720fe56b9e6SYuval Mintz { 1721c78df14eSAriel Elior struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 1722c78df14eSAriel Elior int rc; 1723fe56b9e6SYuval Mintz 1724fe56b9e6SYuval Mintz /* Store the precompiled init data ptrs */ 17251408cc1fSYuval Mintz if (IS_PF(cdev)) 1726fe56b9e6SYuval Mintz qed_init_iro_array(cdev); 1727fe56b9e6SYuval Mintz 1728fe56b9e6SYuval Mintz /* Initialize the first hwfn - will learn number of hwfns */ 1729c78df14eSAriel Elior rc = qed_hw_prepare_single(p_hwfn, 1730c78df14eSAriel Elior cdev->regview, 1731fe56b9e6SYuval Mintz cdev->doorbells, personality); 1732fe56b9e6SYuval Mintz if (rc) 1733fe56b9e6SYuval Mintz return rc; 1734fe56b9e6SYuval Mintz 1735c78df14eSAriel Elior personality = p_hwfn->hw_info.personality; 1736fe56b9e6SYuval Mintz 1737fe56b9e6SYuval Mintz /* Initialize the rest of the hwfns */ 1738c78df14eSAriel Elior if (cdev->num_hwfns > 1) { 1739fe56b9e6SYuval Mintz void __iomem *p_regview, *p_doorbell; 1740c78df14eSAriel Elior u8 __iomem *addr; 1741fe56b9e6SYuval Mintz 1742c78df14eSAriel Elior /* adjust bar offset for second engine */ 1743c2035eeaSRam Amrani addr = cdev->regview + qed_hw_bar_size(p_hwfn, BAR_ID_0) / 2; 1744c78df14eSAriel Elior p_regview = addr; 1745c78df14eSAriel Elior 1746c78df14eSAriel Elior /* adjust doorbell bar offset for second engine */ 1747c2035eeaSRam Amrani addr = cdev->doorbells + qed_hw_bar_size(p_hwfn, BAR_ID_1) / 2; 1748c78df14eSAriel Elior p_doorbell = addr; 1749c78df14eSAriel Elior 1750c78df14eSAriel Elior /* prepare second hw function */ 1751c78df14eSAriel Elior rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview, 1752fe56b9e6SYuval Mintz p_doorbell, personality); 1753c78df14eSAriel Elior 1754c78df14eSAriel Elior /* in case of error, need to free the previously 1755c78df14eSAriel Elior * initiliazed hwfn 0. 1756c78df14eSAriel Elior */ 1757fe56b9e6SYuval Mintz if (rc) { 17581408cc1fSYuval Mintz if (IS_PF(cdev)) { 1759c78df14eSAriel Elior qed_init_free(p_hwfn); 1760c78df14eSAriel Elior qed_mcp_free(p_hwfn); 1761c78df14eSAriel Elior qed_hw_hwfn_free(p_hwfn); 1762fe56b9e6SYuval Mintz } 1763fe56b9e6SYuval Mintz } 17641408cc1fSYuval Mintz } 1765fe56b9e6SYuval Mintz 1766c78df14eSAriel Elior return rc; 1767fe56b9e6SYuval Mintz } 1768fe56b9e6SYuval Mintz 1769fe56b9e6SYuval Mintz void qed_hw_remove(struct qed_dev *cdev) 1770fe56b9e6SYuval Mintz { 1771fe56b9e6SYuval Mintz int i; 1772fe56b9e6SYuval Mintz 1773fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 1774fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1775fe56b9e6SYuval Mintz 17761408cc1fSYuval Mintz if (IS_VF(cdev)) { 17770b55e27dSYuval Mintz qed_vf_pf_release(p_hwfn); 17781408cc1fSYuval Mintz continue; 17791408cc1fSYuval Mintz } 17801408cc1fSYuval Mintz 1781fe56b9e6SYuval Mintz qed_init_free(p_hwfn); 1782fe56b9e6SYuval Mintz qed_hw_hwfn_free(p_hwfn); 1783fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 1784fe56b9e6SYuval Mintz } 178532a47e72SYuval Mintz 178632a47e72SYuval Mintz qed_iov_free_hw_info(cdev); 1787fe56b9e6SYuval Mintz } 1788fe56b9e6SYuval Mintz 1789a91eb52aSYuval Mintz static void qed_chain_free_next_ptr(struct qed_dev *cdev, 1790a91eb52aSYuval Mintz struct qed_chain *p_chain) 1791a91eb52aSYuval Mintz { 1792a91eb52aSYuval Mintz void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL; 1793a91eb52aSYuval Mintz dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0; 1794a91eb52aSYuval Mintz struct qed_chain_next *p_next; 1795a91eb52aSYuval Mintz u32 size, i; 1796a91eb52aSYuval Mintz 1797a91eb52aSYuval Mintz if (!p_virt) 1798a91eb52aSYuval Mintz return; 1799a91eb52aSYuval Mintz 1800a91eb52aSYuval Mintz size = p_chain->elem_size * p_chain->usable_per_page; 1801a91eb52aSYuval Mintz 1802a91eb52aSYuval Mintz for (i = 0; i < p_chain->page_cnt; i++) { 1803a91eb52aSYuval Mintz if (!p_virt) 1804a91eb52aSYuval Mintz break; 1805a91eb52aSYuval Mintz 1806a91eb52aSYuval Mintz p_next = (struct qed_chain_next *)((u8 *)p_virt + size); 1807a91eb52aSYuval Mintz p_virt_next = p_next->next_virt; 1808a91eb52aSYuval Mintz p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys); 1809a91eb52aSYuval Mintz 1810a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 1811a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, p_virt, p_phys); 1812a91eb52aSYuval Mintz 1813a91eb52aSYuval Mintz p_virt = p_virt_next; 1814a91eb52aSYuval Mintz p_phys = p_phys_next; 1815a91eb52aSYuval Mintz } 1816a91eb52aSYuval Mintz } 1817a91eb52aSYuval Mintz 1818a91eb52aSYuval Mintz static void qed_chain_free_single(struct qed_dev *cdev, 1819a91eb52aSYuval Mintz struct qed_chain *p_chain) 1820a91eb52aSYuval Mintz { 1821a91eb52aSYuval Mintz if (!p_chain->p_virt_addr) 1822a91eb52aSYuval Mintz return; 1823a91eb52aSYuval Mintz 1824a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 1825a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 1826a91eb52aSYuval Mintz p_chain->p_virt_addr, p_chain->p_phys_addr); 1827a91eb52aSYuval Mintz } 1828a91eb52aSYuval Mintz 1829a91eb52aSYuval Mintz static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain) 1830a91eb52aSYuval Mintz { 1831a91eb52aSYuval Mintz void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl; 1832a91eb52aSYuval Mintz u32 page_cnt = p_chain->page_cnt, i, pbl_size; 1833a91eb52aSYuval Mintz u8 *p_pbl_virt = p_chain->pbl.p_virt_table; 1834a91eb52aSYuval Mintz 1835a91eb52aSYuval Mintz if (!pp_virt_addr_tbl) 1836a91eb52aSYuval Mintz return; 1837a91eb52aSYuval Mintz 1838a91eb52aSYuval Mintz if (!p_chain->pbl.p_virt_table) 1839a91eb52aSYuval Mintz goto out; 1840a91eb52aSYuval Mintz 1841a91eb52aSYuval Mintz for (i = 0; i < page_cnt; i++) { 1842a91eb52aSYuval Mintz if (!pp_virt_addr_tbl[i]) 1843a91eb52aSYuval Mintz break; 1844a91eb52aSYuval Mintz 1845a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 1846a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 1847a91eb52aSYuval Mintz pp_virt_addr_tbl[i], 1848a91eb52aSYuval Mintz *(dma_addr_t *)p_pbl_virt); 1849a91eb52aSYuval Mintz 1850a91eb52aSYuval Mintz p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE; 1851a91eb52aSYuval Mintz } 1852a91eb52aSYuval Mintz 1853a91eb52aSYuval Mintz pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; 1854a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 1855a91eb52aSYuval Mintz pbl_size, 1856a91eb52aSYuval Mintz p_chain->pbl.p_virt_table, p_chain->pbl.p_phys_table); 1857a91eb52aSYuval Mintz out: 1858a91eb52aSYuval Mintz vfree(p_chain->pbl.pp_virt_addr_tbl); 1859a91eb52aSYuval Mintz } 1860a91eb52aSYuval Mintz 1861a91eb52aSYuval Mintz void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain) 1862a91eb52aSYuval Mintz { 1863a91eb52aSYuval Mintz switch (p_chain->mode) { 1864a91eb52aSYuval Mintz case QED_CHAIN_MODE_NEXT_PTR: 1865a91eb52aSYuval Mintz qed_chain_free_next_ptr(cdev, p_chain); 1866a91eb52aSYuval Mintz break; 1867a91eb52aSYuval Mintz case QED_CHAIN_MODE_SINGLE: 1868a91eb52aSYuval Mintz qed_chain_free_single(cdev, p_chain); 1869a91eb52aSYuval Mintz break; 1870a91eb52aSYuval Mintz case QED_CHAIN_MODE_PBL: 1871a91eb52aSYuval Mintz qed_chain_free_pbl(cdev, p_chain); 1872a91eb52aSYuval Mintz break; 1873a91eb52aSYuval Mintz } 1874a91eb52aSYuval Mintz } 1875a91eb52aSYuval Mintz 1876a91eb52aSYuval Mintz static int 1877a91eb52aSYuval Mintz qed_chain_alloc_sanity_check(struct qed_dev *cdev, 1878a91eb52aSYuval Mintz enum qed_chain_cnt_type cnt_type, 1879a91eb52aSYuval Mintz size_t elem_size, u32 page_cnt) 1880a91eb52aSYuval Mintz { 1881a91eb52aSYuval Mintz u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt; 1882a91eb52aSYuval Mintz 1883a91eb52aSYuval Mintz /* The actual chain size can be larger than the maximal possible value 1884a91eb52aSYuval Mintz * after rounding up the requested elements number to pages, and after 1885a91eb52aSYuval Mintz * taking into acount the unusuable elements (next-ptr elements). 1886a91eb52aSYuval Mintz * The size of a "u16" chain can be (U16_MAX + 1) since the chain 1887a91eb52aSYuval Mintz * size/capacity fields are of a u32 type. 1888a91eb52aSYuval Mintz */ 1889a91eb52aSYuval Mintz if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 && 1890a91eb52aSYuval Mintz chain_size > 0x10000) || 1891a91eb52aSYuval Mintz (cnt_type == QED_CHAIN_CNT_TYPE_U32 && 1892a91eb52aSYuval Mintz chain_size > 0x100000000ULL)) { 1893a91eb52aSYuval Mintz DP_NOTICE(cdev, 1894a91eb52aSYuval Mintz "The actual chain size (0x%llx) is larger than the maximal possible value\n", 1895a91eb52aSYuval Mintz chain_size); 1896a91eb52aSYuval Mintz return -EINVAL; 1897a91eb52aSYuval Mintz } 1898a91eb52aSYuval Mintz 1899a91eb52aSYuval Mintz return 0; 1900a91eb52aSYuval Mintz } 1901a91eb52aSYuval Mintz 1902a91eb52aSYuval Mintz static int 1903a91eb52aSYuval Mintz qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain) 1904a91eb52aSYuval Mintz { 1905a91eb52aSYuval Mintz void *p_virt = NULL, *p_virt_prev = NULL; 1906a91eb52aSYuval Mintz dma_addr_t p_phys = 0; 1907a91eb52aSYuval Mintz u32 i; 1908a91eb52aSYuval Mintz 1909a91eb52aSYuval Mintz for (i = 0; i < p_chain->page_cnt; i++) { 1910a91eb52aSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 1911a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 1912a91eb52aSYuval Mintz &p_phys, GFP_KERNEL); 1913a91eb52aSYuval Mintz if (!p_virt) { 1914a91eb52aSYuval Mintz DP_NOTICE(cdev, "Failed to allocate chain memory\n"); 1915a91eb52aSYuval Mintz return -ENOMEM; 1916a91eb52aSYuval Mintz } 1917a91eb52aSYuval Mintz 1918a91eb52aSYuval Mintz if (i == 0) { 1919a91eb52aSYuval Mintz qed_chain_init_mem(p_chain, p_virt, p_phys); 1920a91eb52aSYuval Mintz qed_chain_reset(p_chain); 1921a91eb52aSYuval Mintz } else { 1922a91eb52aSYuval Mintz qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, 1923a91eb52aSYuval Mintz p_virt, p_phys); 1924a91eb52aSYuval Mintz } 1925a91eb52aSYuval Mintz 1926a91eb52aSYuval Mintz p_virt_prev = p_virt; 1927a91eb52aSYuval Mintz } 1928a91eb52aSYuval Mintz /* Last page's next element should point to the beginning of the 1929a91eb52aSYuval Mintz * chain. 1930a91eb52aSYuval Mintz */ 1931a91eb52aSYuval Mintz qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, 1932a91eb52aSYuval Mintz p_chain->p_virt_addr, 1933a91eb52aSYuval Mintz p_chain->p_phys_addr); 1934a91eb52aSYuval Mintz 1935a91eb52aSYuval Mintz return 0; 1936a91eb52aSYuval Mintz } 1937a91eb52aSYuval Mintz 1938a91eb52aSYuval Mintz static int 1939a91eb52aSYuval Mintz qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain) 1940a91eb52aSYuval Mintz { 1941a91eb52aSYuval Mintz dma_addr_t p_phys = 0; 1942a91eb52aSYuval Mintz void *p_virt = NULL; 1943a91eb52aSYuval Mintz 1944a91eb52aSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 1945a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL); 1946a91eb52aSYuval Mintz if (!p_virt) { 1947a91eb52aSYuval Mintz DP_NOTICE(cdev, "Failed to allocate chain memory\n"); 1948a91eb52aSYuval Mintz return -ENOMEM; 1949a91eb52aSYuval Mintz } 1950a91eb52aSYuval Mintz 1951a91eb52aSYuval Mintz qed_chain_init_mem(p_chain, p_virt, p_phys); 1952a91eb52aSYuval Mintz qed_chain_reset(p_chain); 1953a91eb52aSYuval Mintz 1954a91eb52aSYuval Mintz return 0; 1955a91eb52aSYuval Mintz } 1956a91eb52aSYuval Mintz 1957a91eb52aSYuval Mintz static int qed_chain_alloc_pbl(struct qed_dev *cdev, struct qed_chain *p_chain) 1958a91eb52aSYuval Mintz { 1959a91eb52aSYuval Mintz u32 page_cnt = p_chain->page_cnt, size, i; 1960a91eb52aSYuval Mintz dma_addr_t p_phys = 0, p_pbl_phys = 0; 1961a91eb52aSYuval Mintz void **pp_virt_addr_tbl = NULL; 1962a91eb52aSYuval Mintz u8 *p_pbl_virt = NULL; 1963a91eb52aSYuval Mintz void *p_virt = NULL; 1964a91eb52aSYuval Mintz 1965a91eb52aSYuval Mintz size = page_cnt * sizeof(*pp_virt_addr_tbl); 1966a91eb52aSYuval Mintz pp_virt_addr_tbl = vmalloc(size); 1967a91eb52aSYuval Mintz if (!pp_virt_addr_tbl) { 1968a91eb52aSYuval Mintz DP_NOTICE(cdev, 1969a91eb52aSYuval Mintz "Failed to allocate memory for the chain virtual addresses table\n"); 1970a91eb52aSYuval Mintz return -ENOMEM; 1971a91eb52aSYuval Mintz } 1972a91eb52aSYuval Mintz memset(pp_virt_addr_tbl, 0, size); 1973a91eb52aSYuval Mintz 1974a91eb52aSYuval Mintz /* The allocation of the PBL table is done with its full size, since it 1975a91eb52aSYuval Mintz * is expected to be successive. 1976a91eb52aSYuval Mintz * qed_chain_init_pbl_mem() is called even in a case of an allocation 1977a91eb52aSYuval Mintz * failure, since pp_virt_addr_tbl was previously allocated, and it 1978a91eb52aSYuval Mintz * should be saved to allow its freeing during the error flow. 1979a91eb52aSYuval Mintz */ 1980a91eb52aSYuval Mintz size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; 1981a91eb52aSYuval Mintz p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev, 1982a91eb52aSYuval Mintz size, &p_pbl_phys, GFP_KERNEL); 1983a91eb52aSYuval Mintz qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys, 1984a91eb52aSYuval Mintz pp_virt_addr_tbl); 1985a91eb52aSYuval Mintz if (!p_pbl_virt) { 1986a91eb52aSYuval Mintz DP_NOTICE(cdev, "Failed to allocate chain pbl memory\n"); 1987a91eb52aSYuval Mintz return -ENOMEM; 1988a91eb52aSYuval Mintz } 1989a91eb52aSYuval Mintz 1990a91eb52aSYuval Mintz for (i = 0; i < page_cnt; i++) { 1991a91eb52aSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 1992a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 1993a91eb52aSYuval Mintz &p_phys, GFP_KERNEL); 1994a91eb52aSYuval Mintz if (!p_virt) { 1995a91eb52aSYuval Mintz DP_NOTICE(cdev, "Failed to allocate chain memory\n"); 1996a91eb52aSYuval Mintz return -ENOMEM; 1997a91eb52aSYuval Mintz } 1998a91eb52aSYuval Mintz 1999a91eb52aSYuval Mintz if (i == 0) { 2000a91eb52aSYuval Mintz qed_chain_init_mem(p_chain, p_virt, p_phys); 2001a91eb52aSYuval Mintz qed_chain_reset(p_chain); 2002a91eb52aSYuval Mintz } 2003a91eb52aSYuval Mintz 2004a91eb52aSYuval Mintz /* Fill the PBL table with the physical address of the page */ 2005a91eb52aSYuval Mintz *(dma_addr_t *)p_pbl_virt = p_phys; 2006a91eb52aSYuval Mintz /* Keep the virtual address of the page */ 2007a91eb52aSYuval Mintz p_chain->pbl.pp_virt_addr_tbl[i] = p_virt; 2008a91eb52aSYuval Mintz 2009a91eb52aSYuval Mintz p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE; 2010a91eb52aSYuval Mintz } 2011a91eb52aSYuval Mintz 2012a91eb52aSYuval Mintz return 0; 2013a91eb52aSYuval Mintz } 2014a91eb52aSYuval Mintz 2015fe56b9e6SYuval Mintz int qed_chain_alloc(struct qed_dev *cdev, 2016fe56b9e6SYuval Mintz enum qed_chain_use_mode intended_use, 2017fe56b9e6SYuval Mintz enum qed_chain_mode mode, 2018a91eb52aSYuval Mintz enum qed_chain_cnt_type cnt_type, 2019a91eb52aSYuval Mintz u32 num_elems, size_t elem_size, struct qed_chain *p_chain) 2020fe56b9e6SYuval Mintz { 2021a91eb52aSYuval Mintz u32 page_cnt; 2022a91eb52aSYuval Mintz int rc = 0; 2023fe56b9e6SYuval Mintz 2024fe56b9e6SYuval Mintz if (mode == QED_CHAIN_MODE_SINGLE) 2025fe56b9e6SYuval Mintz page_cnt = 1; 2026fe56b9e6SYuval Mintz else 2027fe56b9e6SYuval Mintz page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode); 2028fe56b9e6SYuval Mintz 2029a91eb52aSYuval Mintz rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt); 2030a91eb52aSYuval Mintz if (rc) { 2031a91eb52aSYuval Mintz DP_NOTICE(cdev, 2032a91eb52aSYuval Mintz "Cannot allocate a chain with the given arguments:\n" 2033a91eb52aSYuval Mintz "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n", 2034a91eb52aSYuval Mintz intended_use, mode, cnt_type, num_elems, elem_size); 2035a91eb52aSYuval Mintz return rc; 2036fe56b9e6SYuval Mintz } 2037fe56b9e6SYuval Mintz 2038a91eb52aSYuval Mintz qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use, 2039a91eb52aSYuval Mintz mode, cnt_type); 2040fe56b9e6SYuval Mintz 2041a91eb52aSYuval Mintz switch (mode) { 2042a91eb52aSYuval Mintz case QED_CHAIN_MODE_NEXT_PTR: 2043a91eb52aSYuval Mintz rc = qed_chain_alloc_next_ptr(cdev, p_chain); 2044a91eb52aSYuval Mintz break; 2045a91eb52aSYuval Mintz case QED_CHAIN_MODE_SINGLE: 2046a91eb52aSYuval Mintz rc = qed_chain_alloc_single(cdev, p_chain); 2047a91eb52aSYuval Mintz break; 2048a91eb52aSYuval Mintz case QED_CHAIN_MODE_PBL: 2049a91eb52aSYuval Mintz rc = qed_chain_alloc_pbl(cdev, p_chain); 2050a91eb52aSYuval Mintz break; 2051fe56b9e6SYuval Mintz } 2052a91eb52aSYuval Mintz if (rc) 2053a91eb52aSYuval Mintz goto nomem; 2054fe56b9e6SYuval Mintz 2055fe56b9e6SYuval Mintz return 0; 2056fe56b9e6SYuval Mintz 2057fe56b9e6SYuval Mintz nomem: 2058a91eb52aSYuval Mintz qed_chain_free(cdev, p_chain); 2059a91eb52aSYuval Mintz return rc; 2060fe56b9e6SYuval Mintz } 2061fe56b9e6SYuval Mintz 2062a91eb52aSYuval Mintz int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id) 2063cee4d264SManish Chopra { 2064cee4d264SManish Chopra if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) { 2065cee4d264SManish Chopra u16 min, max; 2066cee4d264SManish Chopra 2067cee4d264SManish Chopra min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE); 2068cee4d264SManish Chopra max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE); 2069cee4d264SManish Chopra DP_NOTICE(p_hwfn, 2070cee4d264SManish Chopra "l2_queue id [%d] is not valid, available indices [%d - %d]\n", 2071cee4d264SManish Chopra src_id, min, max); 2072cee4d264SManish Chopra 2073cee4d264SManish Chopra return -EINVAL; 2074cee4d264SManish Chopra } 2075cee4d264SManish Chopra 2076cee4d264SManish Chopra *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id; 2077cee4d264SManish Chopra 2078cee4d264SManish Chopra return 0; 2079cee4d264SManish Chopra } 2080cee4d264SManish Chopra 2081cee4d264SManish Chopra int qed_fw_vport(struct qed_hwfn *p_hwfn, 2082cee4d264SManish Chopra u8 src_id, u8 *dst_id) 2083cee4d264SManish Chopra { 2084cee4d264SManish Chopra if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) { 2085cee4d264SManish Chopra u8 min, max; 2086cee4d264SManish Chopra 2087cee4d264SManish Chopra min = (u8)RESC_START(p_hwfn, QED_VPORT); 2088cee4d264SManish Chopra max = min + RESC_NUM(p_hwfn, QED_VPORT); 2089cee4d264SManish Chopra DP_NOTICE(p_hwfn, 2090cee4d264SManish Chopra "vport id [%d] is not valid, available indices [%d - %d]\n", 2091cee4d264SManish Chopra src_id, min, max); 2092cee4d264SManish Chopra 2093cee4d264SManish Chopra return -EINVAL; 2094cee4d264SManish Chopra } 2095cee4d264SManish Chopra 2096cee4d264SManish Chopra *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id; 2097cee4d264SManish Chopra 2098cee4d264SManish Chopra return 0; 2099cee4d264SManish Chopra } 2100cee4d264SManish Chopra 2101cee4d264SManish Chopra int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, 2102cee4d264SManish Chopra u8 src_id, u8 *dst_id) 2103cee4d264SManish Chopra { 2104cee4d264SManish Chopra if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) { 2105cee4d264SManish Chopra u8 min, max; 2106cee4d264SManish Chopra 2107cee4d264SManish Chopra min = (u8)RESC_START(p_hwfn, QED_RSS_ENG); 2108cee4d264SManish Chopra max = min + RESC_NUM(p_hwfn, QED_RSS_ENG); 2109cee4d264SManish Chopra DP_NOTICE(p_hwfn, 2110cee4d264SManish Chopra "rss_eng id [%d] is not valid, available indices [%d - %d]\n", 2111cee4d264SManish Chopra src_id, min, max); 2112cee4d264SManish Chopra 2113cee4d264SManish Chopra return -EINVAL; 2114cee4d264SManish Chopra } 2115cee4d264SManish Chopra 2116cee4d264SManish Chopra *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id; 2117cee4d264SManish Chopra 2118cee4d264SManish Chopra return 0; 2119cee4d264SManish Chopra } 2120bcd197c8SManish Chopra 2121bcd197c8SManish Chopra /* Calculate final WFQ values for all vports and configure them. 2122bcd197c8SManish Chopra * After this configuration each vport will have 2123bcd197c8SManish Chopra * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT) 2124bcd197c8SManish Chopra */ 2125bcd197c8SManish Chopra static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 2126bcd197c8SManish Chopra struct qed_ptt *p_ptt, 2127bcd197c8SManish Chopra u32 min_pf_rate) 2128bcd197c8SManish Chopra { 2129bcd197c8SManish Chopra struct init_qm_vport_params *vport_params; 2130bcd197c8SManish Chopra int i; 2131bcd197c8SManish Chopra 2132bcd197c8SManish Chopra vport_params = p_hwfn->qm_info.qm_vport_params; 2133bcd197c8SManish Chopra 2134bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 2135bcd197c8SManish Chopra u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 2136bcd197c8SManish Chopra 2137bcd197c8SManish Chopra vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) / 2138bcd197c8SManish Chopra min_pf_rate; 2139bcd197c8SManish Chopra qed_init_vport_wfq(p_hwfn, p_ptt, 2140bcd197c8SManish Chopra vport_params[i].first_tx_pq_id, 2141bcd197c8SManish Chopra vport_params[i].vport_wfq); 2142bcd197c8SManish Chopra } 2143bcd197c8SManish Chopra } 2144bcd197c8SManish Chopra 2145bcd197c8SManish Chopra static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn, 2146bcd197c8SManish Chopra u32 min_pf_rate) 2147bcd197c8SManish Chopra 2148bcd197c8SManish Chopra { 2149bcd197c8SManish Chopra int i; 2150bcd197c8SManish Chopra 2151bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) 2152bcd197c8SManish Chopra p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1; 2153bcd197c8SManish Chopra } 2154bcd197c8SManish Chopra 2155bcd197c8SManish Chopra static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 2156bcd197c8SManish Chopra struct qed_ptt *p_ptt, 2157bcd197c8SManish Chopra u32 min_pf_rate) 2158bcd197c8SManish Chopra { 2159bcd197c8SManish Chopra struct init_qm_vport_params *vport_params; 2160bcd197c8SManish Chopra int i; 2161bcd197c8SManish Chopra 2162bcd197c8SManish Chopra vport_params = p_hwfn->qm_info.qm_vport_params; 2163bcd197c8SManish Chopra 2164bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 2165bcd197c8SManish Chopra qed_init_wfq_default_param(p_hwfn, min_pf_rate); 2166bcd197c8SManish Chopra qed_init_vport_wfq(p_hwfn, p_ptt, 2167bcd197c8SManish Chopra vport_params[i].first_tx_pq_id, 2168bcd197c8SManish Chopra vport_params[i].vport_wfq); 2169bcd197c8SManish Chopra } 2170bcd197c8SManish Chopra } 2171bcd197c8SManish Chopra 2172bcd197c8SManish Chopra /* This function performs several validations for WFQ 2173bcd197c8SManish Chopra * configuration and required min rate for a given vport 2174bcd197c8SManish Chopra * 1. req_rate must be greater than one percent of min_pf_rate. 2175bcd197c8SManish Chopra * 2. req_rate should not cause other vports [not configured for WFQ explicitly] 2176bcd197c8SManish Chopra * rates to get less than one percent of min_pf_rate. 2177bcd197c8SManish Chopra * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate. 2178bcd197c8SManish Chopra */ 2179bcd197c8SManish Chopra static int qed_init_wfq_param(struct qed_hwfn *p_hwfn, 2180bcd197c8SManish Chopra u16 vport_id, u32 req_rate, 2181bcd197c8SManish Chopra u32 min_pf_rate) 2182bcd197c8SManish Chopra { 2183bcd197c8SManish Chopra u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0; 2184bcd197c8SManish Chopra int non_requested_count = 0, req_count = 0, i, num_vports; 2185bcd197c8SManish Chopra 2186bcd197c8SManish Chopra num_vports = p_hwfn->qm_info.num_vports; 2187bcd197c8SManish Chopra 2188bcd197c8SManish Chopra /* Accounting for the vports which are configured for WFQ explicitly */ 2189bcd197c8SManish Chopra for (i = 0; i < num_vports; i++) { 2190bcd197c8SManish Chopra u32 tmp_speed; 2191bcd197c8SManish Chopra 2192bcd197c8SManish Chopra if ((i != vport_id) && 2193bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[i].configured) { 2194bcd197c8SManish Chopra req_count++; 2195bcd197c8SManish Chopra tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 2196bcd197c8SManish Chopra total_req_min_rate += tmp_speed; 2197bcd197c8SManish Chopra } 2198bcd197c8SManish Chopra } 2199bcd197c8SManish Chopra 2200bcd197c8SManish Chopra /* Include current vport data as well */ 2201bcd197c8SManish Chopra req_count++; 2202bcd197c8SManish Chopra total_req_min_rate += req_rate; 2203bcd197c8SManish Chopra non_requested_count = num_vports - req_count; 2204bcd197c8SManish Chopra 2205bcd197c8SManish Chopra if (req_rate < min_pf_rate / QED_WFQ_UNIT) { 2206bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2207bcd197c8SManish Chopra "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 2208bcd197c8SManish Chopra vport_id, req_rate, min_pf_rate); 2209bcd197c8SManish Chopra return -EINVAL; 2210bcd197c8SManish Chopra } 2211bcd197c8SManish Chopra 2212bcd197c8SManish Chopra if (num_vports > QED_WFQ_UNIT) { 2213bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2214bcd197c8SManish Chopra "Number of vports is greater than %d\n", 2215bcd197c8SManish Chopra QED_WFQ_UNIT); 2216bcd197c8SManish Chopra return -EINVAL; 2217bcd197c8SManish Chopra } 2218bcd197c8SManish Chopra 2219bcd197c8SManish Chopra if (total_req_min_rate > min_pf_rate) { 2220bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2221bcd197c8SManish Chopra "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n", 2222bcd197c8SManish Chopra total_req_min_rate, min_pf_rate); 2223bcd197c8SManish Chopra return -EINVAL; 2224bcd197c8SManish Chopra } 2225bcd197c8SManish Chopra 2226bcd197c8SManish Chopra total_left_rate = min_pf_rate - total_req_min_rate; 2227bcd197c8SManish Chopra 2228bcd197c8SManish Chopra left_rate_per_vp = total_left_rate / non_requested_count; 2229bcd197c8SManish Chopra if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) { 2230bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2231bcd197c8SManish Chopra "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 2232bcd197c8SManish Chopra left_rate_per_vp, min_pf_rate); 2233bcd197c8SManish Chopra return -EINVAL; 2234bcd197c8SManish Chopra } 2235bcd197c8SManish Chopra 2236bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate; 2237bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[vport_id].configured = true; 2238bcd197c8SManish Chopra 2239bcd197c8SManish Chopra for (i = 0; i < num_vports; i++) { 2240bcd197c8SManish Chopra if (p_hwfn->qm_info.wfq_data[i].configured) 2241bcd197c8SManish Chopra continue; 2242bcd197c8SManish Chopra 2243bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp; 2244bcd197c8SManish Chopra } 2245bcd197c8SManish Chopra 2246bcd197c8SManish Chopra return 0; 2247bcd197c8SManish Chopra } 2248bcd197c8SManish Chopra 2249733def6aSYuval Mintz static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn, 2250733def6aSYuval Mintz struct qed_ptt *p_ptt, u16 vp_id, u32 rate) 2251733def6aSYuval Mintz { 2252733def6aSYuval Mintz struct qed_mcp_link_state *p_link; 2253733def6aSYuval Mintz int rc = 0; 2254733def6aSYuval Mintz 2255733def6aSYuval Mintz p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output; 2256733def6aSYuval Mintz 2257733def6aSYuval Mintz if (!p_link->min_pf_rate) { 2258733def6aSYuval Mintz p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate; 2259733def6aSYuval Mintz p_hwfn->qm_info.wfq_data[vp_id].configured = true; 2260733def6aSYuval Mintz return rc; 2261733def6aSYuval Mintz } 2262733def6aSYuval Mintz 2263733def6aSYuval Mintz rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate); 2264733def6aSYuval Mintz 2265733def6aSYuval Mintz if (rc == 0) 2266733def6aSYuval Mintz qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, 2267733def6aSYuval Mintz p_link->min_pf_rate); 2268733def6aSYuval Mintz else 2269733def6aSYuval Mintz DP_NOTICE(p_hwfn, 2270733def6aSYuval Mintz "Validation failed while configuring min rate\n"); 2271733def6aSYuval Mintz 2272733def6aSYuval Mintz return rc; 2273733def6aSYuval Mintz } 2274733def6aSYuval Mintz 2275bcd197c8SManish Chopra static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn, 2276bcd197c8SManish Chopra struct qed_ptt *p_ptt, 2277bcd197c8SManish Chopra u32 min_pf_rate) 2278bcd197c8SManish Chopra { 2279bcd197c8SManish Chopra bool use_wfq = false; 2280bcd197c8SManish Chopra int rc = 0; 2281bcd197c8SManish Chopra u16 i; 2282bcd197c8SManish Chopra 2283bcd197c8SManish Chopra /* Validate all pre configured vports for wfq */ 2284bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 2285bcd197c8SManish Chopra u32 rate; 2286bcd197c8SManish Chopra 2287bcd197c8SManish Chopra if (!p_hwfn->qm_info.wfq_data[i].configured) 2288bcd197c8SManish Chopra continue; 2289bcd197c8SManish Chopra 2290bcd197c8SManish Chopra rate = p_hwfn->qm_info.wfq_data[i].min_speed; 2291bcd197c8SManish Chopra use_wfq = true; 2292bcd197c8SManish Chopra 2293bcd197c8SManish Chopra rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate); 2294bcd197c8SManish Chopra if (rc) { 2295bcd197c8SManish Chopra DP_NOTICE(p_hwfn, 2296bcd197c8SManish Chopra "WFQ validation failed while configuring min rate\n"); 2297bcd197c8SManish Chopra break; 2298bcd197c8SManish Chopra } 2299bcd197c8SManish Chopra } 2300bcd197c8SManish Chopra 2301bcd197c8SManish Chopra if (!rc && use_wfq) 2302bcd197c8SManish Chopra qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 2303bcd197c8SManish Chopra else 2304bcd197c8SManish Chopra qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 2305bcd197c8SManish Chopra 2306bcd197c8SManish Chopra return rc; 2307bcd197c8SManish Chopra } 2308bcd197c8SManish Chopra 2309733def6aSYuval Mintz /* Main API for qed clients to configure vport min rate. 2310733def6aSYuval Mintz * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)] 2311733def6aSYuval Mintz * rate - Speed in Mbps needs to be assigned to a given vport. 2312733def6aSYuval Mintz */ 2313733def6aSYuval Mintz int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate) 2314733def6aSYuval Mintz { 2315733def6aSYuval Mintz int i, rc = -EINVAL; 2316733def6aSYuval Mintz 2317733def6aSYuval Mintz /* Currently not supported; Might change in future */ 2318733def6aSYuval Mintz if (cdev->num_hwfns > 1) { 2319733def6aSYuval Mintz DP_NOTICE(cdev, 2320733def6aSYuval Mintz "WFQ configuration is not supported for this device\n"); 2321733def6aSYuval Mintz return rc; 2322733def6aSYuval Mintz } 2323733def6aSYuval Mintz 2324733def6aSYuval Mintz for_each_hwfn(cdev, i) { 2325733def6aSYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2326733def6aSYuval Mintz struct qed_ptt *p_ptt; 2327733def6aSYuval Mintz 2328733def6aSYuval Mintz p_ptt = qed_ptt_acquire(p_hwfn); 2329733def6aSYuval Mintz if (!p_ptt) 2330733def6aSYuval Mintz return -EBUSY; 2331733def6aSYuval Mintz 2332733def6aSYuval Mintz rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate); 2333733def6aSYuval Mintz 2334733def6aSYuval Mintz if (!rc) { 2335733def6aSYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 2336733def6aSYuval Mintz return rc; 2337733def6aSYuval Mintz } 2338733def6aSYuval Mintz 2339733def6aSYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 2340733def6aSYuval Mintz } 2341733def6aSYuval Mintz 2342733def6aSYuval Mintz return rc; 2343733def6aSYuval Mintz } 2344733def6aSYuval Mintz 2345bcd197c8SManish Chopra /* API to configure WFQ from mcp link change */ 2346bcd197c8SManish Chopra void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate) 2347bcd197c8SManish Chopra { 2348bcd197c8SManish Chopra int i; 2349bcd197c8SManish Chopra 23503e7cfce2SYuval Mintz if (cdev->num_hwfns > 1) { 23513e7cfce2SYuval Mintz DP_VERBOSE(cdev, 23523e7cfce2SYuval Mintz NETIF_MSG_LINK, 23533e7cfce2SYuval Mintz "WFQ configuration is not supported for this device\n"); 23543e7cfce2SYuval Mintz return; 23553e7cfce2SYuval Mintz } 23563e7cfce2SYuval Mintz 2357bcd197c8SManish Chopra for_each_hwfn(cdev, i) { 2358bcd197c8SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2359bcd197c8SManish Chopra 2360bcd197c8SManish Chopra __qed_configure_vp_wfq_on_link_change(p_hwfn, 2361bcd197c8SManish Chopra p_hwfn->p_dpc_ptt, 2362bcd197c8SManish Chopra min_pf_rate); 2363bcd197c8SManish Chopra } 2364bcd197c8SManish Chopra } 23654b01e519SManish Chopra 23664b01e519SManish Chopra int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn, 23674b01e519SManish Chopra struct qed_ptt *p_ptt, 23684b01e519SManish Chopra struct qed_mcp_link_state *p_link, 23694b01e519SManish Chopra u8 max_bw) 23704b01e519SManish Chopra { 23714b01e519SManish Chopra int rc = 0; 23724b01e519SManish Chopra 23734b01e519SManish Chopra p_hwfn->mcp_info->func_info.bandwidth_max = max_bw; 23744b01e519SManish Chopra 23754b01e519SManish Chopra if (!p_link->line_speed && (max_bw != 100)) 23764b01e519SManish Chopra return rc; 23774b01e519SManish Chopra 23784b01e519SManish Chopra p_link->speed = (p_link->line_speed * max_bw) / 100; 23794b01e519SManish Chopra p_hwfn->qm_info.pf_rl = p_link->speed; 23804b01e519SManish Chopra 23814b01e519SManish Chopra /* Since the limiter also affects Tx-switched traffic, we don't want it 23824b01e519SManish Chopra * to limit such traffic in case there's no actual limit. 23834b01e519SManish Chopra * In that case, set limit to imaginary high boundary. 23844b01e519SManish Chopra */ 23854b01e519SManish Chopra if (max_bw == 100) 23864b01e519SManish Chopra p_hwfn->qm_info.pf_rl = 100000; 23874b01e519SManish Chopra 23884b01e519SManish Chopra rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, 23894b01e519SManish Chopra p_hwfn->qm_info.pf_rl); 23904b01e519SManish Chopra 23914b01e519SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 23924b01e519SManish Chopra "Configured MAX bandwidth to be %08x Mb/sec\n", 23934b01e519SManish Chopra p_link->speed); 23944b01e519SManish Chopra 23954b01e519SManish Chopra return rc; 23964b01e519SManish Chopra } 23974b01e519SManish Chopra 23984b01e519SManish Chopra /* Main API to configure PF max bandwidth where bw range is [1 - 100] */ 23994b01e519SManish Chopra int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw) 24004b01e519SManish Chopra { 24014b01e519SManish Chopra int i, rc = -EINVAL; 24024b01e519SManish Chopra 24034b01e519SManish Chopra if (max_bw < 1 || max_bw > 100) { 24044b01e519SManish Chopra DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n"); 24054b01e519SManish Chopra return rc; 24064b01e519SManish Chopra } 24074b01e519SManish Chopra 24084b01e519SManish Chopra for_each_hwfn(cdev, i) { 24094b01e519SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 24104b01e519SManish Chopra struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 24114b01e519SManish Chopra struct qed_mcp_link_state *p_link; 24124b01e519SManish Chopra struct qed_ptt *p_ptt; 24134b01e519SManish Chopra 24144b01e519SManish Chopra p_link = &p_lead->mcp_info->link_output; 24154b01e519SManish Chopra 24164b01e519SManish Chopra p_ptt = qed_ptt_acquire(p_hwfn); 24174b01e519SManish Chopra if (!p_ptt) 24184b01e519SManish Chopra return -EBUSY; 24194b01e519SManish Chopra 24204b01e519SManish Chopra rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, 24214b01e519SManish Chopra p_link, max_bw); 24224b01e519SManish Chopra 24234b01e519SManish Chopra qed_ptt_release(p_hwfn, p_ptt); 24244b01e519SManish Chopra 24254b01e519SManish Chopra if (rc) 24264b01e519SManish Chopra break; 24274b01e519SManish Chopra } 24284b01e519SManish Chopra 24294b01e519SManish Chopra return rc; 24304b01e519SManish Chopra } 2431a64b02d5SManish Chopra 2432a64b02d5SManish Chopra int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn, 2433a64b02d5SManish Chopra struct qed_ptt *p_ptt, 2434a64b02d5SManish Chopra struct qed_mcp_link_state *p_link, 2435a64b02d5SManish Chopra u8 min_bw) 2436a64b02d5SManish Chopra { 2437a64b02d5SManish Chopra int rc = 0; 2438a64b02d5SManish Chopra 2439a64b02d5SManish Chopra p_hwfn->mcp_info->func_info.bandwidth_min = min_bw; 2440a64b02d5SManish Chopra p_hwfn->qm_info.pf_wfq = min_bw; 2441a64b02d5SManish Chopra 2442a64b02d5SManish Chopra if (!p_link->line_speed) 2443a64b02d5SManish Chopra return rc; 2444a64b02d5SManish Chopra 2445a64b02d5SManish Chopra p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100; 2446a64b02d5SManish Chopra 2447a64b02d5SManish Chopra rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw); 2448a64b02d5SManish Chopra 2449a64b02d5SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2450a64b02d5SManish Chopra "Configured MIN bandwidth to be %d Mb/sec\n", 2451a64b02d5SManish Chopra p_link->min_pf_rate); 2452a64b02d5SManish Chopra 2453a64b02d5SManish Chopra return rc; 2454a64b02d5SManish Chopra } 2455a64b02d5SManish Chopra 2456a64b02d5SManish Chopra /* Main API to configure PF min bandwidth where bw range is [1-100] */ 2457a64b02d5SManish Chopra int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw) 2458a64b02d5SManish Chopra { 2459a64b02d5SManish Chopra int i, rc = -EINVAL; 2460a64b02d5SManish Chopra 2461a64b02d5SManish Chopra if (min_bw < 1 || min_bw > 100) { 2462a64b02d5SManish Chopra DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n"); 2463a64b02d5SManish Chopra return rc; 2464a64b02d5SManish Chopra } 2465a64b02d5SManish Chopra 2466a64b02d5SManish Chopra for_each_hwfn(cdev, i) { 2467a64b02d5SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2468a64b02d5SManish Chopra struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 2469a64b02d5SManish Chopra struct qed_mcp_link_state *p_link; 2470a64b02d5SManish Chopra struct qed_ptt *p_ptt; 2471a64b02d5SManish Chopra 2472a64b02d5SManish Chopra p_link = &p_lead->mcp_info->link_output; 2473a64b02d5SManish Chopra 2474a64b02d5SManish Chopra p_ptt = qed_ptt_acquire(p_hwfn); 2475a64b02d5SManish Chopra if (!p_ptt) 2476a64b02d5SManish Chopra return -EBUSY; 2477a64b02d5SManish Chopra 2478a64b02d5SManish Chopra rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, 2479a64b02d5SManish Chopra p_link, min_bw); 2480a64b02d5SManish Chopra if (rc) { 2481a64b02d5SManish Chopra qed_ptt_release(p_hwfn, p_ptt); 2482a64b02d5SManish Chopra return rc; 2483a64b02d5SManish Chopra } 2484a64b02d5SManish Chopra 2485a64b02d5SManish Chopra if (p_link->min_pf_rate) { 2486a64b02d5SManish Chopra u32 min_rate = p_link->min_pf_rate; 2487a64b02d5SManish Chopra 2488a64b02d5SManish Chopra rc = __qed_configure_vp_wfq_on_link_change(p_hwfn, 2489a64b02d5SManish Chopra p_ptt, 2490a64b02d5SManish Chopra min_rate); 2491a64b02d5SManish Chopra } 2492a64b02d5SManish Chopra 2493a64b02d5SManish Chopra qed_ptt_release(p_hwfn, p_ptt); 2494a64b02d5SManish Chopra } 2495a64b02d5SManish Chopra 2496a64b02d5SManish Chopra return rc; 2497a64b02d5SManish Chopra } 2498733def6aSYuval Mintz 2499733def6aSYuval Mintz void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2500733def6aSYuval Mintz { 2501733def6aSYuval Mintz struct qed_mcp_link_state *p_link; 2502733def6aSYuval Mintz 2503733def6aSYuval Mintz p_link = &p_hwfn->mcp_info->link_output; 2504733def6aSYuval Mintz 2505733def6aSYuval Mintz if (p_link->min_pf_rate) 2506733def6aSYuval Mintz qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, 2507733def6aSYuval Mintz p_link->min_pf_rate); 2508733def6aSYuval Mintz 2509733def6aSYuval Mintz memset(p_hwfn->qm_info.wfq_data, 0, 2510733def6aSYuval Mintz sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports); 2511733def6aSYuval Mintz } 2512