1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #include <linux/types.h> 34fe56b9e6SYuval Mintz #include <asm/byteorder.h> 35fe56b9e6SYuval Mintz #include <linux/io.h> 36fe56b9e6SYuval Mintz #include <linux/delay.h> 37fe56b9e6SYuval Mintz #include <linux/dma-mapping.h> 38fe56b9e6SYuval Mintz #include <linux/errno.h> 39fe56b9e6SYuval Mintz #include <linux/kernel.h> 40fe56b9e6SYuval Mintz #include <linux/mutex.h> 41fe56b9e6SYuval Mintz #include <linux/pci.h> 42fe56b9e6SYuval Mintz #include <linux/slab.h> 43fe56b9e6SYuval Mintz #include <linux/string.h> 44a91eb52aSYuval Mintz #include <linux/vmalloc.h> 45fe56b9e6SYuval Mintz #include <linux/etherdevice.h> 46fe56b9e6SYuval Mintz #include <linux/qed/qed_chain.h> 47fe56b9e6SYuval Mintz #include <linux/qed/qed_if.h> 48fe56b9e6SYuval Mintz #include "qed.h" 49fe56b9e6SYuval Mintz #include "qed_cxt.h" 5039651abdSSudarsana Reddy Kalluru #include "qed_dcbx.h" 51fe56b9e6SYuval Mintz #include "qed_dev_api.h" 521e128c81SArun Easi #include "qed_fcoe.h" 53fe56b9e6SYuval Mintz #include "qed_hsi.h" 54fe56b9e6SYuval Mintz #include "qed_hw.h" 55fe56b9e6SYuval Mintz #include "qed_init_ops.h" 56fe56b9e6SYuval Mintz #include "qed_int.h" 57fc831825SYuval Mintz #include "qed_iscsi.h" 580a7fb11cSYuval Mintz #include "qed_ll2.h" 59fe56b9e6SYuval Mintz #include "qed_mcp.h" 601d6cff4fSYuval Mintz #include "qed_ooo.h" 61fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 62fe56b9e6SYuval Mintz #include "qed_sp.h" 6332a47e72SYuval Mintz #include "qed_sriov.h" 640b55e27dSYuval Mintz #include "qed_vf.h" 6551ff1725SRam Amrani #include "qed_roce.h" 66fe56b9e6SYuval Mintz 670caf5b26SWei Yongjun static DEFINE_SPINLOCK(qm_lock); 6839651abdSSudarsana Reddy Kalluru 6951ff1725SRam Amrani #define QED_MIN_DPIS (4) 7051ff1725SRam Amrani #define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS) 7151ff1725SRam Amrani 72fe56b9e6SYuval Mintz /* API common to all protocols */ 73c2035eeaSRam Amrani enum BAR_ID { 74c2035eeaSRam Amrani BAR_ID_0, /* used for GRC */ 75c2035eeaSRam Amrani BAR_ID_1 /* Used for doorbells */ 76c2035eeaSRam Amrani }; 77c2035eeaSRam Amrani 781a635e48SYuval Mintz static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, enum BAR_ID bar_id) 79c2035eeaSRam Amrani { 80c2035eeaSRam Amrani u32 bar_reg = (bar_id == BAR_ID_0 ? 81c2035eeaSRam Amrani PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE); 821408cc1fSYuval Mintz u32 val; 83c2035eeaSRam Amrani 841408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 851408cc1fSYuval Mintz return 1 << 17; 861408cc1fSYuval Mintz 871408cc1fSYuval Mintz val = qed_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg); 88c2035eeaSRam Amrani if (val) 89c2035eeaSRam Amrani return 1 << (val + 15); 90c2035eeaSRam Amrani 91c2035eeaSRam Amrani /* Old MFW initialized above registered only conditionally */ 92c2035eeaSRam Amrani if (p_hwfn->cdev->num_hwfns > 1) { 93c2035eeaSRam Amrani DP_INFO(p_hwfn, 94c2035eeaSRam Amrani "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n"); 95c2035eeaSRam Amrani return BAR_ID_0 ? 256 * 1024 : 512 * 1024; 96c2035eeaSRam Amrani } else { 97c2035eeaSRam Amrani DP_INFO(p_hwfn, 98c2035eeaSRam Amrani "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n"); 99c2035eeaSRam Amrani return 512 * 1024; 100c2035eeaSRam Amrani } 101c2035eeaSRam Amrani } 102c2035eeaSRam Amrani 1031a635e48SYuval Mintz void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level) 104fe56b9e6SYuval Mintz { 105fe56b9e6SYuval Mintz u32 i; 106fe56b9e6SYuval Mintz 107fe56b9e6SYuval Mintz cdev->dp_level = dp_level; 108fe56b9e6SYuval Mintz cdev->dp_module = dp_module; 109fe56b9e6SYuval Mintz for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 110fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 111fe56b9e6SYuval Mintz 112fe56b9e6SYuval Mintz p_hwfn->dp_level = dp_level; 113fe56b9e6SYuval Mintz p_hwfn->dp_module = dp_module; 114fe56b9e6SYuval Mintz } 115fe56b9e6SYuval Mintz } 116fe56b9e6SYuval Mintz 117fe56b9e6SYuval Mintz void qed_init_struct(struct qed_dev *cdev) 118fe56b9e6SYuval Mintz { 119fe56b9e6SYuval Mintz u8 i; 120fe56b9e6SYuval Mintz 121fe56b9e6SYuval Mintz for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 122fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 123fe56b9e6SYuval Mintz 124fe56b9e6SYuval Mintz p_hwfn->cdev = cdev; 125fe56b9e6SYuval Mintz p_hwfn->my_id = i; 126fe56b9e6SYuval Mintz p_hwfn->b_active = false; 127fe56b9e6SYuval Mintz 128fe56b9e6SYuval Mintz mutex_init(&p_hwfn->dmae_info.mutex); 129fe56b9e6SYuval Mintz } 130fe56b9e6SYuval Mintz 131fe56b9e6SYuval Mintz /* hwfn 0 is always active */ 132fe56b9e6SYuval Mintz cdev->hwfns[0].b_active = true; 133fe56b9e6SYuval Mintz 134fe56b9e6SYuval Mintz /* set the default cache alignment to 128 */ 135fe56b9e6SYuval Mintz cdev->cache_shift = 7; 136fe56b9e6SYuval Mintz } 137fe56b9e6SYuval Mintz 138fe56b9e6SYuval Mintz static void qed_qm_info_free(struct qed_hwfn *p_hwfn) 139fe56b9e6SYuval Mintz { 140fe56b9e6SYuval Mintz struct qed_qm_info *qm_info = &p_hwfn->qm_info; 141fe56b9e6SYuval Mintz 142fe56b9e6SYuval Mintz kfree(qm_info->qm_pq_params); 143fe56b9e6SYuval Mintz qm_info->qm_pq_params = NULL; 144fe56b9e6SYuval Mintz kfree(qm_info->qm_vport_params); 145fe56b9e6SYuval Mintz qm_info->qm_vport_params = NULL; 146fe56b9e6SYuval Mintz kfree(qm_info->qm_port_params); 147fe56b9e6SYuval Mintz qm_info->qm_port_params = NULL; 148bcd197c8SManish Chopra kfree(qm_info->wfq_data); 149bcd197c8SManish Chopra qm_info->wfq_data = NULL; 150fe56b9e6SYuval Mintz } 151fe56b9e6SYuval Mintz 152fe56b9e6SYuval Mintz void qed_resc_free(struct qed_dev *cdev) 153fe56b9e6SYuval Mintz { 154fe56b9e6SYuval Mintz int i; 155fe56b9e6SYuval Mintz 1561408cc1fSYuval Mintz if (IS_VF(cdev)) 1571408cc1fSYuval Mintz return; 1581408cc1fSYuval Mintz 159fe56b9e6SYuval Mintz kfree(cdev->fw_data); 160fe56b9e6SYuval Mintz cdev->fw_data = NULL; 161fe56b9e6SYuval Mintz 162fe56b9e6SYuval Mintz kfree(cdev->reset_stats); 163fe56b9e6SYuval Mintz 164fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 165fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 166fe56b9e6SYuval Mintz 167fe56b9e6SYuval Mintz qed_cxt_mngr_free(p_hwfn); 168fe56b9e6SYuval Mintz qed_qm_info_free(p_hwfn); 169fe56b9e6SYuval Mintz qed_spq_free(p_hwfn); 170fe56b9e6SYuval Mintz qed_eq_free(p_hwfn, p_hwfn->p_eq); 171fe56b9e6SYuval Mintz qed_consq_free(p_hwfn, p_hwfn->p_consq); 172fe56b9e6SYuval Mintz qed_int_free(p_hwfn); 1730a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 1740a7fb11cSYuval Mintz qed_ll2_free(p_hwfn, p_hwfn->p_ll2_info); 1750a7fb11cSYuval Mintz #endif 1761e128c81SArun Easi if (p_hwfn->hw_info.personality == QED_PCI_FCOE) 1771e128c81SArun Easi qed_fcoe_free(p_hwfn, p_hwfn->p_fcoe_info); 1781e128c81SArun Easi 1791d6cff4fSYuval Mintz if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 180fc831825SYuval Mintz qed_iscsi_free(p_hwfn, p_hwfn->p_iscsi_info); 1811d6cff4fSYuval Mintz qed_ooo_free(p_hwfn, p_hwfn->p_ooo_info); 1821d6cff4fSYuval Mintz } 18332a47e72SYuval Mintz qed_iov_free(p_hwfn); 184fe56b9e6SYuval Mintz qed_dmae_info_free(p_hwfn); 18539651abdSSudarsana Reddy Kalluru qed_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info); 186fe56b9e6SYuval Mintz } 187fe56b9e6SYuval Mintz } 188fe56b9e6SYuval Mintz 18979529291SSudarsana Reddy Kalluru static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable) 190fe56b9e6SYuval Mintz { 1911408cc1fSYuval Mintz u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue = 0; 192fe56b9e6SYuval Mintz struct qed_qm_info *qm_info = &p_hwfn->qm_info; 193fe56b9e6SYuval Mintz struct init_qm_port_params *p_qm_port; 194dbb799c3SYuval Mintz bool init_rdma_offload_pq = false; 195dbb799c3SYuval Mintz bool init_pure_ack_pq = false; 196dbb799c3SYuval Mintz bool init_ooo_pq = false; 197fe56b9e6SYuval Mintz u16 num_pqs, multi_cos_tcs = 1; 198cc3d5eb0SYuval Mintz u8 pf_wfq = qm_info->pf_wfq; 199cc3d5eb0SYuval Mintz u32 pf_rl = qm_info->pf_rl; 200dbb799c3SYuval Mintz u16 num_pf_rls = 0; 2011408cc1fSYuval Mintz u16 num_vfs = 0; 202fe56b9e6SYuval Mintz 2031408cc1fSYuval Mintz #ifdef CONFIG_QED_SRIOV 2041408cc1fSYuval Mintz if (p_hwfn->cdev->p_iov_info) 2051408cc1fSYuval Mintz num_vfs = p_hwfn->cdev->p_iov_info->total_vfs; 2061408cc1fSYuval Mintz #endif 207fe56b9e6SYuval Mintz memset(qm_info, 0, sizeof(*qm_info)); 208fe56b9e6SYuval Mintz 2091408cc1fSYuval Mintz num_pqs = multi_cos_tcs + num_vfs + 1; /* The '1' is for pure-LB */ 210fe56b9e6SYuval Mintz num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT); 211fe56b9e6SYuval Mintz 212dbb799c3SYuval Mintz if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) { 213dbb799c3SYuval Mintz num_pqs++; /* for RoCE queue */ 214dbb799c3SYuval Mintz init_rdma_offload_pq = true; 215dbb799c3SYuval Mintz /* we subtract num_vfs because each require a rate limiter, 216dbb799c3SYuval Mintz * and one default rate limiter 217dbb799c3SYuval Mintz */ 218dbb799c3SYuval Mintz if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn) 219dbb799c3SYuval Mintz num_pf_rls = RESC_NUM(p_hwfn, QED_RL) - num_vfs - 1; 220dbb799c3SYuval Mintz 221dbb799c3SYuval Mintz num_pqs += num_pf_rls; 222dbb799c3SYuval Mintz qm_info->num_pf_rls = (u8) num_pf_rls; 223dbb799c3SYuval Mintz } 224dbb799c3SYuval Mintz 225dbb799c3SYuval Mintz if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 226dbb799c3SYuval Mintz num_pqs += 2; /* for iSCSI pure-ACK / OOO queue */ 227dbb799c3SYuval Mintz init_pure_ack_pq = true; 228dbb799c3SYuval Mintz init_ooo_pq = true; 229dbb799c3SYuval Mintz } 230dbb799c3SYuval Mintz 231fe56b9e6SYuval Mintz /* Sanity checking that setup requires legal number of resources */ 232fe56b9e6SYuval Mintz if (num_pqs > RESC_NUM(p_hwfn, QED_PQ)) { 233fe56b9e6SYuval Mintz DP_ERR(p_hwfn, 234fe56b9e6SYuval Mintz "Need too many Physical queues - 0x%04x when only %04x are available\n", 235fe56b9e6SYuval Mintz num_pqs, RESC_NUM(p_hwfn, QED_PQ)); 236fe56b9e6SYuval Mintz return -EINVAL; 237fe56b9e6SYuval Mintz } 238fe56b9e6SYuval Mintz 239fe56b9e6SYuval Mintz /* PQs will be arranged as follows: First per-TC PQ then pure-LB quete. 240fe56b9e6SYuval Mintz */ 24179529291SSudarsana Reddy Kalluru qm_info->qm_pq_params = kcalloc(num_pqs, 24279529291SSudarsana Reddy Kalluru sizeof(struct init_qm_pq_params), 24379529291SSudarsana Reddy Kalluru b_sleepable ? GFP_KERNEL : GFP_ATOMIC); 244fe56b9e6SYuval Mintz if (!qm_info->qm_pq_params) 245fe56b9e6SYuval Mintz goto alloc_err; 246fe56b9e6SYuval Mintz 24779529291SSudarsana Reddy Kalluru qm_info->qm_vport_params = kcalloc(num_vports, 24879529291SSudarsana Reddy Kalluru sizeof(struct init_qm_vport_params), 24979529291SSudarsana Reddy Kalluru b_sleepable ? GFP_KERNEL 25079529291SSudarsana Reddy Kalluru : GFP_ATOMIC); 251fe56b9e6SYuval Mintz if (!qm_info->qm_vport_params) 252fe56b9e6SYuval Mintz goto alloc_err; 253fe56b9e6SYuval Mintz 25479529291SSudarsana Reddy Kalluru qm_info->qm_port_params = kcalloc(MAX_NUM_PORTS, 25579529291SSudarsana Reddy Kalluru sizeof(struct init_qm_port_params), 25679529291SSudarsana Reddy Kalluru b_sleepable ? GFP_KERNEL 25779529291SSudarsana Reddy Kalluru : GFP_ATOMIC); 258fe56b9e6SYuval Mintz if (!qm_info->qm_port_params) 259fe56b9e6SYuval Mintz goto alloc_err; 260fe56b9e6SYuval Mintz 26179529291SSudarsana Reddy Kalluru qm_info->wfq_data = kcalloc(num_vports, sizeof(struct qed_wfq_data), 26279529291SSudarsana Reddy Kalluru b_sleepable ? GFP_KERNEL : GFP_ATOMIC); 263bcd197c8SManish Chopra if (!qm_info->wfq_data) 264bcd197c8SManish Chopra goto alloc_err; 265bcd197c8SManish Chopra 266fe56b9e6SYuval Mintz vport_id = (u8)RESC_START(p_hwfn, QED_VPORT); 267fe56b9e6SYuval Mintz 268dbb799c3SYuval Mintz /* First init rate limited queues */ 269dbb799c3SYuval Mintz for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) { 270dbb799c3SYuval Mintz qm_info->qm_pq_params[curr_queue].vport_id = vport_id++; 271dbb799c3SYuval Mintz qm_info->qm_pq_params[curr_queue].tc_id = 272dbb799c3SYuval Mintz p_hwfn->hw_info.non_offload_tc; 273dbb799c3SYuval Mintz qm_info->qm_pq_params[curr_queue].wrr_group = 1; 274dbb799c3SYuval Mintz qm_info->qm_pq_params[curr_queue].rl_valid = 1; 275dbb799c3SYuval Mintz } 276dbb799c3SYuval Mintz 277fe56b9e6SYuval Mintz /* First init per-TC PQs */ 27839651abdSSudarsana Reddy Kalluru for (i = 0; i < multi_cos_tcs; i++) { 2791408cc1fSYuval Mintz struct init_qm_pq_params *params = 28039651abdSSudarsana Reddy Kalluru &qm_info->qm_pq_params[curr_queue++]; 281fe56b9e6SYuval Mintz 282dbb799c3SYuval Mintz if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE || 283dbb799c3SYuval Mintz p_hwfn->hw_info.personality == QED_PCI_ETH) { 284fe56b9e6SYuval Mintz params->vport_id = vport_id; 285fe56b9e6SYuval Mintz params->tc_id = p_hwfn->hw_info.non_offload_tc; 286fe56b9e6SYuval Mintz params->wrr_group = 1; 28739651abdSSudarsana Reddy Kalluru } else { 28839651abdSSudarsana Reddy Kalluru params->vport_id = vport_id; 28939651abdSSudarsana Reddy Kalluru params->tc_id = p_hwfn->hw_info.offload_tc; 29039651abdSSudarsana Reddy Kalluru params->wrr_group = 1; 29139651abdSSudarsana Reddy Kalluru } 292fe56b9e6SYuval Mintz } 293fe56b9e6SYuval Mintz 294fe56b9e6SYuval Mintz /* Then init pure-LB PQ */ 2951408cc1fSYuval Mintz qm_info->pure_lb_pq = curr_queue; 2961408cc1fSYuval Mintz qm_info->qm_pq_params[curr_queue].vport_id = 2971408cc1fSYuval Mintz (u8) RESC_START(p_hwfn, QED_VPORT); 2981408cc1fSYuval Mintz qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC; 2991408cc1fSYuval Mintz qm_info->qm_pq_params[curr_queue].wrr_group = 1; 3001408cc1fSYuval Mintz curr_queue++; 301fe56b9e6SYuval Mintz 302fe56b9e6SYuval Mintz qm_info->offload_pq = 0; 303dbb799c3SYuval Mintz if (init_rdma_offload_pq) { 304dbb799c3SYuval Mintz qm_info->offload_pq = curr_queue; 305dbb799c3SYuval Mintz qm_info->qm_pq_params[curr_queue].vport_id = vport_id; 306dbb799c3SYuval Mintz qm_info->qm_pq_params[curr_queue].tc_id = 307dbb799c3SYuval Mintz p_hwfn->hw_info.offload_tc; 308dbb799c3SYuval Mintz qm_info->qm_pq_params[curr_queue].wrr_group = 1; 309dbb799c3SYuval Mintz curr_queue++; 310dbb799c3SYuval Mintz } 311dbb799c3SYuval Mintz 312dbb799c3SYuval Mintz if (init_pure_ack_pq) { 313dbb799c3SYuval Mintz qm_info->pure_ack_pq = curr_queue; 314dbb799c3SYuval Mintz qm_info->qm_pq_params[curr_queue].vport_id = vport_id; 315dbb799c3SYuval Mintz qm_info->qm_pq_params[curr_queue].tc_id = 316dbb799c3SYuval Mintz p_hwfn->hw_info.offload_tc; 317dbb799c3SYuval Mintz qm_info->qm_pq_params[curr_queue].wrr_group = 1; 318dbb799c3SYuval Mintz curr_queue++; 319dbb799c3SYuval Mintz } 320dbb799c3SYuval Mintz 321dbb799c3SYuval Mintz if (init_ooo_pq) { 322dbb799c3SYuval Mintz qm_info->ooo_pq = curr_queue; 323dbb799c3SYuval Mintz qm_info->qm_pq_params[curr_queue].vport_id = vport_id; 324dbb799c3SYuval Mintz qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC; 325dbb799c3SYuval Mintz qm_info->qm_pq_params[curr_queue].wrr_group = 1; 326dbb799c3SYuval Mintz curr_queue++; 327dbb799c3SYuval Mintz } 328dbb799c3SYuval Mintz 3291408cc1fSYuval Mintz /* Then init per-VF PQs */ 3301408cc1fSYuval Mintz vf_offset = curr_queue; 3311408cc1fSYuval Mintz for (i = 0; i < num_vfs; i++) { 3321408cc1fSYuval Mintz /* First vport is used by the PF */ 3331408cc1fSYuval Mintz qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1; 3341408cc1fSYuval Mintz qm_info->qm_pq_params[curr_queue].tc_id = 3351408cc1fSYuval Mintz p_hwfn->hw_info.non_offload_tc; 3361408cc1fSYuval Mintz qm_info->qm_pq_params[curr_queue].wrr_group = 1; 337351a4dedSYuval Mintz qm_info->qm_pq_params[curr_queue].rl_valid = 1; 3381408cc1fSYuval Mintz curr_queue++; 3391408cc1fSYuval Mintz } 3401408cc1fSYuval Mintz 3411408cc1fSYuval Mintz qm_info->vf_queues_offset = vf_offset; 342fe56b9e6SYuval Mintz qm_info->num_pqs = num_pqs; 343fe56b9e6SYuval Mintz qm_info->num_vports = num_vports; 344fe56b9e6SYuval Mintz 345fe56b9e6SYuval Mintz /* Initialize qm port parameters */ 346fe56b9e6SYuval Mintz num_ports = p_hwfn->cdev->num_ports_in_engines; 347fe56b9e6SYuval Mintz for (i = 0; i < num_ports; i++) { 348fe56b9e6SYuval Mintz p_qm_port = &qm_info->qm_port_params[i]; 349fe56b9e6SYuval Mintz p_qm_port->active = 1; 350351a4dedSYuval Mintz if (num_ports == 4) 351351a4dedSYuval Mintz p_qm_port->active_phys_tcs = 0x7; 352351a4dedSYuval Mintz else 353351a4dedSYuval Mintz p_qm_port->active_phys_tcs = 0x9f; 354fe56b9e6SYuval Mintz p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports; 355fe56b9e6SYuval Mintz p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports; 356fe56b9e6SYuval Mintz } 357fe56b9e6SYuval Mintz 358fe56b9e6SYuval Mintz qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS; 359fe56b9e6SYuval Mintz 360fe56b9e6SYuval Mintz qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ); 361fe56b9e6SYuval Mintz 3621408cc1fSYuval Mintz qm_info->num_vf_pqs = num_vfs; 363fe56b9e6SYuval Mintz qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT); 364fe56b9e6SYuval Mintz 365a64b02d5SManish Chopra for (i = 0; i < qm_info->num_vports; i++) 366a64b02d5SManish Chopra qm_info->qm_vport_params[i].vport_wfq = 1; 367a64b02d5SManish Chopra 368fe56b9e6SYuval Mintz qm_info->vport_rl_en = 1; 369a64b02d5SManish Chopra qm_info->vport_wfq_en = 1; 370cc3d5eb0SYuval Mintz qm_info->pf_rl = pf_rl; 371cc3d5eb0SYuval Mintz qm_info->pf_wfq = pf_wfq; 372fe56b9e6SYuval Mintz 373fe56b9e6SYuval Mintz return 0; 374fe56b9e6SYuval Mintz 375fe56b9e6SYuval Mintz alloc_err: 376bcd197c8SManish Chopra qed_qm_info_free(p_hwfn); 377fe56b9e6SYuval Mintz return -ENOMEM; 378fe56b9e6SYuval Mintz } 379fe56b9e6SYuval Mintz 38039651abdSSudarsana Reddy Kalluru /* This function reconfigures the QM pf on the fly. 38139651abdSSudarsana Reddy Kalluru * For this purpose we: 38239651abdSSudarsana Reddy Kalluru * 1. reconfigure the QM database 38339651abdSSudarsana Reddy Kalluru * 2. set new values to runtime arrat 38439651abdSSudarsana Reddy Kalluru * 3. send an sdm_qm_cmd through the rbc interface to stop the QM 38539651abdSSudarsana Reddy Kalluru * 4. activate init tool in QM_PF stage 38639651abdSSudarsana Reddy Kalluru * 5. send an sdm_qm_cmd through rbc interface to release the QM 38739651abdSSudarsana Reddy Kalluru */ 38839651abdSSudarsana Reddy Kalluru int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 38939651abdSSudarsana Reddy Kalluru { 39039651abdSSudarsana Reddy Kalluru struct qed_qm_info *qm_info = &p_hwfn->qm_info; 39139651abdSSudarsana Reddy Kalluru bool b_rc; 39239651abdSSudarsana Reddy Kalluru int rc; 39339651abdSSudarsana Reddy Kalluru 39439651abdSSudarsana Reddy Kalluru /* qm_info is allocated in qed_init_qm_info() which is already called 39539651abdSSudarsana Reddy Kalluru * from qed_resc_alloc() or previous call of qed_qm_reconf(). 39639651abdSSudarsana Reddy Kalluru * The allocated size may change each init, so we free it before next 39739651abdSSudarsana Reddy Kalluru * allocation. 39839651abdSSudarsana Reddy Kalluru */ 39939651abdSSudarsana Reddy Kalluru qed_qm_info_free(p_hwfn); 40039651abdSSudarsana Reddy Kalluru 40139651abdSSudarsana Reddy Kalluru /* initialize qed's qm data structure */ 40279529291SSudarsana Reddy Kalluru rc = qed_init_qm_info(p_hwfn, false); 40339651abdSSudarsana Reddy Kalluru if (rc) 40439651abdSSudarsana Reddy Kalluru return rc; 40539651abdSSudarsana Reddy Kalluru 40639651abdSSudarsana Reddy Kalluru /* stop PF's qm queues */ 40739651abdSSudarsana Reddy Kalluru spin_lock_bh(&qm_lock); 40839651abdSSudarsana Reddy Kalluru b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true, 40939651abdSSudarsana Reddy Kalluru qm_info->start_pq, qm_info->num_pqs); 41039651abdSSudarsana Reddy Kalluru spin_unlock_bh(&qm_lock); 41139651abdSSudarsana Reddy Kalluru if (!b_rc) 41239651abdSSudarsana Reddy Kalluru return -EINVAL; 41339651abdSSudarsana Reddy Kalluru 41439651abdSSudarsana Reddy Kalluru /* clear the QM_PF runtime phase leftovers from previous init */ 41539651abdSSudarsana Reddy Kalluru qed_init_clear_rt_data(p_hwfn); 41639651abdSSudarsana Reddy Kalluru 41739651abdSSudarsana Reddy Kalluru /* prepare QM portion of runtime array */ 41839651abdSSudarsana Reddy Kalluru qed_qm_init_pf(p_hwfn); 41939651abdSSudarsana Reddy Kalluru 42039651abdSSudarsana Reddy Kalluru /* activate init tool on runtime array */ 42139651abdSSudarsana Reddy Kalluru rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id, 42239651abdSSudarsana Reddy Kalluru p_hwfn->hw_info.hw_mode); 42339651abdSSudarsana Reddy Kalluru if (rc) 42439651abdSSudarsana Reddy Kalluru return rc; 42539651abdSSudarsana Reddy Kalluru 42639651abdSSudarsana Reddy Kalluru /* start PF's qm queues */ 42739651abdSSudarsana Reddy Kalluru spin_lock_bh(&qm_lock); 42839651abdSSudarsana Reddy Kalluru b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true, 42939651abdSSudarsana Reddy Kalluru qm_info->start_pq, qm_info->num_pqs); 43039651abdSSudarsana Reddy Kalluru spin_unlock_bh(&qm_lock); 43139651abdSSudarsana Reddy Kalluru if (!b_rc) 43239651abdSSudarsana Reddy Kalluru return -EINVAL; 43339651abdSSudarsana Reddy Kalluru 43439651abdSSudarsana Reddy Kalluru return 0; 43539651abdSSudarsana Reddy Kalluru } 43639651abdSSudarsana Reddy Kalluru 437fe56b9e6SYuval Mintz int qed_resc_alloc(struct qed_dev *cdev) 438fe56b9e6SYuval Mintz { 439fc831825SYuval Mintz struct qed_iscsi_info *p_iscsi_info; 4401e128c81SArun Easi struct qed_fcoe_info *p_fcoe_info; 4411d6cff4fSYuval Mintz struct qed_ooo_info *p_ooo_info; 4420a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 4430a7fb11cSYuval Mintz struct qed_ll2_info *p_ll2_info; 4440a7fb11cSYuval Mintz #endif 445fe56b9e6SYuval Mintz struct qed_consq *p_consq; 446fe56b9e6SYuval Mintz struct qed_eq *p_eq; 447fe56b9e6SYuval Mintz int i, rc = 0; 448fe56b9e6SYuval Mintz 4491408cc1fSYuval Mintz if (IS_VF(cdev)) 4501408cc1fSYuval Mintz return rc; 4511408cc1fSYuval Mintz 452fe56b9e6SYuval Mintz cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL); 453fe56b9e6SYuval Mintz if (!cdev->fw_data) 454fe56b9e6SYuval Mintz return -ENOMEM; 455fe56b9e6SYuval Mintz 456fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 457fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 458dbb799c3SYuval Mintz u32 n_eqes, num_cons; 459fe56b9e6SYuval Mintz 460fe56b9e6SYuval Mintz /* First allocate the context manager structure */ 461fe56b9e6SYuval Mintz rc = qed_cxt_mngr_alloc(p_hwfn); 462fe56b9e6SYuval Mintz if (rc) 463fe56b9e6SYuval Mintz goto alloc_err; 464fe56b9e6SYuval Mintz 465fe56b9e6SYuval Mintz /* Set the HW cid/tid numbers (in the contest manager) 466fe56b9e6SYuval Mintz * Must be done prior to any further computations. 467fe56b9e6SYuval Mintz */ 468fe56b9e6SYuval Mintz rc = qed_cxt_set_pf_params(p_hwfn); 469fe56b9e6SYuval Mintz if (rc) 470fe56b9e6SYuval Mintz goto alloc_err; 471fe56b9e6SYuval Mintz 472fe56b9e6SYuval Mintz /* Prepare and process QM requirements */ 47379529291SSudarsana Reddy Kalluru rc = qed_init_qm_info(p_hwfn, true); 474fe56b9e6SYuval Mintz if (rc) 475fe56b9e6SYuval Mintz goto alloc_err; 476fe56b9e6SYuval Mintz 477fe56b9e6SYuval Mintz /* Compute the ILT client partition */ 478fe56b9e6SYuval Mintz rc = qed_cxt_cfg_ilt_compute(p_hwfn); 479fe56b9e6SYuval Mintz if (rc) 480fe56b9e6SYuval Mintz goto alloc_err; 481fe56b9e6SYuval Mintz 482fe56b9e6SYuval Mintz /* CID map / ILT shadow table / T2 483fe56b9e6SYuval Mintz * The talbes sizes are determined by the computations above 484fe56b9e6SYuval Mintz */ 485fe56b9e6SYuval Mintz rc = qed_cxt_tables_alloc(p_hwfn); 486fe56b9e6SYuval Mintz if (rc) 487fe56b9e6SYuval Mintz goto alloc_err; 488fe56b9e6SYuval Mintz 489fe56b9e6SYuval Mintz /* SPQ, must follow ILT because initializes SPQ context */ 490fe56b9e6SYuval Mintz rc = qed_spq_alloc(p_hwfn); 491fe56b9e6SYuval Mintz if (rc) 492fe56b9e6SYuval Mintz goto alloc_err; 493fe56b9e6SYuval Mintz 494fe56b9e6SYuval Mintz /* SP status block allocation */ 495fe56b9e6SYuval Mintz p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn, 496fe56b9e6SYuval Mintz RESERVED_PTT_DPC); 497fe56b9e6SYuval Mintz 498fe56b9e6SYuval Mintz rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt); 499fe56b9e6SYuval Mintz if (rc) 500fe56b9e6SYuval Mintz goto alloc_err; 501fe56b9e6SYuval Mintz 50232a47e72SYuval Mintz rc = qed_iov_alloc(p_hwfn); 50332a47e72SYuval Mintz if (rc) 50432a47e72SYuval Mintz goto alloc_err; 50532a47e72SYuval Mintz 506fe56b9e6SYuval Mintz /* EQ */ 507dbb799c3SYuval Mintz n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain); 508dbb799c3SYuval Mintz if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) { 509dbb799c3SYuval Mintz num_cons = qed_cxt_get_proto_cid_count(p_hwfn, 510dbb799c3SYuval Mintz PROTOCOLID_ROCE, 5118c93beafSYuval Mintz NULL) * 2; 512dbb799c3SYuval Mintz n_eqes += num_cons + 2 * MAX_NUM_VFS_BB; 513dbb799c3SYuval Mintz } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 514dbb799c3SYuval Mintz num_cons = 515dbb799c3SYuval Mintz qed_cxt_get_proto_cid_count(p_hwfn, 5168c93beafSYuval Mintz PROTOCOLID_ISCSI, 5178c93beafSYuval Mintz NULL); 518dbb799c3SYuval Mintz n_eqes += 2 * num_cons; 519dbb799c3SYuval Mintz } 520dbb799c3SYuval Mintz 521dbb799c3SYuval Mintz if (n_eqes > 0xFFFF) { 522dbb799c3SYuval Mintz DP_ERR(p_hwfn, 523dbb799c3SYuval Mintz "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n", 524dbb799c3SYuval Mintz n_eqes, 0xFFFF); 5251b4985b5SWei Yongjun rc = -EINVAL; 526fe56b9e6SYuval Mintz goto alloc_err; 5279b15acbfSDan Carpenter } 528dbb799c3SYuval Mintz 529dbb799c3SYuval Mintz p_eq = qed_eq_alloc(p_hwfn, (u16) n_eqes); 530dbb799c3SYuval Mintz if (!p_eq) 531dbb799c3SYuval Mintz goto alloc_no_mem; 532fe56b9e6SYuval Mintz p_hwfn->p_eq = p_eq; 533fe56b9e6SYuval Mintz 534fe56b9e6SYuval Mintz p_consq = qed_consq_alloc(p_hwfn); 535dbb799c3SYuval Mintz if (!p_consq) 536dbb799c3SYuval Mintz goto alloc_no_mem; 537fe56b9e6SYuval Mintz p_hwfn->p_consq = p_consq; 538fe56b9e6SYuval Mintz 5390a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 5400a7fb11cSYuval Mintz if (p_hwfn->using_ll2) { 5410a7fb11cSYuval Mintz p_ll2_info = qed_ll2_alloc(p_hwfn); 5420a7fb11cSYuval Mintz if (!p_ll2_info) 5430a7fb11cSYuval Mintz goto alloc_no_mem; 5440a7fb11cSYuval Mintz p_hwfn->p_ll2_info = p_ll2_info; 5450a7fb11cSYuval Mintz } 5460a7fb11cSYuval Mintz #endif 5471e128c81SArun Easi 5481e128c81SArun Easi if (p_hwfn->hw_info.personality == QED_PCI_FCOE) { 5491e128c81SArun Easi p_fcoe_info = qed_fcoe_alloc(p_hwfn); 5501e128c81SArun Easi if (!p_fcoe_info) 5511e128c81SArun Easi goto alloc_no_mem; 5521e128c81SArun Easi p_hwfn->p_fcoe_info = p_fcoe_info; 5531e128c81SArun Easi } 5541e128c81SArun Easi 555fc831825SYuval Mintz if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 556fc831825SYuval Mintz p_iscsi_info = qed_iscsi_alloc(p_hwfn); 557fc831825SYuval Mintz if (!p_iscsi_info) 558fc831825SYuval Mintz goto alloc_no_mem; 559fc831825SYuval Mintz p_hwfn->p_iscsi_info = p_iscsi_info; 5601d6cff4fSYuval Mintz p_ooo_info = qed_ooo_alloc(p_hwfn); 5611d6cff4fSYuval Mintz if (!p_ooo_info) 5621d6cff4fSYuval Mintz goto alloc_no_mem; 5631d6cff4fSYuval Mintz p_hwfn->p_ooo_info = p_ooo_info; 564fc831825SYuval Mintz } 5650a7fb11cSYuval Mintz 566fe56b9e6SYuval Mintz /* DMA info initialization */ 567fe56b9e6SYuval Mintz rc = qed_dmae_info_alloc(p_hwfn); 5682591c280SJoe Perches if (rc) 569fe56b9e6SYuval Mintz goto alloc_err; 57039651abdSSudarsana Reddy Kalluru 57139651abdSSudarsana Reddy Kalluru /* DCBX initialization */ 57239651abdSSudarsana Reddy Kalluru rc = qed_dcbx_info_alloc(p_hwfn); 5732591c280SJoe Perches if (rc) 57439651abdSSudarsana Reddy Kalluru goto alloc_err; 57539651abdSSudarsana Reddy Kalluru } 576fe56b9e6SYuval Mintz 577fe56b9e6SYuval Mintz cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL); 5782591c280SJoe Perches if (!cdev->reset_stats) 57983aeb933SYuval Mintz goto alloc_no_mem; 580fe56b9e6SYuval Mintz 581fe56b9e6SYuval Mintz return 0; 582fe56b9e6SYuval Mintz 583dbb799c3SYuval Mintz alloc_no_mem: 584dbb799c3SYuval Mintz rc = -ENOMEM; 585fe56b9e6SYuval Mintz alloc_err: 586fe56b9e6SYuval Mintz qed_resc_free(cdev); 587fe56b9e6SYuval Mintz return rc; 588fe56b9e6SYuval Mintz } 589fe56b9e6SYuval Mintz 590fe56b9e6SYuval Mintz void qed_resc_setup(struct qed_dev *cdev) 591fe56b9e6SYuval Mintz { 592fe56b9e6SYuval Mintz int i; 593fe56b9e6SYuval Mintz 5941408cc1fSYuval Mintz if (IS_VF(cdev)) 5951408cc1fSYuval Mintz return; 5961408cc1fSYuval Mintz 597fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 598fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 599fe56b9e6SYuval Mintz 600fe56b9e6SYuval Mintz qed_cxt_mngr_setup(p_hwfn); 601fe56b9e6SYuval Mintz qed_spq_setup(p_hwfn); 602fe56b9e6SYuval Mintz qed_eq_setup(p_hwfn, p_hwfn->p_eq); 603fe56b9e6SYuval Mintz qed_consq_setup(p_hwfn, p_hwfn->p_consq); 604fe56b9e6SYuval Mintz 605fe56b9e6SYuval Mintz /* Read shadow of current MFW mailbox */ 606fe56b9e6SYuval Mintz qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt); 607fe56b9e6SYuval Mintz memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 608fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_cur, 609fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_length); 610fe56b9e6SYuval Mintz 611fe56b9e6SYuval Mintz qed_int_setup(p_hwfn, p_hwfn->p_main_ptt); 61232a47e72SYuval Mintz 61332a47e72SYuval Mintz qed_iov_setup(p_hwfn, p_hwfn->p_main_ptt); 6140a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 6150a7fb11cSYuval Mintz if (p_hwfn->using_ll2) 6160a7fb11cSYuval Mintz qed_ll2_setup(p_hwfn, p_hwfn->p_ll2_info); 6170a7fb11cSYuval Mintz #endif 6181e128c81SArun Easi if (p_hwfn->hw_info.personality == QED_PCI_FCOE) 6191e128c81SArun Easi qed_fcoe_setup(p_hwfn, p_hwfn->p_fcoe_info); 6201e128c81SArun Easi 6211d6cff4fSYuval Mintz if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 622fc831825SYuval Mintz qed_iscsi_setup(p_hwfn, p_hwfn->p_iscsi_info); 6231d6cff4fSYuval Mintz qed_ooo_setup(p_hwfn, p_hwfn->p_ooo_info); 6241d6cff4fSYuval Mintz } 625fe56b9e6SYuval Mintz } 626fe56b9e6SYuval Mintz } 627fe56b9e6SYuval Mintz 628fe56b9e6SYuval Mintz #define FINAL_CLEANUP_POLL_CNT (100) 629fe56b9e6SYuval Mintz #define FINAL_CLEANUP_POLL_TIME (10) 630fe56b9e6SYuval Mintz int qed_final_cleanup(struct qed_hwfn *p_hwfn, 6310b55e27dSYuval Mintz struct qed_ptt *p_ptt, u16 id, bool is_vf) 632fe56b9e6SYuval Mintz { 633fe56b9e6SYuval Mintz u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT; 634fe56b9e6SYuval Mintz int rc = -EBUSY; 635fe56b9e6SYuval Mintz 636fc48b7a6SYuval Mintz addr = GTT_BAR0_MAP_REG_USDM_RAM + 637fc48b7a6SYuval Mintz USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id); 638fe56b9e6SYuval Mintz 6390b55e27dSYuval Mintz if (is_vf) 6400b55e27dSYuval Mintz id += 0x10; 6410b55e27dSYuval Mintz 642fc48b7a6SYuval Mintz command |= X_FINAL_CLEANUP_AGG_INT << 643fc48b7a6SYuval Mintz SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT; 644fc48b7a6SYuval Mintz command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT; 645fc48b7a6SYuval Mintz command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT; 646fc48b7a6SYuval Mintz command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT; 647fe56b9e6SYuval Mintz 648fe56b9e6SYuval Mintz /* Make sure notification is not set before initiating final cleanup */ 649fe56b9e6SYuval Mintz if (REG_RD(p_hwfn, addr)) { 6501a635e48SYuval Mintz DP_NOTICE(p_hwfn, 651fe56b9e6SYuval Mintz "Unexpected; Found final cleanup notification before initiating final cleanup\n"); 652fe56b9e6SYuval Mintz REG_WR(p_hwfn, addr, 0); 653fe56b9e6SYuval Mintz } 654fe56b9e6SYuval Mintz 655fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_IOV, 656fe56b9e6SYuval Mintz "Sending final cleanup for PFVF[%d] [Command %08x\n]", 657fe56b9e6SYuval Mintz id, command); 658fe56b9e6SYuval Mintz 659fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command); 660fe56b9e6SYuval Mintz 661fe56b9e6SYuval Mintz /* Poll until completion */ 662fe56b9e6SYuval Mintz while (!REG_RD(p_hwfn, addr) && count--) 663fe56b9e6SYuval Mintz msleep(FINAL_CLEANUP_POLL_TIME); 664fe56b9e6SYuval Mintz 665fe56b9e6SYuval Mintz if (REG_RD(p_hwfn, addr)) 666fe56b9e6SYuval Mintz rc = 0; 667fe56b9e6SYuval Mintz else 668fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 669fe56b9e6SYuval Mintz "Failed to receive FW final cleanup notification\n"); 670fe56b9e6SYuval Mintz 671fe56b9e6SYuval Mintz /* Cleanup afterwards */ 672fe56b9e6SYuval Mintz REG_WR(p_hwfn, addr, 0); 673fe56b9e6SYuval Mintz 674fe56b9e6SYuval Mintz return rc; 675fe56b9e6SYuval Mintz } 676fe56b9e6SYuval Mintz 677fe56b9e6SYuval Mintz static void qed_calc_hw_mode(struct qed_hwfn *p_hwfn) 678fe56b9e6SYuval Mintz { 679fe56b9e6SYuval Mintz int hw_mode = 0; 680fe56b9e6SYuval Mintz 68112e09c69SYuval Mintz hw_mode = (1 << MODE_BB_B0); 682fe56b9e6SYuval Mintz 683fe56b9e6SYuval Mintz switch (p_hwfn->cdev->num_ports_in_engines) { 684fe56b9e6SYuval Mintz case 1: 685fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_PORTS_PER_ENG_1; 686fe56b9e6SYuval Mintz break; 687fe56b9e6SYuval Mintz case 2: 688fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_PORTS_PER_ENG_2; 689fe56b9e6SYuval Mintz break; 690fe56b9e6SYuval Mintz case 4: 691fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_PORTS_PER_ENG_4; 692fe56b9e6SYuval Mintz break; 693fe56b9e6SYuval Mintz default: 694fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n", 695fe56b9e6SYuval Mintz p_hwfn->cdev->num_ports_in_engines); 696fe56b9e6SYuval Mintz return; 697fe56b9e6SYuval Mintz } 698fe56b9e6SYuval Mintz 699fe56b9e6SYuval Mintz switch (p_hwfn->cdev->mf_mode) { 700fc48b7a6SYuval Mintz case QED_MF_DEFAULT: 701fc48b7a6SYuval Mintz case QED_MF_NPAR: 702fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_MF_SI; 703fe56b9e6SYuval Mintz break; 704fc48b7a6SYuval Mintz case QED_MF_OVLAN: 705fc48b7a6SYuval Mintz hw_mode |= 1 << MODE_MF_SD; 706fc48b7a6SYuval Mintz break; 707fe56b9e6SYuval Mintz default: 708fc48b7a6SYuval Mintz DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n"); 709fc48b7a6SYuval Mintz hw_mode |= 1 << MODE_MF_SI; 710fe56b9e6SYuval Mintz } 711fe56b9e6SYuval Mintz 712fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_ASIC; 713fe56b9e6SYuval Mintz 7141af9dcf7SYuval Mintz if (p_hwfn->cdev->num_hwfns > 1) 7151af9dcf7SYuval Mintz hw_mode |= 1 << MODE_100G; 7161af9dcf7SYuval Mintz 717fe56b9e6SYuval Mintz p_hwfn->hw_info.hw_mode = hw_mode; 7181af9dcf7SYuval Mintz 7191af9dcf7SYuval Mintz DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP), 7201af9dcf7SYuval Mintz "Configuring function for hw_mode: 0x%08x\n", 7211af9dcf7SYuval Mintz p_hwfn->hw_info.hw_mode); 722fe56b9e6SYuval Mintz } 723fe56b9e6SYuval Mintz 724fe56b9e6SYuval Mintz /* Init run time data for all PFs on an engine. */ 725fe56b9e6SYuval Mintz static void qed_init_cau_rt_data(struct qed_dev *cdev) 726fe56b9e6SYuval Mintz { 727fe56b9e6SYuval Mintz u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET; 728fe56b9e6SYuval Mintz int i, sb_id; 729fe56b9e6SYuval Mintz 730fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 731fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 732fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 733fe56b9e6SYuval Mintz struct qed_igu_block *p_block; 734fe56b9e6SYuval Mintz struct cau_sb_entry sb_entry; 735fe56b9e6SYuval Mintz 736fe56b9e6SYuval Mintz p_igu_info = p_hwfn->hw_info.p_igu_info; 737fe56b9e6SYuval Mintz 738fe56b9e6SYuval Mintz for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev); 739fe56b9e6SYuval Mintz sb_id++) { 740fe56b9e6SYuval Mintz p_block = &p_igu_info->igu_map.igu_blocks[sb_id]; 741fe56b9e6SYuval Mintz if (!p_block->is_pf) 742fe56b9e6SYuval Mintz continue; 743fe56b9e6SYuval Mintz 744fe56b9e6SYuval Mintz qed_init_cau_sb_entry(p_hwfn, &sb_entry, 7451a635e48SYuval Mintz p_block->function_id, 0, 0); 7461a635e48SYuval Mintz STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry); 747fe56b9e6SYuval Mintz } 748fe56b9e6SYuval Mintz } 749fe56b9e6SYuval Mintz } 750fe56b9e6SYuval Mintz 751fe56b9e6SYuval Mintz static int qed_hw_init_common(struct qed_hwfn *p_hwfn, 7521a635e48SYuval Mintz struct qed_ptt *p_ptt, int hw_mode) 753fe56b9e6SYuval Mintz { 754fe56b9e6SYuval Mintz struct qed_qm_info *qm_info = &p_hwfn->qm_info; 755fe56b9e6SYuval Mintz struct qed_qm_common_rt_init_params params; 756fe56b9e6SYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 757dbb799c3SYuval Mintz u16 num_pfs, pf_id; 7581408cc1fSYuval Mintz u32 concrete_fid; 759fe56b9e6SYuval Mintz int rc = 0; 7601408cc1fSYuval Mintz u8 vf_id; 761fe56b9e6SYuval Mintz 762fe56b9e6SYuval Mintz qed_init_cau_rt_data(cdev); 763fe56b9e6SYuval Mintz 764fe56b9e6SYuval Mintz /* Program GTT windows */ 765fe56b9e6SYuval Mintz qed_gtt_init(p_hwfn); 766fe56b9e6SYuval Mintz 767fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 768fe56b9e6SYuval Mintz if (p_hwfn->mcp_info->func_info.bandwidth_max) 769fe56b9e6SYuval Mintz qm_info->pf_rl_en = 1; 770fe56b9e6SYuval Mintz if (p_hwfn->mcp_info->func_info.bandwidth_min) 771fe56b9e6SYuval Mintz qm_info->pf_wfq_en = 1; 772fe56b9e6SYuval Mintz } 773fe56b9e6SYuval Mintz 774fe56b9e6SYuval Mintz memset(¶ms, 0, sizeof(params)); 775fe56b9e6SYuval Mintz params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engines; 776fe56b9e6SYuval Mintz params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port; 777fe56b9e6SYuval Mintz params.pf_rl_en = qm_info->pf_rl_en; 778fe56b9e6SYuval Mintz params.pf_wfq_en = qm_info->pf_wfq_en; 779fe56b9e6SYuval Mintz params.vport_rl_en = qm_info->vport_rl_en; 780fe56b9e6SYuval Mintz params.vport_wfq_en = qm_info->vport_wfq_en; 781fe56b9e6SYuval Mintz params.port_params = qm_info->qm_port_params; 782fe56b9e6SYuval Mintz 783fe56b9e6SYuval Mintz qed_qm_common_rt_init(p_hwfn, ¶ms); 784fe56b9e6SYuval Mintz 785fe56b9e6SYuval Mintz qed_cxt_hw_init_common(p_hwfn); 786fe56b9e6SYuval Mintz 787fe56b9e6SYuval Mintz /* Close gate from NIG to BRB/Storm; By default they are open, but 788fe56b9e6SYuval Mintz * we close them to prevent NIG from passing data to reset blocks. 789fe56b9e6SYuval Mintz * Should have been done in the ENGINE phase, but init-tool lacks 790fe56b9e6SYuval Mintz * proper port-pretend capabilities. 791fe56b9e6SYuval Mintz */ 792fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0); 793fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0); 794fe56b9e6SYuval Mintz qed_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1); 795fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0); 796fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0); 797fe56b9e6SYuval Mintz qed_port_unpretend(p_hwfn, p_ptt); 798fe56b9e6SYuval Mintz 799fe56b9e6SYuval Mintz rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode); 8001a635e48SYuval Mintz if (rc) 801fe56b9e6SYuval Mintz return rc; 802fe56b9e6SYuval Mintz 803fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0); 804fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1); 805fe56b9e6SYuval Mintz 806dbb799c3SYuval Mintz if (QED_IS_BB(p_hwfn->cdev)) { 807dbb799c3SYuval Mintz num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev); 808dbb799c3SYuval Mintz for (pf_id = 0; pf_id < num_pfs; pf_id++) { 809dbb799c3SYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, pf_id); 810dbb799c3SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 811dbb799c3SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 812dbb799c3SYuval Mintz } 813dbb799c3SYuval Mintz /* pretend to original PF */ 814dbb799c3SYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 815dbb799c3SYuval Mintz } 816fe56b9e6SYuval Mintz 8171408cc1fSYuval Mintz for (vf_id = 0; vf_id < MAX_NUM_VFS_BB; vf_id++) { 8181408cc1fSYuval Mintz concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id); 8191408cc1fSYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid); 8201408cc1fSYuval Mintz qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1); 82105fafbfbSYuval Mintz qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0); 82205fafbfbSYuval Mintz qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1); 82305fafbfbSYuval Mintz qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0); 8241408cc1fSYuval Mintz } 8251408cc1fSYuval Mintz /* pretend to original PF */ 8261408cc1fSYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 8271408cc1fSYuval Mintz 828fe56b9e6SYuval Mintz return rc; 829fe56b9e6SYuval Mintz } 830fe56b9e6SYuval Mintz 83151ff1725SRam Amrani static int 83251ff1725SRam Amrani qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn, 83351ff1725SRam Amrani struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus) 83451ff1725SRam Amrani { 83551ff1725SRam Amrani u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size; 83651ff1725SRam Amrani u32 dpi_bit_shift, dpi_count; 83751ff1725SRam Amrani u32 min_dpis; 83851ff1725SRam Amrani 83951ff1725SRam Amrani /* Calculate DPI size */ 84051ff1725SRam Amrani dpi_page_size_1 = QED_WID_SIZE * n_cpus; 84151ff1725SRam Amrani dpi_page_size_2 = max_t(u32, QED_WID_SIZE, PAGE_SIZE); 84251ff1725SRam Amrani dpi_page_size = max_t(u32, dpi_page_size_1, dpi_page_size_2); 84351ff1725SRam Amrani dpi_page_size = roundup_pow_of_two(dpi_page_size); 84451ff1725SRam Amrani dpi_bit_shift = ilog2(dpi_page_size / 4096); 84551ff1725SRam Amrani 84651ff1725SRam Amrani dpi_count = pwm_region_size / dpi_page_size; 84751ff1725SRam Amrani 84851ff1725SRam Amrani min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis; 84951ff1725SRam Amrani min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis); 85051ff1725SRam Amrani 85151ff1725SRam Amrani p_hwfn->dpi_size = dpi_page_size; 85251ff1725SRam Amrani p_hwfn->dpi_count = dpi_count; 85351ff1725SRam Amrani 85451ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift); 85551ff1725SRam Amrani 85651ff1725SRam Amrani if (dpi_count < min_dpis) 85751ff1725SRam Amrani return -EINVAL; 85851ff1725SRam Amrani 85951ff1725SRam Amrani return 0; 86051ff1725SRam Amrani } 86151ff1725SRam Amrani 86251ff1725SRam Amrani enum QED_ROCE_EDPM_MODE { 86351ff1725SRam Amrani QED_ROCE_EDPM_MODE_ENABLE = 0, 86451ff1725SRam Amrani QED_ROCE_EDPM_MODE_FORCE_ON = 1, 86551ff1725SRam Amrani QED_ROCE_EDPM_MODE_DISABLE = 2, 86651ff1725SRam Amrani }; 86751ff1725SRam Amrani 86851ff1725SRam Amrani static int 86951ff1725SRam Amrani qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 87051ff1725SRam Amrani { 87151ff1725SRam Amrani u32 pwm_regsize, norm_regsize; 87251ff1725SRam Amrani u32 non_pwm_conn, min_addr_reg1; 87351ff1725SRam Amrani u32 db_bar_size, n_cpus; 87451ff1725SRam Amrani u32 roce_edpm_mode; 87551ff1725SRam Amrani u32 pf_dems_shift; 87651ff1725SRam Amrani int rc = 0; 87751ff1725SRam Amrani u8 cond; 87851ff1725SRam Amrani 87951ff1725SRam Amrani db_bar_size = qed_hw_bar_size(p_hwfn, BAR_ID_1); 88051ff1725SRam Amrani if (p_hwfn->cdev->num_hwfns > 1) 88151ff1725SRam Amrani db_bar_size /= 2; 88251ff1725SRam Amrani 88351ff1725SRam Amrani /* Calculate doorbell regions */ 88451ff1725SRam Amrani non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) + 88551ff1725SRam Amrani qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE, 88651ff1725SRam Amrani NULL) + 88751ff1725SRam Amrani qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, 88851ff1725SRam Amrani NULL); 88951ff1725SRam Amrani norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, 4096); 89051ff1725SRam Amrani min_addr_reg1 = norm_regsize / 4096; 89151ff1725SRam Amrani pwm_regsize = db_bar_size - norm_regsize; 89251ff1725SRam Amrani 89351ff1725SRam Amrani /* Check that the normal and PWM sizes are valid */ 89451ff1725SRam Amrani if (db_bar_size < norm_regsize) { 89551ff1725SRam Amrani DP_ERR(p_hwfn->cdev, 89651ff1725SRam Amrani "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n", 89751ff1725SRam Amrani db_bar_size, norm_regsize); 89851ff1725SRam Amrani return -EINVAL; 89951ff1725SRam Amrani } 90051ff1725SRam Amrani 90151ff1725SRam Amrani if (pwm_regsize < QED_MIN_PWM_REGION) { 90251ff1725SRam Amrani DP_ERR(p_hwfn->cdev, 90351ff1725SRam Amrani "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n", 90451ff1725SRam Amrani pwm_regsize, 90551ff1725SRam Amrani QED_MIN_PWM_REGION, db_bar_size, norm_regsize); 90651ff1725SRam Amrani return -EINVAL; 90751ff1725SRam Amrani } 90851ff1725SRam Amrani 90951ff1725SRam Amrani /* Calculate number of DPIs */ 91051ff1725SRam Amrani roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode; 91151ff1725SRam Amrani if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) || 91251ff1725SRam Amrani ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) { 91351ff1725SRam Amrani /* Either EDPM is mandatory, or we are attempting to allocate a 91451ff1725SRam Amrani * WID per CPU. 91551ff1725SRam Amrani */ 916c2dedf87SRam Amrani n_cpus = num_present_cpus(); 91751ff1725SRam Amrani rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 91851ff1725SRam Amrani } 91951ff1725SRam Amrani 92051ff1725SRam Amrani cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) || 92151ff1725SRam Amrani (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE); 92251ff1725SRam Amrani if (cond || p_hwfn->dcbx_no_edpm) { 92351ff1725SRam Amrani /* Either EDPM is disabled from user configuration, or it is 92451ff1725SRam Amrani * disabled via DCBx, or it is not mandatory and we failed to 92551ff1725SRam Amrani * allocated a WID per CPU. 92651ff1725SRam Amrani */ 92751ff1725SRam Amrani n_cpus = 1; 92851ff1725SRam Amrani rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 92951ff1725SRam Amrani 93051ff1725SRam Amrani if (cond) 93151ff1725SRam Amrani qed_rdma_dpm_bar(p_hwfn, p_ptt); 93251ff1725SRam Amrani } 93351ff1725SRam Amrani 93451ff1725SRam Amrani DP_INFO(p_hwfn, 93551ff1725SRam Amrani "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n", 93651ff1725SRam Amrani norm_regsize, 93751ff1725SRam Amrani pwm_regsize, 93851ff1725SRam Amrani p_hwfn->dpi_size, 93951ff1725SRam Amrani p_hwfn->dpi_count, 94051ff1725SRam Amrani ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ? 94151ff1725SRam Amrani "disabled" : "enabled"); 94251ff1725SRam Amrani 94351ff1725SRam Amrani if (rc) { 94451ff1725SRam Amrani DP_ERR(p_hwfn, 94551ff1725SRam Amrani "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n", 94651ff1725SRam Amrani p_hwfn->dpi_count, 94751ff1725SRam Amrani p_hwfn->pf_params.rdma_pf_params.min_dpis); 94851ff1725SRam Amrani return -EINVAL; 94951ff1725SRam Amrani } 95051ff1725SRam Amrani 95151ff1725SRam Amrani p_hwfn->dpi_start_offset = norm_regsize; 95251ff1725SRam Amrani 95351ff1725SRam Amrani /* DEMS size is configured log2 of DWORDs, hence the division by 4 */ 95451ff1725SRam Amrani pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4); 95551ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift); 95651ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1); 95751ff1725SRam Amrani 95851ff1725SRam Amrani return 0; 95951ff1725SRam Amrani } 96051ff1725SRam Amrani 961fe56b9e6SYuval Mintz static int qed_hw_init_port(struct qed_hwfn *p_hwfn, 9621a635e48SYuval Mintz struct qed_ptt *p_ptt, int hw_mode) 963fe56b9e6SYuval Mintz { 96405fafbfbSYuval Mintz return qed_init_run(p_hwfn, p_ptt, PHASE_PORT, 96505fafbfbSYuval Mintz p_hwfn->port_id, hw_mode); 966fe56b9e6SYuval Mintz } 967fe56b9e6SYuval Mintz 968fe56b9e6SYuval Mintz static int qed_hw_init_pf(struct qed_hwfn *p_hwfn, 969fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 970464f6645SManish Chopra struct qed_tunn_start_params *p_tunn, 971fe56b9e6SYuval Mintz int hw_mode, 972fe56b9e6SYuval Mintz bool b_hw_start, 973fe56b9e6SYuval Mintz enum qed_int_mode int_mode, 974fe56b9e6SYuval Mintz bool allow_npar_tx_switch) 975fe56b9e6SYuval Mintz { 976fe56b9e6SYuval Mintz u8 rel_pf_id = p_hwfn->rel_pf_id; 977fe56b9e6SYuval Mintz int rc = 0; 978fe56b9e6SYuval Mintz 979fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 980fe56b9e6SYuval Mintz struct qed_mcp_function_info *p_info; 981fe56b9e6SYuval Mintz 982fe56b9e6SYuval Mintz p_info = &p_hwfn->mcp_info->func_info; 983fe56b9e6SYuval Mintz if (p_info->bandwidth_min) 984fe56b9e6SYuval Mintz p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min; 985fe56b9e6SYuval Mintz 986fe56b9e6SYuval Mintz /* Update rate limit once we'll actually have a link */ 9874b01e519SManish Chopra p_hwfn->qm_info.pf_rl = 100000; 988fe56b9e6SYuval Mintz } 989fe56b9e6SYuval Mintz 990fe56b9e6SYuval Mintz qed_cxt_hw_init_pf(p_hwfn); 991fe56b9e6SYuval Mintz 992fe56b9e6SYuval Mintz qed_int_igu_init_rt(p_hwfn); 993fe56b9e6SYuval Mintz 994fe56b9e6SYuval Mintz /* Set VLAN in NIG if needed */ 9951a635e48SYuval Mintz if (hw_mode & BIT(MODE_MF_SD)) { 996fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n"); 997fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1); 998fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET, 999fe56b9e6SYuval Mintz p_hwfn->hw_info.ovlan); 1000fe56b9e6SYuval Mintz } 1001fe56b9e6SYuval Mintz 1002fe56b9e6SYuval Mintz /* Enable classification by MAC if needed */ 10031a635e48SYuval Mintz if (hw_mode & BIT(MODE_MF_SI)) { 1004fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 1005fe56b9e6SYuval Mintz "Configuring TAGMAC_CLS_TYPE\n"); 1006fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, 1007fe56b9e6SYuval Mintz NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1); 1008fe56b9e6SYuval Mintz } 1009fe56b9e6SYuval Mintz 1010fe56b9e6SYuval Mintz /* Protocl Configuration */ 1011dbb799c3SYuval Mintz STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 1012dbb799c3SYuval Mintz (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0); 10131e128c81SArun Easi STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 10141e128c81SArun Easi (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0); 1015fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0); 1016fe56b9e6SYuval Mintz 1017fe56b9e6SYuval Mintz /* Cleanup chip from previous driver if such remains exist */ 10180b55e27dSYuval Mintz rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false); 10191a635e48SYuval Mintz if (rc) 1020fe56b9e6SYuval Mintz return rc; 1021fe56b9e6SYuval Mintz 1022fe56b9e6SYuval Mintz /* PF Init sequence */ 1023fe56b9e6SYuval Mintz rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode); 1024fe56b9e6SYuval Mintz if (rc) 1025fe56b9e6SYuval Mintz return rc; 1026fe56b9e6SYuval Mintz 1027fe56b9e6SYuval Mintz /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */ 1028fe56b9e6SYuval Mintz rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode); 1029fe56b9e6SYuval Mintz if (rc) 1030fe56b9e6SYuval Mintz return rc; 1031fe56b9e6SYuval Mintz 1032fe56b9e6SYuval Mintz /* Pure runtime initializations - directly to the HW */ 1033fe56b9e6SYuval Mintz qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true); 1034fe56b9e6SYuval Mintz 103551ff1725SRam Amrani rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt); 103651ff1725SRam Amrani if (rc) 103751ff1725SRam Amrani return rc; 103851ff1725SRam Amrani 1039fe56b9e6SYuval Mintz if (b_hw_start) { 1040fe56b9e6SYuval Mintz /* enable interrupts */ 1041fe56b9e6SYuval Mintz qed_int_igu_enable(p_hwfn, p_ptt, int_mode); 1042fe56b9e6SYuval Mintz 1043fe56b9e6SYuval Mintz /* send function start command */ 1044831bfb0eSYuval Mintz rc = qed_sp_pf_start(p_hwfn, p_tunn, p_hwfn->cdev->mf_mode, 1045831bfb0eSYuval Mintz allow_npar_tx_switch); 10461e128c81SArun Easi if (rc) { 1047fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Function start ramrod failed\n"); 10481e128c81SArun Easi return rc; 10491e128c81SArun Easi } 10501e128c81SArun Easi if (p_hwfn->hw_info.personality == QED_PCI_FCOE) { 10511e128c81SArun Easi qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2)); 10521e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 10531e128c81SArun Easi PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST, 10541e128c81SArun Easi 0x100); 10551e128c81SArun Easi } 1056fe56b9e6SYuval Mintz } 1057fe56b9e6SYuval Mintz return rc; 1058fe56b9e6SYuval Mintz } 1059fe56b9e6SYuval Mintz 1060fe56b9e6SYuval Mintz static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn, 1061fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1062fe56b9e6SYuval Mintz u8 enable) 1063fe56b9e6SYuval Mintz { 1064fe56b9e6SYuval Mintz u32 delay_idx = 0, val, set_val = enable ? 1 : 0; 1065fe56b9e6SYuval Mintz 1066fe56b9e6SYuval Mintz /* Change PF in PXP */ 1067fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 1068fe56b9e6SYuval Mintz PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val); 1069fe56b9e6SYuval Mintz 1070fe56b9e6SYuval Mintz /* wait until value is set - try for 1 second every 50us */ 1071fe56b9e6SYuval Mintz for (delay_idx = 0; delay_idx < 20000; delay_idx++) { 1072fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, 1073fe56b9e6SYuval Mintz PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1074fe56b9e6SYuval Mintz if (val == set_val) 1075fe56b9e6SYuval Mintz break; 1076fe56b9e6SYuval Mintz 1077fe56b9e6SYuval Mintz usleep_range(50, 60); 1078fe56b9e6SYuval Mintz } 1079fe56b9e6SYuval Mintz 1080fe56b9e6SYuval Mintz if (val != set_val) { 1081fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 1082fe56b9e6SYuval Mintz "PFID_ENABLE_MASTER wasn't changed after a second\n"); 1083fe56b9e6SYuval Mintz return -EAGAIN; 1084fe56b9e6SYuval Mintz } 1085fe56b9e6SYuval Mintz 1086fe56b9e6SYuval Mintz return 0; 1087fe56b9e6SYuval Mintz } 1088fe56b9e6SYuval Mintz 1089fe56b9e6SYuval Mintz static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn, 1090fe56b9e6SYuval Mintz struct qed_ptt *p_main_ptt) 1091fe56b9e6SYuval Mintz { 1092fe56b9e6SYuval Mintz /* Read shadow of current MFW mailbox */ 1093fe56b9e6SYuval Mintz qed_mcp_read_mb(p_hwfn, p_main_ptt); 1094fe56b9e6SYuval Mintz memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 10951a635e48SYuval Mintz p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length); 1096fe56b9e6SYuval Mintz } 1097fe56b9e6SYuval Mintz 1098fe56b9e6SYuval Mintz int qed_hw_init(struct qed_dev *cdev, 1099464f6645SManish Chopra struct qed_tunn_start_params *p_tunn, 1100fe56b9e6SYuval Mintz bool b_hw_start, 1101fe56b9e6SYuval Mintz enum qed_int_mode int_mode, 1102fe56b9e6SYuval Mintz bool allow_npar_tx_switch, 1103fe56b9e6SYuval Mintz const u8 *bin_fw_data) 1104fe56b9e6SYuval Mintz { 11050fefbfbaSSudarsana Kalluru u32 load_code, param, drv_mb_param; 11060fefbfbaSSudarsana Kalluru bool b_default_mtu = true; 11070fefbfbaSSudarsana Kalluru struct qed_hwfn *p_hwfn; 11080fefbfbaSSudarsana Kalluru int rc = 0, mfw_rc, i; 1109fe56b9e6SYuval Mintz 1110bb13ace7SSudarsana Reddy Kalluru if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) { 1111bb13ace7SSudarsana Reddy Kalluru DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n"); 1112bb13ace7SSudarsana Reddy Kalluru return -EINVAL; 1113bb13ace7SSudarsana Reddy Kalluru } 1114bb13ace7SSudarsana Reddy Kalluru 11151408cc1fSYuval Mintz if (IS_PF(cdev)) { 1116fe56b9e6SYuval Mintz rc = qed_init_fw_data(cdev, bin_fw_data); 11171a635e48SYuval Mintz if (rc) 1118fe56b9e6SYuval Mintz return rc; 11191408cc1fSYuval Mintz } 1120fe56b9e6SYuval Mintz 1121fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 1122fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1123fe56b9e6SYuval Mintz 11240fefbfbaSSudarsana Kalluru /* If management didn't provide a default, set one of our own */ 11250fefbfbaSSudarsana Kalluru if (!p_hwfn->hw_info.mtu) { 11260fefbfbaSSudarsana Kalluru p_hwfn->hw_info.mtu = 1500; 11270fefbfbaSSudarsana Kalluru b_default_mtu = false; 11280fefbfbaSSudarsana Kalluru } 11290fefbfbaSSudarsana Kalluru 11301408cc1fSYuval Mintz if (IS_VF(cdev)) { 11311408cc1fSYuval Mintz p_hwfn->b_int_enabled = 1; 11321408cc1fSYuval Mintz continue; 11331408cc1fSYuval Mintz } 11341408cc1fSYuval Mintz 1135fe56b9e6SYuval Mintz /* Enable DMAE in PXP */ 1136fe56b9e6SYuval Mintz rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true); 1137fe56b9e6SYuval Mintz 1138fe56b9e6SYuval Mintz qed_calc_hw_mode(p_hwfn); 1139fe56b9e6SYuval Mintz 11401a635e48SYuval Mintz rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code); 1141fe56b9e6SYuval Mintz if (rc) { 1142fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed sending LOAD_REQ command\n"); 1143fe56b9e6SYuval Mintz return rc; 1144fe56b9e6SYuval Mintz } 1145fe56b9e6SYuval Mintz 1146fe56b9e6SYuval Mintz qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt); 1147fe56b9e6SYuval Mintz 1148fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 1149fe56b9e6SYuval Mintz "Load request was sent. Resp:0x%x, Load code: 0x%x\n", 1150fe56b9e6SYuval Mintz rc, load_code); 1151fe56b9e6SYuval Mintz 1152fe56b9e6SYuval Mintz p_hwfn->first_on_engine = (load_code == 1153fe56b9e6SYuval Mintz FW_MSG_CODE_DRV_LOAD_ENGINE); 1154fe56b9e6SYuval Mintz 1155fe56b9e6SYuval Mintz switch (load_code) { 1156fe56b9e6SYuval Mintz case FW_MSG_CODE_DRV_LOAD_ENGINE: 1157fe56b9e6SYuval Mintz rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt, 1158fe56b9e6SYuval Mintz p_hwfn->hw_info.hw_mode); 1159fe56b9e6SYuval Mintz if (rc) 1160fe56b9e6SYuval Mintz break; 1161fe56b9e6SYuval Mintz /* Fall into */ 1162fe56b9e6SYuval Mintz case FW_MSG_CODE_DRV_LOAD_PORT: 1163fe56b9e6SYuval Mintz rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt, 1164fe56b9e6SYuval Mintz p_hwfn->hw_info.hw_mode); 1165fe56b9e6SYuval Mintz if (rc) 1166fe56b9e6SYuval Mintz break; 1167fe56b9e6SYuval Mintz 1168fe56b9e6SYuval Mintz /* Fall into */ 1169fe56b9e6SYuval Mintz case FW_MSG_CODE_DRV_LOAD_FUNCTION: 1170fe56b9e6SYuval Mintz rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt, 1171464f6645SManish Chopra p_tunn, p_hwfn->hw_info.hw_mode, 1172fe56b9e6SYuval Mintz b_hw_start, int_mode, 1173fe56b9e6SYuval Mintz allow_npar_tx_switch); 1174fe56b9e6SYuval Mintz break; 1175fe56b9e6SYuval Mintz default: 1176fe56b9e6SYuval Mintz rc = -EINVAL; 1177fe56b9e6SYuval Mintz break; 1178fe56b9e6SYuval Mintz } 1179fe56b9e6SYuval Mintz 1180fe56b9e6SYuval Mintz if (rc) 1181fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 1182fe56b9e6SYuval Mintz "init phase failed for loadcode 0x%x (rc %d)\n", 1183fe56b9e6SYuval Mintz load_code, rc); 1184fe56b9e6SYuval Mintz 1185fe56b9e6SYuval Mintz /* ACK mfw regardless of success or failure of initialization */ 1186fe56b9e6SYuval Mintz mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1187fe56b9e6SYuval Mintz DRV_MSG_CODE_LOAD_DONE, 1188fe56b9e6SYuval Mintz 0, &load_code, ¶m); 1189fe56b9e6SYuval Mintz if (rc) 1190fe56b9e6SYuval Mintz return rc; 1191fe56b9e6SYuval Mintz if (mfw_rc) { 1192fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n"); 1193fe56b9e6SYuval Mintz return mfw_rc; 1194fe56b9e6SYuval Mintz } 1195fe56b9e6SYuval Mintz 119639651abdSSudarsana Reddy Kalluru /* send DCBX attention request command */ 119739651abdSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, 119839651abdSSudarsana Reddy Kalluru QED_MSG_DCB, 119939651abdSSudarsana Reddy Kalluru "sending phony dcbx set command to trigger DCBx attention handling\n"); 120039651abdSSudarsana Reddy Kalluru mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 120139651abdSSudarsana Reddy Kalluru DRV_MSG_CODE_SET_DCBX, 120239651abdSSudarsana Reddy Kalluru 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT, 120339651abdSSudarsana Reddy Kalluru &load_code, ¶m); 120439651abdSSudarsana Reddy Kalluru if (mfw_rc) { 120539651abdSSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 120639651abdSSudarsana Reddy Kalluru "Failed to send DCBX attention request\n"); 120739651abdSSudarsana Reddy Kalluru return mfw_rc; 120839651abdSSudarsana Reddy Kalluru } 120939651abdSSudarsana Reddy Kalluru 1210fe56b9e6SYuval Mintz p_hwfn->hw_init_done = true; 1211fe56b9e6SYuval Mintz } 1212fe56b9e6SYuval Mintz 12130fefbfbaSSudarsana Kalluru if (IS_PF(cdev)) { 12140fefbfbaSSudarsana Kalluru p_hwfn = QED_LEADING_HWFN(cdev); 12150fefbfbaSSudarsana Kalluru drv_mb_param = (FW_MAJOR_VERSION << 24) | 12160fefbfbaSSudarsana Kalluru (FW_MINOR_VERSION << 16) | 12170fefbfbaSSudarsana Kalluru (FW_REVISION_VERSION << 8) | 12180fefbfbaSSudarsana Kalluru (FW_ENGINEERING_VERSION); 12190fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 12200fefbfbaSSudarsana Kalluru DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER, 12210fefbfbaSSudarsana Kalluru drv_mb_param, &load_code, ¶m); 12220fefbfbaSSudarsana Kalluru if (rc) 12230fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, "Failed to update firmware version\n"); 12240fefbfbaSSudarsana Kalluru 12250fefbfbaSSudarsana Kalluru if (!b_default_mtu) { 12260fefbfbaSSudarsana Kalluru rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt, 12270fefbfbaSSudarsana Kalluru p_hwfn->hw_info.mtu); 12280fefbfbaSSudarsana Kalluru if (rc) 12290fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, 12300fefbfbaSSudarsana Kalluru "Failed to update default mtu\n"); 12310fefbfbaSSudarsana Kalluru } 12320fefbfbaSSudarsana Kalluru 12330fefbfbaSSudarsana Kalluru rc = qed_mcp_ov_update_driver_state(p_hwfn, 12340fefbfbaSSudarsana Kalluru p_hwfn->p_main_ptt, 12350fefbfbaSSudarsana Kalluru QED_OV_DRIVER_STATE_DISABLED); 12360fefbfbaSSudarsana Kalluru if (rc) 12370fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, "Failed to update driver state\n"); 12380fefbfbaSSudarsana Kalluru 12390fefbfbaSSudarsana Kalluru rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt, 12400fefbfbaSSudarsana Kalluru QED_OV_ESWITCH_VEB); 12410fefbfbaSSudarsana Kalluru if (rc) 12420fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, "Failed to update eswitch mode\n"); 12430fefbfbaSSudarsana Kalluru } 12440fefbfbaSSudarsana Kalluru 1245fe56b9e6SYuval Mintz return 0; 1246fe56b9e6SYuval Mintz } 1247fe56b9e6SYuval Mintz 1248fe56b9e6SYuval Mintz #define QED_HW_STOP_RETRY_LIMIT (10) 12491a635e48SYuval Mintz static void qed_hw_timers_stop(struct qed_dev *cdev, 12501a635e48SYuval Mintz struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 12518c925c44SYuval Mintz { 12528c925c44SYuval Mintz int i; 12538c925c44SYuval Mintz 12548c925c44SYuval Mintz /* close timers */ 12558c925c44SYuval Mintz qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0); 12568c925c44SYuval Mintz qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0); 12578c925c44SYuval Mintz 12588c925c44SYuval Mintz for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) { 12598c925c44SYuval Mintz if ((!qed_rd(p_hwfn, p_ptt, 12608c925c44SYuval Mintz TM_REG_PF_SCAN_ACTIVE_CONN)) && 12611a635e48SYuval Mintz (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK))) 12628c925c44SYuval Mintz break; 12638c925c44SYuval Mintz 12648c925c44SYuval Mintz /* Dependent on number of connection/tasks, possibly 12658c925c44SYuval Mintz * 1ms sleep is required between polls 12668c925c44SYuval Mintz */ 12678c925c44SYuval Mintz usleep_range(1000, 2000); 12688c925c44SYuval Mintz } 12698c925c44SYuval Mintz 12708c925c44SYuval Mintz if (i < QED_HW_STOP_RETRY_LIMIT) 12718c925c44SYuval Mintz return; 12728c925c44SYuval Mintz 12738c925c44SYuval Mintz DP_NOTICE(p_hwfn, 12748c925c44SYuval Mintz "Timers linear scans are not over [Connection %02x Tasks %02x]\n", 12758c925c44SYuval Mintz (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN), 12768c925c44SYuval Mintz (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)); 12778c925c44SYuval Mintz } 12788c925c44SYuval Mintz 12798c925c44SYuval Mintz void qed_hw_timers_stop_all(struct qed_dev *cdev) 12808c925c44SYuval Mintz { 12818c925c44SYuval Mintz int j; 12828c925c44SYuval Mintz 12838c925c44SYuval Mintz for_each_hwfn(cdev, j) { 12848c925c44SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 12858c925c44SYuval Mintz struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 12868c925c44SYuval Mintz 12878c925c44SYuval Mintz qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 12888c925c44SYuval Mintz } 12898c925c44SYuval Mintz } 12908c925c44SYuval Mintz 1291fe56b9e6SYuval Mintz int qed_hw_stop(struct qed_dev *cdev) 1292fe56b9e6SYuval Mintz { 1293fe56b9e6SYuval Mintz int rc = 0, t_rc; 12948c925c44SYuval Mintz int j; 1295fe56b9e6SYuval Mintz 1296fe56b9e6SYuval Mintz for_each_hwfn(cdev, j) { 1297fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 1298fe56b9e6SYuval Mintz struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 1299fe56b9e6SYuval Mintz 1300fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n"); 1301fe56b9e6SYuval Mintz 13021408cc1fSYuval Mintz if (IS_VF(cdev)) { 13030b55e27dSYuval Mintz qed_vf_pf_int_cleanup(p_hwfn); 13041408cc1fSYuval Mintz continue; 13051408cc1fSYuval Mintz } 13061408cc1fSYuval Mintz 1307fe56b9e6SYuval Mintz /* mark the hw as uninitialized... */ 1308fe56b9e6SYuval Mintz p_hwfn->hw_init_done = false; 1309fe56b9e6SYuval Mintz 1310fe56b9e6SYuval Mintz rc = qed_sp_pf_stop(p_hwfn); 1311fe56b9e6SYuval Mintz if (rc) 13128c925c44SYuval Mintz DP_NOTICE(p_hwfn, 13138c925c44SYuval Mintz "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n"); 1314fe56b9e6SYuval Mintz 1315fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 1316fe56b9e6SYuval Mintz NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 1317fe56b9e6SYuval Mintz 1318fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1319fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 1320fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 1321fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1322fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 1323fe56b9e6SYuval Mintz 13248c925c44SYuval Mintz qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 1325fe56b9e6SYuval Mintz 1326fe56b9e6SYuval Mintz /* Disable Attention Generation */ 1327fe56b9e6SYuval Mintz qed_int_igu_disable_int(p_hwfn, p_ptt); 1328fe56b9e6SYuval Mintz 1329fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0); 1330fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0); 1331fe56b9e6SYuval Mintz 1332fe56b9e6SYuval Mintz qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true); 1333fe56b9e6SYuval Mintz 1334fe56b9e6SYuval Mintz /* Need to wait 1ms to guarantee SBs are cleared */ 1335fe56b9e6SYuval Mintz usleep_range(1000, 2000); 1336fe56b9e6SYuval Mintz } 1337fe56b9e6SYuval Mintz 13381408cc1fSYuval Mintz if (IS_PF(cdev)) { 1339fe56b9e6SYuval Mintz /* Disable DMAE in PXP - in CMT, this should only be done for 1340fe56b9e6SYuval Mintz * first hw-function, and only after all transactions have 1341fe56b9e6SYuval Mintz * stopped for all active hw-functions. 1342fe56b9e6SYuval Mintz */ 1343fe56b9e6SYuval Mintz t_rc = qed_change_pci_hwfn(&cdev->hwfns[0], 13441408cc1fSYuval Mintz cdev->hwfns[0].p_main_ptt, false); 1345fe56b9e6SYuval Mintz if (t_rc != 0) 1346fe56b9e6SYuval Mintz rc = t_rc; 13471408cc1fSYuval Mintz } 1348fe56b9e6SYuval Mintz 1349fe56b9e6SYuval Mintz return rc; 1350fe56b9e6SYuval Mintz } 1351fe56b9e6SYuval Mintz 1352cee4d264SManish Chopra void qed_hw_stop_fastpath(struct qed_dev *cdev) 1353cee4d264SManish Chopra { 13548c925c44SYuval Mintz int j; 1355cee4d264SManish Chopra 1356cee4d264SManish Chopra for_each_hwfn(cdev, j) { 1357cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 1358cee4d264SManish Chopra struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 1359cee4d264SManish Chopra 1360dacd88d6SYuval Mintz if (IS_VF(cdev)) { 1361dacd88d6SYuval Mintz qed_vf_pf_int_cleanup(p_hwfn); 1362dacd88d6SYuval Mintz continue; 1363dacd88d6SYuval Mintz } 1364dacd88d6SYuval Mintz 1365cee4d264SManish Chopra DP_VERBOSE(p_hwfn, 13661a635e48SYuval Mintz NETIF_MSG_IFDOWN, "Shutting down the fastpath\n"); 1367cee4d264SManish Chopra 1368cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, 1369cee4d264SManish Chopra NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 1370cee4d264SManish Chopra 1371cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1372cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 1373cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 1374cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1375cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 1376cee4d264SManish Chopra 1377cee4d264SManish Chopra qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false); 1378cee4d264SManish Chopra 1379cee4d264SManish Chopra /* Need to wait 1ms to guarantee SBs are cleared */ 1380cee4d264SManish Chopra usleep_range(1000, 2000); 1381cee4d264SManish Chopra } 1382cee4d264SManish Chopra } 1383cee4d264SManish Chopra 1384cee4d264SManish Chopra void qed_hw_start_fastpath(struct qed_hwfn *p_hwfn) 1385cee4d264SManish Chopra { 1386dacd88d6SYuval Mintz if (IS_VF(p_hwfn->cdev)) 1387dacd88d6SYuval Mintz return; 1388dacd88d6SYuval Mintz 1389cee4d264SManish Chopra /* Re-open incoming traffic */ 1390cee4d264SManish Chopra qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1391cee4d264SManish Chopra NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0); 1392cee4d264SManish Chopra } 1393cee4d264SManish Chopra 13941a635e48SYuval Mintz static int qed_reg_assert(struct qed_hwfn *p_hwfn, 13951a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 reg, bool expected) 1396fe56b9e6SYuval Mintz { 13971a635e48SYuval Mintz u32 assert_val = qed_rd(p_hwfn, p_ptt, reg); 1398fe56b9e6SYuval Mintz 1399fe56b9e6SYuval Mintz if (assert_val != expected) { 1400525ef5c0SYuval Mintz DP_NOTICE(p_hwfn, "Value at address 0x%08x != 0x%08x\n", 1401fe56b9e6SYuval Mintz reg, expected); 1402fe56b9e6SYuval Mintz return -EINVAL; 1403fe56b9e6SYuval Mintz } 1404fe56b9e6SYuval Mintz 1405fe56b9e6SYuval Mintz return 0; 1406fe56b9e6SYuval Mintz } 1407fe56b9e6SYuval Mintz 1408fe56b9e6SYuval Mintz int qed_hw_reset(struct qed_dev *cdev) 1409fe56b9e6SYuval Mintz { 1410fe56b9e6SYuval Mintz int rc = 0; 1411fe56b9e6SYuval Mintz u32 unload_resp, unload_param; 141214d39648SMintz, Yuval u32 wol_param; 1413fe56b9e6SYuval Mintz int i; 1414fe56b9e6SYuval Mintz 141514d39648SMintz, Yuval switch (cdev->wol_config) { 141614d39648SMintz, Yuval case QED_OV_WOL_DISABLED: 141714d39648SMintz, Yuval wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED; 141814d39648SMintz, Yuval break; 141914d39648SMintz, Yuval case QED_OV_WOL_ENABLED: 142014d39648SMintz, Yuval wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED; 142114d39648SMintz, Yuval break; 142214d39648SMintz, Yuval default: 142314d39648SMintz, Yuval DP_NOTICE(cdev, 142414d39648SMintz, Yuval "Unknown WoL configuration %02x\n", cdev->wol_config); 142514d39648SMintz, Yuval /* Fallthrough */ 142614d39648SMintz, Yuval case QED_OV_WOL_DEFAULT: 142714d39648SMintz, Yuval wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP; 142814d39648SMintz, Yuval } 142914d39648SMintz, Yuval 1430fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 1431fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1432fe56b9e6SYuval Mintz 14331408cc1fSYuval Mintz if (IS_VF(cdev)) { 14340b55e27dSYuval Mintz rc = qed_vf_pf_reset(p_hwfn); 14350b55e27dSYuval Mintz if (rc) 14360b55e27dSYuval Mintz return rc; 14371408cc1fSYuval Mintz continue; 14381408cc1fSYuval Mintz } 14391408cc1fSYuval Mintz 1440fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Resetting hw/fw\n"); 1441fe56b9e6SYuval Mintz 1442fe56b9e6SYuval Mintz /* Check for incorrect states */ 1443fe56b9e6SYuval Mintz qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt, 1444fe56b9e6SYuval Mintz QM_REG_USG_CNT_PF_TX, 0); 1445fe56b9e6SYuval Mintz qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt, 1446fe56b9e6SYuval Mintz QM_REG_USG_CNT_PF_OTHER, 0); 1447fe56b9e6SYuval Mintz 1448fe56b9e6SYuval Mintz /* Disable PF in HW blocks */ 1449fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0); 1450fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0); 1451fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1452fe56b9e6SYuval Mintz TCFC_REG_STRONG_ENABLE_PF, 0); 1453fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1454fe56b9e6SYuval Mintz CCFC_REG_STRONG_ENABLE_PF, 0); 1455fe56b9e6SYuval Mintz 1456fe56b9e6SYuval Mintz /* Send unload command to MCP */ 1457fe56b9e6SYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 145814d39648SMintz, Yuval DRV_MSG_CODE_UNLOAD_REQ, wol_param, 1459fe56b9e6SYuval Mintz &unload_resp, &unload_param); 1460fe56b9e6SYuval Mintz if (rc) { 1461fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_REQ failed\n"); 1462fe56b9e6SYuval Mintz unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE; 1463fe56b9e6SYuval Mintz } 1464fe56b9e6SYuval Mintz 1465fe56b9e6SYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1466fe56b9e6SYuval Mintz DRV_MSG_CODE_UNLOAD_DONE, 1467fe56b9e6SYuval Mintz 0, &unload_resp, &unload_param); 1468fe56b9e6SYuval Mintz if (rc) { 1469fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_DONE failed\n"); 1470fe56b9e6SYuval Mintz return rc; 1471fe56b9e6SYuval Mintz } 1472fe56b9e6SYuval Mintz } 1473fe56b9e6SYuval Mintz 1474fe56b9e6SYuval Mintz return rc; 1475fe56b9e6SYuval Mintz } 1476fe56b9e6SYuval Mintz 1477fe56b9e6SYuval Mintz /* Free hwfn memory and resources acquired in hw_hwfn_prepare */ 1478fe56b9e6SYuval Mintz static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn) 1479fe56b9e6SYuval Mintz { 1480fe56b9e6SYuval Mintz qed_ptt_pool_free(p_hwfn); 1481fe56b9e6SYuval Mintz kfree(p_hwfn->hw_info.p_igu_info); 1482fe56b9e6SYuval Mintz } 1483fe56b9e6SYuval Mintz 1484fe56b9e6SYuval Mintz /* Setup bar access */ 148512e09c69SYuval Mintz static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn) 1486fe56b9e6SYuval Mintz { 1487fe56b9e6SYuval Mintz /* clear indirect access */ 1488fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0); 1489fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0); 1490fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0); 1491fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0); 1492fe56b9e6SYuval Mintz 1493fe56b9e6SYuval Mintz /* Clean Previous errors if such exist */ 1494fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, 14951a635e48SYuval Mintz PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id); 1496fe56b9e6SYuval Mintz 1497fe56b9e6SYuval Mintz /* enable internal target-read */ 1498fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1499fe56b9e6SYuval Mintz PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 1500fe56b9e6SYuval Mintz } 1501fe56b9e6SYuval Mintz 1502fe56b9e6SYuval Mintz static void get_function_id(struct qed_hwfn *p_hwfn) 1503fe56b9e6SYuval Mintz { 1504fe56b9e6SYuval Mintz /* ME Register */ 15051a635e48SYuval Mintz p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn, 15061a635e48SYuval Mintz PXP_PF_ME_OPAQUE_ADDR); 1507fe56b9e6SYuval Mintz 1508fe56b9e6SYuval Mintz p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); 1509fe56b9e6SYuval Mintz 1510fe56b9e6SYuval Mintz p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf; 1511fe56b9e6SYuval Mintz p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 1512fe56b9e6SYuval Mintz PXP_CONCRETE_FID_PFID); 1513fe56b9e6SYuval Mintz p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 1514fe56b9e6SYuval Mintz PXP_CONCRETE_FID_PORT); 1515525ef5c0SYuval Mintz 1516525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, 1517525ef5c0SYuval Mintz "Read ME register: Concrete 0x%08x Opaque 0x%04x\n", 1518525ef5c0SYuval Mintz p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid); 1519fe56b9e6SYuval Mintz } 1520fe56b9e6SYuval Mintz 152125c089d7SYuval Mintz static void qed_hw_set_feat(struct qed_hwfn *p_hwfn) 152225c089d7SYuval Mintz { 152325c089d7SYuval Mintz u32 *feat_num = p_hwfn->hw_info.feat_num; 15245a1f965aSMintz, Yuval struct qed_sb_cnt_info sb_cnt_info; 152525c089d7SYuval Mintz int num_features = 1; 152625c089d7SYuval Mintz 15270189efb8SYuval Mintz if (IS_ENABLED(CONFIG_QED_RDMA) && 15280189efb8SYuval Mintz p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) { 15290189efb8SYuval Mintz /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide 15300189efb8SYuval Mintz * the status blocks equally between L2 / RoCE but with 15310189efb8SYuval Mintz * consideration as to how many l2 queues / cnqs we have. 153251ff1725SRam Amrani */ 153351ff1725SRam Amrani num_features++; 153451ff1725SRam Amrani 153551ff1725SRam Amrani feat_num[QED_RDMA_CNQ] = 153651ff1725SRam Amrani min_t(u32, RESC_NUM(p_hwfn, QED_SB) / num_features, 153751ff1725SRam Amrani RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM)); 153851ff1725SRam Amrani } 15390189efb8SYuval Mintz 154025c089d7SYuval Mintz feat_num[QED_PF_L2_QUE] = min_t(u32, RESC_NUM(p_hwfn, QED_SB) / 154125c089d7SYuval Mintz num_features, 154225c089d7SYuval Mintz RESC_NUM(p_hwfn, QED_L2_QUEUE)); 15435a1f965aSMintz, Yuval 15445a1f965aSMintz, Yuval memset(&sb_cnt_info, 0, sizeof(sb_cnt_info)); 15455a1f965aSMintz, Yuval qed_int_get_num_sbs(p_hwfn, &sb_cnt_info); 15465a1f965aSMintz, Yuval feat_num[QED_VF_L2_QUE] = 15475a1f965aSMintz, Yuval min_t(u32, 15485a1f965aSMintz, Yuval RESC_NUM(p_hwfn, QED_L2_QUEUE) - 15495a1f965aSMintz, Yuval FEAT_NUM(p_hwfn, QED_PF_L2_QUE), sb_cnt_info.sb_iov_cnt); 15505a1f965aSMintz, Yuval 15515a1f965aSMintz, Yuval DP_VERBOSE(p_hwfn, 15525a1f965aSMintz, Yuval NETIF_MSG_PROBE, 15535a1f965aSMintz, Yuval "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #SBS=%d num_features=%d\n", 15545a1f965aSMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE), 15555a1f965aSMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE), 15565a1f965aSMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ), 15575a1f965aSMintz, Yuval RESC_NUM(p_hwfn, QED_SB), num_features); 155825c089d7SYuval Mintz } 155925c089d7SYuval Mintz 15602edbff8dSTomer Tayar static enum resource_id_enum qed_hw_get_mfw_res_id(enum qed_resources res_id) 15612edbff8dSTomer Tayar { 15622edbff8dSTomer Tayar enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID; 15632edbff8dSTomer Tayar 15642edbff8dSTomer Tayar switch (res_id) { 15652edbff8dSTomer Tayar case QED_SB: 15662edbff8dSTomer Tayar mfw_res_id = RESOURCE_NUM_SB_E; 15672edbff8dSTomer Tayar break; 15682edbff8dSTomer Tayar case QED_L2_QUEUE: 15692edbff8dSTomer Tayar mfw_res_id = RESOURCE_NUM_L2_QUEUE_E; 15702edbff8dSTomer Tayar break; 15712edbff8dSTomer Tayar case QED_VPORT: 15722edbff8dSTomer Tayar mfw_res_id = RESOURCE_NUM_VPORT_E; 15732edbff8dSTomer Tayar break; 15742edbff8dSTomer Tayar case QED_RSS_ENG: 15752edbff8dSTomer Tayar mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E; 15762edbff8dSTomer Tayar break; 15772edbff8dSTomer Tayar case QED_PQ: 15782edbff8dSTomer Tayar mfw_res_id = RESOURCE_NUM_PQ_E; 15792edbff8dSTomer Tayar break; 15802edbff8dSTomer Tayar case QED_RL: 15812edbff8dSTomer Tayar mfw_res_id = RESOURCE_NUM_RL_E; 15822edbff8dSTomer Tayar break; 15832edbff8dSTomer Tayar case QED_MAC: 15842edbff8dSTomer Tayar case QED_VLAN: 15852edbff8dSTomer Tayar /* Each VFC resource can accommodate both a MAC and a VLAN */ 15862edbff8dSTomer Tayar mfw_res_id = RESOURCE_VFC_FILTER_E; 15872edbff8dSTomer Tayar break; 15882edbff8dSTomer Tayar case QED_ILT: 15892edbff8dSTomer Tayar mfw_res_id = RESOURCE_ILT_E; 15902edbff8dSTomer Tayar break; 15912edbff8dSTomer Tayar case QED_LL2_QUEUE: 15922edbff8dSTomer Tayar mfw_res_id = RESOURCE_LL2_QUEUE_E; 15932edbff8dSTomer Tayar break; 15942edbff8dSTomer Tayar case QED_RDMA_CNQ_RAM: 15952edbff8dSTomer Tayar case QED_CMDQS_CQS: 15962edbff8dSTomer Tayar /* CNQ/CMDQS are the same resource */ 15972edbff8dSTomer Tayar mfw_res_id = RESOURCE_CQS_E; 15982edbff8dSTomer Tayar break; 15992edbff8dSTomer Tayar case QED_RDMA_STATS_QUEUE: 16002edbff8dSTomer Tayar mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E; 16012edbff8dSTomer Tayar break; 16022edbff8dSTomer Tayar default: 16032edbff8dSTomer Tayar break; 16042edbff8dSTomer Tayar } 16052edbff8dSTomer Tayar 16062edbff8dSTomer Tayar return mfw_res_id; 16072edbff8dSTomer Tayar } 16082edbff8dSTomer Tayar 16092edbff8dSTomer Tayar static u32 qed_hw_get_dflt_resc_num(struct qed_hwfn *p_hwfn, 16102edbff8dSTomer Tayar enum qed_resources res_id) 16112edbff8dSTomer Tayar { 16122edbff8dSTomer Tayar u8 num_funcs = p_hwfn->num_funcs_on_engine; 16132edbff8dSTomer Tayar struct qed_sb_cnt_info sb_cnt_info; 16142edbff8dSTomer Tayar u32 dflt_resc_num = 0; 16152edbff8dSTomer Tayar 16162edbff8dSTomer Tayar switch (res_id) { 16172edbff8dSTomer Tayar case QED_SB: 16182edbff8dSTomer Tayar memset(&sb_cnt_info, 0, sizeof(sb_cnt_info)); 16192edbff8dSTomer Tayar qed_int_get_num_sbs(p_hwfn, &sb_cnt_info); 16202edbff8dSTomer Tayar dflt_resc_num = sb_cnt_info.sb_cnt; 16212edbff8dSTomer Tayar break; 16222edbff8dSTomer Tayar case QED_L2_QUEUE: 16232edbff8dSTomer Tayar dflt_resc_num = MAX_NUM_L2_QUEUES_BB / num_funcs; 16242edbff8dSTomer Tayar break; 16252edbff8dSTomer Tayar case QED_VPORT: 16262edbff8dSTomer Tayar dflt_resc_num = MAX_NUM_VPORTS_BB / num_funcs; 16272edbff8dSTomer Tayar break; 16282edbff8dSTomer Tayar case QED_RSS_ENG: 16292edbff8dSTomer Tayar dflt_resc_num = ETH_RSS_ENGINE_NUM_BB / num_funcs; 16302edbff8dSTomer Tayar break; 16312edbff8dSTomer Tayar case QED_PQ: 16322edbff8dSTomer Tayar /* The granularity of the PQs is 8 */ 16332edbff8dSTomer Tayar dflt_resc_num = MAX_QM_TX_QUEUES_BB / num_funcs; 16342edbff8dSTomer Tayar dflt_resc_num &= ~0x7; 16352edbff8dSTomer Tayar break; 16362edbff8dSTomer Tayar case QED_RL: 16372edbff8dSTomer Tayar dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs; 16382edbff8dSTomer Tayar break; 16392edbff8dSTomer Tayar case QED_MAC: 16402edbff8dSTomer Tayar case QED_VLAN: 16412edbff8dSTomer Tayar /* Each VFC resource can accommodate both a MAC and a VLAN */ 16422edbff8dSTomer Tayar dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs; 16432edbff8dSTomer Tayar break; 16442edbff8dSTomer Tayar case QED_ILT: 16452edbff8dSTomer Tayar dflt_resc_num = PXP_NUM_ILT_RECORDS_BB / num_funcs; 16462edbff8dSTomer Tayar break; 16472edbff8dSTomer Tayar case QED_LL2_QUEUE: 16482edbff8dSTomer Tayar dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs; 16492edbff8dSTomer Tayar break; 16502edbff8dSTomer Tayar case QED_RDMA_CNQ_RAM: 16512edbff8dSTomer Tayar case QED_CMDQS_CQS: 16522edbff8dSTomer Tayar /* CNQ/CMDQS are the same resource */ 16532edbff8dSTomer Tayar dflt_resc_num = NUM_OF_CMDQS_CQS / num_funcs; 16542edbff8dSTomer Tayar break; 16552edbff8dSTomer Tayar case QED_RDMA_STATS_QUEUE: 16562edbff8dSTomer Tayar dflt_resc_num = RDMA_NUM_STATISTIC_COUNTERS_BB / num_funcs; 16572edbff8dSTomer Tayar break; 16582edbff8dSTomer Tayar default: 16592edbff8dSTomer Tayar break; 16602edbff8dSTomer Tayar } 16612edbff8dSTomer Tayar 16622edbff8dSTomer Tayar return dflt_resc_num; 16632edbff8dSTomer Tayar } 16642edbff8dSTomer Tayar 16652edbff8dSTomer Tayar static const char *qed_hw_get_resc_name(enum qed_resources res_id) 16662edbff8dSTomer Tayar { 16672edbff8dSTomer Tayar switch (res_id) { 16682edbff8dSTomer Tayar case QED_SB: 16692edbff8dSTomer Tayar return "SB"; 16702edbff8dSTomer Tayar case QED_L2_QUEUE: 16712edbff8dSTomer Tayar return "L2_QUEUE"; 16722edbff8dSTomer Tayar case QED_VPORT: 16732edbff8dSTomer Tayar return "VPORT"; 16742edbff8dSTomer Tayar case QED_RSS_ENG: 16752edbff8dSTomer Tayar return "RSS_ENG"; 16762edbff8dSTomer Tayar case QED_PQ: 16772edbff8dSTomer Tayar return "PQ"; 16782edbff8dSTomer Tayar case QED_RL: 16792edbff8dSTomer Tayar return "RL"; 16802edbff8dSTomer Tayar case QED_MAC: 16812edbff8dSTomer Tayar return "MAC"; 16822edbff8dSTomer Tayar case QED_VLAN: 16832edbff8dSTomer Tayar return "VLAN"; 16842edbff8dSTomer Tayar case QED_RDMA_CNQ_RAM: 16852edbff8dSTomer Tayar return "RDMA_CNQ_RAM"; 16862edbff8dSTomer Tayar case QED_ILT: 16872edbff8dSTomer Tayar return "ILT"; 16882edbff8dSTomer Tayar case QED_LL2_QUEUE: 16892edbff8dSTomer Tayar return "LL2_QUEUE"; 16902edbff8dSTomer Tayar case QED_CMDQS_CQS: 16912edbff8dSTomer Tayar return "CMDQS_CQS"; 16922edbff8dSTomer Tayar case QED_RDMA_STATS_QUEUE: 16932edbff8dSTomer Tayar return "RDMA_STATS_QUEUE"; 16942edbff8dSTomer Tayar default: 16952edbff8dSTomer Tayar return "UNKNOWN_RESOURCE"; 16962edbff8dSTomer Tayar } 16972edbff8dSTomer Tayar } 16982edbff8dSTomer Tayar 16992edbff8dSTomer Tayar static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn, 17002edbff8dSTomer Tayar enum qed_resources res_id) 17012edbff8dSTomer Tayar { 17022edbff8dSTomer Tayar u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param; 17032edbff8dSTomer Tayar u32 *p_resc_num, *p_resc_start; 17042edbff8dSTomer Tayar struct resource_info resc_info; 17052edbff8dSTomer Tayar int rc; 17062edbff8dSTomer Tayar 17072edbff8dSTomer Tayar p_resc_num = &RESC_NUM(p_hwfn, res_id); 17082edbff8dSTomer Tayar p_resc_start = &RESC_START(p_hwfn, res_id); 17092edbff8dSTomer Tayar 17102edbff8dSTomer Tayar /* Default values assumes that each function received equal share */ 17112edbff8dSTomer Tayar dflt_resc_num = qed_hw_get_dflt_resc_num(p_hwfn, res_id); 17122edbff8dSTomer Tayar if (!dflt_resc_num) { 17132edbff8dSTomer Tayar DP_ERR(p_hwfn, 17142edbff8dSTomer Tayar "Failed to get default amount for resource %d [%s]\n", 17152edbff8dSTomer Tayar res_id, qed_hw_get_resc_name(res_id)); 17162edbff8dSTomer Tayar return -EINVAL; 17172edbff8dSTomer Tayar } 17182edbff8dSTomer Tayar dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx; 17192edbff8dSTomer Tayar 17202edbff8dSTomer Tayar memset(&resc_info, 0, sizeof(resc_info)); 17212edbff8dSTomer Tayar resc_info.res_id = qed_hw_get_mfw_res_id(res_id); 17222edbff8dSTomer Tayar if (resc_info.res_id == RESOURCE_NUM_INVALID) { 17232edbff8dSTomer Tayar DP_ERR(p_hwfn, 17242edbff8dSTomer Tayar "Failed to match resource %d [%s] with the MFW resources\n", 17252edbff8dSTomer Tayar res_id, qed_hw_get_resc_name(res_id)); 17262edbff8dSTomer Tayar return -EINVAL; 17272edbff8dSTomer Tayar } 17282edbff8dSTomer Tayar 17292edbff8dSTomer Tayar rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info, 17302edbff8dSTomer Tayar &mcp_resp, &mcp_param); 17312edbff8dSTomer Tayar if (rc) { 17322edbff8dSTomer Tayar DP_NOTICE(p_hwfn, 17332edbff8dSTomer Tayar "MFW response failure for an allocation request for resource %d [%s]\n", 17342edbff8dSTomer Tayar res_id, qed_hw_get_resc_name(res_id)); 17352edbff8dSTomer Tayar return rc; 17362edbff8dSTomer Tayar } 17372edbff8dSTomer Tayar 17382edbff8dSTomer Tayar /* Default driver values are applied in the following cases: 17392edbff8dSTomer Tayar * - The resource allocation MB command is not supported by the MFW 17402edbff8dSTomer Tayar * - There is an internal error in the MFW while processing the request 17412edbff8dSTomer Tayar * - The resource ID is unknown to the MFW 17422edbff8dSTomer Tayar */ 17432edbff8dSTomer Tayar if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK && 17442edbff8dSTomer Tayar mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) { 17452edbff8dSTomer Tayar DP_NOTICE(p_hwfn, 17462edbff8dSTomer Tayar "Resource %d [%s]: No allocation info was received [mcp_resp 0x%x]. Applying default values [num %d, start %d].\n", 17472edbff8dSTomer Tayar res_id, 17482edbff8dSTomer Tayar qed_hw_get_resc_name(res_id), 17492edbff8dSTomer Tayar mcp_resp, dflt_resc_num, dflt_resc_start); 17502edbff8dSTomer Tayar *p_resc_num = dflt_resc_num; 17512edbff8dSTomer Tayar *p_resc_start = dflt_resc_start; 17522edbff8dSTomer Tayar goto out; 17532edbff8dSTomer Tayar } 17542edbff8dSTomer Tayar 17552edbff8dSTomer Tayar /* Special handling for status blocks; Would be revised in future */ 17562edbff8dSTomer Tayar if (res_id == QED_SB) { 17572edbff8dSTomer Tayar resc_info.size -= 1; 17582edbff8dSTomer Tayar resc_info.offset -= p_hwfn->enabled_func_idx; 17592edbff8dSTomer Tayar } 17602edbff8dSTomer Tayar 17612edbff8dSTomer Tayar *p_resc_num = resc_info.size; 17622edbff8dSTomer Tayar *p_resc_start = resc_info.offset; 17632edbff8dSTomer Tayar 17642edbff8dSTomer Tayar out: 17652edbff8dSTomer Tayar /* PQs have to divide by 8 [that's the HW granularity]. 17662edbff8dSTomer Tayar * Reduce number so it would fit. 17672edbff8dSTomer Tayar */ 17682edbff8dSTomer Tayar if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) { 17692edbff8dSTomer Tayar DP_INFO(p_hwfn, 17702edbff8dSTomer Tayar "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n", 17712edbff8dSTomer Tayar *p_resc_num, 17722edbff8dSTomer Tayar (*p_resc_num) & ~0x7, 17732edbff8dSTomer Tayar *p_resc_start, (*p_resc_start) & ~0x7); 17742edbff8dSTomer Tayar *p_resc_num &= ~0x7; 17752edbff8dSTomer Tayar *p_resc_start &= ~0x7; 17762edbff8dSTomer Tayar } 17772edbff8dSTomer Tayar 17782edbff8dSTomer Tayar return 0; 17792edbff8dSTomer Tayar } 17802edbff8dSTomer Tayar 1781dbb799c3SYuval Mintz static int qed_hw_get_resc(struct qed_hwfn *p_hwfn) 1782fe56b9e6SYuval Mintz { 17832edbff8dSTomer Tayar u8 res_id; 17842edbff8dSTomer Tayar int rc; 1785fe56b9e6SYuval Mintz 17862edbff8dSTomer Tayar for (res_id = 0; res_id < QED_MAX_RESC; res_id++) { 17872edbff8dSTomer Tayar rc = qed_hw_set_resc_info(p_hwfn, res_id); 17882edbff8dSTomer Tayar if (rc) 17892edbff8dSTomer Tayar return rc; 17902edbff8dSTomer Tayar } 1791dbb799c3SYuval Mintz 1792dbb799c3SYuval Mintz /* Sanity for ILT */ 17932edbff8dSTomer Tayar if ((RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB)) { 1794dbb799c3SYuval Mintz DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n", 1795dbb799c3SYuval Mintz RESC_START(p_hwfn, QED_ILT), 1796dbb799c3SYuval Mintz RESC_END(p_hwfn, QED_ILT) - 1); 1797dbb799c3SYuval Mintz return -EINVAL; 1798dbb799c3SYuval Mintz } 1799fe56b9e6SYuval Mintz 180025c089d7SYuval Mintz qed_hw_set_feat(p_hwfn); 180125c089d7SYuval Mintz 1802fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, 18032edbff8dSTomer Tayar "The numbers for each resource are:\n"); 18042edbff8dSTomer Tayar for (res_id = 0; res_id < QED_MAX_RESC; res_id++) 18052edbff8dSTomer Tayar DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n", 18062edbff8dSTomer Tayar qed_hw_get_resc_name(res_id), 18072edbff8dSTomer Tayar RESC_NUM(p_hwfn, res_id), 18082edbff8dSTomer Tayar RESC_START(p_hwfn, res_id)); 1809dbb799c3SYuval Mintz 1810dbb799c3SYuval Mintz return 0; 1811fe56b9e6SYuval Mintz } 1812fe56b9e6SYuval Mintz 18131a635e48SYuval Mintz static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1814fe56b9e6SYuval Mintz { 1815fc48b7a6SYuval Mintz u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities; 18161e128c81SArun Easi u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg; 1817cc875c2eSYuval Mintz struct qed_mcp_link_params *link; 1818fe56b9e6SYuval Mintz 1819fe56b9e6SYuval Mintz /* Read global nvm_cfg address */ 1820fe56b9e6SYuval Mintz nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 1821fe56b9e6SYuval Mintz 1822fe56b9e6SYuval Mintz /* Verify MCP has initialized it */ 1823fe56b9e6SYuval Mintz if (!nvm_cfg_addr) { 1824fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 1825fe56b9e6SYuval Mintz return -EINVAL; 1826fe56b9e6SYuval Mintz } 1827fe56b9e6SYuval Mintz 1828fe56b9e6SYuval Mintz /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */ 1829fe56b9e6SYuval Mintz nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 1830fe56b9e6SYuval Mintz 1831cc875c2eSYuval Mintz addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1832cc875c2eSYuval Mintz offsetof(struct nvm_cfg1, glob) + 1833cc875c2eSYuval Mintz offsetof(struct nvm_cfg1_glob, core_cfg); 1834cc875c2eSYuval Mintz 1835cc875c2eSYuval Mintz core_cfg = qed_rd(p_hwfn, p_ptt, addr); 1836cc875c2eSYuval Mintz 1837cc875c2eSYuval Mintz switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >> 1838cc875c2eSYuval Mintz NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) { 1839351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G: 1840cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G; 1841cc875c2eSYuval Mintz break; 1842351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G: 1843cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G; 1844cc875c2eSYuval Mintz break; 1845351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G: 1846cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G; 1847cc875c2eSYuval Mintz break; 1848351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F: 1849cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F; 1850cc875c2eSYuval Mintz break; 1851351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E: 1852cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E; 1853cc875c2eSYuval Mintz break; 1854351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G: 1855cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G; 1856cc875c2eSYuval Mintz break; 1857351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G: 1858cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G; 1859cc875c2eSYuval Mintz break; 1860351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G: 1861cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G; 1862cc875c2eSYuval Mintz break; 1863351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G: 1864cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G; 1865cc875c2eSYuval Mintz break; 1866cc875c2eSYuval Mintz default: 18671a635e48SYuval Mintz DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg); 1868cc875c2eSYuval Mintz break; 1869cc875c2eSYuval Mintz } 1870cc875c2eSYuval Mintz 1871cc875c2eSYuval Mintz /* Read default link configuration */ 1872cc875c2eSYuval Mintz link = &p_hwfn->mcp_info->link_input; 1873cc875c2eSYuval Mintz port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1874cc875c2eSYuval Mintz offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 1875cc875c2eSYuval Mintz link_temp = qed_rd(p_hwfn, p_ptt, 1876cc875c2eSYuval Mintz port_cfg_addr + 1877cc875c2eSYuval Mintz offsetof(struct nvm_cfg1_port, speed_cap_mask)); 187883aeb933SYuval Mintz link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK; 187983aeb933SYuval Mintz link->speed.advertised_speeds = link_temp; 1880cc875c2eSYuval Mintz 188183aeb933SYuval Mintz link_temp = link->speed.advertised_speeds; 188283aeb933SYuval Mintz p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp; 1883cc875c2eSYuval Mintz 1884cc875c2eSYuval Mintz link_temp = qed_rd(p_hwfn, p_ptt, 1885cc875c2eSYuval Mintz port_cfg_addr + 1886cc875c2eSYuval Mintz offsetof(struct nvm_cfg1_port, link_settings)); 1887cc875c2eSYuval Mintz switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >> 1888cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) { 1889cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG: 1890cc875c2eSYuval Mintz link->speed.autoneg = true; 1891cc875c2eSYuval Mintz break; 1892cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_1G: 1893cc875c2eSYuval Mintz link->speed.forced_speed = 1000; 1894cc875c2eSYuval Mintz break; 1895cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_10G: 1896cc875c2eSYuval Mintz link->speed.forced_speed = 10000; 1897cc875c2eSYuval Mintz break; 1898cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_25G: 1899cc875c2eSYuval Mintz link->speed.forced_speed = 25000; 1900cc875c2eSYuval Mintz break; 1901cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_40G: 1902cc875c2eSYuval Mintz link->speed.forced_speed = 40000; 1903cc875c2eSYuval Mintz break; 1904cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_50G: 1905cc875c2eSYuval Mintz link->speed.forced_speed = 50000; 1906cc875c2eSYuval Mintz break; 1907351a4dedSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G: 1908cc875c2eSYuval Mintz link->speed.forced_speed = 100000; 1909cc875c2eSYuval Mintz break; 1910cc875c2eSYuval Mintz default: 19111a635e48SYuval Mintz DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp); 1912cc875c2eSYuval Mintz } 1913cc875c2eSYuval Mintz 1914cc875c2eSYuval Mintz link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK; 1915cc875c2eSYuval Mintz link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET; 1916cc875c2eSYuval Mintz link->pause.autoneg = !!(link_temp & 1917cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG); 1918cc875c2eSYuval Mintz link->pause.forced_rx = !!(link_temp & 1919cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX); 1920cc875c2eSYuval Mintz link->pause.forced_tx = !!(link_temp & 1921cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX); 1922cc875c2eSYuval Mintz link->loopback_mode = 0; 1923cc875c2eSYuval Mintz 1924cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1925cc875c2eSYuval Mintz "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n", 1926cc875c2eSYuval Mintz link->speed.forced_speed, link->speed.advertised_speeds, 1927cc875c2eSYuval Mintz link->speed.autoneg, link->pause.autoneg); 1928cc875c2eSYuval Mintz 1929fe56b9e6SYuval Mintz /* Read Multi-function information from shmem */ 1930fe56b9e6SYuval Mintz addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1931fe56b9e6SYuval Mintz offsetof(struct nvm_cfg1, glob) + 1932fe56b9e6SYuval Mintz offsetof(struct nvm_cfg1_glob, generic_cont0); 1933fe56b9e6SYuval Mintz 1934fe56b9e6SYuval Mintz generic_cont0 = qed_rd(p_hwfn, p_ptt, addr); 1935fe56b9e6SYuval Mintz 1936fe56b9e6SYuval Mintz mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >> 1937fe56b9e6SYuval Mintz NVM_CFG1_GLOB_MF_MODE_OFFSET; 1938fe56b9e6SYuval Mintz 1939fe56b9e6SYuval Mintz switch (mf_mode) { 1940fe56b9e6SYuval Mintz case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED: 1941fc48b7a6SYuval Mintz p_hwfn->cdev->mf_mode = QED_MF_OVLAN; 1942fe56b9e6SYuval Mintz break; 1943fe56b9e6SYuval Mintz case NVM_CFG1_GLOB_MF_MODE_NPAR1_0: 1944fc48b7a6SYuval Mintz p_hwfn->cdev->mf_mode = QED_MF_NPAR; 1945fe56b9e6SYuval Mintz break; 1946fc48b7a6SYuval Mintz case NVM_CFG1_GLOB_MF_MODE_DEFAULT: 1947fc48b7a6SYuval Mintz p_hwfn->cdev->mf_mode = QED_MF_DEFAULT; 1948fe56b9e6SYuval Mintz break; 1949fe56b9e6SYuval Mintz } 1950fe56b9e6SYuval Mintz DP_INFO(p_hwfn, "Multi function mode is %08x\n", 1951fe56b9e6SYuval Mintz p_hwfn->cdev->mf_mode); 1952fe56b9e6SYuval Mintz 1953fc48b7a6SYuval Mintz /* Read Multi-function information from shmem */ 1954fc48b7a6SYuval Mintz addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1955fc48b7a6SYuval Mintz offsetof(struct nvm_cfg1, glob) + 1956fc48b7a6SYuval Mintz offsetof(struct nvm_cfg1_glob, device_capabilities); 1957fc48b7a6SYuval Mintz 1958fc48b7a6SYuval Mintz device_capabilities = qed_rd(p_hwfn, p_ptt, addr); 1959fc48b7a6SYuval Mintz if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET) 1960fc48b7a6SYuval Mintz __set_bit(QED_DEV_CAP_ETH, 1961fc48b7a6SYuval Mintz &p_hwfn->hw_info.device_capabilities); 19621e128c81SArun Easi if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE) 19631e128c81SArun Easi __set_bit(QED_DEV_CAP_FCOE, 19641e128c81SArun Easi &p_hwfn->hw_info.device_capabilities); 1965c5ac9319SYuval Mintz if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI) 1966c5ac9319SYuval Mintz __set_bit(QED_DEV_CAP_ISCSI, 1967c5ac9319SYuval Mintz &p_hwfn->hw_info.device_capabilities); 1968c5ac9319SYuval Mintz if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE) 1969c5ac9319SYuval Mintz __set_bit(QED_DEV_CAP_ROCE, 1970c5ac9319SYuval Mintz &p_hwfn->hw_info.device_capabilities); 1971fc48b7a6SYuval Mintz 1972fe56b9e6SYuval Mintz return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt); 1973fe56b9e6SYuval Mintz } 1974fe56b9e6SYuval Mintz 19751408cc1fSYuval Mintz static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 19761408cc1fSYuval Mintz { 1977dbb799c3SYuval Mintz u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id; 1978dbb799c3SYuval Mintz u32 reg_function_hide, tmp, eng_mask, low_pfs_mask; 19791408cc1fSYuval Mintz 19801408cc1fSYuval Mintz num_funcs = MAX_NUM_PFS_BB; 19811408cc1fSYuval Mintz 19821408cc1fSYuval Mintz /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values 19831408cc1fSYuval Mintz * in the other bits are selected. 19841408cc1fSYuval Mintz * Bits 1-15 are for functions 1-15, respectively, and their value is 19851408cc1fSYuval Mintz * '0' only for enabled functions (function 0 always exists and 19861408cc1fSYuval Mintz * enabled). 19871408cc1fSYuval Mintz * In case of CMT, only the "even" functions are enabled, and thus the 19881408cc1fSYuval Mintz * number of functions for both hwfns is learnt from the same bits. 19891408cc1fSYuval Mintz */ 19901408cc1fSYuval Mintz reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE); 19911408cc1fSYuval Mintz 19921408cc1fSYuval Mintz if (reg_function_hide & 0x1) { 19931408cc1fSYuval Mintz if (QED_PATH_ID(p_hwfn) && p_hwfn->cdev->num_hwfns == 1) { 19941408cc1fSYuval Mintz num_funcs = 0; 19951408cc1fSYuval Mintz eng_mask = 0xaaaa; 19961408cc1fSYuval Mintz } else { 19971408cc1fSYuval Mintz num_funcs = 1; 19981408cc1fSYuval Mintz eng_mask = 0x5554; 19991408cc1fSYuval Mintz } 20001408cc1fSYuval Mintz 20011408cc1fSYuval Mintz /* Get the number of the enabled functions on the engine */ 20021408cc1fSYuval Mintz tmp = (reg_function_hide ^ 0xffffffff) & eng_mask; 20031408cc1fSYuval Mintz while (tmp) { 20041408cc1fSYuval Mintz if (tmp & 0x1) 20051408cc1fSYuval Mintz num_funcs++; 20061408cc1fSYuval Mintz tmp >>= 0x1; 20071408cc1fSYuval Mintz } 2008dbb799c3SYuval Mintz 2009dbb799c3SYuval Mintz /* Get the PF index within the enabled functions */ 2010dbb799c3SYuval Mintz low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1; 2011dbb799c3SYuval Mintz tmp = reg_function_hide & eng_mask & low_pfs_mask; 2012dbb799c3SYuval Mintz while (tmp) { 2013dbb799c3SYuval Mintz if (tmp & 0x1) 2014dbb799c3SYuval Mintz enabled_func_idx--; 2015dbb799c3SYuval Mintz tmp >>= 0x1; 2016dbb799c3SYuval Mintz } 20171408cc1fSYuval Mintz } 20181408cc1fSYuval Mintz 20191408cc1fSYuval Mintz p_hwfn->num_funcs_on_engine = num_funcs; 2020dbb799c3SYuval Mintz p_hwfn->enabled_func_idx = enabled_func_idx; 20211408cc1fSYuval Mintz 20221408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, 20231408cc1fSYuval Mintz NETIF_MSG_PROBE, 2024525ef5c0SYuval Mintz "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n", 20251408cc1fSYuval Mintz p_hwfn->rel_pf_id, 20261408cc1fSYuval Mintz p_hwfn->abs_pf_id, 2027525ef5c0SYuval Mintz p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine); 20281408cc1fSYuval Mintz } 20291408cc1fSYuval Mintz 2030fe56b9e6SYuval Mintz static int 2031fe56b9e6SYuval Mintz qed_get_hw_info(struct qed_hwfn *p_hwfn, 2032fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 2033fe56b9e6SYuval Mintz enum qed_pci_personality personality) 2034fe56b9e6SYuval Mintz { 2035fe56b9e6SYuval Mintz u32 port_mode; 2036fe56b9e6SYuval Mintz int rc; 2037fe56b9e6SYuval Mintz 203832a47e72SYuval Mintz /* Since all information is common, only first hwfns should do this */ 203932a47e72SYuval Mintz if (IS_LEAD_HWFN(p_hwfn)) { 204032a47e72SYuval Mintz rc = qed_iov_hw_info(p_hwfn); 204132a47e72SYuval Mintz if (rc) 204232a47e72SYuval Mintz return rc; 204332a47e72SYuval Mintz } 204432a47e72SYuval Mintz 2045fe56b9e6SYuval Mintz /* Read the port mode */ 2046fe56b9e6SYuval Mintz port_mode = qed_rd(p_hwfn, p_ptt, 2047fe56b9e6SYuval Mintz CNIG_REG_NW_PORT_MODE_BB_B0); 2048fe56b9e6SYuval Mintz 2049fe56b9e6SYuval Mintz if (port_mode < 3) { 2050fe56b9e6SYuval Mintz p_hwfn->cdev->num_ports_in_engines = 1; 2051fe56b9e6SYuval Mintz } else if (port_mode <= 5) { 2052fe56b9e6SYuval Mintz p_hwfn->cdev->num_ports_in_engines = 2; 2053fe56b9e6SYuval Mintz } else { 2054fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n", 2055fe56b9e6SYuval Mintz p_hwfn->cdev->num_ports_in_engines); 2056fe56b9e6SYuval Mintz 2057fe56b9e6SYuval Mintz /* Default num_ports_in_engines to something */ 2058fe56b9e6SYuval Mintz p_hwfn->cdev->num_ports_in_engines = 1; 2059fe56b9e6SYuval Mintz } 2060fe56b9e6SYuval Mintz 2061fe56b9e6SYuval Mintz qed_hw_get_nvm_info(p_hwfn, p_ptt); 2062fe56b9e6SYuval Mintz 2063fe56b9e6SYuval Mintz rc = qed_int_igu_read_cam(p_hwfn, p_ptt); 2064fe56b9e6SYuval Mintz if (rc) 2065fe56b9e6SYuval Mintz return rc; 2066fe56b9e6SYuval Mintz 2067fe56b9e6SYuval Mintz if (qed_mcp_is_init(p_hwfn)) 2068fe56b9e6SYuval Mintz ether_addr_copy(p_hwfn->hw_info.hw_mac_addr, 2069fe56b9e6SYuval Mintz p_hwfn->mcp_info->func_info.mac); 2070fe56b9e6SYuval Mintz else 2071fe56b9e6SYuval Mintz eth_random_addr(p_hwfn->hw_info.hw_mac_addr); 2072fe56b9e6SYuval Mintz 2073fe56b9e6SYuval Mintz if (qed_mcp_is_init(p_hwfn)) { 2074fe56b9e6SYuval Mintz if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET) 2075fe56b9e6SYuval Mintz p_hwfn->hw_info.ovlan = 2076fe56b9e6SYuval Mintz p_hwfn->mcp_info->func_info.ovlan; 2077fe56b9e6SYuval Mintz 2078fe56b9e6SYuval Mintz qed_mcp_cmd_port_init(p_hwfn, p_ptt); 2079fe56b9e6SYuval Mintz } 2080fe56b9e6SYuval Mintz 2081fe56b9e6SYuval Mintz if (qed_mcp_is_init(p_hwfn)) { 2082fe56b9e6SYuval Mintz enum qed_pci_personality protocol; 2083fe56b9e6SYuval Mintz 2084fe56b9e6SYuval Mintz protocol = p_hwfn->mcp_info->func_info.protocol; 2085fe56b9e6SYuval Mintz p_hwfn->hw_info.personality = protocol; 2086fe56b9e6SYuval Mintz } 2087fe56b9e6SYuval Mintz 20881408cc1fSYuval Mintz qed_get_num_funcs(p_hwfn, p_ptt); 20891408cc1fSYuval Mintz 20900fefbfbaSSudarsana Kalluru if (qed_mcp_is_init(p_hwfn)) 20910fefbfbaSSudarsana Kalluru p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu; 20920fefbfbaSSudarsana Kalluru 2093dbb799c3SYuval Mintz return qed_hw_get_resc(p_hwfn); 2094fe56b9e6SYuval Mintz } 2095fe56b9e6SYuval Mintz 209612e09c69SYuval Mintz static int qed_get_dev_info(struct qed_dev *cdev) 2097fe56b9e6SYuval Mintz { 2098fc48b7a6SYuval Mintz struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2099fe56b9e6SYuval Mintz u32 tmp; 2100fe56b9e6SYuval Mintz 2101fc48b7a6SYuval Mintz /* Read Vendor Id / Device Id */ 21021a635e48SYuval Mintz pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id); 21031a635e48SYuval Mintz pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id); 21041a635e48SYuval Mintz 2105fc48b7a6SYuval Mintz cdev->chip_num = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, 2106fe56b9e6SYuval Mintz MISCS_REG_CHIP_NUM); 2107fc48b7a6SYuval Mintz cdev->chip_rev = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, 2108fe56b9e6SYuval Mintz MISCS_REG_CHIP_REV); 2109fe56b9e6SYuval Mintz MASK_FIELD(CHIP_REV, cdev->chip_rev); 2110fe56b9e6SYuval Mintz 2111fc48b7a6SYuval Mintz cdev->type = QED_DEV_TYPE_BB; 2112fe56b9e6SYuval Mintz /* Learn number of HW-functions */ 2113fc48b7a6SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_main_ptt, 2114fe56b9e6SYuval Mintz MISCS_REG_CMT_ENABLED_FOR_PAIR); 2115fe56b9e6SYuval Mintz 2116fc48b7a6SYuval Mintz if (tmp & (1 << p_hwfn->rel_pf_id)) { 2117fe56b9e6SYuval Mintz DP_NOTICE(cdev->hwfns, "device in CMT mode\n"); 2118fe56b9e6SYuval Mintz cdev->num_hwfns = 2; 2119fe56b9e6SYuval Mintz } else { 2120fe56b9e6SYuval Mintz cdev->num_hwfns = 1; 2121fe56b9e6SYuval Mintz } 2122fe56b9e6SYuval Mintz 2123fc48b7a6SYuval Mintz cdev->chip_bond_id = qed_rd(p_hwfn, p_hwfn->p_main_ptt, 2124fe56b9e6SYuval Mintz MISCS_REG_CHIP_TEST_REG) >> 4; 2125fe56b9e6SYuval Mintz MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id); 2126fc48b7a6SYuval Mintz cdev->chip_metal = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, 2127fe56b9e6SYuval Mintz MISCS_REG_CHIP_METAL); 2128fe56b9e6SYuval Mintz MASK_FIELD(CHIP_METAL, cdev->chip_metal); 2129fe56b9e6SYuval Mintz 2130fe56b9e6SYuval Mintz DP_INFO(cdev->hwfns, 2131fe56b9e6SYuval Mintz "Chip details - Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n", 2132fe56b9e6SYuval Mintz cdev->chip_num, cdev->chip_rev, 2133fe56b9e6SYuval Mintz cdev->chip_bond_id, cdev->chip_metal); 213412e09c69SYuval Mintz 213512e09c69SYuval Mintz if (QED_IS_BB(cdev) && CHIP_REV_IS_A0(cdev)) { 213612e09c69SYuval Mintz DP_NOTICE(cdev->hwfns, 213712e09c69SYuval Mintz "The chip type/rev (BB A0) is not supported!\n"); 213812e09c69SYuval Mintz return -EINVAL; 213912e09c69SYuval Mintz } 214012e09c69SYuval Mintz 214112e09c69SYuval Mintz return 0; 2142fe56b9e6SYuval Mintz } 2143fe56b9e6SYuval Mintz 2144fe56b9e6SYuval Mintz static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn, 2145fe56b9e6SYuval Mintz void __iomem *p_regview, 2146fe56b9e6SYuval Mintz void __iomem *p_doorbells, 2147fe56b9e6SYuval Mintz enum qed_pci_personality personality) 2148fe56b9e6SYuval Mintz { 2149fe56b9e6SYuval Mintz int rc = 0; 2150fe56b9e6SYuval Mintz 2151fe56b9e6SYuval Mintz /* Split PCI bars evenly between hwfns */ 2152fe56b9e6SYuval Mintz p_hwfn->regview = p_regview; 2153fe56b9e6SYuval Mintz p_hwfn->doorbells = p_doorbells; 2154fe56b9e6SYuval Mintz 21551408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 21561408cc1fSYuval Mintz return qed_vf_hw_prepare(p_hwfn); 21571408cc1fSYuval Mintz 2158fe56b9e6SYuval Mintz /* Validate that chip access is feasible */ 2159fe56b9e6SYuval Mintz if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) { 2160fe56b9e6SYuval Mintz DP_ERR(p_hwfn, 2161fe56b9e6SYuval Mintz "Reading the ME register returns all Fs; Preventing further chip access\n"); 2162fe56b9e6SYuval Mintz return -EINVAL; 2163fe56b9e6SYuval Mintz } 2164fe56b9e6SYuval Mintz 2165fe56b9e6SYuval Mintz get_function_id(p_hwfn); 2166fe56b9e6SYuval Mintz 216712e09c69SYuval Mintz /* Allocate PTT pool */ 216812e09c69SYuval Mintz rc = qed_ptt_pool_alloc(p_hwfn); 21692591c280SJoe Perches if (rc) 2170fe56b9e6SYuval Mintz goto err0; 2171fe56b9e6SYuval Mintz 217212e09c69SYuval Mintz /* Allocate the main PTT */ 217312e09c69SYuval Mintz p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN); 217412e09c69SYuval Mintz 2175fe56b9e6SYuval Mintz /* First hwfn learns basic information, e.g., number of hwfns */ 217612e09c69SYuval Mintz if (!p_hwfn->my_id) { 217712e09c69SYuval Mintz rc = qed_get_dev_info(p_hwfn->cdev); 21781a635e48SYuval Mintz if (rc) 217912e09c69SYuval Mintz goto err1; 218012e09c69SYuval Mintz } 218112e09c69SYuval Mintz 218212e09c69SYuval Mintz qed_hw_hwfn_prepare(p_hwfn); 2183fe56b9e6SYuval Mintz 2184fe56b9e6SYuval Mintz /* Initialize MCP structure */ 2185fe56b9e6SYuval Mintz rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt); 2186fe56b9e6SYuval Mintz if (rc) { 2187fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed initializing mcp command\n"); 2188fe56b9e6SYuval Mintz goto err1; 2189fe56b9e6SYuval Mintz } 2190fe56b9e6SYuval Mintz 2191fe56b9e6SYuval Mintz /* Read the device configuration information from the HW and SHMEM */ 2192fe56b9e6SYuval Mintz rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality); 2193fe56b9e6SYuval Mintz if (rc) { 2194fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed to get HW information\n"); 2195fe56b9e6SYuval Mintz goto err2; 2196fe56b9e6SYuval Mintz } 2197fe56b9e6SYuval Mintz 2198fe56b9e6SYuval Mintz /* Allocate the init RT array and initialize the init-ops engine */ 2199fe56b9e6SYuval Mintz rc = qed_init_alloc(p_hwfn); 22002591c280SJoe Perches if (rc) 2201fe56b9e6SYuval Mintz goto err2; 2202fe56b9e6SYuval Mintz 2203fe56b9e6SYuval Mintz return rc; 2204fe56b9e6SYuval Mintz err2: 220532a47e72SYuval Mintz if (IS_LEAD_HWFN(p_hwfn)) 220632a47e72SYuval Mintz qed_iov_free_hw_info(p_hwfn->cdev); 2207fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 2208fe56b9e6SYuval Mintz err1: 2209fe56b9e6SYuval Mintz qed_hw_hwfn_free(p_hwfn); 2210fe56b9e6SYuval Mintz err0: 2211fe56b9e6SYuval Mintz return rc; 2212fe56b9e6SYuval Mintz } 2213fe56b9e6SYuval Mintz 2214fe56b9e6SYuval Mintz int qed_hw_prepare(struct qed_dev *cdev, 2215fe56b9e6SYuval Mintz int personality) 2216fe56b9e6SYuval Mintz { 2217c78df14eSAriel Elior struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2218c78df14eSAriel Elior int rc; 2219fe56b9e6SYuval Mintz 2220fe56b9e6SYuval Mintz /* Store the precompiled init data ptrs */ 22211408cc1fSYuval Mintz if (IS_PF(cdev)) 2222fe56b9e6SYuval Mintz qed_init_iro_array(cdev); 2223fe56b9e6SYuval Mintz 2224fe56b9e6SYuval Mintz /* Initialize the first hwfn - will learn number of hwfns */ 2225c78df14eSAriel Elior rc = qed_hw_prepare_single(p_hwfn, 2226c78df14eSAriel Elior cdev->regview, 2227fe56b9e6SYuval Mintz cdev->doorbells, personality); 2228fe56b9e6SYuval Mintz if (rc) 2229fe56b9e6SYuval Mintz return rc; 2230fe56b9e6SYuval Mintz 2231c78df14eSAriel Elior personality = p_hwfn->hw_info.personality; 2232fe56b9e6SYuval Mintz 2233fe56b9e6SYuval Mintz /* Initialize the rest of the hwfns */ 2234c78df14eSAriel Elior if (cdev->num_hwfns > 1) { 2235fe56b9e6SYuval Mintz void __iomem *p_regview, *p_doorbell; 2236c78df14eSAriel Elior u8 __iomem *addr; 2237fe56b9e6SYuval Mintz 2238c78df14eSAriel Elior /* adjust bar offset for second engine */ 2239c2035eeaSRam Amrani addr = cdev->regview + qed_hw_bar_size(p_hwfn, BAR_ID_0) / 2; 2240c78df14eSAriel Elior p_regview = addr; 2241c78df14eSAriel Elior 2242c78df14eSAriel Elior /* adjust doorbell bar offset for second engine */ 2243c2035eeaSRam Amrani addr = cdev->doorbells + qed_hw_bar_size(p_hwfn, BAR_ID_1) / 2; 2244c78df14eSAriel Elior p_doorbell = addr; 2245c78df14eSAriel Elior 2246c78df14eSAriel Elior /* prepare second hw function */ 2247c78df14eSAriel Elior rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview, 2248fe56b9e6SYuval Mintz p_doorbell, personality); 2249c78df14eSAriel Elior 2250c78df14eSAriel Elior /* in case of error, need to free the previously 2251c78df14eSAriel Elior * initiliazed hwfn 0. 2252c78df14eSAriel Elior */ 2253fe56b9e6SYuval Mintz if (rc) { 22541408cc1fSYuval Mintz if (IS_PF(cdev)) { 2255c78df14eSAriel Elior qed_init_free(p_hwfn); 2256c78df14eSAriel Elior qed_mcp_free(p_hwfn); 2257c78df14eSAriel Elior qed_hw_hwfn_free(p_hwfn); 2258fe56b9e6SYuval Mintz } 2259fe56b9e6SYuval Mintz } 22601408cc1fSYuval Mintz } 2261fe56b9e6SYuval Mintz 2262c78df14eSAriel Elior return rc; 2263fe56b9e6SYuval Mintz } 2264fe56b9e6SYuval Mintz 2265fe56b9e6SYuval Mintz void qed_hw_remove(struct qed_dev *cdev) 2266fe56b9e6SYuval Mintz { 22670fefbfbaSSudarsana Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2268fe56b9e6SYuval Mintz int i; 2269fe56b9e6SYuval Mintz 22700fefbfbaSSudarsana Kalluru if (IS_PF(cdev)) 22710fefbfbaSSudarsana Kalluru qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt, 22720fefbfbaSSudarsana Kalluru QED_OV_DRIVER_STATE_NOT_LOADED); 22730fefbfbaSSudarsana Kalluru 2274fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 2275fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2276fe56b9e6SYuval Mintz 22771408cc1fSYuval Mintz if (IS_VF(cdev)) { 22780b55e27dSYuval Mintz qed_vf_pf_release(p_hwfn); 22791408cc1fSYuval Mintz continue; 22801408cc1fSYuval Mintz } 22811408cc1fSYuval Mintz 2282fe56b9e6SYuval Mintz qed_init_free(p_hwfn); 2283fe56b9e6SYuval Mintz qed_hw_hwfn_free(p_hwfn); 2284fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 2285fe56b9e6SYuval Mintz } 228632a47e72SYuval Mintz 228732a47e72SYuval Mintz qed_iov_free_hw_info(cdev); 2288fe56b9e6SYuval Mintz } 2289fe56b9e6SYuval Mintz 2290a91eb52aSYuval Mintz static void qed_chain_free_next_ptr(struct qed_dev *cdev, 2291a91eb52aSYuval Mintz struct qed_chain *p_chain) 2292a91eb52aSYuval Mintz { 2293a91eb52aSYuval Mintz void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL; 2294a91eb52aSYuval Mintz dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0; 2295a91eb52aSYuval Mintz struct qed_chain_next *p_next; 2296a91eb52aSYuval Mintz u32 size, i; 2297a91eb52aSYuval Mintz 2298a91eb52aSYuval Mintz if (!p_virt) 2299a91eb52aSYuval Mintz return; 2300a91eb52aSYuval Mintz 2301a91eb52aSYuval Mintz size = p_chain->elem_size * p_chain->usable_per_page; 2302a91eb52aSYuval Mintz 2303a91eb52aSYuval Mintz for (i = 0; i < p_chain->page_cnt; i++) { 2304a91eb52aSYuval Mintz if (!p_virt) 2305a91eb52aSYuval Mintz break; 2306a91eb52aSYuval Mintz 2307a91eb52aSYuval Mintz p_next = (struct qed_chain_next *)((u8 *)p_virt + size); 2308a91eb52aSYuval Mintz p_virt_next = p_next->next_virt; 2309a91eb52aSYuval Mintz p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys); 2310a91eb52aSYuval Mintz 2311a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 2312a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, p_virt, p_phys); 2313a91eb52aSYuval Mintz 2314a91eb52aSYuval Mintz p_virt = p_virt_next; 2315a91eb52aSYuval Mintz p_phys = p_phys_next; 2316a91eb52aSYuval Mintz } 2317a91eb52aSYuval Mintz } 2318a91eb52aSYuval Mintz 2319a91eb52aSYuval Mintz static void qed_chain_free_single(struct qed_dev *cdev, 2320a91eb52aSYuval Mintz struct qed_chain *p_chain) 2321a91eb52aSYuval Mintz { 2322a91eb52aSYuval Mintz if (!p_chain->p_virt_addr) 2323a91eb52aSYuval Mintz return; 2324a91eb52aSYuval Mintz 2325a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 2326a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 2327a91eb52aSYuval Mintz p_chain->p_virt_addr, p_chain->p_phys_addr); 2328a91eb52aSYuval Mintz } 2329a91eb52aSYuval Mintz 2330a91eb52aSYuval Mintz static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain) 2331a91eb52aSYuval Mintz { 2332a91eb52aSYuval Mintz void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl; 2333a91eb52aSYuval Mintz u32 page_cnt = p_chain->page_cnt, i, pbl_size; 23346d937acfSMintz, Yuval u8 *p_pbl_virt = p_chain->pbl_sp.p_virt_table; 2335a91eb52aSYuval Mintz 2336a91eb52aSYuval Mintz if (!pp_virt_addr_tbl) 2337a91eb52aSYuval Mintz return; 2338a91eb52aSYuval Mintz 23396d937acfSMintz, Yuval if (!p_pbl_virt) 2340a91eb52aSYuval Mintz goto out; 2341a91eb52aSYuval Mintz 2342a91eb52aSYuval Mintz for (i = 0; i < page_cnt; i++) { 2343a91eb52aSYuval Mintz if (!pp_virt_addr_tbl[i]) 2344a91eb52aSYuval Mintz break; 2345a91eb52aSYuval Mintz 2346a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 2347a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 2348a91eb52aSYuval Mintz pp_virt_addr_tbl[i], 2349a91eb52aSYuval Mintz *(dma_addr_t *)p_pbl_virt); 2350a91eb52aSYuval Mintz 2351a91eb52aSYuval Mintz p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE; 2352a91eb52aSYuval Mintz } 2353a91eb52aSYuval Mintz 2354a91eb52aSYuval Mintz pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; 2355a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 2356a91eb52aSYuval Mintz pbl_size, 23576d937acfSMintz, Yuval p_chain->pbl_sp.p_virt_table, 23586d937acfSMintz, Yuval p_chain->pbl_sp.p_phys_table); 2359a91eb52aSYuval Mintz out: 2360a91eb52aSYuval Mintz vfree(p_chain->pbl.pp_virt_addr_tbl); 2361a91eb52aSYuval Mintz } 2362a91eb52aSYuval Mintz 2363a91eb52aSYuval Mintz void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain) 2364a91eb52aSYuval Mintz { 2365a91eb52aSYuval Mintz switch (p_chain->mode) { 2366a91eb52aSYuval Mintz case QED_CHAIN_MODE_NEXT_PTR: 2367a91eb52aSYuval Mintz qed_chain_free_next_ptr(cdev, p_chain); 2368a91eb52aSYuval Mintz break; 2369a91eb52aSYuval Mintz case QED_CHAIN_MODE_SINGLE: 2370a91eb52aSYuval Mintz qed_chain_free_single(cdev, p_chain); 2371a91eb52aSYuval Mintz break; 2372a91eb52aSYuval Mintz case QED_CHAIN_MODE_PBL: 2373a91eb52aSYuval Mintz qed_chain_free_pbl(cdev, p_chain); 2374a91eb52aSYuval Mintz break; 2375a91eb52aSYuval Mintz } 2376a91eb52aSYuval Mintz } 2377a91eb52aSYuval Mintz 2378a91eb52aSYuval Mintz static int 2379a91eb52aSYuval Mintz qed_chain_alloc_sanity_check(struct qed_dev *cdev, 2380a91eb52aSYuval Mintz enum qed_chain_cnt_type cnt_type, 2381a91eb52aSYuval Mintz size_t elem_size, u32 page_cnt) 2382a91eb52aSYuval Mintz { 2383a91eb52aSYuval Mintz u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt; 2384a91eb52aSYuval Mintz 2385a91eb52aSYuval Mintz /* The actual chain size can be larger than the maximal possible value 2386a91eb52aSYuval Mintz * after rounding up the requested elements number to pages, and after 2387a91eb52aSYuval Mintz * taking into acount the unusuable elements (next-ptr elements). 2388a91eb52aSYuval Mintz * The size of a "u16" chain can be (U16_MAX + 1) since the chain 2389a91eb52aSYuval Mintz * size/capacity fields are of a u32 type. 2390a91eb52aSYuval Mintz */ 2391a91eb52aSYuval Mintz if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 && 2392a91eb52aSYuval Mintz chain_size > 0x10000) || 2393a91eb52aSYuval Mintz (cnt_type == QED_CHAIN_CNT_TYPE_U32 && 2394a91eb52aSYuval Mintz chain_size > 0x100000000ULL)) { 2395a91eb52aSYuval Mintz DP_NOTICE(cdev, 2396a91eb52aSYuval Mintz "The actual chain size (0x%llx) is larger than the maximal possible value\n", 2397a91eb52aSYuval Mintz chain_size); 2398a91eb52aSYuval Mintz return -EINVAL; 2399a91eb52aSYuval Mintz } 2400a91eb52aSYuval Mintz 2401a91eb52aSYuval Mintz return 0; 2402a91eb52aSYuval Mintz } 2403a91eb52aSYuval Mintz 2404a91eb52aSYuval Mintz static int 2405a91eb52aSYuval Mintz qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain) 2406a91eb52aSYuval Mintz { 2407a91eb52aSYuval Mintz void *p_virt = NULL, *p_virt_prev = NULL; 2408a91eb52aSYuval Mintz dma_addr_t p_phys = 0; 2409a91eb52aSYuval Mintz u32 i; 2410a91eb52aSYuval Mintz 2411a91eb52aSYuval Mintz for (i = 0; i < p_chain->page_cnt; i++) { 2412a91eb52aSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 2413a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 2414a91eb52aSYuval Mintz &p_phys, GFP_KERNEL); 24152591c280SJoe Perches if (!p_virt) 2416a91eb52aSYuval Mintz return -ENOMEM; 2417a91eb52aSYuval Mintz 2418a91eb52aSYuval Mintz if (i == 0) { 2419a91eb52aSYuval Mintz qed_chain_init_mem(p_chain, p_virt, p_phys); 2420a91eb52aSYuval Mintz qed_chain_reset(p_chain); 2421a91eb52aSYuval Mintz } else { 2422a91eb52aSYuval Mintz qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, 2423a91eb52aSYuval Mintz p_virt, p_phys); 2424a91eb52aSYuval Mintz } 2425a91eb52aSYuval Mintz 2426a91eb52aSYuval Mintz p_virt_prev = p_virt; 2427a91eb52aSYuval Mintz } 2428a91eb52aSYuval Mintz /* Last page's next element should point to the beginning of the 2429a91eb52aSYuval Mintz * chain. 2430a91eb52aSYuval Mintz */ 2431a91eb52aSYuval Mintz qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, 2432a91eb52aSYuval Mintz p_chain->p_virt_addr, 2433a91eb52aSYuval Mintz p_chain->p_phys_addr); 2434a91eb52aSYuval Mintz 2435a91eb52aSYuval Mintz return 0; 2436a91eb52aSYuval Mintz } 2437a91eb52aSYuval Mintz 2438a91eb52aSYuval Mintz static int 2439a91eb52aSYuval Mintz qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain) 2440a91eb52aSYuval Mintz { 2441a91eb52aSYuval Mintz dma_addr_t p_phys = 0; 2442a91eb52aSYuval Mintz void *p_virt = NULL; 2443a91eb52aSYuval Mintz 2444a91eb52aSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 2445a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL); 24462591c280SJoe Perches if (!p_virt) 2447a91eb52aSYuval Mintz return -ENOMEM; 2448a91eb52aSYuval Mintz 2449a91eb52aSYuval Mintz qed_chain_init_mem(p_chain, p_virt, p_phys); 2450a91eb52aSYuval Mintz qed_chain_reset(p_chain); 2451a91eb52aSYuval Mintz 2452a91eb52aSYuval Mintz return 0; 2453a91eb52aSYuval Mintz } 2454a91eb52aSYuval Mintz 2455a91eb52aSYuval Mintz static int qed_chain_alloc_pbl(struct qed_dev *cdev, struct qed_chain *p_chain) 2456a91eb52aSYuval Mintz { 2457a91eb52aSYuval Mintz u32 page_cnt = p_chain->page_cnt, size, i; 2458a91eb52aSYuval Mintz dma_addr_t p_phys = 0, p_pbl_phys = 0; 2459a91eb52aSYuval Mintz void **pp_virt_addr_tbl = NULL; 2460a91eb52aSYuval Mintz u8 *p_pbl_virt = NULL; 2461a91eb52aSYuval Mintz void *p_virt = NULL; 2462a91eb52aSYuval Mintz 2463a91eb52aSYuval Mintz size = page_cnt * sizeof(*pp_virt_addr_tbl); 24642591c280SJoe Perches pp_virt_addr_tbl = vzalloc(size); 24652591c280SJoe Perches if (!pp_virt_addr_tbl) 2466a91eb52aSYuval Mintz return -ENOMEM; 2467a91eb52aSYuval Mintz 2468a91eb52aSYuval Mintz /* The allocation of the PBL table is done with its full size, since it 2469a91eb52aSYuval Mintz * is expected to be successive. 2470a91eb52aSYuval Mintz * qed_chain_init_pbl_mem() is called even in a case of an allocation 2471a91eb52aSYuval Mintz * failure, since pp_virt_addr_tbl was previously allocated, and it 2472a91eb52aSYuval Mintz * should be saved to allow its freeing during the error flow. 2473a91eb52aSYuval Mintz */ 2474a91eb52aSYuval Mintz size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; 2475a91eb52aSYuval Mintz p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev, 2476a91eb52aSYuval Mintz size, &p_pbl_phys, GFP_KERNEL); 2477a91eb52aSYuval Mintz qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys, 2478a91eb52aSYuval Mintz pp_virt_addr_tbl); 24792591c280SJoe Perches if (!p_pbl_virt) 2480a91eb52aSYuval Mintz return -ENOMEM; 2481a91eb52aSYuval Mintz 2482a91eb52aSYuval Mintz for (i = 0; i < page_cnt; i++) { 2483a91eb52aSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 2484a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 2485a91eb52aSYuval Mintz &p_phys, GFP_KERNEL); 24862591c280SJoe Perches if (!p_virt) 2487a91eb52aSYuval Mintz return -ENOMEM; 2488a91eb52aSYuval Mintz 2489a91eb52aSYuval Mintz if (i == 0) { 2490a91eb52aSYuval Mintz qed_chain_init_mem(p_chain, p_virt, p_phys); 2491a91eb52aSYuval Mintz qed_chain_reset(p_chain); 2492a91eb52aSYuval Mintz } 2493a91eb52aSYuval Mintz 2494a91eb52aSYuval Mintz /* Fill the PBL table with the physical address of the page */ 2495a91eb52aSYuval Mintz *(dma_addr_t *)p_pbl_virt = p_phys; 2496a91eb52aSYuval Mintz /* Keep the virtual address of the page */ 2497a91eb52aSYuval Mintz p_chain->pbl.pp_virt_addr_tbl[i] = p_virt; 2498a91eb52aSYuval Mintz 2499a91eb52aSYuval Mintz p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE; 2500a91eb52aSYuval Mintz } 2501a91eb52aSYuval Mintz 2502a91eb52aSYuval Mintz return 0; 2503a91eb52aSYuval Mintz } 2504a91eb52aSYuval Mintz 2505fe56b9e6SYuval Mintz int qed_chain_alloc(struct qed_dev *cdev, 2506fe56b9e6SYuval Mintz enum qed_chain_use_mode intended_use, 2507fe56b9e6SYuval Mintz enum qed_chain_mode mode, 2508a91eb52aSYuval Mintz enum qed_chain_cnt_type cnt_type, 2509a91eb52aSYuval Mintz u32 num_elems, size_t elem_size, struct qed_chain *p_chain) 2510fe56b9e6SYuval Mintz { 2511a91eb52aSYuval Mintz u32 page_cnt; 2512a91eb52aSYuval Mintz int rc = 0; 2513fe56b9e6SYuval Mintz 2514fe56b9e6SYuval Mintz if (mode == QED_CHAIN_MODE_SINGLE) 2515fe56b9e6SYuval Mintz page_cnt = 1; 2516fe56b9e6SYuval Mintz else 2517fe56b9e6SYuval Mintz page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode); 2518fe56b9e6SYuval Mintz 2519a91eb52aSYuval Mintz rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt); 2520a91eb52aSYuval Mintz if (rc) { 2521a91eb52aSYuval Mintz DP_NOTICE(cdev, 25222591c280SJoe Perches "Cannot allocate a chain with the given arguments:\n"); 25232591c280SJoe Perches DP_NOTICE(cdev, 2524a91eb52aSYuval Mintz "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n", 2525a91eb52aSYuval Mintz intended_use, mode, cnt_type, num_elems, elem_size); 2526a91eb52aSYuval Mintz return rc; 2527fe56b9e6SYuval Mintz } 2528fe56b9e6SYuval Mintz 2529a91eb52aSYuval Mintz qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use, 2530a91eb52aSYuval Mintz mode, cnt_type); 2531fe56b9e6SYuval Mintz 2532a91eb52aSYuval Mintz switch (mode) { 2533a91eb52aSYuval Mintz case QED_CHAIN_MODE_NEXT_PTR: 2534a91eb52aSYuval Mintz rc = qed_chain_alloc_next_ptr(cdev, p_chain); 2535a91eb52aSYuval Mintz break; 2536a91eb52aSYuval Mintz case QED_CHAIN_MODE_SINGLE: 2537a91eb52aSYuval Mintz rc = qed_chain_alloc_single(cdev, p_chain); 2538a91eb52aSYuval Mintz break; 2539a91eb52aSYuval Mintz case QED_CHAIN_MODE_PBL: 2540a91eb52aSYuval Mintz rc = qed_chain_alloc_pbl(cdev, p_chain); 2541a91eb52aSYuval Mintz break; 2542fe56b9e6SYuval Mintz } 2543a91eb52aSYuval Mintz if (rc) 2544a91eb52aSYuval Mintz goto nomem; 2545fe56b9e6SYuval Mintz 2546fe56b9e6SYuval Mintz return 0; 2547fe56b9e6SYuval Mintz 2548fe56b9e6SYuval Mintz nomem: 2549a91eb52aSYuval Mintz qed_chain_free(cdev, p_chain); 2550a91eb52aSYuval Mintz return rc; 2551fe56b9e6SYuval Mintz } 2552fe56b9e6SYuval Mintz 2553a91eb52aSYuval Mintz int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id) 2554cee4d264SManish Chopra { 2555cee4d264SManish Chopra if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) { 2556cee4d264SManish Chopra u16 min, max; 2557cee4d264SManish Chopra 2558cee4d264SManish Chopra min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE); 2559cee4d264SManish Chopra max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE); 2560cee4d264SManish Chopra DP_NOTICE(p_hwfn, 2561cee4d264SManish Chopra "l2_queue id [%d] is not valid, available indices [%d - %d]\n", 2562cee4d264SManish Chopra src_id, min, max); 2563cee4d264SManish Chopra 2564cee4d264SManish Chopra return -EINVAL; 2565cee4d264SManish Chopra } 2566cee4d264SManish Chopra 2567cee4d264SManish Chopra *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id; 2568cee4d264SManish Chopra 2569cee4d264SManish Chopra return 0; 2570cee4d264SManish Chopra } 2571cee4d264SManish Chopra 25721a635e48SYuval Mintz int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id) 2573cee4d264SManish Chopra { 2574cee4d264SManish Chopra if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) { 2575cee4d264SManish Chopra u8 min, max; 2576cee4d264SManish Chopra 2577cee4d264SManish Chopra min = (u8)RESC_START(p_hwfn, QED_VPORT); 2578cee4d264SManish Chopra max = min + RESC_NUM(p_hwfn, QED_VPORT); 2579cee4d264SManish Chopra DP_NOTICE(p_hwfn, 2580cee4d264SManish Chopra "vport id [%d] is not valid, available indices [%d - %d]\n", 2581cee4d264SManish Chopra src_id, min, max); 2582cee4d264SManish Chopra 2583cee4d264SManish Chopra return -EINVAL; 2584cee4d264SManish Chopra } 2585cee4d264SManish Chopra 2586cee4d264SManish Chopra *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id; 2587cee4d264SManish Chopra 2588cee4d264SManish Chopra return 0; 2589cee4d264SManish Chopra } 2590cee4d264SManish Chopra 25911a635e48SYuval Mintz int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id) 2592cee4d264SManish Chopra { 2593cee4d264SManish Chopra if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) { 2594cee4d264SManish Chopra u8 min, max; 2595cee4d264SManish Chopra 2596cee4d264SManish Chopra min = (u8)RESC_START(p_hwfn, QED_RSS_ENG); 2597cee4d264SManish Chopra max = min + RESC_NUM(p_hwfn, QED_RSS_ENG); 2598cee4d264SManish Chopra DP_NOTICE(p_hwfn, 2599cee4d264SManish Chopra "rss_eng id [%d] is not valid, available indices [%d - %d]\n", 2600cee4d264SManish Chopra src_id, min, max); 2601cee4d264SManish Chopra 2602cee4d264SManish Chopra return -EINVAL; 2603cee4d264SManish Chopra } 2604cee4d264SManish Chopra 2605cee4d264SManish Chopra *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id; 2606cee4d264SManish Chopra 2607cee4d264SManish Chopra return 0; 2608cee4d264SManish Chopra } 2609bcd197c8SManish Chopra 26100a7fb11cSYuval Mintz static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low, 26110a7fb11cSYuval Mintz u8 *p_filter) 26120a7fb11cSYuval Mintz { 26130a7fb11cSYuval Mintz *p_high = p_filter[1] | (p_filter[0] << 8); 26140a7fb11cSYuval Mintz *p_low = p_filter[5] | (p_filter[4] << 8) | 26150a7fb11cSYuval Mintz (p_filter[3] << 16) | (p_filter[2] << 24); 26160a7fb11cSYuval Mintz } 26170a7fb11cSYuval Mintz 26180a7fb11cSYuval Mintz int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn, 26190a7fb11cSYuval Mintz struct qed_ptt *p_ptt, u8 *p_filter) 26200a7fb11cSYuval Mintz { 26210a7fb11cSYuval Mintz u32 high = 0, low = 0, en; 26220a7fb11cSYuval Mintz int i; 26230a7fb11cSYuval Mintz 26240a7fb11cSYuval Mintz if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 26250a7fb11cSYuval Mintz return 0; 26260a7fb11cSYuval Mintz 26270a7fb11cSYuval Mintz qed_llh_mac_to_filter(&high, &low, p_filter); 26280a7fb11cSYuval Mintz 26290a7fb11cSYuval Mintz /* Find a free entry and utilize it */ 26300a7fb11cSYuval Mintz for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 26310a7fb11cSYuval Mintz en = qed_rd(p_hwfn, p_ptt, 26320a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)); 26330a7fb11cSYuval Mintz if (en) 26340a7fb11cSYuval Mintz continue; 26350a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 26360a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 26370a7fb11cSYuval Mintz 2 * i * sizeof(u32), low); 26380a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 26390a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 26400a7fb11cSYuval Mintz (2 * i + 1) * sizeof(u32), high); 26410a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 26420a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0); 26430a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 26440a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 26450a7fb11cSYuval Mintz i * sizeof(u32), 0); 26460a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 26470a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1); 26480a7fb11cSYuval Mintz break; 26490a7fb11cSYuval Mintz } 26500a7fb11cSYuval Mintz if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) { 26510a7fb11cSYuval Mintz DP_NOTICE(p_hwfn, 26520a7fb11cSYuval Mintz "Failed to find an empty LLH filter to utilize\n"); 26530a7fb11cSYuval Mintz return -EINVAL; 26540a7fb11cSYuval Mintz } 26550a7fb11cSYuval Mintz 26560a7fb11cSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 26570a7fb11cSYuval Mintz "mac: %pM is added at %d\n", 26580a7fb11cSYuval Mintz p_filter, i); 26590a7fb11cSYuval Mintz 26600a7fb11cSYuval Mintz return 0; 26610a7fb11cSYuval Mintz } 26620a7fb11cSYuval Mintz 26630a7fb11cSYuval Mintz void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn, 26640a7fb11cSYuval Mintz struct qed_ptt *p_ptt, u8 *p_filter) 26650a7fb11cSYuval Mintz { 26660a7fb11cSYuval Mintz u32 high = 0, low = 0; 26670a7fb11cSYuval Mintz int i; 26680a7fb11cSYuval Mintz 26690a7fb11cSYuval Mintz if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 26700a7fb11cSYuval Mintz return; 26710a7fb11cSYuval Mintz 26720a7fb11cSYuval Mintz qed_llh_mac_to_filter(&high, &low, p_filter); 26730a7fb11cSYuval Mintz 26740a7fb11cSYuval Mintz /* Find the entry and clean it */ 26750a7fb11cSYuval Mintz for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 26760a7fb11cSYuval Mintz if (qed_rd(p_hwfn, p_ptt, 26770a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 26780a7fb11cSYuval Mintz 2 * i * sizeof(u32)) != low) 26790a7fb11cSYuval Mintz continue; 26800a7fb11cSYuval Mintz if (qed_rd(p_hwfn, p_ptt, 26810a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 26820a7fb11cSYuval Mintz (2 * i + 1) * sizeof(u32)) != high) 26830a7fb11cSYuval Mintz continue; 26840a7fb11cSYuval Mintz 26850a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 26860a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0); 26870a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 26880a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0); 26890a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 26900a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 26910a7fb11cSYuval Mintz (2 * i + 1) * sizeof(u32), 0); 26920a7fb11cSYuval Mintz 26930a7fb11cSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 26940a7fb11cSYuval Mintz "mac: %pM is removed from %d\n", 26950a7fb11cSYuval Mintz p_filter, i); 26960a7fb11cSYuval Mintz break; 26970a7fb11cSYuval Mintz } 26980a7fb11cSYuval Mintz if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) 26990a7fb11cSYuval Mintz DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n"); 27000a7fb11cSYuval Mintz } 27010a7fb11cSYuval Mintz 27021e128c81SArun Easi int 27031e128c81SArun Easi qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn, 27041e128c81SArun Easi struct qed_ptt *p_ptt, 27051e128c81SArun Easi u16 source_port_or_eth_type, 27061e128c81SArun Easi u16 dest_port, enum qed_llh_port_filter_type_t type) 27071e128c81SArun Easi { 27081e128c81SArun Easi u32 high = 0, low = 0, en; 27091e128c81SArun Easi int i; 27101e128c81SArun Easi 27111e128c81SArun Easi if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 27121e128c81SArun Easi return 0; 27131e128c81SArun Easi 27141e128c81SArun Easi switch (type) { 27151e128c81SArun Easi case QED_LLH_FILTER_ETHERTYPE: 27161e128c81SArun Easi high = source_port_or_eth_type; 27171e128c81SArun Easi break; 27181e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_PORT: 27191e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_PORT: 27201e128c81SArun Easi low = source_port_or_eth_type << 16; 27211e128c81SArun Easi break; 27221e128c81SArun Easi case QED_LLH_FILTER_TCP_DEST_PORT: 27231e128c81SArun Easi case QED_LLH_FILTER_UDP_DEST_PORT: 27241e128c81SArun Easi low = dest_port; 27251e128c81SArun Easi break; 27261e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 27271e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 27281e128c81SArun Easi low = (source_port_or_eth_type << 16) | dest_port; 27291e128c81SArun Easi break; 27301e128c81SArun Easi default: 27311e128c81SArun Easi DP_NOTICE(p_hwfn, 27321e128c81SArun Easi "Non valid LLH protocol filter type %d\n", type); 27331e128c81SArun Easi return -EINVAL; 27341e128c81SArun Easi } 27351e128c81SArun Easi /* Find a free entry and utilize it */ 27361e128c81SArun Easi for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 27371e128c81SArun Easi en = qed_rd(p_hwfn, p_ptt, 27381e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)); 27391e128c81SArun Easi if (en) 27401e128c81SArun Easi continue; 27411e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 27421e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 27431e128c81SArun Easi 2 * i * sizeof(u32), low); 27441e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 27451e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 27461e128c81SArun Easi (2 * i + 1) * sizeof(u32), high); 27471e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 27481e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1); 27491e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 27501e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 27511e128c81SArun Easi i * sizeof(u32), 1 << type); 27521e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 27531e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1); 27541e128c81SArun Easi break; 27551e128c81SArun Easi } 27561e128c81SArun Easi if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) { 27571e128c81SArun Easi DP_NOTICE(p_hwfn, 27581e128c81SArun Easi "Failed to find an empty LLH filter to utilize\n"); 27591e128c81SArun Easi return -EINVAL; 27601e128c81SArun Easi } 27611e128c81SArun Easi switch (type) { 27621e128c81SArun Easi case QED_LLH_FILTER_ETHERTYPE: 27631e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 27641e128c81SArun Easi "ETH type %x is added at %d\n", 27651e128c81SArun Easi source_port_or_eth_type, i); 27661e128c81SArun Easi break; 27671e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_PORT: 27681e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 27691e128c81SArun Easi "TCP src port %x is added at %d\n", 27701e128c81SArun Easi source_port_or_eth_type, i); 27711e128c81SArun Easi break; 27721e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_PORT: 27731e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 27741e128c81SArun Easi "UDP src port %x is added at %d\n", 27751e128c81SArun Easi source_port_or_eth_type, i); 27761e128c81SArun Easi break; 27771e128c81SArun Easi case QED_LLH_FILTER_TCP_DEST_PORT: 27781e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 27791e128c81SArun Easi "TCP dst port %x is added at %d\n", dest_port, i); 27801e128c81SArun Easi break; 27811e128c81SArun Easi case QED_LLH_FILTER_UDP_DEST_PORT: 27821e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 27831e128c81SArun Easi "UDP dst port %x is added at %d\n", dest_port, i); 27841e128c81SArun Easi break; 27851e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 27861e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 27871e128c81SArun Easi "TCP src/dst ports %x/%x are added at %d\n", 27881e128c81SArun Easi source_port_or_eth_type, dest_port, i); 27891e128c81SArun Easi break; 27901e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 27911e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 27921e128c81SArun Easi "UDP src/dst ports %x/%x are added at %d\n", 27931e128c81SArun Easi source_port_or_eth_type, dest_port, i); 27941e128c81SArun Easi break; 27951e128c81SArun Easi } 27961e128c81SArun Easi return 0; 27971e128c81SArun Easi } 27981e128c81SArun Easi 27991e128c81SArun Easi void 28001e128c81SArun Easi qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn, 28011e128c81SArun Easi struct qed_ptt *p_ptt, 28021e128c81SArun Easi u16 source_port_or_eth_type, 28031e128c81SArun Easi u16 dest_port, 28041e128c81SArun Easi enum qed_llh_port_filter_type_t type) 28051e128c81SArun Easi { 28061e128c81SArun Easi u32 high = 0, low = 0; 28071e128c81SArun Easi int i; 28081e128c81SArun Easi 28091e128c81SArun Easi if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 28101e128c81SArun Easi return; 28111e128c81SArun Easi 28121e128c81SArun Easi switch (type) { 28131e128c81SArun Easi case QED_LLH_FILTER_ETHERTYPE: 28141e128c81SArun Easi high = source_port_or_eth_type; 28151e128c81SArun Easi break; 28161e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_PORT: 28171e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_PORT: 28181e128c81SArun Easi low = source_port_or_eth_type << 16; 28191e128c81SArun Easi break; 28201e128c81SArun Easi case QED_LLH_FILTER_TCP_DEST_PORT: 28211e128c81SArun Easi case QED_LLH_FILTER_UDP_DEST_PORT: 28221e128c81SArun Easi low = dest_port; 28231e128c81SArun Easi break; 28241e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 28251e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 28261e128c81SArun Easi low = (source_port_or_eth_type << 16) | dest_port; 28271e128c81SArun Easi break; 28281e128c81SArun Easi default: 28291e128c81SArun Easi DP_NOTICE(p_hwfn, 28301e128c81SArun Easi "Non valid LLH protocol filter type %d\n", type); 28311e128c81SArun Easi return; 28321e128c81SArun Easi } 28331e128c81SArun Easi 28341e128c81SArun Easi for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 28351e128c81SArun Easi if (!qed_rd(p_hwfn, p_ptt, 28361e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32))) 28371e128c81SArun Easi continue; 28381e128c81SArun Easi if (!qed_rd(p_hwfn, p_ptt, 28391e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32))) 28401e128c81SArun Easi continue; 28411e128c81SArun Easi if (!(qed_rd(p_hwfn, p_ptt, 28421e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 28431e128c81SArun Easi i * sizeof(u32)) & BIT(type))) 28441e128c81SArun Easi continue; 28451e128c81SArun Easi if (qed_rd(p_hwfn, p_ptt, 28461e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 28471e128c81SArun Easi 2 * i * sizeof(u32)) != low) 28481e128c81SArun Easi continue; 28491e128c81SArun Easi if (qed_rd(p_hwfn, p_ptt, 28501e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 28511e128c81SArun Easi (2 * i + 1) * sizeof(u32)) != high) 28521e128c81SArun Easi continue; 28531e128c81SArun Easi 28541e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 28551e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0); 28561e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 28571e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0); 28581e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 28591e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 28601e128c81SArun Easi i * sizeof(u32), 0); 28611e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 28621e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0); 28631e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 28641e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 28651e128c81SArun Easi (2 * i + 1) * sizeof(u32), 0); 28661e128c81SArun Easi break; 28671e128c81SArun Easi } 28681e128c81SArun Easi 28691e128c81SArun Easi if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) 28701e128c81SArun Easi DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n"); 28711e128c81SArun Easi } 28721e128c81SArun Easi 2873722003acSSudarsana Reddy Kalluru static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2874722003acSSudarsana Reddy Kalluru u32 hw_addr, void *p_eth_qzone, 2875722003acSSudarsana Reddy Kalluru size_t eth_qzone_size, u8 timeset) 2876722003acSSudarsana Reddy Kalluru { 2877722003acSSudarsana Reddy Kalluru struct coalescing_timeset *p_coal_timeset; 2878722003acSSudarsana Reddy Kalluru 2879722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) { 2880722003acSSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n"); 2881722003acSSudarsana Reddy Kalluru return -EINVAL; 2882722003acSSudarsana Reddy Kalluru } 2883722003acSSudarsana Reddy Kalluru 2884722003acSSudarsana Reddy Kalluru p_coal_timeset = p_eth_qzone; 2885722003acSSudarsana Reddy Kalluru memset(p_coal_timeset, 0, eth_qzone_size); 2886722003acSSudarsana Reddy Kalluru SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset); 2887722003acSSudarsana Reddy Kalluru SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1); 2888722003acSSudarsana Reddy Kalluru qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size); 2889722003acSSudarsana Reddy Kalluru 2890722003acSSudarsana Reddy Kalluru return 0; 2891722003acSSudarsana Reddy Kalluru } 2892722003acSSudarsana Reddy Kalluru 2893722003acSSudarsana Reddy Kalluru int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2894722003acSSudarsana Reddy Kalluru u16 coalesce, u8 qid, u16 sb_id) 2895722003acSSudarsana Reddy Kalluru { 2896722003acSSudarsana Reddy Kalluru struct ustorm_eth_queue_zone eth_qzone; 2897722003acSSudarsana Reddy Kalluru u8 timeset, timer_res; 2898722003acSSudarsana Reddy Kalluru u16 fw_qid = 0; 2899722003acSSudarsana Reddy Kalluru u32 address; 2900722003acSSudarsana Reddy Kalluru int rc; 2901722003acSSudarsana Reddy Kalluru 2902722003acSSudarsana Reddy Kalluru /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 2903722003acSSudarsana Reddy Kalluru if (coalesce <= 0x7F) { 2904722003acSSudarsana Reddy Kalluru timer_res = 0; 2905722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0xFF) { 2906722003acSSudarsana Reddy Kalluru timer_res = 1; 2907722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0x1FF) { 2908722003acSSudarsana Reddy Kalluru timer_res = 2; 2909722003acSSudarsana Reddy Kalluru } else { 2910722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 2911722003acSSudarsana Reddy Kalluru return -EINVAL; 2912722003acSSudarsana Reddy Kalluru } 2913722003acSSudarsana Reddy Kalluru timeset = (u8)(coalesce >> timer_res); 2914722003acSSudarsana Reddy Kalluru 2915722003acSSudarsana Reddy Kalluru rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid); 2916722003acSSudarsana Reddy Kalluru if (rc) 2917722003acSSudarsana Reddy Kalluru return rc; 2918722003acSSudarsana Reddy Kalluru 2919722003acSSudarsana Reddy Kalluru rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false); 2920722003acSSudarsana Reddy Kalluru if (rc) 2921722003acSSudarsana Reddy Kalluru goto out; 2922722003acSSudarsana Reddy Kalluru 2923722003acSSudarsana Reddy Kalluru address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid); 2924722003acSSudarsana Reddy Kalluru 2925722003acSSudarsana Reddy Kalluru rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 2926722003acSSudarsana Reddy Kalluru sizeof(struct ustorm_eth_queue_zone), timeset); 2927722003acSSudarsana Reddy Kalluru if (rc) 2928722003acSSudarsana Reddy Kalluru goto out; 2929722003acSSudarsana Reddy Kalluru 2930722003acSSudarsana Reddy Kalluru p_hwfn->cdev->rx_coalesce_usecs = coalesce; 2931722003acSSudarsana Reddy Kalluru out: 2932722003acSSudarsana Reddy Kalluru return rc; 2933722003acSSudarsana Reddy Kalluru } 2934722003acSSudarsana Reddy Kalluru 2935722003acSSudarsana Reddy Kalluru int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2936722003acSSudarsana Reddy Kalluru u16 coalesce, u8 qid, u16 sb_id) 2937722003acSSudarsana Reddy Kalluru { 2938722003acSSudarsana Reddy Kalluru struct xstorm_eth_queue_zone eth_qzone; 2939722003acSSudarsana Reddy Kalluru u8 timeset, timer_res; 2940722003acSSudarsana Reddy Kalluru u16 fw_qid = 0; 2941722003acSSudarsana Reddy Kalluru u32 address; 2942722003acSSudarsana Reddy Kalluru int rc; 2943722003acSSudarsana Reddy Kalluru 2944722003acSSudarsana Reddy Kalluru /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 2945722003acSSudarsana Reddy Kalluru if (coalesce <= 0x7F) { 2946722003acSSudarsana Reddy Kalluru timer_res = 0; 2947722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0xFF) { 2948722003acSSudarsana Reddy Kalluru timer_res = 1; 2949722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0x1FF) { 2950722003acSSudarsana Reddy Kalluru timer_res = 2; 2951722003acSSudarsana Reddy Kalluru } else { 2952722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 2953722003acSSudarsana Reddy Kalluru return -EINVAL; 2954722003acSSudarsana Reddy Kalluru } 2955722003acSSudarsana Reddy Kalluru timeset = (u8)(coalesce >> timer_res); 2956722003acSSudarsana Reddy Kalluru 2957722003acSSudarsana Reddy Kalluru rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid); 2958722003acSSudarsana Reddy Kalluru if (rc) 2959722003acSSudarsana Reddy Kalluru return rc; 2960722003acSSudarsana Reddy Kalluru 2961722003acSSudarsana Reddy Kalluru rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true); 2962722003acSSudarsana Reddy Kalluru if (rc) 2963722003acSSudarsana Reddy Kalluru goto out; 2964722003acSSudarsana Reddy Kalluru 2965722003acSSudarsana Reddy Kalluru address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid); 2966722003acSSudarsana Reddy Kalluru 2967722003acSSudarsana Reddy Kalluru rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 2968722003acSSudarsana Reddy Kalluru sizeof(struct xstorm_eth_queue_zone), timeset); 2969722003acSSudarsana Reddy Kalluru if (rc) 2970722003acSSudarsana Reddy Kalluru goto out; 2971722003acSSudarsana Reddy Kalluru 2972722003acSSudarsana Reddy Kalluru p_hwfn->cdev->tx_coalesce_usecs = coalesce; 2973722003acSSudarsana Reddy Kalluru out: 2974722003acSSudarsana Reddy Kalluru return rc; 2975722003acSSudarsana Reddy Kalluru } 2976722003acSSudarsana Reddy Kalluru 2977bcd197c8SManish Chopra /* Calculate final WFQ values for all vports and configure them. 2978bcd197c8SManish Chopra * After this configuration each vport will have 2979bcd197c8SManish Chopra * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT) 2980bcd197c8SManish Chopra */ 2981bcd197c8SManish Chopra static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 2982bcd197c8SManish Chopra struct qed_ptt *p_ptt, 2983bcd197c8SManish Chopra u32 min_pf_rate) 2984bcd197c8SManish Chopra { 2985bcd197c8SManish Chopra struct init_qm_vport_params *vport_params; 2986bcd197c8SManish Chopra int i; 2987bcd197c8SManish Chopra 2988bcd197c8SManish Chopra vport_params = p_hwfn->qm_info.qm_vport_params; 2989bcd197c8SManish Chopra 2990bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 2991bcd197c8SManish Chopra u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 2992bcd197c8SManish Chopra 2993bcd197c8SManish Chopra vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) / 2994bcd197c8SManish Chopra min_pf_rate; 2995bcd197c8SManish Chopra qed_init_vport_wfq(p_hwfn, p_ptt, 2996bcd197c8SManish Chopra vport_params[i].first_tx_pq_id, 2997bcd197c8SManish Chopra vport_params[i].vport_wfq); 2998bcd197c8SManish Chopra } 2999bcd197c8SManish Chopra } 3000bcd197c8SManish Chopra 3001bcd197c8SManish Chopra static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn, 3002bcd197c8SManish Chopra u32 min_pf_rate) 3003bcd197c8SManish Chopra 3004bcd197c8SManish Chopra { 3005bcd197c8SManish Chopra int i; 3006bcd197c8SManish Chopra 3007bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) 3008bcd197c8SManish Chopra p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1; 3009bcd197c8SManish Chopra } 3010bcd197c8SManish Chopra 3011bcd197c8SManish Chopra static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 3012bcd197c8SManish Chopra struct qed_ptt *p_ptt, 3013bcd197c8SManish Chopra u32 min_pf_rate) 3014bcd197c8SManish Chopra { 3015bcd197c8SManish Chopra struct init_qm_vport_params *vport_params; 3016bcd197c8SManish Chopra int i; 3017bcd197c8SManish Chopra 3018bcd197c8SManish Chopra vport_params = p_hwfn->qm_info.qm_vport_params; 3019bcd197c8SManish Chopra 3020bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 3021bcd197c8SManish Chopra qed_init_wfq_default_param(p_hwfn, min_pf_rate); 3022bcd197c8SManish Chopra qed_init_vport_wfq(p_hwfn, p_ptt, 3023bcd197c8SManish Chopra vport_params[i].first_tx_pq_id, 3024bcd197c8SManish Chopra vport_params[i].vport_wfq); 3025bcd197c8SManish Chopra } 3026bcd197c8SManish Chopra } 3027bcd197c8SManish Chopra 3028bcd197c8SManish Chopra /* This function performs several validations for WFQ 3029bcd197c8SManish Chopra * configuration and required min rate for a given vport 3030bcd197c8SManish Chopra * 1. req_rate must be greater than one percent of min_pf_rate. 3031bcd197c8SManish Chopra * 2. req_rate should not cause other vports [not configured for WFQ explicitly] 3032bcd197c8SManish Chopra * rates to get less than one percent of min_pf_rate. 3033bcd197c8SManish Chopra * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate. 3034bcd197c8SManish Chopra */ 3035bcd197c8SManish Chopra static int qed_init_wfq_param(struct qed_hwfn *p_hwfn, 30361a635e48SYuval Mintz u16 vport_id, u32 req_rate, u32 min_pf_rate) 3037bcd197c8SManish Chopra { 3038bcd197c8SManish Chopra u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0; 3039bcd197c8SManish Chopra int non_requested_count = 0, req_count = 0, i, num_vports; 3040bcd197c8SManish Chopra 3041bcd197c8SManish Chopra num_vports = p_hwfn->qm_info.num_vports; 3042bcd197c8SManish Chopra 3043bcd197c8SManish Chopra /* Accounting for the vports which are configured for WFQ explicitly */ 3044bcd197c8SManish Chopra for (i = 0; i < num_vports; i++) { 3045bcd197c8SManish Chopra u32 tmp_speed; 3046bcd197c8SManish Chopra 3047bcd197c8SManish Chopra if ((i != vport_id) && 3048bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[i].configured) { 3049bcd197c8SManish Chopra req_count++; 3050bcd197c8SManish Chopra tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 3051bcd197c8SManish Chopra total_req_min_rate += tmp_speed; 3052bcd197c8SManish Chopra } 3053bcd197c8SManish Chopra } 3054bcd197c8SManish Chopra 3055bcd197c8SManish Chopra /* Include current vport data as well */ 3056bcd197c8SManish Chopra req_count++; 3057bcd197c8SManish Chopra total_req_min_rate += req_rate; 3058bcd197c8SManish Chopra non_requested_count = num_vports - req_count; 3059bcd197c8SManish Chopra 3060bcd197c8SManish Chopra if (req_rate < min_pf_rate / QED_WFQ_UNIT) { 3061bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 3062bcd197c8SManish Chopra "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 3063bcd197c8SManish Chopra vport_id, req_rate, min_pf_rate); 3064bcd197c8SManish Chopra return -EINVAL; 3065bcd197c8SManish Chopra } 3066bcd197c8SManish Chopra 3067bcd197c8SManish Chopra if (num_vports > QED_WFQ_UNIT) { 3068bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 3069bcd197c8SManish Chopra "Number of vports is greater than %d\n", 3070bcd197c8SManish Chopra QED_WFQ_UNIT); 3071bcd197c8SManish Chopra return -EINVAL; 3072bcd197c8SManish Chopra } 3073bcd197c8SManish Chopra 3074bcd197c8SManish Chopra if (total_req_min_rate > min_pf_rate) { 3075bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 3076bcd197c8SManish Chopra "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n", 3077bcd197c8SManish Chopra total_req_min_rate, min_pf_rate); 3078bcd197c8SManish Chopra return -EINVAL; 3079bcd197c8SManish Chopra } 3080bcd197c8SManish Chopra 3081bcd197c8SManish Chopra total_left_rate = min_pf_rate - total_req_min_rate; 3082bcd197c8SManish Chopra 3083bcd197c8SManish Chopra left_rate_per_vp = total_left_rate / non_requested_count; 3084bcd197c8SManish Chopra if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) { 3085bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 3086bcd197c8SManish Chopra "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 3087bcd197c8SManish Chopra left_rate_per_vp, min_pf_rate); 3088bcd197c8SManish Chopra return -EINVAL; 3089bcd197c8SManish Chopra } 3090bcd197c8SManish Chopra 3091bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate; 3092bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[vport_id].configured = true; 3093bcd197c8SManish Chopra 3094bcd197c8SManish Chopra for (i = 0; i < num_vports; i++) { 3095bcd197c8SManish Chopra if (p_hwfn->qm_info.wfq_data[i].configured) 3096bcd197c8SManish Chopra continue; 3097bcd197c8SManish Chopra 3098bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp; 3099bcd197c8SManish Chopra } 3100bcd197c8SManish Chopra 3101bcd197c8SManish Chopra return 0; 3102bcd197c8SManish Chopra } 3103bcd197c8SManish Chopra 3104733def6aSYuval Mintz static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn, 3105733def6aSYuval Mintz struct qed_ptt *p_ptt, u16 vp_id, u32 rate) 3106733def6aSYuval Mintz { 3107733def6aSYuval Mintz struct qed_mcp_link_state *p_link; 3108733def6aSYuval Mintz int rc = 0; 3109733def6aSYuval Mintz 3110733def6aSYuval Mintz p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output; 3111733def6aSYuval Mintz 3112733def6aSYuval Mintz if (!p_link->min_pf_rate) { 3113733def6aSYuval Mintz p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate; 3114733def6aSYuval Mintz p_hwfn->qm_info.wfq_data[vp_id].configured = true; 3115733def6aSYuval Mintz return rc; 3116733def6aSYuval Mintz } 3117733def6aSYuval Mintz 3118733def6aSYuval Mintz rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate); 3119733def6aSYuval Mintz 31201a635e48SYuval Mintz if (!rc) 3121733def6aSYuval Mintz qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, 3122733def6aSYuval Mintz p_link->min_pf_rate); 3123733def6aSYuval Mintz else 3124733def6aSYuval Mintz DP_NOTICE(p_hwfn, 3125733def6aSYuval Mintz "Validation failed while configuring min rate\n"); 3126733def6aSYuval Mintz 3127733def6aSYuval Mintz return rc; 3128733def6aSYuval Mintz } 3129733def6aSYuval Mintz 3130bcd197c8SManish Chopra static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn, 3131bcd197c8SManish Chopra struct qed_ptt *p_ptt, 3132bcd197c8SManish Chopra u32 min_pf_rate) 3133bcd197c8SManish Chopra { 3134bcd197c8SManish Chopra bool use_wfq = false; 3135bcd197c8SManish Chopra int rc = 0; 3136bcd197c8SManish Chopra u16 i; 3137bcd197c8SManish Chopra 3138bcd197c8SManish Chopra /* Validate all pre configured vports for wfq */ 3139bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 3140bcd197c8SManish Chopra u32 rate; 3141bcd197c8SManish Chopra 3142bcd197c8SManish Chopra if (!p_hwfn->qm_info.wfq_data[i].configured) 3143bcd197c8SManish Chopra continue; 3144bcd197c8SManish Chopra 3145bcd197c8SManish Chopra rate = p_hwfn->qm_info.wfq_data[i].min_speed; 3146bcd197c8SManish Chopra use_wfq = true; 3147bcd197c8SManish Chopra 3148bcd197c8SManish Chopra rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate); 3149bcd197c8SManish Chopra if (rc) { 3150bcd197c8SManish Chopra DP_NOTICE(p_hwfn, 3151bcd197c8SManish Chopra "WFQ validation failed while configuring min rate\n"); 3152bcd197c8SManish Chopra break; 3153bcd197c8SManish Chopra } 3154bcd197c8SManish Chopra } 3155bcd197c8SManish Chopra 3156bcd197c8SManish Chopra if (!rc && use_wfq) 3157bcd197c8SManish Chopra qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 3158bcd197c8SManish Chopra else 3159bcd197c8SManish Chopra qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 3160bcd197c8SManish Chopra 3161bcd197c8SManish Chopra return rc; 3162bcd197c8SManish Chopra } 3163bcd197c8SManish Chopra 3164733def6aSYuval Mintz /* Main API for qed clients to configure vport min rate. 3165733def6aSYuval Mintz * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)] 3166733def6aSYuval Mintz * rate - Speed in Mbps needs to be assigned to a given vport. 3167733def6aSYuval Mintz */ 3168733def6aSYuval Mintz int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate) 3169733def6aSYuval Mintz { 3170733def6aSYuval Mintz int i, rc = -EINVAL; 3171733def6aSYuval Mintz 3172733def6aSYuval Mintz /* Currently not supported; Might change in future */ 3173733def6aSYuval Mintz if (cdev->num_hwfns > 1) { 3174733def6aSYuval Mintz DP_NOTICE(cdev, 3175733def6aSYuval Mintz "WFQ configuration is not supported for this device\n"); 3176733def6aSYuval Mintz return rc; 3177733def6aSYuval Mintz } 3178733def6aSYuval Mintz 3179733def6aSYuval Mintz for_each_hwfn(cdev, i) { 3180733def6aSYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 3181733def6aSYuval Mintz struct qed_ptt *p_ptt; 3182733def6aSYuval Mintz 3183733def6aSYuval Mintz p_ptt = qed_ptt_acquire(p_hwfn); 3184733def6aSYuval Mintz if (!p_ptt) 3185733def6aSYuval Mintz return -EBUSY; 3186733def6aSYuval Mintz 3187733def6aSYuval Mintz rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate); 3188733def6aSYuval Mintz 3189d572c430SYuval Mintz if (rc) { 3190733def6aSYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 3191733def6aSYuval Mintz return rc; 3192733def6aSYuval Mintz } 3193733def6aSYuval Mintz 3194733def6aSYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 3195733def6aSYuval Mintz } 3196733def6aSYuval Mintz 3197733def6aSYuval Mintz return rc; 3198733def6aSYuval Mintz } 3199733def6aSYuval Mintz 3200bcd197c8SManish Chopra /* API to configure WFQ from mcp link change */ 3201bcd197c8SManish Chopra void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate) 3202bcd197c8SManish Chopra { 3203bcd197c8SManish Chopra int i; 3204bcd197c8SManish Chopra 32053e7cfce2SYuval Mintz if (cdev->num_hwfns > 1) { 32063e7cfce2SYuval Mintz DP_VERBOSE(cdev, 32073e7cfce2SYuval Mintz NETIF_MSG_LINK, 32083e7cfce2SYuval Mintz "WFQ configuration is not supported for this device\n"); 32093e7cfce2SYuval Mintz return; 32103e7cfce2SYuval Mintz } 32113e7cfce2SYuval Mintz 3212bcd197c8SManish Chopra for_each_hwfn(cdev, i) { 3213bcd197c8SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 3214bcd197c8SManish Chopra 3215bcd197c8SManish Chopra __qed_configure_vp_wfq_on_link_change(p_hwfn, 3216bcd197c8SManish Chopra p_hwfn->p_dpc_ptt, 3217bcd197c8SManish Chopra min_pf_rate); 3218bcd197c8SManish Chopra } 3219bcd197c8SManish Chopra } 32204b01e519SManish Chopra 32214b01e519SManish Chopra int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn, 32224b01e519SManish Chopra struct qed_ptt *p_ptt, 32234b01e519SManish Chopra struct qed_mcp_link_state *p_link, 32244b01e519SManish Chopra u8 max_bw) 32254b01e519SManish Chopra { 32264b01e519SManish Chopra int rc = 0; 32274b01e519SManish Chopra 32284b01e519SManish Chopra p_hwfn->mcp_info->func_info.bandwidth_max = max_bw; 32294b01e519SManish Chopra 32304b01e519SManish Chopra if (!p_link->line_speed && (max_bw != 100)) 32314b01e519SManish Chopra return rc; 32324b01e519SManish Chopra 32334b01e519SManish Chopra p_link->speed = (p_link->line_speed * max_bw) / 100; 32344b01e519SManish Chopra p_hwfn->qm_info.pf_rl = p_link->speed; 32354b01e519SManish Chopra 32364b01e519SManish Chopra /* Since the limiter also affects Tx-switched traffic, we don't want it 32374b01e519SManish Chopra * to limit such traffic in case there's no actual limit. 32384b01e519SManish Chopra * In that case, set limit to imaginary high boundary. 32394b01e519SManish Chopra */ 32404b01e519SManish Chopra if (max_bw == 100) 32414b01e519SManish Chopra p_hwfn->qm_info.pf_rl = 100000; 32424b01e519SManish Chopra 32434b01e519SManish Chopra rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, 32444b01e519SManish Chopra p_hwfn->qm_info.pf_rl); 32454b01e519SManish Chopra 32464b01e519SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 32474b01e519SManish Chopra "Configured MAX bandwidth to be %08x Mb/sec\n", 32484b01e519SManish Chopra p_link->speed); 32494b01e519SManish Chopra 32504b01e519SManish Chopra return rc; 32514b01e519SManish Chopra } 32524b01e519SManish Chopra 32534b01e519SManish Chopra /* Main API to configure PF max bandwidth where bw range is [1 - 100] */ 32544b01e519SManish Chopra int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw) 32554b01e519SManish Chopra { 32564b01e519SManish Chopra int i, rc = -EINVAL; 32574b01e519SManish Chopra 32584b01e519SManish Chopra if (max_bw < 1 || max_bw > 100) { 32594b01e519SManish Chopra DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n"); 32604b01e519SManish Chopra return rc; 32614b01e519SManish Chopra } 32624b01e519SManish Chopra 32634b01e519SManish Chopra for_each_hwfn(cdev, i) { 32644b01e519SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 32654b01e519SManish Chopra struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 32664b01e519SManish Chopra struct qed_mcp_link_state *p_link; 32674b01e519SManish Chopra struct qed_ptt *p_ptt; 32684b01e519SManish Chopra 32694b01e519SManish Chopra p_link = &p_lead->mcp_info->link_output; 32704b01e519SManish Chopra 32714b01e519SManish Chopra p_ptt = qed_ptt_acquire(p_hwfn); 32724b01e519SManish Chopra if (!p_ptt) 32734b01e519SManish Chopra return -EBUSY; 32744b01e519SManish Chopra 32754b01e519SManish Chopra rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, 32764b01e519SManish Chopra p_link, max_bw); 32774b01e519SManish Chopra 32784b01e519SManish Chopra qed_ptt_release(p_hwfn, p_ptt); 32794b01e519SManish Chopra 32804b01e519SManish Chopra if (rc) 32814b01e519SManish Chopra break; 32824b01e519SManish Chopra } 32834b01e519SManish Chopra 32844b01e519SManish Chopra return rc; 32854b01e519SManish Chopra } 3286a64b02d5SManish Chopra 3287a64b02d5SManish Chopra int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn, 3288a64b02d5SManish Chopra struct qed_ptt *p_ptt, 3289a64b02d5SManish Chopra struct qed_mcp_link_state *p_link, 3290a64b02d5SManish Chopra u8 min_bw) 3291a64b02d5SManish Chopra { 3292a64b02d5SManish Chopra int rc = 0; 3293a64b02d5SManish Chopra 3294a64b02d5SManish Chopra p_hwfn->mcp_info->func_info.bandwidth_min = min_bw; 3295a64b02d5SManish Chopra p_hwfn->qm_info.pf_wfq = min_bw; 3296a64b02d5SManish Chopra 3297a64b02d5SManish Chopra if (!p_link->line_speed) 3298a64b02d5SManish Chopra return rc; 3299a64b02d5SManish Chopra 3300a64b02d5SManish Chopra p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100; 3301a64b02d5SManish Chopra 3302a64b02d5SManish Chopra rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw); 3303a64b02d5SManish Chopra 3304a64b02d5SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 3305a64b02d5SManish Chopra "Configured MIN bandwidth to be %d Mb/sec\n", 3306a64b02d5SManish Chopra p_link->min_pf_rate); 3307a64b02d5SManish Chopra 3308a64b02d5SManish Chopra return rc; 3309a64b02d5SManish Chopra } 3310a64b02d5SManish Chopra 3311a64b02d5SManish Chopra /* Main API to configure PF min bandwidth where bw range is [1-100] */ 3312a64b02d5SManish Chopra int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw) 3313a64b02d5SManish Chopra { 3314a64b02d5SManish Chopra int i, rc = -EINVAL; 3315a64b02d5SManish Chopra 3316a64b02d5SManish Chopra if (min_bw < 1 || min_bw > 100) { 3317a64b02d5SManish Chopra DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n"); 3318a64b02d5SManish Chopra return rc; 3319a64b02d5SManish Chopra } 3320a64b02d5SManish Chopra 3321a64b02d5SManish Chopra for_each_hwfn(cdev, i) { 3322a64b02d5SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 3323a64b02d5SManish Chopra struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 3324a64b02d5SManish Chopra struct qed_mcp_link_state *p_link; 3325a64b02d5SManish Chopra struct qed_ptt *p_ptt; 3326a64b02d5SManish Chopra 3327a64b02d5SManish Chopra p_link = &p_lead->mcp_info->link_output; 3328a64b02d5SManish Chopra 3329a64b02d5SManish Chopra p_ptt = qed_ptt_acquire(p_hwfn); 3330a64b02d5SManish Chopra if (!p_ptt) 3331a64b02d5SManish Chopra return -EBUSY; 3332a64b02d5SManish Chopra 3333a64b02d5SManish Chopra rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, 3334a64b02d5SManish Chopra p_link, min_bw); 3335a64b02d5SManish Chopra if (rc) { 3336a64b02d5SManish Chopra qed_ptt_release(p_hwfn, p_ptt); 3337a64b02d5SManish Chopra return rc; 3338a64b02d5SManish Chopra } 3339a64b02d5SManish Chopra 3340a64b02d5SManish Chopra if (p_link->min_pf_rate) { 3341a64b02d5SManish Chopra u32 min_rate = p_link->min_pf_rate; 3342a64b02d5SManish Chopra 3343a64b02d5SManish Chopra rc = __qed_configure_vp_wfq_on_link_change(p_hwfn, 3344a64b02d5SManish Chopra p_ptt, 3345a64b02d5SManish Chopra min_rate); 3346a64b02d5SManish Chopra } 3347a64b02d5SManish Chopra 3348a64b02d5SManish Chopra qed_ptt_release(p_hwfn, p_ptt); 3349a64b02d5SManish Chopra } 3350a64b02d5SManish Chopra 3351a64b02d5SManish Chopra return rc; 3352a64b02d5SManish Chopra } 3353733def6aSYuval Mintz 3354733def6aSYuval Mintz void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3355733def6aSYuval Mintz { 3356733def6aSYuval Mintz struct qed_mcp_link_state *p_link; 3357733def6aSYuval Mintz 3358733def6aSYuval Mintz p_link = &p_hwfn->mcp_info->link_output; 3359733def6aSYuval Mintz 3360733def6aSYuval Mintz if (p_link->min_pf_rate) 3361733def6aSYuval Mintz qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, 3362733def6aSYuval Mintz p_link->min_pf_rate); 3363733def6aSYuval Mintz 3364733def6aSYuval Mintz memset(p_hwfn->qm_info.wfq_data, 0, 3365733def6aSYuval Mintz sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports); 3366733def6aSYuval Mintz } 3367