1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #include <linux/types.h> 34fe56b9e6SYuval Mintz #include <asm/byteorder.h> 35fe56b9e6SYuval Mintz #include <linux/io.h> 36fe56b9e6SYuval Mintz #include <linux/delay.h> 37fe56b9e6SYuval Mintz #include <linux/dma-mapping.h> 38fe56b9e6SYuval Mintz #include <linux/errno.h> 39fe56b9e6SYuval Mintz #include <linux/kernel.h> 40fe56b9e6SYuval Mintz #include <linux/mutex.h> 41fe56b9e6SYuval Mintz #include <linux/pci.h> 42fe56b9e6SYuval Mintz #include <linux/slab.h> 43fe56b9e6SYuval Mintz #include <linux/string.h> 44a91eb52aSYuval Mintz #include <linux/vmalloc.h> 45fe56b9e6SYuval Mintz #include <linux/etherdevice.h> 46fe56b9e6SYuval Mintz #include <linux/qed/qed_chain.h> 47fe56b9e6SYuval Mintz #include <linux/qed/qed_if.h> 48fe56b9e6SYuval Mintz #include "qed.h" 49fe56b9e6SYuval Mintz #include "qed_cxt.h" 5039651abdSSudarsana Reddy Kalluru #include "qed_dcbx.h" 51fe56b9e6SYuval Mintz #include "qed_dev_api.h" 521e128c81SArun Easi #include "qed_fcoe.h" 53fe56b9e6SYuval Mintz #include "qed_hsi.h" 54fe56b9e6SYuval Mintz #include "qed_hw.h" 55fe56b9e6SYuval Mintz #include "qed_init_ops.h" 56fe56b9e6SYuval Mintz #include "qed_int.h" 57fc831825SYuval Mintz #include "qed_iscsi.h" 580a7fb11cSYuval Mintz #include "qed_ll2.h" 59fe56b9e6SYuval Mintz #include "qed_mcp.h" 601d6cff4fSYuval Mintz #include "qed_ooo.h" 61fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 62fe56b9e6SYuval Mintz #include "qed_sp.h" 6332a47e72SYuval Mintz #include "qed_sriov.h" 640b55e27dSYuval Mintz #include "qed_vf.h" 65b71b9afdSKalderon, Michal #include "qed_rdma.h" 66fe56b9e6SYuval Mintz 670caf5b26SWei Yongjun static DEFINE_SPINLOCK(qm_lock); 6839651abdSSudarsana Reddy Kalluru 6951ff1725SRam Amrani #define QED_MIN_DPIS (4) 7051ff1725SRam Amrani #define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS) 7151ff1725SRam Amrani 7215582962SRahul Verma static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, 7315582962SRahul Verma struct qed_ptt *p_ptt, enum BAR_ID bar_id) 74c2035eeaSRam Amrani { 75c2035eeaSRam Amrani u32 bar_reg = (bar_id == BAR_ID_0 ? 76c2035eeaSRam Amrani PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE); 771408cc1fSYuval Mintz u32 val; 78c2035eeaSRam Amrani 791408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 801a850bfcSMintz, Yuval return qed_vf_hw_bar_size(p_hwfn, bar_id); 811408cc1fSYuval Mintz 8215582962SRahul Verma val = qed_rd(p_hwfn, p_ptt, bar_reg); 83c2035eeaSRam Amrani if (val) 84c2035eeaSRam Amrani return 1 << (val + 15); 85c2035eeaSRam Amrani 86c2035eeaSRam Amrani /* Old MFW initialized above registered only conditionally */ 87c2035eeaSRam Amrani if (p_hwfn->cdev->num_hwfns > 1) { 88c2035eeaSRam Amrani DP_INFO(p_hwfn, 89c2035eeaSRam Amrani "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n"); 90c2035eeaSRam Amrani return BAR_ID_0 ? 256 * 1024 : 512 * 1024; 91c2035eeaSRam Amrani } else { 92c2035eeaSRam Amrani DP_INFO(p_hwfn, 93c2035eeaSRam Amrani "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n"); 94c2035eeaSRam Amrani return 512 * 1024; 95c2035eeaSRam Amrani } 96c2035eeaSRam Amrani } 97c2035eeaSRam Amrani 981a635e48SYuval Mintz void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level) 99fe56b9e6SYuval Mintz { 100fe56b9e6SYuval Mintz u32 i; 101fe56b9e6SYuval Mintz 102fe56b9e6SYuval Mintz cdev->dp_level = dp_level; 103fe56b9e6SYuval Mintz cdev->dp_module = dp_module; 104fe56b9e6SYuval Mintz for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 105fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 106fe56b9e6SYuval Mintz 107fe56b9e6SYuval Mintz p_hwfn->dp_level = dp_level; 108fe56b9e6SYuval Mintz p_hwfn->dp_module = dp_module; 109fe56b9e6SYuval Mintz } 110fe56b9e6SYuval Mintz } 111fe56b9e6SYuval Mintz 112fe56b9e6SYuval Mintz void qed_init_struct(struct qed_dev *cdev) 113fe56b9e6SYuval Mintz { 114fe56b9e6SYuval Mintz u8 i; 115fe56b9e6SYuval Mintz 116fe56b9e6SYuval Mintz for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 117fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 118fe56b9e6SYuval Mintz 119fe56b9e6SYuval Mintz p_hwfn->cdev = cdev; 120fe56b9e6SYuval Mintz p_hwfn->my_id = i; 121fe56b9e6SYuval Mintz p_hwfn->b_active = false; 122fe56b9e6SYuval Mintz 123fe56b9e6SYuval Mintz mutex_init(&p_hwfn->dmae_info.mutex); 124fe56b9e6SYuval Mintz } 125fe56b9e6SYuval Mintz 126fe56b9e6SYuval Mintz /* hwfn 0 is always active */ 127fe56b9e6SYuval Mintz cdev->hwfns[0].b_active = true; 128fe56b9e6SYuval Mintz 129fe56b9e6SYuval Mintz /* set the default cache alignment to 128 */ 130fe56b9e6SYuval Mintz cdev->cache_shift = 7; 131fe56b9e6SYuval Mintz } 132fe56b9e6SYuval Mintz 133fe56b9e6SYuval Mintz static void qed_qm_info_free(struct qed_hwfn *p_hwfn) 134fe56b9e6SYuval Mintz { 135fe56b9e6SYuval Mintz struct qed_qm_info *qm_info = &p_hwfn->qm_info; 136fe56b9e6SYuval Mintz 137fe56b9e6SYuval Mintz kfree(qm_info->qm_pq_params); 138fe56b9e6SYuval Mintz qm_info->qm_pq_params = NULL; 139fe56b9e6SYuval Mintz kfree(qm_info->qm_vport_params); 140fe56b9e6SYuval Mintz qm_info->qm_vport_params = NULL; 141fe56b9e6SYuval Mintz kfree(qm_info->qm_port_params); 142fe56b9e6SYuval Mintz qm_info->qm_port_params = NULL; 143bcd197c8SManish Chopra kfree(qm_info->wfq_data); 144bcd197c8SManish Chopra qm_info->wfq_data = NULL; 145fe56b9e6SYuval Mintz } 146fe56b9e6SYuval Mintz 147fe56b9e6SYuval Mintz void qed_resc_free(struct qed_dev *cdev) 148fe56b9e6SYuval Mintz { 149fe56b9e6SYuval Mintz int i; 150fe56b9e6SYuval Mintz 1510db711bbSMintz, Yuval if (IS_VF(cdev)) { 1520db711bbSMintz, Yuval for_each_hwfn(cdev, i) 1530db711bbSMintz, Yuval qed_l2_free(&cdev->hwfns[i]); 1541408cc1fSYuval Mintz return; 1550db711bbSMintz, Yuval } 1561408cc1fSYuval Mintz 157fe56b9e6SYuval Mintz kfree(cdev->fw_data); 158fe56b9e6SYuval Mintz cdev->fw_data = NULL; 159fe56b9e6SYuval Mintz 160fe56b9e6SYuval Mintz kfree(cdev->reset_stats); 1613587cb87STomer Tayar cdev->reset_stats = NULL; 162fe56b9e6SYuval Mintz 163fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 164fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 165fe56b9e6SYuval Mintz 166fe56b9e6SYuval Mintz qed_cxt_mngr_free(p_hwfn); 167fe56b9e6SYuval Mintz qed_qm_info_free(p_hwfn); 168fe56b9e6SYuval Mintz qed_spq_free(p_hwfn); 1693587cb87STomer Tayar qed_eq_free(p_hwfn); 1703587cb87STomer Tayar qed_consq_free(p_hwfn); 171fe56b9e6SYuval Mintz qed_int_free(p_hwfn); 1720a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 1733587cb87STomer Tayar qed_ll2_free(p_hwfn); 1740a7fb11cSYuval Mintz #endif 1751e128c81SArun Easi if (p_hwfn->hw_info.personality == QED_PCI_FCOE) 1763587cb87STomer Tayar qed_fcoe_free(p_hwfn); 1771e128c81SArun Easi 1781d6cff4fSYuval Mintz if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 1793587cb87STomer Tayar qed_iscsi_free(p_hwfn); 1803587cb87STomer Tayar qed_ooo_free(p_hwfn); 1811d6cff4fSYuval Mintz } 18232a47e72SYuval Mintz qed_iov_free(p_hwfn); 1830db711bbSMintz, Yuval qed_l2_free(p_hwfn); 184fe56b9e6SYuval Mintz qed_dmae_info_free(p_hwfn); 185270837b3Ssudarsana.kalluru@cavium.com qed_dcbx_info_free(p_hwfn); 186fe56b9e6SYuval Mintz } 187fe56b9e6SYuval Mintz } 188fe56b9e6SYuval Mintz 189b5a9ee7cSAriel Elior /******************** QM initialization *******************/ 190b5a9ee7cSAriel Elior #define ACTIVE_TCS_BMAP 0x9f 191b5a9ee7cSAriel Elior #define ACTIVE_TCS_BMAP_4PORT_K2 0xf 192b5a9ee7cSAriel Elior 193b5a9ee7cSAriel Elior /* determines the physical queue flags for a given PF. */ 194b5a9ee7cSAriel Elior static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn) 195fe56b9e6SYuval Mintz { 196b5a9ee7cSAriel Elior u32 flags; 197fe56b9e6SYuval Mintz 198b5a9ee7cSAriel Elior /* common flags */ 199b5a9ee7cSAriel Elior flags = PQ_FLAGS_LB; 200fe56b9e6SYuval Mintz 201b5a9ee7cSAriel Elior /* feature flags */ 202b5a9ee7cSAriel Elior if (IS_QED_SRIOV(p_hwfn->cdev)) 203b5a9ee7cSAriel Elior flags |= PQ_FLAGS_VFS; 204fe56b9e6SYuval Mintz 205b5a9ee7cSAriel Elior /* protocol flags */ 206b5a9ee7cSAriel Elior switch (p_hwfn->hw_info.personality) { 207b5a9ee7cSAriel Elior case QED_PCI_ETH: 208b5a9ee7cSAriel Elior flags |= PQ_FLAGS_MCOS; 209b5a9ee7cSAriel Elior break; 210b5a9ee7cSAriel Elior case QED_PCI_FCOE: 211b5a9ee7cSAriel Elior flags |= PQ_FLAGS_OFLD; 212b5a9ee7cSAriel Elior break; 213b5a9ee7cSAriel Elior case QED_PCI_ISCSI: 214b5a9ee7cSAriel Elior flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD; 215b5a9ee7cSAriel Elior break; 216b5a9ee7cSAriel Elior case QED_PCI_ETH_ROCE: 217b5a9ee7cSAriel Elior flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT; 218b5a9ee7cSAriel Elior break; 21993c45984SKalderon, Michal case QED_PCI_ETH_IWARP: 22093c45984SKalderon, Michal flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO | 22193c45984SKalderon, Michal PQ_FLAGS_OFLD; 22293c45984SKalderon, Michal break; 223b5a9ee7cSAriel Elior default: 224fe56b9e6SYuval Mintz DP_ERR(p_hwfn, 225b5a9ee7cSAriel Elior "unknown personality %d\n", p_hwfn->hw_info.personality); 226b5a9ee7cSAriel Elior return 0; 227fe56b9e6SYuval Mintz } 228fe56b9e6SYuval Mintz 229b5a9ee7cSAriel Elior return flags; 230b5a9ee7cSAriel Elior } 231b5a9ee7cSAriel Elior 232b5a9ee7cSAriel Elior /* Getters for resource amounts necessary for qm initialization */ 233bf774d14SYueHaibing static u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn) 234b5a9ee7cSAriel Elior { 235b5a9ee7cSAriel Elior return p_hwfn->hw_info.num_hw_tc; 236b5a9ee7cSAriel Elior } 237b5a9ee7cSAriel Elior 238bf774d14SYueHaibing static u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn) 239b5a9ee7cSAriel Elior { 240b5a9ee7cSAriel Elior return IS_QED_SRIOV(p_hwfn->cdev) ? 241b5a9ee7cSAriel Elior p_hwfn->cdev->p_iov_info->total_vfs : 0; 242b5a9ee7cSAriel Elior } 243b5a9ee7cSAriel Elior 244b5a9ee7cSAriel Elior #define NUM_DEFAULT_RLS 1 245b5a9ee7cSAriel Elior 246bf774d14SYueHaibing static u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn) 247b5a9ee7cSAriel Elior { 248b5a9ee7cSAriel Elior u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn); 249b5a9ee7cSAriel Elior 250b5a9ee7cSAriel Elior /* num RLs can't exceed resource amount of rls or vports */ 251b5a9ee7cSAriel Elior num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL), 252b5a9ee7cSAriel Elior RESC_NUM(p_hwfn, QED_VPORT)); 253b5a9ee7cSAriel Elior 254b5a9ee7cSAriel Elior /* Make sure after we reserve there's something left */ 255b5a9ee7cSAriel Elior if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) 256b5a9ee7cSAriel Elior return 0; 257b5a9ee7cSAriel Elior 258b5a9ee7cSAriel Elior /* subtract rls necessary for VFs and one default one for the PF */ 259b5a9ee7cSAriel Elior num_pf_rls -= num_vfs + NUM_DEFAULT_RLS; 260b5a9ee7cSAriel Elior 261b5a9ee7cSAriel Elior return num_pf_rls; 262b5a9ee7cSAriel Elior } 263b5a9ee7cSAriel Elior 264bf774d14SYueHaibing static u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn) 265b5a9ee7cSAriel Elior { 266b5a9ee7cSAriel Elior u32 pq_flags = qed_get_pq_flags(p_hwfn); 267b5a9ee7cSAriel Elior 268b5a9ee7cSAriel Elior /* all pqs share the same vport, except for vfs and pf_rl pqs */ 269b5a9ee7cSAriel Elior return (!!(PQ_FLAGS_RLS & pq_flags)) * 270b5a9ee7cSAriel Elior qed_init_qm_get_num_pf_rls(p_hwfn) + 271b5a9ee7cSAriel Elior (!!(PQ_FLAGS_VFS & pq_flags)) * 272b5a9ee7cSAriel Elior qed_init_qm_get_num_vfs(p_hwfn) + 1; 273b5a9ee7cSAriel Elior } 274b5a9ee7cSAriel Elior 275b5a9ee7cSAriel Elior /* calc amount of PQs according to the requested flags */ 276bf774d14SYueHaibing static u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn) 277b5a9ee7cSAriel Elior { 278b5a9ee7cSAriel Elior u32 pq_flags = qed_get_pq_flags(p_hwfn); 279b5a9ee7cSAriel Elior 280b5a9ee7cSAriel Elior return (!!(PQ_FLAGS_RLS & pq_flags)) * 281b5a9ee7cSAriel Elior qed_init_qm_get_num_pf_rls(p_hwfn) + 282b5a9ee7cSAriel Elior (!!(PQ_FLAGS_MCOS & pq_flags)) * 283b5a9ee7cSAriel Elior qed_init_qm_get_num_tcs(p_hwfn) + 284b5a9ee7cSAriel Elior (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) + 285b5a9ee7cSAriel Elior (!!(PQ_FLAGS_ACK & pq_flags)) + (!!(PQ_FLAGS_OFLD & pq_flags)) + 286b5a9ee7cSAriel Elior (!!(PQ_FLAGS_LLT & pq_flags)) + 287b5a9ee7cSAriel Elior (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn); 288b5a9ee7cSAriel Elior } 289b5a9ee7cSAriel Elior 290b5a9ee7cSAriel Elior /* initialize the top level QM params */ 291b5a9ee7cSAriel Elior static void qed_init_qm_params(struct qed_hwfn *p_hwfn) 292b5a9ee7cSAriel Elior { 293b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 294b5a9ee7cSAriel Elior bool four_port; 295b5a9ee7cSAriel Elior 296b5a9ee7cSAriel Elior /* pq and vport bases for this PF */ 297b5a9ee7cSAriel Elior qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ); 298b5a9ee7cSAriel Elior qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT); 299b5a9ee7cSAriel Elior 300b5a9ee7cSAriel Elior /* rate limiting and weighted fair queueing are always enabled */ 301c7281d59SGustavo A. R. Silva qm_info->vport_rl_en = true; 302c7281d59SGustavo A. R. Silva qm_info->vport_wfq_en = true; 303b5a9ee7cSAriel Elior 304b5a9ee7cSAriel Elior /* TC config is different for AH 4 port */ 30578cea9ffSTomer Tayar four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2; 306b5a9ee7cSAriel Elior 307b5a9ee7cSAriel Elior /* in AH 4 port we have fewer TCs per port */ 308b5a9ee7cSAriel Elior qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 : 309b5a9ee7cSAriel Elior NUM_OF_PHYS_TCS; 310b5a9ee7cSAriel Elior 311b5a9ee7cSAriel Elior /* unless MFW indicated otherwise, ooo_tc == 3 for 312b5a9ee7cSAriel Elior * AH 4-port and 4 otherwise. 313fe56b9e6SYuval Mintz */ 314b5a9ee7cSAriel Elior if (!qm_info->ooo_tc) 315b5a9ee7cSAriel Elior qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC : 316b5a9ee7cSAriel Elior DCBX_TCP_OOO_TC; 317dbb799c3SYuval Mintz } 318dbb799c3SYuval Mintz 319b5a9ee7cSAriel Elior /* initialize qm vport params */ 320b5a9ee7cSAriel Elior static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn) 321b5a9ee7cSAriel Elior { 322b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 323b5a9ee7cSAriel Elior u8 i; 324fe56b9e6SYuval Mintz 325b5a9ee7cSAriel Elior /* all vports participate in weighted fair queueing */ 326b5a9ee7cSAriel Elior for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++) 327b5a9ee7cSAriel Elior qm_info->qm_vport_params[i].vport_wfq = 1; 328fe56b9e6SYuval Mintz } 329fe56b9e6SYuval Mintz 330b5a9ee7cSAriel Elior /* initialize qm port params */ 331b5a9ee7cSAriel Elior static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn) 332b5a9ee7cSAriel Elior { 333fe56b9e6SYuval Mintz /* Initialize qm port parameters */ 33478cea9ffSTomer Tayar u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine; 335b5a9ee7cSAriel Elior 336b5a9ee7cSAriel Elior /* indicate how ooo and high pri traffic is dealt with */ 337b5a9ee7cSAriel Elior active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ? 338b5a9ee7cSAriel Elior ACTIVE_TCS_BMAP_4PORT_K2 : 339b5a9ee7cSAriel Elior ACTIVE_TCS_BMAP; 340b5a9ee7cSAriel Elior 341fe56b9e6SYuval Mintz for (i = 0; i < num_ports; i++) { 342b5a9ee7cSAriel Elior struct init_qm_port_params *p_qm_port = 343b5a9ee7cSAriel Elior &p_hwfn->qm_info.qm_port_params[i]; 344b5a9ee7cSAriel Elior 345fe56b9e6SYuval Mintz p_qm_port->active = 1; 346b5a9ee7cSAriel Elior p_qm_port->active_phys_tcs = active_phys_tcs; 347fe56b9e6SYuval Mintz p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports; 348fe56b9e6SYuval Mintz p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports; 349fe56b9e6SYuval Mintz } 350b5a9ee7cSAriel Elior } 351fe56b9e6SYuval Mintz 352b5a9ee7cSAriel Elior /* Reset the params which must be reset for qm init. QM init may be called as 353b5a9ee7cSAriel Elior * a result of flows other than driver load (e.g. dcbx renegotiation). Other 354b5a9ee7cSAriel Elior * params may be affected by the init but would simply recalculate to the same 355b5a9ee7cSAriel Elior * values. The allocations made for QM init, ports, vports, pqs and vfqs are not 356b5a9ee7cSAriel Elior * affected as these amounts stay the same. 357b5a9ee7cSAriel Elior */ 358b5a9ee7cSAriel Elior static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn) 359b5a9ee7cSAriel Elior { 360b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 361fe56b9e6SYuval Mintz 362b5a9ee7cSAriel Elior qm_info->num_pqs = 0; 363b5a9ee7cSAriel Elior qm_info->num_vports = 0; 364b5a9ee7cSAriel Elior qm_info->num_pf_rls = 0; 365b5a9ee7cSAriel Elior qm_info->num_vf_pqs = 0; 366b5a9ee7cSAriel Elior qm_info->first_vf_pq = 0; 367b5a9ee7cSAriel Elior qm_info->first_mcos_pq = 0; 368b5a9ee7cSAriel Elior qm_info->first_rl_pq = 0; 369b5a9ee7cSAriel Elior } 370fe56b9e6SYuval Mintz 371b5a9ee7cSAriel Elior static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn) 372b5a9ee7cSAriel Elior { 373b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 374b5a9ee7cSAriel Elior 375b5a9ee7cSAriel Elior qm_info->num_vports++; 376b5a9ee7cSAriel Elior 377b5a9ee7cSAriel Elior if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn)) 378b5a9ee7cSAriel Elior DP_ERR(p_hwfn, 379b5a9ee7cSAriel Elior "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n", 380b5a9ee7cSAriel Elior qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn)); 381b5a9ee7cSAriel Elior } 382b5a9ee7cSAriel Elior 383b5a9ee7cSAriel Elior /* initialize a single pq and manage qm_info resources accounting. 384b5a9ee7cSAriel Elior * The pq_init_flags param determines whether the PQ is rate limited 385b5a9ee7cSAriel Elior * (for VF or PF) and whether a new vport is allocated to the pq or not 386b5a9ee7cSAriel Elior * (i.e. vport will be shared). 387b5a9ee7cSAriel Elior */ 388b5a9ee7cSAriel Elior 389b5a9ee7cSAriel Elior /* flags for pq init */ 390b5a9ee7cSAriel Elior #define PQ_INIT_SHARE_VPORT (1 << 0) 391b5a9ee7cSAriel Elior #define PQ_INIT_PF_RL (1 << 1) 392b5a9ee7cSAriel Elior #define PQ_INIT_VF_RL (1 << 2) 393b5a9ee7cSAriel Elior 394b5a9ee7cSAriel Elior /* defines for pq init */ 395b5a9ee7cSAriel Elior #define PQ_INIT_DEFAULT_WRR_GROUP 1 396b5a9ee7cSAriel Elior #define PQ_INIT_DEFAULT_TC 0 397b5a9ee7cSAriel Elior #define PQ_INIT_OFLD_TC (p_hwfn->hw_info.offload_tc) 398b5a9ee7cSAriel Elior 399b5a9ee7cSAriel Elior static void qed_init_qm_pq(struct qed_hwfn *p_hwfn, 400b5a9ee7cSAriel Elior struct qed_qm_info *qm_info, 401b5a9ee7cSAriel Elior u8 tc, u32 pq_init_flags) 402b5a9ee7cSAriel Elior { 403b5a9ee7cSAriel Elior u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn); 404b5a9ee7cSAriel Elior 405b5a9ee7cSAriel Elior if (pq_idx > max_pq) 406b5a9ee7cSAriel Elior DP_ERR(p_hwfn, 407b5a9ee7cSAriel Elior "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq); 408b5a9ee7cSAriel Elior 409b5a9ee7cSAriel Elior /* init pq params */ 41050bc60cbSMichal Kalderon qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id; 411b5a9ee7cSAriel Elior qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport + 412b5a9ee7cSAriel Elior qm_info->num_vports; 413b5a9ee7cSAriel Elior qm_info->qm_pq_params[pq_idx].tc_id = tc; 414b5a9ee7cSAriel Elior qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP; 415b5a9ee7cSAriel Elior qm_info->qm_pq_params[pq_idx].rl_valid = 416b5a9ee7cSAriel Elior (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL); 417b5a9ee7cSAriel Elior 418b5a9ee7cSAriel Elior /* qm params accounting */ 419b5a9ee7cSAriel Elior qm_info->num_pqs++; 420b5a9ee7cSAriel Elior if (!(pq_init_flags & PQ_INIT_SHARE_VPORT)) 421b5a9ee7cSAriel Elior qm_info->num_vports++; 422b5a9ee7cSAriel Elior 423b5a9ee7cSAriel Elior if (pq_init_flags & PQ_INIT_PF_RL) 424b5a9ee7cSAriel Elior qm_info->num_pf_rls++; 425b5a9ee7cSAriel Elior 426b5a9ee7cSAriel Elior if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn)) 427b5a9ee7cSAriel Elior DP_ERR(p_hwfn, 428b5a9ee7cSAriel Elior "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n", 429b5a9ee7cSAriel Elior qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn)); 430b5a9ee7cSAriel Elior 431b5a9ee7cSAriel Elior if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn)) 432b5a9ee7cSAriel Elior DP_ERR(p_hwfn, 433b5a9ee7cSAriel Elior "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n", 434b5a9ee7cSAriel Elior qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn)); 435b5a9ee7cSAriel Elior } 436b5a9ee7cSAriel Elior 437b5a9ee7cSAriel Elior /* get pq index according to PQ_FLAGS */ 438b5a9ee7cSAriel Elior static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn, 439b5a9ee7cSAriel Elior u32 pq_flags) 440b5a9ee7cSAriel Elior { 441b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 442b5a9ee7cSAriel Elior 443b5a9ee7cSAriel Elior /* Can't have multiple flags set here */ 444b5a9ee7cSAriel Elior if (bitmap_weight((unsigned long *)&pq_flags, sizeof(pq_flags)) > 1) 445b5a9ee7cSAriel Elior goto err; 446b5a9ee7cSAriel Elior 447b5a9ee7cSAriel Elior switch (pq_flags) { 448b5a9ee7cSAriel Elior case PQ_FLAGS_RLS: 449b5a9ee7cSAriel Elior return &qm_info->first_rl_pq; 450b5a9ee7cSAriel Elior case PQ_FLAGS_MCOS: 451b5a9ee7cSAriel Elior return &qm_info->first_mcos_pq; 452b5a9ee7cSAriel Elior case PQ_FLAGS_LB: 453b5a9ee7cSAriel Elior return &qm_info->pure_lb_pq; 454b5a9ee7cSAriel Elior case PQ_FLAGS_OOO: 455b5a9ee7cSAriel Elior return &qm_info->ooo_pq; 456b5a9ee7cSAriel Elior case PQ_FLAGS_ACK: 457b5a9ee7cSAriel Elior return &qm_info->pure_ack_pq; 458b5a9ee7cSAriel Elior case PQ_FLAGS_OFLD: 459b5a9ee7cSAriel Elior return &qm_info->offload_pq; 460b5a9ee7cSAriel Elior case PQ_FLAGS_LLT: 461b5a9ee7cSAriel Elior return &qm_info->low_latency_pq; 462b5a9ee7cSAriel Elior case PQ_FLAGS_VFS: 463b5a9ee7cSAriel Elior return &qm_info->first_vf_pq; 464b5a9ee7cSAriel Elior default: 465b5a9ee7cSAriel Elior goto err; 466b5a9ee7cSAriel Elior } 467b5a9ee7cSAriel Elior 468b5a9ee7cSAriel Elior err: 469b5a9ee7cSAriel Elior DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags); 470b5a9ee7cSAriel Elior return NULL; 471b5a9ee7cSAriel Elior } 472b5a9ee7cSAriel Elior 473b5a9ee7cSAriel Elior /* save pq index in qm info */ 474b5a9ee7cSAriel Elior static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn, 475b5a9ee7cSAriel Elior u32 pq_flags, u16 pq_val) 476b5a9ee7cSAriel Elior { 477b5a9ee7cSAriel Elior u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags); 478b5a9ee7cSAriel Elior 479b5a9ee7cSAriel Elior *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val; 480b5a9ee7cSAriel Elior } 481b5a9ee7cSAriel Elior 482b5a9ee7cSAriel Elior /* get tx pq index, with the PQ TX base already set (ready for context init) */ 483b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags) 484b5a9ee7cSAriel Elior { 485b5a9ee7cSAriel Elior u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags); 486b5a9ee7cSAriel Elior 487b5a9ee7cSAriel Elior return *base_pq_idx + CM_TX_PQ_BASE; 488b5a9ee7cSAriel Elior } 489b5a9ee7cSAriel Elior 490b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc) 491b5a9ee7cSAriel Elior { 492b5a9ee7cSAriel Elior u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn); 493b5a9ee7cSAriel Elior 494b5a9ee7cSAriel Elior if (tc > max_tc) 495b5a9ee7cSAriel Elior DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc); 496b5a9ee7cSAriel Elior 497b5a9ee7cSAriel Elior return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc; 498b5a9ee7cSAriel Elior } 499b5a9ee7cSAriel Elior 500b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf) 501b5a9ee7cSAriel Elior { 502b5a9ee7cSAriel Elior u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn); 503b5a9ee7cSAriel Elior 504b5a9ee7cSAriel Elior if (vf > max_vf) 505b5a9ee7cSAriel Elior DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf); 506b5a9ee7cSAriel Elior 507b5a9ee7cSAriel Elior return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf; 508b5a9ee7cSAriel Elior } 509b5a9ee7cSAriel Elior 510b5a9ee7cSAriel Elior /* Functions for creating specific types of pqs */ 511b5a9ee7cSAriel Elior static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn) 512b5a9ee7cSAriel Elior { 513b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 514b5a9ee7cSAriel Elior 515b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB)) 516b5a9ee7cSAriel Elior return; 517b5a9ee7cSAriel Elior 518b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs); 519b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT); 520b5a9ee7cSAriel Elior } 521b5a9ee7cSAriel Elior 522b5a9ee7cSAriel Elior static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn) 523b5a9ee7cSAriel Elior { 524b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 525b5a9ee7cSAriel Elior 526b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO)) 527b5a9ee7cSAriel Elior return; 528b5a9ee7cSAriel Elior 529b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs); 530b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT); 531b5a9ee7cSAriel Elior } 532b5a9ee7cSAriel Elior 533b5a9ee7cSAriel Elior static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn) 534b5a9ee7cSAriel Elior { 535b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 536b5a9ee7cSAriel Elior 537b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK)) 538b5a9ee7cSAriel Elior return; 539b5a9ee7cSAriel Elior 540b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs); 541b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT); 542b5a9ee7cSAriel Elior } 543b5a9ee7cSAriel Elior 544b5a9ee7cSAriel Elior static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn) 545b5a9ee7cSAriel Elior { 546b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 547b5a9ee7cSAriel Elior 548b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD)) 549b5a9ee7cSAriel Elior return; 550b5a9ee7cSAriel Elior 551b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs); 552b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT); 553b5a9ee7cSAriel Elior } 554b5a9ee7cSAriel Elior 555b5a9ee7cSAriel Elior static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn) 556b5a9ee7cSAriel Elior { 557b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 558b5a9ee7cSAriel Elior 559b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT)) 560b5a9ee7cSAriel Elior return; 561b5a9ee7cSAriel Elior 562b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs); 563b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT); 564b5a9ee7cSAriel Elior } 565b5a9ee7cSAriel Elior 566b5a9ee7cSAriel Elior static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn) 567b5a9ee7cSAriel Elior { 568b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 569b5a9ee7cSAriel Elior u8 tc_idx; 570b5a9ee7cSAriel Elior 571b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS)) 572b5a9ee7cSAriel Elior return; 573b5a9ee7cSAriel Elior 574b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs); 575b5a9ee7cSAriel Elior for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++) 576b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT); 577b5a9ee7cSAriel Elior } 578b5a9ee7cSAriel Elior 579b5a9ee7cSAriel Elior static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn) 580b5a9ee7cSAriel Elior { 581b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 582b5a9ee7cSAriel Elior u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn); 583b5a9ee7cSAriel Elior 584b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS)) 585b5a9ee7cSAriel Elior return; 586b5a9ee7cSAriel Elior 587b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs); 5881408cc1fSYuval Mintz qm_info->num_vf_pqs = num_vfs; 589b5a9ee7cSAriel Elior for (vf_idx = 0; vf_idx < num_vfs; vf_idx++) 590b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, 591b5a9ee7cSAriel Elior qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL); 592b5a9ee7cSAriel Elior } 593fe56b9e6SYuval Mintz 594b5a9ee7cSAriel Elior static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn) 595b5a9ee7cSAriel Elior { 596b5a9ee7cSAriel Elior u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn); 597b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 598a64b02d5SManish Chopra 599b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS)) 600b5a9ee7cSAriel Elior return; 601b5a9ee7cSAriel Elior 602b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs); 603b5a9ee7cSAriel Elior for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++) 604b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_PF_RL); 605b5a9ee7cSAriel Elior } 606b5a9ee7cSAriel Elior 607b5a9ee7cSAriel Elior static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn) 608b5a9ee7cSAriel Elior { 609b5a9ee7cSAriel Elior /* rate limited pqs, must come first (FW assumption) */ 610b5a9ee7cSAriel Elior qed_init_qm_rl_pqs(p_hwfn); 611b5a9ee7cSAriel Elior 612b5a9ee7cSAriel Elior /* pqs for multi cos */ 613b5a9ee7cSAriel Elior qed_init_qm_mcos_pqs(p_hwfn); 614b5a9ee7cSAriel Elior 615b5a9ee7cSAriel Elior /* pure loopback pq */ 616b5a9ee7cSAriel Elior qed_init_qm_lb_pq(p_hwfn); 617b5a9ee7cSAriel Elior 618b5a9ee7cSAriel Elior /* out of order pq */ 619b5a9ee7cSAriel Elior qed_init_qm_ooo_pq(p_hwfn); 620b5a9ee7cSAriel Elior 621b5a9ee7cSAriel Elior /* pure ack pq */ 622b5a9ee7cSAriel Elior qed_init_qm_pure_ack_pq(p_hwfn); 623b5a9ee7cSAriel Elior 624b5a9ee7cSAriel Elior /* pq for offloaded protocol */ 625b5a9ee7cSAriel Elior qed_init_qm_offload_pq(p_hwfn); 626b5a9ee7cSAriel Elior 627b5a9ee7cSAriel Elior /* low latency pq */ 628b5a9ee7cSAriel Elior qed_init_qm_low_latency_pq(p_hwfn); 629b5a9ee7cSAriel Elior 630b5a9ee7cSAriel Elior /* done sharing vports */ 631b5a9ee7cSAriel Elior qed_init_qm_advance_vport(p_hwfn); 632b5a9ee7cSAriel Elior 633b5a9ee7cSAriel Elior /* pqs for vfs */ 634b5a9ee7cSAriel Elior qed_init_qm_vf_pqs(p_hwfn); 635b5a9ee7cSAriel Elior } 636b5a9ee7cSAriel Elior 637b5a9ee7cSAriel Elior /* compare values of getters against resources amounts */ 638b5a9ee7cSAriel Elior static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn) 639b5a9ee7cSAriel Elior { 640b5a9ee7cSAriel Elior if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) { 641b5a9ee7cSAriel Elior DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n"); 642b5a9ee7cSAriel Elior return -EINVAL; 643b5a9ee7cSAriel Elior } 644b5a9ee7cSAriel Elior 645b5a9ee7cSAriel Elior if (qed_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, QED_PQ)) { 646b5a9ee7cSAriel Elior DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n"); 647b5a9ee7cSAriel Elior return -EINVAL; 648b5a9ee7cSAriel Elior } 649fe56b9e6SYuval Mintz 650fe56b9e6SYuval Mintz return 0; 651b5a9ee7cSAriel Elior } 652fe56b9e6SYuval Mintz 653b5a9ee7cSAriel Elior static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn) 654b5a9ee7cSAriel Elior { 655b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 656b5a9ee7cSAriel Elior struct init_qm_vport_params *vport; 657b5a9ee7cSAriel Elior struct init_qm_port_params *port; 658b5a9ee7cSAriel Elior struct init_qm_pq_params *pq; 659b5a9ee7cSAriel Elior int i, tc; 660b5a9ee7cSAriel Elior 661b5a9ee7cSAriel Elior /* top level params */ 662b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 663b5a9ee7cSAriel Elior NETIF_MSG_HW, 664b5a9ee7cSAriel Elior "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n", 665b5a9ee7cSAriel Elior qm_info->start_pq, 666b5a9ee7cSAriel Elior qm_info->start_vport, 667b5a9ee7cSAriel Elior qm_info->pure_lb_pq, 668b5a9ee7cSAriel Elior qm_info->offload_pq, qm_info->pure_ack_pq); 669b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 670b5a9ee7cSAriel Elior NETIF_MSG_HW, 671b5a9ee7cSAriel Elior "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n", 672b5a9ee7cSAriel Elior qm_info->ooo_pq, 673b5a9ee7cSAriel Elior qm_info->first_vf_pq, 674b5a9ee7cSAriel Elior qm_info->num_pqs, 675b5a9ee7cSAriel Elior qm_info->num_vf_pqs, 676b5a9ee7cSAriel Elior qm_info->num_vports, qm_info->max_phys_tcs_per_port); 677b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 678b5a9ee7cSAriel Elior NETIF_MSG_HW, 679b5a9ee7cSAriel Elior "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n", 680b5a9ee7cSAriel Elior qm_info->pf_rl_en, 681b5a9ee7cSAriel Elior qm_info->pf_wfq_en, 682b5a9ee7cSAriel Elior qm_info->vport_rl_en, 683b5a9ee7cSAriel Elior qm_info->vport_wfq_en, 684b5a9ee7cSAriel Elior qm_info->pf_wfq, 685b5a9ee7cSAriel Elior qm_info->pf_rl, 686b5a9ee7cSAriel Elior qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn)); 687b5a9ee7cSAriel Elior 688b5a9ee7cSAriel Elior /* port table */ 68978cea9ffSTomer Tayar for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) { 690b5a9ee7cSAriel Elior port = &(qm_info->qm_port_params[i]); 691b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 692b5a9ee7cSAriel Elior NETIF_MSG_HW, 693b5a9ee7cSAriel Elior "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n", 694b5a9ee7cSAriel Elior i, 695b5a9ee7cSAriel Elior port->active, 696b5a9ee7cSAriel Elior port->active_phys_tcs, 697b5a9ee7cSAriel Elior port->num_pbf_cmd_lines, 698b5a9ee7cSAriel Elior port->num_btb_blocks, port->reserved); 699b5a9ee7cSAriel Elior } 700b5a9ee7cSAriel Elior 701b5a9ee7cSAriel Elior /* vport table */ 702b5a9ee7cSAriel Elior for (i = 0; i < qm_info->num_vports; i++) { 703b5a9ee7cSAriel Elior vport = &(qm_info->qm_vport_params[i]); 704b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 705b5a9ee7cSAriel Elior NETIF_MSG_HW, 706b5a9ee7cSAriel Elior "vport idx %d, vport_rl %d, wfq %d, first_tx_pq_id [ ", 707b5a9ee7cSAriel Elior qm_info->start_vport + i, 708b5a9ee7cSAriel Elior vport->vport_rl, vport->vport_wfq); 709b5a9ee7cSAriel Elior for (tc = 0; tc < NUM_OF_TCS; tc++) 710b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 711b5a9ee7cSAriel Elior NETIF_MSG_HW, 712b5a9ee7cSAriel Elior "%d ", vport->first_tx_pq_id[tc]); 713b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n"); 714b5a9ee7cSAriel Elior } 715b5a9ee7cSAriel Elior 716b5a9ee7cSAriel Elior /* pq table */ 717b5a9ee7cSAriel Elior for (i = 0; i < qm_info->num_pqs; i++) { 718b5a9ee7cSAriel Elior pq = &(qm_info->qm_pq_params[i]); 719b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 720b5a9ee7cSAriel Elior NETIF_MSG_HW, 72150bc60cbSMichal Kalderon "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n", 722b5a9ee7cSAriel Elior qm_info->start_pq + i, 72350bc60cbSMichal Kalderon pq->port_id, 724b5a9ee7cSAriel Elior pq->vport_id, 725b5a9ee7cSAriel Elior pq->tc_id, pq->wrr_group, pq->rl_valid); 726b5a9ee7cSAriel Elior } 727b5a9ee7cSAriel Elior } 728b5a9ee7cSAriel Elior 729b5a9ee7cSAriel Elior static void qed_init_qm_info(struct qed_hwfn *p_hwfn) 730b5a9ee7cSAriel Elior { 731b5a9ee7cSAriel Elior /* reset params required for init run */ 732b5a9ee7cSAriel Elior qed_init_qm_reset_params(p_hwfn); 733b5a9ee7cSAriel Elior 734b5a9ee7cSAriel Elior /* init QM top level params */ 735b5a9ee7cSAriel Elior qed_init_qm_params(p_hwfn); 736b5a9ee7cSAriel Elior 737b5a9ee7cSAriel Elior /* init QM port params */ 738b5a9ee7cSAriel Elior qed_init_qm_port_params(p_hwfn); 739b5a9ee7cSAriel Elior 740b5a9ee7cSAriel Elior /* init QM vport params */ 741b5a9ee7cSAriel Elior qed_init_qm_vport_params(p_hwfn); 742b5a9ee7cSAriel Elior 743b5a9ee7cSAriel Elior /* init QM physical queue params */ 744b5a9ee7cSAriel Elior qed_init_qm_pq_params(p_hwfn); 745b5a9ee7cSAriel Elior 746b5a9ee7cSAriel Elior /* display all that init */ 747b5a9ee7cSAriel Elior qed_dp_init_qm_params(p_hwfn); 748fe56b9e6SYuval Mintz } 749fe56b9e6SYuval Mintz 75039651abdSSudarsana Reddy Kalluru /* This function reconfigures the QM pf on the fly. 75139651abdSSudarsana Reddy Kalluru * For this purpose we: 75239651abdSSudarsana Reddy Kalluru * 1. reconfigure the QM database 753a2e7699eSTomer Tayar * 2. set new values to runtime array 75439651abdSSudarsana Reddy Kalluru * 3. send an sdm_qm_cmd through the rbc interface to stop the QM 75539651abdSSudarsana Reddy Kalluru * 4. activate init tool in QM_PF stage 75639651abdSSudarsana Reddy Kalluru * 5. send an sdm_qm_cmd through rbc interface to release the QM 75739651abdSSudarsana Reddy Kalluru */ 75839651abdSSudarsana Reddy Kalluru int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 75939651abdSSudarsana Reddy Kalluru { 76039651abdSSudarsana Reddy Kalluru struct qed_qm_info *qm_info = &p_hwfn->qm_info; 76139651abdSSudarsana Reddy Kalluru bool b_rc; 76239651abdSSudarsana Reddy Kalluru int rc; 76339651abdSSudarsana Reddy Kalluru 76439651abdSSudarsana Reddy Kalluru /* initialize qed's qm data structure */ 765b5a9ee7cSAriel Elior qed_init_qm_info(p_hwfn); 76639651abdSSudarsana Reddy Kalluru 76739651abdSSudarsana Reddy Kalluru /* stop PF's qm queues */ 76839651abdSSudarsana Reddy Kalluru spin_lock_bh(&qm_lock); 76939651abdSSudarsana Reddy Kalluru b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true, 77039651abdSSudarsana Reddy Kalluru qm_info->start_pq, qm_info->num_pqs); 77139651abdSSudarsana Reddy Kalluru spin_unlock_bh(&qm_lock); 77239651abdSSudarsana Reddy Kalluru if (!b_rc) 77339651abdSSudarsana Reddy Kalluru return -EINVAL; 77439651abdSSudarsana Reddy Kalluru 77539651abdSSudarsana Reddy Kalluru /* clear the QM_PF runtime phase leftovers from previous init */ 77639651abdSSudarsana Reddy Kalluru qed_init_clear_rt_data(p_hwfn); 77739651abdSSudarsana Reddy Kalluru 77839651abdSSudarsana Reddy Kalluru /* prepare QM portion of runtime array */ 779da090917STomer Tayar qed_qm_init_pf(p_hwfn, p_ptt, false); 78039651abdSSudarsana Reddy Kalluru 78139651abdSSudarsana Reddy Kalluru /* activate init tool on runtime array */ 78239651abdSSudarsana Reddy Kalluru rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id, 78339651abdSSudarsana Reddy Kalluru p_hwfn->hw_info.hw_mode); 78439651abdSSudarsana Reddy Kalluru if (rc) 78539651abdSSudarsana Reddy Kalluru return rc; 78639651abdSSudarsana Reddy Kalluru 78739651abdSSudarsana Reddy Kalluru /* start PF's qm queues */ 78839651abdSSudarsana Reddy Kalluru spin_lock_bh(&qm_lock); 78939651abdSSudarsana Reddy Kalluru b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true, 79039651abdSSudarsana Reddy Kalluru qm_info->start_pq, qm_info->num_pqs); 79139651abdSSudarsana Reddy Kalluru spin_unlock_bh(&qm_lock); 79239651abdSSudarsana Reddy Kalluru if (!b_rc) 79339651abdSSudarsana Reddy Kalluru return -EINVAL; 79439651abdSSudarsana Reddy Kalluru 79539651abdSSudarsana Reddy Kalluru return 0; 79639651abdSSudarsana Reddy Kalluru } 79739651abdSSudarsana Reddy Kalluru 798b5a9ee7cSAriel Elior static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn) 799b5a9ee7cSAriel Elior { 800b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 801b5a9ee7cSAriel Elior int rc; 802b5a9ee7cSAriel Elior 803b5a9ee7cSAriel Elior rc = qed_init_qm_sanity(p_hwfn); 804b5a9ee7cSAriel Elior if (rc) 805b5a9ee7cSAriel Elior goto alloc_err; 806b5a9ee7cSAriel Elior 8076396bb22SKees Cook qm_info->qm_pq_params = kcalloc(qed_init_qm_get_num_pqs(p_hwfn), 8086396bb22SKees Cook sizeof(*qm_info->qm_pq_params), 809b5a9ee7cSAriel Elior GFP_KERNEL); 810b5a9ee7cSAriel Elior if (!qm_info->qm_pq_params) 811b5a9ee7cSAriel Elior goto alloc_err; 812b5a9ee7cSAriel Elior 8136396bb22SKees Cook qm_info->qm_vport_params = kcalloc(qed_init_qm_get_num_vports(p_hwfn), 8146396bb22SKees Cook sizeof(*qm_info->qm_vport_params), 815b5a9ee7cSAriel Elior GFP_KERNEL); 816b5a9ee7cSAriel Elior if (!qm_info->qm_vport_params) 817b5a9ee7cSAriel Elior goto alloc_err; 818b5a9ee7cSAriel Elior 8196396bb22SKees Cook qm_info->qm_port_params = kcalloc(p_hwfn->cdev->num_ports_in_engine, 8206396bb22SKees Cook sizeof(*qm_info->qm_port_params), 821b5a9ee7cSAriel Elior GFP_KERNEL); 822b5a9ee7cSAriel Elior if (!qm_info->qm_port_params) 823b5a9ee7cSAriel Elior goto alloc_err; 824b5a9ee7cSAriel Elior 8256396bb22SKees Cook qm_info->wfq_data = kcalloc(qed_init_qm_get_num_vports(p_hwfn), 8266396bb22SKees Cook sizeof(*qm_info->wfq_data), 827b5a9ee7cSAriel Elior GFP_KERNEL); 828b5a9ee7cSAriel Elior if (!qm_info->wfq_data) 829b5a9ee7cSAriel Elior goto alloc_err; 830b5a9ee7cSAriel Elior 831b5a9ee7cSAriel Elior return 0; 832b5a9ee7cSAriel Elior 833b5a9ee7cSAriel Elior alloc_err: 834b5a9ee7cSAriel Elior DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n"); 835b5a9ee7cSAriel Elior qed_qm_info_free(p_hwfn); 836b5a9ee7cSAriel Elior return -ENOMEM; 837b5a9ee7cSAriel Elior } 838b5a9ee7cSAriel Elior 839fe56b9e6SYuval Mintz int qed_resc_alloc(struct qed_dev *cdev) 840fe56b9e6SYuval Mintz { 841f9dc4d1fSRam Amrani u32 rdma_tasks, excess_tasks; 842f9dc4d1fSRam Amrani u32 line_count; 843fe56b9e6SYuval Mintz int i, rc = 0; 844fe56b9e6SYuval Mintz 8450db711bbSMintz, Yuval if (IS_VF(cdev)) { 8460db711bbSMintz, Yuval for_each_hwfn(cdev, i) { 8470db711bbSMintz, Yuval rc = qed_l2_alloc(&cdev->hwfns[i]); 8480db711bbSMintz, Yuval if (rc) 8491408cc1fSYuval Mintz return rc; 8500db711bbSMintz, Yuval } 8510db711bbSMintz, Yuval return rc; 8520db711bbSMintz, Yuval } 8531408cc1fSYuval Mintz 854fe56b9e6SYuval Mintz cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL); 855fe56b9e6SYuval Mintz if (!cdev->fw_data) 856fe56b9e6SYuval Mintz return -ENOMEM; 857fe56b9e6SYuval Mintz 858fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 859fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 860dbb799c3SYuval Mintz u32 n_eqes, num_cons; 861fe56b9e6SYuval Mintz 862fe56b9e6SYuval Mintz /* First allocate the context manager structure */ 863fe56b9e6SYuval Mintz rc = qed_cxt_mngr_alloc(p_hwfn); 864fe56b9e6SYuval Mintz if (rc) 865fe56b9e6SYuval Mintz goto alloc_err; 866fe56b9e6SYuval Mintz 867fe56b9e6SYuval Mintz /* Set the HW cid/tid numbers (in the contest manager) 868fe56b9e6SYuval Mintz * Must be done prior to any further computations. 869fe56b9e6SYuval Mintz */ 870f9dc4d1fSRam Amrani rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS); 871fe56b9e6SYuval Mintz if (rc) 872fe56b9e6SYuval Mintz goto alloc_err; 873fe56b9e6SYuval Mintz 874b5a9ee7cSAriel Elior rc = qed_alloc_qm_data(p_hwfn); 875fe56b9e6SYuval Mintz if (rc) 876fe56b9e6SYuval Mintz goto alloc_err; 877fe56b9e6SYuval Mintz 878b5a9ee7cSAriel Elior /* init qm info */ 879b5a9ee7cSAriel Elior qed_init_qm_info(p_hwfn); 880b5a9ee7cSAriel Elior 881fe56b9e6SYuval Mintz /* Compute the ILT client partition */ 882f9dc4d1fSRam Amrani rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count); 883f9dc4d1fSRam Amrani if (rc) { 884f9dc4d1fSRam Amrani DP_NOTICE(p_hwfn, 885f9dc4d1fSRam Amrani "too many ILT lines; re-computing with less lines\n"); 886f9dc4d1fSRam Amrani /* In case there are not enough ILT lines we reduce the 887f9dc4d1fSRam Amrani * number of RDMA tasks and re-compute. 888f9dc4d1fSRam Amrani */ 889f9dc4d1fSRam Amrani excess_tasks = 890f9dc4d1fSRam Amrani qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count); 891f9dc4d1fSRam Amrani if (!excess_tasks) 892f9dc4d1fSRam Amrani goto alloc_err; 893f9dc4d1fSRam Amrani 894f9dc4d1fSRam Amrani rdma_tasks = RDMA_MAX_TIDS - excess_tasks; 895f9dc4d1fSRam Amrani rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks); 896fe56b9e6SYuval Mintz if (rc) 897fe56b9e6SYuval Mintz goto alloc_err; 898fe56b9e6SYuval Mintz 899f9dc4d1fSRam Amrani rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count); 900f9dc4d1fSRam Amrani if (rc) { 901f9dc4d1fSRam Amrani DP_ERR(p_hwfn, 902f9dc4d1fSRam Amrani "failed ILT compute. Requested too many lines: %u\n", 903f9dc4d1fSRam Amrani line_count); 904f9dc4d1fSRam Amrani 905f9dc4d1fSRam Amrani goto alloc_err; 906f9dc4d1fSRam Amrani } 907f9dc4d1fSRam Amrani } 908f9dc4d1fSRam Amrani 909fe56b9e6SYuval Mintz /* CID map / ILT shadow table / T2 910fe56b9e6SYuval Mintz * The talbes sizes are determined by the computations above 911fe56b9e6SYuval Mintz */ 912fe56b9e6SYuval Mintz rc = qed_cxt_tables_alloc(p_hwfn); 913fe56b9e6SYuval Mintz if (rc) 914fe56b9e6SYuval Mintz goto alloc_err; 915fe56b9e6SYuval Mintz 916fe56b9e6SYuval Mintz /* SPQ, must follow ILT because initializes SPQ context */ 917fe56b9e6SYuval Mintz rc = qed_spq_alloc(p_hwfn); 918fe56b9e6SYuval Mintz if (rc) 919fe56b9e6SYuval Mintz goto alloc_err; 920fe56b9e6SYuval Mintz 921fe56b9e6SYuval Mintz /* SP status block allocation */ 922fe56b9e6SYuval Mintz p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn, 923fe56b9e6SYuval Mintz RESERVED_PTT_DPC); 924fe56b9e6SYuval Mintz 925fe56b9e6SYuval Mintz rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt); 926fe56b9e6SYuval Mintz if (rc) 927fe56b9e6SYuval Mintz goto alloc_err; 928fe56b9e6SYuval Mintz 92932a47e72SYuval Mintz rc = qed_iov_alloc(p_hwfn); 93032a47e72SYuval Mintz if (rc) 93132a47e72SYuval Mintz goto alloc_err; 93232a47e72SYuval Mintz 933fe56b9e6SYuval Mintz /* EQ */ 934dbb799c3SYuval Mintz n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain); 935c851a9dcSKalderon, Michal if (QED_IS_RDMA_PERSONALITY(p_hwfn)) { 93667b40dccSKalderon, Michal enum protocol_type rdma_proto; 93767b40dccSKalderon, Michal 93867b40dccSKalderon, Michal if (QED_IS_ROCE_PERSONALITY(p_hwfn)) 93967b40dccSKalderon, Michal rdma_proto = PROTOCOLID_ROCE; 94067b40dccSKalderon, Michal else 94167b40dccSKalderon, Michal rdma_proto = PROTOCOLID_IWARP; 94267b40dccSKalderon, Michal 943dbb799c3SYuval Mintz num_cons = qed_cxt_get_proto_cid_count(p_hwfn, 94467b40dccSKalderon, Michal rdma_proto, 9458c93beafSYuval Mintz NULL) * 2; 946dbb799c3SYuval Mintz n_eqes += num_cons + 2 * MAX_NUM_VFS_BB; 947dbb799c3SYuval Mintz } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 948dbb799c3SYuval Mintz num_cons = 949dbb799c3SYuval Mintz qed_cxt_get_proto_cid_count(p_hwfn, 9508c93beafSYuval Mintz PROTOCOLID_ISCSI, 9518c93beafSYuval Mintz NULL); 952dbb799c3SYuval Mintz n_eqes += 2 * num_cons; 953dbb799c3SYuval Mintz } 954dbb799c3SYuval Mintz 955dbb799c3SYuval Mintz if (n_eqes > 0xFFFF) { 956dbb799c3SYuval Mintz DP_ERR(p_hwfn, 957dbb799c3SYuval Mintz "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n", 958dbb799c3SYuval Mintz n_eqes, 0xFFFF); 9593587cb87STomer Tayar goto alloc_no_mem; 9609b15acbfSDan Carpenter } 961dbb799c3SYuval Mintz 9623587cb87STomer Tayar rc = qed_eq_alloc(p_hwfn, (u16) n_eqes); 9633587cb87STomer Tayar if (rc) 9643587cb87STomer Tayar goto alloc_err; 965fe56b9e6SYuval Mintz 9663587cb87STomer Tayar rc = qed_consq_alloc(p_hwfn); 9673587cb87STomer Tayar if (rc) 9683587cb87STomer Tayar goto alloc_err; 969fe56b9e6SYuval Mintz 9700db711bbSMintz, Yuval rc = qed_l2_alloc(p_hwfn); 9710db711bbSMintz, Yuval if (rc) 9720db711bbSMintz, Yuval goto alloc_err; 9730db711bbSMintz, Yuval 9740a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 9750a7fb11cSYuval Mintz if (p_hwfn->using_ll2) { 9763587cb87STomer Tayar rc = qed_ll2_alloc(p_hwfn); 9773587cb87STomer Tayar if (rc) 9783587cb87STomer Tayar goto alloc_err; 9790a7fb11cSYuval Mintz } 9800a7fb11cSYuval Mintz #endif 9811e128c81SArun Easi 9821e128c81SArun Easi if (p_hwfn->hw_info.personality == QED_PCI_FCOE) { 9833587cb87STomer Tayar rc = qed_fcoe_alloc(p_hwfn); 9843587cb87STomer Tayar if (rc) 9853587cb87STomer Tayar goto alloc_err; 9861e128c81SArun Easi } 9871e128c81SArun Easi 988fc831825SYuval Mintz if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 9893587cb87STomer Tayar rc = qed_iscsi_alloc(p_hwfn); 9903587cb87STomer Tayar if (rc) 9913587cb87STomer Tayar goto alloc_err; 9923587cb87STomer Tayar rc = qed_ooo_alloc(p_hwfn); 9933587cb87STomer Tayar if (rc) 9943587cb87STomer Tayar goto alloc_err; 995fc831825SYuval Mintz } 9960a7fb11cSYuval Mintz 997fe56b9e6SYuval Mintz /* DMA info initialization */ 998fe56b9e6SYuval Mintz rc = qed_dmae_info_alloc(p_hwfn); 9992591c280SJoe Perches if (rc) 1000fe56b9e6SYuval Mintz goto alloc_err; 100139651abdSSudarsana Reddy Kalluru 100239651abdSSudarsana Reddy Kalluru /* DCBX initialization */ 100339651abdSSudarsana Reddy Kalluru rc = qed_dcbx_info_alloc(p_hwfn); 10042591c280SJoe Perches if (rc) 100539651abdSSudarsana Reddy Kalluru goto alloc_err; 100639651abdSSudarsana Reddy Kalluru } 1007fe56b9e6SYuval Mintz 1008fe56b9e6SYuval Mintz cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL); 10092591c280SJoe Perches if (!cdev->reset_stats) 101083aeb933SYuval Mintz goto alloc_no_mem; 1011fe56b9e6SYuval Mintz 1012fe56b9e6SYuval Mintz return 0; 1013fe56b9e6SYuval Mintz 1014dbb799c3SYuval Mintz alloc_no_mem: 1015dbb799c3SYuval Mintz rc = -ENOMEM; 1016fe56b9e6SYuval Mintz alloc_err: 1017fe56b9e6SYuval Mintz qed_resc_free(cdev); 1018fe56b9e6SYuval Mintz return rc; 1019fe56b9e6SYuval Mintz } 1020fe56b9e6SYuval Mintz 1021fe56b9e6SYuval Mintz void qed_resc_setup(struct qed_dev *cdev) 1022fe56b9e6SYuval Mintz { 1023fe56b9e6SYuval Mintz int i; 1024fe56b9e6SYuval Mintz 10250db711bbSMintz, Yuval if (IS_VF(cdev)) { 10260db711bbSMintz, Yuval for_each_hwfn(cdev, i) 10270db711bbSMintz, Yuval qed_l2_setup(&cdev->hwfns[i]); 10281408cc1fSYuval Mintz return; 10290db711bbSMintz, Yuval } 10301408cc1fSYuval Mintz 1031fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 1032fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1033fe56b9e6SYuval Mintz 1034fe56b9e6SYuval Mintz qed_cxt_mngr_setup(p_hwfn); 1035fe56b9e6SYuval Mintz qed_spq_setup(p_hwfn); 10363587cb87STomer Tayar qed_eq_setup(p_hwfn); 10373587cb87STomer Tayar qed_consq_setup(p_hwfn); 1038fe56b9e6SYuval Mintz 1039fe56b9e6SYuval Mintz /* Read shadow of current MFW mailbox */ 1040fe56b9e6SYuval Mintz qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt); 1041fe56b9e6SYuval Mintz memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 1042fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_cur, 1043fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_length); 1044fe56b9e6SYuval Mintz 1045fe56b9e6SYuval Mintz qed_int_setup(p_hwfn, p_hwfn->p_main_ptt); 104632a47e72SYuval Mintz 10470db711bbSMintz, Yuval qed_l2_setup(p_hwfn); 10481ee240e3SMintz, Yuval qed_iov_setup(p_hwfn); 10490a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 10500a7fb11cSYuval Mintz if (p_hwfn->using_ll2) 10513587cb87STomer Tayar qed_ll2_setup(p_hwfn); 10520a7fb11cSYuval Mintz #endif 10531e128c81SArun Easi if (p_hwfn->hw_info.personality == QED_PCI_FCOE) 10543587cb87STomer Tayar qed_fcoe_setup(p_hwfn); 10551e128c81SArun Easi 10561d6cff4fSYuval Mintz if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 10573587cb87STomer Tayar qed_iscsi_setup(p_hwfn); 10583587cb87STomer Tayar qed_ooo_setup(p_hwfn); 10591d6cff4fSYuval Mintz } 1060fe56b9e6SYuval Mintz } 1061fe56b9e6SYuval Mintz } 1062fe56b9e6SYuval Mintz 1063fe56b9e6SYuval Mintz #define FINAL_CLEANUP_POLL_CNT (100) 1064fe56b9e6SYuval Mintz #define FINAL_CLEANUP_POLL_TIME (10) 1065fe56b9e6SYuval Mintz int qed_final_cleanup(struct qed_hwfn *p_hwfn, 10660b55e27dSYuval Mintz struct qed_ptt *p_ptt, u16 id, bool is_vf) 1067fe56b9e6SYuval Mintz { 1068fe56b9e6SYuval Mintz u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT; 1069fe56b9e6SYuval Mintz int rc = -EBUSY; 1070fe56b9e6SYuval Mintz 1071fc48b7a6SYuval Mintz addr = GTT_BAR0_MAP_REG_USDM_RAM + 1072fc48b7a6SYuval Mintz USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id); 1073fe56b9e6SYuval Mintz 10740b55e27dSYuval Mintz if (is_vf) 10750b55e27dSYuval Mintz id += 0x10; 10760b55e27dSYuval Mintz 1077fc48b7a6SYuval Mintz command |= X_FINAL_CLEANUP_AGG_INT << 1078fc48b7a6SYuval Mintz SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT; 1079fc48b7a6SYuval Mintz command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT; 1080fc48b7a6SYuval Mintz command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT; 1081fc48b7a6SYuval Mintz command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT; 1082fe56b9e6SYuval Mintz 1083fe56b9e6SYuval Mintz /* Make sure notification is not set before initiating final cleanup */ 1084fe56b9e6SYuval Mintz if (REG_RD(p_hwfn, addr)) { 10851a635e48SYuval Mintz DP_NOTICE(p_hwfn, 1086fe56b9e6SYuval Mintz "Unexpected; Found final cleanup notification before initiating final cleanup\n"); 1087fe56b9e6SYuval Mintz REG_WR(p_hwfn, addr, 0); 1088fe56b9e6SYuval Mintz } 1089fe56b9e6SYuval Mintz 1090fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_IOV, 1091d602de8eSJoe Perches "Sending final cleanup for PFVF[%d] [Command %08x]\n", 1092fe56b9e6SYuval Mintz id, command); 1093fe56b9e6SYuval Mintz 1094fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command); 1095fe56b9e6SYuval Mintz 1096fe56b9e6SYuval Mintz /* Poll until completion */ 1097fe56b9e6SYuval Mintz while (!REG_RD(p_hwfn, addr) && count--) 1098fe56b9e6SYuval Mintz msleep(FINAL_CLEANUP_POLL_TIME); 1099fe56b9e6SYuval Mintz 1100fe56b9e6SYuval Mintz if (REG_RD(p_hwfn, addr)) 1101fe56b9e6SYuval Mintz rc = 0; 1102fe56b9e6SYuval Mintz else 1103fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 1104fe56b9e6SYuval Mintz "Failed to receive FW final cleanup notification\n"); 1105fe56b9e6SYuval Mintz 1106fe56b9e6SYuval Mintz /* Cleanup afterwards */ 1107fe56b9e6SYuval Mintz REG_WR(p_hwfn, addr, 0); 1108fe56b9e6SYuval Mintz 1109fe56b9e6SYuval Mintz return rc; 1110fe56b9e6SYuval Mintz } 1111fe56b9e6SYuval Mintz 11129c79ddaaSMintz, Yuval static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn) 1113fe56b9e6SYuval Mintz { 1114fe56b9e6SYuval Mintz int hw_mode = 0; 1115fe56b9e6SYuval Mintz 11169c79ddaaSMintz, Yuval if (QED_IS_BB_B0(p_hwfn->cdev)) { 11179c79ddaaSMintz, Yuval hw_mode |= 1 << MODE_BB; 11189c79ddaaSMintz, Yuval } else if (QED_IS_AH(p_hwfn->cdev)) { 11199c79ddaaSMintz, Yuval hw_mode |= 1 << MODE_K2; 11209c79ddaaSMintz, Yuval } else { 11219c79ddaaSMintz, Yuval DP_NOTICE(p_hwfn, "Unknown chip type %#x\n", 11229c79ddaaSMintz, Yuval p_hwfn->cdev->type); 11239c79ddaaSMintz, Yuval return -EINVAL; 11249c79ddaaSMintz, Yuval } 1125fe56b9e6SYuval Mintz 112678cea9ffSTomer Tayar switch (p_hwfn->cdev->num_ports_in_engine) { 1127fe56b9e6SYuval Mintz case 1: 1128fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_PORTS_PER_ENG_1; 1129fe56b9e6SYuval Mintz break; 1130fe56b9e6SYuval Mintz case 2: 1131fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_PORTS_PER_ENG_2; 1132fe56b9e6SYuval Mintz break; 1133fe56b9e6SYuval Mintz case 4: 1134fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_PORTS_PER_ENG_4; 1135fe56b9e6SYuval Mintz break; 1136fe56b9e6SYuval Mintz default: 1137fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n", 113878cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine); 11399c79ddaaSMintz, Yuval return -EINVAL; 1140fe56b9e6SYuval Mintz } 1141fe56b9e6SYuval Mintz 11420bc5fe85SSudarsana Reddy Kalluru if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits)) 1143fc48b7a6SYuval Mintz hw_mode |= 1 << MODE_MF_SD; 11440bc5fe85SSudarsana Reddy Kalluru else 1145fc48b7a6SYuval Mintz hw_mode |= 1 << MODE_MF_SI; 1146fe56b9e6SYuval Mintz 1147fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_ASIC; 1148fe56b9e6SYuval Mintz 11491af9dcf7SYuval Mintz if (p_hwfn->cdev->num_hwfns > 1) 11501af9dcf7SYuval Mintz hw_mode |= 1 << MODE_100G; 11511af9dcf7SYuval Mintz 1152fe56b9e6SYuval Mintz p_hwfn->hw_info.hw_mode = hw_mode; 11531af9dcf7SYuval Mintz 11541af9dcf7SYuval Mintz DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP), 11551af9dcf7SYuval Mintz "Configuring function for hw_mode: 0x%08x\n", 11561af9dcf7SYuval Mintz p_hwfn->hw_info.hw_mode); 11579c79ddaaSMintz, Yuval 11589c79ddaaSMintz, Yuval return 0; 1159fe56b9e6SYuval Mintz } 1160fe56b9e6SYuval Mintz 1161fe56b9e6SYuval Mintz /* Init run time data for all PFs on an engine. */ 1162fe56b9e6SYuval Mintz static void qed_init_cau_rt_data(struct qed_dev *cdev) 1163fe56b9e6SYuval Mintz { 1164fe56b9e6SYuval Mintz u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET; 1165d031548eSMintz, Yuval int i, igu_sb_id; 1166fe56b9e6SYuval Mintz 1167fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 1168fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1169fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 1170fe56b9e6SYuval Mintz struct qed_igu_block *p_block; 1171fe56b9e6SYuval Mintz struct cau_sb_entry sb_entry; 1172fe56b9e6SYuval Mintz 1173fe56b9e6SYuval Mintz p_igu_info = p_hwfn->hw_info.p_igu_info; 1174fe56b9e6SYuval Mintz 1175d031548eSMintz, Yuval for (igu_sb_id = 0; 1176d031548eSMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) { 1177d031548eSMintz, Yuval p_block = &p_igu_info->entry[igu_sb_id]; 1178d031548eSMintz, Yuval 1179fe56b9e6SYuval Mintz if (!p_block->is_pf) 1180fe56b9e6SYuval Mintz continue; 1181fe56b9e6SYuval Mintz 1182fe56b9e6SYuval Mintz qed_init_cau_sb_entry(p_hwfn, &sb_entry, 11831a635e48SYuval Mintz p_block->function_id, 0, 0); 1184d031548eSMintz, Yuval STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2, 1185d031548eSMintz, Yuval sb_entry); 1186fe56b9e6SYuval Mintz } 1187fe56b9e6SYuval Mintz } 1188fe56b9e6SYuval Mintz } 1189fe56b9e6SYuval Mintz 119060afed72STomer Tayar static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn, 119160afed72STomer Tayar struct qed_ptt *p_ptt) 119260afed72STomer Tayar { 119360afed72STomer Tayar u32 val, wr_mbs, cache_line_size; 119460afed72STomer Tayar 119560afed72STomer Tayar val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0); 119660afed72STomer Tayar switch (val) { 119760afed72STomer Tayar case 0: 119860afed72STomer Tayar wr_mbs = 128; 119960afed72STomer Tayar break; 120060afed72STomer Tayar case 1: 120160afed72STomer Tayar wr_mbs = 256; 120260afed72STomer Tayar break; 120360afed72STomer Tayar case 2: 120460afed72STomer Tayar wr_mbs = 512; 120560afed72STomer Tayar break; 120660afed72STomer Tayar default: 120760afed72STomer Tayar DP_INFO(p_hwfn, 120860afed72STomer Tayar "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n", 120960afed72STomer Tayar val); 121060afed72STomer Tayar return; 121160afed72STomer Tayar } 121260afed72STomer Tayar 121360afed72STomer Tayar cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs); 121460afed72STomer Tayar switch (cache_line_size) { 121560afed72STomer Tayar case 32: 121660afed72STomer Tayar val = 0; 121760afed72STomer Tayar break; 121860afed72STomer Tayar case 64: 121960afed72STomer Tayar val = 1; 122060afed72STomer Tayar break; 122160afed72STomer Tayar case 128: 122260afed72STomer Tayar val = 2; 122360afed72STomer Tayar break; 122460afed72STomer Tayar case 256: 122560afed72STomer Tayar val = 3; 122660afed72STomer Tayar break; 122760afed72STomer Tayar default: 122860afed72STomer Tayar DP_INFO(p_hwfn, 122960afed72STomer Tayar "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n", 123060afed72STomer Tayar cache_line_size); 123160afed72STomer Tayar } 123260afed72STomer Tayar 123360afed72STomer Tayar if (L1_CACHE_BYTES > wr_mbs) 123460afed72STomer Tayar DP_INFO(p_hwfn, 123560afed72STomer Tayar "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n", 123660afed72STomer Tayar L1_CACHE_BYTES, wr_mbs); 123760afed72STomer Tayar 123860afed72STomer Tayar STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val); 1239fc6575bcSMintz, Yuval if (val > 0) { 1240fc6575bcSMintz, Yuval STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val); 1241fc6575bcSMintz, Yuval STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val); 1242fc6575bcSMintz, Yuval } 124360afed72STomer Tayar } 124460afed72STomer Tayar 1245fe56b9e6SYuval Mintz static int qed_hw_init_common(struct qed_hwfn *p_hwfn, 12461a635e48SYuval Mintz struct qed_ptt *p_ptt, int hw_mode) 1247fe56b9e6SYuval Mintz { 1248fe56b9e6SYuval Mintz struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1249fe56b9e6SYuval Mintz struct qed_qm_common_rt_init_params params; 1250fe56b9e6SYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 12519c79ddaaSMintz, Yuval u8 vf_id, max_num_vfs; 1252dbb799c3SYuval Mintz u16 num_pfs, pf_id; 12531408cc1fSYuval Mintz u32 concrete_fid; 1254fe56b9e6SYuval Mintz int rc = 0; 1255fe56b9e6SYuval Mintz 1256fe56b9e6SYuval Mintz qed_init_cau_rt_data(cdev); 1257fe56b9e6SYuval Mintz 1258fe56b9e6SYuval Mintz /* Program GTT windows */ 1259fe56b9e6SYuval Mintz qed_gtt_init(p_hwfn); 1260fe56b9e6SYuval Mintz 1261fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 1262fe56b9e6SYuval Mintz if (p_hwfn->mcp_info->func_info.bandwidth_max) 1263c7281d59SGustavo A. R. Silva qm_info->pf_rl_en = true; 1264fe56b9e6SYuval Mintz if (p_hwfn->mcp_info->func_info.bandwidth_min) 1265c7281d59SGustavo A. R. Silva qm_info->pf_wfq_en = true; 1266fe56b9e6SYuval Mintz } 1267fe56b9e6SYuval Mintz 1268fe56b9e6SYuval Mintz memset(¶ms, 0, sizeof(params)); 126978cea9ffSTomer Tayar params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine; 1270fe56b9e6SYuval Mintz params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port; 1271fe56b9e6SYuval Mintz params.pf_rl_en = qm_info->pf_rl_en; 1272fe56b9e6SYuval Mintz params.pf_wfq_en = qm_info->pf_wfq_en; 1273fe56b9e6SYuval Mintz params.vport_rl_en = qm_info->vport_rl_en; 1274fe56b9e6SYuval Mintz params.vport_wfq_en = qm_info->vport_wfq_en; 1275fe56b9e6SYuval Mintz params.port_params = qm_info->qm_port_params; 1276fe56b9e6SYuval Mintz 1277fe56b9e6SYuval Mintz qed_qm_common_rt_init(p_hwfn, ¶ms); 1278fe56b9e6SYuval Mintz 1279fe56b9e6SYuval Mintz qed_cxt_hw_init_common(p_hwfn); 1280fe56b9e6SYuval Mintz 128160afed72STomer Tayar qed_init_cache_line_size(p_hwfn, p_ptt); 128260afed72STomer Tayar 1283fe56b9e6SYuval Mintz rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode); 12841a635e48SYuval Mintz if (rc) 1285fe56b9e6SYuval Mintz return rc; 1286fe56b9e6SYuval Mintz 1287fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0); 1288fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1); 1289fe56b9e6SYuval Mintz 1290dbb799c3SYuval Mintz if (QED_IS_BB(p_hwfn->cdev)) { 1291dbb799c3SYuval Mintz num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev); 1292dbb799c3SYuval Mintz for (pf_id = 0; pf_id < num_pfs; pf_id++) { 1293dbb799c3SYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, pf_id); 1294dbb799c3SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1295dbb799c3SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1296dbb799c3SYuval Mintz } 1297dbb799c3SYuval Mintz /* pretend to original PF */ 1298dbb799c3SYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 1299dbb799c3SYuval Mintz } 1300fe56b9e6SYuval Mintz 13019c79ddaaSMintz, Yuval max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB; 13029c79ddaaSMintz, Yuval for (vf_id = 0; vf_id < max_num_vfs; vf_id++) { 13031408cc1fSYuval Mintz concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id); 13041408cc1fSYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid); 13051408cc1fSYuval Mintz qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1); 130605fafbfbSYuval Mintz qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0); 130705fafbfbSYuval Mintz qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1); 130805fafbfbSYuval Mintz qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0); 13091408cc1fSYuval Mintz } 13101408cc1fSYuval Mintz /* pretend to original PF */ 13111408cc1fSYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 13121408cc1fSYuval Mintz 1313fe56b9e6SYuval Mintz return rc; 1314fe56b9e6SYuval Mintz } 1315fe56b9e6SYuval Mintz 131651ff1725SRam Amrani static int 131751ff1725SRam Amrani qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn, 131851ff1725SRam Amrani struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus) 131951ff1725SRam Amrani { 1320107392b7SRam Amrani u32 dpi_bit_shift, dpi_count, dpi_page_size; 132151ff1725SRam Amrani u32 min_dpis; 1322107392b7SRam Amrani u32 n_wids; 132351ff1725SRam Amrani 132451ff1725SRam Amrani /* Calculate DPI size */ 1325107392b7SRam Amrani n_wids = max_t(u32, QED_MIN_WIDS, n_cpus); 1326107392b7SRam Amrani dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids); 1327107392b7SRam Amrani dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1); 132851ff1725SRam Amrani dpi_bit_shift = ilog2(dpi_page_size / 4096); 132951ff1725SRam Amrani dpi_count = pwm_region_size / dpi_page_size; 133051ff1725SRam Amrani 133151ff1725SRam Amrani min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis; 133251ff1725SRam Amrani min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis); 133351ff1725SRam Amrani 133451ff1725SRam Amrani p_hwfn->dpi_size = dpi_page_size; 133551ff1725SRam Amrani p_hwfn->dpi_count = dpi_count; 133651ff1725SRam Amrani 133751ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift); 133851ff1725SRam Amrani 133951ff1725SRam Amrani if (dpi_count < min_dpis) 134051ff1725SRam Amrani return -EINVAL; 134151ff1725SRam Amrani 134251ff1725SRam Amrani return 0; 134351ff1725SRam Amrani } 134451ff1725SRam Amrani 134551ff1725SRam Amrani enum QED_ROCE_EDPM_MODE { 134651ff1725SRam Amrani QED_ROCE_EDPM_MODE_ENABLE = 0, 134751ff1725SRam Amrani QED_ROCE_EDPM_MODE_FORCE_ON = 1, 134851ff1725SRam Amrani QED_ROCE_EDPM_MODE_DISABLE = 2, 134951ff1725SRam Amrani }; 135051ff1725SRam Amrani 135151ff1725SRam Amrani static int 135251ff1725SRam Amrani qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 135351ff1725SRam Amrani { 135451ff1725SRam Amrani u32 pwm_regsize, norm_regsize; 135551ff1725SRam Amrani u32 non_pwm_conn, min_addr_reg1; 135620b1bd96SRam Amrani u32 db_bar_size, n_cpus = 1; 135751ff1725SRam Amrani u32 roce_edpm_mode; 135851ff1725SRam Amrani u32 pf_dems_shift; 135951ff1725SRam Amrani int rc = 0; 136051ff1725SRam Amrani u8 cond; 136151ff1725SRam Amrani 136215582962SRahul Verma db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1); 136351ff1725SRam Amrani if (p_hwfn->cdev->num_hwfns > 1) 136451ff1725SRam Amrani db_bar_size /= 2; 136551ff1725SRam Amrani 136651ff1725SRam Amrani /* Calculate doorbell regions */ 136751ff1725SRam Amrani non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) + 136851ff1725SRam Amrani qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE, 136951ff1725SRam Amrani NULL) + 137051ff1725SRam Amrani qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, 137151ff1725SRam Amrani NULL); 1372a82dadbcSRam Amrani norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE); 137351ff1725SRam Amrani min_addr_reg1 = norm_regsize / 4096; 137451ff1725SRam Amrani pwm_regsize = db_bar_size - norm_regsize; 137551ff1725SRam Amrani 137651ff1725SRam Amrani /* Check that the normal and PWM sizes are valid */ 137751ff1725SRam Amrani if (db_bar_size < norm_regsize) { 137851ff1725SRam Amrani DP_ERR(p_hwfn->cdev, 137951ff1725SRam Amrani "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n", 138051ff1725SRam Amrani db_bar_size, norm_regsize); 138151ff1725SRam Amrani return -EINVAL; 138251ff1725SRam Amrani } 138351ff1725SRam Amrani 138451ff1725SRam Amrani if (pwm_regsize < QED_MIN_PWM_REGION) { 138551ff1725SRam Amrani DP_ERR(p_hwfn->cdev, 138651ff1725SRam Amrani "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n", 138751ff1725SRam Amrani pwm_regsize, 138851ff1725SRam Amrani QED_MIN_PWM_REGION, db_bar_size, norm_regsize); 138951ff1725SRam Amrani return -EINVAL; 139051ff1725SRam Amrani } 139151ff1725SRam Amrani 139251ff1725SRam Amrani /* Calculate number of DPIs */ 139351ff1725SRam Amrani roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode; 139451ff1725SRam Amrani if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) || 139551ff1725SRam Amrani ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) { 139651ff1725SRam Amrani /* Either EDPM is mandatory, or we are attempting to allocate a 139751ff1725SRam Amrani * WID per CPU. 139851ff1725SRam Amrani */ 1399c2dedf87SRam Amrani n_cpus = num_present_cpus(); 140051ff1725SRam Amrani rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 140151ff1725SRam Amrani } 140251ff1725SRam Amrani 140351ff1725SRam Amrani cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) || 140451ff1725SRam Amrani (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE); 140551ff1725SRam Amrani if (cond || p_hwfn->dcbx_no_edpm) { 140651ff1725SRam Amrani /* Either EDPM is disabled from user configuration, or it is 140751ff1725SRam Amrani * disabled via DCBx, or it is not mandatory and we failed to 140851ff1725SRam Amrani * allocated a WID per CPU. 140951ff1725SRam Amrani */ 141051ff1725SRam Amrani n_cpus = 1; 141151ff1725SRam Amrani rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 141251ff1725SRam Amrani 141351ff1725SRam Amrani if (cond) 141451ff1725SRam Amrani qed_rdma_dpm_bar(p_hwfn, p_ptt); 141551ff1725SRam Amrani } 141651ff1725SRam Amrani 141720b1bd96SRam Amrani p_hwfn->wid_count = (u16) n_cpus; 141820b1bd96SRam Amrani 141951ff1725SRam Amrani DP_INFO(p_hwfn, 142051ff1725SRam Amrani "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n", 142151ff1725SRam Amrani norm_regsize, 142251ff1725SRam Amrani pwm_regsize, 142351ff1725SRam Amrani p_hwfn->dpi_size, 142451ff1725SRam Amrani p_hwfn->dpi_count, 142551ff1725SRam Amrani ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ? 142651ff1725SRam Amrani "disabled" : "enabled"); 142751ff1725SRam Amrani 142851ff1725SRam Amrani if (rc) { 142951ff1725SRam Amrani DP_ERR(p_hwfn, 143051ff1725SRam Amrani "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n", 143151ff1725SRam Amrani p_hwfn->dpi_count, 143251ff1725SRam Amrani p_hwfn->pf_params.rdma_pf_params.min_dpis); 143351ff1725SRam Amrani return -EINVAL; 143451ff1725SRam Amrani } 143551ff1725SRam Amrani 143651ff1725SRam Amrani p_hwfn->dpi_start_offset = norm_regsize; 143751ff1725SRam Amrani 143851ff1725SRam Amrani /* DEMS size is configured log2 of DWORDs, hence the division by 4 */ 143951ff1725SRam Amrani pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4); 144051ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift); 144151ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1); 144251ff1725SRam Amrani 144351ff1725SRam Amrani return 0; 144451ff1725SRam Amrani } 144551ff1725SRam Amrani 1446fe56b9e6SYuval Mintz static int qed_hw_init_port(struct qed_hwfn *p_hwfn, 14471a635e48SYuval Mintz struct qed_ptt *p_ptt, int hw_mode) 1448fe56b9e6SYuval Mintz { 1449fc6575bcSMintz, Yuval int rc = 0; 1450fc6575bcSMintz, Yuval 1451fc6575bcSMintz, Yuval rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode); 1452fc6575bcSMintz, Yuval if (rc) 1453fc6575bcSMintz, Yuval return rc; 1454fc6575bcSMintz, Yuval 1455fc6575bcSMintz, Yuval qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0); 1456fc6575bcSMintz, Yuval 1457fc6575bcSMintz, Yuval return 0; 1458fe56b9e6SYuval Mintz } 1459fe56b9e6SYuval Mintz 1460fe56b9e6SYuval Mintz static int qed_hw_init_pf(struct qed_hwfn *p_hwfn, 1461fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 146219968430SChopra, Manish struct qed_tunnel_info *p_tunn, 1463fe56b9e6SYuval Mintz int hw_mode, 1464fe56b9e6SYuval Mintz bool b_hw_start, 1465fe56b9e6SYuval Mintz enum qed_int_mode int_mode, 1466fe56b9e6SYuval Mintz bool allow_npar_tx_switch) 1467fe56b9e6SYuval Mintz { 1468fe56b9e6SYuval Mintz u8 rel_pf_id = p_hwfn->rel_pf_id; 1469fe56b9e6SYuval Mintz int rc = 0; 1470fe56b9e6SYuval Mintz 1471fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 1472fe56b9e6SYuval Mintz struct qed_mcp_function_info *p_info; 1473fe56b9e6SYuval Mintz 1474fe56b9e6SYuval Mintz p_info = &p_hwfn->mcp_info->func_info; 1475fe56b9e6SYuval Mintz if (p_info->bandwidth_min) 1476fe56b9e6SYuval Mintz p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min; 1477fe56b9e6SYuval Mintz 1478fe56b9e6SYuval Mintz /* Update rate limit once we'll actually have a link */ 14794b01e519SManish Chopra p_hwfn->qm_info.pf_rl = 100000; 1480fe56b9e6SYuval Mintz } 1481fe56b9e6SYuval Mintz 148215582962SRahul Verma qed_cxt_hw_init_pf(p_hwfn, p_ptt); 1483fe56b9e6SYuval Mintz 1484fe56b9e6SYuval Mintz qed_int_igu_init_rt(p_hwfn); 1485fe56b9e6SYuval Mintz 1486fe56b9e6SYuval Mintz /* Set VLAN in NIG if needed */ 14871a635e48SYuval Mintz if (hw_mode & BIT(MODE_MF_SD)) { 1488fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n"); 1489fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1); 1490fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET, 1491fe56b9e6SYuval Mintz p_hwfn->hw_info.ovlan); 1492cac6f691SSudarsana Reddy Kalluru 1493cac6f691SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 1494cac6f691SSudarsana Reddy Kalluru "Configuring LLH_FUNC_FILTER_HDR_SEL\n"); 1495cac6f691SSudarsana Reddy Kalluru STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET, 1496cac6f691SSudarsana Reddy Kalluru 1); 1497fe56b9e6SYuval Mintz } 1498fe56b9e6SYuval Mintz 1499fe56b9e6SYuval Mintz /* Enable classification by MAC if needed */ 15001a635e48SYuval Mintz if (hw_mode & BIT(MODE_MF_SI)) { 1501fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 1502fe56b9e6SYuval Mintz "Configuring TAGMAC_CLS_TYPE\n"); 1503fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, 1504fe56b9e6SYuval Mintz NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1); 1505fe56b9e6SYuval Mintz } 1506fe56b9e6SYuval Mintz 1507a2e7699eSTomer Tayar /* Protocol Configuration */ 1508dbb799c3SYuval Mintz STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 1509dbb799c3SYuval Mintz (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0); 15101e128c81SArun Easi STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 15111e128c81SArun Easi (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0); 1512fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0); 1513fe56b9e6SYuval Mintz 1514fe56b9e6SYuval Mintz /* Cleanup chip from previous driver if such remains exist */ 15150b55e27dSYuval Mintz rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false); 15161a635e48SYuval Mintz if (rc) 1517fe56b9e6SYuval Mintz return rc; 1518fe56b9e6SYuval Mintz 1519da090917STomer Tayar /* Sanity check before the PF init sequence that uses DMAE */ 1520da090917STomer Tayar rc = qed_dmae_sanity(p_hwfn, p_ptt, "pf_phase"); 1521da090917STomer Tayar if (rc) 1522da090917STomer Tayar return rc; 1523da090917STomer Tayar 1524fe56b9e6SYuval Mintz /* PF Init sequence */ 1525fe56b9e6SYuval Mintz rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode); 1526fe56b9e6SYuval Mintz if (rc) 1527fe56b9e6SYuval Mintz return rc; 1528fe56b9e6SYuval Mintz 1529fe56b9e6SYuval Mintz /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */ 1530fe56b9e6SYuval Mintz rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode); 1531fe56b9e6SYuval Mintz if (rc) 1532fe56b9e6SYuval Mintz return rc; 1533fe56b9e6SYuval Mintz 1534fe56b9e6SYuval Mintz /* Pure runtime initializations - directly to the HW */ 1535fe56b9e6SYuval Mintz qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true); 1536fe56b9e6SYuval Mintz 153751ff1725SRam Amrani rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt); 153851ff1725SRam Amrani if (rc) 153951ff1725SRam Amrani return rc; 154051ff1725SRam Amrani 1541fe56b9e6SYuval Mintz if (b_hw_start) { 1542fe56b9e6SYuval Mintz /* enable interrupts */ 1543fe56b9e6SYuval Mintz qed_int_igu_enable(p_hwfn, p_ptt, int_mode); 1544fe56b9e6SYuval Mintz 1545fe56b9e6SYuval Mintz /* send function start command */ 15464f64675fSManish Chopra rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn, 1547831bfb0eSYuval Mintz allow_npar_tx_switch); 15481e128c81SArun Easi if (rc) { 1549fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Function start ramrod failed\n"); 15501e128c81SArun Easi return rc; 15511e128c81SArun Easi } 15521e128c81SArun Easi if (p_hwfn->hw_info.personality == QED_PCI_FCOE) { 15531e128c81SArun Easi qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2)); 15541e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 15551e128c81SArun Easi PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST, 15561e128c81SArun Easi 0x100); 15571e128c81SArun Easi } 1558fe56b9e6SYuval Mintz } 1559fe56b9e6SYuval Mintz return rc; 1560fe56b9e6SYuval Mintz } 1561fe56b9e6SYuval Mintz 1562fe56b9e6SYuval Mintz static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn, 1563fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1564fe56b9e6SYuval Mintz u8 enable) 1565fe56b9e6SYuval Mintz { 1566fe56b9e6SYuval Mintz u32 delay_idx = 0, val, set_val = enable ? 1 : 0; 1567fe56b9e6SYuval Mintz 1568fe56b9e6SYuval Mintz /* Change PF in PXP */ 1569fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 1570fe56b9e6SYuval Mintz PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val); 1571fe56b9e6SYuval Mintz 1572fe56b9e6SYuval Mintz /* wait until value is set - try for 1 second every 50us */ 1573fe56b9e6SYuval Mintz for (delay_idx = 0; delay_idx < 20000; delay_idx++) { 1574fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, 1575fe56b9e6SYuval Mintz PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1576fe56b9e6SYuval Mintz if (val == set_val) 1577fe56b9e6SYuval Mintz break; 1578fe56b9e6SYuval Mintz 1579fe56b9e6SYuval Mintz usleep_range(50, 60); 1580fe56b9e6SYuval Mintz } 1581fe56b9e6SYuval Mintz 1582fe56b9e6SYuval Mintz if (val != set_val) { 1583fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 1584fe56b9e6SYuval Mintz "PFID_ENABLE_MASTER wasn't changed after a second\n"); 1585fe56b9e6SYuval Mintz return -EAGAIN; 1586fe56b9e6SYuval Mintz } 1587fe56b9e6SYuval Mintz 1588fe56b9e6SYuval Mintz return 0; 1589fe56b9e6SYuval Mintz } 1590fe56b9e6SYuval Mintz 1591fe56b9e6SYuval Mintz static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn, 1592fe56b9e6SYuval Mintz struct qed_ptt *p_main_ptt) 1593fe56b9e6SYuval Mintz { 1594fe56b9e6SYuval Mintz /* Read shadow of current MFW mailbox */ 1595fe56b9e6SYuval Mintz qed_mcp_read_mb(p_hwfn, p_main_ptt); 1596fe56b9e6SYuval Mintz memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 15971a635e48SYuval Mintz p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length); 1598fe56b9e6SYuval Mintz } 1599fe56b9e6SYuval Mintz 16005d24bcf1STomer Tayar static void 16015d24bcf1STomer Tayar qed_fill_load_req_params(struct qed_load_req_params *p_load_req, 16025d24bcf1STomer Tayar struct qed_drv_load_params *p_drv_load) 16035d24bcf1STomer Tayar { 16045d24bcf1STomer Tayar memset(p_load_req, 0, sizeof(*p_load_req)); 16055d24bcf1STomer Tayar 16065d24bcf1STomer Tayar p_load_req->drv_role = p_drv_load->is_crash_kernel ? 16075d24bcf1STomer Tayar QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS; 16085d24bcf1STomer Tayar p_load_req->timeout_val = p_drv_load->mfw_timeout_val; 16095d24bcf1STomer Tayar p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset; 16105d24bcf1STomer Tayar p_load_req->override_force_load = p_drv_load->override_force_load; 16115d24bcf1STomer Tayar } 16125d24bcf1STomer Tayar 1613eaf3c0c6SChopra, Manish static int qed_vf_start(struct qed_hwfn *p_hwfn, 1614eaf3c0c6SChopra, Manish struct qed_hw_init_params *p_params) 1615eaf3c0c6SChopra, Manish { 1616eaf3c0c6SChopra, Manish if (p_params->p_tunn) { 1617eaf3c0c6SChopra, Manish qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn); 1618eaf3c0c6SChopra, Manish qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn); 1619eaf3c0c6SChopra, Manish } 1620eaf3c0c6SChopra, Manish 1621c7281d59SGustavo A. R. Silva p_hwfn->b_int_enabled = true; 1622eaf3c0c6SChopra, Manish 1623eaf3c0c6SChopra, Manish return 0; 1624eaf3c0c6SChopra, Manish } 1625eaf3c0c6SChopra, Manish 1626c0c2d0b4SMintz, Yuval int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params) 1627fe56b9e6SYuval Mintz { 16285d24bcf1STomer Tayar struct qed_load_req_params load_req_params; 16290fefbfbaSSudarsana Kalluru u32 load_code, param, drv_mb_param; 16300fefbfbaSSudarsana Kalluru bool b_default_mtu = true; 16310fefbfbaSSudarsana Kalluru struct qed_hwfn *p_hwfn; 16320fefbfbaSSudarsana Kalluru int rc = 0, mfw_rc, i; 1633cac6f691SSudarsana Reddy Kalluru u16 ether_type; 1634fe56b9e6SYuval Mintz 1635c0c2d0b4SMintz, Yuval if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) { 1636bb13ace7SSudarsana Reddy Kalluru DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n"); 1637bb13ace7SSudarsana Reddy Kalluru return -EINVAL; 1638bb13ace7SSudarsana Reddy Kalluru } 1639bb13ace7SSudarsana Reddy Kalluru 16401408cc1fSYuval Mintz if (IS_PF(cdev)) { 1641c0c2d0b4SMintz, Yuval rc = qed_init_fw_data(cdev, p_params->bin_fw_data); 16421a635e48SYuval Mintz if (rc) 1643fe56b9e6SYuval Mintz return rc; 16441408cc1fSYuval Mintz } 1645fe56b9e6SYuval Mintz 1646fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 1647fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1648fe56b9e6SYuval Mintz 16490fefbfbaSSudarsana Kalluru /* If management didn't provide a default, set one of our own */ 16500fefbfbaSSudarsana Kalluru if (!p_hwfn->hw_info.mtu) { 16510fefbfbaSSudarsana Kalluru p_hwfn->hw_info.mtu = 1500; 16520fefbfbaSSudarsana Kalluru b_default_mtu = false; 16530fefbfbaSSudarsana Kalluru } 16540fefbfbaSSudarsana Kalluru 16551408cc1fSYuval Mintz if (IS_VF(cdev)) { 1656eaf3c0c6SChopra, Manish qed_vf_start(p_hwfn, p_params); 16571408cc1fSYuval Mintz continue; 16581408cc1fSYuval Mintz } 16591408cc1fSYuval Mintz 1660fe56b9e6SYuval Mintz /* Enable DMAE in PXP */ 1661fe56b9e6SYuval Mintz rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true); 1662fe56b9e6SYuval Mintz 16639c79ddaaSMintz, Yuval rc = qed_calc_hw_mode(p_hwfn); 16649c79ddaaSMintz, Yuval if (rc) 16659c79ddaaSMintz, Yuval return rc; 1666fe56b9e6SYuval Mintz 1667cac6f691SSudarsana Reddy Kalluru if (IS_PF(cdev) && (test_bit(QED_MF_8021Q_TAGGING, 1668cac6f691SSudarsana Reddy Kalluru &cdev->mf_bits) || 1669cac6f691SSudarsana Reddy Kalluru test_bit(QED_MF_8021AD_TAGGING, 1670cac6f691SSudarsana Reddy Kalluru &cdev->mf_bits))) { 1671cac6f691SSudarsana Reddy Kalluru if (test_bit(QED_MF_8021Q_TAGGING, &cdev->mf_bits)) 1672cac6f691SSudarsana Reddy Kalluru ether_type = ETH_P_8021Q; 1673cac6f691SSudarsana Reddy Kalluru else 1674cac6f691SSudarsana Reddy Kalluru ether_type = ETH_P_8021AD; 1675b51bdfb9SSudarsana Reddy Kalluru STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET, 1676cac6f691SSudarsana Reddy Kalluru ether_type); 1677b51bdfb9SSudarsana Reddy Kalluru STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET, 1678cac6f691SSudarsana Reddy Kalluru ether_type); 1679b51bdfb9SSudarsana Reddy Kalluru STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET, 1680cac6f691SSudarsana Reddy Kalluru ether_type); 1681b51bdfb9SSudarsana Reddy Kalluru STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET, 1682cac6f691SSudarsana Reddy Kalluru ether_type); 1683b51bdfb9SSudarsana Reddy Kalluru } 1684b51bdfb9SSudarsana Reddy Kalluru 16855d24bcf1STomer Tayar qed_fill_load_req_params(&load_req_params, 16865d24bcf1STomer Tayar p_params->p_drv_load_params); 16875d24bcf1STomer Tayar rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, 16885d24bcf1STomer Tayar &load_req_params); 1689fe56b9e6SYuval Mintz if (rc) { 16905d24bcf1STomer Tayar DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n"); 1691fe56b9e6SYuval Mintz return rc; 1692fe56b9e6SYuval Mintz } 1693fe56b9e6SYuval Mintz 16945d24bcf1STomer Tayar load_code = load_req_params.load_code; 1695fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 16965d24bcf1STomer Tayar "Load request was sent. Load code: 0x%x\n", 16975d24bcf1STomer Tayar load_code); 16985d24bcf1STomer Tayar 1699645874e5SSudarsana Reddy Kalluru qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt); 1700645874e5SSudarsana Reddy Kalluru 17015d24bcf1STomer Tayar qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt); 1702fe56b9e6SYuval Mintz 1703fe56b9e6SYuval Mintz p_hwfn->first_on_engine = (load_code == 1704fe56b9e6SYuval Mintz FW_MSG_CODE_DRV_LOAD_ENGINE); 1705fe56b9e6SYuval Mintz 1706fe56b9e6SYuval Mintz switch (load_code) { 1707fe56b9e6SYuval Mintz case FW_MSG_CODE_DRV_LOAD_ENGINE: 1708fe56b9e6SYuval Mintz rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt, 1709fe56b9e6SYuval Mintz p_hwfn->hw_info.hw_mode); 1710fe56b9e6SYuval Mintz if (rc) 1711fe56b9e6SYuval Mintz break; 1712fe56b9e6SYuval Mintz /* Fall into */ 1713fe56b9e6SYuval Mintz case FW_MSG_CODE_DRV_LOAD_PORT: 1714fe56b9e6SYuval Mintz rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt, 1715fe56b9e6SYuval Mintz p_hwfn->hw_info.hw_mode); 1716fe56b9e6SYuval Mintz if (rc) 1717fe56b9e6SYuval Mintz break; 1718fe56b9e6SYuval Mintz 1719fe56b9e6SYuval Mintz /* Fall into */ 1720fe56b9e6SYuval Mintz case FW_MSG_CODE_DRV_LOAD_FUNCTION: 1721fe56b9e6SYuval Mintz rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt, 1722c0c2d0b4SMintz, Yuval p_params->p_tunn, 1723c0c2d0b4SMintz, Yuval p_hwfn->hw_info.hw_mode, 1724c0c2d0b4SMintz, Yuval p_params->b_hw_start, 1725c0c2d0b4SMintz, Yuval p_params->int_mode, 1726c0c2d0b4SMintz, Yuval p_params->allow_npar_tx_switch); 1727fe56b9e6SYuval Mintz break; 1728fe56b9e6SYuval Mintz default: 1729c0c2d0b4SMintz, Yuval DP_NOTICE(p_hwfn, 1730c0c2d0b4SMintz, Yuval "Unexpected load code [0x%08x]", load_code); 1731fe56b9e6SYuval Mintz rc = -EINVAL; 1732fe56b9e6SYuval Mintz break; 1733fe56b9e6SYuval Mintz } 1734fe56b9e6SYuval Mintz 1735fe56b9e6SYuval Mintz if (rc) 1736fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 1737fe56b9e6SYuval Mintz "init phase failed for loadcode 0x%x (rc %d)\n", 1738fe56b9e6SYuval Mintz load_code, rc); 1739fe56b9e6SYuval Mintz 1740fe56b9e6SYuval Mintz /* ACK mfw regardless of success or failure of initialization */ 1741fe56b9e6SYuval Mintz mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1742fe56b9e6SYuval Mintz DRV_MSG_CODE_LOAD_DONE, 1743fe56b9e6SYuval Mintz 0, &load_code, ¶m); 1744fe56b9e6SYuval Mintz if (rc) 1745fe56b9e6SYuval Mintz return rc; 1746fe56b9e6SYuval Mintz if (mfw_rc) { 1747fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n"); 1748fe56b9e6SYuval Mintz return mfw_rc; 1749fe56b9e6SYuval Mintz } 1750fe56b9e6SYuval Mintz 1751fc561c8bSTomer Tayar /* Check if there is a DID mismatch between nvm-cfg/efuse */ 1752fc561c8bSTomer Tayar if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR) 1753fc561c8bSTomer Tayar DP_NOTICE(p_hwfn, 1754fc561c8bSTomer Tayar "warning: device configuration is not supported on this board type. The device may not function as expected.\n"); 1755fc561c8bSTomer Tayar 175639651abdSSudarsana Reddy Kalluru /* send DCBX attention request command */ 175739651abdSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, 175839651abdSSudarsana Reddy Kalluru QED_MSG_DCB, 175939651abdSSudarsana Reddy Kalluru "sending phony dcbx set command to trigger DCBx attention handling\n"); 176039651abdSSudarsana Reddy Kalluru mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 176139651abdSSudarsana Reddy Kalluru DRV_MSG_CODE_SET_DCBX, 176239651abdSSudarsana Reddy Kalluru 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT, 176339651abdSSudarsana Reddy Kalluru &load_code, ¶m); 176439651abdSSudarsana Reddy Kalluru if (mfw_rc) { 176539651abdSSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 176639651abdSSudarsana Reddy Kalluru "Failed to send DCBX attention request\n"); 176739651abdSSudarsana Reddy Kalluru return mfw_rc; 176839651abdSSudarsana Reddy Kalluru } 176939651abdSSudarsana Reddy Kalluru 1770fe56b9e6SYuval Mintz p_hwfn->hw_init_done = true; 1771fe56b9e6SYuval Mintz } 1772fe56b9e6SYuval Mintz 17730fefbfbaSSudarsana Kalluru if (IS_PF(cdev)) { 17740fefbfbaSSudarsana Kalluru p_hwfn = QED_LEADING_HWFN(cdev); 17755d24bcf1STomer Tayar drv_mb_param = STORM_FW_VERSION; 17760fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 17770fefbfbaSSudarsana Kalluru DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER, 17780fefbfbaSSudarsana Kalluru drv_mb_param, &load_code, ¶m); 17790fefbfbaSSudarsana Kalluru if (rc) 17800fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, "Failed to update firmware version\n"); 17810fefbfbaSSudarsana Kalluru 17820fefbfbaSSudarsana Kalluru if (!b_default_mtu) { 17830fefbfbaSSudarsana Kalluru rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt, 17840fefbfbaSSudarsana Kalluru p_hwfn->hw_info.mtu); 17850fefbfbaSSudarsana Kalluru if (rc) 17860fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, 17870fefbfbaSSudarsana Kalluru "Failed to update default mtu\n"); 17880fefbfbaSSudarsana Kalluru } 17890fefbfbaSSudarsana Kalluru 17900fefbfbaSSudarsana Kalluru rc = qed_mcp_ov_update_driver_state(p_hwfn, 17910fefbfbaSSudarsana Kalluru p_hwfn->p_main_ptt, 17920fefbfbaSSudarsana Kalluru QED_OV_DRIVER_STATE_DISABLED); 17930fefbfbaSSudarsana Kalluru if (rc) 17940fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, "Failed to update driver state\n"); 17950fefbfbaSSudarsana Kalluru 17960fefbfbaSSudarsana Kalluru rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt, 1797538f8d00SSudarsana Reddy Kalluru QED_OV_ESWITCH_NONE); 17980fefbfbaSSudarsana Kalluru if (rc) 17990fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, "Failed to update eswitch mode\n"); 18000fefbfbaSSudarsana Kalluru } 18010fefbfbaSSudarsana Kalluru 1802fe56b9e6SYuval Mintz return 0; 1803fe56b9e6SYuval Mintz } 1804fe56b9e6SYuval Mintz 1805fe56b9e6SYuval Mintz #define QED_HW_STOP_RETRY_LIMIT (10) 18061a635e48SYuval Mintz static void qed_hw_timers_stop(struct qed_dev *cdev, 18071a635e48SYuval Mintz struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 18088c925c44SYuval Mintz { 18098c925c44SYuval Mintz int i; 18108c925c44SYuval Mintz 18118c925c44SYuval Mintz /* close timers */ 18128c925c44SYuval Mintz qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0); 18138c925c44SYuval Mintz qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0); 18148c925c44SYuval Mintz 18158c925c44SYuval Mintz for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) { 18168c925c44SYuval Mintz if ((!qed_rd(p_hwfn, p_ptt, 18178c925c44SYuval Mintz TM_REG_PF_SCAN_ACTIVE_CONN)) && 18181a635e48SYuval Mintz (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK))) 18198c925c44SYuval Mintz break; 18208c925c44SYuval Mintz 18218c925c44SYuval Mintz /* Dependent on number of connection/tasks, possibly 18228c925c44SYuval Mintz * 1ms sleep is required between polls 18238c925c44SYuval Mintz */ 18248c925c44SYuval Mintz usleep_range(1000, 2000); 18258c925c44SYuval Mintz } 18268c925c44SYuval Mintz 18278c925c44SYuval Mintz if (i < QED_HW_STOP_RETRY_LIMIT) 18288c925c44SYuval Mintz return; 18298c925c44SYuval Mintz 18308c925c44SYuval Mintz DP_NOTICE(p_hwfn, 18318c925c44SYuval Mintz "Timers linear scans are not over [Connection %02x Tasks %02x]\n", 18328c925c44SYuval Mintz (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN), 18338c925c44SYuval Mintz (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)); 18348c925c44SYuval Mintz } 18358c925c44SYuval Mintz 18368c925c44SYuval Mintz void qed_hw_timers_stop_all(struct qed_dev *cdev) 18378c925c44SYuval Mintz { 18388c925c44SYuval Mintz int j; 18398c925c44SYuval Mintz 18408c925c44SYuval Mintz for_each_hwfn(cdev, j) { 18418c925c44SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 18428c925c44SYuval Mintz struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 18438c925c44SYuval Mintz 18448c925c44SYuval Mintz qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 18458c925c44SYuval Mintz } 18468c925c44SYuval Mintz } 18478c925c44SYuval Mintz 1848fe56b9e6SYuval Mintz int qed_hw_stop(struct qed_dev *cdev) 1849fe56b9e6SYuval Mintz { 18501226337aSTomer Tayar struct qed_hwfn *p_hwfn; 18511226337aSTomer Tayar struct qed_ptt *p_ptt; 18521226337aSTomer Tayar int rc, rc2 = 0; 18538c925c44SYuval Mintz int j; 1854fe56b9e6SYuval Mintz 1855fe56b9e6SYuval Mintz for_each_hwfn(cdev, j) { 18561226337aSTomer Tayar p_hwfn = &cdev->hwfns[j]; 18571226337aSTomer Tayar p_ptt = p_hwfn->p_main_ptt; 1858fe56b9e6SYuval Mintz 1859fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n"); 1860fe56b9e6SYuval Mintz 18611408cc1fSYuval Mintz if (IS_VF(cdev)) { 18620b55e27dSYuval Mintz qed_vf_pf_int_cleanup(p_hwfn); 18631226337aSTomer Tayar rc = qed_vf_pf_reset(p_hwfn); 18641226337aSTomer Tayar if (rc) { 18651226337aSTomer Tayar DP_NOTICE(p_hwfn, 18661226337aSTomer Tayar "qed_vf_pf_reset failed. rc = %d.\n", 18671226337aSTomer Tayar rc); 18681226337aSTomer Tayar rc2 = -EINVAL; 18691226337aSTomer Tayar } 18701408cc1fSYuval Mintz continue; 18711408cc1fSYuval Mintz } 18721408cc1fSYuval Mintz 1873fe56b9e6SYuval Mintz /* mark the hw as uninitialized... */ 1874fe56b9e6SYuval Mintz p_hwfn->hw_init_done = false; 1875fe56b9e6SYuval Mintz 18761226337aSTomer Tayar /* Send unload command to MCP */ 18771226337aSTomer Tayar rc = qed_mcp_unload_req(p_hwfn, p_ptt); 18781226337aSTomer Tayar if (rc) { 18798c925c44SYuval Mintz DP_NOTICE(p_hwfn, 18801226337aSTomer Tayar "Failed sending a UNLOAD_REQ command. rc = %d.\n", 18811226337aSTomer Tayar rc); 18821226337aSTomer Tayar rc2 = -EINVAL; 18831226337aSTomer Tayar } 18841226337aSTomer Tayar 18851226337aSTomer Tayar qed_slowpath_irq_sync(p_hwfn); 18861226337aSTomer Tayar 18871226337aSTomer Tayar /* After this point no MFW attentions are expected, e.g. prevent 18881226337aSTomer Tayar * race between pf stop and dcbx pf update. 18891226337aSTomer Tayar */ 18901226337aSTomer Tayar rc = qed_sp_pf_stop(p_hwfn); 18911226337aSTomer Tayar if (rc) { 18921226337aSTomer Tayar DP_NOTICE(p_hwfn, 18931226337aSTomer Tayar "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n", 18941226337aSTomer Tayar rc); 18951226337aSTomer Tayar rc2 = -EINVAL; 18961226337aSTomer Tayar } 1897fe56b9e6SYuval Mintz 1898fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 1899fe56b9e6SYuval Mintz NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 1900fe56b9e6SYuval Mintz 1901fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1902fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 1903fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 1904fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1905fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 1906fe56b9e6SYuval Mintz 19078c925c44SYuval Mintz qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 1908fe56b9e6SYuval Mintz 1909fe56b9e6SYuval Mintz /* Disable Attention Generation */ 1910fe56b9e6SYuval Mintz qed_int_igu_disable_int(p_hwfn, p_ptt); 1911fe56b9e6SYuval Mintz 1912fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0); 1913fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0); 1914fe56b9e6SYuval Mintz 1915fe56b9e6SYuval Mintz qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true); 1916fe56b9e6SYuval Mintz 1917fe56b9e6SYuval Mintz /* Need to wait 1ms to guarantee SBs are cleared */ 1918fe56b9e6SYuval Mintz usleep_range(1000, 2000); 19191226337aSTomer Tayar 19201226337aSTomer Tayar /* Disable PF in HW blocks */ 19211226337aSTomer Tayar qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0); 19221226337aSTomer Tayar qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0); 19231226337aSTomer Tayar 19241226337aSTomer Tayar qed_mcp_unload_done(p_hwfn, p_ptt); 19251226337aSTomer Tayar if (rc) { 19261226337aSTomer Tayar DP_NOTICE(p_hwfn, 19271226337aSTomer Tayar "Failed sending a UNLOAD_DONE command. rc = %d.\n", 19281226337aSTomer Tayar rc); 19291226337aSTomer Tayar rc2 = -EINVAL; 19301226337aSTomer Tayar } 1931fe56b9e6SYuval Mintz } 1932fe56b9e6SYuval Mintz 19331408cc1fSYuval Mintz if (IS_PF(cdev)) { 19341226337aSTomer Tayar p_hwfn = QED_LEADING_HWFN(cdev); 19351226337aSTomer Tayar p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt; 19361226337aSTomer Tayar 1937fe56b9e6SYuval Mintz /* Disable DMAE in PXP - in CMT, this should only be done for 1938fe56b9e6SYuval Mintz * first hw-function, and only after all transactions have 1939fe56b9e6SYuval Mintz * stopped for all active hw-functions. 1940fe56b9e6SYuval Mintz */ 19411226337aSTomer Tayar rc = qed_change_pci_hwfn(p_hwfn, p_ptt, false); 19421226337aSTomer Tayar if (rc) { 19431226337aSTomer Tayar DP_NOTICE(p_hwfn, 19441226337aSTomer Tayar "qed_change_pci_hwfn failed. rc = %d.\n", rc); 19451226337aSTomer Tayar rc2 = -EINVAL; 19461226337aSTomer Tayar } 19471408cc1fSYuval Mintz } 1948fe56b9e6SYuval Mintz 19491226337aSTomer Tayar return rc2; 1950fe56b9e6SYuval Mintz } 1951fe56b9e6SYuval Mintz 195215582962SRahul Verma int qed_hw_stop_fastpath(struct qed_dev *cdev) 1953cee4d264SManish Chopra { 19548c925c44SYuval Mintz int j; 1955cee4d264SManish Chopra 1956cee4d264SManish Chopra for_each_hwfn(cdev, j) { 1957cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 195815582962SRahul Verma struct qed_ptt *p_ptt; 1959cee4d264SManish Chopra 1960dacd88d6SYuval Mintz if (IS_VF(cdev)) { 1961dacd88d6SYuval Mintz qed_vf_pf_int_cleanup(p_hwfn); 1962dacd88d6SYuval Mintz continue; 1963dacd88d6SYuval Mintz } 196415582962SRahul Verma p_ptt = qed_ptt_acquire(p_hwfn); 196515582962SRahul Verma if (!p_ptt) 196615582962SRahul Verma return -EAGAIN; 1967dacd88d6SYuval Mintz 1968cee4d264SManish Chopra DP_VERBOSE(p_hwfn, 19691a635e48SYuval Mintz NETIF_MSG_IFDOWN, "Shutting down the fastpath\n"); 1970cee4d264SManish Chopra 1971cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, 1972cee4d264SManish Chopra NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 1973cee4d264SManish Chopra 1974cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1975cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 1976cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 1977cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1978cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 1979cee4d264SManish Chopra 1980cee4d264SManish Chopra qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false); 1981cee4d264SManish Chopra 1982cee4d264SManish Chopra /* Need to wait 1ms to guarantee SBs are cleared */ 1983cee4d264SManish Chopra usleep_range(1000, 2000); 198415582962SRahul Verma qed_ptt_release(p_hwfn, p_ptt); 1985cee4d264SManish Chopra } 1986cee4d264SManish Chopra 198715582962SRahul Verma return 0; 198815582962SRahul Verma } 198915582962SRahul Verma 199015582962SRahul Verma int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn) 1991cee4d264SManish Chopra { 199215582962SRahul Verma struct qed_ptt *p_ptt; 199315582962SRahul Verma 1994dacd88d6SYuval Mintz if (IS_VF(p_hwfn->cdev)) 199515582962SRahul Verma return 0; 199615582962SRahul Verma 199715582962SRahul Verma p_ptt = qed_ptt_acquire(p_hwfn); 199815582962SRahul Verma if (!p_ptt) 199915582962SRahul Verma return -EAGAIN; 2000dacd88d6SYuval Mintz 2001f855df22SMichal Kalderon /* If roce info is allocated it means roce is initialized and should 2002f855df22SMichal Kalderon * be enabled in searcher. 2003f855df22SMichal Kalderon */ 2004f855df22SMichal Kalderon if (p_hwfn->p_rdma_info && 2005f855df22SMichal Kalderon p_hwfn->b_rdma_enabled_in_prs) 2006f855df22SMichal Kalderon qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1); 2007f855df22SMichal Kalderon 2008cee4d264SManish Chopra /* Re-open incoming traffic */ 200915582962SRahul Verma qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0); 201015582962SRahul Verma qed_ptt_release(p_hwfn, p_ptt); 201115582962SRahul Verma 201215582962SRahul Verma return 0; 2013cee4d264SManish Chopra } 2014cee4d264SManish Chopra 2015fe56b9e6SYuval Mintz /* Free hwfn memory and resources acquired in hw_hwfn_prepare */ 2016fe56b9e6SYuval Mintz static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn) 2017fe56b9e6SYuval Mintz { 2018fe56b9e6SYuval Mintz qed_ptt_pool_free(p_hwfn); 2019fe56b9e6SYuval Mintz kfree(p_hwfn->hw_info.p_igu_info); 20203587cb87STomer Tayar p_hwfn->hw_info.p_igu_info = NULL; 2021fe56b9e6SYuval Mintz } 2022fe56b9e6SYuval Mintz 2023fe56b9e6SYuval Mintz /* Setup bar access */ 202412e09c69SYuval Mintz static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn) 2025fe56b9e6SYuval Mintz { 2026fe56b9e6SYuval Mintz /* clear indirect access */ 20279c79ddaaSMintz, Yuval if (QED_IS_AH(p_hwfn->cdev)) { 20289c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 20299c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0); 20309c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 20319c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0); 20329c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 20339c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0); 20349c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 20359c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0); 20369c79ddaaSMintz, Yuval } else { 20379c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 20389c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0); 20399c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 20409c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0); 20419c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 20429c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0); 20439c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 20449c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0); 20459c79ddaaSMintz, Yuval } 2046fe56b9e6SYuval Mintz 2047fe56b9e6SYuval Mintz /* Clean Previous errors if such exist */ 2048fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, 20491a635e48SYuval Mintz PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id); 2050fe56b9e6SYuval Mintz 2051fe56b9e6SYuval Mintz /* enable internal target-read */ 2052fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, 2053fe56b9e6SYuval Mintz PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 2054fe56b9e6SYuval Mintz } 2055fe56b9e6SYuval Mintz 2056fe56b9e6SYuval Mintz static void get_function_id(struct qed_hwfn *p_hwfn) 2057fe56b9e6SYuval Mintz { 2058fe56b9e6SYuval Mintz /* ME Register */ 20591a635e48SYuval Mintz p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn, 20601a635e48SYuval Mintz PXP_PF_ME_OPAQUE_ADDR); 2061fe56b9e6SYuval Mintz 2062fe56b9e6SYuval Mintz p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); 2063fe56b9e6SYuval Mintz 2064fe56b9e6SYuval Mintz p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf; 2065fe56b9e6SYuval Mintz p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 2066fe56b9e6SYuval Mintz PXP_CONCRETE_FID_PFID); 2067fe56b9e6SYuval Mintz p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 2068fe56b9e6SYuval Mintz PXP_CONCRETE_FID_PORT); 2069525ef5c0SYuval Mintz 2070525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, 2071525ef5c0SYuval Mintz "Read ME register: Concrete 0x%08x Opaque 0x%04x\n", 2072525ef5c0SYuval Mintz p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid); 2073fe56b9e6SYuval Mintz } 2074fe56b9e6SYuval Mintz 207525c089d7SYuval Mintz static void qed_hw_set_feat(struct qed_hwfn *p_hwfn) 207625c089d7SYuval Mintz { 207725c089d7SYuval Mintz u32 *feat_num = p_hwfn->hw_info.feat_num; 2078ebbdcc66SMintz, Yuval struct qed_sb_cnt_info sb_cnt; 2079810bb1f0SMintz, Yuval u32 non_l2_sbs = 0; 208025c089d7SYuval Mintz 2081ebbdcc66SMintz, Yuval memset(&sb_cnt, 0, sizeof(sb_cnt)); 2082ebbdcc66SMintz, Yuval qed_int_get_num_sbs(p_hwfn, &sb_cnt); 2083ebbdcc66SMintz, Yuval 20840189efb8SYuval Mintz if (IS_ENABLED(CONFIG_QED_RDMA) && 2085c851a9dcSKalderon, Michal QED_IS_RDMA_PERSONALITY(p_hwfn)) { 20860189efb8SYuval Mintz /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide 20870189efb8SYuval Mintz * the status blocks equally between L2 / RoCE but with 20880189efb8SYuval Mintz * consideration as to how many l2 queues / cnqs we have. 208951ff1725SRam Amrani */ 209051ff1725SRam Amrani feat_num[QED_RDMA_CNQ] = 2091ebbdcc66SMintz, Yuval min_t(u32, sb_cnt.cnt / 2, 209251ff1725SRam Amrani RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM)); 2093810bb1f0SMintz, Yuval 2094810bb1f0SMintz, Yuval non_l2_sbs = feat_num[QED_RDMA_CNQ]; 209551ff1725SRam Amrani } 2096c851a9dcSKalderon, Michal if (QED_IS_L2_PERSONALITY(p_hwfn)) { 2097dec26533SMintz, Yuval /* Start by allocating VF queues, then PF's */ 2098dec26533SMintz, Yuval feat_num[QED_VF_L2_QUE] = min_t(u32, 2099dec26533SMintz, Yuval RESC_NUM(p_hwfn, QED_L2_QUEUE), 2100ebbdcc66SMintz, Yuval sb_cnt.iov_cnt); 2101810bb1f0SMintz, Yuval feat_num[QED_PF_L2_QUE] = min_t(u32, 2102ebbdcc66SMintz, Yuval sb_cnt.cnt - non_l2_sbs, 2103dec26533SMintz, Yuval RESC_NUM(p_hwfn, 2104dec26533SMintz, Yuval QED_L2_QUEUE) - 2105dec26533SMintz, Yuval FEAT_NUM(p_hwfn, 2106dec26533SMintz, Yuval QED_VF_L2_QUE)); 2107dec26533SMintz, Yuval } 21085a1f965aSMintz, Yuval 2109c851a9dcSKalderon, Michal if (QED_IS_FCOE_PERSONALITY(p_hwfn)) 21103c5da942SMintz, Yuval feat_num[QED_FCOE_CQ] = min_t(u32, sb_cnt.cnt, 21113c5da942SMintz, Yuval RESC_NUM(p_hwfn, 21123c5da942SMintz, Yuval QED_CMDQS_CQS)); 21133c5da942SMintz, Yuval 2114c851a9dcSKalderon, Michal if (QED_IS_ISCSI_PERSONALITY(p_hwfn)) 2115ebbdcc66SMintz, Yuval feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt, 211608737a3fSMintz, Yuval RESC_NUM(p_hwfn, 211708737a3fSMintz, Yuval QED_CMDQS_CQS)); 21185a1f965aSMintz, Yuval DP_VERBOSE(p_hwfn, 21195a1f965aSMintz, Yuval NETIF_MSG_PROBE, 21203c5da942SMintz, Yuval "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d #SBS=%d\n", 21215a1f965aSMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE), 21225a1f965aSMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE), 21235a1f965aSMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ), 21243c5da942SMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ), 212508737a3fSMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ), 2126ebbdcc66SMintz, Yuval (int)sb_cnt.cnt); 212725c089d7SYuval Mintz } 212825c089d7SYuval Mintz 21299c8517c4STomer Tayar const char *qed_hw_get_resc_name(enum qed_resources res_id) 21302edbff8dSTomer Tayar { 21312edbff8dSTomer Tayar switch (res_id) { 21322edbff8dSTomer Tayar case QED_L2_QUEUE: 21332edbff8dSTomer Tayar return "L2_QUEUE"; 21342edbff8dSTomer Tayar case QED_VPORT: 21352edbff8dSTomer Tayar return "VPORT"; 21362edbff8dSTomer Tayar case QED_RSS_ENG: 21372edbff8dSTomer Tayar return "RSS_ENG"; 21382edbff8dSTomer Tayar case QED_PQ: 21392edbff8dSTomer Tayar return "PQ"; 21402edbff8dSTomer Tayar case QED_RL: 21412edbff8dSTomer Tayar return "RL"; 21422edbff8dSTomer Tayar case QED_MAC: 21432edbff8dSTomer Tayar return "MAC"; 21442edbff8dSTomer Tayar case QED_VLAN: 21452edbff8dSTomer Tayar return "VLAN"; 21462edbff8dSTomer Tayar case QED_RDMA_CNQ_RAM: 21472edbff8dSTomer Tayar return "RDMA_CNQ_RAM"; 21482edbff8dSTomer Tayar case QED_ILT: 21492edbff8dSTomer Tayar return "ILT"; 21502edbff8dSTomer Tayar case QED_LL2_QUEUE: 21512edbff8dSTomer Tayar return "LL2_QUEUE"; 21522edbff8dSTomer Tayar case QED_CMDQS_CQS: 21532edbff8dSTomer Tayar return "CMDQS_CQS"; 21542edbff8dSTomer Tayar case QED_RDMA_STATS_QUEUE: 21552edbff8dSTomer Tayar return "RDMA_STATS_QUEUE"; 21569c8517c4STomer Tayar case QED_BDQ: 21579c8517c4STomer Tayar return "BDQ"; 21589c8517c4STomer Tayar case QED_SB: 21599c8517c4STomer Tayar return "SB"; 21602edbff8dSTomer Tayar default: 21612edbff8dSTomer Tayar return "UNKNOWN_RESOURCE"; 21622edbff8dSTomer Tayar } 21632edbff8dSTomer Tayar } 21642edbff8dSTomer Tayar 21659c8517c4STomer Tayar static int 21669c8517c4STomer Tayar __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, 21679c8517c4STomer Tayar struct qed_ptt *p_ptt, 21689c8517c4STomer Tayar enum qed_resources res_id, 21699c8517c4STomer Tayar u32 resc_max_val, u32 *p_mcp_resp) 21709c8517c4STomer Tayar { 21719c8517c4STomer Tayar int rc; 21729c8517c4STomer Tayar 21739c8517c4STomer Tayar rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id, 21749c8517c4STomer Tayar resc_max_val, p_mcp_resp); 21759c8517c4STomer Tayar if (rc) { 21769c8517c4STomer Tayar DP_NOTICE(p_hwfn, 21779c8517c4STomer Tayar "MFW response failure for a max value setting of resource %d [%s]\n", 21789c8517c4STomer Tayar res_id, qed_hw_get_resc_name(res_id)); 21799c8517c4STomer Tayar return rc; 21809c8517c4STomer Tayar } 21819c8517c4STomer Tayar 21829c8517c4STomer Tayar if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) 21839c8517c4STomer Tayar DP_INFO(p_hwfn, 21849c8517c4STomer Tayar "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n", 21859c8517c4STomer Tayar res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp); 21869c8517c4STomer Tayar 21879c8517c4STomer Tayar return 0; 21889c8517c4STomer Tayar } 21899c8517c4STomer Tayar 21909c8517c4STomer Tayar static int 21919c8517c4STomer Tayar qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 21929c8517c4STomer Tayar { 21939c8517c4STomer Tayar bool b_ah = QED_IS_AH(p_hwfn->cdev); 21949c8517c4STomer Tayar u32 resc_max_val, mcp_resp; 21959c8517c4STomer Tayar u8 res_id; 21969c8517c4STomer Tayar int rc; 21979c8517c4STomer Tayar 21989c8517c4STomer Tayar for (res_id = 0; res_id < QED_MAX_RESC; res_id++) { 21999c8517c4STomer Tayar switch (res_id) { 22009c8517c4STomer Tayar case QED_LL2_QUEUE: 22019c8517c4STomer Tayar resc_max_val = MAX_NUM_LL2_RX_QUEUES; 22029c8517c4STomer Tayar break; 22039c8517c4STomer Tayar case QED_RDMA_CNQ_RAM: 22049c8517c4STomer Tayar /* No need for a case for QED_CMDQS_CQS since 22059c8517c4STomer Tayar * CNQ/CMDQS are the same resource. 22069c8517c4STomer Tayar */ 2207da090917STomer Tayar resc_max_val = NUM_OF_GLOBAL_QUEUES; 22089c8517c4STomer Tayar break; 22099c8517c4STomer Tayar case QED_RDMA_STATS_QUEUE: 22109c8517c4STomer Tayar resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 22119c8517c4STomer Tayar : RDMA_NUM_STATISTIC_COUNTERS_BB; 22129c8517c4STomer Tayar break; 22139c8517c4STomer Tayar case QED_BDQ: 22149c8517c4STomer Tayar resc_max_val = BDQ_NUM_RESOURCES; 22159c8517c4STomer Tayar break; 22169c8517c4STomer Tayar default: 22179c8517c4STomer Tayar continue; 22189c8517c4STomer Tayar } 22199c8517c4STomer Tayar 22209c8517c4STomer Tayar rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id, 22219c8517c4STomer Tayar resc_max_val, &mcp_resp); 22229c8517c4STomer Tayar if (rc) 22239c8517c4STomer Tayar return rc; 22249c8517c4STomer Tayar 22259c8517c4STomer Tayar /* There's no point to continue to the next resource if the 22269c8517c4STomer Tayar * command is not supported by the MFW. 22279c8517c4STomer Tayar * We do continue if the command is supported but the resource 22289c8517c4STomer Tayar * is unknown to the MFW. Such a resource will be later 22299c8517c4STomer Tayar * configured with the default allocation values. 22309c8517c4STomer Tayar */ 22319c8517c4STomer Tayar if (mcp_resp == FW_MSG_CODE_UNSUPPORTED) 22329c8517c4STomer Tayar return -EINVAL; 22339c8517c4STomer Tayar } 22349c8517c4STomer Tayar 22359c8517c4STomer Tayar return 0; 22369c8517c4STomer Tayar } 22379c8517c4STomer Tayar 22389c8517c4STomer Tayar static 22399c8517c4STomer Tayar int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn, 22409c8517c4STomer Tayar enum qed_resources res_id, 22419c8517c4STomer Tayar u32 *p_resc_num, u32 *p_resc_start) 22429c8517c4STomer Tayar { 22439c8517c4STomer Tayar u8 num_funcs = p_hwfn->num_funcs_on_engine; 22449c8517c4STomer Tayar bool b_ah = QED_IS_AH(p_hwfn->cdev); 22459c8517c4STomer Tayar 22469c8517c4STomer Tayar switch (res_id) { 22479c8517c4STomer Tayar case QED_L2_QUEUE: 22489c8517c4STomer Tayar *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 : 22499c8517c4STomer Tayar MAX_NUM_L2_QUEUES_BB) / num_funcs; 22509c8517c4STomer Tayar break; 22519c8517c4STomer Tayar case QED_VPORT: 22529c8517c4STomer Tayar *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 : 22539c8517c4STomer Tayar MAX_NUM_VPORTS_BB) / num_funcs; 22549c8517c4STomer Tayar break; 22559c8517c4STomer Tayar case QED_RSS_ENG: 22569c8517c4STomer Tayar *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 : 22579c8517c4STomer Tayar ETH_RSS_ENGINE_NUM_BB) / num_funcs; 22589c8517c4STomer Tayar break; 22599c8517c4STomer Tayar case QED_PQ: 22609c8517c4STomer Tayar *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 : 22619c8517c4STomer Tayar MAX_QM_TX_QUEUES_BB) / num_funcs; 22629c8517c4STomer Tayar *p_resc_num &= ~0x7; /* The granularity of the PQs is 8 */ 22639c8517c4STomer Tayar break; 22649c8517c4STomer Tayar case QED_RL: 22659c8517c4STomer Tayar *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs; 22669c8517c4STomer Tayar break; 22679c8517c4STomer Tayar case QED_MAC: 22689c8517c4STomer Tayar case QED_VLAN: 22699c8517c4STomer Tayar /* Each VFC resource can accommodate both a MAC and a VLAN */ 22709c8517c4STomer Tayar *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs; 22719c8517c4STomer Tayar break; 22729c8517c4STomer Tayar case QED_ILT: 22739c8517c4STomer Tayar *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 : 22749c8517c4STomer Tayar PXP_NUM_ILT_RECORDS_BB) / num_funcs; 22759c8517c4STomer Tayar break; 22769c8517c4STomer Tayar case QED_LL2_QUEUE: 22779c8517c4STomer Tayar *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs; 22789c8517c4STomer Tayar break; 22799c8517c4STomer Tayar case QED_RDMA_CNQ_RAM: 22809c8517c4STomer Tayar case QED_CMDQS_CQS: 22819c8517c4STomer Tayar /* CNQ/CMDQS are the same resource */ 2282da090917STomer Tayar *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs; 22839c8517c4STomer Tayar break; 22849c8517c4STomer Tayar case QED_RDMA_STATS_QUEUE: 22859c8517c4STomer Tayar *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 : 22869c8517c4STomer Tayar RDMA_NUM_STATISTIC_COUNTERS_BB) / num_funcs; 22879c8517c4STomer Tayar break; 22889c8517c4STomer Tayar case QED_BDQ: 22899c8517c4STomer Tayar if (p_hwfn->hw_info.personality != QED_PCI_ISCSI && 22909c8517c4STomer Tayar p_hwfn->hw_info.personality != QED_PCI_FCOE) 22919c8517c4STomer Tayar *p_resc_num = 0; 22929c8517c4STomer Tayar else 22939c8517c4STomer Tayar *p_resc_num = 1; 22949c8517c4STomer Tayar break; 22959c8517c4STomer Tayar case QED_SB: 2296ebbdcc66SMintz, Yuval /* Since we want its value to reflect whether MFW supports 2297ebbdcc66SMintz, Yuval * the new scheme, have a default of 0. 2298ebbdcc66SMintz, Yuval */ 2299ebbdcc66SMintz, Yuval *p_resc_num = 0; 23009c8517c4STomer Tayar break; 23019c8517c4STomer Tayar default: 23029c8517c4STomer Tayar return -EINVAL; 23039c8517c4STomer Tayar } 23049c8517c4STomer Tayar 23059c8517c4STomer Tayar switch (res_id) { 23069c8517c4STomer Tayar case QED_BDQ: 23079c8517c4STomer Tayar if (!*p_resc_num) 23089c8517c4STomer Tayar *p_resc_start = 0; 230978cea9ffSTomer Tayar else if (p_hwfn->cdev->num_ports_in_engine == 4) 23109c8517c4STomer Tayar *p_resc_start = p_hwfn->port_id; 23119c8517c4STomer Tayar else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) 23129c8517c4STomer Tayar *p_resc_start = p_hwfn->port_id; 23139c8517c4STomer Tayar else if (p_hwfn->hw_info.personality == QED_PCI_FCOE) 23149c8517c4STomer Tayar *p_resc_start = p_hwfn->port_id + 2; 23159c8517c4STomer Tayar break; 23169c8517c4STomer Tayar default: 23179c8517c4STomer Tayar *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx; 23189c8517c4STomer Tayar break; 23199c8517c4STomer Tayar } 23209c8517c4STomer Tayar 23219c8517c4STomer Tayar return 0; 23229c8517c4STomer Tayar } 23239c8517c4STomer Tayar 23249c8517c4STomer Tayar static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn, 23252edbff8dSTomer Tayar enum qed_resources res_id) 23262edbff8dSTomer Tayar { 23279c8517c4STomer Tayar u32 dflt_resc_num = 0, dflt_resc_start = 0; 23289c8517c4STomer Tayar u32 mcp_resp, *p_resc_num, *p_resc_start; 23292edbff8dSTomer Tayar int rc; 23302edbff8dSTomer Tayar 23312edbff8dSTomer Tayar p_resc_num = &RESC_NUM(p_hwfn, res_id); 23322edbff8dSTomer Tayar p_resc_start = &RESC_START(p_hwfn, res_id); 23332edbff8dSTomer Tayar 23349c8517c4STomer Tayar rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num, 23359c8517c4STomer Tayar &dflt_resc_start); 23369c8517c4STomer Tayar if (rc) { 23372edbff8dSTomer Tayar DP_ERR(p_hwfn, 23382edbff8dSTomer Tayar "Failed to get default amount for resource %d [%s]\n", 23392edbff8dSTomer Tayar res_id, qed_hw_get_resc_name(res_id)); 23409c8517c4STomer Tayar return rc; 23412edbff8dSTomer Tayar } 23422edbff8dSTomer Tayar 23439c8517c4STomer Tayar rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id, 23449c8517c4STomer Tayar &mcp_resp, p_resc_num, p_resc_start); 23452edbff8dSTomer Tayar if (rc) { 23462edbff8dSTomer Tayar DP_NOTICE(p_hwfn, 23472edbff8dSTomer Tayar "MFW response failure for an allocation request for resource %d [%s]\n", 23482edbff8dSTomer Tayar res_id, qed_hw_get_resc_name(res_id)); 23492edbff8dSTomer Tayar return rc; 23502edbff8dSTomer Tayar } 23512edbff8dSTomer Tayar 23522edbff8dSTomer Tayar /* Default driver values are applied in the following cases: 23532edbff8dSTomer Tayar * - The resource allocation MB command is not supported by the MFW 23542edbff8dSTomer Tayar * - There is an internal error in the MFW while processing the request 23552edbff8dSTomer Tayar * - The resource ID is unknown to the MFW 23562edbff8dSTomer Tayar */ 23579c8517c4STomer Tayar if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) { 23589c8517c4STomer Tayar DP_INFO(p_hwfn, 23599c8517c4STomer Tayar "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n", 23602edbff8dSTomer Tayar res_id, 23612edbff8dSTomer Tayar qed_hw_get_resc_name(res_id), 23622edbff8dSTomer Tayar mcp_resp, dflt_resc_num, dflt_resc_start); 23632edbff8dSTomer Tayar *p_resc_num = dflt_resc_num; 23642edbff8dSTomer Tayar *p_resc_start = dflt_resc_start; 23652edbff8dSTomer Tayar goto out; 23662edbff8dSTomer Tayar } 23672edbff8dSTomer Tayar 23682edbff8dSTomer Tayar out: 23692edbff8dSTomer Tayar /* PQs have to divide by 8 [that's the HW granularity]. 23702edbff8dSTomer Tayar * Reduce number so it would fit. 23712edbff8dSTomer Tayar */ 23722edbff8dSTomer Tayar if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) { 23732edbff8dSTomer Tayar DP_INFO(p_hwfn, 23742edbff8dSTomer Tayar "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n", 23752edbff8dSTomer Tayar *p_resc_num, 23762edbff8dSTomer Tayar (*p_resc_num) & ~0x7, 23772edbff8dSTomer Tayar *p_resc_start, (*p_resc_start) & ~0x7); 23782edbff8dSTomer Tayar *p_resc_num &= ~0x7; 23792edbff8dSTomer Tayar *p_resc_start &= ~0x7; 23802edbff8dSTomer Tayar } 23812edbff8dSTomer Tayar 23822edbff8dSTomer Tayar return 0; 23832edbff8dSTomer Tayar } 23842edbff8dSTomer Tayar 23859c8517c4STomer Tayar static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn) 2386fe56b9e6SYuval Mintz { 23879c8517c4STomer Tayar int rc; 23889c8517c4STomer Tayar u8 res_id; 23899c8517c4STomer Tayar 23909c8517c4STomer Tayar for (res_id = 0; res_id < QED_MAX_RESC; res_id++) { 23919c8517c4STomer Tayar rc = __qed_hw_set_resc_info(p_hwfn, res_id); 23929c8517c4STomer Tayar if (rc) 23939c8517c4STomer Tayar return rc; 23949c8517c4STomer Tayar } 23959c8517c4STomer Tayar 23969c8517c4STomer Tayar return 0; 23979c8517c4STomer Tayar } 23989c8517c4STomer Tayar 23999c8517c4STomer Tayar static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 24009c8517c4STomer Tayar { 24019c8517c4STomer Tayar struct qed_resc_unlock_params resc_unlock_params; 24029c8517c4STomer Tayar struct qed_resc_lock_params resc_lock_params; 24039c79ddaaSMintz, Yuval bool b_ah = QED_IS_AH(p_hwfn->cdev); 24042edbff8dSTomer Tayar u8 res_id; 24052edbff8dSTomer Tayar int rc; 2406fe56b9e6SYuval Mintz 24079c8517c4STomer Tayar /* Setting the max values of the soft resources and the following 24089c8517c4STomer Tayar * resources allocation queries should be atomic. Since several PFs can 24099c8517c4STomer Tayar * run in parallel - a resource lock is needed. 24109c8517c4STomer Tayar * If either the resource lock or resource set value commands are not 24119c8517c4STomer Tayar * supported - skip the the max values setting, release the lock if 24129c8517c4STomer Tayar * needed, and proceed to the queries. Other failures, including a 24139c8517c4STomer Tayar * failure to acquire the lock, will cause this function to fail. 24149c8517c4STomer Tayar */ 2415f470f22cSsudarsana.kalluru@cavium.com qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params, 2416f470f22cSsudarsana.kalluru@cavium.com QED_RESC_LOCK_RESC_ALLOC, false); 24179c8517c4STomer Tayar 24189c8517c4STomer Tayar rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params); 24199c8517c4STomer Tayar if (rc && rc != -EINVAL) { 24202edbff8dSTomer Tayar return rc; 24219c8517c4STomer Tayar } else if (rc == -EINVAL) { 24229c8517c4STomer Tayar DP_INFO(p_hwfn, 24239c8517c4STomer Tayar "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n"); 24249c8517c4STomer Tayar } else if (!rc && !resc_lock_params.b_granted) { 24259c8517c4STomer Tayar DP_NOTICE(p_hwfn, 24269c8517c4STomer Tayar "Failed to acquire the resource lock for the resource allocation commands\n"); 24279c8517c4STomer Tayar return -EBUSY; 24289c8517c4STomer Tayar } else { 24299c8517c4STomer Tayar rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt); 24309c8517c4STomer Tayar if (rc && rc != -EINVAL) { 24319c8517c4STomer Tayar DP_NOTICE(p_hwfn, 24329c8517c4STomer Tayar "Failed to set the max values of the soft resources\n"); 24339c8517c4STomer Tayar goto unlock_and_exit; 24349c8517c4STomer Tayar } else if (rc == -EINVAL) { 24359c8517c4STomer Tayar DP_INFO(p_hwfn, 24369c8517c4STomer Tayar "Skip the max values setting of the soft resources since it is not supported by the MFW\n"); 24379c8517c4STomer Tayar rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, 24389c8517c4STomer Tayar &resc_unlock_params); 24399c8517c4STomer Tayar if (rc) 24409c8517c4STomer Tayar DP_INFO(p_hwfn, 24419c8517c4STomer Tayar "Failed to release the resource lock for the resource allocation commands\n"); 24429c8517c4STomer Tayar } 24439c8517c4STomer Tayar } 24449c8517c4STomer Tayar 24459c8517c4STomer Tayar rc = qed_hw_set_resc_info(p_hwfn); 24469c8517c4STomer Tayar if (rc) 24479c8517c4STomer Tayar goto unlock_and_exit; 24489c8517c4STomer Tayar 24499c8517c4STomer Tayar if (resc_lock_params.b_granted && !resc_unlock_params.b_released) { 24509c8517c4STomer Tayar rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params); 24519c8517c4STomer Tayar if (rc) 24529c8517c4STomer Tayar DP_INFO(p_hwfn, 24539c8517c4STomer Tayar "Failed to release the resource lock for the resource allocation commands\n"); 24542edbff8dSTomer Tayar } 2455dbb799c3SYuval Mintz 2456dbb799c3SYuval Mintz /* Sanity for ILT */ 24579c79ddaaSMintz, Yuval if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) || 24589c79ddaaSMintz, Yuval (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) { 2459dbb799c3SYuval Mintz DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n", 2460dbb799c3SYuval Mintz RESC_START(p_hwfn, QED_ILT), 2461dbb799c3SYuval Mintz RESC_END(p_hwfn, QED_ILT) - 1); 2462dbb799c3SYuval Mintz return -EINVAL; 2463dbb799c3SYuval Mintz } 2464fe56b9e6SYuval Mintz 2465ebbdcc66SMintz, Yuval /* This will also learn the number of SBs from MFW */ 2466ebbdcc66SMintz, Yuval if (qed_int_igu_reset_cam(p_hwfn, p_ptt)) 2467ebbdcc66SMintz, Yuval return -EINVAL; 2468ebbdcc66SMintz, Yuval 246925c089d7SYuval Mintz qed_hw_set_feat(p_hwfn); 247025c089d7SYuval Mintz 24712edbff8dSTomer Tayar for (res_id = 0; res_id < QED_MAX_RESC; res_id++) 24722edbff8dSTomer Tayar DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n", 24732edbff8dSTomer Tayar qed_hw_get_resc_name(res_id), 24742edbff8dSTomer Tayar RESC_NUM(p_hwfn, res_id), 24752edbff8dSTomer Tayar RESC_START(p_hwfn, res_id)); 2476dbb799c3SYuval Mintz 2477dbb799c3SYuval Mintz return 0; 24789c8517c4STomer Tayar 24799c8517c4STomer Tayar unlock_and_exit: 24809c8517c4STomer Tayar if (resc_lock_params.b_granted && !resc_unlock_params.b_released) 24819c8517c4STomer Tayar qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params); 24829c8517c4STomer Tayar return rc; 2483fe56b9e6SYuval Mintz } 2484fe56b9e6SYuval Mintz 24851a635e48SYuval Mintz static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2486fe56b9e6SYuval Mintz { 2487fc48b7a6SYuval Mintz u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities; 24881e128c81SArun Easi u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg; 2489645874e5SSudarsana Reddy Kalluru struct qed_mcp_link_capabilities *p_caps; 2490cc875c2eSYuval Mintz struct qed_mcp_link_params *link; 2491fe56b9e6SYuval Mintz 2492fe56b9e6SYuval Mintz /* Read global nvm_cfg address */ 2493fe56b9e6SYuval Mintz nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 2494fe56b9e6SYuval Mintz 2495fe56b9e6SYuval Mintz /* Verify MCP has initialized it */ 2496fe56b9e6SYuval Mintz if (!nvm_cfg_addr) { 2497fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 2498fe56b9e6SYuval Mintz return -EINVAL; 2499fe56b9e6SYuval Mintz } 2500fe56b9e6SYuval Mintz 2501fe56b9e6SYuval Mintz /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */ 2502fe56b9e6SYuval Mintz nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 2503fe56b9e6SYuval Mintz 2504cc875c2eSYuval Mintz addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2505cc875c2eSYuval Mintz offsetof(struct nvm_cfg1, glob) + 2506cc875c2eSYuval Mintz offsetof(struct nvm_cfg1_glob, core_cfg); 2507cc875c2eSYuval Mintz 2508cc875c2eSYuval Mintz core_cfg = qed_rd(p_hwfn, p_ptt, addr); 2509cc875c2eSYuval Mintz 2510cc875c2eSYuval Mintz switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >> 2511cc875c2eSYuval Mintz NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) { 2512351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G: 2513cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G; 2514cc875c2eSYuval Mintz break; 2515351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G: 2516cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G; 2517cc875c2eSYuval Mintz break; 2518351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G: 2519cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G; 2520cc875c2eSYuval Mintz break; 2521351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F: 2522cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F; 2523cc875c2eSYuval Mintz break; 2524351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E: 2525cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E; 2526cc875c2eSYuval Mintz break; 2527351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G: 2528cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G; 2529cc875c2eSYuval Mintz break; 2530351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G: 2531cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G; 2532cc875c2eSYuval Mintz break; 2533351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G: 2534cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G; 2535cc875c2eSYuval Mintz break; 25369c79ddaaSMintz, Yuval case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G: 25379c79ddaaSMintz, Yuval p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G; 25389c79ddaaSMintz, Yuval break; 2539351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G: 2540cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G; 2541cc875c2eSYuval Mintz break; 25429c79ddaaSMintz, Yuval case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G: 25439c79ddaaSMintz, Yuval p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G; 25449c79ddaaSMintz, Yuval break; 2545cc875c2eSYuval Mintz default: 25461a635e48SYuval Mintz DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg); 2547cc875c2eSYuval Mintz break; 2548cc875c2eSYuval Mintz } 2549cc875c2eSYuval Mintz 2550cc875c2eSYuval Mintz /* Read default link configuration */ 2551cc875c2eSYuval Mintz link = &p_hwfn->mcp_info->link_input; 2552645874e5SSudarsana Reddy Kalluru p_caps = &p_hwfn->mcp_info->link_capabilities; 2553cc875c2eSYuval Mintz port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2554cc875c2eSYuval Mintz offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 2555cc875c2eSYuval Mintz link_temp = qed_rd(p_hwfn, p_ptt, 2556cc875c2eSYuval Mintz port_cfg_addr + 2557cc875c2eSYuval Mintz offsetof(struct nvm_cfg1_port, speed_cap_mask)); 255883aeb933SYuval Mintz link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK; 255983aeb933SYuval Mintz link->speed.advertised_speeds = link_temp; 2560cc875c2eSYuval Mintz 256183aeb933SYuval Mintz link_temp = link->speed.advertised_speeds; 256283aeb933SYuval Mintz p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp; 2563cc875c2eSYuval Mintz 2564cc875c2eSYuval Mintz link_temp = qed_rd(p_hwfn, p_ptt, 2565cc875c2eSYuval Mintz port_cfg_addr + 2566cc875c2eSYuval Mintz offsetof(struct nvm_cfg1_port, link_settings)); 2567cc875c2eSYuval Mintz switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >> 2568cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) { 2569cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG: 2570cc875c2eSYuval Mintz link->speed.autoneg = true; 2571cc875c2eSYuval Mintz break; 2572cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_1G: 2573cc875c2eSYuval Mintz link->speed.forced_speed = 1000; 2574cc875c2eSYuval Mintz break; 2575cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_10G: 2576cc875c2eSYuval Mintz link->speed.forced_speed = 10000; 2577cc875c2eSYuval Mintz break; 2578cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_25G: 2579cc875c2eSYuval Mintz link->speed.forced_speed = 25000; 2580cc875c2eSYuval Mintz break; 2581cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_40G: 2582cc875c2eSYuval Mintz link->speed.forced_speed = 40000; 2583cc875c2eSYuval Mintz break; 2584cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_50G: 2585cc875c2eSYuval Mintz link->speed.forced_speed = 50000; 2586cc875c2eSYuval Mintz break; 2587351a4dedSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G: 2588cc875c2eSYuval Mintz link->speed.forced_speed = 100000; 2589cc875c2eSYuval Mintz break; 2590cc875c2eSYuval Mintz default: 25911a635e48SYuval Mintz DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp); 2592cc875c2eSYuval Mintz } 2593cc875c2eSYuval Mintz 259434f9199cSsudarsana.kalluru@cavium.com p_hwfn->mcp_info->link_capabilities.default_speed_autoneg = 259534f9199cSsudarsana.kalluru@cavium.com link->speed.autoneg; 259634f9199cSsudarsana.kalluru@cavium.com 2597cc875c2eSYuval Mintz link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK; 2598cc875c2eSYuval Mintz link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET; 2599cc875c2eSYuval Mintz link->pause.autoneg = !!(link_temp & 2600cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG); 2601cc875c2eSYuval Mintz link->pause.forced_rx = !!(link_temp & 2602cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX); 2603cc875c2eSYuval Mintz link->pause.forced_tx = !!(link_temp & 2604cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX); 2605cc875c2eSYuval Mintz link->loopback_mode = 0; 2606cc875c2eSYuval Mintz 2607645874e5SSudarsana Reddy Kalluru if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) { 2608645874e5SSudarsana Reddy Kalluru link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr + 2609645874e5SSudarsana Reddy Kalluru offsetof(struct nvm_cfg1_port, ext_phy)); 2610645874e5SSudarsana Reddy Kalluru link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK; 2611645874e5SSudarsana Reddy Kalluru link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET; 2612645874e5SSudarsana Reddy Kalluru p_caps->default_eee = QED_MCP_EEE_ENABLED; 2613645874e5SSudarsana Reddy Kalluru link->eee.enable = true; 2614645874e5SSudarsana Reddy Kalluru switch (link_temp) { 2615645874e5SSudarsana Reddy Kalluru case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED: 2616645874e5SSudarsana Reddy Kalluru p_caps->default_eee = QED_MCP_EEE_DISABLED; 2617645874e5SSudarsana Reddy Kalluru link->eee.enable = false; 2618645874e5SSudarsana Reddy Kalluru break; 2619645874e5SSudarsana Reddy Kalluru case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED: 2620645874e5SSudarsana Reddy Kalluru p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME; 2621645874e5SSudarsana Reddy Kalluru break; 2622645874e5SSudarsana Reddy Kalluru case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE: 2623645874e5SSudarsana Reddy Kalluru p_caps->eee_lpi_timer = 2624645874e5SSudarsana Reddy Kalluru EEE_TX_TIMER_USEC_AGGRESSIVE_TIME; 2625645874e5SSudarsana Reddy Kalluru break; 2626645874e5SSudarsana Reddy Kalluru case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY: 2627645874e5SSudarsana Reddy Kalluru p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME; 2628645874e5SSudarsana Reddy Kalluru break; 2629645874e5SSudarsana Reddy Kalluru } 2630645874e5SSudarsana Reddy Kalluru 2631645874e5SSudarsana Reddy Kalluru link->eee.tx_lpi_timer = p_caps->eee_lpi_timer; 2632645874e5SSudarsana Reddy Kalluru link->eee.tx_lpi_enable = link->eee.enable; 2633645874e5SSudarsana Reddy Kalluru link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV; 2634645874e5SSudarsana Reddy Kalluru } else { 2635645874e5SSudarsana Reddy Kalluru p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED; 2636645874e5SSudarsana Reddy Kalluru } 2637645874e5SSudarsana Reddy Kalluru 2638645874e5SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, 2639645874e5SSudarsana Reddy Kalluru NETIF_MSG_LINK, 2640645874e5SSudarsana Reddy Kalluru "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x EEE: %02x [%08x usec]\n", 2641645874e5SSudarsana Reddy Kalluru link->speed.forced_speed, 2642645874e5SSudarsana Reddy Kalluru link->speed.advertised_speeds, 2643645874e5SSudarsana Reddy Kalluru link->speed.autoneg, 2644645874e5SSudarsana Reddy Kalluru link->pause.autoneg, 2645645874e5SSudarsana Reddy Kalluru p_caps->default_eee, p_caps->eee_lpi_timer); 2646cc875c2eSYuval Mintz 2647b51bdfb9SSudarsana Reddy Kalluru if (IS_LEAD_HWFN(p_hwfn)) { 2648b51bdfb9SSudarsana Reddy Kalluru struct qed_dev *cdev = p_hwfn->cdev; 2649b51bdfb9SSudarsana Reddy Kalluru 2650fe56b9e6SYuval Mintz /* Read Multi-function information from shmem */ 2651fe56b9e6SYuval Mintz addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2652fe56b9e6SYuval Mintz offsetof(struct nvm_cfg1, glob) + 2653fe56b9e6SYuval Mintz offsetof(struct nvm_cfg1_glob, generic_cont0); 2654fe56b9e6SYuval Mintz 2655fe56b9e6SYuval Mintz generic_cont0 = qed_rd(p_hwfn, p_ptt, addr); 2656fe56b9e6SYuval Mintz 2657fe56b9e6SYuval Mintz mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >> 2658fe56b9e6SYuval Mintz NVM_CFG1_GLOB_MF_MODE_OFFSET; 2659fe56b9e6SYuval Mintz 2660fe56b9e6SYuval Mintz switch (mf_mode) { 2661fe56b9e6SYuval Mintz case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED: 2662b51bdfb9SSudarsana Reddy Kalluru cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS); 2663b51bdfb9SSudarsana Reddy Kalluru break; 2664cac6f691SSudarsana Reddy Kalluru case NVM_CFG1_GLOB_MF_MODE_UFP: 2665cac6f691SSudarsana Reddy Kalluru cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) | 2666cac6f691SSudarsana Reddy Kalluru BIT(QED_MF_LLH_PROTO_CLSS) | 2667cac6f691SSudarsana Reddy Kalluru BIT(QED_MF_UFP_SPECIFIC) | 2668cac6f691SSudarsana Reddy Kalluru BIT(QED_MF_8021Q_TAGGING); 2669cac6f691SSudarsana Reddy Kalluru break; 2670b51bdfb9SSudarsana Reddy Kalluru case NVM_CFG1_GLOB_MF_MODE_BD: 2671b51bdfb9SSudarsana Reddy Kalluru cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) | 2672b51bdfb9SSudarsana Reddy Kalluru BIT(QED_MF_LLH_PROTO_CLSS) | 2673b51bdfb9SSudarsana Reddy Kalluru BIT(QED_MF_8021AD_TAGGING); 2674fe56b9e6SYuval Mintz break; 2675fe56b9e6SYuval Mintz case NVM_CFG1_GLOB_MF_MODE_NPAR1_0: 2676b51bdfb9SSudarsana Reddy Kalluru cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) | 26770bc5fe85SSudarsana Reddy Kalluru BIT(QED_MF_LLH_PROTO_CLSS) | 26780bc5fe85SSudarsana Reddy Kalluru BIT(QED_MF_LL2_NON_UNICAST) | 26790bc5fe85SSudarsana Reddy Kalluru BIT(QED_MF_INTER_PF_SWITCH); 2680fe56b9e6SYuval Mintz break; 2681fc48b7a6SYuval Mintz case NVM_CFG1_GLOB_MF_MODE_DEFAULT: 2682b51bdfb9SSudarsana Reddy Kalluru cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) | 26830bc5fe85SSudarsana Reddy Kalluru BIT(QED_MF_LLH_PROTO_CLSS) | 26840bc5fe85SSudarsana Reddy Kalluru BIT(QED_MF_LL2_NON_UNICAST); 26850bc5fe85SSudarsana Reddy Kalluru if (QED_IS_BB(p_hwfn->cdev)) 2686b51bdfb9SSudarsana Reddy Kalluru cdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF); 2687fe56b9e6SYuval Mintz break; 2688fe56b9e6SYuval Mintz } 26890bc5fe85SSudarsana Reddy Kalluru 26900bc5fe85SSudarsana Reddy Kalluru DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n", 2691b51bdfb9SSudarsana Reddy Kalluru cdev->mf_bits); 2692b51bdfb9SSudarsana Reddy Kalluru } 2693b51bdfb9SSudarsana Reddy Kalluru 2694b51bdfb9SSudarsana Reddy Kalluru DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n", 26950bc5fe85SSudarsana Reddy Kalluru p_hwfn->cdev->mf_bits); 2696fe56b9e6SYuval Mintz 2697b51bdfb9SSudarsana Reddy Kalluru /* Read device capabilities information from shmem */ 2698fc48b7a6SYuval Mintz addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2699fc48b7a6SYuval Mintz offsetof(struct nvm_cfg1, glob) + 2700fc48b7a6SYuval Mintz offsetof(struct nvm_cfg1_glob, device_capabilities); 2701fc48b7a6SYuval Mintz 2702fc48b7a6SYuval Mintz device_capabilities = qed_rd(p_hwfn, p_ptt, addr); 2703fc48b7a6SYuval Mintz if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET) 2704fc48b7a6SYuval Mintz __set_bit(QED_DEV_CAP_ETH, 2705fc48b7a6SYuval Mintz &p_hwfn->hw_info.device_capabilities); 27061e128c81SArun Easi if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE) 27071e128c81SArun Easi __set_bit(QED_DEV_CAP_FCOE, 27081e128c81SArun Easi &p_hwfn->hw_info.device_capabilities); 2709c5ac9319SYuval Mintz if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI) 2710c5ac9319SYuval Mintz __set_bit(QED_DEV_CAP_ISCSI, 2711c5ac9319SYuval Mintz &p_hwfn->hw_info.device_capabilities); 2712c5ac9319SYuval Mintz if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE) 2713c5ac9319SYuval Mintz __set_bit(QED_DEV_CAP_ROCE, 2714c5ac9319SYuval Mintz &p_hwfn->hw_info.device_capabilities); 2715fc48b7a6SYuval Mintz 2716fe56b9e6SYuval Mintz return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt); 2717fe56b9e6SYuval Mintz } 2718fe56b9e6SYuval Mintz 27191408cc1fSYuval Mintz static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 27201408cc1fSYuval Mintz { 2721dbb799c3SYuval Mintz u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id; 2722dbb799c3SYuval Mintz u32 reg_function_hide, tmp, eng_mask, low_pfs_mask; 27239c79ddaaSMintz, Yuval struct qed_dev *cdev = p_hwfn->cdev; 27241408cc1fSYuval Mintz 27259c79ddaaSMintz, Yuval num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB; 27261408cc1fSYuval Mintz 27271408cc1fSYuval Mintz /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values 27281408cc1fSYuval Mintz * in the other bits are selected. 27291408cc1fSYuval Mintz * Bits 1-15 are for functions 1-15, respectively, and their value is 27301408cc1fSYuval Mintz * '0' only for enabled functions (function 0 always exists and 27311408cc1fSYuval Mintz * enabled). 27321408cc1fSYuval Mintz * In case of CMT, only the "even" functions are enabled, and thus the 27331408cc1fSYuval Mintz * number of functions for both hwfns is learnt from the same bits. 27341408cc1fSYuval Mintz */ 27351408cc1fSYuval Mintz reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE); 27361408cc1fSYuval Mintz 27371408cc1fSYuval Mintz if (reg_function_hide & 0x1) { 27389c79ddaaSMintz, Yuval if (QED_IS_BB(cdev)) { 27399c79ddaaSMintz, Yuval if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) { 27401408cc1fSYuval Mintz num_funcs = 0; 27411408cc1fSYuval Mintz eng_mask = 0xaaaa; 27421408cc1fSYuval Mintz } else { 27431408cc1fSYuval Mintz num_funcs = 1; 27441408cc1fSYuval Mintz eng_mask = 0x5554; 27451408cc1fSYuval Mintz } 27469c79ddaaSMintz, Yuval } else { 27479c79ddaaSMintz, Yuval num_funcs = 1; 27489c79ddaaSMintz, Yuval eng_mask = 0xfffe; 27499c79ddaaSMintz, Yuval } 27501408cc1fSYuval Mintz 27511408cc1fSYuval Mintz /* Get the number of the enabled functions on the engine */ 27521408cc1fSYuval Mintz tmp = (reg_function_hide ^ 0xffffffff) & eng_mask; 27531408cc1fSYuval Mintz while (tmp) { 27541408cc1fSYuval Mintz if (tmp & 0x1) 27551408cc1fSYuval Mintz num_funcs++; 27561408cc1fSYuval Mintz tmp >>= 0x1; 27571408cc1fSYuval Mintz } 2758dbb799c3SYuval Mintz 2759dbb799c3SYuval Mintz /* Get the PF index within the enabled functions */ 2760dbb799c3SYuval Mintz low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1; 2761dbb799c3SYuval Mintz tmp = reg_function_hide & eng_mask & low_pfs_mask; 2762dbb799c3SYuval Mintz while (tmp) { 2763dbb799c3SYuval Mintz if (tmp & 0x1) 2764dbb799c3SYuval Mintz enabled_func_idx--; 2765dbb799c3SYuval Mintz tmp >>= 0x1; 2766dbb799c3SYuval Mintz } 27671408cc1fSYuval Mintz } 27681408cc1fSYuval Mintz 27691408cc1fSYuval Mintz p_hwfn->num_funcs_on_engine = num_funcs; 2770dbb799c3SYuval Mintz p_hwfn->enabled_func_idx = enabled_func_idx; 27711408cc1fSYuval Mintz 27721408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, 27731408cc1fSYuval Mintz NETIF_MSG_PROBE, 2774525ef5c0SYuval Mintz "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n", 27751408cc1fSYuval Mintz p_hwfn->rel_pf_id, 27761408cc1fSYuval Mintz p_hwfn->abs_pf_id, 2777525ef5c0SYuval Mintz p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine); 27781408cc1fSYuval Mintz } 27791408cc1fSYuval Mintz 27809c79ddaaSMintz, Yuval static void qed_hw_info_port_num_bb(struct qed_hwfn *p_hwfn, 27819c79ddaaSMintz, Yuval struct qed_ptt *p_ptt) 2782fe56b9e6SYuval Mintz { 2783fe56b9e6SYuval Mintz u32 port_mode; 2784fe56b9e6SYuval Mintz 2785d52c89f1SMichal Kalderon port_mode = qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB); 2786fe56b9e6SYuval Mintz 2787fe56b9e6SYuval Mintz if (port_mode < 3) { 278878cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine = 1; 2789fe56b9e6SYuval Mintz } else if (port_mode <= 5) { 279078cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine = 2; 2791fe56b9e6SYuval Mintz } else { 2792fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n", 279378cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine); 2794fe56b9e6SYuval Mintz 279578cea9ffSTomer Tayar /* Default num_ports_in_engine to something */ 279678cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine = 1; 2797fe56b9e6SYuval Mintz } 27989c79ddaaSMintz, Yuval } 27999c79ddaaSMintz, Yuval 28009c79ddaaSMintz, Yuval static void qed_hw_info_port_num_ah(struct qed_hwfn *p_hwfn, 28019c79ddaaSMintz, Yuval struct qed_ptt *p_ptt) 28029c79ddaaSMintz, Yuval { 28039c79ddaaSMintz, Yuval u32 port; 28049c79ddaaSMintz, Yuval int i; 28059c79ddaaSMintz, Yuval 280678cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine = 0; 28079c79ddaaSMintz, Yuval 28089c79ddaaSMintz, Yuval for (i = 0; i < MAX_NUM_PORTS_K2; i++) { 28099c79ddaaSMintz, Yuval port = qed_rd(p_hwfn, p_ptt, 28109c79ddaaSMintz, Yuval CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4)); 28119c79ddaaSMintz, Yuval if (port & 1) 281278cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine++; 28139c79ddaaSMintz, Yuval } 28149c79ddaaSMintz, Yuval 281578cea9ffSTomer Tayar if (!p_hwfn->cdev->num_ports_in_engine) { 28169c79ddaaSMintz, Yuval DP_NOTICE(p_hwfn, "All NIG ports are inactive\n"); 28179c79ddaaSMintz, Yuval 28189c79ddaaSMintz, Yuval /* Default num_ports_in_engine to something */ 281978cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine = 1; 28209c79ddaaSMintz, Yuval } 28219c79ddaaSMintz, Yuval } 28229c79ddaaSMintz, Yuval 28239c79ddaaSMintz, Yuval static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 28249c79ddaaSMintz, Yuval { 28259c79ddaaSMintz, Yuval if (QED_IS_BB(p_hwfn->cdev)) 28269c79ddaaSMintz, Yuval qed_hw_info_port_num_bb(p_hwfn, p_ptt); 28279c79ddaaSMintz, Yuval else 28289c79ddaaSMintz, Yuval qed_hw_info_port_num_ah(p_hwfn, p_ptt); 28299c79ddaaSMintz, Yuval } 28309c79ddaaSMintz, Yuval 2831645874e5SSudarsana Reddy Kalluru static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2832645874e5SSudarsana Reddy Kalluru { 2833645874e5SSudarsana Reddy Kalluru struct qed_mcp_link_capabilities *p_caps; 2834645874e5SSudarsana Reddy Kalluru u32 eee_status; 2835645874e5SSudarsana Reddy Kalluru 2836645874e5SSudarsana Reddy Kalluru p_caps = &p_hwfn->mcp_info->link_capabilities; 2837645874e5SSudarsana Reddy Kalluru if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED) 2838645874e5SSudarsana Reddy Kalluru return; 2839645874e5SSudarsana Reddy Kalluru 2840645874e5SSudarsana Reddy Kalluru p_caps->eee_speed_caps = 0; 2841645874e5SSudarsana Reddy Kalluru eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 2842645874e5SSudarsana Reddy Kalluru offsetof(struct public_port, eee_status)); 2843645874e5SSudarsana Reddy Kalluru eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >> 2844645874e5SSudarsana Reddy Kalluru EEE_SUPPORTED_SPEED_OFFSET; 2845645874e5SSudarsana Reddy Kalluru 2846645874e5SSudarsana Reddy Kalluru if (eee_status & EEE_1G_SUPPORTED) 2847645874e5SSudarsana Reddy Kalluru p_caps->eee_speed_caps |= QED_EEE_1G_ADV; 2848645874e5SSudarsana Reddy Kalluru if (eee_status & EEE_10G_ADV) 2849645874e5SSudarsana Reddy Kalluru p_caps->eee_speed_caps |= QED_EEE_10G_ADV; 2850645874e5SSudarsana Reddy Kalluru } 2851645874e5SSudarsana Reddy Kalluru 28529c79ddaaSMintz, Yuval static int 28539c79ddaaSMintz, Yuval qed_get_hw_info(struct qed_hwfn *p_hwfn, 28549c79ddaaSMintz, Yuval struct qed_ptt *p_ptt, 28559c79ddaaSMintz, Yuval enum qed_pci_personality personality) 28569c79ddaaSMintz, Yuval { 28579c79ddaaSMintz, Yuval int rc; 28589c79ddaaSMintz, Yuval 28599c79ddaaSMintz, Yuval /* Since all information is common, only first hwfns should do this */ 28609c79ddaaSMintz, Yuval if (IS_LEAD_HWFN(p_hwfn)) { 28619c79ddaaSMintz, Yuval rc = qed_iov_hw_info(p_hwfn); 28629c79ddaaSMintz, Yuval if (rc) 28639c79ddaaSMintz, Yuval return rc; 28649c79ddaaSMintz, Yuval } 28659c79ddaaSMintz, Yuval 28669c79ddaaSMintz, Yuval qed_hw_info_port_num(p_hwfn, p_ptt); 2867fe56b9e6SYuval Mintz 2868645874e5SSudarsana Reddy Kalluru qed_mcp_get_capabilities(p_hwfn, p_ptt); 2869645874e5SSudarsana Reddy Kalluru 2870fe56b9e6SYuval Mintz qed_hw_get_nvm_info(p_hwfn, p_ptt); 2871fe56b9e6SYuval Mintz 2872fe56b9e6SYuval Mintz rc = qed_int_igu_read_cam(p_hwfn, p_ptt); 2873fe56b9e6SYuval Mintz if (rc) 2874fe56b9e6SYuval Mintz return rc; 2875fe56b9e6SYuval Mintz 2876fe56b9e6SYuval Mintz if (qed_mcp_is_init(p_hwfn)) 2877fe56b9e6SYuval Mintz ether_addr_copy(p_hwfn->hw_info.hw_mac_addr, 2878fe56b9e6SYuval Mintz p_hwfn->mcp_info->func_info.mac); 2879fe56b9e6SYuval Mintz else 2880fe56b9e6SYuval Mintz eth_random_addr(p_hwfn->hw_info.hw_mac_addr); 2881fe56b9e6SYuval Mintz 2882fe56b9e6SYuval Mintz if (qed_mcp_is_init(p_hwfn)) { 2883fe56b9e6SYuval Mintz if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET) 2884fe56b9e6SYuval Mintz p_hwfn->hw_info.ovlan = 2885fe56b9e6SYuval Mintz p_hwfn->mcp_info->func_info.ovlan; 2886fe56b9e6SYuval Mintz 2887fe56b9e6SYuval Mintz qed_mcp_cmd_port_init(p_hwfn, p_ptt); 2888645874e5SSudarsana Reddy Kalluru 2889645874e5SSudarsana Reddy Kalluru qed_get_eee_caps(p_hwfn, p_ptt); 2890cac6f691SSudarsana Reddy Kalluru 2891cac6f691SSudarsana Reddy Kalluru qed_mcp_read_ufp_config(p_hwfn, p_ptt); 2892fe56b9e6SYuval Mintz } 2893fe56b9e6SYuval Mintz 2894fe56b9e6SYuval Mintz if (qed_mcp_is_init(p_hwfn)) { 2895fe56b9e6SYuval Mintz enum qed_pci_personality protocol; 2896fe56b9e6SYuval Mintz 2897fe56b9e6SYuval Mintz protocol = p_hwfn->mcp_info->func_info.protocol; 2898fe56b9e6SYuval Mintz p_hwfn->hw_info.personality = protocol; 2899fe56b9e6SYuval Mintz } 2900fe56b9e6SYuval Mintz 2901b5a9ee7cSAriel Elior p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2; 2902b5a9ee7cSAriel Elior p_hwfn->hw_info.num_active_tc = 1; 2903b5a9ee7cSAriel Elior 29041408cc1fSYuval Mintz qed_get_num_funcs(p_hwfn, p_ptt); 29051408cc1fSYuval Mintz 29060fefbfbaSSudarsana Kalluru if (qed_mcp_is_init(p_hwfn)) 29070fefbfbaSSudarsana Kalluru p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu; 29080fefbfbaSSudarsana Kalluru 29099c8517c4STomer Tayar return qed_hw_get_resc(p_hwfn, p_ptt); 2910fe56b9e6SYuval Mintz } 2911fe56b9e6SYuval Mintz 291215582962SRahul Verma static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2913fe56b9e6SYuval Mintz { 291415582962SRahul Verma struct qed_dev *cdev = p_hwfn->cdev; 29159c79ddaaSMintz, Yuval u16 device_id_mask; 2916fe56b9e6SYuval Mintz u32 tmp; 2917fe56b9e6SYuval Mintz 2918fc48b7a6SYuval Mintz /* Read Vendor Id / Device Id */ 29191a635e48SYuval Mintz pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id); 29201a635e48SYuval Mintz pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id); 29211a635e48SYuval Mintz 29229c79ddaaSMintz, Yuval /* Determine type */ 29239c79ddaaSMintz, Yuval device_id_mask = cdev->device_id & QED_DEV_ID_MASK; 29249c79ddaaSMintz, Yuval switch (device_id_mask) { 29259c79ddaaSMintz, Yuval case QED_DEV_ID_MASK_BB: 29269c79ddaaSMintz, Yuval cdev->type = QED_DEV_TYPE_BB; 29279c79ddaaSMintz, Yuval break; 29289c79ddaaSMintz, Yuval case QED_DEV_ID_MASK_AH: 29299c79ddaaSMintz, Yuval cdev->type = QED_DEV_TYPE_AH; 29309c79ddaaSMintz, Yuval break; 29319c79ddaaSMintz, Yuval default: 29329c79ddaaSMintz, Yuval DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id); 29339c79ddaaSMintz, Yuval return -EBUSY; 29349c79ddaaSMintz, Yuval } 29359c79ddaaSMintz, Yuval 293615582962SRahul Verma cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM); 293715582962SRahul Verma cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV); 293815582962SRahul Verma 2939fe56b9e6SYuval Mintz MASK_FIELD(CHIP_REV, cdev->chip_rev); 2940fe56b9e6SYuval Mintz 2941fe56b9e6SYuval Mintz /* Learn number of HW-functions */ 294215582962SRahul Verma tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR); 2943fe56b9e6SYuval Mintz 2944fc48b7a6SYuval Mintz if (tmp & (1 << p_hwfn->rel_pf_id)) { 2945fe56b9e6SYuval Mintz DP_NOTICE(cdev->hwfns, "device in CMT mode\n"); 2946fe56b9e6SYuval Mintz cdev->num_hwfns = 2; 2947fe56b9e6SYuval Mintz } else { 2948fe56b9e6SYuval Mintz cdev->num_hwfns = 1; 2949fe56b9e6SYuval Mintz } 2950fe56b9e6SYuval Mintz 295115582962SRahul Verma cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt, 2952fe56b9e6SYuval Mintz MISCS_REG_CHIP_TEST_REG) >> 4; 2953fe56b9e6SYuval Mintz MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id); 295415582962SRahul Verma cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL); 2955fe56b9e6SYuval Mintz MASK_FIELD(CHIP_METAL, cdev->chip_metal); 2956fe56b9e6SYuval Mintz 2957fe56b9e6SYuval Mintz DP_INFO(cdev->hwfns, 29589c79ddaaSMintz, Yuval "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n", 29599c79ddaaSMintz, Yuval QED_IS_BB(cdev) ? "BB" : "AH", 29609c79ddaaSMintz, Yuval 'A' + cdev->chip_rev, 29619c79ddaaSMintz, Yuval (int)cdev->chip_metal, 2962fe56b9e6SYuval Mintz cdev->chip_num, cdev->chip_rev, 2963fe56b9e6SYuval Mintz cdev->chip_bond_id, cdev->chip_metal); 296412e09c69SYuval Mintz 296512e09c69SYuval Mintz return 0; 2966fe56b9e6SYuval Mintz } 2967fe56b9e6SYuval Mintz 296843645ce0SSudarsana Reddy Kalluru static void qed_nvm_info_free(struct qed_hwfn *p_hwfn) 296943645ce0SSudarsana Reddy Kalluru { 297043645ce0SSudarsana Reddy Kalluru kfree(p_hwfn->nvm_info.image_att); 297143645ce0SSudarsana Reddy Kalluru p_hwfn->nvm_info.image_att = NULL; 297243645ce0SSudarsana Reddy Kalluru } 297343645ce0SSudarsana Reddy Kalluru 2974fe56b9e6SYuval Mintz static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn, 2975fe56b9e6SYuval Mintz void __iomem *p_regview, 2976fe56b9e6SYuval Mintz void __iomem *p_doorbells, 2977fe56b9e6SYuval Mintz enum qed_pci_personality personality) 2978fe56b9e6SYuval Mintz { 2979fe56b9e6SYuval Mintz int rc = 0; 2980fe56b9e6SYuval Mintz 2981fe56b9e6SYuval Mintz /* Split PCI bars evenly between hwfns */ 2982fe56b9e6SYuval Mintz p_hwfn->regview = p_regview; 2983fe56b9e6SYuval Mintz p_hwfn->doorbells = p_doorbells; 2984fe56b9e6SYuval Mintz 29851408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 29861408cc1fSYuval Mintz return qed_vf_hw_prepare(p_hwfn); 29871408cc1fSYuval Mintz 2988fe56b9e6SYuval Mintz /* Validate that chip access is feasible */ 2989fe56b9e6SYuval Mintz if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) { 2990fe56b9e6SYuval Mintz DP_ERR(p_hwfn, 2991fe56b9e6SYuval Mintz "Reading the ME register returns all Fs; Preventing further chip access\n"); 2992fe56b9e6SYuval Mintz return -EINVAL; 2993fe56b9e6SYuval Mintz } 2994fe56b9e6SYuval Mintz 2995fe56b9e6SYuval Mintz get_function_id(p_hwfn); 2996fe56b9e6SYuval Mintz 299712e09c69SYuval Mintz /* Allocate PTT pool */ 299812e09c69SYuval Mintz rc = qed_ptt_pool_alloc(p_hwfn); 29992591c280SJoe Perches if (rc) 3000fe56b9e6SYuval Mintz goto err0; 3001fe56b9e6SYuval Mintz 300212e09c69SYuval Mintz /* Allocate the main PTT */ 300312e09c69SYuval Mintz p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN); 300412e09c69SYuval Mintz 3005fe56b9e6SYuval Mintz /* First hwfn learns basic information, e.g., number of hwfns */ 300612e09c69SYuval Mintz if (!p_hwfn->my_id) { 300715582962SRahul Verma rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt); 30081a635e48SYuval Mintz if (rc) 300912e09c69SYuval Mintz goto err1; 301012e09c69SYuval Mintz } 301112e09c69SYuval Mintz 301212e09c69SYuval Mintz qed_hw_hwfn_prepare(p_hwfn); 3013fe56b9e6SYuval Mintz 3014fe56b9e6SYuval Mintz /* Initialize MCP structure */ 3015fe56b9e6SYuval Mintz rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt); 3016fe56b9e6SYuval Mintz if (rc) { 3017fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed initializing mcp command\n"); 3018fe56b9e6SYuval Mintz goto err1; 3019fe56b9e6SYuval Mintz } 3020fe56b9e6SYuval Mintz 3021fe56b9e6SYuval Mintz /* Read the device configuration information from the HW and SHMEM */ 3022fe56b9e6SYuval Mintz rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality); 3023fe56b9e6SYuval Mintz if (rc) { 3024fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed to get HW information\n"); 3025fe56b9e6SYuval Mintz goto err2; 3026fe56b9e6SYuval Mintz } 3027fe56b9e6SYuval Mintz 302818a69e36SMintz, Yuval /* Sending a mailbox to the MFW should be done after qed_get_hw_info() 302918a69e36SMintz, Yuval * is called as it sets the ports number in an engine. 303018a69e36SMintz, Yuval */ 303118a69e36SMintz, Yuval if (IS_LEAD_HWFN(p_hwfn)) { 303218a69e36SMintz, Yuval rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt); 303318a69e36SMintz, Yuval if (rc) 303418a69e36SMintz, Yuval DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n"); 303518a69e36SMintz, Yuval } 303618a69e36SMintz, Yuval 303743645ce0SSudarsana Reddy Kalluru /* NVRAM info initialization and population */ 303843645ce0SSudarsana Reddy Kalluru if (IS_LEAD_HWFN(p_hwfn)) { 303943645ce0SSudarsana Reddy Kalluru rc = qed_mcp_nvm_info_populate(p_hwfn); 304043645ce0SSudarsana Reddy Kalluru if (rc) { 304143645ce0SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 304243645ce0SSudarsana Reddy Kalluru "Failed to populate nvm info shadow\n"); 304343645ce0SSudarsana Reddy Kalluru goto err2; 304443645ce0SSudarsana Reddy Kalluru } 304543645ce0SSudarsana Reddy Kalluru } 304643645ce0SSudarsana Reddy Kalluru 3047fe56b9e6SYuval Mintz /* Allocate the init RT array and initialize the init-ops engine */ 3048fe56b9e6SYuval Mintz rc = qed_init_alloc(p_hwfn); 30492591c280SJoe Perches if (rc) 305043645ce0SSudarsana Reddy Kalluru goto err3; 3051fe56b9e6SYuval Mintz 3052fe56b9e6SYuval Mintz return rc; 305343645ce0SSudarsana Reddy Kalluru err3: 305443645ce0SSudarsana Reddy Kalluru if (IS_LEAD_HWFN(p_hwfn)) 305543645ce0SSudarsana Reddy Kalluru qed_nvm_info_free(p_hwfn); 3056fe56b9e6SYuval Mintz err2: 305732a47e72SYuval Mintz if (IS_LEAD_HWFN(p_hwfn)) 305832a47e72SYuval Mintz qed_iov_free_hw_info(p_hwfn->cdev); 3059fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 3060fe56b9e6SYuval Mintz err1: 3061fe56b9e6SYuval Mintz qed_hw_hwfn_free(p_hwfn); 3062fe56b9e6SYuval Mintz err0: 3063fe56b9e6SYuval Mintz return rc; 3064fe56b9e6SYuval Mintz } 3065fe56b9e6SYuval Mintz 3066fe56b9e6SYuval Mintz int qed_hw_prepare(struct qed_dev *cdev, 3067fe56b9e6SYuval Mintz int personality) 3068fe56b9e6SYuval Mintz { 3069c78df14eSAriel Elior struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 3070c78df14eSAriel Elior int rc; 3071fe56b9e6SYuval Mintz 3072fe56b9e6SYuval Mintz /* Store the precompiled init data ptrs */ 30731408cc1fSYuval Mintz if (IS_PF(cdev)) 3074fe56b9e6SYuval Mintz qed_init_iro_array(cdev); 3075fe56b9e6SYuval Mintz 3076fe56b9e6SYuval Mintz /* Initialize the first hwfn - will learn number of hwfns */ 3077c78df14eSAriel Elior rc = qed_hw_prepare_single(p_hwfn, 3078c78df14eSAriel Elior cdev->regview, 3079fe56b9e6SYuval Mintz cdev->doorbells, personality); 3080fe56b9e6SYuval Mintz if (rc) 3081fe56b9e6SYuval Mintz return rc; 3082fe56b9e6SYuval Mintz 3083c78df14eSAriel Elior personality = p_hwfn->hw_info.personality; 3084fe56b9e6SYuval Mintz 3085fe56b9e6SYuval Mintz /* Initialize the rest of the hwfns */ 3086c78df14eSAriel Elior if (cdev->num_hwfns > 1) { 3087fe56b9e6SYuval Mintz void __iomem *p_regview, *p_doorbell; 3088c78df14eSAriel Elior u8 __iomem *addr; 3089fe56b9e6SYuval Mintz 3090c78df14eSAriel Elior /* adjust bar offset for second engine */ 309115582962SRahul Verma addr = cdev->regview + 309215582962SRahul Verma qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt, 309315582962SRahul Verma BAR_ID_0) / 2; 3094c78df14eSAriel Elior p_regview = addr; 3095c78df14eSAriel Elior 309615582962SRahul Verma addr = cdev->doorbells + 309715582962SRahul Verma qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt, 309815582962SRahul Verma BAR_ID_1) / 2; 3099c78df14eSAriel Elior p_doorbell = addr; 3100c78df14eSAriel Elior 3101c78df14eSAriel Elior /* prepare second hw function */ 3102c78df14eSAriel Elior rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview, 3103fe56b9e6SYuval Mintz p_doorbell, personality); 3104c78df14eSAriel Elior 3105c78df14eSAriel Elior /* in case of error, need to free the previously 3106c78df14eSAriel Elior * initiliazed hwfn 0. 3107c78df14eSAriel Elior */ 3108fe56b9e6SYuval Mintz if (rc) { 31091408cc1fSYuval Mintz if (IS_PF(cdev)) { 3110c78df14eSAriel Elior qed_init_free(p_hwfn); 311143645ce0SSudarsana Reddy Kalluru qed_nvm_info_free(p_hwfn); 3112c78df14eSAriel Elior qed_mcp_free(p_hwfn); 3113c78df14eSAriel Elior qed_hw_hwfn_free(p_hwfn); 3114fe56b9e6SYuval Mintz } 3115fe56b9e6SYuval Mintz } 31161408cc1fSYuval Mintz } 3117fe56b9e6SYuval Mintz 3118c78df14eSAriel Elior return rc; 3119fe56b9e6SYuval Mintz } 3120fe56b9e6SYuval Mintz 3121fe56b9e6SYuval Mintz void qed_hw_remove(struct qed_dev *cdev) 3122fe56b9e6SYuval Mintz { 31230fefbfbaSSudarsana Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 3124fe56b9e6SYuval Mintz int i; 3125fe56b9e6SYuval Mintz 31260fefbfbaSSudarsana Kalluru if (IS_PF(cdev)) 31270fefbfbaSSudarsana Kalluru qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt, 31280fefbfbaSSudarsana Kalluru QED_OV_DRIVER_STATE_NOT_LOADED); 31290fefbfbaSSudarsana Kalluru 3130fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 3131fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 3132fe56b9e6SYuval Mintz 31331408cc1fSYuval Mintz if (IS_VF(cdev)) { 31340b55e27dSYuval Mintz qed_vf_pf_release(p_hwfn); 31351408cc1fSYuval Mintz continue; 31361408cc1fSYuval Mintz } 31371408cc1fSYuval Mintz 3138fe56b9e6SYuval Mintz qed_init_free(p_hwfn); 3139fe56b9e6SYuval Mintz qed_hw_hwfn_free(p_hwfn); 3140fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 3141fe56b9e6SYuval Mintz } 314232a47e72SYuval Mintz 314332a47e72SYuval Mintz qed_iov_free_hw_info(cdev); 314443645ce0SSudarsana Reddy Kalluru 314543645ce0SSudarsana Reddy Kalluru qed_nvm_info_free(p_hwfn); 3146fe56b9e6SYuval Mintz } 3147fe56b9e6SYuval Mintz 3148a91eb52aSYuval Mintz static void qed_chain_free_next_ptr(struct qed_dev *cdev, 3149a91eb52aSYuval Mintz struct qed_chain *p_chain) 3150a91eb52aSYuval Mintz { 3151a91eb52aSYuval Mintz void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL; 3152a91eb52aSYuval Mintz dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0; 3153a91eb52aSYuval Mintz struct qed_chain_next *p_next; 3154a91eb52aSYuval Mintz u32 size, i; 3155a91eb52aSYuval Mintz 3156a91eb52aSYuval Mintz if (!p_virt) 3157a91eb52aSYuval Mintz return; 3158a91eb52aSYuval Mintz 3159a91eb52aSYuval Mintz size = p_chain->elem_size * p_chain->usable_per_page; 3160a91eb52aSYuval Mintz 3161a91eb52aSYuval Mintz for (i = 0; i < p_chain->page_cnt; i++) { 3162a91eb52aSYuval Mintz if (!p_virt) 3163a91eb52aSYuval Mintz break; 3164a91eb52aSYuval Mintz 3165a91eb52aSYuval Mintz p_next = (struct qed_chain_next *)((u8 *)p_virt + size); 3166a91eb52aSYuval Mintz p_virt_next = p_next->next_virt; 3167a91eb52aSYuval Mintz p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys); 3168a91eb52aSYuval Mintz 3169a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 3170a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, p_virt, p_phys); 3171a91eb52aSYuval Mintz 3172a91eb52aSYuval Mintz p_virt = p_virt_next; 3173a91eb52aSYuval Mintz p_phys = p_phys_next; 3174a91eb52aSYuval Mintz } 3175a91eb52aSYuval Mintz } 3176a91eb52aSYuval Mintz 3177a91eb52aSYuval Mintz static void qed_chain_free_single(struct qed_dev *cdev, 3178a91eb52aSYuval Mintz struct qed_chain *p_chain) 3179a91eb52aSYuval Mintz { 3180a91eb52aSYuval Mintz if (!p_chain->p_virt_addr) 3181a91eb52aSYuval Mintz return; 3182a91eb52aSYuval Mintz 3183a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 3184a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 3185a91eb52aSYuval Mintz p_chain->p_virt_addr, p_chain->p_phys_addr); 3186a91eb52aSYuval Mintz } 3187a91eb52aSYuval Mintz 3188a91eb52aSYuval Mintz static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain) 3189a91eb52aSYuval Mintz { 3190a91eb52aSYuval Mintz void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl; 3191a91eb52aSYuval Mintz u32 page_cnt = p_chain->page_cnt, i, pbl_size; 31926d937acfSMintz, Yuval u8 *p_pbl_virt = p_chain->pbl_sp.p_virt_table; 3193a91eb52aSYuval Mintz 3194a91eb52aSYuval Mintz if (!pp_virt_addr_tbl) 3195a91eb52aSYuval Mintz return; 3196a91eb52aSYuval Mintz 31976d937acfSMintz, Yuval if (!p_pbl_virt) 3198a91eb52aSYuval Mintz goto out; 3199a91eb52aSYuval Mintz 3200a91eb52aSYuval Mintz for (i = 0; i < page_cnt; i++) { 3201a91eb52aSYuval Mintz if (!pp_virt_addr_tbl[i]) 3202a91eb52aSYuval Mintz break; 3203a91eb52aSYuval Mintz 3204a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 3205a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 3206a91eb52aSYuval Mintz pp_virt_addr_tbl[i], 3207a91eb52aSYuval Mintz *(dma_addr_t *)p_pbl_virt); 3208a91eb52aSYuval Mintz 3209a91eb52aSYuval Mintz p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE; 3210a91eb52aSYuval Mintz } 3211a91eb52aSYuval Mintz 3212a91eb52aSYuval Mintz pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; 32131a4a6975SMintz, Yuval 32141a4a6975SMintz, Yuval if (!p_chain->b_external_pbl) 3215a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 3216a91eb52aSYuval Mintz pbl_size, 32176d937acfSMintz, Yuval p_chain->pbl_sp.p_virt_table, 32186d937acfSMintz, Yuval p_chain->pbl_sp.p_phys_table); 3219a91eb52aSYuval Mintz out: 3220a91eb52aSYuval Mintz vfree(p_chain->pbl.pp_virt_addr_tbl); 32211a4a6975SMintz, Yuval p_chain->pbl.pp_virt_addr_tbl = NULL; 3222a91eb52aSYuval Mintz } 3223a91eb52aSYuval Mintz 3224a91eb52aSYuval Mintz void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain) 3225a91eb52aSYuval Mintz { 3226a91eb52aSYuval Mintz switch (p_chain->mode) { 3227a91eb52aSYuval Mintz case QED_CHAIN_MODE_NEXT_PTR: 3228a91eb52aSYuval Mintz qed_chain_free_next_ptr(cdev, p_chain); 3229a91eb52aSYuval Mintz break; 3230a91eb52aSYuval Mintz case QED_CHAIN_MODE_SINGLE: 3231a91eb52aSYuval Mintz qed_chain_free_single(cdev, p_chain); 3232a91eb52aSYuval Mintz break; 3233a91eb52aSYuval Mintz case QED_CHAIN_MODE_PBL: 3234a91eb52aSYuval Mintz qed_chain_free_pbl(cdev, p_chain); 3235a91eb52aSYuval Mintz break; 3236a91eb52aSYuval Mintz } 3237a91eb52aSYuval Mintz } 3238a91eb52aSYuval Mintz 3239a91eb52aSYuval Mintz static int 3240a91eb52aSYuval Mintz qed_chain_alloc_sanity_check(struct qed_dev *cdev, 3241a91eb52aSYuval Mintz enum qed_chain_cnt_type cnt_type, 3242a91eb52aSYuval Mintz size_t elem_size, u32 page_cnt) 3243a91eb52aSYuval Mintz { 3244a91eb52aSYuval Mintz u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt; 3245a91eb52aSYuval Mintz 3246a91eb52aSYuval Mintz /* The actual chain size can be larger than the maximal possible value 3247a91eb52aSYuval Mintz * after rounding up the requested elements number to pages, and after 3248a91eb52aSYuval Mintz * taking into acount the unusuable elements (next-ptr elements). 3249a91eb52aSYuval Mintz * The size of a "u16" chain can be (U16_MAX + 1) since the chain 3250a91eb52aSYuval Mintz * size/capacity fields are of a u32 type. 3251a91eb52aSYuval Mintz */ 3252a91eb52aSYuval Mintz if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 && 32533ef310a7STomer Tayar chain_size > ((u32)U16_MAX + 1)) || 32543ef310a7STomer Tayar (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) { 3255a91eb52aSYuval Mintz DP_NOTICE(cdev, 3256a91eb52aSYuval Mintz "The actual chain size (0x%llx) is larger than the maximal possible value\n", 3257a91eb52aSYuval Mintz chain_size); 3258a91eb52aSYuval Mintz return -EINVAL; 3259a91eb52aSYuval Mintz } 3260a91eb52aSYuval Mintz 3261a91eb52aSYuval Mintz return 0; 3262a91eb52aSYuval Mintz } 3263a91eb52aSYuval Mintz 3264a91eb52aSYuval Mintz static int 3265a91eb52aSYuval Mintz qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain) 3266a91eb52aSYuval Mintz { 3267a91eb52aSYuval Mintz void *p_virt = NULL, *p_virt_prev = NULL; 3268a91eb52aSYuval Mintz dma_addr_t p_phys = 0; 3269a91eb52aSYuval Mintz u32 i; 3270a91eb52aSYuval Mintz 3271a91eb52aSYuval Mintz for (i = 0; i < p_chain->page_cnt; i++) { 3272a91eb52aSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 3273a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 3274a91eb52aSYuval Mintz &p_phys, GFP_KERNEL); 32752591c280SJoe Perches if (!p_virt) 3276a91eb52aSYuval Mintz return -ENOMEM; 3277a91eb52aSYuval Mintz 3278a91eb52aSYuval Mintz if (i == 0) { 3279a91eb52aSYuval Mintz qed_chain_init_mem(p_chain, p_virt, p_phys); 3280a91eb52aSYuval Mintz qed_chain_reset(p_chain); 3281a91eb52aSYuval Mintz } else { 3282a91eb52aSYuval Mintz qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, 3283a91eb52aSYuval Mintz p_virt, p_phys); 3284a91eb52aSYuval Mintz } 3285a91eb52aSYuval Mintz 3286a91eb52aSYuval Mintz p_virt_prev = p_virt; 3287a91eb52aSYuval Mintz } 3288a91eb52aSYuval Mintz /* Last page's next element should point to the beginning of the 3289a91eb52aSYuval Mintz * chain. 3290a91eb52aSYuval Mintz */ 3291a91eb52aSYuval Mintz qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, 3292a91eb52aSYuval Mintz p_chain->p_virt_addr, 3293a91eb52aSYuval Mintz p_chain->p_phys_addr); 3294a91eb52aSYuval Mintz 3295a91eb52aSYuval Mintz return 0; 3296a91eb52aSYuval Mintz } 3297a91eb52aSYuval Mintz 3298a91eb52aSYuval Mintz static int 3299a91eb52aSYuval Mintz qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain) 3300a91eb52aSYuval Mintz { 3301a91eb52aSYuval Mintz dma_addr_t p_phys = 0; 3302a91eb52aSYuval Mintz void *p_virt = NULL; 3303a91eb52aSYuval Mintz 3304a91eb52aSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 3305a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL); 33062591c280SJoe Perches if (!p_virt) 3307a91eb52aSYuval Mintz return -ENOMEM; 3308a91eb52aSYuval Mintz 3309a91eb52aSYuval Mintz qed_chain_init_mem(p_chain, p_virt, p_phys); 3310a91eb52aSYuval Mintz qed_chain_reset(p_chain); 3311a91eb52aSYuval Mintz 3312a91eb52aSYuval Mintz return 0; 3313a91eb52aSYuval Mintz } 3314a91eb52aSYuval Mintz 33151a4a6975SMintz, Yuval static int 33161a4a6975SMintz, Yuval qed_chain_alloc_pbl(struct qed_dev *cdev, 33171a4a6975SMintz, Yuval struct qed_chain *p_chain, 33181a4a6975SMintz, Yuval struct qed_chain_ext_pbl *ext_pbl) 3319a91eb52aSYuval Mintz { 3320a91eb52aSYuval Mintz u32 page_cnt = p_chain->page_cnt, size, i; 3321a91eb52aSYuval Mintz dma_addr_t p_phys = 0, p_pbl_phys = 0; 3322a91eb52aSYuval Mintz void **pp_virt_addr_tbl = NULL; 3323a91eb52aSYuval Mintz u8 *p_pbl_virt = NULL; 3324a91eb52aSYuval Mintz void *p_virt = NULL; 3325a91eb52aSYuval Mintz 3326a91eb52aSYuval Mintz size = page_cnt * sizeof(*pp_virt_addr_tbl); 33272591c280SJoe Perches pp_virt_addr_tbl = vzalloc(size); 33282591c280SJoe Perches if (!pp_virt_addr_tbl) 3329a91eb52aSYuval Mintz return -ENOMEM; 3330a91eb52aSYuval Mintz 3331a91eb52aSYuval Mintz /* The allocation of the PBL table is done with its full size, since it 3332a91eb52aSYuval Mintz * is expected to be successive. 3333a91eb52aSYuval Mintz * qed_chain_init_pbl_mem() is called even in a case of an allocation 3334a91eb52aSYuval Mintz * failure, since pp_virt_addr_tbl was previously allocated, and it 3335a91eb52aSYuval Mintz * should be saved to allow its freeing during the error flow. 3336a91eb52aSYuval Mintz */ 3337a91eb52aSYuval Mintz size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; 33381a4a6975SMintz, Yuval 33391a4a6975SMintz, Yuval if (!ext_pbl) { 3340a91eb52aSYuval Mintz p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev, 3341a91eb52aSYuval Mintz size, &p_pbl_phys, GFP_KERNEL); 33421a4a6975SMintz, Yuval } else { 33431a4a6975SMintz, Yuval p_pbl_virt = ext_pbl->p_pbl_virt; 33441a4a6975SMintz, Yuval p_pbl_phys = ext_pbl->p_pbl_phys; 33451a4a6975SMintz, Yuval p_chain->b_external_pbl = true; 33461a4a6975SMintz, Yuval } 33471a4a6975SMintz, Yuval 3348a91eb52aSYuval Mintz qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys, 3349a91eb52aSYuval Mintz pp_virt_addr_tbl); 33502591c280SJoe Perches if (!p_pbl_virt) 3351a91eb52aSYuval Mintz return -ENOMEM; 3352a91eb52aSYuval Mintz 3353a91eb52aSYuval Mintz for (i = 0; i < page_cnt; i++) { 3354a91eb52aSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 3355a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 3356a91eb52aSYuval Mintz &p_phys, GFP_KERNEL); 33572591c280SJoe Perches if (!p_virt) 3358a91eb52aSYuval Mintz return -ENOMEM; 3359a91eb52aSYuval Mintz 3360a91eb52aSYuval Mintz if (i == 0) { 3361a91eb52aSYuval Mintz qed_chain_init_mem(p_chain, p_virt, p_phys); 3362a91eb52aSYuval Mintz qed_chain_reset(p_chain); 3363a91eb52aSYuval Mintz } 3364a91eb52aSYuval Mintz 3365a91eb52aSYuval Mintz /* Fill the PBL table with the physical address of the page */ 3366a91eb52aSYuval Mintz *(dma_addr_t *)p_pbl_virt = p_phys; 3367a91eb52aSYuval Mintz /* Keep the virtual address of the page */ 3368a91eb52aSYuval Mintz p_chain->pbl.pp_virt_addr_tbl[i] = p_virt; 3369a91eb52aSYuval Mintz 3370a91eb52aSYuval Mintz p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE; 3371a91eb52aSYuval Mintz } 3372a91eb52aSYuval Mintz 3373a91eb52aSYuval Mintz return 0; 3374a91eb52aSYuval Mintz } 3375a91eb52aSYuval Mintz 3376fe56b9e6SYuval Mintz int qed_chain_alloc(struct qed_dev *cdev, 3377fe56b9e6SYuval Mintz enum qed_chain_use_mode intended_use, 3378fe56b9e6SYuval Mintz enum qed_chain_mode mode, 3379a91eb52aSYuval Mintz enum qed_chain_cnt_type cnt_type, 33801a4a6975SMintz, Yuval u32 num_elems, 33811a4a6975SMintz, Yuval size_t elem_size, 33821a4a6975SMintz, Yuval struct qed_chain *p_chain, 33831a4a6975SMintz, Yuval struct qed_chain_ext_pbl *ext_pbl) 3384fe56b9e6SYuval Mintz { 3385a91eb52aSYuval Mintz u32 page_cnt; 3386a91eb52aSYuval Mintz int rc = 0; 3387fe56b9e6SYuval Mintz 3388fe56b9e6SYuval Mintz if (mode == QED_CHAIN_MODE_SINGLE) 3389fe56b9e6SYuval Mintz page_cnt = 1; 3390fe56b9e6SYuval Mintz else 3391fe56b9e6SYuval Mintz page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode); 3392fe56b9e6SYuval Mintz 3393a91eb52aSYuval Mintz rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt); 3394a91eb52aSYuval Mintz if (rc) { 3395a91eb52aSYuval Mintz DP_NOTICE(cdev, 33962591c280SJoe Perches "Cannot allocate a chain with the given arguments:\n"); 33972591c280SJoe Perches DP_NOTICE(cdev, 3398a91eb52aSYuval Mintz "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n", 3399a91eb52aSYuval Mintz intended_use, mode, cnt_type, num_elems, elem_size); 3400a91eb52aSYuval Mintz return rc; 3401fe56b9e6SYuval Mintz } 3402fe56b9e6SYuval Mintz 3403a91eb52aSYuval Mintz qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use, 3404a91eb52aSYuval Mintz mode, cnt_type); 3405fe56b9e6SYuval Mintz 3406a91eb52aSYuval Mintz switch (mode) { 3407a91eb52aSYuval Mintz case QED_CHAIN_MODE_NEXT_PTR: 3408a91eb52aSYuval Mintz rc = qed_chain_alloc_next_ptr(cdev, p_chain); 3409a91eb52aSYuval Mintz break; 3410a91eb52aSYuval Mintz case QED_CHAIN_MODE_SINGLE: 3411a91eb52aSYuval Mintz rc = qed_chain_alloc_single(cdev, p_chain); 3412a91eb52aSYuval Mintz break; 3413a91eb52aSYuval Mintz case QED_CHAIN_MODE_PBL: 34141a4a6975SMintz, Yuval rc = qed_chain_alloc_pbl(cdev, p_chain, ext_pbl); 3415a91eb52aSYuval Mintz break; 3416fe56b9e6SYuval Mintz } 3417a91eb52aSYuval Mintz if (rc) 3418a91eb52aSYuval Mintz goto nomem; 3419fe56b9e6SYuval Mintz 3420fe56b9e6SYuval Mintz return 0; 3421fe56b9e6SYuval Mintz 3422fe56b9e6SYuval Mintz nomem: 3423a91eb52aSYuval Mintz qed_chain_free(cdev, p_chain); 3424a91eb52aSYuval Mintz return rc; 3425fe56b9e6SYuval Mintz } 3426fe56b9e6SYuval Mintz 3427a91eb52aSYuval Mintz int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id) 3428cee4d264SManish Chopra { 3429cee4d264SManish Chopra if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) { 3430cee4d264SManish Chopra u16 min, max; 3431cee4d264SManish Chopra 3432cee4d264SManish Chopra min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE); 3433cee4d264SManish Chopra max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE); 3434cee4d264SManish Chopra DP_NOTICE(p_hwfn, 3435cee4d264SManish Chopra "l2_queue id [%d] is not valid, available indices [%d - %d]\n", 3436cee4d264SManish Chopra src_id, min, max); 3437cee4d264SManish Chopra 3438cee4d264SManish Chopra return -EINVAL; 3439cee4d264SManish Chopra } 3440cee4d264SManish Chopra 3441cee4d264SManish Chopra *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id; 3442cee4d264SManish Chopra 3443cee4d264SManish Chopra return 0; 3444cee4d264SManish Chopra } 3445cee4d264SManish Chopra 34461a635e48SYuval Mintz int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id) 3447cee4d264SManish Chopra { 3448cee4d264SManish Chopra if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) { 3449cee4d264SManish Chopra u8 min, max; 3450cee4d264SManish Chopra 3451cee4d264SManish Chopra min = (u8)RESC_START(p_hwfn, QED_VPORT); 3452cee4d264SManish Chopra max = min + RESC_NUM(p_hwfn, QED_VPORT); 3453cee4d264SManish Chopra DP_NOTICE(p_hwfn, 3454cee4d264SManish Chopra "vport id [%d] is not valid, available indices [%d - %d]\n", 3455cee4d264SManish Chopra src_id, min, max); 3456cee4d264SManish Chopra 3457cee4d264SManish Chopra return -EINVAL; 3458cee4d264SManish Chopra } 3459cee4d264SManish Chopra 3460cee4d264SManish Chopra *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id; 3461cee4d264SManish Chopra 3462cee4d264SManish Chopra return 0; 3463cee4d264SManish Chopra } 3464cee4d264SManish Chopra 34651a635e48SYuval Mintz int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id) 3466cee4d264SManish Chopra { 3467cee4d264SManish Chopra if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) { 3468cee4d264SManish Chopra u8 min, max; 3469cee4d264SManish Chopra 3470cee4d264SManish Chopra min = (u8)RESC_START(p_hwfn, QED_RSS_ENG); 3471cee4d264SManish Chopra max = min + RESC_NUM(p_hwfn, QED_RSS_ENG); 3472cee4d264SManish Chopra DP_NOTICE(p_hwfn, 3473cee4d264SManish Chopra "rss_eng id [%d] is not valid, available indices [%d - %d]\n", 3474cee4d264SManish Chopra src_id, min, max); 3475cee4d264SManish Chopra 3476cee4d264SManish Chopra return -EINVAL; 3477cee4d264SManish Chopra } 3478cee4d264SManish Chopra 3479cee4d264SManish Chopra *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id; 3480cee4d264SManish Chopra 3481cee4d264SManish Chopra return 0; 3482cee4d264SManish Chopra } 3483bcd197c8SManish Chopra 34840a7fb11cSYuval Mintz static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low, 34850a7fb11cSYuval Mintz u8 *p_filter) 34860a7fb11cSYuval Mintz { 34870a7fb11cSYuval Mintz *p_high = p_filter[1] | (p_filter[0] << 8); 34880a7fb11cSYuval Mintz *p_low = p_filter[5] | (p_filter[4] << 8) | 34890a7fb11cSYuval Mintz (p_filter[3] << 16) | (p_filter[2] << 24); 34900a7fb11cSYuval Mintz } 34910a7fb11cSYuval Mintz 34920a7fb11cSYuval Mintz int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn, 34930a7fb11cSYuval Mintz struct qed_ptt *p_ptt, u8 *p_filter) 34940a7fb11cSYuval Mintz { 34950a7fb11cSYuval Mintz u32 high = 0, low = 0, en; 34960a7fb11cSYuval Mintz int i; 34970a7fb11cSYuval Mintz 34980bc5fe85SSudarsana Reddy Kalluru if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits)) 34990a7fb11cSYuval Mintz return 0; 35000a7fb11cSYuval Mintz 35010a7fb11cSYuval Mintz qed_llh_mac_to_filter(&high, &low, p_filter); 35020a7fb11cSYuval Mintz 35030a7fb11cSYuval Mintz /* Find a free entry and utilize it */ 35040a7fb11cSYuval Mintz for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 35050a7fb11cSYuval Mintz en = qed_rd(p_hwfn, p_ptt, 35060a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)); 35070a7fb11cSYuval Mintz if (en) 35080a7fb11cSYuval Mintz continue; 35090a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 35100a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 35110a7fb11cSYuval Mintz 2 * i * sizeof(u32), low); 35120a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 35130a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 35140a7fb11cSYuval Mintz (2 * i + 1) * sizeof(u32), high); 35150a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 35160a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0); 35170a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 35180a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 35190a7fb11cSYuval Mintz i * sizeof(u32), 0); 35200a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 35210a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1); 35220a7fb11cSYuval Mintz break; 35230a7fb11cSYuval Mintz } 35240a7fb11cSYuval Mintz if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) { 35250a7fb11cSYuval Mintz DP_NOTICE(p_hwfn, 35260a7fb11cSYuval Mintz "Failed to find an empty LLH filter to utilize\n"); 35270a7fb11cSYuval Mintz return -EINVAL; 35280a7fb11cSYuval Mintz } 35290a7fb11cSYuval Mintz 35300a7fb11cSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 35310a7fb11cSYuval Mintz "mac: %pM is added at %d\n", 35320a7fb11cSYuval Mintz p_filter, i); 35330a7fb11cSYuval Mintz 35340a7fb11cSYuval Mintz return 0; 35350a7fb11cSYuval Mintz } 35360a7fb11cSYuval Mintz 35370a7fb11cSYuval Mintz void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn, 35380a7fb11cSYuval Mintz struct qed_ptt *p_ptt, u8 *p_filter) 35390a7fb11cSYuval Mintz { 35400a7fb11cSYuval Mintz u32 high = 0, low = 0; 35410a7fb11cSYuval Mintz int i; 35420a7fb11cSYuval Mintz 35430bc5fe85SSudarsana Reddy Kalluru if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits)) 35440a7fb11cSYuval Mintz return; 35450a7fb11cSYuval Mintz 35460a7fb11cSYuval Mintz qed_llh_mac_to_filter(&high, &low, p_filter); 35470a7fb11cSYuval Mintz 35480a7fb11cSYuval Mintz /* Find the entry and clean it */ 35490a7fb11cSYuval Mintz for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 35500a7fb11cSYuval Mintz if (qed_rd(p_hwfn, p_ptt, 35510a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 35520a7fb11cSYuval Mintz 2 * i * sizeof(u32)) != low) 35530a7fb11cSYuval Mintz continue; 35540a7fb11cSYuval Mintz if (qed_rd(p_hwfn, p_ptt, 35550a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 35560a7fb11cSYuval Mintz (2 * i + 1) * sizeof(u32)) != high) 35570a7fb11cSYuval Mintz continue; 35580a7fb11cSYuval Mintz 35590a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 35600a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0); 35610a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 35620a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0); 35630a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 35640a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 35650a7fb11cSYuval Mintz (2 * i + 1) * sizeof(u32), 0); 35660a7fb11cSYuval Mintz 35670a7fb11cSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 35680a7fb11cSYuval Mintz "mac: %pM is removed from %d\n", 35690a7fb11cSYuval Mintz p_filter, i); 35700a7fb11cSYuval Mintz break; 35710a7fb11cSYuval Mintz } 35720a7fb11cSYuval Mintz if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) 35730a7fb11cSYuval Mintz DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n"); 35740a7fb11cSYuval Mintz } 35750a7fb11cSYuval Mintz 35761e128c81SArun Easi int 35771e128c81SArun Easi qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn, 35781e128c81SArun Easi struct qed_ptt *p_ptt, 35791e128c81SArun Easi u16 source_port_or_eth_type, 35801e128c81SArun Easi u16 dest_port, enum qed_llh_port_filter_type_t type) 35811e128c81SArun Easi { 35821e128c81SArun Easi u32 high = 0, low = 0, en; 35831e128c81SArun Easi int i; 35841e128c81SArun Easi 35850bc5fe85SSudarsana Reddy Kalluru if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits)) 35861e128c81SArun Easi return 0; 35871e128c81SArun Easi 35881e128c81SArun Easi switch (type) { 35891e128c81SArun Easi case QED_LLH_FILTER_ETHERTYPE: 35901e128c81SArun Easi high = source_port_or_eth_type; 35911e128c81SArun Easi break; 35921e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_PORT: 35931e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_PORT: 35941e128c81SArun Easi low = source_port_or_eth_type << 16; 35951e128c81SArun Easi break; 35961e128c81SArun Easi case QED_LLH_FILTER_TCP_DEST_PORT: 35971e128c81SArun Easi case QED_LLH_FILTER_UDP_DEST_PORT: 35981e128c81SArun Easi low = dest_port; 35991e128c81SArun Easi break; 36001e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 36011e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 36021e128c81SArun Easi low = (source_port_or_eth_type << 16) | dest_port; 36031e128c81SArun Easi break; 36041e128c81SArun Easi default: 36051e128c81SArun Easi DP_NOTICE(p_hwfn, 36061e128c81SArun Easi "Non valid LLH protocol filter type %d\n", type); 36071e128c81SArun Easi return -EINVAL; 36081e128c81SArun Easi } 36091e128c81SArun Easi /* Find a free entry and utilize it */ 36101e128c81SArun Easi for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 36111e128c81SArun Easi en = qed_rd(p_hwfn, p_ptt, 36121e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)); 36131e128c81SArun Easi if (en) 36141e128c81SArun Easi continue; 36151e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 36161e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 36171e128c81SArun Easi 2 * i * sizeof(u32), low); 36181e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 36191e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 36201e128c81SArun Easi (2 * i + 1) * sizeof(u32), high); 36211e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 36221e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1); 36231e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 36241e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 36251e128c81SArun Easi i * sizeof(u32), 1 << type); 36261e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 36271e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1); 36281e128c81SArun Easi break; 36291e128c81SArun Easi } 36301e128c81SArun Easi if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) { 36311e128c81SArun Easi DP_NOTICE(p_hwfn, 36321e128c81SArun Easi "Failed to find an empty LLH filter to utilize\n"); 36331e128c81SArun Easi return -EINVAL; 36341e128c81SArun Easi } 36351e128c81SArun Easi switch (type) { 36361e128c81SArun Easi case QED_LLH_FILTER_ETHERTYPE: 36371e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 36381e128c81SArun Easi "ETH type %x is added at %d\n", 36391e128c81SArun Easi source_port_or_eth_type, i); 36401e128c81SArun Easi break; 36411e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_PORT: 36421e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 36431e128c81SArun Easi "TCP src port %x is added at %d\n", 36441e128c81SArun Easi source_port_or_eth_type, i); 36451e128c81SArun Easi break; 36461e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_PORT: 36471e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 36481e128c81SArun Easi "UDP src port %x is added at %d\n", 36491e128c81SArun Easi source_port_or_eth_type, i); 36501e128c81SArun Easi break; 36511e128c81SArun Easi case QED_LLH_FILTER_TCP_DEST_PORT: 36521e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 36531e128c81SArun Easi "TCP dst port %x is added at %d\n", dest_port, i); 36541e128c81SArun Easi break; 36551e128c81SArun Easi case QED_LLH_FILTER_UDP_DEST_PORT: 36561e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 36571e128c81SArun Easi "UDP dst port %x is added at %d\n", dest_port, i); 36581e128c81SArun Easi break; 36591e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 36601e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 36611e128c81SArun Easi "TCP src/dst ports %x/%x are added at %d\n", 36621e128c81SArun Easi source_port_or_eth_type, dest_port, i); 36631e128c81SArun Easi break; 36641e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 36651e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 36661e128c81SArun Easi "UDP src/dst ports %x/%x are added at %d\n", 36671e128c81SArun Easi source_port_or_eth_type, dest_port, i); 36681e128c81SArun Easi break; 36691e128c81SArun Easi } 36701e128c81SArun Easi return 0; 36711e128c81SArun Easi } 36721e128c81SArun Easi 36731e128c81SArun Easi void 36741e128c81SArun Easi qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn, 36751e128c81SArun Easi struct qed_ptt *p_ptt, 36761e128c81SArun Easi u16 source_port_or_eth_type, 36771e128c81SArun Easi u16 dest_port, 36781e128c81SArun Easi enum qed_llh_port_filter_type_t type) 36791e128c81SArun Easi { 36801e128c81SArun Easi u32 high = 0, low = 0; 36811e128c81SArun Easi int i; 36821e128c81SArun Easi 36830bc5fe85SSudarsana Reddy Kalluru if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits)) 36841e128c81SArun Easi return; 36851e128c81SArun Easi 36861e128c81SArun Easi switch (type) { 36871e128c81SArun Easi case QED_LLH_FILTER_ETHERTYPE: 36881e128c81SArun Easi high = source_port_or_eth_type; 36891e128c81SArun Easi break; 36901e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_PORT: 36911e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_PORT: 36921e128c81SArun Easi low = source_port_or_eth_type << 16; 36931e128c81SArun Easi break; 36941e128c81SArun Easi case QED_LLH_FILTER_TCP_DEST_PORT: 36951e128c81SArun Easi case QED_LLH_FILTER_UDP_DEST_PORT: 36961e128c81SArun Easi low = dest_port; 36971e128c81SArun Easi break; 36981e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 36991e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 37001e128c81SArun Easi low = (source_port_or_eth_type << 16) | dest_port; 37011e128c81SArun Easi break; 37021e128c81SArun Easi default: 37031e128c81SArun Easi DP_NOTICE(p_hwfn, 37041e128c81SArun Easi "Non valid LLH protocol filter type %d\n", type); 37051e128c81SArun Easi return; 37061e128c81SArun Easi } 37071e128c81SArun Easi 37081e128c81SArun Easi for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 37091e128c81SArun Easi if (!qed_rd(p_hwfn, p_ptt, 37101e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32))) 37111e128c81SArun Easi continue; 37121e128c81SArun Easi if (!qed_rd(p_hwfn, p_ptt, 37131e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32))) 37141e128c81SArun Easi continue; 37151e128c81SArun Easi if (!(qed_rd(p_hwfn, p_ptt, 37161e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 37171e128c81SArun Easi i * sizeof(u32)) & BIT(type))) 37181e128c81SArun Easi continue; 37191e128c81SArun Easi if (qed_rd(p_hwfn, p_ptt, 37201e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 37211e128c81SArun Easi 2 * i * sizeof(u32)) != low) 37221e128c81SArun Easi continue; 37231e128c81SArun Easi if (qed_rd(p_hwfn, p_ptt, 37241e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 37251e128c81SArun Easi (2 * i + 1) * sizeof(u32)) != high) 37261e128c81SArun Easi continue; 37271e128c81SArun Easi 37281e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 37291e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0); 37301e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 37311e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0); 37321e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 37331e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 37341e128c81SArun Easi i * sizeof(u32), 0); 37351e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 37361e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0); 37371e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 37381e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 37391e128c81SArun Easi (2 * i + 1) * sizeof(u32), 0); 37401e128c81SArun Easi break; 37411e128c81SArun Easi } 37421e128c81SArun Easi 37431e128c81SArun Easi if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) 37441e128c81SArun Easi DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n"); 37451e128c81SArun Easi } 37461e128c81SArun Easi 3747722003acSSudarsana Reddy Kalluru static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 3748722003acSSudarsana Reddy Kalluru u32 hw_addr, void *p_eth_qzone, 3749722003acSSudarsana Reddy Kalluru size_t eth_qzone_size, u8 timeset) 3750722003acSSudarsana Reddy Kalluru { 3751722003acSSudarsana Reddy Kalluru struct coalescing_timeset *p_coal_timeset; 3752722003acSSudarsana Reddy Kalluru 3753722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) { 3754722003acSSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n"); 3755722003acSSudarsana Reddy Kalluru return -EINVAL; 3756722003acSSudarsana Reddy Kalluru } 3757722003acSSudarsana Reddy Kalluru 3758722003acSSudarsana Reddy Kalluru p_coal_timeset = p_eth_qzone; 3759477f2d14SRahul Verma memset(p_eth_qzone, 0, eth_qzone_size); 3760722003acSSudarsana Reddy Kalluru SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset); 3761722003acSSudarsana Reddy Kalluru SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1); 3762722003acSSudarsana Reddy Kalluru qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size); 3763722003acSSudarsana Reddy Kalluru 3764722003acSSudarsana Reddy Kalluru return 0; 3765722003acSSudarsana Reddy Kalluru } 3766722003acSSudarsana Reddy Kalluru 3767477f2d14SRahul Verma int qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle) 3768477f2d14SRahul Verma { 3769477f2d14SRahul Verma struct qed_queue_cid *p_cid = p_handle; 3770477f2d14SRahul Verma struct qed_hwfn *p_hwfn; 3771477f2d14SRahul Verma struct qed_ptt *p_ptt; 3772477f2d14SRahul Verma int rc = 0; 3773477f2d14SRahul Verma 3774477f2d14SRahul Verma p_hwfn = p_cid->p_owner; 3775477f2d14SRahul Verma 3776477f2d14SRahul Verma if (IS_VF(p_hwfn->cdev)) 3777477f2d14SRahul Verma return qed_vf_pf_set_coalesce(p_hwfn, rx_coal, tx_coal, p_cid); 3778477f2d14SRahul Verma 3779477f2d14SRahul Verma p_ptt = qed_ptt_acquire(p_hwfn); 3780477f2d14SRahul Verma if (!p_ptt) 3781477f2d14SRahul Verma return -EAGAIN; 3782477f2d14SRahul Verma 3783477f2d14SRahul Verma if (rx_coal) { 3784477f2d14SRahul Verma rc = qed_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid); 3785477f2d14SRahul Verma if (rc) 3786477f2d14SRahul Verma goto out; 3787477f2d14SRahul Verma p_hwfn->cdev->rx_coalesce_usecs = rx_coal; 3788477f2d14SRahul Verma } 3789477f2d14SRahul Verma 3790477f2d14SRahul Verma if (tx_coal) { 3791477f2d14SRahul Verma rc = qed_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid); 3792477f2d14SRahul Verma if (rc) 3793477f2d14SRahul Verma goto out; 3794477f2d14SRahul Verma p_hwfn->cdev->tx_coalesce_usecs = tx_coal; 3795477f2d14SRahul Verma } 3796477f2d14SRahul Verma out: 3797477f2d14SRahul Verma qed_ptt_release(p_hwfn, p_ptt); 3798477f2d14SRahul Verma return rc; 3799477f2d14SRahul Verma } 3800477f2d14SRahul Verma 3801477f2d14SRahul Verma int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, 3802477f2d14SRahul Verma struct qed_ptt *p_ptt, 3803477f2d14SRahul Verma u16 coalesce, struct qed_queue_cid *p_cid) 3804722003acSSudarsana Reddy Kalluru { 3805722003acSSudarsana Reddy Kalluru struct ustorm_eth_queue_zone eth_qzone; 3806722003acSSudarsana Reddy Kalluru u8 timeset, timer_res; 3807722003acSSudarsana Reddy Kalluru u32 address; 3808722003acSSudarsana Reddy Kalluru int rc; 3809722003acSSudarsana Reddy Kalluru 3810722003acSSudarsana Reddy Kalluru /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 3811722003acSSudarsana Reddy Kalluru if (coalesce <= 0x7F) { 3812722003acSSudarsana Reddy Kalluru timer_res = 0; 3813722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0xFF) { 3814722003acSSudarsana Reddy Kalluru timer_res = 1; 3815722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0x1FF) { 3816722003acSSudarsana Reddy Kalluru timer_res = 2; 3817722003acSSudarsana Reddy Kalluru } else { 3818722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 3819722003acSSudarsana Reddy Kalluru return -EINVAL; 3820722003acSSudarsana Reddy Kalluru } 3821722003acSSudarsana Reddy Kalluru timeset = (u8)(coalesce >> timer_res); 3822722003acSSudarsana Reddy Kalluru 3823477f2d14SRahul Verma rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, 3824477f2d14SRahul Verma p_cid->sb_igu_id, false); 3825722003acSSudarsana Reddy Kalluru if (rc) 3826722003acSSudarsana Reddy Kalluru goto out; 3827722003acSSudarsana Reddy Kalluru 3828477f2d14SRahul Verma address = BAR0_MAP_REG_USDM_RAM + 3829477f2d14SRahul Verma USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id); 3830722003acSSudarsana Reddy Kalluru 3831722003acSSudarsana Reddy Kalluru rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 3832722003acSSudarsana Reddy Kalluru sizeof(struct ustorm_eth_queue_zone), timeset); 3833722003acSSudarsana Reddy Kalluru if (rc) 3834722003acSSudarsana Reddy Kalluru goto out; 3835722003acSSudarsana Reddy Kalluru 3836722003acSSudarsana Reddy Kalluru out: 3837722003acSSudarsana Reddy Kalluru return rc; 3838722003acSSudarsana Reddy Kalluru } 3839722003acSSudarsana Reddy Kalluru 3840477f2d14SRahul Verma int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, 3841477f2d14SRahul Verma struct qed_ptt *p_ptt, 3842477f2d14SRahul Verma u16 coalesce, struct qed_queue_cid *p_cid) 3843722003acSSudarsana Reddy Kalluru { 3844722003acSSudarsana Reddy Kalluru struct xstorm_eth_queue_zone eth_qzone; 3845722003acSSudarsana Reddy Kalluru u8 timeset, timer_res; 3846722003acSSudarsana Reddy Kalluru u32 address; 3847722003acSSudarsana Reddy Kalluru int rc; 3848722003acSSudarsana Reddy Kalluru 3849722003acSSudarsana Reddy Kalluru /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 3850722003acSSudarsana Reddy Kalluru if (coalesce <= 0x7F) { 3851722003acSSudarsana Reddy Kalluru timer_res = 0; 3852722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0xFF) { 3853722003acSSudarsana Reddy Kalluru timer_res = 1; 3854722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0x1FF) { 3855722003acSSudarsana Reddy Kalluru timer_res = 2; 3856722003acSSudarsana Reddy Kalluru } else { 3857722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 3858722003acSSudarsana Reddy Kalluru return -EINVAL; 3859722003acSSudarsana Reddy Kalluru } 3860722003acSSudarsana Reddy Kalluru timeset = (u8)(coalesce >> timer_res); 3861722003acSSudarsana Reddy Kalluru 3862477f2d14SRahul Verma rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, 3863477f2d14SRahul Verma p_cid->sb_igu_id, true); 3864722003acSSudarsana Reddy Kalluru if (rc) 3865722003acSSudarsana Reddy Kalluru goto out; 3866722003acSSudarsana Reddy Kalluru 3867477f2d14SRahul Verma address = BAR0_MAP_REG_XSDM_RAM + 3868477f2d14SRahul Verma XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id); 3869722003acSSudarsana Reddy Kalluru 3870722003acSSudarsana Reddy Kalluru rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 3871722003acSSudarsana Reddy Kalluru sizeof(struct xstorm_eth_queue_zone), timeset); 3872722003acSSudarsana Reddy Kalluru out: 3873722003acSSudarsana Reddy Kalluru return rc; 3874722003acSSudarsana Reddy Kalluru } 3875722003acSSudarsana Reddy Kalluru 3876bcd197c8SManish Chopra /* Calculate final WFQ values for all vports and configure them. 3877bcd197c8SManish Chopra * After this configuration each vport will have 3878bcd197c8SManish Chopra * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT) 3879bcd197c8SManish Chopra */ 3880bcd197c8SManish Chopra static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 3881bcd197c8SManish Chopra struct qed_ptt *p_ptt, 3882bcd197c8SManish Chopra u32 min_pf_rate) 3883bcd197c8SManish Chopra { 3884bcd197c8SManish Chopra struct init_qm_vport_params *vport_params; 3885bcd197c8SManish Chopra int i; 3886bcd197c8SManish Chopra 3887bcd197c8SManish Chopra vport_params = p_hwfn->qm_info.qm_vport_params; 3888bcd197c8SManish Chopra 3889bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 3890bcd197c8SManish Chopra u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 3891bcd197c8SManish Chopra 3892bcd197c8SManish Chopra vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) / 3893bcd197c8SManish Chopra min_pf_rate; 3894bcd197c8SManish Chopra qed_init_vport_wfq(p_hwfn, p_ptt, 3895bcd197c8SManish Chopra vport_params[i].first_tx_pq_id, 3896bcd197c8SManish Chopra vport_params[i].vport_wfq); 3897bcd197c8SManish Chopra } 3898bcd197c8SManish Chopra } 3899bcd197c8SManish Chopra 3900bcd197c8SManish Chopra static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn, 3901bcd197c8SManish Chopra u32 min_pf_rate) 3902bcd197c8SManish Chopra 3903bcd197c8SManish Chopra { 3904bcd197c8SManish Chopra int i; 3905bcd197c8SManish Chopra 3906bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) 3907bcd197c8SManish Chopra p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1; 3908bcd197c8SManish Chopra } 3909bcd197c8SManish Chopra 3910bcd197c8SManish Chopra static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 3911bcd197c8SManish Chopra struct qed_ptt *p_ptt, 3912bcd197c8SManish Chopra u32 min_pf_rate) 3913bcd197c8SManish Chopra { 3914bcd197c8SManish Chopra struct init_qm_vport_params *vport_params; 3915bcd197c8SManish Chopra int i; 3916bcd197c8SManish Chopra 3917bcd197c8SManish Chopra vport_params = p_hwfn->qm_info.qm_vport_params; 3918bcd197c8SManish Chopra 3919bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 3920bcd197c8SManish Chopra qed_init_wfq_default_param(p_hwfn, min_pf_rate); 3921bcd197c8SManish Chopra qed_init_vport_wfq(p_hwfn, p_ptt, 3922bcd197c8SManish Chopra vport_params[i].first_tx_pq_id, 3923bcd197c8SManish Chopra vport_params[i].vport_wfq); 3924bcd197c8SManish Chopra } 3925bcd197c8SManish Chopra } 3926bcd197c8SManish Chopra 3927bcd197c8SManish Chopra /* This function performs several validations for WFQ 3928bcd197c8SManish Chopra * configuration and required min rate for a given vport 3929bcd197c8SManish Chopra * 1. req_rate must be greater than one percent of min_pf_rate. 3930bcd197c8SManish Chopra * 2. req_rate should not cause other vports [not configured for WFQ explicitly] 3931bcd197c8SManish Chopra * rates to get less than one percent of min_pf_rate. 3932bcd197c8SManish Chopra * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate. 3933bcd197c8SManish Chopra */ 3934bcd197c8SManish Chopra static int qed_init_wfq_param(struct qed_hwfn *p_hwfn, 39351a635e48SYuval Mintz u16 vport_id, u32 req_rate, u32 min_pf_rate) 3936bcd197c8SManish Chopra { 3937bcd197c8SManish Chopra u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0; 3938bcd197c8SManish Chopra int non_requested_count = 0, req_count = 0, i, num_vports; 3939bcd197c8SManish Chopra 3940bcd197c8SManish Chopra num_vports = p_hwfn->qm_info.num_vports; 3941bcd197c8SManish Chopra 3942bcd197c8SManish Chopra /* Accounting for the vports which are configured for WFQ explicitly */ 3943bcd197c8SManish Chopra for (i = 0; i < num_vports; i++) { 3944bcd197c8SManish Chopra u32 tmp_speed; 3945bcd197c8SManish Chopra 3946bcd197c8SManish Chopra if ((i != vport_id) && 3947bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[i].configured) { 3948bcd197c8SManish Chopra req_count++; 3949bcd197c8SManish Chopra tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 3950bcd197c8SManish Chopra total_req_min_rate += tmp_speed; 3951bcd197c8SManish Chopra } 3952bcd197c8SManish Chopra } 3953bcd197c8SManish Chopra 3954bcd197c8SManish Chopra /* Include current vport data as well */ 3955bcd197c8SManish Chopra req_count++; 3956bcd197c8SManish Chopra total_req_min_rate += req_rate; 3957bcd197c8SManish Chopra non_requested_count = num_vports - req_count; 3958bcd197c8SManish Chopra 3959bcd197c8SManish Chopra if (req_rate < min_pf_rate / QED_WFQ_UNIT) { 3960bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 3961bcd197c8SManish Chopra "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 3962bcd197c8SManish Chopra vport_id, req_rate, min_pf_rate); 3963bcd197c8SManish Chopra return -EINVAL; 3964bcd197c8SManish Chopra } 3965bcd197c8SManish Chopra 3966bcd197c8SManish Chopra if (num_vports > QED_WFQ_UNIT) { 3967bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 3968bcd197c8SManish Chopra "Number of vports is greater than %d\n", 3969bcd197c8SManish Chopra QED_WFQ_UNIT); 3970bcd197c8SManish Chopra return -EINVAL; 3971bcd197c8SManish Chopra } 3972bcd197c8SManish Chopra 3973bcd197c8SManish Chopra if (total_req_min_rate > min_pf_rate) { 3974bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 3975bcd197c8SManish Chopra "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n", 3976bcd197c8SManish Chopra total_req_min_rate, min_pf_rate); 3977bcd197c8SManish Chopra return -EINVAL; 3978bcd197c8SManish Chopra } 3979bcd197c8SManish Chopra 3980bcd197c8SManish Chopra total_left_rate = min_pf_rate - total_req_min_rate; 3981bcd197c8SManish Chopra 3982bcd197c8SManish Chopra left_rate_per_vp = total_left_rate / non_requested_count; 3983bcd197c8SManish Chopra if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) { 3984bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 3985bcd197c8SManish Chopra "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 3986bcd197c8SManish Chopra left_rate_per_vp, min_pf_rate); 3987bcd197c8SManish Chopra return -EINVAL; 3988bcd197c8SManish Chopra } 3989bcd197c8SManish Chopra 3990bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate; 3991bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[vport_id].configured = true; 3992bcd197c8SManish Chopra 3993bcd197c8SManish Chopra for (i = 0; i < num_vports; i++) { 3994bcd197c8SManish Chopra if (p_hwfn->qm_info.wfq_data[i].configured) 3995bcd197c8SManish Chopra continue; 3996bcd197c8SManish Chopra 3997bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp; 3998bcd197c8SManish Chopra } 3999bcd197c8SManish Chopra 4000bcd197c8SManish Chopra return 0; 4001bcd197c8SManish Chopra } 4002bcd197c8SManish Chopra 4003733def6aSYuval Mintz static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn, 4004733def6aSYuval Mintz struct qed_ptt *p_ptt, u16 vp_id, u32 rate) 4005733def6aSYuval Mintz { 4006733def6aSYuval Mintz struct qed_mcp_link_state *p_link; 4007733def6aSYuval Mintz int rc = 0; 4008733def6aSYuval Mintz 4009733def6aSYuval Mintz p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output; 4010733def6aSYuval Mintz 4011733def6aSYuval Mintz if (!p_link->min_pf_rate) { 4012733def6aSYuval Mintz p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate; 4013733def6aSYuval Mintz p_hwfn->qm_info.wfq_data[vp_id].configured = true; 4014733def6aSYuval Mintz return rc; 4015733def6aSYuval Mintz } 4016733def6aSYuval Mintz 4017733def6aSYuval Mintz rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate); 4018733def6aSYuval Mintz 40191a635e48SYuval Mintz if (!rc) 4020733def6aSYuval Mintz qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, 4021733def6aSYuval Mintz p_link->min_pf_rate); 4022733def6aSYuval Mintz else 4023733def6aSYuval Mintz DP_NOTICE(p_hwfn, 4024733def6aSYuval Mintz "Validation failed while configuring min rate\n"); 4025733def6aSYuval Mintz 4026733def6aSYuval Mintz return rc; 4027733def6aSYuval Mintz } 4028733def6aSYuval Mintz 4029bcd197c8SManish Chopra static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn, 4030bcd197c8SManish Chopra struct qed_ptt *p_ptt, 4031bcd197c8SManish Chopra u32 min_pf_rate) 4032bcd197c8SManish Chopra { 4033bcd197c8SManish Chopra bool use_wfq = false; 4034bcd197c8SManish Chopra int rc = 0; 4035bcd197c8SManish Chopra u16 i; 4036bcd197c8SManish Chopra 4037bcd197c8SManish Chopra /* Validate all pre configured vports for wfq */ 4038bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 4039bcd197c8SManish Chopra u32 rate; 4040bcd197c8SManish Chopra 4041bcd197c8SManish Chopra if (!p_hwfn->qm_info.wfq_data[i].configured) 4042bcd197c8SManish Chopra continue; 4043bcd197c8SManish Chopra 4044bcd197c8SManish Chopra rate = p_hwfn->qm_info.wfq_data[i].min_speed; 4045bcd197c8SManish Chopra use_wfq = true; 4046bcd197c8SManish Chopra 4047bcd197c8SManish Chopra rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate); 4048bcd197c8SManish Chopra if (rc) { 4049bcd197c8SManish Chopra DP_NOTICE(p_hwfn, 4050bcd197c8SManish Chopra "WFQ validation failed while configuring min rate\n"); 4051bcd197c8SManish Chopra break; 4052bcd197c8SManish Chopra } 4053bcd197c8SManish Chopra } 4054bcd197c8SManish Chopra 4055bcd197c8SManish Chopra if (!rc && use_wfq) 4056bcd197c8SManish Chopra qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 4057bcd197c8SManish Chopra else 4058bcd197c8SManish Chopra qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 4059bcd197c8SManish Chopra 4060bcd197c8SManish Chopra return rc; 4061bcd197c8SManish Chopra } 4062bcd197c8SManish Chopra 4063733def6aSYuval Mintz /* Main API for qed clients to configure vport min rate. 4064733def6aSYuval Mintz * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)] 4065733def6aSYuval Mintz * rate - Speed in Mbps needs to be assigned to a given vport. 4066733def6aSYuval Mintz */ 4067733def6aSYuval Mintz int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate) 4068733def6aSYuval Mintz { 4069733def6aSYuval Mintz int i, rc = -EINVAL; 4070733def6aSYuval Mintz 4071733def6aSYuval Mintz /* Currently not supported; Might change in future */ 4072733def6aSYuval Mintz if (cdev->num_hwfns > 1) { 4073733def6aSYuval Mintz DP_NOTICE(cdev, 4074733def6aSYuval Mintz "WFQ configuration is not supported for this device\n"); 4075733def6aSYuval Mintz return rc; 4076733def6aSYuval Mintz } 4077733def6aSYuval Mintz 4078733def6aSYuval Mintz for_each_hwfn(cdev, i) { 4079733def6aSYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 4080733def6aSYuval Mintz struct qed_ptt *p_ptt; 4081733def6aSYuval Mintz 4082733def6aSYuval Mintz p_ptt = qed_ptt_acquire(p_hwfn); 4083733def6aSYuval Mintz if (!p_ptt) 4084733def6aSYuval Mintz return -EBUSY; 4085733def6aSYuval Mintz 4086733def6aSYuval Mintz rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate); 4087733def6aSYuval Mintz 4088d572c430SYuval Mintz if (rc) { 4089733def6aSYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 4090733def6aSYuval Mintz return rc; 4091733def6aSYuval Mintz } 4092733def6aSYuval Mintz 4093733def6aSYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 4094733def6aSYuval Mintz } 4095733def6aSYuval Mintz 4096733def6aSYuval Mintz return rc; 4097733def6aSYuval Mintz } 4098733def6aSYuval Mintz 4099bcd197c8SManish Chopra /* API to configure WFQ from mcp link change */ 41006f437d43SMintz, Yuval void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, 41016f437d43SMintz, Yuval struct qed_ptt *p_ptt, u32 min_pf_rate) 4102bcd197c8SManish Chopra { 4103bcd197c8SManish Chopra int i; 4104bcd197c8SManish Chopra 41053e7cfce2SYuval Mintz if (cdev->num_hwfns > 1) { 41063e7cfce2SYuval Mintz DP_VERBOSE(cdev, 41073e7cfce2SYuval Mintz NETIF_MSG_LINK, 41083e7cfce2SYuval Mintz "WFQ configuration is not supported for this device\n"); 41093e7cfce2SYuval Mintz return; 41103e7cfce2SYuval Mintz } 41113e7cfce2SYuval Mintz 4112bcd197c8SManish Chopra for_each_hwfn(cdev, i) { 4113bcd197c8SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 4114bcd197c8SManish Chopra 41156f437d43SMintz, Yuval __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt, 4116bcd197c8SManish Chopra min_pf_rate); 4117bcd197c8SManish Chopra } 4118bcd197c8SManish Chopra } 41194b01e519SManish Chopra 41204b01e519SManish Chopra int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn, 41214b01e519SManish Chopra struct qed_ptt *p_ptt, 41224b01e519SManish Chopra struct qed_mcp_link_state *p_link, 41234b01e519SManish Chopra u8 max_bw) 41244b01e519SManish Chopra { 41254b01e519SManish Chopra int rc = 0; 41264b01e519SManish Chopra 41274b01e519SManish Chopra p_hwfn->mcp_info->func_info.bandwidth_max = max_bw; 41284b01e519SManish Chopra 41294b01e519SManish Chopra if (!p_link->line_speed && (max_bw != 100)) 41304b01e519SManish Chopra return rc; 41314b01e519SManish Chopra 41324b01e519SManish Chopra p_link->speed = (p_link->line_speed * max_bw) / 100; 41334b01e519SManish Chopra p_hwfn->qm_info.pf_rl = p_link->speed; 41344b01e519SManish Chopra 41354b01e519SManish Chopra /* Since the limiter also affects Tx-switched traffic, we don't want it 41364b01e519SManish Chopra * to limit such traffic in case there's no actual limit. 41374b01e519SManish Chopra * In that case, set limit to imaginary high boundary. 41384b01e519SManish Chopra */ 41394b01e519SManish Chopra if (max_bw == 100) 41404b01e519SManish Chopra p_hwfn->qm_info.pf_rl = 100000; 41414b01e519SManish Chopra 41424b01e519SManish Chopra rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, 41434b01e519SManish Chopra p_hwfn->qm_info.pf_rl); 41444b01e519SManish Chopra 41454b01e519SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 41464b01e519SManish Chopra "Configured MAX bandwidth to be %08x Mb/sec\n", 41474b01e519SManish Chopra p_link->speed); 41484b01e519SManish Chopra 41494b01e519SManish Chopra return rc; 41504b01e519SManish Chopra } 41514b01e519SManish Chopra 41524b01e519SManish Chopra /* Main API to configure PF max bandwidth where bw range is [1 - 100] */ 41534b01e519SManish Chopra int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw) 41544b01e519SManish Chopra { 41554b01e519SManish Chopra int i, rc = -EINVAL; 41564b01e519SManish Chopra 41574b01e519SManish Chopra if (max_bw < 1 || max_bw > 100) { 41584b01e519SManish Chopra DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n"); 41594b01e519SManish Chopra return rc; 41604b01e519SManish Chopra } 41614b01e519SManish Chopra 41624b01e519SManish Chopra for_each_hwfn(cdev, i) { 41634b01e519SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 41644b01e519SManish Chopra struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 41654b01e519SManish Chopra struct qed_mcp_link_state *p_link; 41664b01e519SManish Chopra struct qed_ptt *p_ptt; 41674b01e519SManish Chopra 41684b01e519SManish Chopra p_link = &p_lead->mcp_info->link_output; 41694b01e519SManish Chopra 41704b01e519SManish Chopra p_ptt = qed_ptt_acquire(p_hwfn); 41714b01e519SManish Chopra if (!p_ptt) 41724b01e519SManish Chopra return -EBUSY; 41734b01e519SManish Chopra 41744b01e519SManish Chopra rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, 41754b01e519SManish Chopra p_link, max_bw); 41764b01e519SManish Chopra 41774b01e519SManish Chopra qed_ptt_release(p_hwfn, p_ptt); 41784b01e519SManish Chopra 41794b01e519SManish Chopra if (rc) 41804b01e519SManish Chopra break; 41814b01e519SManish Chopra } 41824b01e519SManish Chopra 41834b01e519SManish Chopra return rc; 41844b01e519SManish Chopra } 4185a64b02d5SManish Chopra 4186a64b02d5SManish Chopra int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn, 4187a64b02d5SManish Chopra struct qed_ptt *p_ptt, 4188a64b02d5SManish Chopra struct qed_mcp_link_state *p_link, 4189a64b02d5SManish Chopra u8 min_bw) 4190a64b02d5SManish Chopra { 4191a64b02d5SManish Chopra int rc = 0; 4192a64b02d5SManish Chopra 4193a64b02d5SManish Chopra p_hwfn->mcp_info->func_info.bandwidth_min = min_bw; 4194a64b02d5SManish Chopra p_hwfn->qm_info.pf_wfq = min_bw; 4195a64b02d5SManish Chopra 4196a64b02d5SManish Chopra if (!p_link->line_speed) 4197a64b02d5SManish Chopra return rc; 4198a64b02d5SManish Chopra 4199a64b02d5SManish Chopra p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100; 4200a64b02d5SManish Chopra 4201a64b02d5SManish Chopra rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw); 4202a64b02d5SManish Chopra 4203a64b02d5SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 4204a64b02d5SManish Chopra "Configured MIN bandwidth to be %d Mb/sec\n", 4205a64b02d5SManish Chopra p_link->min_pf_rate); 4206a64b02d5SManish Chopra 4207a64b02d5SManish Chopra return rc; 4208a64b02d5SManish Chopra } 4209a64b02d5SManish Chopra 4210a64b02d5SManish Chopra /* Main API to configure PF min bandwidth where bw range is [1-100] */ 4211a64b02d5SManish Chopra int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw) 4212a64b02d5SManish Chopra { 4213a64b02d5SManish Chopra int i, rc = -EINVAL; 4214a64b02d5SManish Chopra 4215a64b02d5SManish Chopra if (min_bw < 1 || min_bw > 100) { 4216a64b02d5SManish Chopra DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n"); 4217a64b02d5SManish Chopra return rc; 4218a64b02d5SManish Chopra } 4219a64b02d5SManish Chopra 4220a64b02d5SManish Chopra for_each_hwfn(cdev, i) { 4221a64b02d5SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 4222a64b02d5SManish Chopra struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 4223a64b02d5SManish Chopra struct qed_mcp_link_state *p_link; 4224a64b02d5SManish Chopra struct qed_ptt *p_ptt; 4225a64b02d5SManish Chopra 4226a64b02d5SManish Chopra p_link = &p_lead->mcp_info->link_output; 4227a64b02d5SManish Chopra 4228a64b02d5SManish Chopra p_ptt = qed_ptt_acquire(p_hwfn); 4229a64b02d5SManish Chopra if (!p_ptt) 4230a64b02d5SManish Chopra return -EBUSY; 4231a64b02d5SManish Chopra 4232a64b02d5SManish Chopra rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, 4233a64b02d5SManish Chopra p_link, min_bw); 4234a64b02d5SManish Chopra if (rc) { 4235a64b02d5SManish Chopra qed_ptt_release(p_hwfn, p_ptt); 4236a64b02d5SManish Chopra return rc; 4237a64b02d5SManish Chopra } 4238a64b02d5SManish Chopra 4239a64b02d5SManish Chopra if (p_link->min_pf_rate) { 4240a64b02d5SManish Chopra u32 min_rate = p_link->min_pf_rate; 4241a64b02d5SManish Chopra 4242a64b02d5SManish Chopra rc = __qed_configure_vp_wfq_on_link_change(p_hwfn, 4243a64b02d5SManish Chopra p_ptt, 4244a64b02d5SManish Chopra min_rate); 4245a64b02d5SManish Chopra } 4246a64b02d5SManish Chopra 4247a64b02d5SManish Chopra qed_ptt_release(p_hwfn, p_ptt); 4248a64b02d5SManish Chopra } 4249a64b02d5SManish Chopra 4250a64b02d5SManish Chopra return rc; 4251a64b02d5SManish Chopra } 4252733def6aSYuval Mintz 4253733def6aSYuval Mintz void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 4254733def6aSYuval Mintz { 4255733def6aSYuval Mintz struct qed_mcp_link_state *p_link; 4256733def6aSYuval Mintz 4257733def6aSYuval Mintz p_link = &p_hwfn->mcp_info->link_output; 4258733def6aSYuval Mintz 4259733def6aSYuval Mintz if (p_link->min_pf_rate) 4260733def6aSYuval Mintz qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, 4261733def6aSYuval Mintz p_link->min_pf_rate); 4262733def6aSYuval Mintz 4263733def6aSYuval Mintz memset(p_hwfn->qm_info.wfq_data, 0, 4264733def6aSYuval Mintz sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports); 4265733def6aSYuval Mintz } 42669c79ddaaSMintz, Yuval 42679c79ddaaSMintz, Yuval int qed_device_num_engines(struct qed_dev *cdev) 42689c79ddaaSMintz, Yuval { 42699c79ddaaSMintz, Yuval return QED_IS_BB(cdev) ? 2 : 1; 42709c79ddaaSMintz, Yuval } 4271db82f70eSsudarsana.kalluru@cavium.com 4272db82f70eSsudarsana.kalluru@cavium.com static int qed_device_num_ports(struct qed_dev *cdev) 4273db82f70eSsudarsana.kalluru@cavium.com { 4274db82f70eSsudarsana.kalluru@cavium.com /* in CMT always only one port */ 4275db82f70eSsudarsana.kalluru@cavium.com if (cdev->num_hwfns > 1) 4276db82f70eSsudarsana.kalluru@cavium.com return 1; 4277db82f70eSsudarsana.kalluru@cavium.com 427878cea9ffSTomer Tayar return cdev->num_ports_in_engine * qed_device_num_engines(cdev); 4279db82f70eSsudarsana.kalluru@cavium.com } 4280db82f70eSsudarsana.kalluru@cavium.com 4281db82f70eSsudarsana.kalluru@cavium.com int qed_device_get_port_id(struct qed_dev *cdev) 4282db82f70eSsudarsana.kalluru@cavium.com { 4283db82f70eSsudarsana.kalluru@cavium.com return (QED_LEADING_HWFN(cdev)->abs_pf_id) % qed_device_num_ports(cdev); 4284db82f70eSsudarsana.kalluru@cavium.com } 4285456a5849SKalderon, Michal 4286456a5849SKalderon, Michal void qed_set_fw_mac_addr(__le16 *fw_msb, 4287456a5849SKalderon, Michal __le16 *fw_mid, __le16 *fw_lsb, u8 *mac) 4288456a5849SKalderon, Michal { 4289456a5849SKalderon, Michal ((u8 *)fw_msb)[0] = mac[1]; 4290456a5849SKalderon, Michal ((u8 *)fw_msb)[1] = mac[0]; 4291456a5849SKalderon, Michal ((u8 *)fw_mid)[0] = mac[3]; 4292456a5849SKalderon, Michal ((u8 *)fw_mid)[1] = mac[2]; 4293456a5849SKalderon, Michal ((u8 *)fw_lsb)[0] = mac[5]; 4294456a5849SKalderon, Michal ((u8 *)fw_lsb)[1] = mac[4]; 4295456a5849SKalderon, Michal } 4296