1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #include <linux/types.h> 34fe56b9e6SYuval Mintz #include <asm/byteorder.h> 35fe56b9e6SYuval Mintz #include <linux/io.h> 36fe56b9e6SYuval Mintz #include <linux/delay.h> 37fe56b9e6SYuval Mintz #include <linux/dma-mapping.h> 38fe56b9e6SYuval Mintz #include <linux/errno.h> 39fe56b9e6SYuval Mintz #include <linux/kernel.h> 40fe56b9e6SYuval Mintz #include <linux/mutex.h> 41fe56b9e6SYuval Mintz #include <linux/pci.h> 42fe56b9e6SYuval Mintz #include <linux/slab.h> 43fe56b9e6SYuval Mintz #include <linux/string.h> 44a91eb52aSYuval Mintz #include <linux/vmalloc.h> 45fe56b9e6SYuval Mintz #include <linux/etherdevice.h> 46fe56b9e6SYuval Mintz #include <linux/qed/qed_chain.h> 47fe56b9e6SYuval Mintz #include <linux/qed/qed_if.h> 48fe56b9e6SYuval Mintz #include "qed.h" 49fe56b9e6SYuval Mintz #include "qed_cxt.h" 5039651abdSSudarsana Reddy Kalluru #include "qed_dcbx.h" 51fe56b9e6SYuval Mintz #include "qed_dev_api.h" 521e128c81SArun Easi #include "qed_fcoe.h" 53fe56b9e6SYuval Mintz #include "qed_hsi.h" 54fe56b9e6SYuval Mintz #include "qed_hw.h" 55fe56b9e6SYuval Mintz #include "qed_init_ops.h" 56fe56b9e6SYuval Mintz #include "qed_int.h" 57fc831825SYuval Mintz #include "qed_iscsi.h" 580a7fb11cSYuval Mintz #include "qed_ll2.h" 59fe56b9e6SYuval Mintz #include "qed_mcp.h" 601d6cff4fSYuval Mintz #include "qed_ooo.h" 61fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 62fe56b9e6SYuval Mintz #include "qed_sp.h" 6332a47e72SYuval Mintz #include "qed_sriov.h" 640b55e27dSYuval Mintz #include "qed_vf.h" 65b71b9afdSKalderon, Michal #include "qed_rdma.h" 66fe56b9e6SYuval Mintz 670caf5b26SWei Yongjun static DEFINE_SPINLOCK(qm_lock); 6839651abdSSudarsana Reddy Kalluru 6951ff1725SRam Amrani #define QED_MIN_DPIS (4) 7051ff1725SRam Amrani #define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS) 7151ff1725SRam Amrani 7215582962SRahul Verma static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, 7315582962SRahul Verma struct qed_ptt *p_ptt, enum BAR_ID bar_id) 74c2035eeaSRam Amrani { 75c2035eeaSRam Amrani u32 bar_reg = (bar_id == BAR_ID_0 ? 76c2035eeaSRam Amrani PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE); 771408cc1fSYuval Mintz u32 val; 78c2035eeaSRam Amrani 791408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 801a850bfcSMintz, Yuval return qed_vf_hw_bar_size(p_hwfn, bar_id); 811408cc1fSYuval Mintz 8215582962SRahul Verma val = qed_rd(p_hwfn, p_ptt, bar_reg); 83c2035eeaSRam Amrani if (val) 84c2035eeaSRam Amrani return 1 << (val + 15); 85c2035eeaSRam Amrani 86c2035eeaSRam Amrani /* Old MFW initialized above registered only conditionally */ 87c2035eeaSRam Amrani if (p_hwfn->cdev->num_hwfns > 1) { 88c2035eeaSRam Amrani DP_INFO(p_hwfn, 89c2035eeaSRam Amrani "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n"); 90c2035eeaSRam Amrani return BAR_ID_0 ? 256 * 1024 : 512 * 1024; 91c2035eeaSRam Amrani } else { 92c2035eeaSRam Amrani DP_INFO(p_hwfn, 93c2035eeaSRam Amrani "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n"); 94c2035eeaSRam Amrani return 512 * 1024; 95c2035eeaSRam Amrani } 96c2035eeaSRam Amrani } 97c2035eeaSRam Amrani 981a635e48SYuval Mintz void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level) 99fe56b9e6SYuval Mintz { 100fe56b9e6SYuval Mintz u32 i; 101fe56b9e6SYuval Mintz 102fe56b9e6SYuval Mintz cdev->dp_level = dp_level; 103fe56b9e6SYuval Mintz cdev->dp_module = dp_module; 104fe56b9e6SYuval Mintz for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 105fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 106fe56b9e6SYuval Mintz 107fe56b9e6SYuval Mintz p_hwfn->dp_level = dp_level; 108fe56b9e6SYuval Mintz p_hwfn->dp_module = dp_module; 109fe56b9e6SYuval Mintz } 110fe56b9e6SYuval Mintz } 111fe56b9e6SYuval Mintz 112fe56b9e6SYuval Mintz void qed_init_struct(struct qed_dev *cdev) 113fe56b9e6SYuval Mintz { 114fe56b9e6SYuval Mintz u8 i; 115fe56b9e6SYuval Mintz 116fe56b9e6SYuval Mintz for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 117fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 118fe56b9e6SYuval Mintz 119fe56b9e6SYuval Mintz p_hwfn->cdev = cdev; 120fe56b9e6SYuval Mintz p_hwfn->my_id = i; 121fe56b9e6SYuval Mintz p_hwfn->b_active = false; 122fe56b9e6SYuval Mintz 123fe56b9e6SYuval Mintz mutex_init(&p_hwfn->dmae_info.mutex); 124fe56b9e6SYuval Mintz } 125fe56b9e6SYuval Mintz 126fe56b9e6SYuval Mintz /* hwfn 0 is always active */ 127fe56b9e6SYuval Mintz cdev->hwfns[0].b_active = true; 128fe56b9e6SYuval Mintz 129fe56b9e6SYuval Mintz /* set the default cache alignment to 128 */ 130fe56b9e6SYuval Mintz cdev->cache_shift = 7; 131fe56b9e6SYuval Mintz } 132fe56b9e6SYuval Mintz 133fe56b9e6SYuval Mintz static void qed_qm_info_free(struct qed_hwfn *p_hwfn) 134fe56b9e6SYuval Mintz { 135fe56b9e6SYuval Mintz struct qed_qm_info *qm_info = &p_hwfn->qm_info; 136fe56b9e6SYuval Mintz 137fe56b9e6SYuval Mintz kfree(qm_info->qm_pq_params); 138fe56b9e6SYuval Mintz qm_info->qm_pq_params = NULL; 139fe56b9e6SYuval Mintz kfree(qm_info->qm_vport_params); 140fe56b9e6SYuval Mintz qm_info->qm_vport_params = NULL; 141fe56b9e6SYuval Mintz kfree(qm_info->qm_port_params); 142fe56b9e6SYuval Mintz qm_info->qm_port_params = NULL; 143bcd197c8SManish Chopra kfree(qm_info->wfq_data); 144bcd197c8SManish Chopra qm_info->wfq_data = NULL; 145fe56b9e6SYuval Mintz } 146fe56b9e6SYuval Mintz 147fe56b9e6SYuval Mintz void qed_resc_free(struct qed_dev *cdev) 148fe56b9e6SYuval Mintz { 149fe56b9e6SYuval Mintz int i; 150fe56b9e6SYuval Mintz 1510db711bbSMintz, Yuval if (IS_VF(cdev)) { 1520db711bbSMintz, Yuval for_each_hwfn(cdev, i) 1530db711bbSMintz, Yuval qed_l2_free(&cdev->hwfns[i]); 1541408cc1fSYuval Mintz return; 1550db711bbSMintz, Yuval } 1561408cc1fSYuval Mintz 157fe56b9e6SYuval Mintz kfree(cdev->fw_data); 158fe56b9e6SYuval Mintz cdev->fw_data = NULL; 159fe56b9e6SYuval Mintz 160fe56b9e6SYuval Mintz kfree(cdev->reset_stats); 1613587cb87STomer Tayar cdev->reset_stats = NULL; 162fe56b9e6SYuval Mintz 163fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 164fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 165fe56b9e6SYuval Mintz 166fe56b9e6SYuval Mintz qed_cxt_mngr_free(p_hwfn); 167fe56b9e6SYuval Mintz qed_qm_info_free(p_hwfn); 168fe56b9e6SYuval Mintz qed_spq_free(p_hwfn); 1693587cb87STomer Tayar qed_eq_free(p_hwfn); 1703587cb87STomer Tayar qed_consq_free(p_hwfn); 171fe56b9e6SYuval Mintz qed_int_free(p_hwfn); 1720a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 1733587cb87STomer Tayar qed_ll2_free(p_hwfn); 1740a7fb11cSYuval Mintz #endif 1751e128c81SArun Easi if (p_hwfn->hw_info.personality == QED_PCI_FCOE) 1763587cb87STomer Tayar qed_fcoe_free(p_hwfn); 1771e128c81SArun Easi 1781d6cff4fSYuval Mintz if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 1793587cb87STomer Tayar qed_iscsi_free(p_hwfn); 1803587cb87STomer Tayar qed_ooo_free(p_hwfn); 1811d6cff4fSYuval Mintz } 18232a47e72SYuval Mintz qed_iov_free(p_hwfn); 1830db711bbSMintz, Yuval qed_l2_free(p_hwfn); 184fe56b9e6SYuval Mintz qed_dmae_info_free(p_hwfn); 185270837b3Ssudarsana.kalluru@cavium.com qed_dcbx_info_free(p_hwfn); 186fe56b9e6SYuval Mintz } 187fe56b9e6SYuval Mintz } 188fe56b9e6SYuval Mintz 189b5a9ee7cSAriel Elior /******************** QM initialization *******************/ 190b5a9ee7cSAriel Elior #define ACTIVE_TCS_BMAP 0x9f 191b5a9ee7cSAriel Elior #define ACTIVE_TCS_BMAP_4PORT_K2 0xf 192b5a9ee7cSAriel Elior 193b5a9ee7cSAriel Elior /* determines the physical queue flags for a given PF. */ 194b5a9ee7cSAriel Elior static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn) 195fe56b9e6SYuval Mintz { 196b5a9ee7cSAriel Elior u32 flags; 197fe56b9e6SYuval Mintz 198b5a9ee7cSAriel Elior /* common flags */ 199b5a9ee7cSAriel Elior flags = PQ_FLAGS_LB; 200fe56b9e6SYuval Mintz 201b5a9ee7cSAriel Elior /* feature flags */ 202b5a9ee7cSAriel Elior if (IS_QED_SRIOV(p_hwfn->cdev)) 203b5a9ee7cSAriel Elior flags |= PQ_FLAGS_VFS; 204fe56b9e6SYuval Mintz 205b5a9ee7cSAriel Elior /* protocol flags */ 206b5a9ee7cSAriel Elior switch (p_hwfn->hw_info.personality) { 207b5a9ee7cSAriel Elior case QED_PCI_ETH: 208b5a9ee7cSAriel Elior flags |= PQ_FLAGS_MCOS; 209b5a9ee7cSAriel Elior break; 210b5a9ee7cSAriel Elior case QED_PCI_FCOE: 211b5a9ee7cSAriel Elior flags |= PQ_FLAGS_OFLD; 212b5a9ee7cSAriel Elior break; 213b5a9ee7cSAriel Elior case QED_PCI_ISCSI: 214b5a9ee7cSAriel Elior flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD; 215b5a9ee7cSAriel Elior break; 216b5a9ee7cSAriel Elior case QED_PCI_ETH_ROCE: 217b5a9ee7cSAriel Elior flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT; 218b5a9ee7cSAriel Elior break; 219b5a9ee7cSAriel Elior default: 220fe56b9e6SYuval Mintz DP_ERR(p_hwfn, 221b5a9ee7cSAriel Elior "unknown personality %d\n", p_hwfn->hw_info.personality); 222b5a9ee7cSAriel Elior return 0; 223fe56b9e6SYuval Mintz } 224fe56b9e6SYuval Mintz 225b5a9ee7cSAriel Elior return flags; 226b5a9ee7cSAriel Elior } 227b5a9ee7cSAriel Elior 228b5a9ee7cSAriel Elior /* Getters for resource amounts necessary for qm initialization */ 229b5a9ee7cSAriel Elior u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn) 230b5a9ee7cSAriel Elior { 231b5a9ee7cSAriel Elior return p_hwfn->hw_info.num_hw_tc; 232b5a9ee7cSAriel Elior } 233b5a9ee7cSAriel Elior 234b5a9ee7cSAriel Elior u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn) 235b5a9ee7cSAriel Elior { 236b5a9ee7cSAriel Elior return IS_QED_SRIOV(p_hwfn->cdev) ? 237b5a9ee7cSAriel Elior p_hwfn->cdev->p_iov_info->total_vfs : 0; 238b5a9ee7cSAriel Elior } 239b5a9ee7cSAriel Elior 240b5a9ee7cSAriel Elior #define NUM_DEFAULT_RLS 1 241b5a9ee7cSAriel Elior 242b5a9ee7cSAriel Elior u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn) 243b5a9ee7cSAriel Elior { 244b5a9ee7cSAriel Elior u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn); 245b5a9ee7cSAriel Elior 246b5a9ee7cSAriel Elior /* num RLs can't exceed resource amount of rls or vports */ 247b5a9ee7cSAriel Elior num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL), 248b5a9ee7cSAriel Elior RESC_NUM(p_hwfn, QED_VPORT)); 249b5a9ee7cSAriel Elior 250b5a9ee7cSAriel Elior /* Make sure after we reserve there's something left */ 251b5a9ee7cSAriel Elior if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) 252b5a9ee7cSAriel Elior return 0; 253b5a9ee7cSAriel Elior 254b5a9ee7cSAriel Elior /* subtract rls necessary for VFs and one default one for the PF */ 255b5a9ee7cSAriel Elior num_pf_rls -= num_vfs + NUM_DEFAULT_RLS; 256b5a9ee7cSAriel Elior 257b5a9ee7cSAriel Elior return num_pf_rls; 258b5a9ee7cSAriel Elior } 259b5a9ee7cSAriel Elior 260b5a9ee7cSAriel Elior u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn) 261b5a9ee7cSAriel Elior { 262b5a9ee7cSAriel Elior u32 pq_flags = qed_get_pq_flags(p_hwfn); 263b5a9ee7cSAriel Elior 264b5a9ee7cSAriel Elior /* all pqs share the same vport, except for vfs and pf_rl pqs */ 265b5a9ee7cSAriel Elior return (!!(PQ_FLAGS_RLS & pq_flags)) * 266b5a9ee7cSAriel Elior qed_init_qm_get_num_pf_rls(p_hwfn) + 267b5a9ee7cSAriel Elior (!!(PQ_FLAGS_VFS & pq_flags)) * 268b5a9ee7cSAriel Elior qed_init_qm_get_num_vfs(p_hwfn) + 1; 269b5a9ee7cSAriel Elior } 270b5a9ee7cSAriel Elior 271b5a9ee7cSAriel Elior /* calc amount of PQs according to the requested flags */ 272b5a9ee7cSAriel Elior u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn) 273b5a9ee7cSAriel Elior { 274b5a9ee7cSAriel Elior u32 pq_flags = qed_get_pq_flags(p_hwfn); 275b5a9ee7cSAriel Elior 276b5a9ee7cSAriel Elior return (!!(PQ_FLAGS_RLS & pq_flags)) * 277b5a9ee7cSAriel Elior qed_init_qm_get_num_pf_rls(p_hwfn) + 278b5a9ee7cSAriel Elior (!!(PQ_FLAGS_MCOS & pq_flags)) * 279b5a9ee7cSAriel Elior qed_init_qm_get_num_tcs(p_hwfn) + 280b5a9ee7cSAriel Elior (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) + 281b5a9ee7cSAriel Elior (!!(PQ_FLAGS_ACK & pq_flags)) + (!!(PQ_FLAGS_OFLD & pq_flags)) + 282b5a9ee7cSAriel Elior (!!(PQ_FLAGS_LLT & pq_flags)) + 283b5a9ee7cSAriel Elior (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn); 284b5a9ee7cSAriel Elior } 285b5a9ee7cSAriel Elior 286b5a9ee7cSAriel Elior /* initialize the top level QM params */ 287b5a9ee7cSAriel Elior static void qed_init_qm_params(struct qed_hwfn *p_hwfn) 288b5a9ee7cSAriel Elior { 289b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 290b5a9ee7cSAriel Elior bool four_port; 291b5a9ee7cSAriel Elior 292b5a9ee7cSAriel Elior /* pq and vport bases for this PF */ 293b5a9ee7cSAriel Elior qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ); 294b5a9ee7cSAriel Elior qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT); 295b5a9ee7cSAriel Elior 296b5a9ee7cSAriel Elior /* rate limiting and weighted fair queueing are always enabled */ 297b5a9ee7cSAriel Elior qm_info->vport_rl_en = 1; 298b5a9ee7cSAriel Elior qm_info->vport_wfq_en = 1; 299b5a9ee7cSAriel Elior 300b5a9ee7cSAriel Elior /* TC config is different for AH 4 port */ 30178cea9ffSTomer Tayar four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2; 302b5a9ee7cSAriel Elior 303b5a9ee7cSAriel Elior /* in AH 4 port we have fewer TCs per port */ 304b5a9ee7cSAriel Elior qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 : 305b5a9ee7cSAriel Elior NUM_OF_PHYS_TCS; 306b5a9ee7cSAriel Elior 307b5a9ee7cSAriel Elior /* unless MFW indicated otherwise, ooo_tc == 3 for 308b5a9ee7cSAriel Elior * AH 4-port and 4 otherwise. 309fe56b9e6SYuval Mintz */ 310b5a9ee7cSAriel Elior if (!qm_info->ooo_tc) 311b5a9ee7cSAriel Elior qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC : 312b5a9ee7cSAriel Elior DCBX_TCP_OOO_TC; 313dbb799c3SYuval Mintz } 314dbb799c3SYuval Mintz 315b5a9ee7cSAriel Elior /* initialize qm vport params */ 316b5a9ee7cSAriel Elior static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn) 317b5a9ee7cSAriel Elior { 318b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 319b5a9ee7cSAriel Elior u8 i; 320fe56b9e6SYuval Mintz 321b5a9ee7cSAriel Elior /* all vports participate in weighted fair queueing */ 322b5a9ee7cSAriel Elior for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++) 323b5a9ee7cSAriel Elior qm_info->qm_vport_params[i].vport_wfq = 1; 324fe56b9e6SYuval Mintz } 325fe56b9e6SYuval Mintz 326b5a9ee7cSAriel Elior /* initialize qm port params */ 327b5a9ee7cSAriel Elior static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn) 328b5a9ee7cSAriel Elior { 329fe56b9e6SYuval Mintz /* Initialize qm port parameters */ 33078cea9ffSTomer Tayar u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine; 331b5a9ee7cSAriel Elior 332b5a9ee7cSAriel Elior /* indicate how ooo and high pri traffic is dealt with */ 333b5a9ee7cSAriel Elior active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ? 334b5a9ee7cSAriel Elior ACTIVE_TCS_BMAP_4PORT_K2 : 335b5a9ee7cSAriel Elior ACTIVE_TCS_BMAP; 336b5a9ee7cSAriel Elior 337fe56b9e6SYuval Mintz for (i = 0; i < num_ports; i++) { 338b5a9ee7cSAriel Elior struct init_qm_port_params *p_qm_port = 339b5a9ee7cSAriel Elior &p_hwfn->qm_info.qm_port_params[i]; 340b5a9ee7cSAriel Elior 341fe56b9e6SYuval Mintz p_qm_port->active = 1; 342b5a9ee7cSAriel Elior p_qm_port->active_phys_tcs = active_phys_tcs; 343fe56b9e6SYuval Mintz p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports; 344fe56b9e6SYuval Mintz p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports; 345fe56b9e6SYuval Mintz } 346b5a9ee7cSAriel Elior } 347fe56b9e6SYuval Mintz 348b5a9ee7cSAriel Elior /* Reset the params which must be reset for qm init. QM init may be called as 349b5a9ee7cSAriel Elior * a result of flows other than driver load (e.g. dcbx renegotiation). Other 350b5a9ee7cSAriel Elior * params may be affected by the init but would simply recalculate to the same 351b5a9ee7cSAriel Elior * values. The allocations made for QM init, ports, vports, pqs and vfqs are not 352b5a9ee7cSAriel Elior * affected as these amounts stay the same. 353b5a9ee7cSAriel Elior */ 354b5a9ee7cSAriel Elior static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn) 355b5a9ee7cSAriel Elior { 356b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 357fe56b9e6SYuval Mintz 358b5a9ee7cSAriel Elior qm_info->num_pqs = 0; 359b5a9ee7cSAriel Elior qm_info->num_vports = 0; 360b5a9ee7cSAriel Elior qm_info->num_pf_rls = 0; 361b5a9ee7cSAriel Elior qm_info->num_vf_pqs = 0; 362b5a9ee7cSAriel Elior qm_info->first_vf_pq = 0; 363b5a9ee7cSAriel Elior qm_info->first_mcos_pq = 0; 364b5a9ee7cSAriel Elior qm_info->first_rl_pq = 0; 365b5a9ee7cSAriel Elior } 366fe56b9e6SYuval Mintz 367b5a9ee7cSAriel Elior static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn) 368b5a9ee7cSAriel Elior { 369b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 370b5a9ee7cSAriel Elior 371b5a9ee7cSAriel Elior qm_info->num_vports++; 372b5a9ee7cSAriel Elior 373b5a9ee7cSAriel Elior if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn)) 374b5a9ee7cSAriel Elior DP_ERR(p_hwfn, 375b5a9ee7cSAriel Elior "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n", 376b5a9ee7cSAriel Elior qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn)); 377b5a9ee7cSAriel Elior } 378b5a9ee7cSAriel Elior 379b5a9ee7cSAriel Elior /* initialize a single pq and manage qm_info resources accounting. 380b5a9ee7cSAriel Elior * The pq_init_flags param determines whether the PQ is rate limited 381b5a9ee7cSAriel Elior * (for VF or PF) and whether a new vport is allocated to the pq or not 382b5a9ee7cSAriel Elior * (i.e. vport will be shared). 383b5a9ee7cSAriel Elior */ 384b5a9ee7cSAriel Elior 385b5a9ee7cSAriel Elior /* flags for pq init */ 386b5a9ee7cSAriel Elior #define PQ_INIT_SHARE_VPORT (1 << 0) 387b5a9ee7cSAriel Elior #define PQ_INIT_PF_RL (1 << 1) 388b5a9ee7cSAriel Elior #define PQ_INIT_VF_RL (1 << 2) 389b5a9ee7cSAriel Elior 390b5a9ee7cSAriel Elior /* defines for pq init */ 391b5a9ee7cSAriel Elior #define PQ_INIT_DEFAULT_WRR_GROUP 1 392b5a9ee7cSAriel Elior #define PQ_INIT_DEFAULT_TC 0 393b5a9ee7cSAriel Elior #define PQ_INIT_OFLD_TC (p_hwfn->hw_info.offload_tc) 394b5a9ee7cSAriel Elior 395b5a9ee7cSAriel Elior static void qed_init_qm_pq(struct qed_hwfn *p_hwfn, 396b5a9ee7cSAriel Elior struct qed_qm_info *qm_info, 397b5a9ee7cSAriel Elior u8 tc, u32 pq_init_flags) 398b5a9ee7cSAriel Elior { 399b5a9ee7cSAriel Elior u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn); 400b5a9ee7cSAriel Elior 401b5a9ee7cSAriel Elior if (pq_idx > max_pq) 402b5a9ee7cSAriel Elior DP_ERR(p_hwfn, 403b5a9ee7cSAriel Elior "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq); 404b5a9ee7cSAriel Elior 405b5a9ee7cSAriel Elior /* init pq params */ 406b5a9ee7cSAriel Elior qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport + 407b5a9ee7cSAriel Elior qm_info->num_vports; 408b5a9ee7cSAriel Elior qm_info->qm_pq_params[pq_idx].tc_id = tc; 409b5a9ee7cSAriel Elior qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP; 410b5a9ee7cSAriel Elior qm_info->qm_pq_params[pq_idx].rl_valid = 411b5a9ee7cSAriel Elior (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL); 412b5a9ee7cSAriel Elior 413b5a9ee7cSAriel Elior /* qm params accounting */ 414b5a9ee7cSAriel Elior qm_info->num_pqs++; 415b5a9ee7cSAriel Elior if (!(pq_init_flags & PQ_INIT_SHARE_VPORT)) 416b5a9ee7cSAriel Elior qm_info->num_vports++; 417b5a9ee7cSAriel Elior 418b5a9ee7cSAriel Elior if (pq_init_flags & PQ_INIT_PF_RL) 419b5a9ee7cSAriel Elior qm_info->num_pf_rls++; 420b5a9ee7cSAriel Elior 421b5a9ee7cSAriel Elior if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn)) 422b5a9ee7cSAriel Elior DP_ERR(p_hwfn, 423b5a9ee7cSAriel Elior "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n", 424b5a9ee7cSAriel Elior qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn)); 425b5a9ee7cSAriel Elior 426b5a9ee7cSAriel Elior if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn)) 427b5a9ee7cSAriel Elior DP_ERR(p_hwfn, 428b5a9ee7cSAriel Elior "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n", 429b5a9ee7cSAriel Elior qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn)); 430b5a9ee7cSAriel Elior } 431b5a9ee7cSAriel Elior 432b5a9ee7cSAriel Elior /* get pq index according to PQ_FLAGS */ 433b5a9ee7cSAriel Elior static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn, 434b5a9ee7cSAriel Elior u32 pq_flags) 435b5a9ee7cSAriel Elior { 436b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 437b5a9ee7cSAriel Elior 438b5a9ee7cSAriel Elior /* Can't have multiple flags set here */ 439b5a9ee7cSAriel Elior if (bitmap_weight((unsigned long *)&pq_flags, sizeof(pq_flags)) > 1) 440b5a9ee7cSAriel Elior goto err; 441b5a9ee7cSAriel Elior 442b5a9ee7cSAriel Elior switch (pq_flags) { 443b5a9ee7cSAriel Elior case PQ_FLAGS_RLS: 444b5a9ee7cSAriel Elior return &qm_info->first_rl_pq; 445b5a9ee7cSAriel Elior case PQ_FLAGS_MCOS: 446b5a9ee7cSAriel Elior return &qm_info->first_mcos_pq; 447b5a9ee7cSAriel Elior case PQ_FLAGS_LB: 448b5a9ee7cSAriel Elior return &qm_info->pure_lb_pq; 449b5a9ee7cSAriel Elior case PQ_FLAGS_OOO: 450b5a9ee7cSAriel Elior return &qm_info->ooo_pq; 451b5a9ee7cSAriel Elior case PQ_FLAGS_ACK: 452b5a9ee7cSAriel Elior return &qm_info->pure_ack_pq; 453b5a9ee7cSAriel Elior case PQ_FLAGS_OFLD: 454b5a9ee7cSAriel Elior return &qm_info->offload_pq; 455b5a9ee7cSAriel Elior case PQ_FLAGS_LLT: 456b5a9ee7cSAriel Elior return &qm_info->low_latency_pq; 457b5a9ee7cSAriel Elior case PQ_FLAGS_VFS: 458b5a9ee7cSAriel Elior return &qm_info->first_vf_pq; 459b5a9ee7cSAriel Elior default: 460b5a9ee7cSAriel Elior goto err; 461b5a9ee7cSAriel Elior } 462b5a9ee7cSAriel Elior 463b5a9ee7cSAriel Elior err: 464b5a9ee7cSAriel Elior DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags); 465b5a9ee7cSAriel Elior return NULL; 466b5a9ee7cSAriel Elior } 467b5a9ee7cSAriel Elior 468b5a9ee7cSAriel Elior /* save pq index in qm info */ 469b5a9ee7cSAriel Elior static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn, 470b5a9ee7cSAriel Elior u32 pq_flags, u16 pq_val) 471b5a9ee7cSAriel Elior { 472b5a9ee7cSAriel Elior u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags); 473b5a9ee7cSAriel Elior 474b5a9ee7cSAriel Elior *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val; 475b5a9ee7cSAriel Elior } 476b5a9ee7cSAriel Elior 477b5a9ee7cSAriel Elior /* get tx pq index, with the PQ TX base already set (ready for context init) */ 478b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags) 479b5a9ee7cSAriel Elior { 480b5a9ee7cSAriel Elior u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags); 481b5a9ee7cSAriel Elior 482b5a9ee7cSAriel Elior return *base_pq_idx + CM_TX_PQ_BASE; 483b5a9ee7cSAriel Elior } 484b5a9ee7cSAriel Elior 485b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc) 486b5a9ee7cSAriel Elior { 487b5a9ee7cSAriel Elior u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn); 488b5a9ee7cSAriel Elior 489b5a9ee7cSAriel Elior if (tc > max_tc) 490b5a9ee7cSAriel Elior DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc); 491b5a9ee7cSAriel Elior 492b5a9ee7cSAriel Elior return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc; 493b5a9ee7cSAriel Elior } 494b5a9ee7cSAriel Elior 495b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf) 496b5a9ee7cSAriel Elior { 497b5a9ee7cSAriel Elior u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn); 498b5a9ee7cSAriel Elior 499b5a9ee7cSAriel Elior if (vf > max_vf) 500b5a9ee7cSAriel Elior DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf); 501b5a9ee7cSAriel Elior 502b5a9ee7cSAriel Elior return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf; 503b5a9ee7cSAriel Elior } 504b5a9ee7cSAriel Elior 505b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx_rl(struct qed_hwfn *p_hwfn, u8 rl) 506b5a9ee7cSAriel Elior { 507b5a9ee7cSAriel Elior u16 max_rl = qed_init_qm_get_num_pf_rls(p_hwfn); 508b5a9ee7cSAriel Elior 509b5a9ee7cSAriel Elior if (rl > max_rl) 510b5a9ee7cSAriel Elior DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl); 511b5a9ee7cSAriel Elior 512b5a9ee7cSAriel Elior return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl; 513b5a9ee7cSAriel Elior } 514b5a9ee7cSAriel Elior 515b5a9ee7cSAriel Elior /* Functions for creating specific types of pqs */ 516b5a9ee7cSAriel Elior static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn) 517b5a9ee7cSAriel Elior { 518b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 519b5a9ee7cSAriel Elior 520b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB)) 521b5a9ee7cSAriel Elior return; 522b5a9ee7cSAriel Elior 523b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs); 524b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT); 525b5a9ee7cSAriel Elior } 526b5a9ee7cSAriel Elior 527b5a9ee7cSAriel Elior static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn) 528b5a9ee7cSAriel Elior { 529b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 530b5a9ee7cSAriel Elior 531b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO)) 532b5a9ee7cSAriel Elior return; 533b5a9ee7cSAriel Elior 534b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs); 535b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT); 536b5a9ee7cSAriel Elior } 537b5a9ee7cSAriel Elior 538b5a9ee7cSAriel Elior static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn) 539b5a9ee7cSAriel Elior { 540b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 541b5a9ee7cSAriel Elior 542b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK)) 543b5a9ee7cSAriel Elior return; 544b5a9ee7cSAriel Elior 545b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs); 546b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT); 547b5a9ee7cSAriel Elior } 548b5a9ee7cSAriel Elior 549b5a9ee7cSAriel Elior static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn) 550b5a9ee7cSAriel Elior { 551b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 552b5a9ee7cSAriel Elior 553b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD)) 554b5a9ee7cSAriel Elior return; 555b5a9ee7cSAriel Elior 556b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs); 557b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT); 558b5a9ee7cSAriel Elior } 559b5a9ee7cSAriel Elior 560b5a9ee7cSAriel Elior static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn) 561b5a9ee7cSAriel Elior { 562b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 563b5a9ee7cSAriel Elior 564b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT)) 565b5a9ee7cSAriel Elior return; 566b5a9ee7cSAriel Elior 567b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs); 568b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT); 569b5a9ee7cSAriel Elior } 570b5a9ee7cSAriel Elior 571b5a9ee7cSAriel Elior static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn) 572b5a9ee7cSAriel Elior { 573b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 574b5a9ee7cSAriel Elior u8 tc_idx; 575b5a9ee7cSAriel Elior 576b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS)) 577b5a9ee7cSAriel Elior return; 578b5a9ee7cSAriel Elior 579b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs); 580b5a9ee7cSAriel Elior for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++) 581b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT); 582b5a9ee7cSAriel Elior } 583b5a9ee7cSAriel Elior 584b5a9ee7cSAriel Elior static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn) 585b5a9ee7cSAriel Elior { 586b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 587b5a9ee7cSAriel Elior u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn); 588b5a9ee7cSAriel Elior 589b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS)) 590b5a9ee7cSAriel Elior return; 591b5a9ee7cSAriel Elior 592b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs); 5931408cc1fSYuval Mintz qm_info->num_vf_pqs = num_vfs; 594b5a9ee7cSAriel Elior for (vf_idx = 0; vf_idx < num_vfs; vf_idx++) 595b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, 596b5a9ee7cSAriel Elior qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL); 597b5a9ee7cSAriel Elior } 598fe56b9e6SYuval Mintz 599b5a9ee7cSAriel Elior static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn) 600b5a9ee7cSAriel Elior { 601b5a9ee7cSAriel Elior u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn); 602b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 603a64b02d5SManish Chopra 604b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS)) 605b5a9ee7cSAriel Elior return; 606b5a9ee7cSAriel Elior 607b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs); 608b5a9ee7cSAriel Elior for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++) 609b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_PF_RL); 610b5a9ee7cSAriel Elior } 611b5a9ee7cSAriel Elior 612b5a9ee7cSAriel Elior static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn) 613b5a9ee7cSAriel Elior { 614b5a9ee7cSAriel Elior /* rate limited pqs, must come first (FW assumption) */ 615b5a9ee7cSAriel Elior qed_init_qm_rl_pqs(p_hwfn); 616b5a9ee7cSAriel Elior 617b5a9ee7cSAriel Elior /* pqs for multi cos */ 618b5a9ee7cSAriel Elior qed_init_qm_mcos_pqs(p_hwfn); 619b5a9ee7cSAriel Elior 620b5a9ee7cSAriel Elior /* pure loopback pq */ 621b5a9ee7cSAriel Elior qed_init_qm_lb_pq(p_hwfn); 622b5a9ee7cSAriel Elior 623b5a9ee7cSAriel Elior /* out of order pq */ 624b5a9ee7cSAriel Elior qed_init_qm_ooo_pq(p_hwfn); 625b5a9ee7cSAriel Elior 626b5a9ee7cSAriel Elior /* pure ack pq */ 627b5a9ee7cSAriel Elior qed_init_qm_pure_ack_pq(p_hwfn); 628b5a9ee7cSAriel Elior 629b5a9ee7cSAriel Elior /* pq for offloaded protocol */ 630b5a9ee7cSAriel Elior qed_init_qm_offload_pq(p_hwfn); 631b5a9ee7cSAriel Elior 632b5a9ee7cSAriel Elior /* low latency pq */ 633b5a9ee7cSAriel Elior qed_init_qm_low_latency_pq(p_hwfn); 634b5a9ee7cSAriel Elior 635b5a9ee7cSAriel Elior /* done sharing vports */ 636b5a9ee7cSAriel Elior qed_init_qm_advance_vport(p_hwfn); 637b5a9ee7cSAriel Elior 638b5a9ee7cSAriel Elior /* pqs for vfs */ 639b5a9ee7cSAriel Elior qed_init_qm_vf_pqs(p_hwfn); 640b5a9ee7cSAriel Elior } 641b5a9ee7cSAriel Elior 642b5a9ee7cSAriel Elior /* compare values of getters against resources amounts */ 643b5a9ee7cSAriel Elior static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn) 644b5a9ee7cSAriel Elior { 645b5a9ee7cSAriel Elior if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) { 646b5a9ee7cSAriel Elior DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n"); 647b5a9ee7cSAriel Elior return -EINVAL; 648b5a9ee7cSAriel Elior } 649b5a9ee7cSAriel Elior 650b5a9ee7cSAriel Elior if (qed_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, QED_PQ)) { 651b5a9ee7cSAriel Elior DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n"); 652b5a9ee7cSAriel Elior return -EINVAL; 653b5a9ee7cSAriel Elior } 654fe56b9e6SYuval Mintz 655fe56b9e6SYuval Mintz return 0; 656b5a9ee7cSAriel Elior } 657fe56b9e6SYuval Mintz 658b5a9ee7cSAriel Elior static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn) 659b5a9ee7cSAriel Elior { 660b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 661b5a9ee7cSAriel Elior struct init_qm_vport_params *vport; 662b5a9ee7cSAriel Elior struct init_qm_port_params *port; 663b5a9ee7cSAriel Elior struct init_qm_pq_params *pq; 664b5a9ee7cSAriel Elior int i, tc; 665b5a9ee7cSAriel Elior 666b5a9ee7cSAriel Elior /* top level params */ 667b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 668b5a9ee7cSAriel Elior NETIF_MSG_HW, 669b5a9ee7cSAriel Elior "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n", 670b5a9ee7cSAriel Elior qm_info->start_pq, 671b5a9ee7cSAriel Elior qm_info->start_vport, 672b5a9ee7cSAriel Elior qm_info->pure_lb_pq, 673b5a9ee7cSAriel Elior qm_info->offload_pq, qm_info->pure_ack_pq); 674b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 675b5a9ee7cSAriel Elior NETIF_MSG_HW, 676b5a9ee7cSAriel Elior "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n", 677b5a9ee7cSAriel Elior qm_info->ooo_pq, 678b5a9ee7cSAriel Elior qm_info->first_vf_pq, 679b5a9ee7cSAriel Elior qm_info->num_pqs, 680b5a9ee7cSAriel Elior qm_info->num_vf_pqs, 681b5a9ee7cSAriel Elior qm_info->num_vports, qm_info->max_phys_tcs_per_port); 682b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 683b5a9ee7cSAriel Elior NETIF_MSG_HW, 684b5a9ee7cSAriel Elior "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n", 685b5a9ee7cSAriel Elior qm_info->pf_rl_en, 686b5a9ee7cSAriel Elior qm_info->pf_wfq_en, 687b5a9ee7cSAriel Elior qm_info->vport_rl_en, 688b5a9ee7cSAriel Elior qm_info->vport_wfq_en, 689b5a9ee7cSAriel Elior qm_info->pf_wfq, 690b5a9ee7cSAriel Elior qm_info->pf_rl, 691b5a9ee7cSAriel Elior qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn)); 692b5a9ee7cSAriel Elior 693b5a9ee7cSAriel Elior /* port table */ 69478cea9ffSTomer Tayar for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) { 695b5a9ee7cSAriel Elior port = &(qm_info->qm_port_params[i]); 696b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 697b5a9ee7cSAriel Elior NETIF_MSG_HW, 698b5a9ee7cSAriel Elior "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n", 699b5a9ee7cSAriel Elior i, 700b5a9ee7cSAriel Elior port->active, 701b5a9ee7cSAriel Elior port->active_phys_tcs, 702b5a9ee7cSAriel Elior port->num_pbf_cmd_lines, 703b5a9ee7cSAriel Elior port->num_btb_blocks, port->reserved); 704b5a9ee7cSAriel Elior } 705b5a9ee7cSAriel Elior 706b5a9ee7cSAriel Elior /* vport table */ 707b5a9ee7cSAriel Elior for (i = 0; i < qm_info->num_vports; i++) { 708b5a9ee7cSAriel Elior vport = &(qm_info->qm_vport_params[i]); 709b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 710b5a9ee7cSAriel Elior NETIF_MSG_HW, 711b5a9ee7cSAriel Elior "vport idx %d, vport_rl %d, wfq %d, first_tx_pq_id [ ", 712b5a9ee7cSAriel Elior qm_info->start_vport + i, 713b5a9ee7cSAriel Elior vport->vport_rl, vport->vport_wfq); 714b5a9ee7cSAriel Elior for (tc = 0; tc < NUM_OF_TCS; tc++) 715b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 716b5a9ee7cSAriel Elior NETIF_MSG_HW, 717b5a9ee7cSAriel Elior "%d ", vport->first_tx_pq_id[tc]); 718b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n"); 719b5a9ee7cSAriel Elior } 720b5a9ee7cSAriel Elior 721b5a9ee7cSAriel Elior /* pq table */ 722b5a9ee7cSAriel Elior for (i = 0; i < qm_info->num_pqs; i++) { 723b5a9ee7cSAriel Elior pq = &(qm_info->qm_pq_params[i]); 724b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 725b5a9ee7cSAriel Elior NETIF_MSG_HW, 726b5a9ee7cSAriel Elior "pq idx %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n", 727b5a9ee7cSAriel Elior qm_info->start_pq + i, 728b5a9ee7cSAriel Elior pq->vport_id, 729b5a9ee7cSAriel Elior pq->tc_id, pq->wrr_group, pq->rl_valid); 730b5a9ee7cSAriel Elior } 731b5a9ee7cSAriel Elior } 732b5a9ee7cSAriel Elior 733b5a9ee7cSAriel Elior static void qed_init_qm_info(struct qed_hwfn *p_hwfn) 734b5a9ee7cSAriel Elior { 735b5a9ee7cSAriel Elior /* reset params required for init run */ 736b5a9ee7cSAriel Elior qed_init_qm_reset_params(p_hwfn); 737b5a9ee7cSAriel Elior 738b5a9ee7cSAriel Elior /* init QM top level params */ 739b5a9ee7cSAriel Elior qed_init_qm_params(p_hwfn); 740b5a9ee7cSAriel Elior 741b5a9ee7cSAriel Elior /* init QM port params */ 742b5a9ee7cSAriel Elior qed_init_qm_port_params(p_hwfn); 743b5a9ee7cSAriel Elior 744b5a9ee7cSAriel Elior /* init QM vport params */ 745b5a9ee7cSAriel Elior qed_init_qm_vport_params(p_hwfn); 746b5a9ee7cSAriel Elior 747b5a9ee7cSAriel Elior /* init QM physical queue params */ 748b5a9ee7cSAriel Elior qed_init_qm_pq_params(p_hwfn); 749b5a9ee7cSAriel Elior 750b5a9ee7cSAriel Elior /* display all that init */ 751b5a9ee7cSAriel Elior qed_dp_init_qm_params(p_hwfn); 752fe56b9e6SYuval Mintz } 753fe56b9e6SYuval Mintz 75439651abdSSudarsana Reddy Kalluru /* This function reconfigures the QM pf on the fly. 75539651abdSSudarsana Reddy Kalluru * For this purpose we: 75639651abdSSudarsana Reddy Kalluru * 1. reconfigure the QM database 75739651abdSSudarsana Reddy Kalluru * 2. set new values to runtime arrat 75839651abdSSudarsana Reddy Kalluru * 3. send an sdm_qm_cmd through the rbc interface to stop the QM 75939651abdSSudarsana Reddy Kalluru * 4. activate init tool in QM_PF stage 76039651abdSSudarsana Reddy Kalluru * 5. send an sdm_qm_cmd through rbc interface to release the QM 76139651abdSSudarsana Reddy Kalluru */ 76239651abdSSudarsana Reddy Kalluru int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 76339651abdSSudarsana Reddy Kalluru { 76439651abdSSudarsana Reddy Kalluru struct qed_qm_info *qm_info = &p_hwfn->qm_info; 76539651abdSSudarsana Reddy Kalluru bool b_rc; 76639651abdSSudarsana Reddy Kalluru int rc; 76739651abdSSudarsana Reddy Kalluru 76839651abdSSudarsana Reddy Kalluru /* initialize qed's qm data structure */ 769b5a9ee7cSAriel Elior qed_init_qm_info(p_hwfn); 77039651abdSSudarsana Reddy Kalluru 77139651abdSSudarsana Reddy Kalluru /* stop PF's qm queues */ 77239651abdSSudarsana Reddy Kalluru spin_lock_bh(&qm_lock); 77339651abdSSudarsana Reddy Kalluru b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true, 77439651abdSSudarsana Reddy Kalluru qm_info->start_pq, qm_info->num_pqs); 77539651abdSSudarsana Reddy Kalluru spin_unlock_bh(&qm_lock); 77639651abdSSudarsana Reddy Kalluru if (!b_rc) 77739651abdSSudarsana Reddy Kalluru return -EINVAL; 77839651abdSSudarsana Reddy Kalluru 77939651abdSSudarsana Reddy Kalluru /* clear the QM_PF runtime phase leftovers from previous init */ 78039651abdSSudarsana Reddy Kalluru qed_init_clear_rt_data(p_hwfn); 78139651abdSSudarsana Reddy Kalluru 78239651abdSSudarsana Reddy Kalluru /* prepare QM portion of runtime array */ 78315582962SRahul Verma qed_qm_init_pf(p_hwfn, p_ptt); 78439651abdSSudarsana Reddy Kalluru 78539651abdSSudarsana Reddy Kalluru /* activate init tool on runtime array */ 78639651abdSSudarsana Reddy Kalluru rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id, 78739651abdSSudarsana Reddy Kalluru p_hwfn->hw_info.hw_mode); 78839651abdSSudarsana Reddy Kalluru if (rc) 78939651abdSSudarsana Reddy Kalluru return rc; 79039651abdSSudarsana Reddy Kalluru 79139651abdSSudarsana Reddy Kalluru /* start PF's qm queues */ 79239651abdSSudarsana Reddy Kalluru spin_lock_bh(&qm_lock); 79339651abdSSudarsana Reddy Kalluru b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true, 79439651abdSSudarsana Reddy Kalluru qm_info->start_pq, qm_info->num_pqs); 79539651abdSSudarsana Reddy Kalluru spin_unlock_bh(&qm_lock); 79639651abdSSudarsana Reddy Kalluru if (!b_rc) 79739651abdSSudarsana Reddy Kalluru return -EINVAL; 79839651abdSSudarsana Reddy Kalluru 79939651abdSSudarsana Reddy Kalluru return 0; 80039651abdSSudarsana Reddy Kalluru } 80139651abdSSudarsana Reddy Kalluru 802b5a9ee7cSAriel Elior static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn) 803b5a9ee7cSAriel Elior { 804b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 805b5a9ee7cSAriel Elior int rc; 806b5a9ee7cSAriel Elior 807b5a9ee7cSAriel Elior rc = qed_init_qm_sanity(p_hwfn); 808b5a9ee7cSAriel Elior if (rc) 809b5a9ee7cSAriel Elior goto alloc_err; 810b5a9ee7cSAriel Elior 811b5a9ee7cSAriel Elior qm_info->qm_pq_params = kzalloc(sizeof(*qm_info->qm_pq_params) * 812b5a9ee7cSAriel Elior qed_init_qm_get_num_pqs(p_hwfn), 813b5a9ee7cSAriel Elior GFP_KERNEL); 814b5a9ee7cSAriel Elior if (!qm_info->qm_pq_params) 815b5a9ee7cSAriel Elior goto alloc_err; 816b5a9ee7cSAriel Elior 817b5a9ee7cSAriel Elior qm_info->qm_vport_params = kzalloc(sizeof(*qm_info->qm_vport_params) * 818b5a9ee7cSAriel Elior qed_init_qm_get_num_vports(p_hwfn), 819b5a9ee7cSAriel Elior GFP_KERNEL); 820b5a9ee7cSAriel Elior if (!qm_info->qm_vport_params) 821b5a9ee7cSAriel Elior goto alloc_err; 822b5a9ee7cSAriel Elior 8232f7878c0SWei Yongjun qm_info->qm_port_params = kzalloc(sizeof(*qm_info->qm_port_params) * 82478cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine, 825b5a9ee7cSAriel Elior GFP_KERNEL); 826b5a9ee7cSAriel Elior if (!qm_info->qm_port_params) 827b5a9ee7cSAriel Elior goto alloc_err; 828b5a9ee7cSAriel Elior 829b5a9ee7cSAriel Elior qm_info->wfq_data = kzalloc(sizeof(*qm_info->wfq_data) * 830b5a9ee7cSAriel Elior qed_init_qm_get_num_vports(p_hwfn), 831b5a9ee7cSAriel Elior GFP_KERNEL); 832b5a9ee7cSAriel Elior if (!qm_info->wfq_data) 833b5a9ee7cSAriel Elior goto alloc_err; 834b5a9ee7cSAriel Elior 835b5a9ee7cSAriel Elior return 0; 836b5a9ee7cSAriel Elior 837b5a9ee7cSAriel Elior alloc_err: 838b5a9ee7cSAriel Elior DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n"); 839b5a9ee7cSAriel Elior qed_qm_info_free(p_hwfn); 840b5a9ee7cSAriel Elior return -ENOMEM; 841b5a9ee7cSAriel Elior } 842b5a9ee7cSAriel Elior 843fe56b9e6SYuval Mintz int qed_resc_alloc(struct qed_dev *cdev) 844fe56b9e6SYuval Mintz { 845f9dc4d1fSRam Amrani u32 rdma_tasks, excess_tasks; 846f9dc4d1fSRam Amrani u32 line_count; 847fe56b9e6SYuval Mintz int i, rc = 0; 848fe56b9e6SYuval Mintz 8490db711bbSMintz, Yuval if (IS_VF(cdev)) { 8500db711bbSMintz, Yuval for_each_hwfn(cdev, i) { 8510db711bbSMintz, Yuval rc = qed_l2_alloc(&cdev->hwfns[i]); 8520db711bbSMintz, Yuval if (rc) 8531408cc1fSYuval Mintz return rc; 8540db711bbSMintz, Yuval } 8550db711bbSMintz, Yuval return rc; 8560db711bbSMintz, Yuval } 8571408cc1fSYuval Mintz 858fe56b9e6SYuval Mintz cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL); 859fe56b9e6SYuval Mintz if (!cdev->fw_data) 860fe56b9e6SYuval Mintz return -ENOMEM; 861fe56b9e6SYuval Mintz 862fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 863fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 864dbb799c3SYuval Mintz u32 n_eqes, num_cons; 865fe56b9e6SYuval Mintz 866fe56b9e6SYuval Mintz /* First allocate the context manager structure */ 867fe56b9e6SYuval Mintz rc = qed_cxt_mngr_alloc(p_hwfn); 868fe56b9e6SYuval Mintz if (rc) 869fe56b9e6SYuval Mintz goto alloc_err; 870fe56b9e6SYuval Mintz 871fe56b9e6SYuval Mintz /* Set the HW cid/tid numbers (in the contest manager) 872fe56b9e6SYuval Mintz * Must be done prior to any further computations. 873fe56b9e6SYuval Mintz */ 874f9dc4d1fSRam Amrani rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS); 875fe56b9e6SYuval Mintz if (rc) 876fe56b9e6SYuval Mintz goto alloc_err; 877fe56b9e6SYuval Mintz 878b5a9ee7cSAriel Elior rc = qed_alloc_qm_data(p_hwfn); 879fe56b9e6SYuval Mintz if (rc) 880fe56b9e6SYuval Mintz goto alloc_err; 881fe56b9e6SYuval Mintz 882b5a9ee7cSAriel Elior /* init qm info */ 883b5a9ee7cSAriel Elior qed_init_qm_info(p_hwfn); 884b5a9ee7cSAriel Elior 885fe56b9e6SYuval Mintz /* Compute the ILT client partition */ 886f9dc4d1fSRam Amrani rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count); 887f9dc4d1fSRam Amrani if (rc) { 888f9dc4d1fSRam Amrani DP_NOTICE(p_hwfn, 889f9dc4d1fSRam Amrani "too many ILT lines; re-computing with less lines\n"); 890f9dc4d1fSRam Amrani /* In case there are not enough ILT lines we reduce the 891f9dc4d1fSRam Amrani * number of RDMA tasks and re-compute. 892f9dc4d1fSRam Amrani */ 893f9dc4d1fSRam Amrani excess_tasks = 894f9dc4d1fSRam Amrani qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count); 895f9dc4d1fSRam Amrani if (!excess_tasks) 896f9dc4d1fSRam Amrani goto alloc_err; 897f9dc4d1fSRam Amrani 898f9dc4d1fSRam Amrani rdma_tasks = RDMA_MAX_TIDS - excess_tasks; 899f9dc4d1fSRam Amrani rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks); 900fe56b9e6SYuval Mintz if (rc) 901fe56b9e6SYuval Mintz goto alloc_err; 902fe56b9e6SYuval Mintz 903f9dc4d1fSRam Amrani rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count); 904f9dc4d1fSRam Amrani if (rc) { 905f9dc4d1fSRam Amrani DP_ERR(p_hwfn, 906f9dc4d1fSRam Amrani "failed ILT compute. Requested too many lines: %u\n", 907f9dc4d1fSRam Amrani line_count); 908f9dc4d1fSRam Amrani 909f9dc4d1fSRam Amrani goto alloc_err; 910f9dc4d1fSRam Amrani } 911f9dc4d1fSRam Amrani } 912f9dc4d1fSRam Amrani 913fe56b9e6SYuval Mintz /* CID map / ILT shadow table / T2 914fe56b9e6SYuval Mintz * The talbes sizes are determined by the computations above 915fe56b9e6SYuval Mintz */ 916fe56b9e6SYuval Mintz rc = qed_cxt_tables_alloc(p_hwfn); 917fe56b9e6SYuval Mintz if (rc) 918fe56b9e6SYuval Mintz goto alloc_err; 919fe56b9e6SYuval Mintz 920fe56b9e6SYuval Mintz /* SPQ, must follow ILT because initializes SPQ context */ 921fe56b9e6SYuval Mintz rc = qed_spq_alloc(p_hwfn); 922fe56b9e6SYuval Mintz if (rc) 923fe56b9e6SYuval Mintz goto alloc_err; 924fe56b9e6SYuval Mintz 925fe56b9e6SYuval Mintz /* SP status block allocation */ 926fe56b9e6SYuval Mintz p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn, 927fe56b9e6SYuval Mintz RESERVED_PTT_DPC); 928fe56b9e6SYuval Mintz 929fe56b9e6SYuval Mintz rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt); 930fe56b9e6SYuval Mintz if (rc) 931fe56b9e6SYuval Mintz goto alloc_err; 932fe56b9e6SYuval Mintz 93332a47e72SYuval Mintz rc = qed_iov_alloc(p_hwfn); 93432a47e72SYuval Mintz if (rc) 93532a47e72SYuval Mintz goto alloc_err; 93632a47e72SYuval Mintz 937fe56b9e6SYuval Mintz /* EQ */ 938dbb799c3SYuval Mintz n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain); 939dbb799c3SYuval Mintz if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) { 940dbb799c3SYuval Mintz num_cons = qed_cxt_get_proto_cid_count(p_hwfn, 941dbb799c3SYuval Mintz PROTOCOLID_ROCE, 9428c93beafSYuval Mintz NULL) * 2; 943dbb799c3SYuval Mintz n_eqes += num_cons + 2 * MAX_NUM_VFS_BB; 944dbb799c3SYuval Mintz } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 945dbb799c3SYuval Mintz num_cons = 946dbb799c3SYuval Mintz qed_cxt_get_proto_cid_count(p_hwfn, 9478c93beafSYuval Mintz PROTOCOLID_ISCSI, 9488c93beafSYuval Mintz NULL); 949dbb799c3SYuval Mintz n_eqes += 2 * num_cons; 950dbb799c3SYuval Mintz } 951dbb799c3SYuval Mintz 952dbb799c3SYuval Mintz if (n_eqes > 0xFFFF) { 953dbb799c3SYuval Mintz DP_ERR(p_hwfn, 954dbb799c3SYuval Mintz "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n", 955dbb799c3SYuval Mintz n_eqes, 0xFFFF); 9563587cb87STomer Tayar goto alloc_no_mem; 9579b15acbfSDan Carpenter } 958dbb799c3SYuval Mintz 9593587cb87STomer Tayar rc = qed_eq_alloc(p_hwfn, (u16) n_eqes); 9603587cb87STomer Tayar if (rc) 9613587cb87STomer Tayar goto alloc_err; 962fe56b9e6SYuval Mintz 9633587cb87STomer Tayar rc = qed_consq_alloc(p_hwfn); 9643587cb87STomer Tayar if (rc) 9653587cb87STomer Tayar goto alloc_err; 966fe56b9e6SYuval Mintz 9670db711bbSMintz, Yuval rc = qed_l2_alloc(p_hwfn); 9680db711bbSMintz, Yuval if (rc) 9690db711bbSMintz, Yuval goto alloc_err; 9700db711bbSMintz, Yuval 9710a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 9720a7fb11cSYuval Mintz if (p_hwfn->using_ll2) { 9733587cb87STomer Tayar rc = qed_ll2_alloc(p_hwfn); 9743587cb87STomer Tayar if (rc) 9753587cb87STomer Tayar goto alloc_err; 9760a7fb11cSYuval Mintz } 9770a7fb11cSYuval Mintz #endif 9781e128c81SArun Easi 9791e128c81SArun Easi if (p_hwfn->hw_info.personality == QED_PCI_FCOE) { 9803587cb87STomer Tayar rc = qed_fcoe_alloc(p_hwfn); 9813587cb87STomer Tayar if (rc) 9823587cb87STomer Tayar goto alloc_err; 9831e128c81SArun Easi } 9841e128c81SArun Easi 985fc831825SYuval Mintz if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 9863587cb87STomer Tayar rc = qed_iscsi_alloc(p_hwfn); 9873587cb87STomer Tayar if (rc) 9883587cb87STomer Tayar goto alloc_err; 9893587cb87STomer Tayar rc = qed_ooo_alloc(p_hwfn); 9903587cb87STomer Tayar if (rc) 9913587cb87STomer Tayar goto alloc_err; 992fc831825SYuval Mintz } 9930a7fb11cSYuval Mintz 994fe56b9e6SYuval Mintz /* DMA info initialization */ 995fe56b9e6SYuval Mintz rc = qed_dmae_info_alloc(p_hwfn); 9962591c280SJoe Perches if (rc) 997fe56b9e6SYuval Mintz goto alloc_err; 99839651abdSSudarsana Reddy Kalluru 99939651abdSSudarsana Reddy Kalluru /* DCBX initialization */ 100039651abdSSudarsana Reddy Kalluru rc = qed_dcbx_info_alloc(p_hwfn); 10012591c280SJoe Perches if (rc) 100239651abdSSudarsana Reddy Kalluru goto alloc_err; 100339651abdSSudarsana Reddy Kalluru } 1004fe56b9e6SYuval Mintz 1005fe56b9e6SYuval Mintz cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL); 10062591c280SJoe Perches if (!cdev->reset_stats) 100783aeb933SYuval Mintz goto alloc_no_mem; 1008fe56b9e6SYuval Mintz 1009fe56b9e6SYuval Mintz return 0; 1010fe56b9e6SYuval Mintz 1011dbb799c3SYuval Mintz alloc_no_mem: 1012dbb799c3SYuval Mintz rc = -ENOMEM; 1013fe56b9e6SYuval Mintz alloc_err: 1014fe56b9e6SYuval Mintz qed_resc_free(cdev); 1015fe56b9e6SYuval Mintz return rc; 1016fe56b9e6SYuval Mintz } 1017fe56b9e6SYuval Mintz 1018fe56b9e6SYuval Mintz void qed_resc_setup(struct qed_dev *cdev) 1019fe56b9e6SYuval Mintz { 1020fe56b9e6SYuval Mintz int i; 1021fe56b9e6SYuval Mintz 10220db711bbSMintz, Yuval if (IS_VF(cdev)) { 10230db711bbSMintz, Yuval for_each_hwfn(cdev, i) 10240db711bbSMintz, Yuval qed_l2_setup(&cdev->hwfns[i]); 10251408cc1fSYuval Mintz return; 10260db711bbSMintz, Yuval } 10271408cc1fSYuval Mintz 1028fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 1029fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1030fe56b9e6SYuval Mintz 1031fe56b9e6SYuval Mintz qed_cxt_mngr_setup(p_hwfn); 1032fe56b9e6SYuval Mintz qed_spq_setup(p_hwfn); 10333587cb87STomer Tayar qed_eq_setup(p_hwfn); 10343587cb87STomer Tayar qed_consq_setup(p_hwfn); 1035fe56b9e6SYuval Mintz 1036fe56b9e6SYuval Mintz /* Read shadow of current MFW mailbox */ 1037fe56b9e6SYuval Mintz qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt); 1038fe56b9e6SYuval Mintz memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 1039fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_cur, 1040fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_length); 1041fe56b9e6SYuval Mintz 1042fe56b9e6SYuval Mintz qed_int_setup(p_hwfn, p_hwfn->p_main_ptt); 104332a47e72SYuval Mintz 10440db711bbSMintz, Yuval qed_l2_setup(p_hwfn); 10451ee240e3SMintz, Yuval qed_iov_setup(p_hwfn); 10460a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 10470a7fb11cSYuval Mintz if (p_hwfn->using_ll2) 10483587cb87STomer Tayar qed_ll2_setup(p_hwfn); 10490a7fb11cSYuval Mintz #endif 10501e128c81SArun Easi if (p_hwfn->hw_info.personality == QED_PCI_FCOE) 10513587cb87STomer Tayar qed_fcoe_setup(p_hwfn); 10521e128c81SArun Easi 10531d6cff4fSYuval Mintz if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 10543587cb87STomer Tayar qed_iscsi_setup(p_hwfn); 10553587cb87STomer Tayar qed_ooo_setup(p_hwfn); 10561d6cff4fSYuval Mintz } 1057fe56b9e6SYuval Mintz } 1058fe56b9e6SYuval Mintz } 1059fe56b9e6SYuval Mintz 1060fe56b9e6SYuval Mintz #define FINAL_CLEANUP_POLL_CNT (100) 1061fe56b9e6SYuval Mintz #define FINAL_CLEANUP_POLL_TIME (10) 1062fe56b9e6SYuval Mintz int qed_final_cleanup(struct qed_hwfn *p_hwfn, 10630b55e27dSYuval Mintz struct qed_ptt *p_ptt, u16 id, bool is_vf) 1064fe56b9e6SYuval Mintz { 1065fe56b9e6SYuval Mintz u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT; 1066fe56b9e6SYuval Mintz int rc = -EBUSY; 1067fe56b9e6SYuval Mintz 1068fc48b7a6SYuval Mintz addr = GTT_BAR0_MAP_REG_USDM_RAM + 1069fc48b7a6SYuval Mintz USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id); 1070fe56b9e6SYuval Mintz 10710b55e27dSYuval Mintz if (is_vf) 10720b55e27dSYuval Mintz id += 0x10; 10730b55e27dSYuval Mintz 1074fc48b7a6SYuval Mintz command |= X_FINAL_CLEANUP_AGG_INT << 1075fc48b7a6SYuval Mintz SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT; 1076fc48b7a6SYuval Mintz command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT; 1077fc48b7a6SYuval Mintz command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT; 1078fc48b7a6SYuval Mintz command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT; 1079fe56b9e6SYuval Mintz 1080fe56b9e6SYuval Mintz /* Make sure notification is not set before initiating final cleanup */ 1081fe56b9e6SYuval Mintz if (REG_RD(p_hwfn, addr)) { 10821a635e48SYuval Mintz DP_NOTICE(p_hwfn, 1083fe56b9e6SYuval Mintz "Unexpected; Found final cleanup notification before initiating final cleanup\n"); 1084fe56b9e6SYuval Mintz REG_WR(p_hwfn, addr, 0); 1085fe56b9e6SYuval Mintz } 1086fe56b9e6SYuval Mintz 1087fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_IOV, 1088fe56b9e6SYuval Mintz "Sending final cleanup for PFVF[%d] [Command %08x\n]", 1089fe56b9e6SYuval Mintz id, command); 1090fe56b9e6SYuval Mintz 1091fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command); 1092fe56b9e6SYuval Mintz 1093fe56b9e6SYuval Mintz /* Poll until completion */ 1094fe56b9e6SYuval Mintz while (!REG_RD(p_hwfn, addr) && count--) 1095fe56b9e6SYuval Mintz msleep(FINAL_CLEANUP_POLL_TIME); 1096fe56b9e6SYuval Mintz 1097fe56b9e6SYuval Mintz if (REG_RD(p_hwfn, addr)) 1098fe56b9e6SYuval Mintz rc = 0; 1099fe56b9e6SYuval Mintz else 1100fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 1101fe56b9e6SYuval Mintz "Failed to receive FW final cleanup notification\n"); 1102fe56b9e6SYuval Mintz 1103fe56b9e6SYuval Mintz /* Cleanup afterwards */ 1104fe56b9e6SYuval Mintz REG_WR(p_hwfn, addr, 0); 1105fe56b9e6SYuval Mintz 1106fe56b9e6SYuval Mintz return rc; 1107fe56b9e6SYuval Mintz } 1108fe56b9e6SYuval Mintz 11099c79ddaaSMintz, Yuval static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn) 1110fe56b9e6SYuval Mintz { 1111fe56b9e6SYuval Mintz int hw_mode = 0; 1112fe56b9e6SYuval Mintz 11139c79ddaaSMintz, Yuval if (QED_IS_BB_B0(p_hwfn->cdev)) { 11149c79ddaaSMintz, Yuval hw_mode |= 1 << MODE_BB; 11159c79ddaaSMintz, Yuval } else if (QED_IS_AH(p_hwfn->cdev)) { 11169c79ddaaSMintz, Yuval hw_mode |= 1 << MODE_K2; 11179c79ddaaSMintz, Yuval } else { 11189c79ddaaSMintz, Yuval DP_NOTICE(p_hwfn, "Unknown chip type %#x\n", 11199c79ddaaSMintz, Yuval p_hwfn->cdev->type); 11209c79ddaaSMintz, Yuval return -EINVAL; 11219c79ddaaSMintz, Yuval } 1122fe56b9e6SYuval Mintz 112378cea9ffSTomer Tayar switch (p_hwfn->cdev->num_ports_in_engine) { 1124fe56b9e6SYuval Mintz case 1: 1125fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_PORTS_PER_ENG_1; 1126fe56b9e6SYuval Mintz break; 1127fe56b9e6SYuval Mintz case 2: 1128fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_PORTS_PER_ENG_2; 1129fe56b9e6SYuval Mintz break; 1130fe56b9e6SYuval Mintz case 4: 1131fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_PORTS_PER_ENG_4; 1132fe56b9e6SYuval Mintz break; 1133fe56b9e6SYuval Mintz default: 1134fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n", 113578cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine); 11369c79ddaaSMintz, Yuval return -EINVAL; 1137fe56b9e6SYuval Mintz } 1138fe56b9e6SYuval Mintz 1139fe56b9e6SYuval Mintz switch (p_hwfn->cdev->mf_mode) { 1140fc48b7a6SYuval Mintz case QED_MF_DEFAULT: 1141fc48b7a6SYuval Mintz case QED_MF_NPAR: 1142fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_MF_SI; 1143fe56b9e6SYuval Mintz break; 1144fc48b7a6SYuval Mintz case QED_MF_OVLAN: 1145fc48b7a6SYuval Mintz hw_mode |= 1 << MODE_MF_SD; 1146fc48b7a6SYuval Mintz break; 1147fe56b9e6SYuval Mintz default: 1148fc48b7a6SYuval Mintz DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n"); 1149fc48b7a6SYuval Mintz hw_mode |= 1 << MODE_MF_SI; 1150fe56b9e6SYuval Mintz } 1151fe56b9e6SYuval Mintz 1152fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_ASIC; 1153fe56b9e6SYuval Mintz 11541af9dcf7SYuval Mintz if (p_hwfn->cdev->num_hwfns > 1) 11551af9dcf7SYuval Mintz hw_mode |= 1 << MODE_100G; 11561af9dcf7SYuval Mintz 1157fe56b9e6SYuval Mintz p_hwfn->hw_info.hw_mode = hw_mode; 11581af9dcf7SYuval Mintz 11591af9dcf7SYuval Mintz DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP), 11601af9dcf7SYuval Mintz "Configuring function for hw_mode: 0x%08x\n", 11611af9dcf7SYuval Mintz p_hwfn->hw_info.hw_mode); 11629c79ddaaSMintz, Yuval 11639c79ddaaSMintz, Yuval return 0; 1164fe56b9e6SYuval Mintz } 1165fe56b9e6SYuval Mintz 1166fe56b9e6SYuval Mintz /* Init run time data for all PFs on an engine. */ 1167fe56b9e6SYuval Mintz static void qed_init_cau_rt_data(struct qed_dev *cdev) 1168fe56b9e6SYuval Mintz { 1169fe56b9e6SYuval Mintz u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET; 1170d031548eSMintz, Yuval int i, igu_sb_id; 1171fe56b9e6SYuval Mintz 1172fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 1173fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1174fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 1175fe56b9e6SYuval Mintz struct qed_igu_block *p_block; 1176fe56b9e6SYuval Mintz struct cau_sb_entry sb_entry; 1177fe56b9e6SYuval Mintz 1178fe56b9e6SYuval Mintz p_igu_info = p_hwfn->hw_info.p_igu_info; 1179fe56b9e6SYuval Mintz 1180d031548eSMintz, Yuval for (igu_sb_id = 0; 1181d031548eSMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) { 1182d031548eSMintz, Yuval p_block = &p_igu_info->entry[igu_sb_id]; 1183d031548eSMintz, Yuval 1184fe56b9e6SYuval Mintz if (!p_block->is_pf) 1185fe56b9e6SYuval Mintz continue; 1186fe56b9e6SYuval Mintz 1187fe56b9e6SYuval Mintz qed_init_cau_sb_entry(p_hwfn, &sb_entry, 11881a635e48SYuval Mintz p_block->function_id, 0, 0); 1189d031548eSMintz, Yuval STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2, 1190d031548eSMintz, Yuval sb_entry); 1191fe56b9e6SYuval Mintz } 1192fe56b9e6SYuval Mintz } 1193fe56b9e6SYuval Mintz } 1194fe56b9e6SYuval Mintz 119560afed72STomer Tayar static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn, 119660afed72STomer Tayar struct qed_ptt *p_ptt) 119760afed72STomer Tayar { 119860afed72STomer Tayar u32 val, wr_mbs, cache_line_size; 119960afed72STomer Tayar 120060afed72STomer Tayar val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0); 120160afed72STomer Tayar switch (val) { 120260afed72STomer Tayar case 0: 120360afed72STomer Tayar wr_mbs = 128; 120460afed72STomer Tayar break; 120560afed72STomer Tayar case 1: 120660afed72STomer Tayar wr_mbs = 256; 120760afed72STomer Tayar break; 120860afed72STomer Tayar case 2: 120960afed72STomer Tayar wr_mbs = 512; 121060afed72STomer Tayar break; 121160afed72STomer Tayar default: 121260afed72STomer Tayar DP_INFO(p_hwfn, 121360afed72STomer Tayar "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n", 121460afed72STomer Tayar val); 121560afed72STomer Tayar return; 121660afed72STomer Tayar } 121760afed72STomer Tayar 121860afed72STomer Tayar cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs); 121960afed72STomer Tayar switch (cache_line_size) { 122060afed72STomer Tayar case 32: 122160afed72STomer Tayar val = 0; 122260afed72STomer Tayar break; 122360afed72STomer Tayar case 64: 122460afed72STomer Tayar val = 1; 122560afed72STomer Tayar break; 122660afed72STomer Tayar case 128: 122760afed72STomer Tayar val = 2; 122860afed72STomer Tayar break; 122960afed72STomer Tayar case 256: 123060afed72STomer Tayar val = 3; 123160afed72STomer Tayar break; 123260afed72STomer Tayar default: 123360afed72STomer Tayar DP_INFO(p_hwfn, 123460afed72STomer Tayar "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n", 123560afed72STomer Tayar cache_line_size); 123660afed72STomer Tayar } 123760afed72STomer Tayar 123860afed72STomer Tayar if (L1_CACHE_BYTES > wr_mbs) 123960afed72STomer Tayar DP_INFO(p_hwfn, 124060afed72STomer Tayar "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n", 124160afed72STomer Tayar L1_CACHE_BYTES, wr_mbs); 124260afed72STomer Tayar 124360afed72STomer Tayar STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val); 1244fc6575bcSMintz, Yuval if (val > 0) { 1245fc6575bcSMintz, Yuval STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val); 1246fc6575bcSMintz, Yuval STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val); 1247fc6575bcSMintz, Yuval } 124860afed72STomer Tayar } 124960afed72STomer Tayar 1250fe56b9e6SYuval Mintz static int qed_hw_init_common(struct qed_hwfn *p_hwfn, 12511a635e48SYuval Mintz struct qed_ptt *p_ptt, int hw_mode) 1252fe56b9e6SYuval Mintz { 1253fe56b9e6SYuval Mintz struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1254fe56b9e6SYuval Mintz struct qed_qm_common_rt_init_params params; 1255fe56b9e6SYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 12569c79ddaaSMintz, Yuval u8 vf_id, max_num_vfs; 1257dbb799c3SYuval Mintz u16 num_pfs, pf_id; 12581408cc1fSYuval Mintz u32 concrete_fid; 1259fe56b9e6SYuval Mintz int rc = 0; 1260fe56b9e6SYuval Mintz 1261fe56b9e6SYuval Mintz qed_init_cau_rt_data(cdev); 1262fe56b9e6SYuval Mintz 1263fe56b9e6SYuval Mintz /* Program GTT windows */ 1264fe56b9e6SYuval Mintz qed_gtt_init(p_hwfn); 1265fe56b9e6SYuval Mintz 1266fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 1267fe56b9e6SYuval Mintz if (p_hwfn->mcp_info->func_info.bandwidth_max) 1268fe56b9e6SYuval Mintz qm_info->pf_rl_en = 1; 1269fe56b9e6SYuval Mintz if (p_hwfn->mcp_info->func_info.bandwidth_min) 1270fe56b9e6SYuval Mintz qm_info->pf_wfq_en = 1; 1271fe56b9e6SYuval Mintz } 1272fe56b9e6SYuval Mintz 1273fe56b9e6SYuval Mintz memset(¶ms, 0, sizeof(params)); 127478cea9ffSTomer Tayar params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine; 1275fe56b9e6SYuval Mintz params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port; 1276fe56b9e6SYuval Mintz params.pf_rl_en = qm_info->pf_rl_en; 1277fe56b9e6SYuval Mintz params.pf_wfq_en = qm_info->pf_wfq_en; 1278fe56b9e6SYuval Mintz params.vport_rl_en = qm_info->vport_rl_en; 1279fe56b9e6SYuval Mintz params.vport_wfq_en = qm_info->vport_wfq_en; 1280fe56b9e6SYuval Mintz params.port_params = qm_info->qm_port_params; 1281fe56b9e6SYuval Mintz 1282fe56b9e6SYuval Mintz qed_qm_common_rt_init(p_hwfn, ¶ms); 1283fe56b9e6SYuval Mintz 1284fe56b9e6SYuval Mintz qed_cxt_hw_init_common(p_hwfn); 1285fe56b9e6SYuval Mintz 128660afed72STomer Tayar qed_init_cache_line_size(p_hwfn, p_ptt); 128760afed72STomer Tayar 1288fe56b9e6SYuval Mintz rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode); 12891a635e48SYuval Mintz if (rc) 1290fe56b9e6SYuval Mintz return rc; 1291fe56b9e6SYuval Mintz 1292fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0); 1293fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1); 1294fe56b9e6SYuval Mintz 1295dbb799c3SYuval Mintz if (QED_IS_BB(p_hwfn->cdev)) { 1296dbb799c3SYuval Mintz num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev); 1297dbb799c3SYuval Mintz for (pf_id = 0; pf_id < num_pfs; pf_id++) { 1298dbb799c3SYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, pf_id); 1299dbb799c3SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1300dbb799c3SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1301dbb799c3SYuval Mintz } 1302dbb799c3SYuval Mintz /* pretend to original PF */ 1303dbb799c3SYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 1304dbb799c3SYuval Mintz } 1305fe56b9e6SYuval Mintz 13069c79ddaaSMintz, Yuval max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB; 13079c79ddaaSMintz, Yuval for (vf_id = 0; vf_id < max_num_vfs; vf_id++) { 13081408cc1fSYuval Mintz concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id); 13091408cc1fSYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid); 13101408cc1fSYuval Mintz qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1); 131105fafbfbSYuval Mintz qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0); 131205fafbfbSYuval Mintz qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1); 131305fafbfbSYuval Mintz qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0); 13141408cc1fSYuval Mintz } 13151408cc1fSYuval Mintz /* pretend to original PF */ 13161408cc1fSYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 13171408cc1fSYuval Mintz 1318fe56b9e6SYuval Mintz return rc; 1319fe56b9e6SYuval Mintz } 1320fe56b9e6SYuval Mintz 132151ff1725SRam Amrani static int 132251ff1725SRam Amrani qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn, 132351ff1725SRam Amrani struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus) 132451ff1725SRam Amrani { 1325107392b7SRam Amrani u32 dpi_bit_shift, dpi_count, dpi_page_size; 132651ff1725SRam Amrani u32 min_dpis; 1327107392b7SRam Amrani u32 n_wids; 132851ff1725SRam Amrani 132951ff1725SRam Amrani /* Calculate DPI size */ 1330107392b7SRam Amrani n_wids = max_t(u32, QED_MIN_WIDS, n_cpus); 1331107392b7SRam Amrani dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids); 1332107392b7SRam Amrani dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1); 133351ff1725SRam Amrani dpi_bit_shift = ilog2(dpi_page_size / 4096); 133451ff1725SRam Amrani dpi_count = pwm_region_size / dpi_page_size; 133551ff1725SRam Amrani 133651ff1725SRam Amrani min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis; 133751ff1725SRam Amrani min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis); 133851ff1725SRam Amrani 133951ff1725SRam Amrani p_hwfn->dpi_size = dpi_page_size; 134051ff1725SRam Amrani p_hwfn->dpi_count = dpi_count; 134151ff1725SRam Amrani 134251ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift); 134351ff1725SRam Amrani 134451ff1725SRam Amrani if (dpi_count < min_dpis) 134551ff1725SRam Amrani return -EINVAL; 134651ff1725SRam Amrani 134751ff1725SRam Amrani return 0; 134851ff1725SRam Amrani } 134951ff1725SRam Amrani 135051ff1725SRam Amrani enum QED_ROCE_EDPM_MODE { 135151ff1725SRam Amrani QED_ROCE_EDPM_MODE_ENABLE = 0, 135251ff1725SRam Amrani QED_ROCE_EDPM_MODE_FORCE_ON = 1, 135351ff1725SRam Amrani QED_ROCE_EDPM_MODE_DISABLE = 2, 135451ff1725SRam Amrani }; 135551ff1725SRam Amrani 135651ff1725SRam Amrani static int 135751ff1725SRam Amrani qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 135851ff1725SRam Amrani { 135951ff1725SRam Amrani u32 pwm_regsize, norm_regsize; 136051ff1725SRam Amrani u32 non_pwm_conn, min_addr_reg1; 136120b1bd96SRam Amrani u32 db_bar_size, n_cpus = 1; 136251ff1725SRam Amrani u32 roce_edpm_mode; 136351ff1725SRam Amrani u32 pf_dems_shift; 136451ff1725SRam Amrani int rc = 0; 136551ff1725SRam Amrani u8 cond; 136651ff1725SRam Amrani 136715582962SRahul Verma db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1); 136851ff1725SRam Amrani if (p_hwfn->cdev->num_hwfns > 1) 136951ff1725SRam Amrani db_bar_size /= 2; 137051ff1725SRam Amrani 137151ff1725SRam Amrani /* Calculate doorbell regions */ 137251ff1725SRam Amrani non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) + 137351ff1725SRam Amrani qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE, 137451ff1725SRam Amrani NULL) + 137551ff1725SRam Amrani qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, 137651ff1725SRam Amrani NULL); 1377a82dadbcSRam Amrani norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE); 137851ff1725SRam Amrani min_addr_reg1 = norm_regsize / 4096; 137951ff1725SRam Amrani pwm_regsize = db_bar_size - norm_regsize; 138051ff1725SRam Amrani 138151ff1725SRam Amrani /* Check that the normal and PWM sizes are valid */ 138251ff1725SRam Amrani if (db_bar_size < norm_regsize) { 138351ff1725SRam Amrani DP_ERR(p_hwfn->cdev, 138451ff1725SRam Amrani "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n", 138551ff1725SRam Amrani db_bar_size, norm_regsize); 138651ff1725SRam Amrani return -EINVAL; 138751ff1725SRam Amrani } 138851ff1725SRam Amrani 138951ff1725SRam Amrani if (pwm_regsize < QED_MIN_PWM_REGION) { 139051ff1725SRam Amrani DP_ERR(p_hwfn->cdev, 139151ff1725SRam Amrani "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n", 139251ff1725SRam Amrani pwm_regsize, 139351ff1725SRam Amrani QED_MIN_PWM_REGION, db_bar_size, norm_regsize); 139451ff1725SRam Amrani return -EINVAL; 139551ff1725SRam Amrani } 139651ff1725SRam Amrani 139751ff1725SRam Amrani /* Calculate number of DPIs */ 139851ff1725SRam Amrani roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode; 139951ff1725SRam Amrani if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) || 140051ff1725SRam Amrani ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) { 140151ff1725SRam Amrani /* Either EDPM is mandatory, or we are attempting to allocate a 140251ff1725SRam Amrani * WID per CPU. 140351ff1725SRam Amrani */ 1404c2dedf87SRam Amrani n_cpus = num_present_cpus(); 140551ff1725SRam Amrani rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 140651ff1725SRam Amrani } 140751ff1725SRam Amrani 140851ff1725SRam Amrani cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) || 140951ff1725SRam Amrani (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE); 141051ff1725SRam Amrani if (cond || p_hwfn->dcbx_no_edpm) { 141151ff1725SRam Amrani /* Either EDPM is disabled from user configuration, or it is 141251ff1725SRam Amrani * disabled via DCBx, or it is not mandatory and we failed to 141351ff1725SRam Amrani * allocated a WID per CPU. 141451ff1725SRam Amrani */ 141551ff1725SRam Amrani n_cpus = 1; 141651ff1725SRam Amrani rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 141751ff1725SRam Amrani 141851ff1725SRam Amrani if (cond) 141951ff1725SRam Amrani qed_rdma_dpm_bar(p_hwfn, p_ptt); 142051ff1725SRam Amrani } 142151ff1725SRam Amrani 142220b1bd96SRam Amrani p_hwfn->wid_count = (u16) n_cpus; 142320b1bd96SRam Amrani 142451ff1725SRam Amrani DP_INFO(p_hwfn, 142551ff1725SRam Amrani "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n", 142651ff1725SRam Amrani norm_regsize, 142751ff1725SRam Amrani pwm_regsize, 142851ff1725SRam Amrani p_hwfn->dpi_size, 142951ff1725SRam Amrani p_hwfn->dpi_count, 143051ff1725SRam Amrani ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ? 143151ff1725SRam Amrani "disabled" : "enabled"); 143251ff1725SRam Amrani 143351ff1725SRam Amrani if (rc) { 143451ff1725SRam Amrani DP_ERR(p_hwfn, 143551ff1725SRam Amrani "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n", 143651ff1725SRam Amrani p_hwfn->dpi_count, 143751ff1725SRam Amrani p_hwfn->pf_params.rdma_pf_params.min_dpis); 143851ff1725SRam Amrani return -EINVAL; 143951ff1725SRam Amrani } 144051ff1725SRam Amrani 144151ff1725SRam Amrani p_hwfn->dpi_start_offset = norm_regsize; 144251ff1725SRam Amrani 144351ff1725SRam Amrani /* DEMS size is configured log2 of DWORDs, hence the division by 4 */ 144451ff1725SRam Amrani pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4); 144551ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift); 144651ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1); 144751ff1725SRam Amrani 144851ff1725SRam Amrani return 0; 144951ff1725SRam Amrani } 145051ff1725SRam Amrani 1451fe56b9e6SYuval Mintz static int qed_hw_init_port(struct qed_hwfn *p_hwfn, 14521a635e48SYuval Mintz struct qed_ptt *p_ptt, int hw_mode) 1453fe56b9e6SYuval Mintz { 1454fc6575bcSMintz, Yuval int rc = 0; 1455fc6575bcSMintz, Yuval 1456fc6575bcSMintz, Yuval rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode); 1457fc6575bcSMintz, Yuval if (rc) 1458fc6575bcSMintz, Yuval return rc; 1459fc6575bcSMintz, Yuval 1460fc6575bcSMintz, Yuval qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0); 1461fc6575bcSMintz, Yuval 1462fc6575bcSMintz, Yuval return 0; 1463fe56b9e6SYuval Mintz } 1464fe56b9e6SYuval Mintz 1465fe56b9e6SYuval Mintz static int qed_hw_init_pf(struct qed_hwfn *p_hwfn, 1466fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 146719968430SChopra, Manish struct qed_tunnel_info *p_tunn, 1468fe56b9e6SYuval Mintz int hw_mode, 1469fe56b9e6SYuval Mintz bool b_hw_start, 1470fe56b9e6SYuval Mintz enum qed_int_mode int_mode, 1471fe56b9e6SYuval Mintz bool allow_npar_tx_switch) 1472fe56b9e6SYuval Mintz { 1473fe56b9e6SYuval Mintz u8 rel_pf_id = p_hwfn->rel_pf_id; 1474fe56b9e6SYuval Mintz int rc = 0; 1475fe56b9e6SYuval Mintz 1476fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 1477fe56b9e6SYuval Mintz struct qed_mcp_function_info *p_info; 1478fe56b9e6SYuval Mintz 1479fe56b9e6SYuval Mintz p_info = &p_hwfn->mcp_info->func_info; 1480fe56b9e6SYuval Mintz if (p_info->bandwidth_min) 1481fe56b9e6SYuval Mintz p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min; 1482fe56b9e6SYuval Mintz 1483fe56b9e6SYuval Mintz /* Update rate limit once we'll actually have a link */ 14844b01e519SManish Chopra p_hwfn->qm_info.pf_rl = 100000; 1485fe56b9e6SYuval Mintz } 1486fe56b9e6SYuval Mintz 148715582962SRahul Verma qed_cxt_hw_init_pf(p_hwfn, p_ptt); 1488fe56b9e6SYuval Mintz 1489fe56b9e6SYuval Mintz qed_int_igu_init_rt(p_hwfn); 1490fe56b9e6SYuval Mintz 1491fe56b9e6SYuval Mintz /* Set VLAN in NIG if needed */ 14921a635e48SYuval Mintz if (hw_mode & BIT(MODE_MF_SD)) { 1493fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n"); 1494fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1); 1495fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET, 1496fe56b9e6SYuval Mintz p_hwfn->hw_info.ovlan); 1497fe56b9e6SYuval Mintz } 1498fe56b9e6SYuval Mintz 1499fe56b9e6SYuval Mintz /* Enable classification by MAC if needed */ 15001a635e48SYuval Mintz if (hw_mode & BIT(MODE_MF_SI)) { 1501fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 1502fe56b9e6SYuval Mintz "Configuring TAGMAC_CLS_TYPE\n"); 1503fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, 1504fe56b9e6SYuval Mintz NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1); 1505fe56b9e6SYuval Mintz } 1506fe56b9e6SYuval Mintz 1507fe56b9e6SYuval Mintz /* Protocl Configuration */ 1508dbb799c3SYuval Mintz STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 1509dbb799c3SYuval Mintz (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0); 15101e128c81SArun Easi STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 15111e128c81SArun Easi (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0); 1512fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0); 1513fe56b9e6SYuval Mintz 1514fe56b9e6SYuval Mintz /* Cleanup chip from previous driver if such remains exist */ 15150b55e27dSYuval Mintz rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false); 15161a635e48SYuval Mintz if (rc) 1517fe56b9e6SYuval Mintz return rc; 1518fe56b9e6SYuval Mintz 1519fe56b9e6SYuval Mintz /* PF Init sequence */ 1520fe56b9e6SYuval Mintz rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode); 1521fe56b9e6SYuval Mintz if (rc) 1522fe56b9e6SYuval Mintz return rc; 1523fe56b9e6SYuval Mintz 1524fe56b9e6SYuval Mintz /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */ 1525fe56b9e6SYuval Mintz rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode); 1526fe56b9e6SYuval Mintz if (rc) 1527fe56b9e6SYuval Mintz return rc; 1528fe56b9e6SYuval Mintz 1529fe56b9e6SYuval Mintz /* Pure runtime initializations - directly to the HW */ 1530fe56b9e6SYuval Mintz qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true); 1531fe56b9e6SYuval Mintz 153251ff1725SRam Amrani rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt); 153351ff1725SRam Amrani if (rc) 153451ff1725SRam Amrani return rc; 153551ff1725SRam Amrani 1536fe56b9e6SYuval Mintz if (b_hw_start) { 1537fe56b9e6SYuval Mintz /* enable interrupts */ 1538fe56b9e6SYuval Mintz qed_int_igu_enable(p_hwfn, p_ptt, int_mode); 1539fe56b9e6SYuval Mintz 1540fe56b9e6SYuval Mintz /* send function start command */ 15414f64675fSManish Chopra rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn, 15424f64675fSManish Chopra p_hwfn->cdev->mf_mode, 1543831bfb0eSYuval Mintz allow_npar_tx_switch); 15441e128c81SArun Easi if (rc) { 1545fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Function start ramrod failed\n"); 15461e128c81SArun Easi return rc; 15471e128c81SArun Easi } 15481e128c81SArun Easi if (p_hwfn->hw_info.personality == QED_PCI_FCOE) { 15491e128c81SArun Easi qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2)); 15501e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 15511e128c81SArun Easi PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST, 15521e128c81SArun Easi 0x100); 15531e128c81SArun Easi } 1554fe56b9e6SYuval Mintz } 1555fe56b9e6SYuval Mintz return rc; 1556fe56b9e6SYuval Mintz } 1557fe56b9e6SYuval Mintz 1558fe56b9e6SYuval Mintz static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn, 1559fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1560fe56b9e6SYuval Mintz u8 enable) 1561fe56b9e6SYuval Mintz { 1562fe56b9e6SYuval Mintz u32 delay_idx = 0, val, set_val = enable ? 1 : 0; 1563fe56b9e6SYuval Mintz 1564fe56b9e6SYuval Mintz /* Change PF in PXP */ 1565fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 1566fe56b9e6SYuval Mintz PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val); 1567fe56b9e6SYuval Mintz 1568fe56b9e6SYuval Mintz /* wait until value is set - try for 1 second every 50us */ 1569fe56b9e6SYuval Mintz for (delay_idx = 0; delay_idx < 20000; delay_idx++) { 1570fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, 1571fe56b9e6SYuval Mintz PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1572fe56b9e6SYuval Mintz if (val == set_val) 1573fe56b9e6SYuval Mintz break; 1574fe56b9e6SYuval Mintz 1575fe56b9e6SYuval Mintz usleep_range(50, 60); 1576fe56b9e6SYuval Mintz } 1577fe56b9e6SYuval Mintz 1578fe56b9e6SYuval Mintz if (val != set_val) { 1579fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 1580fe56b9e6SYuval Mintz "PFID_ENABLE_MASTER wasn't changed after a second\n"); 1581fe56b9e6SYuval Mintz return -EAGAIN; 1582fe56b9e6SYuval Mintz } 1583fe56b9e6SYuval Mintz 1584fe56b9e6SYuval Mintz return 0; 1585fe56b9e6SYuval Mintz } 1586fe56b9e6SYuval Mintz 1587fe56b9e6SYuval Mintz static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn, 1588fe56b9e6SYuval Mintz struct qed_ptt *p_main_ptt) 1589fe56b9e6SYuval Mintz { 1590fe56b9e6SYuval Mintz /* Read shadow of current MFW mailbox */ 1591fe56b9e6SYuval Mintz qed_mcp_read_mb(p_hwfn, p_main_ptt); 1592fe56b9e6SYuval Mintz memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 15931a635e48SYuval Mintz p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length); 1594fe56b9e6SYuval Mintz } 1595fe56b9e6SYuval Mintz 15965d24bcf1STomer Tayar static void 15975d24bcf1STomer Tayar qed_fill_load_req_params(struct qed_load_req_params *p_load_req, 15985d24bcf1STomer Tayar struct qed_drv_load_params *p_drv_load) 15995d24bcf1STomer Tayar { 16005d24bcf1STomer Tayar memset(p_load_req, 0, sizeof(*p_load_req)); 16015d24bcf1STomer Tayar 16025d24bcf1STomer Tayar p_load_req->drv_role = p_drv_load->is_crash_kernel ? 16035d24bcf1STomer Tayar QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS; 16045d24bcf1STomer Tayar p_load_req->timeout_val = p_drv_load->mfw_timeout_val; 16055d24bcf1STomer Tayar p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset; 16065d24bcf1STomer Tayar p_load_req->override_force_load = p_drv_load->override_force_load; 16075d24bcf1STomer Tayar } 16085d24bcf1STomer Tayar 1609eaf3c0c6SChopra, Manish static int qed_vf_start(struct qed_hwfn *p_hwfn, 1610eaf3c0c6SChopra, Manish struct qed_hw_init_params *p_params) 1611eaf3c0c6SChopra, Manish { 1612eaf3c0c6SChopra, Manish if (p_params->p_tunn) { 1613eaf3c0c6SChopra, Manish qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn); 1614eaf3c0c6SChopra, Manish qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn); 1615eaf3c0c6SChopra, Manish } 1616eaf3c0c6SChopra, Manish 1617eaf3c0c6SChopra, Manish p_hwfn->b_int_enabled = 1; 1618eaf3c0c6SChopra, Manish 1619eaf3c0c6SChopra, Manish return 0; 1620eaf3c0c6SChopra, Manish } 1621eaf3c0c6SChopra, Manish 1622c0c2d0b4SMintz, Yuval int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params) 1623fe56b9e6SYuval Mintz { 16245d24bcf1STomer Tayar struct qed_load_req_params load_req_params; 16250fefbfbaSSudarsana Kalluru u32 load_code, param, drv_mb_param; 16260fefbfbaSSudarsana Kalluru bool b_default_mtu = true; 16270fefbfbaSSudarsana Kalluru struct qed_hwfn *p_hwfn; 16280fefbfbaSSudarsana Kalluru int rc = 0, mfw_rc, i; 1629fe56b9e6SYuval Mintz 1630c0c2d0b4SMintz, Yuval if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) { 1631bb13ace7SSudarsana Reddy Kalluru DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n"); 1632bb13ace7SSudarsana Reddy Kalluru return -EINVAL; 1633bb13ace7SSudarsana Reddy Kalluru } 1634bb13ace7SSudarsana Reddy Kalluru 16351408cc1fSYuval Mintz if (IS_PF(cdev)) { 1636c0c2d0b4SMintz, Yuval rc = qed_init_fw_data(cdev, p_params->bin_fw_data); 16371a635e48SYuval Mintz if (rc) 1638fe56b9e6SYuval Mintz return rc; 16391408cc1fSYuval Mintz } 1640fe56b9e6SYuval Mintz 1641fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 1642fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1643fe56b9e6SYuval Mintz 16440fefbfbaSSudarsana Kalluru /* If management didn't provide a default, set one of our own */ 16450fefbfbaSSudarsana Kalluru if (!p_hwfn->hw_info.mtu) { 16460fefbfbaSSudarsana Kalluru p_hwfn->hw_info.mtu = 1500; 16470fefbfbaSSudarsana Kalluru b_default_mtu = false; 16480fefbfbaSSudarsana Kalluru } 16490fefbfbaSSudarsana Kalluru 16501408cc1fSYuval Mintz if (IS_VF(cdev)) { 1651eaf3c0c6SChopra, Manish qed_vf_start(p_hwfn, p_params); 16521408cc1fSYuval Mintz continue; 16531408cc1fSYuval Mintz } 16541408cc1fSYuval Mintz 1655fe56b9e6SYuval Mintz /* Enable DMAE in PXP */ 1656fe56b9e6SYuval Mintz rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true); 1657fe56b9e6SYuval Mintz 16589c79ddaaSMintz, Yuval rc = qed_calc_hw_mode(p_hwfn); 16599c79ddaaSMintz, Yuval if (rc) 16609c79ddaaSMintz, Yuval return rc; 1661fe56b9e6SYuval Mintz 16625d24bcf1STomer Tayar qed_fill_load_req_params(&load_req_params, 16635d24bcf1STomer Tayar p_params->p_drv_load_params); 16645d24bcf1STomer Tayar rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, 16655d24bcf1STomer Tayar &load_req_params); 1666fe56b9e6SYuval Mintz if (rc) { 16675d24bcf1STomer Tayar DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n"); 1668fe56b9e6SYuval Mintz return rc; 1669fe56b9e6SYuval Mintz } 1670fe56b9e6SYuval Mintz 16715d24bcf1STomer Tayar load_code = load_req_params.load_code; 1672fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 16735d24bcf1STomer Tayar "Load request was sent. Load code: 0x%x\n", 16745d24bcf1STomer Tayar load_code); 16755d24bcf1STomer Tayar 16765d24bcf1STomer Tayar qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt); 1677fe56b9e6SYuval Mintz 1678fe56b9e6SYuval Mintz p_hwfn->first_on_engine = (load_code == 1679fe56b9e6SYuval Mintz FW_MSG_CODE_DRV_LOAD_ENGINE); 1680fe56b9e6SYuval Mintz 1681fe56b9e6SYuval Mintz switch (load_code) { 1682fe56b9e6SYuval Mintz case FW_MSG_CODE_DRV_LOAD_ENGINE: 1683fe56b9e6SYuval Mintz rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt, 1684fe56b9e6SYuval Mintz p_hwfn->hw_info.hw_mode); 1685fe56b9e6SYuval Mintz if (rc) 1686fe56b9e6SYuval Mintz break; 1687fe56b9e6SYuval Mintz /* Fall into */ 1688fe56b9e6SYuval Mintz case FW_MSG_CODE_DRV_LOAD_PORT: 1689fe56b9e6SYuval Mintz rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt, 1690fe56b9e6SYuval Mintz p_hwfn->hw_info.hw_mode); 1691fe56b9e6SYuval Mintz if (rc) 1692fe56b9e6SYuval Mintz break; 1693fe56b9e6SYuval Mintz 1694fe56b9e6SYuval Mintz /* Fall into */ 1695fe56b9e6SYuval Mintz case FW_MSG_CODE_DRV_LOAD_FUNCTION: 1696fe56b9e6SYuval Mintz rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt, 1697c0c2d0b4SMintz, Yuval p_params->p_tunn, 1698c0c2d0b4SMintz, Yuval p_hwfn->hw_info.hw_mode, 1699c0c2d0b4SMintz, Yuval p_params->b_hw_start, 1700c0c2d0b4SMintz, Yuval p_params->int_mode, 1701c0c2d0b4SMintz, Yuval p_params->allow_npar_tx_switch); 1702fe56b9e6SYuval Mintz break; 1703fe56b9e6SYuval Mintz default: 1704c0c2d0b4SMintz, Yuval DP_NOTICE(p_hwfn, 1705c0c2d0b4SMintz, Yuval "Unexpected load code [0x%08x]", load_code); 1706fe56b9e6SYuval Mintz rc = -EINVAL; 1707fe56b9e6SYuval Mintz break; 1708fe56b9e6SYuval Mintz } 1709fe56b9e6SYuval Mintz 1710fe56b9e6SYuval Mintz if (rc) 1711fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 1712fe56b9e6SYuval Mintz "init phase failed for loadcode 0x%x (rc %d)\n", 1713fe56b9e6SYuval Mintz load_code, rc); 1714fe56b9e6SYuval Mintz 1715fe56b9e6SYuval Mintz /* ACK mfw regardless of success or failure of initialization */ 1716fe56b9e6SYuval Mintz mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1717fe56b9e6SYuval Mintz DRV_MSG_CODE_LOAD_DONE, 1718fe56b9e6SYuval Mintz 0, &load_code, ¶m); 1719fe56b9e6SYuval Mintz if (rc) 1720fe56b9e6SYuval Mintz return rc; 1721fe56b9e6SYuval Mintz if (mfw_rc) { 1722fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n"); 1723fe56b9e6SYuval Mintz return mfw_rc; 1724fe56b9e6SYuval Mintz } 1725fe56b9e6SYuval Mintz 1726fc561c8bSTomer Tayar /* Check if there is a DID mismatch between nvm-cfg/efuse */ 1727fc561c8bSTomer Tayar if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR) 1728fc561c8bSTomer Tayar DP_NOTICE(p_hwfn, 1729fc561c8bSTomer Tayar "warning: device configuration is not supported on this board type. The device may not function as expected.\n"); 1730fc561c8bSTomer Tayar 173139651abdSSudarsana Reddy Kalluru /* send DCBX attention request command */ 173239651abdSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, 173339651abdSSudarsana Reddy Kalluru QED_MSG_DCB, 173439651abdSSudarsana Reddy Kalluru "sending phony dcbx set command to trigger DCBx attention handling\n"); 173539651abdSSudarsana Reddy Kalluru mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 173639651abdSSudarsana Reddy Kalluru DRV_MSG_CODE_SET_DCBX, 173739651abdSSudarsana Reddy Kalluru 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT, 173839651abdSSudarsana Reddy Kalluru &load_code, ¶m); 173939651abdSSudarsana Reddy Kalluru if (mfw_rc) { 174039651abdSSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 174139651abdSSudarsana Reddy Kalluru "Failed to send DCBX attention request\n"); 174239651abdSSudarsana Reddy Kalluru return mfw_rc; 174339651abdSSudarsana Reddy Kalluru } 174439651abdSSudarsana Reddy Kalluru 1745fe56b9e6SYuval Mintz p_hwfn->hw_init_done = true; 1746fe56b9e6SYuval Mintz } 1747fe56b9e6SYuval Mintz 17480fefbfbaSSudarsana Kalluru if (IS_PF(cdev)) { 17490fefbfbaSSudarsana Kalluru p_hwfn = QED_LEADING_HWFN(cdev); 17505d24bcf1STomer Tayar drv_mb_param = STORM_FW_VERSION; 17510fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 17520fefbfbaSSudarsana Kalluru DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER, 17530fefbfbaSSudarsana Kalluru drv_mb_param, &load_code, ¶m); 17540fefbfbaSSudarsana Kalluru if (rc) 17550fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, "Failed to update firmware version\n"); 17560fefbfbaSSudarsana Kalluru 17570fefbfbaSSudarsana Kalluru if (!b_default_mtu) { 17580fefbfbaSSudarsana Kalluru rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt, 17590fefbfbaSSudarsana Kalluru p_hwfn->hw_info.mtu); 17600fefbfbaSSudarsana Kalluru if (rc) 17610fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, 17620fefbfbaSSudarsana Kalluru "Failed to update default mtu\n"); 17630fefbfbaSSudarsana Kalluru } 17640fefbfbaSSudarsana Kalluru 17650fefbfbaSSudarsana Kalluru rc = qed_mcp_ov_update_driver_state(p_hwfn, 17660fefbfbaSSudarsana Kalluru p_hwfn->p_main_ptt, 17670fefbfbaSSudarsana Kalluru QED_OV_DRIVER_STATE_DISABLED); 17680fefbfbaSSudarsana Kalluru if (rc) 17690fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, "Failed to update driver state\n"); 17700fefbfbaSSudarsana Kalluru 17710fefbfbaSSudarsana Kalluru rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt, 17720fefbfbaSSudarsana Kalluru QED_OV_ESWITCH_VEB); 17730fefbfbaSSudarsana Kalluru if (rc) 17740fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, "Failed to update eswitch mode\n"); 17750fefbfbaSSudarsana Kalluru } 17760fefbfbaSSudarsana Kalluru 1777fe56b9e6SYuval Mintz return 0; 1778fe56b9e6SYuval Mintz } 1779fe56b9e6SYuval Mintz 1780fe56b9e6SYuval Mintz #define QED_HW_STOP_RETRY_LIMIT (10) 17811a635e48SYuval Mintz static void qed_hw_timers_stop(struct qed_dev *cdev, 17821a635e48SYuval Mintz struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 17838c925c44SYuval Mintz { 17848c925c44SYuval Mintz int i; 17858c925c44SYuval Mintz 17868c925c44SYuval Mintz /* close timers */ 17878c925c44SYuval Mintz qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0); 17888c925c44SYuval Mintz qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0); 17898c925c44SYuval Mintz 17908c925c44SYuval Mintz for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) { 17918c925c44SYuval Mintz if ((!qed_rd(p_hwfn, p_ptt, 17928c925c44SYuval Mintz TM_REG_PF_SCAN_ACTIVE_CONN)) && 17931a635e48SYuval Mintz (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK))) 17948c925c44SYuval Mintz break; 17958c925c44SYuval Mintz 17968c925c44SYuval Mintz /* Dependent on number of connection/tasks, possibly 17978c925c44SYuval Mintz * 1ms sleep is required between polls 17988c925c44SYuval Mintz */ 17998c925c44SYuval Mintz usleep_range(1000, 2000); 18008c925c44SYuval Mintz } 18018c925c44SYuval Mintz 18028c925c44SYuval Mintz if (i < QED_HW_STOP_RETRY_LIMIT) 18038c925c44SYuval Mintz return; 18048c925c44SYuval Mintz 18058c925c44SYuval Mintz DP_NOTICE(p_hwfn, 18068c925c44SYuval Mintz "Timers linear scans are not over [Connection %02x Tasks %02x]\n", 18078c925c44SYuval Mintz (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN), 18088c925c44SYuval Mintz (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)); 18098c925c44SYuval Mintz } 18108c925c44SYuval Mintz 18118c925c44SYuval Mintz void qed_hw_timers_stop_all(struct qed_dev *cdev) 18128c925c44SYuval Mintz { 18138c925c44SYuval Mintz int j; 18148c925c44SYuval Mintz 18158c925c44SYuval Mintz for_each_hwfn(cdev, j) { 18168c925c44SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 18178c925c44SYuval Mintz struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 18188c925c44SYuval Mintz 18198c925c44SYuval Mintz qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 18208c925c44SYuval Mintz } 18218c925c44SYuval Mintz } 18228c925c44SYuval Mintz 1823fe56b9e6SYuval Mintz int qed_hw_stop(struct qed_dev *cdev) 1824fe56b9e6SYuval Mintz { 18251226337aSTomer Tayar struct qed_hwfn *p_hwfn; 18261226337aSTomer Tayar struct qed_ptt *p_ptt; 18271226337aSTomer Tayar int rc, rc2 = 0; 18288c925c44SYuval Mintz int j; 1829fe56b9e6SYuval Mintz 1830fe56b9e6SYuval Mintz for_each_hwfn(cdev, j) { 18311226337aSTomer Tayar p_hwfn = &cdev->hwfns[j]; 18321226337aSTomer Tayar p_ptt = p_hwfn->p_main_ptt; 1833fe56b9e6SYuval Mintz 1834fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n"); 1835fe56b9e6SYuval Mintz 18361408cc1fSYuval Mintz if (IS_VF(cdev)) { 18370b55e27dSYuval Mintz qed_vf_pf_int_cleanup(p_hwfn); 18381226337aSTomer Tayar rc = qed_vf_pf_reset(p_hwfn); 18391226337aSTomer Tayar if (rc) { 18401226337aSTomer Tayar DP_NOTICE(p_hwfn, 18411226337aSTomer Tayar "qed_vf_pf_reset failed. rc = %d.\n", 18421226337aSTomer Tayar rc); 18431226337aSTomer Tayar rc2 = -EINVAL; 18441226337aSTomer Tayar } 18451408cc1fSYuval Mintz continue; 18461408cc1fSYuval Mintz } 18471408cc1fSYuval Mintz 1848fe56b9e6SYuval Mintz /* mark the hw as uninitialized... */ 1849fe56b9e6SYuval Mintz p_hwfn->hw_init_done = false; 1850fe56b9e6SYuval Mintz 18511226337aSTomer Tayar /* Send unload command to MCP */ 18521226337aSTomer Tayar rc = qed_mcp_unload_req(p_hwfn, p_ptt); 18531226337aSTomer Tayar if (rc) { 18548c925c44SYuval Mintz DP_NOTICE(p_hwfn, 18551226337aSTomer Tayar "Failed sending a UNLOAD_REQ command. rc = %d.\n", 18561226337aSTomer Tayar rc); 18571226337aSTomer Tayar rc2 = -EINVAL; 18581226337aSTomer Tayar } 18591226337aSTomer Tayar 18601226337aSTomer Tayar qed_slowpath_irq_sync(p_hwfn); 18611226337aSTomer Tayar 18621226337aSTomer Tayar /* After this point no MFW attentions are expected, e.g. prevent 18631226337aSTomer Tayar * race between pf stop and dcbx pf update. 18641226337aSTomer Tayar */ 18651226337aSTomer Tayar rc = qed_sp_pf_stop(p_hwfn); 18661226337aSTomer Tayar if (rc) { 18671226337aSTomer Tayar DP_NOTICE(p_hwfn, 18681226337aSTomer Tayar "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n", 18691226337aSTomer Tayar rc); 18701226337aSTomer Tayar rc2 = -EINVAL; 18711226337aSTomer Tayar } 1872fe56b9e6SYuval Mintz 1873fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 1874fe56b9e6SYuval Mintz NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 1875fe56b9e6SYuval Mintz 1876fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1877fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 1878fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 1879fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1880fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 1881fe56b9e6SYuval Mintz 18828c925c44SYuval Mintz qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 1883fe56b9e6SYuval Mintz 1884fe56b9e6SYuval Mintz /* Disable Attention Generation */ 1885fe56b9e6SYuval Mintz qed_int_igu_disable_int(p_hwfn, p_ptt); 1886fe56b9e6SYuval Mintz 1887fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0); 1888fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0); 1889fe56b9e6SYuval Mintz 1890fe56b9e6SYuval Mintz qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true); 1891fe56b9e6SYuval Mintz 1892fe56b9e6SYuval Mintz /* Need to wait 1ms to guarantee SBs are cleared */ 1893fe56b9e6SYuval Mintz usleep_range(1000, 2000); 18941226337aSTomer Tayar 18951226337aSTomer Tayar /* Disable PF in HW blocks */ 18961226337aSTomer Tayar qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0); 18971226337aSTomer Tayar qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0); 18981226337aSTomer Tayar 18991226337aSTomer Tayar qed_mcp_unload_done(p_hwfn, p_ptt); 19001226337aSTomer Tayar if (rc) { 19011226337aSTomer Tayar DP_NOTICE(p_hwfn, 19021226337aSTomer Tayar "Failed sending a UNLOAD_DONE command. rc = %d.\n", 19031226337aSTomer Tayar rc); 19041226337aSTomer Tayar rc2 = -EINVAL; 19051226337aSTomer Tayar } 1906fe56b9e6SYuval Mintz } 1907fe56b9e6SYuval Mintz 19081408cc1fSYuval Mintz if (IS_PF(cdev)) { 19091226337aSTomer Tayar p_hwfn = QED_LEADING_HWFN(cdev); 19101226337aSTomer Tayar p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt; 19111226337aSTomer Tayar 1912fe56b9e6SYuval Mintz /* Disable DMAE in PXP - in CMT, this should only be done for 1913fe56b9e6SYuval Mintz * first hw-function, and only after all transactions have 1914fe56b9e6SYuval Mintz * stopped for all active hw-functions. 1915fe56b9e6SYuval Mintz */ 19161226337aSTomer Tayar rc = qed_change_pci_hwfn(p_hwfn, p_ptt, false); 19171226337aSTomer Tayar if (rc) { 19181226337aSTomer Tayar DP_NOTICE(p_hwfn, 19191226337aSTomer Tayar "qed_change_pci_hwfn failed. rc = %d.\n", rc); 19201226337aSTomer Tayar rc2 = -EINVAL; 19211226337aSTomer Tayar } 19221408cc1fSYuval Mintz } 1923fe56b9e6SYuval Mintz 19241226337aSTomer Tayar return rc2; 1925fe56b9e6SYuval Mintz } 1926fe56b9e6SYuval Mintz 192715582962SRahul Verma int qed_hw_stop_fastpath(struct qed_dev *cdev) 1928cee4d264SManish Chopra { 19298c925c44SYuval Mintz int j; 1930cee4d264SManish Chopra 1931cee4d264SManish Chopra for_each_hwfn(cdev, j) { 1932cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 193315582962SRahul Verma struct qed_ptt *p_ptt; 1934cee4d264SManish Chopra 1935dacd88d6SYuval Mintz if (IS_VF(cdev)) { 1936dacd88d6SYuval Mintz qed_vf_pf_int_cleanup(p_hwfn); 1937dacd88d6SYuval Mintz continue; 1938dacd88d6SYuval Mintz } 193915582962SRahul Verma p_ptt = qed_ptt_acquire(p_hwfn); 194015582962SRahul Verma if (!p_ptt) 194115582962SRahul Verma return -EAGAIN; 1942dacd88d6SYuval Mintz 1943cee4d264SManish Chopra DP_VERBOSE(p_hwfn, 19441a635e48SYuval Mintz NETIF_MSG_IFDOWN, "Shutting down the fastpath\n"); 1945cee4d264SManish Chopra 1946cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, 1947cee4d264SManish Chopra NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 1948cee4d264SManish Chopra 1949cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1950cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 1951cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 1952cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1953cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 1954cee4d264SManish Chopra 1955cee4d264SManish Chopra qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false); 1956cee4d264SManish Chopra 1957cee4d264SManish Chopra /* Need to wait 1ms to guarantee SBs are cleared */ 1958cee4d264SManish Chopra usleep_range(1000, 2000); 195915582962SRahul Verma qed_ptt_release(p_hwfn, p_ptt); 1960cee4d264SManish Chopra } 1961cee4d264SManish Chopra 196215582962SRahul Verma return 0; 196315582962SRahul Verma } 196415582962SRahul Verma 196515582962SRahul Verma int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn) 1966cee4d264SManish Chopra { 196715582962SRahul Verma struct qed_ptt *p_ptt; 196815582962SRahul Verma 1969dacd88d6SYuval Mintz if (IS_VF(p_hwfn->cdev)) 197015582962SRahul Verma return 0; 197115582962SRahul Verma 197215582962SRahul Verma p_ptt = qed_ptt_acquire(p_hwfn); 197315582962SRahul Verma if (!p_ptt) 197415582962SRahul Verma return -EAGAIN; 1975dacd88d6SYuval Mintz 1976f855df22SMichal Kalderon /* If roce info is allocated it means roce is initialized and should 1977f855df22SMichal Kalderon * be enabled in searcher. 1978f855df22SMichal Kalderon */ 1979f855df22SMichal Kalderon if (p_hwfn->p_rdma_info && 1980f855df22SMichal Kalderon p_hwfn->b_rdma_enabled_in_prs) 1981f855df22SMichal Kalderon qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1); 1982f855df22SMichal Kalderon 1983cee4d264SManish Chopra /* Re-open incoming traffic */ 198415582962SRahul Verma qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0); 198515582962SRahul Verma qed_ptt_release(p_hwfn, p_ptt); 198615582962SRahul Verma 198715582962SRahul Verma return 0; 1988cee4d264SManish Chopra } 1989cee4d264SManish Chopra 1990fe56b9e6SYuval Mintz /* Free hwfn memory and resources acquired in hw_hwfn_prepare */ 1991fe56b9e6SYuval Mintz static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn) 1992fe56b9e6SYuval Mintz { 1993fe56b9e6SYuval Mintz qed_ptt_pool_free(p_hwfn); 1994fe56b9e6SYuval Mintz kfree(p_hwfn->hw_info.p_igu_info); 19953587cb87STomer Tayar p_hwfn->hw_info.p_igu_info = NULL; 1996fe56b9e6SYuval Mintz } 1997fe56b9e6SYuval Mintz 1998fe56b9e6SYuval Mintz /* Setup bar access */ 199912e09c69SYuval Mintz static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn) 2000fe56b9e6SYuval Mintz { 2001fe56b9e6SYuval Mintz /* clear indirect access */ 20029c79ddaaSMintz, Yuval if (QED_IS_AH(p_hwfn->cdev)) { 20039c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 20049c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0); 20059c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 20069c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0); 20079c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 20089c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0); 20099c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 20109c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0); 20119c79ddaaSMintz, Yuval } else { 20129c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 20139c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0); 20149c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 20159c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0); 20169c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 20179c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0); 20189c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 20199c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0); 20209c79ddaaSMintz, Yuval } 2021fe56b9e6SYuval Mintz 2022fe56b9e6SYuval Mintz /* Clean Previous errors if such exist */ 2023fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, 20241a635e48SYuval Mintz PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id); 2025fe56b9e6SYuval Mintz 2026fe56b9e6SYuval Mintz /* enable internal target-read */ 2027fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, 2028fe56b9e6SYuval Mintz PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 2029fe56b9e6SYuval Mintz } 2030fe56b9e6SYuval Mintz 2031fe56b9e6SYuval Mintz static void get_function_id(struct qed_hwfn *p_hwfn) 2032fe56b9e6SYuval Mintz { 2033fe56b9e6SYuval Mintz /* ME Register */ 20341a635e48SYuval Mintz p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn, 20351a635e48SYuval Mintz PXP_PF_ME_OPAQUE_ADDR); 2036fe56b9e6SYuval Mintz 2037fe56b9e6SYuval Mintz p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); 2038fe56b9e6SYuval Mintz 2039fe56b9e6SYuval Mintz p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf; 2040fe56b9e6SYuval Mintz p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 2041fe56b9e6SYuval Mintz PXP_CONCRETE_FID_PFID); 2042fe56b9e6SYuval Mintz p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 2043fe56b9e6SYuval Mintz PXP_CONCRETE_FID_PORT); 2044525ef5c0SYuval Mintz 2045525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, 2046525ef5c0SYuval Mintz "Read ME register: Concrete 0x%08x Opaque 0x%04x\n", 2047525ef5c0SYuval Mintz p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid); 2048fe56b9e6SYuval Mintz } 2049fe56b9e6SYuval Mintz 205025c089d7SYuval Mintz static void qed_hw_set_feat(struct qed_hwfn *p_hwfn) 205125c089d7SYuval Mintz { 205225c089d7SYuval Mintz u32 *feat_num = p_hwfn->hw_info.feat_num; 2053ebbdcc66SMintz, Yuval struct qed_sb_cnt_info sb_cnt; 2054810bb1f0SMintz, Yuval u32 non_l2_sbs = 0; 205525c089d7SYuval Mintz 2056ebbdcc66SMintz, Yuval memset(&sb_cnt, 0, sizeof(sb_cnt)); 2057ebbdcc66SMintz, Yuval qed_int_get_num_sbs(p_hwfn, &sb_cnt); 2058ebbdcc66SMintz, Yuval 20590189efb8SYuval Mintz if (IS_ENABLED(CONFIG_QED_RDMA) && 20600189efb8SYuval Mintz p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) { 20610189efb8SYuval Mintz /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide 20620189efb8SYuval Mintz * the status blocks equally between L2 / RoCE but with 20630189efb8SYuval Mintz * consideration as to how many l2 queues / cnqs we have. 206451ff1725SRam Amrani */ 206551ff1725SRam Amrani feat_num[QED_RDMA_CNQ] = 2066ebbdcc66SMintz, Yuval min_t(u32, sb_cnt.cnt / 2, 206751ff1725SRam Amrani RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM)); 2068810bb1f0SMintz, Yuval 2069810bb1f0SMintz, Yuval non_l2_sbs = feat_num[QED_RDMA_CNQ]; 207051ff1725SRam Amrani } 20710189efb8SYuval Mintz 2072dec26533SMintz, Yuval if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE || 2073dec26533SMintz, Yuval p_hwfn->hw_info.personality == QED_PCI_ETH) { 2074dec26533SMintz, Yuval /* Start by allocating VF queues, then PF's */ 2075dec26533SMintz, Yuval feat_num[QED_VF_L2_QUE] = min_t(u32, 2076dec26533SMintz, Yuval RESC_NUM(p_hwfn, QED_L2_QUEUE), 2077ebbdcc66SMintz, Yuval sb_cnt.iov_cnt); 2078810bb1f0SMintz, Yuval feat_num[QED_PF_L2_QUE] = min_t(u32, 2079ebbdcc66SMintz, Yuval sb_cnt.cnt - non_l2_sbs, 2080dec26533SMintz, Yuval RESC_NUM(p_hwfn, 2081dec26533SMintz, Yuval QED_L2_QUEUE) - 2082dec26533SMintz, Yuval FEAT_NUM(p_hwfn, 2083dec26533SMintz, Yuval QED_VF_L2_QUE)); 2084dec26533SMintz, Yuval } 20855a1f965aSMintz, Yuval 20863c5da942SMintz, Yuval if (p_hwfn->hw_info.personality == QED_PCI_FCOE) 20873c5da942SMintz, Yuval feat_num[QED_FCOE_CQ] = min_t(u32, sb_cnt.cnt, 20883c5da942SMintz, Yuval RESC_NUM(p_hwfn, 20893c5da942SMintz, Yuval QED_CMDQS_CQS)); 20903c5da942SMintz, Yuval 209108737a3fSMintz, Yuval if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) 2092ebbdcc66SMintz, Yuval feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt, 209308737a3fSMintz, Yuval RESC_NUM(p_hwfn, 209408737a3fSMintz, Yuval QED_CMDQS_CQS)); 20955a1f965aSMintz, Yuval DP_VERBOSE(p_hwfn, 20965a1f965aSMintz, Yuval NETIF_MSG_PROBE, 20973c5da942SMintz, Yuval "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d #SBS=%d\n", 20985a1f965aSMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE), 20995a1f965aSMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE), 21005a1f965aSMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ), 21013c5da942SMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ), 210208737a3fSMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ), 2103ebbdcc66SMintz, Yuval (int)sb_cnt.cnt); 210425c089d7SYuval Mintz } 210525c089d7SYuval Mintz 21069c8517c4STomer Tayar const char *qed_hw_get_resc_name(enum qed_resources res_id) 21072edbff8dSTomer Tayar { 21082edbff8dSTomer Tayar switch (res_id) { 21092edbff8dSTomer Tayar case QED_L2_QUEUE: 21102edbff8dSTomer Tayar return "L2_QUEUE"; 21112edbff8dSTomer Tayar case QED_VPORT: 21122edbff8dSTomer Tayar return "VPORT"; 21132edbff8dSTomer Tayar case QED_RSS_ENG: 21142edbff8dSTomer Tayar return "RSS_ENG"; 21152edbff8dSTomer Tayar case QED_PQ: 21162edbff8dSTomer Tayar return "PQ"; 21172edbff8dSTomer Tayar case QED_RL: 21182edbff8dSTomer Tayar return "RL"; 21192edbff8dSTomer Tayar case QED_MAC: 21202edbff8dSTomer Tayar return "MAC"; 21212edbff8dSTomer Tayar case QED_VLAN: 21222edbff8dSTomer Tayar return "VLAN"; 21232edbff8dSTomer Tayar case QED_RDMA_CNQ_RAM: 21242edbff8dSTomer Tayar return "RDMA_CNQ_RAM"; 21252edbff8dSTomer Tayar case QED_ILT: 21262edbff8dSTomer Tayar return "ILT"; 21272edbff8dSTomer Tayar case QED_LL2_QUEUE: 21282edbff8dSTomer Tayar return "LL2_QUEUE"; 21292edbff8dSTomer Tayar case QED_CMDQS_CQS: 21302edbff8dSTomer Tayar return "CMDQS_CQS"; 21312edbff8dSTomer Tayar case QED_RDMA_STATS_QUEUE: 21322edbff8dSTomer Tayar return "RDMA_STATS_QUEUE"; 21339c8517c4STomer Tayar case QED_BDQ: 21349c8517c4STomer Tayar return "BDQ"; 21359c8517c4STomer Tayar case QED_SB: 21369c8517c4STomer Tayar return "SB"; 21372edbff8dSTomer Tayar default: 21382edbff8dSTomer Tayar return "UNKNOWN_RESOURCE"; 21392edbff8dSTomer Tayar } 21402edbff8dSTomer Tayar } 21412edbff8dSTomer Tayar 21429c8517c4STomer Tayar static int 21439c8517c4STomer Tayar __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, 21449c8517c4STomer Tayar struct qed_ptt *p_ptt, 21459c8517c4STomer Tayar enum qed_resources res_id, 21469c8517c4STomer Tayar u32 resc_max_val, u32 *p_mcp_resp) 21479c8517c4STomer Tayar { 21489c8517c4STomer Tayar int rc; 21499c8517c4STomer Tayar 21509c8517c4STomer Tayar rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id, 21519c8517c4STomer Tayar resc_max_val, p_mcp_resp); 21529c8517c4STomer Tayar if (rc) { 21539c8517c4STomer Tayar DP_NOTICE(p_hwfn, 21549c8517c4STomer Tayar "MFW response failure for a max value setting of resource %d [%s]\n", 21559c8517c4STomer Tayar res_id, qed_hw_get_resc_name(res_id)); 21569c8517c4STomer Tayar return rc; 21579c8517c4STomer Tayar } 21589c8517c4STomer Tayar 21599c8517c4STomer Tayar if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) 21609c8517c4STomer Tayar DP_INFO(p_hwfn, 21619c8517c4STomer Tayar "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n", 21629c8517c4STomer Tayar res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp); 21639c8517c4STomer Tayar 21649c8517c4STomer Tayar return 0; 21659c8517c4STomer Tayar } 21669c8517c4STomer Tayar 21679c8517c4STomer Tayar static int 21689c8517c4STomer Tayar qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 21699c8517c4STomer Tayar { 21709c8517c4STomer Tayar bool b_ah = QED_IS_AH(p_hwfn->cdev); 21719c8517c4STomer Tayar u32 resc_max_val, mcp_resp; 21729c8517c4STomer Tayar u8 res_id; 21739c8517c4STomer Tayar int rc; 21749c8517c4STomer Tayar 21759c8517c4STomer Tayar for (res_id = 0; res_id < QED_MAX_RESC; res_id++) { 21769c8517c4STomer Tayar switch (res_id) { 21779c8517c4STomer Tayar case QED_LL2_QUEUE: 21789c8517c4STomer Tayar resc_max_val = MAX_NUM_LL2_RX_QUEUES; 21799c8517c4STomer Tayar break; 21809c8517c4STomer Tayar case QED_RDMA_CNQ_RAM: 21819c8517c4STomer Tayar /* No need for a case for QED_CMDQS_CQS since 21829c8517c4STomer Tayar * CNQ/CMDQS are the same resource. 21839c8517c4STomer Tayar */ 21849c8517c4STomer Tayar resc_max_val = NUM_OF_CMDQS_CQS; 21859c8517c4STomer Tayar break; 21869c8517c4STomer Tayar case QED_RDMA_STATS_QUEUE: 21879c8517c4STomer Tayar resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 21889c8517c4STomer Tayar : RDMA_NUM_STATISTIC_COUNTERS_BB; 21899c8517c4STomer Tayar break; 21909c8517c4STomer Tayar case QED_BDQ: 21919c8517c4STomer Tayar resc_max_val = BDQ_NUM_RESOURCES; 21929c8517c4STomer Tayar break; 21939c8517c4STomer Tayar default: 21949c8517c4STomer Tayar continue; 21959c8517c4STomer Tayar } 21969c8517c4STomer Tayar 21979c8517c4STomer Tayar rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id, 21989c8517c4STomer Tayar resc_max_val, &mcp_resp); 21999c8517c4STomer Tayar if (rc) 22009c8517c4STomer Tayar return rc; 22019c8517c4STomer Tayar 22029c8517c4STomer Tayar /* There's no point to continue to the next resource if the 22039c8517c4STomer Tayar * command is not supported by the MFW. 22049c8517c4STomer Tayar * We do continue if the command is supported but the resource 22059c8517c4STomer Tayar * is unknown to the MFW. Such a resource will be later 22069c8517c4STomer Tayar * configured with the default allocation values. 22079c8517c4STomer Tayar */ 22089c8517c4STomer Tayar if (mcp_resp == FW_MSG_CODE_UNSUPPORTED) 22099c8517c4STomer Tayar return -EINVAL; 22109c8517c4STomer Tayar } 22119c8517c4STomer Tayar 22129c8517c4STomer Tayar return 0; 22139c8517c4STomer Tayar } 22149c8517c4STomer Tayar 22159c8517c4STomer Tayar static 22169c8517c4STomer Tayar int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn, 22179c8517c4STomer Tayar enum qed_resources res_id, 22189c8517c4STomer Tayar u32 *p_resc_num, u32 *p_resc_start) 22199c8517c4STomer Tayar { 22209c8517c4STomer Tayar u8 num_funcs = p_hwfn->num_funcs_on_engine; 22219c8517c4STomer Tayar bool b_ah = QED_IS_AH(p_hwfn->cdev); 22229c8517c4STomer Tayar 22239c8517c4STomer Tayar switch (res_id) { 22249c8517c4STomer Tayar case QED_L2_QUEUE: 22259c8517c4STomer Tayar *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 : 22269c8517c4STomer Tayar MAX_NUM_L2_QUEUES_BB) / num_funcs; 22279c8517c4STomer Tayar break; 22289c8517c4STomer Tayar case QED_VPORT: 22299c8517c4STomer Tayar *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 : 22309c8517c4STomer Tayar MAX_NUM_VPORTS_BB) / num_funcs; 22319c8517c4STomer Tayar break; 22329c8517c4STomer Tayar case QED_RSS_ENG: 22339c8517c4STomer Tayar *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 : 22349c8517c4STomer Tayar ETH_RSS_ENGINE_NUM_BB) / num_funcs; 22359c8517c4STomer Tayar break; 22369c8517c4STomer Tayar case QED_PQ: 22379c8517c4STomer Tayar *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 : 22389c8517c4STomer Tayar MAX_QM_TX_QUEUES_BB) / num_funcs; 22399c8517c4STomer Tayar *p_resc_num &= ~0x7; /* The granularity of the PQs is 8 */ 22409c8517c4STomer Tayar break; 22419c8517c4STomer Tayar case QED_RL: 22429c8517c4STomer Tayar *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs; 22439c8517c4STomer Tayar break; 22449c8517c4STomer Tayar case QED_MAC: 22459c8517c4STomer Tayar case QED_VLAN: 22469c8517c4STomer Tayar /* Each VFC resource can accommodate both a MAC and a VLAN */ 22479c8517c4STomer Tayar *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs; 22489c8517c4STomer Tayar break; 22499c8517c4STomer Tayar case QED_ILT: 22509c8517c4STomer Tayar *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 : 22519c8517c4STomer Tayar PXP_NUM_ILT_RECORDS_BB) / num_funcs; 22529c8517c4STomer Tayar break; 22539c8517c4STomer Tayar case QED_LL2_QUEUE: 22549c8517c4STomer Tayar *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs; 22559c8517c4STomer Tayar break; 22569c8517c4STomer Tayar case QED_RDMA_CNQ_RAM: 22579c8517c4STomer Tayar case QED_CMDQS_CQS: 22589c8517c4STomer Tayar /* CNQ/CMDQS are the same resource */ 22599c8517c4STomer Tayar *p_resc_num = NUM_OF_CMDQS_CQS / num_funcs; 22609c8517c4STomer Tayar break; 22619c8517c4STomer Tayar case QED_RDMA_STATS_QUEUE: 22629c8517c4STomer Tayar *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 : 22639c8517c4STomer Tayar RDMA_NUM_STATISTIC_COUNTERS_BB) / num_funcs; 22649c8517c4STomer Tayar break; 22659c8517c4STomer Tayar case QED_BDQ: 22669c8517c4STomer Tayar if (p_hwfn->hw_info.personality != QED_PCI_ISCSI && 22679c8517c4STomer Tayar p_hwfn->hw_info.personality != QED_PCI_FCOE) 22689c8517c4STomer Tayar *p_resc_num = 0; 22699c8517c4STomer Tayar else 22709c8517c4STomer Tayar *p_resc_num = 1; 22719c8517c4STomer Tayar break; 22729c8517c4STomer Tayar case QED_SB: 2273ebbdcc66SMintz, Yuval /* Since we want its value to reflect whether MFW supports 2274ebbdcc66SMintz, Yuval * the new scheme, have a default of 0. 2275ebbdcc66SMintz, Yuval */ 2276ebbdcc66SMintz, Yuval *p_resc_num = 0; 22779c8517c4STomer Tayar break; 22789c8517c4STomer Tayar default: 22799c8517c4STomer Tayar return -EINVAL; 22809c8517c4STomer Tayar } 22819c8517c4STomer Tayar 22829c8517c4STomer Tayar switch (res_id) { 22839c8517c4STomer Tayar case QED_BDQ: 22849c8517c4STomer Tayar if (!*p_resc_num) 22859c8517c4STomer Tayar *p_resc_start = 0; 228678cea9ffSTomer Tayar else if (p_hwfn->cdev->num_ports_in_engine == 4) 22879c8517c4STomer Tayar *p_resc_start = p_hwfn->port_id; 22889c8517c4STomer Tayar else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) 22899c8517c4STomer Tayar *p_resc_start = p_hwfn->port_id; 22909c8517c4STomer Tayar else if (p_hwfn->hw_info.personality == QED_PCI_FCOE) 22919c8517c4STomer Tayar *p_resc_start = p_hwfn->port_id + 2; 22929c8517c4STomer Tayar break; 22939c8517c4STomer Tayar default: 22949c8517c4STomer Tayar *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx; 22959c8517c4STomer Tayar break; 22969c8517c4STomer Tayar } 22979c8517c4STomer Tayar 22989c8517c4STomer Tayar return 0; 22999c8517c4STomer Tayar } 23009c8517c4STomer Tayar 23019c8517c4STomer Tayar static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn, 23022edbff8dSTomer Tayar enum qed_resources res_id) 23032edbff8dSTomer Tayar { 23049c8517c4STomer Tayar u32 dflt_resc_num = 0, dflt_resc_start = 0; 23059c8517c4STomer Tayar u32 mcp_resp, *p_resc_num, *p_resc_start; 23062edbff8dSTomer Tayar int rc; 23072edbff8dSTomer Tayar 23082edbff8dSTomer Tayar p_resc_num = &RESC_NUM(p_hwfn, res_id); 23092edbff8dSTomer Tayar p_resc_start = &RESC_START(p_hwfn, res_id); 23102edbff8dSTomer Tayar 23119c8517c4STomer Tayar rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num, 23129c8517c4STomer Tayar &dflt_resc_start); 23139c8517c4STomer Tayar if (rc) { 23142edbff8dSTomer Tayar DP_ERR(p_hwfn, 23152edbff8dSTomer Tayar "Failed to get default amount for resource %d [%s]\n", 23162edbff8dSTomer Tayar res_id, qed_hw_get_resc_name(res_id)); 23179c8517c4STomer Tayar return rc; 23182edbff8dSTomer Tayar } 23192edbff8dSTomer Tayar 23209c8517c4STomer Tayar rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id, 23219c8517c4STomer Tayar &mcp_resp, p_resc_num, p_resc_start); 23222edbff8dSTomer Tayar if (rc) { 23232edbff8dSTomer Tayar DP_NOTICE(p_hwfn, 23242edbff8dSTomer Tayar "MFW response failure for an allocation request for resource %d [%s]\n", 23252edbff8dSTomer Tayar res_id, qed_hw_get_resc_name(res_id)); 23262edbff8dSTomer Tayar return rc; 23272edbff8dSTomer Tayar } 23282edbff8dSTomer Tayar 23292edbff8dSTomer Tayar /* Default driver values are applied in the following cases: 23302edbff8dSTomer Tayar * - The resource allocation MB command is not supported by the MFW 23312edbff8dSTomer Tayar * - There is an internal error in the MFW while processing the request 23322edbff8dSTomer Tayar * - The resource ID is unknown to the MFW 23332edbff8dSTomer Tayar */ 23349c8517c4STomer Tayar if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) { 23359c8517c4STomer Tayar DP_INFO(p_hwfn, 23369c8517c4STomer Tayar "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n", 23372edbff8dSTomer Tayar res_id, 23382edbff8dSTomer Tayar qed_hw_get_resc_name(res_id), 23392edbff8dSTomer Tayar mcp_resp, dflt_resc_num, dflt_resc_start); 23402edbff8dSTomer Tayar *p_resc_num = dflt_resc_num; 23412edbff8dSTomer Tayar *p_resc_start = dflt_resc_start; 23422edbff8dSTomer Tayar goto out; 23432edbff8dSTomer Tayar } 23442edbff8dSTomer Tayar 23452edbff8dSTomer Tayar out: 23462edbff8dSTomer Tayar /* PQs have to divide by 8 [that's the HW granularity]. 23472edbff8dSTomer Tayar * Reduce number so it would fit. 23482edbff8dSTomer Tayar */ 23492edbff8dSTomer Tayar if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) { 23502edbff8dSTomer Tayar DP_INFO(p_hwfn, 23512edbff8dSTomer Tayar "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n", 23522edbff8dSTomer Tayar *p_resc_num, 23532edbff8dSTomer Tayar (*p_resc_num) & ~0x7, 23542edbff8dSTomer Tayar *p_resc_start, (*p_resc_start) & ~0x7); 23552edbff8dSTomer Tayar *p_resc_num &= ~0x7; 23562edbff8dSTomer Tayar *p_resc_start &= ~0x7; 23572edbff8dSTomer Tayar } 23582edbff8dSTomer Tayar 23592edbff8dSTomer Tayar return 0; 23602edbff8dSTomer Tayar } 23612edbff8dSTomer Tayar 23629c8517c4STomer Tayar static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn) 2363fe56b9e6SYuval Mintz { 23649c8517c4STomer Tayar int rc; 23659c8517c4STomer Tayar u8 res_id; 23669c8517c4STomer Tayar 23679c8517c4STomer Tayar for (res_id = 0; res_id < QED_MAX_RESC; res_id++) { 23689c8517c4STomer Tayar rc = __qed_hw_set_resc_info(p_hwfn, res_id); 23699c8517c4STomer Tayar if (rc) 23709c8517c4STomer Tayar return rc; 23719c8517c4STomer Tayar } 23729c8517c4STomer Tayar 23739c8517c4STomer Tayar return 0; 23749c8517c4STomer Tayar } 23759c8517c4STomer Tayar 23769c8517c4STomer Tayar static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 23779c8517c4STomer Tayar { 23789c8517c4STomer Tayar struct qed_resc_unlock_params resc_unlock_params; 23799c8517c4STomer Tayar struct qed_resc_lock_params resc_lock_params; 23809c79ddaaSMintz, Yuval bool b_ah = QED_IS_AH(p_hwfn->cdev); 23812edbff8dSTomer Tayar u8 res_id; 23822edbff8dSTomer Tayar int rc; 2383fe56b9e6SYuval Mintz 23849c8517c4STomer Tayar /* Setting the max values of the soft resources and the following 23859c8517c4STomer Tayar * resources allocation queries should be atomic. Since several PFs can 23869c8517c4STomer Tayar * run in parallel - a resource lock is needed. 23879c8517c4STomer Tayar * If either the resource lock or resource set value commands are not 23889c8517c4STomer Tayar * supported - skip the the max values setting, release the lock if 23899c8517c4STomer Tayar * needed, and proceed to the queries. Other failures, including a 23909c8517c4STomer Tayar * failure to acquire the lock, will cause this function to fail. 23919c8517c4STomer Tayar */ 2392f470f22cSsudarsana.kalluru@cavium.com qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params, 2393f470f22cSsudarsana.kalluru@cavium.com QED_RESC_LOCK_RESC_ALLOC, false); 23949c8517c4STomer Tayar 23959c8517c4STomer Tayar rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params); 23969c8517c4STomer Tayar if (rc && rc != -EINVAL) { 23972edbff8dSTomer Tayar return rc; 23989c8517c4STomer Tayar } else if (rc == -EINVAL) { 23999c8517c4STomer Tayar DP_INFO(p_hwfn, 24009c8517c4STomer Tayar "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n"); 24019c8517c4STomer Tayar } else if (!rc && !resc_lock_params.b_granted) { 24029c8517c4STomer Tayar DP_NOTICE(p_hwfn, 24039c8517c4STomer Tayar "Failed to acquire the resource lock for the resource allocation commands\n"); 24049c8517c4STomer Tayar return -EBUSY; 24059c8517c4STomer Tayar } else { 24069c8517c4STomer Tayar rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt); 24079c8517c4STomer Tayar if (rc && rc != -EINVAL) { 24089c8517c4STomer Tayar DP_NOTICE(p_hwfn, 24099c8517c4STomer Tayar "Failed to set the max values of the soft resources\n"); 24109c8517c4STomer Tayar goto unlock_and_exit; 24119c8517c4STomer Tayar } else if (rc == -EINVAL) { 24129c8517c4STomer Tayar DP_INFO(p_hwfn, 24139c8517c4STomer Tayar "Skip the max values setting of the soft resources since it is not supported by the MFW\n"); 24149c8517c4STomer Tayar rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, 24159c8517c4STomer Tayar &resc_unlock_params); 24169c8517c4STomer Tayar if (rc) 24179c8517c4STomer Tayar DP_INFO(p_hwfn, 24189c8517c4STomer Tayar "Failed to release the resource lock for the resource allocation commands\n"); 24199c8517c4STomer Tayar } 24209c8517c4STomer Tayar } 24219c8517c4STomer Tayar 24229c8517c4STomer Tayar rc = qed_hw_set_resc_info(p_hwfn); 24239c8517c4STomer Tayar if (rc) 24249c8517c4STomer Tayar goto unlock_and_exit; 24259c8517c4STomer Tayar 24269c8517c4STomer Tayar if (resc_lock_params.b_granted && !resc_unlock_params.b_released) { 24279c8517c4STomer Tayar rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params); 24289c8517c4STomer Tayar if (rc) 24299c8517c4STomer Tayar DP_INFO(p_hwfn, 24309c8517c4STomer Tayar "Failed to release the resource lock for the resource allocation commands\n"); 24312edbff8dSTomer Tayar } 2432dbb799c3SYuval Mintz 2433dbb799c3SYuval Mintz /* Sanity for ILT */ 24349c79ddaaSMintz, Yuval if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) || 24359c79ddaaSMintz, Yuval (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) { 2436dbb799c3SYuval Mintz DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n", 2437dbb799c3SYuval Mintz RESC_START(p_hwfn, QED_ILT), 2438dbb799c3SYuval Mintz RESC_END(p_hwfn, QED_ILT) - 1); 2439dbb799c3SYuval Mintz return -EINVAL; 2440dbb799c3SYuval Mintz } 2441fe56b9e6SYuval Mintz 2442ebbdcc66SMintz, Yuval /* This will also learn the number of SBs from MFW */ 2443ebbdcc66SMintz, Yuval if (qed_int_igu_reset_cam(p_hwfn, p_ptt)) 2444ebbdcc66SMintz, Yuval return -EINVAL; 2445ebbdcc66SMintz, Yuval 244625c089d7SYuval Mintz qed_hw_set_feat(p_hwfn); 244725c089d7SYuval Mintz 24482edbff8dSTomer Tayar for (res_id = 0; res_id < QED_MAX_RESC; res_id++) 24492edbff8dSTomer Tayar DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n", 24502edbff8dSTomer Tayar qed_hw_get_resc_name(res_id), 24512edbff8dSTomer Tayar RESC_NUM(p_hwfn, res_id), 24522edbff8dSTomer Tayar RESC_START(p_hwfn, res_id)); 2453dbb799c3SYuval Mintz 2454dbb799c3SYuval Mintz return 0; 24559c8517c4STomer Tayar 24569c8517c4STomer Tayar unlock_and_exit: 24579c8517c4STomer Tayar if (resc_lock_params.b_granted && !resc_unlock_params.b_released) 24589c8517c4STomer Tayar qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params); 24599c8517c4STomer Tayar return rc; 2460fe56b9e6SYuval Mintz } 2461fe56b9e6SYuval Mintz 24621a635e48SYuval Mintz static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2463fe56b9e6SYuval Mintz { 2464fc48b7a6SYuval Mintz u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities; 24651e128c81SArun Easi u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg; 2466cc875c2eSYuval Mintz struct qed_mcp_link_params *link; 2467fe56b9e6SYuval Mintz 2468fe56b9e6SYuval Mintz /* Read global nvm_cfg address */ 2469fe56b9e6SYuval Mintz nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 2470fe56b9e6SYuval Mintz 2471fe56b9e6SYuval Mintz /* Verify MCP has initialized it */ 2472fe56b9e6SYuval Mintz if (!nvm_cfg_addr) { 2473fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 2474fe56b9e6SYuval Mintz return -EINVAL; 2475fe56b9e6SYuval Mintz } 2476fe56b9e6SYuval Mintz 2477fe56b9e6SYuval Mintz /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */ 2478fe56b9e6SYuval Mintz nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 2479fe56b9e6SYuval Mintz 2480cc875c2eSYuval Mintz addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2481cc875c2eSYuval Mintz offsetof(struct nvm_cfg1, glob) + 2482cc875c2eSYuval Mintz offsetof(struct nvm_cfg1_glob, core_cfg); 2483cc875c2eSYuval Mintz 2484cc875c2eSYuval Mintz core_cfg = qed_rd(p_hwfn, p_ptt, addr); 2485cc875c2eSYuval Mintz 2486cc875c2eSYuval Mintz switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >> 2487cc875c2eSYuval Mintz NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) { 2488351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G: 2489cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G; 2490cc875c2eSYuval Mintz break; 2491351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G: 2492cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G; 2493cc875c2eSYuval Mintz break; 2494351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G: 2495cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G; 2496cc875c2eSYuval Mintz break; 2497351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F: 2498cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F; 2499cc875c2eSYuval Mintz break; 2500351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E: 2501cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E; 2502cc875c2eSYuval Mintz break; 2503351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G: 2504cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G; 2505cc875c2eSYuval Mintz break; 2506351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G: 2507cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G; 2508cc875c2eSYuval Mintz break; 2509351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G: 2510cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G; 2511cc875c2eSYuval Mintz break; 25129c79ddaaSMintz, Yuval case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G: 25139c79ddaaSMintz, Yuval p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G; 25149c79ddaaSMintz, Yuval break; 2515351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G: 2516cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G; 2517cc875c2eSYuval Mintz break; 25189c79ddaaSMintz, Yuval case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G: 25199c79ddaaSMintz, Yuval p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G; 25209c79ddaaSMintz, Yuval break; 2521cc875c2eSYuval Mintz default: 25221a635e48SYuval Mintz DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg); 2523cc875c2eSYuval Mintz break; 2524cc875c2eSYuval Mintz } 2525cc875c2eSYuval Mintz 2526cc875c2eSYuval Mintz /* Read default link configuration */ 2527cc875c2eSYuval Mintz link = &p_hwfn->mcp_info->link_input; 2528cc875c2eSYuval Mintz port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2529cc875c2eSYuval Mintz offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 2530cc875c2eSYuval Mintz link_temp = qed_rd(p_hwfn, p_ptt, 2531cc875c2eSYuval Mintz port_cfg_addr + 2532cc875c2eSYuval Mintz offsetof(struct nvm_cfg1_port, speed_cap_mask)); 253383aeb933SYuval Mintz link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK; 253483aeb933SYuval Mintz link->speed.advertised_speeds = link_temp; 2535cc875c2eSYuval Mintz 253683aeb933SYuval Mintz link_temp = link->speed.advertised_speeds; 253783aeb933SYuval Mintz p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp; 2538cc875c2eSYuval Mintz 2539cc875c2eSYuval Mintz link_temp = qed_rd(p_hwfn, p_ptt, 2540cc875c2eSYuval Mintz port_cfg_addr + 2541cc875c2eSYuval Mintz offsetof(struct nvm_cfg1_port, link_settings)); 2542cc875c2eSYuval Mintz switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >> 2543cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) { 2544cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG: 2545cc875c2eSYuval Mintz link->speed.autoneg = true; 2546cc875c2eSYuval Mintz break; 2547cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_1G: 2548cc875c2eSYuval Mintz link->speed.forced_speed = 1000; 2549cc875c2eSYuval Mintz break; 2550cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_10G: 2551cc875c2eSYuval Mintz link->speed.forced_speed = 10000; 2552cc875c2eSYuval Mintz break; 2553cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_25G: 2554cc875c2eSYuval Mintz link->speed.forced_speed = 25000; 2555cc875c2eSYuval Mintz break; 2556cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_40G: 2557cc875c2eSYuval Mintz link->speed.forced_speed = 40000; 2558cc875c2eSYuval Mintz break; 2559cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_50G: 2560cc875c2eSYuval Mintz link->speed.forced_speed = 50000; 2561cc875c2eSYuval Mintz break; 2562351a4dedSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G: 2563cc875c2eSYuval Mintz link->speed.forced_speed = 100000; 2564cc875c2eSYuval Mintz break; 2565cc875c2eSYuval Mintz default: 25661a635e48SYuval Mintz DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp); 2567cc875c2eSYuval Mintz } 2568cc875c2eSYuval Mintz 256934f9199cSsudarsana.kalluru@cavium.com p_hwfn->mcp_info->link_capabilities.default_speed_autoneg = 257034f9199cSsudarsana.kalluru@cavium.com link->speed.autoneg; 257134f9199cSsudarsana.kalluru@cavium.com 2572cc875c2eSYuval Mintz link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK; 2573cc875c2eSYuval Mintz link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET; 2574cc875c2eSYuval Mintz link->pause.autoneg = !!(link_temp & 2575cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG); 2576cc875c2eSYuval Mintz link->pause.forced_rx = !!(link_temp & 2577cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX); 2578cc875c2eSYuval Mintz link->pause.forced_tx = !!(link_temp & 2579cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX); 2580cc875c2eSYuval Mintz link->loopback_mode = 0; 2581cc875c2eSYuval Mintz 2582cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2583cc875c2eSYuval Mintz "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n", 2584cc875c2eSYuval Mintz link->speed.forced_speed, link->speed.advertised_speeds, 2585cc875c2eSYuval Mintz link->speed.autoneg, link->pause.autoneg); 2586cc875c2eSYuval Mintz 2587fe56b9e6SYuval Mintz /* Read Multi-function information from shmem */ 2588fe56b9e6SYuval Mintz addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2589fe56b9e6SYuval Mintz offsetof(struct nvm_cfg1, glob) + 2590fe56b9e6SYuval Mintz offsetof(struct nvm_cfg1_glob, generic_cont0); 2591fe56b9e6SYuval Mintz 2592fe56b9e6SYuval Mintz generic_cont0 = qed_rd(p_hwfn, p_ptt, addr); 2593fe56b9e6SYuval Mintz 2594fe56b9e6SYuval Mintz mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >> 2595fe56b9e6SYuval Mintz NVM_CFG1_GLOB_MF_MODE_OFFSET; 2596fe56b9e6SYuval Mintz 2597fe56b9e6SYuval Mintz switch (mf_mode) { 2598fe56b9e6SYuval Mintz case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED: 2599fc48b7a6SYuval Mintz p_hwfn->cdev->mf_mode = QED_MF_OVLAN; 2600fe56b9e6SYuval Mintz break; 2601fe56b9e6SYuval Mintz case NVM_CFG1_GLOB_MF_MODE_NPAR1_0: 2602fc48b7a6SYuval Mintz p_hwfn->cdev->mf_mode = QED_MF_NPAR; 2603fe56b9e6SYuval Mintz break; 2604fc48b7a6SYuval Mintz case NVM_CFG1_GLOB_MF_MODE_DEFAULT: 2605fc48b7a6SYuval Mintz p_hwfn->cdev->mf_mode = QED_MF_DEFAULT; 2606fe56b9e6SYuval Mintz break; 2607fe56b9e6SYuval Mintz } 2608fe56b9e6SYuval Mintz DP_INFO(p_hwfn, "Multi function mode is %08x\n", 2609fe56b9e6SYuval Mintz p_hwfn->cdev->mf_mode); 2610fe56b9e6SYuval Mintz 2611fc48b7a6SYuval Mintz /* Read Multi-function information from shmem */ 2612fc48b7a6SYuval Mintz addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2613fc48b7a6SYuval Mintz offsetof(struct nvm_cfg1, glob) + 2614fc48b7a6SYuval Mintz offsetof(struct nvm_cfg1_glob, device_capabilities); 2615fc48b7a6SYuval Mintz 2616fc48b7a6SYuval Mintz device_capabilities = qed_rd(p_hwfn, p_ptt, addr); 2617fc48b7a6SYuval Mintz if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET) 2618fc48b7a6SYuval Mintz __set_bit(QED_DEV_CAP_ETH, 2619fc48b7a6SYuval Mintz &p_hwfn->hw_info.device_capabilities); 26201e128c81SArun Easi if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE) 26211e128c81SArun Easi __set_bit(QED_DEV_CAP_FCOE, 26221e128c81SArun Easi &p_hwfn->hw_info.device_capabilities); 2623c5ac9319SYuval Mintz if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI) 2624c5ac9319SYuval Mintz __set_bit(QED_DEV_CAP_ISCSI, 2625c5ac9319SYuval Mintz &p_hwfn->hw_info.device_capabilities); 2626c5ac9319SYuval Mintz if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE) 2627c5ac9319SYuval Mintz __set_bit(QED_DEV_CAP_ROCE, 2628c5ac9319SYuval Mintz &p_hwfn->hw_info.device_capabilities); 2629fc48b7a6SYuval Mintz 2630fe56b9e6SYuval Mintz return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt); 2631fe56b9e6SYuval Mintz } 2632fe56b9e6SYuval Mintz 26331408cc1fSYuval Mintz static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 26341408cc1fSYuval Mintz { 2635dbb799c3SYuval Mintz u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id; 2636dbb799c3SYuval Mintz u32 reg_function_hide, tmp, eng_mask, low_pfs_mask; 26379c79ddaaSMintz, Yuval struct qed_dev *cdev = p_hwfn->cdev; 26381408cc1fSYuval Mintz 26399c79ddaaSMintz, Yuval num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB; 26401408cc1fSYuval Mintz 26411408cc1fSYuval Mintz /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values 26421408cc1fSYuval Mintz * in the other bits are selected. 26431408cc1fSYuval Mintz * Bits 1-15 are for functions 1-15, respectively, and their value is 26441408cc1fSYuval Mintz * '0' only for enabled functions (function 0 always exists and 26451408cc1fSYuval Mintz * enabled). 26461408cc1fSYuval Mintz * In case of CMT, only the "even" functions are enabled, and thus the 26471408cc1fSYuval Mintz * number of functions for both hwfns is learnt from the same bits. 26481408cc1fSYuval Mintz */ 26491408cc1fSYuval Mintz reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE); 26501408cc1fSYuval Mintz 26511408cc1fSYuval Mintz if (reg_function_hide & 0x1) { 26529c79ddaaSMintz, Yuval if (QED_IS_BB(cdev)) { 26539c79ddaaSMintz, Yuval if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) { 26541408cc1fSYuval Mintz num_funcs = 0; 26551408cc1fSYuval Mintz eng_mask = 0xaaaa; 26561408cc1fSYuval Mintz } else { 26571408cc1fSYuval Mintz num_funcs = 1; 26581408cc1fSYuval Mintz eng_mask = 0x5554; 26591408cc1fSYuval Mintz } 26609c79ddaaSMintz, Yuval } else { 26619c79ddaaSMintz, Yuval num_funcs = 1; 26629c79ddaaSMintz, Yuval eng_mask = 0xfffe; 26639c79ddaaSMintz, Yuval } 26641408cc1fSYuval Mintz 26651408cc1fSYuval Mintz /* Get the number of the enabled functions on the engine */ 26661408cc1fSYuval Mintz tmp = (reg_function_hide ^ 0xffffffff) & eng_mask; 26671408cc1fSYuval Mintz while (tmp) { 26681408cc1fSYuval Mintz if (tmp & 0x1) 26691408cc1fSYuval Mintz num_funcs++; 26701408cc1fSYuval Mintz tmp >>= 0x1; 26711408cc1fSYuval Mintz } 2672dbb799c3SYuval Mintz 2673dbb799c3SYuval Mintz /* Get the PF index within the enabled functions */ 2674dbb799c3SYuval Mintz low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1; 2675dbb799c3SYuval Mintz tmp = reg_function_hide & eng_mask & low_pfs_mask; 2676dbb799c3SYuval Mintz while (tmp) { 2677dbb799c3SYuval Mintz if (tmp & 0x1) 2678dbb799c3SYuval Mintz enabled_func_idx--; 2679dbb799c3SYuval Mintz tmp >>= 0x1; 2680dbb799c3SYuval Mintz } 26811408cc1fSYuval Mintz } 26821408cc1fSYuval Mintz 26831408cc1fSYuval Mintz p_hwfn->num_funcs_on_engine = num_funcs; 2684dbb799c3SYuval Mintz p_hwfn->enabled_func_idx = enabled_func_idx; 26851408cc1fSYuval Mintz 26861408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, 26871408cc1fSYuval Mintz NETIF_MSG_PROBE, 2688525ef5c0SYuval Mintz "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n", 26891408cc1fSYuval Mintz p_hwfn->rel_pf_id, 26901408cc1fSYuval Mintz p_hwfn->abs_pf_id, 2691525ef5c0SYuval Mintz p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine); 26921408cc1fSYuval Mintz } 26931408cc1fSYuval Mintz 26949c79ddaaSMintz, Yuval static void qed_hw_info_port_num_bb(struct qed_hwfn *p_hwfn, 26959c79ddaaSMintz, Yuval struct qed_ptt *p_ptt) 2696fe56b9e6SYuval Mintz { 2697fe56b9e6SYuval Mintz u32 port_mode; 2698fe56b9e6SYuval Mintz 26999c79ddaaSMintz, Yuval port_mode = qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0); 2700fe56b9e6SYuval Mintz 2701fe56b9e6SYuval Mintz if (port_mode < 3) { 270278cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine = 1; 2703fe56b9e6SYuval Mintz } else if (port_mode <= 5) { 270478cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine = 2; 2705fe56b9e6SYuval Mintz } else { 2706fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n", 270778cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine); 2708fe56b9e6SYuval Mintz 270978cea9ffSTomer Tayar /* Default num_ports_in_engine to something */ 271078cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine = 1; 2711fe56b9e6SYuval Mintz } 27129c79ddaaSMintz, Yuval } 27139c79ddaaSMintz, Yuval 27149c79ddaaSMintz, Yuval static void qed_hw_info_port_num_ah(struct qed_hwfn *p_hwfn, 27159c79ddaaSMintz, Yuval struct qed_ptt *p_ptt) 27169c79ddaaSMintz, Yuval { 27179c79ddaaSMintz, Yuval u32 port; 27189c79ddaaSMintz, Yuval int i; 27199c79ddaaSMintz, Yuval 272078cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine = 0; 27219c79ddaaSMintz, Yuval 27229c79ddaaSMintz, Yuval for (i = 0; i < MAX_NUM_PORTS_K2; i++) { 27239c79ddaaSMintz, Yuval port = qed_rd(p_hwfn, p_ptt, 27249c79ddaaSMintz, Yuval CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4)); 27259c79ddaaSMintz, Yuval if (port & 1) 272678cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine++; 27279c79ddaaSMintz, Yuval } 27289c79ddaaSMintz, Yuval 272978cea9ffSTomer Tayar if (!p_hwfn->cdev->num_ports_in_engine) { 27309c79ddaaSMintz, Yuval DP_NOTICE(p_hwfn, "All NIG ports are inactive\n"); 27319c79ddaaSMintz, Yuval 27329c79ddaaSMintz, Yuval /* Default num_ports_in_engine to something */ 273378cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine = 1; 27349c79ddaaSMintz, Yuval } 27359c79ddaaSMintz, Yuval } 27369c79ddaaSMintz, Yuval 27379c79ddaaSMintz, Yuval static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 27389c79ddaaSMintz, Yuval { 27399c79ddaaSMintz, Yuval if (QED_IS_BB(p_hwfn->cdev)) 27409c79ddaaSMintz, Yuval qed_hw_info_port_num_bb(p_hwfn, p_ptt); 27419c79ddaaSMintz, Yuval else 27429c79ddaaSMintz, Yuval qed_hw_info_port_num_ah(p_hwfn, p_ptt); 27439c79ddaaSMintz, Yuval } 27449c79ddaaSMintz, Yuval 27459c79ddaaSMintz, Yuval static int 27469c79ddaaSMintz, Yuval qed_get_hw_info(struct qed_hwfn *p_hwfn, 27479c79ddaaSMintz, Yuval struct qed_ptt *p_ptt, 27489c79ddaaSMintz, Yuval enum qed_pci_personality personality) 27499c79ddaaSMintz, Yuval { 27509c79ddaaSMintz, Yuval int rc; 27519c79ddaaSMintz, Yuval 27529c79ddaaSMintz, Yuval /* Since all information is common, only first hwfns should do this */ 27539c79ddaaSMintz, Yuval if (IS_LEAD_HWFN(p_hwfn)) { 27549c79ddaaSMintz, Yuval rc = qed_iov_hw_info(p_hwfn); 27559c79ddaaSMintz, Yuval if (rc) 27569c79ddaaSMintz, Yuval return rc; 27579c79ddaaSMintz, Yuval } 27589c79ddaaSMintz, Yuval 27599c79ddaaSMintz, Yuval qed_hw_info_port_num(p_hwfn, p_ptt); 2760fe56b9e6SYuval Mintz 2761fe56b9e6SYuval Mintz qed_hw_get_nvm_info(p_hwfn, p_ptt); 2762fe56b9e6SYuval Mintz 2763fe56b9e6SYuval Mintz rc = qed_int_igu_read_cam(p_hwfn, p_ptt); 2764fe56b9e6SYuval Mintz if (rc) 2765fe56b9e6SYuval Mintz return rc; 2766fe56b9e6SYuval Mintz 2767fe56b9e6SYuval Mintz if (qed_mcp_is_init(p_hwfn)) 2768fe56b9e6SYuval Mintz ether_addr_copy(p_hwfn->hw_info.hw_mac_addr, 2769fe56b9e6SYuval Mintz p_hwfn->mcp_info->func_info.mac); 2770fe56b9e6SYuval Mintz else 2771fe56b9e6SYuval Mintz eth_random_addr(p_hwfn->hw_info.hw_mac_addr); 2772fe56b9e6SYuval Mintz 2773fe56b9e6SYuval Mintz if (qed_mcp_is_init(p_hwfn)) { 2774fe56b9e6SYuval Mintz if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET) 2775fe56b9e6SYuval Mintz p_hwfn->hw_info.ovlan = 2776fe56b9e6SYuval Mintz p_hwfn->mcp_info->func_info.ovlan; 2777fe56b9e6SYuval Mintz 2778fe56b9e6SYuval Mintz qed_mcp_cmd_port_init(p_hwfn, p_ptt); 2779fe56b9e6SYuval Mintz } 2780fe56b9e6SYuval Mintz 2781fe56b9e6SYuval Mintz if (qed_mcp_is_init(p_hwfn)) { 2782fe56b9e6SYuval Mintz enum qed_pci_personality protocol; 2783fe56b9e6SYuval Mintz 2784fe56b9e6SYuval Mintz protocol = p_hwfn->mcp_info->func_info.protocol; 2785fe56b9e6SYuval Mintz p_hwfn->hw_info.personality = protocol; 2786fe56b9e6SYuval Mintz } 2787fe56b9e6SYuval Mintz 2788b5a9ee7cSAriel Elior p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2; 2789b5a9ee7cSAriel Elior p_hwfn->hw_info.num_active_tc = 1; 2790b5a9ee7cSAriel Elior 27911408cc1fSYuval Mintz qed_get_num_funcs(p_hwfn, p_ptt); 27921408cc1fSYuval Mintz 27930fefbfbaSSudarsana Kalluru if (qed_mcp_is_init(p_hwfn)) 27940fefbfbaSSudarsana Kalluru p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu; 27950fefbfbaSSudarsana Kalluru 27969c8517c4STomer Tayar return qed_hw_get_resc(p_hwfn, p_ptt); 2797fe56b9e6SYuval Mintz } 2798fe56b9e6SYuval Mintz 279915582962SRahul Verma static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2800fe56b9e6SYuval Mintz { 280115582962SRahul Verma struct qed_dev *cdev = p_hwfn->cdev; 28029c79ddaaSMintz, Yuval u16 device_id_mask; 2803fe56b9e6SYuval Mintz u32 tmp; 2804fe56b9e6SYuval Mintz 2805fc48b7a6SYuval Mintz /* Read Vendor Id / Device Id */ 28061a635e48SYuval Mintz pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id); 28071a635e48SYuval Mintz pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id); 28081a635e48SYuval Mintz 28099c79ddaaSMintz, Yuval /* Determine type */ 28109c79ddaaSMintz, Yuval device_id_mask = cdev->device_id & QED_DEV_ID_MASK; 28119c79ddaaSMintz, Yuval switch (device_id_mask) { 28129c79ddaaSMintz, Yuval case QED_DEV_ID_MASK_BB: 28139c79ddaaSMintz, Yuval cdev->type = QED_DEV_TYPE_BB; 28149c79ddaaSMintz, Yuval break; 28159c79ddaaSMintz, Yuval case QED_DEV_ID_MASK_AH: 28169c79ddaaSMintz, Yuval cdev->type = QED_DEV_TYPE_AH; 28179c79ddaaSMintz, Yuval break; 28189c79ddaaSMintz, Yuval default: 28199c79ddaaSMintz, Yuval DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id); 28209c79ddaaSMintz, Yuval return -EBUSY; 28219c79ddaaSMintz, Yuval } 28229c79ddaaSMintz, Yuval 282315582962SRahul Verma cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM); 282415582962SRahul Verma cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV); 282515582962SRahul Verma 2826fe56b9e6SYuval Mintz MASK_FIELD(CHIP_REV, cdev->chip_rev); 2827fe56b9e6SYuval Mintz 2828fe56b9e6SYuval Mintz /* Learn number of HW-functions */ 282915582962SRahul Verma tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR); 2830fe56b9e6SYuval Mintz 2831fc48b7a6SYuval Mintz if (tmp & (1 << p_hwfn->rel_pf_id)) { 2832fe56b9e6SYuval Mintz DP_NOTICE(cdev->hwfns, "device in CMT mode\n"); 2833fe56b9e6SYuval Mintz cdev->num_hwfns = 2; 2834fe56b9e6SYuval Mintz } else { 2835fe56b9e6SYuval Mintz cdev->num_hwfns = 1; 2836fe56b9e6SYuval Mintz } 2837fe56b9e6SYuval Mintz 283815582962SRahul Verma cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt, 2839fe56b9e6SYuval Mintz MISCS_REG_CHIP_TEST_REG) >> 4; 2840fe56b9e6SYuval Mintz MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id); 284115582962SRahul Verma cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL); 2842fe56b9e6SYuval Mintz MASK_FIELD(CHIP_METAL, cdev->chip_metal); 2843fe56b9e6SYuval Mintz 2844fe56b9e6SYuval Mintz DP_INFO(cdev->hwfns, 28459c79ddaaSMintz, Yuval "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n", 28469c79ddaaSMintz, Yuval QED_IS_BB(cdev) ? "BB" : "AH", 28479c79ddaaSMintz, Yuval 'A' + cdev->chip_rev, 28489c79ddaaSMintz, Yuval (int)cdev->chip_metal, 2849fe56b9e6SYuval Mintz cdev->chip_num, cdev->chip_rev, 2850fe56b9e6SYuval Mintz cdev->chip_bond_id, cdev->chip_metal); 285112e09c69SYuval Mintz 285212e09c69SYuval Mintz return 0; 2853fe56b9e6SYuval Mintz } 2854fe56b9e6SYuval Mintz 2855fe56b9e6SYuval Mintz static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn, 2856fe56b9e6SYuval Mintz void __iomem *p_regview, 2857fe56b9e6SYuval Mintz void __iomem *p_doorbells, 2858fe56b9e6SYuval Mintz enum qed_pci_personality personality) 2859fe56b9e6SYuval Mintz { 2860fe56b9e6SYuval Mintz int rc = 0; 2861fe56b9e6SYuval Mintz 2862fe56b9e6SYuval Mintz /* Split PCI bars evenly between hwfns */ 2863fe56b9e6SYuval Mintz p_hwfn->regview = p_regview; 2864fe56b9e6SYuval Mintz p_hwfn->doorbells = p_doorbells; 2865fe56b9e6SYuval Mintz 28661408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 28671408cc1fSYuval Mintz return qed_vf_hw_prepare(p_hwfn); 28681408cc1fSYuval Mintz 2869fe56b9e6SYuval Mintz /* Validate that chip access is feasible */ 2870fe56b9e6SYuval Mintz if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) { 2871fe56b9e6SYuval Mintz DP_ERR(p_hwfn, 2872fe56b9e6SYuval Mintz "Reading the ME register returns all Fs; Preventing further chip access\n"); 2873fe56b9e6SYuval Mintz return -EINVAL; 2874fe56b9e6SYuval Mintz } 2875fe56b9e6SYuval Mintz 2876fe56b9e6SYuval Mintz get_function_id(p_hwfn); 2877fe56b9e6SYuval Mintz 287812e09c69SYuval Mintz /* Allocate PTT pool */ 287912e09c69SYuval Mintz rc = qed_ptt_pool_alloc(p_hwfn); 28802591c280SJoe Perches if (rc) 2881fe56b9e6SYuval Mintz goto err0; 2882fe56b9e6SYuval Mintz 288312e09c69SYuval Mintz /* Allocate the main PTT */ 288412e09c69SYuval Mintz p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN); 288512e09c69SYuval Mintz 2886fe56b9e6SYuval Mintz /* First hwfn learns basic information, e.g., number of hwfns */ 288712e09c69SYuval Mintz if (!p_hwfn->my_id) { 288815582962SRahul Verma rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt); 28891a635e48SYuval Mintz if (rc) 289012e09c69SYuval Mintz goto err1; 289112e09c69SYuval Mintz } 289212e09c69SYuval Mintz 289312e09c69SYuval Mintz qed_hw_hwfn_prepare(p_hwfn); 2894fe56b9e6SYuval Mintz 2895fe56b9e6SYuval Mintz /* Initialize MCP structure */ 2896fe56b9e6SYuval Mintz rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt); 2897fe56b9e6SYuval Mintz if (rc) { 2898fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed initializing mcp command\n"); 2899fe56b9e6SYuval Mintz goto err1; 2900fe56b9e6SYuval Mintz } 2901fe56b9e6SYuval Mintz 2902fe56b9e6SYuval Mintz /* Read the device configuration information from the HW and SHMEM */ 2903fe56b9e6SYuval Mintz rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality); 2904fe56b9e6SYuval Mintz if (rc) { 2905fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed to get HW information\n"); 2906fe56b9e6SYuval Mintz goto err2; 2907fe56b9e6SYuval Mintz } 2908fe56b9e6SYuval Mintz 290918a69e36SMintz, Yuval /* Sending a mailbox to the MFW should be done after qed_get_hw_info() 291018a69e36SMintz, Yuval * is called as it sets the ports number in an engine. 291118a69e36SMintz, Yuval */ 291218a69e36SMintz, Yuval if (IS_LEAD_HWFN(p_hwfn)) { 291318a69e36SMintz, Yuval rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt); 291418a69e36SMintz, Yuval if (rc) 291518a69e36SMintz, Yuval DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n"); 291618a69e36SMintz, Yuval } 291718a69e36SMintz, Yuval 2918fe56b9e6SYuval Mintz /* Allocate the init RT array and initialize the init-ops engine */ 2919fe56b9e6SYuval Mintz rc = qed_init_alloc(p_hwfn); 29202591c280SJoe Perches if (rc) 2921fe56b9e6SYuval Mintz goto err2; 2922fe56b9e6SYuval Mintz 2923fe56b9e6SYuval Mintz return rc; 2924fe56b9e6SYuval Mintz err2: 292532a47e72SYuval Mintz if (IS_LEAD_HWFN(p_hwfn)) 292632a47e72SYuval Mintz qed_iov_free_hw_info(p_hwfn->cdev); 2927fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 2928fe56b9e6SYuval Mintz err1: 2929fe56b9e6SYuval Mintz qed_hw_hwfn_free(p_hwfn); 2930fe56b9e6SYuval Mintz err0: 2931fe56b9e6SYuval Mintz return rc; 2932fe56b9e6SYuval Mintz } 2933fe56b9e6SYuval Mintz 2934fe56b9e6SYuval Mintz int qed_hw_prepare(struct qed_dev *cdev, 2935fe56b9e6SYuval Mintz int personality) 2936fe56b9e6SYuval Mintz { 2937c78df14eSAriel Elior struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2938c78df14eSAriel Elior int rc; 2939fe56b9e6SYuval Mintz 2940fe56b9e6SYuval Mintz /* Store the precompiled init data ptrs */ 29411408cc1fSYuval Mintz if (IS_PF(cdev)) 2942fe56b9e6SYuval Mintz qed_init_iro_array(cdev); 2943fe56b9e6SYuval Mintz 2944fe56b9e6SYuval Mintz /* Initialize the first hwfn - will learn number of hwfns */ 2945c78df14eSAriel Elior rc = qed_hw_prepare_single(p_hwfn, 2946c78df14eSAriel Elior cdev->regview, 2947fe56b9e6SYuval Mintz cdev->doorbells, personality); 2948fe56b9e6SYuval Mintz if (rc) 2949fe56b9e6SYuval Mintz return rc; 2950fe56b9e6SYuval Mintz 2951c78df14eSAriel Elior personality = p_hwfn->hw_info.personality; 2952fe56b9e6SYuval Mintz 2953fe56b9e6SYuval Mintz /* Initialize the rest of the hwfns */ 2954c78df14eSAriel Elior if (cdev->num_hwfns > 1) { 2955fe56b9e6SYuval Mintz void __iomem *p_regview, *p_doorbell; 2956c78df14eSAriel Elior u8 __iomem *addr; 2957fe56b9e6SYuval Mintz 2958c78df14eSAriel Elior /* adjust bar offset for second engine */ 295915582962SRahul Verma addr = cdev->regview + 296015582962SRahul Verma qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt, 296115582962SRahul Verma BAR_ID_0) / 2; 2962c78df14eSAriel Elior p_regview = addr; 2963c78df14eSAriel Elior 296415582962SRahul Verma addr = cdev->doorbells + 296515582962SRahul Verma qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt, 296615582962SRahul Verma BAR_ID_1) / 2; 2967c78df14eSAriel Elior p_doorbell = addr; 2968c78df14eSAriel Elior 2969c78df14eSAriel Elior /* prepare second hw function */ 2970c78df14eSAriel Elior rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview, 2971fe56b9e6SYuval Mintz p_doorbell, personality); 2972c78df14eSAriel Elior 2973c78df14eSAriel Elior /* in case of error, need to free the previously 2974c78df14eSAriel Elior * initiliazed hwfn 0. 2975c78df14eSAriel Elior */ 2976fe56b9e6SYuval Mintz if (rc) { 29771408cc1fSYuval Mintz if (IS_PF(cdev)) { 2978c78df14eSAriel Elior qed_init_free(p_hwfn); 2979c78df14eSAriel Elior qed_mcp_free(p_hwfn); 2980c78df14eSAriel Elior qed_hw_hwfn_free(p_hwfn); 2981fe56b9e6SYuval Mintz } 2982fe56b9e6SYuval Mintz } 29831408cc1fSYuval Mintz } 2984fe56b9e6SYuval Mintz 2985c78df14eSAriel Elior return rc; 2986fe56b9e6SYuval Mintz } 2987fe56b9e6SYuval Mintz 2988fe56b9e6SYuval Mintz void qed_hw_remove(struct qed_dev *cdev) 2989fe56b9e6SYuval Mintz { 29900fefbfbaSSudarsana Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2991fe56b9e6SYuval Mintz int i; 2992fe56b9e6SYuval Mintz 29930fefbfbaSSudarsana Kalluru if (IS_PF(cdev)) 29940fefbfbaSSudarsana Kalluru qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt, 29950fefbfbaSSudarsana Kalluru QED_OV_DRIVER_STATE_NOT_LOADED); 29960fefbfbaSSudarsana Kalluru 2997fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 2998fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2999fe56b9e6SYuval Mintz 30001408cc1fSYuval Mintz if (IS_VF(cdev)) { 30010b55e27dSYuval Mintz qed_vf_pf_release(p_hwfn); 30021408cc1fSYuval Mintz continue; 30031408cc1fSYuval Mintz } 30041408cc1fSYuval Mintz 3005fe56b9e6SYuval Mintz qed_init_free(p_hwfn); 3006fe56b9e6SYuval Mintz qed_hw_hwfn_free(p_hwfn); 3007fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 3008fe56b9e6SYuval Mintz } 300932a47e72SYuval Mintz 301032a47e72SYuval Mintz qed_iov_free_hw_info(cdev); 3011fe56b9e6SYuval Mintz } 3012fe56b9e6SYuval Mintz 3013a91eb52aSYuval Mintz static void qed_chain_free_next_ptr(struct qed_dev *cdev, 3014a91eb52aSYuval Mintz struct qed_chain *p_chain) 3015a91eb52aSYuval Mintz { 3016a91eb52aSYuval Mintz void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL; 3017a91eb52aSYuval Mintz dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0; 3018a91eb52aSYuval Mintz struct qed_chain_next *p_next; 3019a91eb52aSYuval Mintz u32 size, i; 3020a91eb52aSYuval Mintz 3021a91eb52aSYuval Mintz if (!p_virt) 3022a91eb52aSYuval Mintz return; 3023a91eb52aSYuval Mintz 3024a91eb52aSYuval Mintz size = p_chain->elem_size * p_chain->usable_per_page; 3025a91eb52aSYuval Mintz 3026a91eb52aSYuval Mintz for (i = 0; i < p_chain->page_cnt; i++) { 3027a91eb52aSYuval Mintz if (!p_virt) 3028a91eb52aSYuval Mintz break; 3029a91eb52aSYuval Mintz 3030a91eb52aSYuval Mintz p_next = (struct qed_chain_next *)((u8 *)p_virt + size); 3031a91eb52aSYuval Mintz p_virt_next = p_next->next_virt; 3032a91eb52aSYuval Mintz p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys); 3033a91eb52aSYuval Mintz 3034a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 3035a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, p_virt, p_phys); 3036a91eb52aSYuval Mintz 3037a91eb52aSYuval Mintz p_virt = p_virt_next; 3038a91eb52aSYuval Mintz p_phys = p_phys_next; 3039a91eb52aSYuval Mintz } 3040a91eb52aSYuval Mintz } 3041a91eb52aSYuval Mintz 3042a91eb52aSYuval Mintz static void qed_chain_free_single(struct qed_dev *cdev, 3043a91eb52aSYuval Mintz struct qed_chain *p_chain) 3044a91eb52aSYuval Mintz { 3045a91eb52aSYuval Mintz if (!p_chain->p_virt_addr) 3046a91eb52aSYuval Mintz return; 3047a91eb52aSYuval Mintz 3048a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 3049a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 3050a91eb52aSYuval Mintz p_chain->p_virt_addr, p_chain->p_phys_addr); 3051a91eb52aSYuval Mintz } 3052a91eb52aSYuval Mintz 3053a91eb52aSYuval Mintz static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain) 3054a91eb52aSYuval Mintz { 3055a91eb52aSYuval Mintz void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl; 3056a91eb52aSYuval Mintz u32 page_cnt = p_chain->page_cnt, i, pbl_size; 30576d937acfSMintz, Yuval u8 *p_pbl_virt = p_chain->pbl_sp.p_virt_table; 3058a91eb52aSYuval Mintz 3059a91eb52aSYuval Mintz if (!pp_virt_addr_tbl) 3060a91eb52aSYuval Mintz return; 3061a91eb52aSYuval Mintz 30626d937acfSMintz, Yuval if (!p_pbl_virt) 3063a91eb52aSYuval Mintz goto out; 3064a91eb52aSYuval Mintz 3065a91eb52aSYuval Mintz for (i = 0; i < page_cnt; i++) { 3066a91eb52aSYuval Mintz if (!pp_virt_addr_tbl[i]) 3067a91eb52aSYuval Mintz break; 3068a91eb52aSYuval Mintz 3069a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 3070a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 3071a91eb52aSYuval Mintz pp_virt_addr_tbl[i], 3072a91eb52aSYuval Mintz *(dma_addr_t *)p_pbl_virt); 3073a91eb52aSYuval Mintz 3074a91eb52aSYuval Mintz p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE; 3075a91eb52aSYuval Mintz } 3076a91eb52aSYuval Mintz 3077a91eb52aSYuval Mintz pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; 30781a4a6975SMintz, Yuval 30791a4a6975SMintz, Yuval if (!p_chain->b_external_pbl) 3080a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 3081a91eb52aSYuval Mintz pbl_size, 30826d937acfSMintz, Yuval p_chain->pbl_sp.p_virt_table, 30836d937acfSMintz, Yuval p_chain->pbl_sp.p_phys_table); 3084a91eb52aSYuval Mintz out: 3085a91eb52aSYuval Mintz vfree(p_chain->pbl.pp_virt_addr_tbl); 30861a4a6975SMintz, Yuval p_chain->pbl.pp_virt_addr_tbl = NULL; 3087a91eb52aSYuval Mintz } 3088a91eb52aSYuval Mintz 3089a91eb52aSYuval Mintz void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain) 3090a91eb52aSYuval Mintz { 3091a91eb52aSYuval Mintz switch (p_chain->mode) { 3092a91eb52aSYuval Mintz case QED_CHAIN_MODE_NEXT_PTR: 3093a91eb52aSYuval Mintz qed_chain_free_next_ptr(cdev, p_chain); 3094a91eb52aSYuval Mintz break; 3095a91eb52aSYuval Mintz case QED_CHAIN_MODE_SINGLE: 3096a91eb52aSYuval Mintz qed_chain_free_single(cdev, p_chain); 3097a91eb52aSYuval Mintz break; 3098a91eb52aSYuval Mintz case QED_CHAIN_MODE_PBL: 3099a91eb52aSYuval Mintz qed_chain_free_pbl(cdev, p_chain); 3100a91eb52aSYuval Mintz break; 3101a91eb52aSYuval Mintz } 3102a91eb52aSYuval Mintz } 3103a91eb52aSYuval Mintz 3104a91eb52aSYuval Mintz static int 3105a91eb52aSYuval Mintz qed_chain_alloc_sanity_check(struct qed_dev *cdev, 3106a91eb52aSYuval Mintz enum qed_chain_cnt_type cnt_type, 3107a91eb52aSYuval Mintz size_t elem_size, u32 page_cnt) 3108a91eb52aSYuval Mintz { 3109a91eb52aSYuval Mintz u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt; 3110a91eb52aSYuval Mintz 3111a91eb52aSYuval Mintz /* The actual chain size can be larger than the maximal possible value 3112a91eb52aSYuval Mintz * after rounding up the requested elements number to pages, and after 3113a91eb52aSYuval Mintz * taking into acount the unusuable elements (next-ptr elements). 3114a91eb52aSYuval Mintz * The size of a "u16" chain can be (U16_MAX + 1) since the chain 3115a91eb52aSYuval Mintz * size/capacity fields are of a u32 type. 3116a91eb52aSYuval Mintz */ 3117a91eb52aSYuval Mintz if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 && 31183ef310a7STomer Tayar chain_size > ((u32)U16_MAX + 1)) || 31193ef310a7STomer Tayar (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) { 3120a91eb52aSYuval Mintz DP_NOTICE(cdev, 3121a91eb52aSYuval Mintz "The actual chain size (0x%llx) is larger than the maximal possible value\n", 3122a91eb52aSYuval Mintz chain_size); 3123a91eb52aSYuval Mintz return -EINVAL; 3124a91eb52aSYuval Mintz } 3125a91eb52aSYuval Mintz 3126a91eb52aSYuval Mintz return 0; 3127a91eb52aSYuval Mintz } 3128a91eb52aSYuval Mintz 3129a91eb52aSYuval Mintz static int 3130a91eb52aSYuval Mintz qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain) 3131a91eb52aSYuval Mintz { 3132a91eb52aSYuval Mintz void *p_virt = NULL, *p_virt_prev = NULL; 3133a91eb52aSYuval Mintz dma_addr_t p_phys = 0; 3134a91eb52aSYuval Mintz u32 i; 3135a91eb52aSYuval Mintz 3136a91eb52aSYuval Mintz for (i = 0; i < p_chain->page_cnt; i++) { 3137a91eb52aSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 3138a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 3139a91eb52aSYuval Mintz &p_phys, GFP_KERNEL); 31402591c280SJoe Perches if (!p_virt) 3141a91eb52aSYuval Mintz return -ENOMEM; 3142a91eb52aSYuval Mintz 3143a91eb52aSYuval Mintz if (i == 0) { 3144a91eb52aSYuval Mintz qed_chain_init_mem(p_chain, p_virt, p_phys); 3145a91eb52aSYuval Mintz qed_chain_reset(p_chain); 3146a91eb52aSYuval Mintz } else { 3147a91eb52aSYuval Mintz qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, 3148a91eb52aSYuval Mintz p_virt, p_phys); 3149a91eb52aSYuval Mintz } 3150a91eb52aSYuval Mintz 3151a91eb52aSYuval Mintz p_virt_prev = p_virt; 3152a91eb52aSYuval Mintz } 3153a91eb52aSYuval Mintz /* Last page's next element should point to the beginning of the 3154a91eb52aSYuval Mintz * chain. 3155a91eb52aSYuval Mintz */ 3156a91eb52aSYuval Mintz qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, 3157a91eb52aSYuval Mintz p_chain->p_virt_addr, 3158a91eb52aSYuval Mintz p_chain->p_phys_addr); 3159a91eb52aSYuval Mintz 3160a91eb52aSYuval Mintz return 0; 3161a91eb52aSYuval Mintz } 3162a91eb52aSYuval Mintz 3163a91eb52aSYuval Mintz static int 3164a91eb52aSYuval Mintz qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain) 3165a91eb52aSYuval Mintz { 3166a91eb52aSYuval Mintz dma_addr_t p_phys = 0; 3167a91eb52aSYuval Mintz void *p_virt = NULL; 3168a91eb52aSYuval Mintz 3169a91eb52aSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 3170a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL); 31712591c280SJoe Perches if (!p_virt) 3172a91eb52aSYuval Mintz return -ENOMEM; 3173a91eb52aSYuval Mintz 3174a91eb52aSYuval Mintz qed_chain_init_mem(p_chain, p_virt, p_phys); 3175a91eb52aSYuval Mintz qed_chain_reset(p_chain); 3176a91eb52aSYuval Mintz 3177a91eb52aSYuval Mintz return 0; 3178a91eb52aSYuval Mintz } 3179a91eb52aSYuval Mintz 31801a4a6975SMintz, Yuval static int 31811a4a6975SMintz, Yuval qed_chain_alloc_pbl(struct qed_dev *cdev, 31821a4a6975SMintz, Yuval struct qed_chain *p_chain, 31831a4a6975SMintz, Yuval struct qed_chain_ext_pbl *ext_pbl) 3184a91eb52aSYuval Mintz { 3185a91eb52aSYuval Mintz u32 page_cnt = p_chain->page_cnt, size, i; 3186a91eb52aSYuval Mintz dma_addr_t p_phys = 0, p_pbl_phys = 0; 3187a91eb52aSYuval Mintz void **pp_virt_addr_tbl = NULL; 3188a91eb52aSYuval Mintz u8 *p_pbl_virt = NULL; 3189a91eb52aSYuval Mintz void *p_virt = NULL; 3190a91eb52aSYuval Mintz 3191a91eb52aSYuval Mintz size = page_cnt * sizeof(*pp_virt_addr_tbl); 31922591c280SJoe Perches pp_virt_addr_tbl = vzalloc(size); 31932591c280SJoe Perches if (!pp_virt_addr_tbl) 3194a91eb52aSYuval Mintz return -ENOMEM; 3195a91eb52aSYuval Mintz 3196a91eb52aSYuval Mintz /* The allocation of the PBL table is done with its full size, since it 3197a91eb52aSYuval Mintz * is expected to be successive. 3198a91eb52aSYuval Mintz * qed_chain_init_pbl_mem() is called even in a case of an allocation 3199a91eb52aSYuval Mintz * failure, since pp_virt_addr_tbl was previously allocated, and it 3200a91eb52aSYuval Mintz * should be saved to allow its freeing during the error flow. 3201a91eb52aSYuval Mintz */ 3202a91eb52aSYuval Mintz size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; 32031a4a6975SMintz, Yuval 32041a4a6975SMintz, Yuval if (!ext_pbl) { 3205a91eb52aSYuval Mintz p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev, 3206a91eb52aSYuval Mintz size, &p_pbl_phys, GFP_KERNEL); 32071a4a6975SMintz, Yuval } else { 32081a4a6975SMintz, Yuval p_pbl_virt = ext_pbl->p_pbl_virt; 32091a4a6975SMintz, Yuval p_pbl_phys = ext_pbl->p_pbl_phys; 32101a4a6975SMintz, Yuval p_chain->b_external_pbl = true; 32111a4a6975SMintz, Yuval } 32121a4a6975SMintz, Yuval 3213a91eb52aSYuval Mintz qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys, 3214a91eb52aSYuval Mintz pp_virt_addr_tbl); 32152591c280SJoe Perches if (!p_pbl_virt) 3216a91eb52aSYuval Mintz return -ENOMEM; 3217a91eb52aSYuval Mintz 3218a91eb52aSYuval Mintz for (i = 0; i < page_cnt; i++) { 3219a91eb52aSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 3220a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 3221a91eb52aSYuval Mintz &p_phys, GFP_KERNEL); 32222591c280SJoe Perches if (!p_virt) 3223a91eb52aSYuval Mintz return -ENOMEM; 3224a91eb52aSYuval Mintz 3225a91eb52aSYuval Mintz if (i == 0) { 3226a91eb52aSYuval Mintz qed_chain_init_mem(p_chain, p_virt, p_phys); 3227a91eb52aSYuval Mintz qed_chain_reset(p_chain); 3228a91eb52aSYuval Mintz } 3229a91eb52aSYuval Mintz 3230a91eb52aSYuval Mintz /* Fill the PBL table with the physical address of the page */ 3231a91eb52aSYuval Mintz *(dma_addr_t *)p_pbl_virt = p_phys; 3232a91eb52aSYuval Mintz /* Keep the virtual address of the page */ 3233a91eb52aSYuval Mintz p_chain->pbl.pp_virt_addr_tbl[i] = p_virt; 3234a91eb52aSYuval Mintz 3235a91eb52aSYuval Mintz p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE; 3236a91eb52aSYuval Mintz } 3237a91eb52aSYuval Mintz 3238a91eb52aSYuval Mintz return 0; 3239a91eb52aSYuval Mintz } 3240a91eb52aSYuval Mintz 3241fe56b9e6SYuval Mintz int qed_chain_alloc(struct qed_dev *cdev, 3242fe56b9e6SYuval Mintz enum qed_chain_use_mode intended_use, 3243fe56b9e6SYuval Mintz enum qed_chain_mode mode, 3244a91eb52aSYuval Mintz enum qed_chain_cnt_type cnt_type, 32451a4a6975SMintz, Yuval u32 num_elems, 32461a4a6975SMintz, Yuval size_t elem_size, 32471a4a6975SMintz, Yuval struct qed_chain *p_chain, 32481a4a6975SMintz, Yuval struct qed_chain_ext_pbl *ext_pbl) 3249fe56b9e6SYuval Mintz { 3250a91eb52aSYuval Mintz u32 page_cnt; 3251a91eb52aSYuval Mintz int rc = 0; 3252fe56b9e6SYuval Mintz 3253fe56b9e6SYuval Mintz if (mode == QED_CHAIN_MODE_SINGLE) 3254fe56b9e6SYuval Mintz page_cnt = 1; 3255fe56b9e6SYuval Mintz else 3256fe56b9e6SYuval Mintz page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode); 3257fe56b9e6SYuval Mintz 3258a91eb52aSYuval Mintz rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt); 3259a91eb52aSYuval Mintz if (rc) { 3260a91eb52aSYuval Mintz DP_NOTICE(cdev, 32612591c280SJoe Perches "Cannot allocate a chain with the given arguments:\n"); 32622591c280SJoe Perches DP_NOTICE(cdev, 3263a91eb52aSYuval Mintz "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n", 3264a91eb52aSYuval Mintz intended_use, mode, cnt_type, num_elems, elem_size); 3265a91eb52aSYuval Mintz return rc; 3266fe56b9e6SYuval Mintz } 3267fe56b9e6SYuval Mintz 3268a91eb52aSYuval Mintz qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use, 3269a91eb52aSYuval Mintz mode, cnt_type); 3270fe56b9e6SYuval Mintz 3271a91eb52aSYuval Mintz switch (mode) { 3272a91eb52aSYuval Mintz case QED_CHAIN_MODE_NEXT_PTR: 3273a91eb52aSYuval Mintz rc = qed_chain_alloc_next_ptr(cdev, p_chain); 3274a91eb52aSYuval Mintz break; 3275a91eb52aSYuval Mintz case QED_CHAIN_MODE_SINGLE: 3276a91eb52aSYuval Mintz rc = qed_chain_alloc_single(cdev, p_chain); 3277a91eb52aSYuval Mintz break; 3278a91eb52aSYuval Mintz case QED_CHAIN_MODE_PBL: 32791a4a6975SMintz, Yuval rc = qed_chain_alloc_pbl(cdev, p_chain, ext_pbl); 3280a91eb52aSYuval Mintz break; 3281fe56b9e6SYuval Mintz } 3282a91eb52aSYuval Mintz if (rc) 3283a91eb52aSYuval Mintz goto nomem; 3284fe56b9e6SYuval Mintz 3285fe56b9e6SYuval Mintz return 0; 3286fe56b9e6SYuval Mintz 3287fe56b9e6SYuval Mintz nomem: 3288a91eb52aSYuval Mintz qed_chain_free(cdev, p_chain); 3289a91eb52aSYuval Mintz return rc; 3290fe56b9e6SYuval Mintz } 3291fe56b9e6SYuval Mintz 3292a91eb52aSYuval Mintz int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id) 3293cee4d264SManish Chopra { 3294cee4d264SManish Chopra if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) { 3295cee4d264SManish Chopra u16 min, max; 3296cee4d264SManish Chopra 3297cee4d264SManish Chopra min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE); 3298cee4d264SManish Chopra max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE); 3299cee4d264SManish Chopra DP_NOTICE(p_hwfn, 3300cee4d264SManish Chopra "l2_queue id [%d] is not valid, available indices [%d - %d]\n", 3301cee4d264SManish Chopra src_id, min, max); 3302cee4d264SManish Chopra 3303cee4d264SManish Chopra return -EINVAL; 3304cee4d264SManish Chopra } 3305cee4d264SManish Chopra 3306cee4d264SManish Chopra *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id; 3307cee4d264SManish Chopra 3308cee4d264SManish Chopra return 0; 3309cee4d264SManish Chopra } 3310cee4d264SManish Chopra 33111a635e48SYuval Mintz int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id) 3312cee4d264SManish Chopra { 3313cee4d264SManish Chopra if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) { 3314cee4d264SManish Chopra u8 min, max; 3315cee4d264SManish Chopra 3316cee4d264SManish Chopra min = (u8)RESC_START(p_hwfn, QED_VPORT); 3317cee4d264SManish Chopra max = min + RESC_NUM(p_hwfn, QED_VPORT); 3318cee4d264SManish Chopra DP_NOTICE(p_hwfn, 3319cee4d264SManish Chopra "vport id [%d] is not valid, available indices [%d - %d]\n", 3320cee4d264SManish Chopra src_id, min, max); 3321cee4d264SManish Chopra 3322cee4d264SManish Chopra return -EINVAL; 3323cee4d264SManish Chopra } 3324cee4d264SManish Chopra 3325cee4d264SManish Chopra *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id; 3326cee4d264SManish Chopra 3327cee4d264SManish Chopra return 0; 3328cee4d264SManish Chopra } 3329cee4d264SManish Chopra 33301a635e48SYuval Mintz int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id) 3331cee4d264SManish Chopra { 3332cee4d264SManish Chopra if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) { 3333cee4d264SManish Chopra u8 min, max; 3334cee4d264SManish Chopra 3335cee4d264SManish Chopra min = (u8)RESC_START(p_hwfn, QED_RSS_ENG); 3336cee4d264SManish Chopra max = min + RESC_NUM(p_hwfn, QED_RSS_ENG); 3337cee4d264SManish Chopra DP_NOTICE(p_hwfn, 3338cee4d264SManish Chopra "rss_eng id [%d] is not valid, available indices [%d - %d]\n", 3339cee4d264SManish Chopra src_id, min, max); 3340cee4d264SManish Chopra 3341cee4d264SManish Chopra return -EINVAL; 3342cee4d264SManish Chopra } 3343cee4d264SManish Chopra 3344cee4d264SManish Chopra *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id; 3345cee4d264SManish Chopra 3346cee4d264SManish Chopra return 0; 3347cee4d264SManish Chopra } 3348bcd197c8SManish Chopra 33490a7fb11cSYuval Mintz static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low, 33500a7fb11cSYuval Mintz u8 *p_filter) 33510a7fb11cSYuval Mintz { 33520a7fb11cSYuval Mintz *p_high = p_filter[1] | (p_filter[0] << 8); 33530a7fb11cSYuval Mintz *p_low = p_filter[5] | (p_filter[4] << 8) | 33540a7fb11cSYuval Mintz (p_filter[3] << 16) | (p_filter[2] << 24); 33550a7fb11cSYuval Mintz } 33560a7fb11cSYuval Mintz 33570a7fb11cSYuval Mintz int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn, 33580a7fb11cSYuval Mintz struct qed_ptt *p_ptt, u8 *p_filter) 33590a7fb11cSYuval Mintz { 33600a7fb11cSYuval Mintz u32 high = 0, low = 0, en; 33610a7fb11cSYuval Mintz int i; 33620a7fb11cSYuval Mintz 33630a7fb11cSYuval Mintz if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 33640a7fb11cSYuval Mintz return 0; 33650a7fb11cSYuval Mintz 33660a7fb11cSYuval Mintz qed_llh_mac_to_filter(&high, &low, p_filter); 33670a7fb11cSYuval Mintz 33680a7fb11cSYuval Mintz /* Find a free entry and utilize it */ 33690a7fb11cSYuval Mintz for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 33700a7fb11cSYuval Mintz en = qed_rd(p_hwfn, p_ptt, 33710a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)); 33720a7fb11cSYuval Mintz if (en) 33730a7fb11cSYuval Mintz continue; 33740a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 33750a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 33760a7fb11cSYuval Mintz 2 * i * sizeof(u32), low); 33770a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 33780a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 33790a7fb11cSYuval Mintz (2 * i + 1) * sizeof(u32), high); 33800a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 33810a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0); 33820a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 33830a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 33840a7fb11cSYuval Mintz i * sizeof(u32), 0); 33850a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 33860a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1); 33870a7fb11cSYuval Mintz break; 33880a7fb11cSYuval Mintz } 33890a7fb11cSYuval Mintz if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) { 33900a7fb11cSYuval Mintz DP_NOTICE(p_hwfn, 33910a7fb11cSYuval Mintz "Failed to find an empty LLH filter to utilize\n"); 33920a7fb11cSYuval Mintz return -EINVAL; 33930a7fb11cSYuval Mintz } 33940a7fb11cSYuval Mintz 33950a7fb11cSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 33960a7fb11cSYuval Mintz "mac: %pM is added at %d\n", 33970a7fb11cSYuval Mintz p_filter, i); 33980a7fb11cSYuval Mintz 33990a7fb11cSYuval Mintz return 0; 34000a7fb11cSYuval Mintz } 34010a7fb11cSYuval Mintz 34020a7fb11cSYuval Mintz void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn, 34030a7fb11cSYuval Mintz struct qed_ptt *p_ptt, u8 *p_filter) 34040a7fb11cSYuval Mintz { 34050a7fb11cSYuval Mintz u32 high = 0, low = 0; 34060a7fb11cSYuval Mintz int i; 34070a7fb11cSYuval Mintz 34080a7fb11cSYuval Mintz if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 34090a7fb11cSYuval Mintz return; 34100a7fb11cSYuval Mintz 34110a7fb11cSYuval Mintz qed_llh_mac_to_filter(&high, &low, p_filter); 34120a7fb11cSYuval Mintz 34130a7fb11cSYuval Mintz /* Find the entry and clean it */ 34140a7fb11cSYuval Mintz for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 34150a7fb11cSYuval Mintz if (qed_rd(p_hwfn, p_ptt, 34160a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 34170a7fb11cSYuval Mintz 2 * i * sizeof(u32)) != low) 34180a7fb11cSYuval Mintz continue; 34190a7fb11cSYuval Mintz if (qed_rd(p_hwfn, p_ptt, 34200a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 34210a7fb11cSYuval Mintz (2 * i + 1) * sizeof(u32)) != high) 34220a7fb11cSYuval Mintz continue; 34230a7fb11cSYuval Mintz 34240a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 34250a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0); 34260a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 34270a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0); 34280a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 34290a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 34300a7fb11cSYuval Mintz (2 * i + 1) * sizeof(u32), 0); 34310a7fb11cSYuval Mintz 34320a7fb11cSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 34330a7fb11cSYuval Mintz "mac: %pM is removed from %d\n", 34340a7fb11cSYuval Mintz p_filter, i); 34350a7fb11cSYuval Mintz break; 34360a7fb11cSYuval Mintz } 34370a7fb11cSYuval Mintz if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) 34380a7fb11cSYuval Mintz DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n"); 34390a7fb11cSYuval Mintz } 34400a7fb11cSYuval Mintz 34411e128c81SArun Easi int 34421e128c81SArun Easi qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn, 34431e128c81SArun Easi struct qed_ptt *p_ptt, 34441e128c81SArun Easi u16 source_port_or_eth_type, 34451e128c81SArun Easi u16 dest_port, enum qed_llh_port_filter_type_t type) 34461e128c81SArun Easi { 34471e128c81SArun Easi u32 high = 0, low = 0, en; 34481e128c81SArun Easi int i; 34491e128c81SArun Easi 34501e128c81SArun Easi if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 34511e128c81SArun Easi return 0; 34521e128c81SArun Easi 34531e128c81SArun Easi switch (type) { 34541e128c81SArun Easi case QED_LLH_FILTER_ETHERTYPE: 34551e128c81SArun Easi high = source_port_or_eth_type; 34561e128c81SArun Easi break; 34571e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_PORT: 34581e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_PORT: 34591e128c81SArun Easi low = source_port_or_eth_type << 16; 34601e128c81SArun Easi break; 34611e128c81SArun Easi case QED_LLH_FILTER_TCP_DEST_PORT: 34621e128c81SArun Easi case QED_LLH_FILTER_UDP_DEST_PORT: 34631e128c81SArun Easi low = dest_port; 34641e128c81SArun Easi break; 34651e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 34661e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 34671e128c81SArun Easi low = (source_port_or_eth_type << 16) | dest_port; 34681e128c81SArun Easi break; 34691e128c81SArun Easi default: 34701e128c81SArun Easi DP_NOTICE(p_hwfn, 34711e128c81SArun Easi "Non valid LLH protocol filter type %d\n", type); 34721e128c81SArun Easi return -EINVAL; 34731e128c81SArun Easi } 34741e128c81SArun Easi /* Find a free entry and utilize it */ 34751e128c81SArun Easi for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 34761e128c81SArun Easi en = qed_rd(p_hwfn, p_ptt, 34771e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)); 34781e128c81SArun Easi if (en) 34791e128c81SArun Easi continue; 34801e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 34811e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 34821e128c81SArun Easi 2 * i * sizeof(u32), low); 34831e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 34841e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 34851e128c81SArun Easi (2 * i + 1) * sizeof(u32), high); 34861e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 34871e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1); 34881e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 34891e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 34901e128c81SArun Easi i * sizeof(u32), 1 << type); 34911e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 34921e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1); 34931e128c81SArun Easi break; 34941e128c81SArun Easi } 34951e128c81SArun Easi if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) { 34961e128c81SArun Easi DP_NOTICE(p_hwfn, 34971e128c81SArun Easi "Failed to find an empty LLH filter to utilize\n"); 34981e128c81SArun Easi return -EINVAL; 34991e128c81SArun Easi } 35001e128c81SArun Easi switch (type) { 35011e128c81SArun Easi case QED_LLH_FILTER_ETHERTYPE: 35021e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 35031e128c81SArun Easi "ETH type %x is added at %d\n", 35041e128c81SArun Easi source_port_or_eth_type, i); 35051e128c81SArun Easi break; 35061e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_PORT: 35071e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 35081e128c81SArun Easi "TCP src port %x is added at %d\n", 35091e128c81SArun Easi source_port_or_eth_type, i); 35101e128c81SArun Easi break; 35111e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_PORT: 35121e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 35131e128c81SArun Easi "UDP src port %x is added at %d\n", 35141e128c81SArun Easi source_port_or_eth_type, i); 35151e128c81SArun Easi break; 35161e128c81SArun Easi case QED_LLH_FILTER_TCP_DEST_PORT: 35171e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 35181e128c81SArun Easi "TCP dst port %x is added at %d\n", dest_port, i); 35191e128c81SArun Easi break; 35201e128c81SArun Easi case QED_LLH_FILTER_UDP_DEST_PORT: 35211e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 35221e128c81SArun Easi "UDP dst port %x is added at %d\n", dest_port, i); 35231e128c81SArun Easi break; 35241e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 35251e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 35261e128c81SArun Easi "TCP src/dst ports %x/%x are added at %d\n", 35271e128c81SArun Easi source_port_or_eth_type, dest_port, i); 35281e128c81SArun Easi break; 35291e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 35301e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 35311e128c81SArun Easi "UDP src/dst ports %x/%x are added at %d\n", 35321e128c81SArun Easi source_port_or_eth_type, dest_port, i); 35331e128c81SArun Easi break; 35341e128c81SArun Easi } 35351e128c81SArun Easi return 0; 35361e128c81SArun Easi } 35371e128c81SArun Easi 35381e128c81SArun Easi void 35391e128c81SArun Easi qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn, 35401e128c81SArun Easi struct qed_ptt *p_ptt, 35411e128c81SArun Easi u16 source_port_or_eth_type, 35421e128c81SArun Easi u16 dest_port, 35431e128c81SArun Easi enum qed_llh_port_filter_type_t type) 35441e128c81SArun Easi { 35451e128c81SArun Easi u32 high = 0, low = 0; 35461e128c81SArun Easi int i; 35471e128c81SArun Easi 35481e128c81SArun Easi if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 35491e128c81SArun Easi return; 35501e128c81SArun Easi 35511e128c81SArun Easi switch (type) { 35521e128c81SArun Easi case QED_LLH_FILTER_ETHERTYPE: 35531e128c81SArun Easi high = source_port_or_eth_type; 35541e128c81SArun Easi break; 35551e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_PORT: 35561e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_PORT: 35571e128c81SArun Easi low = source_port_or_eth_type << 16; 35581e128c81SArun Easi break; 35591e128c81SArun Easi case QED_LLH_FILTER_TCP_DEST_PORT: 35601e128c81SArun Easi case QED_LLH_FILTER_UDP_DEST_PORT: 35611e128c81SArun Easi low = dest_port; 35621e128c81SArun Easi break; 35631e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 35641e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 35651e128c81SArun Easi low = (source_port_or_eth_type << 16) | dest_port; 35661e128c81SArun Easi break; 35671e128c81SArun Easi default: 35681e128c81SArun Easi DP_NOTICE(p_hwfn, 35691e128c81SArun Easi "Non valid LLH protocol filter type %d\n", type); 35701e128c81SArun Easi return; 35711e128c81SArun Easi } 35721e128c81SArun Easi 35731e128c81SArun Easi for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 35741e128c81SArun Easi if (!qed_rd(p_hwfn, p_ptt, 35751e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32))) 35761e128c81SArun Easi continue; 35771e128c81SArun Easi if (!qed_rd(p_hwfn, p_ptt, 35781e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32))) 35791e128c81SArun Easi continue; 35801e128c81SArun Easi if (!(qed_rd(p_hwfn, p_ptt, 35811e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 35821e128c81SArun Easi i * sizeof(u32)) & BIT(type))) 35831e128c81SArun Easi continue; 35841e128c81SArun Easi if (qed_rd(p_hwfn, p_ptt, 35851e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 35861e128c81SArun Easi 2 * i * sizeof(u32)) != low) 35871e128c81SArun Easi continue; 35881e128c81SArun Easi if (qed_rd(p_hwfn, p_ptt, 35891e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 35901e128c81SArun Easi (2 * i + 1) * sizeof(u32)) != high) 35911e128c81SArun Easi continue; 35921e128c81SArun Easi 35931e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 35941e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0); 35951e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 35961e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0); 35971e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 35981e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 35991e128c81SArun Easi i * sizeof(u32), 0); 36001e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 36011e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0); 36021e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 36031e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 36041e128c81SArun Easi (2 * i + 1) * sizeof(u32), 0); 36051e128c81SArun Easi break; 36061e128c81SArun Easi } 36071e128c81SArun Easi 36081e128c81SArun Easi if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) 36091e128c81SArun Easi DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n"); 36101e128c81SArun Easi } 36111e128c81SArun Easi 3612722003acSSudarsana Reddy Kalluru static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 3613722003acSSudarsana Reddy Kalluru u32 hw_addr, void *p_eth_qzone, 3614722003acSSudarsana Reddy Kalluru size_t eth_qzone_size, u8 timeset) 3615722003acSSudarsana Reddy Kalluru { 3616722003acSSudarsana Reddy Kalluru struct coalescing_timeset *p_coal_timeset; 3617722003acSSudarsana Reddy Kalluru 3618722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) { 3619722003acSSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n"); 3620722003acSSudarsana Reddy Kalluru return -EINVAL; 3621722003acSSudarsana Reddy Kalluru } 3622722003acSSudarsana Reddy Kalluru 3623722003acSSudarsana Reddy Kalluru p_coal_timeset = p_eth_qzone; 3624722003acSSudarsana Reddy Kalluru memset(p_coal_timeset, 0, eth_qzone_size); 3625722003acSSudarsana Reddy Kalluru SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset); 3626722003acSSudarsana Reddy Kalluru SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1); 3627722003acSSudarsana Reddy Kalluru qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size); 3628722003acSSudarsana Reddy Kalluru 3629722003acSSudarsana Reddy Kalluru return 0; 3630722003acSSudarsana Reddy Kalluru } 3631722003acSSudarsana Reddy Kalluru 3632722003acSSudarsana Reddy Kalluru int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 3633f870a3c6Ssudarsana.kalluru@cavium.com u16 coalesce, u16 qid, u16 sb_id) 3634722003acSSudarsana Reddy Kalluru { 3635722003acSSudarsana Reddy Kalluru struct ustorm_eth_queue_zone eth_qzone; 3636722003acSSudarsana Reddy Kalluru u8 timeset, timer_res; 3637722003acSSudarsana Reddy Kalluru u16 fw_qid = 0; 3638722003acSSudarsana Reddy Kalluru u32 address; 3639722003acSSudarsana Reddy Kalluru int rc; 3640722003acSSudarsana Reddy Kalluru 3641722003acSSudarsana Reddy Kalluru /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 3642722003acSSudarsana Reddy Kalluru if (coalesce <= 0x7F) { 3643722003acSSudarsana Reddy Kalluru timer_res = 0; 3644722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0xFF) { 3645722003acSSudarsana Reddy Kalluru timer_res = 1; 3646722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0x1FF) { 3647722003acSSudarsana Reddy Kalluru timer_res = 2; 3648722003acSSudarsana Reddy Kalluru } else { 3649722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 3650722003acSSudarsana Reddy Kalluru return -EINVAL; 3651722003acSSudarsana Reddy Kalluru } 3652722003acSSudarsana Reddy Kalluru timeset = (u8)(coalesce >> timer_res); 3653722003acSSudarsana Reddy Kalluru 3654f870a3c6Ssudarsana.kalluru@cavium.com rc = qed_fw_l2_queue(p_hwfn, qid, &fw_qid); 3655722003acSSudarsana Reddy Kalluru if (rc) 3656722003acSSudarsana Reddy Kalluru return rc; 3657722003acSSudarsana Reddy Kalluru 3658722003acSSudarsana Reddy Kalluru rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false); 3659722003acSSudarsana Reddy Kalluru if (rc) 3660722003acSSudarsana Reddy Kalluru goto out; 3661722003acSSudarsana Reddy Kalluru 3662722003acSSudarsana Reddy Kalluru address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid); 3663722003acSSudarsana Reddy Kalluru 3664722003acSSudarsana Reddy Kalluru rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 3665722003acSSudarsana Reddy Kalluru sizeof(struct ustorm_eth_queue_zone), timeset); 3666722003acSSudarsana Reddy Kalluru if (rc) 3667722003acSSudarsana Reddy Kalluru goto out; 3668722003acSSudarsana Reddy Kalluru 3669722003acSSudarsana Reddy Kalluru p_hwfn->cdev->rx_coalesce_usecs = coalesce; 3670722003acSSudarsana Reddy Kalluru out: 3671722003acSSudarsana Reddy Kalluru return rc; 3672722003acSSudarsana Reddy Kalluru } 3673722003acSSudarsana Reddy Kalluru 3674722003acSSudarsana Reddy Kalluru int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 3675f870a3c6Ssudarsana.kalluru@cavium.com u16 coalesce, u16 qid, u16 sb_id) 3676722003acSSudarsana Reddy Kalluru { 3677722003acSSudarsana Reddy Kalluru struct xstorm_eth_queue_zone eth_qzone; 3678722003acSSudarsana Reddy Kalluru u8 timeset, timer_res; 3679722003acSSudarsana Reddy Kalluru u16 fw_qid = 0; 3680722003acSSudarsana Reddy Kalluru u32 address; 3681722003acSSudarsana Reddy Kalluru int rc; 3682722003acSSudarsana Reddy Kalluru 3683722003acSSudarsana Reddy Kalluru /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 3684722003acSSudarsana Reddy Kalluru if (coalesce <= 0x7F) { 3685722003acSSudarsana Reddy Kalluru timer_res = 0; 3686722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0xFF) { 3687722003acSSudarsana Reddy Kalluru timer_res = 1; 3688722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0x1FF) { 3689722003acSSudarsana Reddy Kalluru timer_res = 2; 3690722003acSSudarsana Reddy Kalluru } else { 3691722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 3692722003acSSudarsana Reddy Kalluru return -EINVAL; 3693722003acSSudarsana Reddy Kalluru } 3694722003acSSudarsana Reddy Kalluru timeset = (u8)(coalesce >> timer_res); 3695722003acSSudarsana Reddy Kalluru 3696f870a3c6Ssudarsana.kalluru@cavium.com rc = qed_fw_l2_queue(p_hwfn, qid, &fw_qid); 3697722003acSSudarsana Reddy Kalluru if (rc) 3698722003acSSudarsana Reddy Kalluru return rc; 3699722003acSSudarsana Reddy Kalluru 3700722003acSSudarsana Reddy Kalluru rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true); 3701722003acSSudarsana Reddy Kalluru if (rc) 3702722003acSSudarsana Reddy Kalluru goto out; 3703722003acSSudarsana Reddy Kalluru 3704722003acSSudarsana Reddy Kalluru address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid); 3705722003acSSudarsana Reddy Kalluru 3706722003acSSudarsana Reddy Kalluru rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 3707722003acSSudarsana Reddy Kalluru sizeof(struct xstorm_eth_queue_zone), timeset); 3708722003acSSudarsana Reddy Kalluru if (rc) 3709722003acSSudarsana Reddy Kalluru goto out; 3710722003acSSudarsana Reddy Kalluru 3711722003acSSudarsana Reddy Kalluru p_hwfn->cdev->tx_coalesce_usecs = coalesce; 3712722003acSSudarsana Reddy Kalluru out: 3713722003acSSudarsana Reddy Kalluru return rc; 3714722003acSSudarsana Reddy Kalluru } 3715722003acSSudarsana Reddy Kalluru 3716bcd197c8SManish Chopra /* Calculate final WFQ values for all vports and configure them. 3717bcd197c8SManish Chopra * After this configuration each vport will have 3718bcd197c8SManish Chopra * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT) 3719bcd197c8SManish Chopra */ 3720bcd197c8SManish Chopra static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 3721bcd197c8SManish Chopra struct qed_ptt *p_ptt, 3722bcd197c8SManish Chopra u32 min_pf_rate) 3723bcd197c8SManish Chopra { 3724bcd197c8SManish Chopra struct init_qm_vport_params *vport_params; 3725bcd197c8SManish Chopra int i; 3726bcd197c8SManish Chopra 3727bcd197c8SManish Chopra vport_params = p_hwfn->qm_info.qm_vport_params; 3728bcd197c8SManish Chopra 3729bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 3730bcd197c8SManish Chopra u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 3731bcd197c8SManish Chopra 3732bcd197c8SManish Chopra vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) / 3733bcd197c8SManish Chopra min_pf_rate; 3734bcd197c8SManish Chopra qed_init_vport_wfq(p_hwfn, p_ptt, 3735bcd197c8SManish Chopra vport_params[i].first_tx_pq_id, 3736bcd197c8SManish Chopra vport_params[i].vport_wfq); 3737bcd197c8SManish Chopra } 3738bcd197c8SManish Chopra } 3739bcd197c8SManish Chopra 3740bcd197c8SManish Chopra static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn, 3741bcd197c8SManish Chopra u32 min_pf_rate) 3742bcd197c8SManish Chopra 3743bcd197c8SManish Chopra { 3744bcd197c8SManish Chopra int i; 3745bcd197c8SManish Chopra 3746bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) 3747bcd197c8SManish Chopra p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1; 3748bcd197c8SManish Chopra } 3749bcd197c8SManish Chopra 3750bcd197c8SManish Chopra static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 3751bcd197c8SManish Chopra struct qed_ptt *p_ptt, 3752bcd197c8SManish Chopra u32 min_pf_rate) 3753bcd197c8SManish Chopra { 3754bcd197c8SManish Chopra struct init_qm_vport_params *vport_params; 3755bcd197c8SManish Chopra int i; 3756bcd197c8SManish Chopra 3757bcd197c8SManish Chopra vport_params = p_hwfn->qm_info.qm_vport_params; 3758bcd197c8SManish Chopra 3759bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 3760bcd197c8SManish Chopra qed_init_wfq_default_param(p_hwfn, min_pf_rate); 3761bcd197c8SManish Chopra qed_init_vport_wfq(p_hwfn, p_ptt, 3762bcd197c8SManish Chopra vport_params[i].first_tx_pq_id, 3763bcd197c8SManish Chopra vport_params[i].vport_wfq); 3764bcd197c8SManish Chopra } 3765bcd197c8SManish Chopra } 3766bcd197c8SManish Chopra 3767bcd197c8SManish Chopra /* This function performs several validations for WFQ 3768bcd197c8SManish Chopra * configuration and required min rate for a given vport 3769bcd197c8SManish Chopra * 1. req_rate must be greater than one percent of min_pf_rate. 3770bcd197c8SManish Chopra * 2. req_rate should not cause other vports [not configured for WFQ explicitly] 3771bcd197c8SManish Chopra * rates to get less than one percent of min_pf_rate. 3772bcd197c8SManish Chopra * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate. 3773bcd197c8SManish Chopra */ 3774bcd197c8SManish Chopra static int qed_init_wfq_param(struct qed_hwfn *p_hwfn, 37751a635e48SYuval Mintz u16 vport_id, u32 req_rate, u32 min_pf_rate) 3776bcd197c8SManish Chopra { 3777bcd197c8SManish Chopra u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0; 3778bcd197c8SManish Chopra int non_requested_count = 0, req_count = 0, i, num_vports; 3779bcd197c8SManish Chopra 3780bcd197c8SManish Chopra num_vports = p_hwfn->qm_info.num_vports; 3781bcd197c8SManish Chopra 3782bcd197c8SManish Chopra /* Accounting for the vports which are configured for WFQ explicitly */ 3783bcd197c8SManish Chopra for (i = 0; i < num_vports; i++) { 3784bcd197c8SManish Chopra u32 tmp_speed; 3785bcd197c8SManish Chopra 3786bcd197c8SManish Chopra if ((i != vport_id) && 3787bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[i].configured) { 3788bcd197c8SManish Chopra req_count++; 3789bcd197c8SManish Chopra tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 3790bcd197c8SManish Chopra total_req_min_rate += tmp_speed; 3791bcd197c8SManish Chopra } 3792bcd197c8SManish Chopra } 3793bcd197c8SManish Chopra 3794bcd197c8SManish Chopra /* Include current vport data as well */ 3795bcd197c8SManish Chopra req_count++; 3796bcd197c8SManish Chopra total_req_min_rate += req_rate; 3797bcd197c8SManish Chopra non_requested_count = num_vports - req_count; 3798bcd197c8SManish Chopra 3799bcd197c8SManish Chopra if (req_rate < min_pf_rate / QED_WFQ_UNIT) { 3800bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 3801bcd197c8SManish Chopra "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 3802bcd197c8SManish Chopra vport_id, req_rate, min_pf_rate); 3803bcd197c8SManish Chopra return -EINVAL; 3804bcd197c8SManish Chopra } 3805bcd197c8SManish Chopra 3806bcd197c8SManish Chopra if (num_vports > QED_WFQ_UNIT) { 3807bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 3808bcd197c8SManish Chopra "Number of vports is greater than %d\n", 3809bcd197c8SManish Chopra QED_WFQ_UNIT); 3810bcd197c8SManish Chopra return -EINVAL; 3811bcd197c8SManish Chopra } 3812bcd197c8SManish Chopra 3813bcd197c8SManish Chopra if (total_req_min_rate > min_pf_rate) { 3814bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 3815bcd197c8SManish Chopra "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n", 3816bcd197c8SManish Chopra total_req_min_rate, min_pf_rate); 3817bcd197c8SManish Chopra return -EINVAL; 3818bcd197c8SManish Chopra } 3819bcd197c8SManish Chopra 3820bcd197c8SManish Chopra total_left_rate = min_pf_rate - total_req_min_rate; 3821bcd197c8SManish Chopra 3822bcd197c8SManish Chopra left_rate_per_vp = total_left_rate / non_requested_count; 3823bcd197c8SManish Chopra if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) { 3824bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 3825bcd197c8SManish Chopra "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 3826bcd197c8SManish Chopra left_rate_per_vp, min_pf_rate); 3827bcd197c8SManish Chopra return -EINVAL; 3828bcd197c8SManish Chopra } 3829bcd197c8SManish Chopra 3830bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate; 3831bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[vport_id].configured = true; 3832bcd197c8SManish Chopra 3833bcd197c8SManish Chopra for (i = 0; i < num_vports; i++) { 3834bcd197c8SManish Chopra if (p_hwfn->qm_info.wfq_data[i].configured) 3835bcd197c8SManish Chopra continue; 3836bcd197c8SManish Chopra 3837bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp; 3838bcd197c8SManish Chopra } 3839bcd197c8SManish Chopra 3840bcd197c8SManish Chopra return 0; 3841bcd197c8SManish Chopra } 3842bcd197c8SManish Chopra 3843733def6aSYuval Mintz static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn, 3844733def6aSYuval Mintz struct qed_ptt *p_ptt, u16 vp_id, u32 rate) 3845733def6aSYuval Mintz { 3846733def6aSYuval Mintz struct qed_mcp_link_state *p_link; 3847733def6aSYuval Mintz int rc = 0; 3848733def6aSYuval Mintz 3849733def6aSYuval Mintz p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output; 3850733def6aSYuval Mintz 3851733def6aSYuval Mintz if (!p_link->min_pf_rate) { 3852733def6aSYuval Mintz p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate; 3853733def6aSYuval Mintz p_hwfn->qm_info.wfq_data[vp_id].configured = true; 3854733def6aSYuval Mintz return rc; 3855733def6aSYuval Mintz } 3856733def6aSYuval Mintz 3857733def6aSYuval Mintz rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate); 3858733def6aSYuval Mintz 38591a635e48SYuval Mintz if (!rc) 3860733def6aSYuval Mintz qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, 3861733def6aSYuval Mintz p_link->min_pf_rate); 3862733def6aSYuval Mintz else 3863733def6aSYuval Mintz DP_NOTICE(p_hwfn, 3864733def6aSYuval Mintz "Validation failed while configuring min rate\n"); 3865733def6aSYuval Mintz 3866733def6aSYuval Mintz return rc; 3867733def6aSYuval Mintz } 3868733def6aSYuval Mintz 3869bcd197c8SManish Chopra static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn, 3870bcd197c8SManish Chopra struct qed_ptt *p_ptt, 3871bcd197c8SManish Chopra u32 min_pf_rate) 3872bcd197c8SManish Chopra { 3873bcd197c8SManish Chopra bool use_wfq = false; 3874bcd197c8SManish Chopra int rc = 0; 3875bcd197c8SManish Chopra u16 i; 3876bcd197c8SManish Chopra 3877bcd197c8SManish Chopra /* Validate all pre configured vports for wfq */ 3878bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 3879bcd197c8SManish Chopra u32 rate; 3880bcd197c8SManish Chopra 3881bcd197c8SManish Chopra if (!p_hwfn->qm_info.wfq_data[i].configured) 3882bcd197c8SManish Chopra continue; 3883bcd197c8SManish Chopra 3884bcd197c8SManish Chopra rate = p_hwfn->qm_info.wfq_data[i].min_speed; 3885bcd197c8SManish Chopra use_wfq = true; 3886bcd197c8SManish Chopra 3887bcd197c8SManish Chopra rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate); 3888bcd197c8SManish Chopra if (rc) { 3889bcd197c8SManish Chopra DP_NOTICE(p_hwfn, 3890bcd197c8SManish Chopra "WFQ validation failed while configuring min rate\n"); 3891bcd197c8SManish Chopra break; 3892bcd197c8SManish Chopra } 3893bcd197c8SManish Chopra } 3894bcd197c8SManish Chopra 3895bcd197c8SManish Chopra if (!rc && use_wfq) 3896bcd197c8SManish Chopra qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 3897bcd197c8SManish Chopra else 3898bcd197c8SManish Chopra qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 3899bcd197c8SManish Chopra 3900bcd197c8SManish Chopra return rc; 3901bcd197c8SManish Chopra } 3902bcd197c8SManish Chopra 3903733def6aSYuval Mintz /* Main API for qed clients to configure vport min rate. 3904733def6aSYuval Mintz * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)] 3905733def6aSYuval Mintz * rate - Speed in Mbps needs to be assigned to a given vport. 3906733def6aSYuval Mintz */ 3907733def6aSYuval Mintz int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate) 3908733def6aSYuval Mintz { 3909733def6aSYuval Mintz int i, rc = -EINVAL; 3910733def6aSYuval Mintz 3911733def6aSYuval Mintz /* Currently not supported; Might change in future */ 3912733def6aSYuval Mintz if (cdev->num_hwfns > 1) { 3913733def6aSYuval Mintz DP_NOTICE(cdev, 3914733def6aSYuval Mintz "WFQ configuration is not supported for this device\n"); 3915733def6aSYuval Mintz return rc; 3916733def6aSYuval Mintz } 3917733def6aSYuval Mintz 3918733def6aSYuval Mintz for_each_hwfn(cdev, i) { 3919733def6aSYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 3920733def6aSYuval Mintz struct qed_ptt *p_ptt; 3921733def6aSYuval Mintz 3922733def6aSYuval Mintz p_ptt = qed_ptt_acquire(p_hwfn); 3923733def6aSYuval Mintz if (!p_ptt) 3924733def6aSYuval Mintz return -EBUSY; 3925733def6aSYuval Mintz 3926733def6aSYuval Mintz rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate); 3927733def6aSYuval Mintz 3928d572c430SYuval Mintz if (rc) { 3929733def6aSYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 3930733def6aSYuval Mintz return rc; 3931733def6aSYuval Mintz } 3932733def6aSYuval Mintz 3933733def6aSYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 3934733def6aSYuval Mintz } 3935733def6aSYuval Mintz 3936733def6aSYuval Mintz return rc; 3937733def6aSYuval Mintz } 3938733def6aSYuval Mintz 3939bcd197c8SManish Chopra /* API to configure WFQ from mcp link change */ 39406f437d43SMintz, Yuval void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, 39416f437d43SMintz, Yuval struct qed_ptt *p_ptt, u32 min_pf_rate) 3942bcd197c8SManish Chopra { 3943bcd197c8SManish Chopra int i; 3944bcd197c8SManish Chopra 39453e7cfce2SYuval Mintz if (cdev->num_hwfns > 1) { 39463e7cfce2SYuval Mintz DP_VERBOSE(cdev, 39473e7cfce2SYuval Mintz NETIF_MSG_LINK, 39483e7cfce2SYuval Mintz "WFQ configuration is not supported for this device\n"); 39493e7cfce2SYuval Mintz return; 39503e7cfce2SYuval Mintz } 39513e7cfce2SYuval Mintz 3952bcd197c8SManish Chopra for_each_hwfn(cdev, i) { 3953bcd197c8SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 3954bcd197c8SManish Chopra 39556f437d43SMintz, Yuval __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt, 3956bcd197c8SManish Chopra min_pf_rate); 3957bcd197c8SManish Chopra } 3958bcd197c8SManish Chopra } 39594b01e519SManish Chopra 39604b01e519SManish Chopra int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn, 39614b01e519SManish Chopra struct qed_ptt *p_ptt, 39624b01e519SManish Chopra struct qed_mcp_link_state *p_link, 39634b01e519SManish Chopra u8 max_bw) 39644b01e519SManish Chopra { 39654b01e519SManish Chopra int rc = 0; 39664b01e519SManish Chopra 39674b01e519SManish Chopra p_hwfn->mcp_info->func_info.bandwidth_max = max_bw; 39684b01e519SManish Chopra 39694b01e519SManish Chopra if (!p_link->line_speed && (max_bw != 100)) 39704b01e519SManish Chopra return rc; 39714b01e519SManish Chopra 39724b01e519SManish Chopra p_link->speed = (p_link->line_speed * max_bw) / 100; 39734b01e519SManish Chopra p_hwfn->qm_info.pf_rl = p_link->speed; 39744b01e519SManish Chopra 39754b01e519SManish Chopra /* Since the limiter also affects Tx-switched traffic, we don't want it 39764b01e519SManish Chopra * to limit such traffic in case there's no actual limit. 39774b01e519SManish Chopra * In that case, set limit to imaginary high boundary. 39784b01e519SManish Chopra */ 39794b01e519SManish Chopra if (max_bw == 100) 39804b01e519SManish Chopra p_hwfn->qm_info.pf_rl = 100000; 39814b01e519SManish Chopra 39824b01e519SManish Chopra rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, 39834b01e519SManish Chopra p_hwfn->qm_info.pf_rl); 39844b01e519SManish Chopra 39854b01e519SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 39864b01e519SManish Chopra "Configured MAX bandwidth to be %08x Mb/sec\n", 39874b01e519SManish Chopra p_link->speed); 39884b01e519SManish Chopra 39894b01e519SManish Chopra return rc; 39904b01e519SManish Chopra } 39914b01e519SManish Chopra 39924b01e519SManish Chopra /* Main API to configure PF max bandwidth where bw range is [1 - 100] */ 39934b01e519SManish Chopra int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw) 39944b01e519SManish Chopra { 39954b01e519SManish Chopra int i, rc = -EINVAL; 39964b01e519SManish Chopra 39974b01e519SManish Chopra if (max_bw < 1 || max_bw > 100) { 39984b01e519SManish Chopra DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n"); 39994b01e519SManish Chopra return rc; 40004b01e519SManish Chopra } 40014b01e519SManish Chopra 40024b01e519SManish Chopra for_each_hwfn(cdev, i) { 40034b01e519SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 40044b01e519SManish Chopra struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 40054b01e519SManish Chopra struct qed_mcp_link_state *p_link; 40064b01e519SManish Chopra struct qed_ptt *p_ptt; 40074b01e519SManish Chopra 40084b01e519SManish Chopra p_link = &p_lead->mcp_info->link_output; 40094b01e519SManish Chopra 40104b01e519SManish Chopra p_ptt = qed_ptt_acquire(p_hwfn); 40114b01e519SManish Chopra if (!p_ptt) 40124b01e519SManish Chopra return -EBUSY; 40134b01e519SManish Chopra 40144b01e519SManish Chopra rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, 40154b01e519SManish Chopra p_link, max_bw); 40164b01e519SManish Chopra 40174b01e519SManish Chopra qed_ptt_release(p_hwfn, p_ptt); 40184b01e519SManish Chopra 40194b01e519SManish Chopra if (rc) 40204b01e519SManish Chopra break; 40214b01e519SManish Chopra } 40224b01e519SManish Chopra 40234b01e519SManish Chopra return rc; 40244b01e519SManish Chopra } 4025a64b02d5SManish Chopra 4026a64b02d5SManish Chopra int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn, 4027a64b02d5SManish Chopra struct qed_ptt *p_ptt, 4028a64b02d5SManish Chopra struct qed_mcp_link_state *p_link, 4029a64b02d5SManish Chopra u8 min_bw) 4030a64b02d5SManish Chopra { 4031a64b02d5SManish Chopra int rc = 0; 4032a64b02d5SManish Chopra 4033a64b02d5SManish Chopra p_hwfn->mcp_info->func_info.bandwidth_min = min_bw; 4034a64b02d5SManish Chopra p_hwfn->qm_info.pf_wfq = min_bw; 4035a64b02d5SManish Chopra 4036a64b02d5SManish Chopra if (!p_link->line_speed) 4037a64b02d5SManish Chopra return rc; 4038a64b02d5SManish Chopra 4039a64b02d5SManish Chopra p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100; 4040a64b02d5SManish Chopra 4041a64b02d5SManish Chopra rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw); 4042a64b02d5SManish Chopra 4043a64b02d5SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 4044a64b02d5SManish Chopra "Configured MIN bandwidth to be %d Mb/sec\n", 4045a64b02d5SManish Chopra p_link->min_pf_rate); 4046a64b02d5SManish Chopra 4047a64b02d5SManish Chopra return rc; 4048a64b02d5SManish Chopra } 4049a64b02d5SManish Chopra 4050a64b02d5SManish Chopra /* Main API to configure PF min bandwidth where bw range is [1-100] */ 4051a64b02d5SManish Chopra int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw) 4052a64b02d5SManish Chopra { 4053a64b02d5SManish Chopra int i, rc = -EINVAL; 4054a64b02d5SManish Chopra 4055a64b02d5SManish Chopra if (min_bw < 1 || min_bw > 100) { 4056a64b02d5SManish Chopra DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n"); 4057a64b02d5SManish Chopra return rc; 4058a64b02d5SManish Chopra } 4059a64b02d5SManish Chopra 4060a64b02d5SManish Chopra for_each_hwfn(cdev, i) { 4061a64b02d5SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 4062a64b02d5SManish Chopra struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 4063a64b02d5SManish Chopra struct qed_mcp_link_state *p_link; 4064a64b02d5SManish Chopra struct qed_ptt *p_ptt; 4065a64b02d5SManish Chopra 4066a64b02d5SManish Chopra p_link = &p_lead->mcp_info->link_output; 4067a64b02d5SManish Chopra 4068a64b02d5SManish Chopra p_ptt = qed_ptt_acquire(p_hwfn); 4069a64b02d5SManish Chopra if (!p_ptt) 4070a64b02d5SManish Chopra return -EBUSY; 4071a64b02d5SManish Chopra 4072a64b02d5SManish Chopra rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, 4073a64b02d5SManish Chopra p_link, min_bw); 4074a64b02d5SManish Chopra if (rc) { 4075a64b02d5SManish Chopra qed_ptt_release(p_hwfn, p_ptt); 4076a64b02d5SManish Chopra return rc; 4077a64b02d5SManish Chopra } 4078a64b02d5SManish Chopra 4079a64b02d5SManish Chopra if (p_link->min_pf_rate) { 4080a64b02d5SManish Chopra u32 min_rate = p_link->min_pf_rate; 4081a64b02d5SManish Chopra 4082a64b02d5SManish Chopra rc = __qed_configure_vp_wfq_on_link_change(p_hwfn, 4083a64b02d5SManish Chopra p_ptt, 4084a64b02d5SManish Chopra min_rate); 4085a64b02d5SManish Chopra } 4086a64b02d5SManish Chopra 4087a64b02d5SManish Chopra qed_ptt_release(p_hwfn, p_ptt); 4088a64b02d5SManish Chopra } 4089a64b02d5SManish Chopra 4090a64b02d5SManish Chopra return rc; 4091a64b02d5SManish Chopra } 4092733def6aSYuval Mintz 4093733def6aSYuval Mintz void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 4094733def6aSYuval Mintz { 4095733def6aSYuval Mintz struct qed_mcp_link_state *p_link; 4096733def6aSYuval Mintz 4097733def6aSYuval Mintz p_link = &p_hwfn->mcp_info->link_output; 4098733def6aSYuval Mintz 4099733def6aSYuval Mintz if (p_link->min_pf_rate) 4100733def6aSYuval Mintz qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, 4101733def6aSYuval Mintz p_link->min_pf_rate); 4102733def6aSYuval Mintz 4103733def6aSYuval Mintz memset(p_hwfn->qm_info.wfq_data, 0, 4104733def6aSYuval Mintz sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports); 4105733def6aSYuval Mintz } 41069c79ddaaSMintz, Yuval 41079c79ddaaSMintz, Yuval int qed_device_num_engines(struct qed_dev *cdev) 41089c79ddaaSMintz, Yuval { 41099c79ddaaSMintz, Yuval return QED_IS_BB(cdev) ? 2 : 1; 41109c79ddaaSMintz, Yuval } 4111db82f70eSsudarsana.kalluru@cavium.com 4112db82f70eSsudarsana.kalluru@cavium.com static int qed_device_num_ports(struct qed_dev *cdev) 4113db82f70eSsudarsana.kalluru@cavium.com { 4114db82f70eSsudarsana.kalluru@cavium.com /* in CMT always only one port */ 4115db82f70eSsudarsana.kalluru@cavium.com if (cdev->num_hwfns > 1) 4116db82f70eSsudarsana.kalluru@cavium.com return 1; 4117db82f70eSsudarsana.kalluru@cavium.com 411878cea9ffSTomer Tayar return cdev->num_ports_in_engine * qed_device_num_engines(cdev); 4119db82f70eSsudarsana.kalluru@cavium.com } 4120db82f70eSsudarsana.kalluru@cavium.com 4121db82f70eSsudarsana.kalluru@cavium.com int qed_device_get_port_id(struct qed_dev *cdev) 4122db82f70eSsudarsana.kalluru@cavium.com { 4123db82f70eSsudarsana.kalluru@cavium.com return (QED_LEADING_HWFN(cdev)->abs_pf_id) % qed_device_num_ports(cdev); 4124db82f70eSsudarsana.kalluru@cavium.com } 4125