1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #include <linux/types.h> 34fe56b9e6SYuval Mintz #include <asm/byteorder.h> 35fe56b9e6SYuval Mintz #include <linux/io.h> 36fe56b9e6SYuval Mintz #include <linux/delay.h> 37fe56b9e6SYuval Mintz #include <linux/dma-mapping.h> 38fe56b9e6SYuval Mintz #include <linux/errno.h> 39fe56b9e6SYuval Mintz #include <linux/kernel.h> 40fe56b9e6SYuval Mintz #include <linux/mutex.h> 41fe56b9e6SYuval Mintz #include <linux/pci.h> 42fe56b9e6SYuval Mintz #include <linux/slab.h> 43fe56b9e6SYuval Mintz #include <linux/string.h> 44a91eb52aSYuval Mintz #include <linux/vmalloc.h> 45fe56b9e6SYuval Mintz #include <linux/etherdevice.h> 46fe56b9e6SYuval Mintz #include <linux/qed/qed_chain.h> 47fe56b9e6SYuval Mintz #include <linux/qed/qed_if.h> 48fe56b9e6SYuval Mintz #include "qed.h" 49fe56b9e6SYuval Mintz #include "qed_cxt.h" 5039651abdSSudarsana Reddy Kalluru #include "qed_dcbx.h" 51fe56b9e6SYuval Mintz #include "qed_dev_api.h" 521e128c81SArun Easi #include "qed_fcoe.h" 53fe56b9e6SYuval Mintz #include "qed_hsi.h" 54fe56b9e6SYuval Mintz #include "qed_hw.h" 55fe56b9e6SYuval Mintz #include "qed_init_ops.h" 56fe56b9e6SYuval Mintz #include "qed_int.h" 57fc831825SYuval Mintz #include "qed_iscsi.h" 580a7fb11cSYuval Mintz #include "qed_ll2.h" 59fe56b9e6SYuval Mintz #include "qed_mcp.h" 601d6cff4fSYuval Mintz #include "qed_ooo.h" 61fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 62fe56b9e6SYuval Mintz #include "qed_sp.h" 6332a47e72SYuval Mintz #include "qed_sriov.h" 640b55e27dSYuval Mintz #include "qed_vf.h" 65b71b9afdSKalderon, Michal #include "qed_rdma.h" 66fe56b9e6SYuval Mintz 670caf5b26SWei Yongjun static DEFINE_SPINLOCK(qm_lock); 6839651abdSSudarsana Reddy Kalluru 6951ff1725SRam Amrani #define QED_MIN_DPIS (4) 7051ff1725SRam Amrani #define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS) 7151ff1725SRam Amrani 7215582962SRahul Verma static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, 7315582962SRahul Verma struct qed_ptt *p_ptt, enum BAR_ID bar_id) 74c2035eeaSRam Amrani { 75c2035eeaSRam Amrani u32 bar_reg = (bar_id == BAR_ID_0 ? 76c2035eeaSRam Amrani PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE); 771408cc1fSYuval Mintz u32 val; 78c2035eeaSRam Amrani 791408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 801a850bfcSMintz, Yuval return qed_vf_hw_bar_size(p_hwfn, bar_id); 811408cc1fSYuval Mintz 8215582962SRahul Verma val = qed_rd(p_hwfn, p_ptt, bar_reg); 83c2035eeaSRam Amrani if (val) 84c2035eeaSRam Amrani return 1 << (val + 15); 85c2035eeaSRam Amrani 86c2035eeaSRam Amrani /* Old MFW initialized above registered only conditionally */ 87c2035eeaSRam Amrani if (p_hwfn->cdev->num_hwfns > 1) { 88c2035eeaSRam Amrani DP_INFO(p_hwfn, 89c2035eeaSRam Amrani "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n"); 90c2035eeaSRam Amrani return BAR_ID_0 ? 256 * 1024 : 512 * 1024; 91c2035eeaSRam Amrani } else { 92c2035eeaSRam Amrani DP_INFO(p_hwfn, 93c2035eeaSRam Amrani "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n"); 94c2035eeaSRam Amrani return 512 * 1024; 95c2035eeaSRam Amrani } 96c2035eeaSRam Amrani } 97c2035eeaSRam Amrani 981a635e48SYuval Mintz void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level) 99fe56b9e6SYuval Mintz { 100fe56b9e6SYuval Mintz u32 i; 101fe56b9e6SYuval Mintz 102fe56b9e6SYuval Mintz cdev->dp_level = dp_level; 103fe56b9e6SYuval Mintz cdev->dp_module = dp_module; 104fe56b9e6SYuval Mintz for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 105fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 106fe56b9e6SYuval Mintz 107fe56b9e6SYuval Mintz p_hwfn->dp_level = dp_level; 108fe56b9e6SYuval Mintz p_hwfn->dp_module = dp_module; 109fe56b9e6SYuval Mintz } 110fe56b9e6SYuval Mintz } 111fe56b9e6SYuval Mintz 112fe56b9e6SYuval Mintz void qed_init_struct(struct qed_dev *cdev) 113fe56b9e6SYuval Mintz { 114fe56b9e6SYuval Mintz u8 i; 115fe56b9e6SYuval Mintz 116fe56b9e6SYuval Mintz for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 117fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 118fe56b9e6SYuval Mintz 119fe56b9e6SYuval Mintz p_hwfn->cdev = cdev; 120fe56b9e6SYuval Mintz p_hwfn->my_id = i; 121fe56b9e6SYuval Mintz p_hwfn->b_active = false; 122fe56b9e6SYuval Mintz 123fe56b9e6SYuval Mintz mutex_init(&p_hwfn->dmae_info.mutex); 124fe56b9e6SYuval Mintz } 125fe56b9e6SYuval Mintz 126fe56b9e6SYuval Mintz /* hwfn 0 is always active */ 127fe56b9e6SYuval Mintz cdev->hwfns[0].b_active = true; 128fe56b9e6SYuval Mintz 129fe56b9e6SYuval Mintz /* set the default cache alignment to 128 */ 130fe56b9e6SYuval Mintz cdev->cache_shift = 7; 131fe56b9e6SYuval Mintz } 132fe56b9e6SYuval Mintz 133fe56b9e6SYuval Mintz static void qed_qm_info_free(struct qed_hwfn *p_hwfn) 134fe56b9e6SYuval Mintz { 135fe56b9e6SYuval Mintz struct qed_qm_info *qm_info = &p_hwfn->qm_info; 136fe56b9e6SYuval Mintz 137fe56b9e6SYuval Mintz kfree(qm_info->qm_pq_params); 138fe56b9e6SYuval Mintz qm_info->qm_pq_params = NULL; 139fe56b9e6SYuval Mintz kfree(qm_info->qm_vport_params); 140fe56b9e6SYuval Mintz qm_info->qm_vport_params = NULL; 141fe56b9e6SYuval Mintz kfree(qm_info->qm_port_params); 142fe56b9e6SYuval Mintz qm_info->qm_port_params = NULL; 143bcd197c8SManish Chopra kfree(qm_info->wfq_data); 144bcd197c8SManish Chopra qm_info->wfq_data = NULL; 145fe56b9e6SYuval Mintz } 146fe56b9e6SYuval Mintz 147a3f72307SDenis Bolotin static void qed_dbg_user_data_free(struct qed_hwfn *p_hwfn) 148a3f72307SDenis Bolotin { 149a3f72307SDenis Bolotin kfree(p_hwfn->dbg_user_info); 150a3f72307SDenis Bolotin p_hwfn->dbg_user_info = NULL; 151a3f72307SDenis Bolotin } 152a3f72307SDenis Bolotin 153fe56b9e6SYuval Mintz void qed_resc_free(struct qed_dev *cdev) 154fe56b9e6SYuval Mintz { 155fe56b9e6SYuval Mintz int i; 156fe56b9e6SYuval Mintz 1570db711bbSMintz, Yuval if (IS_VF(cdev)) { 1580db711bbSMintz, Yuval for_each_hwfn(cdev, i) 1590db711bbSMintz, Yuval qed_l2_free(&cdev->hwfns[i]); 1601408cc1fSYuval Mintz return; 1610db711bbSMintz, Yuval } 1621408cc1fSYuval Mintz 163fe56b9e6SYuval Mintz kfree(cdev->fw_data); 164fe56b9e6SYuval Mintz cdev->fw_data = NULL; 165fe56b9e6SYuval Mintz 166fe56b9e6SYuval Mintz kfree(cdev->reset_stats); 1673587cb87STomer Tayar cdev->reset_stats = NULL; 168fe56b9e6SYuval Mintz 169fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 170fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 171fe56b9e6SYuval Mintz 172fe56b9e6SYuval Mintz qed_cxt_mngr_free(p_hwfn); 173fe56b9e6SYuval Mintz qed_qm_info_free(p_hwfn); 174fe56b9e6SYuval Mintz qed_spq_free(p_hwfn); 1753587cb87STomer Tayar qed_eq_free(p_hwfn); 1763587cb87STomer Tayar qed_consq_free(p_hwfn); 177fe56b9e6SYuval Mintz qed_int_free(p_hwfn); 1780a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 1793587cb87STomer Tayar qed_ll2_free(p_hwfn); 1800a7fb11cSYuval Mintz #endif 1811e128c81SArun Easi if (p_hwfn->hw_info.personality == QED_PCI_FCOE) 1823587cb87STomer Tayar qed_fcoe_free(p_hwfn); 1831e128c81SArun Easi 1841d6cff4fSYuval Mintz if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 1853587cb87STomer Tayar qed_iscsi_free(p_hwfn); 1863587cb87STomer Tayar qed_ooo_free(p_hwfn); 1871d6cff4fSYuval Mintz } 18832a47e72SYuval Mintz qed_iov_free(p_hwfn); 1890db711bbSMintz, Yuval qed_l2_free(p_hwfn); 190fe56b9e6SYuval Mintz qed_dmae_info_free(p_hwfn); 191270837b3Ssudarsana.kalluru@cavium.com qed_dcbx_info_free(p_hwfn); 192a3f72307SDenis Bolotin qed_dbg_user_data_free(p_hwfn); 193fe56b9e6SYuval Mintz } 194fe56b9e6SYuval Mintz } 195fe56b9e6SYuval Mintz 196b5a9ee7cSAriel Elior /******************** QM initialization *******************/ 197b5a9ee7cSAriel Elior #define ACTIVE_TCS_BMAP 0x9f 198b5a9ee7cSAriel Elior #define ACTIVE_TCS_BMAP_4PORT_K2 0xf 199b5a9ee7cSAriel Elior 200b5a9ee7cSAriel Elior /* determines the physical queue flags for a given PF. */ 201b5a9ee7cSAriel Elior static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn) 202fe56b9e6SYuval Mintz { 203b5a9ee7cSAriel Elior u32 flags; 204fe56b9e6SYuval Mintz 205b5a9ee7cSAriel Elior /* common flags */ 206b5a9ee7cSAriel Elior flags = PQ_FLAGS_LB; 207fe56b9e6SYuval Mintz 208b5a9ee7cSAriel Elior /* feature flags */ 209b5a9ee7cSAriel Elior if (IS_QED_SRIOV(p_hwfn->cdev)) 210b5a9ee7cSAriel Elior flags |= PQ_FLAGS_VFS; 211fe56b9e6SYuval Mintz 212b5a9ee7cSAriel Elior /* protocol flags */ 213b5a9ee7cSAriel Elior switch (p_hwfn->hw_info.personality) { 214b5a9ee7cSAriel Elior case QED_PCI_ETH: 215b5a9ee7cSAriel Elior flags |= PQ_FLAGS_MCOS; 216b5a9ee7cSAriel Elior break; 217b5a9ee7cSAriel Elior case QED_PCI_FCOE: 218b5a9ee7cSAriel Elior flags |= PQ_FLAGS_OFLD; 219b5a9ee7cSAriel Elior break; 220b5a9ee7cSAriel Elior case QED_PCI_ISCSI: 221b5a9ee7cSAriel Elior flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD; 222b5a9ee7cSAriel Elior break; 223b5a9ee7cSAriel Elior case QED_PCI_ETH_ROCE: 224b5a9ee7cSAriel Elior flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT; 22561be82b0SDenis Bolotin if (IS_QED_MULTI_TC_ROCE(p_hwfn)) 22661be82b0SDenis Bolotin flags |= PQ_FLAGS_MTC; 227b5a9ee7cSAriel Elior break; 22893c45984SKalderon, Michal case QED_PCI_ETH_IWARP: 22993c45984SKalderon, Michal flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO | 23093c45984SKalderon, Michal PQ_FLAGS_OFLD; 23193c45984SKalderon, Michal break; 232b5a9ee7cSAriel Elior default: 233fe56b9e6SYuval Mintz DP_ERR(p_hwfn, 234b5a9ee7cSAriel Elior "unknown personality %d\n", p_hwfn->hw_info.personality); 235b5a9ee7cSAriel Elior return 0; 236fe56b9e6SYuval Mintz } 237fe56b9e6SYuval Mintz 238b5a9ee7cSAriel Elior return flags; 239b5a9ee7cSAriel Elior } 240b5a9ee7cSAriel Elior 241b5a9ee7cSAriel Elior /* Getters for resource amounts necessary for qm initialization */ 242bf774d14SYueHaibing static u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn) 243b5a9ee7cSAriel Elior { 244b5a9ee7cSAriel Elior return p_hwfn->hw_info.num_hw_tc; 245b5a9ee7cSAriel Elior } 246b5a9ee7cSAriel Elior 247bf774d14SYueHaibing static u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn) 248b5a9ee7cSAriel Elior { 249b5a9ee7cSAriel Elior return IS_QED_SRIOV(p_hwfn->cdev) ? 250b5a9ee7cSAriel Elior p_hwfn->cdev->p_iov_info->total_vfs : 0; 251b5a9ee7cSAriel Elior } 252b5a9ee7cSAriel Elior 25361be82b0SDenis Bolotin static u8 qed_init_qm_get_num_mtc_tcs(struct qed_hwfn *p_hwfn) 25461be82b0SDenis Bolotin { 25561be82b0SDenis Bolotin u32 pq_flags = qed_get_pq_flags(p_hwfn); 25661be82b0SDenis Bolotin 25761be82b0SDenis Bolotin if (!(PQ_FLAGS_MTC & pq_flags)) 25861be82b0SDenis Bolotin return 1; 25961be82b0SDenis Bolotin 26061be82b0SDenis Bolotin return qed_init_qm_get_num_tcs(p_hwfn); 26161be82b0SDenis Bolotin } 26261be82b0SDenis Bolotin 263b5a9ee7cSAriel Elior #define NUM_DEFAULT_RLS 1 264b5a9ee7cSAriel Elior 265bf774d14SYueHaibing static u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn) 266b5a9ee7cSAriel Elior { 267b5a9ee7cSAriel Elior u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn); 268b5a9ee7cSAriel Elior 269b5a9ee7cSAriel Elior /* num RLs can't exceed resource amount of rls or vports */ 270b5a9ee7cSAriel Elior num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL), 271b5a9ee7cSAriel Elior RESC_NUM(p_hwfn, QED_VPORT)); 272b5a9ee7cSAriel Elior 273b5a9ee7cSAriel Elior /* Make sure after we reserve there's something left */ 274b5a9ee7cSAriel Elior if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) 275b5a9ee7cSAriel Elior return 0; 276b5a9ee7cSAriel Elior 277b5a9ee7cSAriel Elior /* subtract rls necessary for VFs and one default one for the PF */ 278b5a9ee7cSAriel Elior num_pf_rls -= num_vfs + NUM_DEFAULT_RLS; 279b5a9ee7cSAriel Elior 280b5a9ee7cSAriel Elior return num_pf_rls; 281b5a9ee7cSAriel Elior } 282b5a9ee7cSAriel Elior 283bf774d14SYueHaibing static u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn) 284b5a9ee7cSAriel Elior { 285b5a9ee7cSAriel Elior u32 pq_flags = qed_get_pq_flags(p_hwfn); 286b5a9ee7cSAriel Elior 287b5a9ee7cSAriel Elior /* all pqs share the same vport, except for vfs and pf_rl pqs */ 288b5a9ee7cSAriel Elior return (!!(PQ_FLAGS_RLS & pq_flags)) * 289b5a9ee7cSAriel Elior qed_init_qm_get_num_pf_rls(p_hwfn) + 290b5a9ee7cSAriel Elior (!!(PQ_FLAGS_VFS & pq_flags)) * 291b5a9ee7cSAriel Elior qed_init_qm_get_num_vfs(p_hwfn) + 1; 292b5a9ee7cSAriel Elior } 293b5a9ee7cSAriel Elior 294b5a9ee7cSAriel Elior /* calc amount of PQs according to the requested flags */ 295bf774d14SYueHaibing static u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn) 296b5a9ee7cSAriel Elior { 297b5a9ee7cSAriel Elior u32 pq_flags = qed_get_pq_flags(p_hwfn); 298b5a9ee7cSAriel Elior 299b5a9ee7cSAriel Elior return (!!(PQ_FLAGS_RLS & pq_flags)) * 300b5a9ee7cSAriel Elior qed_init_qm_get_num_pf_rls(p_hwfn) + 301b5a9ee7cSAriel Elior (!!(PQ_FLAGS_MCOS & pq_flags)) * 302b5a9ee7cSAriel Elior qed_init_qm_get_num_tcs(p_hwfn) + 303b5a9ee7cSAriel Elior (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) + 30461be82b0SDenis Bolotin (!!(PQ_FLAGS_ACK & pq_flags)) + 30561be82b0SDenis Bolotin (!!(PQ_FLAGS_OFLD & pq_flags)) * 30661be82b0SDenis Bolotin qed_init_qm_get_num_mtc_tcs(p_hwfn) + 30761be82b0SDenis Bolotin (!!(PQ_FLAGS_LLT & pq_flags)) * 30861be82b0SDenis Bolotin qed_init_qm_get_num_mtc_tcs(p_hwfn) + 309b5a9ee7cSAriel Elior (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn); 310b5a9ee7cSAriel Elior } 311b5a9ee7cSAriel Elior 312b5a9ee7cSAriel Elior /* initialize the top level QM params */ 313b5a9ee7cSAriel Elior static void qed_init_qm_params(struct qed_hwfn *p_hwfn) 314b5a9ee7cSAriel Elior { 315b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 316b5a9ee7cSAriel Elior bool four_port; 317b5a9ee7cSAriel Elior 318b5a9ee7cSAriel Elior /* pq and vport bases for this PF */ 319b5a9ee7cSAriel Elior qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ); 320b5a9ee7cSAriel Elior qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT); 321b5a9ee7cSAriel Elior 322b5a9ee7cSAriel Elior /* rate limiting and weighted fair queueing are always enabled */ 323c7281d59SGustavo A. R. Silva qm_info->vport_rl_en = true; 324c7281d59SGustavo A. R. Silva qm_info->vport_wfq_en = true; 325b5a9ee7cSAriel Elior 326b5a9ee7cSAriel Elior /* TC config is different for AH 4 port */ 32778cea9ffSTomer Tayar four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2; 328b5a9ee7cSAriel Elior 329b5a9ee7cSAriel Elior /* in AH 4 port we have fewer TCs per port */ 330b5a9ee7cSAriel Elior qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 : 331b5a9ee7cSAriel Elior NUM_OF_PHYS_TCS; 332b5a9ee7cSAriel Elior 333b5a9ee7cSAriel Elior /* unless MFW indicated otherwise, ooo_tc == 3 for 334b5a9ee7cSAriel Elior * AH 4-port and 4 otherwise. 335fe56b9e6SYuval Mintz */ 336b5a9ee7cSAriel Elior if (!qm_info->ooo_tc) 337b5a9ee7cSAriel Elior qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC : 338b5a9ee7cSAriel Elior DCBX_TCP_OOO_TC; 339dbb799c3SYuval Mintz } 340dbb799c3SYuval Mintz 341b5a9ee7cSAriel Elior /* initialize qm vport params */ 342b5a9ee7cSAriel Elior static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn) 343b5a9ee7cSAriel Elior { 344b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 345b5a9ee7cSAriel Elior u8 i; 346fe56b9e6SYuval Mintz 347b5a9ee7cSAriel Elior /* all vports participate in weighted fair queueing */ 348b5a9ee7cSAriel Elior for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++) 349b5a9ee7cSAriel Elior qm_info->qm_vport_params[i].vport_wfq = 1; 350fe56b9e6SYuval Mintz } 351fe56b9e6SYuval Mintz 352b5a9ee7cSAriel Elior /* initialize qm port params */ 353b5a9ee7cSAriel Elior static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn) 354b5a9ee7cSAriel Elior { 355fe56b9e6SYuval Mintz /* Initialize qm port parameters */ 35678cea9ffSTomer Tayar u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine; 357b5a9ee7cSAriel Elior 358b5a9ee7cSAriel Elior /* indicate how ooo and high pri traffic is dealt with */ 359b5a9ee7cSAriel Elior active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ? 360b5a9ee7cSAriel Elior ACTIVE_TCS_BMAP_4PORT_K2 : 361b5a9ee7cSAriel Elior ACTIVE_TCS_BMAP; 362b5a9ee7cSAriel Elior 363fe56b9e6SYuval Mintz for (i = 0; i < num_ports; i++) { 364b5a9ee7cSAriel Elior struct init_qm_port_params *p_qm_port = 365b5a9ee7cSAriel Elior &p_hwfn->qm_info.qm_port_params[i]; 366b5a9ee7cSAriel Elior 367fe56b9e6SYuval Mintz p_qm_port->active = 1; 368b5a9ee7cSAriel Elior p_qm_port->active_phys_tcs = active_phys_tcs; 369fe56b9e6SYuval Mintz p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports; 370fe56b9e6SYuval Mintz p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports; 371fe56b9e6SYuval Mintz } 372b5a9ee7cSAriel Elior } 373fe56b9e6SYuval Mintz 374b5a9ee7cSAriel Elior /* Reset the params which must be reset for qm init. QM init may be called as 375b5a9ee7cSAriel Elior * a result of flows other than driver load (e.g. dcbx renegotiation). Other 376b5a9ee7cSAriel Elior * params may be affected by the init but would simply recalculate to the same 377b5a9ee7cSAriel Elior * values. The allocations made for QM init, ports, vports, pqs and vfqs are not 378b5a9ee7cSAriel Elior * affected as these amounts stay the same. 379b5a9ee7cSAriel Elior */ 380b5a9ee7cSAriel Elior static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn) 381b5a9ee7cSAriel Elior { 382b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 383fe56b9e6SYuval Mintz 384b5a9ee7cSAriel Elior qm_info->num_pqs = 0; 385b5a9ee7cSAriel Elior qm_info->num_vports = 0; 386b5a9ee7cSAriel Elior qm_info->num_pf_rls = 0; 387b5a9ee7cSAriel Elior qm_info->num_vf_pqs = 0; 388b5a9ee7cSAriel Elior qm_info->first_vf_pq = 0; 389b5a9ee7cSAriel Elior qm_info->first_mcos_pq = 0; 390b5a9ee7cSAriel Elior qm_info->first_rl_pq = 0; 391b5a9ee7cSAriel Elior } 392fe56b9e6SYuval Mintz 393b5a9ee7cSAriel Elior static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn) 394b5a9ee7cSAriel Elior { 395b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 396b5a9ee7cSAriel Elior 397b5a9ee7cSAriel Elior qm_info->num_vports++; 398b5a9ee7cSAriel Elior 399b5a9ee7cSAriel Elior if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn)) 400b5a9ee7cSAriel Elior DP_ERR(p_hwfn, 401b5a9ee7cSAriel Elior "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n", 402b5a9ee7cSAriel Elior qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn)); 403b5a9ee7cSAriel Elior } 404b5a9ee7cSAriel Elior 405b5a9ee7cSAriel Elior /* initialize a single pq and manage qm_info resources accounting. 406b5a9ee7cSAriel Elior * The pq_init_flags param determines whether the PQ is rate limited 407b5a9ee7cSAriel Elior * (for VF or PF) and whether a new vport is allocated to the pq or not 408b5a9ee7cSAriel Elior * (i.e. vport will be shared). 409b5a9ee7cSAriel Elior */ 410b5a9ee7cSAriel Elior 411b5a9ee7cSAriel Elior /* flags for pq init */ 412b5a9ee7cSAriel Elior #define PQ_INIT_SHARE_VPORT (1 << 0) 413b5a9ee7cSAriel Elior #define PQ_INIT_PF_RL (1 << 1) 414b5a9ee7cSAriel Elior #define PQ_INIT_VF_RL (1 << 2) 415b5a9ee7cSAriel Elior 416b5a9ee7cSAriel Elior /* defines for pq init */ 417b5a9ee7cSAriel Elior #define PQ_INIT_DEFAULT_WRR_GROUP 1 418b5a9ee7cSAriel Elior #define PQ_INIT_DEFAULT_TC 0 419c4259ddaSDenis Bolotin 420c4259ddaSDenis Bolotin void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc) 421c4259ddaSDenis Bolotin { 422c4259ddaSDenis Bolotin p_info->offload_tc = tc; 423c4259ddaSDenis Bolotin p_info->offload_tc_set = true; 424c4259ddaSDenis Bolotin } 425c4259ddaSDenis Bolotin 426c4259ddaSDenis Bolotin static bool qed_is_offload_tc_set(struct qed_hwfn *p_hwfn) 427c4259ddaSDenis Bolotin { 428c4259ddaSDenis Bolotin return p_hwfn->hw_info.offload_tc_set; 429c4259ddaSDenis Bolotin } 430c4259ddaSDenis Bolotin 431c4259ddaSDenis Bolotin static u32 qed_get_offload_tc(struct qed_hwfn *p_hwfn) 432c4259ddaSDenis Bolotin { 433c4259ddaSDenis Bolotin if (qed_is_offload_tc_set(p_hwfn)) 434c4259ddaSDenis Bolotin return p_hwfn->hw_info.offload_tc; 435c4259ddaSDenis Bolotin 436c4259ddaSDenis Bolotin return PQ_INIT_DEFAULT_TC; 437c4259ddaSDenis Bolotin } 438b5a9ee7cSAriel Elior 439b5a9ee7cSAriel Elior static void qed_init_qm_pq(struct qed_hwfn *p_hwfn, 440b5a9ee7cSAriel Elior struct qed_qm_info *qm_info, 441b5a9ee7cSAriel Elior u8 tc, u32 pq_init_flags) 442b5a9ee7cSAriel Elior { 443b5a9ee7cSAriel Elior u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn); 444b5a9ee7cSAriel Elior 445b5a9ee7cSAriel Elior if (pq_idx > max_pq) 446b5a9ee7cSAriel Elior DP_ERR(p_hwfn, 447b5a9ee7cSAriel Elior "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq); 448b5a9ee7cSAriel Elior 449b5a9ee7cSAriel Elior /* init pq params */ 45050bc60cbSMichal Kalderon qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id; 451b5a9ee7cSAriel Elior qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport + 452b5a9ee7cSAriel Elior qm_info->num_vports; 453b5a9ee7cSAriel Elior qm_info->qm_pq_params[pq_idx].tc_id = tc; 454b5a9ee7cSAriel Elior qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP; 455b5a9ee7cSAriel Elior qm_info->qm_pq_params[pq_idx].rl_valid = 456b5a9ee7cSAriel Elior (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL); 457b5a9ee7cSAriel Elior 458b5a9ee7cSAriel Elior /* qm params accounting */ 459b5a9ee7cSAriel Elior qm_info->num_pqs++; 460b5a9ee7cSAriel Elior if (!(pq_init_flags & PQ_INIT_SHARE_VPORT)) 461b5a9ee7cSAriel Elior qm_info->num_vports++; 462b5a9ee7cSAriel Elior 463b5a9ee7cSAriel Elior if (pq_init_flags & PQ_INIT_PF_RL) 464b5a9ee7cSAriel Elior qm_info->num_pf_rls++; 465b5a9ee7cSAriel Elior 466b5a9ee7cSAriel Elior if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn)) 467b5a9ee7cSAriel Elior DP_ERR(p_hwfn, 468b5a9ee7cSAriel Elior "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n", 469b5a9ee7cSAriel Elior qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn)); 470b5a9ee7cSAriel Elior 471b5a9ee7cSAriel Elior if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn)) 472b5a9ee7cSAriel Elior DP_ERR(p_hwfn, 473b5a9ee7cSAriel Elior "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n", 474b5a9ee7cSAriel Elior qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn)); 475b5a9ee7cSAriel Elior } 476b5a9ee7cSAriel Elior 477b5a9ee7cSAriel Elior /* get pq index according to PQ_FLAGS */ 478b5a9ee7cSAriel Elior static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn, 479b5a9ee7cSAriel Elior u32 pq_flags) 480b5a9ee7cSAriel Elior { 481b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 482b5a9ee7cSAriel Elior 483b5a9ee7cSAriel Elior /* Can't have multiple flags set here */ 484b5a9ee7cSAriel Elior if (bitmap_weight((unsigned long *)&pq_flags, sizeof(pq_flags)) > 1) 485b5a9ee7cSAriel Elior goto err; 486b5a9ee7cSAriel Elior 487b5a9ee7cSAriel Elior switch (pq_flags) { 488b5a9ee7cSAriel Elior case PQ_FLAGS_RLS: 489b5a9ee7cSAriel Elior return &qm_info->first_rl_pq; 490b5a9ee7cSAriel Elior case PQ_FLAGS_MCOS: 491b5a9ee7cSAriel Elior return &qm_info->first_mcos_pq; 492b5a9ee7cSAriel Elior case PQ_FLAGS_LB: 493b5a9ee7cSAriel Elior return &qm_info->pure_lb_pq; 494b5a9ee7cSAriel Elior case PQ_FLAGS_OOO: 495b5a9ee7cSAriel Elior return &qm_info->ooo_pq; 496b5a9ee7cSAriel Elior case PQ_FLAGS_ACK: 497b5a9ee7cSAriel Elior return &qm_info->pure_ack_pq; 498b5a9ee7cSAriel Elior case PQ_FLAGS_OFLD: 49961be82b0SDenis Bolotin return &qm_info->first_ofld_pq; 500b5a9ee7cSAriel Elior case PQ_FLAGS_LLT: 50161be82b0SDenis Bolotin return &qm_info->first_llt_pq; 502b5a9ee7cSAriel Elior case PQ_FLAGS_VFS: 503b5a9ee7cSAriel Elior return &qm_info->first_vf_pq; 504b5a9ee7cSAriel Elior default: 505b5a9ee7cSAriel Elior goto err; 506b5a9ee7cSAriel Elior } 507b5a9ee7cSAriel Elior 508b5a9ee7cSAriel Elior err: 509b5a9ee7cSAriel Elior DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags); 510b5a9ee7cSAriel Elior return NULL; 511b5a9ee7cSAriel Elior } 512b5a9ee7cSAriel Elior 513b5a9ee7cSAriel Elior /* save pq index in qm info */ 514b5a9ee7cSAriel Elior static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn, 515b5a9ee7cSAriel Elior u32 pq_flags, u16 pq_val) 516b5a9ee7cSAriel Elior { 517b5a9ee7cSAriel Elior u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags); 518b5a9ee7cSAriel Elior 519b5a9ee7cSAriel Elior *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val; 520b5a9ee7cSAriel Elior } 521b5a9ee7cSAriel Elior 522b5a9ee7cSAriel Elior /* get tx pq index, with the PQ TX base already set (ready for context init) */ 523b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags) 524b5a9ee7cSAriel Elior { 525b5a9ee7cSAriel Elior u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags); 526b5a9ee7cSAriel Elior 527b5a9ee7cSAriel Elior return *base_pq_idx + CM_TX_PQ_BASE; 528b5a9ee7cSAriel Elior } 529b5a9ee7cSAriel Elior 530b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc) 531b5a9ee7cSAriel Elior { 532b5a9ee7cSAriel Elior u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn); 533b5a9ee7cSAriel Elior 534b5a9ee7cSAriel Elior if (tc > max_tc) 535b5a9ee7cSAriel Elior DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc); 536b5a9ee7cSAriel Elior 537b5a9ee7cSAriel Elior return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc; 538b5a9ee7cSAriel Elior } 539b5a9ee7cSAriel Elior 540b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf) 541b5a9ee7cSAriel Elior { 542b5a9ee7cSAriel Elior u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn); 543b5a9ee7cSAriel Elior 544b5a9ee7cSAriel Elior if (vf > max_vf) 545b5a9ee7cSAriel Elior DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf); 546b5a9ee7cSAriel Elior 547b5a9ee7cSAriel Elior return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf; 548b5a9ee7cSAriel Elior } 549b5a9ee7cSAriel Elior 55061be82b0SDenis Bolotin u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc) 55161be82b0SDenis Bolotin { 55261be82b0SDenis Bolotin u16 first_ofld_pq, pq_offset; 55361be82b0SDenis Bolotin 55461be82b0SDenis Bolotin first_ofld_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD); 55561be82b0SDenis Bolotin pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ? 55661be82b0SDenis Bolotin tc : PQ_INIT_DEFAULT_TC; 55761be82b0SDenis Bolotin 55861be82b0SDenis Bolotin return first_ofld_pq + pq_offset; 55961be82b0SDenis Bolotin } 56061be82b0SDenis Bolotin 56161be82b0SDenis Bolotin u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc) 56261be82b0SDenis Bolotin { 56361be82b0SDenis Bolotin u16 first_llt_pq, pq_offset; 56461be82b0SDenis Bolotin 56561be82b0SDenis Bolotin first_llt_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LLT); 56661be82b0SDenis Bolotin pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ? 56761be82b0SDenis Bolotin tc : PQ_INIT_DEFAULT_TC; 56861be82b0SDenis Bolotin 56961be82b0SDenis Bolotin return first_llt_pq + pq_offset; 57061be82b0SDenis Bolotin } 57161be82b0SDenis Bolotin 572b5a9ee7cSAriel Elior /* Functions for creating specific types of pqs */ 573b5a9ee7cSAriel Elior static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn) 574b5a9ee7cSAriel Elior { 575b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 576b5a9ee7cSAriel Elior 577b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB)) 578b5a9ee7cSAriel Elior return; 579b5a9ee7cSAriel Elior 580b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs); 581b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT); 582b5a9ee7cSAriel Elior } 583b5a9ee7cSAriel Elior 584b5a9ee7cSAriel Elior static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn) 585b5a9ee7cSAriel Elior { 586b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 587b5a9ee7cSAriel Elior 588b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO)) 589b5a9ee7cSAriel Elior return; 590b5a9ee7cSAriel Elior 591b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs); 592b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT); 593b5a9ee7cSAriel Elior } 594b5a9ee7cSAriel Elior 595b5a9ee7cSAriel Elior static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn) 596b5a9ee7cSAriel Elior { 597b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 598b5a9ee7cSAriel Elior 599b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK)) 600b5a9ee7cSAriel Elior return; 601b5a9ee7cSAriel Elior 602b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs); 603c4259ddaSDenis Bolotin qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn), 604c4259ddaSDenis Bolotin PQ_INIT_SHARE_VPORT); 605b5a9ee7cSAriel Elior } 606b5a9ee7cSAriel Elior 60761be82b0SDenis Bolotin static void qed_init_qm_mtc_pqs(struct qed_hwfn *p_hwfn) 60861be82b0SDenis Bolotin { 60961be82b0SDenis Bolotin u8 num_tcs = qed_init_qm_get_num_mtc_tcs(p_hwfn); 61061be82b0SDenis Bolotin struct qed_qm_info *qm_info = &p_hwfn->qm_info; 61161be82b0SDenis Bolotin u8 tc; 61261be82b0SDenis Bolotin 61361be82b0SDenis Bolotin /* override pq's TC if offload TC is set */ 61461be82b0SDenis Bolotin for (tc = 0; tc < num_tcs; tc++) 61561be82b0SDenis Bolotin qed_init_qm_pq(p_hwfn, qm_info, 61661be82b0SDenis Bolotin qed_is_offload_tc_set(p_hwfn) ? 61761be82b0SDenis Bolotin p_hwfn->hw_info.offload_tc : tc, 61861be82b0SDenis Bolotin PQ_INIT_SHARE_VPORT); 61961be82b0SDenis Bolotin } 62061be82b0SDenis Bolotin 621b5a9ee7cSAriel Elior static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn) 622b5a9ee7cSAriel Elior { 623b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 624b5a9ee7cSAriel Elior 625b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD)) 626b5a9ee7cSAriel Elior return; 627b5a9ee7cSAriel Elior 628b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs); 62961be82b0SDenis Bolotin qed_init_qm_mtc_pqs(p_hwfn); 630b5a9ee7cSAriel Elior } 631b5a9ee7cSAriel Elior 632b5a9ee7cSAriel Elior static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn) 633b5a9ee7cSAriel Elior { 634b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 635b5a9ee7cSAriel Elior 636b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT)) 637b5a9ee7cSAriel Elior return; 638b5a9ee7cSAriel Elior 639b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs); 64061be82b0SDenis Bolotin qed_init_qm_mtc_pqs(p_hwfn); 641b5a9ee7cSAriel Elior } 642b5a9ee7cSAriel Elior 643b5a9ee7cSAriel Elior static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn) 644b5a9ee7cSAriel Elior { 645b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 646b5a9ee7cSAriel Elior u8 tc_idx; 647b5a9ee7cSAriel Elior 648b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS)) 649b5a9ee7cSAriel Elior return; 650b5a9ee7cSAriel Elior 651b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs); 652b5a9ee7cSAriel Elior for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++) 653b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT); 654b5a9ee7cSAriel Elior } 655b5a9ee7cSAriel Elior 656b5a9ee7cSAriel Elior static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn) 657b5a9ee7cSAriel Elior { 658b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 659b5a9ee7cSAriel Elior u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn); 660b5a9ee7cSAriel Elior 661b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS)) 662b5a9ee7cSAriel Elior return; 663b5a9ee7cSAriel Elior 664b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs); 6651408cc1fSYuval Mintz qm_info->num_vf_pqs = num_vfs; 666b5a9ee7cSAriel Elior for (vf_idx = 0; vf_idx < num_vfs; vf_idx++) 667b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, 668b5a9ee7cSAriel Elior qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL); 669b5a9ee7cSAriel Elior } 670fe56b9e6SYuval Mintz 671b5a9ee7cSAriel Elior static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn) 672b5a9ee7cSAriel Elior { 673b5a9ee7cSAriel Elior u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn); 674b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 675a64b02d5SManish Chopra 676b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS)) 677b5a9ee7cSAriel Elior return; 678b5a9ee7cSAriel Elior 679b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs); 680b5a9ee7cSAriel Elior for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++) 681c4259ddaSDenis Bolotin qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn), 682c4259ddaSDenis Bolotin PQ_INIT_PF_RL); 683b5a9ee7cSAriel Elior } 684b5a9ee7cSAriel Elior 685b5a9ee7cSAriel Elior static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn) 686b5a9ee7cSAriel Elior { 687b5a9ee7cSAriel Elior /* rate limited pqs, must come first (FW assumption) */ 688b5a9ee7cSAriel Elior qed_init_qm_rl_pqs(p_hwfn); 689b5a9ee7cSAriel Elior 690b5a9ee7cSAriel Elior /* pqs for multi cos */ 691b5a9ee7cSAriel Elior qed_init_qm_mcos_pqs(p_hwfn); 692b5a9ee7cSAriel Elior 693b5a9ee7cSAriel Elior /* pure loopback pq */ 694b5a9ee7cSAriel Elior qed_init_qm_lb_pq(p_hwfn); 695b5a9ee7cSAriel Elior 696b5a9ee7cSAriel Elior /* out of order pq */ 697b5a9ee7cSAriel Elior qed_init_qm_ooo_pq(p_hwfn); 698b5a9ee7cSAriel Elior 699b5a9ee7cSAriel Elior /* pure ack pq */ 700b5a9ee7cSAriel Elior qed_init_qm_pure_ack_pq(p_hwfn); 701b5a9ee7cSAriel Elior 702b5a9ee7cSAriel Elior /* pq for offloaded protocol */ 703b5a9ee7cSAriel Elior qed_init_qm_offload_pq(p_hwfn); 704b5a9ee7cSAriel Elior 705b5a9ee7cSAriel Elior /* low latency pq */ 706b5a9ee7cSAriel Elior qed_init_qm_low_latency_pq(p_hwfn); 707b5a9ee7cSAriel Elior 708b5a9ee7cSAriel Elior /* done sharing vports */ 709b5a9ee7cSAriel Elior qed_init_qm_advance_vport(p_hwfn); 710b5a9ee7cSAriel Elior 711b5a9ee7cSAriel Elior /* pqs for vfs */ 712b5a9ee7cSAriel Elior qed_init_qm_vf_pqs(p_hwfn); 713b5a9ee7cSAriel Elior } 714b5a9ee7cSAriel Elior 715b5a9ee7cSAriel Elior /* compare values of getters against resources amounts */ 716b5a9ee7cSAriel Elior static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn) 717b5a9ee7cSAriel Elior { 718b5a9ee7cSAriel Elior if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) { 719b5a9ee7cSAriel Elior DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n"); 720b5a9ee7cSAriel Elior return -EINVAL; 721b5a9ee7cSAriel Elior } 722b5a9ee7cSAriel Elior 72361be82b0SDenis Bolotin if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ)) 72461be82b0SDenis Bolotin return 0; 72561be82b0SDenis Bolotin 72661be82b0SDenis Bolotin if (QED_IS_ROCE_PERSONALITY(p_hwfn)) { 72761be82b0SDenis Bolotin p_hwfn->hw_info.multi_tc_roce_en = 0; 72861be82b0SDenis Bolotin DP_NOTICE(p_hwfn, 72961be82b0SDenis Bolotin "multi-tc roce was disabled to reduce requested amount of pqs\n"); 73061be82b0SDenis Bolotin if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ)) 73161be82b0SDenis Bolotin return 0; 732b5a9ee7cSAriel Elior } 733fe56b9e6SYuval Mintz 73461be82b0SDenis Bolotin DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n"); 73561be82b0SDenis Bolotin return -EINVAL; 736b5a9ee7cSAriel Elior } 737fe56b9e6SYuval Mintz 738b5a9ee7cSAriel Elior static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn) 739b5a9ee7cSAriel Elior { 740b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 741b5a9ee7cSAriel Elior struct init_qm_vport_params *vport; 742b5a9ee7cSAriel Elior struct init_qm_port_params *port; 743b5a9ee7cSAriel Elior struct init_qm_pq_params *pq; 744b5a9ee7cSAriel Elior int i, tc; 745b5a9ee7cSAriel Elior 746b5a9ee7cSAriel Elior /* top level params */ 747b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 748b5a9ee7cSAriel Elior NETIF_MSG_HW, 74961be82b0SDenis Bolotin "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, llt_pq %d, pure_ack_pq %d\n", 750b5a9ee7cSAriel Elior qm_info->start_pq, 751b5a9ee7cSAriel Elior qm_info->start_vport, 752b5a9ee7cSAriel Elior qm_info->pure_lb_pq, 75361be82b0SDenis Bolotin qm_info->first_ofld_pq, 75461be82b0SDenis Bolotin qm_info->first_llt_pq, 75561be82b0SDenis Bolotin qm_info->pure_ack_pq); 756b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 757b5a9ee7cSAriel Elior NETIF_MSG_HW, 758b5a9ee7cSAriel Elior "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n", 759b5a9ee7cSAriel Elior qm_info->ooo_pq, 760b5a9ee7cSAriel Elior qm_info->first_vf_pq, 761b5a9ee7cSAriel Elior qm_info->num_pqs, 762b5a9ee7cSAriel Elior qm_info->num_vf_pqs, 763b5a9ee7cSAriel Elior qm_info->num_vports, qm_info->max_phys_tcs_per_port); 764b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 765b5a9ee7cSAriel Elior NETIF_MSG_HW, 766b5a9ee7cSAriel Elior "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n", 767b5a9ee7cSAriel Elior qm_info->pf_rl_en, 768b5a9ee7cSAriel Elior qm_info->pf_wfq_en, 769b5a9ee7cSAriel Elior qm_info->vport_rl_en, 770b5a9ee7cSAriel Elior qm_info->vport_wfq_en, 771b5a9ee7cSAriel Elior qm_info->pf_wfq, 772b5a9ee7cSAriel Elior qm_info->pf_rl, 773b5a9ee7cSAriel Elior qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn)); 774b5a9ee7cSAriel Elior 775b5a9ee7cSAriel Elior /* port table */ 77678cea9ffSTomer Tayar for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) { 777b5a9ee7cSAriel Elior port = &(qm_info->qm_port_params[i]); 778b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 779b5a9ee7cSAriel Elior NETIF_MSG_HW, 780b5a9ee7cSAriel Elior "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n", 781b5a9ee7cSAriel Elior i, 782b5a9ee7cSAriel Elior port->active, 783b5a9ee7cSAriel Elior port->active_phys_tcs, 784b5a9ee7cSAriel Elior port->num_pbf_cmd_lines, 785b5a9ee7cSAriel Elior port->num_btb_blocks, port->reserved); 786b5a9ee7cSAriel Elior } 787b5a9ee7cSAriel Elior 788b5a9ee7cSAriel Elior /* vport table */ 789b5a9ee7cSAriel Elior for (i = 0; i < qm_info->num_vports; i++) { 790b5a9ee7cSAriel Elior vport = &(qm_info->qm_vport_params[i]); 791b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 792b5a9ee7cSAriel Elior NETIF_MSG_HW, 793b5a9ee7cSAriel Elior "vport idx %d, vport_rl %d, wfq %d, first_tx_pq_id [ ", 794b5a9ee7cSAriel Elior qm_info->start_vport + i, 795b5a9ee7cSAriel Elior vport->vport_rl, vport->vport_wfq); 796b5a9ee7cSAriel Elior for (tc = 0; tc < NUM_OF_TCS; tc++) 797b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 798b5a9ee7cSAriel Elior NETIF_MSG_HW, 799b5a9ee7cSAriel Elior "%d ", vport->first_tx_pq_id[tc]); 800b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n"); 801b5a9ee7cSAriel Elior } 802b5a9ee7cSAriel Elior 803b5a9ee7cSAriel Elior /* pq table */ 804b5a9ee7cSAriel Elior for (i = 0; i < qm_info->num_pqs; i++) { 805b5a9ee7cSAriel Elior pq = &(qm_info->qm_pq_params[i]); 806b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 807b5a9ee7cSAriel Elior NETIF_MSG_HW, 80850bc60cbSMichal Kalderon "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n", 809b5a9ee7cSAriel Elior qm_info->start_pq + i, 81050bc60cbSMichal Kalderon pq->port_id, 811b5a9ee7cSAriel Elior pq->vport_id, 812b5a9ee7cSAriel Elior pq->tc_id, pq->wrr_group, pq->rl_valid); 813b5a9ee7cSAriel Elior } 814b5a9ee7cSAriel Elior } 815b5a9ee7cSAriel Elior 816b5a9ee7cSAriel Elior static void qed_init_qm_info(struct qed_hwfn *p_hwfn) 817b5a9ee7cSAriel Elior { 818b5a9ee7cSAriel Elior /* reset params required for init run */ 819b5a9ee7cSAriel Elior qed_init_qm_reset_params(p_hwfn); 820b5a9ee7cSAriel Elior 821b5a9ee7cSAriel Elior /* init QM top level params */ 822b5a9ee7cSAriel Elior qed_init_qm_params(p_hwfn); 823b5a9ee7cSAriel Elior 824b5a9ee7cSAriel Elior /* init QM port params */ 825b5a9ee7cSAriel Elior qed_init_qm_port_params(p_hwfn); 826b5a9ee7cSAriel Elior 827b5a9ee7cSAriel Elior /* init QM vport params */ 828b5a9ee7cSAriel Elior qed_init_qm_vport_params(p_hwfn); 829b5a9ee7cSAriel Elior 830b5a9ee7cSAriel Elior /* init QM physical queue params */ 831b5a9ee7cSAriel Elior qed_init_qm_pq_params(p_hwfn); 832b5a9ee7cSAriel Elior 833b5a9ee7cSAriel Elior /* display all that init */ 834b5a9ee7cSAriel Elior qed_dp_init_qm_params(p_hwfn); 835fe56b9e6SYuval Mintz } 836fe56b9e6SYuval Mintz 83739651abdSSudarsana Reddy Kalluru /* This function reconfigures the QM pf on the fly. 83839651abdSSudarsana Reddy Kalluru * For this purpose we: 83939651abdSSudarsana Reddy Kalluru * 1. reconfigure the QM database 840a2e7699eSTomer Tayar * 2. set new values to runtime array 84139651abdSSudarsana Reddy Kalluru * 3. send an sdm_qm_cmd through the rbc interface to stop the QM 84239651abdSSudarsana Reddy Kalluru * 4. activate init tool in QM_PF stage 84339651abdSSudarsana Reddy Kalluru * 5. send an sdm_qm_cmd through rbc interface to release the QM 84439651abdSSudarsana Reddy Kalluru */ 84539651abdSSudarsana Reddy Kalluru int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 84639651abdSSudarsana Reddy Kalluru { 84739651abdSSudarsana Reddy Kalluru struct qed_qm_info *qm_info = &p_hwfn->qm_info; 84839651abdSSudarsana Reddy Kalluru bool b_rc; 84939651abdSSudarsana Reddy Kalluru int rc; 85039651abdSSudarsana Reddy Kalluru 85139651abdSSudarsana Reddy Kalluru /* initialize qed's qm data structure */ 852b5a9ee7cSAriel Elior qed_init_qm_info(p_hwfn); 85339651abdSSudarsana Reddy Kalluru 85439651abdSSudarsana Reddy Kalluru /* stop PF's qm queues */ 85539651abdSSudarsana Reddy Kalluru spin_lock_bh(&qm_lock); 85639651abdSSudarsana Reddy Kalluru b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true, 85739651abdSSudarsana Reddy Kalluru qm_info->start_pq, qm_info->num_pqs); 85839651abdSSudarsana Reddy Kalluru spin_unlock_bh(&qm_lock); 85939651abdSSudarsana Reddy Kalluru if (!b_rc) 86039651abdSSudarsana Reddy Kalluru return -EINVAL; 86139651abdSSudarsana Reddy Kalluru 86239651abdSSudarsana Reddy Kalluru /* clear the QM_PF runtime phase leftovers from previous init */ 86339651abdSSudarsana Reddy Kalluru qed_init_clear_rt_data(p_hwfn); 86439651abdSSudarsana Reddy Kalluru 86539651abdSSudarsana Reddy Kalluru /* prepare QM portion of runtime array */ 866da090917STomer Tayar qed_qm_init_pf(p_hwfn, p_ptt, false); 86739651abdSSudarsana Reddy Kalluru 86839651abdSSudarsana Reddy Kalluru /* activate init tool on runtime array */ 86939651abdSSudarsana Reddy Kalluru rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id, 87039651abdSSudarsana Reddy Kalluru p_hwfn->hw_info.hw_mode); 87139651abdSSudarsana Reddy Kalluru if (rc) 87239651abdSSudarsana Reddy Kalluru return rc; 87339651abdSSudarsana Reddy Kalluru 87439651abdSSudarsana Reddy Kalluru /* start PF's qm queues */ 87539651abdSSudarsana Reddy Kalluru spin_lock_bh(&qm_lock); 87639651abdSSudarsana Reddy Kalluru b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true, 87739651abdSSudarsana Reddy Kalluru qm_info->start_pq, qm_info->num_pqs); 87839651abdSSudarsana Reddy Kalluru spin_unlock_bh(&qm_lock); 87939651abdSSudarsana Reddy Kalluru if (!b_rc) 88039651abdSSudarsana Reddy Kalluru return -EINVAL; 88139651abdSSudarsana Reddy Kalluru 88239651abdSSudarsana Reddy Kalluru return 0; 88339651abdSSudarsana Reddy Kalluru } 88439651abdSSudarsana Reddy Kalluru 885b5a9ee7cSAriel Elior static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn) 886b5a9ee7cSAriel Elior { 887b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 888b5a9ee7cSAriel Elior int rc; 889b5a9ee7cSAriel Elior 890b5a9ee7cSAriel Elior rc = qed_init_qm_sanity(p_hwfn); 891b5a9ee7cSAriel Elior if (rc) 892b5a9ee7cSAriel Elior goto alloc_err; 893b5a9ee7cSAriel Elior 8946396bb22SKees Cook qm_info->qm_pq_params = kcalloc(qed_init_qm_get_num_pqs(p_hwfn), 8956396bb22SKees Cook sizeof(*qm_info->qm_pq_params), 896b5a9ee7cSAriel Elior GFP_KERNEL); 897b5a9ee7cSAriel Elior if (!qm_info->qm_pq_params) 898b5a9ee7cSAriel Elior goto alloc_err; 899b5a9ee7cSAriel Elior 9006396bb22SKees Cook qm_info->qm_vport_params = kcalloc(qed_init_qm_get_num_vports(p_hwfn), 9016396bb22SKees Cook sizeof(*qm_info->qm_vport_params), 902b5a9ee7cSAriel Elior GFP_KERNEL); 903b5a9ee7cSAriel Elior if (!qm_info->qm_vport_params) 904b5a9ee7cSAriel Elior goto alloc_err; 905b5a9ee7cSAriel Elior 9066396bb22SKees Cook qm_info->qm_port_params = kcalloc(p_hwfn->cdev->num_ports_in_engine, 9076396bb22SKees Cook sizeof(*qm_info->qm_port_params), 908b5a9ee7cSAriel Elior GFP_KERNEL); 909b5a9ee7cSAriel Elior if (!qm_info->qm_port_params) 910b5a9ee7cSAriel Elior goto alloc_err; 911b5a9ee7cSAriel Elior 9126396bb22SKees Cook qm_info->wfq_data = kcalloc(qed_init_qm_get_num_vports(p_hwfn), 9136396bb22SKees Cook sizeof(*qm_info->wfq_data), 914b5a9ee7cSAriel Elior GFP_KERNEL); 915b5a9ee7cSAriel Elior if (!qm_info->wfq_data) 916b5a9ee7cSAriel Elior goto alloc_err; 917b5a9ee7cSAriel Elior 918b5a9ee7cSAriel Elior return 0; 919b5a9ee7cSAriel Elior 920b5a9ee7cSAriel Elior alloc_err: 921b5a9ee7cSAriel Elior DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n"); 922b5a9ee7cSAriel Elior qed_qm_info_free(p_hwfn); 923b5a9ee7cSAriel Elior return -ENOMEM; 924b5a9ee7cSAriel Elior } 925b5a9ee7cSAriel Elior 926fe56b9e6SYuval Mintz int qed_resc_alloc(struct qed_dev *cdev) 927fe56b9e6SYuval Mintz { 928f9dc4d1fSRam Amrani u32 rdma_tasks, excess_tasks; 929f9dc4d1fSRam Amrani u32 line_count; 930fe56b9e6SYuval Mintz int i, rc = 0; 931fe56b9e6SYuval Mintz 9320db711bbSMintz, Yuval if (IS_VF(cdev)) { 9330db711bbSMintz, Yuval for_each_hwfn(cdev, i) { 9340db711bbSMintz, Yuval rc = qed_l2_alloc(&cdev->hwfns[i]); 9350db711bbSMintz, Yuval if (rc) 9361408cc1fSYuval Mintz return rc; 9370db711bbSMintz, Yuval } 9380db711bbSMintz, Yuval return rc; 9390db711bbSMintz, Yuval } 9401408cc1fSYuval Mintz 941fe56b9e6SYuval Mintz cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL); 942fe56b9e6SYuval Mintz if (!cdev->fw_data) 943fe56b9e6SYuval Mintz return -ENOMEM; 944fe56b9e6SYuval Mintz 945fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 946fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 947dbb799c3SYuval Mintz u32 n_eqes, num_cons; 948fe56b9e6SYuval Mintz 949fe56b9e6SYuval Mintz /* First allocate the context manager structure */ 950fe56b9e6SYuval Mintz rc = qed_cxt_mngr_alloc(p_hwfn); 951fe56b9e6SYuval Mintz if (rc) 952fe56b9e6SYuval Mintz goto alloc_err; 953fe56b9e6SYuval Mintz 954fe56b9e6SYuval Mintz /* Set the HW cid/tid numbers (in the contest manager) 955fe56b9e6SYuval Mintz * Must be done prior to any further computations. 956fe56b9e6SYuval Mintz */ 957f9dc4d1fSRam Amrani rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS); 958fe56b9e6SYuval Mintz if (rc) 959fe56b9e6SYuval Mintz goto alloc_err; 960fe56b9e6SYuval Mintz 961b5a9ee7cSAriel Elior rc = qed_alloc_qm_data(p_hwfn); 962fe56b9e6SYuval Mintz if (rc) 963fe56b9e6SYuval Mintz goto alloc_err; 964fe56b9e6SYuval Mintz 965b5a9ee7cSAriel Elior /* init qm info */ 966b5a9ee7cSAriel Elior qed_init_qm_info(p_hwfn); 967b5a9ee7cSAriel Elior 968fe56b9e6SYuval Mintz /* Compute the ILT client partition */ 969f9dc4d1fSRam Amrani rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count); 970f9dc4d1fSRam Amrani if (rc) { 971f9dc4d1fSRam Amrani DP_NOTICE(p_hwfn, 972f9dc4d1fSRam Amrani "too many ILT lines; re-computing with less lines\n"); 973f9dc4d1fSRam Amrani /* In case there are not enough ILT lines we reduce the 974f9dc4d1fSRam Amrani * number of RDMA tasks and re-compute. 975f9dc4d1fSRam Amrani */ 976f9dc4d1fSRam Amrani excess_tasks = 977f9dc4d1fSRam Amrani qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count); 978f9dc4d1fSRam Amrani if (!excess_tasks) 979f9dc4d1fSRam Amrani goto alloc_err; 980f9dc4d1fSRam Amrani 981f9dc4d1fSRam Amrani rdma_tasks = RDMA_MAX_TIDS - excess_tasks; 982f9dc4d1fSRam Amrani rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks); 983fe56b9e6SYuval Mintz if (rc) 984fe56b9e6SYuval Mintz goto alloc_err; 985fe56b9e6SYuval Mintz 986f9dc4d1fSRam Amrani rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count); 987f9dc4d1fSRam Amrani if (rc) { 988f9dc4d1fSRam Amrani DP_ERR(p_hwfn, 989f9dc4d1fSRam Amrani "failed ILT compute. Requested too many lines: %u\n", 990f9dc4d1fSRam Amrani line_count); 991f9dc4d1fSRam Amrani 992f9dc4d1fSRam Amrani goto alloc_err; 993f9dc4d1fSRam Amrani } 994f9dc4d1fSRam Amrani } 995f9dc4d1fSRam Amrani 996fe56b9e6SYuval Mintz /* CID map / ILT shadow table / T2 997fe56b9e6SYuval Mintz * The talbes sizes are determined by the computations above 998fe56b9e6SYuval Mintz */ 999fe56b9e6SYuval Mintz rc = qed_cxt_tables_alloc(p_hwfn); 1000fe56b9e6SYuval Mintz if (rc) 1001fe56b9e6SYuval Mintz goto alloc_err; 1002fe56b9e6SYuval Mintz 1003fe56b9e6SYuval Mintz /* SPQ, must follow ILT because initializes SPQ context */ 1004fe56b9e6SYuval Mintz rc = qed_spq_alloc(p_hwfn); 1005fe56b9e6SYuval Mintz if (rc) 1006fe56b9e6SYuval Mintz goto alloc_err; 1007fe56b9e6SYuval Mintz 1008fe56b9e6SYuval Mintz /* SP status block allocation */ 1009fe56b9e6SYuval Mintz p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn, 1010fe56b9e6SYuval Mintz RESERVED_PTT_DPC); 1011fe56b9e6SYuval Mintz 1012fe56b9e6SYuval Mintz rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt); 1013fe56b9e6SYuval Mintz if (rc) 1014fe56b9e6SYuval Mintz goto alloc_err; 1015fe56b9e6SYuval Mintz 101632a47e72SYuval Mintz rc = qed_iov_alloc(p_hwfn); 101732a47e72SYuval Mintz if (rc) 101832a47e72SYuval Mintz goto alloc_err; 101932a47e72SYuval Mintz 1020fe56b9e6SYuval Mintz /* EQ */ 1021dbb799c3SYuval Mintz n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain); 1022c851a9dcSKalderon, Michal if (QED_IS_RDMA_PERSONALITY(p_hwfn)) { 102367b40dccSKalderon, Michal enum protocol_type rdma_proto; 102467b40dccSKalderon, Michal 102567b40dccSKalderon, Michal if (QED_IS_ROCE_PERSONALITY(p_hwfn)) 102667b40dccSKalderon, Michal rdma_proto = PROTOCOLID_ROCE; 102767b40dccSKalderon, Michal else 102867b40dccSKalderon, Michal rdma_proto = PROTOCOLID_IWARP; 102967b40dccSKalderon, Michal 1030dbb799c3SYuval Mintz num_cons = qed_cxt_get_proto_cid_count(p_hwfn, 103167b40dccSKalderon, Michal rdma_proto, 10328c93beafSYuval Mintz NULL) * 2; 1033dbb799c3SYuval Mintz n_eqes += num_cons + 2 * MAX_NUM_VFS_BB; 1034dbb799c3SYuval Mintz } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 1035dbb799c3SYuval Mintz num_cons = 1036dbb799c3SYuval Mintz qed_cxt_get_proto_cid_count(p_hwfn, 10378c93beafSYuval Mintz PROTOCOLID_ISCSI, 10388c93beafSYuval Mintz NULL); 1039dbb799c3SYuval Mintz n_eqes += 2 * num_cons; 1040dbb799c3SYuval Mintz } 1041dbb799c3SYuval Mintz 1042dbb799c3SYuval Mintz if (n_eqes > 0xFFFF) { 1043dbb799c3SYuval Mintz DP_ERR(p_hwfn, 1044dbb799c3SYuval Mintz "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n", 1045dbb799c3SYuval Mintz n_eqes, 0xFFFF); 10463587cb87STomer Tayar goto alloc_no_mem; 10479b15acbfSDan Carpenter } 1048dbb799c3SYuval Mintz 10493587cb87STomer Tayar rc = qed_eq_alloc(p_hwfn, (u16) n_eqes); 10503587cb87STomer Tayar if (rc) 10513587cb87STomer Tayar goto alloc_err; 1052fe56b9e6SYuval Mintz 10533587cb87STomer Tayar rc = qed_consq_alloc(p_hwfn); 10543587cb87STomer Tayar if (rc) 10553587cb87STomer Tayar goto alloc_err; 1056fe56b9e6SYuval Mintz 10570db711bbSMintz, Yuval rc = qed_l2_alloc(p_hwfn); 10580db711bbSMintz, Yuval if (rc) 10590db711bbSMintz, Yuval goto alloc_err; 10600db711bbSMintz, Yuval 10610a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 10620a7fb11cSYuval Mintz if (p_hwfn->using_ll2) { 10633587cb87STomer Tayar rc = qed_ll2_alloc(p_hwfn); 10643587cb87STomer Tayar if (rc) 10653587cb87STomer Tayar goto alloc_err; 10660a7fb11cSYuval Mintz } 10670a7fb11cSYuval Mintz #endif 10681e128c81SArun Easi 10691e128c81SArun Easi if (p_hwfn->hw_info.personality == QED_PCI_FCOE) { 10703587cb87STomer Tayar rc = qed_fcoe_alloc(p_hwfn); 10713587cb87STomer Tayar if (rc) 10723587cb87STomer Tayar goto alloc_err; 10731e128c81SArun Easi } 10741e128c81SArun Easi 1075fc831825SYuval Mintz if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 10763587cb87STomer Tayar rc = qed_iscsi_alloc(p_hwfn); 10773587cb87STomer Tayar if (rc) 10783587cb87STomer Tayar goto alloc_err; 10793587cb87STomer Tayar rc = qed_ooo_alloc(p_hwfn); 10803587cb87STomer Tayar if (rc) 10813587cb87STomer Tayar goto alloc_err; 1082fc831825SYuval Mintz } 10830a7fb11cSYuval Mintz 1084fe56b9e6SYuval Mintz /* DMA info initialization */ 1085fe56b9e6SYuval Mintz rc = qed_dmae_info_alloc(p_hwfn); 10862591c280SJoe Perches if (rc) 1087fe56b9e6SYuval Mintz goto alloc_err; 108839651abdSSudarsana Reddy Kalluru 108939651abdSSudarsana Reddy Kalluru /* DCBX initialization */ 109039651abdSSudarsana Reddy Kalluru rc = qed_dcbx_info_alloc(p_hwfn); 10912591c280SJoe Perches if (rc) 109239651abdSSudarsana Reddy Kalluru goto alloc_err; 1093a3f72307SDenis Bolotin 1094a3f72307SDenis Bolotin rc = qed_dbg_alloc_user_data(p_hwfn); 1095a3f72307SDenis Bolotin if (rc) 1096a3f72307SDenis Bolotin goto alloc_err; 109739651abdSSudarsana Reddy Kalluru } 1098fe56b9e6SYuval Mintz 1099fe56b9e6SYuval Mintz cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL); 11002591c280SJoe Perches if (!cdev->reset_stats) 110183aeb933SYuval Mintz goto alloc_no_mem; 1102fe56b9e6SYuval Mintz 1103fe56b9e6SYuval Mintz return 0; 1104fe56b9e6SYuval Mintz 1105dbb799c3SYuval Mintz alloc_no_mem: 1106dbb799c3SYuval Mintz rc = -ENOMEM; 1107fe56b9e6SYuval Mintz alloc_err: 1108fe56b9e6SYuval Mintz qed_resc_free(cdev); 1109fe56b9e6SYuval Mintz return rc; 1110fe56b9e6SYuval Mintz } 1111fe56b9e6SYuval Mintz 1112fe56b9e6SYuval Mintz void qed_resc_setup(struct qed_dev *cdev) 1113fe56b9e6SYuval Mintz { 1114fe56b9e6SYuval Mintz int i; 1115fe56b9e6SYuval Mintz 11160db711bbSMintz, Yuval if (IS_VF(cdev)) { 11170db711bbSMintz, Yuval for_each_hwfn(cdev, i) 11180db711bbSMintz, Yuval qed_l2_setup(&cdev->hwfns[i]); 11191408cc1fSYuval Mintz return; 11200db711bbSMintz, Yuval } 11211408cc1fSYuval Mintz 1122fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 1123fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1124fe56b9e6SYuval Mintz 1125fe56b9e6SYuval Mintz qed_cxt_mngr_setup(p_hwfn); 1126fe56b9e6SYuval Mintz qed_spq_setup(p_hwfn); 11273587cb87STomer Tayar qed_eq_setup(p_hwfn); 11283587cb87STomer Tayar qed_consq_setup(p_hwfn); 1129fe56b9e6SYuval Mintz 1130fe56b9e6SYuval Mintz /* Read shadow of current MFW mailbox */ 1131fe56b9e6SYuval Mintz qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt); 1132fe56b9e6SYuval Mintz memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 1133fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_cur, 1134fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_length); 1135fe56b9e6SYuval Mintz 1136fe56b9e6SYuval Mintz qed_int_setup(p_hwfn, p_hwfn->p_main_ptt); 113732a47e72SYuval Mintz 11380db711bbSMintz, Yuval qed_l2_setup(p_hwfn); 11391ee240e3SMintz, Yuval qed_iov_setup(p_hwfn); 11400a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 11410a7fb11cSYuval Mintz if (p_hwfn->using_ll2) 11423587cb87STomer Tayar qed_ll2_setup(p_hwfn); 11430a7fb11cSYuval Mintz #endif 11441e128c81SArun Easi if (p_hwfn->hw_info.personality == QED_PCI_FCOE) 11453587cb87STomer Tayar qed_fcoe_setup(p_hwfn); 11461e128c81SArun Easi 11471d6cff4fSYuval Mintz if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 11483587cb87STomer Tayar qed_iscsi_setup(p_hwfn); 11493587cb87STomer Tayar qed_ooo_setup(p_hwfn); 11501d6cff4fSYuval Mintz } 1151fe56b9e6SYuval Mintz } 1152fe56b9e6SYuval Mintz } 1153fe56b9e6SYuval Mintz 1154fe56b9e6SYuval Mintz #define FINAL_CLEANUP_POLL_CNT (100) 1155fe56b9e6SYuval Mintz #define FINAL_CLEANUP_POLL_TIME (10) 1156fe56b9e6SYuval Mintz int qed_final_cleanup(struct qed_hwfn *p_hwfn, 11570b55e27dSYuval Mintz struct qed_ptt *p_ptt, u16 id, bool is_vf) 1158fe56b9e6SYuval Mintz { 1159fe56b9e6SYuval Mintz u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT; 1160fe56b9e6SYuval Mintz int rc = -EBUSY; 1161fe56b9e6SYuval Mintz 1162fc48b7a6SYuval Mintz addr = GTT_BAR0_MAP_REG_USDM_RAM + 1163fc48b7a6SYuval Mintz USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id); 1164fe56b9e6SYuval Mintz 11650b55e27dSYuval Mintz if (is_vf) 11660b55e27dSYuval Mintz id += 0x10; 11670b55e27dSYuval Mintz 1168fc48b7a6SYuval Mintz command |= X_FINAL_CLEANUP_AGG_INT << 1169fc48b7a6SYuval Mintz SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT; 1170fc48b7a6SYuval Mintz command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT; 1171fc48b7a6SYuval Mintz command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT; 1172fc48b7a6SYuval Mintz command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT; 1173fe56b9e6SYuval Mintz 1174fe56b9e6SYuval Mintz /* Make sure notification is not set before initiating final cleanup */ 1175fe56b9e6SYuval Mintz if (REG_RD(p_hwfn, addr)) { 11761a635e48SYuval Mintz DP_NOTICE(p_hwfn, 1177fe56b9e6SYuval Mintz "Unexpected; Found final cleanup notification before initiating final cleanup\n"); 1178fe56b9e6SYuval Mintz REG_WR(p_hwfn, addr, 0); 1179fe56b9e6SYuval Mintz } 1180fe56b9e6SYuval Mintz 1181fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_IOV, 1182d602de8eSJoe Perches "Sending final cleanup for PFVF[%d] [Command %08x]\n", 1183fe56b9e6SYuval Mintz id, command); 1184fe56b9e6SYuval Mintz 1185fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command); 1186fe56b9e6SYuval Mintz 1187fe56b9e6SYuval Mintz /* Poll until completion */ 1188fe56b9e6SYuval Mintz while (!REG_RD(p_hwfn, addr) && count--) 1189fe56b9e6SYuval Mintz msleep(FINAL_CLEANUP_POLL_TIME); 1190fe56b9e6SYuval Mintz 1191fe56b9e6SYuval Mintz if (REG_RD(p_hwfn, addr)) 1192fe56b9e6SYuval Mintz rc = 0; 1193fe56b9e6SYuval Mintz else 1194fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 1195fe56b9e6SYuval Mintz "Failed to receive FW final cleanup notification\n"); 1196fe56b9e6SYuval Mintz 1197fe56b9e6SYuval Mintz /* Cleanup afterwards */ 1198fe56b9e6SYuval Mintz REG_WR(p_hwfn, addr, 0); 1199fe56b9e6SYuval Mintz 1200fe56b9e6SYuval Mintz return rc; 1201fe56b9e6SYuval Mintz } 1202fe56b9e6SYuval Mintz 12039c79ddaaSMintz, Yuval static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn) 1204fe56b9e6SYuval Mintz { 1205fe56b9e6SYuval Mintz int hw_mode = 0; 1206fe56b9e6SYuval Mintz 12079c79ddaaSMintz, Yuval if (QED_IS_BB_B0(p_hwfn->cdev)) { 12089c79ddaaSMintz, Yuval hw_mode |= 1 << MODE_BB; 12099c79ddaaSMintz, Yuval } else if (QED_IS_AH(p_hwfn->cdev)) { 12109c79ddaaSMintz, Yuval hw_mode |= 1 << MODE_K2; 12119c79ddaaSMintz, Yuval } else { 12129c79ddaaSMintz, Yuval DP_NOTICE(p_hwfn, "Unknown chip type %#x\n", 12139c79ddaaSMintz, Yuval p_hwfn->cdev->type); 12149c79ddaaSMintz, Yuval return -EINVAL; 12159c79ddaaSMintz, Yuval } 1216fe56b9e6SYuval Mintz 121778cea9ffSTomer Tayar switch (p_hwfn->cdev->num_ports_in_engine) { 1218fe56b9e6SYuval Mintz case 1: 1219fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_PORTS_PER_ENG_1; 1220fe56b9e6SYuval Mintz break; 1221fe56b9e6SYuval Mintz case 2: 1222fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_PORTS_PER_ENG_2; 1223fe56b9e6SYuval Mintz break; 1224fe56b9e6SYuval Mintz case 4: 1225fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_PORTS_PER_ENG_4; 1226fe56b9e6SYuval Mintz break; 1227fe56b9e6SYuval Mintz default: 1228fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n", 122978cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine); 12309c79ddaaSMintz, Yuval return -EINVAL; 1231fe56b9e6SYuval Mintz } 1232fe56b9e6SYuval Mintz 12330bc5fe85SSudarsana Reddy Kalluru if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits)) 1234fc48b7a6SYuval Mintz hw_mode |= 1 << MODE_MF_SD; 12350bc5fe85SSudarsana Reddy Kalluru else 1236fc48b7a6SYuval Mintz hw_mode |= 1 << MODE_MF_SI; 1237fe56b9e6SYuval Mintz 1238fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_ASIC; 1239fe56b9e6SYuval Mintz 12401af9dcf7SYuval Mintz if (p_hwfn->cdev->num_hwfns > 1) 12411af9dcf7SYuval Mintz hw_mode |= 1 << MODE_100G; 12421af9dcf7SYuval Mintz 1243fe56b9e6SYuval Mintz p_hwfn->hw_info.hw_mode = hw_mode; 12441af9dcf7SYuval Mintz 12451af9dcf7SYuval Mintz DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP), 12461af9dcf7SYuval Mintz "Configuring function for hw_mode: 0x%08x\n", 12471af9dcf7SYuval Mintz p_hwfn->hw_info.hw_mode); 12489c79ddaaSMintz, Yuval 12499c79ddaaSMintz, Yuval return 0; 1250fe56b9e6SYuval Mintz } 1251fe56b9e6SYuval Mintz 1252fe56b9e6SYuval Mintz /* Init run time data for all PFs on an engine. */ 1253fe56b9e6SYuval Mintz static void qed_init_cau_rt_data(struct qed_dev *cdev) 1254fe56b9e6SYuval Mintz { 1255fe56b9e6SYuval Mintz u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET; 1256d031548eSMintz, Yuval int i, igu_sb_id; 1257fe56b9e6SYuval Mintz 1258fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 1259fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1260fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 1261fe56b9e6SYuval Mintz struct qed_igu_block *p_block; 1262fe56b9e6SYuval Mintz struct cau_sb_entry sb_entry; 1263fe56b9e6SYuval Mintz 1264fe56b9e6SYuval Mintz p_igu_info = p_hwfn->hw_info.p_igu_info; 1265fe56b9e6SYuval Mintz 1266d031548eSMintz, Yuval for (igu_sb_id = 0; 1267d031548eSMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) { 1268d031548eSMintz, Yuval p_block = &p_igu_info->entry[igu_sb_id]; 1269d031548eSMintz, Yuval 1270fe56b9e6SYuval Mintz if (!p_block->is_pf) 1271fe56b9e6SYuval Mintz continue; 1272fe56b9e6SYuval Mintz 1273fe56b9e6SYuval Mintz qed_init_cau_sb_entry(p_hwfn, &sb_entry, 12741a635e48SYuval Mintz p_block->function_id, 0, 0); 1275d031548eSMintz, Yuval STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2, 1276d031548eSMintz, Yuval sb_entry); 1277fe56b9e6SYuval Mintz } 1278fe56b9e6SYuval Mintz } 1279fe56b9e6SYuval Mintz } 1280fe56b9e6SYuval Mintz 128160afed72STomer Tayar static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn, 128260afed72STomer Tayar struct qed_ptt *p_ptt) 128360afed72STomer Tayar { 128460afed72STomer Tayar u32 val, wr_mbs, cache_line_size; 128560afed72STomer Tayar 128660afed72STomer Tayar val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0); 128760afed72STomer Tayar switch (val) { 128860afed72STomer Tayar case 0: 128960afed72STomer Tayar wr_mbs = 128; 129060afed72STomer Tayar break; 129160afed72STomer Tayar case 1: 129260afed72STomer Tayar wr_mbs = 256; 129360afed72STomer Tayar break; 129460afed72STomer Tayar case 2: 129560afed72STomer Tayar wr_mbs = 512; 129660afed72STomer Tayar break; 129760afed72STomer Tayar default: 129860afed72STomer Tayar DP_INFO(p_hwfn, 129960afed72STomer Tayar "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n", 130060afed72STomer Tayar val); 130160afed72STomer Tayar return; 130260afed72STomer Tayar } 130360afed72STomer Tayar 130460afed72STomer Tayar cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs); 130560afed72STomer Tayar switch (cache_line_size) { 130660afed72STomer Tayar case 32: 130760afed72STomer Tayar val = 0; 130860afed72STomer Tayar break; 130960afed72STomer Tayar case 64: 131060afed72STomer Tayar val = 1; 131160afed72STomer Tayar break; 131260afed72STomer Tayar case 128: 131360afed72STomer Tayar val = 2; 131460afed72STomer Tayar break; 131560afed72STomer Tayar case 256: 131660afed72STomer Tayar val = 3; 131760afed72STomer Tayar break; 131860afed72STomer Tayar default: 131960afed72STomer Tayar DP_INFO(p_hwfn, 132060afed72STomer Tayar "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n", 132160afed72STomer Tayar cache_line_size); 132260afed72STomer Tayar } 132360afed72STomer Tayar 132460afed72STomer Tayar if (L1_CACHE_BYTES > wr_mbs) 132560afed72STomer Tayar DP_INFO(p_hwfn, 132660afed72STomer Tayar "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n", 132760afed72STomer Tayar L1_CACHE_BYTES, wr_mbs); 132860afed72STomer Tayar 132960afed72STomer Tayar STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val); 1330fc6575bcSMintz, Yuval if (val > 0) { 1331fc6575bcSMintz, Yuval STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val); 1332fc6575bcSMintz, Yuval STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val); 1333fc6575bcSMintz, Yuval } 133460afed72STomer Tayar } 133560afed72STomer Tayar 1336fe56b9e6SYuval Mintz static int qed_hw_init_common(struct qed_hwfn *p_hwfn, 13371a635e48SYuval Mintz struct qed_ptt *p_ptt, int hw_mode) 1338fe56b9e6SYuval Mintz { 1339fe56b9e6SYuval Mintz struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1340fe56b9e6SYuval Mintz struct qed_qm_common_rt_init_params params; 1341fe56b9e6SYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 13429c79ddaaSMintz, Yuval u8 vf_id, max_num_vfs; 1343dbb799c3SYuval Mintz u16 num_pfs, pf_id; 13441408cc1fSYuval Mintz u32 concrete_fid; 1345fe56b9e6SYuval Mintz int rc = 0; 1346fe56b9e6SYuval Mintz 1347fe56b9e6SYuval Mintz qed_init_cau_rt_data(cdev); 1348fe56b9e6SYuval Mintz 1349fe56b9e6SYuval Mintz /* Program GTT windows */ 1350fe56b9e6SYuval Mintz qed_gtt_init(p_hwfn); 1351fe56b9e6SYuval Mintz 1352fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 1353fe56b9e6SYuval Mintz if (p_hwfn->mcp_info->func_info.bandwidth_max) 1354c7281d59SGustavo A. R. Silva qm_info->pf_rl_en = true; 1355fe56b9e6SYuval Mintz if (p_hwfn->mcp_info->func_info.bandwidth_min) 1356c7281d59SGustavo A. R. Silva qm_info->pf_wfq_en = true; 1357fe56b9e6SYuval Mintz } 1358fe56b9e6SYuval Mintz 1359fe56b9e6SYuval Mintz memset(¶ms, 0, sizeof(params)); 136078cea9ffSTomer Tayar params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine; 1361fe56b9e6SYuval Mintz params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port; 1362fe56b9e6SYuval Mintz params.pf_rl_en = qm_info->pf_rl_en; 1363fe56b9e6SYuval Mintz params.pf_wfq_en = qm_info->pf_wfq_en; 1364fe56b9e6SYuval Mintz params.vport_rl_en = qm_info->vport_rl_en; 1365fe56b9e6SYuval Mintz params.vport_wfq_en = qm_info->vport_wfq_en; 1366fe56b9e6SYuval Mintz params.port_params = qm_info->qm_port_params; 1367fe56b9e6SYuval Mintz 1368fe56b9e6SYuval Mintz qed_qm_common_rt_init(p_hwfn, ¶ms); 1369fe56b9e6SYuval Mintz 1370fe56b9e6SYuval Mintz qed_cxt_hw_init_common(p_hwfn); 1371fe56b9e6SYuval Mintz 137260afed72STomer Tayar qed_init_cache_line_size(p_hwfn, p_ptt); 137360afed72STomer Tayar 1374fe56b9e6SYuval Mintz rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode); 13751a635e48SYuval Mintz if (rc) 1376fe56b9e6SYuval Mintz return rc; 1377fe56b9e6SYuval Mintz 1378fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0); 1379fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1); 1380fe56b9e6SYuval Mintz 1381dbb799c3SYuval Mintz if (QED_IS_BB(p_hwfn->cdev)) { 1382dbb799c3SYuval Mintz num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev); 1383dbb799c3SYuval Mintz for (pf_id = 0; pf_id < num_pfs; pf_id++) { 1384dbb799c3SYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, pf_id); 1385dbb799c3SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1386dbb799c3SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1387dbb799c3SYuval Mintz } 1388dbb799c3SYuval Mintz /* pretend to original PF */ 1389dbb799c3SYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 1390dbb799c3SYuval Mintz } 1391fe56b9e6SYuval Mintz 13929c79ddaaSMintz, Yuval max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB; 13939c79ddaaSMintz, Yuval for (vf_id = 0; vf_id < max_num_vfs; vf_id++) { 13941408cc1fSYuval Mintz concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id); 13951408cc1fSYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid); 13961408cc1fSYuval Mintz qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1); 139705fafbfbSYuval Mintz qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0); 139805fafbfbSYuval Mintz qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1); 139905fafbfbSYuval Mintz qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0); 14001408cc1fSYuval Mintz } 14011408cc1fSYuval Mintz /* pretend to original PF */ 14021408cc1fSYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 14031408cc1fSYuval Mintz 1404fe56b9e6SYuval Mintz return rc; 1405fe56b9e6SYuval Mintz } 1406fe56b9e6SYuval Mintz 140751ff1725SRam Amrani static int 140851ff1725SRam Amrani qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn, 140951ff1725SRam Amrani struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus) 141051ff1725SRam Amrani { 1411107392b7SRam Amrani u32 dpi_bit_shift, dpi_count, dpi_page_size; 141251ff1725SRam Amrani u32 min_dpis; 1413107392b7SRam Amrani u32 n_wids; 141451ff1725SRam Amrani 141551ff1725SRam Amrani /* Calculate DPI size */ 1416107392b7SRam Amrani n_wids = max_t(u32, QED_MIN_WIDS, n_cpus); 1417107392b7SRam Amrani dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids); 1418107392b7SRam Amrani dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1); 141951ff1725SRam Amrani dpi_bit_shift = ilog2(dpi_page_size / 4096); 142051ff1725SRam Amrani dpi_count = pwm_region_size / dpi_page_size; 142151ff1725SRam Amrani 142251ff1725SRam Amrani min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis; 142351ff1725SRam Amrani min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis); 142451ff1725SRam Amrani 142551ff1725SRam Amrani p_hwfn->dpi_size = dpi_page_size; 142651ff1725SRam Amrani p_hwfn->dpi_count = dpi_count; 142751ff1725SRam Amrani 142851ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift); 142951ff1725SRam Amrani 143051ff1725SRam Amrani if (dpi_count < min_dpis) 143151ff1725SRam Amrani return -EINVAL; 143251ff1725SRam Amrani 143351ff1725SRam Amrani return 0; 143451ff1725SRam Amrani } 143551ff1725SRam Amrani 143651ff1725SRam Amrani enum QED_ROCE_EDPM_MODE { 143751ff1725SRam Amrani QED_ROCE_EDPM_MODE_ENABLE = 0, 143851ff1725SRam Amrani QED_ROCE_EDPM_MODE_FORCE_ON = 1, 143951ff1725SRam Amrani QED_ROCE_EDPM_MODE_DISABLE = 2, 144051ff1725SRam Amrani }; 144151ff1725SRam Amrani 144251ff1725SRam Amrani static int 144351ff1725SRam Amrani qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 144451ff1725SRam Amrani { 144551ff1725SRam Amrani u32 pwm_regsize, norm_regsize; 144651ff1725SRam Amrani u32 non_pwm_conn, min_addr_reg1; 144720b1bd96SRam Amrani u32 db_bar_size, n_cpus = 1; 144851ff1725SRam Amrani u32 roce_edpm_mode; 144951ff1725SRam Amrani u32 pf_dems_shift; 145051ff1725SRam Amrani int rc = 0; 145151ff1725SRam Amrani u8 cond; 145251ff1725SRam Amrani 145315582962SRahul Verma db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1); 145451ff1725SRam Amrani if (p_hwfn->cdev->num_hwfns > 1) 145551ff1725SRam Amrani db_bar_size /= 2; 145651ff1725SRam Amrani 145751ff1725SRam Amrani /* Calculate doorbell regions */ 145851ff1725SRam Amrani non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) + 145951ff1725SRam Amrani qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE, 146051ff1725SRam Amrani NULL) + 146151ff1725SRam Amrani qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, 146251ff1725SRam Amrani NULL); 1463a82dadbcSRam Amrani norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE); 146451ff1725SRam Amrani min_addr_reg1 = norm_regsize / 4096; 146551ff1725SRam Amrani pwm_regsize = db_bar_size - norm_regsize; 146651ff1725SRam Amrani 146751ff1725SRam Amrani /* Check that the normal and PWM sizes are valid */ 146851ff1725SRam Amrani if (db_bar_size < norm_regsize) { 146951ff1725SRam Amrani DP_ERR(p_hwfn->cdev, 147051ff1725SRam Amrani "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n", 147151ff1725SRam Amrani db_bar_size, norm_regsize); 147251ff1725SRam Amrani return -EINVAL; 147351ff1725SRam Amrani } 147451ff1725SRam Amrani 147551ff1725SRam Amrani if (pwm_regsize < QED_MIN_PWM_REGION) { 147651ff1725SRam Amrani DP_ERR(p_hwfn->cdev, 147751ff1725SRam Amrani "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n", 147851ff1725SRam Amrani pwm_regsize, 147951ff1725SRam Amrani QED_MIN_PWM_REGION, db_bar_size, norm_regsize); 148051ff1725SRam Amrani return -EINVAL; 148151ff1725SRam Amrani } 148251ff1725SRam Amrani 148351ff1725SRam Amrani /* Calculate number of DPIs */ 148451ff1725SRam Amrani roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode; 148551ff1725SRam Amrani if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) || 148651ff1725SRam Amrani ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) { 148751ff1725SRam Amrani /* Either EDPM is mandatory, or we are attempting to allocate a 148851ff1725SRam Amrani * WID per CPU. 148951ff1725SRam Amrani */ 1490c2dedf87SRam Amrani n_cpus = num_present_cpus(); 149151ff1725SRam Amrani rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 149251ff1725SRam Amrani } 149351ff1725SRam Amrani 149451ff1725SRam Amrani cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) || 149551ff1725SRam Amrani (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE); 149651ff1725SRam Amrani if (cond || p_hwfn->dcbx_no_edpm) { 149751ff1725SRam Amrani /* Either EDPM is disabled from user configuration, or it is 149851ff1725SRam Amrani * disabled via DCBx, or it is not mandatory and we failed to 149951ff1725SRam Amrani * allocated a WID per CPU. 150051ff1725SRam Amrani */ 150151ff1725SRam Amrani n_cpus = 1; 150251ff1725SRam Amrani rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 150351ff1725SRam Amrani 150451ff1725SRam Amrani if (cond) 150551ff1725SRam Amrani qed_rdma_dpm_bar(p_hwfn, p_ptt); 150651ff1725SRam Amrani } 150751ff1725SRam Amrani 150820b1bd96SRam Amrani p_hwfn->wid_count = (u16) n_cpus; 150920b1bd96SRam Amrani 151051ff1725SRam Amrani DP_INFO(p_hwfn, 151151ff1725SRam Amrani "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n", 151251ff1725SRam Amrani norm_regsize, 151351ff1725SRam Amrani pwm_regsize, 151451ff1725SRam Amrani p_hwfn->dpi_size, 151551ff1725SRam Amrani p_hwfn->dpi_count, 151651ff1725SRam Amrani ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ? 151751ff1725SRam Amrani "disabled" : "enabled"); 151851ff1725SRam Amrani 151951ff1725SRam Amrani if (rc) { 152051ff1725SRam Amrani DP_ERR(p_hwfn, 152151ff1725SRam Amrani "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n", 152251ff1725SRam Amrani p_hwfn->dpi_count, 152351ff1725SRam Amrani p_hwfn->pf_params.rdma_pf_params.min_dpis); 152451ff1725SRam Amrani return -EINVAL; 152551ff1725SRam Amrani } 152651ff1725SRam Amrani 152751ff1725SRam Amrani p_hwfn->dpi_start_offset = norm_regsize; 152851ff1725SRam Amrani 152951ff1725SRam Amrani /* DEMS size is configured log2 of DWORDs, hence the division by 4 */ 153051ff1725SRam Amrani pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4); 153151ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift); 153251ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1); 153351ff1725SRam Amrani 153451ff1725SRam Amrani return 0; 153551ff1725SRam Amrani } 153651ff1725SRam Amrani 1537fe56b9e6SYuval Mintz static int qed_hw_init_port(struct qed_hwfn *p_hwfn, 15381a635e48SYuval Mintz struct qed_ptt *p_ptt, int hw_mode) 1539fe56b9e6SYuval Mintz { 1540fc6575bcSMintz, Yuval int rc = 0; 1541fc6575bcSMintz, Yuval 1542fc6575bcSMintz, Yuval rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode); 1543fc6575bcSMintz, Yuval if (rc) 1544fc6575bcSMintz, Yuval return rc; 1545fc6575bcSMintz, Yuval 1546fc6575bcSMintz, Yuval qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0); 1547fc6575bcSMintz, Yuval 1548fc6575bcSMintz, Yuval return 0; 1549fe56b9e6SYuval Mintz } 1550fe56b9e6SYuval Mintz 1551fe56b9e6SYuval Mintz static int qed_hw_init_pf(struct qed_hwfn *p_hwfn, 1552fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 155319968430SChopra, Manish struct qed_tunnel_info *p_tunn, 1554fe56b9e6SYuval Mintz int hw_mode, 1555fe56b9e6SYuval Mintz bool b_hw_start, 1556fe56b9e6SYuval Mintz enum qed_int_mode int_mode, 1557fe56b9e6SYuval Mintz bool allow_npar_tx_switch) 1558fe56b9e6SYuval Mintz { 1559fe56b9e6SYuval Mintz u8 rel_pf_id = p_hwfn->rel_pf_id; 1560fe56b9e6SYuval Mintz int rc = 0; 1561fe56b9e6SYuval Mintz 1562fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 1563fe56b9e6SYuval Mintz struct qed_mcp_function_info *p_info; 1564fe56b9e6SYuval Mintz 1565fe56b9e6SYuval Mintz p_info = &p_hwfn->mcp_info->func_info; 1566fe56b9e6SYuval Mintz if (p_info->bandwidth_min) 1567fe56b9e6SYuval Mintz p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min; 1568fe56b9e6SYuval Mintz 1569fe56b9e6SYuval Mintz /* Update rate limit once we'll actually have a link */ 15704b01e519SManish Chopra p_hwfn->qm_info.pf_rl = 100000; 1571fe56b9e6SYuval Mintz } 1572fe56b9e6SYuval Mintz 157315582962SRahul Verma qed_cxt_hw_init_pf(p_hwfn, p_ptt); 1574fe56b9e6SYuval Mintz 1575fe56b9e6SYuval Mintz qed_int_igu_init_rt(p_hwfn); 1576fe56b9e6SYuval Mintz 1577fe56b9e6SYuval Mintz /* Set VLAN in NIG if needed */ 15781a635e48SYuval Mintz if (hw_mode & BIT(MODE_MF_SD)) { 1579fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n"); 1580fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1); 1581fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET, 1582fe56b9e6SYuval Mintz p_hwfn->hw_info.ovlan); 1583cac6f691SSudarsana Reddy Kalluru 1584cac6f691SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 1585cac6f691SSudarsana Reddy Kalluru "Configuring LLH_FUNC_FILTER_HDR_SEL\n"); 1586cac6f691SSudarsana Reddy Kalluru STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET, 1587cac6f691SSudarsana Reddy Kalluru 1); 1588fe56b9e6SYuval Mintz } 1589fe56b9e6SYuval Mintz 1590fe56b9e6SYuval Mintz /* Enable classification by MAC if needed */ 15911a635e48SYuval Mintz if (hw_mode & BIT(MODE_MF_SI)) { 1592fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 1593fe56b9e6SYuval Mintz "Configuring TAGMAC_CLS_TYPE\n"); 1594fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, 1595fe56b9e6SYuval Mintz NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1); 1596fe56b9e6SYuval Mintz } 1597fe56b9e6SYuval Mintz 1598a2e7699eSTomer Tayar /* Protocol Configuration */ 1599dbb799c3SYuval Mintz STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 1600dbb799c3SYuval Mintz (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0); 16011e128c81SArun Easi STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 16021e128c81SArun Easi (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0); 1603fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0); 1604fe56b9e6SYuval Mintz 1605fe56b9e6SYuval Mintz /* Cleanup chip from previous driver if such remains exist */ 16060b55e27dSYuval Mintz rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false); 16071a635e48SYuval Mintz if (rc) 1608fe56b9e6SYuval Mintz return rc; 1609fe56b9e6SYuval Mintz 1610da090917STomer Tayar /* Sanity check before the PF init sequence that uses DMAE */ 1611da090917STomer Tayar rc = qed_dmae_sanity(p_hwfn, p_ptt, "pf_phase"); 1612da090917STomer Tayar if (rc) 1613da090917STomer Tayar return rc; 1614da090917STomer Tayar 1615fe56b9e6SYuval Mintz /* PF Init sequence */ 1616fe56b9e6SYuval Mintz rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode); 1617fe56b9e6SYuval Mintz if (rc) 1618fe56b9e6SYuval Mintz return rc; 1619fe56b9e6SYuval Mintz 1620fe56b9e6SYuval Mintz /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */ 1621fe56b9e6SYuval Mintz rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode); 1622fe56b9e6SYuval Mintz if (rc) 1623fe56b9e6SYuval Mintz return rc; 1624fe56b9e6SYuval Mintz 1625fe56b9e6SYuval Mintz /* Pure runtime initializations - directly to the HW */ 1626fe56b9e6SYuval Mintz qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true); 1627fe56b9e6SYuval Mintz 162851ff1725SRam Amrani rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt); 162951ff1725SRam Amrani if (rc) 163051ff1725SRam Amrani return rc; 163151ff1725SRam Amrani 1632fe56b9e6SYuval Mintz if (b_hw_start) { 1633fe56b9e6SYuval Mintz /* enable interrupts */ 1634fe56b9e6SYuval Mintz qed_int_igu_enable(p_hwfn, p_ptt, int_mode); 1635fe56b9e6SYuval Mintz 1636fe56b9e6SYuval Mintz /* send function start command */ 16374f64675fSManish Chopra rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn, 1638831bfb0eSYuval Mintz allow_npar_tx_switch); 16391e128c81SArun Easi if (rc) { 1640fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Function start ramrod failed\n"); 16411e128c81SArun Easi return rc; 16421e128c81SArun Easi } 16431e128c81SArun Easi if (p_hwfn->hw_info.personality == QED_PCI_FCOE) { 16441e128c81SArun Easi qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2)); 16451e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 16461e128c81SArun Easi PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST, 16471e128c81SArun Easi 0x100); 16481e128c81SArun Easi } 1649fe56b9e6SYuval Mintz } 1650fe56b9e6SYuval Mintz return rc; 1651fe56b9e6SYuval Mintz } 1652fe56b9e6SYuval Mintz 1653fe56b9e6SYuval Mintz static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn, 1654fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1655fe56b9e6SYuval Mintz u8 enable) 1656fe56b9e6SYuval Mintz { 1657fe56b9e6SYuval Mintz u32 delay_idx = 0, val, set_val = enable ? 1 : 0; 1658fe56b9e6SYuval Mintz 1659fe56b9e6SYuval Mintz /* Change PF in PXP */ 1660fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 1661fe56b9e6SYuval Mintz PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val); 1662fe56b9e6SYuval Mintz 1663fe56b9e6SYuval Mintz /* wait until value is set - try for 1 second every 50us */ 1664fe56b9e6SYuval Mintz for (delay_idx = 0; delay_idx < 20000; delay_idx++) { 1665fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, 1666fe56b9e6SYuval Mintz PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1667fe56b9e6SYuval Mintz if (val == set_val) 1668fe56b9e6SYuval Mintz break; 1669fe56b9e6SYuval Mintz 1670fe56b9e6SYuval Mintz usleep_range(50, 60); 1671fe56b9e6SYuval Mintz } 1672fe56b9e6SYuval Mintz 1673fe56b9e6SYuval Mintz if (val != set_val) { 1674fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 1675fe56b9e6SYuval Mintz "PFID_ENABLE_MASTER wasn't changed after a second\n"); 1676fe56b9e6SYuval Mintz return -EAGAIN; 1677fe56b9e6SYuval Mintz } 1678fe56b9e6SYuval Mintz 1679fe56b9e6SYuval Mintz return 0; 1680fe56b9e6SYuval Mintz } 1681fe56b9e6SYuval Mintz 1682fe56b9e6SYuval Mintz static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn, 1683fe56b9e6SYuval Mintz struct qed_ptt *p_main_ptt) 1684fe56b9e6SYuval Mintz { 1685fe56b9e6SYuval Mintz /* Read shadow of current MFW mailbox */ 1686fe56b9e6SYuval Mintz qed_mcp_read_mb(p_hwfn, p_main_ptt); 1687fe56b9e6SYuval Mintz memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 16881a635e48SYuval Mintz p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length); 1689fe56b9e6SYuval Mintz } 1690fe56b9e6SYuval Mintz 16915d24bcf1STomer Tayar static void 16925d24bcf1STomer Tayar qed_fill_load_req_params(struct qed_load_req_params *p_load_req, 16935d24bcf1STomer Tayar struct qed_drv_load_params *p_drv_load) 16945d24bcf1STomer Tayar { 16955d24bcf1STomer Tayar memset(p_load_req, 0, sizeof(*p_load_req)); 16965d24bcf1STomer Tayar 16975d24bcf1STomer Tayar p_load_req->drv_role = p_drv_load->is_crash_kernel ? 16985d24bcf1STomer Tayar QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS; 16995d24bcf1STomer Tayar p_load_req->timeout_val = p_drv_load->mfw_timeout_val; 17005d24bcf1STomer Tayar p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset; 17015d24bcf1STomer Tayar p_load_req->override_force_load = p_drv_load->override_force_load; 17025d24bcf1STomer Tayar } 17035d24bcf1STomer Tayar 1704eaf3c0c6SChopra, Manish static int qed_vf_start(struct qed_hwfn *p_hwfn, 1705eaf3c0c6SChopra, Manish struct qed_hw_init_params *p_params) 1706eaf3c0c6SChopra, Manish { 1707eaf3c0c6SChopra, Manish if (p_params->p_tunn) { 1708eaf3c0c6SChopra, Manish qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn); 1709eaf3c0c6SChopra, Manish qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn); 1710eaf3c0c6SChopra, Manish } 1711eaf3c0c6SChopra, Manish 1712c7281d59SGustavo A. R. Silva p_hwfn->b_int_enabled = true; 1713eaf3c0c6SChopra, Manish 1714eaf3c0c6SChopra, Manish return 0; 1715eaf3c0c6SChopra, Manish } 1716eaf3c0c6SChopra, Manish 1717c0c2d0b4SMintz, Yuval int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params) 1718fe56b9e6SYuval Mintz { 17195d24bcf1STomer Tayar struct qed_load_req_params load_req_params; 17200fefbfbaSSudarsana Kalluru u32 load_code, param, drv_mb_param; 17210fefbfbaSSudarsana Kalluru bool b_default_mtu = true; 17220fefbfbaSSudarsana Kalluru struct qed_hwfn *p_hwfn; 17230fefbfbaSSudarsana Kalluru int rc = 0, mfw_rc, i; 1724cac6f691SSudarsana Reddy Kalluru u16 ether_type; 1725fe56b9e6SYuval Mintz 1726c0c2d0b4SMintz, Yuval if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) { 1727bb13ace7SSudarsana Reddy Kalluru DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n"); 1728bb13ace7SSudarsana Reddy Kalluru return -EINVAL; 1729bb13ace7SSudarsana Reddy Kalluru } 1730bb13ace7SSudarsana Reddy Kalluru 17311408cc1fSYuval Mintz if (IS_PF(cdev)) { 1732c0c2d0b4SMintz, Yuval rc = qed_init_fw_data(cdev, p_params->bin_fw_data); 17331a635e48SYuval Mintz if (rc) 1734fe56b9e6SYuval Mintz return rc; 17351408cc1fSYuval Mintz } 1736fe56b9e6SYuval Mintz 1737fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 1738fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1739fe56b9e6SYuval Mintz 17400fefbfbaSSudarsana Kalluru /* If management didn't provide a default, set one of our own */ 17410fefbfbaSSudarsana Kalluru if (!p_hwfn->hw_info.mtu) { 17420fefbfbaSSudarsana Kalluru p_hwfn->hw_info.mtu = 1500; 17430fefbfbaSSudarsana Kalluru b_default_mtu = false; 17440fefbfbaSSudarsana Kalluru } 17450fefbfbaSSudarsana Kalluru 17461408cc1fSYuval Mintz if (IS_VF(cdev)) { 1747eaf3c0c6SChopra, Manish qed_vf_start(p_hwfn, p_params); 17481408cc1fSYuval Mintz continue; 17491408cc1fSYuval Mintz } 17501408cc1fSYuval Mintz 1751fe56b9e6SYuval Mintz /* Enable DMAE in PXP */ 1752fe56b9e6SYuval Mintz rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true); 1753fe56b9e6SYuval Mintz 17549c79ddaaSMintz, Yuval rc = qed_calc_hw_mode(p_hwfn); 17559c79ddaaSMintz, Yuval if (rc) 17569c79ddaaSMintz, Yuval return rc; 1757fe56b9e6SYuval Mintz 1758cac6f691SSudarsana Reddy Kalluru if (IS_PF(cdev) && (test_bit(QED_MF_8021Q_TAGGING, 1759cac6f691SSudarsana Reddy Kalluru &cdev->mf_bits) || 1760cac6f691SSudarsana Reddy Kalluru test_bit(QED_MF_8021AD_TAGGING, 1761cac6f691SSudarsana Reddy Kalluru &cdev->mf_bits))) { 1762cac6f691SSudarsana Reddy Kalluru if (test_bit(QED_MF_8021Q_TAGGING, &cdev->mf_bits)) 1763cac6f691SSudarsana Reddy Kalluru ether_type = ETH_P_8021Q; 1764cac6f691SSudarsana Reddy Kalluru else 1765cac6f691SSudarsana Reddy Kalluru ether_type = ETH_P_8021AD; 1766b51bdfb9SSudarsana Reddy Kalluru STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET, 1767cac6f691SSudarsana Reddy Kalluru ether_type); 1768b51bdfb9SSudarsana Reddy Kalluru STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET, 1769cac6f691SSudarsana Reddy Kalluru ether_type); 1770b51bdfb9SSudarsana Reddy Kalluru STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET, 1771cac6f691SSudarsana Reddy Kalluru ether_type); 1772b51bdfb9SSudarsana Reddy Kalluru STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET, 1773cac6f691SSudarsana Reddy Kalluru ether_type); 1774b51bdfb9SSudarsana Reddy Kalluru } 1775b51bdfb9SSudarsana Reddy Kalluru 17765d24bcf1STomer Tayar qed_fill_load_req_params(&load_req_params, 17775d24bcf1STomer Tayar p_params->p_drv_load_params); 17785d24bcf1STomer Tayar rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, 17795d24bcf1STomer Tayar &load_req_params); 1780fe56b9e6SYuval Mintz if (rc) { 17815d24bcf1STomer Tayar DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n"); 1782fe56b9e6SYuval Mintz return rc; 1783fe56b9e6SYuval Mintz } 1784fe56b9e6SYuval Mintz 17855d24bcf1STomer Tayar load_code = load_req_params.load_code; 1786fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 17875d24bcf1STomer Tayar "Load request was sent. Load code: 0x%x\n", 17885d24bcf1STomer Tayar load_code); 17895d24bcf1STomer Tayar 1790645874e5SSudarsana Reddy Kalluru qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt); 1791645874e5SSudarsana Reddy Kalluru 17925d24bcf1STomer Tayar qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt); 1793fe56b9e6SYuval Mintz 1794fe56b9e6SYuval Mintz p_hwfn->first_on_engine = (load_code == 1795fe56b9e6SYuval Mintz FW_MSG_CODE_DRV_LOAD_ENGINE); 1796fe56b9e6SYuval Mintz 1797fe56b9e6SYuval Mintz switch (load_code) { 1798fe56b9e6SYuval Mintz case FW_MSG_CODE_DRV_LOAD_ENGINE: 1799fe56b9e6SYuval Mintz rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt, 1800fe56b9e6SYuval Mintz p_hwfn->hw_info.hw_mode); 1801fe56b9e6SYuval Mintz if (rc) 1802fe56b9e6SYuval Mintz break; 180353a42286SGustavo A. R. Silva /* Fall through */ 1804fe56b9e6SYuval Mintz case FW_MSG_CODE_DRV_LOAD_PORT: 1805fe56b9e6SYuval Mintz rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt, 1806fe56b9e6SYuval Mintz p_hwfn->hw_info.hw_mode); 1807fe56b9e6SYuval Mintz if (rc) 1808fe56b9e6SYuval Mintz break; 1809fe56b9e6SYuval Mintz 181053a42286SGustavo A. R. Silva /* Fall through */ 1811fe56b9e6SYuval Mintz case FW_MSG_CODE_DRV_LOAD_FUNCTION: 1812fe56b9e6SYuval Mintz rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt, 1813c0c2d0b4SMintz, Yuval p_params->p_tunn, 1814c0c2d0b4SMintz, Yuval p_hwfn->hw_info.hw_mode, 1815c0c2d0b4SMintz, Yuval p_params->b_hw_start, 1816c0c2d0b4SMintz, Yuval p_params->int_mode, 1817c0c2d0b4SMintz, Yuval p_params->allow_npar_tx_switch); 1818fe56b9e6SYuval Mintz break; 1819fe56b9e6SYuval Mintz default: 1820c0c2d0b4SMintz, Yuval DP_NOTICE(p_hwfn, 1821c0c2d0b4SMintz, Yuval "Unexpected load code [0x%08x]", load_code); 1822fe56b9e6SYuval Mintz rc = -EINVAL; 1823fe56b9e6SYuval Mintz break; 1824fe56b9e6SYuval Mintz } 1825fe56b9e6SYuval Mintz 1826fe56b9e6SYuval Mintz if (rc) 1827fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 1828fe56b9e6SYuval Mintz "init phase failed for loadcode 0x%x (rc %d)\n", 1829fe56b9e6SYuval Mintz load_code, rc); 1830fe56b9e6SYuval Mintz 1831fe56b9e6SYuval Mintz /* ACK mfw regardless of success or failure of initialization */ 1832fe56b9e6SYuval Mintz mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1833fe56b9e6SYuval Mintz DRV_MSG_CODE_LOAD_DONE, 1834fe56b9e6SYuval Mintz 0, &load_code, ¶m); 1835fe56b9e6SYuval Mintz if (rc) 1836fe56b9e6SYuval Mintz return rc; 1837fe56b9e6SYuval Mintz if (mfw_rc) { 1838fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n"); 1839fe56b9e6SYuval Mintz return mfw_rc; 1840fe56b9e6SYuval Mintz } 1841fe56b9e6SYuval Mintz 1842fc561c8bSTomer Tayar /* Check if there is a DID mismatch between nvm-cfg/efuse */ 1843fc561c8bSTomer Tayar if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR) 1844fc561c8bSTomer Tayar DP_NOTICE(p_hwfn, 1845fc561c8bSTomer Tayar "warning: device configuration is not supported on this board type. The device may not function as expected.\n"); 1846fc561c8bSTomer Tayar 184739651abdSSudarsana Reddy Kalluru /* send DCBX attention request command */ 184839651abdSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, 184939651abdSSudarsana Reddy Kalluru QED_MSG_DCB, 185039651abdSSudarsana Reddy Kalluru "sending phony dcbx set command to trigger DCBx attention handling\n"); 185139651abdSSudarsana Reddy Kalluru mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 185239651abdSSudarsana Reddy Kalluru DRV_MSG_CODE_SET_DCBX, 185339651abdSSudarsana Reddy Kalluru 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT, 185439651abdSSudarsana Reddy Kalluru &load_code, ¶m); 185539651abdSSudarsana Reddy Kalluru if (mfw_rc) { 185639651abdSSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 185739651abdSSudarsana Reddy Kalluru "Failed to send DCBX attention request\n"); 185839651abdSSudarsana Reddy Kalluru return mfw_rc; 185939651abdSSudarsana Reddy Kalluru } 186039651abdSSudarsana Reddy Kalluru 1861fe56b9e6SYuval Mintz p_hwfn->hw_init_done = true; 1862fe56b9e6SYuval Mintz } 1863fe56b9e6SYuval Mintz 18640fefbfbaSSudarsana Kalluru if (IS_PF(cdev)) { 18650fefbfbaSSudarsana Kalluru p_hwfn = QED_LEADING_HWFN(cdev); 18665d24bcf1STomer Tayar drv_mb_param = STORM_FW_VERSION; 18670fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 18680fefbfbaSSudarsana Kalluru DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER, 18690fefbfbaSSudarsana Kalluru drv_mb_param, &load_code, ¶m); 18700fefbfbaSSudarsana Kalluru if (rc) 18710fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, "Failed to update firmware version\n"); 18720fefbfbaSSudarsana Kalluru 18730fefbfbaSSudarsana Kalluru if (!b_default_mtu) { 18740fefbfbaSSudarsana Kalluru rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt, 18750fefbfbaSSudarsana Kalluru p_hwfn->hw_info.mtu); 18760fefbfbaSSudarsana Kalluru if (rc) 18770fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, 18780fefbfbaSSudarsana Kalluru "Failed to update default mtu\n"); 18790fefbfbaSSudarsana Kalluru } 18800fefbfbaSSudarsana Kalluru 18810fefbfbaSSudarsana Kalluru rc = qed_mcp_ov_update_driver_state(p_hwfn, 18820fefbfbaSSudarsana Kalluru p_hwfn->p_main_ptt, 18830fefbfbaSSudarsana Kalluru QED_OV_DRIVER_STATE_DISABLED); 18840fefbfbaSSudarsana Kalluru if (rc) 18850fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, "Failed to update driver state\n"); 18860fefbfbaSSudarsana Kalluru 18870fefbfbaSSudarsana Kalluru rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt, 1888538f8d00SSudarsana Reddy Kalluru QED_OV_ESWITCH_NONE); 18890fefbfbaSSudarsana Kalluru if (rc) 18900fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, "Failed to update eswitch mode\n"); 18910fefbfbaSSudarsana Kalluru } 18920fefbfbaSSudarsana Kalluru 1893fe56b9e6SYuval Mintz return 0; 1894fe56b9e6SYuval Mintz } 1895fe56b9e6SYuval Mintz 1896fe56b9e6SYuval Mintz #define QED_HW_STOP_RETRY_LIMIT (10) 18971a635e48SYuval Mintz static void qed_hw_timers_stop(struct qed_dev *cdev, 18981a635e48SYuval Mintz struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 18998c925c44SYuval Mintz { 19008c925c44SYuval Mintz int i; 19018c925c44SYuval Mintz 19028c925c44SYuval Mintz /* close timers */ 19038c925c44SYuval Mintz qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0); 19048c925c44SYuval Mintz qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0); 19058c925c44SYuval Mintz 19068c925c44SYuval Mintz for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) { 19078c925c44SYuval Mintz if ((!qed_rd(p_hwfn, p_ptt, 19088c925c44SYuval Mintz TM_REG_PF_SCAN_ACTIVE_CONN)) && 19091a635e48SYuval Mintz (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK))) 19108c925c44SYuval Mintz break; 19118c925c44SYuval Mintz 19128c925c44SYuval Mintz /* Dependent on number of connection/tasks, possibly 19138c925c44SYuval Mintz * 1ms sleep is required between polls 19148c925c44SYuval Mintz */ 19158c925c44SYuval Mintz usleep_range(1000, 2000); 19168c925c44SYuval Mintz } 19178c925c44SYuval Mintz 19188c925c44SYuval Mintz if (i < QED_HW_STOP_RETRY_LIMIT) 19198c925c44SYuval Mintz return; 19208c925c44SYuval Mintz 19218c925c44SYuval Mintz DP_NOTICE(p_hwfn, 19228c925c44SYuval Mintz "Timers linear scans are not over [Connection %02x Tasks %02x]\n", 19238c925c44SYuval Mintz (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN), 19248c925c44SYuval Mintz (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)); 19258c925c44SYuval Mintz } 19268c925c44SYuval Mintz 19278c925c44SYuval Mintz void qed_hw_timers_stop_all(struct qed_dev *cdev) 19288c925c44SYuval Mintz { 19298c925c44SYuval Mintz int j; 19308c925c44SYuval Mintz 19318c925c44SYuval Mintz for_each_hwfn(cdev, j) { 19328c925c44SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 19338c925c44SYuval Mintz struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 19348c925c44SYuval Mintz 19358c925c44SYuval Mintz qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 19368c925c44SYuval Mintz } 19378c925c44SYuval Mintz } 19388c925c44SYuval Mintz 1939fe56b9e6SYuval Mintz int qed_hw_stop(struct qed_dev *cdev) 1940fe56b9e6SYuval Mintz { 19411226337aSTomer Tayar struct qed_hwfn *p_hwfn; 19421226337aSTomer Tayar struct qed_ptt *p_ptt; 19431226337aSTomer Tayar int rc, rc2 = 0; 19448c925c44SYuval Mintz int j; 1945fe56b9e6SYuval Mintz 1946fe56b9e6SYuval Mintz for_each_hwfn(cdev, j) { 19471226337aSTomer Tayar p_hwfn = &cdev->hwfns[j]; 19481226337aSTomer Tayar p_ptt = p_hwfn->p_main_ptt; 1949fe56b9e6SYuval Mintz 1950fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n"); 1951fe56b9e6SYuval Mintz 19521408cc1fSYuval Mintz if (IS_VF(cdev)) { 19530b55e27dSYuval Mintz qed_vf_pf_int_cleanup(p_hwfn); 19541226337aSTomer Tayar rc = qed_vf_pf_reset(p_hwfn); 19551226337aSTomer Tayar if (rc) { 19561226337aSTomer Tayar DP_NOTICE(p_hwfn, 19571226337aSTomer Tayar "qed_vf_pf_reset failed. rc = %d.\n", 19581226337aSTomer Tayar rc); 19591226337aSTomer Tayar rc2 = -EINVAL; 19601226337aSTomer Tayar } 19611408cc1fSYuval Mintz continue; 19621408cc1fSYuval Mintz } 19631408cc1fSYuval Mintz 1964fe56b9e6SYuval Mintz /* mark the hw as uninitialized... */ 1965fe56b9e6SYuval Mintz p_hwfn->hw_init_done = false; 1966fe56b9e6SYuval Mintz 19671226337aSTomer Tayar /* Send unload command to MCP */ 19681226337aSTomer Tayar rc = qed_mcp_unload_req(p_hwfn, p_ptt); 19691226337aSTomer Tayar if (rc) { 19708c925c44SYuval Mintz DP_NOTICE(p_hwfn, 19711226337aSTomer Tayar "Failed sending a UNLOAD_REQ command. rc = %d.\n", 19721226337aSTomer Tayar rc); 19731226337aSTomer Tayar rc2 = -EINVAL; 19741226337aSTomer Tayar } 19751226337aSTomer Tayar 19761226337aSTomer Tayar qed_slowpath_irq_sync(p_hwfn); 19771226337aSTomer Tayar 19781226337aSTomer Tayar /* After this point no MFW attentions are expected, e.g. prevent 19791226337aSTomer Tayar * race between pf stop and dcbx pf update. 19801226337aSTomer Tayar */ 19811226337aSTomer Tayar rc = qed_sp_pf_stop(p_hwfn); 19821226337aSTomer Tayar if (rc) { 19831226337aSTomer Tayar DP_NOTICE(p_hwfn, 19841226337aSTomer Tayar "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n", 19851226337aSTomer Tayar rc); 19861226337aSTomer Tayar rc2 = -EINVAL; 19871226337aSTomer Tayar } 1988fe56b9e6SYuval Mintz 1989fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 1990fe56b9e6SYuval Mintz NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 1991fe56b9e6SYuval Mintz 1992fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1993fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 1994fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 1995fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1996fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 1997fe56b9e6SYuval Mintz 19988c925c44SYuval Mintz qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 1999fe56b9e6SYuval Mintz 2000fe56b9e6SYuval Mintz /* Disable Attention Generation */ 2001fe56b9e6SYuval Mintz qed_int_igu_disable_int(p_hwfn, p_ptt); 2002fe56b9e6SYuval Mintz 2003fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0); 2004fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0); 2005fe56b9e6SYuval Mintz 2006fe56b9e6SYuval Mintz qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true); 2007fe56b9e6SYuval Mintz 2008fe56b9e6SYuval Mintz /* Need to wait 1ms to guarantee SBs are cleared */ 2009fe56b9e6SYuval Mintz usleep_range(1000, 2000); 20101226337aSTomer Tayar 20111226337aSTomer Tayar /* Disable PF in HW blocks */ 20121226337aSTomer Tayar qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0); 20131226337aSTomer Tayar qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0); 20141226337aSTomer Tayar 20151226337aSTomer Tayar qed_mcp_unload_done(p_hwfn, p_ptt); 20161226337aSTomer Tayar if (rc) { 20171226337aSTomer Tayar DP_NOTICE(p_hwfn, 20181226337aSTomer Tayar "Failed sending a UNLOAD_DONE command. rc = %d.\n", 20191226337aSTomer Tayar rc); 20201226337aSTomer Tayar rc2 = -EINVAL; 20211226337aSTomer Tayar } 2022fe56b9e6SYuval Mintz } 2023fe56b9e6SYuval Mintz 20241408cc1fSYuval Mintz if (IS_PF(cdev)) { 20251226337aSTomer Tayar p_hwfn = QED_LEADING_HWFN(cdev); 20261226337aSTomer Tayar p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt; 20271226337aSTomer Tayar 2028fe56b9e6SYuval Mintz /* Disable DMAE in PXP - in CMT, this should only be done for 2029fe56b9e6SYuval Mintz * first hw-function, and only after all transactions have 2030fe56b9e6SYuval Mintz * stopped for all active hw-functions. 2031fe56b9e6SYuval Mintz */ 20321226337aSTomer Tayar rc = qed_change_pci_hwfn(p_hwfn, p_ptt, false); 20331226337aSTomer Tayar if (rc) { 20341226337aSTomer Tayar DP_NOTICE(p_hwfn, 20351226337aSTomer Tayar "qed_change_pci_hwfn failed. rc = %d.\n", rc); 20361226337aSTomer Tayar rc2 = -EINVAL; 20371226337aSTomer Tayar } 20381408cc1fSYuval Mintz } 2039fe56b9e6SYuval Mintz 20401226337aSTomer Tayar return rc2; 2041fe56b9e6SYuval Mintz } 2042fe56b9e6SYuval Mintz 204315582962SRahul Verma int qed_hw_stop_fastpath(struct qed_dev *cdev) 2044cee4d264SManish Chopra { 20458c925c44SYuval Mintz int j; 2046cee4d264SManish Chopra 2047cee4d264SManish Chopra for_each_hwfn(cdev, j) { 2048cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 204915582962SRahul Verma struct qed_ptt *p_ptt; 2050cee4d264SManish Chopra 2051dacd88d6SYuval Mintz if (IS_VF(cdev)) { 2052dacd88d6SYuval Mintz qed_vf_pf_int_cleanup(p_hwfn); 2053dacd88d6SYuval Mintz continue; 2054dacd88d6SYuval Mintz } 205515582962SRahul Verma p_ptt = qed_ptt_acquire(p_hwfn); 205615582962SRahul Verma if (!p_ptt) 205715582962SRahul Verma return -EAGAIN; 2058dacd88d6SYuval Mintz 2059cee4d264SManish Chopra DP_VERBOSE(p_hwfn, 20601a635e48SYuval Mintz NETIF_MSG_IFDOWN, "Shutting down the fastpath\n"); 2061cee4d264SManish Chopra 2062cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, 2063cee4d264SManish Chopra NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 2064cee4d264SManish Chopra 2065cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 2066cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 2067cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 2068cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 2069cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 2070cee4d264SManish Chopra 2071cee4d264SManish Chopra qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false); 2072cee4d264SManish Chopra 2073cee4d264SManish Chopra /* Need to wait 1ms to guarantee SBs are cleared */ 2074cee4d264SManish Chopra usleep_range(1000, 2000); 207515582962SRahul Verma qed_ptt_release(p_hwfn, p_ptt); 2076cee4d264SManish Chopra } 2077cee4d264SManish Chopra 207815582962SRahul Verma return 0; 207915582962SRahul Verma } 208015582962SRahul Verma 208115582962SRahul Verma int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn) 2082cee4d264SManish Chopra { 208315582962SRahul Verma struct qed_ptt *p_ptt; 208415582962SRahul Verma 2085dacd88d6SYuval Mintz if (IS_VF(p_hwfn->cdev)) 208615582962SRahul Verma return 0; 208715582962SRahul Verma 208815582962SRahul Verma p_ptt = qed_ptt_acquire(p_hwfn); 208915582962SRahul Verma if (!p_ptt) 209015582962SRahul Verma return -EAGAIN; 2091dacd88d6SYuval Mintz 2092f855df22SMichal Kalderon /* If roce info is allocated it means roce is initialized and should 2093f855df22SMichal Kalderon * be enabled in searcher. 2094f855df22SMichal Kalderon */ 2095f855df22SMichal Kalderon if (p_hwfn->p_rdma_info && 2096f855df22SMichal Kalderon p_hwfn->b_rdma_enabled_in_prs) 2097f855df22SMichal Kalderon qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1); 2098f855df22SMichal Kalderon 2099cee4d264SManish Chopra /* Re-open incoming traffic */ 210015582962SRahul Verma qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0); 210115582962SRahul Verma qed_ptt_release(p_hwfn, p_ptt); 210215582962SRahul Verma 210315582962SRahul Verma return 0; 2104cee4d264SManish Chopra } 2105cee4d264SManish Chopra 2106fe56b9e6SYuval Mintz /* Free hwfn memory and resources acquired in hw_hwfn_prepare */ 2107fe56b9e6SYuval Mintz static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn) 2108fe56b9e6SYuval Mintz { 2109fe56b9e6SYuval Mintz qed_ptt_pool_free(p_hwfn); 2110fe56b9e6SYuval Mintz kfree(p_hwfn->hw_info.p_igu_info); 21113587cb87STomer Tayar p_hwfn->hw_info.p_igu_info = NULL; 2112fe56b9e6SYuval Mintz } 2113fe56b9e6SYuval Mintz 2114fe56b9e6SYuval Mintz /* Setup bar access */ 211512e09c69SYuval Mintz static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn) 2116fe56b9e6SYuval Mintz { 2117fe56b9e6SYuval Mintz /* clear indirect access */ 21189c79ddaaSMintz, Yuval if (QED_IS_AH(p_hwfn->cdev)) { 21199c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 21209c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0); 21219c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 21229c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0); 21239c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 21249c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0); 21259c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 21269c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0); 21279c79ddaaSMintz, Yuval } else { 21289c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 21299c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0); 21309c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 21319c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0); 21329c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 21339c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0); 21349c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 21359c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0); 21369c79ddaaSMintz, Yuval } 2137fe56b9e6SYuval Mintz 2138fe56b9e6SYuval Mintz /* Clean Previous errors if such exist */ 2139fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, 21401a635e48SYuval Mintz PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id); 2141fe56b9e6SYuval Mintz 2142fe56b9e6SYuval Mintz /* enable internal target-read */ 2143fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, 2144fe56b9e6SYuval Mintz PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 2145fe56b9e6SYuval Mintz } 2146fe56b9e6SYuval Mintz 2147fe56b9e6SYuval Mintz static void get_function_id(struct qed_hwfn *p_hwfn) 2148fe56b9e6SYuval Mintz { 2149fe56b9e6SYuval Mintz /* ME Register */ 21501a635e48SYuval Mintz p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn, 21511a635e48SYuval Mintz PXP_PF_ME_OPAQUE_ADDR); 2152fe56b9e6SYuval Mintz 2153fe56b9e6SYuval Mintz p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); 2154fe56b9e6SYuval Mintz 2155fe56b9e6SYuval Mintz p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf; 2156fe56b9e6SYuval Mintz p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 2157fe56b9e6SYuval Mintz PXP_CONCRETE_FID_PFID); 2158fe56b9e6SYuval Mintz p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 2159fe56b9e6SYuval Mintz PXP_CONCRETE_FID_PORT); 2160525ef5c0SYuval Mintz 2161525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, 2162525ef5c0SYuval Mintz "Read ME register: Concrete 0x%08x Opaque 0x%04x\n", 2163525ef5c0SYuval Mintz p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid); 2164fe56b9e6SYuval Mintz } 2165fe56b9e6SYuval Mintz 216625c089d7SYuval Mintz static void qed_hw_set_feat(struct qed_hwfn *p_hwfn) 216725c089d7SYuval Mintz { 216825c089d7SYuval Mintz u32 *feat_num = p_hwfn->hw_info.feat_num; 2169ebbdcc66SMintz, Yuval struct qed_sb_cnt_info sb_cnt; 2170810bb1f0SMintz, Yuval u32 non_l2_sbs = 0; 217125c089d7SYuval Mintz 2172ebbdcc66SMintz, Yuval memset(&sb_cnt, 0, sizeof(sb_cnt)); 2173ebbdcc66SMintz, Yuval qed_int_get_num_sbs(p_hwfn, &sb_cnt); 2174ebbdcc66SMintz, Yuval 21750189efb8SYuval Mintz if (IS_ENABLED(CONFIG_QED_RDMA) && 2176c851a9dcSKalderon, Michal QED_IS_RDMA_PERSONALITY(p_hwfn)) { 21770189efb8SYuval Mintz /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide 21780189efb8SYuval Mintz * the status blocks equally between L2 / RoCE but with 21790189efb8SYuval Mintz * consideration as to how many l2 queues / cnqs we have. 218051ff1725SRam Amrani */ 218151ff1725SRam Amrani feat_num[QED_RDMA_CNQ] = 2182ebbdcc66SMintz, Yuval min_t(u32, sb_cnt.cnt / 2, 218351ff1725SRam Amrani RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM)); 2184810bb1f0SMintz, Yuval 2185810bb1f0SMintz, Yuval non_l2_sbs = feat_num[QED_RDMA_CNQ]; 218651ff1725SRam Amrani } 2187c851a9dcSKalderon, Michal if (QED_IS_L2_PERSONALITY(p_hwfn)) { 2188dec26533SMintz, Yuval /* Start by allocating VF queues, then PF's */ 2189dec26533SMintz, Yuval feat_num[QED_VF_L2_QUE] = min_t(u32, 2190dec26533SMintz, Yuval RESC_NUM(p_hwfn, QED_L2_QUEUE), 2191ebbdcc66SMintz, Yuval sb_cnt.iov_cnt); 2192810bb1f0SMintz, Yuval feat_num[QED_PF_L2_QUE] = min_t(u32, 2193ebbdcc66SMintz, Yuval sb_cnt.cnt - non_l2_sbs, 2194dec26533SMintz, Yuval RESC_NUM(p_hwfn, 2195dec26533SMintz, Yuval QED_L2_QUEUE) - 2196dec26533SMintz, Yuval FEAT_NUM(p_hwfn, 2197dec26533SMintz, Yuval QED_VF_L2_QUE)); 2198dec26533SMintz, Yuval } 21995a1f965aSMintz, Yuval 2200c851a9dcSKalderon, Michal if (QED_IS_FCOE_PERSONALITY(p_hwfn)) 22013c5da942SMintz, Yuval feat_num[QED_FCOE_CQ] = min_t(u32, sb_cnt.cnt, 22023c5da942SMintz, Yuval RESC_NUM(p_hwfn, 22033c5da942SMintz, Yuval QED_CMDQS_CQS)); 22043c5da942SMintz, Yuval 2205c851a9dcSKalderon, Michal if (QED_IS_ISCSI_PERSONALITY(p_hwfn)) 2206ebbdcc66SMintz, Yuval feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt, 220708737a3fSMintz, Yuval RESC_NUM(p_hwfn, 220808737a3fSMintz, Yuval QED_CMDQS_CQS)); 22095a1f965aSMintz, Yuval DP_VERBOSE(p_hwfn, 22105a1f965aSMintz, Yuval NETIF_MSG_PROBE, 22113c5da942SMintz, Yuval "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d #SBS=%d\n", 22125a1f965aSMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE), 22135a1f965aSMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE), 22145a1f965aSMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ), 22153c5da942SMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ), 221608737a3fSMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ), 2217ebbdcc66SMintz, Yuval (int)sb_cnt.cnt); 221825c089d7SYuval Mintz } 221925c089d7SYuval Mintz 22209c8517c4STomer Tayar const char *qed_hw_get_resc_name(enum qed_resources res_id) 22212edbff8dSTomer Tayar { 22222edbff8dSTomer Tayar switch (res_id) { 22232edbff8dSTomer Tayar case QED_L2_QUEUE: 22242edbff8dSTomer Tayar return "L2_QUEUE"; 22252edbff8dSTomer Tayar case QED_VPORT: 22262edbff8dSTomer Tayar return "VPORT"; 22272edbff8dSTomer Tayar case QED_RSS_ENG: 22282edbff8dSTomer Tayar return "RSS_ENG"; 22292edbff8dSTomer Tayar case QED_PQ: 22302edbff8dSTomer Tayar return "PQ"; 22312edbff8dSTomer Tayar case QED_RL: 22322edbff8dSTomer Tayar return "RL"; 22332edbff8dSTomer Tayar case QED_MAC: 22342edbff8dSTomer Tayar return "MAC"; 22352edbff8dSTomer Tayar case QED_VLAN: 22362edbff8dSTomer Tayar return "VLAN"; 22372edbff8dSTomer Tayar case QED_RDMA_CNQ_RAM: 22382edbff8dSTomer Tayar return "RDMA_CNQ_RAM"; 22392edbff8dSTomer Tayar case QED_ILT: 22402edbff8dSTomer Tayar return "ILT"; 22412edbff8dSTomer Tayar case QED_LL2_QUEUE: 22422edbff8dSTomer Tayar return "LL2_QUEUE"; 22432edbff8dSTomer Tayar case QED_CMDQS_CQS: 22442edbff8dSTomer Tayar return "CMDQS_CQS"; 22452edbff8dSTomer Tayar case QED_RDMA_STATS_QUEUE: 22462edbff8dSTomer Tayar return "RDMA_STATS_QUEUE"; 22479c8517c4STomer Tayar case QED_BDQ: 22489c8517c4STomer Tayar return "BDQ"; 22499c8517c4STomer Tayar case QED_SB: 22509c8517c4STomer Tayar return "SB"; 22512edbff8dSTomer Tayar default: 22522edbff8dSTomer Tayar return "UNKNOWN_RESOURCE"; 22532edbff8dSTomer Tayar } 22542edbff8dSTomer Tayar } 22552edbff8dSTomer Tayar 22569c8517c4STomer Tayar static int 22579c8517c4STomer Tayar __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, 22589c8517c4STomer Tayar struct qed_ptt *p_ptt, 22599c8517c4STomer Tayar enum qed_resources res_id, 22609c8517c4STomer Tayar u32 resc_max_val, u32 *p_mcp_resp) 22619c8517c4STomer Tayar { 22629c8517c4STomer Tayar int rc; 22639c8517c4STomer Tayar 22649c8517c4STomer Tayar rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id, 22659c8517c4STomer Tayar resc_max_val, p_mcp_resp); 22669c8517c4STomer Tayar if (rc) { 22679c8517c4STomer Tayar DP_NOTICE(p_hwfn, 22689c8517c4STomer Tayar "MFW response failure for a max value setting of resource %d [%s]\n", 22699c8517c4STomer Tayar res_id, qed_hw_get_resc_name(res_id)); 22709c8517c4STomer Tayar return rc; 22719c8517c4STomer Tayar } 22729c8517c4STomer Tayar 22739c8517c4STomer Tayar if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) 22749c8517c4STomer Tayar DP_INFO(p_hwfn, 22759c8517c4STomer Tayar "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n", 22769c8517c4STomer Tayar res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp); 22779c8517c4STomer Tayar 22789c8517c4STomer Tayar return 0; 22799c8517c4STomer Tayar } 22809c8517c4STomer Tayar 22819c8517c4STomer Tayar static int 22829c8517c4STomer Tayar qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 22839c8517c4STomer Tayar { 22849c8517c4STomer Tayar bool b_ah = QED_IS_AH(p_hwfn->cdev); 22859c8517c4STomer Tayar u32 resc_max_val, mcp_resp; 22869c8517c4STomer Tayar u8 res_id; 22879c8517c4STomer Tayar int rc; 22889c8517c4STomer Tayar 22899c8517c4STomer Tayar for (res_id = 0; res_id < QED_MAX_RESC; res_id++) { 22909c8517c4STomer Tayar switch (res_id) { 22919c8517c4STomer Tayar case QED_LL2_QUEUE: 22929c8517c4STomer Tayar resc_max_val = MAX_NUM_LL2_RX_QUEUES; 22939c8517c4STomer Tayar break; 22949c8517c4STomer Tayar case QED_RDMA_CNQ_RAM: 22959c8517c4STomer Tayar /* No need for a case for QED_CMDQS_CQS since 22969c8517c4STomer Tayar * CNQ/CMDQS are the same resource. 22979c8517c4STomer Tayar */ 2298da090917STomer Tayar resc_max_val = NUM_OF_GLOBAL_QUEUES; 22999c8517c4STomer Tayar break; 23009c8517c4STomer Tayar case QED_RDMA_STATS_QUEUE: 23019c8517c4STomer Tayar resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 23029c8517c4STomer Tayar : RDMA_NUM_STATISTIC_COUNTERS_BB; 23039c8517c4STomer Tayar break; 23049c8517c4STomer Tayar case QED_BDQ: 23059c8517c4STomer Tayar resc_max_val = BDQ_NUM_RESOURCES; 23069c8517c4STomer Tayar break; 23079c8517c4STomer Tayar default: 23089c8517c4STomer Tayar continue; 23099c8517c4STomer Tayar } 23109c8517c4STomer Tayar 23119c8517c4STomer Tayar rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id, 23129c8517c4STomer Tayar resc_max_val, &mcp_resp); 23139c8517c4STomer Tayar if (rc) 23149c8517c4STomer Tayar return rc; 23159c8517c4STomer Tayar 23169c8517c4STomer Tayar /* There's no point to continue to the next resource if the 23179c8517c4STomer Tayar * command is not supported by the MFW. 23189c8517c4STomer Tayar * We do continue if the command is supported but the resource 23199c8517c4STomer Tayar * is unknown to the MFW. Such a resource will be later 23209c8517c4STomer Tayar * configured with the default allocation values. 23219c8517c4STomer Tayar */ 23229c8517c4STomer Tayar if (mcp_resp == FW_MSG_CODE_UNSUPPORTED) 23239c8517c4STomer Tayar return -EINVAL; 23249c8517c4STomer Tayar } 23259c8517c4STomer Tayar 23269c8517c4STomer Tayar return 0; 23279c8517c4STomer Tayar } 23289c8517c4STomer Tayar 23299c8517c4STomer Tayar static 23309c8517c4STomer Tayar int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn, 23319c8517c4STomer Tayar enum qed_resources res_id, 23329c8517c4STomer Tayar u32 *p_resc_num, u32 *p_resc_start) 23339c8517c4STomer Tayar { 23349c8517c4STomer Tayar u8 num_funcs = p_hwfn->num_funcs_on_engine; 23359c8517c4STomer Tayar bool b_ah = QED_IS_AH(p_hwfn->cdev); 23369c8517c4STomer Tayar 23379c8517c4STomer Tayar switch (res_id) { 23389c8517c4STomer Tayar case QED_L2_QUEUE: 23399c8517c4STomer Tayar *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 : 23409c8517c4STomer Tayar MAX_NUM_L2_QUEUES_BB) / num_funcs; 23419c8517c4STomer Tayar break; 23429c8517c4STomer Tayar case QED_VPORT: 23439c8517c4STomer Tayar *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 : 23449c8517c4STomer Tayar MAX_NUM_VPORTS_BB) / num_funcs; 23459c8517c4STomer Tayar break; 23469c8517c4STomer Tayar case QED_RSS_ENG: 23479c8517c4STomer Tayar *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 : 23489c8517c4STomer Tayar ETH_RSS_ENGINE_NUM_BB) / num_funcs; 23499c8517c4STomer Tayar break; 23509c8517c4STomer Tayar case QED_PQ: 23519c8517c4STomer Tayar *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 : 23529c8517c4STomer Tayar MAX_QM_TX_QUEUES_BB) / num_funcs; 23539c8517c4STomer Tayar *p_resc_num &= ~0x7; /* The granularity of the PQs is 8 */ 23549c8517c4STomer Tayar break; 23559c8517c4STomer Tayar case QED_RL: 23569c8517c4STomer Tayar *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs; 23579c8517c4STomer Tayar break; 23589c8517c4STomer Tayar case QED_MAC: 23599c8517c4STomer Tayar case QED_VLAN: 23609c8517c4STomer Tayar /* Each VFC resource can accommodate both a MAC and a VLAN */ 23619c8517c4STomer Tayar *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs; 23629c8517c4STomer Tayar break; 23639c8517c4STomer Tayar case QED_ILT: 23649c8517c4STomer Tayar *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 : 23659c8517c4STomer Tayar PXP_NUM_ILT_RECORDS_BB) / num_funcs; 23669c8517c4STomer Tayar break; 23679c8517c4STomer Tayar case QED_LL2_QUEUE: 23689c8517c4STomer Tayar *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs; 23699c8517c4STomer Tayar break; 23709c8517c4STomer Tayar case QED_RDMA_CNQ_RAM: 23719c8517c4STomer Tayar case QED_CMDQS_CQS: 23729c8517c4STomer Tayar /* CNQ/CMDQS are the same resource */ 2373da090917STomer Tayar *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs; 23749c8517c4STomer Tayar break; 23759c8517c4STomer Tayar case QED_RDMA_STATS_QUEUE: 23769c8517c4STomer Tayar *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 : 23779c8517c4STomer Tayar RDMA_NUM_STATISTIC_COUNTERS_BB) / num_funcs; 23789c8517c4STomer Tayar break; 23799c8517c4STomer Tayar case QED_BDQ: 23809c8517c4STomer Tayar if (p_hwfn->hw_info.personality != QED_PCI_ISCSI && 23819c8517c4STomer Tayar p_hwfn->hw_info.personality != QED_PCI_FCOE) 23829c8517c4STomer Tayar *p_resc_num = 0; 23839c8517c4STomer Tayar else 23849c8517c4STomer Tayar *p_resc_num = 1; 23859c8517c4STomer Tayar break; 23869c8517c4STomer Tayar case QED_SB: 2387ebbdcc66SMintz, Yuval /* Since we want its value to reflect whether MFW supports 2388ebbdcc66SMintz, Yuval * the new scheme, have a default of 0. 2389ebbdcc66SMintz, Yuval */ 2390ebbdcc66SMintz, Yuval *p_resc_num = 0; 23919c8517c4STomer Tayar break; 23929c8517c4STomer Tayar default: 23939c8517c4STomer Tayar return -EINVAL; 23949c8517c4STomer Tayar } 23959c8517c4STomer Tayar 23969c8517c4STomer Tayar switch (res_id) { 23979c8517c4STomer Tayar case QED_BDQ: 23989c8517c4STomer Tayar if (!*p_resc_num) 23999c8517c4STomer Tayar *p_resc_start = 0; 240078cea9ffSTomer Tayar else if (p_hwfn->cdev->num_ports_in_engine == 4) 24019c8517c4STomer Tayar *p_resc_start = p_hwfn->port_id; 24029c8517c4STomer Tayar else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) 24039c8517c4STomer Tayar *p_resc_start = p_hwfn->port_id; 24049c8517c4STomer Tayar else if (p_hwfn->hw_info.personality == QED_PCI_FCOE) 24059c8517c4STomer Tayar *p_resc_start = p_hwfn->port_id + 2; 24069c8517c4STomer Tayar break; 24079c8517c4STomer Tayar default: 24089c8517c4STomer Tayar *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx; 24099c8517c4STomer Tayar break; 24109c8517c4STomer Tayar } 24119c8517c4STomer Tayar 24129c8517c4STomer Tayar return 0; 24139c8517c4STomer Tayar } 24149c8517c4STomer Tayar 24159c8517c4STomer Tayar static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn, 24162edbff8dSTomer Tayar enum qed_resources res_id) 24172edbff8dSTomer Tayar { 24189c8517c4STomer Tayar u32 dflt_resc_num = 0, dflt_resc_start = 0; 24199c8517c4STomer Tayar u32 mcp_resp, *p_resc_num, *p_resc_start; 24202edbff8dSTomer Tayar int rc; 24212edbff8dSTomer Tayar 24222edbff8dSTomer Tayar p_resc_num = &RESC_NUM(p_hwfn, res_id); 24232edbff8dSTomer Tayar p_resc_start = &RESC_START(p_hwfn, res_id); 24242edbff8dSTomer Tayar 24259c8517c4STomer Tayar rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num, 24269c8517c4STomer Tayar &dflt_resc_start); 24279c8517c4STomer Tayar if (rc) { 24282edbff8dSTomer Tayar DP_ERR(p_hwfn, 24292edbff8dSTomer Tayar "Failed to get default amount for resource %d [%s]\n", 24302edbff8dSTomer Tayar res_id, qed_hw_get_resc_name(res_id)); 24319c8517c4STomer Tayar return rc; 24322edbff8dSTomer Tayar } 24332edbff8dSTomer Tayar 24349c8517c4STomer Tayar rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id, 24359c8517c4STomer Tayar &mcp_resp, p_resc_num, p_resc_start); 24362edbff8dSTomer Tayar if (rc) { 24372edbff8dSTomer Tayar DP_NOTICE(p_hwfn, 24382edbff8dSTomer Tayar "MFW response failure for an allocation request for resource %d [%s]\n", 24392edbff8dSTomer Tayar res_id, qed_hw_get_resc_name(res_id)); 24402edbff8dSTomer Tayar return rc; 24412edbff8dSTomer Tayar } 24422edbff8dSTomer Tayar 24432edbff8dSTomer Tayar /* Default driver values are applied in the following cases: 24442edbff8dSTomer Tayar * - The resource allocation MB command is not supported by the MFW 24452edbff8dSTomer Tayar * - There is an internal error in the MFW while processing the request 24462edbff8dSTomer Tayar * - The resource ID is unknown to the MFW 24472edbff8dSTomer Tayar */ 24489c8517c4STomer Tayar if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) { 24499c8517c4STomer Tayar DP_INFO(p_hwfn, 24509c8517c4STomer Tayar "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n", 24512edbff8dSTomer Tayar res_id, 24522edbff8dSTomer Tayar qed_hw_get_resc_name(res_id), 24532edbff8dSTomer Tayar mcp_resp, dflt_resc_num, dflt_resc_start); 24542edbff8dSTomer Tayar *p_resc_num = dflt_resc_num; 24552edbff8dSTomer Tayar *p_resc_start = dflt_resc_start; 24562edbff8dSTomer Tayar goto out; 24572edbff8dSTomer Tayar } 24582edbff8dSTomer Tayar 24592edbff8dSTomer Tayar out: 24602edbff8dSTomer Tayar /* PQs have to divide by 8 [that's the HW granularity]. 24612edbff8dSTomer Tayar * Reduce number so it would fit. 24622edbff8dSTomer Tayar */ 24632edbff8dSTomer Tayar if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) { 24642edbff8dSTomer Tayar DP_INFO(p_hwfn, 24652edbff8dSTomer Tayar "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n", 24662edbff8dSTomer Tayar *p_resc_num, 24672edbff8dSTomer Tayar (*p_resc_num) & ~0x7, 24682edbff8dSTomer Tayar *p_resc_start, (*p_resc_start) & ~0x7); 24692edbff8dSTomer Tayar *p_resc_num &= ~0x7; 24702edbff8dSTomer Tayar *p_resc_start &= ~0x7; 24712edbff8dSTomer Tayar } 24722edbff8dSTomer Tayar 24732edbff8dSTomer Tayar return 0; 24742edbff8dSTomer Tayar } 24752edbff8dSTomer Tayar 24769c8517c4STomer Tayar static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn) 2477fe56b9e6SYuval Mintz { 24789c8517c4STomer Tayar int rc; 24799c8517c4STomer Tayar u8 res_id; 24809c8517c4STomer Tayar 24819c8517c4STomer Tayar for (res_id = 0; res_id < QED_MAX_RESC; res_id++) { 24829c8517c4STomer Tayar rc = __qed_hw_set_resc_info(p_hwfn, res_id); 24839c8517c4STomer Tayar if (rc) 24849c8517c4STomer Tayar return rc; 24859c8517c4STomer Tayar } 24869c8517c4STomer Tayar 24879c8517c4STomer Tayar return 0; 24889c8517c4STomer Tayar } 24899c8517c4STomer Tayar 24909c8517c4STomer Tayar static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 24919c8517c4STomer Tayar { 24929c8517c4STomer Tayar struct qed_resc_unlock_params resc_unlock_params; 24939c8517c4STomer Tayar struct qed_resc_lock_params resc_lock_params; 24949c79ddaaSMintz, Yuval bool b_ah = QED_IS_AH(p_hwfn->cdev); 24952edbff8dSTomer Tayar u8 res_id; 24962edbff8dSTomer Tayar int rc; 2497fe56b9e6SYuval Mintz 24989c8517c4STomer Tayar /* Setting the max values of the soft resources and the following 24999c8517c4STomer Tayar * resources allocation queries should be atomic. Since several PFs can 25009c8517c4STomer Tayar * run in parallel - a resource lock is needed. 25019c8517c4STomer Tayar * If either the resource lock or resource set value commands are not 25029c8517c4STomer Tayar * supported - skip the the max values setting, release the lock if 25039c8517c4STomer Tayar * needed, and proceed to the queries. Other failures, including a 25049c8517c4STomer Tayar * failure to acquire the lock, will cause this function to fail. 25059c8517c4STomer Tayar */ 2506f470f22cSsudarsana.kalluru@cavium.com qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params, 2507f470f22cSsudarsana.kalluru@cavium.com QED_RESC_LOCK_RESC_ALLOC, false); 25089c8517c4STomer Tayar 25099c8517c4STomer Tayar rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params); 25109c8517c4STomer Tayar if (rc && rc != -EINVAL) { 25112edbff8dSTomer Tayar return rc; 25129c8517c4STomer Tayar } else if (rc == -EINVAL) { 25139c8517c4STomer Tayar DP_INFO(p_hwfn, 25149c8517c4STomer Tayar "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n"); 25159c8517c4STomer Tayar } else if (!rc && !resc_lock_params.b_granted) { 25169c8517c4STomer Tayar DP_NOTICE(p_hwfn, 25179c8517c4STomer Tayar "Failed to acquire the resource lock for the resource allocation commands\n"); 25189c8517c4STomer Tayar return -EBUSY; 25199c8517c4STomer Tayar } else { 25209c8517c4STomer Tayar rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt); 25219c8517c4STomer Tayar if (rc && rc != -EINVAL) { 25229c8517c4STomer Tayar DP_NOTICE(p_hwfn, 25239c8517c4STomer Tayar "Failed to set the max values of the soft resources\n"); 25249c8517c4STomer Tayar goto unlock_and_exit; 25259c8517c4STomer Tayar } else if (rc == -EINVAL) { 25269c8517c4STomer Tayar DP_INFO(p_hwfn, 25279c8517c4STomer Tayar "Skip the max values setting of the soft resources since it is not supported by the MFW\n"); 25289c8517c4STomer Tayar rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, 25299c8517c4STomer Tayar &resc_unlock_params); 25309c8517c4STomer Tayar if (rc) 25319c8517c4STomer Tayar DP_INFO(p_hwfn, 25329c8517c4STomer Tayar "Failed to release the resource lock for the resource allocation commands\n"); 25339c8517c4STomer Tayar } 25349c8517c4STomer Tayar } 25359c8517c4STomer Tayar 25369c8517c4STomer Tayar rc = qed_hw_set_resc_info(p_hwfn); 25379c8517c4STomer Tayar if (rc) 25389c8517c4STomer Tayar goto unlock_and_exit; 25399c8517c4STomer Tayar 25409c8517c4STomer Tayar if (resc_lock_params.b_granted && !resc_unlock_params.b_released) { 25419c8517c4STomer Tayar rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params); 25429c8517c4STomer Tayar if (rc) 25439c8517c4STomer Tayar DP_INFO(p_hwfn, 25449c8517c4STomer Tayar "Failed to release the resource lock for the resource allocation commands\n"); 25452edbff8dSTomer Tayar } 2546dbb799c3SYuval Mintz 2547dbb799c3SYuval Mintz /* Sanity for ILT */ 25489c79ddaaSMintz, Yuval if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) || 25499c79ddaaSMintz, Yuval (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) { 2550dbb799c3SYuval Mintz DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n", 2551dbb799c3SYuval Mintz RESC_START(p_hwfn, QED_ILT), 2552dbb799c3SYuval Mintz RESC_END(p_hwfn, QED_ILT) - 1); 2553dbb799c3SYuval Mintz return -EINVAL; 2554dbb799c3SYuval Mintz } 2555fe56b9e6SYuval Mintz 2556ebbdcc66SMintz, Yuval /* This will also learn the number of SBs from MFW */ 2557ebbdcc66SMintz, Yuval if (qed_int_igu_reset_cam(p_hwfn, p_ptt)) 2558ebbdcc66SMintz, Yuval return -EINVAL; 2559ebbdcc66SMintz, Yuval 256025c089d7SYuval Mintz qed_hw_set_feat(p_hwfn); 256125c089d7SYuval Mintz 25622edbff8dSTomer Tayar for (res_id = 0; res_id < QED_MAX_RESC; res_id++) 25632edbff8dSTomer Tayar DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n", 25642edbff8dSTomer Tayar qed_hw_get_resc_name(res_id), 25652edbff8dSTomer Tayar RESC_NUM(p_hwfn, res_id), 25662edbff8dSTomer Tayar RESC_START(p_hwfn, res_id)); 2567dbb799c3SYuval Mintz 2568dbb799c3SYuval Mintz return 0; 25699c8517c4STomer Tayar 25709c8517c4STomer Tayar unlock_and_exit: 25719c8517c4STomer Tayar if (resc_lock_params.b_granted && !resc_unlock_params.b_released) 25729c8517c4STomer Tayar qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params); 25739c8517c4STomer Tayar return rc; 2574fe56b9e6SYuval Mintz } 2575fe56b9e6SYuval Mintz 25761a635e48SYuval Mintz static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2577fe56b9e6SYuval Mintz { 2578fc48b7a6SYuval Mintz u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities; 25791e128c81SArun Easi u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg; 2580645874e5SSudarsana Reddy Kalluru struct qed_mcp_link_capabilities *p_caps; 2581cc875c2eSYuval Mintz struct qed_mcp_link_params *link; 2582fe56b9e6SYuval Mintz 2583fe56b9e6SYuval Mintz /* Read global nvm_cfg address */ 2584fe56b9e6SYuval Mintz nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 2585fe56b9e6SYuval Mintz 2586fe56b9e6SYuval Mintz /* Verify MCP has initialized it */ 2587fe56b9e6SYuval Mintz if (!nvm_cfg_addr) { 2588fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 2589fe56b9e6SYuval Mintz return -EINVAL; 2590fe56b9e6SYuval Mintz } 2591fe56b9e6SYuval Mintz 2592fe56b9e6SYuval Mintz /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */ 2593fe56b9e6SYuval Mintz nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 2594fe56b9e6SYuval Mintz 2595cc875c2eSYuval Mintz addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2596cc875c2eSYuval Mintz offsetof(struct nvm_cfg1, glob) + 2597cc875c2eSYuval Mintz offsetof(struct nvm_cfg1_glob, core_cfg); 2598cc875c2eSYuval Mintz 2599cc875c2eSYuval Mintz core_cfg = qed_rd(p_hwfn, p_ptt, addr); 2600cc875c2eSYuval Mintz 2601cc875c2eSYuval Mintz switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >> 2602cc875c2eSYuval Mintz NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) { 2603351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G: 2604cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G; 2605cc875c2eSYuval Mintz break; 2606351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G: 2607cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G; 2608cc875c2eSYuval Mintz break; 2609351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G: 2610cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G; 2611cc875c2eSYuval Mintz break; 2612351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F: 2613cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F; 2614cc875c2eSYuval Mintz break; 2615351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E: 2616cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E; 2617cc875c2eSYuval Mintz break; 2618351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G: 2619cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G; 2620cc875c2eSYuval Mintz break; 2621351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G: 2622cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G; 2623cc875c2eSYuval Mintz break; 2624351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G: 2625cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G; 2626cc875c2eSYuval Mintz break; 26279c79ddaaSMintz, Yuval case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G: 26289c79ddaaSMintz, Yuval p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G; 26299c79ddaaSMintz, Yuval break; 2630351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G: 2631cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G; 2632cc875c2eSYuval Mintz break; 26339c79ddaaSMintz, Yuval case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G: 26349c79ddaaSMintz, Yuval p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G; 26359c79ddaaSMintz, Yuval break; 2636cc875c2eSYuval Mintz default: 26371a635e48SYuval Mintz DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg); 2638cc875c2eSYuval Mintz break; 2639cc875c2eSYuval Mintz } 2640cc875c2eSYuval Mintz 2641cc875c2eSYuval Mintz /* Read default link configuration */ 2642cc875c2eSYuval Mintz link = &p_hwfn->mcp_info->link_input; 2643645874e5SSudarsana Reddy Kalluru p_caps = &p_hwfn->mcp_info->link_capabilities; 2644cc875c2eSYuval Mintz port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2645cc875c2eSYuval Mintz offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 2646cc875c2eSYuval Mintz link_temp = qed_rd(p_hwfn, p_ptt, 2647cc875c2eSYuval Mintz port_cfg_addr + 2648cc875c2eSYuval Mintz offsetof(struct nvm_cfg1_port, speed_cap_mask)); 264983aeb933SYuval Mintz link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK; 265083aeb933SYuval Mintz link->speed.advertised_speeds = link_temp; 2651cc875c2eSYuval Mintz 265283aeb933SYuval Mintz link_temp = link->speed.advertised_speeds; 265383aeb933SYuval Mintz p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp; 2654cc875c2eSYuval Mintz 2655cc875c2eSYuval Mintz link_temp = qed_rd(p_hwfn, p_ptt, 2656cc875c2eSYuval Mintz port_cfg_addr + 2657cc875c2eSYuval Mintz offsetof(struct nvm_cfg1_port, link_settings)); 2658cc875c2eSYuval Mintz switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >> 2659cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) { 2660cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG: 2661cc875c2eSYuval Mintz link->speed.autoneg = true; 2662cc875c2eSYuval Mintz break; 2663cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_1G: 2664cc875c2eSYuval Mintz link->speed.forced_speed = 1000; 2665cc875c2eSYuval Mintz break; 2666cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_10G: 2667cc875c2eSYuval Mintz link->speed.forced_speed = 10000; 2668cc875c2eSYuval Mintz break; 2669cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_25G: 2670cc875c2eSYuval Mintz link->speed.forced_speed = 25000; 2671cc875c2eSYuval Mintz break; 2672cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_40G: 2673cc875c2eSYuval Mintz link->speed.forced_speed = 40000; 2674cc875c2eSYuval Mintz break; 2675cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_50G: 2676cc875c2eSYuval Mintz link->speed.forced_speed = 50000; 2677cc875c2eSYuval Mintz break; 2678351a4dedSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G: 2679cc875c2eSYuval Mintz link->speed.forced_speed = 100000; 2680cc875c2eSYuval Mintz break; 2681cc875c2eSYuval Mintz default: 26821a635e48SYuval Mintz DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp); 2683cc875c2eSYuval Mintz } 2684cc875c2eSYuval Mintz 268534f9199cSsudarsana.kalluru@cavium.com p_hwfn->mcp_info->link_capabilities.default_speed_autoneg = 268634f9199cSsudarsana.kalluru@cavium.com link->speed.autoneg; 268734f9199cSsudarsana.kalluru@cavium.com 2688cc875c2eSYuval Mintz link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK; 2689cc875c2eSYuval Mintz link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET; 2690cc875c2eSYuval Mintz link->pause.autoneg = !!(link_temp & 2691cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG); 2692cc875c2eSYuval Mintz link->pause.forced_rx = !!(link_temp & 2693cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX); 2694cc875c2eSYuval Mintz link->pause.forced_tx = !!(link_temp & 2695cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX); 2696cc875c2eSYuval Mintz link->loopback_mode = 0; 2697cc875c2eSYuval Mintz 2698645874e5SSudarsana Reddy Kalluru if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) { 2699645874e5SSudarsana Reddy Kalluru link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr + 2700645874e5SSudarsana Reddy Kalluru offsetof(struct nvm_cfg1_port, ext_phy)); 2701645874e5SSudarsana Reddy Kalluru link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK; 2702645874e5SSudarsana Reddy Kalluru link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET; 2703645874e5SSudarsana Reddy Kalluru p_caps->default_eee = QED_MCP_EEE_ENABLED; 2704645874e5SSudarsana Reddy Kalluru link->eee.enable = true; 2705645874e5SSudarsana Reddy Kalluru switch (link_temp) { 2706645874e5SSudarsana Reddy Kalluru case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED: 2707645874e5SSudarsana Reddy Kalluru p_caps->default_eee = QED_MCP_EEE_DISABLED; 2708645874e5SSudarsana Reddy Kalluru link->eee.enable = false; 2709645874e5SSudarsana Reddy Kalluru break; 2710645874e5SSudarsana Reddy Kalluru case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED: 2711645874e5SSudarsana Reddy Kalluru p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME; 2712645874e5SSudarsana Reddy Kalluru break; 2713645874e5SSudarsana Reddy Kalluru case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE: 2714645874e5SSudarsana Reddy Kalluru p_caps->eee_lpi_timer = 2715645874e5SSudarsana Reddy Kalluru EEE_TX_TIMER_USEC_AGGRESSIVE_TIME; 2716645874e5SSudarsana Reddy Kalluru break; 2717645874e5SSudarsana Reddy Kalluru case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY: 2718645874e5SSudarsana Reddy Kalluru p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME; 2719645874e5SSudarsana Reddy Kalluru break; 2720645874e5SSudarsana Reddy Kalluru } 2721645874e5SSudarsana Reddy Kalluru 2722645874e5SSudarsana Reddy Kalluru link->eee.tx_lpi_timer = p_caps->eee_lpi_timer; 2723645874e5SSudarsana Reddy Kalluru link->eee.tx_lpi_enable = link->eee.enable; 2724645874e5SSudarsana Reddy Kalluru link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV; 2725645874e5SSudarsana Reddy Kalluru } else { 2726645874e5SSudarsana Reddy Kalluru p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED; 2727645874e5SSudarsana Reddy Kalluru } 2728645874e5SSudarsana Reddy Kalluru 2729645874e5SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, 2730645874e5SSudarsana Reddy Kalluru NETIF_MSG_LINK, 2731645874e5SSudarsana Reddy Kalluru "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x EEE: %02x [%08x usec]\n", 2732645874e5SSudarsana Reddy Kalluru link->speed.forced_speed, 2733645874e5SSudarsana Reddy Kalluru link->speed.advertised_speeds, 2734645874e5SSudarsana Reddy Kalluru link->speed.autoneg, 2735645874e5SSudarsana Reddy Kalluru link->pause.autoneg, 2736645874e5SSudarsana Reddy Kalluru p_caps->default_eee, p_caps->eee_lpi_timer); 2737cc875c2eSYuval Mintz 2738b51bdfb9SSudarsana Reddy Kalluru if (IS_LEAD_HWFN(p_hwfn)) { 2739b51bdfb9SSudarsana Reddy Kalluru struct qed_dev *cdev = p_hwfn->cdev; 2740b51bdfb9SSudarsana Reddy Kalluru 2741fe56b9e6SYuval Mintz /* Read Multi-function information from shmem */ 2742fe56b9e6SYuval Mintz addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2743fe56b9e6SYuval Mintz offsetof(struct nvm_cfg1, glob) + 2744fe56b9e6SYuval Mintz offsetof(struct nvm_cfg1_glob, generic_cont0); 2745fe56b9e6SYuval Mintz 2746fe56b9e6SYuval Mintz generic_cont0 = qed_rd(p_hwfn, p_ptt, addr); 2747fe56b9e6SYuval Mintz 2748fe56b9e6SYuval Mintz mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >> 2749fe56b9e6SYuval Mintz NVM_CFG1_GLOB_MF_MODE_OFFSET; 2750fe56b9e6SYuval Mintz 2751fe56b9e6SYuval Mintz switch (mf_mode) { 2752fe56b9e6SYuval Mintz case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED: 2753b51bdfb9SSudarsana Reddy Kalluru cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS); 2754b51bdfb9SSudarsana Reddy Kalluru break; 2755cac6f691SSudarsana Reddy Kalluru case NVM_CFG1_GLOB_MF_MODE_UFP: 2756cac6f691SSudarsana Reddy Kalluru cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) | 2757cac6f691SSudarsana Reddy Kalluru BIT(QED_MF_LLH_PROTO_CLSS) | 2758cac6f691SSudarsana Reddy Kalluru BIT(QED_MF_UFP_SPECIFIC) | 2759cac6f691SSudarsana Reddy Kalluru BIT(QED_MF_8021Q_TAGGING); 2760cac6f691SSudarsana Reddy Kalluru break; 2761b51bdfb9SSudarsana Reddy Kalluru case NVM_CFG1_GLOB_MF_MODE_BD: 2762b51bdfb9SSudarsana Reddy Kalluru cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) | 2763b51bdfb9SSudarsana Reddy Kalluru BIT(QED_MF_LLH_PROTO_CLSS) | 2764b51bdfb9SSudarsana Reddy Kalluru BIT(QED_MF_8021AD_TAGGING); 2765fe56b9e6SYuval Mintz break; 2766fe56b9e6SYuval Mintz case NVM_CFG1_GLOB_MF_MODE_NPAR1_0: 2767b51bdfb9SSudarsana Reddy Kalluru cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) | 27680bc5fe85SSudarsana Reddy Kalluru BIT(QED_MF_LLH_PROTO_CLSS) | 27690bc5fe85SSudarsana Reddy Kalluru BIT(QED_MF_LL2_NON_UNICAST) | 27700bc5fe85SSudarsana Reddy Kalluru BIT(QED_MF_INTER_PF_SWITCH); 2771fe56b9e6SYuval Mintz break; 2772fc48b7a6SYuval Mintz case NVM_CFG1_GLOB_MF_MODE_DEFAULT: 2773b51bdfb9SSudarsana Reddy Kalluru cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) | 27740bc5fe85SSudarsana Reddy Kalluru BIT(QED_MF_LLH_PROTO_CLSS) | 27750bc5fe85SSudarsana Reddy Kalluru BIT(QED_MF_LL2_NON_UNICAST); 27760bc5fe85SSudarsana Reddy Kalluru if (QED_IS_BB(p_hwfn->cdev)) 2777b51bdfb9SSudarsana Reddy Kalluru cdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF); 2778fe56b9e6SYuval Mintz break; 2779fe56b9e6SYuval Mintz } 27800bc5fe85SSudarsana Reddy Kalluru 27810bc5fe85SSudarsana Reddy Kalluru DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n", 2782b51bdfb9SSudarsana Reddy Kalluru cdev->mf_bits); 2783b51bdfb9SSudarsana Reddy Kalluru } 2784b51bdfb9SSudarsana Reddy Kalluru 2785b51bdfb9SSudarsana Reddy Kalluru DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n", 27860bc5fe85SSudarsana Reddy Kalluru p_hwfn->cdev->mf_bits); 2787fe56b9e6SYuval Mintz 2788b51bdfb9SSudarsana Reddy Kalluru /* Read device capabilities information from shmem */ 2789fc48b7a6SYuval Mintz addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2790fc48b7a6SYuval Mintz offsetof(struct nvm_cfg1, glob) + 2791fc48b7a6SYuval Mintz offsetof(struct nvm_cfg1_glob, device_capabilities); 2792fc48b7a6SYuval Mintz 2793fc48b7a6SYuval Mintz device_capabilities = qed_rd(p_hwfn, p_ptt, addr); 2794fc48b7a6SYuval Mintz if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET) 2795fc48b7a6SYuval Mintz __set_bit(QED_DEV_CAP_ETH, 2796fc48b7a6SYuval Mintz &p_hwfn->hw_info.device_capabilities); 27971e128c81SArun Easi if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE) 27981e128c81SArun Easi __set_bit(QED_DEV_CAP_FCOE, 27991e128c81SArun Easi &p_hwfn->hw_info.device_capabilities); 2800c5ac9319SYuval Mintz if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI) 2801c5ac9319SYuval Mintz __set_bit(QED_DEV_CAP_ISCSI, 2802c5ac9319SYuval Mintz &p_hwfn->hw_info.device_capabilities); 2803c5ac9319SYuval Mintz if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE) 2804c5ac9319SYuval Mintz __set_bit(QED_DEV_CAP_ROCE, 2805c5ac9319SYuval Mintz &p_hwfn->hw_info.device_capabilities); 2806fc48b7a6SYuval Mintz 2807fe56b9e6SYuval Mintz return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt); 2808fe56b9e6SYuval Mintz } 2809fe56b9e6SYuval Mintz 28101408cc1fSYuval Mintz static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 28111408cc1fSYuval Mintz { 2812dbb799c3SYuval Mintz u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id; 2813dbb799c3SYuval Mintz u32 reg_function_hide, tmp, eng_mask, low_pfs_mask; 28149c79ddaaSMintz, Yuval struct qed_dev *cdev = p_hwfn->cdev; 28151408cc1fSYuval Mintz 28169c79ddaaSMintz, Yuval num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB; 28171408cc1fSYuval Mintz 28181408cc1fSYuval Mintz /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values 28191408cc1fSYuval Mintz * in the other bits are selected. 28201408cc1fSYuval Mintz * Bits 1-15 are for functions 1-15, respectively, and their value is 28211408cc1fSYuval Mintz * '0' only for enabled functions (function 0 always exists and 28221408cc1fSYuval Mintz * enabled). 28231408cc1fSYuval Mintz * In case of CMT, only the "even" functions are enabled, and thus the 28241408cc1fSYuval Mintz * number of functions for both hwfns is learnt from the same bits. 28251408cc1fSYuval Mintz */ 28261408cc1fSYuval Mintz reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE); 28271408cc1fSYuval Mintz 28281408cc1fSYuval Mintz if (reg_function_hide & 0x1) { 28299c79ddaaSMintz, Yuval if (QED_IS_BB(cdev)) { 28309c79ddaaSMintz, Yuval if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) { 28311408cc1fSYuval Mintz num_funcs = 0; 28321408cc1fSYuval Mintz eng_mask = 0xaaaa; 28331408cc1fSYuval Mintz } else { 28341408cc1fSYuval Mintz num_funcs = 1; 28351408cc1fSYuval Mintz eng_mask = 0x5554; 28361408cc1fSYuval Mintz } 28379c79ddaaSMintz, Yuval } else { 28389c79ddaaSMintz, Yuval num_funcs = 1; 28399c79ddaaSMintz, Yuval eng_mask = 0xfffe; 28409c79ddaaSMintz, Yuval } 28411408cc1fSYuval Mintz 28421408cc1fSYuval Mintz /* Get the number of the enabled functions on the engine */ 28431408cc1fSYuval Mintz tmp = (reg_function_hide ^ 0xffffffff) & eng_mask; 28441408cc1fSYuval Mintz while (tmp) { 28451408cc1fSYuval Mintz if (tmp & 0x1) 28461408cc1fSYuval Mintz num_funcs++; 28471408cc1fSYuval Mintz tmp >>= 0x1; 28481408cc1fSYuval Mintz } 2849dbb799c3SYuval Mintz 2850dbb799c3SYuval Mintz /* Get the PF index within the enabled functions */ 2851dbb799c3SYuval Mintz low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1; 2852dbb799c3SYuval Mintz tmp = reg_function_hide & eng_mask & low_pfs_mask; 2853dbb799c3SYuval Mintz while (tmp) { 2854dbb799c3SYuval Mintz if (tmp & 0x1) 2855dbb799c3SYuval Mintz enabled_func_idx--; 2856dbb799c3SYuval Mintz tmp >>= 0x1; 2857dbb799c3SYuval Mintz } 28581408cc1fSYuval Mintz } 28591408cc1fSYuval Mintz 28601408cc1fSYuval Mintz p_hwfn->num_funcs_on_engine = num_funcs; 2861dbb799c3SYuval Mintz p_hwfn->enabled_func_idx = enabled_func_idx; 28621408cc1fSYuval Mintz 28631408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, 28641408cc1fSYuval Mintz NETIF_MSG_PROBE, 2865525ef5c0SYuval Mintz "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n", 28661408cc1fSYuval Mintz p_hwfn->rel_pf_id, 28671408cc1fSYuval Mintz p_hwfn->abs_pf_id, 2868525ef5c0SYuval Mintz p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine); 28691408cc1fSYuval Mintz } 28701408cc1fSYuval Mintz 28719c79ddaaSMintz, Yuval static void qed_hw_info_port_num_bb(struct qed_hwfn *p_hwfn, 28729c79ddaaSMintz, Yuval struct qed_ptt *p_ptt) 2873fe56b9e6SYuval Mintz { 2874fe56b9e6SYuval Mintz u32 port_mode; 2875fe56b9e6SYuval Mintz 2876d52c89f1SMichal Kalderon port_mode = qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB); 2877fe56b9e6SYuval Mintz 2878fe56b9e6SYuval Mintz if (port_mode < 3) { 287978cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine = 1; 2880fe56b9e6SYuval Mintz } else if (port_mode <= 5) { 288178cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine = 2; 2882fe56b9e6SYuval Mintz } else { 2883fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n", 288478cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine); 2885fe56b9e6SYuval Mintz 288678cea9ffSTomer Tayar /* Default num_ports_in_engine to something */ 288778cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine = 1; 2888fe56b9e6SYuval Mintz } 28899c79ddaaSMintz, Yuval } 28909c79ddaaSMintz, Yuval 28919c79ddaaSMintz, Yuval static void qed_hw_info_port_num_ah(struct qed_hwfn *p_hwfn, 28929c79ddaaSMintz, Yuval struct qed_ptt *p_ptt) 28939c79ddaaSMintz, Yuval { 28949c79ddaaSMintz, Yuval u32 port; 28959c79ddaaSMintz, Yuval int i; 28969c79ddaaSMintz, Yuval 289778cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine = 0; 28989c79ddaaSMintz, Yuval 28999c79ddaaSMintz, Yuval for (i = 0; i < MAX_NUM_PORTS_K2; i++) { 29009c79ddaaSMintz, Yuval port = qed_rd(p_hwfn, p_ptt, 29019c79ddaaSMintz, Yuval CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4)); 29029c79ddaaSMintz, Yuval if (port & 1) 290378cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine++; 29049c79ddaaSMintz, Yuval } 29059c79ddaaSMintz, Yuval 290678cea9ffSTomer Tayar if (!p_hwfn->cdev->num_ports_in_engine) { 29079c79ddaaSMintz, Yuval DP_NOTICE(p_hwfn, "All NIG ports are inactive\n"); 29089c79ddaaSMintz, Yuval 29099c79ddaaSMintz, Yuval /* Default num_ports_in_engine to something */ 291078cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine = 1; 29119c79ddaaSMintz, Yuval } 29129c79ddaaSMintz, Yuval } 29139c79ddaaSMintz, Yuval 29149c79ddaaSMintz, Yuval static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 29159c79ddaaSMintz, Yuval { 29169c79ddaaSMintz, Yuval if (QED_IS_BB(p_hwfn->cdev)) 29179c79ddaaSMintz, Yuval qed_hw_info_port_num_bb(p_hwfn, p_ptt); 29189c79ddaaSMintz, Yuval else 29199c79ddaaSMintz, Yuval qed_hw_info_port_num_ah(p_hwfn, p_ptt); 29209c79ddaaSMintz, Yuval } 29219c79ddaaSMintz, Yuval 2922645874e5SSudarsana Reddy Kalluru static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2923645874e5SSudarsana Reddy Kalluru { 2924645874e5SSudarsana Reddy Kalluru struct qed_mcp_link_capabilities *p_caps; 2925645874e5SSudarsana Reddy Kalluru u32 eee_status; 2926645874e5SSudarsana Reddy Kalluru 2927645874e5SSudarsana Reddy Kalluru p_caps = &p_hwfn->mcp_info->link_capabilities; 2928645874e5SSudarsana Reddy Kalluru if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED) 2929645874e5SSudarsana Reddy Kalluru return; 2930645874e5SSudarsana Reddy Kalluru 2931645874e5SSudarsana Reddy Kalluru p_caps->eee_speed_caps = 0; 2932645874e5SSudarsana Reddy Kalluru eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 2933645874e5SSudarsana Reddy Kalluru offsetof(struct public_port, eee_status)); 2934645874e5SSudarsana Reddy Kalluru eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >> 2935645874e5SSudarsana Reddy Kalluru EEE_SUPPORTED_SPEED_OFFSET; 2936645874e5SSudarsana Reddy Kalluru 2937645874e5SSudarsana Reddy Kalluru if (eee_status & EEE_1G_SUPPORTED) 2938645874e5SSudarsana Reddy Kalluru p_caps->eee_speed_caps |= QED_EEE_1G_ADV; 2939645874e5SSudarsana Reddy Kalluru if (eee_status & EEE_10G_ADV) 2940645874e5SSudarsana Reddy Kalluru p_caps->eee_speed_caps |= QED_EEE_10G_ADV; 2941645874e5SSudarsana Reddy Kalluru } 2942645874e5SSudarsana Reddy Kalluru 29439c79ddaaSMintz, Yuval static int 29449c79ddaaSMintz, Yuval qed_get_hw_info(struct qed_hwfn *p_hwfn, 29459c79ddaaSMintz, Yuval struct qed_ptt *p_ptt, 29469c79ddaaSMintz, Yuval enum qed_pci_personality personality) 29479c79ddaaSMintz, Yuval { 29489c79ddaaSMintz, Yuval int rc; 29499c79ddaaSMintz, Yuval 29509c79ddaaSMintz, Yuval /* Since all information is common, only first hwfns should do this */ 29519c79ddaaSMintz, Yuval if (IS_LEAD_HWFN(p_hwfn)) { 29529c79ddaaSMintz, Yuval rc = qed_iov_hw_info(p_hwfn); 29539c79ddaaSMintz, Yuval if (rc) 29549c79ddaaSMintz, Yuval return rc; 29559c79ddaaSMintz, Yuval } 29569c79ddaaSMintz, Yuval 29579c79ddaaSMintz, Yuval qed_hw_info_port_num(p_hwfn, p_ptt); 2958fe56b9e6SYuval Mintz 2959645874e5SSudarsana Reddy Kalluru qed_mcp_get_capabilities(p_hwfn, p_ptt); 2960645874e5SSudarsana Reddy Kalluru 2961fe56b9e6SYuval Mintz qed_hw_get_nvm_info(p_hwfn, p_ptt); 2962fe56b9e6SYuval Mintz 2963fe56b9e6SYuval Mintz rc = qed_int_igu_read_cam(p_hwfn, p_ptt); 2964fe56b9e6SYuval Mintz if (rc) 2965fe56b9e6SYuval Mintz return rc; 2966fe56b9e6SYuval Mintz 2967fe56b9e6SYuval Mintz if (qed_mcp_is_init(p_hwfn)) 2968fe56b9e6SYuval Mintz ether_addr_copy(p_hwfn->hw_info.hw_mac_addr, 2969fe56b9e6SYuval Mintz p_hwfn->mcp_info->func_info.mac); 2970fe56b9e6SYuval Mintz else 2971fe56b9e6SYuval Mintz eth_random_addr(p_hwfn->hw_info.hw_mac_addr); 2972fe56b9e6SYuval Mintz 2973fe56b9e6SYuval Mintz if (qed_mcp_is_init(p_hwfn)) { 2974fe56b9e6SYuval Mintz if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET) 2975fe56b9e6SYuval Mintz p_hwfn->hw_info.ovlan = 2976fe56b9e6SYuval Mintz p_hwfn->mcp_info->func_info.ovlan; 2977fe56b9e6SYuval Mintz 2978fe56b9e6SYuval Mintz qed_mcp_cmd_port_init(p_hwfn, p_ptt); 2979645874e5SSudarsana Reddy Kalluru 2980645874e5SSudarsana Reddy Kalluru qed_get_eee_caps(p_hwfn, p_ptt); 2981cac6f691SSudarsana Reddy Kalluru 2982cac6f691SSudarsana Reddy Kalluru qed_mcp_read_ufp_config(p_hwfn, p_ptt); 2983fe56b9e6SYuval Mintz } 2984fe56b9e6SYuval Mintz 2985fe56b9e6SYuval Mintz if (qed_mcp_is_init(p_hwfn)) { 2986fe56b9e6SYuval Mintz enum qed_pci_personality protocol; 2987fe56b9e6SYuval Mintz 2988fe56b9e6SYuval Mintz protocol = p_hwfn->mcp_info->func_info.protocol; 2989fe56b9e6SYuval Mintz p_hwfn->hw_info.personality = protocol; 2990fe56b9e6SYuval Mintz } 2991fe56b9e6SYuval Mintz 299261be82b0SDenis Bolotin if (QED_IS_ROCE_PERSONALITY(p_hwfn)) 299361be82b0SDenis Bolotin p_hwfn->hw_info.multi_tc_roce_en = 1; 299461be82b0SDenis Bolotin 2995b5a9ee7cSAriel Elior p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2; 2996b5a9ee7cSAriel Elior p_hwfn->hw_info.num_active_tc = 1; 2997b5a9ee7cSAriel Elior 29981408cc1fSYuval Mintz qed_get_num_funcs(p_hwfn, p_ptt); 29991408cc1fSYuval Mintz 30000fefbfbaSSudarsana Kalluru if (qed_mcp_is_init(p_hwfn)) 30010fefbfbaSSudarsana Kalluru p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu; 30020fefbfbaSSudarsana Kalluru 30039c8517c4STomer Tayar return qed_hw_get_resc(p_hwfn, p_ptt); 3004fe56b9e6SYuval Mintz } 3005fe56b9e6SYuval Mintz 300615582962SRahul Verma static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3007fe56b9e6SYuval Mintz { 300815582962SRahul Verma struct qed_dev *cdev = p_hwfn->cdev; 30099c79ddaaSMintz, Yuval u16 device_id_mask; 3010fe56b9e6SYuval Mintz u32 tmp; 3011fe56b9e6SYuval Mintz 3012fc48b7a6SYuval Mintz /* Read Vendor Id / Device Id */ 30131a635e48SYuval Mintz pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id); 30141a635e48SYuval Mintz pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id); 30151a635e48SYuval Mintz 30169c79ddaaSMintz, Yuval /* Determine type */ 30179c79ddaaSMintz, Yuval device_id_mask = cdev->device_id & QED_DEV_ID_MASK; 30189c79ddaaSMintz, Yuval switch (device_id_mask) { 30199c79ddaaSMintz, Yuval case QED_DEV_ID_MASK_BB: 30209c79ddaaSMintz, Yuval cdev->type = QED_DEV_TYPE_BB; 30219c79ddaaSMintz, Yuval break; 30229c79ddaaSMintz, Yuval case QED_DEV_ID_MASK_AH: 30239c79ddaaSMintz, Yuval cdev->type = QED_DEV_TYPE_AH; 30249c79ddaaSMintz, Yuval break; 30259c79ddaaSMintz, Yuval default: 30269c79ddaaSMintz, Yuval DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id); 30279c79ddaaSMintz, Yuval return -EBUSY; 30289c79ddaaSMintz, Yuval } 30299c79ddaaSMintz, Yuval 303015582962SRahul Verma cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM); 303115582962SRahul Verma cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV); 303215582962SRahul Verma 3033fe56b9e6SYuval Mintz MASK_FIELD(CHIP_REV, cdev->chip_rev); 3034fe56b9e6SYuval Mintz 3035fe56b9e6SYuval Mintz /* Learn number of HW-functions */ 303615582962SRahul Verma tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR); 3037fe56b9e6SYuval Mintz 3038fc48b7a6SYuval Mintz if (tmp & (1 << p_hwfn->rel_pf_id)) { 3039fe56b9e6SYuval Mintz DP_NOTICE(cdev->hwfns, "device in CMT mode\n"); 3040fe56b9e6SYuval Mintz cdev->num_hwfns = 2; 3041fe56b9e6SYuval Mintz } else { 3042fe56b9e6SYuval Mintz cdev->num_hwfns = 1; 3043fe56b9e6SYuval Mintz } 3044fe56b9e6SYuval Mintz 304515582962SRahul Verma cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt, 3046fe56b9e6SYuval Mintz MISCS_REG_CHIP_TEST_REG) >> 4; 3047fe56b9e6SYuval Mintz MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id); 304815582962SRahul Verma cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL); 3049fe56b9e6SYuval Mintz MASK_FIELD(CHIP_METAL, cdev->chip_metal); 3050fe56b9e6SYuval Mintz 3051fe56b9e6SYuval Mintz DP_INFO(cdev->hwfns, 30529c79ddaaSMintz, Yuval "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n", 30539c79ddaaSMintz, Yuval QED_IS_BB(cdev) ? "BB" : "AH", 30549c79ddaaSMintz, Yuval 'A' + cdev->chip_rev, 30559c79ddaaSMintz, Yuval (int)cdev->chip_metal, 3056fe56b9e6SYuval Mintz cdev->chip_num, cdev->chip_rev, 3057fe56b9e6SYuval Mintz cdev->chip_bond_id, cdev->chip_metal); 305812e09c69SYuval Mintz 305912e09c69SYuval Mintz return 0; 3060fe56b9e6SYuval Mintz } 3061fe56b9e6SYuval Mintz 306243645ce0SSudarsana Reddy Kalluru static void qed_nvm_info_free(struct qed_hwfn *p_hwfn) 306343645ce0SSudarsana Reddy Kalluru { 306443645ce0SSudarsana Reddy Kalluru kfree(p_hwfn->nvm_info.image_att); 306543645ce0SSudarsana Reddy Kalluru p_hwfn->nvm_info.image_att = NULL; 306643645ce0SSudarsana Reddy Kalluru } 306743645ce0SSudarsana Reddy Kalluru 3068fe56b9e6SYuval Mintz static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn, 3069fe56b9e6SYuval Mintz void __iomem *p_regview, 3070fe56b9e6SYuval Mintz void __iomem *p_doorbells, 3071fe56b9e6SYuval Mintz enum qed_pci_personality personality) 3072fe56b9e6SYuval Mintz { 3073fe56b9e6SYuval Mintz int rc = 0; 3074fe56b9e6SYuval Mintz 3075fe56b9e6SYuval Mintz /* Split PCI bars evenly between hwfns */ 3076fe56b9e6SYuval Mintz p_hwfn->regview = p_regview; 3077fe56b9e6SYuval Mintz p_hwfn->doorbells = p_doorbells; 3078fe56b9e6SYuval Mintz 30791408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 30801408cc1fSYuval Mintz return qed_vf_hw_prepare(p_hwfn); 30811408cc1fSYuval Mintz 3082fe56b9e6SYuval Mintz /* Validate that chip access is feasible */ 3083fe56b9e6SYuval Mintz if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) { 3084fe56b9e6SYuval Mintz DP_ERR(p_hwfn, 3085fe56b9e6SYuval Mintz "Reading the ME register returns all Fs; Preventing further chip access\n"); 3086fe56b9e6SYuval Mintz return -EINVAL; 3087fe56b9e6SYuval Mintz } 3088fe56b9e6SYuval Mintz 3089fe56b9e6SYuval Mintz get_function_id(p_hwfn); 3090fe56b9e6SYuval Mintz 309112e09c69SYuval Mintz /* Allocate PTT pool */ 309212e09c69SYuval Mintz rc = qed_ptt_pool_alloc(p_hwfn); 30932591c280SJoe Perches if (rc) 3094fe56b9e6SYuval Mintz goto err0; 3095fe56b9e6SYuval Mintz 309612e09c69SYuval Mintz /* Allocate the main PTT */ 309712e09c69SYuval Mintz p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN); 309812e09c69SYuval Mintz 3099fe56b9e6SYuval Mintz /* First hwfn learns basic information, e.g., number of hwfns */ 310012e09c69SYuval Mintz if (!p_hwfn->my_id) { 310115582962SRahul Verma rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt); 31021a635e48SYuval Mintz if (rc) 310312e09c69SYuval Mintz goto err1; 310412e09c69SYuval Mintz } 310512e09c69SYuval Mintz 310612e09c69SYuval Mintz qed_hw_hwfn_prepare(p_hwfn); 3107fe56b9e6SYuval Mintz 3108fe56b9e6SYuval Mintz /* Initialize MCP structure */ 3109fe56b9e6SYuval Mintz rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt); 3110fe56b9e6SYuval Mintz if (rc) { 3111fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed initializing mcp command\n"); 3112fe56b9e6SYuval Mintz goto err1; 3113fe56b9e6SYuval Mintz } 3114fe56b9e6SYuval Mintz 3115fe56b9e6SYuval Mintz /* Read the device configuration information from the HW and SHMEM */ 3116fe56b9e6SYuval Mintz rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality); 3117fe56b9e6SYuval Mintz if (rc) { 3118fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed to get HW information\n"); 3119fe56b9e6SYuval Mintz goto err2; 3120fe56b9e6SYuval Mintz } 3121fe56b9e6SYuval Mintz 312218a69e36SMintz, Yuval /* Sending a mailbox to the MFW should be done after qed_get_hw_info() 312318a69e36SMintz, Yuval * is called as it sets the ports number in an engine. 312418a69e36SMintz, Yuval */ 312518a69e36SMintz, Yuval if (IS_LEAD_HWFN(p_hwfn)) { 312618a69e36SMintz, Yuval rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt); 312718a69e36SMintz, Yuval if (rc) 312818a69e36SMintz, Yuval DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n"); 312918a69e36SMintz, Yuval } 313018a69e36SMintz, Yuval 313143645ce0SSudarsana Reddy Kalluru /* NVRAM info initialization and population */ 313243645ce0SSudarsana Reddy Kalluru if (IS_LEAD_HWFN(p_hwfn)) { 313343645ce0SSudarsana Reddy Kalluru rc = qed_mcp_nvm_info_populate(p_hwfn); 313443645ce0SSudarsana Reddy Kalluru if (rc) { 313543645ce0SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 313643645ce0SSudarsana Reddy Kalluru "Failed to populate nvm info shadow\n"); 313743645ce0SSudarsana Reddy Kalluru goto err2; 313843645ce0SSudarsana Reddy Kalluru } 313943645ce0SSudarsana Reddy Kalluru } 314043645ce0SSudarsana Reddy Kalluru 3141fe56b9e6SYuval Mintz /* Allocate the init RT array and initialize the init-ops engine */ 3142fe56b9e6SYuval Mintz rc = qed_init_alloc(p_hwfn); 31432591c280SJoe Perches if (rc) 314443645ce0SSudarsana Reddy Kalluru goto err3; 3145fe56b9e6SYuval Mintz 3146fe56b9e6SYuval Mintz return rc; 314743645ce0SSudarsana Reddy Kalluru err3: 314843645ce0SSudarsana Reddy Kalluru if (IS_LEAD_HWFN(p_hwfn)) 314943645ce0SSudarsana Reddy Kalluru qed_nvm_info_free(p_hwfn); 3150fe56b9e6SYuval Mintz err2: 315132a47e72SYuval Mintz if (IS_LEAD_HWFN(p_hwfn)) 315232a47e72SYuval Mintz qed_iov_free_hw_info(p_hwfn->cdev); 3153fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 3154fe56b9e6SYuval Mintz err1: 3155fe56b9e6SYuval Mintz qed_hw_hwfn_free(p_hwfn); 3156fe56b9e6SYuval Mintz err0: 3157fe56b9e6SYuval Mintz return rc; 3158fe56b9e6SYuval Mintz } 3159fe56b9e6SYuval Mintz 3160fe56b9e6SYuval Mintz int qed_hw_prepare(struct qed_dev *cdev, 3161fe56b9e6SYuval Mintz int personality) 3162fe56b9e6SYuval Mintz { 3163c78df14eSAriel Elior struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 3164c78df14eSAriel Elior int rc; 3165fe56b9e6SYuval Mintz 3166fe56b9e6SYuval Mintz /* Store the precompiled init data ptrs */ 31671408cc1fSYuval Mintz if (IS_PF(cdev)) 3168fe56b9e6SYuval Mintz qed_init_iro_array(cdev); 3169fe56b9e6SYuval Mintz 3170fe56b9e6SYuval Mintz /* Initialize the first hwfn - will learn number of hwfns */ 3171c78df14eSAriel Elior rc = qed_hw_prepare_single(p_hwfn, 3172c78df14eSAriel Elior cdev->regview, 3173fe56b9e6SYuval Mintz cdev->doorbells, personality); 3174fe56b9e6SYuval Mintz if (rc) 3175fe56b9e6SYuval Mintz return rc; 3176fe56b9e6SYuval Mintz 3177c78df14eSAriel Elior personality = p_hwfn->hw_info.personality; 3178fe56b9e6SYuval Mintz 3179fe56b9e6SYuval Mintz /* Initialize the rest of the hwfns */ 3180c78df14eSAriel Elior if (cdev->num_hwfns > 1) { 3181fe56b9e6SYuval Mintz void __iomem *p_regview, *p_doorbell; 3182c78df14eSAriel Elior u8 __iomem *addr; 3183fe56b9e6SYuval Mintz 3184c78df14eSAriel Elior /* adjust bar offset for second engine */ 318515582962SRahul Verma addr = cdev->regview + 318615582962SRahul Verma qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt, 318715582962SRahul Verma BAR_ID_0) / 2; 3188c78df14eSAriel Elior p_regview = addr; 3189c78df14eSAriel Elior 319015582962SRahul Verma addr = cdev->doorbells + 319115582962SRahul Verma qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt, 319215582962SRahul Verma BAR_ID_1) / 2; 3193c78df14eSAriel Elior p_doorbell = addr; 3194c78df14eSAriel Elior 3195c78df14eSAriel Elior /* prepare second hw function */ 3196c78df14eSAriel Elior rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview, 3197fe56b9e6SYuval Mintz p_doorbell, personality); 3198c78df14eSAriel Elior 3199c78df14eSAriel Elior /* in case of error, need to free the previously 3200c78df14eSAriel Elior * initiliazed hwfn 0. 3201c78df14eSAriel Elior */ 3202fe56b9e6SYuval Mintz if (rc) { 32031408cc1fSYuval Mintz if (IS_PF(cdev)) { 3204c78df14eSAriel Elior qed_init_free(p_hwfn); 320543645ce0SSudarsana Reddy Kalluru qed_nvm_info_free(p_hwfn); 3206c78df14eSAriel Elior qed_mcp_free(p_hwfn); 3207c78df14eSAriel Elior qed_hw_hwfn_free(p_hwfn); 3208fe56b9e6SYuval Mintz } 3209fe56b9e6SYuval Mintz } 32101408cc1fSYuval Mintz } 3211fe56b9e6SYuval Mintz 3212c78df14eSAriel Elior return rc; 3213fe56b9e6SYuval Mintz } 3214fe56b9e6SYuval Mintz 3215fe56b9e6SYuval Mintz void qed_hw_remove(struct qed_dev *cdev) 3216fe56b9e6SYuval Mintz { 32170fefbfbaSSudarsana Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 3218fe56b9e6SYuval Mintz int i; 3219fe56b9e6SYuval Mintz 32200fefbfbaSSudarsana Kalluru if (IS_PF(cdev)) 32210fefbfbaSSudarsana Kalluru qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt, 32220fefbfbaSSudarsana Kalluru QED_OV_DRIVER_STATE_NOT_LOADED); 32230fefbfbaSSudarsana Kalluru 3224fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 3225fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 3226fe56b9e6SYuval Mintz 32271408cc1fSYuval Mintz if (IS_VF(cdev)) { 32280b55e27dSYuval Mintz qed_vf_pf_release(p_hwfn); 32291408cc1fSYuval Mintz continue; 32301408cc1fSYuval Mintz } 32311408cc1fSYuval Mintz 3232fe56b9e6SYuval Mintz qed_init_free(p_hwfn); 3233fe56b9e6SYuval Mintz qed_hw_hwfn_free(p_hwfn); 3234fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 3235fe56b9e6SYuval Mintz } 323632a47e72SYuval Mintz 323732a47e72SYuval Mintz qed_iov_free_hw_info(cdev); 323843645ce0SSudarsana Reddy Kalluru 323943645ce0SSudarsana Reddy Kalluru qed_nvm_info_free(p_hwfn); 3240fe56b9e6SYuval Mintz } 3241fe56b9e6SYuval Mintz 3242a91eb52aSYuval Mintz static void qed_chain_free_next_ptr(struct qed_dev *cdev, 3243a91eb52aSYuval Mintz struct qed_chain *p_chain) 3244a91eb52aSYuval Mintz { 3245a91eb52aSYuval Mintz void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL; 3246a91eb52aSYuval Mintz dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0; 3247a91eb52aSYuval Mintz struct qed_chain_next *p_next; 3248a91eb52aSYuval Mintz u32 size, i; 3249a91eb52aSYuval Mintz 3250a91eb52aSYuval Mintz if (!p_virt) 3251a91eb52aSYuval Mintz return; 3252a91eb52aSYuval Mintz 3253a91eb52aSYuval Mintz size = p_chain->elem_size * p_chain->usable_per_page; 3254a91eb52aSYuval Mintz 3255a91eb52aSYuval Mintz for (i = 0; i < p_chain->page_cnt; i++) { 3256a91eb52aSYuval Mintz if (!p_virt) 3257a91eb52aSYuval Mintz break; 3258a91eb52aSYuval Mintz 3259a91eb52aSYuval Mintz p_next = (struct qed_chain_next *)((u8 *)p_virt + size); 3260a91eb52aSYuval Mintz p_virt_next = p_next->next_virt; 3261a91eb52aSYuval Mintz p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys); 3262a91eb52aSYuval Mintz 3263a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 3264a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, p_virt, p_phys); 3265a91eb52aSYuval Mintz 3266a91eb52aSYuval Mintz p_virt = p_virt_next; 3267a91eb52aSYuval Mintz p_phys = p_phys_next; 3268a91eb52aSYuval Mintz } 3269a91eb52aSYuval Mintz } 3270a91eb52aSYuval Mintz 3271a91eb52aSYuval Mintz static void qed_chain_free_single(struct qed_dev *cdev, 3272a91eb52aSYuval Mintz struct qed_chain *p_chain) 3273a91eb52aSYuval Mintz { 3274a91eb52aSYuval Mintz if (!p_chain->p_virt_addr) 3275a91eb52aSYuval Mintz return; 3276a91eb52aSYuval Mintz 3277a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 3278a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 3279a91eb52aSYuval Mintz p_chain->p_virt_addr, p_chain->p_phys_addr); 3280a91eb52aSYuval Mintz } 3281a91eb52aSYuval Mintz 3282a91eb52aSYuval Mintz static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain) 3283a91eb52aSYuval Mintz { 3284a91eb52aSYuval Mintz void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl; 3285a91eb52aSYuval Mintz u32 page_cnt = p_chain->page_cnt, i, pbl_size; 32866d937acfSMintz, Yuval u8 *p_pbl_virt = p_chain->pbl_sp.p_virt_table; 3287a91eb52aSYuval Mintz 3288a91eb52aSYuval Mintz if (!pp_virt_addr_tbl) 3289a91eb52aSYuval Mintz return; 3290a91eb52aSYuval Mintz 32916d937acfSMintz, Yuval if (!p_pbl_virt) 3292a91eb52aSYuval Mintz goto out; 3293a91eb52aSYuval Mintz 3294a91eb52aSYuval Mintz for (i = 0; i < page_cnt; i++) { 3295a91eb52aSYuval Mintz if (!pp_virt_addr_tbl[i]) 3296a91eb52aSYuval Mintz break; 3297a91eb52aSYuval Mintz 3298a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 3299a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 3300a91eb52aSYuval Mintz pp_virt_addr_tbl[i], 3301a91eb52aSYuval Mintz *(dma_addr_t *)p_pbl_virt); 3302a91eb52aSYuval Mintz 3303a91eb52aSYuval Mintz p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE; 3304a91eb52aSYuval Mintz } 3305a91eb52aSYuval Mintz 3306a91eb52aSYuval Mintz pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; 33071a4a6975SMintz, Yuval 33081a4a6975SMintz, Yuval if (!p_chain->b_external_pbl) 3309a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 3310a91eb52aSYuval Mintz pbl_size, 33116d937acfSMintz, Yuval p_chain->pbl_sp.p_virt_table, 33126d937acfSMintz, Yuval p_chain->pbl_sp.p_phys_table); 3313a91eb52aSYuval Mintz out: 3314a91eb52aSYuval Mintz vfree(p_chain->pbl.pp_virt_addr_tbl); 33151a4a6975SMintz, Yuval p_chain->pbl.pp_virt_addr_tbl = NULL; 3316a91eb52aSYuval Mintz } 3317a91eb52aSYuval Mintz 3318a91eb52aSYuval Mintz void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain) 3319a91eb52aSYuval Mintz { 3320a91eb52aSYuval Mintz switch (p_chain->mode) { 3321a91eb52aSYuval Mintz case QED_CHAIN_MODE_NEXT_PTR: 3322a91eb52aSYuval Mintz qed_chain_free_next_ptr(cdev, p_chain); 3323a91eb52aSYuval Mintz break; 3324a91eb52aSYuval Mintz case QED_CHAIN_MODE_SINGLE: 3325a91eb52aSYuval Mintz qed_chain_free_single(cdev, p_chain); 3326a91eb52aSYuval Mintz break; 3327a91eb52aSYuval Mintz case QED_CHAIN_MODE_PBL: 3328a91eb52aSYuval Mintz qed_chain_free_pbl(cdev, p_chain); 3329a91eb52aSYuval Mintz break; 3330a91eb52aSYuval Mintz } 3331a91eb52aSYuval Mintz } 3332a91eb52aSYuval Mintz 3333a91eb52aSYuval Mintz static int 3334a91eb52aSYuval Mintz qed_chain_alloc_sanity_check(struct qed_dev *cdev, 3335a91eb52aSYuval Mintz enum qed_chain_cnt_type cnt_type, 3336a91eb52aSYuval Mintz size_t elem_size, u32 page_cnt) 3337a91eb52aSYuval Mintz { 3338a91eb52aSYuval Mintz u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt; 3339a91eb52aSYuval Mintz 3340a91eb52aSYuval Mintz /* The actual chain size can be larger than the maximal possible value 3341a91eb52aSYuval Mintz * after rounding up the requested elements number to pages, and after 3342a91eb52aSYuval Mintz * taking into acount the unusuable elements (next-ptr elements). 3343a91eb52aSYuval Mintz * The size of a "u16" chain can be (U16_MAX + 1) since the chain 3344a91eb52aSYuval Mintz * size/capacity fields are of a u32 type. 3345a91eb52aSYuval Mintz */ 3346a91eb52aSYuval Mintz if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 && 33473ef310a7STomer Tayar chain_size > ((u32)U16_MAX + 1)) || 33483ef310a7STomer Tayar (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) { 3349a91eb52aSYuval Mintz DP_NOTICE(cdev, 3350a91eb52aSYuval Mintz "The actual chain size (0x%llx) is larger than the maximal possible value\n", 3351a91eb52aSYuval Mintz chain_size); 3352a91eb52aSYuval Mintz return -EINVAL; 3353a91eb52aSYuval Mintz } 3354a91eb52aSYuval Mintz 3355a91eb52aSYuval Mintz return 0; 3356a91eb52aSYuval Mintz } 3357a91eb52aSYuval Mintz 3358a91eb52aSYuval Mintz static int 3359a91eb52aSYuval Mintz qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain) 3360a91eb52aSYuval Mintz { 3361a91eb52aSYuval Mintz void *p_virt = NULL, *p_virt_prev = NULL; 3362a91eb52aSYuval Mintz dma_addr_t p_phys = 0; 3363a91eb52aSYuval Mintz u32 i; 3364a91eb52aSYuval Mintz 3365a91eb52aSYuval Mintz for (i = 0; i < p_chain->page_cnt; i++) { 3366a91eb52aSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 3367a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 3368a91eb52aSYuval Mintz &p_phys, GFP_KERNEL); 33692591c280SJoe Perches if (!p_virt) 3370a91eb52aSYuval Mintz return -ENOMEM; 3371a91eb52aSYuval Mintz 3372a91eb52aSYuval Mintz if (i == 0) { 3373a91eb52aSYuval Mintz qed_chain_init_mem(p_chain, p_virt, p_phys); 3374a91eb52aSYuval Mintz qed_chain_reset(p_chain); 3375a91eb52aSYuval Mintz } else { 3376a91eb52aSYuval Mintz qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, 3377a91eb52aSYuval Mintz p_virt, p_phys); 3378a91eb52aSYuval Mintz } 3379a91eb52aSYuval Mintz 3380a91eb52aSYuval Mintz p_virt_prev = p_virt; 3381a91eb52aSYuval Mintz } 3382a91eb52aSYuval Mintz /* Last page's next element should point to the beginning of the 3383a91eb52aSYuval Mintz * chain. 3384a91eb52aSYuval Mintz */ 3385a91eb52aSYuval Mintz qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, 3386a91eb52aSYuval Mintz p_chain->p_virt_addr, 3387a91eb52aSYuval Mintz p_chain->p_phys_addr); 3388a91eb52aSYuval Mintz 3389a91eb52aSYuval Mintz return 0; 3390a91eb52aSYuval Mintz } 3391a91eb52aSYuval Mintz 3392a91eb52aSYuval Mintz static int 3393a91eb52aSYuval Mintz qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain) 3394a91eb52aSYuval Mintz { 3395a91eb52aSYuval Mintz dma_addr_t p_phys = 0; 3396a91eb52aSYuval Mintz void *p_virt = NULL; 3397a91eb52aSYuval Mintz 3398a91eb52aSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 3399a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL); 34002591c280SJoe Perches if (!p_virt) 3401a91eb52aSYuval Mintz return -ENOMEM; 3402a91eb52aSYuval Mintz 3403a91eb52aSYuval Mintz qed_chain_init_mem(p_chain, p_virt, p_phys); 3404a91eb52aSYuval Mintz qed_chain_reset(p_chain); 3405a91eb52aSYuval Mintz 3406a91eb52aSYuval Mintz return 0; 3407a91eb52aSYuval Mintz } 3408a91eb52aSYuval Mintz 34091a4a6975SMintz, Yuval static int 34101a4a6975SMintz, Yuval qed_chain_alloc_pbl(struct qed_dev *cdev, 34111a4a6975SMintz, Yuval struct qed_chain *p_chain, 34121a4a6975SMintz, Yuval struct qed_chain_ext_pbl *ext_pbl) 3413a91eb52aSYuval Mintz { 3414a91eb52aSYuval Mintz u32 page_cnt = p_chain->page_cnt, size, i; 3415a91eb52aSYuval Mintz dma_addr_t p_phys = 0, p_pbl_phys = 0; 3416a91eb52aSYuval Mintz void **pp_virt_addr_tbl = NULL; 3417a91eb52aSYuval Mintz u8 *p_pbl_virt = NULL; 3418a91eb52aSYuval Mintz void *p_virt = NULL; 3419a91eb52aSYuval Mintz 3420a91eb52aSYuval Mintz size = page_cnt * sizeof(*pp_virt_addr_tbl); 34212591c280SJoe Perches pp_virt_addr_tbl = vzalloc(size); 34222591c280SJoe Perches if (!pp_virt_addr_tbl) 3423a91eb52aSYuval Mintz return -ENOMEM; 3424a91eb52aSYuval Mintz 3425a91eb52aSYuval Mintz /* The allocation of the PBL table is done with its full size, since it 3426a91eb52aSYuval Mintz * is expected to be successive. 3427a91eb52aSYuval Mintz * qed_chain_init_pbl_mem() is called even in a case of an allocation 3428a91eb52aSYuval Mintz * failure, since pp_virt_addr_tbl was previously allocated, and it 3429a91eb52aSYuval Mintz * should be saved to allow its freeing during the error flow. 3430a91eb52aSYuval Mintz */ 3431a91eb52aSYuval Mintz size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; 34321a4a6975SMintz, Yuval 34331a4a6975SMintz, Yuval if (!ext_pbl) { 3434a91eb52aSYuval Mintz p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev, 3435a91eb52aSYuval Mintz size, &p_pbl_phys, GFP_KERNEL); 34361a4a6975SMintz, Yuval } else { 34371a4a6975SMintz, Yuval p_pbl_virt = ext_pbl->p_pbl_virt; 34381a4a6975SMintz, Yuval p_pbl_phys = ext_pbl->p_pbl_phys; 34391a4a6975SMintz, Yuval p_chain->b_external_pbl = true; 34401a4a6975SMintz, Yuval } 34411a4a6975SMintz, Yuval 3442a91eb52aSYuval Mintz qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys, 3443a91eb52aSYuval Mintz pp_virt_addr_tbl); 34442591c280SJoe Perches if (!p_pbl_virt) 3445a91eb52aSYuval Mintz return -ENOMEM; 3446a91eb52aSYuval Mintz 3447a91eb52aSYuval Mintz for (i = 0; i < page_cnt; i++) { 3448a91eb52aSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 3449a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 3450a91eb52aSYuval Mintz &p_phys, GFP_KERNEL); 34512591c280SJoe Perches if (!p_virt) 3452a91eb52aSYuval Mintz return -ENOMEM; 3453a91eb52aSYuval Mintz 3454a91eb52aSYuval Mintz if (i == 0) { 3455a91eb52aSYuval Mintz qed_chain_init_mem(p_chain, p_virt, p_phys); 3456a91eb52aSYuval Mintz qed_chain_reset(p_chain); 3457a91eb52aSYuval Mintz } 3458a91eb52aSYuval Mintz 3459a91eb52aSYuval Mintz /* Fill the PBL table with the physical address of the page */ 3460a91eb52aSYuval Mintz *(dma_addr_t *)p_pbl_virt = p_phys; 3461a91eb52aSYuval Mintz /* Keep the virtual address of the page */ 3462a91eb52aSYuval Mintz p_chain->pbl.pp_virt_addr_tbl[i] = p_virt; 3463a91eb52aSYuval Mintz 3464a91eb52aSYuval Mintz p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE; 3465a91eb52aSYuval Mintz } 3466a91eb52aSYuval Mintz 3467a91eb52aSYuval Mintz return 0; 3468a91eb52aSYuval Mintz } 3469a91eb52aSYuval Mintz 3470fe56b9e6SYuval Mintz int qed_chain_alloc(struct qed_dev *cdev, 3471fe56b9e6SYuval Mintz enum qed_chain_use_mode intended_use, 3472fe56b9e6SYuval Mintz enum qed_chain_mode mode, 3473a91eb52aSYuval Mintz enum qed_chain_cnt_type cnt_type, 34741a4a6975SMintz, Yuval u32 num_elems, 34751a4a6975SMintz, Yuval size_t elem_size, 34761a4a6975SMintz, Yuval struct qed_chain *p_chain, 34771a4a6975SMintz, Yuval struct qed_chain_ext_pbl *ext_pbl) 3478fe56b9e6SYuval Mintz { 3479a91eb52aSYuval Mintz u32 page_cnt; 3480a91eb52aSYuval Mintz int rc = 0; 3481fe56b9e6SYuval Mintz 3482fe56b9e6SYuval Mintz if (mode == QED_CHAIN_MODE_SINGLE) 3483fe56b9e6SYuval Mintz page_cnt = 1; 3484fe56b9e6SYuval Mintz else 3485fe56b9e6SYuval Mintz page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode); 3486fe56b9e6SYuval Mintz 3487a91eb52aSYuval Mintz rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt); 3488a91eb52aSYuval Mintz if (rc) { 3489a91eb52aSYuval Mintz DP_NOTICE(cdev, 34902591c280SJoe Perches "Cannot allocate a chain with the given arguments:\n"); 34912591c280SJoe Perches DP_NOTICE(cdev, 3492a91eb52aSYuval Mintz "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n", 3493a91eb52aSYuval Mintz intended_use, mode, cnt_type, num_elems, elem_size); 3494a91eb52aSYuval Mintz return rc; 3495fe56b9e6SYuval Mintz } 3496fe56b9e6SYuval Mintz 3497a91eb52aSYuval Mintz qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use, 3498a91eb52aSYuval Mintz mode, cnt_type); 3499fe56b9e6SYuval Mintz 3500a91eb52aSYuval Mintz switch (mode) { 3501a91eb52aSYuval Mintz case QED_CHAIN_MODE_NEXT_PTR: 3502a91eb52aSYuval Mintz rc = qed_chain_alloc_next_ptr(cdev, p_chain); 3503a91eb52aSYuval Mintz break; 3504a91eb52aSYuval Mintz case QED_CHAIN_MODE_SINGLE: 3505a91eb52aSYuval Mintz rc = qed_chain_alloc_single(cdev, p_chain); 3506a91eb52aSYuval Mintz break; 3507a91eb52aSYuval Mintz case QED_CHAIN_MODE_PBL: 35081a4a6975SMintz, Yuval rc = qed_chain_alloc_pbl(cdev, p_chain, ext_pbl); 3509a91eb52aSYuval Mintz break; 3510fe56b9e6SYuval Mintz } 3511a91eb52aSYuval Mintz if (rc) 3512a91eb52aSYuval Mintz goto nomem; 3513fe56b9e6SYuval Mintz 3514fe56b9e6SYuval Mintz return 0; 3515fe56b9e6SYuval Mintz 3516fe56b9e6SYuval Mintz nomem: 3517a91eb52aSYuval Mintz qed_chain_free(cdev, p_chain); 3518a91eb52aSYuval Mintz return rc; 3519fe56b9e6SYuval Mintz } 3520fe56b9e6SYuval Mintz 3521a91eb52aSYuval Mintz int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id) 3522cee4d264SManish Chopra { 3523cee4d264SManish Chopra if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) { 3524cee4d264SManish Chopra u16 min, max; 3525cee4d264SManish Chopra 3526cee4d264SManish Chopra min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE); 3527cee4d264SManish Chopra max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE); 3528cee4d264SManish Chopra DP_NOTICE(p_hwfn, 3529cee4d264SManish Chopra "l2_queue id [%d] is not valid, available indices [%d - %d]\n", 3530cee4d264SManish Chopra src_id, min, max); 3531cee4d264SManish Chopra 3532cee4d264SManish Chopra return -EINVAL; 3533cee4d264SManish Chopra } 3534cee4d264SManish Chopra 3535cee4d264SManish Chopra *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id; 3536cee4d264SManish Chopra 3537cee4d264SManish Chopra return 0; 3538cee4d264SManish Chopra } 3539cee4d264SManish Chopra 35401a635e48SYuval Mintz int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id) 3541cee4d264SManish Chopra { 3542cee4d264SManish Chopra if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) { 3543cee4d264SManish Chopra u8 min, max; 3544cee4d264SManish Chopra 3545cee4d264SManish Chopra min = (u8)RESC_START(p_hwfn, QED_VPORT); 3546cee4d264SManish Chopra max = min + RESC_NUM(p_hwfn, QED_VPORT); 3547cee4d264SManish Chopra DP_NOTICE(p_hwfn, 3548cee4d264SManish Chopra "vport id [%d] is not valid, available indices [%d - %d]\n", 3549cee4d264SManish Chopra src_id, min, max); 3550cee4d264SManish Chopra 3551cee4d264SManish Chopra return -EINVAL; 3552cee4d264SManish Chopra } 3553cee4d264SManish Chopra 3554cee4d264SManish Chopra *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id; 3555cee4d264SManish Chopra 3556cee4d264SManish Chopra return 0; 3557cee4d264SManish Chopra } 3558cee4d264SManish Chopra 35591a635e48SYuval Mintz int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id) 3560cee4d264SManish Chopra { 3561cee4d264SManish Chopra if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) { 3562cee4d264SManish Chopra u8 min, max; 3563cee4d264SManish Chopra 3564cee4d264SManish Chopra min = (u8)RESC_START(p_hwfn, QED_RSS_ENG); 3565cee4d264SManish Chopra max = min + RESC_NUM(p_hwfn, QED_RSS_ENG); 3566cee4d264SManish Chopra DP_NOTICE(p_hwfn, 3567cee4d264SManish Chopra "rss_eng id [%d] is not valid, available indices [%d - %d]\n", 3568cee4d264SManish Chopra src_id, min, max); 3569cee4d264SManish Chopra 3570cee4d264SManish Chopra return -EINVAL; 3571cee4d264SManish Chopra } 3572cee4d264SManish Chopra 3573cee4d264SManish Chopra *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id; 3574cee4d264SManish Chopra 3575cee4d264SManish Chopra return 0; 3576cee4d264SManish Chopra } 3577bcd197c8SManish Chopra 35780a7fb11cSYuval Mintz static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low, 35790a7fb11cSYuval Mintz u8 *p_filter) 35800a7fb11cSYuval Mintz { 35810a7fb11cSYuval Mintz *p_high = p_filter[1] | (p_filter[0] << 8); 35820a7fb11cSYuval Mintz *p_low = p_filter[5] | (p_filter[4] << 8) | 35830a7fb11cSYuval Mintz (p_filter[3] << 16) | (p_filter[2] << 24); 35840a7fb11cSYuval Mintz } 35850a7fb11cSYuval Mintz 35860a7fb11cSYuval Mintz int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn, 35870a7fb11cSYuval Mintz struct qed_ptt *p_ptt, u8 *p_filter) 35880a7fb11cSYuval Mintz { 35890a7fb11cSYuval Mintz u32 high = 0, low = 0, en; 35900a7fb11cSYuval Mintz int i; 35910a7fb11cSYuval Mintz 35920bc5fe85SSudarsana Reddy Kalluru if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits)) 35930a7fb11cSYuval Mintz return 0; 35940a7fb11cSYuval Mintz 35950a7fb11cSYuval Mintz qed_llh_mac_to_filter(&high, &low, p_filter); 35960a7fb11cSYuval Mintz 35970a7fb11cSYuval Mintz /* Find a free entry and utilize it */ 35980a7fb11cSYuval Mintz for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 35990a7fb11cSYuval Mintz en = qed_rd(p_hwfn, p_ptt, 36000a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)); 36010a7fb11cSYuval Mintz if (en) 36020a7fb11cSYuval Mintz continue; 36030a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 36040a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 36050a7fb11cSYuval Mintz 2 * i * sizeof(u32), low); 36060a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 36070a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 36080a7fb11cSYuval Mintz (2 * i + 1) * sizeof(u32), high); 36090a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 36100a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0); 36110a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 36120a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 36130a7fb11cSYuval Mintz i * sizeof(u32), 0); 36140a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 36150a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1); 36160a7fb11cSYuval Mintz break; 36170a7fb11cSYuval Mintz } 36180a7fb11cSYuval Mintz if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) { 36190a7fb11cSYuval Mintz DP_NOTICE(p_hwfn, 36200a7fb11cSYuval Mintz "Failed to find an empty LLH filter to utilize\n"); 36210a7fb11cSYuval Mintz return -EINVAL; 36220a7fb11cSYuval Mintz } 36230a7fb11cSYuval Mintz 36240a7fb11cSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 36250a7fb11cSYuval Mintz "mac: %pM is added at %d\n", 36260a7fb11cSYuval Mintz p_filter, i); 36270a7fb11cSYuval Mintz 36280a7fb11cSYuval Mintz return 0; 36290a7fb11cSYuval Mintz } 36300a7fb11cSYuval Mintz 36310a7fb11cSYuval Mintz void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn, 36320a7fb11cSYuval Mintz struct qed_ptt *p_ptt, u8 *p_filter) 36330a7fb11cSYuval Mintz { 36340a7fb11cSYuval Mintz u32 high = 0, low = 0; 36350a7fb11cSYuval Mintz int i; 36360a7fb11cSYuval Mintz 36370bc5fe85SSudarsana Reddy Kalluru if (!test_bit(QED_MF_LLH_MAC_CLSS, &p_hwfn->cdev->mf_bits)) 36380a7fb11cSYuval Mintz return; 36390a7fb11cSYuval Mintz 36400a7fb11cSYuval Mintz qed_llh_mac_to_filter(&high, &low, p_filter); 36410a7fb11cSYuval Mintz 36420a7fb11cSYuval Mintz /* Find the entry and clean it */ 36430a7fb11cSYuval Mintz for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 36440a7fb11cSYuval Mintz if (qed_rd(p_hwfn, p_ptt, 36450a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 36460a7fb11cSYuval Mintz 2 * i * sizeof(u32)) != low) 36470a7fb11cSYuval Mintz continue; 36480a7fb11cSYuval Mintz if (qed_rd(p_hwfn, p_ptt, 36490a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 36500a7fb11cSYuval Mintz (2 * i + 1) * sizeof(u32)) != high) 36510a7fb11cSYuval Mintz continue; 36520a7fb11cSYuval Mintz 36530a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 36540a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0); 36550a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 36560a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0); 36570a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 36580a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 36590a7fb11cSYuval Mintz (2 * i + 1) * sizeof(u32), 0); 36600a7fb11cSYuval Mintz 36610a7fb11cSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 36620a7fb11cSYuval Mintz "mac: %pM is removed from %d\n", 36630a7fb11cSYuval Mintz p_filter, i); 36640a7fb11cSYuval Mintz break; 36650a7fb11cSYuval Mintz } 36660a7fb11cSYuval Mintz if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) 36670a7fb11cSYuval Mintz DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n"); 36680a7fb11cSYuval Mintz } 36690a7fb11cSYuval Mintz 36701e128c81SArun Easi int 36711e128c81SArun Easi qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn, 36721e128c81SArun Easi struct qed_ptt *p_ptt, 36731e128c81SArun Easi u16 source_port_or_eth_type, 36741e128c81SArun Easi u16 dest_port, enum qed_llh_port_filter_type_t type) 36751e128c81SArun Easi { 36761e128c81SArun Easi u32 high = 0, low = 0, en; 36771e128c81SArun Easi int i; 36781e128c81SArun Easi 36790bc5fe85SSudarsana Reddy Kalluru if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits)) 36801e128c81SArun Easi return 0; 36811e128c81SArun Easi 36821e128c81SArun Easi switch (type) { 36831e128c81SArun Easi case QED_LLH_FILTER_ETHERTYPE: 36841e128c81SArun Easi high = source_port_or_eth_type; 36851e128c81SArun Easi break; 36861e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_PORT: 36871e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_PORT: 36881e128c81SArun Easi low = source_port_or_eth_type << 16; 36891e128c81SArun Easi break; 36901e128c81SArun Easi case QED_LLH_FILTER_TCP_DEST_PORT: 36911e128c81SArun Easi case QED_LLH_FILTER_UDP_DEST_PORT: 36921e128c81SArun Easi low = dest_port; 36931e128c81SArun Easi break; 36941e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 36951e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 36961e128c81SArun Easi low = (source_port_or_eth_type << 16) | dest_port; 36971e128c81SArun Easi break; 36981e128c81SArun Easi default: 36991e128c81SArun Easi DP_NOTICE(p_hwfn, 37001e128c81SArun Easi "Non valid LLH protocol filter type %d\n", type); 37011e128c81SArun Easi return -EINVAL; 37021e128c81SArun Easi } 37031e128c81SArun Easi /* Find a free entry and utilize it */ 37041e128c81SArun Easi for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 37051e128c81SArun Easi en = qed_rd(p_hwfn, p_ptt, 37061e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)); 37071e128c81SArun Easi if (en) 37081e128c81SArun Easi continue; 37091e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 37101e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 37111e128c81SArun Easi 2 * i * sizeof(u32), low); 37121e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 37131e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 37141e128c81SArun Easi (2 * i + 1) * sizeof(u32), high); 37151e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 37161e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1); 37171e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 37181e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 37191e128c81SArun Easi i * sizeof(u32), 1 << type); 37201e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 37211e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1); 37221e128c81SArun Easi break; 37231e128c81SArun Easi } 37241e128c81SArun Easi if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) { 37251e128c81SArun Easi DP_NOTICE(p_hwfn, 37261e128c81SArun Easi "Failed to find an empty LLH filter to utilize\n"); 37271e128c81SArun Easi return -EINVAL; 37281e128c81SArun Easi } 37291e128c81SArun Easi switch (type) { 37301e128c81SArun Easi case QED_LLH_FILTER_ETHERTYPE: 37311e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 37321e128c81SArun Easi "ETH type %x is added at %d\n", 37331e128c81SArun Easi source_port_or_eth_type, i); 37341e128c81SArun Easi break; 37351e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_PORT: 37361e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 37371e128c81SArun Easi "TCP src port %x is added at %d\n", 37381e128c81SArun Easi source_port_or_eth_type, i); 37391e128c81SArun Easi break; 37401e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_PORT: 37411e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 37421e128c81SArun Easi "UDP src port %x is added at %d\n", 37431e128c81SArun Easi source_port_or_eth_type, i); 37441e128c81SArun Easi break; 37451e128c81SArun Easi case QED_LLH_FILTER_TCP_DEST_PORT: 37461e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 37471e128c81SArun Easi "TCP dst port %x is added at %d\n", dest_port, i); 37481e128c81SArun Easi break; 37491e128c81SArun Easi case QED_LLH_FILTER_UDP_DEST_PORT: 37501e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 37511e128c81SArun Easi "UDP dst port %x is added at %d\n", dest_port, i); 37521e128c81SArun Easi break; 37531e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 37541e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 37551e128c81SArun Easi "TCP src/dst ports %x/%x are added at %d\n", 37561e128c81SArun Easi source_port_or_eth_type, dest_port, i); 37571e128c81SArun Easi break; 37581e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 37591e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 37601e128c81SArun Easi "UDP src/dst ports %x/%x are added at %d\n", 37611e128c81SArun Easi source_port_or_eth_type, dest_port, i); 37621e128c81SArun Easi break; 37631e128c81SArun Easi } 37641e128c81SArun Easi return 0; 37651e128c81SArun Easi } 37661e128c81SArun Easi 37671e128c81SArun Easi void 37681e128c81SArun Easi qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn, 37691e128c81SArun Easi struct qed_ptt *p_ptt, 37701e128c81SArun Easi u16 source_port_or_eth_type, 37711e128c81SArun Easi u16 dest_port, 37721e128c81SArun Easi enum qed_llh_port_filter_type_t type) 37731e128c81SArun Easi { 37741e128c81SArun Easi u32 high = 0, low = 0; 37751e128c81SArun Easi int i; 37761e128c81SArun Easi 37770bc5fe85SSudarsana Reddy Kalluru if (!test_bit(QED_MF_LLH_PROTO_CLSS, &p_hwfn->cdev->mf_bits)) 37781e128c81SArun Easi return; 37791e128c81SArun Easi 37801e128c81SArun Easi switch (type) { 37811e128c81SArun Easi case QED_LLH_FILTER_ETHERTYPE: 37821e128c81SArun Easi high = source_port_or_eth_type; 37831e128c81SArun Easi break; 37841e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_PORT: 37851e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_PORT: 37861e128c81SArun Easi low = source_port_or_eth_type << 16; 37871e128c81SArun Easi break; 37881e128c81SArun Easi case QED_LLH_FILTER_TCP_DEST_PORT: 37891e128c81SArun Easi case QED_LLH_FILTER_UDP_DEST_PORT: 37901e128c81SArun Easi low = dest_port; 37911e128c81SArun Easi break; 37921e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 37931e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 37941e128c81SArun Easi low = (source_port_or_eth_type << 16) | dest_port; 37951e128c81SArun Easi break; 37961e128c81SArun Easi default: 37971e128c81SArun Easi DP_NOTICE(p_hwfn, 37981e128c81SArun Easi "Non valid LLH protocol filter type %d\n", type); 37991e128c81SArun Easi return; 38001e128c81SArun Easi } 38011e128c81SArun Easi 38021e128c81SArun Easi for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 38031e128c81SArun Easi if (!qed_rd(p_hwfn, p_ptt, 38041e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32))) 38051e128c81SArun Easi continue; 38061e128c81SArun Easi if (!qed_rd(p_hwfn, p_ptt, 38071e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32))) 38081e128c81SArun Easi continue; 38091e128c81SArun Easi if (!(qed_rd(p_hwfn, p_ptt, 38101e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 38111e128c81SArun Easi i * sizeof(u32)) & BIT(type))) 38121e128c81SArun Easi continue; 38131e128c81SArun Easi if (qed_rd(p_hwfn, p_ptt, 38141e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 38151e128c81SArun Easi 2 * i * sizeof(u32)) != low) 38161e128c81SArun Easi continue; 38171e128c81SArun Easi if (qed_rd(p_hwfn, p_ptt, 38181e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 38191e128c81SArun Easi (2 * i + 1) * sizeof(u32)) != high) 38201e128c81SArun Easi continue; 38211e128c81SArun Easi 38221e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 38231e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0); 38241e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 38251e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0); 38261e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 38271e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 38281e128c81SArun Easi i * sizeof(u32), 0); 38291e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 38301e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0); 38311e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 38321e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 38331e128c81SArun Easi (2 * i + 1) * sizeof(u32), 0); 38341e128c81SArun Easi break; 38351e128c81SArun Easi } 38361e128c81SArun Easi 38371e128c81SArun Easi if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) 38381e128c81SArun Easi DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n"); 38391e128c81SArun Easi } 38401e128c81SArun Easi 3841722003acSSudarsana Reddy Kalluru static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 3842722003acSSudarsana Reddy Kalluru u32 hw_addr, void *p_eth_qzone, 3843722003acSSudarsana Reddy Kalluru size_t eth_qzone_size, u8 timeset) 3844722003acSSudarsana Reddy Kalluru { 3845722003acSSudarsana Reddy Kalluru struct coalescing_timeset *p_coal_timeset; 3846722003acSSudarsana Reddy Kalluru 3847722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) { 3848722003acSSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n"); 3849722003acSSudarsana Reddy Kalluru return -EINVAL; 3850722003acSSudarsana Reddy Kalluru } 3851722003acSSudarsana Reddy Kalluru 3852722003acSSudarsana Reddy Kalluru p_coal_timeset = p_eth_qzone; 3853477f2d14SRahul Verma memset(p_eth_qzone, 0, eth_qzone_size); 3854722003acSSudarsana Reddy Kalluru SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset); 3855722003acSSudarsana Reddy Kalluru SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1); 3856722003acSSudarsana Reddy Kalluru qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size); 3857722003acSSudarsana Reddy Kalluru 3858722003acSSudarsana Reddy Kalluru return 0; 3859722003acSSudarsana Reddy Kalluru } 3860722003acSSudarsana Reddy Kalluru 3861477f2d14SRahul Verma int qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle) 3862477f2d14SRahul Verma { 3863477f2d14SRahul Verma struct qed_queue_cid *p_cid = p_handle; 3864477f2d14SRahul Verma struct qed_hwfn *p_hwfn; 3865477f2d14SRahul Verma struct qed_ptt *p_ptt; 3866477f2d14SRahul Verma int rc = 0; 3867477f2d14SRahul Verma 3868477f2d14SRahul Verma p_hwfn = p_cid->p_owner; 3869477f2d14SRahul Verma 3870477f2d14SRahul Verma if (IS_VF(p_hwfn->cdev)) 3871477f2d14SRahul Verma return qed_vf_pf_set_coalesce(p_hwfn, rx_coal, tx_coal, p_cid); 3872477f2d14SRahul Verma 3873477f2d14SRahul Verma p_ptt = qed_ptt_acquire(p_hwfn); 3874477f2d14SRahul Verma if (!p_ptt) 3875477f2d14SRahul Verma return -EAGAIN; 3876477f2d14SRahul Verma 3877477f2d14SRahul Verma if (rx_coal) { 3878477f2d14SRahul Verma rc = qed_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid); 3879477f2d14SRahul Verma if (rc) 3880477f2d14SRahul Verma goto out; 3881477f2d14SRahul Verma p_hwfn->cdev->rx_coalesce_usecs = rx_coal; 3882477f2d14SRahul Verma } 3883477f2d14SRahul Verma 3884477f2d14SRahul Verma if (tx_coal) { 3885477f2d14SRahul Verma rc = qed_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid); 3886477f2d14SRahul Verma if (rc) 3887477f2d14SRahul Verma goto out; 3888477f2d14SRahul Verma p_hwfn->cdev->tx_coalesce_usecs = tx_coal; 3889477f2d14SRahul Verma } 3890477f2d14SRahul Verma out: 3891477f2d14SRahul Verma qed_ptt_release(p_hwfn, p_ptt); 3892477f2d14SRahul Verma return rc; 3893477f2d14SRahul Verma } 3894477f2d14SRahul Verma 3895477f2d14SRahul Verma int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, 3896477f2d14SRahul Verma struct qed_ptt *p_ptt, 3897477f2d14SRahul Verma u16 coalesce, struct qed_queue_cid *p_cid) 3898722003acSSudarsana Reddy Kalluru { 3899722003acSSudarsana Reddy Kalluru struct ustorm_eth_queue_zone eth_qzone; 3900722003acSSudarsana Reddy Kalluru u8 timeset, timer_res; 3901722003acSSudarsana Reddy Kalluru u32 address; 3902722003acSSudarsana Reddy Kalluru int rc; 3903722003acSSudarsana Reddy Kalluru 3904722003acSSudarsana Reddy Kalluru /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 3905722003acSSudarsana Reddy Kalluru if (coalesce <= 0x7F) { 3906722003acSSudarsana Reddy Kalluru timer_res = 0; 3907722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0xFF) { 3908722003acSSudarsana Reddy Kalluru timer_res = 1; 3909722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0x1FF) { 3910722003acSSudarsana Reddy Kalluru timer_res = 2; 3911722003acSSudarsana Reddy Kalluru } else { 3912722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 3913722003acSSudarsana Reddy Kalluru return -EINVAL; 3914722003acSSudarsana Reddy Kalluru } 3915722003acSSudarsana Reddy Kalluru timeset = (u8)(coalesce >> timer_res); 3916722003acSSudarsana Reddy Kalluru 3917477f2d14SRahul Verma rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, 3918477f2d14SRahul Verma p_cid->sb_igu_id, false); 3919722003acSSudarsana Reddy Kalluru if (rc) 3920722003acSSudarsana Reddy Kalluru goto out; 3921722003acSSudarsana Reddy Kalluru 3922477f2d14SRahul Verma address = BAR0_MAP_REG_USDM_RAM + 3923477f2d14SRahul Verma USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id); 3924722003acSSudarsana Reddy Kalluru 3925722003acSSudarsana Reddy Kalluru rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 3926722003acSSudarsana Reddy Kalluru sizeof(struct ustorm_eth_queue_zone), timeset); 3927722003acSSudarsana Reddy Kalluru if (rc) 3928722003acSSudarsana Reddy Kalluru goto out; 3929722003acSSudarsana Reddy Kalluru 3930722003acSSudarsana Reddy Kalluru out: 3931722003acSSudarsana Reddy Kalluru return rc; 3932722003acSSudarsana Reddy Kalluru } 3933722003acSSudarsana Reddy Kalluru 3934477f2d14SRahul Verma int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, 3935477f2d14SRahul Verma struct qed_ptt *p_ptt, 3936477f2d14SRahul Verma u16 coalesce, struct qed_queue_cid *p_cid) 3937722003acSSudarsana Reddy Kalluru { 3938722003acSSudarsana Reddy Kalluru struct xstorm_eth_queue_zone eth_qzone; 3939722003acSSudarsana Reddy Kalluru u8 timeset, timer_res; 3940722003acSSudarsana Reddy Kalluru u32 address; 3941722003acSSudarsana Reddy Kalluru int rc; 3942722003acSSudarsana Reddy Kalluru 3943722003acSSudarsana Reddy Kalluru /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 3944722003acSSudarsana Reddy Kalluru if (coalesce <= 0x7F) { 3945722003acSSudarsana Reddy Kalluru timer_res = 0; 3946722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0xFF) { 3947722003acSSudarsana Reddy Kalluru timer_res = 1; 3948722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0x1FF) { 3949722003acSSudarsana Reddy Kalluru timer_res = 2; 3950722003acSSudarsana Reddy Kalluru } else { 3951722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 3952722003acSSudarsana Reddy Kalluru return -EINVAL; 3953722003acSSudarsana Reddy Kalluru } 3954722003acSSudarsana Reddy Kalluru timeset = (u8)(coalesce >> timer_res); 3955722003acSSudarsana Reddy Kalluru 3956477f2d14SRahul Verma rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, 3957477f2d14SRahul Verma p_cid->sb_igu_id, true); 3958722003acSSudarsana Reddy Kalluru if (rc) 3959722003acSSudarsana Reddy Kalluru goto out; 3960722003acSSudarsana Reddy Kalluru 3961477f2d14SRahul Verma address = BAR0_MAP_REG_XSDM_RAM + 3962477f2d14SRahul Verma XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id); 3963722003acSSudarsana Reddy Kalluru 3964722003acSSudarsana Reddy Kalluru rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 3965722003acSSudarsana Reddy Kalluru sizeof(struct xstorm_eth_queue_zone), timeset); 3966722003acSSudarsana Reddy Kalluru out: 3967722003acSSudarsana Reddy Kalluru return rc; 3968722003acSSudarsana Reddy Kalluru } 3969722003acSSudarsana Reddy Kalluru 3970bcd197c8SManish Chopra /* Calculate final WFQ values for all vports and configure them. 3971bcd197c8SManish Chopra * After this configuration each vport will have 3972bcd197c8SManish Chopra * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT) 3973bcd197c8SManish Chopra */ 3974bcd197c8SManish Chopra static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 3975bcd197c8SManish Chopra struct qed_ptt *p_ptt, 3976bcd197c8SManish Chopra u32 min_pf_rate) 3977bcd197c8SManish Chopra { 3978bcd197c8SManish Chopra struct init_qm_vport_params *vport_params; 3979bcd197c8SManish Chopra int i; 3980bcd197c8SManish Chopra 3981bcd197c8SManish Chopra vport_params = p_hwfn->qm_info.qm_vport_params; 3982bcd197c8SManish Chopra 3983bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 3984bcd197c8SManish Chopra u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 3985bcd197c8SManish Chopra 3986bcd197c8SManish Chopra vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) / 3987bcd197c8SManish Chopra min_pf_rate; 3988bcd197c8SManish Chopra qed_init_vport_wfq(p_hwfn, p_ptt, 3989bcd197c8SManish Chopra vport_params[i].first_tx_pq_id, 3990bcd197c8SManish Chopra vport_params[i].vport_wfq); 3991bcd197c8SManish Chopra } 3992bcd197c8SManish Chopra } 3993bcd197c8SManish Chopra 3994bcd197c8SManish Chopra static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn, 3995bcd197c8SManish Chopra u32 min_pf_rate) 3996bcd197c8SManish Chopra 3997bcd197c8SManish Chopra { 3998bcd197c8SManish Chopra int i; 3999bcd197c8SManish Chopra 4000bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) 4001bcd197c8SManish Chopra p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1; 4002bcd197c8SManish Chopra } 4003bcd197c8SManish Chopra 4004bcd197c8SManish Chopra static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 4005bcd197c8SManish Chopra struct qed_ptt *p_ptt, 4006bcd197c8SManish Chopra u32 min_pf_rate) 4007bcd197c8SManish Chopra { 4008bcd197c8SManish Chopra struct init_qm_vport_params *vport_params; 4009bcd197c8SManish Chopra int i; 4010bcd197c8SManish Chopra 4011bcd197c8SManish Chopra vport_params = p_hwfn->qm_info.qm_vport_params; 4012bcd197c8SManish Chopra 4013bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 4014bcd197c8SManish Chopra qed_init_wfq_default_param(p_hwfn, min_pf_rate); 4015bcd197c8SManish Chopra qed_init_vport_wfq(p_hwfn, p_ptt, 4016bcd197c8SManish Chopra vport_params[i].first_tx_pq_id, 4017bcd197c8SManish Chopra vport_params[i].vport_wfq); 4018bcd197c8SManish Chopra } 4019bcd197c8SManish Chopra } 4020bcd197c8SManish Chopra 4021bcd197c8SManish Chopra /* This function performs several validations for WFQ 4022bcd197c8SManish Chopra * configuration and required min rate for a given vport 4023bcd197c8SManish Chopra * 1. req_rate must be greater than one percent of min_pf_rate. 4024bcd197c8SManish Chopra * 2. req_rate should not cause other vports [not configured for WFQ explicitly] 4025bcd197c8SManish Chopra * rates to get less than one percent of min_pf_rate. 4026bcd197c8SManish Chopra * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate. 4027bcd197c8SManish Chopra */ 4028bcd197c8SManish Chopra static int qed_init_wfq_param(struct qed_hwfn *p_hwfn, 40291a635e48SYuval Mintz u16 vport_id, u32 req_rate, u32 min_pf_rate) 4030bcd197c8SManish Chopra { 4031bcd197c8SManish Chopra u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0; 4032bcd197c8SManish Chopra int non_requested_count = 0, req_count = 0, i, num_vports; 4033bcd197c8SManish Chopra 4034bcd197c8SManish Chopra num_vports = p_hwfn->qm_info.num_vports; 4035bcd197c8SManish Chopra 4036bcd197c8SManish Chopra /* Accounting for the vports which are configured for WFQ explicitly */ 4037bcd197c8SManish Chopra for (i = 0; i < num_vports; i++) { 4038bcd197c8SManish Chopra u32 tmp_speed; 4039bcd197c8SManish Chopra 4040bcd197c8SManish Chopra if ((i != vport_id) && 4041bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[i].configured) { 4042bcd197c8SManish Chopra req_count++; 4043bcd197c8SManish Chopra tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 4044bcd197c8SManish Chopra total_req_min_rate += tmp_speed; 4045bcd197c8SManish Chopra } 4046bcd197c8SManish Chopra } 4047bcd197c8SManish Chopra 4048bcd197c8SManish Chopra /* Include current vport data as well */ 4049bcd197c8SManish Chopra req_count++; 4050bcd197c8SManish Chopra total_req_min_rate += req_rate; 4051bcd197c8SManish Chopra non_requested_count = num_vports - req_count; 4052bcd197c8SManish Chopra 4053bcd197c8SManish Chopra if (req_rate < min_pf_rate / QED_WFQ_UNIT) { 4054bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 4055bcd197c8SManish Chopra "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 4056bcd197c8SManish Chopra vport_id, req_rate, min_pf_rate); 4057bcd197c8SManish Chopra return -EINVAL; 4058bcd197c8SManish Chopra } 4059bcd197c8SManish Chopra 4060bcd197c8SManish Chopra if (num_vports > QED_WFQ_UNIT) { 4061bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 4062bcd197c8SManish Chopra "Number of vports is greater than %d\n", 4063bcd197c8SManish Chopra QED_WFQ_UNIT); 4064bcd197c8SManish Chopra return -EINVAL; 4065bcd197c8SManish Chopra } 4066bcd197c8SManish Chopra 4067bcd197c8SManish Chopra if (total_req_min_rate > min_pf_rate) { 4068bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 4069bcd197c8SManish Chopra "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n", 4070bcd197c8SManish Chopra total_req_min_rate, min_pf_rate); 4071bcd197c8SManish Chopra return -EINVAL; 4072bcd197c8SManish Chopra } 4073bcd197c8SManish Chopra 4074bcd197c8SManish Chopra total_left_rate = min_pf_rate - total_req_min_rate; 4075bcd197c8SManish Chopra 4076bcd197c8SManish Chopra left_rate_per_vp = total_left_rate / non_requested_count; 4077bcd197c8SManish Chopra if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) { 4078bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 4079bcd197c8SManish Chopra "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 4080bcd197c8SManish Chopra left_rate_per_vp, min_pf_rate); 4081bcd197c8SManish Chopra return -EINVAL; 4082bcd197c8SManish Chopra } 4083bcd197c8SManish Chopra 4084bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate; 4085bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[vport_id].configured = true; 4086bcd197c8SManish Chopra 4087bcd197c8SManish Chopra for (i = 0; i < num_vports; i++) { 4088bcd197c8SManish Chopra if (p_hwfn->qm_info.wfq_data[i].configured) 4089bcd197c8SManish Chopra continue; 4090bcd197c8SManish Chopra 4091bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp; 4092bcd197c8SManish Chopra } 4093bcd197c8SManish Chopra 4094bcd197c8SManish Chopra return 0; 4095bcd197c8SManish Chopra } 4096bcd197c8SManish Chopra 4097733def6aSYuval Mintz static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn, 4098733def6aSYuval Mintz struct qed_ptt *p_ptt, u16 vp_id, u32 rate) 4099733def6aSYuval Mintz { 4100733def6aSYuval Mintz struct qed_mcp_link_state *p_link; 4101733def6aSYuval Mintz int rc = 0; 4102733def6aSYuval Mintz 4103733def6aSYuval Mintz p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output; 4104733def6aSYuval Mintz 4105733def6aSYuval Mintz if (!p_link->min_pf_rate) { 4106733def6aSYuval Mintz p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate; 4107733def6aSYuval Mintz p_hwfn->qm_info.wfq_data[vp_id].configured = true; 4108733def6aSYuval Mintz return rc; 4109733def6aSYuval Mintz } 4110733def6aSYuval Mintz 4111733def6aSYuval Mintz rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate); 4112733def6aSYuval Mintz 41131a635e48SYuval Mintz if (!rc) 4114733def6aSYuval Mintz qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, 4115733def6aSYuval Mintz p_link->min_pf_rate); 4116733def6aSYuval Mintz else 4117733def6aSYuval Mintz DP_NOTICE(p_hwfn, 4118733def6aSYuval Mintz "Validation failed while configuring min rate\n"); 4119733def6aSYuval Mintz 4120733def6aSYuval Mintz return rc; 4121733def6aSYuval Mintz } 4122733def6aSYuval Mintz 4123bcd197c8SManish Chopra static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn, 4124bcd197c8SManish Chopra struct qed_ptt *p_ptt, 4125bcd197c8SManish Chopra u32 min_pf_rate) 4126bcd197c8SManish Chopra { 4127bcd197c8SManish Chopra bool use_wfq = false; 4128bcd197c8SManish Chopra int rc = 0; 4129bcd197c8SManish Chopra u16 i; 4130bcd197c8SManish Chopra 4131bcd197c8SManish Chopra /* Validate all pre configured vports for wfq */ 4132bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 4133bcd197c8SManish Chopra u32 rate; 4134bcd197c8SManish Chopra 4135bcd197c8SManish Chopra if (!p_hwfn->qm_info.wfq_data[i].configured) 4136bcd197c8SManish Chopra continue; 4137bcd197c8SManish Chopra 4138bcd197c8SManish Chopra rate = p_hwfn->qm_info.wfq_data[i].min_speed; 4139bcd197c8SManish Chopra use_wfq = true; 4140bcd197c8SManish Chopra 4141bcd197c8SManish Chopra rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate); 4142bcd197c8SManish Chopra if (rc) { 4143bcd197c8SManish Chopra DP_NOTICE(p_hwfn, 4144bcd197c8SManish Chopra "WFQ validation failed while configuring min rate\n"); 4145bcd197c8SManish Chopra break; 4146bcd197c8SManish Chopra } 4147bcd197c8SManish Chopra } 4148bcd197c8SManish Chopra 4149bcd197c8SManish Chopra if (!rc && use_wfq) 4150bcd197c8SManish Chopra qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 4151bcd197c8SManish Chopra else 4152bcd197c8SManish Chopra qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 4153bcd197c8SManish Chopra 4154bcd197c8SManish Chopra return rc; 4155bcd197c8SManish Chopra } 4156bcd197c8SManish Chopra 4157733def6aSYuval Mintz /* Main API for qed clients to configure vport min rate. 4158733def6aSYuval Mintz * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)] 4159733def6aSYuval Mintz * rate - Speed in Mbps needs to be assigned to a given vport. 4160733def6aSYuval Mintz */ 4161733def6aSYuval Mintz int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate) 4162733def6aSYuval Mintz { 4163733def6aSYuval Mintz int i, rc = -EINVAL; 4164733def6aSYuval Mintz 4165733def6aSYuval Mintz /* Currently not supported; Might change in future */ 4166733def6aSYuval Mintz if (cdev->num_hwfns > 1) { 4167733def6aSYuval Mintz DP_NOTICE(cdev, 4168733def6aSYuval Mintz "WFQ configuration is not supported for this device\n"); 4169733def6aSYuval Mintz return rc; 4170733def6aSYuval Mintz } 4171733def6aSYuval Mintz 4172733def6aSYuval Mintz for_each_hwfn(cdev, i) { 4173733def6aSYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 4174733def6aSYuval Mintz struct qed_ptt *p_ptt; 4175733def6aSYuval Mintz 4176733def6aSYuval Mintz p_ptt = qed_ptt_acquire(p_hwfn); 4177733def6aSYuval Mintz if (!p_ptt) 4178733def6aSYuval Mintz return -EBUSY; 4179733def6aSYuval Mintz 4180733def6aSYuval Mintz rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate); 4181733def6aSYuval Mintz 4182d572c430SYuval Mintz if (rc) { 4183733def6aSYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 4184733def6aSYuval Mintz return rc; 4185733def6aSYuval Mintz } 4186733def6aSYuval Mintz 4187733def6aSYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 4188733def6aSYuval Mintz } 4189733def6aSYuval Mintz 4190733def6aSYuval Mintz return rc; 4191733def6aSYuval Mintz } 4192733def6aSYuval Mintz 4193bcd197c8SManish Chopra /* API to configure WFQ from mcp link change */ 41946f437d43SMintz, Yuval void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, 41956f437d43SMintz, Yuval struct qed_ptt *p_ptt, u32 min_pf_rate) 4196bcd197c8SManish Chopra { 4197bcd197c8SManish Chopra int i; 4198bcd197c8SManish Chopra 41993e7cfce2SYuval Mintz if (cdev->num_hwfns > 1) { 42003e7cfce2SYuval Mintz DP_VERBOSE(cdev, 42013e7cfce2SYuval Mintz NETIF_MSG_LINK, 42023e7cfce2SYuval Mintz "WFQ configuration is not supported for this device\n"); 42033e7cfce2SYuval Mintz return; 42043e7cfce2SYuval Mintz } 42053e7cfce2SYuval Mintz 4206bcd197c8SManish Chopra for_each_hwfn(cdev, i) { 4207bcd197c8SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 4208bcd197c8SManish Chopra 42096f437d43SMintz, Yuval __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt, 4210bcd197c8SManish Chopra min_pf_rate); 4211bcd197c8SManish Chopra } 4212bcd197c8SManish Chopra } 42134b01e519SManish Chopra 42144b01e519SManish Chopra int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn, 42154b01e519SManish Chopra struct qed_ptt *p_ptt, 42164b01e519SManish Chopra struct qed_mcp_link_state *p_link, 42174b01e519SManish Chopra u8 max_bw) 42184b01e519SManish Chopra { 42194b01e519SManish Chopra int rc = 0; 42204b01e519SManish Chopra 42214b01e519SManish Chopra p_hwfn->mcp_info->func_info.bandwidth_max = max_bw; 42224b01e519SManish Chopra 42234b01e519SManish Chopra if (!p_link->line_speed && (max_bw != 100)) 42244b01e519SManish Chopra return rc; 42254b01e519SManish Chopra 42264b01e519SManish Chopra p_link->speed = (p_link->line_speed * max_bw) / 100; 42274b01e519SManish Chopra p_hwfn->qm_info.pf_rl = p_link->speed; 42284b01e519SManish Chopra 42294b01e519SManish Chopra /* Since the limiter also affects Tx-switched traffic, we don't want it 42304b01e519SManish Chopra * to limit such traffic in case there's no actual limit. 42314b01e519SManish Chopra * In that case, set limit to imaginary high boundary. 42324b01e519SManish Chopra */ 42334b01e519SManish Chopra if (max_bw == 100) 42344b01e519SManish Chopra p_hwfn->qm_info.pf_rl = 100000; 42354b01e519SManish Chopra 42364b01e519SManish Chopra rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, 42374b01e519SManish Chopra p_hwfn->qm_info.pf_rl); 42384b01e519SManish Chopra 42394b01e519SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 42404b01e519SManish Chopra "Configured MAX bandwidth to be %08x Mb/sec\n", 42414b01e519SManish Chopra p_link->speed); 42424b01e519SManish Chopra 42434b01e519SManish Chopra return rc; 42444b01e519SManish Chopra } 42454b01e519SManish Chopra 42464b01e519SManish Chopra /* Main API to configure PF max bandwidth where bw range is [1 - 100] */ 42474b01e519SManish Chopra int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw) 42484b01e519SManish Chopra { 42494b01e519SManish Chopra int i, rc = -EINVAL; 42504b01e519SManish Chopra 42514b01e519SManish Chopra if (max_bw < 1 || max_bw > 100) { 42524b01e519SManish Chopra DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n"); 42534b01e519SManish Chopra return rc; 42544b01e519SManish Chopra } 42554b01e519SManish Chopra 42564b01e519SManish Chopra for_each_hwfn(cdev, i) { 42574b01e519SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 42584b01e519SManish Chopra struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 42594b01e519SManish Chopra struct qed_mcp_link_state *p_link; 42604b01e519SManish Chopra struct qed_ptt *p_ptt; 42614b01e519SManish Chopra 42624b01e519SManish Chopra p_link = &p_lead->mcp_info->link_output; 42634b01e519SManish Chopra 42644b01e519SManish Chopra p_ptt = qed_ptt_acquire(p_hwfn); 42654b01e519SManish Chopra if (!p_ptt) 42664b01e519SManish Chopra return -EBUSY; 42674b01e519SManish Chopra 42684b01e519SManish Chopra rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, 42694b01e519SManish Chopra p_link, max_bw); 42704b01e519SManish Chopra 42714b01e519SManish Chopra qed_ptt_release(p_hwfn, p_ptt); 42724b01e519SManish Chopra 42734b01e519SManish Chopra if (rc) 42744b01e519SManish Chopra break; 42754b01e519SManish Chopra } 42764b01e519SManish Chopra 42774b01e519SManish Chopra return rc; 42784b01e519SManish Chopra } 4279a64b02d5SManish Chopra 4280a64b02d5SManish Chopra int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn, 4281a64b02d5SManish Chopra struct qed_ptt *p_ptt, 4282a64b02d5SManish Chopra struct qed_mcp_link_state *p_link, 4283a64b02d5SManish Chopra u8 min_bw) 4284a64b02d5SManish Chopra { 4285a64b02d5SManish Chopra int rc = 0; 4286a64b02d5SManish Chopra 4287a64b02d5SManish Chopra p_hwfn->mcp_info->func_info.bandwidth_min = min_bw; 4288a64b02d5SManish Chopra p_hwfn->qm_info.pf_wfq = min_bw; 4289a64b02d5SManish Chopra 4290a64b02d5SManish Chopra if (!p_link->line_speed) 4291a64b02d5SManish Chopra return rc; 4292a64b02d5SManish Chopra 4293a64b02d5SManish Chopra p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100; 4294a64b02d5SManish Chopra 4295a64b02d5SManish Chopra rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw); 4296a64b02d5SManish Chopra 4297a64b02d5SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 4298a64b02d5SManish Chopra "Configured MIN bandwidth to be %d Mb/sec\n", 4299a64b02d5SManish Chopra p_link->min_pf_rate); 4300a64b02d5SManish Chopra 4301a64b02d5SManish Chopra return rc; 4302a64b02d5SManish Chopra } 4303a64b02d5SManish Chopra 4304a64b02d5SManish Chopra /* Main API to configure PF min bandwidth where bw range is [1-100] */ 4305a64b02d5SManish Chopra int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw) 4306a64b02d5SManish Chopra { 4307a64b02d5SManish Chopra int i, rc = -EINVAL; 4308a64b02d5SManish Chopra 4309a64b02d5SManish Chopra if (min_bw < 1 || min_bw > 100) { 4310a64b02d5SManish Chopra DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n"); 4311a64b02d5SManish Chopra return rc; 4312a64b02d5SManish Chopra } 4313a64b02d5SManish Chopra 4314a64b02d5SManish Chopra for_each_hwfn(cdev, i) { 4315a64b02d5SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 4316a64b02d5SManish Chopra struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 4317a64b02d5SManish Chopra struct qed_mcp_link_state *p_link; 4318a64b02d5SManish Chopra struct qed_ptt *p_ptt; 4319a64b02d5SManish Chopra 4320a64b02d5SManish Chopra p_link = &p_lead->mcp_info->link_output; 4321a64b02d5SManish Chopra 4322a64b02d5SManish Chopra p_ptt = qed_ptt_acquire(p_hwfn); 4323a64b02d5SManish Chopra if (!p_ptt) 4324a64b02d5SManish Chopra return -EBUSY; 4325a64b02d5SManish Chopra 4326a64b02d5SManish Chopra rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, 4327a64b02d5SManish Chopra p_link, min_bw); 4328a64b02d5SManish Chopra if (rc) { 4329a64b02d5SManish Chopra qed_ptt_release(p_hwfn, p_ptt); 4330a64b02d5SManish Chopra return rc; 4331a64b02d5SManish Chopra } 4332a64b02d5SManish Chopra 4333a64b02d5SManish Chopra if (p_link->min_pf_rate) { 4334a64b02d5SManish Chopra u32 min_rate = p_link->min_pf_rate; 4335a64b02d5SManish Chopra 4336a64b02d5SManish Chopra rc = __qed_configure_vp_wfq_on_link_change(p_hwfn, 4337a64b02d5SManish Chopra p_ptt, 4338a64b02d5SManish Chopra min_rate); 4339a64b02d5SManish Chopra } 4340a64b02d5SManish Chopra 4341a64b02d5SManish Chopra qed_ptt_release(p_hwfn, p_ptt); 4342a64b02d5SManish Chopra } 4343a64b02d5SManish Chopra 4344a64b02d5SManish Chopra return rc; 4345a64b02d5SManish Chopra } 4346733def6aSYuval Mintz 4347733def6aSYuval Mintz void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 4348733def6aSYuval Mintz { 4349733def6aSYuval Mintz struct qed_mcp_link_state *p_link; 4350733def6aSYuval Mintz 4351733def6aSYuval Mintz p_link = &p_hwfn->mcp_info->link_output; 4352733def6aSYuval Mintz 4353733def6aSYuval Mintz if (p_link->min_pf_rate) 4354733def6aSYuval Mintz qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, 4355733def6aSYuval Mintz p_link->min_pf_rate); 4356733def6aSYuval Mintz 4357733def6aSYuval Mintz memset(p_hwfn->qm_info.wfq_data, 0, 4358733def6aSYuval Mintz sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports); 4359733def6aSYuval Mintz } 43609c79ddaaSMintz, Yuval 43619c79ddaaSMintz, Yuval int qed_device_num_engines(struct qed_dev *cdev) 43629c79ddaaSMintz, Yuval { 43639c79ddaaSMintz, Yuval return QED_IS_BB(cdev) ? 2 : 1; 43649c79ddaaSMintz, Yuval } 4365db82f70eSsudarsana.kalluru@cavium.com 4366db82f70eSsudarsana.kalluru@cavium.com static int qed_device_num_ports(struct qed_dev *cdev) 4367db82f70eSsudarsana.kalluru@cavium.com { 4368db82f70eSsudarsana.kalluru@cavium.com /* in CMT always only one port */ 4369db82f70eSsudarsana.kalluru@cavium.com if (cdev->num_hwfns > 1) 4370db82f70eSsudarsana.kalluru@cavium.com return 1; 4371db82f70eSsudarsana.kalluru@cavium.com 437278cea9ffSTomer Tayar return cdev->num_ports_in_engine * qed_device_num_engines(cdev); 4373db82f70eSsudarsana.kalluru@cavium.com } 4374db82f70eSsudarsana.kalluru@cavium.com 4375db82f70eSsudarsana.kalluru@cavium.com int qed_device_get_port_id(struct qed_dev *cdev) 4376db82f70eSsudarsana.kalluru@cavium.com { 4377db82f70eSsudarsana.kalluru@cavium.com return (QED_LEADING_HWFN(cdev)->abs_pf_id) % qed_device_num_ports(cdev); 4378db82f70eSsudarsana.kalluru@cavium.com } 4379456a5849SKalderon, Michal 4380456a5849SKalderon, Michal void qed_set_fw_mac_addr(__le16 *fw_msb, 4381456a5849SKalderon, Michal __le16 *fw_mid, __le16 *fw_lsb, u8 *mac) 4382456a5849SKalderon, Michal { 4383456a5849SKalderon, Michal ((u8 *)fw_msb)[0] = mac[1]; 4384456a5849SKalderon, Michal ((u8 *)fw_msb)[1] = mac[0]; 4385456a5849SKalderon, Michal ((u8 *)fw_mid)[0] = mac[3]; 4386456a5849SKalderon, Michal ((u8 *)fw_mid)[1] = mac[2]; 4387456a5849SKalderon, Michal ((u8 *)fw_lsb)[0] = mac[5]; 4388456a5849SKalderon, Michal ((u8 *)fw_lsb)[1] = mac[4]; 4389456a5849SKalderon, Michal } 4390