11f4d4ed6SAlexander Lobakin // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 3e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 4663eacd8SAlexander Lobakin * Copyright (c) 2019-2020 Marvell International Ltd. 5fe56b9e6SYuval Mintz */ 6fe56b9e6SYuval Mintz 7fe56b9e6SYuval Mintz #include <linux/types.h> 8fe56b9e6SYuval Mintz #include <asm/byteorder.h> 9fe56b9e6SYuval Mintz #include <linux/io.h> 10fe56b9e6SYuval Mintz #include <linux/delay.h> 11fe56b9e6SYuval Mintz #include <linux/dma-mapping.h> 12fe56b9e6SYuval Mintz #include <linux/errno.h> 13fe56b9e6SYuval Mintz #include <linux/kernel.h> 14fe56b9e6SYuval Mintz #include <linux/mutex.h> 15fe56b9e6SYuval Mintz #include <linux/pci.h> 16fe56b9e6SYuval Mintz #include <linux/slab.h> 17fe56b9e6SYuval Mintz #include <linux/string.h> 18a91eb52aSYuval Mintz #include <linux/vmalloc.h> 19fe56b9e6SYuval Mintz #include <linux/etherdevice.h> 20fe56b9e6SYuval Mintz #include <linux/qed/qed_chain.h> 21fe56b9e6SYuval Mintz #include <linux/qed/qed_if.h> 22fe56b9e6SYuval Mintz #include "qed.h" 23fe56b9e6SYuval Mintz #include "qed_cxt.h" 2439651abdSSudarsana Reddy Kalluru #include "qed_dcbx.h" 25fe56b9e6SYuval Mintz #include "qed_dev_api.h" 261e128c81SArun Easi #include "qed_fcoe.h" 27fe56b9e6SYuval Mintz #include "qed_hsi.h" 28fe56b9e6SYuval Mintz #include "qed_hw.h" 29fe56b9e6SYuval Mintz #include "qed_init_ops.h" 30fe56b9e6SYuval Mintz #include "qed_int.h" 31fc831825SYuval Mintz #include "qed_iscsi.h" 320a7fb11cSYuval Mintz #include "qed_ll2.h" 33fe56b9e6SYuval Mintz #include "qed_mcp.h" 341d6cff4fSYuval Mintz #include "qed_ooo.h" 35fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 36fe56b9e6SYuval Mintz #include "qed_sp.h" 3732a47e72SYuval Mintz #include "qed_sriov.h" 380b55e27dSYuval Mintz #include "qed_vf.h" 39b71b9afdSKalderon, Michal #include "qed_rdma.h" 40fe56b9e6SYuval Mintz 410caf5b26SWei Yongjun static DEFINE_SPINLOCK(qm_lock); 4239651abdSSudarsana Reddy Kalluru 4336907cd5SAriel Elior /******************** Doorbell Recovery *******************/ 4436907cd5SAriel Elior /* The doorbell recovery mechanism consists of a list of entries which represent 4536907cd5SAriel Elior * doorbelling entities (l2 queues, roce sq/rq/cqs, the slowpath spq, etc). Each 4636907cd5SAriel Elior * entity needs to register with the mechanism and provide the parameters 4736907cd5SAriel Elior * describing it's doorbell, including a location where last used doorbell data 4836907cd5SAriel Elior * can be found. The doorbell execute function will traverse the list and 4936907cd5SAriel Elior * doorbell all of the registered entries. 5036907cd5SAriel Elior */ 5136907cd5SAriel Elior struct qed_db_recovery_entry { 5236907cd5SAriel Elior struct list_head list_entry; 5336907cd5SAriel Elior void __iomem *db_addr; 5436907cd5SAriel Elior void *db_data; 5536907cd5SAriel Elior enum qed_db_rec_width db_width; 5636907cd5SAriel Elior enum qed_db_rec_space db_space; 5736907cd5SAriel Elior u8 hwfn_idx; 5836907cd5SAriel Elior }; 5936907cd5SAriel Elior 6036907cd5SAriel Elior /* Display a single doorbell recovery entry */ 6136907cd5SAriel Elior static void qed_db_recovery_dp_entry(struct qed_hwfn *p_hwfn, 6236907cd5SAriel Elior struct qed_db_recovery_entry *db_entry, 6336907cd5SAriel Elior char *action) 6436907cd5SAriel Elior { 6536907cd5SAriel Elior DP_VERBOSE(p_hwfn, 6636907cd5SAriel Elior QED_MSG_SPQ, 6736907cd5SAriel Elior "(%s: db_entry %p, addr %p, data %p, width %s, %s space, hwfn %d)\n", 6836907cd5SAriel Elior action, 6936907cd5SAriel Elior db_entry, 7036907cd5SAriel Elior db_entry->db_addr, 7136907cd5SAriel Elior db_entry->db_data, 7236907cd5SAriel Elior db_entry->db_width == DB_REC_WIDTH_32B ? "32b" : "64b", 7336907cd5SAriel Elior db_entry->db_space == DB_REC_USER ? "user" : "kernel", 7436907cd5SAriel Elior db_entry->hwfn_idx); 7536907cd5SAriel Elior } 7636907cd5SAriel Elior 7736907cd5SAriel Elior /* Doorbell address sanity (address within doorbell bar range) */ 7836907cd5SAriel Elior static bool qed_db_rec_sanity(struct qed_dev *cdev, 79b61b04adSDenis Bolotin void __iomem *db_addr, 80b61b04adSDenis Bolotin enum qed_db_rec_width db_width, 81b61b04adSDenis Bolotin void *db_data) 8236907cd5SAriel Elior { 83b61b04adSDenis Bolotin u32 width = (db_width == DB_REC_WIDTH_32B) ? 32 : 64; 84b61b04adSDenis Bolotin 8536907cd5SAriel Elior /* Make sure doorbell address is within the doorbell bar */ 8636907cd5SAriel Elior if (db_addr < cdev->doorbells || 87b61b04adSDenis Bolotin (u8 __iomem *)db_addr + width > 8836907cd5SAriel Elior (u8 __iomem *)cdev->doorbells + cdev->db_size) { 8936907cd5SAriel Elior WARN(true, 9036907cd5SAriel Elior "Illegal doorbell address: %p. Legal range for doorbell addresses is [%p..%p]\n", 9136907cd5SAriel Elior db_addr, 9236907cd5SAriel Elior cdev->doorbells, 9336907cd5SAriel Elior (u8 __iomem *)cdev->doorbells + cdev->db_size); 9436907cd5SAriel Elior return false; 9536907cd5SAriel Elior } 9636907cd5SAriel Elior 9736907cd5SAriel Elior /* ake sure doorbell data pointer is not null */ 9836907cd5SAriel Elior if (!db_data) { 9936907cd5SAriel Elior WARN(true, "Illegal doorbell data pointer: %p", db_data); 10036907cd5SAriel Elior return false; 10136907cd5SAriel Elior } 10236907cd5SAriel Elior 10336907cd5SAriel Elior return true; 10436907cd5SAriel Elior } 10536907cd5SAriel Elior 10636907cd5SAriel Elior /* Find hwfn according to the doorbell address */ 10736907cd5SAriel Elior static struct qed_hwfn *qed_db_rec_find_hwfn(struct qed_dev *cdev, 10836907cd5SAriel Elior void __iomem *db_addr) 10936907cd5SAriel Elior { 11036907cd5SAriel Elior struct qed_hwfn *p_hwfn; 11136907cd5SAriel Elior 11236907cd5SAriel Elior /* In CMT doorbell bar is split down the middle between engine 0 and enigne 1 */ 11336907cd5SAriel Elior if (cdev->num_hwfns > 1) 11436907cd5SAriel Elior p_hwfn = db_addr < cdev->hwfns[1].doorbells ? 11536907cd5SAriel Elior &cdev->hwfns[0] : &cdev->hwfns[1]; 11636907cd5SAriel Elior else 11736907cd5SAriel Elior p_hwfn = QED_LEADING_HWFN(cdev); 11836907cd5SAriel Elior 11936907cd5SAriel Elior return p_hwfn; 12036907cd5SAriel Elior } 12136907cd5SAriel Elior 12236907cd5SAriel Elior /* Add a new entry to the doorbell recovery mechanism */ 12336907cd5SAriel Elior int qed_db_recovery_add(struct qed_dev *cdev, 12436907cd5SAriel Elior void __iomem *db_addr, 12536907cd5SAriel Elior void *db_data, 12636907cd5SAriel Elior enum qed_db_rec_width db_width, 12736907cd5SAriel Elior enum qed_db_rec_space db_space) 12836907cd5SAriel Elior { 12936907cd5SAriel Elior struct qed_db_recovery_entry *db_entry; 13036907cd5SAriel Elior struct qed_hwfn *p_hwfn; 13136907cd5SAriel Elior 13236907cd5SAriel Elior /* Shortcircuit VFs, for now */ 13336907cd5SAriel Elior if (IS_VF(cdev)) { 13436907cd5SAriel Elior DP_VERBOSE(cdev, 13536907cd5SAriel Elior QED_MSG_IOV, "db recovery - skipping VF doorbell\n"); 13636907cd5SAriel Elior return 0; 13736907cd5SAriel Elior } 13836907cd5SAriel Elior 13936907cd5SAriel Elior /* Sanitize doorbell address */ 140b61b04adSDenis Bolotin if (!qed_db_rec_sanity(cdev, db_addr, db_width, db_data)) 14136907cd5SAriel Elior return -EINVAL; 14236907cd5SAriel Elior 14336907cd5SAriel Elior /* Obtain hwfn from doorbell address */ 14436907cd5SAriel Elior p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr); 14536907cd5SAriel Elior 14636907cd5SAriel Elior /* Create entry */ 14736907cd5SAriel Elior db_entry = kzalloc(sizeof(*db_entry), GFP_KERNEL); 14836907cd5SAriel Elior if (!db_entry) { 14936907cd5SAriel Elior DP_NOTICE(cdev, "Failed to allocate a db recovery entry\n"); 15036907cd5SAriel Elior return -ENOMEM; 15136907cd5SAriel Elior } 15236907cd5SAriel Elior 15336907cd5SAriel Elior /* Populate entry */ 15436907cd5SAriel Elior db_entry->db_addr = db_addr; 15536907cd5SAriel Elior db_entry->db_data = db_data; 15636907cd5SAriel Elior db_entry->db_width = db_width; 15736907cd5SAriel Elior db_entry->db_space = db_space; 15836907cd5SAriel Elior db_entry->hwfn_idx = p_hwfn->my_id; 15936907cd5SAriel Elior 16036907cd5SAriel Elior /* Display */ 16136907cd5SAriel Elior qed_db_recovery_dp_entry(p_hwfn, db_entry, "Adding"); 16236907cd5SAriel Elior 16336907cd5SAriel Elior /* Protect the list */ 16436907cd5SAriel Elior spin_lock_bh(&p_hwfn->db_recovery_info.lock); 16536907cd5SAriel Elior list_add_tail(&db_entry->list_entry, &p_hwfn->db_recovery_info.list); 16636907cd5SAriel Elior spin_unlock_bh(&p_hwfn->db_recovery_info.lock); 16736907cd5SAriel Elior 16836907cd5SAriel Elior return 0; 16936907cd5SAriel Elior } 17036907cd5SAriel Elior 17136907cd5SAriel Elior /* Remove an entry from the doorbell recovery mechanism */ 17236907cd5SAriel Elior int qed_db_recovery_del(struct qed_dev *cdev, 17336907cd5SAriel Elior void __iomem *db_addr, void *db_data) 17436907cd5SAriel Elior { 17536907cd5SAriel Elior struct qed_db_recovery_entry *db_entry = NULL; 17636907cd5SAriel Elior struct qed_hwfn *p_hwfn; 17736907cd5SAriel Elior int rc = -EINVAL; 17836907cd5SAriel Elior 17936907cd5SAriel Elior /* Shortcircuit VFs, for now */ 18036907cd5SAriel Elior if (IS_VF(cdev)) { 18136907cd5SAriel Elior DP_VERBOSE(cdev, 18236907cd5SAriel Elior QED_MSG_IOV, "db recovery - skipping VF doorbell\n"); 18336907cd5SAriel Elior return 0; 18436907cd5SAriel Elior } 18536907cd5SAriel Elior 18636907cd5SAriel Elior /* Obtain hwfn from doorbell address */ 18736907cd5SAriel Elior p_hwfn = qed_db_rec_find_hwfn(cdev, db_addr); 18836907cd5SAriel Elior 18936907cd5SAriel Elior /* Protect the list */ 19036907cd5SAriel Elior spin_lock_bh(&p_hwfn->db_recovery_info.lock); 19136907cd5SAriel Elior list_for_each_entry(db_entry, 19236907cd5SAriel Elior &p_hwfn->db_recovery_info.list, list_entry) { 19336907cd5SAriel Elior /* search according to db_data addr since db_addr is not unique (roce) */ 19436907cd5SAriel Elior if (db_entry->db_data == db_data) { 19536907cd5SAriel Elior qed_db_recovery_dp_entry(p_hwfn, db_entry, "Deleting"); 19636907cd5SAriel Elior list_del(&db_entry->list_entry); 19736907cd5SAriel Elior rc = 0; 19836907cd5SAriel Elior break; 19936907cd5SAriel Elior } 20036907cd5SAriel Elior } 20136907cd5SAriel Elior 20236907cd5SAriel Elior spin_unlock_bh(&p_hwfn->db_recovery_info.lock); 20336907cd5SAriel Elior 20436907cd5SAriel Elior if (rc == -EINVAL) 20536907cd5SAriel Elior 20636907cd5SAriel Elior DP_NOTICE(p_hwfn, 20736907cd5SAriel Elior "Failed to find element in list. Key (db_data addr) was %p. db_addr was %p\n", 20836907cd5SAriel Elior db_data, db_addr); 20936907cd5SAriel Elior else 21036907cd5SAriel Elior kfree(db_entry); 21136907cd5SAriel Elior 21236907cd5SAriel Elior return rc; 21336907cd5SAriel Elior } 21436907cd5SAriel Elior 21536907cd5SAriel Elior /* Initialize the doorbell recovery mechanism */ 21636907cd5SAriel Elior static int qed_db_recovery_setup(struct qed_hwfn *p_hwfn) 21736907cd5SAriel Elior { 21836907cd5SAriel Elior DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Setting up db recovery\n"); 21936907cd5SAriel Elior 22036907cd5SAriel Elior /* Make sure db_size was set in cdev */ 22136907cd5SAriel Elior if (!p_hwfn->cdev->db_size) { 22236907cd5SAriel Elior DP_ERR(p_hwfn->cdev, "db_size not set\n"); 22336907cd5SAriel Elior return -EINVAL; 22436907cd5SAriel Elior } 22536907cd5SAriel Elior 22636907cd5SAriel Elior INIT_LIST_HEAD(&p_hwfn->db_recovery_info.list); 22736907cd5SAriel Elior spin_lock_init(&p_hwfn->db_recovery_info.lock); 22836907cd5SAriel Elior p_hwfn->db_recovery_info.db_recovery_counter = 0; 22936907cd5SAriel Elior 23036907cd5SAriel Elior return 0; 23136907cd5SAriel Elior } 23236907cd5SAriel Elior 23336907cd5SAriel Elior /* Destroy the doorbell recovery mechanism */ 23436907cd5SAriel Elior static void qed_db_recovery_teardown(struct qed_hwfn *p_hwfn) 23536907cd5SAriel Elior { 23636907cd5SAriel Elior struct qed_db_recovery_entry *db_entry = NULL; 23736907cd5SAriel Elior 23836907cd5SAriel Elior DP_VERBOSE(p_hwfn, QED_MSG_SPQ, "Tearing down db recovery\n"); 23936907cd5SAriel Elior if (!list_empty(&p_hwfn->db_recovery_info.list)) { 24036907cd5SAriel Elior DP_VERBOSE(p_hwfn, 24136907cd5SAriel Elior QED_MSG_SPQ, 24236907cd5SAriel Elior "Doorbell Recovery teardown found the doorbell recovery list was not empty (Expected in disorderly driver unload (e.g. recovery) otherwise this probably means some flow forgot to db_recovery_del). Prepare to purge doorbell recovery list...\n"); 24336907cd5SAriel Elior while (!list_empty(&p_hwfn->db_recovery_info.list)) { 24436907cd5SAriel Elior db_entry = 24536907cd5SAriel Elior list_first_entry(&p_hwfn->db_recovery_info.list, 24636907cd5SAriel Elior struct qed_db_recovery_entry, 24736907cd5SAriel Elior list_entry); 24836907cd5SAriel Elior qed_db_recovery_dp_entry(p_hwfn, db_entry, "Purging"); 24936907cd5SAriel Elior list_del(&db_entry->list_entry); 25036907cd5SAriel Elior kfree(db_entry); 25136907cd5SAriel Elior } 25236907cd5SAriel Elior } 25336907cd5SAriel Elior p_hwfn->db_recovery_info.db_recovery_counter = 0; 25436907cd5SAriel Elior } 25536907cd5SAriel Elior 25636907cd5SAriel Elior /* Print the content of the doorbell recovery mechanism */ 25736907cd5SAriel Elior void qed_db_recovery_dp(struct qed_hwfn *p_hwfn) 25836907cd5SAriel Elior { 25936907cd5SAriel Elior struct qed_db_recovery_entry *db_entry = NULL; 26036907cd5SAriel Elior 26136907cd5SAriel Elior DP_NOTICE(p_hwfn, 262d1ecf8a6SColin Ian King "Displaying doorbell recovery database. Counter was %d\n", 26336907cd5SAriel Elior p_hwfn->db_recovery_info.db_recovery_counter); 26436907cd5SAriel Elior 26536907cd5SAriel Elior /* Protect the list */ 26636907cd5SAriel Elior spin_lock_bh(&p_hwfn->db_recovery_info.lock); 26736907cd5SAriel Elior list_for_each_entry(db_entry, 26836907cd5SAriel Elior &p_hwfn->db_recovery_info.list, list_entry) { 26936907cd5SAriel Elior qed_db_recovery_dp_entry(p_hwfn, db_entry, "Printing"); 27036907cd5SAriel Elior } 27136907cd5SAriel Elior 27236907cd5SAriel Elior spin_unlock_bh(&p_hwfn->db_recovery_info.lock); 27336907cd5SAriel Elior } 27436907cd5SAriel Elior 27536907cd5SAriel Elior /* Ring the doorbell of a single doorbell recovery entry */ 27636907cd5SAriel Elior static void qed_db_recovery_ring(struct qed_hwfn *p_hwfn, 2779ac6bb14SDenis Bolotin struct qed_db_recovery_entry *db_entry) 27836907cd5SAriel Elior { 27936907cd5SAriel Elior /* Print according to width */ 28036907cd5SAriel Elior if (db_entry->db_width == DB_REC_WIDTH_32B) { 28136907cd5SAriel Elior DP_VERBOSE(p_hwfn, QED_MSG_SPQ, 2829ac6bb14SDenis Bolotin "ringing doorbell address %p data %x\n", 28336907cd5SAriel Elior db_entry->db_addr, 28436907cd5SAriel Elior *(u32 *)db_entry->db_data); 28536907cd5SAriel Elior } else { 28636907cd5SAriel Elior DP_VERBOSE(p_hwfn, QED_MSG_SPQ, 2879ac6bb14SDenis Bolotin "ringing doorbell address %p data %llx\n", 28836907cd5SAriel Elior db_entry->db_addr, 28936907cd5SAriel Elior *(u64 *)(db_entry->db_data)); 29036907cd5SAriel Elior } 29136907cd5SAriel Elior 29236907cd5SAriel Elior /* Sanity */ 29336907cd5SAriel Elior if (!qed_db_rec_sanity(p_hwfn->cdev, db_entry->db_addr, 294b61b04adSDenis Bolotin db_entry->db_width, db_entry->db_data)) 29536907cd5SAriel Elior return; 29636907cd5SAriel Elior 29736907cd5SAriel Elior /* Flush the write combined buffer. Since there are multiple doorbelling 29836907cd5SAriel Elior * entities using the same address, if we don't flush, a transaction 29936907cd5SAriel Elior * could be lost. 30036907cd5SAriel Elior */ 30136907cd5SAriel Elior wmb(); 30236907cd5SAriel Elior 30336907cd5SAriel Elior /* Ring the doorbell */ 30436907cd5SAriel Elior if (db_entry->db_width == DB_REC_WIDTH_32B) 30536907cd5SAriel Elior DIRECT_REG_WR(db_entry->db_addr, 30636907cd5SAriel Elior *(u32 *)(db_entry->db_data)); 30736907cd5SAriel Elior else 30836907cd5SAriel Elior DIRECT_REG_WR64(db_entry->db_addr, 30936907cd5SAriel Elior *(u64 *)(db_entry->db_data)); 31036907cd5SAriel Elior 31136907cd5SAriel Elior /* Flush the write combined buffer. Next doorbell may come from a 31236907cd5SAriel Elior * different entity to the same address... 31336907cd5SAriel Elior */ 31436907cd5SAriel Elior wmb(); 31536907cd5SAriel Elior } 31636907cd5SAriel Elior 31736907cd5SAriel Elior /* Traverse the doorbell recovery entry list and ring all the doorbells */ 3189ac6bb14SDenis Bolotin void qed_db_recovery_execute(struct qed_hwfn *p_hwfn) 31936907cd5SAriel Elior { 32036907cd5SAriel Elior struct qed_db_recovery_entry *db_entry = NULL; 32136907cd5SAriel Elior 3229ac6bb14SDenis Bolotin DP_NOTICE(p_hwfn, "Executing doorbell recovery. Counter was %d\n", 32336907cd5SAriel Elior p_hwfn->db_recovery_info.db_recovery_counter); 32436907cd5SAriel Elior 32536907cd5SAriel Elior /* Track amount of times recovery was executed */ 32636907cd5SAriel Elior p_hwfn->db_recovery_info.db_recovery_counter++; 32736907cd5SAriel Elior 32836907cd5SAriel Elior /* Protect the list */ 32936907cd5SAriel Elior spin_lock_bh(&p_hwfn->db_recovery_info.lock); 33036907cd5SAriel Elior list_for_each_entry(db_entry, 3319ac6bb14SDenis Bolotin &p_hwfn->db_recovery_info.list, list_entry) 3329ac6bb14SDenis Bolotin qed_db_recovery_ring(p_hwfn, db_entry); 33336907cd5SAriel Elior spin_unlock_bh(&p_hwfn->db_recovery_info.lock); 33436907cd5SAriel Elior } 33536907cd5SAriel Elior 33636907cd5SAriel Elior /******************** Doorbell Recovery end ****************/ 33736907cd5SAriel Elior 33879284adeSMichal Kalderon /********************************** NIG LLH ***********************************/ 33979284adeSMichal Kalderon 34079284adeSMichal Kalderon enum qed_llh_filter_type { 34179284adeSMichal Kalderon QED_LLH_FILTER_TYPE_MAC, 34279284adeSMichal Kalderon QED_LLH_FILTER_TYPE_PROTOCOL, 34379284adeSMichal Kalderon }; 34479284adeSMichal Kalderon 34579284adeSMichal Kalderon struct qed_llh_mac_filter { 34679284adeSMichal Kalderon u8 addr[ETH_ALEN]; 34779284adeSMichal Kalderon }; 34879284adeSMichal Kalderon 34979284adeSMichal Kalderon struct qed_llh_protocol_filter { 35079284adeSMichal Kalderon enum qed_llh_prot_filter_type_t type; 35179284adeSMichal Kalderon u16 source_port_or_eth_type; 35279284adeSMichal Kalderon u16 dest_port; 35379284adeSMichal Kalderon }; 35479284adeSMichal Kalderon 35579284adeSMichal Kalderon union qed_llh_filter { 35679284adeSMichal Kalderon struct qed_llh_mac_filter mac; 35779284adeSMichal Kalderon struct qed_llh_protocol_filter protocol; 35879284adeSMichal Kalderon }; 35979284adeSMichal Kalderon 36079284adeSMichal Kalderon struct qed_llh_filter_info { 36179284adeSMichal Kalderon bool b_enabled; 36279284adeSMichal Kalderon u32 ref_cnt; 36379284adeSMichal Kalderon enum qed_llh_filter_type type; 36479284adeSMichal Kalderon union qed_llh_filter filter; 36579284adeSMichal Kalderon }; 36679284adeSMichal Kalderon 36779284adeSMichal Kalderon struct qed_llh_info { 36879284adeSMichal Kalderon /* Number of LLH filters banks */ 36979284adeSMichal Kalderon u8 num_ppfid; 37079284adeSMichal Kalderon 37179284adeSMichal Kalderon #define MAX_NUM_PPFID 8 37279284adeSMichal Kalderon u8 ppfid_array[MAX_NUM_PPFID]; 37379284adeSMichal Kalderon 37479284adeSMichal Kalderon /* Array of filters arrays: 37579284adeSMichal Kalderon * "num_ppfid" elements of filters banks, where each is an array of 37679284adeSMichal Kalderon * "NIG_REG_LLH_FUNC_FILTER_EN_SIZE" filters. 37779284adeSMichal Kalderon */ 37879284adeSMichal Kalderon struct qed_llh_filter_info **pp_filters; 37979284adeSMichal Kalderon }; 38079284adeSMichal Kalderon 38179284adeSMichal Kalderon static void qed_llh_free(struct qed_dev *cdev) 38279284adeSMichal Kalderon { 38379284adeSMichal Kalderon struct qed_llh_info *p_llh_info = cdev->p_llh_info; 38479284adeSMichal Kalderon u32 i; 38579284adeSMichal Kalderon 38679284adeSMichal Kalderon if (p_llh_info) { 38779284adeSMichal Kalderon if (p_llh_info->pp_filters) 38879284adeSMichal Kalderon for (i = 0; i < p_llh_info->num_ppfid; i++) 38979284adeSMichal Kalderon kfree(p_llh_info->pp_filters[i]); 39079284adeSMichal Kalderon 39179284adeSMichal Kalderon kfree(p_llh_info->pp_filters); 39279284adeSMichal Kalderon } 39379284adeSMichal Kalderon 39479284adeSMichal Kalderon kfree(p_llh_info); 39579284adeSMichal Kalderon cdev->p_llh_info = NULL; 39679284adeSMichal Kalderon } 39779284adeSMichal Kalderon 39879284adeSMichal Kalderon static int qed_llh_alloc(struct qed_dev *cdev) 39979284adeSMichal Kalderon { 40079284adeSMichal Kalderon struct qed_llh_info *p_llh_info; 40179284adeSMichal Kalderon u32 size, i; 40279284adeSMichal Kalderon 40379284adeSMichal Kalderon p_llh_info = kzalloc(sizeof(*p_llh_info), GFP_KERNEL); 40479284adeSMichal Kalderon if (!p_llh_info) 40579284adeSMichal Kalderon return -ENOMEM; 40679284adeSMichal Kalderon cdev->p_llh_info = p_llh_info; 40779284adeSMichal Kalderon 40879284adeSMichal Kalderon for (i = 0; i < MAX_NUM_PPFID; i++) { 40979284adeSMichal Kalderon if (!(cdev->ppfid_bitmap & (0x1 << i))) 41079284adeSMichal Kalderon continue; 41179284adeSMichal Kalderon 41279284adeSMichal Kalderon p_llh_info->ppfid_array[p_llh_info->num_ppfid] = i; 41379284adeSMichal Kalderon DP_VERBOSE(cdev, QED_MSG_SP, "ppfid_array[%d] = %hhd\n", 41479284adeSMichal Kalderon p_llh_info->num_ppfid, i); 41579284adeSMichal Kalderon p_llh_info->num_ppfid++; 41679284adeSMichal Kalderon } 41779284adeSMichal Kalderon 41879284adeSMichal Kalderon size = p_llh_info->num_ppfid * sizeof(*p_llh_info->pp_filters); 41979284adeSMichal Kalderon p_llh_info->pp_filters = kzalloc(size, GFP_KERNEL); 42079284adeSMichal Kalderon if (!p_llh_info->pp_filters) 42179284adeSMichal Kalderon return -ENOMEM; 42279284adeSMichal Kalderon 42379284adeSMichal Kalderon size = NIG_REG_LLH_FUNC_FILTER_EN_SIZE * 42479284adeSMichal Kalderon sizeof(**p_llh_info->pp_filters); 42579284adeSMichal Kalderon for (i = 0; i < p_llh_info->num_ppfid; i++) { 42679284adeSMichal Kalderon p_llh_info->pp_filters[i] = kzalloc(size, GFP_KERNEL); 42779284adeSMichal Kalderon if (!p_llh_info->pp_filters[i]) 42879284adeSMichal Kalderon return -ENOMEM; 42979284adeSMichal Kalderon } 43079284adeSMichal Kalderon 43179284adeSMichal Kalderon return 0; 43279284adeSMichal Kalderon } 43379284adeSMichal Kalderon 43479284adeSMichal Kalderon static int qed_llh_shadow_sanity(struct qed_dev *cdev, 43579284adeSMichal Kalderon u8 ppfid, u8 filter_idx, const char *action) 43679284adeSMichal Kalderon { 43779284adeSMichal Kalderon struct qed_llh_info *p_llh_info = cdev->p_llh_info; 43879284adeSMichal Kalderon 43979284adeSMichal Kalderon if (ppfid >= p_llh_info->num_ppfid) { 44079284adeSMichal Kalderon DP_NOTICE(cdev, 44179284adeSMichal Kalderon "LLH shadow [%s]: using ppfid %d while only %d ppfids are available\n", 44279284adeSMichal Kalderon action, ppfid, p_llh_info->num_ppfid); 44379284adeSMichal Kalderon return -EINVAL; 44479284adeSMichal Kalderon } 44579284adeSMichal Kalderon 44679284adeSMichal Kalderon if (filter_idx >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) { 44779284adeSMichal Kalderon DP_NOTICE(cdev, 44879284adeSMichal Kalderon "LLH shadow [%s]: using filter_idx %d while only %d filters are available\n", 44979284adeSMichal Kalderon action, filter_idx, NIG_REG_LLH_FUNC_FILTER_EN_SIZE); 45079284adeSMichal Kalderon return -EINVAL; 45179284adeSMichal Kalderon } 45279284adeSMichal Kalderon 45379284adeSMichal Kalderon return 0; 45479284adeSMichal Kalderon } 45579284adeSMichal Kalderon 45679284adeSMichal Kalderon #define QED_LLH_INVALID_FILTER_IDX 0xff 45779284adeSMichal Kalderon 45879284adeSMichal Kalderon static int 45979284adeSMichal Kalderon qed_llh_shadow_search_filter(struct qed_dev *cdev, 46079284adeSMichal Kalderon u8 ppfid, 46179284adeSMichal Kalderon union qed_llh_filter *p_filter, u8 *p_filter_idx) 46279284adeSMichal Kalderon { 46379284adeSMichal Kalderon struct qed_llh_info *p_llh_info = cdev->p_llh_info; 46479284adeSMichal Kalderon struct qed_llh_filter_info *p_filters; 46579284adeSMichal Kalderon int rc; 46679284adeSMichal Kalderon u8 i; 46779284adeSMichal Kalderon 46879284adeSMichal Kalderon rc = qed_llh_shadow_sanity(cdev, ppfid, 0, "search"); 46979284adeSMichal Kalderon if (rc) 47079284adeSMichal Kalderon return rc; 47179284adeSMichal Kalderon 47279284adeSMichal Kalderon *p_filter_idx = QED_LLH_INVALID_FILTER_IDX; 47379284adeSMichal Kalderon 47479284adeSMichal Kalderon p_filters = p_llh_info->pp_filters[ppfid]; 47579284adeSMichal Kalderon for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 47679284adeSMichal Kalderon if (!memcmp(p_filter, &p_filters[i].filter, 47779284adeSMichal Kalderon sizeof(*p_filter))) { 47879284adeSMichal Kalderon *p_filter_idx = i; 47979284adeSMichal Kalderon break; 48079284adeSMichal Kalderon } 48179284adeSMichal Kalderon } 48279284adeSMichal Kalderon 48379284adeSMichal Kalderon return 0; 48479284adeSMichal Kalderon } 48579284adeSMichal Kalderon 48679284adeSMichal Kalderon static int 48779284adeSMichal Kalderon qed_llh_shadow_get_free_idx(struct qed_dev *cdev, u8 ppfid, u8 *p_filter_idx) 48879284adeSMichal Kalderon { 48979284adeSMichal Kalderon struct qed_llh_info *p_llh_info = cdev->p_llh_info; 49079284adeSMichal Kalderon struct qed_llh_filter_info *p_filters; 49179284adeSMichal Kalderon int rc; 49279284adeSMichal Kalderon u8 i; 49379284adeSMichal Kalderon 49479284adeSMichal Kalderon rc = qed_llh_shadow_sanity(cdev, ppfid, 0, "get_free_idx"); 49579284adeSMichal Kalderon if (rc) 49679284adeSMichal Kalderon return rc; 49779284adeSMichal Kalderon 49879284adeSMichal Kalderon *p_filter_idx = QED_LLH_INVALID_FILTER_IDX; 49979284adeSMichal Kalderon 50079284adeSMichal Kalderon p_filters = p_llh_info->pp_filters[ppfid]; 50179284adeSMichal Kalderon for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 50279284adeSMichal Kalderon if (!p_filters[i].b_enabled) { 50379284adeSMichal Kalderon *p_filter_idx = i; 50479284adeSMichal Kalderon break; 50579284adeSMichal Kalderon } 50679284adeSMichal Kalderon } 50779284adeSMichal Kalderon 50879284adeSMichal Kalderon return 0; 50979284adeSMichal Kalderon } 51079284adeSMichal Kalderon 51179284adeSMichal Kalderon static int 51279284adeSMichal Kalderon __qed_llh_shadow_add_filter(struct qed_dev *cdev, 51379284adeSMichal Kalderon u8 ppfid, 51479284adeSMichal Kalderon u8 filter_idx, 51579284adeSMichal Kalderon enum qed_llh_filter_type type, 51679284adeSMichal Kalderon union qed_llh_filter *p_filter, u32 *p_ref_cnt) 51779284adeSMichal Kalderon { 51879284adeSMichal Kalderon struct qed_llh_info *p_llh_info = cdev->p_llh_info; 51979284adeSMichal Kalderon struct qed_llh_filter_info *p_filters; 52079284adeSMichal Kalderon int rc; 52179284adeSMichal Kalderon 52279284adeSMichal Kalderon rc = qed_llh_shadow_sanity(cdev, ppfid, filter_idx, "add"); 52379284adeSMichal Kalderon if (rc) 52479284adeSMichal Kalderon return rc; 52579284adeSMichal Kalderon 52679284adeSMichal Kalderon p_filters = p_llh_info->pp_filters[ppfid]; 52779284adeSMichal Kalderon if (!p_filters[filter_idx].ref_cnt) { 52879284adeSMichal Kalderon p_filters[filter_idx].b_enabled = true; 52979284adeSMichal Kalderon p_filters[filter_idx].type = type; 53079284adeSMichal Kalderon memcpy(&p_filters[filter_idx].filter, p_filter, 53179284adeSMichal Kalderon sizeof(p_filters[filter_idx].filter)); 53279284adeSMichal Kalderon } 53379284adeSMichal Kalderon 53479284adeSMichal Kalderon *p_ref_cnt = ++p_filters[filter_idx].ref_cnt; 53579284adeSMichal Kalderon 53679284adeSMichal Kalderon return 0; 53779284adeSMichal Kalderon } 53879284adeSMichal Kalderon 53979284adeSMichal Kalderon static int 54079284adeSMichal Kalderon qed_llh_shadow_add_filter(struct qed_dev *cdev, 54179284adeSMichal Kalderon u8 ppfid, 54279284adeSMichal Kalderon enum qed_llh_filter_type type, 54379284adeSMichal Kalderon union qed_llh_filter *p_filter, 54479284adeSMichal Kalderon u8 *p_filter_idx, u32 *p_ref_cnt) 54579284adeSMichal Kalderon { 54679284adeSMichal Kalderon int rc; 54779284adeSMichal Kalderon 54879284adeSMichal Kalderon /* Check if the same filter already exist */ 54979284adeSMichal Kalderon rc = qed_llh_shadow_search_filter(cdev, ppfid, p_filter, p_filter_idx); 55079284adeSMichal Kalderon if (rc) 55179284adeSMichal Kalderon return rc; 55279284adeSMichal Kalderon 55379284adeSMichal Kalderon /* Find a new entry in case of a new filter */ 55479284adeSMichal Kalderon if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) { 55579284adeSMichal Kalderon rc = qed_llh_shadow_get_free_idx(cdev, ppfid, p_filter_idx); 55679284adeSMichal Kalderon if (rc) 55779284adeSMichal Kalderon return rc; 55879284adeSMichal Kalderon } 55979284adeSMichal Kalderon 56079284adeSMichal Kalderon /* No free entry was found */ 56179284adeSMichal Kalderon if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) { 56279284adeSMichal Kalderon DP_NOTICE(cdev, 56379284adeSMichal Kalderon "Failed to find an empty LLH filter to utilize [ppfid %d]\n", 56479284adeSMichal Kalderon ppfid); 56579284adeSMichal Kalderon return -EINVAL; 56679284adeSMichal Kalderon } 56779284adeSMichal Kalderon 56879284adeSMichal Kalderon return __qed_llh_shadow_add_filter(cdev, ppfid, *p_filter_idx, type, 56979284adeSMichal Kalderon p_filter, p_ref_cnt); 57079284adeSMichal Kalderon } 57179284adeSMichal Kalderon 57279284adeSMichal Kalderon static int 57379284adeSMichal Kalderon __qed_llh_shadow_remove_filter(struct qed_dev *cdev, 57479284adeSMichal Kalderon u8 ppfid, u8 filter_idx, u32 *p_ref_cnt) 57579284adeSMichal Kalderon { 57679284adeSMichal Kalderon struct qed_llh_info *p_llh_info = cdev->p_llh_info; 57779284adeSMichal Kalderon struct qed_llh_filter_info *p_filters; 57879284adeSMichal Kalderon int rc; 57979284adeSMichal Kalderon 58079284adeSMichal Kalderon rc = qed_llh_shadow_sanity(cdev, ppfid, filter_idx, "remove"); 58179284adeSMichal Kalderon if (rc) 58279284adeSMichal Kalderon return rc; 58379284adeSMichal Kalderon 58479284adeSMichal Kalderon p_filters = p_llh_info->pp_filters[ppfid]; 58579284adeSMichal Kalderon if (!p_filters[filter_idx].ref_cnt) { 58679284adeSMichal Kalderon DP_NOTICE(cdev, 58779284adeSMichal Kalderon "LLH shadow: trying to remove a filter with ref_cnt=0\n"); 58879284adeSMichal Kalderon return -EINVAL; 58979284adeSMichal Kalderon } 59079284adeSMichal Kalderon 59179284adeSMichal Kalderon *p_ref_cnt = --p_filters[filter_idx].ref_cnt; 59279284adeSMichal Kalderon if (!p_filters[filter_idx].ref_cnt) 59379284adeSMichal Kalderon memset(&p_filters[filter_idx], 59479284adeSMichal Kalderon 0, sizeof(p_filters[filter_idx])); 59579284adeSMichal Kalderon 59679284adeSMichal Kalderon return 0; 59779284adeSMichal Kalderon } 59879284adeSMichal Kalderon 59979284adeSMichal Kalderon static int 60079284adeSMichal Kalderon qed_llh_shadow_remove_filter(struct qed_dev *cdev, 60179284adeSMichal Kalderon u8 ppfid, 60279284adeSMichal Kalderon union qed_llh_filter *p_filter, 60379284adeSMichal Kalderon u8 *p_filter_idx, u32 *p_ref_cnt) 60479284adeSMichal Kalderon { 60579284adeSMichal Kalderon int rc; 60679284adeSMichal Kalderon 60779284adeSMichal Kalderon rc = qed_llh_shadow_search_filter(cdev, ppfid, p_filter, p_filter_idx); 60879284adeSMichal Kalderon if (rc) 60979284adeSMichal Kalderon return rc; 61079284adeSMichal Kalderon 61179284adeSMichal Kalderon /* No matching filter was found */ 61279284adeSMichal Kalderon if (*p_filter_idx == QED_LLH_INVALID_FILTER_IDX) { 61379284adeSMichal Kalderon DP_NOTICE(cdev, "Failed to find a filter in the LLH shadow\n"); 61479284adeSMichal Kalderon return -EINVAL; 61579284adeSMichal Kalderon } 61679284adeSMichal Kalderon 61779284adeSMichal Kalderon return __qed_llh_shadow_remove_filter(cdev, ppfid, *p_filter_idx, 61879284adeSMichal Kalderon p_ref_cnt); 61979284adeSMichal Kalderon } 62079284adeSMichal Kalderon 62179284adeSMichal Kalderon static int qed_llh_abs_ppfid(struct qed_dev *cdev, u8 ppfid, u8 *p_abs_ppfid) 62279284adeSMichal Kalderon { 62379284adeSMichal Kalderon struct qed_llh_info *p_llh_info = cdev->p_llh_info; 62479284adeSMichal Kalderon 62579284adeSMichal Kalderon if (ppfid >= p_llh_info->num_ppfid) { 62679284adeSMichal Kalderon DP_NOTICE(cdev, 62779284adeSMichal Kalderon "ppfid %d is not valid, available indices are 0..%hhd\n", 62879284adeSMichal Kalderon ppfid, p_llh_info->num_ppfid - 1); 629815deee0SArnd Bergmann *p_abs_ppfid = 0; 63079284adeSMichal Kalderon return -EINVAL; 63179284adeSMichal Kalderon } 63279284adeSMichal Kalderon 63379284adeSMichal Kalderon *p_abs_ppfid = p_llh_info->ppfid_array[ppfid]; 63479284adeSMichal Kalderon 63579284adeSMichal Kalderon return 0; 63679284adeSMichal Kalderon } 63779284adeSMichal Kalderon 63879284adeSMichal Kalderon static int 63979284adeSMichal Kalderon qed_llh_set_engine_affin(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 64079284adeSMichal Kalderon { 64179284adeSMichal Kalderon struct qed_dev *cdev = p_hwfn->cdev; 64279284adeSMichal Kalderon enum qed_eng eng; 64379284adeSMichal Kalderon u8 ppfid; 64479284adeSMichal Kalderon int rc; 64579284adeSMichal Kalderon 64679284adeSMichal Kalderon rc = qed_mcp_get_engine_config(p_hwfn, p_ptt); 64779284adeSMichal Kalderon if (rc != 0 && rc != -EOPNOTSUPP) { 64879284adeSMichal Kalderon DP_NOTICE(p_hwfn, 64979284adeSMichal Kalderon "Failed to get the engine affinity configuration\n"); 65079284adeSMichal Kalderon return rc; 65179284adeSMichal Kalderon } 65279284adeSMichal Kalderon 65379284adeSMichal Kalderon /* RoCE PF is bound to a single engine */ 65479284adeSMichal Kalderon if (QED_IS_ROCE_PERSONALITY(p_hwfn)) { 65579284adeSMichal Kalderon eng = cdev->fir_affin ? QED_ENG1 : QED_ENG0; 65679284adeSMichal Kalderon rc = qed_llh_set_roce_affinity(cdev, eng); 65779284adeSMichal Kalderon if (rc) { 65879284adeSMichal Kalderon DP_NOTICE(cdev, 65979284adeSMichal Kalderon "Failed to set the RoCE engine affinity\n"); 66079284adeSMichal Kalderon return rc; 66179284adeSMichal Kalderon } 66279284adeSMichal Kalderon 66379284adeSMichal Kalderon DP_VERBOSE(cdev, 66479284adeSMichal Kalderon QED_MSG_SP, 66579284adeSMichal Kalderon "LLH: Set the engine affinity of RoCE packets as %d\n", 66679284adeSMichal Kalderon eng); 66779284adeSMichal Kalderon } 66879284adeSMichal Kalderon 66979284adeSMichal Kalderon /* Storage PF is bound to a single engine while L2 PF uses both */ 67079284adeSMichal Kalderon if (QED_IS_FCOE_PERSONALITY(p_hwfn) || QED_IS_ISCSI_PERSONALITY(p_hwfn)) 67179284adeSMichal Kalderon eng = cdev->fir_affin ? QED_ENG1 : QED_ENG0; 67279284adeSMichal Kalderon else /* L2_PERSONALITY */ 67379284adeSMichal Kalderon eng = QED_BOTH_ENG; 67479284adeSMichal Kalderon 67579284adeSMichal Kalderon for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) { 67679284adeSMichal Kalderon rc = qed_llh_set_ppfid_affinity(cdev, ppfid, eng); 67779284adeSMichal Kalderon if (rc) { 67879284adeSMichal Kalderon DP_NOTICE(cdev, 67979284adeSMichal Kalderon "Failed to set the engine affinity of ppfid %d\n", 68079284adeSMichal Kalderon ppfid); 68179284adeSMichal Kalderon return rc; 68279284adeSMichal Kalderon } 68379284adeSMichal Kalderon } 68479284adeSMichal Kalderon 68579284adeSMichal Kalderon DP_VERBOSE(cdev, QED_MSG_SP, 68679284adeSMichal Kalderon "LLH: Set the engine affinity of non-RoCE packets as %d\n", 68779284adeSMichal Kalderon eng); 68879284adeSMichal Kalderon 68979284adeSMichal Kalderon return 0; 69079284adeSMichal Kalderon } 69179284adeSMichal Kalderon 69279284adeSMichal Kalderon static int qed_llh_hw_init_pf(struct qed_hwfn *p_hwfn, 69379284adeSMichal Kalderon struct qed_ptt *p_ptt) 69479284adeSMichal Kalderon { 69579284adeSMichal Kalderon struct qed_dev *cdev = p_hwfn->cdev; 69679284adeSMichal Kalderon u8 ppfid, abs_ppfid; 69779284adeSMichal Kalderon int rc; 69879284adeSMichal Kalderon 69979284adeSMichal Kalderon for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) { 70079284adeSMichal Kalderon u32 addr; 70179284adeSMichal Kalderon 70279284adeSMichal Kalderon rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid); 70379284adeSMichal Kalderon if (rc) 70479284adeSMichal Kalderon return rc; 70579284adeSMichal Kalderon 70679284adeSMichal Kalderon addr = NIG_REG_LLH_PPFID2PFID_TBL_0 + abs_ppfid * 0x4; 70779284adeSMichal Kalderon qed_wr(p_hwfn, p_ptt, addr, p_hwfn->rel_pf_id); 70879284adeSMichal Kalderon } 70979284adeSMichal Kalderon 71079284adeSMichal Kalderon if (test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits) && 71179284adeSMichal Kalderon !QED_IS_FCOE_PERSONALITY(p_hwfn)) { 71279284adeSMichal Kalderon rc = qed_llh_add_mac_filter(cdev, 0, 71379284adeSMichal Kalderon p_hwfn->hw_info.hw_mac_addr); 71479284adeSMichal Kalderon if (rc) 71579284adeSMichal Kalderon DP_NOTICE(cdev, 71679284adeSMichal Kalderon "Failed to add an LLH filter with the primary MAC\n"); 71779284adeSMichal Kalderon } 71879284adeSMichal Kalderon 71979284adeSMichal Kalderon if (QED_IS_CMT(cdev)) { 72079284adeSMichal Kalderon rc = qed_llh_set_engine_affin(p_hwfn, p_ptt); 72179284adeSMichal Kalderon if (rc) 72279284adeSMichal Kalderon return rc; 72379284adeSMichal Kalderon } 72479284adeSMichal Kalderon 72579284adeSMichal Kalderon return 0; 72679284adeSMichal Kalderon } 72779284adeSMichal Kalderon 72879284adeSMichal Kalderon u8 qed_llh_get_num_ppfid(struct qed_dev *cdev) 72979284adeSMichal Kalderon { 73079284adeSMichal Kalderon return cdev->p_llh_info->num_ppfid; 73179284adeSMichal Kalderon } 73279284adeSMichal Kalderon 73379284adeSMichal Kalderon #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_MASK 0x3 73479284adeSMichal Kalderon #define NIG_REG_PPF_TO_ENGINE_SEL_ROCE_SHIFT 0 73579284adeSMichal Kalderon #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_MASK 0x3 73679284adeSMichal Kalderon #define NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE_SHIFT 2 73779284adeSMichal Kalderon 73879284adeSMichal Kalderon int qed_llh_set_ppfid_affinity(struct qed_dev *cdev, u8 ppfid, enum qed_eng eng) 73979284adeSMichal Kalderon { 74079284adeSMichal Kalderon struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 74179284adeSMichal Kalderon struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn); 74279284adeSMichal Kalderon u32 addr, val, eng_sel; 74379284adeSMichal Kalderon u8 abs_ppfid; 74479284adeSMichal Kalderon int rc = 0; 74579284adeSMichal Kalderon 74679284adeSMichal Kalderon if (!p_ptt) 74779284adeSMichal Kalderon return -EAGAIN; 74879284adeSMichal Kalderon 74979284adeSMichal Kalderon if (!QED_IS_CMT(cdev)) 75079284adeSMichal Kalderon goto out; 75179284adeSMichal Kalderon 75279284adeSMichal Kalderon rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid); 75379284adeSMichal Kalderon if (rc) 75479284adeSMichal Kalderon goto out; 75579284adeSMichal Kalderon 75679284adeSMichal Kalderon switch (eng) { 75779284adeSMichal Kalderon case QED_ENG0: 75879284adeSMichal Kalderon eng_sel = 0; 75979284adeSMichal Kalderon break; 76079284adeSMichal Kalderon case QED_ENG1: 76179284adeSMichal Kalderon eng_sel = 1; 76279284adeSMichal Kalderon break; 76379284adeSMichal Kalderon case QED_BOTH_ENG: 76479284adeSMichal Kalderon eng_sel = 2; 76579284adeSMichal Kalderon break; 76679284adeSMichal Kalderon default: 76779284adeSMichal Kalderon DP_NOTICE(cdev, "Invalid affinity value for ppfid [%d]\n", eng); 76879284adeSMichal Kalderon rc = -EINVAL; 76979284adeSMichal Kalderon goto out; 77079284adeSMichal Kalderon } 77179284adeSMichal Kalderon 77279284adeSMichal Kalderon addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4; 77379284adeSMichal Kalderon val = qed_rd(p_hwfn, p_ptt, addr); 77479284adeSMichal Kalderon SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_NON_ROCE, eng_sel); 77579284adeSMichal Kalderon qed_wr(p_hwfn, p_ptt, addr, val); 77679284adeSMichal Kalderon 77779284adeSMichal Kalderon /* The iWARP affinity is set as the affinity of ppfid 0 */ 77879284adeSMichal Kalderon if (!ppfid && QED_IS_IWARP_PERSONALITY(p_hwfn)) 77979284adeSMichal Kalderon cdev->iwarp_affin = (eng == QED_ENG1) ? 1 : 0; 78079284adeSMichal Kalderon out: 78179284adeSMichal Kalderon qed_ptt_release(p_hwfn, p_ptt); 78279284adeSMichal Kalderon 78379284adeSMichal Kalderon return rc; 78479284adeSMichal Kalderon } 78579284adeSMichal Kalderon 78679284adeSMichal Kalderon int qed_llh_set_roce_affinity(struct qed_dev *cdev, enum qed_eng eng) 78779284adeSMichal Kalderon { 78879284adeSMichal Kalderon struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 78979284adeSMichal Kalderon struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn); 79079284adeSMichal Kalderon u32 addr, val, eng_sel; 79179284adeSMichal Kalderon u8 ppfid, abs_ppfid; 79279284adeSMichal Kalderon int rc = 0; 79379284adeSMichal Kalderon 79479284adeSMichal Kalderon if (!p_ptt) 79579284adeSMichal Kalderon return -EAGAIN; 79679284adeSMichal Kalderon 79779284adeSMichal Kalderon if (!QED_IS_CMT(cdev)) 79879284adeSMichal Kalderon goto out; 79979284adeSMichal Kalderon 80079284adeSMichal Kalderon switch (eng) { 80179284adeSMichal Kalderon case QED_ENG0: 80279284adeSMichal Kalderon eng_sel = 0; 80379284adeSMichal Kalderon break; 80479284adeSMichal Kalderon case QED_ENG1: 80579284adeSMichal Kalderon eng_sel = 1; 80679284adeSMichal Kalderon break; 80779284adeSMichal Kalderon case QED_BOTH_ENG: 80879284adeSMichal Kalderon eng_sel = 2; 80979284adeSMichal Kalderon qed_wr(p_hwfn, p_ptt, NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL, 81079284adeSMichal Kalderon 0xf); /* QP bit 15 */ 81179284adeSMichal Kalderon break; 81279284adeSMichal Kalderon default: 81379284adeSMichal Kalderon DP_NOTICE(cdev, "Invalid affinity value for RoCE [%d]\n", eng); 81479284adeSMichal Kalderon rc = -EINVAL; 81579284adeSMichal Kalderon goto out; 81679284adeSMichal Kalderon } 81779284adeSMichal Kalderon 81879284adeSMichal Kalderon for (ppfid = 0; ppfid < cdev->p_llh_info->num_ppfid; ppfid++) { 81979284adeSMichal Kalderon rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid); 82079284adeSMichal Kalderon if (rc) 82179284adeSMichal Kalderon goto out; 82279284adeSMichal Kalderon 82379284adeSMichal Kalderon addr = NIG_REG_PPF_TO_ENGINE_SEL + abs_ppfid * 0x4; 82479284adeSMichal Kalderon val = qed_rd(p_hwfn, p_ptt, addr); 82579284adeSMichal Kalderon SET_FIELD(val, NIG_REG_PPF_TO_ENGINE_SEL_ROCE, eng_sel); 82679284adeSMichal Kalderon qed_wr(p_hwfn, p_ptt, addr, val); 82779284adeSMichal Kalderon } 82879284adeSMichal Kalderon out: 82979284adeSMichal Kalderon qed_ptt_release(p_hwfn, p_ptt); 83079284adeSMichal Kalderon 83179284adeSMichal Kalderon return rc; 83279284adeSMichal Kalderon } 83379284adeSMichal Kalderon 83479284adeSMichal Kalderon struct qed_llh_filter_details { 83579284adeSMichal Kalderon u64 value; 83679284adeSMichal Kalderon u32 mode; 83779284adeSMichal Kalderon u32 protocol_type; 83879284adeSMichal Kalderon u32 hdr_sel; 83979284adeSMichal Kalderon u32 enable; 84079284adeSMichal Kalderon }; 84179284adeSMichal Kalderon 84279284adeSMichal Kalderon static int 84379284adeSMichal Kalderon qed_llh_access_filter(struct qed_hwfn *p_hwfn, 84479284adeSMichal Kalderon struct qed_ptt *p_ptt, 84579284adeSMichal Kalderon u8 abs_ppfid, 84679284adeSMichal Kalderon u8 filter_idx, 84779284adeSMichal Kalderon struct qed_llh_filter_details *p_details) 84879284adeSMichal Kalderon { 84979284adeSMichal Kalderon struct qed_dmae_params params = {0}; 85079284adeSMichal Kalderon u32 addr; 85179284adeSMichal Kalderon u8 pfid; 85279284adeSMichal Kalderon int rc; 85379284adeSMichal Kalderon 85479284adeSMichal Kalderon /* The NIG/LLH registers that are accessed in this function have only 16 85579284adeSMichal Kalderon * rows which are exposed to a PF. I.e. only the 16 filters of its 85679284adeSMichal Kalderon * default ppfid. Accessing filters of other ppfids requires pretending 85779284adeSMichal Kalderon * to another PFs. 85879284adeSMichal Kalderon * The calculation of PPFID->PFID in AH is based on the relative index 85979284adeSMichal Kalderon * of a PF on its port. 86079284adeSMichal Kalderon * For BB the pfid is actually the abs_ppfid. 86179284adeSMichal Kalderon */ 86279284adeSMichal Kalderon if (QED_IS_BB(p_hwfn->cdev)) 86379284adeSMichal Kalderon pfid = abs_ppfid; 86479284adeSMichal Kalderon else 86579284adeSMichal Kalderon pfid = abs_ppfid * p_hwfn->cdev->num_ports_in_engine + 86679284adeSMichal Kalderon MFW_PORT(p_hwfn); 86779284adeSMichal Kalderon 86879284adeSMichal Kalderon /* Filter enable - should be done first when removing a filter */ 86979284adeSMichal Kalderon if (!p_details->enable) { 87079284adeSMichal Kalderon qed_fid_pretend(p_hwfn, p_ptt, 87179284adeSMichal Kalderon pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT); 87279284adeSMichal Kalderon 87379284adeSMichal Kalderon addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4; 87479284adeSMichal Kalderon qed_wr(p_hwfn, p_ptt, addr, p_details->enable); 87579284adeSMichal Kalderon 87679284adeSMichal Kalderon qed_fid_pretend(p_hwfn, p_ptt, 87779284adeSMichal Kalderon p_hwfn->rel_pf_id << 87879284adeSMichal Kalderon PXP_PRETEND_CONCRETE_FID_PFID_SHIFT); 87979284adeSMichal Kalderon } 88079284adeSMichal Kalderon 88179284adeSMichal Kalderon /* Filter value */ 88279284adeSMichal Kalderon addr = NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * filter_idx * 0x4; 88379284adeSMichal Kalderon 884804c5702SMichal Kalderon SET_FIELD(params.flags, QED_DMAE_PARAMS_DST_PF_VALID, 0x1); 88579284adeSMichal Kalderon params.dst_pfid = pfid; 88679284adeSMichal Kalderon rc = qed_dmae_host2grc(p_hwfn, 88779284adeSMichal Kalderon p_ptt, 88879284adeSMichal Kalderon (u64)(uintptr_t)&p_details->value, 88979284adeSMichal Kalderon addr, 2 /* size_in_dwords */, 89079284adeSMichal Kalderon ¶ms); 89179284adeSMichal Kalderon if (rc) 89279284adeSMichal Kalderon return rc; 89379284adeSMichal Kalderon 89479284adeSMichal Kalderon qed_fid_pretend(p_hwfn, p_ptt, 89579284adeSMichal Kalderon pfid << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT); 89679284adeSMichal Kalderon 89779284adeSMichal Kalderon /* Filter mode */ 89879284adeSMichal Kalderon addr = NIG_REG_LLH_FUNC_FILTER_MODE + filter_idx * 0x4; 89979284adeSMichal Kalderon qed_wr(p_hwfn, p_ptt, addr, p_details->mode); 90079284adeSMichal Kalderon 90179284adeSMichal Kalderon /* Filter protocol type */ 90279284adeSMichal Kalderon addr = NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + filter_idx * 0x4; 90379284adeSMichal Kalderon qed_wr(p_hwfn, p_ptt, addr, p_details->protocol_type); 90479284adeSMichal Kalderon 90579284adeSMichal Kalderon /* Filter header select */ 90679284adeSMichal Kalderon addr = NIG_REG_LLH_FUNC_FILTER_HDR_SEL + filter_idx * 0x4; 90779284adeSMichal Kalderon qed_wr(p_hwfn, p_ptt, addr, p_details->hdr_sel); 90879284adeSMichal Kalderon 90979284adeSMichal Kalderon /* Filter enable - should be done last when adding a filter */ 91079284adeSMichal Kalderon if (p_details->enable) { 91179284adeSMichal Kalderon addr = NIG_REG_LLH_FUNC_FILTER_EN + filter_idx * 0x4; 91279284adeSMichal Kalderon qed_wr(p_hwfn, p_ptt, addr, p_details->enable); 91379284adeSMichal Kalderon } 91479284adeSMichal Kalderon 91579284adeSMichal Kalderon qed_fid_pretend(p_hwfn, p_ptt, 91679284adeSMichal Kalderon p_hwfn->rel_pf_id << 91779284adeSMichal Kalderon PXP_PRETEND_CONCRETE_FID_PFID_SHIFT); 91879284adeSMichal Kalderon 91979284adeSMichal Kalderon return 0; 92079284adeSMichal Kalderon } 92179284adeSMichal Kalderon 92279284adeSMichal Kalderon static int 92379284adeSMichal Kalderon qed_llh_add_filter(struct qed_hwfn *p_hwfn, 92479284adeSMichal Kalderon struct qed_ptt *p_ptt, 92579284adeSMichal Kalderon u8 abs_ppfid, 92679284adeSMichal Kalderon u8 filter_idx, u8 filter_prot_type, u32 high, u32 low) 92779284adeSMichal Kalderon { 92879284adeSMichal Kalderon struct qed_llh_filter_details filter_details; 92979284adeSMichal Kalderon 93079284adeSMichal Kalderon filter_details.enable = 1; 93179284adeSMichal Kalderon filter_details.value = ((u64)high << 32) | low; 93279284adeSMichal Kalderon filter_details.hdr_sel = 0; 93379284adeSMichal Kalderon filter_details.protocol_type = filter_prot_type; 93479284adeSMichal Kalderon /* Mode: 0: MAC-address classification 1: protocol classification */ 93579284adeSMichal Kalderon filter_details.mode = filter_prot_type ? 1 : 0; 93679284adeSMichal Kalderon 93779284adeSMichal Kalderon return qed_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx, 93879284adeSMichal Kalderon &filter_details); 93979284adeSMichal Kalderon } 94079284adeSMichal Kalderon 94179284adeSMichal Kalderon static int 94279284adeSMichal Kalderon qed_llh_remove_filter(struct qed_hwfn *p_hwfn, 94379284adeSMichal Kalderon struct qed_ptt *p_ptt, u8 abs_ppfid, u8 filter_idx) 94479284adeSMichal Kalderon { 94579284adeSMichal Kalderon struct qed_llh_filter_details filter_details = {0}; 94679284adeSMichal Kalderon 94779284adeSMichal Kalderon return qed_llh_access_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx, 94879284adeSMichal Kalderon &filter_details); 94979284adeSMichal Kalderon } 95079284adeSMichal Kalderon 95179284adeSMichal Kalderon int qed_llh_add_mac_filter(struct qed_dev *cdev, 95279284adeSMichal Kalderon u8 ppfid, u8 mac_addr[ETH_ALEN]) 95379284adeSMichal Kalderon { 95479284adeSMichal Kalderon struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 95579284adeSMichal Kalderon struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn); 95679284adeSMichal Kalderon union qed_llh_filter filter = {}; 95710f468eaSAlexander Lobakin u8 filter_idx, abs_ppfid = 0; 95879284adeSMichal Kalderon u32 high, low, ref_cnt; 95979284adeSMichal Kalderon int rc = 0; 96079284adeSMichal Kalderon 96179284adeSMichal Kalderon if (!p_ptt) 96279284adeSMichal Kalderon return -EAGAIN; 96379284adeSMichal Kalderon 96479284adeSMichal Kalderon if (!test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits)) 96579284adeSMichal Kalderon goto out; 96679284adeSMichal Kalderon 96779284adeSMichal Kalderon memcpy(filter.mac.addr, mac_addr, ETH_ALEN); 96879284adeSMichal Kalderon rc = qed_llh_shadow_add_filter(cdev, ppfid, 96979284adeSMichal Kalderon QED_LLH_FILTER_TYPE_MAC, 97079284adeSMichal Kalderon &filter, &filter_idx, &ref_cnt); 97179284adeSMichal Kalderon if (rc) 97279284adeSMichal Kalderon goto err; 97379284adeSMichal Kalderon 97479284adeSMichal Kalderon /* Configure the LLH only in case of a new the filter */ 97579284adeSMichal Kalderon if (ref_cnt == 1) { 97679284adeSMichal Kalderon rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid); 97779284adeSMichal Kalderon if (rc) 97879284adeSMichal Kalderon goto err; 97979284adeSMichal Kalderon 98079284adeSMichal Kalderon high = mac_addr[1] | (mac_addr[0] << 8); 98179284adeSMichal Kalderon low = mac_addr[5] | (mac_addr[4] << 8) | (mac_addr[3] << 16) | 98279284adeSMichal Kalderon (mac_addr[2] << 24); 98379284adeSMichal Kalderon rc = qed_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, filter_idx, 98479284adeSMichal Kalderon 0, high, low); 98579284adeSMichal Kalderon if (rc) 98679284adeSMichal Kalderon goto err; 98779284adeSMichal Kalderon } 98879284adeSMichal Kalderon 98979284adeSMichal Kalderon DP_VERBOSE(cdev, 99079284adeSMichal Kalderon QED_MSG_SP, 99179284adeSMichal Kalderon "LLH: Added MAC filter [%pM] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n", 99279284adeSMichal Kalderon mac_addr, ppfid, abs_ppfid, filter_idx, ref_cnt); 99379284adeSMichal Kalderon 99479284adeSMichal Kalderon goto out; 99579284adeSMichal Kalderon 99679284adeSMichal Kalderon err: DP_NOTICE(cdev, 99779284adeSMichal Kalderon "LLH: Failed to add MAC filter [%pM] to ppfid %hhd\n", 99879284adeSMichal Kalderon mac_addr, ppfid); 99979284adeSMichal Kalderon out: 100079284adeSMichal Kalderon qed_ptt_release(p_hwfn, p_ptt); 100179284adeSMichal Kalderon 100279284adeSMichal Kalderon return rc; 100379284adeSMichal Kalderon } 100479284adeSMichal Kalderon 100579284adeSMichal Kalderon static int 100679284adeSMichal Kalderon qed_llh_protocol_filter_stringify(struct qed_dev *cdev, 100779284adeSMichal Kalderon enum qed_llh_prot_filter_type_t type, 100879284adeSMichal Kalderon u16 source_port_or_eth_type, 100979284adeSMichal Kalderon u16 dest_port, u8 *str, size_t str_len) 101079284adeSMichal Kalderon { 101179284adeSMichal Kalderon switch (type) { 101279284adeSMichal Kalderon case QED_LLH_FILTER_ETHERTYPE: 101379284adeSMichal Kalderon snprintf(str, str_len, "Ethertype 0x%04x", 101479284adeSMichal Kalderon source_port_or_eth_type); 101579284adeSMichal Kalderon break; 101679284adeSMichal Kalderon case QED_LLH_FILTER_TCP_SRC_PORT: 101779284adeSMichal Kalderon snprintf(str, str_len, "TCP src port 0x%04x", 101879284adeSMichal Kalderon source_port_or_eth_type); 101979284adeSMichal Kalderon break; 102079284adeSMichal Kalderon case QED_LLH_FILTER_UDP_SRC_PORT: 102179284adeSMichal Kalderon snprintf(str, str_len, "UDP src port 0x%04x", 102279284adeSMichal Kalderon source_port_or_eth_type); 102379284adeSMichal Kalderon break; 102479284adeSMichal Kalderon case QED_LLH_FILTER_TCP_DEST_PORT: 102579284adeSMichal Kalderon snprintf(str, str_len, "TCP dst port 0x%04x", dest_port); 102679284adeSMichal Kalderon break; 102779284adeSMichal Kalderon case QED_LLH_FILTER_UDP_DEST_PORT: 102879284adeSMichal Kalderon snprintf(str, str_len, "UDP dst port 0x%04x", dest_port); 102979284adeSMichal Kalderon break; 103079284adeSMichal Kalderon case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 103179284adeSMichal Kalderon snprintf(str, str_len, "TCP src/dst ports 0x%04x/0x%04x", 103279284adeSMichal Kalderon source_port_or_eth_type, dest_port); 103379284adeSMichal Kalderon break; 103479284adeSMichal Kalderon case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 103579284adeSMichal Kalderon snprintf(str, str_len, "UDP src/dst ports 0x%04x/0x%04x", 103679284adeSMichal Kalderon source_port_or_eth_type, dest_port); 103779284adeSMichal Kalderon break; 103879284adeSMichal Kalderon default: 103979284adeSMichal Kalderon DP_NOTICE(cdev, 104079284adeSMichal Kalderon "Non valid LLH protocol filter type %d\n", type); 104179284adeSMichal Kalderon return -EINVAL; 104279284adeSMichal Kalderon } 104379284adeSMichal Kalderon 104479284adeSMichal Kalderon return 0; 104579284adeSMichal Kalderon } 104679284adeSMichal Kalderon 104779284adeSMichal Kalderon static int 104879284adeSMichal Kalderon qed_llh_protocol_filter_to_hilo(struct qed_dev *cdev, 104979284adeSMichal Kalderon enum qed_llh_prot_filter_type_t type, 105079284adeSMichal Kalderon u16 source_port_or_eth_type, 105179284adeSMichal Kalderon u16 dest_port, u32 *p_high, u32 *p_low) 105279284adeSMichal Kalderon { 105379284adeSMichal Kalderon *p_high = 0; 105479284adeSMichal Kalderon *p_low = 0; 105579284adeSMichal Kalderon 105679284adeSMichal Kalderon switch (type) { 105779284adeSMichal Kalderon case QED_LLH_FILTER_ETHERTYPE: 105879284adeSMichal Kalderon *p_high = source_port_or_eth_type; 105979284adeSMichal Kalderon break; 106079284adeSMichal Kalderon case QED_LLH_FILTER_TCP_SRC_PORT: 106179284adeSMichal Kalderon case QED_LLH_FILTER_UDP_SRC_PORT: 106279284adeSMichal Kalderon *p_low = source_port_or_eth_type << 16; 106379284adeSMichal Kalderon break; 106479284adeSMichal Kalderon case QED_LLH_FILTER_TCP_DEST_PORT: 106579284adeSMichal Kalderon case QED_LLH_FILTER_UDP_DEST_PORT: 106679284adeSMichal Kalderon *p_low = dest_port; 106779284adeSMichal Kalderon break; 106879284adeSMichal Kalderon case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 106979284adeSMichal Kalderon case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 107079284adeSMichal Kalderon *p_low = (source_port_or_eth_type << 16) | dest_port; 107179284adeSMichal Kalderon break; 107279284adeSMichal Kalderon default: 107379284adeSMichal Kalderon DP_NOTICE(cdev, 107479284adeSMichal Kalderon "Non valid LLH protocol filter type %d\n", type); 107579284adeSMichal Kalderon return -EINVAL; 107679284adeSMichal Kalderon } 107779284adeSMichal Kalderon 107879284adeSMichal Kalderon return 0; 107979284adeSMichal Kalderon } 108079284adeSMichal Kalderon 108179284adeSMichal Kalderon int 108279284adeSMichal Kalderon qed_llh_add_protocol_filter(struct qed_dev *cdev, 108379284adeSMichal Kalderon u8 ppfid, 108479284adeSMichal Kalderon enum qed_llh_prot_filter_type_t type, 108579284adeSMichal Kalderon u16 source_port_or_eth_type, u16 dest_port) 108679284adeSMichal Kalderon { 108779284adeSMichal Kalderon struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 108879284adeSMichal Kalderon struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn); 108979284adeSMichal Kalderon u8 filter_idx, abs_ppfid, str[32], type_bitmap; 109079284adeSMichal Kalderon union qed_llh_filter filter = {}; 109179284adeSMichal Kalderon u32 high, low, ref_cnt; 109279284adeSMichal Kalderon int rc = 0; 109379284adeSMichal Kalderon 109479284adeSMichal Kalderon if (!p_ptt) 109579284adeSMichal Kalderon return -EAGAIN; 109679284adeSMichal Kalderon 109779284adeSMichal Kalderon if (!test_bit(QED_MF_LLH_PROTO_CLSS, &cdev->mf_bits)) 109879284adeSMichal Kalderon goto out; 109979284adeSMichal Kalderon 110079284adeSMichal Kalderon rc = qed_llh_protocol_filter_stringify(cdev, type, 110179284adeSMichal Kalderon source_port_or_eth_type, 110279284adeSMichal Kalderon dest_port, str, sizeof(str)); 110379284adeSMichal Kalderon if (rc) 110479284adeSMichal Kalderon goto err; 110579284adeSMichal Kalderon 110679284adeSMichal Kalderon filter.protocol.type = type; 110779284adeSMichal Kalderon filter.protocol.source_port_or_eth_type = source_port_or_eth_type; 110879284adeSMichal Kalderon filter.protocol.dest_port = dest_port; 110979284adeSMichal Kalderon rc = qed_llh_shadow_add_filter(cdev, 111079284adeSMichal Kalderon ppfid, 111179284adeSMichal Kalderon QED_LLH_FILTER_TYPE_PROTOCOL, 111279284adeSMichal Kalderon &filter, &filter_idx, &ref_cnt); 111379284adeSMichal Kalderon if (rc) 111479284adeSMichal Kalderon goto err; 111579284adeSMichal Kalderon 111679284adeSMichal Kalderon rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid); 111779284adeSMichal Kalderon if (rc) 111879284adeSMichal Kalderon goto err; 111979284adeSMichal Kalderon 11208e2ea3eaSMichal Kalderon /* Configure the LLH only in case of a new the filter */ 11218e2ea3eaSMichal Kalderon if (ref_cnt == 1) { 112279284adeSMichal Kalderon rc = qed_llh_protocol_filter_to_hilo(cdev, type, 112379284adeSMichal Kalderon source_port_or_eth_type, 112479284adeSMichal Kalderon dest_port, &high, &low); 112579284adeSMichal Kalderon if (rc) 112679284adeSMichal Kalderon goto err; 112779284adeSMichal Kalderon 112879284adeSMichal Kalderon type_bitmap = 0x1 << type; 112979284adeSMichal Kalderon rc = qed_llh_add_filter(p_hwfn, p_ptt, abs_ppfid, 113079284adeSMichal Kalderon filter_idx, type_bitmap, high, low); 113179284adeSMichal Kalderon if (rc) 113279284adeSMichal Kalderon goto err; 113379284adeSMichal Kalderon } 113479284adeSMichal Kalderon 113579284adeSMichal Kalderon DP_VERBOSE(cdev, 113679284adeSMichal Kalderon QED_MSG_SP, 113779284adeSMichal Kalderon "LLH: Added protocol filter [%s] to ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n", 113879284adeSMichal Kalderon str, ppfid, abs_ppfid, filter_idx, ref_cnt); 113979284adeSMichal Kalderon 114079284adeSMichal Kalderon goto out; 114179284adeSMichal Kalderon 114279284adeSMichal Kalderon err: DP_NOTICE(p_hwfn, 114379284adeSMichal Kalderon "LLH: Failed to add protocol filter [%s] to ppfid %hhd\n", 114479284adeSMichal Kalderon str, ppfid); 114579284adeSMichal Kalderon out: 114679284adeSMichal Kalderon qed_ptt_release(p_hwfn, p_ptt); 114779284adeSMichal Kalderon 114879284adeSMichal Kalderon return rc; 114979284adeSMichal Kalderon } 115079284adeSMichal Kalderon 115179284adeSMichal Kalderon void qed_llh_remove_mac_filter(struct qed_dev *cdev, 115279284adeSMichal Kalderon u8 ppfid, u8 mac_addr[ETH_ALEN]) 115379284adeSMichal Kalderon { 115479284adeSMichal Kalderon struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 115579284adeSMichal Kalderon struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn); 115679284adeSMichal Kalderon union qed_llh_filter filter = {}; 115779284adeSMichal Kalderon u8 filter_idx, abs_ppfid; 115879284adeSMichal Kalderon int rc = 0; 115979284adeSMichal Kalderon u32 ref_cnt; 116079284adeSMichal Kalderon 116179284adeSMichal Kalderon if (!p_ptt) 116279284adeSMichal Kalderon return; 116379284adeSMichal Kalderon 116479284adeSMichal Kalderon if (!test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits)) 116579284adeSMichal Kalderon goto out; 116679284adeSMichal Kalderon 116779284adeSMichal Kalderon ether_addr_copy(filter.mac.addr, mac_addr); 116879284adeSMichal Kalderon rc = qed_llh_shadow_remove_filter(cdev, ppfid, &filter, &filter_idx, 116979284adeSMichal Kalderon &ref_cnt); 117079284adeSMichal Kalderon if (rc) 117179284adeSMichal Kalderon goto err; 117279284adeSMichal Kalderon 117379284adeSMichal Kalderon rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid); 117479284adeSMichal Kalderon if (rc) 117579284adeSMichal Kalderon goto err; 117679284adeSMichal Kalderon 11778e2ea3eaSMichal Kalderon /* Remove from the LLH in case the filter is not in use */ 11788e2ea3eaSMichal Kalderon if (!ref_cnt) { 117979284adeSMichal Kalderon rc = qed_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid, 118079284adeSMichal Kalderon filter_idx); 118179284adeSMichal Kalderon if (rc) 118279284adeSMichal Kalderon goto err; 118379284adeSMichal Kalderon } 118479284adeSMichal Kalderon 118579284adeSMichal Kalderon DP_VERBOSE(cdev, 118679284adeSMichal Kalderon QED_MSG_SP, 118779284adeSMichal Kalderon "LLH: Removed MAC filter [%pM] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n", 118879284adeSMichal Kalderon mac_addr, ppfid, abs_ppfid, filter_idx, ref_cnt); 118979284adeSMichal Kalderon 119079284adeSMichal Kalderon goto out; 119179284adeSMichal Kalderon 119279284adeSMichal Kalderon err: DP_NOTICE(cdev, 119379284adeSMichal Kalderon "LLH: Failed to remove MAC filter [%pM] from ppfid %hhd\n", 119479284adeSMichal Kalderon mac_addr, ppfid); 119579284adeSMichal Kalderon out: 119679284adeSMichal Kalderon qed_ptt_release(p_hwfn, p_ptt); 119779284adeSMichal Kalderon } 119879284adeSMichal Kalderon 119979284adeSMichal Kalderon void qed_llh_remove_protocol_filter(struct qed_dev *cdev, 120079284adeSMichal Kalderon u8 ppfid, 120179284adeSMichal Kalderon enum qed_llh_prot_filter_type_t type, 120279284adeSMichal Kalderon u16 source_port_or_eth_type, u16 dest_port) 120379284adeSMichal Kalderon { 120479284adeSMichal Kalderon struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 120579284adeSMichal Kalderon struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn); 120679284adeSMichal Kalderon u8 filter_idx, abs_ppfid, str[32]; 120779284adeSMichal Kalderon union qed_llh_filter filter = {}; 120879284adeSMichal Kalderon int rc = 0; 120979284adeSMichal Kalderon u32 ref_cnt; 121079284adeSMichal Kalderon 121179284adeSMichal Kalderon if (!p_ptt) 121279284adeSMichal Kalderon return; 121379284adeSMichal Kalderon 121479284adeSMichal Kalderon if (!test_bit(QED_MF_LLH_PROTO_CLSS, &cdev->mf_bits)) 121579284adeSMichal Kalderon goto out; 121679284adeSMichal Kalderon 121779284adeSMichal Kalderon rc = qed_llh_protocol_filter_stringify(cdev, type, 121879284adeSMichal Kalderon source_port_or_eth_type, 121979284adeSMichal Kalderon dest_port, str, sizeof(str)); 122079284adeSMichal Kalderon if (rc) 122179284adeSMichal Kalderon goto err; 122279284adeSMichal Kalderon 122379284adeSMichal Kalderon filter.protocol.type = type; 122479284adeSMichal Kalderon filter.protocol.source_port_or_eth_type = source_port_or_eth_type; 122579284adeSMichal Kalderon filter.protocol.dest_port = dest_port; 122679284adeSMichal Kalderon rc = qed_llh_shadow_remove_filter(cdev, ppfid, &filter, &filter_idx, 122779284adeSMichal Kalderon &ref_cnt); 122879284adeSMichal Kalderon if (rc) 122979284adeSMichal Kalderon goto err; 123079284adeSMichal Kalderon 123179284adeSMichal Kalderon rc = qed_llh_abs_ppfid(cdev, ppfid, &abs_ppfid); 123279284adeSMichal Kalderon if (rc) 123379284adeSMichal Kalderon goto err; 123479284adeSMichal Kalderon 12358e2ea3eaSMichal Kalderon /* Remove from the LLH in case the filter is not in use */ 12368e2ea3eaSMichal Kalderon if (!ref_cnt) { 123779284adeSMichal Kalderon rc = qed_llh_remove_filter(p_hwfn, p_ptt, abs_ppfid, 123879284adeSMichal Kalderon filter_idx); 123979284adeSMichal Kalderon if (rc) 124079284adeSMichal Kalderon goto err; 124179284adeSMichal Kalderon } 124279284adeSMichal Kalderon 124379284adeSMichal Kalderon DP_VERBOSE(cdev, 124479284adeSMichal Kalderon QED_MSG_SP, 124579284adeSMichal Kalderon "LLH: Removed protocol filter [%s] from ppfid %hhd [abs %hhd] at idx %hhd [ref_cnt %d]\n", 124679284adeSMichal Kalderon str, ppfid, abs_ppfid, filter_idx, ref_cnt); 124779284adeSMichal Kalderon 124879284adeSMichal Kalderon goto out; 124979284adeSMichal Kalderon 125079284adeSMichal Kalderon err: DP_NOTICE(cdev, 125179284adeSMichal Kalderon "LLH: Failed to remove protocol filter [%s] from ppfid %hhd\n", 125279284adeSMichal Kalderon str, ppfid); 125379284adeSMichal Kalderon out: 125479284adeSMichal Kalderon qed_ptt_release(p_hwfn, p_ptt); 125579284adeSMichal Kalderon } 125679284adeSMichal Kalderon 125779284adeSMichal Kalderon /******************************* NIG LLH - End ********************************/ 125879284adeSMichal Kalderon 125951ff1725SRam Amrani #define QED_MIN_DPIS (4) 126051ff1725SRam Amrani #define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS) 126151ff1725SRam Amrani 126215582962SRahul Verma static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, 126315582962SRahul Verma struct qed_ptt *p_ptt, enum BAR_ID bar_id) 1264c2035eeaSRam Amrani { 1265c2035eeaSRam Amrani u32 bar_reg = (bar_id == BAR_ID_0 ? 1266c2035eeaSRam Amrani PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE); 12671408cc1fSYuval Mintz u32 val; 1268c2035eeaSRam Amrani 12691408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 12701a850bfcSMintz, Yuval return qed_vf_hw_bar_size(p_hwfn, bar_id); 12711408cc1fSYuval Mintz 127215582962SRahul Verma val = qed_rd(p_hwfn, p_ptt, bar_reg); 1273c2035eeaSRam Amrani if (val) 1274c2035eeaSRam Amrani return 1 << (val + 15); 1275c2035eeaSRam Amrani 1276c2035eeaSRam Amrani /* Old MFW initialized above registered only conditionally */ 1277c2035eeaSRam Amrani if (p_hwfn->cdev->num_hwfns > 1) { 1278c2035eeaSRam Amrani DP_INFO(p_hwfn, 1279c2035eeaSRam Amrani "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n"); 1280c2035eeaSRam Amrani return BAR_ID_0 ? 256 * 1024 : 512 * 1024; 1281c2035eeaSRam Amrani } else { 1282c2035eeaSRam Amrani DP_INFO(p_hwfn, 1283c2035eeaSRam Amrani "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n"); 1284c2035eeaSRam Amrani return 512 * 1024; 1285c2035eeaSRam Amrani } 1286c2035eeaSRam Amrani } 1287c2035eeaSRam Amrani 12881a635e48SYuval Mintz void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level) 1289fe56b9e6SYuval Mintz { 1290fe56b9e6SYuval Mintz u32 i; 1291fe56b9e6SYuval Mintz 1292fe56b9e6SYuval Mintz cdev->dp_level = dp_level; 1293fe56b9e6SYuval Mintz cdev->dp_module = dp_module; 1294fe56b9e6SYuval Mintz for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 1295fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1296fe56b9e6SYuval Mintz 1297fe56b9e6SYuval Mintz p_hwfn->dp_level = dp_level; 1298fe56b9e6SYuval Mintz p_hwfn->dp_module = dp_module; 1299fe56b9e6SYuval Mintz } 1300fe56b9e6SYuval Mintz } 1301fe56b9e6SYuval Mintz 1302fe56b9e6SYuval Mintz void qed_init_struct(struct qed_dev *cdev) 1303fe56b9e6SYuval Mintz { 1304fe56b9e6SYuval Mintz u8 i; 1305fe56b9e6SYuval Mintz 1306fe56b9e6SYuval Mintz for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 1307fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1308fe56b9e6SYuval Mintz 1309fe56b9e6SYuval Mintz p_hwfn->cdev = cdev; 1310fe56b9e6SYuval Mintz p_hwfn->my_id = i; 1311fe56b9e6SYuval Mintz p_hwfn->b_active = false; 1312fe56b9e6SYuval Mintz 1313fe56b9e6SYuval Mintz mutex_init(&p_hwfn->dmae_info.mutex); 1314fe56b9e6SYuval Mintz } 1315fe56b9e6SYuval Mintz 1316fe56b9e6SYuval Mintz /* hwfn 0 is always active */ 1317fe56b9e6SYuval Mintz cdev->hwfns[0].b_active = true; 1318fe56b9e6SYuval Mintz 1319fe56b9e6SYuval Mintz /* set the default cache alignment to 128 */ 1320fe56b9e6SYuval Mintz cdev->cache_shift = 7; 1321fe56b9e6SYuval Mintz } 1322fe56b9e6SYuval Mintz 1323fe56b9e6SYuval Mintz static void qed_qm_info_free(struct qed_hwfn *p_hwfn) 1324fe56b9e6SYuval Mintz { 1325fe56b9e6SYuval Mintz struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1326fe56b9e6SYuval Mintz 1327fe56b9e6SYuval Mintz kfree(qm_info->qm_pq_params); 1328fe56b9e6SYuval Mintz qm_info->qm_pq_params = NULL; 1329fe56b9e6SYuval Mintz kfree(qm_info->qm_vport_params); 1330fe56b9e6SYuval Mintz qm_info->qm_vport_params = NULL; 1331fe56b9e6SYuval Mintz kfree(qm_info->qm_port_params); 1332fe56b9e6SYuval Mintz qm_info->qm_port_params = NULL; 1333bcd197c8SManish Chopra kfree(qm_info->wfq_data); 1334bcd197c8SManish Chopra qm_info->wfq_data = NULL; 1335fe56b9e6SYuval Mintz } 1336fe56b9e6SYuval Mintz 1337a3f72307SDenis Bolotin static void qed_dbg_user_data_free(struct qed_hwfn *p_hwfn) 1338a3f72307SDenis Bolotin { 1339a3f72307SDenis Bolotin kfree(p_hwfn->dbg_user_info); 1340a3f72307SDenis Bolotin p_hwfn->dbg_user_info = NULL; 1341a3f72307SDenis Bolotin } 1342a3f72307SDenis Bolotin 1343fe56b9e6SYuval Mintz void qed_resc_free(struct qed_dev *cdev) 1344fe56b9e6SYuval Mintz { 134531333c1aSAlexander Lobakin struct qed_rdma_info *rdma_info; 134631333c1aSAlexander Lobakin struct qed_hwfn *p_hwfn; 1347fe56b9e6SYuval Mintz int i; 1348fe56b9e6SYuval Mintz 13490db711bbSMintz, Yuval if (IS_VF(cdev)) { 13500db711bbSMintz, Yuval for_each_hwfn(cdev, i) 13510db711bbSMintz, Yuval qed_l2_free(&cdev->hwfns[i]); 13521408cc1fSYuval Mintz return; 13530db711bbSMintz, Yuval } 13541408cc1fSYuval Mintz 1355fe56b9e6SYuval Mintz kfree(cdev->fw_data); 1356fe56b9e6SYuval Mintz cdev->fw_data = NULL; 1357fe56b9e6SYuval Mintz 1358fe56b9e6SYuval Mintz kfree(cdev->reset_stats); 13593587cb87STomer Tayar cdev->reset_stats = NULL; 1360fe56b9e6SYuval Mintz 136179284adeSMichal Kalderon qed_llh_free(cdev); 136279284adeSMichal Kalderon 1363fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 136431333c1aSAlexander Lobakin p_hwfn = cdev->hwfns + i; 136531333c1aSAlexander Lobakin rdma_info = p_hwfn->p_rdma_info; 1366fe56b9e6SYuval Mintz 1367fe56b9e6SYuval Mintz qed_cxt_mngr_free(p_hwfn); 1368fe56b9e6SYuval Mintz qed_qm_info_free(p_hwfn); 1369fe56b9e6SYuval Mintz qed_spq_free(p_hwfn); 13703587cb87STomer Tayar qed_eq_free(p_hwfn); 13713587cb87STomer Tayar qed_consq_free(p_hwfn); 1372fe56b9e6SYuval Mintz qed_int_free(p_hwfn); 13730a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 13743587cb87STomer Tayar qed_ll2_free(p_hwfn); 13750a7fb11cSYuval Mintz #endif 13761e128c81SArun Easi if (p_hwfn->hw_info.personality == QED_PCI_FCOE) 13773587cb87STomer Tayar qed_fcoe_free(p_hwfn); 13781e128c81SArun Easi 13791d6cff4fSYuval Mintz if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 13803587cb87STomer Tayar qed_iscsi_free(p_hwfn); 13813587cb87STomer Tayar qed_ooo_free(p_hwfn); 13821d6cff4fSYuval Mintz } 1383291d57f6SMichal Kalderon 138431333c1aSAlexander Lobakin if (QED_IS_RDMA_PERSONALITY(p_hwfn) && rdma_info) { 138531333c1aSAlexander Lobakin qed_spq_unregister_async_cb(p_hwfn, rdma_info->proto); 1386291d57f6SMichal Kalderon qed_rdma_info_free(p_hwfn); 138731333c1aSAlexander Lobakin } 1388291d57f6SMichal Kalderon 138932a47e72SYuval Mintz qed_iov_free(p_hwfn); 13900db711bbSMintz, Yuval qed_l2_free(p_hwfn); 1391fe56b9e6SYuval Mintz qed_dmae_info_free(p_hwfn); 1392270837b3Ssudarsana.kalluru@cavium.com qed_dcbx_info_free(p_hwfn); 1393a3f72307SDenis Bolotin qed_dbg_user_data_free(p_hwfn); 139430d5f858SMichal Kalderon qed_fw_overlay_mem_free(p_hwfn, p_hwfn->fw_overlay_mem); 139536907cd5SAriel Elior 139636907cd5SAriel Elior /* Destroy doorbell recovery mechanism */ 139736907cd5SAriel Elior qed_db_recovery_teardown(p_hwfn); 1398fe56b9e6SYuval Mintz } 1399fe56b9e6SYuval Mintz } 1400fe56b9e6SYuval Mintz 1401b5a9ee7cSAriel Elior /******************** QM initialization *******************/ 1402b5a9ee7cSAriel Elior #define ACTIVE_TCS_BMAP 0x9f 1403b5a9ee7cSAriel Elior #define ACTIVE_TCS_BMAP_4PORT_K2 0xf 1404b5a9ee7cSAriel Elior 1405b5a9ee7cSAriel Elior /* determines the physical queue flags for a given PF. */ 1406b5a9ee7cSAriel Elior static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn) 1407fe56b9e6SYuval Mintz { 1408b5a9ee7cSAriel Elior u32 flags; 1409fe56b9e6SYuval Mintz 1410b5a9ee7cSAriel Elior /* common flags */ 1411b5a9ee7cSAriel Elior flags = PQ_FLAGS_LB; 1412fe56b9e6SYuval Mintz 1413b5a9ee7cSAriel Elior /* feature flags */ 1414b5a9ee7cSAriel Elior if (IS_QED_SRIOV(p_hwfn->cdev)) 1415b5a9ee7cSAriel Elior flags |= PQ_FLAGS_VFS; 1416fe56b9e6SYuval Mintz 1417b5a9ee7cSAriel Elior /* protocol flags */ 1418b5a9ee7cSAriel Elior switch (p_hwfn->hw_info.personality) { 1419b5a9ee7cSAriel Elior case QED_PCI_ETH: 1420b5a9ee7cSAriel Elior flags |= PQ_FLAGS_MCOS; 1421b5a9ee7cSAriel Elior break; 1422b5a9ee7cSAriel Elior case QED_PCI_FCOE: 1423b5a9ee7cSAriel Elior flags |= PQ_FLAGS_OFLD; 1424b5a9ee7cSAriel Elior break; 1425b5a9ee7cSAriel Elior case QED_PCI_ISCSI: 1426b5a9ee7cSAriel Elior flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD; 1427b5a9ee7cSAriel Elior break; 1428b5a9ee7cSAriel Elior case QED_PCI_ETH_ROCE: 1429b5a9ee7cSAriel Elior flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT; 143061be82b0SDenis Bolotin if (IS_QED_MULTI_TC_ROCE(p_hwfn)) 143161be82b0SDenis Bolotin flags |= PQ_FLAGS_MTC; 1432b5a9ee7cSAriel Elior break; 143393c45984SKalderon, Michal case QED_PCI_ETH_IWARP: 143493c45984SKalderon, Michal flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO | 143593c45984SKalderon, Michal PQ_FLAGS_OFLD; 143693c45984SKalderon, Michal break; 1437b5a9ee7cSAriel Elior default: 1438fe56b9e6SYuval Mintz DP_ERR(p_hwfn, 1439b5a9ee7cSAriel Elior "unknown personality %d\n", p_hwfn->hw_info.personality); 1440b5a9ee7cSAriel Elior return 0; 1441fe56b9e6SYuval Mintz } 1442fe56b9e6SYuval Mintz 1443b5a9ee7cSAriel Elior return flags; 1444b5a9ee7cSAriel Elior } 1445b5a9ee7cSAriel Elior 1446b5a9ee7cSAriel Elior /* Getters for resource amounts necessary for qm initialization */ 1447bf774d14SYueHaibing static u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn) 1448b5a9ee7cSAriel Elior { 1449b5a9ee7cSAriel Elior return p_hwfn->hw_info.num_hw_tc; 1450b5a9ee7cSAriel Elior } 1451b5a9ee7cSAriel Elior 1452bf774d14SYueHaibing static u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn) 1453b5a9ee7cSAriel Elior { 1454b5a9ee7cSAriel Elior return IS_QED_SRIOV(p_hwfn->cdev) ? 1455b5a9ee7cSAriel Elior p_hwfn->cdev->p_iov_info->total_vfs : 0; 1456b5a9ee7cSAriel Elior } 1457b5a9ee7cSAriel Elior 145861be82b0SDenis Bolotin static u8 qed_init_qm_get_num_mtc_tcs(struct qed_hwfn *p_hwfn) 145961be82b0SDenis Bolotin { 146061be82b0SDenis Bolotin u32 pq_flags = qed_get_pq_flags(p_hwfn); 146161be82b0SDenis Bolotin 146261be82b0SDenis Bolotin if (!(PQ_FLAGS_MTC & pq_flags)) 146361be82b0SDenis Bolotin return 1; 146461be82b0SDenis Bolotin 146561be82b0SDenis Bolotin return qed_init_qm_get_num_tcs(p_hwfn); 146661be82b0SDenis Bolotin } 146761be82b0SDenis Bolotin 1468b5a9ee7cSAriel Elior #define NUM_DEFAULT_RLS 1 1469b5a9ee7cSAriel Elior 1470bf774d14SYueHaibing static u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn) 1471b5a9ee7cSAriel Elior { 1472b5a9ee7cSAriel Elior u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn); 1473b5a9ee7cSAriel Elior 1474b5a9ee7cSAriel Elior /* num RLs can't exceed resource amount of rls or vports */ 1475b5a9ee7cSAriel Elior num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL), 1476b5a9ee7cSAriel Elior RESC_NUM(p_hwfn, QED_VPORT)); 1477b5a9ee7cSAriel Elior 1478b5a9ee7cSAriel Elior /* Make sure after we reserve there's something left */ 1479b5a9ee7cSAriel Elior if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) 1480b5a9ee7cSAriel Elior return 0; 1481b5a9ee7cSAriel Elior 1482b5a9ee7cSAriel Elior /* subtract rls necessary for VFs and one default one for the PF */ 1483b5a9ee7cSAriel Elior num_pf_rls -= num_vfs + NUM_DEFAULT_RLS; 1484b5a9ee7cSAriel Elior 1485b5a9ee7cSAriel Elior return num_pf_rls; 1486b5a9ee7cSAriel Elior } 1487b5a9ee7cSAriel Elior 1488bf774d14SYueHaibing static u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn) 1489b5a9ee7cSAriel Elior { 1490b5a9ee7cSAriel Elior u32 pq_flags = qed_get_pq_flags(p_hwfn); 1491b5a9ee7cSAriel Elior 1492b5a9ee7cSAriel Elior /* all pqs share the same vport, except for vfs and pf_rl pqs */ 1493b5a9ee7cSAriel Elior return (!!(PQ_FLAGS_RLS & pq_flags)) * 1494b5a9ee7cSAriel Elior qed_init_qm_get_num_pf_rls(p_hwfn) + 1495b5a9ee7cSAriel Elior (!!(PQ_FLAGS_VFS & pq_flags)) * 1496b5a9ee7cSAriel Elior qed_init_qm_get_num_vfs(p_hwfn) + 1; 1497b5a9ee7cSAriel Elior } 1498b5a9ee7cSAriel Elior 1499b5a9ee7cSAriel Elior /* calc amount of PQs according to the requested flags */ 1500bf774d14SYueHaibing static u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn) 1501b5a9ee7cSAriel Elior { 1502b5a9ee7cSAriel Elior u32 pq_flags = qed_get_pq_flags(p_hwfn); 1503b5a9ee7cSAriel Elior 1504b5a9ee7cSAriel Elior return (!!(PQ_FLAGS_RLS & pq_flags)) * 1505b5a9ee7cSAriel Elior qed_init_qm_get_num_pf_rls(p_hwfn) + 1506b5a9ee7cSAriel Elior (!!(PQ_FLAGS_MCOS & pq_flags)) * 1507b5a9ee7cSAriel Elior qed_init_qm_get_num_tcs(p_hwfn) + 1508b5a9ee7cSAriel Elior (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) + 150961be82b0SDenis Bolotin (!!(PQ_FLAGS_ACK & pq_flags)) + 151061be82b0SDenis Bolotin (!!(PQ_FLAGS_OFLD & pq_flags)) * 151161be82b0SDenis Bolotin qed_init_qm_get_num_mtc_tcs(p_hwfn) + 151261be82b0SDenis Bolotin (!!(PQ_FLAGS_LLT & pq_flags)) * 151361be82b0SDenis Bolotin qed_init_qm_get_num_mtc_tcs(p_hwfn) + 1514b5a9ee7cSAriel Elior (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn); 1515b5a9ee7cSAriel Elior } 1516b5a9ee7cSAriel Elior 1517b5a9ee7cSAriel Elior /* initialize the top level QM params */ 1518b5a9ee7cSAriel Elior static void qed_init_qm_params(struct qed_hwfn *p_hwfn) 1519b5a9ee7cSAriel Elior { 1520b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1521b5a9ee7cSAriel Elior bool four_port; 1522b5a9ee7cSAriel Elior 1523b5a9ee7cSAriel Elior /* pq and vport bases for this PF */ 1524b5a9ee7cSAriel Elior qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ); 1525b5a9ee7cSAriel Elior qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT); 1526b5a9ee7cSAriel Elior 1527b5a9ee7cSAriel Elior /* rate limiting and weighted fair queueing are always enabled */ 1528c7281d59SGustavo A. R. Silva qm_info->vport_rl_en = true; 1529c7281d59SGustavo A. R. Silva qm_info->vport_wfq_en = true; 1530b5a9ee7cSAriel Elior 1531b5a9ee7cSAriel Elior /* TC config is different for AH 4 port */ 153278cea9ffSTomer Tayar four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2; 1533b5a9ee7cSAriel Elior 1534b5a9ee7cSAriel Elior /* in AH 4 port we have fewer TCs per port */ 1535b5a9ee7cSAriel Elior qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 : 1536b5a9ee7cSAriel Elior NUM_OF_PHYS_TCS; 1537b5a9ee7cSAriel Elior 1538b5a9ee7cSAriel Elior /* unless MFW indicated otherwise, ooo_tc == 3 for 1539b5a9ee7cSAriel Elior * AH 4-port and 4 otherwise. 1540fe56b9e6SYuval Mintz */ 1541b5a9ee7cSAriel Elior if (!qm_info->ooo_tc) 1542b5a9ee7cSAriel Elior qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC : 1543b5a9ee7cSAriel Elior DCBX_TCP_OOO_TC; 1544dbb799c3SYuval Mintz } 1545dbb799c3SYuval Mintz 1546b5a9ee7cSAriel Elior /* initialize qm vport params */ 1547b5a9ee7cSAriel Elior static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn) 1548b5a9ee7cSAriel Elior { 1549b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1550b5a9ee7cSAriel Elior u8 i; 1551fe56b9e6SYuval Mintz 1552b5a9ee7cSAriel Elior /* all vports participate in weighted fair queueing */ 1553b5a9ee7cSAriel Elior for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++) 155492fae6fbSMichal Kalderon qm_info->qm_vport_params[i].wfq = 1; 1555fe56b9e6SYuval Mintz } 1556fe56b9e6SYuval Mintz 1557b5a9ee7cSAriel Elior /* initialize qm port params */ 1558b5a9ee7cSAriel Elior static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn) 1559b5a9ee7cSAriel Elior { 1560fe56b9e6SYuval Mintz /* Initialize qm port parameters */ 156178cea9ffSTomer Tayar u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine; 15621392d19fSMichal Kalderon struct qed_dev *cdev = p_hwfn->cdev; 1563b5a9ee7cSAriel Elior 1564b5a9ee7cSAriel Elior /* indicate how ooo and high pri traffic is dealt with */ 1565b5a9ee7cSAriel Elior active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ? 1566b5a9ee7cSAriel Elior ACTIVE_TCS_BMAP_4PORT_K2 : 1567b5a9ee7cSAriel Elior ACTIVE_TCS_BMAP; 1568b5a9ee7cSAriel Elior 1569fe56b9e6SYuval Mintz for (i = 0; i < num_ports; i++) { 1570b5a9ee7cSAriel Elior struct init_qm_port_params *p_qm_port = 1571b5a9ee7cSAriel Elior &p_hwfn->qm_info.qm_port_params[i]; 15721392d19fSMichal Kalderon u16 pbf_max_cmd_lines; 1573b5a9ee7cSAriel Elior 1574fe56b9e6SYuval Mintz p_qm_port->active = 1; 1575b5a9ee7cSAriel Elior p_qm_port->active_phys_tcs = active_phys_tcs; 15761392d19fSMichal Kalderon pbf_max_cmd_lines = (u16)NUM_OF_PBF_CMD_LINES(cdev); 15771392d19fSMichal Kalderon p_qm_port->num_pbf_cmd_lines = pbf_max_cmd_lines / num_ports; 15781392d19fSMichal Kalderon p_qm_port->num_btb_blocks = NUM_OF_BTB_BLOCKS(cdev) / num_ports; 1579fe56b9e6SYuval Mintz } 1580b5a9ee7cSAriel Elior } 1581fe56b9e6SYuval Mintz 1582b5a9ee7cSAriel Elior /* Reset the params which must be reset for qm init. QM init may be called as 1583b5a9ee7cSAriel Elior * a result of flows other than driver load (e.g. dcbx renegotiation). Other 1584b5a9ee7cSAriel Elior * params may be affected by the init but would simply recalculate to the same 1585b5a9ee7cSAriel Elior * values. The allocations made for QM init, ports, vports, pqs and vfqs are not 1586b5a9ee7cSAriel Elior * affected as these amounts stay the same. 1587b5a9ee7cSAriel Elior */ 1588b5a9ee7cSAriel Elior static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn) 1589b5a9ee7cSAriel Elior { 1590b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1591fe56b9e6SYuval Mintz 1592b5a9ee7cSAriel Elior qm_info->num_pqs = 0; 1593b5a9ee7cSAriel Elior qm_info->num_vports = 0; 1594b5a9ee7cSAriel Elior qm_info->num_pf_rls = 0; 1595b5a9ee7cSAriel Elior qm_info->num_vf_pqs = 0; 1596b5a9ee7cSAriel Elior qm_info->first_vf_pq = 0; 1597b5a9ee7cSAriel Elior qm_info->first_mcos_pq = 0; 1598b5a9ee7cSAriel Elior qm_info->first_rl_pq = 0; 1599b5a9ee7cSAriel Elior } 1600fe56b9e6SYuval Mintz 1601b5a9ee7cSAriel Elior static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn) 1602b5a9ee7cSAriel Elior { 1603b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1604b5a9ee7cSAriel Elior 1605b5a9ee7cSAriel Elior qm_info->num_vports++; 1606b5a9ee7cSAriel Elior 1607b5a9ee7cSAriel Elior if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn)) 1608b5a9ee7cSAriel Elior DP_ERR(p_hwfn, 1609b5a9ee7cSAriel Elior "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n", 1610b5a9ee7cSAriel Elior qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn)); 1611b5a9ee7cSAriel Elior } 1612b5a9ee7cSAriel Elior 1613b5a9ee7cSAriel Elior /* initialize a single pq and manage qm_info resources accounting. 1614b5a9ee7cSAriel Elior * The pq_init_flags param determines whether the PQ is rate limited 1615b5a9ee7cSAriel Elior * (for VF or PF) and whether a new vport is allocated to the pq or not 1616b5a9ee7cSAriel Elior * (i.e. vport will be shared). 1617b5a9ee7cSAriel Elior */ 1618b5a9ee7cSAriel Elior 1619b5a9ee7cSAriel Elior /* flags for pq init */ 1620b5a9ee7cSAriel Elior #define PQ_INIT_SHARE_VPORT (1 << 0) 1621b5a9ee7cSAriel Elior #define PQ_INIT_PF_RL (1 << 1) 1622b5a9ee7cSAriel Elior #define PQ_INIT_VF_RL (1 << 2) 1623b5a9ee7cSAriel Elior 1624b5a9ee7cSAriel Elior /* defines for pq init */ 1625b5a9ee7cSAriel Elior #define PQ_INIT_DEFAULT_WRR_GROUP 1 1626b5a9ee7cSAriel Elior #define PQ_INIT_DEFAULT_TC 0 1627c4259ddaSDenis Bolotin 1628c4259ddaSDenis Bolotin void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc) 1629c4259ddaSDenis Bolotin { 1630c4259ddaSDenis Bolotin p_info->offload_tc = tc; 1631c4259ddaSDenis Bolotin p_info->offload_tc_set = true; 1632c4259ddaSDenis Bolotin } 1633c4259ddaSDenis Bolotin 1634c4259ddaSDenis Bolotin static bool qed_is_offload_tc_set(struct qed_hwfn *p_hwfn) 1635c4259ddaSDenis Bolotin { 1636c4259ddaSDenis Bolotin return p_hwfn->hw_info.offload_tc_set; 1637c4259ddaSDenis Bolotin } 1638c4259ddaSDenis Bolotin 1639c4259ddaSDenis Bolotin static u32 qed_get_offload_tc(struct qed_hwfn *p_hwfn) 1640c4259ddaSDenis Bolotin { 1641c4259ddaSDenis Bolotin if (qed_is_offload_tc_set(p_hwfn)) 1642c4259ddaSDenis Bolotin return p_hwfn->hw_info.offload_tc; 1643c4259ddaSDenis Bolotin 1644c4259ddaSDenis Bolotin return PQ_INIT_DEFAULT_TC; 1645c4259ddaSDenis Bolotin } 1646b5a9ee7cSAriel Elior 1647b5a9ee7cSAriel Elior static void qed_init_qm_pq(struct qed_hwfn *p_hwfn, 1648b5a9ee7cSAriel Elior struct qed_qm_info *qm_info, 1649b5a9ee7cSAriel Elior u8 tc, u32 pq_init_flags) 1650b5a9ee7cSAriel Elior { 1651b5a9ee7cSAriel Elior u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn); 1652b5a9ee7cSAriel Elior 1653b5a9ee7cSAriel Elior if (pq_idx > max_pq) 1654b5a9ee7cSAriel Elior DP_ERR(p_hwfn, 1655b5a9ee7cSAriel Elior "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq); 1656b5a9ee7cSAriel Elior 1657b5a9ee7cSAriel Elior /* init pq params */ 165850bc60cbSMichal Kalderon qm_info->qm_pq_params[pq_idx].port_id = p_hwfn->port_id; 1659b5a9ee7cSAriel Elior qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport + 1660b5a9ee7cSAriel Elior qm_info->num_vports; 1661b5a9ee7cSAriel Elior qm_info->qm_pq_params[pq_idx].tc_id = tc; 1662b5a9ee7cSAriel Elior qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP; 1663b5a9ee7cSAriel Elior qm_info->qm_pq_params[pq_idx].rl_valid = 1664b5a9ee7cSAriel Elior (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL); 1665b5a9ee7cSAriel Elior 1666b5a9ee7cSAriel Elior /* qm params accounting */ 1667b5a9ee7cSAriel Elior qm_info->num_pqs++; 1668b5a9ee7cSAriel Elior if (!(pq_init_flags & PQ_INIT_SHARE_VPORT)) 1669b5a9ee7cSAriel Elior qm_info->num_vports++; 1670b5a9ee7cSAriel Elior 1671b5a9ee7cSAriel Elior if (pq_init_flags & PQ_INIT_PF_RL) 1672b5a9ee7cSAriel Elior qm_info->num_pf_rls++; 1673b5a9ee7cSAriel Elior 1674b5a9ee7cSAriel Elior if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn)) 1675b5a9ee7cSAriel Elior DP_ERR(p_hwfn, 1676b5a9ee7cSAriel Elior "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n", 1677b5a9ee7cSAriel Elior qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn)); 1678b5a9ee7cSAriel Elior 1679b5a9ee7cSAriel Elior if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn)) 1680b5a9ee7cSAriel Elior DP_ERR(p_hwfn, 1681b5a9ee7cSAriel Elior "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n", 1682b5a9ee7cSAriel Elior qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn)); 1683b5a9ee7cSAriel Elior } 1684b5a9ee7cSAriel Elior 1685b5a9ee7cSAriel Elior /* get pq index according to PQ_FLAGS */ 1686b5a9ee7cSAriel Elior static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn, 1687ffb057f9SManish Chopra unsigned long pq_flags) 1688b5a9ee7cSAriel Elior { 1689b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1690b5a9ee7cSAriel Elior 1691b5a9ee7cSAriel Elior /* Can't have multiple flags set here */ 1692ffb057f9SManish Chopra if (bitmap_weight(&pq_flags, 1693276d43f0SDenis Bolotin sizeof(pq_flags) * BITS_PER_BYTE) > 1) { 1694ffb057f9SManish Chopra DP_ERR(p_hwfn, "requested multiple pq flags 0x%lx\n", pq_flags); 1695b5a9ee7cSAriel Elior goto err; 1696276d43f0SDenis Bolotin } 1697b5a9ee7cSAriel Elior 1698eb62cca9SDenis Bolotin if (!(qed_get_pq_flags(p_hwfn) & pq_flags)) { 1699ffb057f9SManish Chopra DP_ERR(p_hwfn, "pq flag 0x%lx is not set\n", pq_flags); 1700eb62cca9SDenis Bolotin goto err; 1701eb62cca9SDenis Bolotin } 1702eb62cca9SDenis Bolotin 1703b5a9ee7cSAriel Elior switch (pq_flags) { 1704b5a9ee7cSAriel Elior case PQ_FLAGS_RLS: 1705b5a9ee7cSAriel Elior return &qm_info->first_rl_pq; 1706b5a9ee7cSAriel Elior case PQ_FLAGS_MCOS: 1707b5a9ee7cSAriel Elior return &qm_info->first_mcos_pq; 1708b5a9ee7cSAriel Elior case PQ_FLAGS_LB: 1709b5a9ee7cSAriel Elior return &qm_info->pure_lb_pq; 1710b5a9ee7cSAriel Elior case PQ_FLAGS_OOO: 1711b5a9ee7cSAriel Elior return &qm_info->ooo_pq; 1712b5a9ee7cSAriel Elior case PQ_FLAGS_ACK: 1713b5a9ee7cSAriel Elior return &qm_info->pure_ack_pq; 1714b5a9ee7cSAriel Elior case PQ_FLAGS_OFLD: 171561be82b0SDenis Bolotin return &qm_info->first_ofld_pq; 1716b5a9ee7cSAriel Elior case PQ_FLAGS_LLT: 171761be82b0SDenis Bolotin return &qm_info->first_llt_pq; 1718b5a9ee7cSAriel Elior case PQ_FLAGS_VFS: 1719b5a9ee7cSAriel Elior return &qm_info->first_vf_pq; 1720b5a9ee7cSAriel Elior default: 1721b5a9ee7cSAriel Elior goto err; 1722b5a9ee7cSAriel Elior } 1723b5a9ee7cSAriel Elior 1724b5a9ee7cSAriel Elior err: 1725eb62cca9SDenis Bolotin return &qm_info->start_pq; 1726b5a9ee7cSAriel Elior } 1727b5a9ee7cSAriel Elior 1728b5a9ee7cSAriel Elior /* save pq index in qm info */ 1729b5a9ee7cSAriel Elior static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn, 1730b5a9ee7cSAriel Elior u32 pq_flags, u16 pq_val) 1731b5a9ee7cSAriel Elior { 1732b5a9ee7cSAriel Elior u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags); 1733b5a9ee7cSAriel Elior 1734b5a9ee7cSAriel Elior *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val; 1735b5a9ee7cSAriel Elior } 1736b5a9ee7cSAriel Elior 1737b5a9ee7cSAriel Elior /* get tx pq index, with the PQ TX base already set (ready for context init) */ 1738b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags) 1739b5a9ee7cSAriel Elior { 1740b5a9ee7cSAriel Elior u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags); 1741b5a9ee7cSAriel Elior 1742b5a9ee7cSAriel Elior return *base_pq_idx + CM_TX_PQ_BASE; 1743b5a9ee7cSAriel Elior } 1744b5a9ee7cSAriel Elior 1745b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc) 1746b5a9ee7cSAriel Elior { 1747b5a9ee7cSAriel Elior u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn); 1748b5a9ee7cSAriel Elior 1749eb62cca9SDenis Bolotin if (max_tc == 0) { 1750eb62cca9SDenis Bolotin DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n", 1751eb62cca9SDenis Bolotin PQ_FLAGS_MCOS); 1752eb62cca9SDenis Bolotin return p_hwfn->qm_info.start_pq; 1753eb62cca9SDenis Bolotin } 1754eb62cca9SDenis Bolotin 1755b5a9ee7cSAriel Elior if (tc > max_tc) 1756b5a9ee7cSAriel Elior DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc); 1757b5a9ee7cSAriel Elior 1758eb62cca9SDenis Bolotin return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + (tc % max_tc); 1759b5a9ee7cSAriel Elior } 1760b5a9ee7cSAriel Elior 1761b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf) 1762b5a9ee7cSAriel Elior { 1763b5a9ee7cSAriel Elior u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn); 1764b5a9ee7cSAriel Elior 1765eb62cca9SDenis Bolotin if (max_vf == 0) { 1766eb62cca9SDenis Bolotin DP_ERR(p_hwfn, "pq with flag 0x%lx do not exist\n", 1767eb62cca9SDenis Bolotin PQ_FLAGS_VFS); 1768eb62cca9SDenis Bolotin return p_hwfn->qm_info.start_pq; 1769eb62cca9SDenis Bolotin } 1770eb62cca9SDenis Bolotin 1771b5a9ee7cSAriel Elior if (vf > max_vf) 1772b5a9ee7cSAriel Elior DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf); 1773b5a9ee7cSAriel Elior 1774eb62cca9SDenis Bolotin return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + (vf % max_vf); 1775b5a9ee7cSAriel Elior } 1776b5a9ee7cSAriel Elior 177761be82b0SDenis Bolotin u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc) 177861be82b0SDenis Bolotin { 177961be82b0SDenis Bolotin u16 first_ofld_pq, pq_offset; 178061be82b0SDenis Bolotin 178161be82b0SDenis Bolotin first_ofld_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_OFLD); 178261be82b0SDenis Bolotin pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ? 178361be82b0SDenis Bolotin tc : PQ_INIT_DEFAULT_TC; 178461be82b0SDenis Bolotin 178561be82b0SDenis Bolotin return first_ofld_pq + pq_offset; 178661be82b0SDenis Bolotin } 178761be82b0SDenis Bolotin 178861be82b0SDenis Bolotin u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc) 178961be82b0SDenis Bolotin { 179061be82b0SDenis Bolotin u16 first_llt_pq, pq_offset; 179161be82b0SDenis Bolotin 179261be82b0SDenis Bolotin first_llt_pq = qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LLT); 179361be82b0SDenis Bolotin pq_offset = (tc < qed_init_qm_get_num_mtc_tcs(p_hwfn)) ? 179461be82b0SDenis Bolotin tc : PQ_INIT_DEFAULT_TC; 179561be82b0SDenis Bolotin 179661be82b0SDenis Bolotin return first_llt_pq + pq_offset; 179761be82b0SDenis Bolotin } 179861be82b0SDenis Bolotin 1799b5a9ee7cSAriel Elior /* Functions for creating specific types of pqs */ 1800b5a9ee7cSAriel Elior static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn) 1801b5a9ee7cSAriel Elior { 1802b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1803b5a9ee7cSAriel Elior 1804b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB)) 1805b5a9ee7cSAriel Elior return; 1806b5a9ee7cSAriel Elior 1807b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs); 1808b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT); 1809b5a9ee7cSAriel Elior } 1810b5a9ee7cSAriel Elior 1811b5a9ee7cSAriel Elior static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn) 1812b5a9ee7cSAriel Elior { 1813b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1814b5a9ee7cSAriel Elior 1815b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO)) 1816b5a9ee7cSAriel Elior return; 1817b5a9ee7cSAriel Elior 1818b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs); 1819b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT); 1820b5a9ee7cSAriel Elior } 1821b5a9ee7cSAriel Elior 1822b5a9ee7cSAriel Elior static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn) 1823b5a9ee7cSAriel Elior { 1824b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1825b5a9ee7cSAriel Elior 1826b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK)) 1827b5a9ee7cSAriel Elior return; 1828b5a9ee7cSAriel Elior 1829b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs); 1830c4259ddaSDenis Bolotin qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn), 1831c4259ddaSDenis Bolotin PQ_INIT_SHARE_VPORT); 1832b5a9ee7cSAriel Elior } 1833b5a9ee7cSAriel Elior 183461be82b0SDenis Bolotin static void qed_init_qm_mtc_pqs(struct qed_hwfn *p_hwfn) 183561be82b0SDenis Bolotin { 183661be82b0SDenis Bolotin u8 num_tcs = qed_init_qm_get_num_mtc_tcs(p_hwfn); 183761be82b0SDenis Bolotin struct qed_qm_info *qm_info = &p_hwfn->qm_info; 183861be82b0SDenis Bolotin u8 tc; 183961be82b0SDenis Bolotin 184061be82b0SDenis Bolotin /* override pq's TC if offload TC is set */ 184161be82b0SDenis Bolotin for (tc = 0; tc < num_tcs; tc++) 184261be82b0SDenis Bolotin qed_init_qm_pq(p_hwfn, qm_info, 184361be82b0SDenis Bolotin qed_is_offload_tc_set(p_hwfn) ? 184461be82b0SDenis Bolotin p_hwfn->hw_info.offload_tc : tc, 184561be82b0SDenis Bolotin PQ_INIT_SHARE_VPORT); 184661be82b0SDenis Bolotin } 184761be82b0SDenis Bolotin 1848b5a9ee7cSAriel Elior static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn) 1849b5a9ee7cSAriel Elior { 1850b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1851b5a9ee7cSAriel Elior 1852b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD)) 1853b5a9ee7cSAriel Elior return; 1854b5a9ee7cSAriel Elior 1855b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs); 185661be82b0SDenis Bolotin qed_init_qm_mtc_pqs(p_hwfn); 1857b5a9ee7cSAriel Elior } 1858b5a9ee7cSAriel Elior 1859b5a9ee7cSAriel Elior static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn) 1860b5a9ee7cSAriel Elior { 1861b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1862b5a9ee7cSAriel Elior 1863b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT)) 1864b5a9ee7cSAriel Elior return; 1865b5a9ee7cSAriel Elior 1866b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs); 186761be82b0SDenis Bolotin qed_init_qm_mtc_pqs(p_hwfn); 1868b5a9ee7cSAriel Elior } 1869b5a9ee7cSAriel Elior 1870b5a9ee7cSAriel Elior static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn) 1871b5a9ee7cSAriel Elior { 1872b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1873b5a9ee7cSAriel Elior u8 tc_idx; 1874b5a9ee7cSAriel Elior 1875b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS)) 1876b5a9ee7cSAriel Elior return; 1877b5a9ee7cSAriel Elior 1878b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs); 1879b5a9ee7cSAriel Elior for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++) 1880b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT); 1881b5a9ee7cSAriel Elior } 1882b5a9ee7cSAriel Elior 1883b5a9ee7cSAriel Elior static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn) 1884b5a9ee7cSAriel Elior { 1885b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1886b5a9ee7cSAriel Elior u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn); 1887b5a9ee7cSAriel Elior 1888b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS)) 1889b5a9ee7cSAriel Elior return; 1890b5a9ee7cSAriel Elior 1891b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs); 18921408cc1fSYuval Mintz qm_info->num_vf_pqs = num_vfs; 1893b5a9ee7cSAriel Elior for (vf_idx = 0; vf_idx < num_vfs; vf_idx++) 1894b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, 1895b5a9ee7cSAriel Elior qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL); 1896b5a9ee7cSAriel Elior } 1897fe56b9e6SYuval Mintz 1898b5a9ee7cSAriel Elior static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn) 1899b5a9ee7cSAriel Elior { 1900b5a9ee7cSAriel Elior u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn); 1901b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1902a64b02d5SManish Chopra 1903b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS)) 1904b5a9ee7cSAriel Elior return; 1905b5a9ee7cSAriel Elior 1906b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs); 1907b5a9ee7cSAriel Elior for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++) 1908c4259ddaSDenis Bolotin qed_init_qm_pq(p_hwfn, qm_info, qed_get_offload_tc(p_hwfn), 1909c4259ddaSDenis Bolotin PQ_INIT_PF_RL); 1910b5a9ee7cSAriel Elior } 1911b5a9ee7cSAriel Elior 1912b5a9ee7cSAriel Elior static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn) 1913b5a9ee7cSAriel Elior { 1914b5a9ee7cSAriel Elior /* rate limited pqs, must come first (FW assumption) */ 1915b5a9ee7cSAriel Elior qed_init_qm_rl_pqs(p_hwfn); 1916b5a9ee7cSAriel Elior 1917b5a9ee7cSAriel Elior /* pqs for multi cos */ 1918b5a9ee7cSAriel Elior qed_init_qm_mcos_pqs(p_hwfn); 1919b5a9ee7cSAriel Elior 1920b5a9ee7cSAriel Elior /* pure loopback pq */ 1921b5a9ee7cSAriel Elior qed_init_qm_lb_pq(p_hwfn); 1922b5a9ee7cSAriel Elior 1923b5a9ee7cSAriel Elior /* out of order pq */ 1924b5a9ee7cSAriel Elior qed_init_qm_ooo_pq(p_hwfn); 1925b5a9ee7cSAriel Elior 1926b5a9ee7cSAriel Elior /* pure ack pq */ 1927b5a9ee7cSAriel Elior qed_init_qm_pure_ack_pq(p_hwfn); 1928b5a9ee7cSAriel Elior 1929b5a9ee7cSAriel Elior /* pq for offloaded protocol */ 1930b5a9ee7cSAriel Elior qed_init_qm_offload_pq(p_hwfn); 1931b5a9ee7cSAriel Elior 1932b5a9ee7cSAriel Elior /* low latency pq */ 1933b5a9ee7cSAriel Elior qed_init_qm_low_latency_pq(p_hwfn); 1934b5a9ee7cSAriel Elior 1935b5a9ee7cSAriel Elior /* done sharing vports */ 1936b5a9ee7cSAriel Elior qed_init_qm_advance_vport(p_hwfn); 1937b5a9ee7cSAriel Elior 1938b5a9ee7cSAriel Elior /* pqs for vfs */ 1939b5a9ee7cSAriel Elior qed_init_qm_vf_pqs(p_hwfn); 1940b5a9ee7cSAriel Elior } 1941b5a9ee7cSAriel Elior 1942b5a9ee7cSAriel Elior /* compare values of getters against resources amounts */ 1943b5a9ee7cSAriel Elior static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn) 1944b5a9ee7cSAriel Elior { 1945b5a9ee7cSAriel Elior if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) { 1946b5a9ee7cSAriel Elior DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n"); 1947b5a9ee7cSAriel Elior return -EINVAL; 1948b5a9ee7cSAriel Elior } 1949b5a9ee7cSAriel Elior 195061be82b0SDenis Bolotin if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ)) 195161be82b0SDenis Bolotin return 0; 195261be82b0SDenis Bolotin 195361be82b0SDenis Bolotin if (QED_IS_ROCE_PERSONALITY(p_hwfn)) { 195482ebc889SJason Yan p_hwfn->hw_info.multi_tc_roce_en = false; 195561be82b0SDenis Bolotin DP_NOTICE(p_hwfn, 195661be82b0SDenis Bolotin "multi-tc roce was disabled to reduce requested amount of pqs\n"); 195761be82b0SDenis Bolotin if (qed_init_qm_get_num_pqs(p_hwfn) <= RESC_NUM(p_hwfn, QED_PQ)) 195861be82b0SDenis Bolotin return 0; 1959b5a9ee7cSAriel Elior } 1960fe56b9e6SYuval Mintz 196161be82b0SDenis Bolotin DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n"); 196261be82b0SDenis Bolotin return -EINVAL; 1963b5a9ee7cSAriel Elior } 1964fe56b9e6SYuval Mintz 1965b5a9ee7cSAriel Elior static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn) 1966b5a9ee7cSAriel Elior { 1967b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1968b5a9ee7cSAriel Elior struct init_qm_vport_params *vport; 1969b5a9ee7cSAriel Elior struct init_qm_port_params *port; 1970b5a9ee7cSAriel Elior struct init_qm_pq_params *pq; 1971b5a9ee7cSAriel Elior int i, tc; 1972b5a9ee7cSAriel Elior 1973b5a9ee7cSAriel Elior /* top level params */ 1974b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 1975b5a9ee7cSAriel Elior NETIF_MSG_HW, 197661be82b0SDenis Bolotin "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, llt_pq %d, pure_ack_pq %d\n", 1977b5a9ee7cSAriel Elior qm_info->start_pq, 1978b5a9ee7cSAriel Elior qm_info->start_vport, 1979b5a9ee7cSAriel Elior qm_info->pure_lb_pq, 198061be82b0SDenis Bolotin qm_info->first_ofld_pq, 198161be82b0SDenis Bolotin qm_info->first_llt_pq, 198261be82b0SDenis Bolotin qm_info->pure_ack_pq); 1983b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 1984b5a9ee7cSAriel Elior NETIF_MSG_HW, 1985b5a9ee7cSAriel Elior "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n", 1986b5a9ee7cSAriel Elior qm_info->ooo_pq, 1987b5a9ee7cSAriel Elior qm_info->first_vf_pq, 1988b5a9ee7cSAriel Elior qm_info->num_pqs, 1989b5a9ee7cSAriel Elior qm_info->num_vf_pqs, 1990b5a9ee7cSAriel Elior qm_info->num_vports, qm_info->max_phys_tcs_per_port); 1991b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 1992b5a9ee7cSAriel Elior NETIF_MSG_HW, 1993b5a9ee7cSAriel Elior "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n", 1994b5a9ee7cSAriel Elior qm_info->pf_rl_en, 1995b5a9ee7cSAriel Elior qm_info->pf_wfq_en, 1996b5a9ee7cSAriel Elior qm_info->vport_rl_en, 1997b5a9ee7cSAriel Elior qm_info->vport_wfq_en, 1998b5a9ee7cSAriel Elior qm_info->pf_wfq, 1999b5a9ee7cSAriel Elior qm_info->pf_rl, 2000b5a9ee7cSAriel Elior qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn)); 2001b5a9ee7cSAriel Elior 2002b5a9ee7cSAriel Elior /* port table */ 200378cea9ffSTomer Tayar for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) { 2004b5a9ee7cSAriel Elior port = &(qm_info->qm_port_params[i]); 2005b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 2006b5a9ee7cSAriel Elior NETIF_MSG_HW, 2007b5a9ee7cSAriel Elior "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n", 2008b5a9ee7cSAriel Elior i, 2009b5a9ee7cSAriel Elior port->active, 2010b5a9ee7cSAriel Elior port->active_phys_tcs, 2011b5a9ee7cSAriel Elior port->num_pbf_cmd_lines, 2012b5a9ee7cSAriel Elior port->num_btb_blocks, port->reserved); 2013b5a9ee7cSAriel Elior } 2014b5a9ee7cSAriel Elior 2015b5a9ee7cSAriel Elior /* vport table */ 2016b5a9ee7cSAriel Elior for (i = 0; i < qm_info->num_vports; i++) { 2017b5a9ee7cSAriel Elior vport = &(qm_info->qm_vport_params[i]); 2018b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 2019b5a9ee7cSAriel Elior NETIF_MSG_HW, 202092fae6fbSMichal Kalderon "vport idx %d, wfq %d, first_tx_pq_id [ ", 202192fae6fbSMichal Kalderon qm_info->start_vport + i, vport->wfq); 2022b5a9ee7cSAriel Elior for (tc = 0; tc < NUM_OF_TCS; tc++) 2023b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 2024b5a9ee7cSAriel Elior NETIF_MSG_HW, 2025b5a9ee7cSAriel Elior "%d ", vport->first_tx_pq_id[tc]); 2026b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n"); 2027b5a9ee7cSAriel Elior } 2028b5a9ee7cSAriel Elior 2029b5a9ee7cSAriel Elior /* pq table */ 2030b5a9ee7cSAriel Elior for (i = 0; i < qm_info->num_pqs; i++) { 2031b5a9ee7cSAriel Elior pq = &(qm_info->qm_pq_params[i]); 2032b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 2033b5a9ee7cSAriel Elior NETIF_MSG_HW, 203492fae6fbSMichal Kalderon "pq idx %d, port %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d rl_id %d\n", 2035b5a9ee7cSAriel Elior qm_info->start_pq + i, 203650bc60cbSMichal Kalderon pq->port_id, 2037b5a9ee7cSAriel Elior pq->vport_id, 203892fae6fbSMichal Kalderon pq->tc_id, pq->wrr_group, pq->rl_valid, pq->rl_id); 2039b5a9ee7cSAriel Elior } 2040b5a9ee7cSAriel Elior } 2041b5a9ee7cSAriel Elior 2042b5a9ee7cSAriel Elior static void qed_init_qm_info(struct qed_hwfn *p_hwfn) 2043b5a9ee7cSAriel Elior { 2044b5a9ee7cSAriel Elior /* reset params required for init run */ 2045b5a9ee7cSAriel Elior qed_init_qm_reset_params(p_hwfn); 2046b5a9ee7cSAriel Elior 2047b5a9ee7cSAriel Elior /* init QM top level params */ 2048b5a9ee7cSAriel Elior qed_init_qm_params(p_hwfn); 2049b5a9ee7cSAriel Elior 2050b5a9ee7cSAriel Elior /* init QM port params */ 2051b5a9ee7cSAriel Elior qed_init_qm_port_params(p_hwfn); 2052b5a9ee7cSAriel Elior 2053b5a9ee7cSAriel Elior /* init QM vport params */ 2054b5a9ee7cSAriel Elior qed_init_qm_vport_params(p_hwfn); 2055b5a9ee7cSAriel Elior 2056b5a9ee7cSAriel Elior /* init QM physical queue params */ 2057b5a9ee7cSAriel Elior qed_init_qm_pq_params(p_hwfn); 2058b5a9ee7cSAriel Elior 2059b5a9ee7cSAriel Elior /* display all that init */ 2060b5a9ee7cSAriel Elior qed_dp_init_qm_params(p_hwfn); 2061fe56b9e6SYuval Mintz } 2062fe56b9e6SYuval Mintz 206339651abdSSudarsana Reddy Kalluru /* This function reconfigures the QM pf on the fly. 206439651abdSSudarsana Reddy Kalluru * For this purpose we: 206539651abdSSudarsana Reddy Kalluru * 1. reconfigure the QM database 2066a2e7699eSTomer Tayar * 2. set new values to runtime array 206739651abdSSudarsana Reddy Kalluru * 3. send an sdm_qm_cmd through the rbc interface to stop the QM 206839651abdSSudarsana Reddy Kalluru * 4. activate init tool in QM_PF stage 206939651abdSSudarsana Reddy Kalluru * 5. send an sdm_qm_cmd through rbc interface to release the QM 207039651abdSSudarsana Reddy Kalluru */ 207139651abdSSudarsana Reddy Kalluru int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 207239651abdSSudarsana Reddy Kalluru { 207339651abdSSudarsana Reddy Kalluru struct qed_qm_info *qm_info = &p_hwfn->qm_info; 207439651abdSSudarsana Reddy Kalluru bool b_rc; 207539651abdSSudarsana Reddy Kalluru int rc; 207639651abdSSudarsana Reddy Kalluru 207739651abdSSudarsana Reddy Kalluru /* initialize qed's qm data structure */ 2078b5a9ee7cSAriel Elior qed_init_qm_info(p_hwfn); 207939651abdSSudarsana Reddy Kalluru 208039651abdSSudarsana Reddy Kalluru /* stop PF's qm queues */ 208139651abdSSudarsana Reddy Kalluru spin_lock_bh(&qm_lock); 208239651abdSSudarsana Reddy Kalluru b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true, 208339651abdSSudarsana Reddy Kalluru qm_info->start_pq, qm_info->num_pqs); 208439651abdSSudarsana Reddy Kalluru spin_unlock_bh(&qm_lock); 208539651abdSSudarsana Reddy Kalluru if (!b_rc) 208639651abdSSudarsana Reddy Kalluru return -EINVAL; 208739651abdSSudarsana Reddy Kalluru 208839651abdSSudarsana Reddy Kalluru /* prepare QM portion of runtime array */ 2089da090917STomer Tayar qed_qm_init_pf(p_hwfn, p_ptt, false); 209039651abdSSudarsana Reddy Kalluru 209139651abdSSudarsana Reddy Kalluru /* activate init tool on runtime array */ 209239651abdSSudarsana Reddy Kalluru rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id, 209339651abdSSudarsana Reddy Kalluru p_hwfn->hw_info.hw_mode); 209439651abdSSudarsana Reddy Kalluru if (rc) 209539651abdSSudarsana Reddy Kalluru return rc; 209639651abdSSudarsana Reddy Kalluru 209739651abdSSudarsana Reddy Kalluru /* start PF's qm queues */ 209839651abdSSudarsana Reddy Kalluru spin_lock_bh(&qm_lock); 209939651abdSSudarsana Reddy Kalluru b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true, 210039651abdSSudarsana Reddy Kalluru qm_info->start_pq, qm_info->num_pqs); 210139651abdSSudarsana Reddy Kalluru spin_unlock_bh(&qm_lock); 210239651abdSSudarsana Reddy Kalluru if (!b_rc) 210339651abdSSudarsana Reddy Kalluru return -EINVAL; 210439651abdSSudarsana Reddy Kalluru 210539651abdSSudarsana Reddy Kalluru return 0; 210639651abdSSudarsana Reddy Kalluru } 210739651abdSSudarsana Reddy Kalluru 2108b5a9ee7cSAriel Elior static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn) 2109b5a9ee7cSAriel Elior { 2110b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 2111b5a9ee7cSAriel Elior int rc; 2112b5a9ee7cSAriel Elior 2113b5a9ee7cSAriel Elior rc = qed_init_qm_sanity(p_hwfn); 2114b5a9ee7cSAriel Elior if (rc) 2115b5a9ee7cSAriel Elior goto alloc_err; 2116b5a9ee7cSAriel Elior 21176396bb22SKees Cook qm_info->qm_pq_params = kcalloc(qed_init_qm_get_num_pqs(p_hwfn), 21186396bb22SKees Cook sizeof(*qm_info->qm_pq_params), 2119b5a9ee7cSAriel Elior GFP_KERNEL); 2120b5a9ee7cSAriel Elior if (!qm_info->qm_pq_params) 2121b5a9ee7cSAriel Elior goto alloc_err; 2122b5a9ee7cSAriel Elior 21236396bb22SKees Cook qm_info->qm_vport_params = kcalloc(qed_init_qm_get_num_vports(p_hwfn), 21246396bb22SKees Cook sizeof(*qm_info->qm_vport_params), 2125b5a9ee7cSAriel Elior GFP_KERNEL); 2126b5a9ee7cSAriel Elior if (!qm_info->qm_vport_params) 2127b5a9ee7cSAriel Elior goto alloc_err; 2128b5a9ee7cSAriel Elior 21296396bb22SKees Cook qm_info->qm_port_params = kcalloc(p_hwfn->cdev->num_ports_in_engine, 21306396bb22SKees Cook sizeof(*qm_info->qm_port_params), 2131b5a9ee7cSAriel Elior GFP_KERNEL); 2132b5a9ee7cSAriel Elior if (!qm_info->qm_port_params) 2133b5a9ee7cSAriel Elior goto alloc_err; 2134b5a9ee7cSAriel Elior 21356396bb22SKees Cook qm_info->wfq_data = kcalloc(qed_init_qm_get_num_vports(p_hwfn), 21366396bb22SKees Cook sizeof(*qm_info->wfq_data), 2137b5a9ee7cSAriel Elior GFP_KERNEL); 2138b5a9ee7cSAriel Elior if (!qm_info->wfq_data) 2139b5a9ee7cSAriel Elior goto alloc_err; 2140b5a9ee7cSAriel Elior 2141b5a9ee7cSAriel Elior return 0; 2142b5a9ee7cSAriel Elior 2143b5a9ee7cSAriel Elior alloc_err: 2144b5a9ee7cSAriel Elior DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n"); 2145b5a9ee7cSAriel Elior qed_qm_info_free(p_hwfn); 2146b5a9ee7cSAriel Elior return -ENOMEM; 2147b5a9ee7cSAriel Elior } 2148b5a9ee7cSAriel Elior 2149fe56b9e6SYuval Mintz int qed_resc_alloc(struct qed_dev *cdev) 2150fe56b9e6SYuval Mintz { 2151f9dc4d1fSRam Amrani u32 rdma_tasks, excess_tasks; 2152f9dc4d1fSRam Amrani u32 line_count; 2153fe56b9e6SYuval Mintz int i, rc = 0; 2154fe56b9e6SYuval Mintz 21550db711bbSMintz, Yuval if (IS_VF(cdev)) { 21560db711bbSMintz, Yuval for_each_hwfn(cdev, i) { 21570db711bbSMintz, Yuval rc = qed_l2_alloc(&cdev->hwfns[i]); 21580db711bbSMintz, Yuval if (rc) 21591408cc1fSYuval Mintz return rc; 21600db711bbSMintz, Yuval } 21610db711bbSMintz, Yuval return rc; 21620db711bbSMintz, Yuval } 21631408cc1fSYuval Mintz 2164fe56b9e6SYuval Mintz cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL); 2165fe56b9e6SYuval Mintz if (!cdev->fw_data) 2166fe56b9e6SYuval Mintz return -ENOMEM; 2167fe56b9e6SYuval Mintz 2168fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 2169fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2170dbb799c3SYuval Mintz u32 n_eqes, num_cons; 2171fe56b9e6SYuval Mintz 217236907cd5SAriel Elior /* Initialize the doorbell recovery mechanism */ 217336907cd5SAriel Elior rc = qed_db_recovery_setup(p_hwfn); 217436907cd5SAriel Elior if (rc) 217536907cd5SAriel Elior goto alloc_err; 217636907cd5SAriel Elior 2177fe56b9e6SYuval Mintz /* First allocate the context manager structure */ 2178fe56b9e6SYuval Mintz rc = qed_cxt_mngr_alloc(p_hwfn); 2179fe56b9e6SYuval Mintz if (rc) 2180fe56b9e6SYuval Mintz goto alloc_err; 2181fe56b9e6SYuval Mintz 2182fe56b9e6SYuval Mintz /* Set the HW cid/tid numbers (in the contest manager) 2183fe56b9e6SYuval Mintz * Must be done prior to any further computations. 2184fe56b9e6SYuval Mintz */ 2185f9dc4d1fSRam Amrani rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS); 2186fe56b9e6SYuval Mintz if (rc) 2187fe56b9e6SYuval Mintz goto alloc_err; 2188fe56b9e6SYuval Mintz 2189b5a9ee7cSAriel Elior rc = qed_alloc_qm_data(p_hwfn); 2190fe56b9e6SYuval Mintz if (rc) 2191fe56b9e6SYuval Mintz goto alloc_err; 2192fe56b9e6SYuval Mintz 2193b5a9ee7cSAriel Elior /* init qm info */ 2194b5a9ee7cSAriel Elior qed_init_qm_info(p_hwfn); 2195b5a9ee7cSAriel Elior 2196fe56b9e6SYuval Mintz /* Compute the ILT client partition */ 2197f9dc4d1fSRam Amrani rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count); 2198f9dc4d1fSRam Amrani if (rc) { 2199f9dc4d1fSRam Amrani DP_NOTICE(p_hwfn, 2200f9dc4d1fSRam Amrani "too many ILT lines; re-computing with less lines\n"); 2201f9dc4d1fSRam Amrani /* In case there are not enough ILT lines we reduce the 2202f9dc4d1fSRam Amrani * number of RDMA tasks and re-compute. 2203f9dc4d1fSRam Amrani */ 2204f9dc4d1fSRam Amrani excess_tasks = 2205f9dc4d1fSRam Amrani qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count); 2206f9dc4d1fSRam Amrani if (!excess_tasks) 2207f9dc4d1fSRam Amrani goto alloc_err; 2208f9dc4d1fSRam Amrani 2209f9dc4d1fSRam Amrani rdma_tasks = RDMA_MAX_TIDS - excess_tasks; 2210f9dc4d1fSRam Amrani rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks); 2211fe56b9e6SYuval Mintz if (rc) 2212fe56b9e6SYuval Mintz goto alloc_err; 2213fe56b9e6SYuval Mintz 2214f9dc4d1fSRam Amrani rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count); 2215f9dc4d1fSRam Amrani if (rc) { 2216f9dc4d1fSRam Amrani DP_ERR(p_hwfn, 2217f9dc4d1fSRam Amrani "failed ILT compute. Requested too many lines: %u\n", 2218f9dc4d1fSRam Amrani line_count); 2219f9dc4d1fSRam Amrani 2220f9dc4d1fSRam Amrani goto alloc_err; 2221f9dc4d1fSRam Amrani } 2222f9dc4d1fSRam Amrani } 2223f9dc4d1fSRam Amrani 2224fe56b9e6SYuval Mintz /* CID map / ILT shadow table / T2 2225fe56b9e6SYuval Mintz * The talbes sizes are determined by the computations above 2226fe56b9e6SYuval Mintz */ 2227fe56b9e6SYuval Mintz rc = qed_cxt_tables_alloc(p_hwfn); 2228fe56b9e6SYuval Mintz if (rc) 2229fe56b9e6SYuval Mintz goto alloc_err; 2230fe56b9e6SYuval Mintz 2231fe56b9e6SYuval Mintz /* SPQ, must follow ILT because initializes SPQ context */ 2232fe56b9e6SYuval Mintz rc = qed_spq_alloc(p_hwfn); 2233fe56b9e6SYuval Mintz if (rc) 2234fe56b9e6SYuval Mintz goto alloc_err; 2235fe56b9e6SYuval Mintz 2236fe56b9e6SYuval Mintz /* SP status block allocation */ 2237fe56b9e6SYuval Mintz p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn, 2238fe56b9e6SYuval Mintz RESERVED_PTT_DPC); 2239fe56b9e6SYuval Mintz 2240fe56b9e6SYuval Mintz rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt); 2241fe56b9e6SYuval Mintz if (rc) 2242fe56b9e6SYuval Mintz goto alloc_err; 2243fe56b9e6SYuval Mintz 224432a47e72SYuval Mintz rc = qed_iov_alloc(p_hwfn); 224532a47e72SYuval Mintz if (rc) 224632a47e72SYuval Mintz goto alloc_err; 224732a47e72SYuval Mintz 2248fe56b9e6SYuval Mintz /* EQ */ 2249dbb799c3SYuval Mintz n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain); 2250c851a9dcSKalderon, Michal if (QED_IS_RDMA_PERSONALITY(p_hwfn)) { 2251b8204ad8SYuval Basson u32 n_srq = qed_cxt_get_total_srq_count(p_hwfn); 225267b40dccSKalderon, Michal enum protocol_type rdma_proto; 225367b40dccSKalderon, Michal 225467b40dccSKalderon, Michal if (QED_IS_ROCE_PERSONALITY(p_hwfn)) 225567b40dccSKalderon, Michal rdma_proto = PROTOCOLID_ROCE; 225667b40dccSKalderon, Michal else 225767b40dccSKalderon, Michal rdma_proto = PROTOCOLID_IWARP; 225867b40dccSKalderon, Michal 2259dbb799c3SYuval Mintz num_cons = qed_cxt_get_proto_cid_count(p_hwfn, 226067b40dccSKalderon, Michal rdma_proto, 22618c93beafSYuval Mintz NULL) * 2; 2262b8204ad8SYuval Basson /* EQ should be able to get events from all SRQ's 2263b8204ad8SYuval Basson * at the same time 2264b8204ad8SYuval Basson */ 2265b8204ad8SYuval Basson n_eqes += num_cons + 2 * MAX_NUM_VFS_BB + n_srq; 2266dbb799c3SYuval Mintz } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 2267dbb799c3SYuval Mintz num_cons = 2268dbb799c3SYuval Mintz qed_cxt_get_proto_cid_count(p_hwfn, 22698c93beafSYuval Mintz PROTOCOLID_ISCSI, 22708c93beafSYuval Mintz NULL); 2271dbb799c3SYuval Mintz n_eqes += 2 * num_cons; 2272dbb799c3SYuval Mintz } 2273dbb799c3SYuval Mintz 2274dbb799c3SYuval Mintz if (n_eqes > 0xFFFF) { 2275dbb799c3SYuval Mintz DP_ERR(p_hwfn, 2276dbb799c3SYuval Mintz "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n", 2277dbb799c3SYuval Mintz n_eqes, 0xFFFF); 22783587cb87STomer Tayar goto alloc_no_mem; 22799b15acbfSDan Carpenter } 2280dbb799c3SYuval Mintz 22813587cb87STomer Tayar rc = qed_eq_alloc(p_hwfn, (u16) n_eqes); 22823587cb87STomer Tayar if (rc) 22833587cb87STomer Tayar goto alloc_err; 2284fe56b9e6SYuval Mintz 22853587cb87STomer Tayar rc = qed_consq_alloc(p_hwfn); 22863587cb87STomer Tayar if (rc) 22873587cb87STomer Tayar goto alloc_err; 2288fe56b9e6SYuval Mintz 22890db711bbSMintz, Yuval rc = qed_l2_alloc(p_hwfn); 22900db711bbSMintz, Yuval if (rc) 22910db711bbSMintz, Yuval goto alloc_err; 22920db711bbSMintz, Yuval 22930a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 22940a7fb11cSYuval Mintz if (p_hwfn->using_ll2) { 22953587cb87STomer Tayar rc = qed_ll2_alloc(p_hwfn); 22963587cb87STomer Tayar if (rc) 22973587cb87STomer Tayar goto alloc_err; 22980a7fb11cSYuval Mintz } 22990a7fb11cSYuval Mintz #endif 23001e128c81SArun Easi 23011e128c81SArun Easi if (p_hwfn->hw_info.personality == QED_PCI_FCOE) { 23023587cb87STomer Tayar rc = qed_fcoe_alloc(p_hwfn); 23033587cb87STomer Tayar if (rc) 23043587cb87STomer Tayar goto alloc_err; 23051e128c81SArun Easi } 23061e128c81SArun Easi 2307fc831825SYuval Mintz if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 23083587cb87STomer Tayar rc = qed_iscsi_alloc(p_hwfn); 23093587cb87STomer Tayar if (rc) 23103587cb87STomer Tayar goto alloc_err; 23113587cb87STomer Tayar rc = qed_ooo_alloc(p_hwfn); 23123587cb87STomer Tayar if (rc) 23133587cb87STomer Tayar goto alloc_err; 2314fc831825SYuval Mintz } 23150a7fb11cSYuval Mintz 2316291d57f6SMichal Kalderon if (QED_IS_RDMA_PERSONALITY(p_hwfn)) { 2317291d57f6SMichal Kalderon rc = qed_rdma_info_alloc(p_hwfn); 2318291d57f6SMichal Kalderon if (rc) 2319291d57f6SMichal Kalderon goto alloc_err; 2320291d57f6SMichal Kalderon } 2321291d57f6SMichal Kalderon 2322fe56b9e6SYuval Mintz /* DMA info initialization */ 2323fe56b9e6SYuval Mintz rc = qed_dmae_info_alloc(p_hwfn); 23242591c280SJoe Perches if (rc) 2325fe56b9e6SYuval Mintz goto alloc_err; 232639651abdSSudarsana Reddy Kalluru 232739651abdSSudarsana Reddy Kalluru /* DCBX initialization */ 232839651abdSSudarsana Reddy Kalluru rc = qed_dcbx_info_alloc(p_hwfn); 23292591c280SJoe Perches if (rc) 233039651abdSSudarsana Reddy Kalluru goto alloc_err; 2331a3f72307SDenis Bolotin 23322d22bc83SMichal Kalderon rc = qed_dbg_alloc_user_data(p_hwfn, &p_hwfn->dbg_user_info); 2333a3f72307SDenis Bolotin if (rc) 2334a3f72307SDenis Bolotin goto alloc_err; 233539651abdSSudarsana Reddy Kalluru } 2336fe56b9e6SYuval Mintz 233779284adeSMichal Kalderon rc = qed_llh_alloc(cdev); 233879284adeSMichal Kalderon if (rc) { 233979284adeSMichal Kalderon DP_NOTICE(cdev, 234079284adeSMichal Kalderon "Failed to allocate memory for the llh_info structure\n"); 234179284adeSMichal Kalderon goto alloc_err; 234279284adeSMichal Kalderon } 234379284adeSMichal Kalderon 2344fe56b9e6SYuval Mintz cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL); 23452591c280SJoe Perches if (!cdev->reset_stats) 234683aeb933SYuval Mintz goto alloc_no_mem; 2347fe56b9e6SYuval Mintz 2348fe56b9e6SYuval Mintz return 0; 2349fe56b9e6SYuval Mintz 2350dbb799c3SYuval Mintz alloc_no_mem: 2351dbb799c3SYuval Mintz rc = -ENOMEM; 2352fe56b9e6SYuval Mintz alloc_err: 2353fe56b9e6SYuval Mintz qed_resc_free(cdev); 2354fe56b9e6SYuval Mintz return rc; 2355fe56b9e6SYuval Mintz } 2356fe56b9e6SYuval Mintz 2357fe56b9e6SYuval Mintz void qed_resc_setup(struct qed_dev *cdev) 2358fe56b9e6SYuval Mintz { 2359fe56b9e6SYuval Mintz int i; 2360fe56b9e6SYuval Mintz 23610db711bbSMintz, Yuval if (IS_VF(cdev)) { 23620db711bbSMintz, Yuval for_each_hwfn(cdev, i) 23630db711bbSMintz, Yuval qed_l2_setup(&cdev->hwfns[i]); 23641408cc1fSYuval Mintz return; 23650db711bbSMintz, Yuval } 23661408cc1fSYuval Mintz 2367fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 2368fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2369fe56b9e6SYuval Mintz 2370fe56b9e6SYuval Mintz qed_cxt_mngr_setup(p_hwfn); 2371fe56b9e6SYuval Mintz qed_spq_setup(p_hwfn); 23723587cb87STomer Tayar qed_eq_setup(p_hwfn); 23733587cb87STomer Tayar qed_consq_setup(p_hwfn); 2374fe56b9e6SYuval Mintz 2375fe56b9e6SYuval Mintz /* Read shadow of current MFW mailbox */ 2376fe56b9e6SYuval Mintz qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt); 2377fe56b9e6SYuval Mintz memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 2378fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_cur, 2379fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_length); 2380fe56b9e6SYuval Mintz 2381fe56b9e6SYuval Mintz qed_int_setup(p_hwfn, p_hwfn->p_main_ptt); 238232a47e72SYuval Mintz 23830db711bbSMintz, Yuval qed_l2_setup(p_hwfn); 23841ee240e3SMintz, Yuval qed_iov_setup(p_hwfn); 23850a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 23860a7fb11cSYuval Mintz if (p_hwfn->using_ll2) 23873587cb87STomer Tayar qed_ll2_setup(p_hwfn); 23880a7fb11cSYuval Mintz #endif 23891e128c81SArun Easi if (p_hwfn->hw_info.personality == QED_PCI_FCOE) 23903587cb87STomer Tayar qed_fcoe_setup(p_hwfn); 23911e128c81SArun Easi 23921d6cff4fSYuval Mintz if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 23933587cb87STomer Tayar qed_iscsi_setup(p_hwfn); 23943587cb87STomer Tayar qed_ooo_setup(p_hwfn); 23951d6cff4fSYuval Mintz } 2396fe56b9e6SYuval Mintz } 2397fe56b9e6SYuval Mintz } 2398fe56b9e6SYuval Mintz 2399fe56b9e6SYuval Mintz #define FINAL_CLEANUP_POLL_CNT (100) 2400fe56b9e6SYuval Mintz #define FINAL_CLEANUP_POLL_TIME (10) 2401fe56b9e6SYuval Mintz int qed_final_cleanup(struct qed_hwfn *p_hwfn, 24020b55e27dSYuval Mintz struct qed_ptt *p_ptt, u16 id, bool is_vf) 2403fe56b9e6SYuval Mintz { 2404fe56b9e6SYuval Mintz u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT; 2405fe56b9e6SYuval Mintz int rc = -EBUSY; 2406fe56b9e6SYuval Mintz 2407fc48b7a6SYuval Mintz addr = GTT_BAR0_MAP_REG_USDM_RAM + 2408fc48b7a6SYuval Mintz USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id); 2409fe56b9e6SYuval Mintz 24100b55e27dSYuval Mintz if (is_vf) 24110b55e27dSYuval Mintz id += 0x10; 24120b55e27dSYuval Mintz 2413fc48b7a6SYuval Mintz command |= X_FINAL_CLEANUP_AGG_INT << 2414fc48b7a6SYuval Mintz SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT; 2415fc48b7a6SYuval Mintz command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT; 2416fc48b7a6SYuval Mintz command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT; 2417fc48b7a6SYuval Mintz command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT; 2418fe56b9e6SYuval Mintz 2419fe56b9e6SYuval Mintz /* Make sure notification is not set before initiating final cleanup */ 2420fe56b9e6SYuval Mintz if (REG_RD(p_hwfn, addr)) { 24211a635e48SYuval Mintz DP_NOTICE(p_hwfn, 2422fe56b9e6SYuval Mintz "Unexpected; Found final cleanup notification before initiating final cleanup\n"); 2423fe56b9e6SYuval Mintz REG_WR(p_hwfn, addr, 0); 2424fe56b9e6SYuval Mintz } 2425fe56b9e6SYuval Mintz 2426fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_IOV, 2427d602de8eSJoe Perches "Sending final cleanup for PFVF[%d] [Command %08x]\n", 2428fe56b9e6SYuval Mintz id, command); 2429fe56b9e6SYuval Mintz 2430fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command); 2431fe56b9e6SYuval Mintz 2432fe56b9e6SYuval Mintz /* Poll until completion */ 2433fe56b9e6SYuval Mintz while (!REG_RD(p_hwfn, addr) && count--) 2434fe56b9e6SYuval Mintz msleep(FINAL_CLEANUP_POLL_TIME); 2435fe56b9e6SYuval Mintz 2436fe56b9e6SYuval Mintz if (REG_RD(p_hwfn, addr)) 2437fe56b9e6SYuval Mintz rc = 0; 2438fe56b9e6SYuval Mintz else 2439fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 2440fe56b9e6SYuval Mintz "Failed to receive FW final cleanup notification\n"); 2441fe56b9e6SYuval Mintz 2442fe56b9e6SYuval Mintz /* Cleanup afterwards */ 2443fe56b9e6SYuval Mintz REG_WR(p_hwfn, addr, 0); 2444fe56b9e6SYuval Mintz 2445fe56b9e6SYuval Mintz return rc; 2446fe56b9e6SYuval Mintz } 2447fe56b9e6SYuval Mintz 24489c79ddaaSMintz, Yuval static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn) 2449fe56b9e6SYuval Mintz { 2450fe56b9e6SYuval Mintz int hw_mode = 0; 2451fe56b9e6SYuval Mintz 24529c79ddaaSMintz, Yuval if (QED_IS_BB_B0(p_hwfn->cdev)) { 24539c79ddaaSMintz, Yuval hw_mode |= 1 << MODE_BB; 24549c79ddaaSMintz, Yuval } else if (QED_IS_AH(p_hwfn->cdev)) { 24559c79ddaaSMintz, Yuval hw_mode |= 1 << MODE_K2; 24569c79ddaaSMintz, Yuval } else { 24579c79ddaaSMintz, Yuval DP_NOTICE(p_hwfn, "Unknown chip type %#x\n", 24589c79ddaaSMintz, Yuval p_hwfn->cdev->type); 24599c79ddaaSMintz, Yuval return -EINVAL; 24609c79ddaaSMintz, Yuval } 2461fe56b9e6SYuval Mintz 246278cea9ffSTomer Tayar switch (p_hwfn->cdev->num_ports_in_engine) { 2463fe56b9e6SYuval Mintz case 1: 2464fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_PORTS_PER_ENG_1; 2465fe56b9e6SYuval Mintz break; 2466fe56b9e6SYuval Mintz case 2: 2467fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_PORTS_PER_ENG_2; 2468fe56b9e6SYuval Mintz break; 2469fe56b9e6SYuval Mintz case 4: 2470fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_PORTS_PER_ENG_4; 2471fe56b9e6SYuval Mintz break; 2472fe56b9e6SYuval Mintz default: 2473fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n", 247478cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine); 24759c79ddaaSMintz, Yuval return -EINVAL; 2476fe56b9e6SYuval Mintz } 2477fe56b9e6SYuval Mintz 24780bc5fe85SSudarsana Reddy Kalluru if (test_bit(QED_MF_OVLAN_CLSS, &p_hwfn->cdev->mf_bits)) 2479fc48b7a6SYuval Mintz hw_mode |= 1 << MODE_MF_SD; 24800bc5fe85SSudarsana Reddy Kalluru else 2481fc48b7a6SYuval Mintz hw_mode |= 1 << MODE_MF_SI; 2482fe56b9e6SYuval Mintz 2483fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_ASIC; 2484fe56b9e6SYuval Mintz 24851af9dcf7SYuval Mintz if (p_hwfn->cdev->num_hwfns > 1) 24861af9dcf7SYuval Mintz hw_mode |= 1 << MODE_100G; 24871af9dcf7SYuval Mintz 2488fe56b9e6SYuval Mintz p_hwfn->hw_info.hw_mode = hw_mode; 24891af9dcf7SYuval Mintz 24901af9dcf7SYuval Mintz DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP), 24911af9dcf7SYuval Mintz "Configuring function for hw_mode: 0x%08x\n", 24921af9dcf7SYuval Mintz p_hwfn->hw_info.hw_mode); 24939c79ddaaSMintz, Yuval 24949c79ddaaSMintz, Yuval return 0; 2495fe56b9e6SYuval Mintz } 2496fe56b9e6SYuval Mintz 2497fe56b9e6SYuval Mintz /* Init run time data for all PFs on an engine. */ 2498fe56b9e6SYuval Mintz static void qed_init_cau_rt_data(struct qed_dev *cdev) 2499fe56b9e6SYuval Mintz { 2500fe56b9e6SYuval Mintz u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET; 2501d031548eSMintz, Yuval int i, igu_sb_id; 2502fe56b9e6SYuval Mintz 2503fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 2504fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2505fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 2506fe56b9e6SYuval Mintz struct qed_igu_block *p_block; 2507fe56b9e6SYuval Mintz struct cau_sb_entry sb_entry; 2508fe56b9e6SYuval Mintz 2509fe56b9e6SYuval Mintz p_igu_info = p_hwfn->hw_info.p_igu_info; 2510fe56b9e6SYuval Mintz 2511d031548eSMintz, Yuval for (igu_sb_id = 0; 2512d031548eSMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) { 2513d031548eSMintz, Yuval p_block = &p_igu_info->entry[igu_sb_id]; 2514d031548eSMintz, Yuval 2515fe56b9e6SYuval Mintz if (!p_block->is_pf) 2516fe56b9e6SYuval Mintz continue; 2517fe56b9e6SYuval Mintz 2518fe56b9e6SYuval Mintz qed_init_cau_sb_entry(p_hwfn, &sb_entry, 25191a635e48SYuval Mintz p_block->function_id, 0, 0); 2520d031548eSMintz, Yuval STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2, 2521d031548eSMintz, Yuval sb_entry); 2522fe56b9e6SYuval Mintz } 2523fe56b9e6SYuval Mintz } 2524fe56b9e6SYuval Mintz } 2525fe56b9e6SYuval Mintz 252660afed72STomer Tayar static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn, 252760afed72STomer Tayar struct qed_ptt *p_ptt) 252860afed72STomer Tayar { 252960afed72STomer Tayar u32 val, wr_mbs, cache_line_size; 253060afed72STomer Tayar 253160afed72STomer Tayar val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0); 253260afed72STomer Tayar switch (val) { 253360afed72STomer Tayar case 0: 253460afed72STomer Tayar wr_mbs = 128; 253560afed72STomer Tayar break; 253660afed72STomer Tayar case 1: 253760afed72STomer Tayar wr_mbs = 256; 253860afed72STomer Tayar break; 253960afed72STomer Tayar case 2: 254060afed72STomer Tayar wr_mbs = 512; 254160afed72STomer Tayar break; 254260afed72STomer Tayar default: 254360afed72STomer Tayar DP_INFO(p_hwfn, 254460afed72STomer Tayar "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n", 254560afed72STomer Tayar val); 254660afed72STomer Tayar return; 254760afed72STomer Tayar } 254860afed72STomer Tayar 254960afed72STomer Tayar cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs); 255060afed72STomer Tayar switch (cache_line_size) { 255160afed72STomer Tayar case 32: 255260afed72STomer Tayar val = 0; 255360afed72STomer Tayar break; 255460afed72STomer Tayar case 64: 255560afed72STomer Tayar val = 1; 255660afed72STomer Tayar break; 255760afed72STomer Tayar case 128: 255860afed72STomer Tayar val = 2; 255960afed72STomer Tayar break; 256060afed72STomer Tayar case 256: 256160afed72STomer Tayar val = 3; 256260afed72STomer Tayar break; 256360afed72STomer Tayar default: 256460afed72STomer Tayar DP_INFO(p_hwfn, 256560afed72STomer Tayar "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n", 256660afed72STomer Tayar cache_line_size); 256760afed72STomer Tayar } 256860afed72STomer Tayar 256960afed72STomer Tayar if (L1_CACHE_BYTES > wr_mbs) 257060afed72STomer Tayar DP_INFO(p_hwfn, 257160afed72STomer Tayar "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n", 257260afed72STomer Tayar L1_CACHE_BYTES, wr_mbs); 257360afed72STomer Tayar 257460afed72STomer Tayar STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val); 2575fc6575bcSMintz, Yuval if (val > 0) { 2576fc6575bcSMintz, Yuval STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val); 2577fc6575bcSMintz, Yuval STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val); 2578fc6575bcSMintz, Yuval } 257960afed72STomer Tayar } 258060afed72STomer Tayar 2581fe56b9e6SYuval Mintz static int qed_hw_init_common(struct qed_hwfn *p_hwfn, 25821a635e48SYuval Mintz struct qed_ptt *p_ptt, int hw_mode) 2583fe56b9e6SYuval Mintz { 2584fe56b9e6SYuval Mintz struct qed_qm_info *qm_info = &p_hwfn->qm_info; 2585fe56b9e6SYuval Mintz struct qed_qm_common_rt_init_params params; 2586fe56b9e6SYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 25879c79ddaaSMintz, Yuval u8 vf_id, max_num_vfs; 2588dbb799c3SYuval Mintz u16 num_pfs, pf_id; 25891408cc1fSYuval Mintz u32 concrete_fid; 2590fe56b9e6SYuval Mintz int rc = 0; 2591fe56b9e6SYuval Mintz 2592fe56b9e6SYuval Mintz qed_init_cau_rt_data(cdev); 2593fe56b9e6SYuval Mintz 2594fe56b9e6SYuval Mintz /* Program GTT windows */ 2595fe56b9e6SYuval Mintz qed_gtt_init(p_hwfn); 2596fe56b9e6SYuval Mintz 2597fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 2598fe56b9e6SYuval Mintz if (p_hwfn->mcp_info->func_info.bandwidth_max) 2599c7281d59SGustavo A. R. Silva qm_info->pf_rl_en = true; 2600fe56b9e6SYuval Mintz if (p_hwfn->mcp_info->func_info.bandwidth_min) 2601c7281d59SGustavo A. R. Silva qm_info->pf_wfq_en = true; 2602fe56b9e6SYuval Mintz } 2603fe56b9e6SYuval Mintz 2604fe56b9e6SYuval Mintz memset(¶ms, 0, sizeof(params)); 260578cea9ffSTomer Tayar params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine; 2606fe56b9e6SYuval Mintz params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port; 2607fe56b9e6SYuval Mintz params.pf_rl_en = qm_info->pf_rl_en; 2608fe56b9e6SYuval Mintz params.pf_wfq_en = qm_info->pf_wfq_en; 260992fae6fbSMichal Kalderon params.global_rl_en = qm_info->vport_rl_en; 2610fe56b9e6SYuval Mintz params.vport_wfq_en = qm_info->vport_wfq_en; 2611fe56b9e6SYuval Mintz params.port_params = qm_info->qm_port_params; 2612fe56b9e6SYuval Mintz 2613fe56b9e6SYuval Mintz qed_qm_common_rt_init(p_hwfn, ¶ms); 2614fe56b9e6SYuval Mintz 2615fe56b9e6SYuval Mintz qed_cxt_hw_init_common(p_hwfn); 2616fe56b9e6SYuval Mintz 261760afed72STomer Tayar qed_init_cache_line_size(p_hwfn, p_ptt); 261860afed72STomer Tayar 2619fe56b9e6SYuval Mintz rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode); 26201a635e48SYuval Mintz if (rc) 2621fe56b9e6SYuval Mintz return rc; 2622fe56b9e6SYuval Mintz 2623fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0); 2624fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1); 2625fe56b9e6SYuval Mintz 2626dbb799c3SYuval Mintz if (QED_IS_BB(p_hwfn->cdev)) { 2627dbb799c3SYuval Mintz num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev); 2628dbb799c3SYuval Mintz for (pf_id = 0; pf_id < num_pfs; pf_id++) { 2629dbb799c3SYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, pf_id); 2630dbb799c3SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 2631dbb799c3SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 2632dbb799c3SYuval Mintz } 2633dbb799c3SYuval Mintz /* pretend to original PF */ 2634dbb799c3SYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 2635dbb799c3SYuval Mintz } 2636fe56b9e6SYuval Mintz 26379c79ddaaSMintz, Yuval max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB; 26389c79ddaaSMintz, Yuval for (vf_id = 0; vf_id < max_num_vfs; vf_id++) { 26391408cc1fSYuval Mintz concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id); 26401408cc1fSYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid); 26411408cc1fSYuval Mintz qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1); 264205fafbfbSYuval Mintz qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0); 264305fafbfbSYuval Mintz qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1); 264405fafbfbSYuval Mintz qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0); 26451408cc1fSYuval Mintz } 26461408cc1fSYuval Mintz /* pretend to original PF */ 26471408cc1fSYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 26481408cc1fSYuval Mintz 2649fe56b9e6SYuval Mintz return rc; 2650fe56b9e6SYuval Mintz } 2651fe56b9e6SYuval Mintz 265251ff1725SRam Amrani static int 265351ff1725SRam Amrani qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn, 265451ff1725SRam Amrani struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus) 265551ff1725SRam Amrani { 2656107392b7SRam Amrani u32 dpi_bit_shift, dpi_count, dpi_page_size; 265751ff1725SRam Amrani u32 min_dpis; 2658107392b7SRam Amrani u32 n_wids; 265951ff1725SRam Amrani 266051ff1725SRam Amrani /* Calculate DPI size */ 2661107392b7SRam Amrani n_wids = max_t(u32, QED_MIN_WIDS, n_cpus); 2662107392b7SRam Amrani dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids); 2663107392b7SRam Amrani dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1); 266451ff1725SRam Amrani dpi_bit_shift = ilog2(dpi_page_size / 4096); 266551ff1725SRam Amrani dpi_count = pwm_region_size / dpi_page_size; 266651ff1725SRam Amrani 266751ff1725SRam Amrani min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis; 266851ff1725SRam Amrani min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis); 266951ff1725SRam Amrani 267051ff1725SRam Amrani p_hwfn->dpi_size = dpi_page_size; 267151ff1725SRam Amrani p_hwfn->dpi_count = dpi_count; 267251ff1725SRam Amrani 267351ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift); 267451ff1725SRam Amrani 267551ff1725SRam Amrani if (dpi_count < min_dpis) 267651ff1725SRam Amrani return -EINVAL; 267751ff1725SRam Amrani 267851ff1725SRam Amrani return 0; 267951ff1725SRam Amrani } 268051ff1725SRam Amrani 268151ff1725SRam Amrani enum QED_ROCE_EDPM_MODE { 268251ff1725SRam Amrani QED_ROCE_EDPM_MODE_ENABLE = 0, 268351ff1725SRam Amrani QED_ROCE_EDPM_MODE_FORCE_ON = 1, 268451ff1725SRam Amrani QED_ROCE_EDPM_MODE_DISABLE = 2, 268551ff1725SRam Amrani }; 268651ff1725SRam Amrani 2687a1b469b8SAriel Elior bool qed_edpm_enabled(struct qed_hwfn *p_hwfn) 2688a1b469b8SAriel Elior { 2689a1b469b8SAriel Elior if (p_hwfn->dcbx_no_edpm || p_hwfn->db_bar_no_edpm) 2690a1b469b8SAriel Elior return false; 2691a1b469b8SAriel Elior 2692a1b469b8SAriel Elior return true; 2693a1b469b8SAriel Elior } 2694a1b469b8SAriel Elior 269551ff1725SRam Amrani static int 269651ff1725SRam Amrani qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 269751ff1725SRam Amrani { 269851ff1725SRam Amrani u32 pwm_regsize, norm_regsize; 269951ff1725SRam Amrani u32 non_pwm_conn, min_addr_reg1; 270020b1bd96SRam Amrani u32 db_bar_size, n_cpus = 1; 270151ff1725SRam Amrani u32 roce_edpm_mode; 270251ff1725SRam Amrani u32 pf_dems_shift; 270351ff1725SRam Amrani int rc = 0; 270451ff1725SRam Amrani u8 cond; 270551ff1725SRam Amrani 270615582962SRahul Verma db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1); 270751ff1725SRam Amrani if (p_hwfn->cdev->num_hwfns > 1) 270851ff1725SRam Amrani db_bar_size /= 2; 270951ff1725SRam Amrani 271051ff1725SRam Amrani /* Calculate doorbell regions */ 271151ff1725SRam Amrani non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) + 271251ff1725SRam Amrani qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE, 271351ff1725SRam Amrani NULL) + 271451ff1725SRam Amrani qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, 271551ff1725SRam Amrani NULL); 2716a82dadbcSRam Amrani norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE); 271751ff1725SRam Amrani min_addr_reg1 = norm_regsize / 4096; 271851ff1725SRam Amrani pwm_regsize = db_bar_size - norm_regsize; 271951ff1725SRam Amrani 272051ff1725SRam Amrani /* Check that the normal and PWM sizes are valid */ 272151ff1725SRam Amrani if (db_bar_size < norm_regsize) { 272251ff1725SRam Amrani DP_ERR(p_hwfn->cdev, 272351ff1725SRam Amrani "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n", 272451ff1725SRam Amrani db_bar_size, norm_regsize); 272551ff1725SRam Amrani return -EINVAL; 272651ff1725SRam Amrani } 272751ff1725SRam Amrani 272851ff1725SRam Amrani if (pwm_regsize < QED_MIN_PWM_REGION) { 272951ff1725SRam Amrani DP_ERR(p_hwfn->cdev, 273051ff1725SRam Amrani "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n", 273151ff1725SRam Amrani pwm_regsize, 273251ff1725SRam Amrani QED_MIN_PWM_REGION, db_bar_size, norm_regsize); 273351ff1725SRam Amrani return -EINVAL; 273451ff1725SRam Amrani } 273551ff1725SRam Amrani 273651ff1725SRam Amrani /* Calculate number of DPIs */ 273751ff1725SRam Amrani roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode; 273851ff1725SRam Amrani if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) || 273951ff1725SRam Amrani ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) { 274051ff1725SRam Amrani /* Either EDPM is mandatory, or we are attempting to allocate a 274151ff1725SRam Amrani * WID per CPU. 274251ff1725SRam Amrani */ 2743c2dedf87SRam Amrani n_cpus = num_present_cpus(); 274451ff1725SRam Amrani rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 274551ff1725SRam Amrani } 274651ff1725SRam Amrani 274751ff1725SRam Amrani cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) || 274851ff1725SRam Amrani (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE); 274951ff1725SRam Amrani if (cond || p_hwfn->dcbx_no_edpm) { 275051ff1725SRam Amrani /* Either EDPM is disabled from user configuration, or it is 275151ff1725SRam Amrani * disabled via DCBx, or it is not mandatory and we failed to 275251ff1725SRam Amrani * allocated a WID per CPU. 275351ff1725SRam Amrani */ 275451ff1725SRam Amrani n_cpus = 1; 275551ff1725SRam Amrani rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 275651ff1725SRam Amrani 275751ff1725SRam Amrani if (cond) 275851ff1725SRam Amrani qed_rdma_dpm_bar(p_hwfn, p_ptt); 275951ff1725SRam Amrani } 276051ff1725SRam Amrani 276120b1bd96SRam Amrani p_hwfn->wid_count = (u16) n_cpus; 276220b1bd96SRam Amrani 276351ff1725SRam Amrani DP_INFO(p_hwfn, 2764a1b469b8SAriel Elior "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s, page_size=%lu\n", 276551ff1725SRam Amrani norm_regsize, 276651ff1725SRam Amrani pwm_regsize, 276751ff1725SRam Amrani p_hwfn->dpi_size, 276851ff1725SRam Amrani p_hwfn->dpi_count, 2769a1b469b8SAriel Elior (!qed_edpm_enabled(p_hwfn)) ? 2770a1b469b8SAriel Elior "disabled" : "enabled", PAGE_SIZE); 277151ff1725SRam Amrani 277251ff1725SRam Amrani if (rc) { 277351ff1725SRam Amrani DP_ERR(p_hwfn, 277451ff1725SRam Amrani "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n", 277551ff1725SRam Amrani p_hwfn->dpi_count, 277651ff1725SRam Amrani p_hwfn->pf_params.rdma_pf_params.min_dpis); 277751ff1725SRam Amrani return -EINVAL; 277851ff1725SRam Amrani } 277951ff1725SRam Amrani 278051ff1725SRam Amrani p_hwfn->dpi_start_offset = norm_regsize; 278151ff1725SRam Amrani 278251ff1725SRam Amrani /* DEMS size is configured log2 of DWORDs, hence the division by 4 */ 278351ff1725SRam Amrani pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4); 278451ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift); 278551ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1); 278651ff1725SRam Amrani 278751ff1725SRam Amrani return 0; 278851ff1725SRam Amrani } 278951ff1725SRam Amrani 2790fe56b9e6SYuval Mintz static int qed_hw_init_port(struct qed_hwfn *p_hwfn, 27911a635e48SYuval Mintz struct qed_ptt *p_ptt, int hw_mode) 2792fe56b9e6SYuval Mintz { 2793fc6575bcSMintz, Yuval int rc = 0; 2794fc6575bcSMintz, Yuval 279579284adeSMichal Kalderon /* In CMT the gate should be cleared by the 2nd hwfn */ 279679284adeSMichal Kalderon if (!QED_IS_CMT(p_hwfn->cdev) || !IS_LEAD_HWFN(p_hwfn)) 279779284adeSMichal Kalderon STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0); 279879284adeSMichal Kalderon 2799fc6575bcSMintz, Yuval rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode); 2800fc6575bcSMintz, Yuval if (rc) 2801fc6575bcSMintz, Yuval return rc; 2802fc6575bcSMintz, Yuval 2803fc6575bcSMintz, Yuval qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0); 2804fc6575bcSMintz, Yuval 2805fc6575bcSMintz, Yuval return 0; 2806fe56b9e6SYuval Mintz } 2807fe56b9e6SYuval Mintz 2808fe56b9e6SYuval Mintz static int qed_hw_init_pf(struct qed_hwfn *p_hwfn, 2809fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 281019968430SChopra, Manish struct qed_tunnel_info *p_tunn, 2811fe56b9e6SYuval Mintz int hw_mode, 2812fe56b9e6SYuval Mintz bool b_hw_start, 2813fe56b9e6SYuval Mintz enum qed_int_mode int_mode, 2814fe56b9e6SYuval Mintz bool allow_npar_tx_switch) 2815fe56b9e6SYuval Mintz { 2816fe56b9e6SYuval Mintz u8 rel_pf_id = p_hwfn->rel_pf_id; 2817fe56b9e6SYuval Mintz int rc = 0; 2818fe56b9e6SYuval Mintz 2819fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 2820fe56b9e6SYuval Mintz struct qed_mcp_function_info *p_info; 2821fe56b9e6SYuval Mintz 2822fe56b9e6SYuval Mintz p_info = &p_hwfn->mcp_info->func_info; 2823fe56b9e6SYuval Mintz if (p_info->bandwidth_min) 2824fe56b9e6SYuval Mintz p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min; 2825fe56b9e6SYuval Mintz 2826fe56b9e6SYuval Mintz /* Update rate limit once we'll actually have a link */ 28274b01e519SManish Chopra p_hwfn->qm_info.pf_rl = 100000; 2828fe56b9e6SYuval Mintz } 2829fe56b9e6SYuval Mintz 283015582962SRahul Verma qed_cxt_hw_init_pf(p_hwfn, p_ptt); 2831fe56b9e6SYuval Mintz 2832fe56b9e6SYuval Mintz qed_int_igu_init_rt(p_hwfn); 2833fe56b9e6SYuval Mintz 2834fe56b9e6SYuval Mintz /* Set VLAN in NIG if needed */ 28351a635e48SYuval Mintz if (hw_mode & BIT(MODE_MF_SD)) { 2836fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n"); 2837fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1); 2838fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET, 2839fe56b9e6SYuval Mintz p_hwfn->hw_info.ovlan); 2840cac6f691SSudarsana Reddy Kalluru 2841cac6f691SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 2842cac6f691SSudarsana Reddy Kalluru "Configuring LLH_FUNC_FILTER_HDR_SEL\n"); 2843cac6f691SSudarsana Reddy Kalluru STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET, 2844cac6f691SSudarsana Reddy Kalluru 1); 2845fe56b9e6SYuval Mintz } 2846fe56b9e6SYuval Mintz 2847fe56b9e6SYuval Mintz /* Enable classification by MAC if needed */ 28481a635e48SYuval Mintz if (hw_mode & BIT(MODE_MF_SI)) { 2849fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 2850fe56b9e6SYuval Mintz "Configuring TAGMAC_CLS_TYPE\n"); 2851fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, 2852fe56b9e6SYuval Mintz NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1); 2853fe56b9e6SYuval Mintz } 2854fe56b9e6SYuval Mintz 2855a2e7699eSTomer Tayar /* Protocol Configuration */ 2856dbb799c3SYuval Mintz STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 2857dbb799c3SYuval Mintz (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0); 28581e128c81SArun Easi STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 28591e128c81SArun Easi (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0); 2860fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0); 2861fe56b9e6SYuval Mintz 2862da090917STomer Tayar /* Sanity check before the PF init sequence that uses DMAE */ 2863da090917STomer Tayar rc = qed_dmae_sanity(p_hwfn, p_ptt, "pf_phase"); 2864da090917STomer Tayar if (rc) 2865da090917STomer Tayar return rc; 2866da090917STomer Tayar 2867fe56b9e6SYuval Mintz /* PF Init sequence */ 2868fe56b9e6SYuval Mintz rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode); 2869fe56b9e6SYuval Mintz if (rc) 2870fe56b9e6SYuval Mintz return rc; 2871fe56b9e6SYuval Mintz 2872fe56b9e6SYuval Mintz /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */ 2873fe56b9e6SYuval Mintz rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode); 2874fe56b9e6SYuval Mintz if (rc) 2875fe56b9e6SYuval Mintz return rc; 2876fe56b9e6SYuval Mintz 287730d5f858SMichal Kalderon qed_fw_overlay_init_ram(p_hwfn, p_ptt, p_hwfn->fw_overlay_mem); 287830d5f858SMichal Kalderon 2879fe56b9e6SYuval Mintz /* Pure runtime initializations - directly to the HW */ 2880fe56b9e6SYuval Mintz qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true); 2881fe56b9e6SYuval Mintz 288251ff1725SRam Amrani rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt); 288351ff1725SRam Amrani if (rc) 288451ff1725SRam Amrani return rc; 288551ff1725SRam Amrani 288679284adeSMichal Kalderon /* Use the leading hwfn since in CMT only NIG #0 is operational */ 288779284adeSMichal Kalderon if (IS_LEAD_HWFN(p_hwfn)) { 288879284adeSMichal Kalderon rc = qed_llh_hw_init_pf(p_hwfn, p_ptt); 288979284adeSMichal Kalderon if (rc) 289079284adeSMichal Kalderon return rc; 289179284adeSMichal Kalderon } 289279284adeSMichal Kalderon 2893fe56b9e6SYuval Mintz if (b_hw_start) { 2894fe56b9e6SYuval Mintz /* enable interrupts */ 2895fe56b9e6SYuval Mintz qed_int_igu_enable(p_hwfn, p_ptt, int_mode); 2896fe56b9e6SYuval Mintz 2897fe56b9e6SYuval Mintz /* send function start command */ 28984f64675fSManish Chopra rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn, 2899831bfb0eSYuval Mintz allow_npar_tx_switch); 29001e128c81SArun Easi if (rc) { 2901fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Function start ramrod failed\n"); 29021e128c81SArun Easi return rc; 29031e128c81SArun Easi } 29041e128c81SArun Easi if (p_hwfn->hw_info.personality == QED_PCI_FCOE) { 29051e128c81SArun Easi qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2)); 29061e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 29071e128c81SArun Easi PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST, 29081e128c81SArun Easi 0x100); 29091e128c81SArun Easi } 2910fe56b9e6SYuval Mintz } 2911fe56b9e6SYuval Mintz return rc; 2912fe56b9e6SYuval Mintz } 2913fe56b9e6SYuval Mintz 2914666db486STomer Tayar int qed_pglueb_set_pfid_enable(struct qed_hwfn *p_hwfn, 2915666db486STomer Tayar struct qed_ptt *p_ptt, bool b_enable) 2916fe56b9e6SYuval Mintz { 2917666db486STomer Tayar u32 delay_idx = 0, val, set_val = b_enable ? 1 : 0; 2918fe56b9e6SYuval Mintz 2919666db486STomer Tayar /* Configure the PF's internal FID_enable for master transactions */ 2920666db486STomer Tayar qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val); 2921fe56b9e6SYuval Mintz 2922666db486STomer Tayar /* Wait until value is set - try for 1 second every 50us */ 2923fe56b9e6SYuval Mintz for (delay_idx = 0; delay_idx < 20000; delay_idx++) { 2924fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, 2925fe56b9e6SYuval Mintz PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 2926fe56b9e6SYuval Mintz if (val == set_val) 2927fe56b9e6SYuval Mintz break; 2928fe56b9e6SYuval Mintz 2929fe56b9e6SYuval Mintz usleep_range(50, 60); 2930fe56b9e6SYuval Mintz } 2931fe56b9e6SYuval Mintz 2932fe56b9e6SYuval Mintz if (val != set_val) { 2933fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 2934fe56b9e6SYuval Mintz "PFID_ENABLE_MASTER wasn't changed after a second\n"); 2935fe56b9e6SYuval Mintz return -EAGAIN; 2936fe56b9e6SYuval Mintz } 2937fe56b9e6SYuval Mintz 2938fe56b9e6SYuval Mintz return 0; 2939fe56b9e6SYuval Mintz } 2940fe56b9e6SYuval Mintz 2941fe56b9e6SYuval Mintz static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn, 2942fe56b9e6SYuval Mintz struct qed_ptt *p_main_ptt) 2943fe56b9e6SYuval Mintz { 2944fe56b9e6SYuval Mintz /* Read shadow of current MFW mailbox */ 2945fe56b9e6SYuval Mintz qed_mcp_read_mb(p_hwfn, p_main_ptt); 2946fe56b9e6SYuval Mintz memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 29471a635e48SYuval Mintz p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length); 2948fe56b9e6SYuval Mintz } 2949fe56b9e6SYuval Mintz 29505d24bcf1STomer Tayar static void 29515d24bcf1STomer Tayar qed_fill_load_req_params(struct qed_load_req_params *p_load_req, 29525d24bcf1STomer Tayar struct qed_drv_load_params *p_drv_load) 29535d24bcf1STomer Tayar { 29545d24bcf1STomer Tayar memset(p_load_req, 0, sizeof(*p_load_req)); 29555d24bcf1STomer Tayar 29565d24bcf1STomer Tayar p_load_req->drv_role = p_drv_load->is_crash_kernel ? 29575d24bcf1STomer Tayar QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS; 29585d24bcf1STomer Tayar p_load_req->timeout_val = p_drv_load->mfw_timeout_val; 29595d24bcf1STomer Tayar p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset; 29605d24bcf1STomer Tayar p_load_req->override_force_load = p_drv_load->override_force_load; 29615d24bcf1STomer Tayar } 29625d24bcf1STomer Tayar 2963eaf3c0c6SChopra, Manish static int qed_vf_start(struct qed_hwfn *p_hwfn, 2964eaf3c0c6SChopra, Manish struct qed_hw_init_params *p_params) 2965eaf3c0c6SChopra, Manish { 2966eaf3c0c6SChopra, Manish if (p_params->p_tunn) { 2967eaf3c0c6SChopra, Manish qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn); 2968eaf3c0c6SChopra, Manish qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn); 2969eaf3c0c6SChopra, Manish } 2970eaf3c0c6SChopra, Manish 2971c7281d59SGustavo A. R. Silva p_hwfn->b_int_enabled = true; 2972eaf3c0c6SChopra, Manish 2973eaf3c0c6SChopra, Manish return 0; 2974eaf3c0c6SChopra, Manish } 2975eaf3c0c6SChopra, Manish 2976666db486STomer Tayar static void qed_pglueb_clear_err(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2977666db486STomer Tayar { 2978666db486STomer Tayar qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 2979666db486STomer Tayar BIT(p_hwfn->abs_pf_id)); 2980666db486STomer Tayar } 2981666db486STomer Tayar 2982c0c2d0b4SMintz, Yuval int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params) 2983fe56b9e6SYuval Mintz { 29845d24bcf1STomer Tayar struct qed_load_req_params load_req_params; 298550fdf601SSudarsana Reddy Kalluru u32 load_code, resp, param, drv_mb_param; 29860fefbfbaSSudarsana Kalluru bool b_default_mtu = true; 29870fefbfbaSSudarsana Kalluru struct qed_hwfn *p_hwfn; 298830d5f858SMichal Kalderon const u32 *fw_overlays; 298930d5f858SMichal Kalderon u32 fw_overlays_len; 2990cac6f691SSudarsana Reddy Kalluru u16 ether_type; 299130d5f858SMichal Kalderon int rc = 0, i; 2992fe56b9e6SYuval Mintz 2993c0c2d0b4SMintz, Yuval if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) { 2994bb13ace7SSudarsana Reddy Kalluru DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n"); 2995bb13ace7SSudarsana Reddy Kalluru return -EINVAL; 2996bb13ace7SSudarsana Reddy Kalluru } 2997bb13ace7SSudarsana Reddy Kalluru 29981408cc1fSYuval Mintz if (IS_PF(cdev)) { 2999c0c2d0b4SMintz, Yuval rc = qed_init_fw_data(cdev, p_params->bin_fw_data); 30001a635e48SYuval Mintz if (rc) 3001fe56b9e6SYuval Mintz return rc; 30021408cc1fSYuval Mintz } 3003fe56b9e6SYuval Mintz 3004fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 3005666db486STomer Tayar p_hwfn = &cdev->hwfns[i]; 3006fe56b9e6SYuval Mintz 30070fefbfbaSSudarsana Kalluru /* If management didn't provide a default, set one of our own */ 30080fefbfbaSSudarsana Kalluru if (!p_hwfn->hw_info.mtu) { 30090fefbfbaSSudarsana Kalluru p_hwfn->hw_info.mtu = 1500; 30100fefbfbaSSudarsana Kalluru b_default_mtu = false; 30110fefbfbaSSudarsana Kalluru } 30120fefbfbaSSudarsana Kalluru 30131408cc1fSYuval Mintz if (IS_VF(cdev)) { 3014eaf3c0c6SChopra, Manish qed_vf_start(p_hwfn, p_params); 30151408cc1fSYuval Mintz continue; 30161408cc1fSYuval Mintz } 30171408cc1fSYuval Mintz 30189c79ddaaSMintz, Yuval rc = qed_calc_hw_mode(p_hwfn); 30199c79ddaaSMintz, Yuval if (rc) 30209c79ddaaSMintz, Yuval return rc; 3021fe56b9e6SYuval Mintz 3022cac6f691SSudarsana Reddy Kalluru if (IS_PF(cdev) && (test_bit(QED_MF_8021Q_TAGGING, 3023cac6f691SSudarsana Reddy Kalluru &cdev->mf_bits) || 3024cac6f691SSudarsana Reddy Kalluru test_bit(QED_MF_8021AD_TAGGING, 3025cac6f691SSudarsana Reddy Kalluru &cdev->mf_bits))) { 3026cac6f691SSudarsana Reddy Kalluru if (test_bit(QED_MF_8021Q_TAGGING, &cdev->mf_bits)) 3027cac6f691SSudarsana Reddy Kalluru ether_type = ETH_P_8021Q; 3028cac6f691SSudarsana Reddy Kalluru else 3029cac6f691SSudarsana Reddy Kalluru ether_type = ETH_P_8021AD; 3030b51bdfb9SSudarsana Reddy Kalluru STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET, 3031cac6f691SSudarsana Reddy Kalluru ether_type); 3032b51bdfb9SSudarsana Reddy Kalluru STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET, 3033cac6f691SSudarsana Reddy Kalluru ether_type); 3034b51bdfb9SSudarsana Reddy Kalluru STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET, 3035cac6f691SSudarsana Reddy Kalluru ether_type); 3036b51bdfb9SSudarsana Reddy Kalluru STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET, 3037cac6f691SSudarsana Reddy Kalluru ether_type); 3038b51bdfb9SSudarsana Reddy Kalluru } 3039b51bdfb9SSudarsana Reddy Kalluru 30405d24bcf1STomer Tayar qed_fill_load_req_params(&load_req_params, 30415d24bcf1STomer Tayar p_params->p_drv_load_params); 30425d24bcf1STomer Tayar rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, 30435d24bcf1STomer Tayar &load_req_params); 3044fe56b9e6SYuval Mintz if (rc) { 30455d24bcf1STomer Tayar DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n"); 3046fe56b9e6SYuval Mintz return rc; 3047fe56b9e6SYuval Mintz } 3048fe56b9e6SYuval Mintz 30495d24bcf1STomer Tayar load_code = load_req_params.load_code; 3050fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 30515d24bcf1STomer Tayar "Load request was sent. Load code: 0x%x\n", 30525d24bcf1STomer Tayar load_code); 30535d24bcf1STomer Tayar 305464515dc8STomer Tayar /* Only relevant for recovery: 305564515dc8STomer Tayar * Clear the indication after LOAD_REQ is responded by the MFW. 305664515dc8STomer Tayar */ 305764515dc8STomer Tayar cdev->recov_in_prog = false; 305864515dc8STomer Tayar 3059645874e5SSudarsana Reddy Kalluru qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt); 3060645874e5SSudarsana Reddy Kalluru 30615d24bcf1STomer Tayar qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt); 3062fe56b9e6SYuval Mintz 3063666db486STomer Tayar /* Clean up chip from previous driver if such remains exist. 3064666db486STomer Tayar * This is not needed when the PF is the first one on the 3065666db486STomer Tayar * engine, since afterwards we are going to init the FW. 3066666db486STomer Tayar */ 3067666db486STomer Tayar if (load_code != FW_MSG_CODE_DRV_LOAD_ENGINE) { 3068666db486STomer Tayar rc = qed_final_cleanup(p_hwfn, p_hwfn->p_main_ptt, 3069666db486STomer Tayar p_hwfn->rel_pf_id, false); 3070666db486STomer Tayar if (rc) { 30712ec276d5SIgor Russkikh qed_hw_err_notify(p_hwfn, p_hwfn->p_main_ptt, 30722ec276d5SIgor Russkikh QED_HW_ERR_RAMROD_FAIL, 30732ec276d5SIgor Russkikh "Final cleanup failed\n"); 3074666db486STomer Tayar goto load_err; 3075666db486STomer Tayar } 3076666db486STomer Tayar } 3077666db486STomer Tayar 3078666db486STomer Tayar /* Log and clear previous pglue_b errors if such exist */ 3079666db486STomer Tayar qed_pglueb_rbc_attn_handler(p_hwfn, p_hwfn->p_main_ptt); 3080666db486STomer Tayar 3081666db486STomer Tayar /* Enable the PF's internal FID_enable in the PXP */ 3082666db486STomer Tayar rc = qed_pglueb_set_pfid_enable(p_hwfn, p_hwfn->p_main_ptt, 3083666db486STomer Tayar true); 3084666db486STomer Tayar if (rc) 3085666db486STomer Tayar goto load_err; 3086666db486STomer Tayar 3087666db486STomer Tayar /* Clear the pglue_b was_error indication. 3088666db486STomer Tayar * In E4 it must be done after the BME and the internal 3089666db486STomer Tayar * FID_enable for the PF are set, since VDMs may cause the 3090666db486STomer Tayar * indication to be set again. 3091666db486STomer Tayar */ 3092666db486STomer Tayar qed_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt); 3093fe56b9e6SYuval Mintz 309430d5f858SMichal Kalderon fw_overlays = cdev->fw_data->fw_overlays; 309530d5f858SMichal Kalderon fw_overlays_len = cdev->fw_data->fw_overlays_len; 309630d5f858SMichal Kalderon p_hwfn->fw_overlay_mem = 309730d5f858SMichal Kalderon qed_fw_overlay_mem_alloc(p_hwfn, fw_overlays, 309830d5f858SMichal Kalderon fw_overlays_len); 309930d5f858SMichal Kalderon if (!p_hwfn->fw_overlay_mem) { 310030d5f858SMichal Kalderon DP_NOTICE(p_hwfn, 310130d5f858SMichal Kalderon "Failed to allocate fw overlay memory\n"); 3102d32a06f5SDan Carpenter rc = -ENOMEM; 310330d5f858SMichal Kalderon goto load_err; 310430d5f858SMichal Kalderon } 310530d5f858SMichal Kalderon 3106fe56b9e6SYuval Mintz switch (load_code) { 3107fe56b9e6SYuval Mintz case FW_MSG_CODE_DRV_LOAD_ENGINE: 3108fe56b9e6SYuval Mintz rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt, 3109fe56b9e6SYuval Mintz p_hwfn->hw_info.hw_mode); 3110fe56b9e6SYuval Mintz if (rc) 3111fe56b9e6SYuval Mintz break; 311253a42286SGustavo A. R. Silva /* Fall through */ 3113fe56b9e6SYuval Mintz case FW_MSG_CODE_DRV_LOAD_PORT: 3114fe56b9e6SYuval Mintz rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt, 3115fe56b9e6SYuval Mintz p_hwfn->hw_info.hw_mode); 3116fe56b9e6SYuval Mintz if (rc) 3117fe56b9e6SYuval Mintz break; 3118fe56b9e6SYuval Mintz 311953a42286SGustavo A. R. Silva /* Fall through */ 3120fe56b9e6SYuval Mintz case FW_MSG_CODE_DRV_LOAD_FUNCTION: 3121fe56b9e6SYuval Mintz rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt, 3122c0c2d0b4SMintz, Yuval p_params->p_tunn, 3123c0c2d0b4SMintz, Yuval p_hwfn->hw_info.hw_mode, 3124c0c2d0b4SMintz, Yuval p_params->b_hw_start, 3125c0c2d0b4SMintz, Yuval p_params->int_mode, 3126c0c2d0b4SMintz, Yuval p_params->allow_npar_tx_switch); 3127fe56b9e6SYuval Mintz break; 3128fe56b9e6SYuval Mintz default: 3129c0c2d0b4SMintz, Yuval DP_NOTICE(p_hwfn, 3130c0c2d0b4SMintz, Yuval "Unexpected load code [0x%08x]", load_code); 3131fe56b9e6SYuval Mintz rc = -EINVAL; 3132fe56b9e6SYuval Mintz break; 3133fe56b9e6SYuval Mintz } 3134fe56b9e6SYuval Mintz 3135666db486STomer Tayar if (rc) { 3136fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 3137fe56b9e6SYuval Mintz "init phase failed for loadcode 0x%x (rc %d)\n", 3138fe56b9e6SYuval Mintz load_code, rc); 3139666db486STomer Tayar goto load_err; 3140fe56b9e6SYuval Mintz } 3141fe56b9e6SYuval Mintz 3142666db486STomer Tayar rc = qed_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt); 3143666db486STomer Tayar if (rc) 3144666db486STomer Tayar return rc; 3145fc561c8bSTomer Tayar 314639651abdSSudarsana Reddy Kalluru /* send DCBX attention request command */ 314739651abdSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, 314839651abdSSudarsana Reddy Kalluru QED_MSG_DCB, 314939651abdSSudarsana Reddy Kalluru "sending phony dcbx set command to trigger DCBx attention handling\n"); 3150666db486STomer Tayar rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 315139651abdSSudarsana Reddy Kalluru DRV_MSG_CODE_SET_DCBX, 315239651abdSSudarsana Reddy Kalluru 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT, 3153666db486STomer Tayar &resp, ¶m); 3154666db486STomer Tayar if (rc) { 315539651abdSSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 315639651abdSSudarsana Reddy Kalluru "Failed to send DCBX attention request\n"); 3157666db486STomer Tayar return rc; 315839651abdSSudarsana Reddy Kalluru } 315939651abdSSudarsana Reddy Kalluru 3160fe56b9e6SYuval Mintz p_hwfn->hw_init_done = true; 3161fe56b9e6SYuval Mintz } 3162fe56b9e6SYuval Mintz 31630fefbfbaSSudarsana Kalluru if (IS_PF(cdev)) { 31640fefbfbaSSudarsana Kalluru p_hwfn = QED_LEADING_HWFN(cdev); 316550fdf601SSudarsana Reddy Kalluru 316650fdf601SSudarsana Reddy Kalluru /* Get pre-negotiated values for stag, bandwidth etc. */ 316750fdf601SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, 316850fdf601SSudarsana Reddy Kalluru QED_MSG_SPQ, 316950fdf601SSudarsana Reddy Kalluru "Sending GET_OEM_UPDATES command to trigger stag/bandwidth attention handling\n"); 317050fdf601SSudarsana Reddy Kalluru drv_mb_param = 1 << DRV_MB_PARAM_DUMMY_OEM_UPDATES_OFFSET; 317150fdf601SSudarsana Reddy Kalluru rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 317250fdf601SSudarsana Reddy Kalluru DRV_MSG_CODE_GET_OEM_UPDATES, 317350fdf601SSudarsana Reddy Kalluru drv_mb_param, &resp, ¶m); 317450fdf601SSudarsana Reddy Kalluru if (rc) 317550fdf601SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 317650fdf601SSudarsana Reddy Kalluru "Failed to send GET_OEM_UPDATES attention request\n"); 317750fdf601SSudarsana Reddy Kalluru 31785d24bcf1STomer Tayar drv_mb_param = STORM_FW_VERSION; 31790fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 31800fefbfbaSSudarsana Kalluru DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER, 31810fefbfbaSSudarsana Kalluru drv_mb_param, &load_code, ¶m); 31820fefbfbaSSudarsana Kalluru if (rc) 31830fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, "Failed to update firmware version\n"); 31840fefbfbaSSudarsana Kalluru 31850fefbfbaSSudarsana Kalluru if (!b_default_mtu) { 31860fefbfbaSSudarsana Kalluru rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt, 31870fefbfbaSSudarsana Kalluru p_hwfn->hw_info.mtu); 31880fefbfbaSSudarsana Kalluru if (rc) 31890fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, 31900fefbfbaSSudarsana Kalluru "Failed to update default mtu\n"); 31910fefbfbaSSudarsana Kalluru } 31920fefbfbaSSudarsana Kalluru 31930fefbfbaSSudarsana Kalluru rc = qed_mcp_ov_update_driver_state(p_hwfn, 31940fefbfbaSSudarsana Kalluru p_hwfn->p_main_ptt, 31950fefbfbaSSudarsana Kalluru QED_OV_DRIVER_STATE_DISABLED); 31960fefbfbaSSudarsana Kalluru if (rc) 31970fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, "Failed to update driver state\n"); 31980fefbfbaSSudarsana Kalluru 31990fefbfbaSSudarsana Kalluru rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt, 3200538f8d00SSudarsana Reddy Kalluru QED_OV_ESWITCH_NONE); 32010fefbfbaSSudarsana Kalluru if (rc) 32020fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, "Failed to update eswitch mode\n"); 32030fefbfbaSSudarsana Kalluru } 32040fefbfbaSSudarsana Kalluru 3205fe56b9e6SYuval Mintz return 0; 3206666db486STomer Tayar 3207666db486STomer Tayar load_err: 3208666db486STomer Tayar /* The MFW load lock should be released also when initialization fails. 3209666db486STomer Tayar */ 3210666db486STomer Tayar qed_mcp_load_done(p_hwfn, p_hwfn->p_main_ptt); 3211666db486STomer Tayar return rc; 3212fe56b9e6SYuval Mintz } 3213fe56b9e6SYuval Mintz 3214fe56b9e6SYuval Mintz #define QED_HW_STOP_RETRY_LIMIT (10) 32151a635e48SYuval Mintz static void qed_hw_timers_stop(struct qed_dev *cdev, 32161a635e48SYuval Mintz struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 32178c925c44SYuval Mintz { 32188c925c44SYuval Mintz int i; 32198c925c44SYuval Mintz 32208c925c44SYuval Mintz /* close timers */ 32218c925c44SYuval Mintz qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0); 32228c925c44SYuval Mintz qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0); 32238c925c44SYuval Mintz 322464515dc8STomer Tayar if (cdev->recov_in_prog) 322564515dc8STomer Tayar return; 322664515dc8STomer Tayar 32278c925c44SYuval Mintz for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) { 32288c925c44SYuval Mintz if ((!qed_rd(p_hwfn, p_ptt, 32298c925c44SYuval Mintz TM_REG_PF_SCAN_ACTIVE_CONN)) && 32301a635e48SYuval Mintz (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK))) 32318c925c44SYuval Mintz break; 32328c925c44SYuval Mintz 32338c925c44SYuval Mintz /* Dependent on number of connection/tasks, possibly 32348c925c44SYuval Mintz * 1ms sleep is required between polls 32358c925c44SYuval Mintz */ 32368c925c44SYuval Mintz usleep_range(1000, 2000); 32378c925c44SYuval Mintz } 32388c925c44SYuval Mintz 32398c925c44SYuval Mintz if (i < QED_HW_STOP_RETRY_LIMIT) 32408c925c44SYuval Mintz return; 32418c925c44SYuval Mintz 32428c925c44SYuval Mintz DP_NOTICE(p_hwfn, 32438c925c44SYuval Mintz "Timers linear scans are not over [Connection %02x Tasks %02x]\n", 32448c925c44SYuval Mintz (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN), 32458c925c44SYuval Mintz (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)); 32468c925c44SYuval Mintz } 32478c925c44SYuval Mintz 32488c925c44SYuval Mintz void qed_hw_timers_stop_all(struct qed_dev *cdev) 32498c925c44SYuval Mintz { 32508c925c44SYuval Mintz int j; 32518c925c44SYuval Mintz 32528c925c44SYuval Mintz for_each_hwfn(cdev, j) { 32538c925c44SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 32548c925c44SYuval Mintz struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 32558c925c44SYuval Mintz 32568c925c44SYuval Mintz qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 32578c925c44SYuval Mintz } 32588c925c44SYuval Mintz } 32598c925c44SYuval Mintz 3260fe56b9e6SYuval Mintz int qed_hw_stop(struct qed_dev *cdev) 3261fe56b9e6SYuval Mintz { 32621226337aSTomer Tayar struct qed_hwfn *p_hwfn; 32631226337aSTomer Tayar struct qed_ptt *p_ptt; 32641226337aSTomer Tayar int rc, rc2 = 0; 32658c925c44SYuval Mintz int j; 3266fe56b9e6SYuval Mintz 3267fe56b9e6SYuval Mintz for_each_hwfn(cdev, j) { 32681226337aSTomer Tayar p_hwfn = &cdev->hwfns[j]; 32691226337aSTomer Tayar p_ptt = p_hwfn->p_main_ptt; 3270fe56b9e6SYuval Mintz 3271fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n"); 3272fe56b9e6SYuval Mintz 32731408cc1fSYuval Mintz if (IS_VF(cdev)) { 32740b55e27dSYuval Mintz qed_vf_pf_int_cleanup(p_hwfn); 32751226337aSTomer Tayar rc = qed_vf_pf_reset(p_hwfn); 32761226337aSTomer Tayar if (rc) { 32771226337aSTomer Tayar DP_NOTICE(p_hwfn, 32781226337aSTomer Tayar "qed_vf_pf_reset failed. rc = %d.\n", 32791226337aSTomer Tayar rc); 32801226337aSTomer Tayar rc2 = -EINVAL; 32811226337aSTomer Tayar } 32821408cc1fSYuval Mintz continue; 32831408cc1fSYuval Mintz } 32841408cc1fSYuval Mintz 3285fe56b9e6SYuval Mintz /* mark the hw as uninitialized... */ 3286fe56b9e6SYuval Mintz p_hwfn->hw_init_done = false; 3287fe56b9e6SYuval Mintz 32881226337aSTomer Tayar /* Send unload command to MCP */ 328964515dc8STomer Tayar if (!cdev->recov_in_prog) { 32901226337aSTomer Tayar rc = qed_mcp_unload_req(p_hwfn, p_ptt); 32911226337aSTomer Tayar if (rc) { 32928c925c44SYuval Mintz DP_NOTICE(p_hwfn, 32931226337aSTomer Tayar "Failed sending a UNLOAD_REQ command. rc = %d.\n", 32941226337aSTomer Tayar rc); 32951226337aSTomer Tayar rc2 = -EINVAL; 32961226337aSTomer Tayar } 329764515dc8STomer Tayar } 32981226337aSTomer Tayar 32991226337aSTomer Tayar qed_slowpath_irq_sync(p_hwfn); 33001226337aSTomer Tayar 33011226337aSTomer Tayar /* After this point no MFW attentions are expected, e.g. prevent 33021226337aSTomer Tayar * race between pf stop and dcbx pf update. 33031226337aSTomer Tayar */ 33041226337aSTomer Tayar rc = qed_sp_pf_stop(p_hwfn); 33051226337aSTomer Tayar if (rc) { 33061226337aSTomer Tayar DP_NOTICE(p_hwfn, 33071226337aSTomer Tayar "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n", 33081226337aSTomer Tayar rc); 33091226337aSTomer Tayar rc2 = -EINVAL; 33101226337aSTomer Tayar } 3311fe56b9e6SYuval Mintz 3312fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 3313fe56b9e6SYuval Mintz NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 3314fe56b9e6SYuval Mintz 3315fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 3316fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 3317fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 3318fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 3319fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 3320fe56b9e6SYuval Mintz 33218c925c44SYuval Mintz qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 3322fe56b9e6SYuval Mintz 3323fe56b9e6SYuval Mintz /* Disable Attention Generation */ 3324fe56b9e6SYuval Mintz qed_int_igu_disable_int(p_hwfn, p_ptt); 3325fe56b9e6SYuval Mintz 3326fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0); 3327fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0); 3328fe56b9e6SYuval Mintz 3329fe56b9e6SYuval Mintz qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true); 3330fe56b9e6SYuval Mintz 3331fe56b9e6SYuval Mintz /* Need to wait 1ms to guarantee SBs are cleared */ 3332fe56b9e6SYuval Mintz usleep_range(1000, 2000); 33331226337aSTomer Tayar 33341226337aSTomer Tayar /* Disable PF in HW blocks */ 33351226337aSTomer Tayar qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0); 33361226337aSTomer Tayar qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0); 33371226337aSTomer Tayar 333879284adeSMichal Kalderon if (IS_LEAD_HWFN(p_hwfn) && 333979284adeSMichal Kalderon test_bit(QED_MF_LLH_MAC_CLSS, &cdev->mf_bits) && 334079284adeSMichal Kalderon !QED_IS_FCOE_PERSONALITY(p_hwfn)) 334179284adeSMichal Kalderon qed_llh_remove_mac_filter(cdev, 0, 334279284adeSMichal Kalderon p_hwfn->hw_info.hw_mac_addr); 334379284adeSMichal Kalderon 334464515dc8STomer Tayar if (!cdev->recov_in_prog) { 334564515dc8STomer Tayar rc = qed_mcp_unload_done(p_hwfn, p_ptt); 33461226337aSTomer Tayar if (rc) { 33471226337aSTomer Tayar DP_NOTICE(p_hwfn, 33481226337aSTomer Tayar "Failed sending a UNLOAD_DONE command. rc = %d.\n", 33491226337aSTomer Tayar rc); 33501226337aSTomer Tayar rc2 = -EINVAL; 33511226337aSTomer Tayar } 3352fe56b9e6SYuval Mintz } 335364515dc8STomer Tayar } 3354fe56b9e6SYuval Mintz 335564515dc8STomer Tayar if (IS_PF(cdev) && !cdev->recov_in_prog) { 33561226337aSTomer Tayar p_hwfn = QED_LEADING_HWFN(cdev); 33571226337aSTomer Tayar p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt; 33581226337aSTomer Tayar 3359666db486STomer Tayar /* Clear the PF's internal FID_enable in the PXP. 3360666db486STomer Tayar * In CMT this should only be done for first hw-function, and 3361666db486STomer Tayar * only after all transactions have stopped for all active 3362666db486STomer Tayar * hw-functions. 3363fe56b9e6SYuval Mintz */ 3364666db486STomer Tayar rc = qed_pglueb_set_pfid_enable(p_hwfn, p_ptt, false); 33651226337aSTomer Tayar if (rc) { 33661226337aSTomer Tayar DP_NOTICE(p_hwfn, 3367666db486STomer Tayar "qed_pglueb_set_pfid_enable() failed. rc = %d.\n", 3368666db486STomer Tayar rc); 33691226337aSTomer Tayar rc2 = -EINVAL; 33701226337aSTomer Tayar } 33711408cc1fSYuval Mintz } 3372fe56b9e6SYuval Mintz 33731226337aSTomer Tayar return rc2; 3374fe56b9e6SYuval Mintz } 3375fe56b9e6SYuval Mintz 337615582962SRahul Verma int qed_hw_stop_fastpath(struct qed_dev *cdev) 3377cee4d264SManish Chopra { 33788c925c44SYuval Mintz int j; 3379cee4d264SManish Chopra 3380cee4d264SManish Chopra for_each_hwfn(cdev, j) { 3381cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 338215582962SRahul Verma struct qed_ptt *p_ptt; 3383cee4d264SManish Chopra 3384dacd88d6SYuval Mintz if (IS_VF(cdev)) { 3385dacd88d6SYuval Mintz qed_vf_pf_int_cleanup(p_hwfn); 3386dacd88d6SYuval Mintz continue; 3387dacd88d6SYuval Mintz } 338815582962SRahul Verma p_ptt = qed_ptt_acquire(p_hwfn); 338915582962SRahul Verma if (!p_ptt) 339015582962SRahul Verma return -EAGAIN; 3391dacd88d6SYuval Mintz 3392cee4d264SManish Chopra DP_VERBOSE(p_hwfn, 33931a635e48SYuval Mintz NETIF_MSG_IFDOWN, "Shutting down the fastpath\n"); 3394cee4d264SManish Chopra 3395cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, 3396cee4d264SManish Chopra NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 3397cee4d264SManish Chopra 3398cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 3399cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 3400cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 3401cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 3402cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 3403cee4d264SManish Chopra 3404cee4d264SManish Chopra qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false); 3405cee4d264SManish Chopra 3406cee4d264SManish Chopra /* Need to wait 1ms to guarantee SBs are cleared */ 3407cee4d264SManish Chopra usleep_range(1000, 2000); 340815582962SRahul Verma qed_ptt_release(p_hwfn, p_ptt); 3409cee4d264SManish Chopra } 3410cee4d264SManish Chopra 341115582962SRahul Verma return 0; 341215582962SRahul Verma } 341315582962SRahul Verma 341415582962SRahul Verma int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn) 3415cee4d264SManish Chopra { 341615582962SRahul Verma struct qed_ptt *p_ptt; 341715582962SRahul Verma 3418dacd88d6SYuval Mintz if (IS_VF(p_hwfn->cdev)) 341915582962SRahul Verma return 0; 342015582962SRahul Verma 342115582962SRahul Verma p_ptt = qed_ptt_acquire(p_hwfn); 342215582962SRahul Verma if (!p_ptt) 342315582962SRahul Verma return -EAGAIN; 3424dacd88d6SYuval Mintz 3425f855df22SMichal Kalderon if (p_hwfn->p_rdma_info && 3426291d57f6SMichal Kalderon p_hwfn->p_rdma_info->active && p_hwfn->b_rdma_enabled_in_prs) 3427f855df22SMichal Kalderon qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1); 3428f855df22SMichal Kalderon 3429cee4d264SManish Chopra /* Re-open incoming traffic */ 343015582962SRahul Verma qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0); 343115582962SRahul Verma qed_ptt_release(p_hwfn, p_ptt); 343215582962SRahul Verma 343315582962SRahul Verma return 0; 3434cee4d264SManish Chopra } 3435cee4d264SManish Chopra 3436fe56b9e6SYuval Mintz /* Free hwfn memory and resources acquired in hw_hwfn_prepare */ 3437fe56b9e6SYuval Mintz static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn) 3438fe56b9e6SYuval Mintz { 3439fe56b9e6SYuval Mintz qed_ptt_pool_free(p_hwfn); 3440fe56b9e6SYuval Mintz kfree(p_hwfn->hw_info.p_igu_info); 34413587cb87STomer Tayar p_hwfn->hw_info.p_igu_info = NULL; 3442fe56b9e6SYuval Mintz } 3443fe56b9e6SYuval Mintz 3444fe56b9e6SYuval Mintz /* Setup bar access */ 344512e09c69SYuval Mintz static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn) 3446fe56b9e6SYuval Mintz { 3447fe56b9e6SYuval Mintz /* clear indirect access */ 34489c79ddaaSMintz, Yuval if (QED_IS_AH(p_hwfn->cdev)) { 34499c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 34509c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0); 34519c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 34529c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0); 34539c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 34549c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0); 34559c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 34569c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0); 34579c79ddaaSMintz, Yuval } else { 34589c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 34599c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0); 34609c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 34619c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0); 34629c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 34639c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0); 34649c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 34659c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0); 34669c79ddaaSMintz, Yuval } 3467fe56b9e6SYuval Mintz 3468666db486STomer Tayar /* Clean previous pglue_b errors if such exist */ 3469666db486STomer Tayar qed_pglueb_clear_err(p_hwfn, p_hwfn->p_main_ptt); 3470fe56b9e6SYuval Mintz 3471fe56b9e6SYuval Mintz /* enable internal target-read */ 3472fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, 3473fe56b9e6SYuval Mintz PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 3474fe56b9e6SYuval Mintz } 3475fe56b9e6SYuval Mintz 3476fe56b9e6SYuval Mintz static void get_function_id(struct qed_hwfn *p_hwfn) 3477fe56b9e6SYuval Mintz { 3478fe56b9e6SYuval Mintz /* ME Register */ 34791a635e48SYuval Mintz p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn, 34801a635e48SYuval Mintz PXP_PF_ME_OPAQUE_ADDR); 3481fe56b9e6SYuval Mintz 3482fe56b9e6SYuval Mintz p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); 3483fe56b9e6SYuval Mintz 3484fe56b9e6SYuval Mintz p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf; 3485fe56b9e6SYuval Mintz p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 3486fe56b9e6SYuval Mintz PXP_CONCRETE_FID_PFID); 3487fe56b9e6SYuval Mintz p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 3488fe56b9e6SYuval Mintz PXP_CONCRETE_FID_PORT); 3489525ef5c0SYuval Mintz 3490525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, 3491525ef5c0SYuval Mintz "Read ME register: Concrete 0x%08x Opaque 0x%04x\n", 3492525ef5c0SYuval Mintz p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid); 3493fe56b9e6SYuval Mintz } 3494fe56b9e6SYuval Mintz 349525c089d7SYuval Mintz static void qed_hw_set_feat(struct qed_hwfn *p_hwfn) 349625c089d7SYuval Mintz { 349725c089d7SYuval Mintz u32 *feat_num = p_hwfn->hw_info.feat_num; 3498ebbdcc66SMintz, Yuval struct qed_sb_cnt_info sb_cnt; 3499810bb1f0SMintz, Yuval u32 non_l2_sbs = 0; 350025c089d7SYuval Mintz 3501ebbdcc66SMintz, Yuval memset(&sb_cnt, 0, sizeof(sb_cnt)); 3502ebbdcc66SMintz, Yuval qed_int_get_num_sbs(p_hwfn, &sb_cnt); 3503ebbdcc66SMintz, Yuval 35040189efb8SYuval Mintz if (IS_ENABLED(CONFIG_QED_RDMA) && 3505c851a9dcSKalderon, Michal QED_IS_RDMA_PERSONALITY(p_hwfn)) { 35060189efb8SYuval Mintz /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide 35070189efb8SYuval Mintz * the status blocks equally between L2 / RoCE but with 35080189efb8SYuval Mintz * consideration as to how many l2 queues / cnqs we have. 350951ff1725SRam Amrani */ 351051ff1725SRam Amrani feat_num[QED_RDMA_CNQ] = 3511ebbdcc66SMintz, Yuval min_t(u32, sb_cnt.cnt / 2, 351251ff1725SRam Amrani RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM)); 3513810bb1f0SMintz, Yuval 3514810bb1f0SMintz, Yuval non_l2_sbs = feat_num[QED_RDMA_CNQ]; 351551ff1725SRam Amrani } 3516c851a9dcSKalderon, Michal if (QED_IS_L2_PERSONALITY(p_hwfn)) { 3517dec26533SMintz, Yuval /* Start by allocating VF queues, then PF's */ 3518dec26533SMintz, Yuval feat_num[QED_VF_L2_QUE] = min_t(u32, 3519dec26533SMintz, Yuval RESC_NUM(p_hwfn, QED_L2_QUEUE), 3520ebbdcc66SMintz, Yuval sb_cnt.iov_cnt); 3521810bb1f0SMintz, Yuval feat_num[QED_PF_L2_QUE] = min_t(u32, 3522ebbdcc66SMintz, Yuval sb_cnt.cnt - non_l2_sbs, 3523dec26533SMintz, Yuval RESC_NUM(p_hwfn, 3524dec26533SMintz, Yuval QED_L2_QUEUE) - 3525dec26533SMintz, Yuval FEAT_NUM(p_hwfn, 3526dec26533SMintz, Yuval QED_VF_L2_QUE)); 3527dec26533SMintz, Yuval } 35285a1f965aSMintz, Yuval 3529c851a9dcSKalderon, Michal if (QED_IS_FCOE_PERSONALITY(p_hwfn)) 35303c5da942SMintz, Yuval feat_num[QED_FCOE_CQ] = min_t(u32, sb_cnt.cnt, 35313c5da942SMintz, Yuval RESC_NUM(p_hwfn, 35323c5da942SMintz, Yuval QED_CMDQS_CQS)); 35333c5da942SMintz, Yuval 3534c851a9dcSKalderon, Michal if (QED_IS_ISCSI_PERSONALITY(p_hwfn)) 3535ebbdcc66SMintz, Yuval feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt, 353608737a3fSMintz, Yuval RESC_NUM(p_hwfn, 353708737a3fSMintz, Yuval QED_CMDQS_CQS)); 35385a1f965aSMintz, Yuval DP_VERBOSE(p_hwfn, 35395a1f965aSMintz, Yuval NETIF_MSG_PROBE, 35403c5da942SMintz, Yuval "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d #SBS=%d\n", 35415a1f965aSMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE), 35425a1f965aSMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE), 35435a1f965aSMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ), 35443c5da942SMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ), 354508737a3fSMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ), 3546ebbdcc66SMintz, Yuval (int)sb_cnt.cnt); 354725c089d7SYuval Mintz } 354825c089d7SYuval Mintz 35499c8517c4STomer Tayar const char *qed_hw_get_resc_name(enum qed_resources res_id) 35502edbff8dSTomer Tayar { 35512edbff8dSTomer Tayar switch (res_id) { 35522edbff8dSTomer Tayar case QED_L2_QUEUE: 35532edbff8dSTomer Tayar return "L2_QUEUE"; 35542edbff8dSTomer Tayar case QED_VPORT: 35552edbff8dSTomer Tayar return "VPORT"; 35562edbff8dSTomer Tayar case QED_RSS_ENG: 35572edbff8dSTomer Tayar return "RSS_ENG"; 35582edbff8dSTomer Tayar case QED_PQ: 35592edbff8dSTomer Tayar return "PQ"; 35602edbff8dSTomer Tayar case QED_RL: 35612edbff8dSTomer Tayar return "RL"; 35622edbff8dSTomer Tayar case QED_MAC: 35632edbff8dSTomer Tayar return "MAC"; 35642edbff8dSTomer Tayar case QED_VLAN: 35652edbff8dSTomer Tayar return "VLAN"; 35662edbff8dSTomer Tayar case QED_RDMA_CNQ_RAM: 35672edbff8dSTomer Tayar return "RDMA_CNQ_RAM"; 35682edbff8dSTomer Tayar case QED_ILT: 35692edbff8dSTomer Tayar return "ILT"; 3570997af5dfSMichal Kalderon case QED_LL2_RAM_QUEUE: 3571997af5dfSMichal Kalderon return "LL2_RAM_QUEUE"; 3572997af5dfSMichal Kalderon case QED_LL2_CTX_QUEUE: 3573997af5dfSMichal Kalderon return "LL2_CTX_QUEUE"; 35742edbff8dSTomer Tayar case QED_CMDQS_CQS: 35752edbff8dSTomer Tayar return "CMDQS_CQS"; 35762edbff8dSTomer Tayar case QED_RDMA_STATS_QUEUE: 35772edbff8dSTomer Tayar return "RDMA_STATS_QUEUE"; 35789c8517c4STomer Tayar case QED_BDQ: 35799c8517c4STomer Tayar return "BDQ"; 35809c8517c4STomer Tayar case QED_SB: 35819c8517c4STomer Tayar return "SB"; 35822edbff8dSTomer Tayar default: 35832edbff8dSTomer Tayar return "UNKNOWN_RESOURCE"; 35842edbff8dSTomer Tayar } 35852edbff8dSTomer Tayar } 35862edbff8dSTomer Tayar 35879c8517c4STomer Tayar static int 35889c8517c4STomer Tayar __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, 35899c8517c4STomer Tayar struct qed_ptt *p_ptt, 35909c8517c4STomer Tayar enum qed_resources res_id, 35919c8517c4STomer Tayar u32 resc_max_val, u32 *p_mcp_resp) 35929c8517c4STomer Tayar { 35939c8517c4STomer Tayar int rc; 35949c8517c4STomer Tayar 35959c8517c4STomer Tayar rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id, 35969c8517c4STomer Tayar resc_max_val, p_mcp_resp); 35979c8517c4STomer Tayar if (rc) { 35989c8517c4STomer Tayar DP_NOTICE(p_hwfn, 35999c8517c4STomer Tayar "MFW response failure for a max value setting of resource %d [%s]\n", 36009c8517c4STomer Tayar res_id, qed_hw_get_resc_name(res_id)); 36019c8517c4STomer Tayar return rc; 36029c8517c4STomer Tayar } 36039c8517c4STomer Tayar 36049c8517c4STomer Tayar if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) 36059c8517c4STomer Tayar DP_INFO(p_hwfn, 36069c8517c4STomer Tayar "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n", 36079c8517c4STomer Tayar res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp); 36089c8517c4STomer Tayar 36099c8517c4STomer Tayar return 0; 36109c8517c4STomer Tayar } 36119c8517c4STomer Tayar 36121392d19fSMichal Kalderon static u32 qed_hsi_def_val[][MAX_CHIP_IDS] = { 36131392d19fSMichal Kalderon {MAX_NUM_VFS_BB, MAX_NUM_VFS_K2}, 36141392d19fSMichal Kalderon {MAX_NUM_L2_QUEUES_BB, MAX_NUM_L2_QUEUES_K2}, 36151392d19fSMichal Kalderon {MAX_NUM_PORTS_BB, MAX_NUM_PORTS_K2}, 36161392d19fSMichal Kalderon {MAX_SB_PER_PATH_BB, MAX_SB_PER_PATH_K2,}, 36171392d19fSMichal Kalderon {MAX_NUM_PFS_BB, MAX_NUM_PFS_K2}, 36181392d19fSMichal Kalderon {MAX_NUM_VPORTS_BB, MAX_NUM_VPORTS_K2}, 36191392d19fSMichal Kalderon {ETH_RSS_ENGINE_NUM_BB, ETH_RSS_ENGINE_NUM_K2}, 36201392d19fSMichal Kalderon {MAX_QM_TX_QUEUES_BB, MAX_QM_TX_QUEUES_K2}, 36211392d19fSMichal Kalderon {PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2}, 36221392d19fSMichal Kalderon {RDMA_NUM_STATISTIC_COUNTERS_BB, RDMA_NUM_STATISTIC_COUNTERS_K2}, 36231392d19fSMichal Kalderon {MAX_QM_GLOBAL_RLS, MAX_QM_GLOBAL_RLS}, 36241392d19fSMichal Kalderon {PBF_MAX_CMD_LINES, PBF_MAX_CMD_LINES}, 36251392d19fSMichal Kalderon {BTB_MAX_BLOCKS_BB, BTB_MAX_BLOCKS_K2}, 36261392d19fSMichal Kalderon }; 36271392d19fSMichal Kalderon 36281392d19fSMichal Kalderon u32 qed_get_hsi_def_val(struct qed_dev *cdev, enum qed_hsi_def_type type) 36291392d19fSMichal Kalderon { 36301392d19fSMichal Kalderon enum chip_ids chip_id = QED_IS_BB(cdev) ? CHIP_BB : CHIP_K2; 36311392d19fSMichal Kalderon 36321392d19fSMichal Kalderon if (type >= QED_NUM_HSI_DEFS) { 36331392d19fSMichal Kalderon DP_ERR(cdev, "Unexpected HSI definition type [%d]\n", type); 36341392d19fSMichal Kalderon return 0; 36351392d19fSMichal Kalderon } 36361392d19fSMichal Kalderon 36371392d19fSMichal Kalderon return qed_hsi_def_val[type][chip_id]; 36381392d19fSMichal Kalderon } 36399c8517c4STomer Tayar static int 36409c8517c4STomer Tayar qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 36419c8517c4STomer Tayar { 36429c8517c4STomer Tayar u32 resc_max_val, mcp_resp; 36439c8517c4STomer Tayar u8 res_id; 36449c8517c4STomer Tayar int rc; 36459c8517c4STomer Tayar for (res_id = 0; res_id < QED_MAX_RESC; res_id++) { 36469c8517c4STomer Tayar switch (res_id) { 3647997af5dfSMichal Kalderon case QED_LL2_RAM_QUEUE: 3648997af5dfSMichal Kalderon resc_max_val = MAX_NUM_LL2_RX_RAM_QUEUES; 3649997af5dfSMichal Kalderon break; 3650997af5dfSMichal Kalderon case QED_LL2_CTX_QUEUE: 3651997af5dfSMichal Kalderon resc_max_val = MAX_NUM_LL2_RX_CTX_QUEUES; 36529c8517c4STomer Tayar break; 36539c8517c4STomer Tayar case QED_RDMA_CNQ_RAM: 36549c8517c4STomer Tayar /* No need for a case for QED_CMDQS_CQS since 36559c8517c4STomer Tayar * CNQ/CMDQS are the same resource. 36569c8517c4STomer Tayar */ 3657da090917STomer Tayar resc_max_val = NUM_OF_GLOBAL_QUEUES; 36589c8517c4STomer Tayar break; 36599c8517c4STomer Tayar case QED_RDMA_STATS_QUEUE: 36601392d19fSMichal Kalderon resc_max_val = 36611392d19fSMichal Kalderon NUM_OF_RDMA_STATISTIC_COUNTERS(p_hwfn->cdev); 36629c8517c4STomer Tayar break; 36639c8517c4STomer Tayar case QED_BDQ: 36649c8517c4STomer Tayar resc_max_val = BDQ_NUM_RESOURCES; 36659c8517c4STomer Tayar break; 36669c8517c4STomer Tayar default: 36679c8517c4STomer Tayar continue; 36689c8517c4STomer Tayar } 36699c8517c4STomer Tayar 36709c8517c4STomer Tayar rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id, 36719c8517c4STomer Tayar resc_max_val, &mcp_resp); 36729c8517c4STomer Tayar if (rc) 36739c8517c4STomer Tayar return rc; 36749c8517c4STomer Tayar 36759c8517c4STomer Tayar /* There's no point to continue to the next resource if the 36769c8517c4STomer Tayar * command is not supported by the MFW. 36779c8517c4STomer Tayar * We do continue if the command is supported but the resource 36789c8517c4STomer Tayar * is unknown to the MFW. Such a resource will be later 36799c8517c4STomer Tayar * configured with the default allocation values. 36809c8517c4STomer Tayar */ 36819c8517c4STomer Tayar if (mcp_resp == FW_MSG_CODE_UNSUPPORTED) 36829c8517c4STomer Tayar return -EINVAL; 36839c8517c4STomer Tayar } 36849c8517c4STomer Tayar 36859c8517c4STomer Tayar return 0; 36869c8517c4STomer Tayar } 36879c8517c4STomer Tayar 36889c8517c4STomer Tayar static 36899c8517c4STomer Tayar int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn, 36909c8517c4STomer Tayar enum qed_resources res_id, 36919c8517c4STomer Tayar u32 *p_resc_num, u32 *p_resc_start) 36929c8517c4STomer Tayar { 36939c8517c4STomer Tayar u8 num_funcs = p_hwfn->num_funcs_on_engine; 36941392d19fSMichal Kalderon struct qed_dev *cdev = p_hwfn->cdev; 36959c8517c4STomer Tayar 36969c8517c4STomer Tayar switch (res_id) { 36979c8517c4STomer Tayar case QED_L2_QUEUE: 36981392d19fSMichal Kalderon *p_resc_num = NUM_OF_L2_QUEUES(cdev) / num_funcs; 36999c8517c4STomer Tayar break; 37009c8517c4STomer Tayar case QED_VPORT: 37011392d19fSMichal Kalderon *p_resc_num = NUM_OF_VPORTS(cdev) / num_funcs; 37029c8517c4STomer Tayar break; 37039c8517c4STomer Tayar case QED_RSS_ENG: 37041392d19fSMichal Kalderon *p_resc_num = NUM_OF_RSS_ENGINES(cdev) / num_funcs; 37059c8517c4STomer Tayar break; 37069c8517c4STomer Tayar case QED_PQ: 37071392d19fSMichal Kalderon *p_resc_num = NUM_OF_QM_TX_QUEUES(cdev) / num_funcs; 37089c8517c4STomer Tayar *p_resc_num &= ~0x7; /* The granularity of the PQs is 8 */ 37099c8517c4STomer Tayar break; 37109c8517c4STomer Tayar case QED_RL: 37111392d19fSMichal Kalderon *p_resc_num = NUM_OF_QM_GLOBAL_RLS(cdev) / num_funcs; 37129c8517c4STomer Tayar break; 37139c8517c4STomer Tayar case QED_MAC: 37149c8517c4STomer Tayar case QED_VLAN: 37159c8517c4STomer Tayar /* Each VFC resource can accommodate both a MAC and a VLAN */ 37169c8517c4STomer Tayar *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs; 37179c8517c4STomer Tayar break; 37189c8517c4STomer Tayar case QED_ILT: 37191392d19fSMichal Kalderon *p_resc_num = NUM_OF_PXP_ILT_RECORDS(cdev) / num_funcs; 37209c8517c4STomer Tayar break; 3721997af5dfSMichal Kalderon case QED_LL2_RAM_QUEUE: 3722997af5dfSMichal Kalderon *p_resc_num = MAX_NUM_LL2_RX_RAM_QUEUES / num_funcs; 3723997af5dfSMichal Kalderon break; 3724997af5dfSMichal Kalderon case QED_LL2_CTX_QUEUE: 3725997af5dfSMichal Kalderon *p_resc_num = MAX_NUM_LL2_RX_CTX_QUEUES / num_funcs; 37269c8517c4STomer Tayar break; 37279c8517c4STomer Tayar case QED_RDMA_CNQ_RAM: 37289c8517c4STomer Tayar case QED_CMDQS_CQS: 37299c8517c4STomer Tayar /* CNQ/CMDQS are the same resource */ 3730da090917STomer Tayar *p_resc_num = NUM_OF_GLOBAL_QUEUES / num_funcs; 37319c8517c4STomer Tayar break; 37329c8517c4STomer Tayar case QED_RDMA_STATS_QUEUE: 37331392d19fSMichal Kalderon *p_resc_num = NUM_OF_RDMA_STATISTIC_COUNTERS(cdev) / num_funcs; 37349c8517c4STomer Tayar break; 37359c8517c4STomer Tayar case QED_BDQ: 37369c8517c4STomer Tayar if (p_hwfn->hw_info.personality != QED_PCI_ISCSI && 37379c8517c4STomer Tayar p_hwfn->hw_info.personality != QED_PCI_FCOE) 37389c8517c4STomer Tayar *p_resc_num = 0; 37399c8517c4STomer Tayar else 37409c8517c4STomer Tayar *p_resc_num = 1; 37419c8517c4STomer Tayar break; 37429c8517c4STomer Tayar case QED_SB: 3743ebbdcc66SMintz, Yuval /* Since we want its value to reflect whether MFW supports 3744ebbdcc66SMintz, Yuval * the new scheme, have a default of 0. 3745ebbdcc66SMintz, Yuval */ 3746ebbdcc66SMintz, Yuval *p_resc_num = 0; 37479c8517c4STomer Tayar break; 37489c8517c4STomer Tayar default: 37499c8517c4STomer Tayar return -EINVAL; 37509c8517c4STomer Tayar } 37519c8517c4STomer Tayar 37529c8517c4STomer Tayar switch (res_id) { 37539c8517c4STomer Tayar case QED_BDQ: 37549c8517c4STomer Tayar if (!*p_resc_num) 37559c8517c4STomer Tayar *p_resc_start = 0; 375678cea9ffSTomer Tayar else if (p_hwfn->cdev->num_ports_in_engine == 4) 37579c8517c4STomer Tayar *p_resc_start = p_hwfn->port_id; 37589c8517c4STomer Tayar else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) 37599c8517c4STomer Tayar *p_resc_start = p_hwfn->port_id; 37609c8517c4STomer Tayar else if (p_hwfn->hw_info.personality == QED_PCI_FCOE) 37619c8517c4STomer Tayar *p_resc_start = p_hwfn->port_id + 2; 37629c8517c4STomer Tayar break; 37639c8517c4STomer Tayar default: 37649c8517c4STomer Tayar *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx; 37659c8517c4STomer Tayar break; 37669c8517c4STomer Tayar } 37679c8517c4STomer Tayar 37689c8517c4STomer Tayar return 0; 37699c8517c4STomer Tayar } 37709c8517c4STomer Tayar 37719c8517c4STomer Tayar static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn, 37722edbff8dSTomer Tayar enum qed_resources res_id) 37732edbff8dSTomer Tayar { 37749c8517c4STomer Tayar u32 dflt_resc_num = 0, dflt_resc_start = 0; 37759c8517c4STomer Tayar u32 mcp_resp, *p_resc_num, *p_resc_start; 37762edbff8dSTomer Tayar int rc; 37772edbff8dSTomer Tayar 37782edbff8dSTomer Tayar p_resc_num = &RESC_NUM(p_hwfn, res_id); 37792edbff8dSTomer Tayar p_resc_start = &RESC_START(p_hwfn, res_id); 37802edbff8dSTomer Tayar 37819c8517c4STomer Tayar rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num, 37829c8517c4STomer Tayar &dflt_resc_start); 37839c8517c4STomer Tayar if (rc) { 37842edbff8dSTomer Tayar DP_ERR(p_hwfn, 37852edbff8dSTomer Tayar "Failed to get default amount for resource %d [%s]\n", 37862edbff8dSTomer Tayar res_id, qed_hw_get_resc_name(res_id)); 37879c8517c4STomer Tayar return rc; 37882edbff8dSTomer Tayar } 37892edbff8dSTomer Tayar 37909c8517c4STomer Tayar rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id, 37919c8517c4STomer Tayar &mcp_resp, p_resc_num, p_resc_start); 37922edbff8dSTomer Tayar if (rc) { 37932edbff8dSTomer Tayar DP_NOTICE(p_hwfn, 37942edbff8dSTomer Tayar "MFW response failure for an allocation request for resource %d [%s]\n", 37952edbff8dSTomer Tayar res_id, qed_hw_get_resc_name(res_id)); 37962edbff8dSTomer Tayar return rc; 37972edbff8dSTomer Tayar } 37982edbff8dSTomer Tayar 37992edbff8dSTomer Tayar /* Default driver values are applied in the following cases: 38002edbff8dSTomer Tayar * - The resource allocation MB command is not supported by the MFW 38012edbff8dSTomer Tayar * - There is an internal error in the MFW while processing the request 38022edbff8dSTomer Tayar * - The resource ID is unknown to the MFW 38032edbff8dSTomer Tayar */ 38049c8517c4STomer Tayar if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) { 38059c8517c4STomer Tayar DP_INFO(p_hwfn, 38069c8517c4STomer Tayar "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n", 38072edbff8dSTomer Tayar res_id, 38082edbff8dSTomer Tayar qed_hw_get_resc_name(res_id), 38092edbff8dSTomer Tayar mcp_resp, dflt_resc_num, dflt_resc_start); 38102edbff8dSTomer Tayar *p_resc_num = dflt_resc_num; 38112edbff8dSTomer Tayar *p_resc_start = dflt_resc_start; 38122edbff8dSTomer Tayar goto out; 38132edbff8dSTomer Tayar } 38142edbff8dSTomer Tayar 38152edbff8dSTomer Tayar out: 38162edbff8dSTomer Tayar /* PQs have to divide by 8 [that's the HW granularity]. 38172edbff8dSTomer Tayar * Reduce number so it would fit. 38182edbff8dSTomer Tayar */ 38192edbff8dSTomer Tayar if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) { 38202edbff8dSTomer Tayar DP_INFO(p_hwfn, 38212edbff8dSTomer Tayar "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n", 38222edbff8dSTomer Tayar *p_resc_num, 38232edbff8dSTomer Tayar (*p_resc_num) & ~0x7, 38242edbff8dSTomer Tayar *p_resc_start, (*p_resc_start) & ~0x7); 38252edbff8dSTomer Tayar *p_resc_num &= ~0x7; 38262edbff8dSTomer Tayar *p_resc_start &= ~0x7; 38272edbff8dSTomer Tayar } 38282edbff8dSTomer Tayar 38292edbff8dSTomer Tayar return 0; 38302edbff8dSTomer Tayar } 38312edbff8dSTomer Tayar 38329c8517c4STomer Tayar static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn) 3833fe56b9e6SYuval Mintz { 38349c8517c4STomer Tayar int rc; 38359c8517c4STomer Tayar u8 res_id; 38369c8517c4STomer Tayar 38379c8517c4STomer Tayar for (res_id = 0; res_id < QED_MAX_RESC; res_id++) { 38389c8517c4STomer Tayar rc = __qed_hw_set_resc_info(p_hwfn, res_id); 38399c8517c4STomer Tayar if (rc) 38409c8517c4STomer Tayar return rc; 38419c8517c4STomer Tayar } 38429c8517c4STomer Tayar 38439c8517c4STomer Tayar return 0; 38449c8517c4STomer Tayar } 38459c8517c4STomer Tayar 384679284adeSMichal Kalderon static int qed_hw_get_ppfid_bitmap(struct qed_hwfn *p_hwfn, 384779284adeSMichal Kalderon struct qed_ptt *p_ptt) 384879284adeSMichal Kalderon { 384979284adeSMichal Kalderon struct qed_dev *cdev = p_hwfn->cdev; 385079284adeSMichal Kalderon u8 native_ppfid_idx; 385179284adeSMichal Kalderon int rc; 385279284adeSMichal Kalderon 385379284adeSMichal Kalderon /* Calculation of BB/AH is different for native_ppfid_idx */ 385479284adeSMichal Kalderon if (QED_IS_BB(cdev)) 385579284adeSMichal Kalderon native_ppfid_idx = p_hwfn->rel_pf_id; 385679284adeSMichal Kalderon else 385779284adeSMichal Kalderon native_ppfid_idx = p_hwfn->rel_pf_id / 385879284adeSMichal Kalderon cdev->num_ports_in_engine; 385979284adeSMichal Kalderon 386079284adeSMichal Kalderon rc = qed_mcp_get_ppfid_bitmap(p_hwfn, p_ptt); 386179284adeSMichal Kalderon if (rc != 0 && rc != -EOPNOTSUPP) 386279284adeSMichal Kalderon return rc; 386379284adeSMichal Kalderon else if (rc == -EOPNOTSUPP) 386479284adeSMichal Kalderon cdev->ppfid_bitmap = 0x1 << native_ppfid_idx; 386579284adeSMichal Kalderon 386679284adeSMichal Kalderon if (!(cdev->ppfid_bitmap & (0x1 << native_ppfid_idx))) { 386779284adeSMichal Kalderon DP_INFO(p_hwfn, 38681b3855abSColin Ian King "Fix the PPFID bitmap to include the native PPFID [native_ppfid_idx %hhd, orig_bitmap 0x%hhx]\n", 386979284adeSMichal Kalderon native_ppfid_idx, cdev->ppfid_bitmap); 387079284adeSMichal Kalderon cdev->ppfid_bitmap = 0x1 << native_ppfid_idx; 387179284adeSMichal Kalderon } 387279284adeSMichal Kalderon 387379284adeSMichal Kalderon return 0; 387479284adeSMichal Kalderon } 387579284adeSMichal Kalderon 38769c8517c4STomer Tayar static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 38779c8517c4STomer Tayar { 38789c8517c4STomer Tayar struct qed_resc_unlock_params resc_unlock_params; 38799c8517c4STomer Tayar struct qed_resc_lock_params resc_lock_params; 38809c79ddaaSMintz, Yuval bool b_ah = QED_IS_AH(p_hwfn->cdev); 38812edbff8dSTomer Tayar u8 res_id; 38822edbff8dSTomer Tayar int rc; 3883fe56b9e6SYuval Mintz 38849c8517c4STomer Tayar /* Setting the max values of the soft resources and the following 38859c8517c4STomer Tayar * resources allocation queries should be atomic. Since several PFs can 38869c8517c4STomer Tayar * run in parallel - a resource lock is needed. 38879c8517c4STomer Tayar * If either the resource lock or resource set value commands are not 38889c8517c4STomer Tayar * supported - skip the the max values setting, release the lock if 38899c8517c4STomer Tayar * needed, and proceed to the queries. Other failures, including a 38909c8517c4STomer Tayar * failure to acquire the lock, will cause this function to fail. 38919c8517c4STomer Tayar */ 3892f470f22cSsudarsana.kalluru@cavium.com qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params, 3893f470f22cSsudarsana.kalluru@cavium.com QED_RESC_LOCK_RESC_ALLOC, false); 38949c8517c4STomer Tayar 38959c8517c4STomer Tayar rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params); 38969c8517c4STomer Tayar if (rc && rc != -EINVAL) { 38972edbff8dSTomer Tayar return rc; 38989c8517c4STomer Tayar } else if (rc == -EINVAL) { 38999c8517c4STomer Tayar DP_INFO(p_hwfn, 39009c8517c4STomer Tayar "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n"); 39019c8517c4STomer Tayar } else if (!rc && !resc_lock_params.b_granted) { 39029c8517c4STomer Tayar DP_NOTICE(p_hwfn, 39039c8517c4STomer Tayar "Failed to acquire the resource lock for the resource allocation commands\n"); 39049c8517c4STomer Tayar return -EBUSY; 39059c8517c4STomer Tayar } else { 39069c8517c4STomer Tayar rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt); 39079c8517c4STomer Tayar if (rc && rc != -EINVAL) { 39089c8517c4STomer Tayar DP_NOTICE(p_hwfn, 39099c8517c4STomer Tayar "Failed to set the max values of the soft resources\n"); 39109c8517c4STomer Tayar goto unlock_and_exit; 39119c8517c4STomer Tayar } else if (rc == -EINVAL) { 39129c8517c4STomer Tayar DP_INFO(p_hwfn, 39139c8517c4STomer Tayar "Skip the max values setting of the soft resources since it is not supported by the MFW\n"); 39149c8517c4STomer Tayar rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, 39159c8517c4STomer Tayar &resc_unlock_params); 39169c8517c4STomer Tayar if (rc) 39179c8517c4STomer Tayar DP_INFO(p_hwfn, 39189c8517c4STomer Tayar "Failed to release the resource lock for the resource allocation commands\n"); 39199c8517c4STomer Tayar } 39209c8517c4STomer Tayar } 39219c8517c4STomer Tayar 39229c8517c4STomer Tayar rc = qed_hw_set_resc_info(p_hwfn); 39239c8517c4STomer Tayar if (rc) 39249c8517c4STomer Tayar goto unlock_and_exit; 39259c8517c4STomer Tayar 39269c8517c4STomer Tayar if (resc_lock_params.b_granted && !resc_unlock_params.b_released) { 39279c8517c4STomer Tayar rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params); 39289c8517c4STomer Tayar if (rc) 39299c8517c4STomer Tayar DP_INFO(p_hwfn, 39309c8517c4STomer Tayar "Failed to release the resource lock for the resource allocation commands\n"); 39312edbff8dSTomer Tayar } 3932dbb799c3SYuval Mintz 393379284adeSMichal Kalderon /* PPFID bitmap */ 393479284adeSMichal Kalderon if (IS_LEAD_HWFN(p_hwfn)) { 393579284adeSMichal Kalderon rc = qed_hw_get_ppfid_bitmap(p_hwfn, p_ptt); 393679284adeSMichal Kalderon if (rc) 393779284adeSMichal Kalderon return rc; 393879284adeSMichal Kalderon } 393979284adeSMichal Kalderon 3940dbb799c3SYuval Mintz /* Sanity for ILT */ 39419c79ddaaSMintz, Yuval if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) || 39429c79ddaaSMintz, Yuval (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) { 3943dbb799c3SYuval Mintz DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n", 3944dbb799c3SYuval Mintz RESC_START(p_hwfn, QED_ILT), 3945dbb799c3SYuval Mintz RESC_END(p_hwfn, QED_ILT) - 1); 3946dbb799c3SYuval Mintz return -EINVAL; 3947dbb799c3SYuval Mintz } 3948fe56b9e6SYuval Mintz 3949ebbdcc66SMintz, Yuval /* This will also learn the number of SBs from MFW */ 3950ebbdcc66SMintz, Yuval if (qed_int_igu_reset_cam(p_hwfn, p_ptt)) 3951ebbdcc66SMintz, Yuval return -EINVAL; 3952ebbdcc66SMintz, Yuval 395325c089d7SYuval Mintz qed_hw_set_feat(p_hwfn); 395425c089d7SYuval Mintz 39552edbff8dSTomer Tayar for (res_id = 0; res_id < QED_MAX_RESC; res_id++) 39562edbff8dSTomer Tayar DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n", 39572edbff8dSTomer Tayar qed_hw_get_resc_name(res_id), 39582edbff8dSTomer Tayar RESC_NUM(p_hwfn, res_id), 39592edbff8dSTomer Tayar RESC_START(p_hwfn, res_id)); 3960dbb799c3SYuval Mintz 3961dbb799c3SYuval Mintz return 0; 39629c8517c4STomer Tayar 39639c8517c4STomer Tayar unlock_and_exit: 39649c8517c4STomer Tayar if (resc_lock_params.b_granted && !resc_unlock_params.b_released) 39659c8517c4STomer Tayar qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params); 39669c8517c4STomer Tayar return rc; 3967fe56b9e6SYuval Mintz } 3968fe56b9e6SYuval Mintz 39691a635e48SYuval Mintz static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3970fe56b9e6SYuval Mintz { 3971ae7e6937SAlexander Lobakin u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities, fc; 39721e128c81SArun Easi u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg; 3973645874e5SSudarsana Reddy Kalluru struct qed_mcp_link_capabilities *p_caps; 3974cc875c2eSYuval Mintz struct qed_mcp_link_params *link; 3975fe56b9e6SYuval Mintz 3976fe56b9e6SYuval Mintz /* Read global nvm_cfg address */ 3977fe56b9e6SYuval Mintz nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 3978fe56b9e6SYuval Mintz 3979fe56b9e6SYuval Mintz /* Verify MCP has initialized it */ 3980fe56b9e6SYuval Mintz if (!nvm_cfg_addr) { 3981fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 3982fe56b9e6SYuval Mintz return -EINVAL; 3983fe56b9e6SYuval Mintz } 3984fe56b9e6SYuval Mintz 3985fe56b9e6SYuval Mintz /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */ 3986fe56b9e6SYuval Mintz nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 3987fe56b9e6SYuval Mintz 3988cc875c2eSYuval Mintz addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 3989cc875c2eSYuval Mintz offsetof(struct nvm_cfg1, glob) + 3990cc875c2eSYuval Mintz offsetof(struct nvm_cfg1_glob, core_cfg); 3991cc875c2eSYuval Mintz 3992cc875c2eSYuval Mintz core_cfg = qed_rd(p_hwfn, p_ptt, addr); 3993cc875c2eSYuval Mintz 3994cc875c2eSYuval Mintz switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >> 3995cc875c2eSYuval Mintz NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) { 3996351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G: 3997351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G: 3998351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G: 3999351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F: 4000351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E: 4001351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G: 4002351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G: 4003351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G: 40049c79ddaaSMintz, Yuval case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G: 4005351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G: 40069c79ddaaSMintz, Yuval case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G: 4007a396818cSAlexander Lobakin case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X50G_R1: 4008a396818cSAlexander Lobakin case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_4X50G_R1: 4009a396818cSAlexander Lobakin case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R2: 4010a396818cSAlexander Lobakin case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_2X100G_R2: 4011a396818cSAlexander Lobakin case NVM_CFG1_GLOB_NETWORK_PORT_MODE_AHP_1X100G_R4: 40129c79ddaaSMintz, Yuval break; 4013cc875c2eSYuval Mintz default: 40141a635e48SYuval Mintz DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg); 4015cc875c2eSYuval Mintz break; 4016cc875c2eSYuval Mintz } 4017cc875c2eSYuval Mintz 4018cc875c2eSYuval Mintz /* Read default link configuration */ 4019cc875c2eSYuval Mintz link = &p_hwfn->mcp_info->link_input; 4020645874e5SSudarsana Reddy Kalluru p_caps = &p_hwfn->mcp_info->link_capabilities; 4021cc875c2eSYuval Mintz port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 4022cc875c2eSYuval Mintz offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 4023cc875c2eSYuval Mintz link_temp = qed_rd(p_hwfn, p_ptt, 4024cc875c2eSYuval Mintz port_cfg_addr + 4025cc875c2eSYuval Mintz offsetof(struct nvm_cfg1_port, speed_cap_mask)); 402683aeb933SYuval Mintz link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK; 402783aeb933SYuval Mintz link->speed.advertised_speeds = link_temp; 4028cc875c2eSYuval Mintz 402983aeb933SYuval Mintz link_temp = link->speed.advertised_speeds; 403083aeb933SYuval Mintz p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp; 4031cc875c2eSYuval Mintz 4032cc875c2eSYuval Mintz link_temp = qed_rd(p_hwfn, p_ptt, 4033cc875c2eSYuval Mintz port_cfg_addr + 4034cc875c2eSYuval Mintz offsetof(struct nvm_cfg1_port, link_settings)); 4035cc875c2eSYuval Mintz switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >> 4036cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) { 4037cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG: 4038cc875c2eSYuval Mintz link->speed.autoneg = true; 4039cc875c2eSYuval Mintz break; 4040cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_1G: 4041cc875c2eSYuval Mintz link->speed.forced_speed = 1000; 4042cc875c2eSYuval Mintz break; 4043cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_10G: 4044cc875c2eSYuval Mintz link->speed.forced_speed = 10000; 4045cc875c2eSYuval Mintz break; 40465bf0961cSSudarsana Reddy Kalluru case NVM_CFG1_PORT_DRV_LINK_SPEED_20G: 40475bf0961cSSudarsana Reddy Kalluru link->speed.forced_speed = 20000; 40485bf0961cSSudarsana Reddy Kalluru break; 4049cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_25G: 4050cc875c2eSYuval Mintz link->speed.forced_speed = 25000; 4051cc875c2eSYuval Mintz break; 4052cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_40G: 4053cc875c2eSYuval Mintz link->speed.forced_speed = 40000; 4054cc875c2eSYuval Mintz break; 4055cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_50G: 4056cc875c2eSYuval Mintz link->speed.forced_speed = 50000; 4057cc875c2eSYuval Mintz break; 4058351a4dedSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G: 4059cc875c2eSYuval Mintz link->speed.forced_speed = 100000; 4060cc875c2eSYuval Mintz break; 4061cc875c2eSYuval Mintz default: 40621a635e48SYuval Mintz DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp); 4063cc875c2eSYuval Mintz } 4064cc875c2eSYuval Mintz 406534f9199cSsudarsana.kalluru@cavium.com p_hwfn->mcp_info->link_capabilities.default_speed_autoneg = 406634f9199cSsudarsana.kalluru@cavium.com link->speed.autoneg; 406734f9199cSsudarsana.kalluru@cavium.com 4068ae7e6937SAlexander Lobakin fc = GET_MFW_FIELD(link_temp, NVM_CFG1_PORT_DRV_FLOW_CONTROL); 4069ae7e6937SAlexander Lobakin link->pause.autoneg = !!(fc & NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG); 4070ae7e6937SAlexander Lobakin link->pause.forced_rx = !!(fc & NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX); 4071ae7e6937SAlexander Lobakin link->pause.forced_tx = !!(fc & NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX); 4072cc875c2eSYuval Mintz link->loopback_mode = 0; 4073cc875c2eSYuval Mintz 4074ae7e6937SAlexander Lobakin if (p_hwfn->mcp_info->capabilities & 4075ae7e6937SAlexander Lobakin FW_MB_PARAM_FEATURE_SUPPORT_FEC_CONTROL) { 4076ae7e6937SAlexander Lobakin switch (GET_MFW_FIELD(link_temp, 4077ae7e6937SAlexander Lobakin NVM_CFG1_PORT_FEC_FORCE_MODE)) { 4078ae7e6937SAlexander Lobakin case NVM_CFG1_PORT_FEC_FORCE_MODE_NONE: 4079ae7e6937SAlexander Lobakin p_caps->fec_default |= QED_FEC_MODE_NONE; 4080ae7e6937SAlexander Lobakin break; 4081ae7e6937SAlexander Lobakin case NVM_CFG1_PORT_FEC_FORCE_MODE_FIRECODE: 4082ae7e6937SAlexander Lobakin p_caps->fec_default |= QED_FEC_MODE_FIRECODE; 4083ae7e6937SAlexander Lobakin break; 4084ae7e6937SAlexander Lobakin case NVM_CFG1_PORT_FEC_FORCE_MODE_RS: 4085ae7e6937SAlexander Lobakin p_caps->fec_default |= QED_FEC_MODE_RS; 4086ae7e6937SAlexander Lobakin break; 4087ae7e6937SAlexander Lobakin case NVM_CFG1_PORT_FEC_FORCE_MODE_AUTO: 4088ae7e6937SAlexander Lobakin p_caps->fec_default |= QED_FEC_MODE_AUTO; 4089ae7e6937SAlexander Lobakin break; 4090ae7e6937SAlexander Lobakin default: 4091ae7e6937SAlexander Lobakin DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 4092ae7e6937SAlexander Lobakin "unknown FEC mode in 0x%08x\n", link_temp); 4093ae7e6937SAlexander Lobakin } 4094ae7e6937SAlexander Lobakin } else { 4095ae7e6937SAlexander Lobakin p_caps->fec_default = QED_FEC_MODE_UNSUPPORTED; 4096ae7e6937SAlexander Lobakin } 4097ae7e6937SAlexander Lobakin 4098ae7e6937SAlexander Lobakin link->fec = p_caps->fec_default; 4099ae7e6937SAlexander Lobakin 4100645874e5SSudarsana Reddy Kalluru if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) { 4101645874e5SSudarsana Reddy Kalluru link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr + 4102645874e5SSudarsana Reddy Kalluru offsetof(struct nvm_cfg1_port, ext_phy)); 4103645874e5SSudarsana Reddy Kalluru link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK; 4104645874e5SSudarsana Reddy Kalluru link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET; 4105645874e5SSudarsana Reddy Kalluru p_caps->default_eee = QED_MCP_EEE_ENABLED; 4106645874e5SSudarsana Reddy Kalluru link->eee.enable = true; 4107645874e5SSudarsana Reddy Kalluru switch (link_temp) { 4108645874e5SSudarsana Reddy Kalluru case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED: 4109645874e5SSudarsana Reddy Kalluru p_caps->default_eee = QED_MCP_EEE_DISABLED; 4110645874e5SSudarsana Reddy Kalluru link->eee.enable = false; 4111645874e5SSudarsana Reddy Kalluru break; 4112645874e5SSudarsana Reddy Kalluru case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED: 4113645874e5SSudarsana Reddy Kalluru p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME; 4114645874e5SSudarsana Reddy Kalluru break; 4115645874e5SSudarsana Reddy Kalluru case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE: 4116645874e5SSudarsana Reddy Kalluru p_caps->eee_lpi_timer = 4117645874e5SSudarsana Reddy Kalluru EEE_TX_TIMER_USEC_AGGRESSIVE_TIME; 4118645874e5SSudarsana Reddy Kalluru break; 4119645874e5SSudarsana Reddy Kalluru case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY: 4120645874e5SSudarsana Reddy Kalluru p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME; 4121645874e5SSudarsana Reddy Kalluru break; 4122645874e5SSudarsana Reddy Kalluru } 4123645874e5SSudarsana Reddy Kalluru 4124645874e5SSudarsana Reddy Kalluru link->eee.tx_lpi_timer = p_caps->eee_lpi_timer; 4125645874e5SSudarsana Reddy Kalluru link->eee.tx_lpi_enable = link->eee.enable; 4126645874e5SSudarsana Reddy Kalluru link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV; 4127645874e5SSudarsana Reddy Kalluru } else { 4128645874e5SSudarsana Reddy Kalluru p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED; 4129645874e5SSudarsana Reddy Kalluru } 4130645874e5SSudarsana Reddy Kalluru 4131ae7e6937SAlexander Lobakin DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 4132ae7e6937SAlexander Lobakin "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x, EEE: 0x%02x [0x%08x usec], FEC: 0x%02x\n", 4133ae7e6937SAlexander Lobakin link->speed.forced_speed, link->speed.advertised_speeds, 4134ae7e6937SAlexander Lobakin link->speed.autoneg, link->pause.autoneg, 4135ae7e6937SAlexander Lobakin p_caps->default_eee, p_caps->eee_lpi_timer, 4136ae7e6937SAlexander Lobakin p_caps->fec_default); 4137cc875c2eSYuval Mintz 4138b51bdfb9SSudarsana Reddy Kalluru if (IS_LEAD_HWFN(p_hwfn)) { 4139b51bdfb9SSudarsana Reddy Kalluru struct qed_dev *cdev = p_hwfn->cdev; 4140b51bdfb9SSudarsana Reddy Kalluru 4141fe56b9e6SYuval Mintz /* Read Multi-function information from shmem */ 4142fe56b9e6SYuval Mintz addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 4143fe56b9e6SYuval Mintz offsetof(struct nvm_cfg1, glob) + 4144fe56b9e6SYuval Mintz offsetof(struct nvm_cfg1_glob, generic_cont0); 4145fe56b9e6SYuval Mintz 4146fe56b9e6SYuval Mintz generic_cont0 = qed_rd(p_hwfn, p_ptt, addr); 4147fe56b9e6SYuval Mintz 4148fe56b9e6SYuval Mintz mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >> 4149fe56b9e6SYuval Mintz NVM_CFG1_GLOB_MF_MODE_OFFSET; 4150fe56b9e6SYuval Mintz 4151fe56b9e6SYuval Mintz switch (mf_mode) { 4152fe56b9e6SYuval Mintz case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED: 4153b51bdfb9SSudarsana Reddy Kalluru cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS); 4154b51bdfb9SSudarsana Reddy Kalluru break; 4155cac6f691SSudarsana Reddy Kalluru case NVM_CFG1_GLOB_MF_MODE_UFP: 4156cac6f691SSudarsana Reddy Kalluru cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) | 4157cac6f691SSudarsana Reddy Kalluru BIT(QED_MF_LLH_PROTO_CLSS) | 4158cac6f691SSudarsana Reddy Kalluru BIT(QED_MF_UFP_SPECIFIC) | 41591a3ca250SSudarsana Reddy Kalluru BIT(QED_MF_8021Q_TAGGING) | 41601a3ca250SSudarsana Reddy Kalluru BIT(QED_MF_DONT_ADD_VLAN0_TAG); 4161cac6f691SSudarsana Reddy Kalluru break; 4162b51bdfb9SSudarsana Reddy Kalluru case NVM_CFG1_GLOB_MF_MODE_BD: 4163b51bdfb9SSudarsana Reddy Kalluru cdev->mf_bits = BIT(QED_MF_OVLAN_CLSS) | 4164b51bdfb9SSudarsana Reddy Kalluru BIT(QED_MF_LLH_PROTO_CLSS) | 41651a3ca250SSudarsana Reddy Kalluru BIT(QED_MF_8021AD_TAGGING) | 41661a3ca250SSudarsana Reddy Kalluru BIT(QED_MF_DONT_ADD_VLAN0_TAG); 4167fe56b9e6SYuval Mintz break; 4168fe56b9e6SYuval Mintz case NVM_CFG1_GLOB_MF_MODE_NPAR1_0: 4169b51bdfb9SSudarsana Reddy Kalluru cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) | 41700bc5fe85SSudarsana Reddy Kalluru BIT(QED_MF_LLH_PROTO_CLSS) | 41710bc5fe85SSudarsana Reddy Kalluru BIT(QED_MF_LL2_NON_UNICAST) | 41720bc5fe85SSudarsana Reddy Kalluru BIT(QED_MF_INTER_PF_SWITCH); 4173fe56b9e6SYuval Mintz break; 4174fc48b7a6SYuval Mintz case NVM_CFG1_GLOB_MF_MODE_DEFAULT: 4175b51bdfb9SSudarsana Reddy Kalluru cdev->mf_bits = BIT(QED_MF_LLH_MAC_CLSS) | 41760bc5fe85SSudarsana Reddy Kalluru BIT(QED_MF_LLH_PROTO_CLSS) | 41770bc5fe85SSudarsana Reddy Kalluru BIT(QED_MF_LL2_NON_UNICAST); 41780bc5fe85SSudarsana Reddy Kalluru if (QED_IS_BB(p_hwfn->cdev)) 4179b51bdfb9SSudarsana Reddy Kalluru cdev->mf_bits |= BIT(QED_MF_NEED_DEF_PF); 4180fe56b9e6SYuval Mintz break; 4181fe56b9e6SYuval Mintz } 41820bc5fe85SSudarsana Reddy Kalluru 41830bc5fe85SSudarsana Reddy Kalluru DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n", 4184b51bdfb9SSudarsana Reddy Kalluru cdev->mf_bits); 4185b51bdfb9SSudarsana Reddy Kalluru } 4186b51bdfb9SSudarsana Reddy Kalluru 4187b51bdfb9SSudarsana Reddy Kalluru DP_INFO(p_hwfn, "Multi function mode is 0x%lx\n", 41880bc5fe85SSudarsana Reddy Kalluru p_hwfn->cdev->mf_bits); 4189fe56b9e6SYuval Mintz 4190b51bdfb9SSudarsana Reddy Kalluru /* Read device capabilities information from shmem */ 4191fc48b7a6SYuval Mintz addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 4192fc48b7a6SYuval Mintz offsetof(struct nvm_cfg1, glob) + 4193fc48b7a6SYuval Mintz offsetof(struct nvm_cfg1_glob, device_capabilities); 4194fc48b7a6SYuval Mintz 4195fc48b7a6SYuval Mintz device_capabilities = qed_rd(p_hwfn, p_ptt, addr); 4196fc48b7a6SYuval Mintz if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET) 4197fc48b7a6SYuval Mintz __set_bit(QED_DEV_CAP_ETH, 4198fc48b7a6SYuval Mintz &p_hwfn->hw_info.device_capabilities); 41991e128c81SArun Easi if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE) 42001e128c81SArun Easi __set_bit(QED_DEV_CAP_FCOE, 42011e128c81SArun Easi &p_hwfn->hw_info.device_capabilities); 4202c5ac9319SYuval Mintz if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI) 4203c5ac9319SYuval Mintz __set_bit(QED_DEV_CAP_ISCSI, 4204c5ac9319SYuval Mintz &p_hwfn->hw_info.device_capabilities); 4205c5ac9319SYuval Mintz if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE) 4206c5ac9319SYuval Mintz __set_bit(QED_DEV_CAP_ROCE, 4207c5ac9319SYuval Mintz &p_hwfn->hw_info.device_capabilities); 4208fc48b7a6SYuval Mintz 4209fe56b9e6SYuval Mintz return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt); 4210fe56b9e6SYuval Mintz } 4211fe56b9e6SYuval Mintz 42121408cc1fSYuval Mintz static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 42131408cc1fSYuval Mintz { 4214dbb799c3SYuval Mintz u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id; 4215dbb799c3SYuval Mintz u32 reg_function_hide, tmp, eng_mask, low_pfs_mask; 42169c79ddaaSMintz, Yuval struct qed_dev *cdev = p_hwfn->cdev; 42171408cc1fSYuval Mintz 42189c79ddaaSMintz, Yuval num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB; 42191408cc1fSYuval Mintz 42201408cc1fSYuval Mintz /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values 42211408cc1fSYuval Mintz * in the other bits are selected. 42221408cc1fSYuval Mintz * Bits 1-15 are for functions 1-15, respectively, and their value is 42231408cc1fSYuval Mintz * '0' only for enabled functions (function 0 always exists and 42241408cc1fSYuval Mintz * enabled). 42251408cc1fSYuval Mintz * In case of CMT, only the "even" functions are enabled, and thus the 42261408cc1fSYuval Mintz * number of functions for both hwfns is learnt from the same bits. 42271408cc1fSYuval Mintz */ 42281408cc1fSYuval Mintz reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE); 42291408cc1fSYuval Mintz 42301408cc1fSYuval Mintz if (reg_function_hide & 0x1) { 42319c79ddaaSMintz, Yuval if (QED_IS_BB(cdev)) { 42329c79ddaaSMintz, Yuval if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) { 42331408cc1fSYuval Mintz num_funcs = 0; 42341408cc1fSYuval Mintz eng_mask = 0xaaaa; 42351408cc1fSYuval Mintz } else { 42361408cc1fSYuval Mintz num_funcs = 1; 42371408cc1fSYuval Mintz eng_mask = 0x5554; 42381408cc1fSYuval Mintz } 42399c79ddaaSMintz, Yuval } else { 42409c79ddaaSMintz, Yuval num_funcs = 1; 42419c79ddaaSMintz, Yuval eng_mask = 0xfffe; 42429c79ddaaSMintz, Yuval } 42431408cc1fSYuval Mintz 42441408cc1fSYuval Mintz /* Get the number of the enabled functions on the engine */ 42451408cc1fSYuval Mintz tmp = (reg_function_hide ^ 0xffffffff) & eng_mask; 42461408cc1fSYuval Mintz while (tmp) { 42471408cc1fSYuval Mintz if (tmp & 0x1) 42481408cc1fSYuval Mintz num_funcs++; 42491408cc1fSYuval Mintz tmp >>= 0x1; 42501408cc1fSYuval Mintz } 4251dbb799c3SYuval Mintz 4252dbb799c3SYuval Mintz /* Get the PF index within the enabled functions */ 4253dbb799c3SYuval Mintz low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1; 4254dbb799c3SYuval Mintz tmp = reg_function_hide & eng_mask & low_pfs_mask; 4255dbb799c3SYuval Mintz while (tmp) { 4256dbb799c3SYuval Mintz if (tmp & 0x1) 4257dbb799c3SYuval Mintz enabled_func_idx--; 4258dbb799c3SYuval Mintz tmp >>= 0x1; 4259dbb799c3SYuval Mintz } 42601408cc1fSYuval Mintz } 42611408cc1fSYuval Mintz 42621408cc1fSYuval Mintz p_hwfn->num_funcs_on_engine = num_funcs; 4263dbb799c3SYuval Mintz p_hwfn->enabled_func_idx = enabled_func_idx; 42641408cc1fSYuval Mintz 42651408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, 42661408cc1fSYuval Mintz NETIF_MSG_PROBE, 4267525ef5c0SYuval Mintz "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n", 42681408cc1fSYuval Mintz p_hwfn->rel_pf_id, 42691408cc1fSYuval Mintz p_hwfn->abs_pf_id, 4270525ef5c0SYuval Mintz p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine); 42711408cc1fSYuval Mintz } 42721408cc1fSYuval Mintz 42739c79ddaaSMintz, Yuval static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 42749c79ddaaSMintz, Yuval { 42750ebcebbeSSudarsana Reddy Kalluru u32 addr, global_offsize, global_addr, port_mode; 42760ebcebbeSSudarsana Reddy Kalluru struct qed_dev *cdev = p_hwfn->cdev; 42770ebcebbeSSudarsana Reddy Kalluru 42780ebcebbeSSudarsana Reddy Kalluru /* In CMT there is always only one port */ 42790ebcebbeSSudarsana Reddy Kalluru if (cdev->num_hwfns > 1) { 42800ebcebbeSSudarsana Reddy Kalluru cdev->num_ports_in_engine = 1; 42810ebcebbeSSudarsana Reddy Kalluru cdev->num_ports = 1; 42820ebcebbeSSudarsana Reddy Kalluru return; 42830ebcebbeSSudarsana Reddy Kalluru } 42840ebcebbeSSudarsana Reddy Kalluru 42850ebcebbeSSudarsana Reddy Kalluru /* Determine the number of ports per engine */ 42860ebcebbeSSudarsana Reddy Kalluru port_mode = qed_rd(p_hwfn, p_ptt, MISC_REG_PORT_MODE); 42870ebcebbeSSudarsana Reddy Kalluru switch (port_mode) { 42880ebcebbeSSudarsana Reddy Kalluru case 0x0: 42890ebcebbeSSudarsana Reddy Kalluru cdev->num_ports_in_engine = 1; 42900ebcebbeSSudarsana Reddy Kalluru break; 42910ebcebbeSSudarsana Reddy Kalluru case 0x1: 42920ebcebbeSSudarsana Reddy Kalluru cdev->num_ports_in_engine = 2; 42930ebcebbeSSudarsana Reddy Kalluru break; 42940ebcebbeSSudarsana Reddy Kalluru case 0x2: 42950ebcebbeSSudarsana Reddy Kalluru cdev->num_ports_in_engine = 4; 42960ebcebbeSSudarsana Reddy Kalluru break; 42970ebcebbeSSudarsana Reddy Kalluru default: 42980ebcebbeSSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Unknown port mode 0x%08x\n", port_mode); 42990ebcebbeSSudarsana Reddy Kalluru cdev->num_ports_in_engine = 1; /* Default to something */ 43000ebcebbeSSudarsana Reddy Kalluru break; 43010ebcebbeSSudarsana Reddy Kalluru } 43020ebcebbeSSudarsana Reddy Kalluru 43030ebcebbeSSudarsana Reddy Kalluru /* Get the total number of ports of the device */ 43040ebcebbeSSudarsana Reddy Kalluru addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base, 43050ebcebbeSSudarsana Reddy Kalluru PUBLIC_GLOBAL); 43060ebcebbeSSudarsana Reddy Kalluru global_offsize = qed_rd(p_hwfn, p_ptt, addr); 43070ebcebbeSSudarsana Reddy Kalluru global_addr = SECTION_ADDR(global_offsize, 0); 43080ebcebbeSSudarsana Reddy Kalluru addr = global_addr + offsetof(struct public_global, max_ports); 43090ebcebbeSSudarsana Reddy Kalluru cdev->num_ports = (u8)qed_rd(p_hwfn, p_ptt, addr); 43109c79ddaaSMintz, Yuval } 43119c79ddaaSMintz, Yuval 4312645874e5SSudarsana Reddy Kalluru static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 4313645874e5SSudarsana Reddy Kalluru { 4314645874e5SSudarsana Reddy Kalluru struct qed_mcp_link_capabilities *p_caps; 4315645874e5SSudarsana Reddy Kalluru u32 eee_status; 4316645874e5SSudarsana Reddy Kalluru 4317645874e5SSudarsana Reddy Kalluru p_caps = &p_hwfn->mcp_info->link_capabilities; 4318645874e5SSudarsana Reddy Kalluru if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED) 4319645874e5SSudarsana Reddy Kalluru return; 4320645874e5SSudarsana Reddy Kalluru 4321645874e5SSudarsana Reddy Kalluru p_caps->eee_speed_caps = 0; 4322645874e5SSudarsana Reddy Kalluru eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 4323645874e5SSudarsana Reddy Kalluru offsetof(struct public_port, eee_status)); 4324645874e5SSudarsana Reddy Kalluru eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >> 4325645874e5SSudarsana Reddy Kalluru EEE_SUPPORTED_SPEED_OFFSET; 4326645874e5SSudarsana Reddy Kalluru 4327645874e5SSudarsana Reddy Kalluru if (eee_status & EEE_1G_SUPPORTED) 4328645874e5SSudarsana Reddy Kalluru p_caps->eee_speed_caps |= QED_EEE_1G_ADV; 4329645874e5SSudarsana Reddy Kalluru if (eee_status & EEE_10G_ADV) 4330645874e5SSudarsana Reddy Kalluru p_caps->eee_speed_caps |= QED_EEE_10G_ADV; 4331645874e5SSudarsana Reddy Kalluru } 4332645874e5SSudarsana Reddy Kalluru 43339c79ddaaSMintz, Yuval static int 43349c79ddaaSMintz, Yuval qed_get_hw_info(struct qed_hwfn *p_hwfn, 43359c79ddaaSMintz, Yuval struct qed_ptt *p_ptt, 43369c79ddaaSMintz, Yuval enum qed_pci_personality personality) 43379c79ddaaSMintz, Yuval { 43389c79ddaaSMintz, Yuval int rc; 43399c79ddaaSMintz, Yuval 43409c79ddaaSMintz, Yuval /* Since all information is common, only first hwfns should do this */ 43419c79ddaaSMintz, Yuval if (IS_LEAD_HWFN(p_hwfn)) { 43429c79ddaaSMintz, Yuval rc = qed_iov_hw_info(p_hwfn); 43439c79ddaaSMintz, Yuval if (rc) 43449c79ddaaSMintz, Yuval return rc; 43459c79ddaaSMintz, Yuval } 43469c79ddaaSMintz, Yuval 43470ebcebbeSSudarsana Reddy Kalluru if (IS_LEAD_HWFN(p_hwfn)) 43489c79ddaaSMintz, Yuval qed_hw_info_port_num(p_hwfn, p_ptt); 4349fe56b9e6SYuval Mintz 4350645874e5SSudarsana Reddy Kalluru qed_mcp_get_capabilities(p_hwfn, p_ptt); 4351645874e5SSudarsana Reddy Kalluru 4352fe56b9e6SYuval Mintz qed_hw_get_nvm_info(p_hwfn, p_ptt); 4353fe56b9e6SYuval Mintz 4354fe56b9e6SYuval Mintz rc = qed_int_igu_read_cam(p_hwfn, p_ptt); 4355fe56b9e6SYuval Mintz if (rc) 4356fe56b9e6SYuval Mintz return rc; 4357fe56b9e6SYuval Mintz 4358fe56b9e6SYuval Mintz if (qed_mcp_is_init(p_hwfn)) 4359fe56b9e6SYuval Mintz ether_addr_copy(p_hwfn->hw_info.hw_mac_addr, 4360fe56b9e6SYuval Mintz p_hwfn->mcp_info->func_info.mac); 4361fe56b9e6SYuval Mintz else 4362fe56b9e6SYuval Mintz eth_random_addr(p_hwfn->hw_info.hw_mac_addr); 4363fe56b9e6SYuval Mintz 4364fe56b9e6SYuval Mintz if (qed_mcp_is_init(p_hwfn)) { 4365fe56b9e6SYuval Mintz if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET) 4366fe56b9e6SYuval Mintz p_hwfn->hw_info.ovlan = 4367fe56b9e6SYuval Mintz p_hwfn->mcp_info->func_info.ovlan; 4368fe56b9e6SYuval Mintz 4369fe56b9e6SYuval Mintz qed_mcp_cmd_port_init(p_hwfn, p_ptt); 4370645874e5SSudarsana Reddy Kalluru 4371645874e5SSudarsana Reddy Kalluru qed_get_eee_caps(p_hwfn, p_ptt); 4372cac6f691SSudarsana Reddy Kalluru 4373cac6f691SSudarsana Reddy Kalluru qed_mcp_read_ufp_config(p_hwfn, p_ptt); 4374fe56b9e6SYuval Mintz } 4375fe56b9e6SYuval Mintz 4376fe56b9e6SYuval Mintz if (qed_mcp_is_init(p_hwfn)) { 4377fe56b9e6SYuval Mintz enum qed_pci_personality protocol; 4378fe56b9e6SYuval Mintz 4379fe56b9e6SYuval Mintz protocol = p_hwfn->mcp_info->func_info.protocol; 4380fe56b9e6SYuval Mintz p_hwfn->hw_info.personality = protocol; 4381fe56b9e6SYuval Mintz } 4382fe56b9e6SYuval Mintz 438361be82b0SDenis Bolotin if (QED_IS_ROCE_PERSONALITY(p_hwfn)) 438482ebc889SJason Yan p_hwfn->hw_info.multi_tc_roce_en = true; 438561be82b0SDenis Bolotin 4386b5a9ee7cSAriel Elior p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2; 4387b5a9ee7cSAriel Elior p_hwfn->hw_info.num_active_tc = 1; 4388b5a9ee7cSAriel Elior 43891408cc1fSYuval Mintz qed_get_num_funcs(p_hwfn, p_ptt); 43901408cc1fSYuval Mintz 43910fefbfbaSSudarsana Kalluru if (qed_mcp_is_init(p_hwfn)) 43920fefbfbaSSudarsana Kalluru p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu; 43930fefbfbaSSudarsana Kalluru 43949c8517c4STomer Tayar return qed_hw_get_resc(p_hwfn, p_ptt); 4395fe56b9e6SYuval Mintz } 4396fe56b9e6SYuval Mintz 439715582962SRahul Verma static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 4398fe56b9e6SYuval Mintz { 439915582962SRahul Verma struct qed_dev *cdev = p_hwfn->cdev; 44009c79ddaaSMintz, Yuval u16 device_id_mask; 4401fe56b9e6SYuval Mintz u32 tmp; 4402fe56b9e6SYuval Mintz 4403fc48b7a6SYuval Mintz /* Read Vendor Id / Device Id */ 44041a635e48SYuval Mintz pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id); 44051a635e48SYuval Mintz pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id); 44061a635e48SYuval Mintz 44079c79ddaaSMintz, Yuval /* Determine type */ 44089c79ddaaSMintz, Yuval device_id_mask = cdev->device_id & QED_DEV_ID_MASK; 44099c79ddaaSMintz, Yuval switch (device_id_mask) { 44109c79ddaaSMintz, Yuval case QED_DEV_ID_MASK_BB: 44119c79ddaaSMintz, Yuval cdev->type = QED_DEV_TYPE_BB; 44129c79ddaaSMintz, Yuval break; 44139c79ddaaSMintz, Yuval case QED_DEV_ID_MASK_AH: 44149c79ddaaSMintz, Yuval cdev->type = QED_DEV_TYPE_AH; 44159c79ddaaSMintz, Yuval break; 44169c79ddaaSMintz, Yuval default: 44179c79ddaaSMintz, Yuval DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id); 44189c79ddaaSMintz, Yuval return -EBUSY; 44199c79ddaaSMintz, Yuval } 44209c79ddaaSMintz, Yuval 442115582962SRahul Verma cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM); 442215582962SRahul Verma cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV); 442315582962SRahul Verma 4424fe56b9e6SYuval Mintz MASK_FIELD(CHIP_REV, cdev->chip_rev); 4425fe56b9e6SYuval Mintz 4426fe56b9e6SYuval Mintz /* Learn number of HW-functions */ 442715582962SRahul Verma tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR); 4428fe56b9e6SYuval Mintz 4429fc48b7a6SYuval Mintz if (tmp & (1 << p_hwfn->rel_pf_id)) { 4430fe56b9e6SYuval Mintz DP_NOTICE(cdev->hwfns, "device in CMT mode\n"); 4431fe56b9e6SYuval Mintz cdev->num_hwfns = 2; 4432fe56b9e6SYuval Mintz } else { 4433fe56b9e6SYuval Mintz cdev->num_hwfns = 1; 4434fe56b9e6SYuval Mintz } 4435fe56b9e6SYuval Mintz 443615582962SRahul Verma cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt, 4437fe56b9e6SYuval Mintz MISCS_REG_CHIP_TEST_REG) >> 4; 4438fe56b9e6SYuval Mintz MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id); 443915582962SRahul Verma cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL); 4440fe56b9e6SYuval Mintz MASK_FIELD(CHIP_METAL, cdev->chip_metal); 4441fe56b9e6SYuval Mintz 4442fe56b9e6SYuval Mintz DP_INFO(cdev->hwfns, 44439c79ddaaSMintz, Yuval "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n", 44449c79ddaaSMintz, Yuval QED_IS_BB(cdev) ? "BB" : "AH", 44459c79ddaaSMintz, Yuval 'A' + cdev->chip_rev, 44469c79ddaaSMintz, Yuval (int)cdev->chip_metal, 4447fe56b9e6SYuval Mintz cdev->chip_num, cdev->chip_rev, 4448fe56b9e6SYuval Mintz cdev->chip_bond_id, cdev->chip_metal); 444912e09c69SYuval Mintz 445012e09c69SYuval Mintz return 0; 4451fe56b9e6SYuval Mintz } 4452fe56b9e6SYuval Mintz 4453fe56b9e6SYuval Mintz static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn, 4454fe56b9e6SYuval Mintz void __iomem *p_regview, 4455fe56b9e6SYuval Mintz void __iomem *p_doorbells, 44568366d520SMichal Kalderon u64 db_phys_addr, 4457fe56b9e6SYuval Mintz enum qed_pci_personality personality) 4458fe56b9e6SYuval Mintz { 445964515dc8STomer Tayar struct qed_dev *cdev = p_hwfn->cdev; 4460fe56b9e6SYuval Mintz int rc = 0; 4461fe56b9e6SYuval Mintz 4462fe56b9e6SYuval Mintz /* Split PCI bars evenly between hwfns */ 4463fe56b9e6SYuval Mintz p_hwfn->regview = p_regview; 4464fe56b9e6SYuval Mintz p_hwfn->doorbells = p_doorbells; 44658366d520SMichal Kalderon p_hwfn->db_phys_addr = db_phys_addr; 4466fe56b9e6SYuval Mintz 44671408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 44681408cc1fSYuval Mintz return qed_vf_hw_prepare(p_hwfn); 44691408cc1fSYuval Mintz 4470fe56b9e6SYuval Mintz /* Validate that chip access is feasible */ 4471fe56b9e6SYuval Mintz if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) { 4472fe56b9e6SYuval Mintz DP_ERR(p_hwfn, 4473fe56b9e6SYuval Mintz "Reading the ME register returns all Fs; Preventing further chip access\n"); 4474fe56b9e6SYuval Mintz return -EINVAL; 4475fe56b9e6SYuval Mintz } 4476fe56b9e6SYuval Mintz 4477fe56b9e6SYuval Mintz get_function_id(p_hwfn); 4478fe56b9e6SYuval Mintz 447912e09c69SYuval Mintz /* Allocate PTT pool */ 448012e09c69SYuval Mintz rc = qed_ptt_pool_alloc(p_hwfn); 44812591c280SJoe Perches if (rc) 4482fe56b9e6SYuval Mintz goto err0; 4483fe56b9e6SYuval Mintz 448412e09c69SYuval Mintz /* Allocate the main PTT */ 448512e09c69SYuval Mintz p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN); 448612e09c69SYuval Mintz 4487fe56b9e6SYuval Mintz /* First hwfn learns basic information, e.g., number of hwfns */ 448812e09c69SYuval Mintz if (!p_hwfn->my_id) { 448915582962SRahul Verma rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt); 44901a635e48SYuval Mintz if (rc) 449112e09c69SYuval Mintz goto err1; 449212e09c69SYuval Mintz } 449312e09c69SYuval Mintz 449412e09c69SYuval Mintz qed_hw_hwfn_prepare(p_hwfn); 4495fe56b9e6SYuval Mintz 4496fe56b9e6SYuval Mintz /* Initialize MCP structure */ 4497fe56b9e6SYuval Mintz rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt); 4498fe56b9e6SYuval Mintz if (rc) { 4499fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed initializing mcp command\n"); 4500fe56b9e6SYuval Mintz goto err1; 4501fe56b9e6SYuval Mintz } 4502fe56b9e6SYuval Mintz 4503fe56b9e6SYuval Mintz /* Read the device configuration information from the HW and SHMEM */ 4504fe56b9e6SYuval Mintz rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality); 4505fe56b9e6SYuval Mintz if (rc) { 4506fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed to get HW information\n"); 4507fe56b9e6SYuval Mintz goto err2; 4508fe56b9e6SYuval Mintz } 4509fe56b9e6SYuval Mintz 451018a69e36SMintz, Yuval /* Sending a mailbox to the MFW should be done after qed_get_hw_info() 451118a69e36SMintz, Yuval * is called as it sets the ports number in an engine. 451218a69e36SMintz, Yuval */ 451364515dc8STomer Tayar if (IS_LEAD_HWFN(p_hwfn) && !cdev->recov_in_prog) { 451418a69e36SMintz, Yuval rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt); 451518a69e36SMintz, Yuval if (rc) 451618a69e36SMintz, Yuval DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n"); 451718a69e36SMintz, Yuval } 451818a69e36SMintz, Yuval 451943645ce0SSudarsana Reddy Kalluru /* NVRAM info initialization and population */ 452043645ce0SSudarsana Reddy Kalluru if (IS_LEAD_HWFN(p_hwfn)) { 452143645ce0SSudarsana Reddy Kalluru rc = qed_mcp_nvm_info_populate(p_hwfn); 452243645ce0SSudarsana Reddy Kalluru if (rc) { 452343645ce0SSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 452443645ce0SSudarsana Reddy Kalluru "Failed to populate nvm info shadow\n"); 452543645ce0SSudarsana Reddy Kalluru goto err2; 452643645ce0SSudarsana Reddy Kalluru } 452743645ce0SSudarsana Reddy Kalluru } 452843645ce0SSudarsana Reddy Kalluru 4529fe56b9e6SYuval Mintz /* Allocate the init RT array and initialize the init-ops engine */ 4530fe56b9e6SYuval Mintz rc = qed_init_alloc(p_hwfn); 45312591c280SJoe Perches if (rc) 453243645ce0SSudarsana Reddy Kalluru goto err3; 4533fe56b9e6SYuval Mintz 4534fe56b9e6SYuval Mintz return rc; 453543645ce0SSudarsana Reddy Kalluru err3: 453643645ce0SSudarsana Reddy Kalluru if (IS_LEAD_HWFN(p_hwfn)) 453713cf8aabSSudarsana Reddy Kalluru qed_mcp_nvm_info_free(p_hwfn); 4538fe56b9e6SYuval Mintz err2: 453932a47e72SYuval Mintz if (IS_LEAD_HWFN(p_hwfn)) 454032a47e72SYuval Mintz qed_iov_free_hw_info(p_hwfn->cdev); 4541fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 4542fe56b9e6SYuval Mintz err1: 4543fe56b9e6SYuval Mintz qed_hw_hwfn_free(p_hwfn); 4544fe56b9e6SYuval Mintz err0: 4545fe56b9e6SYuval Mintz return rc; 4546fe56b9e6SYuval Mintz } 4547fe56b9e6SYuval Mintz 4548fe56b9e6SYuval Mintz int qed_hw_prepare(struct qed_dev *cdev, 4549fe56b9e6SYuval Mintz int personality) 4550fe56b9e6SYuval Mintz { 4551c78df14eSAriel Elior struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 4552c78df14eSAriel Elior int rc; 4553fe56b9e6SYuval Mintz 4554fe56b9e6SYuval Mintz /* Store the precompiled init data ptrs */ 45551408cc1fSYuval Mintz if (IS_PF(cdev)) 4556fe56b9e6SYuval Mintz qed_init_iro_array(cdev); 4557fe56b9e6SYuval Mintz 4558fe56b9e6SYuval Mintz /* Initialize the first hwfn - will learn number of hwfns */ 4559c78df14eSAriel Elior rc = qed_hw_prepare_single(p_hwfn, 4560c78df14eSAriel Elior cdev->regview, 45618366d520SMichal Kalderon cdev->doorbells, 45628366d520SMichal Kalderon cdev->db_phys_addr, 45638366d520SMichal Kalderon personality); 4564fe56b9e6SYuval Mintz if (rc) 4565fe56b9e6SYuval Mintz return rc; 4566fe56b9e6SYuval Mintz 4567c78df14eSAriel Elior personality = p_hwfn->hw_info.personality; 4568fe56b9e6SYuval Mintz 4569fe56b9e6SYuval Mintz /* Initialize the rest of the hwfns */ 4570c78df14eSAriel Elior if (cdev->num_hwfns > 1) { 4571fe56b9e6SYuval Mintz void __iomem *p_regview, *p_doorbell; 45728366d520SMichal Kalderon u64 db_phys_addr; 45738366d520SMichal Kalderon u32 offset; 4574fe56b9e6SYuval Mintz 4575c78df14eSAriel Elior /* adjust bar offset for second engine */ 45768366d520SMichal Kalderon offset = qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt, 457715582962SRahul Verma BAR_ID_0) / 2; 45788366d520SMichal Kalderon p_regview = cdev->regview + offset; 4579c78df14eSAriel Elior 45808366d520SMichal Kalderon offset = qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt, 458115582962SRahul Verma BAR_ID_1) / 2; 45828366d520SMichal Kalderon 45838366d520SMichal Kalderon p_doorbell = cdev->doorbells + offset; 45848366d520SMichal Kalderon 45858366d520SMichal Kalderon db_phys_addr = cdev->db_phys_addr + offset; 4586c78df14eSAriel Elior 4587c78df14eSAriel Elior /* prepare second hw function */ 4588c78df14eSAriel Elior rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview, 45898366d520SMichal Kalderon p_doorbell, db_phys_addr, 45908366d520SMichal Kalderon personality); 4591c78df14eSAriel Elior 4592c78df14eSAriel Elior /* in case of error, need to free the previously 4593c78df14eSAriel Elior * initiliazed hwfn 0. 4594c78df14eSAriel Elior */ 4595fe56b9e6SYuval Mintz if (rc) { 45961408cc1fSYuval Mintz if (IS_PF(cdev)) { 4597c78df14eSAriel Elior qed_init_free(p_hwfn); 459813cf8aabSSudarsana Reddy Kalluru qed_mcp_nvm_info_free(p_hwfn); 4599c78df14eSAriel Elior qed_mcp_free(p_hwfn); 4600c78df14eSAriel Elior qed_hw_hwfn_free(p_hwfn); 4601fe56b9e6SYuval Mintz } 4602fe56b9e6SYuval Mintz } 46031408cc1fSYuval Mintz } 4604fe56b9e6SYuval Mintz 4605c78df14eSAriel Elior return rc; 4606fe56b9e6SYuval Mintz } 4607fe56b9e6SYuval Mintz 4608fe56b9e6SYuval Mintz void qed_hw_remove(struct qed_dev *cdev) 4609fe56b9e6SYuval Mintz { 46100fefbfbaSSudarsana Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 4611fe56b9e6SYuval Mintz int i; 4612fe56b9e6SYuval Mintz 46130fefbfbaSSudarsana Kalluru if (IS_PF(cdev)) 46140fefbfbaSSudarsana Kalluru qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt, 46150fefbfbaSSudarsana Kalluru QED_OV_DRIVER_STATE_NOT_LOADED); 46160fefbfbaSSudarsana Kalluru 4617fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 4618fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 4619fe56b9e6SYuval Mintz 46201408cc1fSYuval Mintz if (IS_VF(cdev)) { 46210b55e27dSYuval Mintz qed_vf_pf_release(p_hwfn); 46221408cc1fSYuval Mintz continue; 46231408cc1fSYuval Mintz } 46241408cc1fSYuval Mintz 4625fe56b9e6SYuval Mintz qed_init_free(p_hwfn); 4626fe56b9e6SYuval Mintz qed_hw_hwfn_free(p_hwfn); 4627fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 4628fe56b9e6SYuval Mintz } 462932a47e72SYuval Mintz 463032a47e72SYuval Mintz qed_iov_free_hw_info(cdev); 463143645ce0SSudarsana Reddy Kalluru 463213cf8aabSSudarsana Reddy Kalluru qed_mcp_nvm_info_free(p_hwfn); 4633fe56b9e6SYuval Mintz } 4634fe56b9e6SYuval Mintz 4635a91eb52aSYuval Mintz static void qed_chain_free_next_ptr(struct qed_dev *cdev, 4636a91eb52aSYuval Mintz struct qed_chain *p_chain) 4637a91eb52aSYuval Mintz { 4638a91eb52aSYuval Mintz void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL; 4639a91eb52aSYuval Mintz dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0; 4640a91eb52aSYuval Mintz struct qed_chain_next *p_next; 4641a91eb52aSYuval Mintz u32 size, i; 4642a91eb52aSYuval Mintz 4643a91eb52aSYuval Mintz if (!p_virt) 4644a91eb52aSYuval Mintz return; 4645a91eb52aSYuval Mintz 4646a91eb52aSYuval Mintz size = p_chain->elem_size * p_chain->usable_per_page; 4647a91eb52aSYuval Mintz 4648a91eb52aSYuval Mintz for (i = 0; i < p_chain->page_cnt; i++) { 4649a91eb52aSYuval Mintz if (!p_virt) 4650a91eb52aSYuval Mintz break; 4651a91eb52aSYuval Mintz 4652a91eb52aSYuval Mintz p_next = (struct qed_chain_next *)((u8 *)p_virt + size); 4653a91eb52aSYuval Mintz p_virt_next = p_next->next_virt; 4654a91eb52aSYuval Mintz p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys); 4655a91eb52aSYuval Mintz 4656a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 4657a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, p_virt, p_phys); 4658a91eb52aSYuval Mintz 4659a91eb52aSYuval Mintz p_virt = p_virt_next; 4660a91eb52aSYuval Mintz p_phys = p_phys_next; 4661a91eb52aSYuval Mintz } 4662a91eb52aSYuval Mintz } 4663a91eb52aSYuval Mintz 4664a91eb52aSYuval Mintz static void qed_chain_free_single(struct qed_dev *cdev, 4665a91eb52aSYuval Mintz struct qed_chain *p_chain) 4666a91eb52aSYuval Mintz { 4667a91eb52aSYuval Mintz if (!p_chain->p_virt_addr) 4668a91eb52aSYuval Mintz return; 4669a91eb52aSYuval Mintz 4670a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 4671a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 4672a91eb52aSYuval Mintz p_chain->p_virt_addr, p_chain->p_phys_addr); 4673a91eb52aSYuval Mintz } 4674a91eb52aSYuval Mintz 4675a91eb52aSYuval Mintz static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain) 4676a91eb52aSYuval Mintz { 46778063f761SYuval Basson struct addr_tbl_entry *pp_addr_tbl = p_chain->pbl.pp_addr_tbl; 4678a91eb52aSYuval Mintz u32 page_cnt = p_chain->page_cnt, i, pbl_size; 4679a91eb52aSYuval Mintz 46808063f761SYuval Basson if (!pp_addr_tbl) 4681a91eb52aSYuval Mintz return; 4682a91eb52aSYuval Mintz 4683a91eb52aSYuval Mintz for (i = 0; i < page_cnt; i++) { 46848063f761SYuval Basson if (!pp_addr_tbl[i].virt_addr || !pp_addr_tbl[i].dma_map) 4685a91eb52aSYuval Mintz break; 4686a91eb52aSYuval Mintz 4687a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 4688a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 46898063f761SYuval Basson pp_addr_tbl[i].virt_addr, 46908063f761SYuval Basson pp_addr_tbl[i].dma_map); 4691a91eb52aSYuval Mintz } 4692a91eb52aSYuval Mintz 4693a91eb52aSYuval Mintz pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; 46941a4a6975SMintz, Yuval 46951a4a6975SMintz, Yuval if (!p_chain->b_external_pbl) 4696a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 4697a91eb52aSYuval Mintz pbl_size, 46986d937acfSMintz, Yuval p_chain->pbl_sp.p_virt_table, 46996d937acfSMintz, Yuval p_chain->pbl_sp.p_phys_table); 47008063f761SYuval Basson 47018063f761SYuval Basson vfree(p_chain->pbl.pp_addr_tbl); 47028063f761SYuval Basson p_chain->pbl.pp_addr_tbl = NULL; 4703a91eb52aSYuval Mintz } 4704a91eb52aSYuval Mintz 4705a91eb52aSYuval Mintz void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain) 4706a91eb52aSYuval Mintz { 4707a91eb52aSYuval Mintz switch (p_chain->mode) { 4708a91eb52aSYuval Mintz case QED_CHAIN_MODE_NEXT_PTR: 4709a91eb52aSYuval Mintz qed_chain_free_next_ptr(cdev, p_chain); 4710a91eb52aSYuval Mintz break; 4711a91eb52aSYuval Mintz case QED_CHAIN_MODE_SINGLE: 4712a91eb52aSYuval Mintz qed_chain_free_single(cdev, p_chain); 4713a91eb52aSYuval Mintz break; 4714a91eb52aSYuval Mintz case QED_CHAIN_MODE_PBL: 4715a91eb52aSYuval Mintz qed_chain_free_pbl(cdev, p_chain); 4716a91eb52aSYuval Mintz break; 4717a91eb52aSYuval Mintz } 4718a91eb52aSYuval Mintz } 4719a91eb52aSYuval Mintz 4720a91eb52aSYuval Mintz static int 4721a91eb52aSYuval Mintz qed_chain_alloc_sanity_check(struct qed_dev *cdev, 4722a91eb52aSYuval Mintz enum qed_chain_cnt_type cnt_type, 4723a91eb52aSYuval Mintz size_t elem_size, u32 page_cnt) 4724a91eb52aSYuval Mintz { 4725a91eb52aSYuval Mintz u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt; 4726a91eb52aSYuval Mintz 4727a91eb52aSYuval Mintz /* The actual chain size can be larger than the maximal possible value 4728a91eb52aSYuval Mintz * after rounding up the requested elements number to pages, and after 4729a91eb52aSYuval Mintz * taking into acount the unusuable elements (next-ptr elements). 4730a91eb52aSYuval Mintz * The size of a "u16" chain can be (U16_MAX + 1) since the chain 4731a91eb52aSYuval Mintz * size/capacity fields are of a u32 type. 4732a91eb52aSYuval Mintz */ 4733a91eb52aSYuval Mintz if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 && 47343ef310a7STomer Tayar chain_size > ((u32)U16_MAX + 1)) || 47353ef310a7STomer Tayar (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) { 4736a91eb52aSYuval Mintz DP_NOTICE(cdev, 4737a91eb52aSYuval Mintz "The actual chain size (0x%llx) is larger than the maximal possible value\n", 4738a91eb52aSYuval Mintz chain_size); 4739a91eb52aSYuval Mintz return -EINVAL; 4740a91eb52aSYuval Mintz } 4741a91eb52aSYuval Mintz 4742a91eb52aSYuval Mintz return 0; 4743a91eb52aSYuval Mintz } 4744a91eb52aSYuval Mintz 4745a91eb52aSYuval Mintz static int 4746a91eb52aSYuval Mintz qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain) 4747a91eb52aSYuval Mintz { 4748a91eb52aSYuval Mintz void *p_virt = NULL, *p_virt_prev = NULL; 4749a91eb52aSYuval Mintz dma_addr_t p_phys = 0; 4750a91eb52aSYuval Mintz u32 i; 4751a91eb52aSYuval Mintz 4752a91eb52aSYuval Mintz for (i = 0; i < p_chain->page_cnt; i++) { 4753a91eb52aSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 4754a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 4755a91eb52aSYuval Mintz &p_phys, GFP_KERNEL); 47562591c280SJoe Perches if (!p_virt) 4757a91eb52aSYuval Mintz return -ENOMEM; 4758a91eb52aSYuval Mintz 4759a91eb52aSYuval Mintz if (i == 0) { 4760a91eb52aSYuval Mintz qed_chain_init_mem(p_chain, p_virt, p_phys); 4761a91eb52aSYuval Mintz qed_chain_reset(p_chain); 4762a91eb52aSYuval Mintz } else { 4763a91eb52aSYuval Mintz qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, 4764a91eb52aSYuval Mintz p_virt, p_phys); 4765a91eb52aSYuval Mintz } 4766a91eb52aSYuval Mintz 4767a91eb52aSYuval Mintz p_virt_prev = p_virt; 4768a91eb52aSYuval Mintz } 4769a91eb52aSYuval Mintz /* Last page's next element should point to the beginning of the 4770a91eb52aSYuval Mintz * chain. 4771a91eb52aSYuval Mintz */ 4772a91eb52aSYuval Mintz qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, 4773a91eb52aSYuval Mintz p_chain->p_virt_addr, 4774a91eb52aSYuval Mintz p_chain->p_phys_addr); 4775a91eb52aSYuval Mintz 4776a91eb52aSYuval Mintz return 0; 4777a91eb52aSYuval Mintz } 4778a91eb52aSYuval Mintz 4779a91eb52aSYuval Mintz static int 4780a91eb52aSYuval Mintz qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain) 4781a91eb52aSYuval Mintz { 4782a91eb52aSYuval Mintz dma_addr_t p_phys = 0; 4783a91eb52aSYuval Mintz void *p_virt = NULL; 4784a91eb52aSYuval Mintz 4785a91eb52aSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 4786a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL); 47872591c280SJoe Perches if (!p_virt) 4788a91eb52aSYuval Mintz return -ENOMEM; 4789a91eb52aSYuval Mintz 4790a91eb52aSYuval Mintz qed_chain_init_mem(p_chain, p_virt, p_phys); 4791a91eb52aSYuval Mintz qed_chain_reset(p_chain); 4792a91eb52aSYuval Mintz 4793a91eb52aSYuval Mintz return 0; 4794a91eb52aSYuval Mintz } 4795a91eb52aSYuval Mintz 47961a4a6975SMintz, Yuval static int 47971a4a6975SMintz, Yuval qed_chain_alloc_pbl(struct qed_dev *cdev, 47981a4a6975SMintz, Yuval struct qed_chain *p_chain, 47991a4a6975SMintz, Yuval struct qed_chain_ext_pbl *ext_pbl) 4800a91eb52aSYuval Mintz { 4801a91eb52aSYuval Mintz u32 page_cnt = p_chain->page_cnt, size, i; 4802a91eb52aSYuval Mintz dma_addr_t p_phys = 0, p_pbl_phys = 0; 48038063f761SYuval Basson struct addr_tbl_entry *pp_addr_tbl; 4804a91eb52aSYuval Mintz u8 *p_pbl_virt = NULL; 4805a91eb52aSYuval Mintz void *p_virt = NULL; 4806a91eb52aSYuval Mintz 48078063f761SYuval Basson size = page_cnt * sizeof(*pp_addr_tbl); 48088063f761SYuval Basson pp_addr_tbl = vzalloc(size); 48098063f761SYuval Basson if (!pp_addr_tbl) 4810a91eb52aSYuval Mintz return -ENOMEM; 4811a91eb52aSYuval Mintz 4812a91eb52aSYuval Mintz /* The allocation of the PBL table is done with its full size, since it 4813a91eb52aSYuval Mintz * is expected to be successive. 4814a91eb52aSYuval Mintz * qed_chain_init_pbl_mem() is called even in a case of an allocation 48158063f761SYuval Basson * failure, since tbl was previously allocated, and it 4816a91eb52aSYuval Mintz * should be saved to allow its freeing during the error flow. 4817a91eb52aSYuval Mintz */ 4818a91eb52aSYuval Mintz size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; 48191a4a6975SMintz, Yuval 48201a4a6975SMintz, Yuval if (!ext_pbl) { 4821a91eb52aSYuval Mintz p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev, 4822a91eb52aSYuval Mintz size, &p_pbl_phys, GFP_KERNEL); 48231a4a6975SMintz, Yuval } else { 48241a4a6975SMintz, Yuval p_pbl_virt = ext_pbl->p_pbl_virt; 48251a4a6975SMintz, Yuval p_pbl_phys = ext_pbl->p_pbl_phys; 48261a4a6975SMintz, Yuval p_chain->b_external_pbl = true; 48271a4a6975SMintz, Yuval } 48281a4a6975SMintz, Yuval 48298063f761SYuval Basson qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys, pp_addr_tbl); 48302591c280SJoe Perches if (!p_pbl_virt) 4831a91eb52aSYuval Mintz return -ENOMEM; 4832a91eb52aSYuval Mintz 4833a91eb52aSYuval Mintz for (i = 0; i < page_cnt; i++) { 4834a91eb52aSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 4835a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 4836a91eb52aSYuval Mintz &p_phys, GFP_KERNEL); 48372591c280SJoe Perches if (!p_virt) 4838a91eb52aSYuval Mintz return -ENOMEM; 4839a91eb52aSYuval Mintz 4840a91eb52aSYuval Mintz if (i == 0) { 4841a91eb52aSYuval Mintz qed_chain_init_mem(p_chain, p_virt, p_phys); 4842a91eb52aSYuval Mintz qed_chain_reset(p_chain); 4843a91eb52aSYuval Mintz } 4844a91eb52aSYuval Mintz 4845a91eb52aSYuval Mintz /* Fill the PBL table with the physical address of the page */ 4846a91eb52aSYuval Mintz *(dma_addr_t *)p_pbl_virt = p_phys; 4847a91eb52aSYuval Mintz /* Keep the virtual address of the page */ 48488063f761SYuval Basson p_chain->pbl.pp_addr_tbl[i].virt_addr = p_virt; 48498063f761SYuval Basson p_chain->pbl.pp_addr_tbl[i].dma_map = p_phys; 4850a91eb52aSYuval Mintz 4851a91eb52aSYuval Mintz p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE; 4852a91eb52aSYuval Mintz } 4853a91eb52aSYuval Mintz 4854a91eb52aSYuval Mintz return 0; 4855a91eb52aSYuval Mintz } 4856a91eb52aSYuval Mintz 4857fe56b9e6SYuval Mintz int qed_chain_alloc(struct qed_dev *cdev, 4858fe56b9e6SYuval Mintz enum qed_chain_use_mode intended_use, 4859fe56b9e6SYuval Mintz enum qed_chain_mode mode, 4860a91eb52aSYuval Mintz enum qed_chain_cnt_type cnt_type, 48611a4a6975SMintz, Yuval u32 num_elems, 48621a4a6975SMintz, Yuval size_t elem_size, 48631a4a6975SMintz, Yuval struct qed_chain *p_chain, 48641a4a6975SMintz, Yuval struct qed_chain_ext_pbl *ext_pbl) 4865fe56b9e6SYuval Mintz { 4866a91eb52aSYuval Mintz u32 page_cnt; 4867a91eb52aSYuval Mintz int rc = 0; 4868fe56b9e6SYuval Mintz 4869fe56b9e6SYuval Mintz if (mode == QED_CHAIN_MODE_SINGLE) 4870fe56b9e6SYuval Mintz page_cnt = 1; 4871fe56b9e6SYuval Mintz else 4872fe56b9e6SYuval Mintz page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode); 4873fe56b9e6SYuval Mintz 4874a91eb52aSYuval Mintz rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt); 4875a91eb52aSYuval Mintz if (rc) { 4876a91eb52aSYuval Mintz DP_NOTICE(cdev, 48772591c280SJoe Perches "Cannot allocate a chain with the given arguments:\n"); 48782591c280SJoe Perches DP_NOTICE(cdev, 4879a91eb52aSYuval Mintz "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n", 4880a91eb52aSYuval Mintz intended_use, mode, cnt_type, num_elems, elem_size); 4881a91eb52aSYuval Mintz return rc; 4882fe56b9e6SYuval Mintz } 4883fe56b9e6SYuval Mintz 4884a91eb52aSYuval Mintz qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use, 4885a91eb52aSYuval Mintz mode, cnt_type); 4886fe56b9e6SYuval Mintz 4887a91eb52aSYuval Mintz switch (mode) { 4888a91eb52aSYuval Mintz case QED_CHAIN_MODE_NEXT_PTR: 4889a91eb52aSYuval Mintz rc = qed_chain_alloc_next_ptr(cdev, p_chain); 4890a91eb52aSYuval Mintz break; 4891a91eb52aSYuval Mintz case QED_CHAIN_MODE_SINGLE: 4892a91eb52aSYuval Mintz rc = qed_chain_alloc_single(cdev, p_chain); 4893a91eb52aSYuval Mintz break; 4894a91eb52aSYuval Mintz case QED_CHAIN_MODE_PBL: 48951a4a6975SMintz, Yuval rc = qed_chain_alloc_pbl(cdev, p_chain, ext_pbl); 4896a91eb52aSYuval Mintz break; 4897fe56b9e6SYuval Mintz } 4898a91eb52aSYuval Mintz if (rc) 4899a91eb52aSYuval Mintz goto nomem; 4900fe56b9e6SYuval Mintz 4901fe56b9e6SYuval Mintz return 0; 4902fe56b9e6SYuval Mintz 4903fe56b9e6SYuval Mintz nomem: 4904a91eb52aSYuval Mintz qed_chain_free(cdev, p_chain); 4905a91eb52aSYuval Mintz return rc; 4906fe56b9e6SYuval Mintz } 4907fe56b9e6SYuval Mintz 4908a91eb52aSYuval Mintz int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id) 4909cee4d264SManish Chopra { 4910cee4d264SManish Chopra if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) { 4911cee4d264SManish Chopra u16 min, max; 4912cee4d264SManish Chopra 4913cee4d264SManish Chopra min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE); 4914cee4d264SManish Chopra max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE); 4915cee4d264SManish Chopra DP_NOTICE(p_hwfn, 4916cee4d264SManish Chopra "l2_queue id [%d] is not valid, available indices [%d - %d]\n", 4917cee4d264SManish Chopra src_id, min, max); 4918cee4d264SManish Chopra 4919cee4d264SManish Chopra return -EINVAL; 4920cee4d264SManish Chopra } 4921cee4d264SManish Chopra 4922cee4d264SManish Chopra *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id; 4923cee4d264SManish Chopra 4924cee4d264SManish Chopra return 0; 4925cee4d264SManish Chopra } 4926cee4d264SManish Chopra 49271a635e48SYuval Mintz int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id) 4928cee4d264SManish Chopra { 4929cee4d264SManish Chopra if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) { 4930cee4d264SManish Chopra u8 min, max; 4931cee4d264SManish Chopra 4932cee4d264SManish Chopra min = (u8)RESC_START(p_hwfn, QED_VPORT); 4933cee4d264SManish Chopra max = min + RESC_NUM(p_hwfn, QED_VPORT); 4934cee4d264SManish Chopra DP_NOTICE(p_hwfn, 4935cee4d264SManish Chopra "vport id [%d] is not valid, available indices [%d - %d]\n", 4936cee4d264SManish Chopra src_id, min, max); 4937cee4d264SManish Chopra 4938cee4d264SManish Chopra return -EINVAL; 4939cee4d264SManish Chopra } 4940cee4d264SManish Chopra 4941cee4d264SManish Chopra *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id; 4942cee4d264SManish Chopra 4943cee4d264SManish Chopra return 0; 4944cee4d264SManish Chopra } 4945cee4d264SManish Chopra 49461a635e48SYuval Mintz int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id) 4947cee4d264SManish Chopra { 4948cee4d264SManish Chopra if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) { 4949cee4d264SManish Chopra u8 min, max; 4950cee4d264SManish Chopra 4951cee4d264SManish Chopra min = (u8)RESC_START(p_hwfn, QED_RSS_ENG); 4952cee4d264SManish Chopra max = min + RESC_NUM(p_hwfn, QED_RSS_ENG); 4953cee4d264SManish Chopra DP_NOTICE(p_hwfn, 4954cee4d264SManish Chopra "rss_eng id [%d] is not valid, available indices [%d - %d]\n", 4955cee4d264SManish Chopra src_id, min, max); 4956cee4d264SManish Chopra 4957cee4d264SManish Chopra return -EINVAL; 4958cee4d264SManish Chopra } 4959cee4d264SManish Chopra 4960cee4d264SManish Chopra *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id; 4961cee4d264SManish Chopra 4962cee4d264SManish Chopra return 0; 4963cee4d264SManish Chopra } 4964bcd197c8SManish Chopra 4965722003acSSudarsana Reddy Kalluru static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 4966722003acSSudarsana Reddy Kalluru u32 hw_addr, void *p_eth_qzone, 4967722003acSSudarsana Reddy Kalluru size_t eth_qzone_size, u8 timeset) 4968722003acSSudarsana Reddy Kalluru { 4969722003acSSudarsana Reddy Kalluru struct coalescing_timeset *p_coal_timeset; 4970722003acSSudarsana Reddy Kalluru 4971722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) { 4972722003acSSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n"); 4973722003acSSudarsana Reddy Kalluru return -EINVAL; 4974722003acSSudarsana Reddy Kalluru } 4975722003acSSudarsana Reddy Kalluru 4976722003acSSudarsana Reddy Kalluru p_coal_timeset = p_eth_qzone; 4977477f2d14SRahul Verma memset(p_eth_qzone, 0, eth_qzone_size); 4978722003acSSudarsana Reddy Kalluru SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset); 4979722003acSSudarsana Reddy Kalluru SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1); 4980722003acSSudarsana Reddy Kalluru qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size); 4981722003acSSudarsana Reddy Kalluru 4982722003acSSudarsana Reddy Kalluru return 0; 4983722003acSSudarsana Reddy Kalluru } 4984722003acSSudarsana Reddy Kalluru 4985477f2d14SRahul Verma int qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle) 4986477f2d14SRahul Verma { 4987477f2d14SRahul Verma struct qed_queue_cid *p_cid = p_handle; 4988477f2d14SRahul Verma struct qed_hwfn *p_hwfn; 4989477f2d14SRahul Verma struct qed_ptt *p_ptt; 4990477f2d14SRahul Verma int rc = 0; 4991477f2d14SRahul Verma 4992477f2d14SRahul Verma p_hwfn = p_cid->p_owner; 4993477f2d14SRahul Verma 4994477f2d14SRahul Verma if (IS_VF(p_hwfn->cdev)) 4995477f2d14SRahul Verma return qed_vf_pf_set_coalesce(p_hwfn, rx_coal, tx_coal, p_cid); 4996477f2d14SRahul Verma 4997477f2d14SRahul Verma p_ptt = qed_ptt_acquire(p_hwfn); 4998477f2d14SRahul Verma if (!p_ptt) 4999477f2d14SRahul Verma return -EAGAIN; 5000477f2d14SRahul Verma 5001477f2d14SRahul Verma if (rx_coal) { 5002477f2d14SRahul Verma rc = qed_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid); 5003477f2d14SRahul Verma if (rc) 5004477f2d14SRahul Verma goto out; 5005477f2d14SRahul Verma p_hwfn->cdev->rx_coalesce_usecs = rx_coal; 5006477f2d14SRahul Verma } 5007477f2d14SRahul Verma 5008477f2d14SRahul Verma if (tx_coal) { 5009477f2d14SRahul Verma rc = qed_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid); 5010477f2d14SRahul Verma if (rc) 5011477f2d14SRahul Verma goto out; 5012477f2d14SRahul Verma p_hwfn->cdev->tx_coalesce_usecs = tx_coal; 5013477f2d14SRahul Verma } 5014477f2d14SRahul Verma out: 5015477f2d14SRahul Verma qed_ptt_release(p_hwfn, p_ptt); 5016477f2d14SRahul Verma return rc; 5017477f2d14SRahul Verma } 5018477f2d14SRahul Verma 5019477f2d14SRahul Verma int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, 5020477f2d14SRahul Verma struct qed_ptt *p_ptt, 5021477f2d14SRahul Verma u16 coalesce, struct qed_queue_cid *p_cid) 5022722003acSSudarsana Reddy Kalluru { 5023722003acSSudarsana Reddy Kalluru struct ustorm_eth_queue_zone eth_qzone; 5024722003acSSudarsana Reddy Kalluru u8 timeset, timer_res; 5025722003acSSudarsana Reddy Kalluru u32 address; 5026722003acSSudarsana Reddy Kalluru int rc; 5027722003acSSudarsana Reddy Kalluru 5028722003acSSudarsana Reddy Kalluru /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 5029722003acSSudarsana Reddy Kalluru if (coalesce <= 0x7F) { 5030722003acSSudarsana Reddy Kalluru timer_res = 0; 5031722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0xFF) { 5032722003acSSudarsana Reddy Kalluru timer_res = 1; 5033722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0x1FF) { 5034722003acSSudarsana Reddy Kalluru timer_res = 2; 5035722003acSSudarsana Reddy Kalluru } else { 5036722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 5037722003acSSudarsana Reddy Kalluru return -EINVAL; 5038722003acSSudarsana Reddy Kalluru } 5039722003acSSudarsana Reddy Kalluru timeset = (u8)(coalesce >> timer_res); 5040722003acSSudarsana Reddy Kalluru 5041477f2d14SRahul Verma rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, 5042477f2d14SRahul Verma p_cid->sb_igu_id, false); 5043722003acSSudarsana Reddy Kalluru if (rc) 5044722003acSSudarsana Reddy Kalluru goto out; 5045722003acSSudarsana Reddy Kalluru 5046477f2d14SRahul Verma address = BAR0_MAP_REG_USDM_RAM + 5047477f2d14SRahul Verma USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id); 5048722003acSSudarsana Reddy Kalluru 5049722003acSSudarsana Reddy Kalluru rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 5050722003acSSudarsana Reddy Kalluru sizeof(struct ustorm_eth_queue_zone), timeset); 5051722003acSSudarsana Reddy Kalluru if (rc) 5052722003acSSudarsana Reddy Kalluru goto out; 5053722003acSSudarsana Reddy Kalluru 5054722003acSSudarsana Reddy Kalluru out: 5055722003acSSudarsana Reddy Kalluru return rc; 5056722003acSSudarsana Reddy Kalluru } 5057722003acSSudarsana Reddy Kalluru 5058477f2d14SRahul Verma int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, 5059477f2d14SRahul Verma struct qed_ptt *p_ptt, 5060477f2d14SRahul Verma u16 coalesce, struct qed_queue_cid *p_cid) 5061722003acSSudarsana Reddy Kalluru { 5062722003acSSudarsana Reddy Kalluru struct xstorm_eth_queue_zone eth_qzone; 5063722003acSSudarsana Reddy Kalluru u8 timeset, timer_res; 5064722003acSSudarsana Reddy Kalluru u32 address; 5065722003acSSudarsana Reddy Kalluru int rc; 5066722003acSSudarsana Reddy Kalluru 5067722003acSSudarsana Reddy Kalluru /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 5068722003acSSudarsana Reddy Kalluru if (coalesce <= 0x7F) { 5069722003acSSudarsana Reddy Kalluru timer_res = 0; 5070722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0xFF) { 5071722003acSSudarsana Reddy Kalluru timer_res = 1; 5072722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0x1FF) { 5073722003acSSudarsana Reddy Kalluru timer_res = 2; 5074722003acSSudarsana Reddy Kalluru } else { 5075722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 5076722003acSSudarsana Reddy Kalluru return -EINVAL; 5077722003acSSudarsana Reddy Kalluru } 5078722003acSSudarsana Reddy Kalluru timeset = (u8)(coalesce >> timer_res); 5079722003acSSudarsana Reddy Kalluru 5080477f2d14SRahul Verma rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, 5081477f2d14SRahul Verma p_cid->sb_igu_id, true); 5082722003acSSudarsana Reddy Kalluru if (rc) 5083722003acSSudarsana Reddy Kalluru goto out; 5084722003acSSudarsana Reddy Kalluru 5085477f2d14SRahul Verma address = BAR0_MAP_REG_XSDM_RAM + 5086477f2d14SRahul Verma XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id); 5087722003acSSudarsana Reddy Kalluru 5088722003acSSudarsana Reddy Kalluru rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 5089722003acSSudarsana Reddy Kalluru sizeof(struct xstorm_eth_queue_zone), timeset); 5090722003acSSudarsana Reddy Kalluru out: 5091722003acSSudarsana Reddy Kalluru return rc; 5092722003acSSudarsana Reddy Kalluru } 5093722003acSSudarsana Reddy Kalluru 5094bcd197c8SManish Chopra /* Calculate final WFQ values for all vports and configure them. 5095bcd197c8SManish Chopra * After this configuration each vport will have 5096bcd197c8SManish Chopra * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT) 5097bcd197c8SManish Chopra */ 5098bcd197c8SManish Chopra static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 5099bcd197c8SManish Chopra struct qed_ptt *p_ptt, 5100bcd197c8SManish Chopra u32 min_pf_rate) 5101bcd197c8SManish Chopra { 5102bcd197c8SManish Chopra struct init_qm_vport_params *vport_params; 5103bcd197c8SManish Chopra int i; 5104bcd197c8SManish Chopra 5105bcd197c8SManish Chopra vport_params = p_hwfn->qm_info.qm_vport_params; 5106bcd197c8SManish Chopra 5107bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 5108bcd197c8SManish Chopra u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 5109bcd197c8SManish Chopra 511092fae6fbSMichal Kalderon vport_params[i].wfq = (wfq_speed * QED_WFQ_UNIT) / 5111bcd197c8SManish Chopra min_pf_rate; 5112bcd197c8SManish Chopra qed_init_vport_wfq(p_hwfn, p_ptt, 5113bcd197c8SManish Chopra vport_params[i].first_tx_pq_id, 511492fae6fbSMichal Kalderon vport_params[i].wfq); 5115bcd197c8SManish Chopra } 5116bcd197c8SManish Chopra } 5117bcd197c8SManish Chopra 5118bcd197c8SManish Chopra static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn, 5119bcd197c8SManish Chopra u32 min_pf_rate) 5120bcd197c8SManish Chopra 5121bcd197c8SManish Chopra { 5122bcd197c8SManish Chopra int i; 5123bcd197c8SManish Chopra 5124bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) 512592fae6fbSMichal Kalderon p_hwfn->qm_info.qm_vport_params[i].wfq = 1; 5126bcd197c8SManish Chopra } 5127bcd197c8SManish Chopra 5128bcd197c8SManish Chopra static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 5129bcd197c8SManish Chopra struct qed_ptt *p_ptt, 5130bcd197c8SManish Chopra u32 min_pf_rate) 5131bcd197c8SManish Chopra { 5132bcd197c8SManish Chopra struct init_qm_vport_params *vport_params; 5133bcd197c8SManish Chopra int i; 5134bcd197c8SManish Chopra 5135bcd197c8SManish Chopra vport_params = p_hwfn->qm_info.qm_vport_params; 5136bcd197c8SManish Chopra 5137bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 5138bcd197c8SManish Chopra qed_init_wfq_default_param(p_hwfn, min_pf_rate); 5139bcd197c8SManish Chopra qed_init_vport_wfq(p_hwfn, p_ptt, 5140bcd197c8SManish Chopra vport_params[i].first_tx_pq_id, 514192fae6fbSMichal Kalderon vport_params[i].wfq); 5142bcd197c8SManish Chopra } 5143bcd197c8SManish Chopra } 5144bcd197c8SManish Chopra 5145bcd197c8SManish Chopra /* This function performs several validations for WFQ 5146bcd197c8SManish Chopra * configuration and required min rate for a given vport 5147bcd197c8SManish Chopra * 1. req_rate must be greater than one percent of min_pf_rate. 5148bcd197c8SManish Chopra * 2. req_rate should not cause other vports [not configured for WFQ explicitly] 5149bcd197c8SManish Chopra * rates to get less than one percent of min_pf_rate. 5150bcd197c8SManish Chopra * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate. 5151bcd197c8SManish Chopra */ 5152bcd197c8SManish Chopra static int qed_init_wfq_param(struct qed_hwfn *p_hwfn, 51531a635e48SYuval Mintz u16 vport_id, u32 req_rate, u32 min_pf_rate) 5154bcd197c8SManish Chopra { 5155bcd197c8SManish Chopra u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0; 5156bcd197c8SManish Chopra int non_requested_count = 0, req_count = 0, i, num_vports; 5157bcd197c8SManish Chopra 5158bcd197c8SManish Chopra num_vports = p_hwfn->qm_info.num_vports; 5159bcd197c8SManish Chopra 5160bcd197c8SManish Chopra /* Accounting for the vports which are configured for WFQ explicitly */ 5161bcd197c8SManish Chopra for (i = 0; i < num_vports; i++) { 5162bcd197c8SManish Chopra u32 tmp_speed; 5163bcd197c8SManish Chopra 5164bcd197c8SManish Chopra if ((i != vport_id) && 5165bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[i].configured) { 5166bcd197c8SManish Chopra req_count++; 5167bcd197c8SManish Chopra tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 5168bcd197c8SManish Chopra total_req_min_rate += tmp_speed; 5169bcd197c8SManish Chopra } 5170bcd197c8SManish Chopra } 5171bcd197c8SManish Chopra 5172bcd197c8SManish Chopra /* Include current vport data as well */ 5173bcd197c8SManish Chopra req_count++; 5174bcd197c8SManish Chopra total_req_min_rate += req_rate; 5175bcd197c8SManish Chopra non_requested_count = num_vports - req_count; 5176bcd197c8SManish Chopra 5177bcd197c8SManish Chopra if (req_rate < min_pf_rate / QED_WFQ_UNIT) { 5178bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 5179bcd197c8SManish Chopra "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 5180bcd197c8SManish Chopra vport_id, req_rate, min_pf_rate); 5181bcd197c8SManish Chopra return -EINVAL; 5182bcd197c8SManish Chopra } 5183bcd197c8SManish Chopra 5184bcd197c8SManish Chopra if (num_vports > QED_WFQ_UNIT) { 5185bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 5186bcd197c8SManish Chopra "Number of vports is greater than %d\n", 5187bcd197c8SManish Chopra QED_WFQ_UNIT); 5188bcd197c8SManish Chopra return -EINVAL; 5189bcd197c8SManish Chopra } 5190bcd197c8SManish Chopra 5191bcd197c8SManish Chopra if (total_req_min_rate > min_pf_rate) { 5192bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 5193bcd197c8SManish Chopra "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n", 5194bcd197c8SManish Chopra total_req_min_rate, min_pf_rate); 5195bcd197c8SManish Chopra return -EINVAL; 5196bcd197c8SManish Chopra } 5197bcd197c8SManish Chopra 5198bcd197c8SManish Chopra total_left_rate = min_pf_rate - total_req_min_rate; 5199bcd197c8SManish Chopra 5200bcd197c8SManish Chopra left_rate_per_vp = total_left_rate / non_requested_count; 5201bcd197c8SManish Chopra if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) { 5202bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 5203bcd197c8SManish Chopra "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 5204bcd197c8SManish Chopra left_rate_per_vp, min_pf_rate); 5205bcd197c8SManish Chopra return -EINVAL; 5206bcd197c8SManish Chopra } 5207bcd197c8SManish Chopra 5208bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate; 5209bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[vport_id].configured = true; 5210bcd197c8SManish Chopra 5211bcd197c8SManish Chopra for (i = 0; i < num_vports; i++) { 5212bcd197c8SManish Chopra if (p_hwfn->qm_info.wfq_data[i].configured) 5213bcd197c8SManish Chopra continue; 5214bcd197c8SManish Chopra 5215bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp; 5216bcd197c8SManish Chopra } 5217bcd197c8SManish Chopra 5218bcd197c8SManish Chopra return 0; 5219bcd197c8SManish Chopra } 5220bcd197c8SManish Chopra 5221733def6aSYuval Mintz static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn, 5222733def6aSYuval Mintz struct qed_ptt *p_ptt, u16 vp_id, u32 rate) 5223733def6aSYuval Mintz { 5224733def6aSYuval Mintz struct qed_mcp_link_state *p_link; 5225733def6aSYuval Mintz int rc = 0; 5226733def6aSYuval Mintz 5227733def6aSYuval Mintz p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output; 5228733def6aSYuval Mintz 5229733def6aSYuval Mintz if (!p_link->min_pf_rate) { 5230733def6aSYuval Mintz p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate; 5231733def6aSYuval Mintz p_hwfn->qm_info.wfq_data[vp_id].configured = true; 5232733def6aSYuval Mintz return rc; 5233733def6aSYuval Mintz } 5234733def6aSYuval Mintz 5235733def6aSYuval Mintz rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate); 5236733def6aSYuval Mintz 52371a635e48SYuval Mintz if (!rc) 5238733def6aSYuval Mintz qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, 5239733def6aSYuval Mintz p_link->min_pf_rate); 5240733def6aSYuval Mintz else 5241733def6aSYuval Mintz DP_NOTICE(p_hwfn, 5242733def6aSYuval Mintz "Validation failed while configuring min rate\n"); 5243733def6aSYuval Mintz 5244733def6aSYuval Mintz return rc; 5245733def6aSYuval Mintz } 5246733def6aSYuval Mintz 5247bcd197c8SManish Chopra static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn, 5248bcd197c8SManish Chopra struct qed_ptt *p_ptt, 5249bcd197c8SManish Chopra u32 min_pf_rate) 5250bcd197c8SManish Chopra { 5251bcd197c8SManish Chopra bool use_wfq = false; 5252bcd197c8SManish Chopra int rc = 0; 5253bcd197c8SManish Chopra u16 i; 5254bcd197c8SManish Chopra 5255bcd197c8SManish Chopra /* Validate all pre configured vports for wfq */ 5256bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 5257bcd197c8SManish Chopra u32 rate; 5258bcd197c8SManish Chopra 5259bcd197c8SManish Chopra if (!p_hwfn->qm_info.wfq_data[i].configured) 5260bcd197c8SManish Chopra continue; 5261bcd197c8SManish Chopra 5262bcd197c8SManish Chopra rate = p_hwfn->qm_info.wfq_data[i].min_speed; 5263bcd197c8SManish Chopra use_wfq = true; 5264bcd197c8SManish Chopra 5265bcd197c8SManish Chopra rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate); 5266bcd197c8SManish Chopra if (rc) { 5267bcd197c8SManish Chopra DP_NOTICE(p_hwfn, 5268bcd197c8SManish Chopra "WFQ validation failed while configuring min rate\n"); 5269bcd197c8SManish Chopra break; 5270bcd197c8SManish Chopra } 5271bcd197c8SManish Chopra } 5272bcd197c8SManish Chopra 5273bcd197c8SManish Chopra if (!rc && use_wfq) 5274bcd197c8SManish Chopra qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 5275bcd197c8SManish Chopra else 5276bcd197c8SManish Chopra qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 5277bcd197c8SManish Chopra 5278bcd197c8SManish Chopra return rc; 5279bcd197c8SManish Chopra } 5280bcd197c8SManish Chopra 5281733def6aSYuval Mintz /* Main API for qed clients to configure vport min rate. 5282733def6aSYuval Mintz * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)] 5283733def6aSYuval Mintz * rate - Speed in Mbps needs to be assigned to a given vport. 5284733def6aSYuval Mintz */ 5285733def6aSYuval Mintz int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate) 5286733def6aSYuval Mintz { 5287733def6aSYuval Mintz int i, rc = -EINVAL; 5288733def6aSYuval Mintz 5289733def6aSYuval Mintz /* Currently not supported; Might change in future */ 5290733def6aSYuval Mintz if (cdev->num_hwfns > 1) { 5291733def6aSYuval Mintz DP_NOTICE(cdev, 5292733def6aSYuval Mintz "WFQ configuration is not supported for this device\n"); 5293733def6aSYuval Mintz return rc; 5294733def6aSYuval Mintz } 5295733def6aSYuval Mintz 5296733def6aSYuval Mintz for_each_hwfn(cdev, i) { 5297733def6aSYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 5298733def6aSYuval Mintz struct qed_ptt *p_ptt; 5299733def6aSYuval Mintz 5300733def6aSYuval Mintz p_ptt = qed_ptt_acquire(p_hwfn); 5301733def6aSYuval Mintz if (!p_ptt) 5302733def6aSYuval Mintz return -EBUSY; 5303733def6aSYuval Mintz 5304733def6aSYuval Mintz rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate); 5305733def6aSYuval Mintz 5306d572c430SYuval Mintz if (rc) { 5307733def6aSYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 5308733def6aSYuval Mintz return rc; 5309733def6aSYuval Mintz } 5310733def6aSYuval Mintz 5311733def6aSYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 5312733def6aSYuval Mintz } 5313733def6aSYuval Mintz 5314733def6aSYuval Mintz return rc; 5315733def6aSYuval Mintz } 5316733def6aSYuval Mintz 5317bcd197c8SManish Chopra /* API to configure WFQ from mcp link change */ 53186f437d43SMintz, Yuval void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, 53196f437d43SMintz, Yuval struct qed_ptt *p_ptt, u32 min_pf_rate) 5320bcd197c8SManish Chopra { 5321bcd197c8SManish Chopra int i; 5322bcd197c8SManish Chopra 53233e7cfce2SYuval Mintz if (cdev->num_hwfns > 1) { 53243e7cfce2SYuval Mintz DP_VERBOSE(cdev, 53253e7cfce2SYuval Mintz NETIF_MSG_LINK, 53263e7cfce2SYuval Mintz "WFQ configuration is not supported for this device\n"); 53273e7cfce2SYuval Mintz return; 53283e7cfce2SYuval Mintz } 53293e7cfce2SYuval Mintz 5330bcd197c8SManish Chopra for_each_hwfn(cdev, i) { 5331bcd197c8SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 5332bcd197c8SManish Chopra 53336f437d43SMintz, Yuval __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt, 5334bcd197c8SManish Chopra min_pf_rate); 5335bcd197c8SManish Chopra } 5336bcd197c8SManish Chopra } 53374b01e519SManish Chopra 53384b01e519SManish Chopra int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn, 53394b01e519SManish Chopra struct qed_ptt *p_ptt, 53404b01e519SManish Chopra struct qed_mcp_link_state *p_link, 53414b01e519SManish Chopra u8 max_bw) 53424b01e519SManish Chopra { 53434b01e519SManish Chopra int rc = 0; 53444b01e519SManish Chopra 53454b01e519SManish Chopra p_hwfn->mcp_info->func_info.bandwidth_max = max_bw; 53464b01e519SManish Chopra 53474b01e519SManish Chopra if (!p_link->line_speed && (max_bw != 100)) 53484b01e519SManish Chopra return rc; 53494b01e519SManish Chopra 53504b01e519SManish Chopra p_link->speed = (p_link->line_speed * max_bw) / 100; 53514b01e519SManish Chopra p_hwfn->qm_info.pf_rl = p_link->speed; 53524b01e519SManish Chopra 53534b01e519SManish Chopra /* Since the limiter also affects Tx-switched traffic, we don't want it 53544b01e519SManish Chopra * to limit such traffic in case there's no actual limit. 53554b01e519SManish Chopra * In that case, set limit to imaginary high boundary. 53564b01e519SManish Chopra */ 53574b01e519SManish Chopra if (max_bw == 100) 53584b01e519SManish Chopra p_hwfn->qm_info.pf_rl = 100000; 53594b01e519SManish Chopra 53604b01e519SManish Chopra rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, 53614b01e519SManish Chopra p_hwfn->qm_info.pf_rl); 53624b01e519SManish Chopra 53634b01e519SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 53644b01e519SManish Chopra "Configured MAX bandwidth to be %08x Mb/sec\n", 53654b01e519SManish Chopra p_link->speed); 53664b01e519SManish Chopra 53674b01e519SManish Chopra return rc; 53684b01e519SManish Chopra } 53694b01e519SManish Chopra 53704b01e519SManish Chopra /* Main API to configure PF max bandwidth where bw range is [1 - 100] */ 53714b01e519SManish Chopra int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw) 53724b01e519SManish Chopra { 53734b01e519SManish Chopra int i, rc = -EINVAL; 53744b01e519SManish Chopra 53754b01e519SManish Chopra if (max_bw < 1 || max_bw > 100) { 53764b01e519SManish Chopra DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n"); 53774b01e519SManish Chopra return rc; 53784b01e519SManish Chopra } 53794b01e519SManish Chopra 53804b01e519SManish Chopra for_each_hwfn(cdev, i) { 53814b01e519SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 53824b01e519SManish Chopra struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 53834b01e519SManish Chopra struct qed_mcp_link_state *p_link; 53844b01e519SManish Chopra struct qed_ptt *p_ptt; 53854b01e519SManish Chopra 53864b01e519SManish Chopra p_link = &p_lead->mcp_info->link_output; 53874b01e519SManish Chopra 53884b01e519SManish Chopra p_ptt = qed_ptt_acquire(p_hwfn); 53894b01e519SManish Chopra if (!p_ptt) 53904b01e519SManish Chopra return -EBUSY; 53914b01e519SManish Chopra 53924b01e519SManish Chopra rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, 53934b01e519SManish Chopra p_link, max_bw); 53944b01e519SManish Chopra 53954b01e519SManish Chopra qed_ptt_release(p_hwfn, p_ptt); 53964b01e519SManish Chopra 53974b01e519SManish Chopra if (rc) 53984b01e519SManish Chopra break; 53994b01e519SManish Chopra } 54004b01e519SManish Chopra 54014b01e519SManish Chopra return rc; 54024b01e519SManish Chopra } 5403a64b02d5SManish Chopra 5404a64b02d5SManish Chopra int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn, 5405a64b02d5SManish Chopra struct qed_ptt *p_ptt, 5406a64b02d5SManish Chopra struct qed_mcp_link_state *p_link, 5407a64b02d5SManish Chopra u8 min_bw) 5408a64b02d5SManish Chopra { 5409a64b02d5SManish Chopra int rc = 0; 5410a64b02d5SManish Chopra 5411a64b02d5SManish Chopra p_hwfn->mcp_info->func_info.bandwidth_min = min_bw; 5412a64b02d5SManish Chopra p_hwfn->qm_info.pf_wfq = min_bw; 5413a64b02d5SManish Chopra 5414a64b02d5SManish Chopra if (!p_link->line_speed) 5415a64b02d5SManish Chopra return rc; 5416a64b02d5SManish Chopra 5417a64b02d5SManish Chopra p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100; 5418a64b02d5SManish Chopra 5419a64b02d5SManish Chopra rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw); 5420a64b02d5SManish Chopra 5421a64b02d5SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 5422a64b02d5SManish Chopra "Configured MIN bandwidth to be %d Mb/sec\n", 5423a64b02d5SManish Chopra p_link->min_pf_rate); 5424a64b02d5SManish Chopra 5425a64b02d5SManish Chopra return rc; 5426a64b02d5SManish Chopra } 5427a64b02d5SManish Chopra 5428a64b02d5SManish Chopra /* Main API to configure PF min bandwidth where bw range is [1-100] */ 5429a64b02d5SManish Chopra int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw) 5430a64b02d5SManish Chopra { 5431a64b02d5SManish Chopra int i, rc = -EINVAL; 5432a64b02d5SManish Chopra 5433a64b02d5SManish Chopra if (min_bw < 1 || min_bw > 100) { 5434a64b02d5SManish Chopra DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n"); 5435a64b02d5SManish Chopra return rc; 5436a64b02d5SManish Chopra } 5437a64b02d5SManish Chopra 5438a64b02d5SManish Chopra for_each_hwfn(cdev, i) { 5439a64b02d5SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 5440a64b02d5SManish Chopra struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 5441a64b02d5SManish Chopra struct qed_mcp_link_state *p_link; 5442a64b02d5SManish Chopra struct qed_ptt *p_ptt; 5443a64b02d5SManish Chopra 5444a64b02d5SManish Chopra p_link = &p_lead->mcp_info->link_output; 5445a64b02d5SManish Chopra 5446a64b02d5SManish Chopra p_ptt = qed_ptt_acquire(p_hwfn); 5447a64b02d5SManish Chopra if (!p_ptt) 5448a64b02d5SManish Chopra return -EBUSY; 5449a64b02d5SManish Chopra 5450a64b02d5SManish Chopra rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, 5451a64b02d5SManish Chopra p_link, min_bw); 5452a64b02d5SManish Chopra if (rc) { 5453a64b02d5SManish Chopra qed_ptt_release(p_hwfn, p_ptt); 5454a64b02d5SManish Chopra return rc; 5455a64b02d5SManish Chopra } 5456a64b02d5SManish Chopra 5457a64b02d5SManish Chopra if (p_link->min_pf_rate) { 5458a64b02d5SManish Chopra u32 min_rate = p_link->min_pf_rate; 5459a64b02d5SManish Chopra 5460a64b02d5SManish Chopra rc = __qed_configure_vp_wfq_on_link_change(p_hwfn, 5461a64b02d5SManish Chopra p_ptt, 5462a64b02d5SManish Chopra min_rate); 5463a64b02d5SManish Chopra } 5464a64b02d5SManish Chopra 5465a64b02d5SManish Chopra qed_ptt_release(p_hwfn, p_ptt); 5466a64b02d5SManish Chopra } 5467a64b02d5SManish Chopra 5468a64b02d5SManish Chopra return rc; 5469a64b02d5SManish Chopra } 5470733def6aSYuval Mintz 5471733def6aSYuval Mintz void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 5472733def6aSYuval Mintz { 5473733def6aSYuval Mintz struct qed_mcp_link_state *p_link; 5474733def6aSYuval Mintz 5475733def6aSYuval Mintz p_link = &p_hwfn->mcp_info->link_output; 5476733def6aSYuval Mintz 5477733def6aSYuval Mintz if (p_link->min_pf_rate) 5478733def6aSYuval Mintz qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, 5479733def6aSYuval Mintz p_link->min_pf_rate); 5480733def6aSYuval Mintz 5481733def6aSYuval Mintz memset(p_hwfn->qm_info.wfq_data, 0, 5482733def6aSYuval Mintz sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports); 5483733def6aSYuval Mintz } 54849c79ddaaSMintz, Yuval 54850ebcebbeSSudarsana Reddy Kalluru int qed_device_num_ports(struct qed_dev *cdev) 54869c79ddaaSMintz, Yuval { 54870ebcebbeSSudarsana Reddy Kalluru return cdev->num_ports; 5488db82f70eSsudarsana.kalluru@cavium.com } 5489456a5849SKalderon, Michal 5490456a5849SKalderon, Michal void qed_set_fw_mac_addr(__le16 *fw_msb, 5491456a5849SKalderon, Michal __le16 *fw_mid, __le16 *fw_lsb, u8 *mac) 5492456a5849SKalderon, Michal { 5493456a5849SKalderon, Michal ((u8 *)fw_msb)[0] = mac[1]; 5494456a5849SKalderon, Michal ((u8 *)fw_msb)[1] = mac[0]; 5495456a5849SKalderon, Michal ((u8 *)fw_mid)[0] = mac[3]; 5496456a5849SKalderon, Michal ((u8 *)fw_mid)[1] = mac[2]; 5497456a5849SKalderon, Michal ((u8 *)fw_lsb)[0] = mac[5]; 5498456a5849SKalderon, Michal ((u8 *)fw_lsb)[1] = mac[4]; 5499456a5849SKalderon, Michal } 5500