1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #include <linux/types.h> 34fe56b9e6SYuval Mintz #include <asm/byteorder.h> 35fe56b9e6SYuval Mintz #include <linux/io.h> 36fe56b9e6SYuval Mintz #include <linux/delay.h> 37fe56b9e6SYuval Mintz #include <linux/dma-mapping.h> 38fe56b9e6SYuval Mintz #include <linux/errno.h> 39fe56b9e6SYuval Mintz #include <linux/kernel.h> 40fe56b9e6SYuval Mintz #include <linux/mutex.h> 41fe56b9e6SYuval Mintz #include <linux/pci.h> 42fe56b9e6SYuval Mintz #include <linux/slab.h> 43fe56b9e6SYuval Mintz #include <linux/string.h> 44a91eb52aSYuval Mintz #include <linux/vmalloc.h> 45fe56b9e6SYuval Mintz #include <linux/etherdevice.h> 46fe56b9e6SYuval Mintz #include <linux/qed/qed_chain.h> 47fe56b9e6SYuval Mintz #include <linux/qed/qed_if.h> 48fe56b9e6SYuval Mintz #include "qed.h" 49fe56b9e6SYuval Mintz #include "qed_cxt.h" 5039651abdSSudarsana Reddy Kalluru #include "qed_dcbx.h" 51fe56b9e6SYuval Mintz #include "qed_dev_api.h" 521e128c81SArun Easi #include "qed_fcoe.h" 53fe56b9e6SYuval Mintz #include "qed_hsi.h" 54fe56b9e6SYuval Mintz #include "qed_hw.h" 55fe56b9e6SYuval Mintz #include "qed_init_ops.h" 56fe56b9e6SYuval Mintz #include "qed_int.h" 57fc831825SYuval Mintz #include "qed_iscsi.h" 580a7fb11cSYuval Mintz #include "qed_ll2.h" 59fe56b9e6SYuval Mintz #include "qed_mcp.h" 601d6cff4fSYuval Mintz #include "qed_ooo.h" 61fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 62fe56b9e6SYuval Mintz #include "qed_sp.h" 6332a47e72SYuval Mintz #include "qed_sriov.h" 640b55e27dSYuval Mintz #include "qed_vf.h" 65b71b9afdSKalderon, Michal #include "qed_rdma.h" 66fe56b9e6SYuval Mintz 670caf5b26SWei Yongjun static DEFINE_SPINLOCK(qm_lock); 6839651abdSSudarsana Reddy Kalluru 6951ff1725SRam Amrani #define QED_MIN_DPIS (4) 7051ff1725SRam Amrani #define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS) 7151ff1725SRam Amrani 7215582962SRahul Verma static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, 7315582962SRahul Verma struct qed_ptt *p_ptt, enum BAR_ID bar_id) 74c2035eeaSRam Amrani { 75c2035eeaSRam Amrani u32 bar_reg = (bar_id == BAR_ID_0 ? 76c2035eeaSRam Amrani PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE); 771408cc1fSYuval Mintz u32 val; 78c2035eeaSRam Amrani 791408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 801a850bfcSMintz, Yuval return qed_vf_hw_bar_size(p_hwfn, bar_id); 811408cc1fSYuval Mintz 8215582962SRahul Verma val = qed_rd(p_hwfn, p_ptt, bar_reg); 83c2035eeaSRam Amrani if (val) 84c2035eeaSRam Amrani return 1 << (val + 15); 85c2035eeaSRam Amrani 86c2035eeaSRam Amrani /* Old MFW initialized above registered only conditionally */ 87c2035eeaSRam Amrani if (p_hwfn->cdev->num_hwfns > 1) { 88c2035eeaSRam Amrani DP_INFO(p_hwfn, 89c2035eeaSRam Amrani "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n"); 90c2035eeaSRam Amrani return BAR_ID_0 ? 256 * 1024 : 512 * 1024; 91c2035eeaSRam Amrani } else { 92c2035eeaSRam Amrani DP_INFO(p_hwfn, 93c2035eeaSRam Amrani "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n"); 94c2035eeaSRam Amrani return 512 * 1024; 95c2035eeaSRam Amrani } 96c2035eeaSRam Amrani } 97c2035eeaSRam Amrani 981a635e48SYuval Mintz void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level) 99fe56b9e6SYuval Mintz { 100fe56b9e6SYuval Mintz u32 i; 101fe56b9e6SYuval Mintz 102fe56b9e6SYuval Mintz cdev->dp_level = dp_level; 103fe56b9e6SYuval Mintz cdev->dp_module = dp_module; 104fe56b9e6SYuval Mintz for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 105fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 106fe56b9e6SYuval Mintz 107fe56b9e6SYuval Mintz p_hwfn->dp_level = dp_level; 108fe56b9e6SYuval Mintz p_hwfn->dp_module = dp_module; 109fe56b9e6SYuval Mintz } 110fe56b9e6SYuval Mintz } 111fe56b9e6SYuval Mintz 112fe56b9e6SYuval Mintz void qed_init_struct(struct qed_dev *cdev) 113fe56b9e6SYuval Mintz { 114fe56b9e6SYuval Mintz u8 i; 115fe56b9e6SYuval Mintz 116fe56b9e6SYuval Mintz for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 117fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 118fe56b9e6SYuval Mintz 119fe56b9e6SYuval Mintz p_hwfn->cdev = cdev; 120fe56b9e6SYuval Mintz p_hwfn->my_id = i; 121fe56b9e6SYuval Mintz p_hwfn->b_active = false; 122fe56b9e6SYuval Mintz 123fe56b9e6SYuval Mintz mutex_init(&p_hwfn->dmae_info.mutex); 124fe56b9e6SYuval Mintz } 125fe56b9e6SYuval Mintz 126fe56b9e6SYuval Mintz /* hwfn 0 is always active */ 127fe56b9e6SYuval Mintz cdev->hwfns[0].b_active = true; 128fe56b9e6SYuval Mintz 129fe56b9e6SYuval Mintz /* set the default cache alignment to 128 */ 130fe56b9e6SYuval Mintz cdev->cache_shift = 7; 131fe56b9e6SYuval Mintz } 132fe56b9e6SYuval Mintz 133fe56b9e6SYuval Mintz static void qed_qm_info_free(struct qed_hwfn *p_hwfn) 134fe56b9e6SYuval Mintz { 135fe56b9e6SYuval Mintz struct qed_qm_info *qm_info = &p_hwfn->qm_info; 136fe56b9e6SYuval Mintz 137fe56b9e6SYuval Mintz kfree(qm_info->qm_pq_params); 138fe56b9e6SYuval Mintz qm_info->qm_pq_params = NULL; 139fe56b9e6SYuval Mintz kfree(qm_info->qm_vport_params); 140fe56b9e6SYuval Mintz qm_info->qm_vport_params = NULL; 141fe56b9e6SYuval Mintz kfree(qm_info->qm_port_params); 142fe56b9e6SYuval Mintz qm_info->qm_port_params = NULL; 143bcd197c8SManish Chopra kfree(qm_info->wfq_data); 144bcd197c8SManish Chopra qm_info->wfq_data = NULL; 145fe56b9e6SYuval Mintz } 146fe56b9e6SYuval Mintz 147fe56b9e6SYuval Mintz void qed_resc_free(struct qed_dev *cdev) 148fe56b9e6SYuval Mintz { 149fe56b9e6SYuval Mintz int i; 150fe56b9e6SYuval Mintz 1510db711bbSMintz, Yuval if (IS_VF(cdev)) { 1520db711bbSMintz, Yuval for_each_hwfn(cdev, i) 1530db711bbSMintz, Yuval qed_l2_free(&cdev->hwfns[i]); 1541408cc1fSYuval Mintz return; 1550db711bbSMintz, Yuval } 1561408cc1fSYuval Mintz 157fe56b9e6SYuval Mintz kfree(cdev->fw_data); 158fe56b9e6SYuval Mintz cdev->fw_data = NULL; 159fe56b9e6SYuval Mintz 160fe56b9e6SYuval Mintz kfree(cdev->reset_stats); 1613587cb87STomer Tayar cdev->reset_stats = NULL; 162fe56b9e6SYuval Mintz 163fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 164fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 165fe56b9e6SYuval Mintz 166fe56b9e6SYuval Mintz qed_cxt_mngr_free(p_hwfn); 167fe56b9e6SYuval Mintz qed_qm_info_free(p_hwfn); 168fe56b9e6SYuval Mintz qed_spq_free(p_hwfn); 1693587cb87STomer Tayar qed_eq_free(p_hwfn); 1703587cb87STomer Tayar qed_consq_free(p_hwfn); 171fe56b9e6SYuval Mintz qed_int_free(p_hwfn); 1720a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 1733587cb87STomer Tayar qed_ll2_free(p_hwfn); 1740a7fb11cSYuval Mintz #endif 1751e128c81SArun Easi if (p_hwfn->hw_info.personality == QED_PCI_FCOE) 1763587cb87STomer Tayar qed_fcoe_free(p_hwfn); 1771e128c81SArun Easi 1781d6cff4fSYuval Mintz if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 1793587cb87STomer Tayar qed_iscsi_free(p_hwfn); 1803587cb87STomer Tayar qed_ooo_free(p_hwfn); 1811d6cff4fSYuval Mintz } 18232a47e72SYuval Mintz qed_iov_free(p_hwfn); 1830db711bbSMintz, Yuval qed_l2_free(p_hwfn); 184fe56b9e6SYuval Mintz qed_dmae_info_free(p_hwfn); 185270837b3Ssudarsana.kalluru@cavium.com qed_dcbx_info_free(p_hwfn); 186fe56b9e6SYuval Mintz } 187fe56b9e6SYuval Mintz } 188fe56b9e6SYuval Mintz 189b5a9ee7cSAriel Elior /******************** QM initialization *******************/ 190b5a9ee7cSAriel Elior #define ACTIVE_TCS_BMAP 0x9f 191b5a9ee7cSAriel Elior #define ACTIVE_TCS_BMAP_4PORT_K2 0xf 192b5a9ee7cSAriel Elior 193b5a9ee7cSAriel Elior /* determines the physical queue flags for a given PF. */ 194b5a9ee7cSAriel Elior static u32 qed_get_pq_flags(struct qed_hwfn *p_hwfn) 195fe56b9e6SYuval Mintz { 196b5a9ee7cSAriel Elior u32 flags; 197fe56b9e6SYuval Mintz 198b5a9ee7cSAriel Elior /* common flags */ 199b5a9ee7cSAriel Elior flags = PQ_FLAGS_LB; 200fe56b9e6SYuval Mintz 201b5a9ee7cSAriel Elior /* feature flags */ 202b5a9ee7cSAriel Elior if (IS_QED_SRIOV(p_hwfn->cdev)) 203b5a9ee7cSAriel Elior flags |= PQ_FLAGS_VFS; 204fe56b9e6SYuval Mintz 205b5a9ee7cSAriel Elior /* protocol flags */ 206b5a9ee7cSAriel Elior switch (p_hwfn->hw_info.personality) { 207b5a9ee7cSAriel Elior case QED_PCI_ETH: 208b5a9ee7cSAriel Elior flags |= PQ_FLAGS_MCOS; 209b5a9ee7cSAriel Elior break; 210b5a9ee7cSAriel Elior case QED_PCI_FCOE: 211b5a9ee7cSAriel Elior flags |= PQ_FLAGS_OFLD; 212b5a9ee7cSAriel Elior break; 213b5a9ee7cSAriel Elior case QED_PCI_ISCSI: 214b5a9ee7cSAriel Elior flags |= PQ_FLAGS_ACK | PQ_FLAGS_OOO | PQ_FLAGS_OFLD; 215b5a9ee7cSAriel Elior break; 216b5a9ee7cSAriel Elior case QED_PCI_ETH_ROCE: 217b5a9ee7cSAriel Elior flags |= PQ_FLAGS_MCOS | PQ_FLAGS_OFLD | PQ_FLAGS_LLT; 218b5a9ee7cSAriel Elior break; 21993c45984SKalderon, Michal case QED_PCI_ETH_IWARP: 22093c45984SKalderon, Michal flags |= PQ_FLAGS_MCOS | PQ_FLAGS_ACK | PQ_FLAGS_OOO | 22193c45984SKalderon, Michal PQ_FLAGS_OFLD; 22293c45984SKalderon, Michal break; 223b5a9ee7cSAriel Elior default: 224fe56b9e6SYuval Mintz DP_ERR(p_hwfn, 225b5a9ee7cSAriel Elior "unknown personality %d\n", p_hwfn->hw_info.personality); 226b5a9ee7cSAriel Elior return 0; 227fe56b9e6SYuval Mintz } 228fe56b9e6SYuval Mintz 229b5a9ee7cSAriel Elior return flags; 230b5a9ee7cSAriel Elior } 231b5a9ee7cSAriel Elior 232b5a9ee7cSAriel Elior /* Getters for resource amounts necessary for qm initialization */ 233b5a9ee7cSAriel Elior u8 qed_init_qm_get_num_tcs(struct qed_hwfn *p_hwfn) 234b5a9ee7cSAriel Elior { 235b5a9ee7cSAriel Elior return p_hwfn->hw_info.num_hw_tc; 236b5a9ee7cSAriel Elior } 237b5a9ee7cSAriel Elior 238b5a9ee7cSAriel Elior u16 qed_init_qm_get_num_vfs(struct qed_hwfn *p_hwfn) 239b5a9ee7cSAriel Elior { 240b5a9ee7cSAriel Elior return IS_QED_SRIOV(p_hwfn->cdev) ? 241b5a9ee7cSAriel Elior p_hwfn->cdev->p_iov_info->total_vfs : 0; 242b5a9ee7cSAriel Elior } 243b5a9ee7cSAriel Elior 244b5a9ee7cSAriel Elior #define NUM_DEFAULT_RLS 1 245b5a9ee7cSAriel Elior 246b5a9ee7cSAriel Elior u16 qed_init_qm_get_num_pf_rls(struct qed_hwfn *p_hwfn) 247b5a9ee7cSAriel Elior { 248b5a9ee7cSAriel Elior u16 num_pf_rls, num_vfs = qed_init_qm_get_num_vfs(p_hwfn); 249b5a9ee7cSAriel Elior 250b5a9ee7cSAriel Elior /* num RLs can't exceed resource amount of rls or vports */ 251b5a9ee7cSAriel Elior num_pf_rls = (u16) min_t(u32, RESC_NUM(p_hwfn, QED_RL), 252b5a9ee7cSAriel Elior RESC_NUM(p_hwfn, QED_VPORT)); 253b5a9ee7cSAriel Elior 254b5a9ee7cSAriel Elior /* Make sure after we reserve there's something left */ 255b5a9ee7cSAriel Elior if (num_pf_rls < num_vfs + NUM_DEFAULT_RLS) 256b5a9ee7cSAriel Elior return 0; 257b5a9ee7cSAriel Elior 258b5a9ee7cSAriel Elior /* subtract rls necessary for VFs and one default one for the PF */ 259b5a9ee7cSAriel Elior num_pf_rls -= num_vfs + NUM_DEFAULT_RLS; 260b5a9ee7cSAriel Elior 261b5a9ee7cSAriel Elior return num_pf_rls; 262b5a9ee7cSAriel Elior } 263b5a9ee7cSAriel Elior 264b5a9ee7cSAriel Elior u16 qed_init_qm_get_num_vports(struct qed_hwfn *p_hwfn) 265b5a9ee7cSAriel Elior { 266b5a9ee7cSAriel Elior u32 pq_flags = qed_get_pq_flags(p_hwfn); 267b5a9ee7cSAriel Elior 268b5a9ee7cSAriel Elior /* all pqs share the same vport, except for vfs and pf_rl pqs */ 269b5a9ee7cSAriel Elior return (!!(PQ_FLAGS_RLS & pq_flags)) * 270b5a9ee7cSAriel Elior qed_init_qm_get_num_pf_rls(p_hwfn) + 271b5a9ee7cSAriel Elior (!!(PQ_FLAGS_VFS & pq_flags)) * 272b5a9ee7cSAriel Elior qed_init_qm_get_num_vfs(p_hwfn) + 1; 273b5a9ee7cSAriel Elior } 274b5a9ee7cSAriel Elior 275b5a9ee7cSAriel Elior /* calc amount of PQs according to the requested flags */ 276b5a9ee7cSAriel Elior u16 qed_init_qm_get_num_pqs(struct qed_hwfn *p_hwfn) 277b5a9ee7cSAriel Elior { 278b5a9ee7cSAriel Elior u32 pq_flags = qed_get_pq_flags(p_hwfn); 279b5a9ee7cSAriel Elior 280b5a9ee7cSAriel Elior return (!!(PQ_FLAGS_RLS & pq_flags)) * 281b5a9ee7cSAriel Elior qed_init_qm_get_num_pf_rls(p_hwfn) + 282b5a9ee7cSAriel Elior (!!(PQ_FLAGS_MCOS & pq_flags)) * 283b5a9ee7cSAriel Elior qed_init_qm_get_num_tcs(p_hwfn) + 284b5a9ee7cSAriel Elior (!!(PQ_FLAGS_LB & pq_flags)) + (!!(PQ_FLAGS_OOO & pq_flags)) + 285b5a9ee7cSAriel Elior (!!(PQ_FLAGS_ACK & pq_flags)) + (!!(PQ_FLAGS_OFLD & pq_flags)) + 286b5a9ee7cSAriel Elior (!!(PQ_FLAGS_LLT & pq_flags)) + 287b5a9ee7cSAriel Elior (!!(PQ_FLAGS_VFS & pq_flags)) * qed_init_qm_get_num_vfs(p_hwfn); 288b5a9ee7cSAriel Elior } 289b5a9ee7cSAriel Elior 290b5a9ee7cSAriel Elior /* initialize the top level QM params */ 291b5a9ee7cSAriel Elior static void qed_init_qm_params(struct qed_hwfn *p_hwfn) 292b5a9ee7cSAriel Elior { 293b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 294b5a9ee7cSAriel Elior bool four_port; 295b5a9ee7cSAriel Elior 296b5a9ee7cSAriel Elior /* pq and vport bases for this PF */ 297b5a9ee7cSAriel Elior qm_info->start_pq = (u16) RESC_START(p_hwfn, QED_PQ); 298b5a9ee7cSAriel Elior qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT); 299b5a9ee7cSAriel Elior 300b5a9ee7cSAriel Elior /* rate limiting and weighted fair queueing are always enabled */ 301b5a9ee7cSAriel Elior qm_info->vport_rl_en = 1; 302b5a9ee7cSAriel Elior qm_info->vport_wfq_en = 1; 303b5a9ee7cSAriel Elior 304b5a9ee7cSAriel Elior /* TC config is different for AH 4 port */ 30578cea9ffSTomer Tayar four_port = p_hwfn->cdev->num_ports_in_engine == MAX_NUM_PORTS_K2; 306b5a9ee7cSAriel Elior 307b5a9ee7cSAriel Elior /* in AH 4 port we have fewer TCs per port */ 308b5a9ee7cSAriel Elior qm_info->max_phys_tcs_per_port = four_port ? NUM_PHYS_TCS_4PORT_K2 : 309b5a9ee7cSAriel Elior NUM_OF_PHYS_TCS; 310b5a9ee7cSAriel Elior 311b5a9ee7cSAriel Elior /* unless MFW indicated otherwise, ooo_tc == 3 for 312b5a9ee7cSAriel Elior * AH 4-port and 4 otherwise. 313fe56b9e6SYuval Mintz */ 314b5a9ee7cSAriel Elior if (!qm_info->ooo_tc) 315b5a9ee7cSAriel Elior qm_info->ooo_tc = four_port ? DCBX_TCP_OOO_K2_4PORT_TC : 316b5a9ee7cSAriel Elior DCBX_TCP_OOO_TC; 317dbb799c3SYuval Mintz } 318dbb799c3SYuval Mintz 319b5a9ee7cSAriel Elior /* initialize qm vport params */ 320b5a9ee7cSAriel Elior static void qed_init_qm_vport_params(struct qed_hwfn *p_hwfn) 321b5a9ee7cSAriel Elior { 322b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 323b5a9ee7cSAriel Elior u8 i; 324fe56b9e6SYuval Mintz 325b5a9ee7cSAriel Elior /* all vports participate in weighted fair queueing */ 326b5a9ee7cSAriel Elior for (i = 0; i < qed_init_qm_get_num_vports(p_hwfn); i++) 327b5a9ee7cSAriel Elior qm_info->qm_vport_params[i].vport_wfq = 1; 328fe56b9e6SYuval Mintz } 329fe56b9e6SYuval Mintz 330b5a9ee7cSAriel Elior /* initialize qm port params */ 331b5a9ee7cSAriel Elior static void qed_init_qm_port_params(struct qed_hwfn *p_hwfn) 332b5a9ee7cSAriel Elior { 333fe56b9e6SYuval Mintz /* Initialize qm port parameters */ 33478cea9ffSTomer Tayar u8 i, active_phys_tcs, num_ports = p_hwfn->cdev->num_ports_in_engine; 335b5a9ee7cSAriel Elior 336b5a9ee7cSAriel Elior /* indicate how ooo and high pri traffic is dealt with */ 337b5a9ee7cSAriel Elior active_phys_tcs = num_ports == MAX_NUM_PORTS_K2 ? 338b5a9ee7cSAriel Elior ACTIVE_TCS_BMAP_4PORT_K2 : 339b5a9ee7cSAriel Elior ACTIVE_TCS_BMAP; 340b5a9ee7cSAriel Elior 341fe56b9e6SYuval Mintz for (i = 0; i < num_ports; i++) { 342b5a9ee7cSAriel Elior struct init_qm_port_params *p_qm_port = 343b5a9ee7cSAriel Elior &p_hwfn->qm_info.qm_port_params[i]; 344b5a9ee7cSAriel Elior 345fe56b9e6SYuval Mintz p_qm_port->active = 1; 346b5a9ee7cSAriel Elior p_qm_port->active_phys_tcs = active_phys_tcs; 347fe56b9e6SYuval Mintz p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports; 348fe56b9e6SYuval Mintz p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports; 349fe56b9e6SYuval Mintz } 350b5a9ee7cSAriel Elior } 351fe56b9e6SYuval Mintz 352b5a9ee7cSAriel Elior /* Reset the params which must be reset for qm init. QM init may be called as 353b5a9ee7cSAriel Elior * a result of flows other than driver load (e.g. dcbx renegotiation). Other 354b5a9ee7cSAriel Elior * params may be affected by the init but would simply recalculate to the same 355b5a9ee7cSAriel Elior * values. The allocations made for QM init, ports, vports, pqs and vfqs are not 356b5a9ee7cSAriel Elior * affected as these amounts stay the same. 357b5a9ee7cSAriel Elior */ 358b5a9ee7cSAriel Elior static void qed_init_qm_reset_params(struct qed_hwfn *p_hwfn) 359b5a9ee7cSAriel Elior { 360b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 361fe56b9e6SYuval Mintz 362b5a9ee7cSAriel Elior qm_info->num_pqs = 0; 363b5a9ee7cSAriel Elior qm_info->num_vports = 0; 364b5a9ee7cSAriel Elior qm_info->num_pf_rls = 0; 365b5a9ee7cSAriel Elior qm_info->num_vf_pqs = 0; 366b5a9ee7cSAriel Elior qm_info->first_vf_pq = 0; 367b5a9ee7cSAriel Elior qm_info->first_mcos_pq = 0; 368b5a9ee7cSAriel Elior qm_info->first_rl_pq = 0; 369b5a9ee7cSAriel Elior } 370fe56b9e6SYuval Mintz 371b5a9ee7cSAriel Elior static void qed_init_qm_advance_vport(struct qed_hwfn *p_hwfn) 372b5a9ee7cSAriel Elior { 373b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 374b5a9ee7cSAriel Elior 375b5a9ee7cSAriel Elior qm_info->num_vports++; 376b5a9ee7cSAriel Elior 377b5a9ee7cSAriel Elior if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn)) 378b5a9ee7cSAriel Elior DP_ERR(p_hwfn, 379b5a9ee7cSAriel Elior "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n", 380b5a9ee7cSAriel Elior qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn)); 381b5a9ee7cSAriel Elior } 382b5a9ee7cSAriel Elior 383b5a9ee7cSAriel Elior /* initialize a single pq and manage qm_info resources accounting. 384b5a9ee7cSAriel Elior * The pq_init_flags param determines whether the PQ is rate limited 385b5a9ee7cSAriel Elior * (for VF or PF) and whether a new vport is allocated to the pq or not 386b5a9ee7cSAriel Elior * (i.e. vport will be shared). 387b5a9ee7cSAriel Elior */ 388b5a9ee7cSAriel Elior 389b5a9ee7cSAriel Elior /* flags for pq init */ 390b5a9ee7cSAriel Elior #define PQ_INIT_SHARE_VPORT (1 << 0) 391b5a9ee7cSAriel Elior #define PQ_INIT_PF_RL (1 << 1) 392b5a9ee7cSAriel Elior #define PQ_INIT_VF_RL (1 << 2) 393b5a9ee7cSAriel Elior 394b5a9ee7cSAriel Elior /* defines for pq init */ 395b5a9ee7cSAriel Elior #define PQ_INIT_DEFAULT_WRR_GROUP 1 396b5a9ee7cSAriel Elior #define PQ_INIT_DEFAULT_TC 0 397b5a9ee7cSAriel Elior #define PQ_INIT_OFLD_TC (p_hwfn->hw_info.offload_tc) 398b5a9ee7cSAriel Elior 399b5a9ee7cSAriel Elior static void qed_init_qm_pq(struct qed_hwfn *p_hwfn, 400b5a9ee7cSAriel Elior struct qed_qm_info *qm_info, 401b5a9ee7cSAriel Elior u8 tc, u32 pq_init_flags) 402b5a9ee7cSAriel Elior { 403b5a9ee7cSAriel Elior u16 pq_idx = qm_info->num_pqs, max_pq = qed_init_qm_get_num_pqs(p_hwfn); 404b5a9ee7cSAriel Elior 405b5a9ee7cSAriel Elior if (pq_idx > max_pq) 406b5a9ee7cSAriel Elior DP_ERR(p_hwfn, 407b5a9ee7cSAriel Elior "pq overflow! pq %d, max pq %d\n", pq_idx, max_pq); 408b5a9ee7cSAriel Elior 409b5a9ee7cSAriel Elior /* init pq params */ 410b5a9ee7cSAriel Elior qm_info->qm_pq_params[pq_idx].vport_id = qm_info->start_vport + 411b5a9ee7cSAriel Elior qm_info->num_vports; 412b5a9ee7cSAriel Elior qm_info->qm_pq_params[pq_idx].tc_id = tc; 413b5a9ee7cSAriel Elior qm_info->qm_pq_params[pq_idx].wrr_group = PQ_INIT_DEFAULT_WRR_GROUP; 414b5a9ee7cSAriel Elior qm_info->qm_pq_params[pq_idx].rl_valid = 415b5a9ee7cSAriel Elior (pq_init_flags & PQ_INIT_PF_RL || pq_init_flags & PQ_INIT_VF_RL); 416b5a9ee7cSAriel Elior 417b5a9ee7cSAriel Elior /* qm params accounting */ 418b5a9ee7cSAriel Elior qm_info->num_pqs++; 419b5a9ee7cSAriel Elior if (!(pq_init_flags & PQ_INIT_SHARE_VPORT)) 420b5a9ee7cSAriel Elior qm_info->num_vports++; 421b5a9ee7cSAriel Elior 422b5a9ee7cSAriel Elior if (pq_init_flags & PQ_INIT_PF_RL) 423b5a9ee7cSAriel Elior qm_info->num_pf_rls++; 424b5a9ee7cSAriel Elior 425b5a9ee7cSAriel Elior if (qm_info->num_vports > qed_init_qm_get_num_vports(p_hwfn)) 426b5a9ee7cSAriel Elior DP_ERR(p_hwfn, 427b5a9ee7cSAriel Elior "vport overflow! qm_info->num_vports %d, qm_init_get_num_vports() %d\n", 428b5a9ee7cSAriel Elior qm_info->num_vports, qed_init_qm_get_num_vports(p_hwfn)); 429b5a9ee7cSAriel Elior 430b5a9ee7cSAriel Elior if (qm_info->num_pf_rls > qed_init_qm_get_num_pf_rls(p_hwfn)) 431b5a9ee7cSAriel Elior DP_ERR(p_hwfn, 432b5a9ee7cSAriel Elior "rl overflow! qm_info->num_pf_rls %d, qm_init_get_num_pf_rls() %d\n", 433b5a9ee7cSAriel Elior qm_info->num_pf_rls, qed_init_qm_get_num_pf_rls(p_hwfn)); 434b5a9ee7cSAriel Elior } 435b5a9ee7cSAriel Elior 436b5a9ee7cSAriel Elior /* get pq index according to PQ_FLAGS */ 437b5a9ee7cSAriel Elior static u16 *qed_init_qm_get_idx_from_flags(struct qed_hwfn *p_hwfn, 438b5a9ee7cSAriel Elior u32 pq_flags) 439b5a9ee7cSAriel Elior { 440b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 441b5a9ee7cSAriel Elior 442b5a9ee7cSAriel Elior /* Can't have multiple flags set here */ 443b5a9ee7cSAriel Elior if (bitmap_weight((unsigned long *)&pq_flags, sizeof(pq_flags)) > 1) 444b5a9ee7cSAriel Elior goto err; 445b5a9ee7cSAriel Elior 446b5a9ee7cSAriel Elior switch (pq_flags) { 447b5a9ee7cSAriel Elior case PQ_FLAGS_RLS: 448b5a9ee7cSAriel Elior return &qm_info->first_rl_pq; 449b5a9ee7cSAriel Elior case PQ_FLAGS_MCOS: 450b5a9ee7cSAriel Elior return &qm_info->first_mcos_pq; 451b5a9ee7cSAriel Elior case PQ_FLAGS_LB: 452b5a9ee7cSAriel Elior return &qm_info->pure_lb_pq; 453b5a9ee7cSAriel Elior case PQ_FLAGS_OOO: 454b5a9ee7cSAriel Elior return &qm_info->ooo_pq; 455b5a9ee7cSAriel Elior case PQ_FLAGS_ACK: 456b5a9ee7cSAriel Elior return &qm_info->pure_ack_pq; 457b5a9ee7cSAriel Elior case PQ_FLAGS_OFLD: 458b5a9ee7cSAriel Elior return &qm_info->offload_pq; 459b5a9ee7cSAriel Elior case PQ_FLAGS_LLT: 460b5a9ee7cSAriel Elior return &qm_info->low_latency_pq; 461b5a9ee7cSAriel Elior case PQ_FLAGS_VFS: 462b5a9ee7cSAriel Elior return &qm_info->first_vf_pq; 463b5a9ee7cSAriel Elior default: 464b5a9ee7cSAriel Elior goto err; 465b5a9ee7cSAriel Elior } 466b5a9ee7cSAriel Elior 467b5a9ee7cSAriel Elior err: 468b5a9ee7cSAriel Elior DP_ERR(p_hwfn, "BAD pq flags %d\n", pq_flags); 469b5a9ee7cSAriel Elior return NULL; 470b5a9ee7cSAriel Elior } 471b5a9ee7cSAriel Elior 472b5a9ee7cSAriel Elior /* save pq index in qm info */ 473b5a9ee7cSAriel Elior static void qed_init_qm_set_idx(struct qed_hwfn *p_hwfn, 474b5a9ee7cSAriel Elior u32 pq_flags, u16 pq_val) 475b5a9ee7cSAriel Elior { 476b5a9ee7cSAriel Elior u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags); 477b5a9ee7cSAriel Elior 478b5a9ee7cSAriel Elior *base_pq_idx = p_hwfn->qm_info.start_pq + pq_val; 479b5a9ee7cSAriel Elior } 480b5a9ee7cSAriel Elior 481b5a9ee7cSAriel Elior /* get tx pq index, with the PQ TX base already set (ready for context init) */ 482b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags) 483b5a9ee7cSAriel Elior { 484b5a9ee7cSAriel Elior u16 *base_pq_idx = qed_init_qm_get_idx_from_flags(p_hwfn, pq_flags); 485b5a9ee7cSAriel Elior 486b5a9ee7cSAriel Elior return *base_pq_idx + CM_TX_PQ_BASE; 487b5a9ee7cSAriel Elior } 488b5a9ee7cSAriel Elior 489b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc) 490b5a9ee7cSAriel Elior { 491b5a9ee7cSAriel Elior u8 max_tc = qed_init_qm_get_num_tcs(p_hwfn); 492b5a9ee7cSAriel Elior 493b5a9ee7cSAriel Elior if (tc > max_tc) 494b5a9ee7cSAriel Elior DP_ERR(p_hwfn, "tc %d must be smaller than %d\n", tc, max_tc); 495b5a9ee7cSAriel Elior 496b5a9ee7cSAriel Elior return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_MCOS) + tc; 497b5a9ee7cSAriel Elior } 498b5a9ee7cSAriel Elior 499b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf) 500b5a9ee7cSAriel Elior { 501b5a9ee7cSAriel Elior u16 max_vf = qed_init_qm_get_num_vfs(p_hwfn); 502b5a9ee7cSAriel Elior 503b5a9ee7cSAriel Elior if (vf > max_vf) 504b5a9ee7cSAriel Elior DP_ERR(p_hwfn, "vf %d must be smaller than %d\n", vf, max_vf); 505b5a9ee7cSAriel Elior 506b5a9ee7cSAriel Elior return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_VFS) + vf; 507b5a9ee7cSAriel Elior } 508b5a9ee7cSAriel Elior 509b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx_rl(struct qed_hwfn *p_hwfn, u8 rl) 510b5a9ee7cSAriel Elior { 511b5a9ee7cSAriel Elior u16 max_rl = qed_init_qm_get_num_pf_rls(p_hwfn); 512b5a9ee7cSAriel Elior 513b5a9ee7cSAriel Elior if (rl > max_rl) 514b5a9ee7cSAriel Elior DP_ERR(p_hwfn, "rl %d must be smaller than %d\n", rl, max_rl); 515b5a9ee7cSAriel Elior 516b5a9ee7cSAriel Elior return qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_RLS) + rl; 517b5a9ee7cSAriel Elior } 518b5a9ee7cSAriel Elior 519b5a9ee7cSAriel Elior /* Functions for creating specific types of pqs */ 520b5a9ee7cSAriel Elior static void qed_init_qm_lb_pq(struct qed_hwfn *p_hwfn) 521b5a9ee7cSAriel Elior { 522b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 523b5a9ee7cSAriel Elior 524b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LB)) 525b5a9ee7cSAriel Elior return; 526b5a9ee7cSAriel Elior 527b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LB, qm_info->num_pqs); 528b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, qm_info, PURE_LB_TC, PQ_INIT_SHARE_VPORT); 529b5a9ee7cSAriel Elior } 530b5a9ee7cSAriel Elior 531b5a9ee7cSAriel Elior static void qed_init_qm_ooo_pq(struct qed_hwfn *p_hwfn) 532b5a9ee7cSAriel Elior { 533b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 534b5a9ee7cSAriel Elior 535b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OOO)) 536b5a9ee7cSAriel Elior return; 537b5a9ee7cSAriel Elior 538b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OOO, qm_info->num_pqs); 539b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, qm_info, qm_info->ooo_tc, PQ_INIT_SHARE_VPORT); 540b5a9ee7cSAriel Elior } 541b5a9ee7cSAriel Elior 542b5a9ee7cSAriel Elior static void qed_init_qm_pure_ack_pq(struct qed_hwfn *p_hwfn) 543b5a9ee7cSAriel Elior { 544b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 545b5a9ee7cSAriel Elior 546b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_ACK)) 547b5a9ee7cSAriel Elior return; 548b5a9ee7cSAriel Elior 549b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_ACK, qm_info->num_pqs); 550b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT); 551b5a9ee7cSAriel Elior } 552b5a9ee7cSAriel Elior 553b5a9ee7cSAriel Elior static void qed_init_qm_offload_pq(struct qed_hwfn *p_hwfn) 554b5a9ee7cSAriel Elior { 555b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 556b5a9ee7cSAriel Elior 557b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_OFLD)) 558b5a9ee7cSAriel Elior return; 559b5a9ee7cSAriel Elior 560b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_OFLD, qm_info->num_pqs); 561b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT); 562b5a9ee7cSAriel Elior } 563b5a9ee7cSAriel Elior 564b5a9ee7cSAriel Elior static void qed_init_qm_low_latency_pq(struct qed_hwfn *p_hwfn) 565b5a9ee7cSAriel Elior { 566b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 567b5a9ee7cSAriel Elior 568b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_LLT)) 569b5a9ee7cSAriel Elior return; 570b5a9ee7cSAriel Elior 571b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_LLT, qm_info->num_pqs); 572b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_SHARE_VPORT); 573b5a9ee7cSAriel Elior } 574b5a9ee7cSAriel Elior 575b5a9ee7cSAriel Elior static void qed_init_qm_mcos_pqs(struct qed_hwfn *p_hwfn) 576b5a9ee7cSAriel Elior { 577b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 578b5a9ee7cSAriel Elior u8 tc_idx; 579b5a9ee7cSAriel Elior 580b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_MCOS)) 581b5a9ee7cSAriel Elior return; 582b5a9ee7cSAriel Elior 583b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_MCOS, qm_info->num_pqs); 584b5a9ee7cSAriel Elior for (tc_idx = 0; tc_idx < qed_init_qm_get_num_tcs(p_hwfn); tc_idx++) 585b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, qm_info, tc_idx, PQ_INIT_SHARE_VPORT); 586b5a9ee7cSAriel Elior } 587b5a9ee7cSAriel Elior 588b5a9ee7cSAriel Elior static void qed_init_qm_vf_pqs(struct qed_hwfn *p_hwfn) 589b5a9ee7cSAriel Elior { 590b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 591b5a9ee7cSAriel Elior u16 vf_idx, num_vfs = qed_init_qm_get_num_vfs(p_hwfn); 592b5a9ee7cSAriel Elior 593b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_VFS)) 594b5a9ee7cSAriel Elior return; 595b5a9ee7cSAriel Elior 596b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_VFS, qm_info->num_pqs); 5971408cc1fSYuval Mintz qm_info->num_vf_pqs = num_vfs; 598b5a9ee7cSAriel Elior for (vf_idx = 0; vf_idx < num_vfs; vf_idx++) 599b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, 600b5a9ee7cSAriel Elior qm_info, PQ_INIT_DEFAULT_TC, PQ_INIT_VF_RL); 601b5a9ee7cSAriel Elior } 602fe56b9e6SYuval Mintz 603b5a9ee7cSAriel Elior static void qed_init_qm_rl_pqs(struct qed_hwfn *p_hwfn) 604b5a9ee7cSAriel Elior { 605b5a9ee7cSAriel Elior u16 pf_rls_idx, num_pf_rls = qed_init_qm_get_num_pf_rls(p_hwfn); 606b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 607a64b02d5SManish Chopra 608b5a9ee7cSAriel Elior if (!(qed_get_pq_flags(p_hwfn) & PQ_FLAGS_RLS)) 609b5a9ee7cSAriel Elior return; 610b5a9ee7cSAriel Elior 611b5a9ee7cSAriel Elior qed_init_qm_set_idx(p_hwfn, PQ_FLAGS_RLS, qm_info->num_pqs); 612b5a9ee7cSAriel Elior for (pf_rls_idx = 0; pf_rls_idx < num_pf_rls; pf_rls_idx++) 613b5a9ee7cSAriel Elior qed_init_qm_pq(p_hwfn, qm_info, PQ_INIT_OFLD_TC, PQ_INIT_PF_RL); 614b5a9ee7cSAriel Elior } 615b5a9ee7cSAriel Elior 616b5a9ee7cSAriel Elior static void qed_init_qm_pq_params(struct qed_hwfn *p_hwfn) 617b5a9ee7cSAriel Elior { 618b5a9ee7cSAriel Elior /* rate limited pqs, must come first (FW assumption) */ 619b5a9ee7cSAriel Elior qed_init_qm_rl_pqs(p_hwfn); 620b5a9ee7cSAriel Elior 621b5a9ee7cSAriel Elior /* pqs for multi cos */ 622b5a9ee7cSAriel Elior qed_init_qm_mcos_pqs(p_hwfn); 623b5a9ee7cSAriel Elior 624b5a9ee7cSAriel Elior /* pure loopback pq */ 625b5a9ee7cSAriel Elior qed_init_qm_lb_pq(p_hwfn); 626b5a9ee7cSAriel Elior 627b5a9ee7cSAriel Elior /* out of order pq */ 628b5a9ee7cSAriel Elior qed_init_qm_ooo_pq(p_hwfn); 629b5a9ee7cSAriel Elior 630b5a9ee7cSAriel Elior /* pure ack pq */ 631b5a9ee7cSAriel Elior qed_init_qm_pure_ack_pq(p_hwfn); 632b5a9ee7cSAriel Elior 633b5a9ee7cSAriel Elior /* pq for offloaded protocol */ 634b5a9ee7cSAriel Elior qed_init_qm_offload_pq(p_hwfn); 635b5a9ee7cSAriel Elior 636b5a9ee7cSAriel Elior /* low latency pq */ 637b5a9ee7cSAriel Elior qed_init_qm_low_latency_pq(p_hwfn); 638b5a9ee7cSAriel Elior 639b5a9ee7cSAriel Elior /* done sharing vports */ 640b5a9ee7cSAriel Elior qed_init_qm_advance_vport(p_hwfn); 641b5a9ee7cSAriel Elior 642b5a9ee7cSAriel Elior /* pqs for vfs */ 643b5a9ee7cSAriel Elior qed_init_qm_vf_pqs(p_hwfn); 644b5a9ee7cSAriel Elior } 645b5a9ee7cSAriel Elior 646b5a9ee7cSAriel Elior /* compare values of getters against resources amounts */ 647b5a9ee7cSAriel Elior static int qed_init_qm_sanity(struct qed_hwfn *p_hwfn) 648b5a9ee7cSAriel Elior { 649b5a9ee7cSAriel Elior if (qed_init_qm_get_num_vports(p_hwfn) > RESC_NUM(p_hwfn, QED_VPORT)) { 650b5a9ee7cSAriel Elior DP_ERR(p_hwfn, "requested amount of vports exceeds resource\n"); 651b5a9ee7cSAriel Elior return -EINVAL; 652b5a9ee7cSAriel Elior } 653b5a9ee7cSAriel Elior 654b5a9ee7cSAriel Elior if (qed_init_qm_get_num_pqs(p_hwfn) > RESC_NUM(p_hwfn, QED_PQ)) { 655b5a9ee7cSAriel Elior DP_ERR(p_hwfn, "requested amount of pqs exceeds resource\n"); 656b5a9ee7cSAriel Elior return -EINVAL; 657b5a9ee7cSAriel Elior } 658fe56b9e6SYuval Mintz 659fe56b9e6SYuval Mintz return 0; 660b5a9ee7cSAriel Elior } 661fe56b9e6SYuval Mintz 662b5a9ee7cSAriel Elior static void qed_dp_init_qm_params(struct qed_hwfn *p_hwfn) 663b5a9ee7cSAriel Elior { 664b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 665b5a9ee7cSAriel Elior struct init_qm_vport_params *vport; 666b5a9ee7cSAriel Elior struct init_qm_port_params *port; 667b5a9ee7cSAriel Elior struct init_qm_pq_params *pq; 668b5a9ee7cSAriel Elior int i, tc; 669b5a9ee7cSAriel Elior 670b5a9ee7cSAriel Elior /* top level params */ 671b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 672b5a9ee7cSAriel Elior NETIF_MSG_HW, 673b5a9ee7cSAriel Elior "qm init top level params: start_pq %d, start_vport %d, pure_lb_pq %d, offload_pq %d, pure_ack_pq %d\n", 674b5a9ee7cSAriel Elior qm_info->start_pq, 675b5a9ee7cSAriel Elior qm_info->start_vport, 676b5a9ee7cSAriel Elior qm_info->pure_lb_pq, 677b5a9ee7cSAriel Elior qm_info->offload_pq, qm_info->pure_ack_pq); 678b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 679b5a9ee7cSAriel Elior NETIF_MSG_HW, 680b5a9ee7cSAriel Elior "ooo_pq %d, first_vf_pq %d, num_pqs %d, num_vf_pqs %d, num_vports %d, max_phys_tcs_per_port %d\n", 681b5a9ee7cSAriel Elior qm_info->ooo_pq, 682b5a9ee7cSAriel Elior qm_info->first_vf_pq, 683b5a9ee7cSAriel Elior qm_info->num_pqs, 684b5a9ee7cSAriel Elior qm_info->num_vf_pqs, 685b5a9ee7cSAriel Elior qm_info->num_vports, qm_info->max_phys_tcs_per_port); 686b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 687b5a9ee7cSAriel Elior NETIF_MSG_HW, 688b5a9ee7cSAriel Elior "pf_rl_en %d, pf_wfq_en %d, vport_rl_en %d, vport_wfq_en %d, pf_wfq %d, pf_rl %d, num_pf_rls %d, pq_flags %x\n", 689b5a9ee7cSAriel Elior qm_info->pf_rl_en, 690b5a9ee7cSAriel Elior qm_info->pf_wfq_en, 691b5a9ee7cSAriel Elior qm_info->vport_rl_en, 692b5a9ee7cSAriel Elior qm_info->vport_wfq_en, 693b5a9ee7cSAriel Elior qm_info->pf_wfq, 694b5a9ee7cSAriel Elior qm_info->pf_rl, 695b5a9ee7cSAriel Elior qm_info->num_pf_rls, qed_get_pq_flags(p_hwfn)); 696b5a9ee7cSAriel Elior 697b5a9ee7cSAriel Elior /* port table */ 69878cea9ffSTomer Tayar for (i = 0; i < p_hwfn->cdev->num_ports_in_engine; i++) { 699b5a9ee7cSAriel Elior port = &(qm_info->qm_port_params[i]); 700b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 701b5a9ee7cSAriel Elior NETIF_MSG_HW, 702b5a9ee7cSAriel Elior "port idx %d, active %d, active_phys_tcs %d, num_pbf_cmd_lines %d, num_btb_blocks %d, reserved %d\n", 703b5a9ee7cSAriel Elior i, 704b5a9ee7cSAriel Elior port->active, 705b5a9ee7cSAriel Elior port->active_phys_tcs, 706b5a9ee7cSAriel Elior port->num_pbf_cmd_lines, 707b5a9ee7cSAriel Elior port->num_btb_blocks, port->reserved); 708b5a9ee7cSAriel Elior } 709b5a9ee7cSAriel Elior 710b5a9ee7cSAriel Elior /* vport table */ 711b5a9ee7cSAriel Elior for (i = 0; i < qm_info->num_vports; i++) { 712b5a9ee7cSAriel Elior vport = &(qm_info->qm_vport_params[i]); 713b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 714b5a9ee7cSAriel Elior NETIF_MSG_HW, 715b5a9ee7cSAriel Elior "vport idx %d, vport_rl %d, wfq %d, first_tx_pq_id [ ", 716b5a9ee7cSAriel Elior qm_info->start_vport + i, 717b5a9ee7cSAriel Elior vport->vport_rl, vport->vport_wfq); 718b5a9ee7cSAriel Elior for (tc = 0; tc < NUM_OF_TCS; tc++) 719b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 720b5a9ee7cSAriel Elior NETIF_MSG_HW, 721b5a9ee7cSAriel Elior "%d ", vport->first_tx_pq_id[tc]); 722b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "]\n"); 723b5a9ee7cSAriel Elior } 724b5a9ee7cSAriel Elior 725b5a9ee7cSAriel Elior /* pq table */ 726b5a9ee7cSAriel Elior for (i = 0; i < qm_info->num_pqs; i++) { 727b5a9ee7cSAriel Elior pq = &(qm_info->qm_pq_params[i]); 728b5a9ee7cSAriel Elior DP_VERBOSE(p_hwfn, 729b5a9ee7cSAriel Elior NETIF_MSG_HW, 730b5a9ee7cSAriel Elior "pq idx %d, vport_id %d, tc %d, wrr_grp %d, rl_valid %d\n", 731b5a9ee7cSAriel Elior qm_info->start_pq + i, 732b5a9ee7cSAriel Elior pq->vport_id, 733b5a9ee7cSAriel Elior pq->tc_id, pq->wrr_group, pq->rl_valid); 734b5a9ee7cSAriel Elior } 735b5a9ee7cSAriel Elior } 736b5a9ee7cSAriel Elior 737b5a9ee7cSAriel Elior static void qed_init_qm_info(struct qed_hwfn *p_hwfn) 738b5a9ee7cSAriel Elior { 739b5a9ee7cSAriel Elior /* reset params required for init run */ 740b5a9ee7cSAriel Elior qed_init_qm_reset_params(p_hwfn); 741b5a9ee7cSAriel Elior 742b5a9ee7cSAriel Elior /* init QM top level params */ 743b5a9ee7cSAriel Elior qed_init_qm_params(p_hwfn); 744b5a9ee7cSAriel Elior 745b5a9ee7cSAriel Elior /* init QM port params */ 746b5a9ee7cSAriel Elior qed_init_qm_port_params(p_hwfn); 747b5a9ee7cSAriel Elior 748b5a9ee7cSAriel Elior /* init QM vport params */ 749b5a9ee7cSAriel Elior qed_init_qm_vport_params(p_hwfn); 750b5a9ee7cSAriel Elior 751b5a9ee7cSAriel Elior /* init QM physical queue params */ 752b5a9ee7cSAriel Elior qed_init_qm_pq_params(p_hwfn); 753b5a9ee7cSAriel Elior 754b5a9ee7cSAriel Elior /* display all that init */ 755b5a9ee7cSAriel Elior qed_dp_init_qm_params(p_hwfn); 756fe56b9e6SYuval Mintz } 757fe56b9e6SYuval Mintz 75839651abdSSudarsana Reddy Kalluru /* This function reconfigures the QM pf on the fly. 75939651abdSSudarsana Reddy Kalluru * For this purpose we: 76039651abdSSudarsana Reddy Kalluru * 1. reconfigure the QM database 761a2e7699eSTomer Tayar * 2. set new values to runtime array 76239651abdSSudarsana Reddy Kalluru * 3. send an sdm_qm_cmd through the rbc interface to stop the QM 76339651abdSSudarsana Reddy Kalluru * 4. activate init tool in QM_PF stage 76439651abdSSudarsana Reddy Kalluru * 5. send an sdm_qm_cmd through rbc interface to release the QM 76539651abdSSudarsana Reddy Kalluru */ 76639651abdSSudarsana Reddy Kalluru int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 76739651abdSSudarsana Reddy Kalluru { 76839651abdSSudarsana Reddy Kalluru struct qed_qm_info *qm_info = &p_hwfn->qm_info; 76939651abdSSudarsana Reddy Kalluru bool b_rc; 77039651abdSSudarsana Reddy Kalluru int rc; 77139651abdSSudarsana Reddy Kalluru 77239651abdSSudarsana Reddy Kalluru /* initialize qed's qm data structure */ 773b5a9ee7cSAriel Elior qed_init_qm_info(p_hwfn); 77439651abdSSudarsana Reddy Kalluru 77539651abdSSudarsana Reddy Kalluru /* stop PF's qm queues */ 77639651abdSSudarsana Reddy Kalluru spin_lock_bh(&qm_lock); 77739651abdSSudarsana Reddy Kalluru b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true, 77839651abdSSudarsana Reddy Kalluru qm_info->start_pq, qm_info->num_pqs); 77939651abdSSudarsana Reddy Kalluru spin_unlock_bh(&qm_lock); 78039651abdSSudarsana Reddy Kalluru if (!b_rc) 78139651abdSSudarsana Reddy Kalluru return -EINVAL; 78239651abdSSudarsana Reddy Kalluru 78339651abdSSudarsana Reddy Kalluru /* clear the QM_PF runtime phase leftovers from previous init */ 78439651abdSSudarsana Reddy Kalluru qed_init_clear_rt_data(p_hwfn); 78539651abdSSudarsana Reddy Kalluru 78639651abdSSudarsana Reddy Kalluru /* prepare QM portion of runtime array */ 78715582962SRahul Verma qed_qm_init_pf(p_hwfn, p_ptt); 78839651abdSSudarsana Reddy Kalluru 78939651abdSSudarsana Reddy Kalluru /* activate init tool on runtime array */ 79039651abdSSudarsana Reddy Kalluru rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id, 79139651abdSSudarsana Reddy Kalluru p_hwfn->hw_info.hw_mode); 79239651abdSSudarsana Reddy Kalluru if (rc) 79339651abdSSudarsana Reddy Kalluru return rc; 79439651abdSSudarsana Reddy Kalluru 79539651abdSSudarsana Reddy Kalluru /* start PF's qm queues */ 79639651abdSSudarsana Reddy Kalluru spin_lock_bh(&qm_lock); 79739651abdSSudarsana Reddy Kalluru b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true, 79839651abdSSudarsana Reddy Kalluru qm_info->start_pq, qm_info->num_pqs); 79939651abdSSudarsana Reddy Kalluru spin_unlock_bh(&qm_lock); 80039651abdSSudarsana Reddy Kalluru if (!b_rc) 80139651abdSSudarsana Reddy Kalluru return -EINVAL; 80239651abdSSudarsana Reddy Kalluru 80339651abdSSudarsana Reddy Kalluru return 0; 80439651abdSSudarsana Reddy Kalluru } 80539651abdSSudarsana Reddy Kalluru 806b5a9ee7cSAriel Elior static int qed_alloc_qm_data(struct qed_hwfn *p_hwfn) 807b5a9ee7cSAriel Elior { 808b5a9ee7cSAriel Elior struct qed_qm_info *qm_info = &p_hwfn->qm_info; 809b5a9ee7cSAriel Elior int rc; 810b5a9ee7cSAriel Elior 811b5a9ee7cSAriel Elior rc = qed_init_qm_sanity(p_hwfn); 812b5a9ee7cSAriel Elior if (rc) 813b5a9ee7cSAriel Elior goto alloc_err; 814b5a9ee7cSAriel Elior 815b5a9ee7cSAriel Elior qm_info->qm_pq_params = kzalloc(sizeof(*qm_info->qm_pq_params) * 816b5a9ee7cSAriel Elior qed_init_qm_get_num_pqs(p_hwfn), 817b5a9ee7cSAriel Elior GFP_KERNEL); 818b5a9ee7cSAriel Elior if (!qm_info->qm_pq_params) 819b5a9ee7cSAriel Elior goto alloc_err; 820b5a9ee7cSAriel Elior 821b5a9ee7cSAriel Elior qm_info->qm_vport_params = kzalloc(sizeof(*qm_info->qm_vport_params) * 822b5a9ee7cSAriel Elior qed_init_qm_get_num_vports(p_hwfn), 823b5a9ee7cSAriel Elior GFP_KERNEL); 824b5a9ee7cSAriel Elior if (!qm_info->qm_vport_params) 825b5a9ee7cSAriel Elior goto alloc_err; 826b5a9ee7cSAriel Elior 8272f7878c0SWei Yongjun qm_info->qm_port_params = kzalloc(sizeof(*qm_info->qm_port_params) * 82878cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine, 829b5a9ee7cSAriel Elior GFP_KERNEL); 830b5a9ee7cSAriel Elior if (!qm_info->qm_port_params) 831b5a9ee7cSAriel Elior goto alloc_err; 832b5a9ee7cSAriel Elior 833b5a9ee7cSAriel Elior qm_info->wfq_data = kzalloc(sizeof(*qm_info->wfq_data) * 834b5a9ee7cSAriel Elior qed_init_qm_get_num_vports(p_hwfn), 835b5a9ee7cSAriel Elior GFP_KERNEL); 836b5a9ee7cSAriel Elior if (!qm_info->wfq_data) 837b5a9ee7cSAriel Elior goto alloc_err; 838b5a9ee7cSAriel Elior 839b5a9ee7cSAriel Elior return 0; 840b5a9ee7cSAriel Elior 841b5a9ee7cSAriel Elior alloc_err: 842b5a9ee7cSAriel Elior DP_NOTICE(p_hwfn, "Failed to allocate memory for QM params\n"); 843b5a9ee7cSAriel Elior qed_qm_info_free(p_hwfn); 844b5a9ee7cSAriel Elior return -ENOMEM; 845b5a9ee7cSAriel Elior } 846b5a9ee7cSAriel Elior 847fe56b9e6SYuval Mintz int qed_resc_alloc(struct qed_dev *cdev) 848fe56b9e6SYuval Mintz { 849f9dc4d1fSRam Amrani u32 rdma_tasks, excess_tasks; 850f9dc4d1fSRam Amrani u32 line_count; 851fe56b9e6SYuval Mintz int i, rc = 0; 852fe56b9e6SYuval Mintz 8530db711bbSMintz, Yuval if (IS_VF(cdev)) { 8540db711bbSMintz, Yuval for_each_hwfn(cdev, i) { 8550db711bbSMintz, Yuval rc = qed_l2_alloc(&cdev->hwfns[i]); 8560db711bbSMintz, Yuval if (rc) 8571408cc1fSYuval Mintz return rc; 8580db711bbSMintz, Yuval } 8590db711bbSMintz, Yuval return rc; 8600db711bbSMintz, Yuval } 8611408cc1fSYuval Mintz 862fe56b9e6SYuval Mintz cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL); 863fe56b9e6SYuval Mintz if (!cdev->fw_data) 864fe56b9e6SYuval Mintz return -ENOMEM; 865fe56b9e6SYuval Mintz 866fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 867fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 868dbb799c3SYuval Mintz u32 n_eqes, num_cons; 869fe56b9e6SYuval Mintz 870fe56b9e6SYuval Mintz /* First allocate the context manager structure */ 871fe56b9e6SYuval Mintz rc = qed_cxt_mngr_alloc(p_hwfn); 872fe56b9e6SYuval Mintz if (rc) 873fe56b9e6SYuval Mintz goto alloc_err; 874fe56b9e6SYuval Mintz 875fe56b9e6SYuval Mintz /* Set the HW cid/tid numbers (in the contest manager) 876fe56b9e6SYuval Mintz * Must be done prior to any further computations. 877fe56b9e6SYuval Mintz */ 878f9dc4d1fSRam Amrani rc = qed_cxt_set_pf_params(p_hwfn, RDMA_MAX_TIDS); 879fe56b9e6SYuval Mintz if (rc) 880fe56b9e6SYuval Mintz goto alloc_err; 881fe56b9e6SYuval Mintz 882b5a9ee7cSAriel Elior rc = qed_alloc_qm_data(p_hwfn); 883fe56b9e6SYuval Mintz if (rc) 884fe56b9e6SYuval Mintz goto alloc_err; 885fe56b9e6SYuval Mintz 886b5a9ee7cSAriel Elior /* init qm info */ 887b5a9ee7cSAriel Elior qed_init_qm_info(p_hwfn); 888b5a9ee7cSAriel Elior 889fe56b9e6SYuval Mintz /* Compute the ILT client partition */ 890f9dc4d1fSRam Amrani rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count); 891f9dc4d1fSRam Amrani if (rc) { 892f9dc4d1fSRam Amrani DP_NOTICE(p_hwfn, 893f9dc4d1fSRam Amrani "too many ILT lines; re-computing with less lines\n"); 894f9dc4d1fSRam Amrani /* In case there are not enough ILT lines we reduce the 895f9dc4d1fSRam Amrani * number of RDMA tasks and re-compute. 896f9dc4d1fSRam Amrani */ 897f9dc4d1fSRam Amrani excess_tasks = 898f9dc4d1fSRam Amrani qed_cxt_cfg_ilt_compute_excess(p_hwfn, line_count); 899f9dc4d1fSRam Amrani if (!excess_tasks) 900f9dc4d1fSRam Amrani goto alloc_err; 901f9dc4d1fSRam Amrani 902f9dc4d1fSRam Amrani rdma_tasks = RDMA_MAX_TIDS - excess_tasks; 903f9dc4d1fSRam Amrani rc = qed_cxt_set_pf_params(p_hwfn, rdma_tasks); 904fe56b9e6SYuval Mintz if (rc) 905fe56b9e6SYuval Mintz goto alloc_err; 906fe56b9e6SYuval Mintz 907f9dc4d1fSRam Amrani rc = qed_cxt_cfg_ilt_compute(p_hwfn, &line_count); 908f9dc4d1fSRam Amrani if (rc) { 909f9dc4d1fSRam Amrani DP_ERR(p_hwfn, 910f9dc4d1fSRam Amrani "failed ILT compute. Requested too many lines: %u\n", 911f9dc4d1fSRam Amrani line_count); 912f9dc4d1fSRam Amrani 913f9dc4d1fSRam Amrani goto alloc_err; 914f9dc4d1fSRam Amrani } 915f9dc4d1fSRam Amrani } 916f9dc4d1fSRam Amrani 917fe56b9e6SYuval Mintz /* CID map / ILT shadow table / T2 918fe56b9e6SYuval Mintz * The talbes sizes are determined by the computations above 919fe56b9e6SYuval Mintz */ 920fe56b9e6SYuval Mintz rc = qed_cxt_tables_alloc(p_hwfn); 921fe56b9e6SYuval Mintz if (rc) 922fe56b9e6SYuval Mintz goto alloc_err; 923fe56b9e6SYuval Mintz 924fe56b9e6SYuval Mintz /* SPQ, must follow ILT because initializes SPQ context */ 925fe56b9e6SYuval Mintz rc = qed_spq_alloc(p_hwfn); 926fe56b9e6SYuval Mintz if (rc) 927fe56b9e6SYuval Mintz goto alloc_err; 928fe56b9e6SYuval Mintz 929fe56b9e6SYuval Mintz /* SP status block allocation */ 930fe56b9e6SYuval Mintz p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn, 931fe56b9e6SYuval Mintz RESERVED_PTT_DPC); 932fe56b9e6SYuval Mintz 933fe56b9e6SYuval Mintz rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt); 934fe56b9e6SYuval Mintz if (rc) 935fe56b9e6SYuval Mintz goto alloc_err; 936fe56b9e6SYuval Mintz 93732a47e72SYuval Mintz rc = qed_iov_alloc(p_hwfn); 93832a47e72SYuval Mintz if (rc) 93932a47e72SYuval Mintz goto alloc_err; 94032a47e72SYuval Mintz 941fe56b9e6SYuval Mintz /* EQ */ 942dbb799c3SYuval Mintz n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain); 943c851a9dcSKalderon, Michal if (QED_IS_RDMA_PERSONALITY(p_hwfn)) { 94467b40dccSKalderon, Michal enum protocol_type rdma_proto; 94567b40dccSKalderon, Michal 94667b40dccSKalderon, Michal if (QED_IS_ROCE_PERSONALITY(p_hwfn)) 94767b40dccSKalderon, Michal rdma_proto = PROTOCOLID_ROCE; 94867b40dccSKalderon, Michal else 94967b40dccSKalderon, Michal rdma_proto = PROTOCOLID_IWARP; 95067b40dccSKalderon, Michal 951dbb799c3SYuval Mintz num_cons = qed_cxt_get_proto_cid_count(p_hwfn, 95267b40dccSKalderon, Michal rdma_proto, 9538c93beafSYuval Mintz NULL) * 2; 954dbb799c3SYuval Mintz n_eqes += num_cons + 2 * MAX_NUM_VFS_BB; 955dbb799c3SYuval Mintz } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 956dbb799c3SYuval Mintz num_cons = 957dbb799c3SYuval Mintz qed_cxt_get_proto_cid_count(p_hwfn, 9588c93beafSYuval Mintz PROTOCOLID_ISCSI, 9598c93beafSYuval Mintz NULL); 960dbb799c3SYuval Mintz n_eqes += 2 * num_cons; 961dbb799c3SYuval Mintz } 962dbb799c3SYuval Mintz 963dbb799c3SYuval Mintz if (n_eqes > 0xFFFF) { 964dbb799c3SYuval Mintz DP_ERR(p_hwfn, 965dbb799c3SYuval Mintz "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n", 966dbb799c3SYuval Mintz n_eqes, 0xFFFF); 9673587cb87STomer Tayar goto alloc_no_mem; 9689b15acbfSDan Carpenter } 969dbb799c3SYuval Mintz 9703587cb87STomer Tayar rc = qed_eq_alloc(p_hwfn, (u16) n_eqes); 9713587cb87STomer Tayar if (rc) 9723587cb87STomer Tayar goto alloc_err; 973fe56b9e6SYuval Mintz 9743587cb87STomer Tayar rc = qed_consq_alloc(p_hwfn); 9753587cb87STomer Tayar if (rc) 9763587cb87STomer Tayar goto alloc_err; 977fe56b9e6SYuval Mintz 9780db711bbSMintz, Yuval rc = qed_l2_alloc(p_hwfn); 9790db711bbSMintz, Yuval if (rc) 9800db711bbSMintz, Yuval goto alloc_err; 9810db711bbSMintz, Yuval 9820a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 9830a7fb11cSYuval Mintz if (p_hwfn->using_ll2) { 9843587cb87STomer Tayar rc = qed_ll2_alloc(p_hwfn); 9853587cb87STomer Tayar if (rc) 9863587cb87STomer Tayar goto alloc_err; 9870a7fb11cSYuval Mintz } 9880a7fb11cSYuval Mintz #endif 9891e128c81SArun Easi 9901e128c81SArun Easi if (p_hwfn->hw_info.personality == QED_PCI_FCOE) { 9913587cb87STomer Tayar rc = qed_fcoe_alloc(p_hwfn); 9923587cb87STomer Tayar if (rc) 9933587cb87STomer Tayar goto alloc_err; 9941e128c81SArun Easi } 9951e128c81SArun Easi 996fc831825SYuval Mintz if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 9973587cb87STomer Tayar rc = qed_iscsi_alloc(p_hwfn); 9983587cb87STomer Tayar if (rc) 9993587cb87STomer Tayar goto alloc_err; 10003587cb87STomer Tayar rc = qed_ooo_alloc(p_hwfn); 10013587cb87STomer Tayar if (rc) 10023587cb87STomer Tayar goto alloc_err; 1003fc831825SYuval Mintz } 10040a7fb11cSYuval Mintz 1005fe56b9e6SYuval Mintz /* DMA info initialization */ 1006fe56b9e6SYuval Mintz rc = qed_dmae_info_alloc(p_hwfn); 10072591c280SJoe Perches if (rc) 1008fe56b9e6SYuval Mintz goto alloc_err; 100939651abdSSudarsana Reddy Kalluru 101039651abdSSudarsana Reddy Kalluru /* DCBX initialization */ 101139651abdSSudarsana Reddy Kalluru rc = qed_dcbx_info_alloc(p_hwfn); 10122591c280SJoe Perches if (rc) 101339651abdSSudarsana Reddy Kalluru goto alloc_err; 101439651abdSSudarsana Reddy Kalluru } 1015fe56b9e6SYuval Mintz 1016fe56b9e6SYuval Mintz cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL); 10172591c280SJoe Perches if (!cdev->reset_stats) 101883aeb933SYuval Mintz goto alloc_no_mem; 1019fe56b9e6SYuval Mintz 1020fe56b9e6SYuval Mintz return 0; 1021fe56b9e6SYuval Mintz 1022dbb799c3SYuval Mintz alloc_no_mem: 1023dbb799c3SYuval Mintz rc = -ENOMEM; 1024fe56b9e6SYuval Mintz alloc_err: 1025fe56b9e6SYuval Mintz qed_resc_free(cdev); 1026fe56b9e6SYuval Mintz return rc; 1027fe56b9e6SYuval Mintz } 1028fe56b9e6SYuval Mintz 1029fe56b9e6SYuval Mintz void qed_resc_setup(struct qed_dev *cdev) 1030fe56b9e6SYuval Mintz { 1031fe56b9e6SYuval Mintz int i; 1032fe56b9e6SYuval Mintz 10330db711bbSMintz, Yuval if (IS_VF(cdev)) { 10340db711bbSMintz, Yuval for_each_hwfn(cdev, i) 10350db711bbSMintz, Yuval qed_l2_setup(&cdev->hwfns[i]); 10361408cc1fSYuval Mintz return; 10370db711bbSMintz, Yuval } 10381408cc1fSYuval Mintz 1039fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 1040fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1041fe56b9e6SYuval Mintz 1042fe56b9e6SYuval Mintz qed_cxt_mngr_setup(p_hwfn); 1043fe56b9e6SYuval Mintz qed_spq_setup(p_hwfn); 10443587cb87STomer Tayar qed_eq_setup(p_hwfn); 10453587cb87STomer Tayar qed_consq_setup(p_hwfn); 1046fe56b9e6SYuval Mintz 1047fe56b9e6SYuval Mintz /* Read shadow of current MFW mailbox */ 1048fe56b9e6SYuval Mintz qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt); 1049fe56b9e6SYuval Mintz memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 1050fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_cur, 1051fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_length); 1052fe56b9e6SYuval Mintz 1053fe56b9e6SYuval Mintz qed_int_setup(p_hwfn, p_hwfn->p_main_ptt); 105432a47e72SYuval Mintz 10550db711bbSMintz, Yuval qed_l2_setup(p_hwfn); 10561ee240e3SMintz, Yuval qed_iov_setup(p_hwfn); 10570a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 10580a7fb11cSYuval Mintz if (p_hwfn->using_ll2) 10593587cb87STomer Tayar qed_ll2_setup(p_hwfn); 10600a7fb11cSYuval Mintz #endif 10611e128c81SArun Easi if (p_hwfn->hw_info.personality == QED_PCI_FCOE) 10623587cb87STomer Tayar qed_fcoe_setup(p_hwfn); 10631e128c81SArun Easi 10641d6cff4fSYuval Mintz if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 10653587cb87STomer Tayar qed_iscsi_setup(p_hwfn); 10663587cb87STomer Tayar qed_ooo_setup(p_hwfn); 10671d6cff4fSYuval Mintz } 1068fe56b9e6SYuval Mintz } 1069fe56b9e6SYuval Mintz } 1070fe56b9e6SYuval Mintz 1071fe56b9e6SYuval Mintz #define FINAL_CLEANUP_POLL_CNT (100) 1072fe56b9e6SYuval Mintz #define FINAL_CLEANUP_POLL_TIME (10) 1073fe56b9e6SYuval Mintz int qed_final_cleanup(struct qed_hwfn *p_hwfn, 10740b55e27dSYuval Mintz struct qed_ptt *p_ptt, u16 id, bool is_vf) 1075fe56b9e6SYuval Mintz { 1076fe56b9e6SYuval Mintz u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT; 1077fe56b9e6SYuval Mintz int rc = -EBUSY; 1078fe56b9e6SYuval Mintz 1079fc48b7a6SYuval Mintz addr = GTT_BAR0_MAP_REG_USDM_RAM + 1080fc48b7a6SYuval Mintz USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id); 1081fe56b9e6SYuval Mintz 10820b55e27dSYuval Mintz if (is_vf) 10830b55e27dSYuval Mintz id += 0x10; 10840b55e27dSYuval Mintz 1085fc48b7a6SYuval Mintz command |= X_FINAL_CLEANUP_AGG_INT << 1086fc48b7a6SYuval Mintz SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT; 1087fc48b7a6SYuval Mintz command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT; 1088fc48b7a6SYuval Mintz command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT; 1089fc48b7a6SYuval Mintz command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT; 1090fe56b9e6SYuval Mintz 1091fe56b9e6SYuval Mintz /* Make sure notification is not set before initiating final cleanup */ 1092fe56b9e6SYuval Mintz if (REG_RD(p_hwfn, addr)) { 10931a635e48SYuval Mintz DP_NOTICE(p_hwfn, 1094fe56b9e6SYuval Mintz "Unexpected; Found final cleanup notification before initiating final cleanup\n"); 1095fe56b9e6SYuval Mintz REG_WR(p_hwfn, addr, 0); 1096fe56b9e6SYuval Mintz } 1097fe56b9e6SYuval Mintz 1098fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_IOV, 1099fe56b9e6SYuval Mintz "Sending final cleanup for PFVF[%d] [Command %08x\n]", 1100fe56b9e6SYuval Mintz id, command); 1101fe56b9e6SYuval Mintz 1102fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command); 1103fe56b9e6SYuval Mintz 1104fe56b9e6SYuval Mintz /* Poll until completion */ 1105fe56b9e6SYuval Mintz while (!REG_RD(p_hwfn, addr) && count--) 1106fe56b9e6SYuval Mintz msleep(FINAL_CLEANUP_POLL_TIME); 1107fe56b9e6SYuval Mintz 1108fe56b9e6SYuval Mintz if (REG_RD(p_hwfn, addr)) 1109fe56b9e6SYuval Mintz rc = 0; 1110fe56b9e6SYuval Mintz else 1111fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 1112fe56b9e6SYuval Mintz "Failed to receive FW final cleanup notification\n"); 1113fe56b9e6SYuval Mintz 1114fe56b9e6SYuval Mintz /* Cleanup afterwards */ 1115fe56b9e6SYuval Mintz REG_WR(p_hwfn, addr, 0); 1116fe56b9e6SYuval Mintz 1117fe56b9e6SYuval Mintz return rc; 1118fe56b9e6SYuval Mintz } 1119fe56b9e6SYuval Mintz 11209c79ddaaSMintz, Yuval static int qed_calc_hw_mode(struct qed_hwfn *p_hwfn) 1121fe56b9e6SYuval Mintz { 1122fe56b9e6SYuval Mintz int hw_mode = 0; 1123fe56b9e6SYuval Mintz 11249c79ddaaSMintz, Yuval if (QED_IS_BB_B0(p_hwfn->cdev)) { 11259c79ddaaSMintz, Yuval hw_mode |= 1 << MODE_BB; 11269c79ddaaSMintz, Yuval } else if (QED_IS_AH(p_hwfn->cdev)) { 11279c79ddaaSMintz, Yuval hw_mode |= 1 << MODE_K2; 11289c79ddaaSMintz, Yuval } else { 11299c79ddaaSMintz, Yuval DP_NOTICE(p_hwfn, "Unknown chip type %#x\n", 11309c79ddaaSMintz, Yuval p_hwfn->cdev->type); 11319c79ddaaSMintz, Yuval return -EINVAL; 11329c79ddaaSMintz, Yuval } 1133fe56b9e6SYuval Mintz 113478cea9ffSTomer Tayar switch (p_hwfn->cdev->num_ports_in_engine) { 1135fe56b9e6SYuval Mintz case 1: 1136fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_PORTS_PER_ENG_1; 1137fe56b9e6SYuval Mintz break; 1138fe56b9e6SYuval Mintz case 2: 1139fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_PORTS_PER_ENG_2; 1140fe56b9e6SYuval Mintz break; 1141fe56b9e6SYuval Mintz case 4: 1142fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_PORTS_PER_ENG_4; 1143fe56b9e6SYuval Mintz break; 1144fe56b9e6SYuval Mintz default: 1145fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n", 114678cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine); 11479c79ddaaSMintz, Yuval return -EINVAL; 1148fe56b9e6SYuval Mintz } 1149fe56b9e6SYuval Mintz 1150fe56b9e6SYuval Mintz switch (p_hwfn->cdev->mf_mode) { 1151fc48b7a6SYuval Mintz case QED_MF_DEFAULT: 1152fc48b7a6SYuval Mintz case QED_MF_NPAR: 1153fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_MF_SI; 1154fe56b9e6SYuval Mintz break; 1155fc48b7a6SYuval Mintz case QED_MF_OVLAN: 1156fc48b7a6SYuval Mintz hw_mode |= 1 << MODE_MF_SD; 1157fc48b7a6SYuval Mintz break; 1158fe56b9e6SYuval Mintz default: 1159fc48b7a6SYuval Mintz DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n"); 1160fc48b7a6SYuval Mintz hw_mode |= 1 << MODE_MF_SI; 1161fe56b9e6SYuval Mintz } 1162fe56b9e6SYuval Mintz 1163fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_ASIC; 1164fe56b9e6SYuval Mintz 11651af9dcf7SYuval Mintz if (p_hwfn->cdev->num_hwfns > 1) 11661af9dcf7SYuval Mintz hw_mode |= 1 << MODE_100G; 11671af9dcf7SYuval Mintz 1168fe56b9e6SYuval Mintz p_hwfn->hw_info.hw_mode = hw_mode; 11691af9dcf7SYuval Mintz 11701af9dcf7SYuval Mintz DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP), 11711af9dcf7SYuval Mintz "Configuring function for hw_mode: 0x%08x\n", 11721af9dcf7SYuval Mintz p_hwfn->hw_info.hw_mode); 11739c79ddaaSMintz, Yuval 11749c79ddaaSMintz, Yuval return 0; 1175fe56b9e6SYuval Mintz } 1176fe56b9e6SYuval Mintz 1177fe56b9e6SYuval Mintz /* Init run time data for all PFs on an engine. */ 1178fe56b9e6SYuval Mintz static void qed_init_cau_rt_data(struct qed_dev *cdev) 1179fe56b9e6SYuval Mintz { 1180fe56b9e6SYuval Mintz u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET; 1181d031548eSMintz, Yuval int i, igu_sb_id; 1182fe56b9e6SYuval Mintz 1183fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 1184fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1185fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 1186fe56b9e6SYuval Mintz struct qed_igu_block *p_block; 1187fe56b9e6SYuval Mintz struct cau_sb_entry sb_entry; 1188fe56b9e6SYuval Mintz 1189fe56b9e6SYuval Mintz p_igu_info = p_hwfn->hw_info.p_igu_info; 1190fe56b9e6SYuval Mintz 1191d031548eSMintz, Yuval for (igu_sb_id = 0; 1192d031548eSMintz, Yuval igu_sb_id < QED_MAPPING_MEMORY_SIZE(cdev); igu_sb_id++) { 1193d031548eSMintz, Yuval p_block = &p_igu_info->entry[igu_sb_id]; 1194d031548eSMintz, Yuval 1195fe56b9e6SYuval Mintz if (!p_block->is_pf) 1196fe56b9e6SYuval Mintz continue; 1197fe56b9e6SYuval Mintz 1198fe56b9e6SYuval Mintz qed_init_cau_sb_entry(p_hwfn, &sb_entry, 11991a635e48SYuval Mintz p_block->function_id, 0, 0); 1200d031548eSMintz, Yuval STORE_RT_REG_AGG(p_hwfn, offset + igu_sb_id * 2, 1201d031548eSMintz, Yuval sb_entry); 1202fe56b9e6SYuval Mintz } 1203fe56b9e6SYuval Mintz } 1204fe56b9e6SYuval Mintz } 1205fe56b9e6SYuval Mintz 120660afed72STomer Tayar static void qed_init_cache_line_size(struct qed_hwfn *p_hwfn, 120760afed72STomer Tayar struct qed_ptt *p_ptt) 120860afed72STomer Tayar { 120960afed72STomer Tayar u32 val, wr_mbs, cache_line_size; 121060afed72STomer Tayar 121160afed72STomer Tayar val = qed_rd(p_hwfn, p_ptt, PSWRQ2_REG_WR_MBS0); 121260afed72STomer Tayar switch (val) { 121360afed72STomer Tayar case 0: 121460afed72STomer Tayar wr_mbs = 128; 121560afed72STomer Tayar break; 121660afed72STomer Tayar case 1: 121760afed72STomer Tayar wr_mbs = 256; 121860afed72STomer Tayar break; 121960afed72STomer Tayar case 2: 122060afed72STomer Tayar wr_mbs = 512; 122160afed72STomer Tayar break; 122260afed72STomer Tayar default: 122360afed72STomer Tayar DP_INFO(p_hwfn, 122460afed72STomer Tayar "Unexpected value of PSWRQ2_REG_WR_MBS0 [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n", 122560afed72STomer Tayar val); 122660afed72STomer Tayar return; 122760afed72STomer Tayar } 122860afed72STomer Tayar 122960afed72STomer Tayar cache_line_size = min_t(u32, L1_CACHE_BYTES, wr_mbs); 123060afed72STomer Tayar switch (cache_line_size) { 123160afed72STomer Tayar case 32: 123260afed72STomer Tayar val = 0; 123360afed72STomer Tayar break; 123460afed72STomer Tayar case 64: 123560afed72STomer Tayar val = 1; 123660afed72STomer Tayar break; 123760afed72STomer Tayar case 128: 123860afed72STomer Tayar val = 2; 123960afed72STomer Tayar break; 124060afed72STomer Tayar case 256: 124160afed72STomer Tayar val = 3; 124260afed72STomer Tayar break; 124360afed72STomer Tayar default: 124460afed72STomer Tayar DP_INFO(p_hwfn, 124560afed72STomer Tayar "Unexpected value of cache line size [0x%x]. Avoid configuring PGLUE_B_REG_CACHE_LINE_SIZE.\n", 124660afed72STomer Tayar cache_line_size); 124760afed72STomer Tayar } 124860afed72STomer Tayar 124960afed72STomer Tayar if (L1_CACHE_BYTES > wr_mbs) 125060afed72STomer Tayar DP_INFO(p_hwfn, 125160afed72STomer Tayar "The cache line size for padding is suboptimal for performance [OS cache line size 0x%x, wr mbs 0x%x]\n", 125260afed72STomer Tayar L1_CACHE_BYTES, wr_mbs); 125360afed72STomer Tayar 125460afed72STomer Tayar STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val); 1255fc6575bcSMintz, Yuval if (val > 0) { 1256fc6575bcSMintz, Yuval STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val); 1257fc6575bcSMintz, Yuval STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val); 1258fc6575bcSMintz, Yuval } 125960afed72STomer Tayar } 126060afed72STomer Tayar 1261fe56b9e6SYuval Mintz static int qed_hw_init_common(struct qed_hwfn *p_hwfn, 12621a635e48SYuval Mintz struct qed_ptt *p_ptt, int hw_mode) 1263fe56b9e6SYuval Mintz { 1264fe56b9e6SYuval Mintz struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1265fe56b9e6SYuval Mintz struct qed_qm_common_rt_init_params params; 1266fe56b9e6SYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 12679c79ddaaSMintz, Yuval u8 vf_id, max_num_vfs; 1268dbb799c3SYuval Mintz u16 num_pfs, pf_id; 12691408cc1fSYuval Mintz u32 concrete_fid; 1270fe56b9e6SYuval Mintz int rc = 0; 1271fe56b9e6SYuval Mintz 1272fe56b9e6SYuval Mintz qed_init_cau_rt_data(cdev); 1273fe56b9e6SYuval Mintz 1274fe56b9e6SYuval Mintz /* Program GTT windows */ 1275fe56b9e6SYuval Mintz qed_gtt_init(p_hwfn); 1276fe56b9e6SYuval Mintz 1277fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 1278fe56b9e6SYuval Mintz if (p_hwfn->mcp_info->func_info.bandwidth_max) 1279fe56b9e6SYuval Mintz qm_info->pf_rl_en = 1; 1280fe56b9e6SYuval Mintz if (p_hwfn->mcp_info->func_info.bandwidth_min) 1281fe56b9e6SYuval Mintz qm_info->pf_wfq_en = 1; 1282fe56b9e6SYuval Mintz } 1283fe56b9e6SYuval Mintz 1284fe56b9e6SYuval Mintz memset(¶ms, 0, sizeof(params)); 128578cea9ffSTomer Tayar params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engine; 1286fe56b9e6SYuval Mintz params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port; 1287fe56b9e6SYuval Mintz params.pf_rl_en = qm_info->pf_rl_en; 1288fe56b9e6SYuval Mintz params.pf_wfq_en = qm_info->pf_wfq_en; 1289fe56b9e6SYuval Mintz params.vport_rl_en = qm_info->vport_rl_en; 1290fe56b9e6SYuval Mintz params.vport_wfq_en = qm_info->vport_wfq_en; 1291fe56b9e6SYuval Mintz params.port_params = qm_info->qm_port_params; 1292fe56b9e6SYuval Mintz 1293fe56b9e6SYuval Mintz qed_qm_common_rt_init(p_hwfn, ¶ms); 1294fe56b9e6SYuval Mintz 1295fe56b9e6SYuval Mintz qed_cxt_hw_init_common(p_hwfn); 1296fe56b9e6SYuval Mintz 129760afed72STomer Tayar qed_init_cache_line_size(p_hwfn, p_ptt); 129860afed72STomer Tayar 1299fe56b9e6SYuval Mintz rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode); 13001a635e48SYuval Mintz if (rc) 1301fe56b9e6SYuval Mintz return rc; 1302fe56b9e6SYuval Mintz 1303fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0); 1304fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1); 1305fe56b9e6SYuval Mintz 1306dbb799c3SYuval Mintz if (QED_IS_BB(p_hwfn->cdev)) { 1307dbb799c3SYuval Mintz num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev); 1308dbb799c3SYuval Mintz for (pf_id = 0; pf_id < num_pfs; pf_id++) { 1309dbb799c3SYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, pf_id); 1310dbb799c3SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1311dbb799c3SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1312dbb799c3SYuval Mintz } 1313dbb799c3SYuval Mintz /* pretend to original PF */ 1314dbb799c3SYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 1315dbb799c3SYuval Mintz } 1316fe56b9e6SYuval Mintz 13179c79ddaaSMintz, Yuval max_num_vfs = QED_IS_AH(cdev) ? MAX_NUM_VFS_K2 : MAX_NUM_VFS_BB; 13189c79ddaaSMintz, Yuval for (vf_id = 0; vf_id < max_num_vfs; vf_id++) { 13191408cc1fSYuval Mintz concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id); 13201408cc1fSYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid); 13211408cc1fSYuval Mintz qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1); 132205fafbfbSYuval Mintz qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0); 132305fafbfbSYuval Mintz qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1); 132405fafbfbSYuval Mintz qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0); 13251408cc1fSYuval Mintz } 13261408cc1fSYuval Mintz /* pretend to original PF */ 13271408cc1fSYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 13281408cc1fSYuval Mintz 1329fe56b9e6SYuval Mintz return rc; 1330fe56b9e6SYuval Mintz } 1331fe56b9e6SYuval Mintz 133251ff1725SRam Amrani static int 133351ff1725SRam Amrani qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn, 133451ff1725SRam Amrani struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus) 133551ff1725SRam Amrani { 1336107392b7SRam Amrani u32 dpi_bit_shift, dpi_count, dpi_page_size; 133751ff1725SRam Amrani u32 min_dpis; 1338107392b7SRam Amrani u32 n_wids; 133951ff1725SRam Amrani 134051ff1725SRam Amrani /* Calculate DPI size */ 1341107392b7SRam Amrani n_wids = max_t(u32, QED_MIN_WIDS, n_cpus); 1342107392b7SRam Amrani dpi_page_size = QED_WID_SIZE * roundup_pow_of_two(n_wids); 1343107392b7SRam Amrani dpi_page_size = (dpi_page_size + PAGE_SIZE - 1) & ~(PAGE_SIZE - 1); 134451ff1725SRam Amrani dpi_bit_shift = ilog2(dpi_page_size / 4096); 134551ff1725SRam Amrani dpi_count = pwm_region_size / dpi_page_size; 134651ff1725SRam Amrani 134751ff1725SRam Amrani min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis; 134851ff1725SRam Amrani min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis); 134951ff1725SRam Amrani 135051ff1725SRam Amrani p_hwfn->dpi_size = dpi_page_size; 135151ff1725SRam Amrani p_hwfn->dpi_count = dpi_count; 135251ff1725SRam Amrani 135351ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift); 135451ff1725SRam Amrani 135551ff1725SRam Amrani if (dpi_count < min_dpis) 135651ff1725SRam Amrani return -EINVAL; 135751ff1725SRam Amrani 135851ff1725SRam Amrani return 0; 135951ff1725SRam Amrani } 136051ff1725SRam Amrani 136151ff1725SRam Amrani enum QED_ROCE_EDPM_MODE { 136251ff1725SRam Amrani QED_ROCE_EDPM_MODE_ENABLE = 0, 136351ff1725SRam Amrani QED_ROCE_EDPM_MODE_FORCE_ON = 1, 136451ff1725SRam Amrani QED_ROCE_EDPM_MODE_DISABLE = 2, 136551ff1725SRam Amrani }; 136651ff1725SRam Amrani 136751ff1725SRam Amrani static int 136851ff1725SRam Amrani qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 136951ff1725SRam Amrani { 137051ff1725SRam Amrani u32 pwm_regsize, norm_regsize; 137151ff1725SRam Amrani u32 non_pwm_conn, min_addr_reg1; 137220b1bd96SRam Amrani u32 db_bar_size, n_cpus = 1; 137351ff1725SRam Amrani u32 roce_edpm_mode; 137451ff1725SRam Amrani u32 pf_dems_shift; 137551ff1725SRam Amrani int rc = 0; 137651ff1725SRam Amrani u8 cond; 137751ff1725SRam Amrani 137815582962SRahul Verma db_bar_size = qed_hw_bar_size(p_hwfn, p_ptt, BAR_ID_1); 137951ff1725SRam Amrani if (p_hwfn->cdev->num_hwfns > 1) 138051ff1725SRam Amrani db_bar_size /= 2; 138151ff1725SRam Amrani 138251ff1725SRam Amrani /* Calculate doorbell regions */ 138351ff1725SRam Amrani non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) + 138451ff1725SRam Amrani qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE, 138551ff1725SRam Amrani NULL) + 138651ff1725SRam Amrani qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, 138751ff1725SRam Amrani NULL); 1388a82dadbcSRam Amrani norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, PAGE_SIZE); 138951ff1725SRam Amrani min_addr_reg1 = norm_regsize / 4096; 139051ff1725SRam Amrani pwm_regsize = db_bar_size - norm_regsize; 139151ff1725SRam Amrani 139251ff1725SRam Amrani /* Check that the normal and PWM sizes are valid */ 139351ff1725SRam Amrani if (db_bar_size < norm_regsize) { 139451ff1725SRam Amrani DP_ERR(p_hwfn->cdev, 139551ff1725SRam Amrani "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n", 139651ff1725SRam Amrani db_bar_size, norm_regsize); 139751ff1725SRam Amrani return -EINVAL; 139851ff1725SRam Amrani } 139951ff1725SRam Amrani 140051ff1725SRam Amrani if (pwm_regsize < QED_MIN_PWM_REGION) { 140151ff1725SRam Amrani DP_ERR(p_hwfn->cdev, 140251ff1725SRam Amrani "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n", 140351ff1725SRam Amrani pwm_regsize, 140451ff1725SRam Amrani QED_MIN_PWM_REGION, db_bar_size, norm_regsize); 140551ff1725SRam Amrani return -EINVAL; 140651ff1725SRam Amrani } 140751ff1725SRam Amrani 140851ff1725SRam Amrani /* Calculate number of DPIs */ 140951ff1725SRam Amrani roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode; 141051ff1725SRam Amrani if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) || 141151ff1725SRam Amrani ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) { 141251ff1725SRam Amrani /* Either EDPM is mandatory, or we are attempting to allocate a 141351ff1725SRam Amrani * WID per CPU. 141451ff1725SRam Amrani */ 1415c2dedf87SRam Amrani n_cpus = num_present_cpus(); 141651ff1725SRam Amrani rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 141751ff1725SRam Amrani } 141851ff1725SRam Amrani 141951ff1725SRam Amrani cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) || 142051ff1725SRam Amrani (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE); 142151ff1725SRam Amrani if (cond || p_hwfn->dcbx_no_edpm) { 142251ff1725SRam Amrani /* Either EDPM is disabled from user configuration, or it is 142351ff1725SRam Amrani * disabled via DCBx, or it is not mandatory and we failed to 142451ff1725SRam Amrani * allocated a WID per CPU. 142551ff1725SRam Amrani */ 142651ff1725SRam Amrani n_cpus = 1; 142751ff1725SRam Amrani rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 142851ff1725SRam Amrani 142951ff1725SRam Amrani if (cond) 143051ff1725SRam Amrani qed_rdma_dpm_bar(p_hwfn, p_ptt); 143151ff1725SRam Amrani } 143251ff1725SRam Amrani 143320b1bd96SRam Amrani p_hwfn->wid_count = (u16) n_cpus; 143420b1bd96SRam Amrani 143551ff1725SRam Amrani DP_INFO(p_hwfn, 143651ff1725SRam Amrani "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n", 143751ff1725SRam Amrani norm_regsize, 143851ff1725SRam Amrani pwm_regsize, 143951ff1725SRam Amrani p_hwfn->dpi_size, 144051ff1725SRam Amrani p_hwfn->dpi_count, 144151ff1725SRam Amrani ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ? 144251ff1725SRam Amrani "disabled" : "enabled"); 144351ff1725SRam Amrani 144451ff1725SRam Amrani if (rc) { 144551ff1725SRam Amrani DP_ERR(p_hwfn, 144651ff1725SRam Amrani "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n", 144751ff1725SRam Amrani p_hwfn->dpi_count, 144851ff1725SRam Amrani p_hwfn->pf_params.rdma_pf_params.min_dpis); 144951ff1725SRam Amrani return -EINVAL; 145051ff1725SRam Amrani } 145151ff1725SRam Amrani 145251ff1725SRam Amrani p_hwfn->dpi_start_offset = norm_regsize; 145351ff1725SRam Amrani 145451ff1725SRam Amrani /* DEMS size is configured log2 of DWORDs, hence the division by 4 */ 145551ff1725SRam Amrani pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4); 145651ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift); 145751ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1); 145851ff1725SRam Amrani 145951ff1725SRam Amrani return 0; 146051ff1725SRam Amrani } 146151ff1725SRam Amrani 1462fe56b9e6SYuval Mintz static int qed_hw_init_port(struct qed_hwfn *p_hwfn, 14631a635e48SYuval Mintz struct qed_ptt *p_ptt, int hw_mode) 1464fe56b9e6SYuval Mintz { 1465fc6575bcSMintz, Yuval int rc = 0; 1466fc6575bcSMintz, Yuval 1467fc6575bcSMintz, Yuval rc = qed_init_run(p_hwfn, p_ptt, PHASE_PORT, p_hwfn->port_id, hw_mode); 1468fc6575bcSMintz, Yuval if (rc) 1469fc6575bcSMintz, Yuval return rc; 1470fc6575bcSMintz, Yuval 1471fc6575bcSMintz, Yuval qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_MASTER_WRITE_PAD_ENABLE, 0); 1472fc6575bcSMintz, Yuval 1473fc6575bcSMintz, Yuval return 0; 1474fe56b9e6SYuval Mintz } 1475fe56b9e6SYuval Mintz 1476fe56b9e6SYuval Mintz static int qed_hw_init_pf(struct qed_hwfn *p_hwfn, 1477fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 147819968430SChopra, Manish struct qed_tunnel_info *p_tunn, 1479fe56b9e6SYuval Mintz int hw_mode, 1480fe56b9e6SYuval Mintz bool b_hw_start, 1481fe56b9e6SYuval Mintz enum qed_int_mode int_mode, 1482fe56b9e6SYuval Mintz bool allow_npar_tx_switch) 1483fe56b9e6SYuval Mintz { 1484fe56b9e6SYuval Mintz u8 rel_pf_id = p_hwfn->rel_pf_id; 1485fe56b9e6SYuval Mintz int rc = 0; 1486fe56b9e6SYuval Mintz 1487fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 1488fe56b9e6SYuval Mintz struct qed_mcp_function_info *p_info; 1489fe56b9e6SYuval Mintz 1490fe56b9e6SYuval Mintz p_info = &p_hwfn->mcp_info->func_info; 1491fe56b9e6SYuval Mintz if (p_info->bandwidth_min) 1492fe56b9e6SYuval Mintz p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min; 1493fe56b9e6SYuval Mintz 1494fe56b9e6SYuval Mintz /* Update rate limit once we'll actually have a link */ 14954b01e519SManish Chopra p_hwfn->qm_info.pf_rl = 100000; 1496fe56b9e6SYuval Mintz } 1497fe56b9e6SYuval Mintz 149815582962SRahul Verma qed_cxt_hw_init_pf(p_hwfn, p_ptt); 1499fe56b9e6SYuval Mintz 1500fe56b9e6SYuval Mintz qed_int_igu_init_rt(p_hwfn); 1501fe56b9e6SYuval Mintz 1502fe56b9e6SYuval Mintz /* Set VLAN in NIG if needed */ 15031a635e48SYuval Mintz if (hw_mode & BIT(MODE_MF_SD)) { 1504fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n"); 1505fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1); 1506fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET, 1507fe56b9e6SYuval Mintz p_hwfn->hw_info.ovlan); 1508fe56b9e6SYuval Mintz } 1509fe56b9e6SYuval Mintz 1510fe56b9e6SYuval Mintz /* Enable classification by MAC if needed */ 15111a635e48SYuval Mintz if (hw_mode & BIT(MODE_MF_SI)) { 1512fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 1513fe56b9e6SYuval Mintz "Configuring TAGMAC_CLS_TYPE\n"); 1514fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, 1515fe56b9e6SYuval Mintz NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1); 1516fe56b9e6SYuval Mintz } 1517fe56b9e6SYuval Mintz 1518a2e7699eSTomer Tayar /* Protocol Configuration */ 1519dbb799c3SYuval Mintz STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 1520dbb799c3SYuval Mintz (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0); 15211e128c81SArun Easi STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 15221e128c81SArun Easi (p_hwfn->hw_info.personality == QED_PCI_FCOE) ? 1 : 0); 1523fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0); 1524fe56b9e6SYuval Mintz 1525fe56b9e6SYuval Mintz /* Cleanup chip from previous driver if such remains exist */ 15260b55e27dSYuval Mintz rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false); 15271a635e48SYuval Mintz if (rc) 1528fe56b9e6SYuval Mintz return rc; 1529fe56b9e6SYuval Mintz 1530fe56b9e6SYuval Mintz /* PF Init sequence */ 1531fe56b9e6SYuval Mintz rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode); 1532fe56b9e6SYuval Mintz if (rc) 1533fe56b9e6SYuval Mintz return rc; 1534fe56b9e6SYuval Mintz 1535fe56b9e6SYuval Mintz /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */ 1536fe56b9e6SYuval Mintz rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode); 1537fe56b9e6SYuval Mintz if (rc) 1538fe56b9e6SYuval Mintz return rc; 1539fe56b9e6SYuval Mintz 1540fe56b9e6SYuval Mintz /* Pure runtime initializations - directly to the HW */ 1541fe56b9e6SYuval Mintz qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true); 1542fe56b9e6SYuval Mintz 154351ff1725SRam Amrani rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt); 154451ff1725SRam Amrani if (rc) 154551ff1725SRam Amrani return rc; 154651ff1725SRam Amrani 1547fe56b9e6SYuval Mintz if (b_hw_start) { 1548fe56b9e6SYuval Mintz /* enable interrupts */ 1549fe56b9e6SYuval Mintz qed_int_igu_enable(p_hwfn, p_ptt, int_mode); 1550fe56b9e6SYuval Mintz 1551fe56b9e6SYuval Mintz /* send function start command */ 15524f64675fSManish Chopra rc = qed_sp_pf_start(p_hwfn, p_ptt, p_tunn, 15534f64675fSManish Chopra p_hwfn->cdev->mf_mode, 1554831bfb0eSYuval Mintz allow_npar_tx_switch); 15551e128c81SArun Easi if (rc) { 1556fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Function start ramrod failed\n"); 15571e128c81SArun Easi return rc; 15581e128c81SArun Easi } 15591e128c81SArun Easi if (p_hwfn->hw_info.personality == QED_PCI_FCOE) { 15601e128c81SArun Easi qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TAG1, BIT(2)); 15611e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 15621e128c81SArun Easi PRS_REG_PKT_LEN_STAT_TAGS_NOT_COUNTED_FIRST, 15631e128c81SArun Easi 0x100); 15641e128c81SArun Easi } 1565fe56b9e6SYuval Mintz } 1566fe56b9e6SYuval Mintz return rc; 1567fe56b9e6SYuval Mintz } 1568fe56b9e6SYuval Mintz 1569fe56b9e6SYuval Mintz static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn, 1570fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1571fe56b9e6SYuval Mintz u8 enable) 1572fe56b9e6SYuval Mintz { 1573fe56b9e6SYuval Mintz u32 delay_idx = 0, val, set_val = enable ? 1 : 0; 1574fe56b9e6SYuval Mintz 1575fe56b9e6SYuval Mintz /* Change PF in PXP */ 1576fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 1577fe56b9e6SYuval Mintz PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val); 1578fe56b9e6SYuval Mintz 1579fe56b9e6SYuval Mintz /* wait until value is set - try for 1 second every 50us */ 1580fe56b9e6SYuval Mintz for (delay_idx = 0; delay_idx < 20000; delay_idx++) { 1581fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, 1582fe56b9e6SYuval Mintz PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1583fe56b9e6SYuval Mintz if (val == set_val) 1584fe56b9e6SYuval Mintz break; 1585fe56b9e6SYuval Mintz 1586fe56b9e6SYuval Mintz usleep_range(50, 60); 1587fe56b9e6SYuval Mintz } 1588fe56b9e6SYuval Mintz 1589fe56b9e6SYuval Mintz if (val != set_val) { 1590fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 1591fe56b9e6SYuval Mintz "PFID_ENABLE_MASTER wasn't changed after a second\n"); 1592fe56b9e6SYuval Mintz return -EAGAIN; 1593fe56b9e6SYuval Mintz } 1594fe56b9e6SYuval Mintz 1595fe56b9e6SYuval Mintz return 0; 1596fe56b9e6SYuval Mintz } 1597fe56b9e6SYuval Mintz 1598fe56b9e6SYuval Mintz static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn, 1599fe56b9e6SYuval Mintz struct qed_ptt *p_main_ptt) 1600fe56b9e6SYuval Mintz { 1601fe56b9e6SYuval Mintz /* Read shadow of current MFW mailbox */ 1602fe56b9e6SYuval Mintz qed_mcp_read_mb(p_hwfn, p_main_ptt); 1603fe56b9e6SYuval Mintz memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 16041a635e48SYuval Mintz p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length); 1605fe56b9e6SYuval Mintz } 1606fe56b9e6SYuval Mintz 16075d24bcf1STomer Tayar static void 16085d24bcf1STomer Tayar qed_fill_load_req_params(struct qed_load_req_params *p_load_req, 16095d24bcf1STomer Tayar struct qed_drv_load_params *p_drv_load) 16105d24bcf1STomer Tayar { 16115d24bcf1STomer Tayar memset(p_load_req, 0, sizeof(*p_load_req)); 16125d24bcf1STomer Tayar 16135d24bcf1STomer Tayar p_load_req->drv_role = p_drv_load->is_crash_kernel ? 16145d24bcf1STomer Tayar QED_DRV_ROLE_KDUMP : QED_DRV_ROLE_OS; 16155d24bcf1STomer Tayar p_load_req->timeout_val = p_drv_load->mfw_timeout_val; 16165d24bcf1STomer Tayar p_load_req->avoid_eng_reset = p_drv_load->avoid_eng_reset; 16175d24bcf1STomer Tayar p_load_req->override_force_load = p_drv_load->override_force_load; 16185d24bcf1STomer Tayar } 16195d24bcf1STomer Tayar 1620eaf3c0c6SChopra, Manish static int qed_vf_start(struct qed_hwfn *p_hwfn, 1621eaf3c0c6SChopra, Manish struct qed_hw_init_params *p_params) 1622eaf3c0c6SChopra, Manish { 1623eaf3c0c6SChopra, Manish if (p_params->p_tunn) { 1624eaf3c0c6SChopra, Manish qed_vf_set_vf_start_tunn_update_param(p_params->p_tunn); 1625eaf3c0c6SChopra, Manish qed_vf_pf_tunnel_param_update(p_hwfn, p_params->p_tunn); 1626eaf3c0c6SChopra, Manish } 1627eaf3c0c6SChopra, Manish 1628eaf3c0c6SChopra, Manish p_hwfn->b_int_enabled = 1; 1629eaf3c0c6SChopra, Manish 1630eaf3c0c6SChopra, Manish return 0; 1631eaf3c0c6SChopra, Manish } 1632eaf3c0c6SChopra, Manish 1633c0c2d0b4SMintz, Yuval int qed_hw_init(struct qed_dev *cdev, struct qed_hw_init_params *p_params) 1634fe56b9e6SYuval Mintz { 16355d24bcf1STomer Tayar struct qed_load_req_params load_req_params; 16360fefbfbaSSudarsana Kalluru u32 load_code, param, drv_mb_param; 16370fefbfbaSSudarsana Kalluru bool b_default_mtu = true; 16380fefbfbaSSudarsana Kalluru struct qed_hwfn *p_hwfn; 16390fefbfbaSSudarsana Kalluru int rc = 0, mfw_rc, i; 1640fe56b9e6SYuval Mintz 1641c0c2d0b4SMintz, Yuval if ((p_params->int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) { 1642bb13ace7SSudarsana Reddy Kalluru DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n"); 1643bb13ace7SSudarsana Reddy Kalluru return -EINVAL; 1644bb13ace7SSudarsana Reddy Kalluru } 1645bb13ace7SSudarsana Reddy Kalluru 16461408cc1fSYuval Mintz if (IS_PF(cdev)) { 1647c0c2d0b4SMintz, Yuval rc = qed_init_fw_data(cdev, p_params->bin_fw_data); 16481a635e48SYuval Mintz if (rc) 1649fe56b9e6SYuval Mintz return rc; 16501408cc1fSYuval Mintz } 1651fe56b9e6SYuval Mintz 1652fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 1653fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1654fe56b9e6SYuval Mintz 16550fefbfbaSSudarsana Kalluru /* If management didn't provide a default, set one of our own */ 16560fefbfbaSSudarsana Kalluru if (!p_hwfn->hw_info.mtu) { 16570fefbfbaSSudarsana Kalluru p_hwfn->hw_info.mtu = 1500; 16580fefbfbaSSudarsana Kalluru b_default_mtu = false; 16590fefbfbaSSudarsana Kalluru } 16600fefbfbaSSudarsana Kalluru 16611408cc1fSYuval Mintz if (IS_VF(cdev)) { 1662eaf3c0c6SChopra, Manish qed_vf_start(p_hwfn, p_params); 16631408cc1fSYuval Mintz continue; 16641408cc1fSYuval Mintz } 16651408cc1fSYuval Mintz 1666fe56b9e6SYuval Mintz /* Enable DMAE in PXP */ 1667fe56b9e6SYuval Mintz rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true); 1668fe56b9e6SYuval Mintz 16699c79ddaaSMintz, Yuval rc = qed_calc_hw_mode(p_hwfn); 16709c79ddaaSMintz, Yuval if (rc) 16719c79ddaaSMintz, Yuval return rc; 1672fe56b9e6SYuval Mintz 16735d24bcf1STomer Tayar qed_fill_load_req_params(&load_req_params, 16745d24bcf1STomer Tayar p_params->p_drv_load_params); 16755d24bcf1STomer Tayar rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, 16765d24bcf1STomer Tayar &load_req_params); 1677fe56b9e6SYuval Mintz if (rc) { 16785d24bcf1STomer Tayar DP_NOTICE(p_hwfn, "Failed sending a LOAD_REQ command\n"); 1679fe56b9e6SYuval Mintz return rc; 1680fe56b9e6SYuval Mintz } 1681fe56b9e6SYuval Mintz 16825d24bcf1STomer Tayar load_code = load_req_params.load_code; 1683fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 16845d24bcf1STomer Tayar "Load request was sent. Load code: 0x%x\n", 16855d24bcf1STomer Tayar load_code); 16865d24bcf1STomer Tayar 1687645874e5SSudarsana Reddy Kalluru qed_mcp_set_capabilities(p_hwfn, p_hwfn->p_main_ptt); 1688645874e5SSudarsana Reddy Kalluru 16895d24bcf1STomer Tayar qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt); 1690fe56b9e6SYuval Mintz 1691fe56b9e6SYuval Mintz p_hwfn->first_on_engine = (load_code == 1692fe56b9e6SYuval Mintz FW_MSG_CODE_DRV_LOAD_ENGINE); 1693fe56b9e6SYuval Mintz 1694fe56b9e6SYuval Mintz switch (load_code) { 1695fe56b9e6SYuval Mintz case FW_MSG_CODE_DRV_LOAD_ENGINE: 1696fe56b9e6SYuval Mintz rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt, 1697fe56b9e6SYuval Mintz p_hwfn->hw_info.hw_mode); 1698fe56b9e6SYuval Mintz if (rc) 1699fe56b9e6SYuval Mintz break; 1700fe56b9e6SYuval Mintz /* Fall into */ 1701fe56b9e6SYuval Mintz case FW_MSG_CODE_DRV_LOAD_PORT: 1702fe56b9e6SYuval Mintz rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt, 1703fe56b9e6SYuval Mintz p_hwfn->hw_info.hw_mode); 1704fe56b9e6SYuval Mintz if (rc) 1705fe56b9e6SYuval Mintz break; 1706fe56b9e6SYuval Mintz 1707fe56b9e6SYuval Mintz /* Fall into */ 1708fe56b9e6SYuval Mintz case FW_MSG_CODE_DRV_LOAD_FUNCTION: 1709fe56b9e6SYuval Mintz rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt, 1710c0c2d0b4SMintz, Yuval p_params->p_tunn, 1711c0c2d0b4SMintz, Yuval p_hwfn->hw_info.hw_mode, 1712c0c2d0b4SMintz, Yuval p_params->b_hw_start, 1713c0c2d0b4SMintz, Yuval p_params->int_mode, 1714c0c2d0b4SMintz, Yuval p_params->allow_npar_tx_switch); 1715fe56b9e6SYuval Mintz break; 1716fe56b9e6SYuval Mintz default: 1717c0c2d0b4SMintz, Yuval DP_NOTICE(p_hwfn, 1718c0c2d0b4SMintz, Yuval "Unexpected load code [0x%08x]", load_code); 1719fe56b9e6SYuval Mintz rc = -EINVAL; 1720fe56b9e6SYuval Mintz break; 1721fe56b9e6SYuval Mintz } 1722fe56b9e6SYuval Mintz 1723fe56b9e6SYuval Mintz if (rc) 1724fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 1725fe56b9e6SYuval Mintz "init phase failed for loadcode 0x%x (rc %d)\n", 1726fe56b9e6SYuval Mintz load_code, rc); 1727fe56b9e6SYuval Mintz 1728fe56b9e6SYuval Mintz /* ACK mfw regardless of success or failure of initialization */ 1729fe56b9e6SYuval Mintz mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1730fe56b9e6SYuval Mintz DRV_MSG_CODE_LOAD_DONE, 1731fe56b9e6SYuval Mintz 0, &load_code, ¶m); 1732fe56b9e6SYuval Mintz if (rc) 1733fe56b9e6SYuval Mintz return rc; 1734fe56b9e6SYuval Mintz if (mfw_rc) { 1735fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n"); 1736fe56b9e6SYuval Mintz return mfw_rc; 1737fe56b9e6SYuval Mintz } 1738fe56b9e6SYuval Mintz 1739fc561c8bSTomer Tayar /* Check if there is a DID mismatch between nvm-cfg/efuse */ 1740fc561c8bSTomer Tayar if (param & FW_MB_PARAM_LOAD_DONE_DID_EFUSE_ERROR) 1741fc561c8bSTomer Tayar DP_NOTICE(p_hwfn, 1742fc561c8bSTomer Tayar "warning: device configuration is not supported on this board type. The device may not function as expected.\n"); 1743fc561c8bSTomer Tayar 174439651abdSSudarsana Reddy Kalluru /* send DCBX attention request command */ 174539651abdSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, 174639651abdSSudarsana Reddy Kalluru QED_MSG_DCB, 174739651abdSSudarsana Reddy Kalluru "sending phony dcbx set command to trigger DCBx attention handling\n"); 174839651abdSSudarsana Reddy Kalluru mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 174939651abdSSudarsana Reddy Kalluru DRV_MSG_CODE_SET_DCBX, 175039651abdSSudarsana Reddy Kalluru 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT, 175139651abdSSudarsana Reddy Kalluru &load_code, ¶m); 175239651abdSSudarsana Reddy Kalluru if (mfw_rc) { 175339651abdSSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 175439651abdSSudarsana Reddy Kalluru "Failed to send DCBX attention request\n"); 175539651abdSSudarsana Reddy Kalluru return mfw_rc; 175639651abdSSudarsana Reddy Kalluru } 175739651abdSSudarsana Reddy Kalluru 1758fe56b9e6SYuval Mintz p_hwfn->hw_init_done = true; 1759fe56b9e6SYuval Mintz } 1760fe56b9e6SYuval Mintz 17610fefbfbaSSudarsana Kalluru if (IS_PF(cdev)) { 17620fefbfbaSSudarsana Kalluru p_hwfn = QED_LEADING_HWFN(cdev); 17635d24bcf1STomer Tayar drv_mb_param = STORM_FW_VERSION; 17640fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 17650fefbfbaSSudarsana Kalluru DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER, 17660fefbfbaSSudarsana Kalluru drv_mb_param, &load_code, ¶m); 17670fefbfbaSSudarsana Kalluru if (rc) 17680fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, "Failed to update firmware version\n"); 17690fefbfbaSSudarsana Kalluru 17700fefbfbaSSudarsana Kalluru if (!b_default_mtu) { 17710fefbfbaSSudarsana Kalluru rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt, 17720fefbfbaSSudarsana Kalluru p_hwfn->hw_info.mtu); 17730fefbfbaSSudarsana Kalluru if (rc) 17740fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, 17750fefbfbaSSudarsana Kalluru "Failed to update default mtu\n"); 17760fefbfbaSSudarsana Kalluru } 17770fefbfbaSSudarsana Kalluru 17780fefbfbaSSudarsana Kalluru rc = qed_mcp_ov_update_driver_state(p_hwfn, 17790fefbfbaSSudarsana Kalluru p_hwfn->p_main_ptt, 17800fefbfbaSSudarsana Kalluru QED_OV_DRIVER_STATE_DISABLED); 17810fefbfbaSSudarsana Kalluru if (rc) 17820fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, "Failed to update driver state\n"); 17830fefbfbaSSudarsana Kalluru 17840fefbfbaSSudarsana Kalluru rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt, 17850fefbfbaSSudarsana Kalluru QED_OV_ESWITCH_VEB); 17860fefbfbaSSudarsana Kalluru if (rc) 17870fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, "Failed to update eswitch mode\n"); 17880fefbfbaSSudarsana Kalluru } 17890fefbfbaSSudarsana Kalluru 1790fe56b9e6SYuval Mintz return 0; 1791fe56b9e6SYuval Mintz } 1792fe56b9e6SYuval Mintz 1793fe56b9e6SYuval Mintz #define QED_HW_STOP_RETRY_LIMIT (10) 17941a635e48SYuval Mintz static void qed_hw_timers_stop(struct qed_dev *cdev, 17951a635e48SYuval Mintz struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 17968c925c44SYuval Mintz { 17978c925c44SYuval Mintz int i; 17988c925c44SYuval Mintz 17998c925c44SYuval Mintz /* close timers */ 18008c925c44SYuval Mintz qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0); 18018c925c44SYuval Mintz qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0); 18028c925c44SYuval Mintz 18038c925c44SYuval Mintz for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) { 18048c925c44SYuval Mintz if ((!qed_rd(p_hwfn, p_ptt, 18058c925c44SYuval Mintz TM_REG_PF_SCAN_ACTIVE_CONN)) && 18061a635e48SYuval Mintz (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK))) 18078c925c44SYuval Mintz break; 18088c925c44SYuval Mintz 18098c925c44SYuval Mintz /* Dependent on number of connection/tasks, possibly 18108c925c44SYuval Mintz * 1ms sleep is required between polls 18118c925c44SYuval Mintz */ 18128c925c44SYuval Mintz usleep_range(1000, 2000); 18138c925c44SYuval Mintz } 18148c925c44SYuval Mintz 18158c925c44SYuval Mintz if (i < QED_HW_STOP_RETRY_LIMIT) 18168c925c44SYuval Mintz return; 18178c925c44SYuval Mintz 18188c925c44SYuval Mintz DP_NOTICE(p_hwfn, 18198c925c44SYuval Mintz "Timers linear scans are not over [Connection %02x Tasks %02x]\n", 18208c925c44SYuval Mintz (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN), 18218c925c44SYuval Mintz (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)); 18228c925c44SYuval Mintz } 18238c925c44SYuval Mintz 18248c925c44SYuval Mintz void qed_hw_timers_stop_all(struct qed_dev *cdev) 18258c925c44SYuval Mintz { 18268c925c44SYuval Mintz int j; 18278c925c44SYuval Mintz 18288c925c44SYuval Mintz for_each_hwfn(cdev, j) { 18298c925c44SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 18308c925c44SYuval Mintz struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 18318c925c44SYuval Mintz 18328c925c44SYuval Mintz qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 18338c925c44SYuval Mintz } 18348c925c44SYuval Mintz } 18358c925c44SYuval Mintz 1836fe56b9e6SYuval Mintz int qed_hw_stop(struct qed_dev *cdev) 1837fe56b9e6SYuval Mintz { 18381226337aSTomer Tayar struct qed_hwfn *p_hwfn; 18391226337aSTomer Tayar struct qed_ptt *p_ptt; 18401226337aSTomer Tayar int rc, rc2 = 0; 18418c925c44SYuval Mintz int j; 1842fe56b9e6SYuval Mintz 1843fe56b9e6SYuval Mintz for_each_hwfn(cdev, j) { 18441226337aSTomer Tayar p_hwfn = &cdev->hwfns[j]; 18451226337aSTomer Tayar p_ptt = p_hwfn->p_main_ptt; 1846fe56b9e6SYuval Mintz 1847fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n"); 1848fe56b9e6SYuval Mintz 18491408cc1fSYuval Mintz if (IS_VF(cdev)) { 18500b55e27dSYuval Mintz qed_vf_pf_int_cleanup(p_hwfn); 18511226337aSTomer Tayar rc = qed_vf_pf_reset(p_hwfn); 18521226337aSTomer Tayar if (rc) { 18531226337aSTomer Tayar DP_NOTICE(p_hwfn, 18541226337aSTomer Tayar "qed_vf_pf_reset failed. rc = %d.\n", 18551226337aSTomer Tayar rc); 18561226337aSTomer Tayar rc2 = -EINVAL; 18571226337aSTomer Tayar } 18581408cc1fSYuval Mintz continue; 18591408cc1fSYuval Mintz } 18601408cc1fSYuval Mintz 1861fe56b9e6SYuval Mintz /* mark the hw as uninitialized... */ 1862fe56b9e6SYuval Mintz p_hwfn->hw_init_done = false; 1863fe56b9e6SYuval Mintz 18641226337aSTomer Tayar /* Send unload command to MCP */ 18651226337aSTomer Tayar rc = qed_mcp_unload_req(p_hwfn, p_ptt); 18661226337aSTomer Tayar if (rc) { 18678c925c44SYuval Mintz DP_NOTICE(p_hwfn, 18681226337aSTomer Tayar "Failed sending a UNLOAD_REQ command. rc = %d.\n", 18691226337aSTomer Tayar rc); 18701226337aSTomer Tayar rc2 = -EINVAL; 18711226337aSTomer Tayar } 18721226337aSTomer Tayar 18731226337aSTomer Tayar qed_slowpath_irq_sync(p_hwfn); 18741226337aSTomer Tayar 18751226337aSTomer Tayar /* After this point no MFW attentions are expected, e.g. prevent 18761226337aSTomer Tayar * race between pf stop and dcbx pf update. 18771226337aSTomer Tayar */ 18781226337aSTomer Tayar rc = qed_sp_pf_stop(p_hwfn); 18791226337aSTomer Tayar if (rc) { 18801226337aSTomer Tayar DP_NOTICE(p_hwfn, 18811226337aSTomer Tayar "Failed to close PF against FW [rc = %d]. Continue to stop HW to prevent illegal host access by the device.\n", 18821226337aSTomer Tayar rc); 18831226337aSTomer Tayar rc2 = -EINVAL; 18841226337aSTomer Tayar } 1885fe56b9e6SYuval Mintz 1886fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 1887fe56b9e6SYuval Mintz NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 1888fe56b9e6SYuval Mintz 1889fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1890fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 1891fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 1892fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1893fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 1894fe56b9e6SYuval Mintz 18958c925c44SYuval Mintz qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 1896fe56b9e6SYuval Mintz 1897fe56b9e6SYuval Mintz /* Disable Attention Generation */ 1898fe56b9e6SYuval Mintz qed_int_igu_disable_int(p_hwfn, p_ptt); 1899fe56b9e6SYuval Mintz 1900fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0); 1901fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0); 1902fe56b9e6SYuval Mintz 1903fe56b9e6SYuval Mintz qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true); 1904fe56b9e6SYuval Mintz 1905fe56b9e6SYuval Mintz /* Need to wait 1ms to guarantee SBs are cleared */ 1906fe56b9e6SYuval Mintz usleep_range(1000, 2000); 19071226337aSTomer Tayar 19081226337aSTomer Tayar /* Disable PF in HW blocks */ 19091226337aSTomer Tayar qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DB_ENABLE, 0); 19101226337aSTomer Tayar qed_wr(p_hwfn, p_ptt, QM_REG_PF_EN, 0); 19111226337aSTomer Tayar 19121226337aSTomer Tayar qed_mcp_unload_done(p_hwfn, p_ptt); 19131226337aSTomer Tayar if (rc) { 19141226337aSTomer Tayar DP_NOTICE(p_hwfn, 19151226337aSTomer Tayar "Failed sending a UNLOAD_DONE command. rc = %d.\n", 19161226337aSTomer Tayar rc); 19171226337aSTomer Tayar rc2 = -EINVAL; 19181226337aSTomer Tayar } 1919fe56b9e6SYuval Mintz } 1920fe56b9e6SYuval Mintz 19211408cc1fSYuval Mintz if (IS_PF(cdev)) { 19221226337aSTomer Tayar p_hwfn = QED_LEADING_HWFN(cdev); 19231226337aSTomer Tayar p_ptt = QED_LEADING_HWFN(cdev)->p_main_ptt; 19241226337aSTomer Tayar 1925fe56b9e6SYuval Mintz /* Disable DMAE in PXP - in CMT, this should only be done for 1926fe56b9e6SYuval Mintz * first hw-function, and only after all transactions have 1927fe56b9e6SYuval Mintz * stopped for all active hw-functions. 1928fe56b9e6SYuval Mintz */ 19291226337aSTomer Tayar rc = qed_change_pci_hwfn(p_hwfn, p_ptt, false); 19301226337aSTomer Tayar if (rc) { 19311226337aSTomer Tayar DP_NOTICE(p_hwfn, 19321226337aSTomer Tayar "qed_change_pci_hwfn failed. rc = %d.\n", rc); 19331226337aSTomer Tayar rc2 = -EINVAL; 19341226337aSTomer Tayar } 19351408cc1fSYuval Mintz } 1936fe56b9e6SYuval Mintz 19371226337aSTomer Tayar return rc2; 1938fe56b9e6SYuval Mintz } 1939fe56b9e6SYuval Mintz 194015582962SRahul Verma int qed_hw_stop_fastpath(struct qed_dev *cdev) 1941cee4d264SManish Chopra { 19428c925c44SYuval Mintz int j; 1943cee4d264SManish Chopra 1944cee4d264SManish Chopra for_each_hwfn(cdev, j) { 1945cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 194615582962SRahul Verma struct qed_ptt *p_ptt; 1947cee4d264SManish Chopra 1948dacd88d6SYuval Mintz if (IS_VF(cdev)) { 1949dacd88d6SYuval Mintz qed_vf_pf_int_cleanup(p_hwfn); 1950dacd88d6SYuval Mintz continue; 1951dacd88d6SYuval Mintz } 195215582962SRahul Verma p_ptt = qed_ptt_acquire(p_hwfn); 195315582962SRahul Verma if (!p_ptt) 195415582962SRahul Verma return -EAGAIN; 1955dacd88d6SYuval Mintz 1956cee4d264SManish Chopra DP_VERBOSE(p_hwfn, 19571a635e48SYuval Mintz NETIF_MSG_IFDOWN, "Shutting down the fastpath\n"); 1958cee4d264SManish Chopra 1959cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, 1960cee4d264SManish Chopra NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 1961cee4d264SManish Chopra 1962cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1963cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 1964cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 1965cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1966cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 1967cee4d264SManish Chopra 1968cee4d264SManish Chopra qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false); 1969cee4d264SManish Chopra 1970cee4d264SManish Chopra /* Need to wait 1ms to guarantee SBs are cleared */ 1971cee4d264SManish Chopra usleep_range(1000, 2000); 197215582962SRahul Verma qed_ptt_release(p_hwfn, p_ptt); 1973cee4d264SManish Chopra } 1974cee4d264SManish Chopra 197515582962SRahul Verma return 0; 197615582962SRahul Verma } 197715582962SRahul Verma 197815582962SRahul Verma int qed_hw_start_fastpath(struct qed_hwfn *p_hwfn) 1979cee4d264SManish Chopra { 198015582962SRahul Verma struct qed_ptt *p_ptt; 198115582962SRahul Verma 1982dacd88d6SYuval Mintz if (IS_VF(p_hwfn->cdev)) 198315582962SRahul Verma return 0; 198415582962SRahul Verma 198515582962SRahul Verma p_ptt = qed_ptt_acquire(p_hwfn); 198615582962SRahul Verma if (!p_ptt) 198715582962SRahul Verma return -EAGAIN; 1988dacd88d6SYuval Mintz 1989f855df22SMichal Kalderon /* If roce info is allocated it means roce is initialized and should 1990f855df22SMichal Kalderon * be enabled in searcher. 1991f855df22SMichal Kalderon */ 1992f855df22SMichal Kalderon if (p_hwfn->p_rdma_info && 1993f855df22SMichal Kalderon p_hwfn->b_rdma_enabled_in_prs) 1994f855df22SMichal Kalderon qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 0x1); 1995f855df22SMichal Kalderon 1996cee4d264SManish Chopra /* Re-open incoming traffic */ 199715582962SRahul Verma qed_wr(p_hwfn, p_ptt, NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0); 199815582962SRahul Verma qed_ptt_release(p_hwfn, p_ptt); 199915582962SRahul Verma 200015582962SRahul Verma return 0; 2001cee4d264SManish Chopra } 2002cee4d264SManish Chopra 2003fe56b9e6SYuval Mintz /* Free hwfn memory and resources acquired in hw_hwfn_prepare */ 2004fe56b9e6SYuval Mintz static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn) 2005fe56b9e6SYuval Mintz { 2006fe56b9e6SYuval Mintz qed_ptt_pool_free(p_hwfn); 2007fe56b9e6SYuval Mintz kfree(p_hwfn->hw_info.p_igu_info); 20083587cb87STomer Tayar p_hwfn->hw_info.p_igu_info = NULL; 2009fe56b9e6SYuval Mintz } 2010fe56b9e6SYuval Mintz 2011fe56b9e6SYuval Mintz /* Setup bar access */ 201212e09c69SYuval Mintz static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn) 2013fe56b9e6SYuval Mintz { 2014fe56b9e6SYuval Mintz /* clear indirect access */ 20159c79ddaaSMintz, Yuval if (QED_IS_AH(p_hwfn->cdev)) { 20169c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 20179c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_E8_F0_K2, 0); 20189c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 20199c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_EC_F0_K2, 0); 20209c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 20219c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_F0_F0_K2, 0); 20229c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 20239c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_F4_F0_K2, 0); 20249c79ddaaSMintz, Yuval } else { 20259c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 20269c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_88_F0_BB, 0); 20279c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 20289c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_8C_F0_BB, 0); 20299c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 20309c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_90_F0_BB, 0); 20319c79ddaaSMintz, Yuval qed_wr(p_hwfn, p_hwfn->p_main_ptt, 20329c79ddaaSMintz, Yuval PGLUE_B_REG_PGL_ADDR_94_F0_BB, 0); 20339c79ddaaSMintz, Yuval } 2034fe56b9e6SYuval Mintz 2035fe56b9e6SYuval Mintz /* Clean Previous errors if such exist */ 2036fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, 20371a635e48SYuval Mintz PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id); 2038fe56b9e6SYuval Mintz 2039fe56b9e6SYuval Mintz /* enable internal target-read */ 2040fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, 2041fe56b9e6SYuval Mintz PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 2042fe56b9e6SYuval Mintz } 2043fe56b9e6SYuval Mintz 2044fe56b9e6SYuval Mintz static void get_function_id(struct qed_hwfn *p_hwfn) 2045fe56b9e6SYuval Mintz { 2046fe56b9e6SYuval Mintz /* ME Register */ 20471a635e48SYuval Mintz p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn, 20481a635e48SYuval Mintz PXP_PF_ME_OPAQUE_ADDR); 2049fe56b9e6SYuval Mintz 2050fe56b9e6SYuval Mintz p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); 2051fe56b9e6SYuval Mintz 2052fe56b9e6SYuval Mintz p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf; 2053fe56b9e6SYuval Mintz p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 2054fe56b9e6SYuval Mintz PXP_CONCRETE_FID_PFID); 2055fe56b9e6SYuval Mintz p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 2056fe56b9e6SYuval Mintz PXP_CONCRETE_FID_PORT); 2057525ef5c0SYuval Mintz 2058525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, 2059525ef5c0SYuval Mintz "Read ME register: Concrete 0x%08x Opaque 0x%04x\n", 2060525ef5c0SYuval Mintz p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid); 2061fe56b9e6SYuval Mintz } 2062fe56b9e6SYuval Mintz 206325c089d7SYuval Mintz static void qed_hw_set_feat(struct qed_hwfn *p_hwfn) 206425c089d7SYuval Mintz { 206525c089d7SYuval Mintz u32 *feat_num = p_hwfn->hw_info.feat_num; 2066ebbdcc66SMintz, Yuval struct qed_sb_cnt_info sb_cnt; 2067810bb1f0SMintz, Yuval u32 non_l2_sbs = 0; 206825c089d7SYuval Mintz 2069ebbdcc66SMintz, Yuval memset(&sb_cnt, 0, sizeof(sb_cnt)); 2070ebbdcc66SMintz, Yuval qed_int_get_num_sbs(p_hwfn, &sb_cnt); 2071ebbdcc66SMintz, Yuval 20720189efb8SYuval Mintz if (IS_ENABLED(CONFIG_QED_RDMA) && 2073c851a9dcSKalderon, Michal QED_IS_RDMA_PERSONALITY(p_hwfn)) { 20740189efb8SYuval Mintz /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide 20750189efb8SYuval Mintz * the status blocks equally between L2 / RoCE but with 20760189efb8SYuval Mintz * consideration as to how many l2 queues / cnqs we have. 207751ff1725SRam Amrani */ 207851ff1725SRam Amrani feat_num[QED_RDMA_CNQ] = 2079ebbdcc66SMintz, Yuval min_t(u32, sb_cnt.cnt / 2, 208051ff1725SRam Amrani RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM)); 2081810bb1f0SMintz, Yuval 2082810bb1f0SMintz, Yuval non_l2_sbs = feat_num[QED_RDMA_CNQ]; 208351ff1725SRam Amrani } 2084c851a9dcSKalderon, Michal if (QED_IS_L2_PERSONALITY(p_hwfn)) { 2085dec26533SMintz, Yuval /* Start by allocating VF queues, then PF's */ 2086dec26533SMintz, Yuval feat_num[QED_VF_L2_QUE] = min_t(u32, 2087dec26533SMintz, Yuval RESC_NUM(p_hwfn, QED_L2_QUEUE), 2088ebbdcc66SMintz, Yuval sb_cnt.iov_cnt); 2089810bb1f0SMintz, Yuval feat_num[QED_PF_L2_QUE] = min_t(u32, 2090ebbdcc66SMintz, Yuval sb_cnt.cnt - non_l2_sbs, 2091dec26533SMintz, Yuval RESC_NUM(p_hwfn, 2092dec26533SMintz, Yuval QED_L2_QUEUE) - 2093dec26533SMintz, Yuval FEAT_NUM(p_hwfn, 2094dec26533SMintz, Yuval QED_VF_L2_QUE)); 2095dec26533SMintz, Yuval } 20965a1f965aSMintz, Yuval 2097c851a9dcSKalderon, Michal if (QED_IS_FCOE_PERSONALITY(p_hwfn)) 20983c5da942SMintz, Yuval feat_num[QED_FCOE_CQ] = min_t(u32, sb_cnt.cnt, 20993c5da942SMintz, Yuval RESC_NUM(p_hwfn, 21003c5da942SMintz, Yuval QED_CMDQS_CQS)); 21013c5da942SMintz, Yuval 2102c851a9dcSKalderon, Michal if (QED_IS_ISCSI_PERSONALITY(p_hwfn)) 2103ebbdcc66SMintz, Yuval feat_num[QED_ISCSI_CQ] = min_t(u32, sb_cnt.cnt, 210408737a3fSMintz, Yuval RESC_NUM(p_hwfn, 210508737a3fSMintz, Yuval QED_CMDQS_CQS)); 21065a1f965aSMintz, Yuval DP_VERBOSE(p_hwfn, 21075a1f965aSMintz, Yuval NETIF_MSG_PROBE, 21083c5da942SMintz, Yuval "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d FCOE_CQ=%d ISCSI_CQ=%d #SBS=%d\n", 21095a1f965aSMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE), 21105a1f965aSMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE), 21115a1f965aSMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ), 21123c5da942SMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_FCOE_CQ), 211308737a3fSMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_ISCSI_CQ), 2114ebbdcc66SMintz, Yuval (int)sb_cnt.cnt); 211525c089d7SYuval Mintz } 211625c089d7SYuval Mintz 21179c8517c4STomer Tayar const char *qed_hw_get_resc_name(enum qed_resources res_id) 21182edbff8dSTomer Tayar { 21192edbff8dSTomer Tayar switch (res_id) { 21202edbff8dSTomer Tayar case QED_L2_QUEUE: 21212edbff8dSTomer Tayar return "L2_QUEUE"; 21222edbff8dSTomer Tayar case QED_VPORT: 21232edbff8dSTomer Tayar return "VPORT"; 21242edbff8dSTomer Tayar case QED_RSS_ENG: 21252edbff8dSTomer Tayar return "RSS_ENG"; 21262edbff8dSTomer Tayar case QED_PQ: 21272edbff8dSTomer Tayar return "PQ"; 21282edbff8dSTomer Tayar case QED_RL: 21292edbff8dSTomer Tayar return "RL"; 21302edbff8dSTomer Tayar case QED_MAC: 21312edbff8dSTomer Tayar return "MAC"; 21322edbff8dSTomer Tayar case QED_VLAN: 21332edbff8dSTomer Tayar return "VLAN"; 21342edbff8dSTomer Tayar case QED_RDMA_CNQ_RAM: 21352edbff8dSTomer Tayar return "RDMA_CNQ_RAM"; 21362edbff8dSTomer Tayar case QED_ILT: 21372edbff8dSTomer Tayar return "ILT"; 21382edbff8dSTomer Tayar case QED_LL2_QUEUE: 21392edbff8dSTomer Tayar return "LL2_QUEUE"; 21402edbff8dSTomer Tayar case QED_CMDQS_CQS: 21412edbff8dSTomer Tayar return "CMDQS_CQS"; 21422edbff8dSTomer Tayar case QED_RDMA_STATS_QUEUE: 21432edbff8dSTomer Tayar return "RDMA_STATS_QUEUE"; 21449c8517c4STomer Tayar case QED_BDQ: 21459c8517c4STomer Tayar return "BDQ"; 21469c8517c4STomer Tayar case QED_SB: 21479c8517c4STomer Tayar return "SB"; 21482edbff8dSTomer Tayar default: 21492edbff8dSTomer Tayar return "UNKNOWN_RESOURCE"; 21502edbff8dSTomer Tayar } 21512edbff8dSTomer Tayar } 21522edbff8dSTomer Tayar 21539c8517c4STomer Tayar static int 21549c8517c4STomer Tayar __qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, 21559c8517c4STomer Tayar struct qed_ptt *p_ptt, 21569c8517c4STomer Tayar enum qed_resources res_id, 21579c8517c4STomer Tayar u32 resc_max_val, u32 *p_mcp_resp) 21589c8517c4STomer Tayar { 21599c8517c4STomer Tayar int rc; 21609c8517c4STomer Tayar 21619c8517c4STomer Tayar rc = qed_mcp_set_resc_max_val(p_hwfn, p_ptt, res_id, 21629c8517c4STomer Tayar resc_max_val, p_mcp_resp); 21639c8517c4STomer Tayar if (rc) { 21649c8517c4STomer Tayar DP_NOTICE(p_hwfn, 21659c8517c4STomer Tayar "MFW response failure for a max value setting of resource %d [%s]\n", 21669c8517c4STomer Tayar res_id, qed_hw_get_resc_name(res_id)); 21679c8517c4STomer Tayar return rc; 21689c8517c4STomer Tayar } 21699c8517c4STomer Tayar 21709c8517c4STomer Tayar if (*p_mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) 21719c8517c4STomer Tayar DP_INFO(p_hwfn, 21729c8517c4STomer Tayar "Failed to set the max value of resource %d [%s]. mcp_resp = 0x%08x.\n", 21739c8517c4STomer Tayar res_id, qed_hw_get_resc_name(res_id), *p_mcp_resp); 21749c8517c4STomer Tayar 21759c8517c4STomer Tayar return 0; 21769c8517c4STomer Tayar } 21779c8517c4STomer Tayar 21789c8517c4STomer Tayar static int 21799c8517c4STomer Tayar qed_hw_set_soft_resc_size(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 21809c8517c4STomer Tayar { 21819c8517c4STomer Tayar bool b_ah = QED_IS_AH(p_hwfn->cdev); 21829c8517c4STomer Tayar u32 resc_max_val, mcp_resp; 21839c8517c4STomer Tayar u8 res_id; 21849c8517c4STomer Tayar int rc; 21859c8517c4STomer Tayar 21869c8517c4STomer Tayar for (res_id = 0; res_id < QED_MAX_RESC; res_id++) { 21879c8517c4STomer Tayar switch (res_id) { 21889c8517c4STomer Tayar case QED_LL2_QUEUE: 21899c8517c4STomer Tayar resc_max_val = MAX_NUM_LL2_RX_QUEUES; 21909c8517c4STomer Tayar break; 21919c8517c4STomer Tayar case QED_RDMA_CNQ_RAM: 21929c8517c4STomer Tayar /* No need for a case for QED_CMDQS_CQS since 21939c8517c4STomer Tayar * CNQ/CMDQS are the same resource. 21949c8517c4STomer Tayar */ 21959c8517c4STomer Tayar resc_max_val = NUM_OF_CMDQS_CQS; 21969c8517c4STomer Tayar break; 21979c8517c4STomer Tayar case QED_RDMA_STATS_QUEUE: 21989c8517c4STomer Tayar resc_max_val = b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 21999c8517c4STomer Tayar : RDMA_NUM_STATISTIC_COUNTERS_BB; 22009c8517c4STomer Tayar break; 22019c8517c4STomer Tayar case QED_BDQ: 22029c8517c4STomer Tayar resc_max_val = BDQ_NUM_RESOURCES; 22039c8517c4STomer Tayar break; 22049c8517c4STomer Tayar default: 22059c8517c4STomer Tayar continue; 22069c8517c4STomer Tayar } 22079c8517c4STomer Tayar 22089c8517c4STomer Tayar rc = __qed_hw_set_soft_resc_size(p_hwfn, p_ptt, res_id, 22099c8517c4STomer Tayar resc_max_val, &mcp_resp); 22109c8517c4STomer Tayar if (rc) 22119c8517c4STomer Tayar return rc; 22129c8517c4STomer Tayar 22139c8517c4STomer Tayar /* There's no point to continue to the next resource if the 22149c8517c4STomer Tayar * command is not supported by the MFW. 22159c8517c4STomer Tayar * We do continue if the command is supported but the resource 22169c8517c4STomer Tayar * is unknown to the MFW. Such a resource will be later 22179c8517c4STomer Tayar * configured with the default allocation values. 22189c8517c4STomer Tayar */ 22199c8517c4STomer Tayar if (mcp_resp == FW_MSG_CODE_UNSUPPORTED) 22209c8517c4STomer Tayar return -EINVAL; 22219c8517c4STomer Tayar } 22229c8517c4STomer Tayar 22239c8517c4STomer Tayar return 0; 22249c8517c4STomer Tayar } 22259c8517c4STomer Tayar 22269c8517c4STomer Tayar static 22279c8517c4STomer Tayar int qed_hw_get_dflt_resc(struct qed_hwfn *p_hwfn, 22289c8517c4STomer Tayar enum qed_resources res_id, 22299c8517c4STomer Tayar u32 *p_resc_num, u32 *p_resc_start) 22309c8517c4STomer Tayar { 22319c8517c4STomer Tayar u8 num_funcs = p_hwfn->num_funcs_on_engine; 22329c8517c4STomer Tayar bool b_ah = QED_IS_AH(p_hwfn->cdev); 22339c8517c4STomer Tayar 22349c8517c4STomer Tayar switch (res_id) { 22359c8517c4STomer Tayar case QED_L2_QUEUE: 22369c8517c4STomer Tayar *p_resc_num = (b_ah ? MAX_NUM_L2_QUEUES_K2 : 22379c8517c4STomer Tayar MAX_NUM_L2_QUEUES_BB) / num_funcs; 22389c8517c4STomer Tayar break; 22399c8517c4STomer Tayar case QED_VPORT: 22409c8517c4STomer Tayar *p_resc_num = (b_ah ? MAX_NUM_VPORTS_K2 : 22419c8517c4STomer Tayar MAX_NUM_VPORTS_BB) / num_funcs; 22429c8517c4STomer Tayar break; 22439c8517c4STomer Tayar case QED_RSS_ENG: 22449c8517c4STomer Tayar *p_resc_num = (b_ah ? ETH_RSS_ENGINE_NUM_K2 : 22459c8517c4STomer Tayar ETH_RSS_ENGINE_NUM_BB) / num_funcs; 22469c8517c4STomer Tayar break; 22479c8517c4STomer Tayar case QED_PQ: 22489c8517c4STomer Tayar *p_resc_num = (b_ah ? MAX_QM_TX_QUEUES_K2 : 22499c8517c4STomer Tayar MAX_QM_TX_QUEUES_BB) / num_funcs; 22509c8517c4STomer Tayar *p_resc_num &= ~0x7; /* The granularity of the PQs is 8 */ 22519c8517c4STomer Tayar break; 22529c8517c4STomer Tayar case QED_RL: 22539c8517c4STomer Tayar *p_resc_num = MAX_QM_GLOBAL_RLS / num_funcs; 22549c8517c4STomer Tayar break; 22559c8517c4STomer Tayar case QED_MAC: 22569c8517c4STomer Tayar case QED_VLAN: 22579c8517c4STomer Tayar /* Each VFC resource can accommodate both a MAC and a VLAN */ 22589c8517c4STomer Tayar *p_resc_num = ETH_NUM_MAC_FILTERS / num_funcs; 22599c8517c4STomer Tayar break; 22609c8517c4STomer Tayar case QED_ILT: 22619c8517c4STomer Tayar *p_resc_num = (b_ah ? PXP_NUM_ILT_RECORDS_K2 : 22629c8517c4STomer Tayar PXP_NUM_ILT_RECORDS_BB) / num_funcs; 22639c8517c4STomer Tayar break; 22649c8517c4STomer Tayar case QED_LL2_QUEUE: 22659c8517c4STomer Tayar *p_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs; 22669c8517c4STomer Tayar break; 22679c8517c4STomer Tayar case QED_RDMA_CNQ_RAM: 22689c8517c4STomer Tayar case QED_CMDQS_CQS: 22699c8517c4STomer Tayar /* CNQ/CMDQS are the same resource */ 22709c8517c4STomer Tayar *p_resc_num = NUM_OF_CMDQS_CQS / num_funcs; 22719c8517c4STomer Tayar break; 22729c8517c4STomer Tayar case QED_RDMA_STATS_QUEUE: 22739c8517c4STomer Tayar *p_resc_num = (b_ah ? RDMA_NUM_STATISTIC_COUNTERS_K2 : 22749c8517c4STomer Tayar RDMA_NUM_STATISTIC_COUNTERS_BB) / num_funcs; 22759c8517c4STomer Tayar break; 22769c8517c4STomer Tayar case QED_BDQ: 22779c8517c4STomer Tayar if (p_hwfn->hw_info.personality != QED_PCI_ISCSI && 22789c8517c4STomer Tayar p_hwfn->hw_info.personality != QED_PCI_FCOE) 22799c8517c4STomer Tayar *p_resc_num = 0; 22809c8517c4STomer Tayar else 22819c8517c4STomer Tayar *p_resc_num = 1; 22829c8517c4STomer Tayar break; 22839c8517c4STomer Tayar case QED_SB: 2284ebbdcc66SMintz, Yuval /* Since we want its value to reflect whether MFW supports 2285ebbdcc66SMintz, Yuval * the new scheme, have a default of 0. 2286ebbdcc66SMintz, Yuval */ 2287ebbdcc66SMintz, Yuval *p_resc_num = 0; 22889c8517c4STomer Tayar break; 22899c8517c4STomer Tayar default: 22909c8517c4STomer Tayar return -EINVAL; 22919c8517c4STomer Tayar } 22929c8517c4STomer Tayar 22939c8517c4STomer Tayar switch (res_id) { 22949c8517c4STomer Tayar case QED_BDQ: 22959c8517c4STomer Tayar if (!*p_resc_num) 22969c8517c4STomer Tayar *p_resc_start = 0; 229778cea9ffSTomer Tayar else if (p_hwfn->cdev->num_ports_in_engine == 4) 22989c8517c4STomer Tayar *p_resc_start = p_hwfn->port_id; 22999c8517c4STomer Tayar else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) 23009c8517c4STomer Tayar *p_resc_start = p_hwfn->port_id; 23019c8517c4STomer Tayar else if (p_hwfn->hw_info.personality == QED_PCI_FCOE) 23029c8517c4STomer Tayar *p_resc_start = p_hwfn->port_id + 2; 23039c8517c4STomer Tayar break; 23049c8517c4STomer Tayar default: 23059c8517c4STomer Tayar *p_resc_start = *p_resc_num * p_hwfn->enabled_func_idx; 23069c8517c4STomer Tayar break; 23079c8517c4STomer Tayar } 23089c8517c4STomer Tayar 23099c8517c4STomer Tayar return 0; 23109c8517c4STomer Tayar } 23119c8517c4STomer Tayar 23129c8517c4STomer Tayar static int __qed_hw_set_resc_info(struct qed_hwfn *p_hwfn, 23132edbff8dSTomer Tayar enum qed_resources res_id) 23142edbff8dSTomer Tayar { 23159c8517c4STomer Tayar u32 dflt_resc_num = 0, dflt_resc_start = 0; 23169c8517c4STomer Tayar u32 mcp_resp, *p_resc_num, *p_resc_start; 23172edbff8dSTomer Tayar int rc; 23182edbff8dSTomer Tayar 23192edbff8dSTomer Tayar p_resc_num = &RESC_NUM(p_hwfn, res_id); 23202edbff8dSTomer Tayar p_resc_start = &RESC_START(p_hwfn, res_id); 23212edbff8dSTomer Tayar 23229c8517c4STomer Tayar rc = qed_hw_get_dflt_resc(p_hwfn, res_id, &dflt_resc_num, 23239c8517c4STomer Tayar &dflt_resc_start); 23249c8517c4STomer Tayar if (rc) { 23252edbff8dSTomer Tayar DP_ERR(p_hwfn, 23262edbff8dSTomer Tayar "Failed to get default amount for resource %d [%s]\n", 23272edbff8dSTomer Tayar res_id, qed_hw_get_resc_name(res_id)); 23289c8517c4STomer Tayar return rc; 23292edbff8dSTomer Tayar } 23302edbff8dSTomer Tayar 23319c8517c4STomer Tayar rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, res_id, 23329c8517c4STomer Tayar &mcp_resp, p_resc_num, p_resc_start); 23332edbff8dSTomer Tayar if (rc) { 23342edbff8dSTomer Tayar DP_NOTICE(p_hwfn, 23352edbff8dSTomer Tayar "MFW response failure for an allocation request for resource %d [%s]\n", 23362edbff8dSTomer Tayar res_id, qed_hw_get_resc_name(res_id)); 23372edbff8dSTomer Tayar return rc; 23382edbff8dSTomer Tayar } 23392edbff8dSTomer Tayar 23402edbff8dSTomer Tayar /* Default driver values are applied in the following cases: 23412edbff8dSTomer Tayar * - The resource allocation MB command is not supported by the MFW 23422edbff8dSTomer Tayar * - There is an internal error in the MFW while processing the request 23432edbff8dSTomer Tayar * - The resource ID is unknown to the MFW 23442edbff8dSTomer Tayar */ 23459c8517c4STomer Tayar if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK) { 23469c8517c4STomer Tayar DP_INFO(p_hwfn, 23479c8517c4STomer Tayar "Failed to receive allocation info for resource %d [%s]. mcp_resp = 0x%x. Applying default values [%d,%d].\n", 23482edbff8dSTomer Tayar res_id, 23492edbff8dSTomer Tayar qed_hw_get_resc_name(res_id), 23502edbff8dSTomer Tayar mcp_resp, dflt_resc_num, dflt_resc_start); 23512edbff8dSTomer Tayar *p_resc_num = dflt_resc_num; 23522edbff8dSTomer Tayar *p_resc_start = dflt_resc_start; 23532edbff8dSTomer Tayar goto out; 23542edbff8dSTomer Tayar } 23552edbff8dSTomer Tayar 23562edbff8dSTomer Tayar out: 23572edbff8dSTomer Tayar /* PQs have to divide by 8 [that's the HW granularity]. 23582edbff8dSTomer Tayar * Reduce number so it would fit. 23592edbff8dSTomer Tayar */ 23602edbff8dSTomer Tayar if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) { 23612edbff8dSTomer Tayar DP_INFO(p_hwfn, 23622edbff8dSTomer Tayar "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n", 23632edbff8dSTomer Tayar *p_resc_num, 23642edbff8dSTomer Tayar (*p_resc_num) & ~0x7, 23652edbff8dSTomer Tayar *p_resc_start, (*p_resc_start) & ~0x7); 23662edbff8dSTomer Tayar *p_resc_num &= ~0x7; 23672edbff8dSTomer Tayar *p_resc_start &= ~0x7; 23682edbff8dSTomer Tayar } 23692edbff8dSTomer Tayar 23702edbff8dSTomer Tayar return 0; 23712edbff8dSTomer Tayar } 23722edbff8dSTomer Tayar 23739c8517c4STomer Tayar static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn) 2374fe56b9e6SYuval Mintz { 23759c8517c4STomer Tayar int rc; 23769c8517c4STomer Tayar u8 res_id; 23779c8517c4STomer Tayar 23789c8517c4STomer Tayar for (res_id = 0; res_id < QED_MAX_RESC; res_id++) { 23799c8517c4STomer Tayar rc = __qed_hw_set_resc_info(p_hwfn, res_id); 23809c8517c4STomer Tayar if (rc) 23819c8517c4STomer Tayar return rc; 23829c8517c4STomer Tayar } 23839c8517c4STomer Tayar 23849c8517c4STomer Tayar return 0; 23859c8517c4STomer Tayar } 23869c8517c4STomer Tayar 23879c8517c4STomer Tayar static int qed_hw_get_resc(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 23889c8517c4STomer Tayar { 23899c8517c4STomer Tayar struct qed_resc_unlock_params resc_unlock_params; 23909c8517c4STomer Tayar struct qed_resc_lock_params resc_lock_params; 23919c79ddaaSMintz, Yuval bool b_ah = QED_IS_AH(p_hwfn->cdev); 23922edbff8dSTomer Tayar u8 res_id; 23932edbff8dSTomer Tayar int rc; 2394fe56b9e6SYuval Mintz 23959c8517c4STomer Tayar /* Setting the max values of the soft resources and the following 23969c8517c4STomer Tayar * resources allocation queries should be atomic. Since several PFs can 23979c8517c4STomer Tayar * run in parallel - a resource lock is needed. 23989c8517c4STomer Tayar * If either the resource lock or resource set value commands are not 23999c8517c4STomer Tayar * supported - skip the the max values setting, release the lock if 24009c8517c4STomer Tayar * needed, and proceed to the queries. Other failures, including a 24019c8517c4STomer Tayar * failure to acquire the lock, will cause this function to fail. 24029c8517c4STomer Tayar */ 2403f470f22cSsudarsana.kalluru@cavium.com qed_mcp_resc_lock_default_init(&resc_lock_params, &resc_unlock_params, 2404f470f22cSsudarsana.kalluru@cavium.com QED_RESC_LOCK_RESC_ALLOC, false); 24059c8517c4STomer Tayar 24069c8517c4STomer Tayar rc = qed_mcp_resc_lock(p_hwfn, p_ptt, &resc_lock_params); 24079c8517c4STomer Tayar if (rc && rc != -EINVAL) { 24082edbff8dSTomer Tayar return rc; 24099c8517c4STomer Tayar } else if (rc == -EINVAL) { 24109c8517c4STomer Tayar DP_INFO(p_hwfn, 24119c8517c4STomer Tayar "Skip the max values setting of the soft resources since the resource lock is not supported by the MFW\n"); 24129c8517c4STomer Tayar } else if (!rc && !resc_lock_params.b_granted) { 24139c8517c4STomer Tayar DP_NOTICE(p_hwfn, 24149c8517c4STomer Tayar "Failed to acquire the resource lock for the resource allocation commands\n"); 24159c8517c4STomer Tayar return -EBUSY; 24169c8517c4STomer Tayar } else { 24179c8517c4STomer Tayar rc = qed_hw_set_soft_resc_size(p_hwfn, p_ptt); 24189c8517c4STomer Tayar if (rc && rc != -EINVAL) { 24199c8517c4STomer Tayar DP_NOTICE(p_hwfn, 24209c8517c4STomer Tayar "Failed to set the max values of the soft resources\n"); 24219c8517c4STomer Tayar goto unlock_and_exit; 24229c8517c4STomer Tayar } else if (rc == -EINVAL) { 24239c8517c4STomer Tayar DP_INFO(p_hwfn, 24249c8517c4STomer Tayar "Skip the max values setting of the soft resources since it is not supported by the MFW\n"); 24259c8517c4STomer Tayar rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, 24269c8517c4STomer Tayar &resc_unlock_params); 24279c8517c4STomer Tayar if (rc) 24289c8517c4STomer Tayar DP_INFO(p_hwfn, 24299c8517c4STomer Tayar "Failed to release the resource lock for the resource allocation commands\n"); 24309c8517c4STomer Tayar } 24319c8517c4STomer Tayar } 24329c8517c4STomer Tayar 24339c8517c4STomer Tayar rc = qed_hw_set_resc_info(p_hwfn); 24349c8517c4STomer Tayar if (rc) 24359c8517c4STomer Tayar goto unlock_and_exit; 24369c8517c4STomer Tayar 24379c8517c4STomer Tayar if (resc_lock_params.b_granted && !resc_unlock_params.b_released) { 24389c8517c4STomer Tayar rc = qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params); 24399c8517c4STomer Tayar if (rc) 24409c8517c4STomer Tayar DP_INFO(p_hwfn, 24419c8517c4STomer Tayar "Failed to release the resource lock for the resource allocation commands\n"); 24422edbff8dSTomer Tayar } 2443dbb799c3SYuval Mintz 2444dbb799c3SYuval Mintz /* Sanity for ILT */ 24459c79ddaaSMintz, Yuval if ((b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_K2)) || 24469c79ddaaSMintz, Yuval (!b_ah && (RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB))) { 2447dbb799c3SYuval Mintz DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n", 2448dbb799c3SYuval Mintz RESC_START(p_hwfn, QED_ILT), 2449dbb799c3SYuval Mintz RESC_END(p_hwfn, QED_ILT) - 1); 2450dbb799c3SYuval Mintz return -EINVAL; 2451dbb799c3SYuval Mintz } 2452fe56b9e6SYuval Mintz 2453ebbdcc66SMintz, Yuval /* This will also learn the number of SBs from MFW */ 2454ebbdcc66SMintz, Yuval if (qed_int_igu_reset_cam(p_hwfn, p_ptt)) 2455ebbdcc66SMintz, Yuval return -EINVAL; 2456ebbdcc66SMintz, Yuval 245725c089d7SYuval Mintz qed_hw_set_feat(p_hwfn); 245825c089d7SYuval Mintz 24592edbff8dSTomer Tayar for (res_id = 0; res_id < QED_MAX_RESC; res_id++) 24602edbff8dSTomer Tayar DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n", 24612edbff8dSTomer Tayar qed_hw_get_resc_name(res_id), 24622edbff8dSTomer Tayar RESC_NUM(p_hwfn, res_id), 24632edbff8dSTomer Tayar RESC_START(p_hwfn, res_id)); 2464dbb799c3SYuval Mintz 2465dbb799c3SYuval Mintz return 0; 24669c8517c4STomer Tayar 24679c8517c4STomer Tayar unlock_and_exit: 24689c8517c4STomer Tayar if (resc_lock_params.b_granted && !resc_unlock_params.b_released) 24699c8517c4STomer Tayar qed_mcp_resc_unlock(p_hwfn, p_ptt, &resc_unlock_params); 24709c8517c4STomer Tayar return rc; 2471fe56b9e6SYuval Mintz } 2472fe56b9e6SYuval Mintz 24731a635e48SYuval Mintz static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2474fe56b9e6SYuval Mintz { 2475fc48b7a6SYuval Mintz u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities; 24761e128c81SArun Easi u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg; 2477645874e5SSudarsana Reddy Kalluru struct qed_mcp_link_capabilities *p_caps; 2478cc875c2eSYuval Mintz struct qed_mcp_link_params *link; 2479fe56b9e6SYuval Mintz 2480fe56b9e6SYuval Mintz /* Read global nvm_cfg address */ 2481fe56b9e6SYuval Mintz nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 2482fe56b9e6SYuval Mintz 2483fe56b9e6SYuval Mintz /* Verify MCP has initialized it */ 2484fe56b9e6SYuval Mintz if (!nvm_cfg_addr) { 2485fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 2486fe56b9e6SYuval Mintz return -EINVAL; 2487fe56b9e6SYuval Mintz } 2488fe56b9e6SYuval Mintz 2489fe56b9e6SYuval Mintz /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */ 2490fe56b9e6SYuval Mintz nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 2491fe56b9e6SYuval Mintz 2492cc875c2eSYuval Mintz addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2493cc875c2eSYuval Mintz offsetof(struct nvm_cfg1, glob) + 2494cc875c2eSYuval Mintz offsetof(struct nvm_cfg1_glob, core_cfg); 2495cc875c2eSYuval Mintz 2496cc875c2eSYuval Mintz core_cfg = qed_rd(p_hwfn, p_ptt, addr); 2497cc875c2eSYuval Mintz 2498cc875c2eSYuval Mintz switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >> 2499cc875c2eSYuval Mintz NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) { 2500351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G: 2501cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G; 2502cc875c2eSYuval Mintz break; 2503351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G: 2504cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G; 2505cc875c2eSYuval Mintz break; 2506351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G: 2507cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G; 2508cc875c2eSYuval Mintz break; 2509351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F: 2510cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F; 2511cc875c2eSYuval Mintz break; 2512351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E: 2513cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E; 2514cc875c2eSYuval Mintz break; 2515351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G: 2516cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G; 2517cc875c2eSYuval Mintz break; 2518351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G: 2519cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G; 2520cc875c2eSYuval Mintz break; 2521351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G: 2522cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G; 2523cc875c2eSYuval Mintz break; 25249c79ddaaSMintz, Yuval case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X10G: 25259c79ddaaSMintz, Yuval p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X10G; 25269c79ddaaSMintz, Yuval break; 2527351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G: 2528cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G; 2529cc875c2eSYuval Mintz break; 25309c79ddaaSMintz, Yuval case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X25G: 25319c79ddaaSMintz, Yuval p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X25G; 25329c79ddaaSMintz, Yuval break; 2533cc875c2eSYuval Mintz default: 25341a635e48SYuval Mintz DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg); 2535cc875c2eSYuval Mintz break; 2536cc875c2eSYuval Mintz } 2537cc875c2eSYuval Mintz 2538cc875c2eSYuval Mintz /* Read default link configuration */ 2539cc875c2eSYuval Mintz link = &p_hwfn->mcp_info->link_input; 2540645874e5SSudarsana Reddy Kalluru p_caps = &p_hwfn->mcp_info->link_capabilities; 2541cc875c2eSYuval Mintz port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2542cc875c2eSYuval Mintz offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 2543cc875c2eSYuval Mintz link_temp = qed_rd(p_hwfn, p_ptt, 2544cc875c2eSYuval Mintz port_cfg_addr + 2545cc875c2eSYuval Mintz offsetof(struct nvm_cfg1_port, speed_cap_mask)); 254683aeb933SYuval Mintz link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK; 254783aeb933SYuval Mintz link->speed.advertised_speeds = link_temp; 2548cc875c2eSYuval Mintz 254983aeb933SYuval Mintz link_temp = link->speed.advertised_speeds; 255083aeb933SYuval Mintz p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp; 2551cc875c2eSYuval Mintz 2552cc875c2eSYuval Mintz link_temp = qed_rd(p_hwfn, p_ptt, 2553cc875c2eSYuval Mintz port_cfg_addr + 2554cc875c2eSYuval Mintz offsetof(struct nvm_cfg1_port, link_settings)); 2555cc875c2eSYuval Mintz switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >> 2556cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) { 2557cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG: 2558cc875c2eSYuval Mintz link->speed.autoneg = true; 2559cc875c2eSYuval Mintz break; 2560cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_1G: 2561cc875c2eSYuval Mintz link->speed.forced_speed = 1000; 2562cc875c2eSYuval Mintz break; 2563cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_10G: 2564cc875c2eSYuval Mintz link->speed.forced_speed = 10000; 2565cc875c2eSYuval Mintz break; 2566cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_25G: 2567cc875c2eSYuval Mintz link->speed.forced_speed = 25000; 2568cc875c2eSYuval Mintz break; 2569cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_40G: 2570cc875c2eSYuval Mintz link->speed.forced_speed = 40000; 2571cc875c2eSYuval Mintz break; 2572cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_50G: 2573cc875c2eSYuval Mintz link->speed.forced_speed = 50000; 2574cc875c2eSYuval Mintz break; 2575351a4dedSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G: 2576cc875c2eSYuval Mintz link->speed.forced_speed = 100000; 2577cc875c2eSYuval Mintz break; 2578cc875c2eSYuval Mintz default: 25791a635e48SYuval Mintz DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp); 2580cc875c2eSYuval Mintz } 2581cc875c2eSYuval Mintz 258234f9199cSsudarsana.kalluru@cavium.com p_hwfn->mcp_info->link_capabilities.default_speed_autoneg = 258334f9199cSsudarsana.kalluru@cavium.com link->speed.autoneg; 258434f9199cSsudarsana.kalluru@cavium.com 2585cc875c2eSYuval Mintz link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK; 2586cc875c2eSYuval Mintz link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET; 2587cc875c2eSYuval Mintz link->pause.autoneg = !!(link_temp & 2588cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG); 2589cc875c2eSYuval Mintz link->pause.forced_rx = !!(link_temp & 2590cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX); 2591cc875c2eSYuval Mintz link->pause.forced_tx = !!(link_temp & 2592cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX); 2593cc875c2eSYuval Mintz link->loopback_mode = 0; 2594cc875c2eSYuval Mintz 2595645874e5SSudarsana Reddy Kalluru if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) { 2596645874e5SSudarsana Reddy Kalluru link_temp = qed_rd(p_hwfn, p_ptt, port_cfg_addr + 2597645874e5SSudarsana Reddy Kalluru offsetof(struct nvm_cfg1_port, ext_phy)); 2598645874e5SSudarsana Reddy Kalluru link_temp &= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_MASK; 2599645874e5SSudarsana Reddy Kalluru link_temp >>= NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_OFFSET; 2600645874e5SSudarsana Reddy Kalluru p_caps->default_eee = QED_MCP_EEE_ENABLED; 2601645874e5SSudarsana Reddy Kalluru link->eee.enable = true; 2602645874e5SSudarsana Reddy Kalluru switch (link_temp) { 2603645874e5SSudarsana Reddy Kalluru case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_DISABLED: 2604645874e5SSudarsana Reddy Kalluru p_caps->default_eee = QED_MCP_EEE_DISABLED; 2605645874e5SSudarsana Reddy Kalluru link->eee.enable = false; 2606645874e5SSudarsana Reddy Kalluru break; 2607645874e5SSudarsana Reddy Kalluru case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_BALANCED: 2608645874e5SSudarsana Reddy Kalluru p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_BALANCED_TIME; 2609645874e5SSudarsana Reddy Kalluru break; 2610645874e5SSudarsana Reddy Kalluru case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_AGGRESSIVE: 2611645874e5SSudarsana Reddy Kalluru p_caps->eee_lpi_timer = 2612645874e5SSudarsana Reddy Kalluru EEE_TX_TIMER_USEC_AGGRESSIVE_TIME; 2613645874e5SSudarsana Reddy Kalluru break; 2614645874e5SSudarsana Reddy Kalluru case NVM_CFG1_PORT_EEE_POWER_SAVING_MODE_LOW_LATENCY: 2615645874e5SSudarsana Reddy Kalluru p_caps->eee_lpi_timer = EEE_TX_TIMER_USEC_LATENCY_TIME; 2616645874e5SSudarsana Reddy Kalluru break; 2617645874e5SSudarsana Reddy Kalluru } 2618645874e5SSudarsana Reddy Kalluru 2619645874e5SSudarsana Reddy Kalluru link->eee.tx_lpi_timer = p_caps->eee_lpi_timer; 2620645874e5SSudarsana Reddy Kalluru link->eee.tx_lpi_enable = link->eee.enable; 2621645874e5SSudarsana Reddy Kalluru link->eee.adv_caps = QED_EEE_1G_ADV | QED_EEE_10G_ADV; 2622645874e5SSudarsana Reddy Kalluru } else { 2623645874e5SSudarsana Reddy Kalluru p_caps->default_eee = QED_MCP_EEE_UNSUPPORTED; 2624645874e5SSudarsana Reddy Kalluru } 2625645874e5SSudarsana Reddy Kalluru 2626645874e5SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, 2627645874e5SSudarsana Reddy Kalluru NETIF_MSG_LINK, 2628645874e5SSudarsana Reddy Kalluru "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x EEE: %02x [%08x usec]\n", 2629645874e5SSudarsana Reddy Kalluru link->speed.forced_speed, 2630645874e5SSudarsana Reddy Kalluru link->speed.advertised_speeds, 2631645874e5SSudarsana Reddy Kalluru link->speed.autoneg, 2632645874e5SSudarsana Reddy Kalluru link->pause.autoneg, 2633645874e5SSudarsana Reddy Kalluru p_caps->default_eee, p_caps->eee_lpi_timer); 2634cc875c2eSYuval Mintz 2635fe56b9e6SYuval Mintz /* Read Multi-function information from shmem */ 2636fe56b9e6SYuval Mintz addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2637fe56b9e6SYuval Mintz offsetof(struct nvm_cfg1, glob) + 2638fe56b9e6SYuval Mintz offsetof(struct nvm_cfg1_glob, generic_cont0); 2639fe56b9e6SYuval Mintz 2640fe56b9e6SYuval Mintz generic_cont0 = qed_rd(p_hwfn, p_ptt, addr); 2641fe56b9e6SYuval Mintz 2642fe56b9e6SYuval Mintz mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >> 2643fe56b9e6SYuval Mintz NVM_CFG1_GLOB_MF_MODE_OFFSET; 2644fe56b9e6SYuval Mintz 2645fe56b9e6SYuval Mintz switch (mf_mode) { 2646fe56b9e6SYuval Mintz case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED: 2647fc48b7a6SYuval Mintz p_hwfn->cdev->mf_mode = QED_MF_OVLAN; 2648fe56b9e6SYuval Mintz break; 2649fe56b9e6SYuval Mintz case NVM_CFG1_GLOB_MF_MODE_NPAR1_0: 2650fc48b7a6SYuval Mintz p_hwfn->cdev->mf_mode = QED_MF_NPAR; 2651fe56b9e6SYuval Mintz break; 2652fc48b7a6SYuval Mintz case NVM_CFG1_GLOB_MF_MODE_DEFAULT: 2653fc48b7a6SYuval Mintz p_hwfn->cdev->mf_mode = QED_MF_DEFAULT; 2654fe56b9e6SYuval Mintz break; 2655fe56b9e6SYuval Mintz } 2656fe56b9e6SYuval Mintz DP_INFO(p_hwfn, "Multi function mode is %08x\n", 2657fe56b9e6SYuval Mintz p_hwfn->cdev->mf_mode); 2658fe56b9e6SYuval Mintz 2659fc48b7a6SYuval Mintz /* Read Multi-function information from shmem */ 2660fc48b7a6SYuval Mintz addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 2661fc48b7a6SYuval Mintz offsetof(struct nvm_cfg1, glob) + 2662fc48b7a6SYuval Mintz offsetof(struct nvm_cfg1_glob, device_capabilities); 2663fc48b7a6SYuval Mintz 2664fc48b7a6SYuval Mintz device_capabilities = qed_rd(p_hwfn, p_ptt, addr); 2665fc48b7a6SYuval Mintz if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET) 2666fc48b7a6SYuval Mintz __set_bit(QED_DEV_CAP_ETH, 2667fc48b7a6SYuval Mintz &p_hwfn->hw_info.device_capabilities); 26681e128c81SArun Easi if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_FCOE) 26691e128c81SArun Easi __set_bit(QED_DEV_CAP_FCOE, 26701e128c81SArun Easi &p_hwfn->hw_info.device_capabilities); 2671c5ac9319SYuval Mintz if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI) 2672c5ac9319SYuval Mintz __set_bit(QED_DEV_CAP_ISCSI, 2673c5ac9319SYuval Mintz &p_hwfn->hw_info.device_capabilities); 2674c5ac9319SYuval Mintz if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE) 2675c5ac9319SYuval Mintz __set_bit(QED_DEV_CAP_ROCE, 2676c5ac9319SYuval Mintz &p_hwfn->hw_info.device_capabilities); 2677fc48b7a6SYuval Mintz 2678fe56b9e6SYuval Mintz return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt); 2679fe56b9e6SYuval Mintz } 2680fe56b9e6SYuval Mintz 26811408cc1fSYuval Mintz static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 26821408cc1fSYuval Mintz { 2683dbb799c3SYuval Mintz u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id; 2684dbb799c3SYuval Mintz u32 reg_function_hide, tmp, eng_mask, low_pfs_mask; 26859c79ddaaSMintz, Yuval struct qed_dev *cdev = p_hwfn->cdev; 26861408cc1fSYuval Mintz 26879c79ddaaSMintz, Yuval num_funcs = QED_IS_AH(cdev) ? MAX_NUM_PFS_K2 : MAX_NUM_PFS_BB; 26881408cc1fSYuval Mintz 26891408cc1fSYuval Mintz /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values 26901408cc1fSYuval Mintz * in the other bits are selected. 26911408cc1fSYuval Mintz * Bits 1-15 are for functions 1-15, respectively, and their value is 26921408cc1fSYuval Mintz * '0' only for enabled functions (function 0 always exists and 26931408cc1fSYuval Mintz * enabled). 26941408cc1fSYuval Mintz * In case of CMT, only the "even" functions are enabled, and thus the 26951408cc1fSYuval Mintz * number of functions for both hwfns is learnt from the same bits. 26961408cc1fSYuval Mintz */ 26971408cc1fSYuval Mintz reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE); 26981408cc1fSYuval Mintz 26991408cc1fSYuval Mintz if (reg_function_hide & 0x1) { 27009c79ddaaSMintz, Yuval if (QED_IS_BB(cdev)) { 27019c79ddaaSMintz, Yuval if (QED_PATH_ID(p_hwfn) && cdev->num_hwfns == 1) { 27021408cc1fSYuval Mintz num_funcs = 0; 27031408cc1fSYuval Mintz eng_mask = 0xaaaa; 27041408cc1fSYuval Mintz } else { 27051408cc1fSYuval Mintz num_funcs = 1; 27061408cc1fSYuval Mintz eng_mask = 0x5554; 27071408cc1fSYuval Mintz } 27089c79ddaaSMintz, Yuval } else { 27099c79ddaaSMintz, Yuval num_funcs = 1; 27109c79ddaaSMintz, Yuval eng_mask = 0xfffe; 27119c79ddaaSMintz, Yuval } 27121408cc1fSYuval Mintz 27131408cc1fSYuval Mintz /* Get the number of the enabled functions on the engine */ 27141408cc1fSYuval Mintz tmp = (reg_function_hide ^ 0xffffffff) & eng_mask; 27151408cc1fSYuval Mintz while (tmp) { 27161408cc1fSYuval Mintz if (tmp & 0x1) 27171408cc1fSYuval Mintz num_funcs++; 27181408cc1fSYuval Mintz tmp >>= 0x1; 27191408cc1fSYuval Mintz } 2720dbb799c3SYuval Mintz 2721dbb799c3SYuval Mintz /* Get the PF index within the enabled functions */ 2722dbb799c3SYuval Mintz low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1; 2723dbb799c3SYuval Mintz tmp = reg_function_hide & eng_mask & low_pfs_mask; 2724dbb799c3SYuval Mintz while (tmp) { 2725dbb799c3SYuval Mintz if (tmp & 0x1) 2726dbb799c3SYuval Mintz enabled_func_idx--; 2727dbb799c3SYuval Mintz tmp >>= 0x1; 2728dbb799c3SYuval Mintz } 27291408cc1fSYuval Mintz } 27301408cc1fSYuval Mintz 27311408cc1fSYuval Mintz p_hwfn->num_funcs_on_engine = num_funcs; 2732dbb799c3SYuval Mintz p_hwfn->enabled_func_idx = enabled_func_idx; 27331408cc1fSYuval Mintz 27341408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, 27351408cc1fSYuval Mintz NETIF_MSG_PROBE, 2736525ef5c0SYuval Mintz "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n", 27371408cc1fSYuval Mintz p_hwfn->rel_pf_id, 27381408cc1fSYuval Mintz p_hwfn->abs_pf_id, 2739525ef5c0SYuval Mintz p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine); 27401408cc1fSYuval Mintz } 27411408cc1fSYuval Mintz 27429c79ddaaSMintz, Yuval static void qed_hw_info_port_num_bb(struct qed_hwfn *p_hwfn, 27439c79ddaaSMintz, Yuval struct qed_ptt *p_ptt) 2744fe56b9e6SYuval Mintz { 2745fe56b9e6SYuval Mintz u32 port_mode; 2746fe56b9e6SYuval Mintz 27479c79ddaaSMintz, Yuval port_mode = qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB_B0); 2748fe56b9e6SYuval Mintz 2749fe56b9e6SYuval Mintz if (port_mode < 3) { 275078cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine = 1; 2751fe56b9e6SYuval Mintz } else if (port_mode <= 5) { 275278cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine = 2; 2753fe56b9e6SYuval Mintz } else { 2754fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n", 275578cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine); 2756fe56b9e6SYuval Mintz 275778cea9ffSTomer Tayar /* Default num_ports_in_engine to something */ 275878cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine = 1; 2759fe56b9e6SYuval Mintz } 27609c79ddaaSMintz, Yuval } 27619c79ddaaSMintz, Yuval 27629c79ddaaSMintz, Yuval static void qed_hw_info_port_num_ah(struct qed_hwfn *p_hwfn, 27639c79ddaaSMintz, Yuval struct qed_ptt *p_ptt) 27649c79ddaaSMintz, Yuval { 27659c79ddaaSMintz, Yuval u32 port; 27669c79ddaaSMintz, Yuval int i; 27679c79ddaaSMintz, Yuval 276878cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine = 0; 27699c79ddaaSMintz, Yuval 27709c79ddaaSMintz, Yuval for (i = 0; i < MAX_NUM_PORTS_K2; i++) { 27719c79ddaaSMintz, Yuval port = qed_rd(p_hwfn, p_ptt, 27729c79ddaaSMintz, Yuval CNIG_REG_NIG_PORT0_CONF_K2 + (i * 4)); 27739c79ddaaSMintz, Yuval if (port & 1) 277478cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine++; 27759c79ddaaSMintz, Yuval } 27769c79ddaaSMintz, Yuval 277778cea9ffSTomer Tayar if (!p_hwfn->cdev->num_ports_in_engine) { 27789c79ddaaSMintz, Yuval DP_NOTICE(p_hwfn, "All NIG ports are inactive\n"); 27799c79ddaaSMintz, Yuval 27809c79ddaaSMintz, Yuval /* Default num_ports_in_engine to something */ 278178cea9ffSTomer Tayar p_hwfn->cdev->num_ports_in_engine = 1; 27829c79ddaaSMintz, Yuval } 27839c79ddaaSMintz, Yuval } 27849c79ddaaSMintz, Yuval 27859c79ddaaSMintz, Yuval static void qed_hw_info_port_num(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 27869c79ddaaSMintz, Yuval { 27879c79ddaaSMintz, Yuval if (QED_IS_BB(p_hwfn->cdev)) 27889c79ddaaSMintz, Yuval qed_hw_info_port_num_bb(p_hwfn, p_ptt); 27899c79ddaaSMintz, Yuval else 27909c79ddaaSMintz, Yuval qed_hw_info_port_num_ah(p_hwfn, p_ptt); 27919c79ddaaSMintz, Yuval } 27929c79ddaaSMintz, Yuval 2793645874e5SSudarsana Reddy Kalluru static void qed_get_eee_caps(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2794645874e5SSudarsana Reddy Kalluru { 2795645874e5SSudarsana Reddy Kalluru struct qed_mcp_link_capabilities *p_caps; 2796645874e5SSudarsana Reddy Kalluru u32 eee_status; 2797645874e5SSudarsana Reddy Kalluru 2798645874e5SSudarsana Reddy Kalluru p_caps = &p_hwfn->mcp_info->link_capabilities; 2799645874e5SSudarsana Reddy Kalluru if (p_caps->default_eee == QED_MCP_EEE_UNSUPPORTED) 2800645874e5SSudarsana Reddy Kalluru return; 2801645874e5SSudarsana Reddy Kalluru 2802645874e5SSudarsana Reddy Kalluru p_caps->eee_speed_caps = 0; 2803645874e5SSudarsana Reddy Kalluru eee_status = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr + 2804645874e5SSudarsana Reddy Kalluru offsetof(struct public_port, eee_status)); 2805645874e5SSudarsana Reddy Kalluru eee_status = (eee_status & EEE_SUPPORTED_SPEED_MASK) >> 2806645874e5SSudarsana Reddy Kalluru EEE_SUPPORTED_SPEED_OFFSET; 2807645874e5SSudarsana Reddy Kalluru 2808645874e5SSudarsana Reddy Kalluru if (eee_status & EEE_1G_SUPPORTED) 2809645874e5SSudarsana Reddy Kalluru p_caps->eee_speed_caps |= QED_EEE_1G_ADV; 2810645874e5SSudarsana Reddy Kalluru if (eee_status & EEE_10G_ADV) 2811645874e5SSudarsana Reddy Kalluru p_caps->eee_speed_caps |= QED_EEE_10G_ADV; 2812645874e5SSudarsana Reddy Kalluru } 2813645874e5SSudarsana Reddy Kalluru 28149c79ddaaSMintz, Yuval static int 28159c79ddaaSMintz, Yuval qed_get_hw_info(struct qed_hwfn *p_hwfn, 28169c79ddaaSMintz, Yuval struct qed_ptt *p_ptt, 28179c79ddaaSMintz, Yuval enum qed_pci_personality personality) 28189c79ddaaSMintz, Yuval { 28199c79ddaaSMintz, Yuval int rc; 28209c79ddaaSMintz, Yuval 28219c79ddaaSMintz, Yuval /* Since all information is common, only first hwfns should do this */ 28229c79ddaaSMintz, Yuval if (IS_LEAD_HWFN(p_hwfn)) { 28239c79ddaaSMintz, Yuval rc = qed_iov_hw_info(p_hwfn); 28249c79ddaaSMintz, Yuval if (rc) 28259c79ddaaSMintz, Yuval return rc; 28269c79ddaaSMintz, Yuval } 28279c79ddaaSMintz, Yuval 28289c79ddaaSMintz, Yuval qed_hw_info_port_num(p_hwfn, p_ptt); 2829fe56b9e6SYuval Mintz 2830645874e5SSudarsana Reddy Kalluru qed_mcp_get_capabilities(p_hwfn, p_ptt); 2831645874e5SSudarsana Reddy Kalluru 2832fe56b9e6SYuval Mintz qed_hw_get_nvm_info(p_hwfn, p_ptt); 2833fe56b9e6SYuval Mintz 2834fe56b9e6SYuval Mintz rc = qed_int_igu_read_cam(p_hwfn, p_ptt); 2835fe56b9e6SYuval Mintz if (rc) 2836fe56b9e6SYuval Mintz return rc; 2837fe56b9e6SYuval Mintz 2838fe56b9e6SYuval Mintz if (qed_mcp_is_init(p_hwfn)) 2839fe56b9e6SYuval Mintz ether_addr_copy(p_hwfn->hw_info.hw_mac_addr, 2840fe56b9e6SYuval Mintz p_hwfn->mcp_info->func_info.mac); 2841fe56b9e6SYuval Mintz else 2842fe56b9e6SYuval Mintz eth_random_addr(p_hwfn->hw_info.hw_mac_addr); 2843fe56b9e6SYuval Mintz 2844fe56b9e6SYuval Mintz if (qed_mcp_is_init(p_hwfn)) { 2845fe56b9e6SYuval Mintz if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET) 2846fe56b9e6SYuval Mintz p_hwfn->hw_info.ovlan = 2847fe56b9e6SYuval Mintz p_hwfn->mcp_info->func_info.ovlan; 2848fe56b9e6SYuval Mintz 2849fe56b9e6SYuval Mintz qed_mcp_cmd_port_init(p_hwfn, p_ptt); 2850645874e5SSudarsana Reddy Kalluru 2851645874e5SSudarsana Reddy Kalluru qed_get_eee_caps(p_hwfn, p_ptt); 2852fe56b9e6SYuval Mintz } 2853fe56b9e6SYuval Mintz 2854fe56b9e6SYuval Mintz if (qed_mcp_is_init(p_hwfn)) { 2855fe56b9e6SYuval Mintz enum qed_pci_personality protocol; 2856fe56b9e6SYuval Mintz 2857fe56b9e6SYuval Mintz protocol = p_hwfn->mcp_info->func_info.protocol; 2858fe56b9e6SYuval Mintz p_hwfn->hw_info.personality = protocol; 2859fe56b9e6SYuval Mintz } 2860fe56b9e6SYuval Mintz 2861b5a9ee7cSAriel Elior p_hwfn->hw_info.num_hw_tc = NUM_PHYS_TCS_4PORT_K2; 2862b5a9ee7cSAriel Elior p_hwfn->hw_info.num_active_tc = 1; 2863b5a9ee7cSAriel Elior 28641408cc1fSYuval Mintz qed_get_num_funcs(p_hwfn, p_ptt); 28651408cc1fSYuval Mintz 28660fefbfbaSSudarsana Kalluru if (qed_mcp_is_init(p_hwfn)) 28670fefbfbaSSudarsana Kalluru p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu; 28680fefbfbaSSudarsana Kalluru 28699c8517c4STomer Tayar return qed_hw_get_resc(p_hwfn, p_ptt); 2870fe56b9e6SYuval Mintz } 2871fe56b9e6SYuval Mintz 287215582962SRahul Verma static int qed_get_dev_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 2873fe56b9e6SYuval Mintz { 287415582962SRahul Verma struct qed_dev *cdev = p_hwfn->cdev; 28759c79ddaaSMintz, Yuval u16 device_id_mask; 2876fe56b9e6SYuval Mintz u32 tmp; 2877fe56b9e6SYuval Mintz 2878fc48b7a6SYuval Mintz /* Read Vendor Id / Device Id */ 28791a635e48SYuval Mintz pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id); 28801a635e48SYuval Mintz pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id); 28811a635e48SYuval Mintz 28829c79ddaaSMintz, Yuval /* Determine type */ 28839c79ddaaSMintz, Yuval device_id_mask = cdev->device_id & QED_DEV_ID_MASK; 28849c79ddaaSMintz, Yuval switch (device_id_mask) { 28859c79ddaaSMintz, Yuval case QED_DEV_ID_MASK_BB: 28869c79ddaaSMintz, Yuval cdev->type = QED_DEV_TYPE_BB; 28879c79ddaaSMintz, Yuval break; 28889c79ddaaSMintz, Yuval case QED_DEV_ID_MASK_AH: 28899c79ddaaSMintz, Yuval cdev->type = QED_DEV_TYPE_AH; 28909c79ddaaSMintz, Yuval break; 28919c79ddaaSMintz, Yuval default: 28929c79ddaaSMintz, Yuval DP_NOTICE(p_hwfn, "Unknown device id 0x%x\n", cdev->device_id); 28939c79ddaaSMintz, Yuval return -EBUSY; 28949c79ddaaSMintz, Yuval } 28959c79ddaaSMintz, Yuval 289615582962SRahul Verma cdev->chip_num = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_NUM); 289715582962SRahul Verma cdev->chip_rev = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_REV); 289815582962SRahul Verma 2899fe56b9e6SYuval Mintz MASK_FIELD(CHIP_REV, cdev->chip_rev); 2900fe56b9e6SYuval Mintz 2901fe56b9e6SYuval Mintz /* Learn number of HW-functions */ 290215582962SRahul Verma tmp = qed_rd(p_hwfn, p_ptt, MISCS_REG_CMT_ENABLED_FOR_PAIR); 2903fe56b9e6SYuval Mintz 2904fc48b7a6SYuval Mintz if (tmp & (1 << p_hwfn->rel_pf_id)) { 2905fe56b9e6SYuval Mintz DP_NOTICE(cdev->hwfns, "device in CMT mode\n"); 2906fe56b9e6SYuval Mintz cdev->num_hwfns = 2; 2907fe56b9e6SYuval Mintz } else { 2908fe56b9e6SYuval Mintz cdev->num_hwfns = 1; 2909fe56b9e6SYuval Mintz } 2910fe56b9e6SYuval Mintz 291115582962SRahul Verma cdev->chip_bond_id = qed_rd(p_hwfn, p_ptt, 2912fe56b9e6SYuval Mintz MISCS_REG_CHIP_TEST_REG) >> 4; 2913fe56b9e6SYuval Mintz MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id); 291415582962SRahul Verma cdev->chip_metal = (u16)qed_rd(p_hwfn, p_ptt, MISCS_REG_CHIP_METAL); 2915fe56b9e6SYuval Mintz MASK_FIELD(CHIP_METAL, cdev->chip_metal); 2916fe56b9e6SYuval Mintz 2917fe56b9e6SYuval Mintz DP_INFO(cdev->hwfns, 29189c79ddaaSMintz, Yuval "Chip details - %s %c%d, Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n", 29199c79ddaaSMintz, Yuval QED_IS_BB(cdev) ? "BB" : "AH", 29209c79ddaaSMintz, Yuval 'A' + cdev->chip_rev, 29219c79ddaaSMintz, Yuval (int)cdev->chip_metal, 2922fe56b9e6SYuval Mintz cdev->chip_num, cdev->chip_rev, 2923fe56b9e6SYuval Mintz cdev->chip_bond_id, cdev->chip_metal); 292412e09c69SYuval Mintz 292512e09c69SYuval Mintz return 0; 2926fe56b9e6SYuval Mintz } 2927fe56b9e6SYuval Mintz 2928fe56b9e6SYuval Mintz static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn, 2929fe56b9e6SYuval Mintz void __iomem *p_regview, 2930fe56b9e6SYuval Mintz void __iomem *p_doorbells, 2931fe56b9e6SYuval Mintz enum qed_pci_personality personality) 2932fe56b9e6SYuval Mintz { 2933fe56b9e6SYuval Mintz int rc = 0; 2934fe56b9e6SYuval Mintz 2935fe56b9e6SYuval Mintz /* Split PCI bars evenly between hwfns */ 2936fe56b9e6SYuval Mintz p_hwfn->regview = p_regview; 2937fe56b9e6SYuval Mintz p_hwfn->doorbells = p_doorbells; 2938fe56b9e6SYuval Mintz 29391408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 29401408cc1fSYuval Mintz return qed_vf_hw_prepare(p_hwfn); 29411408cc1fSYuval Mintz 2942fe56b9e6SYuval Mintz /* Validate that chip access is feasible */ 2943fe56b9e6SYuval Mintz if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) { 2944fe56b9e6SYuval Mintz DP_ERR(p_hwfn, 2945fe56b9e6SYuval Mintz "Reading the ME register returns all Fs; Preventing further chip access\n"); 2946fe56b9e6SYuval Mintz return -EINVAL; 2947fe56b9e6SYuval Mintz } 2948fe56b9e6SYuval Mintz 2949fe56b9e6SYuval Mintz get_function_id(p_hwfn); 2950fe56b9e6SYuval Mintz 295112e09c69SYuval Mintz /* Allocate PTT pool */ 295212e09c69SYuval Mintz rc = qed_ptt_pool_alloc(p_hwfn); 29532591c280SJoe Perches if (rc) 2954fe56b9e6SYuval Mintz goto err0; 2955fe56b9e6SYuval Mintz 295612e09c69SYuval Mintz /* Allocate the main PTT */ 295712e09c69SYuval Mintz p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN); 295812e09c69SYuval Mintz 2959fe56b9e6SYuval Mintz /* First hwfn learns basic information, e.g., number of hwfns */ 296012e09c69SYuval Mintz if (!p_hwfn->my_id) { 296115582962SRahul Verma rc = qed_get_dev_info(p_hwfn, p_hwfn->p_main_ptt); 29621a635e48SYuval Mintz if (rc) 296312e09c69SYuval Mintz goto err1; 296412e09c69SYuval Mintz } 296512e09c69SYuval Mintz 296612e09c69SYuval Mintz qed_hw_hwfn_prepare(p_hwfn); 2967fe56b9e6SYuval Mintz 2968fe56b9e6SYuval Mintz /* Initialize MCP structure */ 2969fe56b9e6SYuval Mintz rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt); 2970fe56b9e6SYuval Mintz if (rc) { 2971fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed initializing mcp command\n"); 2972fe56b9e6SYuval Mintz goto err1; 2973fe56b9e6SYuval Mintz } 2974fe56b9e6SYuval Mintz 2975fe56b9e6SYuval Mintz /* Read the device configuration information from the HW and SHMEM */ 2976fe56b9e6SYuval Mintz rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality); 2977fe56b9e6SYuval Mintz if (rc) { 2978fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed to get HW information\n"); 2979fe56b9e6SYuval Mintz goto err2; 2980fe56b9e6SYuval Mintz } 2981fe56b9e6SYuval Mintz 298218a69e36SMintz, Yuval /* Sending a mailbox to the MFW should be done after qed_get_hw_info() 298318a69e36SMintz, Yuval * is called as it sets the ports number in an engine. 298418a69e36SMintz, Yuval */ 298518a69e36SMintz, Yuval if (IS_LEAD_HWFN(p_hwfn)) { 298618a69e36SMintz, Yuval rc = qed_mcp_initiate_pf_flr(p_hwfn, p_hwfn->p_main_ptt); 298718a69e36SMintz, Yuval if (rc) 298818a69e36SMintz, Yuval DP_NOTICE(p_hwfn, "Failed to initiate PF FLR\n"); 298918a69e36SMintz, Yuval } 299018a69e36SMintz, Yuval 2991fe56b9e6SYuval Mintz /* Allocate the init RT array and initialize the init-ops engine */ 2992fe56b9e6SYuval Mintz rc = qed_init_alloc(p_hwfn); 29932591c280SJoe Perches if (rc) 2994fe56b9e6SYuval Mintz goto err2; 2995fe56b9e6SYuval Mintz 2996fe56b9e6SYuval Mintz return rc; 2997fe56b9e6SYuval Mintz err2: 299832a47e72SYuval Mintz if (IS_LEAD_HWFN(p_hwfn)) 299932a47e72SYuval Mintz qed_iov_free_hw_info(p_hwfn->cdev); 3000fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 3001fe56b9e6SYuval Mintz err1: 3002fe56b9e6SYuval Mintz qed_hw_hwfn_free(p_hwfn); 3003fe56b9e6SYuval Mintz err0: 3004fe56b9e6SYuval Mintz return rc; 3005fe56b9e6SYuval Mintz } 3006fe56b9e6SYuval Mintz 3007fe56b9e6SYuval Mintz int qed_hw_prepare(struct qed_dev *cdev, 3008fe56b9e6SYuval Mintz int personality) 3009fe56b9e6SYuval Mintz { 3010c78df14eSAriel Elior struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 3011c78df14eSAriel Elior int rc; 3012fe56b9e6SYuval Mintz 3013fe56b9e6SYuval Mintz /* Store the precompiled init data ptrs */ 30141408cc1fSYuval Mintz if (IS_PF(cdev)) 3015fe56b9e6SYuval Mintz qed_init_iro_array(cdev); 3016fe56b9e6SYuval Mintz 3017fe56b9e6SYuval Mintz /* Initialize the first hwfn - will learn number of hwfns */ 3018c78df14eSAriel Elior rc = qed_hw_prepare_single(p_hwfn, 3019c78df14eSAriel Elior cdev->regview, 3020fe56b9e6SYuval Mintz cdev->doorbells, personality); 3021fe56b9e6SYuval Mintz if (rc) 3022fe56b9e6SYuval Mintz return rc; 3023fe56b9e6SYuval Mintz 3024c78df14eSAriel Elior personality = p_hwfn->hw_info.personality; 3025fe56b9e6SYuval Mintz 3026fe56b9e6SYuval Mintz /* Initialize the rest of the hwfns */ 3027c78df14eSAriel Elior if (cdev->num_hwfns > 1) { 3028fe56b9e6SYuval Mintz void __iomem *p_regview, *p_doorbell; 3029c78df14eSAriel Elior u8 __iomem *addr; 3030fe56b9e6SYuval Mintz 3031c78df14eSAriel Elior /* adjust bar offset for second engine */ 303215582962SRahul Verma addr = cdev->regview + 303315582962SRahul Verma qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt, 303415582962SRahul Verma BAR_ID_0) / 2; 3035c78df14eSAriel Elior p_regview = addr; 3036c78df14eSAriel Elior 303715582962SRahul Verma addr = cdev->doorbells + 303815582962SRahul Verma qed_hw_bar_size(p_hwfn, p_hwfn->p_main_ptt, 303915582962SRahul Verma BAR_ID_1) / 2; 3040c78df14eSAriel Elior p_doorbell = addr; 3041c78df14eSAriel Elior 3042c78df14eSAriel Elior /* prepare second hw function */ 3043c78df14eSAriel Elior rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview, 3044fe56b9e6SYuval Mintz p_doorbell, personality); 3045c78df14eSAriel Elior 3046c78df14eSAriel Elior /* in case of error, need to free the previously 3047c78df14eSAriel Elior * initiliazed hwfn 0. 3048c78df14eSAriel Elior */ 3049fe56b9e6SYuval Mintz if (rc) { 30501408cc1fSYuval Mintz if (IS_PF(cdev)) { 3051c78df14eSAriel Elior qed_init_free(p_hwfn); 3052c78df14eSAriel Elior qed_mcp_free(p_hwfn); 3053c78df14eSAriel Elior qed_hw_hwfn_free(p_hwfn); 3054fe56b9e6SYuval Mintz } 3055fe56b9e6SYuval Mintz } 30561408cc1fSYuval Mintz } 3057fe56b9e6SYuval Mintz 3058c78df14eSAriel Elior return rc; 3059fe56b9e6SYuval Mintz } 3060fe56b9e6SYuval Mintz 3061fe56b9e6SYuval Mintz void qed_hw_remove(struct qed_dev *cdev) 3062fe56b9e6SYuval Mintz { 30630fefbfbaSSudarsana Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 3064fe56b9e6SYuval Mintz int i; 3065fe56b9e6SYuval Mintz 30660fefbfbaSSudarsana Kalluru if (IS_PF(cdev)) 30670fefbfbaSSudarsana Kalluru qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt, 30680fefbfbaSSudarsana Kalluru QED_OV_DRIVER_STATE_NOT_LOADED); 30690fefbfbaSSudarsana Kalluru 3070fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 3071fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 3072fe56b9e6SYuval Mintz 30731408cc1fSYuval Mintz if (IS_VF(cdev)) { 30740b55e27dSYuval Mintz qed_vf_pf_release(p_hwfn); 30751408cc1fSYuval Mintz continue; 30761408cc1fSYuval Mintz } 30771408cc1fSYuval Mintz 3078fe56b9e6SYuval Mintz qed_init_free(p_hwfn); 3079fe56b9e6SYuval Mintz qed_hw_hwfn_free(p_hwfn); 3080fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 3081fe56b9e6SYuval Mintz } 308232a47e72SYuval Mintz 308332a47e72SYuval Mintz qed_iov_free_hw_info(cdev); 3084fe56b9e6SYuval Mintz } 3085fe56b9e6SYuval Mintz 3086a91eb52aSYuval Mintz static void qed_chain_free_next_ptr(struct qed_dev *cdev, 3087a91eb52aSYuval Mintz struct qed_chain *p_chain) 3088a91eb52aSYuval Mintz { 3089a91eb52aSYuval Mintz void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL; 3090a91eb52aSYuval Mintz dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0; 3091a91eb52aSYuval Mintz struct qed_chain_next *p_next; 3092a91eb52aSYuval Mintz u32 size, i; 3093a91eb52aSYuval Mintz 3094a91eb52aSYuval Mintz if (!p_virt) 3095a91eb52aSYuval Mintz return; 3096a91eb52aSYuval Mintz 3097a91eb52aSYuval Mintz size = p_chain->elem_size * p_chain->usable_per_page; 3098a91eb52aSYuval Mintz 3099a91eb52aSYuval Mintz for (i = 0; i < p_chain->page_cnt; i++) { 3100a91eb52aSYuval Mintz if (!p_virt) 3101a91eb52aSYuval Mintz break; 3102a91eb52aSYuval Mintz 3103a91eb52aSYuval Mintz p_next = (struct qed_chain_next *)((u8 *)p_virt + size); 3104a91eb52aSYuval Mintz p_virt_next = p_next->next_virt; 3105a91eb52aSYuval Mintz p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys); 3106a91eb52aSYuval Mintz 3107a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 3108a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, p_virt, p_phys); 3109a91eb52aSYuval Mintz 3110a91eb52aSYuval Mintz p_virt = p_virt_next; 3111a91eb52aSYuval Mintz p_phys = p_phys_next; 3112a91eb52aSYuval Mintz } 3113a91eb52aSYuval Mintz } 3114a91eb52aSYuval Mintz 3115a91eb52aSYuval Mintz static void qed_chain_free_single(struct qed_dev *cdev, 3116a91eb52aSYuval Mintz struct qed_chain *p_chain) 3117a91eb52aSYuval Mintz { 3118a91eb52aSYuval Mintz if (!p_chain->p_virt_addr) 3119a91eb52aSYuval Mintz return; 3120a91eb52aSYuval Mintz 3121a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 3122a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 3123a91eb52aSYuval Mintz p_chain->p_virt_addr, p_chain->p_phys_addr); 3124a91eb52aSYuval Mintz } 3125a91eb52aSYuval Mintz 3126a91eb52aSYuval Mintz static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain) 3127a91eb52aSYuval Mintz { 3128a91eb52aSYuval Mintz void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl; 3129a91eb52aSYuval Mintz u32 page_cnt = p_chain->page_cnt, i, pbl_size; 31306d937acfSMintz, Yuval u8 *p_pbl_virt = p_chain->pbl_sp.p_virt_table; 3131a91eb52aSYuval Mintz 3132a91eb52aSYuval Mintz if (!pp_virt_addr_tbl) 3133a91eb52aSYuval Mintz return; 3134a91eb52aSYuval Mintz 31356d937acfSMintz, Yuval if (!p_pbl_virt) 3136a91eb52aSYuval Mintz goto out; 3137a91eb52aSYuval Mintz 3138a91eb52aSYuval Mintz for (i = 0; i < page_cnt; i++) { 3139a91eb52aSYuval Mintz if (!pp_virt_addr_tbl[i]) 3140a91eb52aSYuval Mintz break; 3141a91eb52aSYuval Mintz 3142a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 3143a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 3144a91eb52aSYuval Mintz pp_virt_addr_tbl[i], 3145a91eb52aSYuval Mintz *(dma_addr_t *)p_pbl_virt); 3146a91eb52aSYuval Mintz 3147a91eb52aSYuval Mintz p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE; 3148a91eb52aSYuval Mintz } 3149a91eb52aSYuval Mintz 3150a91eb52aSYuval Mintz pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; 31511a4a6975SMintz, Yuval 31521a4a6975SMintz, Yuval if (!p_chain->b_external_pbl) 3153a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 3154a91eb52aSYuval Mintz pbl_size, 31556d937acfSMintz, Yuval p_chain->pbl_sp.p_virt_table, 31566d937acfSMintz, Yuval p_chain->pbl_sp.p_phys_table); 3157a91eb52aSYuval Mintz out: 3158a91eb52aSYuval Mintz vfree(p_chain->pbl.pp_virt_addr_tbl); 31591a4a6975SMintz, Yuval p_chain->pbl.pp_virt_addr_tbl = NULL; 3160a91eb52aSYuval Mintz } 3161a91eb52aSYuval Mintz 3162a91eb52aSYuval Mintz void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain) 3163a91eb52aSYuval Mintz { 3164a91eb52aSYuval Mintz switch (p_chain->mode) { 3165a91eb52aSYuval Mintz case QED_CHAIN_MODE_NEXT_PTR: 3166a91eb52aSYuval Mintz qed_chain_free_next_ptr(cdev, p_chain); 3167a91eb52aSYuval Mintz break; 3168a91eb52aSYuval Mintz case QED_CHAIN_MODE_SINGLE: 3169a91eb52aSYuval Mintz qed_chain_free_single(cdev, p_chain); 3170a91eb52aSYuval Mintz break; 3171a91eb52aSYuval Mintz case QED_CHAIN_MODE_PBL: 3172a91eb52aSYuval Mintz qed_chain_free_pbl(cdev, p_chain); 3173a91eb52aSYuval Mintz break; 3174a91eb52aSYuval Mintz } 3175a91eb52aSYuval Mintz } 3176a91eb52aSYuval Mintz 3177a91eb52aSYuval Mintz static int 3178a91eb52aSYuval Mintz qed_chain_alloc_sanity_check(struct qed_dev *cdev, 3179a91eb52aSYuval Mintz enum qed_chain_cnt_type cnt_type, 3180a91eb52aSYuval Mintz size_t elem_size, u32 page_cnt) 3181a91eb52aSYuval Mintz { 3182a91eb52aSYuval Mintz u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt; 3183a91eb52aSYuval Mintz 3184a91eb52aSYuval Mintz /* The actual chain size can be larger than the maximal possible value 3185a91eb52aSYuval Mintz * after rounding up the requested elements number to pages, and after 3186a91eb52aSYuval Mintz * taking into acount the unusuable elements (next-ptr elements). 3187a91eb52aSYuval Mintz * The size of a "u16" chain can be (U16_MAX + 1) since the chain 3188a91eb52aSYuval Mintz * size/capacity fields are of a u32 type. 3189a91eb52aSYuval Mintz */ 3190a91eb52aSYuval Mintz if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 && 31913ef310a7STomer Tayar chain_size > ((u32)U16_MAX + 1)) || 31923ef310a7STomer Tayar (cnt_type == QED_CHAIN_CNT_TYPE_U32 && chain_size > U32_MAX)) { 3193a91eb52aSYuval Mintz DP_NOTICE(cdev, 3194a91eb52aSYuval Mintz "The actual chain size (0x%llx) is larger than the maximal possible value\n", 3195a91eb52aSYuval Mintz chain_size); 3196a91eb52aSYuval Mintz return -EINVAL; 3197a91eb52aSYuval Mintz } 3198a91eb52aSYuval Mintz 3199a91eb52aSYuval Mintz return 0; 3200a91eb52aSYuval Mintz } 3201a91eb52aSYuval Mintz 3202a91eb52aSYuval Mintz static int 3203a91eb52aSYuval Mintz qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain) 3204a91eb52aSYuval Mintz { 3205a91eb52aSYuval Mintz void *p_virt = NULL, *p_virt_prev = NULL; 3206a91eb52aSYuval Mintz dma_addr_t p_phys = 0; 3207a91eb52aSYuval Mintz u32 i; 3208a91eb52aSYuval Mintz 3209a91eb52aSYuval Mintz for (i = 0; i < p_chain->page_cnt; i++) { 3210a91eb52aSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 3211a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 3212a91eb52aSYuval Mintz &p_phys, GFP_KERNEL); 32132591c280SJoe Perches if (!p_virt) 3214a91eb52aSYuval Mintz return -ENOMEM; 3215a91eb52aSYuval Mintz 3216a91eb52aSYuval Mintz if (i == 0) { 3217a91eb52aSYuval Mintz qed_chain_init_mem(p_chain, p_virt, p_phys); 3218a91eb52aSYuval Mintz qed_chain_reset(p_chain); 3219a91eb52aSYuval Mintz } else { 3220a91eb52aSYuval Mintz qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, 3221a91eb52aSYuval Mintz p_virt, p_phys); 3222a91eb52aSYuval Mintz } 3223a91eb52aSYuval Mintz 3224a91eb52aSYuval Mintz p_virt_prev = p_virt; 3225a91eb52aSYuval Mintz } 3226a91eb52aSYuval Mintz /* Last page's next element should point to the beginning of the 3227a91eb52aSYuval Mintz * chain. 3228a91eb52aSYuval Mintz */ 3229a91eb52aSYuval Mintz qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, 3230a91eb52aSYuval Mintz p_chain->p_virt_addr, 3231a91eb52aSYuval Mintz p_chain->p_phys_addr); 3232a91eb52aSYuval Mintz 3233a91eb52aSYuval Mintz return 0; 3234a91eb52aSYuval Mintz } 3235a91eb52aSYuval Mintz 3236a91eb52aSYuval Mintz static int 3237a91eb52aSYuval Mintz qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain) 3238a91eb52aSYuval Mintz { 3239a91eb52aSYuval Mintz dma_addr_t p_phys = 0; 3240a91eb52aSYuval Mintz void *p_virt = NULL; 3241a91eb52aSYuval Mintz 3242a91eb52aSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 3243a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL); 32442591c280SJoe Perches if (!p_virt) 3245a91eb52aSYuval Mintz return -ENOMEM; 3246a91eb52aSYuval Mintz 3247a91eb52aSYuval Mintz qed_chain_init_mem(p_chain, p_virt, p_phys); 3248a91eb52aSYuval Mintz qed_chain_reset(p_chain); 3249a91eb52aSYuval Mintz 3250a91eb52aSYuval Mintz return 0; 3251a91eb52aSYuval Mintz } 3252a91eb52aSYuval Mintz 32531a4a6975SMintz, Yuval static int 32541a4a6975SMintz, Yuval qed_chain_alloc_pbl(struct qed_dev *cdev, 32551a4a6975SMintz, Yuval struct qed_chain *p_chain, 32561a4a6975SMintz, Yuval struct qed_chain_ext_pbl *ext_pbl) 3257a91eb52aSYuval Mintz { 3258a91eb52aSYuval Mintz u32 page_cnt = p_chain->page_cnt, size, i; 3259a91eb52aSYuval Mintz dma_addr_t p_phys = 0, p_pbl_phys = 0; 3260a91eb52aSYuval Mintz void **pp_virt_addr_tbl = NULL; 3261a91eb52aSYuval Mintz u8 *p_pbl_virt = NULL; 3262a91eb52aSYuval Mintz void *p_virt = NULL; 3263a91eb52aSYuval Mintz 3264a91eb52aSYuval Mintz size = page_cnt * sizeof(*pp_virt_addr_tbl); 32652591c280SJoe Perches pp_virt_addr_tbl = vzalloc(size); 32662591c280SJoe Perches if (!pp_virt_addr_tbl) 3267a91eb52aSYuval Mintz return -ENOMEM; 3268a91eb52aSYuval Mintz 3269a91eb52aSYuval Mintz /* The allocation of the PBL table is done with its full size, since it 3270a91eb52aSYuval Mintz * is expected to be successive. 3271a91eb52aSYuval Mintz * qed_chain_init_pbl_mem() is called even in a case of an allocation 3272a91eb52aSYuval Mintz * failure, since pp_virt_addr_tbl was previously allocated, and it 3273a91eb52aSYuval Mintz * should be saved to allow its freeing during the error flow. 3274a91eb52aSYuval Mintz */ 3275a91eb52aSYuval Mintz size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; 32761a4a6975SMintz, Yuval 32771a4a6975SMintz, Yuval if (!ext_pbl) { 3278a91eb52aSYuval Mintz p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev, 3279a91eb52aSYuval Mintz size, &p_pbl_phys, GFP_KERNEL); 32801a4a6975SMintz, Yuval } else { 32811a4a6975SMintz, Yuval p_pbl_virt = ext_pbl->p_pbl_virt; 32821a4a6975SMintz, Yuval p_pbl_phys = ext_pbl->p_pbl_phys; 32831a4a6975SMintz, Yuval p_chain->b_external_pbl = true; 32841a4a6975SMintz, Yuval } 32851a4a6975SMintz, Yuval 3286a91eb52aSYuval Mintz qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys, 3287a91eb52aSYuval Mintz pp_virt_addr_tbl); 32882591c280SJoe Perches if (!p_pbl_virt) 3289a91eb52aSYuval Mintz return -ENOMEM; 3290a91eb52aSYuval Mintz 3291a91eb52aSYuval Mintz for (i = 0; i < page_cnt; i++) { 3292a91eb52aSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 3293a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 3294a91eb52aSYuval Mintz &p_phys, GFP_KERNEL); 32952591c280SJoe Perches if (!p_virt) 3296a91eb52aSYuval Mintz return -ENOMEM; 3297a91eb52aSYuval Mintz 3298a91eb52aSYuval Mintz if (i == 0) { 3299a91eb52aSYuval Mintz qed_chain_init_mem(p_chain, p_virt, p_phys); 3300a91eb52aSYuval Mintz qed_chain_reset(p_chain); 3301a91eb52aSYuval Mintz } 3302a91eb52aSYuval Mintz 3303a91eb52aSYuval Mintz /* Fill the PBL table with the physical address of the page */ 3304a91eb52aSYuval Mintz *(dma_addr_t *)p_pbl_virt = p_phys; 3305a91eb52aSYuval Mintz /* Keep the virtual address of the page */ 3306a91eb52aSYuval Mintz p_chain->pbl.pp_virt_addr_tbl[i] = p_virt; 3307a91eb52aSYuval Mintz 3308a91eb52aSYuval Mintz p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE; 3309a91eb52aSYuval Mintz } 3310a91eb52aSYuval Mintz 3311a91eb52aSYuval Mintz return 0; 3312a91eb52aSYuval Mintz } 3313a91eb52aSYuval Mintz 3314fe56b9e6SYuval Mintz int qed_chain_alloc(struct qed_dev *cdev, 3315fe56b9e6SYuval Mintz enum qed_chain_use_mode intended_use, 3316fe56b9e6SYuval Mintz enum qed_chain_mode mode, 3317a91eb52aSYuval Mintz enum qed_chain_cnt_type cnt_type, 33181a4a6975SMintz, Yuval u32 num_elems, 33191a4a6975SMintz, Yuval size_t elem_size, 33201a4a6975SMintz, Yuval struct qed_chain *p_chain, 33211a4a6975SMintz, Yuval struct qed_chain_ext_pbl *ext_pbl) 3322fe56b9e6SYuval Mintz { 3323a91eb52aSYuval Mintz u32 page_cnt; 3324a91eb52aSYuval Mintz int rc = 0; 3325fe56b9e6SYuval Mintz 3326fe56b9e6SYuval Mintz if (mode == QED_CHAIN_MODE_SINGLE) 3327fe56b9e6SYuval Mintz page_cnt = 1; 3328fe56b9e6SYuval Mintz else 3329fe56b9e6SYuval Mintz page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode); 3330fe56b9e6SYuval Mintz 3331a91eb52aSYuval Mintz rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt); 3332a91eb52aSYuval Mintz if (rc) { 3333a91eb52aSYuval Mintz DP_NOTICE(cdev, 33342591c280SJoe Perches "Cannot allocate a chain with the given arguments:\n"); 33352591c280SJoe Perches DP_NOTICE(cdev, 3336a91eb52aSYuval Mintz "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n", 3337a91eb52aSYuval Mintz intended_use, mode, cnt_type, num_elems, elem_size); 3338a91eb52aSYuval Mintz return rc; 3339fe56b9e6SYuval Mintz } 3340fe56b9e6SYuval Mintz 3341a91eb52aSYuval Mintz qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use, 3342a91eb52aSYuval Mintz mode, cnt_type); 3343fe56b9e6SYuval Mintz 3344a91eb52aSYuval Mintz switch (mode) { 3345a91eb52aSYuval Mintz case QED_CHAIN_MODE_NEXT_PTR: 3346a91eb52aSYuval Mintz rc = qed_chain_alloc_next_ptr(cdev, p_chain); 3347a91eb52aSYuval Mintz break; 3348a91eb52aSYuval Mintz case QED_CHAIN_MODE_SINGLE: 3349a91eb52aSYuval Mintz rc = qed_chain_alloc_single(cdev, p_chain); 3350a91eb52aSYuval Mintz break; 3351a91eb52aSYuval Mintz case QED_CHAIN_MODE_PBL: 33521a4a6975SMintz, Yuval rc = qed_chain_alloc_pbl(cdev, p_chain, ext_pbl); 3353a91eb52aSYuval Mintz break; 3354fe56b9e6SYuval Mintz } 3355a91eb52aSYuval Mintz if (rc) 3356a91eb52aSYuval Mintz goto nomem; 3357fe56b9e6SYuval Mintz 3358fe56b9e6SYuval Mintz return 0; 3359fe56b9e6SYuval Mintz 3360fe56b9e6SYuval Mintz nomem: 3361a91eb52aSYuval Mintz qed_chain_free(cdev, p_chain); 3362a91eb52aSYuval Mintz return rc; 3363fe56b9e6SYuval Mintz } 3364fe56b9e6SYuval Mintz 3365a91eb52aSYuval Mintz int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id) 3366cee4d264SManish Chopra { 3367cee4d264SManish Chopra if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) { 3368cee4d264SManish Chopra u16 min, max; 3369cee4d264SManish Chopra 3370cee4d264SManish Chopra min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE); 3371cee4d264SManish Chopra max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE); 3372cee4d264SManish Chopra DP_NOTICE(p_hwfn, 3373cee4d264SManish Chopra "l2_queue id [%d] is not valid, available indices [%d - %d]\n", 3374cee4d264SManish Chopra src_id, min, max); 3375cee4d264SManish Chopra 3376cee4d264SManish Chopra return -EINVAL; 3377cee4d264SManish Chopra } 3378cee4d264SManish Chopra 3379cee4d264SManish Chopra *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id; 3380cee4d264SManish Chopra 3381cee4d264SManish Chopra return 0; 3382cee4d264SManish Chopra } 3383cee4d264SManish Chopra 33841a635e48SYuval Mintz int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id) 3385cee4d264SManish Chopra { 3386cee4d264SManish Chopra if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) { 3387cee4d264SManish Chopra u8 min, max; 3388cee4d264SManish Chopra 3389cee4d264SManish Chopra min = (u8)RESC_START(p_hwfn, QED_VPORT); 3390cee4d264SManish Chopra max = min + RESC_NUM(p_hwfn, QED_VPORT); 3391cee4d264SManish Chopra DP_NOTICE(p_hwfn, 3392cee4d264SManish Chopra "vport id [%d] is not valid, available indices [%d - %d]\n", 3393cee4d264SManish Chopra src_id, min, max); 3394cee4d264SManish Chopra 3395cee4d264SManish Chopra return -EINVAL; 3396cee4d264SManish Chopra } 3397cee4d264SManish Chopra 3398cee4d264SManish Chopra *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id; 3399cee4d264SManish Chopra 3400cee4d264SManish Chopra return 0; 3401cee4d264SManish Chopra } 3402cee4d264SManish Chopra 34031a635e48SYuval Mintz int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id) 3404cee4d264SManish Chopra { 3405cee4d264SManish Chopra if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) { 3406cee4d264SManish Chopra u8 min, max; 3407cee4d264SManish Chopra 3408cee4d264SManish Chopra min = (u8)RESC_START(p_hwfn, QED_RSS_ENG); 3409cee4d264SManish Chopra max = min + RESC_NUM(p_hwfn, QED_RSS_ENG); 3410cee4d264SManish Chopra DP_NOTICE(p_hwfn, 3411cee4d264SManish Chopra "rss_eng id [%d] is not valid, available indices [%d - %d]\n", 3412cee4d264SManish Chopra src_id, min, max); 3413cee4d264SManish Chopra 3414cee4d264SManish Chopra return -EINVAL; 3415cee4d264SManish Chopra } 3416cee4d264SManish Chopra 3417cee4d264SManish Chopra *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id; 3418cee4d264SManish Chopra 3419cee4d264SManish Chopra return 0; 3420cee4d264SManish Chopra } 3421bcd197c8SManish Chopra 34220a7fb11cSYuval Mintz static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low, 34230a7fb11cSYuval Mintz u8 *p_filter) 34240a7fb11cSYuval Mintz { 34250a7fb11cSYuval Mintz *p_high = p_filter[1] | (p_filter[0] << 8); 34260a7fb11cSYuval Mintz *p_low = p_filter[5] | (p_filter[4] << 8) | 34270a7fb11cSYuval Mintz (p_filter[3] << 16) | (p_filter[2] << 24); 34280a7fb11cSYuval Mintz } 34290a7fb11cSYuval Mintz 34300a7fb11cSYuval Mintz int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn, 34310a7fb11cSYuval Mintz struct qed_ptt *p_ptt, u8 *p_filter) 34320a7fb11cSYuval Mintz { 34330a7fb11cSYuval Mintz u32 high = 0, low = 0, en; 34340a7fb11cSYuval Mintz int i; 34350a7fb11cSYuval Mintz 34360a7fb11cSYuval Mintz if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 34370a7fb11cSYuval Mintz return 0; 34380a7fb11cSYuval Mintz 34390a7fb11cSYuval Mintz qed_llh_mac_to_filter(&high, &low, p_filter); 34400a7fb11cSYuval Mintz 34410a7fb11cSYuval Mintz /* Find a free entry and utilize it */ 34420a7fb11cSYuval Mintz for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 34430a7fb11cSYuval Mintz en = qed_rd(p_hwfn, p_ptt, 34440a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)); 34450a7fb11cSYuval Mintz if (en) 34460a7fb11cSYuval Mintz continue; 34470a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 34480a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 34490a7fb11cSYuval Mintz 2 * i * sizeof(u32), low); 34500a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 34510a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 34520a7fb11cSYuval Mintz (2 * i + 1) * sizeof(u32), high); 34530a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 34540a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0); 34550a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 34560a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 34570a7fb11cSYuval Mintz i * sizeof(u32), 0); 34580a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 34590a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1); 34600a7fb11cSYuval Mintz break; 34610a7fb11cSYuval Mintz } 34620a7fb11cSYuval Mintz if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) { 34630a7fb11cSYuval Mintz DP_NOTICE(p_hwfn, 34640a7fb11cSYuval Mintz "Failed to find an empty LLH filter to utilize\n"); 34650a7fb11cSYuval Mintz return -EINVAL; 34660a7fb11cSYuval Mintz } 34670a7fb11cSYuval Mintz 34680a7fb11cSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 34690a7fb11cSYuval Mintz "mac: %pM is added at %d\n", 34700a7fb11cSYuval Mintz p_filter, i); 34710a7fb11cSYuval Mintz 34720a7fb11cSYuval Mintz return 0; 34730a7fb11cSYuval Mintz } 34740a7fb11cSYuval Mintz 34750a7fb11cSYuval Mintz void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn, 34760a7fb11cSYuval Mintz struct qed_ptt *p_ptt, u8 *p_filter) 34770a7fb11cSYuval Mintz { 34780a7fb11cSYuval Mintz u32 high = 0, low = 0; 34790a7fb11cSYuval Mintz int i; 34800a7fb11cSYuval Mintz 34810a7fb11cSYuval Mintz if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 34820a7fb11cSYuval Mintz return; 34830a7fb11cSYuval Mintz 34840a7fb11cSYuval Mintz qed_llh_mac_to_filter(&high, &low, p_filter); 34850a7fb11cSYuval Mintz 34860a7fb11cSYuval Mintz /* Find the entry and clean it */ 34870a7fb11cSYuval Mintz for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 34880a7fb11cSYuval Mintz if (qed_rd(p_hwfn, p_ptt, 34890a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 34900a7fb11cSYuval Mintz 2 * i * sizeof(u32)) != low) 34910a7fb11cSYuval Mintz continue; 34920a7fb11cSYuval Mintz if (qed_rd(p_hwfn, p_ptt, 34930a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 34940a7fb11cSYuval Mintz (2 * i + 1) * sizeof(u32)) != high) 34950a7fb11cSYuval Mintz continue; 34960a7fb11cSYuval Mintz 34970a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 34980a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0); 34990a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 35000a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0); 35010a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 35020a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 35030a7fb11cSYuval Mintz (2 * i + 1) * sizeof(u32), 0); 35040a7fb11cSYuval Mintz 35050a7fb11cSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 35060a7fb11cSYuval Mintz "mac: %pM is removed from %d\n", 35070a7fb11cSYuval Mintz p_filter, i); 35080a7fb11cSYuval Mintz break; 35090a7fb11cSYuval Mintz } 35100a7fb11cSYuval Mintz if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) 35110a7fb11cSYuval Mintz DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n"); 35120a7fb11cSYuval Mintz } 35130a7fb11cSYuval Mintz 35141e128c81SArun Easi int 35151e128c81SArun Easi qed_llh_add_protocol_filter(struct qed_hwfn *p_hwfn, 35161e128c81SArun Easi struct qed_ptt *p_ptt, 35171e128c81SArun Easi u16 source_port_or_eth_type, 35181e128c81SArun Easi u16 dest_port, enum qed_llh_port_filter_type_t type) 35191e128c81SArun Easi { 35201e128c81SArun Easi u32 high = 0, low = 0, en; 35211e128c81SArun Easi int i; 35221e128c81SArun Easi 35231e128c81SArun Easi if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 35241e128c81SArun Easi return 0; 35251e128c81SArun Easi 35261e128c81SArun Easi switch (type) { 35271e128c81SArun Easi case QED_LLH_FILTER_ETHERTYPE: 35281e128c81SArun Easi high = source_port_or_eth_type; 35291e128c81SArun Easi break; 35301e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_PORT: 35311e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_PORT: 35321e128c81SArun Easi low = source_port_or_eth_type << 16; 35331e128c81SArun Easi break; 35341e128c81SArun Easi case QED_LLH_FILTER_TCP_DEST_PORT: 35351e128c81SArun Easi case QED_LLH_FILTER_UDP_DEST_PORT: 35361e128c81SArun Easi low = dest_port; 35371e128c81SArun Easi break; 35381e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 35391e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 35401e128c81SArun Easi low = (source_port_or_eth_type << 16) | dest_port; 35411e128c81SArun Easi break; 35421e128c81SArun Easi default: 35431e128c81SArun Easi DP_NOTICE(p_hwfn, 35441e128c81SArun Easi "Non valid LLH protocol filter type %d\n", type); 35451e128c81SArun Easi return -EINVAL; 35461e128c81SArun Easi } 35471e128c81SArun Easi /* Find a free entry and utilize it */ 35481e128c81SArun Easi for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 35491e128c81SArun Easi en = qed_rd(p_hwfn, p_ptt, 35501e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)); 35511e128c81SArun Easi if (en) 35521e128c81SArun Easi continue; 35531e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 35541e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 35551e128c81SArun Easi 2 * i * sizeof(u32), low); 35561e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 35571e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 35581e128c81SArun Easi (2 * i + 1) * sizeof(u32), high); 35591e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 35601e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 1); 35611e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 35621e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 35631e128c81SArun Easi i * sizeof(u32), 1 << type); 35641e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 35651e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1); 35661e128c81SArun Easi break; 35671e128c81SArun Easi } 35681e128c81SArun Easi if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) { 35691e128c81SArun Easi DP_NOTICE(p_hwfn, 35701e128c81SArun Easi "Failed to find an empty LLH filter to utilize\n"); 35711e128c81SArun Easi return -EINVAL; 35721e128c81SArun Easi } 35731e128c81SArun Easi switch (type) { 35741e128c81SArun Easi case QED_LLH_FILTER_ETHERTYPE: 35751e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 35761e128c81SArun Easi "ETH type %x is added at %d\n", 35771e128c81SArun Easi source_port_or_eth_type, i); 35781e128c81SArun Easi break; 35791e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_PORT: 35801e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 35811e128c81SArun Easi "TCP src port %x is added at %d\n", 35821e128c81SArun Easi source_port_or_eth_type, i); 35831e128c81SArun Easi break; 35841e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_PORT: 35851e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 35861e128c81SArun Easi "UDP src port %x is added at %d\n", 35871e128c81SArun Easi source_port_or_eth_type, i); 35881e128c81SArun Easi break; 35891e128c81SArun Easi case QED_LLH_FILTER_TCP_DEST_PORT: 35901e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 35911e128c81SArun Easi "TCP dst port %x is added at %d\n", dest_port, i); 35921e128c81SArun Easi break; 35931e128c81SArun Easi case QED_LLH_FILTER_UDP_DEST_PORT: 35941e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 35951e128c81SArun Easi "UDP dst port %x is added at %d\n", dest_port, i); 35961e128c81SArun Easi break; 35971e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 35981e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 35991e128c81SArun Easi "TCP src/dst ports %x/%x are added at %d\n", 36001e128c81SArun Easi source_port_or_eth_type, dest_port, i); 36011e128c81SArun Easi break; 36021e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 36031e128c81SArun Easi DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 36041e128c81SArun Easi "UDP src/dst ports %x/%x are added at %d\n", 36051e128c81SArun Easi source_port_or_eth_type, dest_port, i); 36061e128c81SArun Easi break; 36071e128c81SArun Easi } 36081e128c81SArun Easi return 0; 36091e128c81SArun Easi } 36101e128c81SArun Easi 36111e128c81SArun Easi void 36121e128c81SArun Easi qed_llh_remove_protocol_filter(struct qed_hwfn *p_hwfn, 36131e128c81SArun Easi struct qed_ptt *p_ptt, 36141e128c81SArun Easi u16 source_port_or_eth_type, 36151e128c81SArun Easi u16 dest_port, 36161e128c81SArun Easi enum qed_llh_port_filter_type_t type) 36171e128c81SArun Easi { 36181e128c81SArun Easi u32 high = 0, low = 0; 36191e128c81SArun Easi int i; 36201e128c81SArun Easi 36211e128c81SArun Easi if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 36221e128c81SArun Easi return; 36231e128c81SArun Easi 36241e128c81SArun Easi switch (type) { 36251e128c81SArun Easi case QED_LLH_FILTER_ETHERTYPE: 36261e128c81SArun Easi high = source_port_or_eth_type; 36271e128c81SArun Easi break; 36281e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_PORT: 36291e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_PORT: 36301e128c81SArun Easi low = source_port_or_eth_type << 16; 36311e128c81SArun Easi break; 36321e128c81SArun Easi case QED_LLH_FILTER_TCP_DEST_PORT: 36331e128c81SArun Easi case QED_LLH_FILTER_UDP_DEST_PORT: 36341e128c81SArun Easi low = dest_port; 36351e128c81SArun Easi break; 36361e128c81SArun Easi case QED_LLH_FILTER_TCP_SRC_AND_DEST_PORT: 36371e128c81SArun Easi case QED_LLH_FILTER_UDP_SRC_AND_DEST_PORT: 36381e128c81SArun Easi low = (source_port_or_eth_type << 16) | dest_port; 36391e128c81SArun Easi break; 36401e128c81SArun Easi default: 36411e128c81SArun Easi DP_NOTICE(p_hwfn, 36421e128c81SArun Easi "Non valid LLH protocol filter type %d\n", type); 36431e128c81SArun Easi return; 36441e128c81SArun Easi } 36451e128c81SArun Easi 36461e128c81SArun Easi for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 36471e128c81SArun Easi if (!qed_rd(p_hwfn, p_ptt, 36481e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32))) 36491e128c81SArun Easi continue; 36501e128c81SArun Easi if (!qed_rd(p_hwfn, p_ptt, 36511e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32))) 36521e128c81SArun Easi continue; 36531e128c81SArun Easi if (!(qed_rd(p_hwfn, p_ptt, 36541e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 36551e128c81SArun Easi i * sizeof(u32)) & BIT(type))) 36561e128c81SArun Easi continue; 36571e128c81SArun Easi if (qed_rd(p_hwfn, p_ptt, 36581e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 36591e128c81SArun Easi 2 * i * sizeof(u32)) != low) 36601e128c81SArun Easi continue; 36611e128c81SArun Easi if (qed_rd(p_hwfn, p_ptt, 36621e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 36631e128c81SArun Easi (2 * i + 1) * sizeof(u32)) != high) 36641e128c81SArun Easi continue; 36651e128c81SArun Easi 36661e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 36671e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0); 36681e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 36691e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0); 36701e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 36711e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 36721e128c81SArun Easi i * sizeof(u32), 0); 36731e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 36741e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0); 36751e128c81SArun Easi qed_wr(p_hwfn, p_ptt, 36761e128c81SArun Easi NIG_REG_LLH_FUNC_FILTER_VALUE + 36771e128c81SArun Easi (2 * i + 1) * sizeof(u32), 0); 36781e128c81SArun Easi break; 36791e128c81SArun Easi } 36801e128c81SArun Easi 36811e128c81SArun Easi if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) 36821e128c81SArun Easi DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n"); 36831e128c81SArun Easi } 36841e128c81SArun Easi 3685722003acSSudarsana Reddy Kalluru static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 3686722003acSSudarsana Reddy Kalluru u32 hw_addr, void *p_eth_qzone, 3687722003acSSudarsana Reddy Kalluru size_t eth_qzone_size, u8 timeset) 3688722003acSSudarsana Reddy Kalluru { 3689722003acSSudarsana Reddy Kalluru struct coalescing_timeset *p_coal_timeset; 3690722003acSSudarsana Reddy Kalluru 3691722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) { 3692722003acSSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n"); 3693722003acSSudarsana Reddy Kalluru return -EINVAL; 3694722003acSSudarsana Reddy Kalluru } 3695722003acSSudarsana Reddy Kalluru 3696722003acSSudarsana Reddy Kalluru p_coal_timeset = p_eth_qzone; 3697477f2d14SRahul Verma memset(p_eth_qzone, 0, eth_qzone_size); 3698722003acSSudarsana Reddy Kalluru SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset); 3699722003acSSudarsana Reddy Kalluru SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1); 3700722003acSSudarsana Reddy Kalluru qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size); 3701722003acSSudarsana Reddy Kalluru 3702722003acSSudarsana Reddy Kalluru return 0; 3703722003acSSudarsana Reddy Kalluru } 3704722003acSSudarsana Reddy Kalluru 3705477f2d14SRahul Verma int qed_set_queue_coalesce(u16 rx_coal, u16 tx_coal, void *p_handle) 3706477f2d14SRahul Verma { 3707477f2d14SRahul Verma struct qed_queue_cid *p_cid = p_handle; 3708477f2d14SRahul Verma struct qed_hwfn *p_hwfn; 3709477f2d14SRahul Verma struct qed_ptt *p_ptt; 3710477f2d14SRahul Verma int rc = 0; 3711477f2d14SRahul Verma 3712477f2d14SRahul Verma p_hwfn = p_cid->p_owner; 3713477f2d14SRahul Verma 3714477f2d14SRahul Verma if (IS_VF(p_hwfn->cdev)) 3715477f2d14SRahul Verma return qed_vf_pf_set_coalesce(p_hwfn, rx_coal, tx_coal, p_cid); 3716477f2d14SRahul Verma 3717477f2d14SRahul Verma p_ptt = qed_ptt_acquire(p_hwfn); 3718477f2d14SRahul Verma if (!p_ptt) 3719477f2d14SRahul Verma return -EAGAIN; 3720477f2d14SRahul Verma 3721477f2d14SRahul Verma if (rx_coal) { 3722477f2d14SRahul Verma rc = qed_set_rxq_coalesce(p_hwfn, p_ptt, rx_coal, p_cid); 3723477f2d14SRahul Verma if (rc) 3724477f2d14SRahul Verma goto out; 3725477f2d14SRahul Verma p_hwfn->cdev->rx_coalesce_usecs = rx_coal; 3726477f2d14SRahul Verma } 3727477f2d14SRahul Verma 3728477f2d14SRahul Verma if (tx_coal) { 3729477f2d14SRahul Verma rc = qed_set_txq_coalesce(p_hwfn, p_ptt, tx_coal, p_cid); 3730477f2d14SRahul Verma if (rc) 3731477f2d14SRahul Verma goto out; 3732477f2d14SRahul Verma p_hwfn->cdev->tx_coalesce_usecs = tx_coal; 3733477f2d14SRahul Verma } 3734477f2d14SRahul Verma out: 3735477f2d14SRahul Verma qed_ptt_release(p_hwfn, p_ptt); 3736477f2d14SRahul Verma return rc; 3737477f2d14SRahul Verma } 3738477f2d14SRahul Verma 3739477f2d14SRahul Verma int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, 3740477f2d14SRahul Verma struct qed_ptt *p_ptt, 3741477f2d14SRahul Verma u16 coalesce, struct qed_queue_cid *p_cid) 3742722003acSSudarsana Reddy Kalluru { 3743722003acSSudarsana Reddy Kalluru struct ustorm_eth_queue_zone eth_qzone; 3744722003acSSudarsana Reddy Kalluru u8 timeset, timer_res; 3745722003acSSudarsana Reddy Kalluru u32 address; 3746722003acSSudarsana Reddy Kalluru int rc; 3747722003acSSudarsana Reddy Kalluru 3748722003acSSudarsana Reddy Kalluru /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 3749722003acSSudarsana Reddy Kalluru if (coalesce <= 0x7F) { 3750722003acSSudarsana Reddy Kalluru timer_res = 0; 3751722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0xFF) { 3752722003acSSudarsana Reddy Kalluru timer_res = 1; 3753722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0x1FF) { 3754722003acSSudarsana Reddy Kalluru timer_res = 2; 3755722003acSSudarsana Reddy Kalluru } else { 3756722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 3757722003acSSudarsana Reddy Kalluru return -EINVAL; 3758722003acSSudarsana Reddy Kalluru } 3759722003acSSudarsana Reddy Kalluru timeset = (u8)(coalesce >> timer_res); 3760722003acSSudarsana Reddy Kalluru 3761477f2d14SRahul Verma rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, 3762477f2d14SRahul Verma p_cid->sb_igu_id, false); 3763722003acSSudarsana Reddy Kalluru if (rc) 3764722003acSSudarsana Reddy Kalluru goto out; 3765722003acSSudarsana Reddy Kalluru 3766477f2d14SRahul Verma address = BAR0_MAP_REG_USDM_RAM + 3767477f2d14SRahul Verma USTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id); 3768722003acSSudarsana Reddy Kalluru 3769722003acSSudarsana Reddy Kalluru rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 3770722003acSSudarsana Reddy Kalluru sizeof(struct ustorm_eth_queue_zone), timeset); 3771722003acSSudarsana Reddy Kalluru if (rc) 3772722003acSSudarsana Reddy Kalluru goto out; 3773722003acSSudarsana Reddy Kalluru 3774722003acSSudarsana Reddy Kalluru out: 3775722003acSSudarsana Reddy Kalluru return rc; 3776722003acSSudarsana Reddy Kalluru } 3777722003acSSudarsana Reddy Kalluru 3778477f2d14SRahul Verma int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, 3779477f2d14SRahul Verma struct qed_ptt *p_ptt, 3780477f2d14SRahul Verma u16 coalesce, struct qed_queue_cid *p_cid) 3781722003acSSudarsana Reddy Kalluru { 3782722003acSSudarsana Reddy Kalluru struct xstorm_eth_queue_zone eth_qzone; 3783722003acSSudarsana Reddy Kalluru u8 timeset, timer_res; 3784722003acSSudarsana Reddy Kalluru u32 address; 3785722003acSSudarsana Reddy Kalluru int rc; 3786722003acSSudarsana Reddy Kalluru 3787722003acSSudarsana Reddy Kalluru /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 3788722003acSSudarsana Reddy Kalluru if (coalesce <= 0x7F) { 3789722003acSSudarsana Reddy Kalluru timer_res = 0; 3790722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0xFF) { 3791722003acSSudarsana Reddy Kalluru timer_res = 1; 3792722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0x1FF) { 3793722003acSSudarsana Reddy Kalluru timer_res = 2; 3794722003acSSudarsana Reddy Kalluru } else { 3795722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 3796722003acSSudarsana Reddy Kalluru return -EINVAL; 3797722003acSSudarsana Reddy Kalluru } 3798722003acSSudarsana Reddy Kalluru timeset = (u8)(coalesce >> timer_res); 3799722003acSSudarsana Reddy Kalluru 3800477f2d14SRahul Verma rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, 3801477f2d14SRahul Verma p_cid->sb_igu_id, true); 3802722003acSSudarsana Reddy Kalluru if (rc) 3803722003acSSudarsana Reddy Kalluru goto out; 3804722003acSSudarsana Reddy Kalluru 3805477f2d14SRahul Verma address = BAR0_MAP_REG_XSDM_RAM + 3806477f2d14SRahul Verma XSTORM_ETH_QUEUE_ZONE_OFFSET(p_cid->abs.queue_id); 3807722003acSSudarsana Reddy Kalluru 3808722003acSSudarsana Reddy Kalluru rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 3809722003acSSudarsana Reddy Kalluru sizeof(struct xstorm_eth_queue_zone), timeset); 3810722003acSSudarsana Reddy Kalluru out: 3811722003acSSudarsana Reddy Kalluru return rc; 3812722003acSSudarsana Reddy Kalluru } 3813722003acSSudarsana Reddy Kalluru 3814bcd197c8SManish Chopra /* Calculate final WFQ values for all vports and configure them. 3815bcd197c8SManish Chopra * After this configuration each vport will have 3816bcd197c8SManish Chopra * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT) 3817bcd197c8SManish Chopra */ 3818bcd197c8SManish Chopra static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 3819bcd197c8SManish Chopra struct qed_ptt *p_ptt, 3820bcd197c8SManish Chopra u32 min_pf_rate) 3821bcd197c8SManish Chopra { 3822bcd197c8SManish Chopra struct init_qm_vport_params *vport_params; 3823bcd197c8SManish Chopra int i; 3824bcd197c8SManish Chopra 3825bcd197c8SManish Chopra vport_params = p_hwfn->qm_info.qm_vport_params; 3826bcd197c8SManish Chopra 3827bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 3828bcd197c8SManish Chopra u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 3829bcd197c8SManish Chopra 3830bcd197c8SManish Chopra vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) / 3831bcd197c8SManish Chopra min_pf_rate; 3832bcd197c8SManish Chopra qed_init_vport_wfq(p_hwfn, p_ptt, 3833bcd197c8SManish Chopra vport_params[i].first_tx_pq_id, 3834bcd197c8SManish Chopra vport_params[i].vport_wfq); 3835bcd197c8SManish Chopra } 3836bcd197c8SManish Chopra } 3837bcd197c8SManish Chopra 3838bcd197c8SManish Chopra static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn, 3839bcd197c8SManish Chopra u32 min_pf_rate) 3840bcd197c8SManish Chopra 3841bcd197c8SManish Chopra { 3842bcd197c8SManish Chopra int i; 3843bcd197c8SManish Chopra 3844bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) 3845bcd197c8SManish Chopra p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1; 3846bcd197c8SManish Chopra } 3847bcd197c8SManish Chopra 3848bcd197c8SManish Chopra static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 3849bcd197c8SManish Chopra struct qed_ptt *p_ptt, 3850bcd197c8SManish Chopra u32 min_pf_rate) 3851bcd197c8SManish Chopra { 3852bcd197c8SManish Chopra struct init_qm_vport_params *vport_params; 3853bcd197c8SManish Chopra int i; 3854bcd197c8SManish Chopra 3855bcd197c8SManish Chopra vport_params = p_hwfn->qm_info.qm_vport_params; 3856bcd197c8SManish Chopra 3857bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 3858bcd197c8SManish Chopra qed_init_wfq_default_param(p_hwfn, min_pf_rate); 3859bcd197c8SManish Chopra qed_init_vport_wfq(p_hwfn, p_ptt, 3860bcd197c8SManish Chopra vport_params[i].first_tx_pq_id, 3861bcd197c8SManish Chopra vport_params[i].vport_wfq); 3862bcd197c8SManish Chopra } 3863bcd197c8SManish Chopra } 3864bcd197c8SManish Chopra 3865bcd197c8SManish Chopra /* This function performs several validations for WFQ 3866bcd197c8SManish Chopra * configuration and required min rate for a given vport 3867bcd197c8SManish Chopra * 1. req_rate must be greater than one percent of min_pf_rate. 3868bcd197c8SManish Chopra * 2. req_rate should not cause other vports [not configured for WFQ explicitly] 3869bcd197c8SManish Chopra * rates to get less than one percent of min_pf_rate. 3870bcd197c8SManish Chopra * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate. 3871bcd197c8SManish Chopra */ 3872bcd197c8SManish Chopra static int qed_init_wfq_param(struct qed_hwfn *p_hwfn, 38731a635e48SYuval Mintz u16 vport_id, u32 req_rate, u32 min_pf_rate) 3874bcd197c8SManish Chopra { 3875bcd197c8SManish Chopra u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0; 3876bcd197c8SManish Chopra int non_requested_count = 0, req_count = 0, i, num_vports; 3877bcd197c8SManish Chopra 3878bcd197c8SManish Chopra num_vports = p_hwfn->qm_info.num_vports; 3879bcd197c8SManish Chopra 3880bcd197c8SManish Chopra /* Accounting for the vports which are configured for WFQ explicitly */ 3881bcd197c8SManish Chopra for (i = 0; i < num_vports; i++) { 3882bcd197c8SManish Chopra u32 tmp_speed; 3883bcd197c8SManish Chopra 3884bcd197c8SManish Chopra if ((i != vport_id) && 3885bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[i].configured) { 3886bcd197c8SManish Chopra req_count++; 3887bcd197c8SManish Chopra tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 3888bcd197c8SManish Chopra total_req_min_rate += tmp_speed; 3889bcd197c8SManish Chopra } 3890bcd197c8SManish Chopra } 3891bcd197c8SManish Chopra 3892bcd197c8SManish Chopra /* Include current vport data as well */ 3893bcd197c8SManish Chopra req_count++; 3894bcd197c8SManish Chopra total_req_min_rate += req_rate; 3895bcd197c8SManish Chopra non_requested_count = num_vports - req_count; 3896bcd197c8SManish Chopra 3897bcd197c8SManish Chopra if (req_rate < min_pf_rate / QED_WFQ_UNIT) { 3898bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 3899bcd197c8SManish Chopra "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 3900bcd197c8SManish Chopra vport_id, req_rate, min_pf_rate); 3901bcd197c8SManish Chopra return -EINVAL; 3902bcd197c8SManish Chopra } 3903bcd197c8SManish Chopra 3904bcd197c8SManish Chopra if (num_vports > QED_WFQ_UNIT) { 3905bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 3906bcd197c8SManish Chopra "Number of vports is greater than %d\n", 3907bcd197c8SManish Chopra QED_WFQ_UNIT); 3908bcd197c8SManish Chopra return -EINVAL; 3909bcd197c8SManish Chopra } 3910bcd197c8SManish Chopra 3911bcd197c8SManish Chopra if (total_req_min_rate > min_pf_rate) { 3912bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 3913bcd197c8SManish Chopra "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n", 3914bcd197c8SManish Chopra total_req_min_rate, min_pf_rate); 3915bcd197c8SManish Chopra return -EINVAL; 3916bcd197c8SManish Chopra } 3917bcd197c8SManish Chopra 3918bcd197c8SManish Chopra total_left_rate = min_pf_rate - total_req_min_rate; 3919bcd197c8SManish Chopra 3920bcd197c8SManish Chopra left_rate_per_vp = total_left_rate / non_requested_count; 3921bcd197c8SManish Chopra if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) { 3922bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 3923bcd197c8SManish Chopra "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 3924bcd197c8SManish Chopra left_rate_per_vp, min_pf_rate); 3925bcd197c8SManish Chopra return -EINVAL; 3926bcd197c8SManish Chopra } 3927bcd197c8SManish Chopra 3928bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate; 3929bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[vport_id].configured = true; 3930bcd197c8SManish Chopra 3931bcd197c8SManish Chopra for (i = 0; i < num_vports; i++) { 3932bcd197c8SManish Chopra if (p_hwfn->qm_info.wfq_data[i].configured) 3933bcd197c8SManish Chopra continue; 3934bcd197c8SManish Chopra 3935bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp; 3936bcd197c8SManish Chopra } 3937bcd197c8SManish Chopra 3938bcd197c8SManish Chopra return 0; 3939bcd197c8SManish Chopra } 3940bcd197c8SManish Chopra 3941733def6aSYuval Mintz static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn, 3942733def6aSYuval Mintz struct qed_ptt *p_ptt, u16 vp_id, u32 rate) 3943733def6aSYuval Mintz { 3944733def6aSYuval Mintz struct qed_mcp_link_state *p_link; 3945733def6aSYuval Mintz int rc = 0; 3946733def6aSYuval Mintz 3947733def6aSYuval Mintz p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output; 3948733def6aSYuval Mintz 3949733def6aSYuval Mintz if (!p_link->min_pf_rate) { 3950733def6aSYuval Mintz p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate; 3951733def6aSYuval Mintz p_hwfn->qm_info.wfq_data[vp_id].configured = true; 3952733def6aSYuval Mintz return rc; 3953733def6aSYuval Mintz } 3954733def6aSYuval Mintz 3955733def6aSYuval Mintz rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate); 3956733def6aSYuval Mintz 39571a635e48SYuval Mintz if (!rc) 3958733def6aSYuval Mintz qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, 3959733def6aSYuval Mintz p_link->min_pf_rate); 3960733def6aSYuval Mintz else 3961733def6aSYuval Mintz DP_NOTICE(p_hwfn, 3962733def6aSYuval Mintz "Validation failed while configuring min rate\n"); 3963733def6aSYuval Mintz 3964733def6aSYuval Mintz return rc; 3965733def6aSYuval Mintz } 3966733def6aSYuval Mintz 3967bcd197c8SManish Chopra static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn, 3968bcd197c8SManish Chopra struct qed_ptt *p_ptt, 3969bcd197c8SManish Chopra u32 min_pf_rate) 3970bcd197c8SManish Chopra { 3971bcd197c8SManish Chopra bool use_wfq = false; 3972bcd197c8SManish Chopra int rc = 0; 3973bcd197c8SManish Chopra u16 i; 3974bcd197c8SManish Chopra 3975bcd197c8SManish Chopra /* Validate all pre configured vports for wfq */ 3976bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 3977bcd197c8SManish Chopra u32 rate; 3978bcd197c8SManish Chopra 3979bcd197c8SManish Chopra if (!p_hwfn->qm_info.wfq_data[i].configured) 3980bcd197c8SManish Chopra continue; 3981bcd197c8SManish Chopra 3982bcd197c8SManish Chopra rate = p_hwfn->qm_info.wfq_data[i].min_speed; 3983bcd197c8SManish Chopra use_wfq = true; 3984bcd197c8SManish Chopra 3985bcd197c8SManish Chopra rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate); 3986bcd197c8SManish Chopra if (rc) { 3987bcd197c8SManish Chopra DP_NOTICE(p_hwfn, 3988bcd197c8SManish Chopra "WFQ validation failed while configuring min rate\n"); 3989bcd197c8SManish Chopra break; 3990bcd197c8SManish Chopra } 3991bcd197c8SManish Chopra } 3992bcd197c8SManish Chopra 3993bcd197c8SManish Chopra if (!rc && use_wfq) 3994bcd197c8SManish Chopra qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 3995bcd197c8SManish Chopra else 3996bcd197c8SManish Chopra qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 3997bcd197c8SManish Chopra 3998bcd197c8SManish Chopra return rc; 3999bcd197c8SManish Chopra } 4000bcd197c8SManish Chopra 4001733def6aSYuval Mintz /* Main API for qed clients to configure vport min rate. 4002733def6aSYuval Mintz * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)] 4003733def6aSYuval Mintz * rate - Speed in Mbps needs to be assigned to a given vport. 4004733def6aSYuval Mintz */ 4005733def6aSYuval Mintz int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate) 4006733def6aSYuval Mintz { 4007733def6aSYuval Mintz int i, rc = -EINVAL; 4008733def6aSYuval Mintz 4009733def6aSYuval Mintz /* Currently not supported; Might change in future */ 4010733def6aSYuval Mintz if (cdev->num_hwfns > 1) { 4011733def6aSYuval Mintz DP_NOTICE(cdev, 4012733def6aSYuval Mintz "WFQ configuration is not supported for this device\n"); 4013733def6aSYuval Mintz return rc; 4014733def6aSYuval Mintz } 4015733def6aSYuval Mintz 4016733def6aSYuval Mintz for_each_hwfn(cdev, i) { 4017733def6aSYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 4018733def6aSYuval Mintz struct qed_ptt *p_ptt; 4019733def6aSYuval Mintz 4020733def6aSYuval Mintz p_ptt = qed_ptt_acquire(p_hwfn); 4021733def6aSYuval Mintz if (!p_ptt) 4022733def6aSYuval Mintz return -EBUSY; 4023733def6aSYuval Mintz 4024733def6aSYuval Mintz rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate); 4025733def6aSYuval Mintz 4026d572c430SYuval Mintz if (rc) { 4027733def6aSYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 4028733def6aSYuval Mintz return rc; 4029733def6aSYuval Mintz } 4030733def6aSYuval Mintz 4031733def6aSYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 4032733def6aSYuval Mintz } 4033733def6aSYuval Mintz 4034733def6aSYuval Mintz return rc; 4035733def6aSYuval Mintz } 4036733def6aSYuval Mintz 4037bcd197c8SManish Chopra /* API to configure WFQ from mcp link change */ 40386f437d43SMintz, Yuval void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, 40396f437d43SMintz, Yuval struct qed_ptt *p_ptt, u32 min_pf_rate) 4040bcd197c8SManish Chopra { 4041bcd197c8SManish Chopra int i; 4042bcd197c8SManish Chopra 40433e7cfce2SYuval Mintz if (cdev->num_hwfns > 1) { 40443e7cfce2SYuval Mintz DP_VERBOSE(cdev, 40453e7cfce2SYuval Mintz NETIF_MSG_LINK, 40463e7cfce2SYuval Mintz "WFQ configuration is not supported for this device\n"); 40473e7cfce2SYuval Mintz return; 40483e7cfce2SYuval Mintz } 40493e7cfce2SYuval Mintz 4050bcd197c8SManish Chopra for_each_hwfn(cdev, i) { 4051bcd197c8SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 4052bcd197c8SManish Chopra 40536f437d43SMintz, Yuval __qed_configure_vp_wfq_on_link_change(p_hwfn, p_ptt, 4054bcd197c8SManish Chopra min_pf_rate); 4055bcd197c8SManish Chopra } 4056bcd197c8SManish Chopra } 40574b01e519SManish Chopra 40584b01e519SManish Chopra int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn, 40594b01e519SManish Chopra struct qed_ptt *p_ptt, 40604b01e519SManish Chopra struct qed_mcp_link_state *p_link, 40614b01e519SManish Chopra u8 max_bw) 40624b01e519SManish Chopra { 40634b01e519SManish Chopra int rc = 0; 40644b01e519SManish Chopra 40654b01e519SManish Chopra p_hwfn->mcp_info->func_info.bandwidth_max = max_bw; 40664b01e519SManish Chopra 40674b01e519SManish Chopra if (!p_link->line_speed && (max_bw != 100)) 40684b01e519SManish Chopra return rc; 40694b01e519SManish Chopra 40704b01e519SManish Chopra p_link->speed = (p_link->line_speed * max_bw) / 100; 40714b01e519SManish Chopra p_hwfn->qm_info.pf_rl = p_link->speed; 40724b01e519SManish Chopra 40734b01e519SManish Chopra /* Since the limiter also affects Tx-switched traffic, we don't want it 40744b01e519SManish Chopra * to limit such traffic in case there's no actual limit. 40754b01e519SManish Chopra * In that case, set limit to imaginary high boundary. 40764b01e519SManish Chopra */ 40774b01e519SManish Chopra if (max_bw == 100) 40784b01e519SManish Chopra p_hwfn->qm_info.pf_rl = 100000; 40794b01e519SManish Chopra 40804b01e519SManish Chopra rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, 40814b01e519SManish Chopra p_hwfn->qm_info.pf_rl); 40824b01e519SManish Chopra 40834b01e519SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 40844b01e519SManish Chopra "Configured MAX bandwidth to be %08x Mb/sec\n", 40854b01e519SManish Chopra p_link->speed); 40864b01e519SManish Chopra 40874b01e519SManish Chopra return rc; 40884b01e519SManish Chopra } 40894b01e519SManish Chopra 40904b01e519SManish Chopra /* Main API to configure PF max bandwidth where bw range is [1 - 100] */ 40914b01e519SManish Chopra int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw) 40924b01e519SManish Chopra { 40934b01e519SManish Chopra int i, rc = -EINVAL; 40944b01e519SManish Chopra 40954b01e519SManish Chopra if (max_bw < 1 || max_bw > 100) { 40964b01e519SManish Chopra DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n"); 40974b01e519SManish Chopra return rc; 40984b01e519SManish Chopra } 40994b01e519SManish Chopra 41004b01e519SManish Chopra for_each_hwfn(cdev, i) { 41014b01e519SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 41024b01e519SManish Chopra struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 41034b01e519SManish Chopra struct qed_mcp_link_state *p_link; 41044b01e519SManish Chopra struct qed_ptt *p_ptt; 41054b01e519SManish Chopra 41064b01e519SManish Chopra p_link = &p_lead->mcp_info->link_output; 41074b01e519SManish Chopra 41084b01e519SManish Chopra p_ptt = qed_ptt_acquire(p_hwfn); 41094b01e519SManish Chopra if (!p_ptt) 41104b01e519SManish Chopra return -EBUSY; 41114b01e519SManish Chopra 41124b01e519SManish Chopra rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, 41134b01e519SManish Chopra p_link, max_bw); 41144b01e519SManish Chopra 41154b01e519SManish Chopra qed_ptt_release(p_hwfn, p_ptt); 41164b01e519SManish Chopra 41174b01e519SManish Chopra if (rc) 41184b01e519SManish Chopra break; 41194b01e519SManish Chopra } 41204b01e519SManish Chopra 41214b01e519SManish Chopra return rc; 41224b01e519SManish Chopra } 4123a64b02d5SManish Chopra 4124a64b02d5SManish Chopra int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn, 4125a64b02d5SManish Chopra struct qed_ptt *p_ptt, 4126a64b02d5SManish Chopra struct qed_mcp_link_state *p_link, 4127a64b02d5SManish Chopra u8 min_bw) 4128a64b02d5SManish Chopra { 4129a64b02d5SManish Chopra int rc = 0; 4130a64b02d5SManish Chopra 4131a64b02d5SManish Chopra p_hwfn->mcp_info->func_info.bandwidth_min = min_bw; 4132a64b02d5SManish Chopra p_hwfn->qm_info.pf_wfq = min_bw; 4133a64b02d5SManish Chopra 4134a64b02d5SManish Chopra if (!p_link->line_speed) 4135a64b02d5SManish Chopra return rc; 4136a64b02d5SManish Chopra 4137a64b02d5SManish Chopra p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100; 4138a64b02d5SManish Chopra 4139a64b02d5SManish Chopra rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw); 4140a64b02d5SManish Chopra 4141a64b02d5SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 4142a64b02d5SManish Chopra "Configured MIN bandwidth to be %d Mb/sec\n", 4143a64b02d5SManish Chopra p_link->min_pf_rate); 4144a64b02d5SManish Chopra 4145a64b02d5SManish Chopra return rc; 4146a64b02d5SManish Chopra } 4147a64b02d5SManish Chopra 4148a64b02d5SManish Chopra /* Main API to configure PF min bandwidth where bw range is [1-100] */ 4149a64b02d5SManish Chopra int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw) 4150a64b02d5SManish Chopra { 4151a64b02d5SManish Chopra int i, rc = -EINVAL; 4152a64b02d5SManish Chopra 4153a64b02d5SManish Chopra if (min_bw < 1 || min_bw > 100) { 4154a64b02d5SManish Chopra DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n"); 4155a64b02d5SManish Chopra return rc; 4156a64b02d5SManish Chopra } 4157a64b02d5SManish Chopra 4158a64b02d5SManish Chopra for_each_hwfn(cdev, i) { 4159a64b02d5SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 4160a64b02d5SManish Chopra struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 4161a64b02d5SManish Chopra struct qed_mcp_link_state *p_link; 4162a64b02d5SManish Chopra struct qed_ptt *p_ptt; 4163a64b02d5SManish Chopra 4164a64b02d5SManish Chopra p_link = &p_lead->mcp_info->link_output; 4165a64b02d5SManish Chopra 4166a64b02d5SManish Chopra p_ptt = qed_ptt_acquire(p_hwfn); 4167a64b02d5SManish Chopra if (!p_ptt) 4168a64b02d5SManish Chopra return -EBUSY; 4169a64b02d5SManish Chopra 4170a64b02d5SManish Chopra rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, 4171a64b02d5SManish Chopra p_link, min_bw); 4172a64b02d5SManish Chopra if (rc) { 4173a64b02d5SManish Chopra qed_ptt_release(p_hwfn, p_ptt); 4174a64b02d5SManish Chopra return rc; 4175a64b02d5SManish Chopra } 4176a64b02d5SManish Chopra 4177a64b02d5SManish Chopra if (p_link->min_pf_rate) { 4178a64b02d5SManish Chopra u32 min_rate = p_link->min_pf_rate; 4179a64b02d5SManish Chopra 4180a64b02d5SManish Chopra rc = __qed_configure_vp_wfq_on_link_change(p_hwfn, 4181a64b02d5SManish Chopra p_ptt, 4182a64b02d5SManish Chopra min_rate); 4183a64b02d5SManish Chopra } 4184a64b02d5SManish Chopra 4185a64b02d5SManish Chopra qed_ptt_release(p_hwfn, p_ptt); 4186a64b02d5SManish Chopra } 4187a64b02d5SManish Chopra 4188a64b02d5SManish Chopra return rc; 4189a64b02d5SManish Chopra } 4190733def6aSYuval Mintz 4191733def6aSYuval Mintz void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 4192733def6aSYuval Mintz { 4193733def6aSYuval Mintz struct qed_mcp_link_state *p_link; 4194733def6aSYuval Mintz 4195733def6aSYuval Mintz p_link = &p_hwfn->mcp_info->link_output; 4196733def6aSYuval Mintz 4197733def6aSYuval Mintz if (p_link->min_pf_rate) 4198733def6aSYuval Mintz qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, 4199733def6aSYuval Mintz p_link->min_pf_rate); 4200733def6aSYuval Mintz 4201733def6aSYuval Mintz memset(p_hwfn->qm_info.wfq_data, 0, 4202733def6aSYuval Mintz sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports); 4203733def6aSYuval Mintz } 42049c79ddaaSMintz, Yuval 42059c79ddaaSMintz, Yuval int qed_device_num_engines(struct qed_dev *cdev) 42069c79ddaaSMintz, Yuval { 42079c79ddaaSMintz, Yuval return QED_IS_BB(cdev) ? 2 : 1; 42089c79ddaaSMintz, Yuval } 4209db82f70eSsudarsana.kalluru@cavium.com 4210db82f70eSsudarsana.kalluru@cavium.com static int qed_device_num_ports(struct qed_dev *cdev) 4211db82f70eSsudarsana.kalluru@cavium.com { 4212db82f70eSsudarsana.kalluru@cavium.com /* in CMT always only one port */ 4213db82f70eSsudarsana.kalluru@cavium.com if (cdev->num_hwfns > 1) 4214db82f70eSsudarsana.kalluru@cavium.com return 1; 4215db82f70eSsudarsana.kalluru@cavium.com 421678cea9ffSTomer Tayar return cdev->num_ports_in_engine * qed_device_num_engines(cdev); 4217db82f70eSsudarsana.kalluru@cavium.com } 4218db82f70eSsudarsana.kalluru@cavium.com 4219db82f70eSsudarsana.kalluru@cavium.com int qed_device_get_port_id(struct qed_dev *cdev) 4220db82f70eSsudarsana.kalluru@cavium.com { 4221db82f70eSsudarsana.kalluru@cavium.com return (QED_LEADING_HWFN(cdev)->abs_pf_id) % qed_device_num_ports(cdev); 4222db82f70eSsudarsana.kalluru@cavium.com } 4223456a5849SKalderon, Michal 4224456a5849SKalderon, Michal void qed_set_fw_mac_addr(__le16 *fw_msb, 4225456a5849SKalderon, Michal __le16 *fw_mid, __le16 *fw_lsb, u8 *mac) 4226456a5849SKalderon, Michal { 4227456a5849SKalderon, Michal ((u8 *)fw_msb)[0] = mac[1]; 4228456a5849SKalderon, Michal ((u8 *)fw_msb)[1] = mac[0]; 4229456a5849SKalderon, Michal ((u8 *)fw_mid)[0] = mac[3]; 4230456a5849SKalderon, Michal ((u8 *)fw_mid)[1] = mac[2]; 4231456a5849SKalderon, Michal ((u8 *)fw_lsb)[0] = mac[5]; 4232456a5849SKalderon, Michal ((u8 *)fw_lsb)[1] = mac[4]; 4233456a5849SKalderon, Michal } 4234