1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2fe56b9e6SYuval Mintz * Copyright (c) 2015 QLogic Corporation 3fe56b9e6SYuval Mintz * 4fe56b9e6SYuval Mintz * This software is available under the terms of the GNU General Public License 5fe56b9e6SYuval Mintz * (GPL) Version 2, available from the file COPYING in the main directory of 6fe56b9e6SYuval Mintz * this source tree. 7fe56b9e6SYuval Mintz */ 8fe56b9e6SYuval Mintz 9fe56b9e6SYuval Mintz #include <linux/types.h> 10fe56b9e6SYuval Mintz #include <asm/byteorder.h> 11fe56b9e6SYuval Mintz #include <linux/io.h> 12fe56b9e6SYuval Mintz #include <linux/delay.h> 13fe56b9e6SYuval Mintz #include <linux/dma-mapping.h> 14fe56b9e6SYuval Mintz #include <linux/errno.h> 15fe56b9e6SYuval Mintz #include <linux/kernel.h> 16fe56b9e6SYuval Mintz #include <linux/mutex.h> 17fe56b9e6SYuval Mintz #include <linux/pci.h> 18fe56b9e6SYuval Mintz #include <linux/slab.h> 19fe56b9e6SYuval Mintz #include <linux/string.h> 20a91eb52aSYuval Mintz #include <linux/vmalloc.h> 21fe56b9e6SYuval Mintz #include <linux/etherdevice.h> 22fe56b9e6SYuval Mintz #include <linux/qed/qed_chain.h> 23fe56b9e6SYuval Mintz #include <linux/qed/qed_if.h> 24fe56b9e6SYuval Mintz #include "qed.h" 25fe56b9e6SYuval Mintz #include "qed_cxt.h" 2639651abdSSudarsana Reddy Kalluru #include "qed_dcbx.h" 27fe56b9e6SYuval Mintz #include "qed_dev_api.h" 28fe56b9e6SYuval Mintz #include "qed_hsi.h" 29fe56b9e6SYuval Mintz #include "qed_hw.h" 30fe56b9e6SYuval Mintz #include "qed_init_ops.h" 31fe56b9e6SYuval Mintz #include "qed_int.h" 320a7fb11cSYuval Mintz #include "qed_ll2.h" 33fe56b9e6SYuval Mintz #include "qed_mcp.h" 34fe56b9e6SYuval Mintz #include "qed_reg_addr.h" 35fe56b9e6SYuval Mintz #include "qed_sp.h" 3632a47e72SYuval Mintz #include "qed_sriov.h" 370b55e27dSYuval Mintz #include "qed_vf.h" 3851ff1725SRam Amrani #include "qed_roce.h" 39fe56b9e6SYuval Mintz 400caf5b26SWei Yongjun static DEFINE_SPINLOCK(qm_lock); 4139651abdSSudarsana Reddy Kalluru 4251ff1725SRam Amrani #define QED_MIN_DPIS (4) 4351ff1725SRam Amrani #define QED_MIN_PWM_REGION (QED_WID_SIZE * QED_MIN_DPIS) 4451ff1725SRam Amrani 45fe56b9e6SYuval Mintz /* API common to all protocols */ 46c2035eeaSRam Amrani enum BAR_ID { 47c2035eeaSRam Amrani BAR_ID_0, /* used for GRC */ 48c2035eeaSRam Amrani BAR_ID_1 /* Used for doorbells */ 49c2035eeaSRam Amrani }; 50c2035eeaSRam Amrani 511a635e48SYuval Mintz static u32 qed_hw_bar_size(struct qed_hwfn *p_hwfn, enum BAR_ID bar_id) 52c2035eeaSRam Amrani { 53c2035eeaSRam Amrani u32 bar_reg = (bar_id == BAR_ID_0 ? 54c2035eeaSRam Amrani PGLUE_B_REG_PF_BAR0_SIZE : PGLUE_B_REG_PF_BAR1_SIZE); 551408cc1fSYuval Mintz u32 val; 56c2035eeaSRam Amrani 571408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 581408cc1fSYuval Mintz return 1 << 17; 591408cc1fSYuval Mintz 601408cc1fSYuval Mintz val = qed_rd(p_hwfn, p_hwfn->p_main_ptt, bar_reg); 61c2035eeaSRam Amrani if (val) 62c2035eeaSRam Amrani return 1 << (val + 15); 63c2035eeaSRam Amrani 64c2035eeaSRam Amrani /* Old MFW initialized above registered only conditionally */ 65c2035eeaSRam Amrani if (p_hwfn->cdev->num_hwfns > 1) { 66c2035eeaSRam Amrani DP_INFO(p_hwfn, 67c2035eeaSRam Amrani "BAR size not configured. Assuming BAR size of 256kB for GRC and 512kB for DB\n"); 68c2035eeaSRam Amrani return BAR_ID_0 ? 256 * 1024 : 512 * 1024; 69c2035eeaSRam Amrani } else { 70c2035eeaSRam Amrani DP_INFO(p_hwfn, 71c2035eeaSRam Amrani "BAR size not configured. Assuming BAR size of 512kB for GRC and 512kB for DB\n"); 72c2035eeaSRam Amrani return 512 * 1024; 73c2035eeaSRam Amrani } 74c2035eeaSRam Amrani } 75c2035eeaSRam Amrani 761a635e48SYuval Mintz void qed_init_dp(struct qed_dev *cdev, u32 dp_module, u8 dp_level) 77fe56b9e6SYuval Mintz { 78fe56b9e6SYuval Mintz u32 i; 79fe56b9e6SYuval Mintz 80fe56b9e6SYuval Mintz cdev->dp_level = dp_level; 81fe56b9e6SYuval Mintz cdev->dp_module = dp_module; 82fe56b9e6SYuval Mintz for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 83fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 84fe56b9e6SYuval Mintz 85fe56b9e6SYuval Mintz p_hwfn->dp_level = dp_level; 86fe56b9e6SYuval Mintz p_hwfn->dp_module = dp_module; 87fe56b9e6SYuval Mintz } 88fe56b9e6SYuval Mintz } 89fe56b9e6SYuval Mintz 90fe56b9e6SYuval Mintz void qed_init_struct(struct qed_dev *cdev) 91fe56b9e6SYuval Mintz { 92fe56b9e6SYuval Mintz u8 i; 93fe56b9e6SYuval Mintz 94fe56b9e6SYuval Mintz for (i = 0; i < MAX_HWFNS_PER_DEVICE; i++) { 95fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 96fe56b9e6SYuval Mintz 97fe56b9e6SYuval Mintz p_hwfn->cdev = cdev; 98fe56b9e6SYuval Mintz p_hwfn->my_id = i; 99fe56b9e6SYuval Mintz p_hwfn->b_active = false; 100fe56b9e6SYuval Mintz 101fe56b9e6SYuval Mintz mutex_init(&p_hwfn->dmae_info.mutex); 102fe56b9e6SYuval Mintz } 103fe56b9e6SYuval Mintz 104fe56b9e6SYuval Mintz /* hwfn 0 is always active */ 105fe56b9e6SYuval Mintz cdev->hwfns[0].b_active = true; 106fe56b9e6SYuval Mintz 107fe56b9e6SYuval Mintz /* set the default cache alignment to 128 */ 108fe56b9e6SYuval Mintz cdev->cache_shift = 7; 109fe56b9e6SYuval Mintz } 110fe56b9e6SYuval Mintz 111fe56b9e6SYuval Mintz static void qed_qm_info_free(struct qed_hwfn *p_hwfn) 112fe56b9e6SYuval Mintz { 113fe56b9e6SYuval Mintz struct qed_qm_info *qm_info = &p_hwfn->qm_info; 114fe56b9e6SYuval Mintz 115fe56b9e6SYuval Mintz kfree(qm_info->qm_pq_params); 116fe56b9e6SYuval Mintz qm_info->qm_pq_params = NULL; 117fe56b9e6SYuval Mintz kfree(qm_info->qm_vport_params); 118fe56b9e6SYuval Mintz qm_info->qm_vport_params = NULL; 119fe56b9e6SYuval Mintz kfree(qm_info->qm_port_params); 120fe56b9e6SYuval Mintz qm_info->qm_port_params = NULL; 121bcd197c8SManish Chopra kfree(qm_info->wfq_data); 122bcd197c8SManish Chopra qm_info->wfq_data = NULL; 123fe56b9e6SYuval Mintz } 124fe56b9e6SYuval Mintz 125fe56b9e6SYuval Mintz void qed_resc_free(struct qed_dev *cdev) 126fe56b9e6SYuval Mintz { 127fe56b9e6SYuval Mintz int i; 128fe56b9e6SYuval Mintz 1291408cc1fSYuval Mintz if (IS_VF(cdev)) 1301408cc1fSYuval Mintz return; 1311408cc1fSYuval Mintz 132fe56b9e6SYuval Mintz kfree(cdev->fw_data); 133fe56b9e6SYuval Mintz cdev->fw_data = NULL; 134fe56b9e6SYuval Mintz 135fe56b9e6SYuval Mintz kfree(cdev->reset_stats); 136fe56b9e6SYuval Mintz 137fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 138fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 139fe56b9e6SYuval Mintz 14025c089d7SYuval Mintz kfree(p_hwfn->p_tx_cids); 14125c089d7SYuval Mintz p_hwfn->p_tx_cids = NULL; 14225c089d7SYuval Mintz kfree(p_hwfn->p_rx_cids); 14325c089d7SYuval Mintz p_hwfn->p_rx_cids = NULL; 14425c089d7SYuval Mintz } 14525c089d7SYuval Mintz 14625c089d7SYuval Mintz for_each_hwfn(cdev, i) { 14725c089d7SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 14825c089d7SYuval Mintz 149fe56b9e6SYuval Mintz qed_cxt_mngr_free(p_hwfn); 150fe56b9e6SYuval Mintz qed_qm_info_free(p_hwfn); 151fe56b9e6SYuval Mintz qed_spq_free(p_hwfn); 152fe56b9e6SYuval Mintz qed_eq_free(p_hwfn, p_hwfn->p_eq); 153fe56b9e6SYuval Mintz qed_consq_free(p_hwfn, p_hwfn->p_consq); 154fe56b9e6SYuval Mintz qed_int_free(p_hwfn); 1550a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 1560a7fb11cSYuval Mintz qed_ll2_free(p_hwfn, p_hwfn->p_ll2_info); 1570a7fb11cSYuval Mintz #endif 15832a47e72SYuval Mintz qed_iov_free(p_hwfn); 159fe56b9e6SYuval Mintz qed_dmae_info_free(p_hwfn); 16039651abdSSudarsana Reddy Kalluru qed_dcbx_info_free(p_hwfn, p_hwfn->p_dcbx_info); 161fe56b9e6SYuval Mintz } 162fe56b9e6SYuval Mintz } 163fe56b9e6SYuval Mintz 16479529291SSudarsana Reddy Kalluru static int qed_init_qm_info(struct qed_hwfn *p_hwfn, bool b_sleepable) 165fe56b9e6SYuval Mintz { 1661408cc1fSYuval Mintz u8 num_vports, vf_offset = 0, i, vport_id, num_ports, curr_queue = 0; 167fe56b9e6SYuval Mintz struct qed_qm_info *qm_info = &p_hwfn->qm_info; 168fe56b9e6SYuval Mintz struct init_qm_port_params *p_qm_port; 169dbb799c3SYuval Mintz bool init_rdma_offload_pq = false; 170dbb799c3SYuval Mintz bool init_pure_ack_pq = false; 171dbb799c3SYuval Mintz bool init_ooo_pq = false; 172fe56b9e6SYuval Mintz u16 num_pqs, multi_cos_tcs = 1; 173cc3d5eb0SYuval Mintz u8 pf_wfq = qm_info->pf_wfq; 174cc3d5eb0SYuval Mintz u32 pf_rl = qm_info->pf_rl; 175dbb799c3SYuval Mintz u16 num_pf_rls = 0; 1761408cc1fSYuval Mintz u16 num_vfs = 0; 177fe56b9e6SYuval Mintz 1781408cc1fSYuval Mintz #ifdef CONFIG_QED_SRIOV 1791408cc1fSYuval Mintz if (p_hwfn->cdev->p_iov_info) 1801408cc1fSYuval Mintz num_vfs = p_hwfn->cdev->p_iov_info->total_vfs; 1811408cc1fSYuval Mintz #endif 182fe56b9e6SYuval Mintz memset(qm_info, 0, sizeof(*qm_info)); 183fe56b9e6SYuval Mintz 1841408cc1fSYuval Mintz num_pqs = multi_cos_tcs + num_vfs + 1; /* The '1' is for pure-LB */ 185fe56b9e6SYuval Mintz num_vports = (u8)RESC_NUM(p_hwfn, QED_VPORT); 186fe56b9e6SYuval Mintz 187dbb799c3SYuval Mintz if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) { 188dbb799c3SYuval Mintz num_pqs++; /* for RoCE queue */ 189dbb799c3SYuval Mintz init_rdma_offload_pq = true; 190dbb799c3SYuval Mintz /* we subtract num_vfs because each require a rate limiter, 191dbb799c3SYuval Mintz * and one default rate limiter 192dbb799c3SYuval Mintz */ 193dbb799c3SYuval Mintz if (p_hwfn->pf_params.rdma_pf_params.enable_dcqcn) 194dbb799c3SYuval Mintz num_pf_rls = RESC_NUM(p_hwfn, QED_RL) - num_vfs - 1; 195dbb799c3SYuval Mintz 196dbb799c3SYuval Mintz num_pqs += num_pf_rls; 197dbb799c3SYuval Mintz qm_info->num_pf_rls = (u8) num_pf_rls; 198dbb799c3SYuval Mintz } 199dbb799c3SYuval Mintz 200dbb799c3SYuval Mintz if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 201dbb799c3SYuval Mintz num_pqs += 2; /* for iSCSI pure-ACK / OOO queue */ 202dbb799c3SYuval Mintz init_pure_ack_pq = true; 203dbb799c3SYuval Mintz init_ooo_pq = true; 204dbb799c3SYuval Mintz } 205dbb799c3SYuval Mintz 206fe56b9e6SYuval Mintz /* Sanity checking that setup requires legal number of resources */ 207fe56b9e6SYuval Mintz if (num_pqs > RESC_NUM(p_hwfn, QED_PQ)) { 208fe56b9e6SYuval Mintz DP_ERR(p_hwfn, 209fe56b9e6SYuval Mintz "Need too many Physical queues - 0x%04x when only %04x are available\n", 210fe56b9e6SYuval Mintz num_pqs, RESC_NUM(p_hwfn, QED_PQ)); 211fe56b9e6SYuval Mintz return -EINVAL; 212fe56b9e6SYuval Mintz } 213fe56b9e6SYuval Mintz 214fe56b9e6SYuval Mintz /* PQs will be arranged as follows: First per-TC PQ then pure-LB quete. 215fe56b9e6SYuval Mintz */ 21679529291SSudarsana Reddy Kalluru qm_info->qm_pq_params = kcalloc(num_pqs, 21779529291SSudarsana Reddy Kalluru sizeof(struct init_qm_pq_params), 21879529291SSudarsana Reddy Kalluru b_sleepable ? GFP_KERNEL : GFP_ATOMIC); 219fe56b9e6SYuval Mintz if (!qm_info->qm_pq_params) 220fe56b9e6SYuval Mintz goto alloc_err; 221fe56b9e6SYuval Mintz 22279529291SSudarsana Reddy Kalluru qm_info->qm_vport_params = kcalloc(num_vports, 22379529291SSudarsana Reddy Kalluru sizeof(struct init_qm_vport_params), 22479529291SSudarsana Reddy Kalluru b_sleepable ? GFP_KERNEL 22579529291SSudarsana Reddy Kalluru : GFP_ATOMIC); 226fe56b9e6SYuval Mintz if (!qm_info->qm_vport_params) 227fe56b9e6SYuval Mintz goto alloc_err; 228fe56b9e6SYuval Mintz 22979529291SSudarsana Reddy Kalluru qm_info->qm_port_params = kcalloc(MAX_NUM_PORTS, 23079529291SSudarsana Reddy Kalluru sizeof(struct init_qm_port_params), 23179529291SSudarsana Reddy Kalluru b_sleepable ? GFP_KERNEL 23279529291SSudarsana Reddy Kalluru : GFP_ATOMIC); 233fe56b9e6SYuval Mintz if (!qm_info->qm_port_params) 234fe56b9e6SYuval Mintz goto alloc_err; 235fe56b9e6SYuval Mintz 23679529291SSudarsana Reddy Kalluru qm_info->wfq_data = kcalloc(num_vports, sizeof(struct qed_wfq_data), 23779529291SSudarsana Reddy Kalluru b_sleepable ? GFP_KERNEL : GFP_ATOMIC); 238bcd197c8SManish Chopra if (!qm_info->wfq_data) 239bcd197c8SManish Chopra goto alloc_err; 240bcd197c8SManish Chopra 241fe56b9e6SYuval Mintz vport_id = (u8)RESC_START(p_hwfn, QED_VPORT); 242fe56b9e6SYuval Mintz 243dbb799c3SYuval Mintz /* First init rate limited queues */ 244dbb799c3SYuval Mintz for (curr_queue = 0; curr_queue < num_pf_rls; curr_queue++) { 245dbb799c3SYuval Mintz qm_info->qm_pq_params[curr_queue].vport_id = vport_id++; 246dbb799c3SYuval Mintz qm_info->qm_pq_params[curr_queue].tc_id = 247dbb799c3SYuval Mintz p_hwfn->hw_info.non_offload_tc; 248dbb799c3SYuval Mintz qm_info->qm_pq_params[curr_queue].wrr_group = 1; 249dbb799c3SYuval Mintz qm_info->qm_pq_params[curr_queue].rl_valid = 1; 250dbb799c3SYuval Mintz } 251dbb799c3SYuval Mintz 252fe56b9e6SYuval Mintz /* First init per-TC PQs */ 25339651abdSSudarsana Reddy Kalluru for (i = 0; i < multi_cos_tcs; i++) { 2541408cc1fSYuval Mintz struct init_qm_pq_params *params = 25539651abdSSudarsana Reddy Kalluru &qm_info->qm_pq_params[curr_queue++]; 256fe56b9e6SYuval Mintz 257dbb799c3SYuval Mintz if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE || 258dbb799c3SYuval Mintz p_hwfn->hw_info.personality == QED_PCI_ETH) { 259fe56b9e6SYuval Mintz params->vport_id = vport_id; 260fe56b9e6SYuval Mintz params->tc_id = p_hwfn->hw_info.non_offload_tc; 261fe56b9e6SYuval Mintz params->wrr_group = 1; 26239651abdSSudarsana Reddy Kalluru } else { 26339651abdSSudarsana Reddy Kalluru params->vport_id = vport_id; 26439651abdSSudarsana Reddy Kalluru params->tc_id = p_hwfn->hw_info.offload_tc; 26539651abdSSudarsana Reddy Kalluru params->wrr_group = 1; 26639651abdSSudarsana Reddy Kalluru } 267fe56b9e6SYuval Mintz } 268fe56b9e6SYuval Mintz 269fe56b9e6SYuval Mintz /* Then init pure-LB PQ */ 2701408cc1fSYuval Mintz qm_info->pure_lb_pq = curr_queue; 2711408cc1fSYuval Mintz qm_info->qm_pq_params[curr_queue].vport_id = 2721408cc1fSYuval Mintz (u8) RESC_START(p_hwfn, QED_VPORT); 2731408cc1fSYuval Mintz qm_info->qm_pq_params[curr_queue].tc_id = PURE_LB_TC; 2741408cc1fSYuval Mintz qm_info->qm_pq_params[curr_queue].wrr_group = 1; 2751408cc1fSYuval Mintz curr_queue++; 276fe56b9e6SYuval Mintz 277fe56b9e6SYuval Mintz qm_info->offload_pq = 0; 278dbb799c3SYuval Mintz if (init_rdma_offload_pq) { 279dbb799c3SYuval Mintz qm_info->offload_pq = curr_queue; 280dbb799c3SYuval Mintz qm_info->qm_pq_params[curr_queue].vport_id = vport_id; 281dbb799c3SYuval Mintz qm_info->qm_pq_params[curr_queue].tc_id = 282dbb799c3SYuval Mintz p_hwfn->hw_info.offload_tc; 283dbb799c3SYuval Mintz qm_info->qm_pq_params[curr_queue].wrr_group = 1; 284dbb799c3SYuval Mintz curr_queue++; 285dbb799c3SYuval Mintz } 286dbb799c3SYuval Mintz 287dbb799c3SYuval Mintz if (init_pure_ack_pq) { 288dbb799c3SYuval Mintz qm_info->pure_ack_pq = curr_queue; 289dbb799c3SYuval Mintz qm_info->qm_pq_params[curr_queue].vport_id = vport_id; 290dbb799c3SYuval Mintz qm_info->qm_pq_params[curr_queue].tc_id = 291dbb799c3SYuval Mintz p_hwfn->hw_info.offload_tc; 292dbb799c3SYuval Mintz qm_info->qm_pq_params[curr_queue].wrr_group = 1; 293dbb799c3SYuval Mintz curr_queue++; 294dbb799c3SYuval Mintz } 295dbb799c3SYuval Mintz 296dbb799c3SYuval Mintz if (init_ooo_pq) { 297dbb799c3SYuval Mintz qm_info->ooo_pq = curr_queue; 298dbb799c3SYuval Mintz qm_info->qm_pq_params[curr_queue].vport_id = vport_id; 299dbb799c3SYuval Mintz qm_info->qm_pq_params[curr_queue].tc_id = DCBX_ISCSI_OOO_TC; 300dbb799c3SYuval Mintz qm_info->qm_pq_params[curr_queue].wrr_group = 1; 301dbb799c3SYuval Mintz curr_queue++; 302dbb799c3SYuval Mintz } 303dbb799c3SYuval Mintz 3041408cc1fSYuval Mintz /* Then init per-VF PQs */ 3051408cc1fSYuval Mintz vf_offset = curr_queue; 3061408cc1fSYuval Mintz for (i = 0; i < num_vfs; i++) { 3071408cc1fSYuval Mintz /* First vport is used by the PF */ 3081408cc1fSYuval Mintz qm_info->qm_pq_params[curr_queue].vport_id = vport_id + i + 1; 3091408cc1fSYuval Mintz qm_info->qm_pq_params[curr_queue].tc_id = 3101408cc1fSYuval Mintz p_hwfn->hw_info.non_offload_tc; 3111408cc1fSYuval Mintz qm_info->qm_pq_params[curr_queue].wrr_group = 1; 312351a4dedSYuval Mintz qm_info->qm_pq_params[curr_queue].rl_valid = 1; 3131408cc1fSYuval Mintz curr_queue++; 3141408cc1fSYuval Mintz } 3151408cc1fSYuval Mintz 3161408cc1fSYuval Mintz qm_info->vf_queues_offset = vf_offset; 317fe56b9e6SYuval Mintz qm_info->num_pqs = num_pqs; 318fe56b9e6SYuval Mintz qm_info->num_vports = num_vports; 319fe56b9e6SYuval Mintz 320fe56b9e6SYuval Mintz /* Initialize qm port parameters */ 321fe56b9e6SYuval Mintz num_ports = p_hwfn->cdev->num_ports_in_engines; 322fe56b9e6SYuval Mintz for (i = 0; i < num_ports; i++) { 323fe56b9e6SYuval Mintz p_qm_port = &qm_info->qm_port_params[i]; 324fe56b9e6SYuval Mintz p_qm_port->active = 1; 325351a4dedSYuval Mintz if (num_ports == 4) 326351a4dedSYuval Mintz p_qm_port->active_phys_tcs = 0x7; 327351a4dedSYuval Mintz else 328351a4dedSYuval Mintz p_qm_port->active_phys_tcs = 0x9f; 329fe56b9e6SYuval Mintz p_qm_port->num_pbf_cmd_lines = PBF_MAX_CMD_LINES / num_ports; 330fe56b9e6SYuval Mintz p_qm_port->num_btb_blocks = BTB_MAX_BLOCKS / num_ports; 331fe56b9e6SYuval Mintz } 332fe56b9e6SYuval Mintz 333fe56b9e6SYuval Mintz qm_info->max_phys_tcs_per_port = NUM_OF_PHYS_TCS; 334fe56b9e6SYuval Mintz 335fe56b9e6SYuval Mintz qm_info->start_pq = (u16)RESC_START(p_hwfn, QED_PQ); 336fe56b9e6SYuval Mintz 3371408cc1fSYuval Mintz qm_info->num_vf_pqs = num_vfs; 338fe56b9e6SYuval Mintz qm_info->start_vport = (u8) RESC_START(p_hwfn, QED_VPORT); 339fe56b9e6SYuval Mintz 340a64b02d5SManish Chopra for (i = 0; i < qm_info->num_vports; i++) 341a64b02d5SManish Chopra qm_info->qm_vport_params[i].vport_wfq = 1; 342a64b02d5SManish Chopra 343fe56b9e6SYuval Mintz qm_info->vport_rl_en = 1; 344a64b02d5SManish Chopra qm_info->vport_wfq_en = 1; 345cc3d5eb0SYuval Mintz qm_info->pf_rl = pf_rl; 346cc3d5eb0SYuval Mintz qm_info->pf_wfq = pf_wfq; 347fe56b9e6SYuval Mintz 348fe56b9e6SYuval Mintz return 0; 349fe56b9e6SYuval Mintz 350fe56b9e6SYuval Mintz alloc_err: 351bcd197c8SManish Chopra qed_qm_info_free(p_hwfn); 352fe56b9e6SYuval Mintz return -ENOMEM; 353fe56b9e6SYuval Mintz } 354fe56b9e6SYuval Mintz 35539651abdSSudarsana Reddy Kalluru /* This function reconfigures the QM pf on the fly. 35639651abdSSudarsana Reddy Kalluru * For this purpose we: 35739651abdSSudarsana Reddy Kalluru * 1. reconfigure the QM database 35839651abdSSudarsana Reddy Kalluru * 2. set new values to runtime arrat 35939651abdSSudarsana Reddy Kalluru * 3. send an sdm_qm_cmd through the rbc interface to stop the QM 36039651abdSSudarsana Reddy Kalluru * 4. activate init tool in QM_PF stage 36139651abdSSudarsana Reddy Kalluru * 5. send an sdm_qm_cmd through rbc interface to release the QM 36239651abdSSudarsana Reddy Kalluru */ 36339651abdSSudarsana Reddy Kalluru int qed_qm_reconf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 36439651abdSSudarsana Reddy Kalluru { 36539651abdSSudarsana Reddy Kalluru struct qed_qm_info *qm_info = &p_hwfn->qm_info; 36639651abdSSudarsana Reddy Kalluru bool b_rc; 36739651abdSSudarsana Reddy Kalluru int rc; 36839651abdSSudarsana Reddy Kalluru 36939651abdSSudarsana Reddy Kalluru /* qm_info is allocated in qed_init_qm_info() which is already called 37039651abdSSudarsana Reddy Kalluru * from qed_resc_alloc() or previous call of qed_qm_reconf(). 37139651abdSSudarsana Reddy Kalluru * The allocated size may change each init, so we free it before next 37239651abdSSudarsana Reddy Kalluru * allocation. 37339651abdSSudarsana Reddy Kalluru */ 37439651abdSSudarsana Reddy Kalluru qed_qm_info_free(p_hwfn); 37539651abdSSudarsana Reddy Kalluru 37639651abdSSudarsana Reddy Kalluru /* initialize qed's qm data structure */ 37779529291SSudarsana Reddy Kalluru rc = qed_init_qm_info(p_hwfn, false); 37839651abdSSudarsana Reddy Kalluru if (rc) 37939651abdSSudarsana Reddy Kalluru return rc; 38039651abdSSudarsana Reddy Kalluru 38139651abdSSudarsana Reddy Kalluru /* stop PF's qm queues */ 38239651abdSSudarsana Reddy Kalluru spin_lock_bh(&qm_lock); 38339651abdSSudarsana Reddy Kalluru b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, false, true, 38439651abdSSudarsana Reddy Kalluru qm_info->start_pq, qm_info->num_pqs); 38539651abdSSudarsana Reddy Kalluru spin_unlock_bh(&qm_lock); 38639651abdSSudarsana Reddy Kalluru if (!b_rc) 38739651abdSSudarsana Reddy Kalluru return -EINVAL; 38839651abdSSudarsana Reddy Kalluru 38939651abdSSudarsana Reddy Kalluru /* clear the QM_PF runtime phase leftovers from previous init */ 39039651abdSSudarsana Reddy Kalluru qed_init_clear_rt_data(p_hwfn); 39139651abdSSudarsana Reddy Kalluru 39239651abdSSudarsana Reddy Kalluru /* prepare QM portion of runtime array */ 39339651abdSSudarsana Reddy Kalluru qed_qm_init_pf(p_hwfn); 39439651abdSSudarsana Reddy Kalluru 39539651abdSSudarsana Reddy Kalluru /* activate init tool on runtime array */ 39639651abdSSudarsana Reddy Kalluru rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, p_hwfn->rel_pf_id, 39739651abdSSudarsana Reddy Kalluru p_hwfn->hw_info.hw_mode); 39839651abdSSudarsana Reddy Kalluru if (rc) 39939651abdSSudarsana Reddy Kalluru return rc; 40039651abdSSudarsana Reddy Kalluru 40139651abdSSudarsana Reddy Kalluru /* start PF's qm queues */ 40239651abdSSudarsana Reddy Kalluru spin_lock_bh(&qm_lock); 40339651abdSSudarsana Reddy Kalluru b_rc = qed_send_qm_stop_cmd(p_hwfn, p_ptt, true, true, 40439651abdSSudarsana Reddy Kalluru qm_info->start_pq, qm_info->num_pqs); 40539651abdSSudarsana Reddy Kalluru spin_unlock_bh(&qm_lock); 40639651abdSSudarsana Reddy Kalluru if (!b_rc) 40739651abdSSudarsana Reddy Kalluru return -EINVAL; 40839651abdSSudarsana Reddy Kalluru 40939651abdSSudarsana Reddy Kalluru return 0; 41039651abdSSudarsana Reddy Kalluru } 41139651abdSSudarsana Reddy Kalluru 412fe56b9e6SYuval Mintz int qed_resc_alloc(struct qed_dev *cdev) 413fe56b9e6SYuval Mintz { 4140a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 4150a7fb11cSYuval Mintz struct qed_ll2_info *p_ll2_info; 4160a7fb11cSYuval Mintz #endif 417fe56b9e6SYuval Mintz struct qed_consq *p_consq; 418fe56b9e6SYuval Mintz struct qed_eq *p_eq; 419fe56b9e6SYuval Mintz int i, rc = 0; 420fe56b9e6SYuval Mintz 4211408cc1fSYuval Mintz if (IS_VF(cdev)) 4221408cc1fSYuval Mintz return rc; 4231408cc1fSYuval Mintz 424fe56b9e6SYuval Mintz cdev->fw_data = kzalloc(sizeof(*cdev->fw_data), GFP_KERNEL); 425fe56b9e6SYuval Mintz if (!cdev->fw_data) 426fe56b9e6SYuval Mintz return -ENOMEM; 427fe56b9e6SYuval Mintz 42825c089d7SYuval Mintz /* Allocate Memory for the Queue->CID mapping */ 42925c089d7SYuval Mintz for_each_hwfn(cdev, i) { 43025c089d7SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 43125c089d7SYuval Mintz int tx_size = sizeof(struct qed_hw_cid_data) * 43225c089d7SYuval Mintz RESC_NUM(p_hwfn, QED_L2_QUEUE); 43325c089d7SYuval Mintz int rx_size = sizeof(struct qed_hw_cid_data) * 43425c089d7SYuval Mintz RESC_NUM(p_hwfn, QED_L2_QUEUE); 43525c089d7SYuval Mintz 43625c089d7SYuval Mintz p_hwfn->p_tx_cids = kzalloc(tx_size, GFP_KERNEL); 4372591c280SJoe Perches if (!p_hwfn->p_tx_cids) 438dbb799c3SYuval Mintz goto alloc_no_mem; 43925c089d7SYuval Mintz 44025c089d7SYuval Mintz p_hwfn->p_rx_cids = kzalloc(rx_size, GFP_KERNEL); 4412591c280SJoe Perches if (!p_hwfn->p_rx_cids) 442dbb799c3SYuval Mintz goto alloc_no_mem; 44325c089d7SYuval Mintz } 44425c089d7SYuval Mintz 445fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 446fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 447dbb799c3SYuval Mintz u32 n_eqes, num_cons; 448fe56b9e6SYuval Mintz 449fe56b9e6SYuval Mintz /* First allocate the context manager structure */ 450fe56b9e6SYuval Mintz rc = qed_cxt_mngr_alloc(p_hwfn); 451fe56b9e6SYuval Mintz if (rc) 452fe56b9e6SYuval Mintz goto alloc_err; 453fe56b9e6SYuval Mintz 454fe56b9e6SYuval Mintz /* Set the HW cid/tid numbers (in the contest manager) 455fe56b9e6SYuval Mintz * Must be done prior to any further computations. 456fe56b9e6SYuval Mintz */ 457fe56b9e6SYuval Mintz rc = qed_cxt_set_pf_params(p_hwfn); 458fe56b9e6SYuval Mintz if (rc) 459fe56b9e6SYuval Mintz goto alloc_err; 460fe56b9e6SYuval Mintz 461fe56b9e6SYuval Mintz /* Prepare and process QM requirements */ 46279529291SSudarsana Reddy Kalluru rc = qed_init_qm_info(p_hwfn, true); 463fe56b9e6SYuval Mintz if (rc) 464fe56b9e6SYuval Mintz goto alloc_err; 465fe56b9e6SYuval Mintz 466fe56b9e6SYuval Mintz /* Compute the ILT client partition */ 467fe56b9e6SYuval Mintz rc = qed_cxt_cfg_ilt_compute(p_hwfn); 468fe56b9e6SYuval Mintz if (rc) 469fe56b9e6SYuval Mintz goto alloc_err; 470fe56b9e6SYuval Mintz 471fe56b9e6SYuval Mintz /* CID map / ILT shadow table / T2 472fe56b9e6SYuval Mintz * The talbes sizes are determined by the computations above 473fe56b9e6SYuval Mintz */ 474fe56b9e6SYuval Mintz rc = qed_cxt_tables_alloc(p_hwfn); 475fe56b9e6SYuval Mintz if (rc) 476fe56b9e6SYuval Mintz goto alloc_err; 477fe56b9e6SYuval Mintz 478fe56b9e6SYuval Mintz /* SPQ, must follow ILT because initializes SPQ context */ 479fe56b9e6SYuval Mintz rc = qed_spq_alloc(p_hwfn); 480fe56b9e6SYuval Mintz if (rc) 481fe56b9e6SYuval Mintz goto alloc_err; 482fe56b9e6SYuval Mintz 483fe56b9e6SYuval Mintz /* SP status block allocation */ 484fe56b9e6SYuval Mintz p_hwfn->p_dpc_ptt = qed_get_reserved_ptt(p_hwfn, 485fe56b9e6SYuval Mintz RESERVED_PTT_DPC); 486fe56b9e6SYuval Mintz 487fe56b9e6SYuval Mintz rc = qed_int_alloc(p_hwfn, p_hwfn->p_main_ptt); 488fe56b9e6SYuval Mintz if (rc) 489fe56b9e6SYuval Mintz goto alloc_err; 490fe56b9e6SYuval Mintz 49132a47e72SYuval Mintz rc = qed_iov_alloc(p_hwfn); 49232a47e72SYuval Mintz if (rc) 49332a47e72SYuval Mintz goto alloc_err; 49432a47e72SYuval Mintz 495fe56b9e6SYuval Mintz /* EQ */ 496dbb799c3SYuval Mintz n_eqes = qed_chain_get_capacity(&p_hwfn->p_spq->chain); 497dbb799c3SYuval Mintz if (p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) { 498dbb799c3SYuval Mintz num_cons = qed_cxt_get_proto_cid_count(p_hwfn, 499dbb799c3SYuval Mintz PROTOCOLID_ROCE, 5008c93beafSYuval Mintz NULL) * 2; 501dbb799c3SYuval Mintz n_eqes += num_cons + 2 * MAX_NUM_VFS_BB; 502dbb799c3SYuval Mintz } else if (p_hwfn->hw_info.personality == QED_PCI_ISCSI) { 503dbb799c3SYuval Mintz num_cons = 504dbb799c3SYuval Mintz qed_cxt_get_proto_cid_count(p_hwfn, 5058c93beafSYuval Mintz PROTOCOLID_ISCSI, 5068c93beafSYuval Mintz NULL); 507dbb799c3SYuval Mintz n_eqes += 2 * num_cons; 508dbb799c3SYuval Mintz } 509dbb799c3SYuval Mintz 510dbb799c3SYuval Mintz if (n_eqes > 0xFFFF) { 511dbb799c3SYuval Mintz DP_ERR(p_hwfn, 512dbb799c3SYuval Mintz "Cannot allocate 0x%x EQ elements. The maximum of a u16 chain is 0x%x\n", 513dbb799c3SYuval Mintz n_eqes, 0xFFFF); 5141b4985b5SWei Yongjun rc = -EINVAL; 515fe56b9e6SYuval Mintz goto alloc_err; 5169b15acbfSDan Carpenter } 517dbb799c3SYuval Mintz 518dbb799c3SYuval Mintz p_eq = qed_eq_alloc(p_hwfn, (u16) n_eqes); 519dbb799c3SYuval Mintz if (!p_eq) 520dbb799c3SYuval Mintz goto alloc_no_mem; 521fe56b9e6SYuval Mintz p_hwfn->p_eq = p_eq; 522fe56b9e6SYuval Mintz 523fe56b9e6SYuval Mintz p_consq = qed_consq_alloc(p_hwfn); 524dbb799c3SYuval Mintz if (!p_consq) 525dbb799c3SYuval Mintz goto alloc_no_mem; 526fe56b9e6SYuval Mintz p_hwfn->p_consq = p_consq; 527fe56b9e6SYuval Mintz 5280a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 5290a7fb11cSYuval Mintz if (p_hwfn->using_ll2) { 5300a7fb11cSYuval Mintz p_ll2_info = qed_ll2_alloc(p_hwfn); 5310a7fb11cSYuval Mintz if (!p_ll2_info) 5320a7fb11cSYuval Mintz goto alloc_no_mem; 5330a7fb11cSYuval Mintz p_hwfn->p_ll2_info = p_ll2_info; 5340a7fb11cSYuval Mintz } 5350a7fb11cSYuval Mintz #endif 5360a7fb11cSYuval Mintz 537fe56b9e6SYuval Mintz /* DMA info initialization */ 538fe56b9e6SYuval Mintz rc = qed_dmae_info_alloc(p_hwfn); 5392591c280SJoe Perches if (rc) 540fe56b9e6SYuval Mintz goto alloc_err; 54139651abdSSudarsana Reddy Kalluru 54239651abdSSudarsana Reddy Kalluru /* DCBX initialization */ 54339651abdSSudarsana Reddy Kalluru rc = qed_dcbx_info_alloc(p_hwfn); 5442591c280SJoe Perches if (rc) 54539651abdSSudarsana Reddy Kalluru goto alloc_err; 54639651abdSSudarsana Reddy Kalluru } 547fe56b9e6SYuval Mintz 548fe56b9e6SYuval Mintz cdev->reset_stats = kzalloc(sizeof(*cdev->reset_stats), GFP_KERNEL); 5492591c280SJoe Perches if (!cdev->reset_stats) 55083aeb933SYuval Mintz goto alloc_no_mem; 551fe56b9e6SYuval Mintz 552fe56b9e6SYuval Mintz return 0; 553fe56b9e6SYuval Mintz 554dbb799c3SYuval Mintz alloc_no_mem: 555dbb799c3SYuval Mintz rc = -ENOMEM; 556fe56b9e6SYuval Mintz alloc_err: 557fe56b9e6SYuval Mintz qed_resc_free(cdev); 558fe56b9e6SYuval Mintz return rc; 559fe56b9e6SYuval Mintz } 560fe56b9e6SYuval Mintz 561fe56b9e6SYuval Mintz void qed_resc_setup(struct qed_dev *cdev) 562fe56b9e6SYuval Mintz { 563fe56b9e6SYuval Mintz int i; 564fe56b9e6SYuval Mintz 5651408cc1fSYuval Mintz if (IS_VF(cdev)) 5661408cc1fSYuval Mintz return; 5671408cc1fSYuval Mintz 568fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 569fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 570fe56b9e6SYuval Mintz 571fe56b9e6SYuval Mintz qed_cxt_mngr_setup(p_hwfn); 572fe56b9e6SYuval Mintz qed_spq_setup(p_hwfn); 573fe56b9e6SYuval Mintz qed_eq_setup(p_hwfn, p_hwfn->p_eq); 574fe56b9e6SYuval Mintz qed_consq_setup(p_hwfn, p_hwfn->p_consq); 575fe56b9e6SYuval Mintz 576fe56b9e6SYuval Mintz /* Read shadow of current MFW mailbox */ 577fe56b9e6SYuval Mintz qed_mcp_read_mb(p_hwfn, p_hwfn->p_main_ptt); 578fe56b9e6SYuval Mintz memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 579fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_cur, 580fe56b9e6SYuval Mintz p_hwfn->mcp_info->mfw_mb_length); 581fe56b9e6SYuval Mintz 582fe56b9e6SYuval Mintz qed_int_setup(p_hwfn, p_hwfn->p_main_ptt); 58332a47e72SYuval Mintz 58432a47e72SYuval Mintz qed_iov_setup(p_hwfn, p_hwfn->p_main_ptt); 5850a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 5860a7fb11cSYuval Mintz if (p_hwfn->using_ll2) 5870a7fb11cSYuval Mintz qed_ll2_setup(p_hwfn, p_hwfn->p_ll2_info); 5880a7fb11cSYuval Mintz #endif 589fe56b9e6SYuval Mintz } 590fe56b9e6SYuval Mintz } 591fe56b9e6SYuval Mintz 592fe56b9e6SYuval Mintz #define FINAL_CLEANUP_POLL_CNT (100) 593fe56b9e6SYuval Mintz #define FINAL_CLEANUP_POLL_TIME (10) 594fe56b9e6SYuval Mintz int qed_final_cleanup(struct qed_hwfn *p_hwfn, 5950b55e27dSYuval Mintz struct qed_ptt *p_ptt, u16 id, bool is_vf) 596fe56b9e6SYuval Mintz { 597fe56b9e6SYuval Mintz u32 command = 0, addr, count = FINAL_CLEANUP_POLL_CNT; 598fe56b9e6SYuval Mintz int rc = -EBUSY; 599fe56b9e6SYuval Mintz 600fc48b7a6SYuval Mintz addr = GTT_BAR0_MAP_REG_USDM_RAM + 601fc48b7a6SYuval Mintz USTORM_FLR_FINAL_ACK_OFFSET(p_hwfn->rel_pf_id); 602fe56b9e6SYuval Mintz 6030b55e27dSYuval Mintz if (is_vf) 6040b55e27dSYuval Mintz id += 0x10; 6050b55e27dSYuval Mintz 606fc48b7a6SYuval Mintz command |= X_FINAL_CLEANUP_AGG_INT << 607fc48b7a6SYuval Mintz SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT; 608fc48b7a6SYuval Mintz command |= 1 << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT; 609fc48b7a6SYuval Mintz command |= id << SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT; 610fc48b7a6SYuval Mintz command |= SDM_COMP_TYPE_AGG_INT << SDM_OP_GEN_COMP_TYPE_SHIFT; 611fe56b9e6SYuval Mintz 612fe56b9e6SYuval Mintz /* Make sure notification is not set before initiating final cleanup */ 613fe56b9e6SYuval Mintz if (REG_RD(p_hwfn, addr)) { 6141a635e48SYuval Mintz DP_NOTICE(p_hwfn, 615fe56b9e6SYuval Mintz "Unexpected; Found final cleanup notification before initiating final cleanup\n"); 616fe56b9e6SYuval Mintz REG_WR(p_hwfn, addr, 0); 617fe56b9e6SYuval Mintz } 618fe56b9e6SYuval Mintz 619fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_IOV, 620fe56b9e6SYuval Mintz "Sending final cleanup for PFVF[%d] [Command %08x\n]", 621fe56b9e6SYuval Mintz id, command); 622fe56b9e6SYuval Mintz 623fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, XSDM_REG_OPERATION_GEN, command); 624fe56b9e6SYuval Mintz 625fe56b9e6SYuval Mintz /* Poll until completion */ 626fe56b9e6SYuval Mintz while (!REG_RD(p_hwfn, addr) && count--) 627fe56b9e6SYuval Mintz msleep(FINAL_CLEANUP_POLL_TIME); 628fe56b9e6SYuval Mintz 629fe56b9e6SYuval Mintz if (REG_RD(p_hwfn, addr)) 630fe56b9e6SYuval Mintz rc = 0; 631fe56b9e6SYuval Mintz else 632fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 633fe56b9e6SYuval Mintz "Failed to receive FW final cleanup notification\n"); 634fe56b9e6SYuval Mintz 635fe56b9e6SYuval Mintz /* Cleanup afterwards */ 636fe56b9e6SYuval Mintz REG_WR(p_hwfn, addr, 0); 637fe56b9e6SYuval Mintz 638fe56b9e6SYuval Mintz return rc; 639fe56b9e6SYuval Mintz } 640fe56b9e6SYuval Mintz 641fe56b9e6SYuval Mintz static void qed_calc_hw_mode(struct qed_hwfn *p_hwfn) 642fe56b9e6SYuval Mintz { 643fe56b9e6SYuval Mintz int hw_mode = 0; 644fe56b9e6SYuval Mintz 64512e09c69SYuval Mintz hw_mode = (1 << MODE_BB_B0); 646fe56b9e6SYuval Mintz 647fe56b9e6SYuval Mintz switch (p_hwfn->cdev->num_ports_in_engines) { 648fe56b9e6SYuval Mintz case 1: 649fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_PORTS_PER_ENG_1; 650fe56b9e6SYuval Mintz break; 651fe56b9e6SYuval Mintz case 2: 652fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_PORTS_PER_ENG_2; 653fe56b9e6SYuval Mintz break; 654fe56b9e6SYuval Mintz case 4: 655fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_PORTS_PER_ENG_4; 656fe56b9e6SYuval Mintz break; 657fe56b9e6SYuval Mintz default: 658fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "num_ports_in_engine = %d not supported\n", 659fe56b9e6SYuval Mintz p_hwfn->cdev->num_ports_in_engines); 660fe56b9e6SYuval Mintz return; 661fe56b9e6SYuval Mintz } 662fe56b9e6SYuval Mintz 663fe56b9e6SYuval Mintz switch (p_hwfn->cdev->mf_mode) { 664fc48b7a6SYuval Mintz case QED_MF_DEFAULT: 665fc48b7a6SYuval Mintz case QED_MF_NPAR: 666fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_MF_SI; 667fe56b9e6SYuval Mintz break; 668fc48b7a6SYuval Mintz case QED_MF_OVLAN: 669fc48b7a6SYuval Mintz hw_mode |= 1 << MODE_MF_SD; 670fc48b7a6SYuval Mintz break; 671fe56b9e6SYuval Mintz default: 672fc48b7a6SYuval Mintz DP_NOTICE(p_hwfn, "Unsupported MF mode, init as DEFAULT\n"); 673fc48b7a6SYuval Mintz hw_mode |= 1 << MODE_MF_SI; 674fe56b9e6SYuval Mintz } 675fe56b9e6SYuval Mintz 676fe56b9e6SYuval Mintz hw_mode |= 1 << MODE_ASIC; 677fe56b9e6SYuval Mintz 6781af9dcf7SYuval Mintz if (p_hwfn->cdev->num_hwfns > 1) 6791af9dcf7SYuval Mintz hw_mode |= 1 << MODE_100G; 6801af9dcf7SYuval Mintz 681fe56b9e6SYuval Mintz p_hwfn->hw_info.hw_mode = hw_mode; 6821af9dcf7SYuval Mintz 6831af9dcf7SYuval Mintz DP_VERBOSE(p_hwfn, (NETIF_MSG_PROBE | NETIF_MSG_IFUP), 6841af9dcf7SYuval Mintz "Configuring function for hw_mode: 0x%08x\n", 6851af9dcf7SYuval Mintz p_hwfn->hw_info.hw_mode); 686fe56b9e6SYuval Mintz } 687fe56b9e6SYuval Mintz 688fe56b9e6SYuval Mintz /* Init run time data for all PFs on an engine. */ 689fe56b9e6SYuval Mintz static void qed_init_cau_rt_data(struct qed_dev *cdev) 690fe56b9e6SYuval Mintz { 691fe56b9e6SYuval Mintz u32 offset = CAU_REG_SB_VAR_MEMORY_RT_OFFSET; 692fe56b9e6SYuval Mintz int i, sb_id; 693fe56b9e6SYuval Mintz 694fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 695fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 696fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 697fe56b9e6SYuval Mintz struct qed_igu_block *p_block; 698fe56b9e6SYuval Mintz struct cau_sb_entry sb_entry; 699fe56b9e6SYuval Mintz 700fe56b9e6SYuval Mintz p_igu_info = p_hwfn->hw_info.p_igu_info; 701fe56b9e6SYuval Mintz 702fe56b9e6SYuval Mintz for (sb_id = 0; sb_id < QED_MAPPING_MEMORY_SIZE(cdev); 703fe56b9e6SYuval Mintz sb_id++) { 704fe56b9e6SYuval Mintz p_block = &p_igu_info->igu_map.igu_blocks[sb_id]; 705fe56b9e6SYuval Mintz if (!p_block->is_pf) 706fe56b9e6SYuval Mintz continue; 707fe56b9e6SYuval Mintz 708fe56b9e6SYuval Mintz qed_init_cau_sb_entry(p_hwfn, &sb_entry, 7091a635e48SYuval Mintz p_block->function_id, 0, 0); 7101a635e48SYuval Mintz STORE_RT_REG_AGG(p_hwfn, offset + sb_id * 2, sb_entry); 711fe56b9e6SYuval Mintz } 712fe56b9e6SYuval Mintz } 713fe56b9e6SYuval Mintz } 714fe56b9e6SYuval Mintz 715fe56b9e6SYuval Mintz static int qed_hw_init_common(struct qed_hwfn *p_hwfn, 7161a635e48SYuval Mintz struct qed_ptt *p_ptt, int hw_mode) 717fe56b9e6SYuval Mintz { 718fe56b9e6SYuval Mintz struct qed_qm_info *qm_info = &p_hwfn->qm_info; 719fe56b9e6SYuval Mintz struct qed_qm_common_rt_init_params params; 720fe56b9e6SYuval Mintz struct qed_dev *cdev = p_hwfn->cdev; 721dbb799c3SYuval Mintz u16 num_pfs, pf_id; 7221408cc1fSYuval Mintz u32 concrete_fid; 723fe56b9e6SYuval Mintz int rc = 0; 7241408cc1fSYuval Mintz u8 vf_id; 725fe56b9e6SYuval Mintz 726fe56b9e6SYuval Mintz qed_init_cau_rt_data(cdev); 727fe56b9e6SYuval Mintz 728fe56b9e6SYuval Mintz /* Program GTT windows */ 729fe56b9e6SYuval Mintz qed_gtt_init(p_hwfn); 730fe56b9e6SYuval Mintz 731fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 732fe56b9e6SYuval Mintz if (p_hwfn->mcp_info->func_info.bandwidth_max) 733fe56b9e6SYuval Mintz qm_info->pf_rl_en = 1; 734fe56b9e6SYuval Mintz if (p_hwfn->mcp_info->func_info.bandwidth_min) 735fe56b9e6SYuval Mintz qm_info->pf_wfq_en = 1; 736fe56b9e6SYuval Mintz } 737fe56b9e6SYuval Mintz 738fe56b9e6SYuval Mintz memset(¶ms, 0, sizeof(params)); 739fe56b9e6SYuval Mintz params.max_ports_per_engine = p_hwfn->cdev->num_ports_in_engines; 740fe56b9e6SYuval Mintz params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port; 741fe56b9e6SYuval Mintz params.pf_rl_en = qm_info->pf_rl_en; 742fe56b9e6SYuval Mintz params.pf_wfq_en = qm_info->pf_wfq_en; 743fe56b9e6SYuval Mintz params.vport_rl_en = qm_info->vport_rl_en; 744fe56b9e6SYuval Mintz params.vport_wfq_en = qm_info->vport_wfq_en; 745fe56b9e6SYuval Mintz params.port_params = qm_info->qm_port_params; 746fe56b9e6SYuval Mintz 747fe56b9e6SYuval Mintz qed_qm_common_rt_init(p_hwfn, ¶ms); 748fe56b9e6SYuval Mintz 749fe56b9e6SYuval Mintz qed_cxt_hw_init_common(p_hwfn); 750fe56b9e6SYuval Mintz 751fe56b9e6SYuval Mintz /* Close gate from NIG to BRB/Storm; By default they are open, but 752fe56b9e6SYuval Mintz * we close them to prevent NIG from passing data to reset blocks. 753fe56b9e6SYuval Mintz * Should have been done in the ENGINE phase, but init-tool lacks 754fe56b9e6SYuval Mintz * proper port-pretend capabilities. 755fe56b9e6SYuval Mintz */ 756fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0); 757fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0); 758fe56b9e6SYuval Mintz qed_port_pretend(p_hwfn, p_ptt, p_hwfn->port_id ^ 1); 759fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, NIG_REG_RX_BRB_OUT_EN, 0); 760fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, NIG_REG_STORM_OUT_EN, 0); 761fe56b9e6SYuval Mintz qed_port_unpretend(p_hwfn, p_ptt); 762fe56b9e6SYuval Mintz 763fe56b9e6SYuval Mintz rc = qed_init_run(p_hwfn, p_ptt, PHASE_ENGINE, ANY_PHASE_ID, hw_mode); 7641a635e48SYuval Mintz if (rc) 765fe56b9e6SYuval Mintz return rc; 766fe56b9e6SYuval Mintz 767fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PSWRQ2_REG_L2P_VALIDATE_VFID, 0); 768fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PGLUE_B_REG_USE_CLIENTID_IN_TAG, 1); 769fe56b9e6SYuval Mintz 770dbb799c3SYuval Mintz if (QED_IS_BB(p_hwfn->cdev)) { 771dbb799c3SYuval Mintz num_pfs = NUM_OF_ENG_PFS(p_hwfn->cdev); 772dbb799c3SYuval Mintz for (pf_id = 0; pf_id < num_pfs; pf_id++) { 773dbb799c3SYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, pf_id); 774dbb799c3SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 775dbb799c3SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 776dbb799c3SYuval Mintz } 777dbb799c3SYuval Mintz /* pretend to original PF */ 778dbb799c3SYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 779dbb799c3SYuval Mintz } 780fe56b9e6SYuval Mintz 7811408cc1fSYuval Mintz for (vf_id = 0; vf_id < MAX_NUM_VFS_BB; vf_id++) { 7821408cc1fSYuval Mintz concrete_fid = qed_vfid_to_concrete(p_hwfn, vf_id); 7831408cc1fSYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, (u16) concrete_fid); 7841408cc1fSYuval Mintz qed_wr(p_hwfn, p_ptt, CCFC_REG_STRONG_ENABLE_VF, 0x1); 78505fafbfbSYuval Mintz qed_wr(p_hwfn, p_ptt, CCFC_REG_WEAK_ENABLE_VF, 0x0); 78605fafbfbSYuval Mintz qed_wr(p_hwfn, p_ptt, TCFC_REG_STRONG_ENABLE_VF, 0x1); 78705fafbfbSYuval Mintz qed_wr(p_hwfn, p_ptt, TCFC_REG_WEAK_ENABLE_VF, 0x0); 7881408cc1fSYuval Mintz } 7891408cc1fSYuval Mintz /* pretend to original PF */ 7901408cc1fSYuval Mintz qed_fid_pretend(p_hwfn, p_ptt, p_hwfn->rel_pf_id); 7911408cc1fSYuval Mintz 792fe56b9e6SYuval Mintz return rc; 793fe56b9e6SYuval Mintz } 794fe56b9e6SYuval Mintz 79551ff1725SRam Amrani static int 79651ff1725SRam Amrani qed_hw_init_dpi_size(struct qed_hwfn *p_hwfn, 79751ff1725SRam Amrani struct qed_ptt *p_ptt, u32 pwm_region_size, u32 n_cpus) 79851ff1725SRam Amrani { 79951ff1725SRam Amrani u32 dpi_page_size_1, dpi_page_size_2, dpi_page_size; 80051ff1725SRam Amrani u32 dpi_bit_shift, dpi_count; 80151ff1725SRam Amrani u32 min_dpis; 80251ff1725SRam Amrani 80351ff1725SRam Amrani /* Calculate DPI size */ 80451ff1725SRam Amrani dpi_page_size_1 = QED_WID_SIZE * n_cpus; 80551ff1725SRam Amrani dpi_page_size_2 = max_t(u32, QED_WID_SIZE, PAGE_SIZE); 80651ff1725SRam Amrani dpi_page_size = max_t(u32, dpi_page_size_1, dpi_page_size_2); 80751ff1725SRam Amrani dpi_page_size = roundup_pow_of_two(dpi_page_size); 80851ff1725SRam Amrani dpi_bit_shift = ilog2(dpi_page_size / 4096); 80951ff1725SRam Amrani 81051ff1725SRam Amrani dpi_count = pwm_region_size / dpi_page_size; 81151ff1725SRam Amrani 81251ff1725SRam Amrani min_dpis = p_hwfn->pf_params.rdma_pf_params.min_dpis; 81351ff1725SRam Amrani min_dpis = max_t(u32, QED_MIN_DPIS, min_dpis); 81451ff1725SRam Amrani 81551ff1725SRam Amrani p_hwfn->dpi_size = dpi_page_size; 81651ff1725SRam Amrani p_hwfn->dpi_count = dpi_count; 81751ff1725SRam Amrani 81851ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_DPI_BIT_SHIFT, dpi_bit_shift); 81951ff1725SRam Amrani 82051ff1725SRam Amrani if (dpi_count < min_dpis) 82151ff1725SRam Amrani return -EINVAL; 82251ff1725SRam Amrani 82351ff1725SRam Amrani return 0; 82451ff1725SRam Amrani } 82551ff1725SRam Amrani 82651ff1725SRam Amrani enum QED_ROCE_EDPM_MODE { 82751ff1725SRam Amrani QED_ROCE_EDPM_MODE_ENABLE = 0, 82851ff1725SRam Amrani QED_ROCE_EDPM_MODE_FORCE_ON = 1, 82951ff1725SRam Amrani QED_ROCE_EDPM_MODE_DISABLE = 2, 83051ff1725SRam Amrani }; 83151ff1725SRam Amrani 83251ff1725SRam Amrani static int 83351ff1725SRam Amrani qed_hw_init_pf_doorbell_bar(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 83451ff1725SRam Amrani { 83551ff1725SRam Amrani u32 pwm_regsize, norm_regsize; 83651ff1725SRam Amrani u32 non_pwm_conn, min_addr_reg1; 83751ff1725SRam Amrani u32 db_bar_size, n_cpus; 83851ff1725SRam Amrani u32 roce_edpm_mode; 83951ff1725SRam Amrani u32 pf_dems_shift; 84051ff1725SRam Amrani int rc = 0; 84151ff1725SRam Amrani u8 cond; 84251ff1725SRam Amrani 84351ff1725SRam Amrani db_bar_size = qed_hw_bar_size(p_hwfn, BAR_ID_1); 84451ff1725SRam Amrani if (p_hwfn->cdev->num_hwfns > 1) 84551ff1725SRam Amrani db_bar_size /= 2; 84651ff1725SRam Amrani 84751ff1725SRam Amrani /* Calculate doorbell regions */ 84851ff1725SRam Amrani non_pwm_conn = qed_cxt_get_proto_cid_start(p_hwfn, PROTOCOLID_CORE) + 84951ff1725SRam Amrani qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_CORE, 85051ff1725SRam Amrani NULL) + 85151ff1725SRam Amrani qed_cxt_get_proto_cid_count(p_hwfn, PROTOCOLID_ETH, 85251ff1725SRam Amrani NULL); 85351ff1725SRam Amrani norm_regsize = roundup(QED_PF_DEMS_SIZE * non_pwm_conn, 4096); 85451ff1725SRam Amrani min_addr_reg1 = norm_regsize / 4096; 85551ff1725SRam Amrani pwm_regsize = db_bar_size - norm_regsize; 85651ff1725SRam Amrani 85751ff1725SRam Amrani /* Check that the normal and PWM sizes are valid */ 85851ff1725SRam Amrani if (db_bar_size < norm_regsize) { 85951ff1725SRam Amrani DP_ERR(p_hwfn->cdev, 86051ff1725SRam Amrani "Doorbell BAR size 0x%x is too small (normal region is 0x%0x )\n", 86151ff1725SRam Amrani db_bar_size, norm_regsize); 86251ff1725SRam Amrani return -EINVAL; 86351ff1725SRam Amrani } 86451ff1725SRam Amrani 86551ff1725SRam Amrani if (pwm_regsize < QED_MIN_PWM_REGION) { 86651ff1725SRam Amrani DP_ERR(p_hwfn->cdev, 86751ff1725SRam Amrani "PWM region size 0x%0x is too small. Should be at least 0x%0x (Doorbell BAR size is 0x%x and normal region size is 0x%0x)\n", 86851ff1725SRam Amrani pwm_regsize, 86951ff1725SRam Amrani QED_MIN_PWM_REGION, db_bar_size, norm_regsize); 87051ff1725SRam Amrani return -EINVAL; 87151ff1725SRam Amrani } 87251ff1725SRam Amrani 87351ff1725SRam Amrani /* Calculate number of DPIs */ 87451ff1725SRam Amrani roce_edpm_mode = p_hwfn->pf_params.rdma_pf_params.roce_edpm_mode; 87551ff1725SRam Amrani if ((roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE) || 87651ff1725SRam Amrani ((roce_edpm_mode == QED_ROCE_EDPM_MODE_FORCE_ON))) { 87751ff1725SRam Amrani /* Either EDPM is mandatory, or we are attempting to allocate a 87851ff1725SRam Amrani * WID per CPU. 87951ff1725SRam Amrani */ 88051ff1725SRam Amrani n_cpus = num_active_cpus(); 88151ff1725SRam Amrani rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 88251ff1725SRam Amrani } 88351ff1725SRam Amrani 88451ff1725SRam Amrani cond = (rc && (roce_edpm_mode == QED_ROCE_EDPM_MODE_ENABLE)) || 88551ff1725SRam Amrani (roce_edpm_mode == QED_ROCE_EDPM_MODE_DISABLE); 88651ff1725SRam Amrani if (cond || p_hwfn->dcbx_no_edpm) { 88751ff1725SRam Amrani /* Either EDPM is disabled from user configuration, or it is 88851ff1725SRam Amrani * disabled via DCBx, or it is not mandatory and we failed to 88951ff1725SRam Amrani * allocated a WID per CPU. 89051ff1725SRam Amrani */ 89151ff1725SRam Amrani n_cpus = 1; 89251ff1725SRam Amrani rc = qed_hw_init_dpi_size(p_hwfn, p_ptt, pwm_regsize, n_cpus); 89351ff1725SRam Amrani 89451ff1725SRam Amrani if (cond) 89551ff1725SRam Amrani qed_rdma_dpm_bar(p_hwfn, p_ptt); 89651ff1725SRam Amrani } 89751ff1725SRam Amrani 89851ff1725SRam Amrani DP_INFO(p_hwfn, 89951ff1725SRam Amrani "doorbell bar: normal_region_size=%d, pwm_region_size=%d, dpi_size=%d, dpi_count=%d, roce_edpm=%s\n", 90051ff1725SRam Amrani norm_regsize, 90151ff1725SRam Amrani pwm_regsize, 90251ff1725SRam Amrani p_hwfn->dpi_size, 90351ff1725SRam Amrani p_hwfn->dpi_count, 90451ff1725SRam Amrani ((p_hwfn->dcbx_no_edpm) || (p_hwfn->db_bar_no_edpm)) ? 90551ff1725SRam Amrani "disabled" : "enabled"); 90651ff1725SRam Amrani 90751ff1725SRam Amrani if (rc) { 90851ff1725SRam Amrani DP_ERR(p_hwfn, 90951ff1725SRam Amrani "Failed to allocate enough DPIs. Allocated %d but the current minimum is %d.\n", 91051ff1725SRam Amrani p_hwfn->dpi_count, 91151ff1725SRam Amrani p_hwfn->pf_params.rdma_pf_params.min_dpis); 91251ff1725SRam Amrani return -EINVAL; 91351ff1725SRam Amrani } 91451ff1725SRam Amrani 91551ff1725SRam Amrani p_hwfn->dpi_start_offset = norm_regsize; 91651ff1725SRam Amrani 91751ff1725SRam Amrani /* DEMS size is configured log2 of DWORDs, hence the division by 4 */ 91851ff1725SRam Amrani pf_dems_shift = ilog2(QED_PF_DEMS_SIZE / 4); 91951ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_ICID_BIT_SHIFT_NORM, pf_dems_shift); 92051ff1725SRam Amrani qed_wr(p_hwfn, p_ptt, DORQ_REG_PF_MIN_ADDR_REG1, min_addr_reg1); 92151ff1725SRam Amrani 92251ff1725SRam Amrani return 0; 92351ff1725SRam Amrani } 92451ff1725SRam Amrani 925fe56b9e6SYuval Mintz static int qed_hw_init_port(struct qed_hwfn *p_hwfn, 9261a635e48SYuval Mintz struct qed_ptt *p_ptt, int hw_mode) 927fe56b9e6SYuval Mintz { 92805fafbfbSYuval Mintz return qed_init_run(p_hwfn, p_ptt, PHASE_PORT, 92905fafbfbSYuval Mintz p_hwfn->port_id, hw_mode); 930fe56b9e6SYuval Mintz } 931fe56b9e6SYuval Mintz 932fe56b9e6SYuval Mintz static int qed_hw_init_pf(struct qed_hwfn *p_hwfn, 933fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 934464f6645SManish Chopra struct qed_tunn_start_params *p_tunn, 935fe56b9e6SYuval Mintz int hw_mode, 936fe56b9e6SYuval Mintz bool b_hw_start, 937fe56b9e6SYuval Mintz enum qed_int_mode int_mode, 938fe56b9e6SYuval Mintz bool allow_npar_tx_switch) 939fe56b9e6SYuval Mintz { 940fe56b9e6SYuval Mintz u8 rel_pf_id = p_hwfn->rel_pf_id; 941fe56b9e6SYuval Mintz int rc = 0; 942fe56b9e6SYuval Mintz 943fe56b9e6SYuval Mintz if (p_hwfn->mcp_info) { 944fe56b9e6SYuval Mintz struct qed_mcp_function_info *p_info; 945fe56b9e6SYuval Mintz 946fe56b9e6SYuval Mintz p_info = &p_hwfn->mcp_info->func_info; 947fe56b9e6SYuval Mintz if (p_info->bandwidth_min) 948fe56b9e6SYuval Mintz p_hwfn->qm_info.pf_wfq = p_info->bandwidth_min; 949fe56b9e6SYuval Mintz 950fe56b9e6SYuval Mintz /* Update rate limit once we'll actually have a link */ 9514b01e519SManish Chopra p_hwfn->qm_info.pf_rl = 100000; 952fe56b9e6SYuval Mintz } 953fe56b9e6SYuval Mintz 954fe56b9e6SYuval Mintz qed_cxt_hw_init_pf(p_hwfn); 955fe56b9e6SYuval Mintz 956fe56b9e6SYuval Mintz qed_int_igu_init_rt(p_hwfn); 957fe56b9e6SYuval Mintz 958fe56b9e6SYuval Mintz /* Set VLAN in NIG if needed */ 9591a635e48SYuval Mintz if (hw_mode & BIT(MODE_MF_SD)) { 960fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, "Configuring LLH_FUNC_TAG\n"); 961fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1); 962fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET, 963fe56b9e6SYuval Mintz p_hwfn->hw_info.ovlan); 964fe56b9e6SYuval Mintz } 965fe56b9e6SYuval Mintz 966fe56b9e6SYuval Mintz /* Enable classification by MAC if needed */ 9671a635e48SYuval Mintz if (hw_mode & BIT(MODE_MF_SI)) { 968fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 969fe56b9e6SYuval Mintz "Configuring TAGMAC_CLS_TYPE\n"); 970fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, 971fe56b9e6SYuval Mintz NIG_REG_LLH_FUNC_TAGMAC_CLS_TYPE_RT_OFFSET, 1); 972fe56b9e6SYuval Mintz } 973fe56b9e6SYuval Mintz 974fe56b9e6SYuval Mintz /* Protocl Configuration */ 975dbb799c3SYuval Mintz STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET, 976dbb799c3SYuval Mintz (p_hwfn->hw_info.personality == QED_PCI_ISCSI) ? 1 : 0); 977fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET, 0); 978fe56b9e6SYuval Mintz STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0); 979fe56b9e6SYuval Mintz 980fe56b9e6SYuval Mintz /* Cleanup chip from previous driver if such remains exist */ 9810b55e27dSYuval Mintz rc = qed_final_cleanup(p_hwfn, p_ptt, rel_pf_id, false); 9821a635e48SYuval Mintz if (rc) 983fe56b9e6SYuval Mintz return rc; 984fe56b9e6SYuval Mintz 985fe56b9e6SYuval Mintz /* PF Init sequence */ 986fe56b9e6SYuval Mintz rc = qed_init_run(p_hwfn, p_ptt, PHASE_PF, rel_pf_id, hw_mode); 987fe56b9e6SYuval Mintz if (rc) 988fe56b9e6SYuval Mintz return rc; 989fe56b9e6SYuval Mintz 990fe56b9e6SYuval Mintz /* QM_PF Init sequence (may be invoked separately e.g. for DCB) */ 991fe56b9e6SYuval Mintz rc = qed_init_run(p_hwfn, p_ptt, PHASE_QM_PF, rel_pf_id, hw_mode); 992fe56b9e6SYuval Mintz if (rc) 993fe56b9e6SYuval Mintz return rc; 994fe56b9e6SYuval Mintz 995fe56b9e6SYuval Mintz /* Pure runtime initializations - directly to the HW */ 996fe56b9e6SYuval Mintz qed_int_igu_init_pure_rt(p_hwfn, p_ptt, true, true); 997fe56b9e6SYuval Mintz 99851ff1725SRam Amrani rc = qed_hw_init_pf_doorbell_bar(p_hwfn, p_ptt); 99951ff1725SRam Amrani if (rc) 100051ff1725SRam Amrani return rc; 100151ff1725SRam Amrani 1002fe56b9e6SYuval Mintz if (b_hw_start) { 1003fe56b9e6SYuval Mintz /* enable interrupts */ 1004fe56b9e6SYuval Mintz qed_int_igu_enable(p_hwfn, p_ptt, int_mode); 1005fe56b9e6SYuval Mintz 1006fe56b9e6SYuval Mintz /* send function start command */ 1007831bfb0eSYuval Mintz rc = qed_sp_pf_start(p_hwfn, p_tunn, p_hwfn->cdev->mf_mode, 1008831bfb0eSYuval Mintz allow_npar_tx_switch); 1009fe56b9e6SYuval Mintz if (rc) 1010fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Function start ramrod failed\n"); 1011fe56b9e6SYuval Mintz } 1012fe56b9e6SYuval Mintz return rc; 1013fe56b9e6SYuval Mintz } 1014fe56b9e6SYuval Mintz 1015fe56b9e6SYuval Mintz static int qed_change_pci_hwfn(struct qed_hwfn *p_hwfn, 1016fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1017fe56b9e6SYuval Mintz u8 enable) 1018fe56b9e6SYuval Mintz { 1019fe56b9e6SYuval Mintz u32 delay_idx = 0, val, set_val = enable ? 1 : 0; 1020fe56b9e6SYuval Mintz 1021fe56b9e6SYuval Mintz /* Change PF in PXP */ 1022fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 1023fe56b9e6SYuval Mintz PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, set_val); 1024fe56b9e6SYuval Mintz 1025fe56b9e6SYuval Mintz /* wait until value is set - try for 1 second every 50us */ 1026fe56b9e6SYuval Mintz for (delay_idx = 0; delay_idx < 20000; delay_idx++) { 1027fe56b9e6SYuval Mintz val = qed_rd(p_hwfn, p_ptt, 1028fe56b9e6SYuval Mintz PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 1029fe56b9e6SYuval Mintz if (val == set_val) 1030fe56b9e6SYuval Mintz break; 1031fe56b9e6SYuval Mintz 1032fe56b9e6SYuval Mintz usleep_range(50, 60); 1033fe56b9e6SYuval Mintz } 1034fe56b9e6SYuval Mintz 1035fe56b9e6SYuval Mintz if (val != set_val) { 1036fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 1037fe56b9e6SYuval Mintz "PFID_ENABLE_MASTER wasn't changed after a second\n"); 1038fe56b9e6SYuval Mintz return -EAGAIN; 1039fe56b9e6SYuval Mintz } 1040fe56b9e6SYuval Mintz 1041fe56b9e6SYuval Mintz return 0; 1042fe56b9e6SYuval Mintz } 1043fe56b9e6SYuval Mintz 1044fe56b9e6SYuval Mintz static void qed_reset_mb_shadow(struct qed_hwfn *p_hwfn, 1045fe56b9e6SYuval Mintz struct qed_ptt *p_main_ptt) 1046fe56b9e6SYuval Mintz { 1047fe56b9e6SYuval Mintz /* Read shadow of current MFW mailbox */ 1048fe56b9e6SYuval Mintz qed_mcp_read_mb(p_hwfn, p_main_ptt); 1049fe56b9e6SYuval Mintz memcpy(p_hwfn->mcp_info->mfw_mb_shadow, 10501a635e48SYuval Mintz p_hwfn->mcp_info->mfw_mb_cur, p_hwfn->mcp_info->mfw_mb_length); 1051fe56b9e6SYuval Mintz } 1052fe56b9e6SYuval Mintz 1053fe56b9e6SYuval Mintz int qed_hw_init(struct qed_dev *cdev, 1054464f6645SManish Chopra struct qed_tunn_start_params *p_tunn, 1055fe56b9e6SYuval Mintz bool b_hw_start, 1056fe56b9e6SYuval Mintz enum qed_int_mode int_mode, 1057fe56b9e6SYuval Mintz bool allow_npar_tx_switch, 1058fe56b9e6SYuval Mintz const u8 *bin_fw_data) 1059fe56b9e6SYuval Mintz { 10600fefbfbaSSudarsana Kalluru u32 load_code, param, drv_mb_param; 10610fefbfbaSSudarsana Kalluru bool b_default_mtu = true; 10620fefbfbaSSudarsana Kalluru struct qed_hwfn *p_hwfn; 10630fefbfbaSSudarsana Kalluru int rc = 0, mfw_rc, i; 1064fe56b9e6SYuval Mintz 1065bb13ace7SSudarsana Reddy Kalluru if ((int_mode == QED_INT_MODE_MSI) && (cdev->num_hwfns > 1)) { 1066bb13ace7SSudarsana Reddy Kalluru DP_NOTICE(cdev, "MSI mode is not supported for CMT devices\n"); 1067bb13ace7SSudarsana Reddy Kalluru return -EINVAL; 1068bb13ace7SSudarsana Reddy Kalluru } 1069bb13ace7SSudarsana Reddy Kalluru 10701408cc1fSYuval Mintz if (IS_PF(cdev)) { 1071fe56b9e6SYuval Mintz rc = qed_init_fw_data(cdev, bin_fw_data); 10721a635e48SYuval Mintz if (rc) 1073fe56b9e6SYuval Mintz return rc; 10741408cc1fSYuval Mintz } 1075fe56b9e6SYuval Mintz 1076fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 1077fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1078fe56b9e6SYuval Mintz 10790fefbfbaSSudarsana Kalluru /* If management didn't provide a default, set one of our own */ 10800fefbfbaSSudarsana Kalluru if (!p_hwfn->hw_info.mtu) { 10810fefbfbaSSudarsana Kalluru p_hwfn->hw_info.mtu = 1500; 10820fefbfbaSSudarsana Kalluru b_default_mtu = false; 10830fefbfbaSSudarsana Kalluru } 10840fefbfbaSSudarsana Kalluru 10851408cc1fSYuval Mintz if (IS_VF(cdev)) { 10861408cc1fSYuval Mintz p_hwfn->b_int_enabled = 1; 10871408cc1fSYuval Mintz continue; 10881408cc1fSYuval Mintz } 10891408cc1fSYuval Mintz 1090fe56b9e6SYuval Mintz /* Enable DMAE in PXP */ 1091fe56b9e6SYuval Mintz rc = qed_change_pci_hwfn(p_hwfn, p_hwfn->p_main_ptt, true); 1092fe56b9e6SYuval Mintz 1093fe56b9e6SYuval Mintz qed_calc_hw_mode(p_hwfn); 1094fe56b9e6SYuval Mintz 10951a635e48SYuval Mintz rc = qed_mcp_load_req(p_hwfn, p_hwfn->p_main_ptt, &load_code); 1096fe56b9e6SYuval Mintz if (rc) { 1097fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed sending LOAD_REQ command\n"); 1098fe56b9e6SYuval Mintz return rc; 1099fe56b9e6SYuval Mintz } 1100fe56b9e6SYuval Mintz 1101fe56b9e6SYuval Mintz qed_reset_mb_shadow(p_hwfn, p_hwfn->p_main_ptt); 1102fe56b9e6SYuval Mintz 1103fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, QED_MSG_SP, 1104fe56b9e6SYuval Mintz "Load request was sent. Resp:0x%x, Load code: 0x%x\n", 1105fe56b9e6SYuval Mintz rc, load_code); 1106fe56b9e6SYuval Mintz 1107fe56b9e6SYuval Mintz p_hwfn->first_on_engine = (load_code == 1108fe56b9e6SYuval Mintz FW_MSG_CODE_DRV_LOAD_ENGINE); 1109fe56b9e6SYuval Mintz 1110fe56b9e6SYuval Mintz switch (load_code) { 1111fe56b9e6SYuval Mintz case FW_MSG_CODE_DRV_LOAD_ENGINE: 1112fe56b9e6SYuval Mintz rc = qed_hw_init_common(p_hwfn, p_hwfn->p_main_ptt, 1113fe56b9e6SYuval Mintz p_hwfn->hw_info.hw_mode); 1114fe56b9e6SYuval Mintz if (rc) 1115fe56b9e6SYuval Mintz break; 1116fe56b9e6SYuval Mintz /* Fall into */ 1117fe56b9e6SYuval Mintz case FW_MSG_CODE_DRV_LOAD_PORT: 1118fe56b9e6SYuval Mintz rc = qed_hw_init_port(p_hwfn, p_hwfn->p_main_ptt, 1119fe56b9e6SYuval Mintz p_hwfn->hw_info.hw_mode); 1120fe56b9e6SYuval Mintz if (rc) 1121fe56b9e6SYuval Mintz break; 1122fe56b9e6SYuval Mintz 1123fe56b9e6SYuval Mintz /* Fall into */ 1124fe56b9e6SYuval Mintz case FW_MSG_CODE_DRV_LOAD_FUNCTION: 1125fe56b9e6SYuval Mintz rc = qed_hw_init_pf(p_hwfn, p_hwfn->p_main_ptt, 1126464f6645SManish Chopra p_tunn, p_hwfn->hw_info.hw_mode, 1127fe56b9e6SYuval Mintz b_hw_start, int_mode, 1128fe56b9e6SYuval Mintz allow_npar_tx_switch); 1129fe56b9e6SYuval Mintz break; 1130fe56b9e6SYuval Mintz default: 1131fe56b9e6SYuval Mintz rc = -EINVAL; 1132fe56b9e6SYuval Mintz break; 1133fe56b9e6SYuval Mintz } 1134fe56b9e6SYuval Mintz 1135fe56b9e6SYuval Mintz if (rc) 1136fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, 1137fe56b9e6SYuval Mintz "init phase failed for loadcode 0x%x (rc %d)\n", 1138fe56b9e6SYuval Mintz load_code, rc); 1139fe56b9e6SYuval Mintz 1140fe56b9e6SYuval Mintz /* ACK mfw regardless of success or failure of initialization */ 1141fe56b9e6SYuval Mintz mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1142fe56b9e6SYuval Mintz DRV_MSG_CODE_LOAD_DONE, 1143fe56b9e6SYuval Mintz 0, &load_code, ¶m); 1144fe56b9e6SYuval Mintz if (rc) 1145fe56b9e6SYuval Mintz return rc; 1146fe56b9e6SYuval Mintz if (mfw_rc) { 1147fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed sending LOAD_DONE command\n"); 1148fe56b9e6SYuval Mintz return mfw_rc; 1149fe56b9e6SYuval Mintz } 1150fe56b9e6SYuval Mintz 115139651abdSSudarsana Reddy Kalluru /* send DCBX attention request command */ 115239651abdSSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, 115339651abdSSudarsana Reddy Kalluru QED_MSG_DCB, 115439651abdSSudarsana Reddy Kalluru "sending phony dcbx set command to trigger DCBx attention handling\n"); 115539651abdSSudarsana Reddy Kalluru mfw_rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 115639651abdSSudarsana Reddy Kalluru DRV_MSG_CODE_SET_DCBX, 115739651abdSSudarsana Reddy Kalluru 1 << DRV_MB_PARAM_DCBX_NOTIFY_SHIFT, 115839651abdSSudarsana Reddy Kalluru &load_code, ¶m); 115939651abdSSudarsana Reddy Kalluru if (mfw_rc) { 116039651abdSSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, 116139651abdSSudarsana Reddy Kalluru "Failed to send DCBX attention request\n"); 116239651abdSSudarsana Reddy Kalluru return mfw_rc; 116339651abdSSudarsana Reddy Kalluru } 116439651abdSSudarsana Reddy Kalluru 1165fe56b9e6SYuval Mintz p_hwfn->hw_init_done = true; 1166fe56b9e6SYuval Mintz } 1167fe56b9e6SYuval Mintz 11680fefbfbaSSudarsana Kalluru if (IS_PF(cdev)) { 11690fefbfbaSSudarsana Kalluru p_hwfn = QED_LEADING_HWFN(cdev); 11700fefbfbaSSudarsana Kalluru drv_mb_param = (FW_MAJOR_VERSION << 24) | 11710fefbfbaSSudarsana Kalluru (FW_MINOR_VERSION << 16) | 11720fefbfbaSSudarsana Kalluru (FW_REVISION_VERSION << 8) | 11730fefbfbaSSudarsana Kalluru (FW_ENGINEERING_VERSION); 11740fefbfbaSSudarsana Kalluru rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 11750fefbfbaSSudarsana Kalluru DRV_MSG_CODE_OV_UPDATE_STORM_FW_VER, 11760fefbfbaSSudarsana Kalluru drv_mb_param, &load_code, ¶m); 11770fefbfbaSSudarsana Kalluru if (rc) 11780fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, "Failed to update firmware version\n"); 11790fefbfbaSSudarsana Kalluru 11800fefbfbaSSudarsana Kalluru if (!b_default_mtu) { 11810fefbfbaSSudarsana Kalluru rc = qed_mcp_ov_update_mtu(p_hwfn, p_hwfn->p_main_ptt, 11820fefbfbaSSudarsana Kalluru p_hwfn->hw_info.mtu); 11830fefbfbaSSudarsana Kalluru if (rc) 11840fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, 11850fefbfbaSSudarsana Kalluru "Failed to update default mtu\n"); 11860fefbfbaSSudarsana Kalluru } 11870fefbfbaSSudarsana Kalluru 11880fefbfbaSSudarsana Kalluru rc = qed_mcp_ov_update_driver_state(p_hwfn, 11890fefbfbaSSudarsana Kalluru p_hwfn->p_main_ptt, 11900fefbfbaSSudarsana Kalluru QED_OV_DRIVER_STATE_DISABLED); 11910fefbfbaSSudarsana Kalluru if (rc) 11920fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, "Failed to update driver state\n"); 11930fefbfbaSSudarsana Kalluru 11940fefbfbaSSudarsana Kalluru rc = qed_mcp_ov_update_eswitch(p_hwfn, p_hwfn->p_main_ptt, 11950fefbfbaSSudarsana Kalluru QED_OV_ESWITCH_VEB); 11960fefbfbaSSudarsana Kalluru if (rc) 11970fefbfbaSSudarsana Kalluru DP_INFO(p_hwfn, "Failed to update eswitch mode\n"); 11980fefbfbaSSudarsana Kalluru } 11990fefbfbaSSudarsana Kalluru 1200fe56b9e6SYuval Mintz return 0; 1201fe56b9e6SYuval Mintz } 1202fe56b9e6SYuval Mintz 1203fe56b9e6SYuval Mintz #define QED_HW_STOP_RETRY_LIMIT (10) 12041a635e48SYuval Mintz static void qed_hw_timers_stop(struct qed_dev *cdev, 12051a635e48SYuval Mintz struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 12068c925c44SYuval Mintz { 12078c925c44SYuval Mintz int i; 12088c925c44SYuval Mintz 12098c925c44SYuval Mintz /* close timers */ 12108c925c44SYuval Mintz qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_CONN, 0x0); 12118c925c44SYuval Mintz qed_wr(p_hwfn, p_ptt, TM_REG_PF_ENABLE_TASK, 0x0); 12128c925c44SYuval Mintz 12138c925c44SYuval Mintz for (i = 0; i < QED_HW_STOP_RETRY_LIMIT; i++) { 12148c925c44SYuval Mintz if ((!qed_rd(p_hwfn, p_ptt, 12158c925c44SYuval Mintz TM_REG_PF_SCAN_ACTIVE_CONN)) && 12161a635e48SYuval Mintz (!qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK))) 12178c925c44SYuval Mintz break; 12188c925c44SYuval Mintz 12198c925c44SYuval Mintz /* Dependent on number of connection/tasks, possibly 12208c925c44SYuval Mintz * 1ms sleep is required between polls 12218c925c44SYuval Mintz */ 12228c925c44SYuval Mintz usleep_range(1000, 2000); 12238c925c44SYuval Mintz } 12248c925c44SYuval Mintz 12258c925c44SYuval Mintz if (i < QED_HW_STOP_RETRY_LIMIT) 12268c925c44SYuval Mintz return; 12278c925c44SYuval Mintz 12288c925c44SYuval Mintz DP_NOTICE(p_hwfn, 12298c925c44SYuval Mintz "Timers linear scans are not over [Connection %02x Tasks %02x]\n", 12308c925c44SYuval Mintz (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_CONN), 12318c925c44SYuval Mintz (u8)qed_rd(p_hwfn, p_ptt, TM_REG_PF_SCAN_ACTIVE_TASK)); 12328c925c44SYuval Mintz } 12338c925c44SYuval Mintz 12348c925c44SYuval Mintz void qed_hw_timers_stop_all(struct qed_dev *cdev) 12358c925c44SYuval Mintz { 12368c925c44SYuval Mintz int j; 12378c925c44SYuval Mintz 12388c925c44SYuval Mintz for_each_hwfn(cdev, j) { 12398c925c44SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 12408c925c44SYuval Mintz struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 12418c925c44SYuval Mintz 12428c925c44SYuval Mintz qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 12438c925c44SYuval Mintz } 12448c925c44SYuval Mintz } 12458c925c44SYuval Mintz 1246fe56b9e6SYuval Mintz int qed_hw_stop(struct qed_dev *cdev) 1247fe56b9e6SYuval Mintz { 1248fe56b9e6SYuval Mintz int rc = 0, t_rc; 12498c925c44SYuval Mintz int j; 1250fe56b9e6SYuval Mintz 1251fe56b9e6SYuval Mintz for_each_hwfn(cdev, j) { 1252fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 1253fe56b9e6SYuval Mintz struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 1254fe56b9e6SYuval Mintz 1255fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Stopping hw/fw\n"); 1256fe56b9e6SYuval Mintz 12571408cc1fSYuval Mintz if (IS_VF(cdev)) { 12580b55e27dSYuval Mintz qed_vf_pf_int_cleanup(p_hwfn); 12591408cc1fSYuval Mintz continue; 12601408cc1fSYuval Mintz } 12611408cc1fSYuval Mintz 1262fe56b9e6SYuval Mintz /* mark the hw as uninitialized... */ 1263fe56b9e6SYuval Mintz p_hwfn->hw_init_done = false; 1264fe56b9e6SYuval Mintz 1265fe56b9e6SYuval Mintz rc = qed_sp_pf_stop(p_hwfn); 1266fe56b9e6SYuval Mintz if (rc) 12678c925c44SYuval Mintz DP_NOTICE(p_hwfn, 12688c925c44SYuval Mintz "Failed to close PF against FW. Continue to stop HW to prevent illegal host access by the device\n"); 1269fe56b9e6SYuval Mintz 1270fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, 1271fe56b9e6SYuval Mintz NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 1272fe56b9e6SYuval Mintz 1273fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1274fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 1275fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 1276fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1277fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 1278fe56b9e6SYuval Mintz 12798c925c44SYuval Mintz qed_hw_timers_stop(cdev, p_hwfn, p_ptt); 1280fe56b9e6SYuval Mintz 1281fe56b9e6SYuval Mintz /* Disable Attention Generation */ 1282fe56b9e6SYuval Mintz qed_int_igu_disable_int(p_hwfn, p_ptt); 1283fe56b9e6SYuval Mintz 1284fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_LEADING_EDGE_LATCH, 0); 1285fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_ptt, IGU_REG_TRAILING_EDGE_LATCH, 0); 1286fe56b9e6SYuval Mintz 1287fe56b9e6SYuval Mintz qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, true); 1288fe56b9e6SYuval Mintz 1289fe56b9e6SYuval Mintz /* Need to wait 1ms to guarantee SBs are cleared */ 1290fe56b9e6SYuval Mintz usleep_range(1000, 2000); 1291fe56b9e6SYuval Mintz } 1292fe56b9e6SYuval Mintz 12931408cc1fSYuval Mintz if (IS_PF(cdev)) { 1294fe56b9e6SYuval Mintz /* Disable DMAE in PXP - in CMT, this should only be done for 1295fe56b9e6SYuval Mintz * first hw-function, and only after all transactions have 1296fe56b9e6SYuval Mintz * stopped for all active hw-functions. 1297fe56b9e6SYuval Mintz */ 1298fe56b9e6SYuval Mintz t_rc = qed_change_pci_hwfn(&cdev->hwfns[0], 12991408cc1fSYuval Mintz cdev->hwfns[0].p_main_ptt, false); 1300fe56b9e6SYuval Mintz if (t_rc != 0) 1301fe56b9e6SYuval Mintz rc = t_rc; 13021408cc1fSYuval Mintz } 1303fe56b9e6SYuval Mintz 1304fe56b9e6SYuval Mintz return rc; 1305fe56b9e6SYuval Mintz } 1306fe56b9e6SYuval Mintz 1307cee4d264SManish Chopra void qed_hw_stop_fastpath(struct qed_dev *cdev) 1308cee4d264SManish Chopra { 13098c925c44SYuval Mintz int j; 1310cee4d264SManish Chopra 1311cee4d264SManish Chopra for_each_hwfn(cdev, j) { 1312cee4d264SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[j]; 1313cee4d264SManish Chopra struct qed_ptt *p_ptt = p_hwfn->p_main_ptt; 1314cee4d264SManish Chopra 1315dacd88d6SYuval Mintz if (IS_VF(cdev)) { 1316dacd88d6SYuval Mintz qed_vf_pf_int_cleanup(p_hwfn); 1317dacd88d6SYuval Mintz continue; 1318dacd88d6SYuval Mintz } 1319dacd88d6SYuval Mintz 1320cee4d264SManish Chopra DP_VERBOSE(p_hwfn, 13211a635e48SYuval Mintz NETIF_MSG_IFDOWN, "Shutting down the fastpath\n"); 1322cee4d264SManish Chopra 1323cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, 1324cee4d264SManish Chopra NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x1); 1325cee4d264SManish Chopra 1326cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_TCP, 0x0); 1327cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_UDP, 0x0); 1328cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_FCOE, 0x0); 1329cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_ROCE, 0x0); 1330cee4d264SManish Chopra qed_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_OPENFLOW, 0x0); 1331cee4d264SManish Chopra 1332cee4d264SManish Chopra qed_int_igu_init_pure_rt(p_hwfn, p_ptt, false, false); 1333cee4d264SManish Chopra 1334cee4d264SManish Chopra /* Need to wait 1ms to guarantee SBs are cleared */ 1335cee4d264SManish Chopra usleep_range(1000, 2000); 1336cee4d264SManish Chopra } 1337cee4d264SManish Chopra } 1338cee4d264SManish Chopra 1339cee4d264SManish Chopra void qed_hw_start_fastpath(struct qed_hwfn *p_hwfn) 1340cee4d264SManish Chopra { 1341dacd88d6SYuval Mintz if (IS_VF(p_hwfn->cdev)) 1342dacd88d6SYuval Mintz return; 1343dacd88d6SYuval Mintz 1344cee4d264SManish Chopra /* Re-open incoming traffic */ 1345cee4d264SManish Chopra qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1346cee4d264SManish Chopra NIG_REG_RX_LLH_BRB_GATE_DNTFWD_PERPF, 0x0); 1347cee4d264SManish Chopra } 1348cee4d264SManish Chopra 13491a635e48SYuval Mintz static int qed_reg_assert(struct qed_hwfn *p_hwfn, 13501a635e48SYuval Mintz struct qed_ptt *p_ptt, u32 reg, bool expected) 1351fe56b9e6SYuval Mintz { 13521a635e48SYuval Mintz u32 assert_val = qed_rd(p_hwfn, p_ptt, reg); 1353fe56b9e6SYuval Mintz 1354fe56b9e6SYuval Mintz if (assert_val != expected) { 1355525ef5c0SYuval Mintz DP_NOTICE(p_hwfn, "Value at address 0x%08x != 0x%08x\n", 1356fe56b9e6SYuval Mintz reg, expected); 1357fe56b9e6SYuval Mintz return -EINVAL; 1358fe56b9e6SYuval Mintz } 1359fe56b9e6SYuval Mintz 1360fe56b9e6SYuval Mintz return 0; 1361fe56b9e6SYuval Mintz } 1362fe56b9e6SYuval Mintz 1363fe56b9e6SYuval Mintz int qed_hw_reset(struct qed_dev *cdev) 1364fe56b9e6SYuval Mintz { 1365fe56b9e6SYuval Mintz int rc = 0; 1366fe56b9e6SYuval Mintz u32 unload_resp, unload_param; 136714d39648SMintz, Yuval u32 wol_param; 1368fe56b9e6SYuval Mintz int i; 1369fe56b9e6SYuval Mintz 137014d39648SMintz, Yuval switch (cdev->wol_config) { 137114d39648SMintz, Yuval case QED_OV_WOL_DISABLED: 137214d39648SMintz, Yuval wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED; 137314d39648SMintz, Yuval break; 137414d39648SMintz, Yuval case QED_OV_WOL_ENABLED: 137514d39648SMintz, Yuval wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED; 137614d39648SMintz, Yuval break; 137714d39648SMintz, Yuval default: 137814d39648SMintz, Yuval DP_NOTICE(cdev, 137914d39648SMintz, Yuval "Unknown WoL configuration %02x\n", cdev->wol_config); 138014d39648SMintz, Yuval /* Fallthrough */ 138114d39648SMintz, Yuval case QED_OV_WOL_DEFAULT: 138214d39648SMintz, Yuval wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP; 138314d39648SMintz, Yuval } 138414d39648SMintz, Yuval 1385fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 1386fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 1387fe56b9e6SYuval Mintz 13881408cc1fSYuval Mintz if (IS_VF(cdev)) { 13890b55e27dSYuval Mintz rc = qed_vf_pf_reset(p_hwfn); 13900b55e27dSYuval Mintz if (rc) 13910b55e27dSYuval Mintz return rc; 13921408cc1fSYuval Mintz continue; 13931408cc1fSYuval Mintz } 13941408cc1fSYuval Mintz 1395fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_IFDOWN, "Resetting hw/fw\n"); 1396fe56b9e6SYuval Mintz 1397fe56b9e6SYuval Mintz /* Check for incorrect states */ 1398fe56b9e6SYuval Mintz qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt, 1399fe56b9e6SYuval Mintz QM_REG_USG_CNT_PF_TX, 0); 1400fe56b9e6SYuval Mintz qed_reg_assert(p_hwfn, p_hwfn->p_main_ptt, 1401fe56b9e6SYuval Mintz QM_REG_USG_CNT_PF_OTHER, 0); 1402fe56b9e6SYuval Mintz 1403fe56b9e6SYuval Mintz /* Disable PF in HW blocks */ 1404fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, DORQ_REG_PF_DB_ENABLE, 0); 1405fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, QM_REG_PF_EN, 0); 1406fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1407fe56b9e6SYuval Mintz TCFC_REG_STRONG_ENABLE_PF, 0); 1408fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1409fe56b9e6SYuval Mintz CCFC_REG_STRONG_ENABLE_PF, 0); 1410fe56b9e6SYuval Mintz 1411fe56b9e6SYuval Mintz /* Send unload command to MCP */ 1412fe56b9e6SYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 141314d39648SMintz, Yuval DRV_MSG_CODE_UNLOAD_REQ, wol_param, 1414fe56b9e6SYuval Mintz &unload_resp, &unload_param); 1415fe56b9e6SYuval Mintz if (rc) { 1416fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_REQ failed\n"); 1417fe56b9e6SYuval Mintz unload_resp = FW_MSG_CODE_DRV_UNLOAD_ENGINE; 1418fe56b9e6SYuval Mintz } 1419fe56b9e6SYuval Mintz 1420fe56b9e6SYuval Mintz rc = qed_mcp_cmd(p_hwfn, p_hwfn->p_main_ptt, 1421fe56b9e6SYuval Mintz DRV_MSG_CODE_UNLOAD_DONE, 1422fe56b9e6SYuval Mintz 0, &unload_resp, &unload_param); 1423fe56b9e6SYuval Mintz if (rc) { 1424fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "qed_hw_reset: UNLOAD_DONE failed\n"); 1425fe56b9e6SYuval Mintz return rc; 1426fe56b9e6SYuval Mintz } 1427fe56b9e6SYuval Mintz } 1428fe56b9e6SYuval Mintz 1429fe56b9e6SYuval Mintz return rc; 1430fe56b9e6SYuval Mintz } 1431fe56b9e6SYuval Mintz 1432fe56b9e6SYuval Mintz /* Free hwfn memory and resources acquired in hw_hwfn_prepare */ 1433fe56b9e6SYuval Mintz static void qed_hw_hwfn_free(struct qed_hwfn *p_hwfn) 1434fe56b9e6SYuval Mintz { 1435fe56b9e6SYuval Mintz qed_ptt_pool_free(p_hwfn); 1436fe56b9e6SYuval Mintz kfree(p_hwfn->hw_info.p_igu_info); 1437fe56b9e6SYuval Mintz } 1438fe56b9e6SYuval Mintz 1439fe56b9e6SYuval Mintz /* Setup bar access */ 144012e09c69SYuval Mintz static void qed_hw_hwfn_prepare(struct qed_hwfn *p_hwfn) 1441fe56b9e6SYuval Mintz { 1442fe56b9e6SYuval Mintz /* clear indirect access */ 1443fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_88_F0, 0); 1444fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_8C_F0, 0); 1445fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_90_F0, 0); 1446fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, PGLUE_B_REG_PGL_ADDR_94_F0, 0); 1447fe56b9e6SYuval Mintz 1448fe56b9e6SYuval Mintz /* Clean Previous errors if such exist */ 1449fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, 14501a635e48SYuval Mintz PGLUE_B_REG_WAS_ERROR_PF_31_0_CLR, 1 << p_hwfn->abs_pf_id); 1451fe56b9e6SYuval Mintz 1452fe56b9e6SYuval Mintz /* enable internal target-read */ 1453fe56b9e6SYuval Mintz qed_wr(p_hwfn, p_hwfn->p_main_ptt, 1454fe56b9e6SYuval Mintz PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 1455fe56b9e6SYuval Mintz } 1456fe56b9e6SYuval Mintz 1457fe56b9e6SYuval Mintz static void get_function_id(struct qed_hwfn *p_hwfn) 1458fe56b9e6SYuval Mintz { 1459fe56b9e6SYuval Mintz /* ME Register */ 14601a635e48SYuval Mintz p_hwfn->hw_info.opaque_fid = (u16) REG_RD(p_hwfn, 14611a635e48SYuval Mintz PXP_PF_ME_OPAQUE_ADDR); 1462fe56b9e6SYuval Mintz 1463fe56b9e6SYuval Mintz p_hwfn->hw_info.concrete_fid = REG_RD(p_hwfn, PXP_PF_ME_CONCRETE_ADDR); 1464fe56b9e6SYuval Mintz 1465fe56b9e6SYuval Mintz p_hwfn->abs_pf_id = (p_hwfn->hw_info.concrete_fid >> 16) & 0xf; 1466fe56b9e6SYuval Mintz p_hwfn->rel_pf_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 1467fe56b9e6SYuval Mintz PXP_CONCRETE_FID_PFID); 1468fe56b9e6SYuval Mintz p_hwfn->port_id = GET_FIELD(p_hwfn->hw_info.concrete_fid, 1469fe56b9e6SYuval Mintz PXP_CONCRETE_FID_PORT); 1470525ef5c0SYuval Mintz 1471525ef5c0SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, 1472525ef5c0SYuval Mintz "Read ME register: Concrete 0x%08x Opaque 0x%04x\n", 1473525ef5c0SYuval Mintz p_hwfn->hw_info.concrete_fid, p_hwfn->hw_info.opaque_fid); 1474fe56b9e6SYuval Mintz } 1475fe56b9e6SYuval Mintz 147625c089d7SYuval Mintz static void qed_hw_set_feat(struct qed_hwfn *p_hwfn) 147725c089d7SYuval Mintz { 147825c089d7SYuval Mintz u32 *feat_num = p_hwfn->hw_info.feat_num; 14795a1f965aSMintz, Yuval struct qed_sb_cnt_info sb_cnt_info; 148025c089d7SYuval Mintz int num_features = 1; 148125c089d7SYuval Mintz 14820189efb8SYuval Mintz if (IS_ENABLED(CONFIG_QED_RDMA) && 14830189efb8SYuval Mintz p_hwfn->hw_info.personality == QED_PCI_ETH_ROCE) { 14840189efb8SYuval Mintz /* Roce CNQ each requires: 1 status block + 1 CNQ. We divide 14850189efb8SYuval Mintz * the status blocks equally between L2 / RoCE but with 14860189efb8SYuval Mintz * consideration as to how many l2 queues / cnqs we have. 148751ff1725SRam Amrani */ 148851ff1725SRam Amrani num_features++; 148951ff1725SRam Amrani 149051ff1725SRam Amrani feat_num[QED_RDMA_CNQ] = 149151ff1725SRam Amrani min_t(u32, RESC_NUM(p_hwfn, QED_SB) / num_features, 149251ff1725SRam Amrani RESC_NUM(p_hwfn, QED_RDMA_CNQ_RAM)); 149351ff1725SRam Amrani } 14940189efb8SYuval Mintz 149525c089d7SYuval Mintz feat_num[QED_PF_L2_QUE] = min_t(u32, RESC_NUM(p_hwfn, QED_SB) / 149625c089d7SYuval Mintz num_features, 149725c089d7SYuval Mintz RESC_NUM(p_hwfn, QED_L2_QUEUE)); 14985a1f965aSMintz, Yuval 14995a1f965aSMintz, Yuval memset(&sb_cnt_info, 0, sizeof(sb_cnt_info)); 15005a1f965aSMintz, Yuval qed_int_get_num_sbs(p_hwfn, &sb_cnt_info); 15015a1f965aSMintz, Yuval feat_num[QED_VF_L2_QUE] = 15025a1f965aSMintz, Yuval min_t(u32, 15035a1f965aSMintz, Yuval RESC_NUM(p_hwfn, QED_L2_QUEUE) - 15045a1f965aSMintz, Yuval FEAT_NUM(p_hwfn, QED_PF_L2_QUE), sb_cnt_info.sb_iov_cnt); 15055a1f965aSMintz, Yuval 15065a1f965aSMintz, Yuval DP_VERBOSE(p_hwfn, 15075a1f965aSMintz, Yuval NETIF_MSG_PROBE, 15085a1f965aSMintz, Yuval "#PF_L2_QUEUES=%d VF_L2_QUEUES=%d #ROCE_CNQ=%d #SBS=%d num_features=%d\n", 15095a1f965aSMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_PF_L2_QUE), 15105a1f965aSMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_VF_L2_QUE), 15115a1f965aSMintz, Yuval (int)FEAT_NUM(p_hwfn, QED_RDMA_CNQ), 15125a1f965aSMintz, Yuval RESC_NUM(p_hwfn, QED_SB), num_features); 151325c089d7SYuval Mintz } 151425c089d7SYuval Mintz 15152edbff8dSTomer Tayar static enum resource_id_enum qed_hw_get_mfw_res_id(enum qed_resources res_id) 15162edbff8dSTomer Tayar { 15172edbff8dSTomer Tayar enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID; 15182edbff8dSTomer Tayar 15192edbff8dSTomer Tayar switch (res_id) { 15202edbff8dSTomer Tayar case QED_SB: 15212edbff8dSTomer Tayar mfw_res_id = RESOURCE_NUM_SB_E; 15222edbff8dSTomer Tayar break; 15232edbff8dSTomer Tayar case QED_L2_QUEUE: 15242edbff8dSTomer Tayar mfw_res_id = RESOURCE_NUM_L2_QUEUE_E; 15252edbff8dSTomer Tayar break; 15262edbff8dSTomer Tayar case QED_VPORT: 15272edbff8dSTomer Tayar mfw_res_id = RESOURCE_NUM_VPORT_E; 15282edbff8dSTomer Tayar break; 15292edbff8dSTomer Tayar case QED_RSS_ENG: 15302edbff8dSTomer Tayar mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E; 15312edbff8dSTomer Tayar break; 15322edbff8dSTomer Tayar case QED_PQ: 15332edbff8dSTomer Tayar mfw_res_id = RESOURCE_NUM_PQ_E; 15342edbff8dSTomer Tayar break; 15352edbff8dSTomer Tayar case QED_RL: 15362edbff8dSTomer Tayar mfw_res_id = RESOURCE_NUM_RL_E; 15372edbff8dSTomer Tayar break; 15382edbff8dSTomer Tayar case QED_MAC: 15392edbff8dSTomer Tayar case QED_VLAN: 15402edbff8dSTomer Tayar /* Each VFC resource can accommodate both a MAC and a VLAN */ 15412edbff8dSTomer Tayar mfw_res_id = RESOURCE_VFC_FILTER_E; 15422edbff8dSTomer Tayar break; 15432edbff8dSTomer Tayar case QED_ILT: 15442edbff8dSTomer Tayar mfw_res_id = RESOURCE_ILT_E; 15452edbff8dSTomer Tayar break; 15462edbff8dSTomer Tayar case QED_LL2_QUEUE: 15472edbff8dSTomer Tayar mfw_res_id = RESOURCE_LL2_QUEUE_E; 15482edbff8dSTomer Tayar break; 15492edbff8dSTomer Tayar case QED_RDMA_CNQ_RAM: 15502edbff8dSTomer Tayar case QED_CMDQS_CQS: 15512edbff8dSTomer Tayar /* CNQ/CMDQS are the same resource */ 15522edbff8dSTomer Tayar mfw_res_id = RESOURCE_CQS_E; 15532edbff8dSTomer Tayar break; 15542edbff8dSTomer Tayar case QED_RDMA_STATS_QUEUE: 15552edbff8dSTomer Tayar mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E; 15562edbff8dSTomer Tayar break; 15572edbff8dSTomer Tayar default: 15582edbff8dSTomer Tayar break; 15592edbff8dSTomer Tayar } 15602edbff8dSTomer Tayar 15612edbff8dSTomer Tayar return mfw_res_id; 15622edbff8dSTomer Tayar } 15632edbff8dSTomer Tayar 15642edbff8dSTomer Tayar static u32 qed_hw_get_dflt_resc_num(struct qed_hwfn *p_hwfn, 15652edbff8dSTomer Tayar enum qed_resources res_id) 15662edbff8dSTomer Tayar { 15672edbff8dSTomer Tayar u8 num_funcs = p_hwfn->num_funcs_on_engine; 15682edbff8dSTomer Tayar struct qed_sb_cnt_info sb_cnt_info; 15692edbff8dSTomer Tayar u32 dflt_resc_num = 0; 15702edbff8dSTomer Tayar 15712edbff8dSTomer Tayar switch (res_id) { 15722edbff8dSTomer Tayar case QED_SB: 15732edbff8dSTomer Tayar memset(&sb_cnt_info, 0, sizeof(sb_cnt_info)); 15742edbff8dSTomer Tayar qed_int_get_num_sbs(p_hwfn, &sb_cnt_info); 15752edbff8dSTomer Tayar dflt_resc_num = sb_cnt_info.sb_cnt; 15762edbff8dSTomer Tayar break; 15772edbff8dSTomer Tayar case QED_L2_QUEUE: 15782edbff8dSTomer Tayar dflt_resc_num = MAX_NUM_L2_QUEUES_BB / num_funcs; 15792edbff8dSTomer Tayar break; 15802edbff8dSTomer Tayar case QED_VPORT: 15812edbff8dSTomer Tayar dflt_resc_num = MAX_NUM_VPORTS_BB / num_funcs; 15822edbff8dSTomer Tayar break; 15832edbff8dSTomer Tayar case QED_RSS_ENG: 15842edbff8dSTomer Tayar dflt_resc_num = ETH_RSS_ENGINE_NUM_BB / num_funcs; 15852edbff8dSTomer Tayar break; 15862edbff8dSTomer Tayar case QED_PQ: 15872edbff8dSTomer Tayar /* The granularity of the PQs is 8 */ 15882edbff8dSTomer Tayar dflt_resc_num = MAX_QM_TX_QUEUES_BB / num_funcs; 15892edbff8dSTomer Tayar dflt_resc_num &= ~0x7; 15902edbff8dSTomer Tayar break; 15912edbff8dSTomer Tayar case QED_RL: 15922edbff8dSTomer Tayar dflt_resc_num = MAX_QM_GLOBAL_RLS / num_funcs; 15932edbff8dSTomer Tayar break; 15942edbff8dSTomer Tayar case QED_MAC: 15952edbff8dSTomer Tayar case QED_VLAN: 15962edbff8dSTomer Tayar /* Each VFC resource can accommodate both a MAC and a VLAN */ 15972edbff8dSTomer Tayar dflt_resc_num = ETH_NUM_MAC_FILTERS / num_funcs; 15982edbff8dSTomer Tayar break; 15992edbff8dSTomer Tayar case QED_ILT: 16002edbff8dSTomer Tayar dflt_resc_num = PXP_NUM_ILT_RECORDS_BB / num_funcs; 16012edbff8dSTomer Tayar break; 16022edbff8dSTomer Tayar case QED_LL2_QUEUE: 16032edbff8dSTomer Tayar dflt_resc_num = MAX_NUM_LL2_RX_QUEUES / num_funcs; 16042edbff8dSTomer Tayar break; 16052edbff8dSTomer Tayar case QED_RDMA_CNQ_RAM: 16062edbff8dSTomer Tayar case QED_CMDQS_CQS: 16072edbff8dSTomer Tayar /* CNQ/CMDQS are the same resource */ 16082edbff8dSTomer Tayar dflt_resc_num = NUM_OF_CMDQS_CQS / num_funcs; 16092edbff8dSTomer Tayar break; 16102edbff8dSTomer Tayar case QED_RDMA_STATS_QUEUE: 16112edbff8dSTomer Tayar dflt_resc_num = RDMA_NUM_STATISTIC_COUNTERS_BB / num_funcs; 16122edbff8dSTomer Tayar break; 16132edbff8dSTomer Tayar default: 16142edbff8dSTomer Tayar break; 16152edbff8dSTomer Tayar } 16162edbff8dSTomer Tayar 16172edbff8dSTomer Tayar return dflt_resc_num; 16182edbff8dSTomer Tayar } 16192edbff8dSTomer Tayar 16202edbff8dSTomer Tayar static const char *qed_hw_get_resc_name(enum qed_resources res_id) 16212edbff8dSTomer Tayar { 16222edbff8dSTomer Tayar switch (res_id) { 16232edbff8dSTomer Tayar case QED_SB: 16242edbff8dSTomer Tayar return "SB"; 16252edbff8dSTomer Tayar case QED_L2_QUEUE: 16262edbff8dSTomer Tayar return "L2_QUEUE"; 16272edbff8dSTomer Tayar case QED_VPORT: 16282edbff8dSTomer Tayar return "VPORT"; 16292edbff8dSTomer Tayar case QED_RSS_ENG: 16302edbff8dSTomer Tayar return "RSS_ENG"; 16312edbff8dSTomer Tayar case QED_PQ: 16322edbff8dSTomer Tayar return "PQ"; 16332edbff8dSTomer Tayar case QED_RL: 16342edbff8dSTomer Tayar return "RL"; 16352edbff8dSTomer Tayar case QED_MAC: 16362edbff8dSTomer Tayar return "MAC"; 16372edbff8dSTomer Tayar case QED_VLAN: 16382edbff8dSTomer Tayar return "VLAN"; 16392edbff8dSTomer Tayar case QED_RDMA_CNQ_RAM: 16402edbff8dSTomer Tayar return "RDMA_CNQ_RAM"; 16412edbff8dSTomer Tayar case QED_ILT: 16422edbff8dSTomer Tayar return "ILT"; 16432edbff8dSTomer Tayar case QED_LL2_QUEUE: 16442edbff8dSTomer Tayar return "LL2_QUEUE"; 16452edbff8dSTomer Tayar case QED_CMDQS_CQS: 16462edbff8dSTomer Tayar return "CMDQS_CQS"; 16472edbff8dSTomer Tayar case QED_RDMA_STATS_QUEUE: 16482edbff8dSTomer Tayar return "RDMA_STATS_QUEUE"; 16492edbff8dSTomer Tayar default: 16502edbff8dSTomer Tayar return "UNKNOWN_RESOURCE"; 16512edbff8dSTomer Tayar } 16522edbff8dSTomer Tayar } 16532edbff8dSTomer Tayar 16542edbff8dSTomer Tayar static int qed_hw_set_resc_info(struct qed_hwfn *p_hwfn, 16552edbff8dSTomer Tayar enum qed_resources res_id) 16562edbff8dSTomer Tayar { 16572edbff8dSTomer Tayar u32 dflt_resc_num = 0, dflt_resc_start = 0, mcp_resp, mcp_param; 16582edbff8dSTomer Tayar u32 *p_resc_num, *p_resc_start; 16592edbff8dSTomer Tayar struct resource_info resc_info; 16602edbff8dSTomer Tayar int rc; 16612edbff8dSTomer Tayar 16622edbff8dSTomer Tayar p_resc_num = &RESC_NUM(p_hwfn, res_id); 16632edbff8dSTomer Tayar p_resc_start = &RESC_START(p_hwfn, res_id); 16642edbff8dSTomer Tayar 16652edbff8dSTomer Tayar /* Default values assumes that each function received equal share */ 16662edbff8dSTomer Tayar dflt_resc_num = qed_hw_get_dflt_resc_num(p_hwfn, res_id); 16672edbff8dSTomer Tayar if (!dflt_resc_num) { 16682edbff8dSTomer Tayar DP_ERR(p_hwfn, 16692edbff8dSTomer Tayar "Failed to get default amount for resource %d [%s]\n", 16702edbff8dSTomer Tayar res_id, qed_hw_get_resc_name(res_id)); 16712edbff8dSTomer Tayar return -EINVAL; 16722edbff8dSTomer Tayar } 16732edbff8dSTomer Tayar dflt_resc_start = dflt_resc_num * p_hwfn->enabled_func_idx; 16742edbff8dSTomer Tayar 16752edbff8dSTomer Tayar memset(&resc_info, 0, sizeof(resc_info)); 16762edbff8dSTomer Tayar resc_info.res_id = qed_hw_get_mfw_res_id(res_id); 16772edbff8dSTomer Tayar if (resc_info.res_id == RESOURCE_NUM_INVALID) { 16782edbff8dSTomer Tayar DP_ERR(p_hwfn, 16792edbff8dSTomer Tayar "Failed to match resource %d [%s] with the MFW resources\n", 16802edbff8dSTomer Tayar res_id, qed_hw_get_resc_name(res_id)); 16812edbff8dSTomer Tayar return -EINVAL; 16822edbff8dSTomer Tayar } 16832edbff8dSTomer Tayar 16842edbff8dSTomer Tayar rc = qed_mcp_get_resc_info(p_hwfn, p_hwfn->p_main_ptt, &resc_info, 16852edbff8dSTomer Tayar &mcp_resp, &mcp_param); 16862edbff8dSTomer Tayar if (rc) { 16872edbff8dSTomer Tayar DP_NOTICE(p_hwfn, 16882edbff8dSTomer Tayar "MFW response failure for an allocation request for resource %d [%s]\n", 16892edbff8dSTomer Tayar res_id, qed_hw_get_resc_name(res_id)); 16902edbff8dSTomer Tayar return rc; 16912edbff8dSTomer Tayar } 16922edbff8dSTomer Tayar 16932edbff8dSTomer Tayar /* Default driver values are applied in the following cases: 16942edbff8dSTomer Tayar * - The resource allocation MB command is not supported by the MFW 16952edbff8dSTomer Tayar * - There is an internal error in the MFW while processing the request 16962edbff8dSTomer Tayar * - The resource ID is unknown to the MFW 16972edbff8dSTomer Tayar */ 16982edbff8dSTomer Tayar if (mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_OK && 16992edbff8dSTomer Tayar mcp_resp != FW_MSG_CODE_RESOURCE_ALLOC_DEPRECATED) { 17002edbff8dSTomer Tayar DP_NOTICE(p_hwfn, 17012edbff8dSTomer Tayar "Resource %d [%s]: No allocation info was received [mcp_resp 0x%x]. Applying default values [num %d, start %d].\n", 17022edbff8dSTomer Tayar res_id, 17032edbff8dSTomer Tayar qed_hw_get_resc_name(res_id), 17042edbff8dSTomer Tayar mcp_resp, dflt_resc_num, dflt_resc_start); 17052edbff8dSTomer Tayar *p_resc_num = dflt_resc_num; 17062edbff8dSTomer Tayar *p_resc_start = dflt_resc_start; 17072edbff8dSTomer Tayar goto out; 17082edbff8dSTomer Tayar } 17092edbff8dSTomer Tayar 17102edbff8dSTomer Tayar /* Special handling for status blocks; Would be revised in future */ 17112edbff8dSTomer Tayar if (res_id == QED_SB) { 17122edbff8dSTomer Tayar resc_info.size -= 1; 17132edbff8dSTomer Tayar resc_info.offset -= p_hwfn->enabled_func_idx; 17142edbff8dSTomer Tayar } 17152edbff8dSTomer Tayar 17162edbff8dSTomer Tayar *p_resc_num = resc_info.size; 17172edbff8dSTomer Tayar *p_resc_start = resc_info.offset; 17182edbff8dSTomer Tayar 17192edbff8dSTomer Tayar out: 17202edbff8dSTomer Tayar /* PQs have to divide by 8 [that's the HW granularity]. 17212edbff8dSTomer Tayar * Reduce number so it would fit. 17222edbff8dSTomer Tayar */ 17232edbff8dSTomer Tayar if ((res_id == QED_PQ) && ((*p_resc_num % 8) || (*p_resc_start % 8))) { 17242edbff8dSTomer Tayar DP_INFO(p_hwfn, 17252edbff8dSTomer Tayar "PQs need to align by 8; Number %08x --> %08x, Start %08x --> %08x\n", 17262edbff8dSTomer Tayar *p_resc_num, 17272edbff8dSTomer Tayar (*p_resc_num) & ~0x7, 17282edbff8dSTomer Tayar *p_resc_start, (*p_resc_start) & ~0x7); 17292edbff8dSTomer Tayar *p_resc_num &= ~0x7; 17302edbff8dSTomer Tayar *p_resc_start &= ~0x7; 17312edbff8dSTomer Tayar } 17322edbff8dSTomer Tayar 17332edbff8dSTomer Tayar return 0; 17342edbff8dSTomer Tayar } 17352edbff8dSTomer Tayar 1736dbb799c3SYuval Mintz static int qed_hw_get_resc(struct qed_hwfn *p_hwfn) 1737fe56b9e6SYuval Mintz { 17382edbff8dSTomer Tayar u8 res_id; 17392edbff8dSTomer Tayar int rc; 1740fe56b9e6SYuval Mintz 17412edbff8dSTomer Tayar for (res_id = 0; res_id < QED_MAX_RESC; res_id++) { 17422edbff8dSTomer Tayar rc = qed_hw_set_resc_info(p_hwfn, res_id); 17432edbff8dSTomer Tayar if (rc) 17442edbff8dSTomer Tayar return rc; 17452edbff8dSTomer Tayar } 1746dbb799c3SYuval Mintz 1747dbb799c3SYuval Mintz /* Sanity for ILT */ 17482edbff8dSTomer Tayar if ((RESC_END(p_hwfn, QED_ILT) > PXP_NUM_ILT_RECORDS_BB)) { 1749dbb799c3SYuval Mintz DP_NOTICE(p_hwfn, "Can't assign ILT pages [%08x,...,%08x]\n", 1750dbb799c3SYuval Mintz RESC_START(p_hwfn, QED_ILT), 1751dbb799c3SYuval Mintz RESC_END(p_hwfn, QED_ILT) - 1); 1752dbb799c3SYuval Mintz return -EINVAL; 1753dbb799c3SYuval Mintz } 1754fe56b9e6SYuval Mintz 175525c089d7SYuval Mintz qed_hw_set_feat(p_hwfn); 175625c089d7SYuval Mintz 1757fe56b9e6SYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, 17582edbff8dSTomer Tayar "The numbers for each resource are:\n"); 17592edbff8dSTomer Tayar for (res_id = 0; res_id < QED_MAX_RESC; res_id++) 17602edbff8dSTomer Tayar DP_VERBOSE(p_hwfn, NETIF_MSG_PROBE, "%s = %d start = %d\n", 17612edbff8dSTomer Tayar qed_hw_get_resc_name(res_id), 17622edbff8dSTomer Tayar RESC_NUM(p_hwfn, res_id), 17632edbff8dSTomer Tayar RESC_START(p_hwfn, res_id)); 1764dbb799c3SYuval Mintz 1765dbb799c3SYuval Mintz return 0; 1766fe56b9e6SYuval Mintz } 1767fe56b9e6SYuval Mintz 17681a635e48SYuval Mintz static int qed_hw_get_nvm_info(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1769fe56b9e6SYuval Mintz { 1770cc875c2eSYuval Mintz u32 nvm_cfg1_offset, mf_mode, addr, generic_cont0, core_cfg; 1771fc48b7a6SYuval Mintz u32 port_cfg_addr, link_temp, nvm_cfg_addr, device_capabilities; 1772cc875c2eSYuval Mintz struct qed_mcp_link_params *link; 1773fe56b9e6SYuval Mintz 1774fe56b9e6SYuval Mintz /* Read global nvm_cfg address */ 1775fe56b9e6SYuval Mintz nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0); 1776fe56b9e6SYuval Mintz 1777fe56b9e6SYuval Mintz /* Verify MCP has initialized it */ 1778fe56b9e6SYuval Mintz if (!nvm_cfg_addr) { 1779fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Shared memory not initialized\n"); 1780fe56b9e6SYuval Mintz return -EINVAL; 1781fe56b9e6SYuval Mintz } 1782fe56b9e6SYuval Mintz 1783fe56b9e6SYuval Mintz /* Read nvm_cfg1 (Notice this is just offset, and not offsize (TBD) */ 1784fe56b9e6SYuval Mintz nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4); 1785fe56b9e6SYuval Mintz 1786cc875c2eSYuval Mintz addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1787cc875c2eSYuval Mintz offsetof(struct nvm_cfg1, glob) + 1788cc875c2eSYuval Mintz offsetof(struct nvm_cfg1_glob, core_cfg); 1789cc875c2eSYuval Mintz 1790cc875c2eSYuval Mintz core_cfg = qed_rd(p_hwfn, p_ptt, addr); 1791cc875c2eSYuval Mintz 1792cc875c2eSYuval Mintz switch ((core_cfg & NVM_CFG1_GLOB_NETWORK_PORT_MODE_MASK) >> 1793cc875c2eSYuval Mintz NVM_CFG1_GLOB_NETWORK_PORT_MODE_OFFSET) { 1794351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_2X40G: 1795cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X40G; 1796cc875c2eSYuval Mintz break; 1797351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X50G: 1798cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X50G; 1799cc875c2eSYuval Mintz break; 1800351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_1X100G: 1801cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X100G; 1802cc875c2eSYuval Mintz break; 1803351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_4X10G_F: 1804cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_F; 1805cc875c2eSYuval Mintz break; 1806351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X10G_E: 1807cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X10G_E; 1808cc875c2eSYuval Mintz break; 1809351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_BB_4X20G: 1810cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_4X20G; 1811cc875c2eSYuval Mintz break; 1812351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X40G: 1813cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X40G; 1814cc875c2eSYuval Mintz break; 1815351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_2X25G: 1816cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_2X25G; 1817cc875c2eSYuval Mintz break; 1818351a4dedSYuval Mintz case NVM_CFG1_GLOB_NETWORK_PORT_MODE_1X25G: 1819cc875c2eSYuval Mintz p_hwfn->hw_info.port_mode = QED_PORT_MODE_DE_1X25G; 1820cc875c2eSYuval Mintz break; 1821cc875c2eSYuval Mintz default: 18221a635e48SYuval Mintz DP_NOTICE(p_hwfn, "Unknown port mode in 0x%08x\n", core_cfg); 1823cc875c2eSYuval Mintz break; 1824cc875c2eSYuval Mintz } 1825cc875c2eSYuval Mintz 1826cc875c2eSYuval Mintz /* Read default link configuration */ 1827cc875c2eSYuval Mintz link = &p_hwfn->mcp_info->link_input; 1828cc875c2eSYuval Mintz port_cfg_addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1829cc875c2eSYuval Mintz offsetof(struct nvm_cfg1, port[MFW_PORT(p_hwfn)]); 1830cc875c2eSYuval Mintz link_temp = qed_rd(p_hwfn, p_ptt, 1831cc875c2eSYuval Mintz port_cfg_addr + 1832cc875c2eSYuval Mintz offsetof(struct nvm_cfg1_port, speed_cap_mask)); 183383aeb933SYuval Mintz link_temp &= NVM_CFG1_PORT_DRV_SPEED_CAPABILITY_MASK_MASK; 183483aeb933SYuval Mintz link->speed.advertised_speeds = link_temp; 1835cc875c2eSYuval Mintz 183683aeb933SYuval Mintz link_temp = link->speed.advertised_speeds; 183783aeb933SYuval Mintz p_hwfn->mcp_info->link_capabilities.speed_capabilities = link_temp; 1838cc875c2eSYuval Mintz 1839cc875c2eSYuval Mintz link_temp = qed_rd(p_hwfn, p_ptt, 1840cc875c2eSYuval Mintz port_cfg_addr + 1841cc875c2eSYuval Mintz offsetof(struct nvm_cfg1_port, link_settings)); 1842cc875c2eSYuval Mintz switch ((link_temp & NVM_CFG1_PORT_DRV_LINK_SPEED_MASK) >> 1843cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_LINK_SPEED_OFFSET) { 1844cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_AUTONEG: 1845cc875c2eSYuval Mintz link->speed.autoneg = true; 1846cc875c2eSYuval Mintz break; 1847cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_1G: 1848cc875c2eSYuval Mintz link->speed.forced_speed = 1000; 1849cc875c2eSYuval Mintz break; 1850cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_10G: 1851cc875c2eSYuval Mintz link->speed.forced_speed = 10000; 1852cc875c2eSYuval Mintz break; 1853cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_25G: 1854cc875c2eSYuval Mintz link->speed.forced_speed = 25000; 1855cc875c2eSYuval Mintz break; 1856cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_40G: 1857cc875c2eSYuval Mintz link->speed.forced_speed = 40000; 1858cc875c2eSYuval Mintz break; 1859cc875c2eSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_50G: 1860cc875c2eSYuval Mintz link->speed.forced_speed = 50000; 1861cc875c2eSYuval Mintz break; 1862351a4dedSYuval Mintz case NVM_CFG1_PORT_DRV_LINK_SPEED_BB_100G: 1863cc875c2eSYuval Mintz link->speed.forced_speed = 100000; 1864cc875c2eSYuval Mintz break; 1865cc875c2eSYuval Mintz default: 18661a635e48SYuval Mintz DP_NOTICE(p_hwfn, "Unknown Speed in 0x%08x\n", link_temp); 1867cc875c2eSYuval Mintz } 1868cc875c2eSYuval Mintz 1869cc875c2eSYuval Mintz link_temp &= NVM_CFG1_PORT_DRV_FLOW_CONTROL_MASK; 1870cc875c2eSYuval Mintz link_temp >>= NVM_CFG1_PORT_DRV_FLOW_CONTROL_OFFSET; 1871cc875c2eSYuval Mintz link->pause.autoneg = !!(link_temp & 1872cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_FLOW_CONTROL_AUTONEG); 1873cc875c2eSYuval Mintz link->pause.forced_rx = !!(link_temp & 1874cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_FLOW_CONTROL_RX); 1875cc875c2eSYuval Mintz link->pause.forced_tx = !!(link_temp & 1876cc875c2eSYuval Mintz NVM_CFG1_PORT_DRV_FLOW_CONTROL_TX); 1877cc875c2eSYuval Mintz link->loopback_mode = 0; 1878cc875c2eSYuval Mintz 1879cc875c2eSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 1880cc875c2eSYuval Mintz "Read default link: Speed 0x%08x, Adv. Speed 0x%08x, AN: 0x%02x, PAUSE AN: 0x%02x\n", 1881cc875c2eSYuval Mintz link->speed.forced_speed, link->speed.advertised_speeds, 1882cc875c2eSYuval Mintz link->speed.autoneg, link->pause.autoneg); 1883cc875c2eSYuval Mintz 1884fe56b9e6SYuval Mintz /* Read Multi-function information from shmem */ 1885fe56b9e6SYuval Mintz addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1886fe56b9e6SYuval Mintz offsetof(struct nvm_cfg1, glob) + 1887fe56b9e6SYuval Mintz offsetof(struct nvm_cfg1_glob, generic_cont0); 1888fe56b9e6SYuval Mintz 1889fe56b9e6SYuval Mintz generic_cont0 = qed_rd(p_hwfn, p_ptt, addr); 1890fe56b9e6SYuval Mintz 1891fe56b9e6SYuval Mintz mf_mode = (generic_cont0 & NVM_CFG1_GLOB_MF_MODE_MASK) >> 1892fe56b9e6SYuval Mintz NVM_CFG1_GLOB_MF_MODE_OFFSET; 1893fe56b9e6SYuval Mintz 1894fe56b9e6SYuval Mintz switch (mf_mode) { 1895fe56b9e6SYuval Mintz case NVM_CFG1_GLOB_MF_MODE_MF_ALLOWED: 1896fc48b7a6SYuval Mintz p_hwfn->cdev->mf_mode = QED_MF_OVLAN; 1897fe56b9e6SYuval Mintz break; 1898fe56b9e6SYuval Mintz case NVM_CFG1_GLOB_MF_MODE_NPAR1_0: 1899fc48b7a6SYuval Mintz p_hwfn->cdev->mf_mode = QED_MF_NPAR; 1900fe56b9e6SYuval Mintz break; 1901fc48b7a6SYuval Mintz case NVM_CFG1_GLOB_MF_MODE_DEFAULT: 1902fc48b7a6SYuval Mintz p_hwfn->cdev->mf_mode = QED_MF_DEFAULT; 1903fe56b9e6SYuval Mintz break; 1904fe56b9e6SYuval Mintz } 1905fe56b9e6SYuval Mintz DP_INFO(p_hwfn, "Multi function mode is %08x\n", 1906fe56b9e6SYuval Mintz p_hwfn->cdev->mf_mode); 1907fe56b9e6SYuval Mintz 1908fc48b7a6SYuval Mintz /* Read Multi-function information from shmem */ 1909fc48b7a6SYuval Mintz addr = MCP_REG_SCRATCH + nvm_cfg1_offset + 1910fc48b7a6SYuval Mintz offsetof(struct nvm_cfg1, glob) + 1911fc48b7a6SYuval Mintz offsetof(struct nvm_cfg1_glob, device_capabilities); 1912fc48b7a6SYuval Mintz 1913fc48b7a6SYuval Mintz device_capabilities = qed_rd(p_hwfn, p_ptt, addr); 1914fc48b7a6SYuval Mintz if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ETHERNET) 1915fc48b7a6SYuval Mintz __set_bit(QED_DEV_CAP_ETH, 1916fc48b7a6SYuval Mintz &p_hwfn->hw_info.device_capabilities); 1917c5ac9319SYuval Mintz if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ISCSI) 1918c5ac9319SYuval Mintz __set_bit(QED_DEV_CAP_ISCSI, 1919c5ac9319SYuval Mintz &p_hwfn->hw_info.device_capabilities); 1920c5ac9319SYuval Mintz if (device_capabilities & NVM_CFG1_GLOB_DEVICE_CAPABILITIES_ROCE) 1921c5ac9319SYuval Mintz __set_bit(QED_DEV_CAP_ROCE, 1922c5ac9319SYuval Mintz &p_hwfn->hw_info.device_capabilities); 1923fc48b7a6SYuval Mintz 1924fe56b9e6SYuval Mintz return qed_mcp_fill_shmem_func_info(p_hwfn, p_ptt); 1925fe56b9e6SYuval Mintz } 1926fe56b9e6SYuval Mintz 19271408cc1fSYuval Mintz static void qed_get_num_funcs(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 19281408cc1fSYuval Mintz { 1929dbb799c3SYuval Mintz u8 num_funcs, enabled_func_idx = p_hwfn->rel_pf_id; 1930dbb799c3SYuval Mintz u32 reg_function_hide, tmp, eng_mask, low_pfs_mask; 19311408cc1fSYuval Mintz 19321408cc1fSYuval Mintz num_funcs = MAX_NUM_PFS_BB; 19331408cc1fSYuval Mintz 19341408cc1fSYuval Mintz /* Bit 0 of MISCS_REG_FUNCTION_HIDE indicates whether the bypass values 19351408cc1fSYuval Mintz * in the other bits are selected. 19361408cc1fSYuval Mintz * Bits 1-15 are for functions 1-15, respectively, and their value is 19371408cc1fSYuval Mintz * '0' only for enabled functions (function 0 always exists and 19381408cc1fSYuval Mintz * enabled). 19391408cc1fSYuval Mintz * In case of CMT, only the "even" functions are enabled, and thus the 19401408cc1fSYuval Mintz * number of functions for both hwfns is learnt from the same bits. 19411408cc1fSYuval Mintz */ 19421408cc1fSYuval Mintz reg_function_hide = qed_rd(p_hwfn, p_ptt, MISCS_REG_FUNCTION_HIDE); 19431408cc1fSYuval Mintz 19441408cc1fSYuval Mintz if (reg_function_hide & 0x1) { 19451408cc1fSYuval Mintz if (QED_PATH_ID(p_hwfn) && p_hwfn->cdev->num_hwfns == 1) { 19461408cc1fSYuval Mintz num_funcs = 0; 19471408cc1fSYuval Mintz eng_mask = 0xaaaa; 19481408cc1fSYuval Mintz } else { 19491408cc1fSYuval Mintz num_funcs = 1; 19501408cc1fSYuval Mintz eng_mask = 0x5554; 19511408cc1fSYuval Mintz } 19521408cc1fSYuval Mintz 19531408cc1fSYuval Mintz /* Get the number of the enabled functions on the engine */ 19541408cc1fSYuval Mintz tmp = (reg_function_hide ^ 0xffffffff) & eng_mask; 19551408cc1fSYuval Mintz while (tmp) { 19561408cc1fSYuval Mintz if (tmp & 0x1) 19571408cc1fSYuval Mintz num_funcs++; 19581408cc1fSYuval Mintz tmp >>= 0x1; 19591408cc1fSYuval Mintz } 1960dbb799c3SYuval Mintz 1961dbb799c3SYuval Mintz /* Get the PF index within the enabled functions */ 1962dbb799c3SYuval Mintz low_pfs_mask = (0x1 << p_hwfn->abs_pf_id) - 1; 1963dbb799c3SYuval Mintz tmp = reg_function_hide & eng_mask & low_pfs_mask; 1964dbb799c3SYuval Mintz while (tmp) { 1965dbb799c3SYuval Mintz if (tmp & 0x1) 1966dbb799c3SYuval Mintz enabled_func_idx--; 1967dbb799c3SYuval Mintz tmp >>= 0x1; 1968dbb799c3SYuval Mintz } 19691408cc1fSYuval Mintz } 19701408cc1fSYuval Mintz 19711408cc1fSYuval Mintz p_hwfn->num_funcs_on_engine = num_funcs; 1972dbb799c3SYuval Mintz p_hwfn->enabled_func_idx = enabled_func_idx; 19731408cc1fSYuval Mintz 19741408cc1fSYuval Mintz DP_VERBOSE(p_hwfn, 19751408cc1fSYuval Mintz NETIF_MSG_PROBE, 1976525ef5c0SYuval Mintz "PF [rel_id %d, abs_id %d] occupies index %d within the %d enabled functions on the engine\n", 19771408cc1fSYuval Mintz p_hwfn->rel_pf_id, 19781408cc1fSYuval Mintz p_hwfn->abs_pf_id, 1979525ef5c0SYuval Mintz p_hwfn->enabled_func_idx, p_hwfn->num_funcs_on_engine); 19801408cc1fSYuval Mintz } 19811408cc1fSYuval Mintz 1982fe56b9e6SYuval Mintz static int 1983fe56b9e6SYuval Mintz qed_get_hw_info(struct qed_hwfn *p_hwfn, 1984fe56b9e6SYuval Mintz struct qed_ptt *p_ptt, 1985fe56b9e6SYuval Mintz enum qed_pci_personality personality) 1986fe56b9e6SYuval Mintz { 1987fe56b9e6SYuval Mintz u32 port_mode; 1988fe56b9e6SYuval Mintz int rc; 1989fe56b9e6SYuval Mintz 199032a47e72SYuval Mintz /* Since all information is common, only first hwfns should do this */ 199132a47e72SYuval Mintz if (IS_LEAD_HWFN(p_hwfn)) { 199232a47e72SYuval Mintz rc = qed_iov_hw_info(p_hwfn); 199332a47e72SYuval Mintz if (rc) 199432a47e72SYuval Mintz return rc; 199532a47e72SYuval Mintz } 199632a47e72SYuval Mintz 1997fe56b9e6SYuval Mintz /* Read the port mode */ 1998fe56b9e6SYuval Mintz port_mode = qed_rd(p_hwfn, p_ptt, 1999fe56b9e6SYuval Mintz CNIG_REG_NW_PORT_MODE_BB_B0); 2000fe56b9e6SYuval Mintz 2001fe56b9e6SYuval Mintz if (port_mode < 3) { 2002fe56b9e6SYuval Mintz p_hwfn->cdev->num_ports_in_engines = 1; 2003fe56b9e6SYuval Mintz } else if (port_mode <= 5) { 2004fe56b9e6SYuval Mintz p_hwfn->cdev->num_ports_in_engines = 2; 2005fe56b9e6SYuval Mintz } else { 2006fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "PORT MODE: %d not supported\n", 2007fe56b9e6SYuval Mintz p_hwfn->cdev->num_ports_in_engines); 2008fe56b9e6SYuval Mintz 2009fe56b9e6SYuval Mintz /* Default num_ports_in_engines to something */ 2010fe56b9e6SYuval Mintz p_hwfn->cdev->num_ports_in_engines = 1; 2011fe56b9e6SYuval Mintz } 2012fe56b9e6SYuval Mintz 2013fe56b9e6SYuval Mintz qed_hw_get_nvm_info(p_hwfn, p_ptt); 2014fe56b9e6SYuval Mintz 2015fe56b9e6SYuval Mintz rc = qed_int_igu_read_cam(p_hwfn, p_ptt); 2016fe56b9e6SYuval Mintz if (rc) 2017fe56b9e6SYuval Mintz return rc; 2018fe56b9e6SYuval Mintz 2019fe56b9e6SYuval Mintz if (qed_mcp_is_init(p_hwfn)) 2020fe56b9e6SYuval Mintz ether_addr_copy(p_hwfn->hw_info.hw_mac_addr, 2021fe56b9e6SYuval Mintz p_hwfn->mcp_info->func_info.mac); 2022fe56b9e6SYuval Mintz else 2023fe56b9e6SYuval Mintz eth_random_addr(p_hwfn->hw_info.hw_mac_addr); 2024fe56b9e6SYuval Mintz 2025fe56b9e6SYuval Mintz if (qed_mcp_is_init(p_hwfn)) { 2026fe56b9e6SYuval Mintz if (p_hwfn->mcp_info->func_info.ovlan != QED_MCP_VLAN_UNSET) 2027fe56b9e6SYuval Mintz p_hwfn->hw_info.ovlan = 2028fe56b9e6SYuval Mintz p_hwfn->mcp_info->func_info.ovlan; 2029fe56b9e6SYuval Mintz 2030fe56b9e6SYuval Mintz qed_mcp_cmd_port_init(p_hwfn, p_ptt); 2031fe56b9e6SYuval Mintz } 2032fe56b9e6SYuval Mintz 2033fe56b9e6SYuval Mintz if (qed_mcp_is_init(p_hwfn)) { 2034fe56b9e6SYuval Mintz enum qed_pci_personality protocol; 2035fe56b9e6SYuval Mintz 2036fe56b9e6SYuval Mintz protocol = p_hwfn->mcp_info->func_info.protocol; 2037fe56b9e6SYuval Mintz p_hwfn->hw_info.personality = protocol; 2038fe56b9e6SYuval Mintz } 2039fe56b9e6SYuval Mintz 20401408cc1fSYuval Mintz qed_get_num_funcs(p_hwfn, p_ptt); 20411408cc1fSYuval Mintz 20420fefbfbaSSudarsana Kalluru if (qed_mcp_is_init(p_hwfn)) 20430fefbfbaSSudarsana Kalluru p_hwfn->hw_info.mtu = p_hwfn->mcp_info->func_info.mtu; 20440fefbfbaSSudarsana Kalluru 2045dbb799c3SYuval Mintz return qed_hw_get_resc(p_hwfn); 2046fe56b9e6SYuval Mintz } 2047fe56b9e6SYuval Mintz 204812e09c69SYuval Mintz static int qed_get_dev_info(struct qed_dev *cdev) 2049fe56b9e6SYuval Mintz { 2050fc48b7a6SYuval Mintz struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2051fe56b9e6SYuval Mintz u32 tmp; 2052fe56b9e6SYuval Mintz 2053fc48b7a6SYuval Mintz /* Read Vendor Id / Device Id */ 20541a635e48SYuval Mintz pci_read_config_word(cdev->pdev, PCI_VENDOR_ID, &cdev->vendor_id); 20551a635e48SYuval Mintz pci_read_config_word(cdev->pdev, PCI_DEVICE_ID, &cdev->device_id); 20561a635e48SYuval Mintz 2057fc48b7a6SYuval Mintz cdev->chip_num = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, 2058fe56b9e6SYuval Mintz MISCS_REG_CHIP_NUM); 2059fc48b7a6SYuval Mintz cdev->chip_rev = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, 2060fe56b9e6SYuval Mintz MISCS_REG_CHIP_REV); 2061fe56b9e6SYuval Mintz MASK_FIELD(CHIP_REV, cdev->chip_rev); 2062fe56b9e6SYuval Mintz 2063fc48b7a6SYuval Mintz cdev->type = QED_DEV_TYPE_BB; 2064fe56b9e6SYuval Mintz /* Learn number of HW-functions */ 2065fc48b7a6SYuval Mintz tmp = qed_rd(p_hwfn, p_hwfn->p_main_ptt, 2066fe56b9e6SYuval Mintz MISCS_REG_CMT_ENABLED_FOR_PAIR); 2067fe56b9e6SYuval Mintz 2068fc48b7a6SYuval Mintz if (tmp & (1 << p_hwfn->rel_pf_id)) { 2069fe56b9e6SYuval Mintz DP_NOTICE(cdev->hwfns, "device in CMT mode\n"); 2070fe56b9e6SYuval Mintz cdev->num_hwfns = 2; 2071fe56b9e6SYuval Mintz } else { 2072fe56b9e6SYuval Mintz cdev->num_hwfns = 1; 2073fe56b9e6SYuval Mintz } 2074fe56b9e6SYuval Mintz 2075fc48b7a6SYuval Mintz cdev->chip_bond_id = qed_rd(p_hwfn, p_hwfn->p_main_ptt, 2076fe56b9e6SYuval Mintz MISCS_REG_CHIP_TEST_REG) >> 4; 2077fe56b9e6SYuval Mintz MASK_FIELD(CHIP_BOND_ID, cdev->chip_bond_id); 2078fc48b7a6SYuval Mintz cdev->chip_metal = (u16)qed_rd(p_hwfn, p_hwfn->p_main_ptt, 2079fe56b9e6SYuval Mintz MISCS_REG_CHIP_METAL); 2080fe56b9e6SYuval Mintz MASK_FIELD(CHIP_METAL, cdev->chip_metal); 2081fe56b9e6SYuval Mintz 2082fe56b9e6SYuval Mintz DP_INFO(cdev->hwfns, 2083fe56b9e6SYuval Mintz "Chip details - Num: %04x Rev: %04x Bond id: %04x Metal: %04x\n", 2084fe56b9e6SYuval Mintz cdev->chip_num, cdev->chip_rev, 2085fe56b9e6SYuval Mintz cdev->chip_bond_id, cdev->chip_metal); 208612e09c69SYuval Mintz 208712e09c69SYuval Mintz if (QED_IS_BB(cdev) && CHIP_REV_IS_A0(cdev)) { 208812e09c69SYuval Mintz DP_NOTICE(cdev->hwfns, 208912e09c69SYuval Mintz "The chip type/rev (BB A0) is not supported!\n"); 209012e09c69SYuval Mintz return -EINVAL; 209112e09c69SYuval Mintz } 209212e09c69SYuval Mintz 209312e09c69SYuval Mintz return 0; 2094fe56b9e6SYuval Mintz } 2095fe56b9e6SYuval Mintz 2096fe56b9e6SYuval Mintz static int qed_hw_prepare_single(struct qed_hwfn *p_hwfn, 2097fe56b9e6SYuval Mintz void __iomem *p_regview, 2098fe56b9e6SYuval Mintz void __iomem *p_doorbells, 2099fe56b9e6SYuval Mintz enum qed_pci_personality personality) 2100fe56b9e6SYuval Mintz { 2101fe56b9e6SYuval Mintz int rc = 0; 2102fe56b9e6SYuval Mintz 2103fe56b9e6SYuval Mintz /* Split PCI bars evenly between hwfns */ 2104fe56b9e6SYuval Mintz p_hwfn->regview = p_regview; 2105fe56b9e6SYuval Mintz p_hwfn->doorbells = p_doorbells; 2106fe56b9e6SYuval Mintz 21071408cc1fSYuval Mintz if (IS_VF(p_hwfn->cdev)) 21081408cc1fSYuval Mintz return qed_vf_hw_prepare(p_hwfn); 21091408cc1fSYuval Mintz 2110fe56b9e6SYuval Mintz /* Validate that chip access is feasible */ 2111fe56b9e6SYuval Mintz if (REG_RD(p_hwfn, PXP_PF_ME_OPAQUE_ADDR) == 0xffffffff) { 2112fe56b9e6SYuval Mintz DP_ERR(p_hwfn, 2113fe56b9e6SYuval Mintz "Reading the ME register returns all Fs; Preventing further chip access\n"); 2114fe56b9e6SYuval Mintz return -EINVAL; 2115fe56b9e6SYuval Mintz } 2116fe56b9e6SYuval Mintz 2117fe56b9e6SYuval Mintz get_function_id(p_hwfn); 2118fe56b9e6SYuval Mintz 211912e09c69SYuval Mintz /* Allocate PTT pool */ 212012e09c69SYuval Mintz rc = qed_ptt_pool_alloc(p_hwfn); 21212591c280SJoe Perches if (rc) 2122fe56b9e6SYuval Mintz goto err0; 2123fe56b9e6SYuval Mintz 212412e09c69SYuval Mintz /* Allocate the main PTT */ 212512e09c69SYuval Mintz p_hwfn->p_main_ptt = qed_get_reserved_ptt(p_hwfn, RESERVED_PTT_MAIN); 212612e09c69SYuval Mintz 2127fe56b9e6SYuval Mintz /* First hwfn learns basic information, e.g., number of hwfns */ 212812e09c69SYuval Mintz if (!p_hwfn->my_id) { 212912e09c69SYuval Mintz rc = qed_get_dev_info(p_hwfn->cdev); 21301a635e48SYuval Mintz if (rc) 213112e09c69SYuval Mintz goto err1; 213212e09c69SYuval Mintz } 213312e09c69SYuval Mintz 213412e09c69SYuval Mintz qed_hw_hwfn_prepare(p_hwfn); 2135fe56b9e6SYuval Mintz 2136fe56b9e6SYuval Mintz /* Initialize MCP structure */ 2137fe56b9e6SYuval Mintz rc = qed_mcp_cmd_init(p_hwfn, p_hwfn->p_main_ptt); 2138fe56b9e6SYuval Mintz if (rc) { 2139fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed initializing mcp command\n"); 2140fe56b9e6SYuval Mintz goto err1; 2141fe56b9e6SYuval Mintz } 2142fe56b9e6SYuval Mintz 2143fe56b9e6SYuval Mintz /* Read the device configuration information from the HW and SHMEM */ 2144fe56b9e6SYuval Mintz rc = qed_get_hw_info(p_hwfn, p_hwfn->p_main_ptt, personality); 2145fe56b9e6SYuval Mintz if (rc) { 2146fe56b9e6SYuval Mintz DP_NOTICE(p_hwfn, "Failed to get HW information\n"); 2147fe56b9e6SYuval Mintz goto err2; 2148fe56b9e6SYuval Mintz } 2149fe56b9e6SYuval Mintz 2150fe56b9e6SYuval Mintz /* Allocate the init RT array and initialize the init-ops engine */ 2151fe56b9e6SYuval Mintz rc = qed_init_alloc(p_hwfn); 21522591c280SJoe Perches if (rc) 2153fe56b9e6SYuval Mintz goto err2; 2154fe56b9e6SYuval Mintz 2155fe56b9e6SYuval Mintz return rc; 2156fe56b9e6SYuval Mintz err2: 215732a47e72SYuval Mintz if (IS_LEAD_HWFN(p_hwfn)) 215832a47e72SYuval Mintz qed_iov_free_hw_info(p_hwfn->cdev); 2159fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 2160fe56b9e6SYuval Mintz err1: 2161fe56b9e6SYuval Mintz qed_hw_hwfn_free(p_hwfn); 2162fe56b9e6SYuval Mintz err0: 2163fe56b9e6SYuval Mintz return rc; 2164fe56b9e6SYuval Mintz } 2165fe56b9e6SYuval Mintz 2166fe56b9e6SYuval Mintz int qed_hw_prepare(struct qed_dev *cdev, 2167fe56b9e6SYuval Mintz int personality) 2168fe56b9e6SYuval Mintz { 2169c78df14eSAriel Elior struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2170c78df14eSAriel Elior int rc; 2171fe56b9e6SYuval Mintz 2172fe56b9e6SYuval Mintz /* Store the precompiled init data ptrs */ 21731408cc1fSYuval Mintz if (IS_PF(cdev)) 2174fe56b9e6SYuval Mintz qed_init_iro_array(cdev); 2175fe56b9e6SYuval Mintz 2176fe56b9e6SYuval Mintz /* Initialize the first hwfn - will learn number of hwfns */ 2177c78df14eSAriel Elior rc = qed_hw_prepare_single(p_hwfn, 2178c78df14eSAriel Elior cdev->regview, 2179fe56b9e6SYuval Mintz cdev->doorbells, personality); 2180fe56b9e6SYuval Mintz if (rc) 2181fe56b9e6SYuval Mintz return rc; 2182fe56b9e6SYuval Mintz 2183c78df14eSAriel Elior personality = p_hwfn->hw_info.personality; 2184fe56b9e6SYuval Mintz 2185fe56b9e6SYuval Mintz /* Initialize the rest of the hwfns */ 2186c78df14eSAriel Elior if (cdev->num_hwfns > 1) { 2187fe56b9e6SYuval Mintz void __iomem *p_regview, *p_doorbell; 2188c78df14eSAriel Elior u8 __iomem *addr; 2189fe56b9e6SYuval Mintz 2190c78df14eSAriel Elior /* adjust bar offset for second engine */ 2191c2035eeaSRam Amrani addr = cdev->regview + qed_hw_bar_size(p_hwfn, BAR_ID_0) / 2; 2192c78df14eSAriel Elior p_regview = addr; 2193c78df14eSAriel Elior 2194c78df14eSAriel Elior /* adjust doorbell bar offset for second engine */ 2195c2035eeaSRam Amrani addr = cdev->doorbells + qed_hw_bar_size(p_hwfn, BAR_ID_1) / 2; 2196c78df14eSAriel Elior p_doorbell = addr; 2197c78df14eSAriel Elior 2198c78df14eSAriel Elior /* prepare second hw function */ 2199c78df14eSAriel Elior rc = qed_hw_prepare_single(&cdev->hwfns[1], p_regview, 2200fe56b9e6SYuval Mintz p_doorbell, personality); 2201c78df14eSAriel Elior 2202c78df14eSAriel Elior /* in case of error, need to free the previously 2203c78df14eSAriel Elior * initiliazed hwfn 0. 2204c78df14eSAriel Elior */ 2205fe56b9e6SYuval Mintz if (rc) { 22061408cc1fSYuval Mintz if (IS_PF(cdev)) { 2207c78df14eSAriel Elior qed_init_free(p_hwfn); 2208c78df14eSAriel Elior qed_mcp_free(p_hwfn); 2209c78df14eSAriel Elior qed_hw_hwfn_free(p_hwfn); 2210fe56b9e6SYuval Mintz } 2211fe56b9e6SYuval Mintz } 22121408cc1fSYuval Mintz } 2213fe56b9e6SYuval Mintz 2214c78df14eSAriel Elior return rc; 2215fe56b9e6SYuval Mintz } 2216fe56b9e6SYuval Mintz 2217fe56b9e6SYuval Mintz void qed_hw_remove(struct qed_dev *cdev) 2218fe56b9e6SYuval Mintz { 22190fefbfbaSSudarsana Kalluru struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev); 2220fe56b9e6SYuval Mintz int i; 2221fe56b9e6SYuval Mintz 22220fefbfbaSSudarsana Kalluru if (IS_PF(cdev)) 22230fefbfbaSSudarsana Kalluru qed_mcp_ov_update_driver_state(p_hwfn, p_hwfn->p_main_ptt, 22240fefbfbaSSudarsana Kalluru QED_OV_DRIVER_STATE_NOT_LOADED); 22250fefbfbaSSudarsana Kalluru 2226fe56b9e6SYuval Mintz for_each_hwfn(cdev, i) { 2227fe56b9e6SYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2228fe56b9e6SYuval Mintz 22291408cc1fSYuval Mintz if (IS_VF(cdev)) { 22300b55e27dSYuval Mintz qed_vf_pf_release(p_hwfn); 22311408cc1fSYuval Mintz continue; 22321408cc1fSYuval Mintz } 22331408cc1fSYuval Mintz 2234fe56b9e6SYuval Mintz qed_init_free(p_hwfn); 2235fe56b9e6SYuval Mintz qed_hw_hwfn_free(p_hwfn); 2236fe56b9e6SYuval Mintz qed_mcp_free(p_hwfn); 2237fe56b9e6SYuval Mintz } 223832a47e72SYuval Mintz 223932a47e72SYuval Mintz qed_iov_free_hw_info(cdev); 2240fe56b9e6SYuval Mintz } 2241fe56b9e6SYuval Mintz 2242a91eb52aSYuval Mintz static void qed_chain_free_next_ptr(struct qed_dev *cdev, 2243a91eb52aSYuval Mintz struct qed_chain *p_chain) 2244a91eb52aSYuval Mintz { 2245a91eb52aSYuval Mintz void *p_virt = p_chain->p_virt_addr, *p_virt_next = NULL; 2246a91eb52aSYuval Mintz dma_addr_t p_phys = p_chain->p_phys_addr, p_phys_next = 0; 2247a91eb52aSYuval Mintz struct qed_chain_next *p_next; 2248a91eb52aSYuval Mintz u32 size, i; 2249a91eb52aSYuval Mintz 2250a91eb52aSYuval Mintz if (!p_virt) 2251a91eb52aSYuval Mintz return; 2252a91eb52aSYuval Mintz 2253a91eb52aSYuval Mintz size = p_chain->elem_size * p_chain->usable_per_page; 2254a91eb52aSYuval Mintz 2255a91eb52aSYuval Mintz for (i = 0; i < p_chain->page_cnt; i++) { 2256a91eb52aSYuval Mintz if (!p_virt) 2257a91eb52aSYuval Mintz break; 2258a91eb52aSYuval Mintz 2259a91eb52aSYuval Mintz p_next = (struct qed_chain_next *)((u8 *)p_virt + size); 2260a91eb52aSYuval Mintz p_virt_next = p_next->next_virt; 2261a91eb52aSYuval Mintz p_phys_next = HILO_DMA_REGPAIR(p_next->next_phys); 2262a91eb52aSYuval Mintz 2263a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 2264a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, p_virt, p_phys); 2265a91eb52aSYuval Mintz 2266a91eb52aSYuval Mintz p_virt = p_virt_next; 2267a91eb52aSYuval Mintz p_phys = p_phys_next; 2268a91eb52aSYuval Mintz } 2269a91eb52aSYuval Mintz } 2270a91eb52aSYuval Mintz 2271a91eb52aSYuval Mintz static void qed_chain_free_single(struct qed_dev *cdev, 2272a91eb52aSYuval Mintz struct qed_chain *p_chain) 2273a91eb52aSYuval Mintz { 2274a91eb52aSYuval Mintz if (!p_chain->p_virt_addr) 2275a91eb52aSYuval Mintz return; 2276a91eb52aSYuval Mintz 2277a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 2278a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 2279a91eb52aSYuval Mintz p_chain->p_virt_addr, p_chain->p_phys_addr); 2280a91eb52aSYuval Mintz } 2281a91eb52aSYuval Mintz 2282a91eb52aSYuval Mintz static void qed_chain_free_pbl(struct qed_dev *cdev, struct qed_chain *p_chain) 2283a91eb52aSYuval Mintz { 2284a91eb52aSYuval Mintz void **pp_virt_addr_tbl = p_chain->pbl.pp_virt_addr_tbl; 2285a91eb52aSYuval Mintz u32 page_cnt = p_chain->page_cnt, i, pbl_size; 2286a91eb52aSYuval Mintz u8 *p_pbl_virt = p_chain->pbl.p_virt_table; 2287a91eb52aSYuval Mintz 2288a91eb52aSYuval Mintz if (!pp_virt_addr_tbl) 2289a91eb52aSYuval Mintz return; 2290a91eb52aSYuval Mintz 2291a91eb52aSYuval Mintz if (!p_chain->pbl.p_virt_table) 2292a91eb52aSYuval Mintz goto out; 2293a91eb52aSYuval Mintz 2294a91eb52aSYuval Mintz for (i = 0; i < page_cnt; i++) { 2295a91eb52aSYuval Mintz if (!pp_virt_addr_tbl[i]) 2296a91eb52aSYuval Mintz break; 2297a91eb52aSYuval Mintz 2298a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 2299a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 2300a91eb52aSYuval Mintz pp_virt_addr_tbl[i], 2301a91eb52aSYuval Mintz *(dma_addr_t *)p_pbl_virt); 2302a91eb52aSYuval Mintz 2303a91eb52aSYuval Mintz p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE; 2304a91eb52aSYuval Mintz } 2305a91eb52aSYuval Mintz 2306a91eb52aSYuval Mintz pbl_size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; 2307a91eb52aSYuval Mintz dma_free_coherent(&cdev->pdev->dev, 2308a91eb52aSYuval Mintz pbl_size, 2309a91eb52aSYuval Mintz p_chain->pbl.p_virt_table, p_chain->pbl.p_phys_table); 2310a91eb52aSYuval Mintz out: 2311a91eb52aSYuval Mintz vfree(p_chain->pbl.pp_virt_addr_tbl); 2312a91eb52aSYuval Mintz } 2313a91eb52aSYuval Mintz 2314a91eb52aSYuval Mintz void qed_chain_free(struct qed_dev *cdev, struct qed_chain *p_chain) 2315a91eb52aSYuval Mintz { 2316a91eb52aSYuval Mintz switch (p_chain->mode) { 2317a91eb52aSYuval Mintz case QED_CHAIN_MODE_NEXT_PTR: 2318a91eb52aSYuval Mintz qed_chain_free_next_ptr(cdev, p_chain); 2319a91eb52aSYuval Mintz break; 2320a91eb52aSYuval Mintz case QED_CHAIN_MODE_SINGLE: 2321a91eb52aSYuval Mintz qed_chain_free_single(cdev, p_chain); 2322a91eb52aSYuval Mintz break; 2323a91eb52aSYuval Mintz case QED_CHAIN_MODE_PBL: 2324a91eb52aSYuval Mintz qed_chain_free_pbl(cdev, p_chain); 2325a91eb52aSYuval Mintz break; 2326a91eb52aSYuval Mintz } 2327a91eb52aSYuval Mintz } 2328a91eb52aSYuval Mintz 2329a91eb52aSYuval Mintz static int 2330a91eb52aSYuval Mintz qed_chain_alloc_sanity_check(struct qed_dev *cdev, 2331a91eb52aSYuval Mintz enum qed_chain_cnt_type cnt_type, 2332a91eb52aSYuval Mintz size_t elem_size, u32 page_cnt) 2333a91eb52aSYuval Mintz { 2334a91eb52aSYuval Mintz u64 chain_size = ELEMS_PER_PAGE(elem_size) * page_cnt; 2335a91eb52aSYuval Mintz 2336a91eb52aSYuval Mintz /* The actual chain size can be larger than the maximal possible value 2337a91eb52aSYuval Mintz * after rounding up the requested elements number to pages, and after 2338a91eb52aSYuval Mintz * taking into acount the unusuable elements (next-ptr elements). 2339a91eb52aSYuval Mintz * The size of a "u16" chain can be (U16_MAX + 1) since the chain 2340a91eb52aSYuval Mintz * size/capacity fields are of a u32 type. 2341a91eb52aSYuval Mintz */ 2342a91eb52aSYuval Mintz if ((cnt_type == QED_CHAIN_CNT_TYPE_U16 && 2343a91eb52aSYuval Mintz chain_size > 0x10000) || 2344a91eb52aSYuval Mintz (cnt_type == QED_CHAIN_CNT_TYPE_U32 && 2345a91eb52aSYuval Mintz chain_size > 0x100000000ULL)) { 2346a91eb52aSYuval Mintz DP_NOTICE(cdev, 2347a91eb52aSYuval Mintz "The actual chain size (0x%llx) is larger than the maximal possible value\n", 2348a91eb52aSYuval Mintz chain_size); 2349a91eb52aSYuval Mintz return -EINVAL; 2350a91eb52aSYuval Mintz } 2351a91eb52aSYuval Mintz 2352a91eb52aSYuval Mintz return 0; 2353a91eb52aSYuval Mintz } 2354a91eb52aSYuval Mintz 2355a91eb52aSYuval Mintz static int 2356a91eb52aSYuval Mintz qed_chain_alloc_next_ptr(struct qed_dev *cdev, struct qed_chain *p_chain) 2357a91eb52aSYuval Mintz { 2358a91eb52aSYuval Mintz void *p_virt = NULL, *p_virt_prev = NULL; 2359a91eb52aSYuval Mintz dma_addr_t p_phys = 0; 2360a91eb52aSYuval Mintz u32 i; 2361a91eb52aSYuval Mintz 2362a91eb52aSYuval Mintz for (i = 0; i < p_chain->page_cnt; i++) { 2363a91eb52aSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 2364a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 2365a91eb52aSYuval Mintz &p_phys, GFP_KERNEL); 23662591c280SJoe Perches if (!p_virt) 2367a91eb52aSYuval Mintz return -ENOMEM; 2368a91eb52aSYuval Mintz 2369a91eb52aSYuval Mintz if (i == 0) { 2370a91eb52aSYuval Mintz qed_chain_init_mem(p_chain, p_virt, p_phys); 2371a91eb52aSYuval Mintz qed_chain_reset(p_chain); 2372a91eb52aSYuval Mintz } else { 2373a91eb52aSYuval Mintz qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, 2374a91eb52aSYuval Mintz p_virt, p_phys); 2375a91eb52aSYuval Mintz } 2376a91eb52aSYuval Mintz 2377a91eb52aSYuval Mintz p_virt_prev = p_virt; 2378a91eb52aSYuval Mintz } 2379a91eb52aSYuval Mintz /* Last page's next element should point to the beginning of the 2380a91eb52aSYuval Mintz * chain. 2381a91eb52aSYuval Mintz */ 2382a91eb52aSYuval Mintz qed_chain_init_next_ptr_elem(p_chain, p_virt_prev, 2383a91eb52aSYuval Mintz p_chain->p_virt_addr, 2384a91eb52aSYuval Mintz p_chain->p_phys_addr); 2385a91eb52aSYuval Mintz 2386a91eb52aSYuval Mintz return 0; 2387a91eb52aSYuval Mintz } 2388a91eb52aSYuval Mintz 2389a91eb52aSYuval Mintz static int 2390a91eb52aSYuval Mintz qed_chain_alloc_single(struct qed_dev *cdev, struct qed_chain *p_chain) 2391a91eb52aSYuval Mintz { 2392a91eb52aSYuval Mintz dma_addr_t p_phys = 0; 2393a91eb52aSYuval Mintz void *p_virt = NULL; 2394a91eb52aSYuval Mintz 2395a91eb52aSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 2396a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, &p_phys, GFP_KERNEL); 23972591c280SJoe Perches if (!p_virt) 2398a91eb52aSYuval Mintz return -ENOMEM; 2399a91eb52aSYuval Mintz 2400a91eb52aSYuval Mintz qed_chain_init_mem(p_chain, p_virt, p_phys); 2401a91eb52aSYuval Mintz qed_chain_reset(p_chain); 2402a91eb52aSYuval Mintz 2403a91eb52aSYuval Mintz return 0; 2404a91eb52aSYuval Mintz } 2405a91eb52aSYuval Mintz 2406a91eb52aSYuval Mintz static int qed_chain_alloc_pbl(struct qed_dev *cdev, struct qed_chain *p_chain) 2407a91eb52aSYuval Mintz { 2408a91eb52aSYuval Mintz u32 page_cnt = p_chain->page_cnt, size, i; 2409a91eb52aSYuval Mintz dma_addr_t p_phys = 0, p_pbl_phys = 0; 2410a91eb52aSYuval Mintz void **pp_virt_addr_tbl = NULL; 2411a91eb52aSYuval Mintz u8 *p_pbl_virt = NULL; 2412a91eb52aSYuval Mintz void *p_virt = NULL; 2413a91eb52aSYuval Mintz 2414a91eb52aSYuval Mintz size = page_cnt * sizeof(*pp_virt_addr_tbl); 24152591c280SJoe Perches pp_virt_addr_tbl = vzalloc(size); 24162591c280SJoe Perches if (!pp_virt_addr_tbl) 2417a91eb52aSYuval Mintz return -ENOMEM; 2418a91eb52aSYuval Mintz 2419a91eb52aSYuval Mintz /* The allocation of the PBL table is done with its full size, since it 2420a91eb52aSYuval Mintz * is expected to be successive. 2421a91eb52aSYuval Mintz * qed_chain_init_pbl_mem() is called even in a case of an allocation 2422a91eb52aSYuval Mintz * failure, since pp_virt_addr_tbl was previously allocated, and it 2423a91eb52aSYuval Mintz * should be saved to allow its freeing during the error flow. 2424a91eb52aSYuval Mintz */ 2425a91eb52aSYuval Mintz size = page_cnt * QED_CHAIN_PBL_ENTRY_SIZE; 2426a91eb52aSYuval Mintz p_pbl_virt = dma_alloc_coherent(&cdev->pdev->dev, 2427a91eb52aSYuval Mintz size, &p_pbl_phys, GFP_KERNEL); 2428a91eb52aSYuval Mintz qed_chain_init_pbl_mem(p_chain, p_pbl_virt, p_pbl_phys, 2429a91eb52aSYuval Mintz pp_virt_addr_tbl); 24302591c280SJoe Perches if (!p_pbl_virt) 2431a91eb52aSYuval Mintz return -ENOMEM; 2432a91eb52aSYuval Mintz 2433a91eb52aSYuval Mintz for (i = 0; i < page_cnt; i++) { 2434a91eb52aSYuval Mintz p_virt = dma_alloc_coherent(&cdev->pdev->dev, 2435a91eb52aSYuval Mintz QED_CHAIN_PAGE_SIZE, 2436a91eb52aSYuval Mintz &p_phys, GFP_KERNEL); 24372591c280SJoe Perches if (!p_virt) 2438a91eb52aSYuval Mintz return -ENOMEM; 2439a91eb52aSYuval Mintz 2440a91eb52aSYuval Mintz if (i == 0) { 2441a91eb52aSYuval Mintz qed_chain_init_mem(p_chain, p_virt, p_phys); 2442a91eb52aSYuval Mintz qed_chain_reset(p_chain); 2443a91eb52aSYuval Mintz } 2444a91eb52aSYuval Mintz 2445a91eb52aSYuval Mintz /* Fill the PBL table with the physical address of the page */ 2446a91eb52aSYuval Mintz *(dma_addr_t *)p_pbl_virt = p_phys; 2447a91eb52aSYuval Mintz /* Keep the virtual address of the page */ 2448a91eb52aSYuval Mintz p_chain->pbl.pp_virt_addr_tbl[i] = p_virt; 2449a91eb52aSYuval Mintz 2450a91eb52aSYuval Mintz p_pbl_virt += QED_CHAIN_PBL_ENTRY_SIZE; 2451a91eb52aSYuval Mintz } 2452a91eb52aSYuval Mintz 2453a91eb52aSYuval Mintz return 0; 2454a91eb52aSYuval Mintz } 2455a91eb52aSYuval Mintz 2456fe56b9e6SYuval Mintz int qed_chain_alloc(struct qed_dev *cdev, 2457fe56b9e6SYuval Mintz enum qed_chain_use_mode intended_use, 2458fe56b9e6SYuval Mintz enum qed_chain_mode mode, 2459a91eb52aSYuval Mintz enum qed_chain_cnt_type cnt_type, 2460a91eb52aSYuval Mintz u32 num_elems, size_t elem_size, struct qed_chain *p_chain) 2461fe56b9e6SYuval Mintz { 2462a91eb52aSYuval Mintz u32 page_cnt; 2463a91eb52aSYuval Mintz int rc = 0; 2464fe56b9e6SYuval Mintz 2465fe56b9e6SYuval Mintz if (mode == QED_CHAIN_MODE_SINGLE) 2466fe56b9e6SYuval Mintz page_cnt = 1; 2467fe56b9e6SYuval Mintz else 2468fe56b9e6SYuval Mintz page_cnt = QED_CHAIN_PAGE_CNT(num_elems, elem_size, mode); 2469fe56b9e6SYuval Mintz 2470a91eb52aSYuval Mintz rc = qed_chain_alloc_sanity_check(cdev, cnt_type, elem_size, page_cnt); 2471a91eb52aSYuval Mintz if (rc) { 2472a91eb52aSYuval Mintz DP_NOTICE(cdev, 24732591c280SJoe Perches "Cannot allocate a chain with the given arguments:\n"); 24742591c280SJoe Perches DP_NOTICE(cdev, 2475a91eb52aSYuval Mintz "[use_mode %d, mode %d, cnt_type %d, num_elems %d, elem_size %zu]\n", 2476a91eb52aSYuval Mintz intended_use, mode, cnt_type, num_elems, elem_size); 2477a91eb52aSYuval Mintz return rc; 2478fe56b9e6SYuval Mintz } 2479fe56b9e6SYuval Mintz 2480a91eb52aSYuval Mintz qed_chain_init_params(p_chain, page_cnt, (u8) elem_size, intended_use, 2481a91eb52aSYuval Mintz mode, cnt_type); 2482fe56b9e6SYuval Mintz 2483a91eb52aSYuval Mintz switch (mode) { 2484a91eb52aSYuval Mintz case QED_CHAIN_MODE_NEXT_PTR: 2485a91eb52aSYuval Mintz rc = qed_chain_alloc_next_ptr(cdev, p_chain); 2486a91eb52aSYuval Mintz break; 2487a91eb52aSYuval Mintz case QED_CHAIN_MODE_SINGLE: 2488a91eb52aSYuval Mintz rc = qed_chain_alloc_single(cdev, p_chain); 2489a91eb52aSYuval Mintz break; 2490a91eb52aSYuval Mintz case QED_CHAIN_MODE_PBL: 2491a91eb52aSYuval Mintz rc = qed_chain_alloc_pbl(cdev, p_chain); 2492a91eb52aSYuval Mintz break; 2493fe56b9e6SYuval Mintz } 2494a91eb52aSYuval Mintz if (rc) 2495a91eb52aSYuval Mintz goto nomem; 2496fe56b9e6SYuval Mintz 2497fe56b9e6SYuval Mintz return 0; 2498fe56b9e6SYuval Mintz 2499fe56b9e6SYuval Mintz nomem: 2500a91eb52aSYuval Mintz qed_chain_free(cdev, p_chain); 2501a91eb52aSYuval Mintz return rc; 2502fe56b9e6SYuval Mintz } 2503fe56b9e6SYuval Mintz 2504a91eb52aSYuval Mintz int qed_fw_l2_queue(struct qed_hwfn *p_hwfn, u16 src_id, u16 *dst_id) 2505cee4d264SManish Chopra { 2506cee4d264SManish Chopra if (src_id >= RESC_NUM(p_hwfn, QED_L2_QUEUE)) { 2507cee4d264SManish Chopra u16 min, max; 2508cee4d264SManish Chopra 2509cee4d264SManish Chopra min = (u16) RESC_START(p_hwfn, QED_L2_QUEUE); 2510cee4d264SManish Chopra max = min + RESC_NUM(p_hwfn, QED_L2_QUEUE); 2511cee4d264SManish Chopra DP_NOTICE(p_hwfn, 2512cee4d264SManish Chopra "l2_queue id [%d] is not valid, available indices [%d - %d]\n", 2513cee4d264SManish Chopra src_id, min, max); 2514cee4d264SManish Chopra 2515cee4d264SManish Chopra return -EINVAL; 2516cee4d264SManish Chopra } 2517cee4d264SManish Chopra 2518cee4d264SManish Chopra *dst_id = RESC_START(p_hwfn, QED_L2_QUEUE) + src_id; 2519cee4d264SManish Chopra 2520cee4d264SManish Chopra return 0; 2521cee4d264SManish Chopra } 2522cee4d264SManish Chopra 25231a635e48SYuval Mintz int qed_fw_vport(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id) 2524cee4d264SManish Chopra { 2525cee4d264SManish Chopra if (src_id >= RESC_NUM(p_hwfn, QED_VPORT)) { 2526cee4d264SManish Chopra u8 min, max; 2527cee4d264SManish Chopra 2528cee4d264SManish Chopra min = (u8)RESC_START(p_hwfn, QED_VPORT); 2529cee4d264SManish Chopra max = min + RESC_NUM(p_hwfn, QED_VPORT); 2530cee4d264SManish Chopra DP_NOTICE(p_hwfn, 2531cee4d264SManish Chopra "vport id [%d] is not valid, available indices [%d - %d]\n", 2532cee4d264SManish Chopra src_id, min, max); 2533cee4d264SManish Chopra 2534cee4d264SManish Chopra return -EINVAL; 2535cee4d264SManish Chopra } 2536cee4d264SManish Chopra 2537cee4d264SManish Chopra *dst_id = RESC_START(p_hwfn, QED_VPORT) + src_id; 2538cee4d264SManish Chopra 2539cee4d264SManish Chopra return 0; 2540cee4d264SManish Chopra } 2541cee4d264SManish Chopra 25421a635e48SYuval Mintz int qed_fw_rss_eng(struct qed_hwfn *p_hwfn, u8 src_id, u8 *dst_id) 2543cee4d264SManish Chopra { 2544cee4d264SManish Chopra if (src_id >= RESC_NUM(p_hwfn, QED_RSS_ENG)) { 2545cee4d264SManish Chopra u8 min, max; 2546cee4d264SManish Chopra 2547cee4d264SManish Chopra min = (u8)RESC_START(p_hwfn, QED_RSS_ENG); 2548cee4d264SManish Chopra max = min + RESC_NUM(p_hwfn, QED_RSS_ENG); 2549cee4d264SManish Chopra DP_NOTICE(p_hwfn, 2550cee4d264SManish Chopra "rss_eng id [%d] is not valid, available indices [%d - %d]\n", 2551cee4d264SManish Chopra src_id, min, max); 2552cee4d264SManish Chopra 2553cee4d264SManish Chopra return -EINVAL; 2554cee4d264SManish Chopra } 2555cee4d264SManish Chopra 2556cee4d264SManish Chopra *dst_id = RESC_START(p_hwfn, QED_RSS_ENG) + src_id; 2557cee4d264SManish Chopra 2558cee4d264SManish Chopra return 0; 2559cee4d264SManish Chopra } 2560bcd197c8SManish Chopra 25610a7fb11cSYuval Mintz static void qed_llh_mac_to_filter(u32 *p_high, u32 *p_low, 25620a7fb11cSYuval Mintz u8 *p_filter) 25630a7fb11cSYuval Mintz { 25640a7fb11cSYuval Mintz *p_high = p_filter[1] | (p_filter[0] << 8); 25650a7fb11cSYuval Mintz *p_low = p_filter[5] | (p_filter[4] << 8) | 25660a7fb11cSYuval Mintz (p_filter[3] << 16) | (p_filter[2] << 24); 25670a7fb11cSYuval Mintz } 25680a7fb11cSYuval Mintz 25690a7fb11cSYuval Mintz int qed_llh_add_mac_filter(struct qed_hwfn *p_hwfn, 25700a7fb11cSYuval Mintz struct qed_ptt *p_ptt, u8 *p_filter) 25710a7fb11cSYuval Mintz { 25720a7fb11cSYuval Mintz u32 high = 0, low = 0, en; 25730a7fb11cSYuval Mintz int i; 25740a7fb11cSYuval Mintz 25750a7fb11cSYuval Mintz if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 25760a7fb11cSYuval Mintz return 0; 25770a7fb11cSYuval Mintz 25780a7fb11cSYuval Mintz qed_llh_mac_to_filter(&high, &low, p_filter); 25790a7fb11cSYuval Mintz 25800a7fb11cSYuval Mintz /* Find a free entry and utilize it */ 25810a7fb11cSYuval Mintz for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 25820a7fb11cSYuval Mintz en = qed_rd(p_hwfn, p_ptt, 25830a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32)); 25840a7fb11cSYuval Mintz if (en) 25850a7fb11cSYuval Mintz continue; 25860a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 25870a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 25880a7fb11cSYuval Mintz 2 * i * sizeof(u32), low); 25890a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 25900a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 25910a7fb11cSYuval Mintz (2 * i + 1) * sizeof(u32), high); 25920a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 25930a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_MODE + i * sizeof(u32), 0); 25940a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 25950a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_PROTOCOL_TYPE + 25960a7fb11cSYuval Mintz i * sizeof(u32), 0); 25970a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 25980a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 1); 25990a7fb11cSYuval Mintz break; 26000a7fb11cSYuval Mintz } 26010a7fb11cSYuval Mintz if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) { 26020a7fb11cSYuval Mintz DP_NOTICE(p_hwfn, 26030a7fb11cSYuval Mintz "Failed to find an empty LLH filter to utilize\n"); 26040a7fb11cSYuval Mintz return -EINVAL; 26050a7fb11cSYuval Mintz } 26060a7fb11cSYuval Mintz 26070a7fb11cSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 26080a7fb11cSYuval Mintz "mac: %pM is added at %d\n", 26090a7fb11cSYuval Mintz p_filter, i); 26100a7fb11cSYuval Mintz 26110a7fb11cSYuval Mintz return 0; 26120a7fb11cSYuval Mintz } 26130a7fb11cSYuval Mintz 26140a7fb11cSYuval Mintz void qed_llh_remove_mac_filter(struct qed_hwfn *p_hwfn, 26150a7fb11cSYuval Mintz struct qed_ptt *p_ptt, u8 *p_filter) 26160a7fb11cSYuval Mintz { 26170a7fb11cSYuval Mintz u32 high = 0, low = 0; 26180a7fb11cSYuval Mintz int i; 26190a7fb11cSYuval Mintz 26200a7fb11cSYuval Mintz if (!(IS_MF_SI(p_hwfn) || IS_MF_DEFAULT(p_hwfn))) 26210a7fb11cSYuval Mintz return; 26220a7fb11cSYuval Mintz 26230a7fb11cSYuval Mintz qed_llh_mac_to_filter(&high, &low, p_filter); 26240a7fb11cSYuval Mintz 26250a7fb11cSYuval Mintz /* Find the entry and clean it */ 26260a7fb11cSYuval Mintz for (i = 0; i < NIG_REG_LLH_FUNC_FILTER_EN_SIZE; i++) { 26270a7fb11cSYuval Mintz if (qed_rd(p_hwfn, p_ptt, 26280a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 26290a7fb11cSYuval Mintz 2 * i * sizeof(u32)) != low) 26300a7fb11cSYuval Mintz continue; 26310a7fb11cSYuval Mintz if (qed_rd(p_hwfn, p_ptt, 26320a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 26330a7fb11cSYuval Mintz (2 * i + 1) * sizeof(u32)) != high) 26340a7fb11cSYuval Mintz continue; 26350a7fb11cSYuval Mintz 26360a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 26370a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_EN + i * sizeof(u32), 0); 26380a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 26390a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 2 * i * sizeof(u32), 0); 26400a7fb11cSYuval Mintz qed_wr(p_hwfn, p_ptt, 26410a7fb11cSYuval Mintz NIG_REG_LLH_FUNC_FILTER_VALUE + 26420a7fb11cSYuval Mintz (2 * i + 1) * sizeof(u32), 0); 26430a7fb11cSYuval Mintz 26440a7fb11cSYuval Mintz DP_VERBOSE(p_hwfn, NETIF_MSG_HW, 26450a7fb11cSYuval Mintz "mac: %pM is removed from %d\n", 26460a7fb11cSYuval Mintz p_filter, i); 26470a7fb11cSYuval Mintz break; 26480a7fb11cSYuval Mintz } 26490a7fb11cSYuval Mintz if (i >= NIG_REG_LLH_FUNC_FILTER_EN_SIZE) 26500a7fb11cSYuval Mintz DP_NOTICE(p_hwfn, "Tried to remove a non-configured filter\n"); 26510a7fb11cSYuval Mintz } 26520a7fb11cSYuval Mintz 2653722003acSSudarsana Reddy Kalluru static int qed_set_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2654722003acSSudarsana Reddy Kalluru u32 hw_addr, void *p_eth_qzone, 2655722003acSSudarsana Reddy Kalluru size_t eth_qzone_size, u8 timeset) 2656722003acSSudarsana Reddy Kalluru { 2657722003acSSudarsana Reddy Kalluru struct coalescing_timeset *p_coal_timeset; 2658722003acSSudarsana Reddy Kalluru 2659722003acSSudarsana Reddy Kalluru if (p_hwfn->cdev->int_coalescing_mode != QED_COAL_MODE_ENABLE) { 2660722003acSSudarsana Reddy Kalluru DP_NOTICE(p_hwfn, "Coalescing configuration not enabled\n"); 2661722003acSSudarsana Reddy Kalluru return -EINVAL; 2662722003acSSudarsana Reddy Kalluru } 2663722003acSSudarsana Reddy Kalluru 2664722003acSSudarsana Reddy Kalluru p_coal_timeset = p_eth_qzone; 2665722003acSSudarsana Reddy Kalluru memset(p_coal_timeset, 0, eth_qzone_size); 2666722003acSSudarsana Reddy Kalluru SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_TIMESET, timeset); 2667722003acSSudarsana Reddy Kalluru SET_FIELD(p_coal_timeset->value, COALESCING_TIMESET_VALID, 1); 2668722003acSSudarsana Reddy Kalluru qed_memcpy_to(p_hwfn, p_ptt, hw_addr, p_eth_qzone, eth_qzone_size); 2669722003acSSudarsana Reddy Kalluru 2670722003acSSudarsana Reddy Kalluru return 0; 2671722003acSSudarsana Reddy Kalluru } 2672722003acSSudarsana Reddy Kalluru 2673722003acSSudarsana Reddy Kalluru int qed_set_rxq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2674722003acSSudarsana Reddy Kalluru u16 coalesce, u8 qid, u16 sb_id) 2675722003acSSudarsana Reddy Kalluru { 2676722003acSSudarsana Reddy Kalluru struct ustorm_eth_queue_zone eth_qzone; 2677722003acSSudarsana Reddy Kalluru u8 timeset, timer_res; 2678722003acSSudarsana Reddy Kalluru u16 fw_qid = 0; 2679722003acSSudarsana Reddy Kalluru u32 address; 2680722003acSSudarsana Reddy Kalluru int rc; 2681722003acSSudarsana Reddy Kalluru 2682722003acSSudarsana Reddy Kalluru /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 2683722003acSSudarsana Reddy Kalluru if (coalesce <= 0x7F) { 2684722003acSSudarsana Reddy Kalluru timer_res = 0; 2685722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0xFF) { 2686722003acSSudarsana Reddy Kalluru timer_res = 1; 2687722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0x1FF) { 2688722003acSSudarsana Reddy Kalluru timer_res = 2; 2689722003acSSudarsana Reddy Kalluru } else { 2690722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 2691722003acSSudarsana Reddy Kalluru return -EINVAL; 2692722003acSSudarsana Reddy Kalluru } 2693722003acSSudarsana Reddy Kalluru timeset = (u8)(coalesce >> timer_res); 2694722003acSSudarsana Reddy Kalluru 2695722003acSSudarsana Reddy Kalluru rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid); 2696722003acSSudarsana Reddy Kalluru if (rc) 2697722003acSSudarsana Reddy Kalluru return rc; 2698722003acSSudarsana Reddy Kalluru 2699722003acSSudarsana Reddy Kalluru rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, false); 2700722003acSSudarsana Reddy Kalluru if (rc) 2701722003acSSudarsana Reddy Kalluru goto out; 2702722003acSSudarsana Reddy Kalluru 2703722003acSSudarsana Reddy Kalluru address = BAR0_MAP_REG_USDM_RAM + USTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid); 2704722003acSSudarsana Reddy Kalluru 2705722003acSSudarsana Reddy Kalluru rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 2706722003acSSudarsana Reddy Kalluru sizeof(struct ustorm_eth_queue_zone), timeset); 2707722003acSSudarsana Reddy Kalluru if (rc) 2708722003acSSudarsana Reddy Kalluru goto out; 2709722003acSSudarsana Reddy Kalluru 2710722003acSSudarsana Reddy Kalluru p_hwfn->cdev->rx_coalesce_usecs = coalesce; 2711722003acSSudarsana Reddy Kalluru out: 2712722003acSSudarsana Reddy Kalluru return rc; 2713722003acSSudarsana Reddy Kalluru } 2714722003acSSudarsana Reddy Kalluru 2715722003acSSudarsana Reddy Kalluru int qed_set_txq_coalesce(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 2716722003acSSudarsana Reddy Kalluru u16 coalesce, u8 qid, u16 sb_id) 2717722003acSSudarsana Reddy Kalluru { 2718722003acSSudarsana Reddy Kalluru struct xstorm_eth_queue_zone eth_qzone; 2719722003acSSudarsana Reddy Kalluru u8 timeset, timer_res; 2720722003acSSudarsana Reddy Kalluru u16 fw_qid = 0; 2721722003acSSudarsana Reddy Kalluru u32 address; 2722722003acSSudarsana Reddy Kalluru int rc; 2723722003acSSudarsana Reddy Kalluru 2724722003acSSudarsana Reddy Kalluru /* Coalesce = (timeset << timer-resolution), timeset is 7bit wide */ 2725722003acSSudarsana Reddy Kalluru if (coalesce <= 0x7F) { 2726722003acSSudarsana Reddy Kalluru timer_res = 0; 2727722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0xFF) { 2728722003acSSudarsana Reddy Kalluru timer_res = 1; 2729722003acSSudarsana Reddy Kalluru } else if (coalesce <= 0x1FF) { 2730722003acSSudarsana Reddy Kalluru timer_res = 2; 2731722003acSSudarsana Reddy Kalluru } else { 2732722003acSSudarsana Reddy Kalluru DP_ERR(p_hwfn, "Invalid coalesce value - %d\n", coalesce); 2733722003acSSudarsana Reddy Kalluru return -EINVAL; 2734722003acSSudarsana Reddy Kalluru } 2735722003acSSudarsana Reddy Kalluru timeset = (u8)(coalesce >> timer_res); 2736722003acSSudarsana Reddy Kalluru 2737722003acSSudarsana Reddy Kalluru rc = qed_fw_l2_queue(p_hwfn, (u16)qid, &fw_qid); 2738722003acSSudarsana Reddy Kalluru if (rc) 2739722003acSSudarsana Reddy Kalluru return rc; 2740722003acSSudarsana Reddy Kalluru 2741722003acSSudarsana Reddy Kalluru rc = qed_int_set_timer_res(p_hwfn, p_ptt, timer_res, sb_id, true); 2742722003acSSudarsana Reddy Kalluru if (rc) 2743722003acSSudarsana Reddy Kalluru goto out; 2744722003acSSudarsana Reddy Kalluru 2745722003acSSudarsana Reddy Kalluru address = BAR0_MAP_REG_XSDM_RAM + XSTORM_ETH_QUEUE_ZONE_OFFSET(fw_qid); 2746722003acSSudarsana Reddy Kalluru 2747722003acSSudarsana Reddy Kalluru rc = qed_set_coalesce(p_hwfn, p_ptt, address, ð_qzone, 2748722003acSSudarsana Reddy Kalluru sizeof(struct xstorm_eth_queue_zone), timeset); 2749722003acSSudarsana Reddy Kalluru if (rc) 2750722003acSSudarsana Reddy Kalluru goto out; 2751722003acSSudarsana Reddy Kalluru 2752722003acSSudarsana Reddy Kalluru p_hwfn->cdev->tx_coalesce_usecs = coalesce; 2753722003acSSudarsana Reddy Kalluru out: 2754722003acSSudarsana Reddy Kalluru return rc; 2755722003acSSudarsana Reddy Kalluru } 2756722003acSSudarsana Reddy Kalluru 2757bcd197c8SManish Chopra /* Calculate final WFQ values for all vports and configure them. 2758bcd197c8SManish Chopra * After this configuration each vport will have 2759bcd197c8SManish Chopra * approx min rate = min_pf_rate * (vport_wfq / QED_WFQ_UNIT) 2760bcd197c8SManish Chopra */ 2761bcd197c8SManish Chopra static void qed_configure_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 2762bcd197c8SManish Chopra struct qed_ptt *p_ptt, 2763bcd197c8SManish Chopra u32 min_pf_rate) 2764bcd197c8SManish Chopra { 2765bcd197c8SManish Chopra struct init_qm_vport_params *vport_params; 2766bcd197c8SManish Chopra int i; 2767bcd197c8SManish Chopra 2768bcd197c8SManish Chopra vport_params = p_hwfn->qm_info.qm_vport_params; 2769bcd197c8SManish Chopra 2770bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 2771bcd197c8SManish Chopra u32 wfq_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 2772bcd197c8SManish Chopra 2773bcd197c8SManish Chopra vport_params[i].vport_wfq = (wfq_speed * QED_WFQ_UNIT) / 2774bcd197c8SManish Chopra min_pf_rate; 2775bcd197c8SManish Chopra qed_init_vport_wfq(p_hwfn, p_ptt, 2776bcd197c8SManish Chopra vport_params[i].first_tx_pq_id, 2777bcd197c8SManish Chopra vport_params[i].vport_wfq); 2778bcd197c8SManish Chopra } 2779bcd197c8SManish Chopra } 2780bcd197c8SManish Chopra 2781bcd197c8SManish Chopra static void qed_init_wfq_default_param(struct qed_hwfn *p_hwfn, 2782bcd197c8SManish Chopra u32 min_pf_rate) 2783bcd197c8SManish Chopra 2784bcd197c8SManish Chopra { 2785bcd197c8SManish Chopra int i; 2786bcd197c8SManish Chopra 2787bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) 2788bcd197c8SManish Chopra p_hwfn->qm_info.qm_vport_params[i].vport_wfq = 1; 2789bcd197c8SManish Chopra } 2790bcd197c8SManish Chopra 2791bcd197c8SManish Chopra static void qed_disable_wfq_for_all_vports(struct qed_hwfn *p_hwfn, 2792bcd197c8SManish Chopra struct qed_ptt *p_ptt, 2793bcd197c8SManish Chopra u32 min_pf_rate) 2794bcd197c8SManish Chopra { 2795bcd197c8SManish Chopra struct init_qm_vport_params *vport_params; 2796bcd197c8SManish Chopra int i; 2797bcd197c8SManish Chopra 2798bcd197c8SManish Chopra vport_params = p_hwfn->qm_info.qm_vport_params; 2799bcd197c8SManish Chopra 2800bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 2801bcd197c8SManish Chopra qed_init_wfq_default_param(p_hwfn, min_pf_rate); 2802bcd197c8SManish Chopra qed_init_vport_wfq(p_hwfn, p_ptt, 2803bcd197c8SManish Chopra vport_params[i].first_tx_pq_id, 2804bcd197c8SManish Chopra vport_params[i].vport_wfq); 2805bcd197c8SManish Chopra } 2806bcd197c8SManish Chopra } 2807bcd197c8SManish Chopra 2808bcd197c8SManish Chopra /* This function performs several validations for WFQ 2809bcd197c8SManish Chopra * configuration and required min rate for a given vport 2810bcd197c8SManish Chopra * 1. req_rate must be greater than one percent of min_pf_rate. 2811bcd197c8SManish Chopra * 2. req_rate should not cause other vports [not configured for WFQ explicitly] 2812bcd197c8SManish Chopra * rates to get less than one percent of min_pf_rate. 2813bcd197c8SManish Chopra * 3. total_req_min_rate [all vports min rate sum] shouldn't exceed min_pf_rate. 2814bcd197c8SManish Chopra */ 2815bcd197c8SManish Chopra static int qed_init_wfq_param(struct qed_hwfn *p_hwfn, 28161a635e48SYuval Mintz u16 vport_id, u32 req_rate, u32 min_pf_rate) 2817bcd197c8SManish Chopra { 2818bcd197c8SManish Chopra u32 total_req_min_rate = 0, total_left_rate = 0, left_rate_per_vp = 0; 2819bcd197c8SManish Chopra int non_requested_count = 0, req_count = 0, i, num_vports; 2820bcd197c8SManish Chopra 2821bcd197c8SManish Chopra num_vports = p_hwfn->qm_info.num_vports; 2822bcd197c8SManish Chopra 2823bcd197c8SManish Chopra /* Accounting for the vports which are configured for WFQ explicitly */ 2824bcd197c8SManish Chopra for (i = 0; i < num_vports; i++) { 2825bcd197c8SManish Chopra u32 tmp_speed; 2826bcd197c8SManish Chopra 2827bcd197c8SManish Chopra if ((i != vport_id) && 2828bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[i].configured) { 2829bcd197c8SManish Chopra req_count++; 2830bcd197c8SManish Chopra tmp_speed = p_hwfn->qm_info.wfq_data[i].min_speed; 2831bcd197c8SManish Chopra total_req_min_rate += tmp_speed; 2832bcd197c8SManish Chopra } 2833bcd197c8SManish Chopra } 2834bcd197c8SManish Chopra 2835bcd197c8SManish Chopra /* Include current vport data as well */ 2836bcd197c8SManish Chopra req_count++; 2837bcd197c8SManish Chopra total_req_min_rate += req_rate; 2838bcd197c8SManish Chopra non_requested_count = num_vports - req_count; 2839bcd197c8SManish Chopra 2840bcd197c8SManish Chopra if (req_rate < min_pf_rate / QED_WFQ_UNIT) { 2841bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2842bcd197c8SManish Chopra "Vport [%d] - Requested rate[%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 2843bcd197c8SManish Chopra vport_id, req_rate, min_pf_rate); 2844bcd197c8SManish Chopra return -EINVAL; 2845bcd197c8SManish Chopra } 2846bcd197c8SManish Chopra 2847bcd197c8SManish Chopra if (num_vports > QED_WFQ_UNIT) { 2848bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2849bcd197c8SManish Chopra "Number of vports is greater than %d\n", 2850bcd197c8SManish Chopra QED_WFQ_UNIT); 2851bcd197c8SManish Chopra return -EINVAL; 2852bcd197c8SManish Chopra } 2853bcd197c8SManish Chopra 2854bcd197c8SManish Chopra if (total_req_min_rate > min_pf_rate) { 2855bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2856bcd197c8SManish Chopra "Total requested min rate for all vports[%d Mbps] is greater than configured PF min rate[%d Mbps]\n", 2857bcd197c8SManish Chopra total_req_min_rate, min_pf_rate); 2858bcd197c8SManish Chopra return -EINVAL; 2859bcd197c8SManish Chopra } 2860bcd197c8SManish Chopra 2861bcd197c8SManish Chopra total_left_rate = min_pf_rate - total_req_min_rate; 2862bcd197c8SManish Chopra 2863bcd197c8SManish Chopra left_rate_per_vp = total_left_rate / non_requested_count; 2864bcd197c8SManish Chopra if (left_rate_per_vp < min_pf_rate / QED_WFQ_UNIT) { 2865bcd197c8SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 2866bcd197c8SManish Chopra "Non WFQ configured vports rate [%d Mbps] is less than one percent of configured PF min rate[%d Mbps]\n", 2867bcd197c8SManish Chopra left_rate_per_vp, min_pf_rate); 2868bcd197c8SManish Chopra return -EINVAL; 2869bcd197c8SManish Chopra } 2870bcd197c8SManish Chopra 2871bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[vport_id].min_speed = req_rate; 2872bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[vport_id].configured = true; 2873bcd197c8SManish Chopra 2874bcd197c8SManish Chopra for (i = 0; i < num_vports; i++) { 2875bcd197c8SManish Chopra if (p_hwfn->qm_info.wfq_data[i].configured) 2876bcd197c8SManish Chopra continue; 2877bcd197c8SManish Chopra 2878bcd197c8SManish Chopra p_hwfn->qm_info.wfq_data[i].min_speed = left_rate_per_vp; 2879bcd197c8SManish Chopra } 2880bcd197c8SManish Chopra 2881bcd197c8SManish Chopra return 0; 2882bcd197c8SManish Chopra } 2883bcd197c8SManish Chopra 2884733def6aSYuval Mintz static int __qed_configure_vport_wfq(struct qed_hwfn *p_hwfn, 2885733def6aSYuval Mintz struct qed_ptt *p_ptt, u16 vp_id, u32 rate) 2886733def6aSYuval Mintz { 2887733def6aSYuval Mintz struct qed_mcp_link_state *p_link; 2888733def6aSYuval Mintz int rc = 0; 2889733def6aSYuval Mintz 2890733def6aSYuval Mintz p_link = &p_hwfn->cdev->hwfns[0].mcp_info->link_output; 2891733def6aSYuval Mintz 2892733def6aSYuval Mintz if (!p_link->min_pf_rate) { 2893733def6aSYuval Mintz p_hwfn->qm_info.wfq_data[vp_id].min_speed = rate; 2894733def6aSYuval Mintz p_hwfn->qm_info.wfq_data[vp_id].configured = true; 2895733def6aSYuval Mintz return rc; 2896733def6aSYuval Mintz } 2897733def6aSYuval Mintz 2898733def6aSYuval Mintz rc = qed_init_wfq_param(p_hwfn, vp_id, rate, p_link->min_pf_rate); 2899733def6aSYuval Mintz 29001a635e48SYuval Mintz if (!rc) 2901733def6aSYuval Mintz qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, 2902733def6aSYuval Mintz p_link->min_pf_rate); 2903733def6aSYuval Mintz else 2904733def6aSYuval Mintz DP_NOTICE(p_hwfn, 2905733def6aSYuval Mintz "Validation failed while configuring min rate\n"); 2906733def6aSYuval Mintz 2907733def6aSYuval Mintz return rc; 2908733def6aSYuval Mintz } 2909733def6aSYuval Mintz 2910bcd197c8SManish Chopra static int __qed_configure_vp_wfq_on_link_change(struct qed_hwfn *p_hwfn, 2911bcd197c8SManish Chopra struct qed_ptt *p_ptt, 2912bcd197c8SManish Chopra u32 min_pf_rate) 2913bcd197c8SManish Chopra { 2914bcd197c8SManish Chopra bool use_wfq = false; 2915bcd197c8SManish Chopra int rc = 0; 2916bcd197c8SManish Chopra u16 i; 2917bcd197c8SManish Chopra 2918bcd197c8SManish Chopra /* Validate all pre configured vports for wfq */ 2919bcd197c8SManish Chopra for (i = 0; i < p_hwfn->qm_info.num_vports; i++) { 2920bcd197c8SManish Chopra u32 rate; 2921bcd197c8SManish Chopra 2922bcd197c8SManish Chopra if (!p_hwfn->qm_info.wfq_data[i].configured) 2923bcd197c8SManish Chopra continue; 2924bcd197c8SManish Chopra 2925bcd197c8SManish Chopra rate = p_hwfn->qm_info.wfq_data[i].min_speed; 2926bcd197c8SManish Chopra use_wfq = true; 2927bcd197c8SManish Chopra 2928bcd197c8SManish Chopra rc = qed_init_wfq_param(p_hwfn, i, rate, min_pf_rate); 2929bcd197c8SManish Chopra if (rc) { 2930bcd197c8SManish Chopra DP_NOTICE(p_hwfn, 2931bcd197c8SManish Chopra "WFQ validation failed while configuring min rate\n"); 2932bcd197c8SManish Chopra break; 2933bcd197c8SManish Chopra } 2934bcd197c8SManish Chopra } 2935bcd197c8SManish Chopra 2936bcd197c8SManish Chopra if (!rc && use_wfq) 2937bcd197c8SManish Chopra qed_configure_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 2938bcd197c8SManish Chopra else 2939bcd197c8SManish Chopra qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, min_pf_rate); 2940bcd197c8SManish Chopra 2941bcd197c8SManish Chopra return rc; 2942bcd197c8SManish Chopra } 2943bcd197c8SManish Chopra 2944733def6aSYuval Mintz /* Main API for qed clients to configure vport min rate. 2945733def6aSYuval Mintz * vp_id - vport id in PF Range[0 - (total_num_vports_per_pf - 1)] 2946733def6aSYuval Mintz * rate - Speed in Mbps needs to be assigned to a given vport. 2947733def6aSYuval Mintz */ 2948733def6aSYuval Mintz int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate) 2949733def6aSYuval Mintz { 2950733def6aSYuval Mintz int i, rc = -EINVAL; 2951733def6aSYuval Mintz 2952733def6aSYuval Mintz /* Currently not supported; Might change in future */ 2953733def6aSYuval Mintz if (cdev->num_hwfns > 1) { 2954733def6aSYuval Mintz DP_NOTICE(cdev, 2955733def6aSYuval Mintz "WFQ configuration is not supported for this device\n"); 2956733def6aSYuval Mintz return rc; 2957733def6aSYuval Mintz } 2958733def6aSYuval Mintz 2959733def6aSYuval Mintz for_each_hwfn(cdev, i) { 2960733def6aSYuval Mintz struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2961733def6aSYuval Mintz struct qed_ptt *p_ptt; 2962733def6aSYuval Mintz 2963733def6aSYuval Mintz p_ptt = qed_ptt_acquire(p_hwfn); 2964733def6aSYuval Mintz if (!p_ptt) 2965733def6aSYuval Mintz return -EBUSY; 2966733def6aSYuval Mintz 2967733def6aSYuval Mintz rc = __qed_configure_vport_wfq(p_hwfn, p_ptt, vp_id, rate); 2968733def6aSYuval Mintz 2969d572c430SYuval Mintz if (rc) { 2970733def6aSYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 2971733def6aSYuval Mintz return rc; 2972733def6aSYuval Mintz } 2973733def6aSYuval Mintz 2974733def6aSYuval Mintz qed_ptt_release(p_hwfn, p_ptt); 2975733def6aSYuval Mintz } 2976733def6aSYuval Mintz 2977733def6aSYuval Mintz return rc; 2978733def6aSYuval Mintz } 2979733def6aSYuval Mintz 2980bcd197c8SManish Chopra /* API to configure WFQ from mcp link change */ 2981bcd197c8SManish Chopra void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate) 2982bcd197c8SManish Chopra { 2983bcd197c8SManish Chopra int i; 2984bcd197c8SManish Chopra 29853e7cfce2SYuval Mintz if (cdev->num_hwfns > 1) { 29863e7cfce2SYuval Mintz DP_VERBOSE(cdev, 29873e7cfce2SYuval Mintz NETIF_MSG_LINK, 29883e7cfce2SYuval Mintz "WFQ configuration is not supported for this device\n"); 29893e7cfce2SYuval Mintz return; 29903e7cfce2SYuval Mintz } 29913e7cfce2SYuval Mintz 2992bcd197c8SManish Chopra for_each_hwfn(cdev, i) { 2993bcd197c8SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 2994bcd197c8SManish Chopra 2995bcd197c8SManish Chopra __qed_configure_vp_wfq_on_link_change(p_hwfn, 2996bcd197c8SManish Chopra p_hwfn->p_dpc_ptt, 2997bcd197c8SManish Chopra min_pf_rate); 2998bcd197c8SManish Chopra } 2999bcd197c8SManish Chopra } 30004b01e519SManish Chopra 30014b01e519SManish Chopra int __qed_configure_pf_max_bandwidth(struct qed_hwfn *p_hwfn, 30024b01e519SManish Chopra struct qed_ptt *p_ptt, 30034b01e519SManish Chopra struct qed_mcp_link_state *p_link, 30044b01e519SManish Chopra u8 max_bw) 30054b01e519SManish Chopra { 30064b01e519SManish Chopra int rc = 0; 30074b01e519SManish Chopra 30084b01e519SManish Chopra p_hwfn->mcp_info->func_info.bandwidth_max = max_bw; 30094b01e519SManish Chopra 30104b01e519SManish Chopra if (!p_link->line_speed && (max_bw != 100)) 30114b01e519SManish Chopra return rc; 30124b01e519SManish Chopra 30134b01e519SManish Chopra p_link->speed = (p_link->line_speed * max_bw) / 100; 30144b01e519SManish Chopra p_hwfn->qm_info.pf_rl = p_link->speed; 30154b01e519SManish Chopra 30164b01e519SManish Chopra /* Since the limiter also affects Tx-switched traffic, we don't want it 30174b01e519SManish Chopra * to limit such traffic in case there's no actual limit. 30184b01e519SManish Chopra * In that case, set limit to imaginary high boundary. 30194b01e519SManish Chopra */ 30204b01e519SManish Chopra if (max_bw == 100) 30214b01e519SManish Chopra p_hwfn->qm_info.pf_rl = 100000; 30224b01e519SManish Chopra 30234b01e519SManish Chopra rc = qed_init_pf_rl(p_hwfn, p_ptt, p_hwfn->rel_pf_id, 30244b01e519SManish Chopra p_hwfn->qm_info.pf_rl); 30254b01e519SManish Chopra 30264b01e519SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 30274b01e519SManish Chopra "Configured MAX bandwidth to be %08x Mb/sec\n", 30284b01e519SManish Chopra p_link->speed); 30294b01e519SManish Chopra 30304b01e519SManish Chopra return rc; 30314b01e519SManish Chopra } 30324b01e519SManish Chopra 30334b01e519SManish Chopra /* Main API to configure PF max bandwidth where bw range is [1 - 100] */ 30344b01e519SManish Chopra int qed_configure_pf_max_bandwidth(struct qed_dev *cdev, u8 max_bw) 30354b01e519SManish Chopra { 30364b01e519SManish Chopra int i, rc = -EINVAL; 30374b01e519SManish Chopra 30384b01e519SManish Chopra if (max_bw < 1 || max_bw > 100) { 30394b01e519SManish Chopra DP_NOTICE(cdev, "PF max bw valid range is [1-100]\n"); 30404b01e519SManish Chopra return rc; 30414b01e519SManish Chopra } 30424b01e519SManish Chopra 30434b01e519SManish Chopra for_each_hwfn(cdev, i) { 30444b01e519SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 30454b01e519SManish Chopra struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 30464b01e519SManish Chopra struct qed_mcp_link_state *p_link; 30474b01e519SManish Chopra struct qed_ptt *p_ptt; 30484b01e519SManish Chopra 30494b01e519SManish Chopra p_link = &p_lead->mcp_info->link_output; 30504b01e519SManish Chopra 30514b01e519SManish Chopra p_ptt = qed_ptt_acquire(p_hwfn); 30524b01e519SManish Chopra if (!p_ptt) 30534b01e519SManish Chopra return -EBUSY; 30544b01e519SManish Chopra 30554b01e519SManish Chopra rc = __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, 30564b01e519SManish Chopra p_link, max_bw); 30574b01e519SManish Chopra 30584b01e519SManish Chopra qed_ptt_release(p_hwfn, p_ptt); 30594b01e519SManish Chopra 30604b01e519SManish Chopra if (rc) 30614b01e519SManish Chopra break; 30624b01e519SManish Chopra } 30634b01e519SManish Chopra 30644b01e519SManish Chopra return rc; 30654b01e519SManish Chopra } 3066a64b02d5SManish Chopra 3067a64b02d5SManish Chopra int __qed_configure_pf_min_bandwidth(struct qed_hwfn *p_hwfn, 3068a64b02d5SManish Chopra struct qed_ptt *p_ptt, 3069a64b02d5SManish Chopra struct qed_mcp_link_state *p_link, 3070a64b02d5SManish Chopra u8 min_bw) 3071a64b02d5SManish Chopra { 3072a64b02d5SManish Chopra int rc = 0; 3073a64b02d5SManish Chopra 3074a64b02d5SManish Chopra p_hwfn->mcp_info->func_info.bandwidth_min = min_bw; 3075a64b02d5SManish Chopra p_hwfn->qm_info.pf_wfq = min_bw; 3076a64b02d5SManish Chopra 3077a64b02d5SManish Chopra if (!p_link->line_speed) 3078a64b02d5SManish Chopra return rc; 3079a64b02d5SManish Chopra 3080a64b02d5SManish Chopra p_link->min_pf_rate = (p_link->line_speed * min_bw) / 100; 3081a64b02d5SManish Chopra 3082a64b02d5SManish Chopra rc = qed_init_pf_wfq(p_hwfn, p_ptt, p_hwfn->rel_pf_id, min_bw); 3083a64b02d5SManish Chopra 3084a64b02d5SManish Chopra DP_VERBOSE(p_hwfn, NETIF_MSG_LINK, 3085a64b02d5SManish Chopra "Configured MIN bandwidth to be %d Mb/sec\n", 3086a64b02d5SManish Chopra p_link->min_pf_rate); 3087a64b02d5SManish Chopra 3088a64b02d5SManish Chopra return rc; 3089a64b02d5SManish Chopra } 3090a64b02d5SManish Chopra 3091a64b02d5SManish Chopra /* Main API to configure PF min bandwidth where bw range is [1-100] */ 3092a64b02d5SManish Chopra int qed_configure_pf_min_bandwidth(struct qed_dev *cdev, u8 min_bw) 3093a64b02d5SManish Chopra { 3094a64b02d5SManish Chopra int i, rc = -EINVAL; 3095a64b02d5SManish Chopra 3096a64b02d5SManish Chopra if (min_bw < 1 || min_bw > 100) { 3097a64b02d5SManish Chopra DP_NOTICE(cdev, "PF min bw valid range is [1-100]\n"); 3098a64b02d5SManish Chopra return rc; 3099a64b02d5SManish Chopra } 3100a64b02d5SManish Chopra 3101a64b02d5SManish Chopra for_each_hwfn(cdev, i) { 3102a64b02d5SManish Chopra struct qed_hwfn *p_hwfn = &cdev->hwfns[i]; 3103a64b02d5SManish Chopra struct qed_hwfn *p_lead = QED_LEADING_HWFN(cdev); 3104a64b02d5SManish Chopra struct qed_mcp_link_state *p_link; 3105a64b02d5SManish Chopra struct qed_ptt *p_ptt; 3106a64b02d5SManish Chopra 3107a64b02d5SManish Chopra p_link = &p_lead->mcp_info->link_output; 3108a64b02d5SManish Chopra 3109a64b02d5SManish Chopra p_ptt = qed_ptt_acquire(p_hwfn); 3110a64b02d5SManish Chopra if (!p_ptt) 3111a64b02d5SManish Chopra return -EBUSY; 3112a64b02d5SManish Chopra 3113a64b02d5SManish Chopra rc = __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, 3114a64b02d5SManish Chopra p_link, min_bw); 3115a64b02d5SManish Chopra if (rc) { 3116a64b02d5SManish Chopra qed_ptt_release(p_hwfn, p_ptt); 3117a64b02d5SManish Chopra return rc; 3118a64b02d5SManish Chopra } 3119a64b02d5SManish Chopra 3120a64b02d5SManish Chopra if (p_link->min_pf_rate) { 3121a64b02d5SManish Chopra u32 min_rate = p_link->min_pf_rate; 3122a64b02d5SManish Chopra 3123a64b02d5SManish Chopra rc = __qed_configure_vp_wfq_on_link_change(p_hwfn, 3124a64b02d5SManish Chopra p_ptt, 3125a64b02d5SManish Chopra min_rate); 3126a64b02d5SManish Chopra } 3127a64b02d5SManish Chopra 3128a64b02d5SManish Chopra qed_ptt_release(p_hwfn, p_ptt); 3129a64b02d5SManish Chopra } 3130a64b02d5SManish Chopra 3131a64b02d5SManish Chopra return rc; 3132a64b02d5SManish Chopra } 3133733def6aSYuval Mintz 3134733def6aSYuval Mintz void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 3135733def6aSYuval Mintz { 3136733def6aSYuval Mintz struct qed_mcp_link_state *p_link; 3137733def6aSYuval Mintz 3138733def6aSYuval Mintz p_link = &p_hwfn->mcp_info->link_output; 3139733def6aSYuval Mintz 3140733def6aSYuval Mintz if (p_link->min_pf_rate) 3141733def6aSYuval Mintz qed_disable_wfq_for_all_vports(p_hwfn, p_ptt, 3142733def6aSYuval Mintz p_link->min_pf_rate); 3143733def6aSYuval Mintz 3144733def6aSYuval Mintz memset(p_hwfn->qm_info.wfq_data, 0, 3145733def6aSYuval Mintz sizeof(*p_hwfn->qm_info.wfq_data) * p_hwfn->qm_info.num_vports); 3146733def6aSYuval Mintz } 3147