1c965db44STomer Tayar /* QLogic qed NIC Driver 2c965db44STomer Tayar * Copyright (c) 2015 QLogic Corporation 3c965db44STomer Tayar * 4c965db44STomer Tayar * This software is available under the terms of the GNU General Public License 5c965db44STomer Tayar * (GPL) Version 2, available from the file COPYING in the main directory of 6c965db44STomer Tayar * this source tree. 7c965db44STomer Tayar */ 8c965db44STomer Tayar 9c965db44STomer Tayar #include <linux/module.h> 10c965db44STomer Tayar #include <linux/vmalloc.h> 11c965db44STomer Tayar #include <linux/crc32.h> 12c965db44STomer Tayar #include "qed.h" 13c965db44STomer Tayar #include "qed_hsi.h" 14c965db44STomer Tayar #include "qed_hw.h" 15c965db44STomer Tayar #include "qed_mcp.h" 16c965db44STomer Tayar #include "qed_reg_addr.h" 17c965db44STomer Tayar 18c965db44STomer Tayar /* Memory groups enum */ 19c965db44STomer Tayar enum mem_groups { 20c965db44STomer Tayar MEM_GROUP_PXP_MEM, 21c965db44STomer Tayar MEM_GROUP_DMAE_MEM, 22c965db44STomer Tayar MEM_GROUP_CM_MEM, 23c965db44STomer Tayar MEM_GROUP_QM_MEM, 24da090917STomer Tayar MEM_GROUP_DORQ_MEM, 25c965db44STomer Tayar MEM_GROUP_BRB_RAM, 26c965db44STomer Tayar MEM_GROUP_BRB_MEM, 27c965db44STomer Tayar MEM_GROUP_PRS_MEM, 28c965db44STomer Tayar MEM_GROUP_IOR, 29c965db44STomer Tayar MEM_GROUP_BTB_RAM, 30c965db44STomer Tayar MEM_GROUP_CONN_CFC_MEM, 31c965db44STomer Tayar MEM_GROUP_TASK_CFC_MEM, 32c965db44STomer Tayar MEM_GROUP_CAU_PI, 33c965db44STomer Tayar MEM_GROUP_CAU_MEM, 34c965db44STomer Tayar MEM_GROUP_PXP_ILT, 35da090917STomer Tayar MEM_GROUP_TM_MEM, 36da090917STomer Tayar MEM_GROUP_SDM_MEM, 377b6859fbSMintz, Yuval MEM_GROUP_PBUF, 38da090917STomer Tayar MEM_GROUP_RAM, 39c965db44STomer Tayar MEM_GROUP_MULD_MEM, 40c965db44STomer Tayar MEM_GROUP_BTB_MEM, 41da090917STomer Tayar MEM_GROUP_RDIF_CTX, 42da090917STomer Tayar MEM_GROUP_TDIF_CTX, 43da090917STomer Tayar MEM_GROUP_CFC_MEM, 44c965db44STomer Tayar MEM_GROUP_IGU_MEM, 45c965db44STomer Tayar MEM_GROUP_IGU_MSIX, 46c965db44STomer Tayar MEM_GROUP_CAU_SB, 47c965db44STomer Tayar MEM_GROUP_BMB_RAM, 48c965db44STomer Tayar MEM_GROUP_BMB_MEM, 49c965db44STomer Tayar MEM_GROUPS_NUM 50c965db44STomer Tayar }; 51c965db44STomer Tayar 52c965db44STomer Tayar /* Memory groups names */ 53c965db44STomer Tayar static const char * const s_mem_group_names[] = { 54c965db44STomer Tayar "PXP_MEM", 55c965db44STomer Tayar "DMAE_MEM", 56c965db44STomer Tayar "CM_MEM", 57c965db44STomer Tayar "QM_MEM", 58da090917STomer Tayar "DORQ_MEM", 59c965db44STomer Tayar "BRB_RAM", 60c965db44STomer Tayar "BRB_MEM", 61c965db44STomer Tayar "PRS_MEM", 62c965db44STomer Tayar "IOR", 63c965db44STomer Tayar "BTB_RAM", 64c965db44STomer Tayar "CONN_CFC_MEM", 65c965db44STomer Tayar "TASK_CFC_MEM", 66c965db44STomer Tayar "CAU_PI", 67c965db44STomer Tayar "CAU_MEM", 68c965db44STomer Tayar "PXP_ILT", 69da090917STomer Tayar "TM_MEM", 70da090917STomer Tayar "SDM_MEM", 717b6859fbSMintz, Yuval "PBUF", 72da090917STomer Tayar "RAM", 73c965db44STomer Tayar "MULD_MEM", 74c965db44STomer Tayar "BTB_MEM", 75da090917STomer Tayar "RDIF_CTX", 76da090917STomer Tayar "TDIF_CTX", 77da090917STomer Tayar "CFC_MEM", 78c965db44STomer Tayar "IGU_MEM", 79c965db44STomer Tayar "IGU_MSIX", 80c965db44STomer Tayar "CAU_SB", 81c965db44STomer Tayar "BMB_RAM", 82c965db44STomer Tayar "BMB_MEM", 83c965db44STomer Tayar }; 84c965db44STomer Tayar 85c965db44STomer Tayar /* Idle check conditions */ 867b6859fbSMintz, Yuval 877b6859fbSMintz, Yuval static u32 cond5(const u32 *r, const u32 *imm) 88c965db44STomer Tayar { 89c965db44STomer Tayar return ((r[0] & imm[0]) != imm[1]) && ((r[1] & imm[2]) != imm[3]); 90c965db44STomer Tayar } 91c965db44STomer Tayar 927b6859fbSMintz, Yuval static u32 cond7(const u32 *r, const u32 *imm) 93c965db44STomer Tayar { 94c965db44STomer Tayar return ((r[0] >> imm[0]) & imm[1]) != imm[2]; 95c965db44STomer Tayar } 96c965db44STomer Tayar 977b6859fbSMintz, Yuval static u32 cond6(const u32 *r, const u32 *imm) 98c965db44STomer Tayar { 99c965db44STomer Tayar return (r[0] & imm[0]) != imm[1]; 100c965db44STomer Tayar } 101c965db44STomer Tayar 1027b6859fbSMintz, Yuval static u32 cond9(const u32 *r, const u32 *imm) 103c965db44STomer Tayar { 104c965db44STomer Tayar return ((r[0] & imm[0]) >> imm[1]) != 105c965db44STomer Tayar (((r[0] & imm[2]) >> imm[3]) | ((r[1] & imm[4]) << imm[5])); 106c965db44STomer Tayar } 107c965db44STomer Tayar 1087b6859fbSMintz, Yuval static u32 cond10(const u32 *r, const u32 *imm) 109c965db44STomer Tayar { 110c965db44STomer Tayar return ((r[0] & imm[0]) >> imm[1]) != (r[0] & imm[2]); 111c965db44STomer Tayar } 112c965db44STomer Tayar 1137b6859fbSMintz, Yuval static u32 cond4(const u32 *r, const u32 *imm) 114c965db44STomer Tayar { 115c965db44STomer Tayar return (r[0] & ~imm[0]) != imm[1]; 116c965db44STomer Tayar } 117c965db44STomer Tayar 118c965db44STomer Tayar static u32 cond0(const u32 *r, const u32 *imm) 119c965db44STomer Tayar { 1207b6859fbSMintz, Yuval return (r[0] & ~r[1]) != imm[0]; 1217b6859fbSMintz, Yuval } 1227b6859fbSMintz, Yuval 1237b6859fbSMintz, Yuval static u32 cond1(const u32 *r, const u32 *imm) 1247b6859fbSMintz, Yuval { 125c965db44STomer Tayar return r[0] != imm[0]; 126c965db44STomer Tayar } 127c965db44STomer Tayar 1287b6859fbSMintz, Yuval static u32 cond11(const u32 *r, const u32 *imm) 129c965db44STomer Tayar { 130c965db44STomer Tayar return r[0] != r[1] && r[2] == imm[0]; 131c965db44STomer Tayar } 132c965db44STomer Tayar 1337b6859fbSMintz, Yuval static u32 cond12(const u32 *r, const u32 *imm) 134c965db44STomer Tayar { 135c965db44STomer Tayar return r[0] != r[1] && r[2] > imm[0]; 136c965db44STomer Tayar } 137c965db44STomer Tayar 138c965db44STomer Tayar static u32 cond3(const u32 *r, const u32 *imm) 139c965db44STomer Tayar { 140c965db44STomer Tayar return r[0] != r[1]; 141c965db44STomer Tayar } 142c965db44STomer Tayar 1437b6859fbSMintz, Yuval static u32 cond13(const u32 *r, const u32 *imm) 144c965db44STomer Tayar { 145c965db44STomer Tayar return r[0] & imm[0]; 146c965db44STomer Tayar } 147c965db44STomer Tayar 1487b6859fbSMintz, Yuval static u32 cond8(const u32 *r, const u32 *imm) 149c965db44STomer Tayar { 150c965db44STomer Tayar return r[0] < (r[1] - imm[0]); 151c965db44STomer Tayar } 152c965db44STomer Tayar 153c965db44STomer Tayar static u32 cond2(const u32 *r, const u32 *imm) 154c965db44STomer Tayar { 155c965db44STomer Tayar return r[0] > imm[0]; 156c965db44STomer Tayar } 157c965db44STomer Tayar 158c965db44STomer Tayar /* Array of Idle Check conditions */ 159c965db44STomer Tayar static u32(*cond_arr[]) (const u32 *r, const u32 *imm) = { 160c965db44STomer Tayar cond0, 161c965db44STomer Tayar cond1, 162c965db44STomer Tayar cond2, 163c965db44STomer Tayar cond3, 164c965db44STomer Tayar cond4, 165c965db44STomer Tayar cond5, 166c965db44STomer Tayar cond6, 167c965db44STomer Tayar cond7, 168c965db44STomer Tayar cond8, 169c965db44STomer Tayar cond9, 170c965db44STomer Tayar cond10, 171c965db44STomer Tayar cond11, 172c965db44STomer Tayar cond12, 1737b6859fbSMintz, Yuval cond13, 174c965db44STomer Tayar }; 175c965db44STomer Tayar 176c965db44STomer Tayar /******************************* Data Types **********************************/ 177c965db44STomer Tayar 178c965db44STomer Tayar enum platform_ids { 179c965db44STomer Tayar PLATFORM_ASIC, 180c965db44STomer Tayar PLATFORM_RESERVED, 181c965db44STomer Tayar PLATFORM_RESERVED2, 182c965db44STomer Tayar PLATFORM_RESERVED3, 183c965db44STomer Tayar MAX_PLATFORM_IDS 184c965db44STomer Tayar }; 185c965db44STomer Tayar 186be086e7cSMintz, Yuval struct chip_platform_defs { 187be086e7cSMintz, Yuval u8 num_ports; 188be086e7cSMintz, Yuval u8 num_pfs; 189be086e7cSMintz, Yuval u8 num_vfs; 190be086e7cSMintz, Yuval }; 191be086e7cSMintz, Yuval 192c965db44STomer Tayar /* Chip constant definitions */ 193c965db44STomer Tayar struct chip_defs { 194c965db44STomer Tayar const char *name; 195be086e7cSMintz, Yuval struct chip_platform_defs per_platform[MAX_PLATFORM_IDS]; 196c965db44STomer Tayar }; 197c965db44STomer Tayar 198c965db44STomer Tayar /* Platform constant definitions */ 199c965db44STomer Tayar struct platform_defs { 200c965db44STomer Tayar const char *name; 201c965db44STomer Tayar u32 delay_factor; 202da090917STomer Tayar u32 dmae_thresh; 203da090917STomer Tayar u32 log_thresh; 204c965db44STomer Tayar }; 205c965db44STomer Tayar 2067b6859fbSMintz, Yuval /* Storm constant definitions. 2077b6859fbSMintz, Yuval * Addresses are in bytes, sizes are in quad-regs. 2087b6859fbSMintz, Yuval */ 209c965db44STomer Tayar struct storm_defs { 210c965db44STomer Tayar char letter; 211c965db44STomer Tayar enum block_id block_id; 212c965db44STomer Tayar enum dbg_bus_clients dbg_client_id[MAX_CHIP_IDS]; 213c965db44STomer Tayar bool has_vfc; 214c965db44STomer Tayar u32 sem_fast_mem_addr; 215c965db44STomer Tayar u32 sem_frame_mode_addr; 216c965db44STomer Tayar u32 sem_slow_enable_addr; 217c965db44STomer Tayar u32 sem_slow_mode_addr; 218c965db44STomer Tayar u32 sem_slow_mode1_conf_addr; 219c965db44STomer Tayar u32 sem_sync_dbg_empty_addr; 220c965db44STomer Tayar u32 sem_slow_dbg_empty_addr; 221c965db44STomer Tayar u32 cm_ctx_wr_addr; 2227b6859fbSMintz, Yuval u32 cm_conn_ag_ctx_lid_size; 223c965db44STomer Tayar u32 cm_conn_ag_ctx_rd_addr; 2247b6859fbSMintz, Yuval u32 cm_conn_st_ctx_lid_size; 225c965db44STomer Tayar u32 cm_conn_st_ctx_rd_addr; 2267b6859fbSMintz, Yuval u32 cm_task_ag_ctx_lid_size; 227c965db44STomer Tayar u32 cm_task_ag_ctx_rd_addr; 2287b6859fbSMintz, Yuval u32 cm_task_st_ctx_lid_size; 229c965db44STomer Tayar u32 cm_task_st_ctx_rd_addr; 230c965db44STomer Tayar }; 231c965db44STomer Tayar 232c965db44STomer Tayar /* Block constant definitions */ 233c965db44STomer Tayar struct block_defs { 234c965db44STomer Tayar const char *name; 235da090917STomer Tayar bool exists[MAX_CHIP_IDS]; 236c965db44STomer Tayar bool associated_to_storm; 2377b6859fbSMintz, Yuval 2387b6859fbSMintz, Yuval /* Valid only if associated_to_storm is true */ 2397b6859fbSMintz, Yuval u32 storm_id; 240c965db44STomer Tayar enum dbg_bus_clients dbg_client_id[MAX_CHIP_IDS]; 241c965db44STomer Tayar u32 dbg_select_addr; 2427b6859fbSMintz, Yuval u32 dbg_enable_addr; 243c965db44STomer Tayar u32 dbg_shift_addr; 244c965db44STomer Tayar u32 dbg_force_valid_addr; 245c965db44STomer Tayar u32 dbg_force_frame_addr; 246c965db44STomer Tayar bool has_reset_bit; 2477b6859fbSMintz, Yuval 2487b6859fbSMintz, Yuval /* If true, block is taken out of reset before dump */ 2497b6859fbSMintz, Yuval bool unreset; 250c965db44STomer Tayar enum dbg_reset_regs reset_reg; 2517b6859fbSMintz, Yuval 2527b6859fbSMintz, Yuval /* Bit offset in reset register */ 2537b6859fbSMintz, Yuval u8 reset_bit_offset; 254c965db44STomer Tayar }; 255c965db44STomer Tayar 256c965db44STomer Tayar /* Reset register definitions */ 257c965db44STomer Tayar struct reset_reg_defs { 258c965db44STomer Tayar u32 addr; 259c965db44STomer Tayar bool exists[MAX_CHIP_IDS]; 260da090917STomer Tayar u32 unreset_val[MAX_CHIP_IDS]; 261c965db44STomer Tayar }; 262c965db44STomer Tayar 263c965db44STomer Tayar struct grc_param_defs { 264c965db44STomer Tayar u32 default_val[MAX_CHIP_IDS]; 265c965db44STomer Tayar u32 min; 266c965db44STomer Tayar u32 max; 267c965db44STomer Tayar bool is_preset; 268c965db44STomer Tayar u32 exclude_all_preset_val; 269c965db44STomer Tayar u32 crash_preset_val; 270c965db44STomer Tayar }; 271c965db44STomer Tayar 2727b6859fbSMintz, Yuval /* Address is in 128b units. Width is in bits. */ 273c965db44STomer Tayar struct rss_mem_defs { 274c965db44STomer Tayar const char *mem_name; 275c965db44STomer Tayar const char *type_name; 2767b6859fbSMintz, Yuval u32 addr; 277da090917STomer Tayar u32 entry_width; 278c965db44STomer Tayar u32 num_entries[MAX_CHIP_IDS]; 279c965db44STomer Tayar }; 280c965db44STomer Tayar 281c965db44STomer Tayar struct vfc_ram_defs { 282c965db44STomer Tayar const char *mem_name; 283c965db44STomer Tayar const char *type_name; 284c965db44STomer Tayar u32 base_row; 285c965db44STomer Tayar u32 num_rows; 286c965db44STomer Tayar }; 287c965db44STomer Tayar 288c965db44STomer Tayar struct big_ram_defs { 289c965db44STomer Tayar const char *instance_name; 290c965db44STomer Tayar enum mem_groups mem_group_id; 291c965db44STomer Tayar enum mem_groups ram_mem_group_id; 292c965db44STomer Tayar enum dbg_grc_params grc_param; 293c965db44STomer Tayar u32 addr_reg_addr; 294c965db44STomer Tayar u32 data_reg_addr; 295da090917STomer Tayar u32 is_256b_reg_addr; 296da090917STomer Tayar u32 is_256b_bit_offset[MAX_CHIP_IDS]; 297da090917STomer Tayar u32 ram_size[MAX_CHIP_IDS]; /* In dwords */ 298c965db44STomer Tayar }; 299c965db44STomer Tayar 300c965db44STomer Tayar struct phy_defs { 301c965db44STomer Tayar const char *phy_name; 3027b6859fbSMintz, Yuval 3037b6859fbSMintz, Yuval /* PHY base GRC address */ 304c965db44STomer Tayar u32 base_addr; 3057b6859fbSMintz, Yuval 3067b6859fbSMintz, Yuval /* Relative address of indirect TBUS address register (bits 0..7) */ 307c965db44STomer Tayar u32 tbus_addr_lo_addr; 3087b6859fbSMintz, Yuval 3097b6859fbSMintz, Yuval /* Relative address of indirect TBUS address register (bits 8..10) */ 310c965db44STomer Tayar u32 tbus_addr_hi_addr; 3117b6859fbSMintz, Yuval 3127b6859fbSMintz, Yuval /* Relative address of indirect TBUS data register (bits 0..7) */ 313c965db44STomer Tayar u32 tbus_data_lo_addr; 3147b6859fbSMintz, Yuval 3157b6859fbSMintz, Yuval /* Relative address of indirect TBUS data register (bits 8..11) */ 316c965db44STomer Tayar u32 tbus_data_hi_addr; 317c965db44STomer Tayar }; 318c965db44STomer Tayar 319c965db44STomer Tayar /******************************** Constants **********************************/ 320c965db44STomer Tayar 321c965db44STomer Tayar #define MAX_LCIDS 320 322c965db44STomer Tayar #define MAX_LTIDS 320 3237b6859fbSMintz, Yuval 324c965db44STomer Tayar #define NUM_IOR_SETS 2 325c965db44STomer Tayar #define IORS_PER_SET 176 326c965db44STomer Tayar #define IOR_SET_OFFSET(set_id) ((set_id) * 256) 3277b6859fbSMintz, Yuval 328c965db44STomer Tayar #define BYTES_IN_DWORD sizeof(u32) 329c965db44STomer Tayar 330c965db44STomer Tayar /* In the macros below, size and offset are specified in bits */ 331c965db44STomer Tayar #define CEIL_DWORDS(size) DIV_ROUND_UP(size, 32) 332c965db44STomer Tayar #define FIELD_BIT_OFFSET(type, field) type ## _ ## field ## _ ## OFFSET 333c965db44STomer Tayar #define FIELD_BIT_SIZE(type, field) type ## _ ## field ## _ ## SIZE 334c965db44STomer Tayar #define FIELD_DWORD_OFFSET(type, field) \ 335c965db44STomer Tayar (int)(FIELD_BIT_OFFSET(type, field) / 32) 336c965db44STomer Tayar #define FIELD_DWORD_SHIFT(type, field) (FIELD_BIT_OFFSET(type, field) % 32) 337c965db44STomer Tayar #define FIELD_BIT_MASK(type, field) \ 338c965db44STomer Tayar (((1 << FIELD_BIT_SIZE(type, field)) - 1) << \ 339c965db44STomer Tayar FIELD_DWORD_SHIFT(type, field)) 3407b6859fbSMintz, Yuval 341c965db44STomer Tayar #define SET_VAR_FIELD(var, type, field, val) \ 342c965db44STomer Tayar do { \ 343c965db44STomer Tayar var[FIELD_DWORD_OFFSET(type, field)] &= \ 344c965db44STomer Tayar (~FIELD_BIT_MASK(type, field)); \ 345c965db44STomer Tayar var[FIELD_DWORD_OFFSET(type, field)] |= \ 346c965db44STomer Tayar (val) << FIELD_DWORD_SHIFT(type, field); \ 347c965db44STomer Tayar } while (0) 3487b6859fbSMintz, Yuval 349c965db44STomer Tayar #define ARR_REG_WR(dev, ptt, addr, arr, arr_size) \ 350c965db44STomer Tayar do { \ 351c965db44STomer Tayar for (i = 0; i < (arr_size); i++) \ 352c965db44STomer Tayar qed_wr(dev, ptt, addr, (arr)[i]); \ 353c965db44STomer Tayar } while (0) 3547b6859fbSMintz, Yuval 355c965db44STomer Tayar #define ARR_REG_RD(dev, ptt, addr, arr, arr_size) \ 356c965db44STomer Tayar do { \ 357c965db44STomer Tayar for (i = 0; i < (arr_size); i++) \ 358c965db44STomer Tayar (arr)[i] = qed_rd(dev, ptt, addr); \ 359c965db44STomer Tayar } while (0) 360c965db44STomer Tayar 361c965db44STomer Tayar #define DWORDS_TO_BYTES(dwords) ((dwords) * BYTES_IN_DWORD) 362c965db44STomer Tayar #define BYTES_TO_DWORDS(bytes) ((bytes) / BYTES_IN_DWORD) 3637b6859fbSMintz, Yuval 364a2e7699eSTomer Tayar /* Extra lines include a signature line + optional latency events line */ 3657b6859fbSMintz, Yuval #define NUM_EXTRA_DBG_LINES(block_desc) \ 3667b6859fbSMintz, Yuval (1 + ((block_desc)->has_latency_events ? 1 : 0)) 3677b6859fbSMintz, Yuval #define NUM_DBG_LINES(block_desc) \ 3687b6859fbSMintz, Yuval ((block_desc)->num_of_lines + NUM_EXTRA_DBG_LINES(block_desc)) 3697b6859fbSMintz, Yuval 370c965db44STomer Tayar #define RAM_LINES_TO_DWORDS(lines) ((lines) * 2) 371c965db44STomer Tayar #define RAM_LINES_TO_BYTES(lines) \ 372c965db44STomer Tayar DWORDS_TO_BYTES(RAM_LINES_TO_DWORDS(lines)) 3737b6859fbSMintz, Yuval 374c965db44STomer Tayar #define REG_DUMP_LEN_SHIFT 24 375c965db44STomer Tayar #define MEM_DUMP_ENTRY_SIZE_DWORDS \ 376c965db44STomer Tayar BYTES_TO_DWORDS(sizeof(struct dbg_dump_mem)) 3777b6859fbSMintz, Yuval 378c965db44STomer Tayar #define IDLE_CHK_RULE_SIZE_DWORDS \ 379c965db44STomer Tayar BYTES_TO_DWORDS(sizeof(struct dbg_idle_chk_rule)) 3807b6859fbSMintz, Yuval 381c965db44STomer Tayar #define IDLE_CHK_RESULT_HDR_DWORDS \ 382c965db44STomer Tayar BYTES_TO_DWORDS(sizeof(struct dbg_idle_chk_result_hdr)) 3837b6859fbSMintz, Yuval 384c965db44STomer Tayar #define IDLE_CHK_RESULT_REG_HDR_DWORDS \ 385c965db44STomer Tayar BYTES_TO_DWORDS(sizeof(struct dbg_idle_chk_result_reg_hdr)) 3867b6859fbSMintz, Yuval 387c965db44STomer Tayar #define IDLE_CHK_MAX_ENTRIES_SIZE 32 388c965db44STomer Tayar 389c965db44STomer Tayar /* The sizes and offsets below are specified in bits */ 390c965db44STomer Tayar #define VFC_CAM_CMD_STRUCT_SIZE 64 391c965db44STomer Tayar #define VFC_CAM_CMD_ROW_OFFSET 48 392c965db44STomer Tayar #define VFC_CAM_CMD_ROW_SIZE 9 393c965db44STomer Tayar #define VFC_CAM_ADDR_STRUCT_SIZE 16 394c965db44STomer Tayar #define VFC_CAM_ADDR_OP_OFFSET 0 395c965db44STomer Tayar #define VFC_CAM_ADDR_OP_SIZE 4 396c965db44STomer Tayar #define VFC_CAM_RESP_STRUCT_SIZE 256 397c965db44STomer Tayar #define VFC_RAM_ADDR_STRUCT_SIZE 16 398c965db44STomer Tayar #define VFC_RAM_ADDR_OP_OFFSET 0 399c965db44STomer Tayar #define VFC_RAM_ADDR_OP_SIZE 2 400c965db44STomer Tayar #define VFC_RAM_ADDR_ROW_OFFSET 2 401c965db44STomer Tayar #define VFC_RAM_ADDR_ROW_SIZE 10 402c965db44STomer Tayar #define VFC_RAM_RESP_STRUCT_SIZE 256 4037b6859fbSMintz, Yuval 404c965db44STomer Tayar #define VFC_CAM_CMD_DWORDS CEIL_DWORDS(VFC_CAM_CMD_STRUCT_SIZE) 405c965db44STomer Tayar #define VFC_CAM_ADDR_DWORDS CEIL_DWORDS(VFC_CAM_ADDR_STRUCT_SIZE) 406c965db44STomer Tayar #define VFC_CAM_RESP_DWORDS CEIL_DWORDS(VFC_CAM_RESP_STRUCT_SIZE) 407c965db44STomer Tayar #define VFC_RAM_CMD_DWORDS VFC_CAM_CMD_DWORDS 408c965db44STomer Tayar #define VFC_RAM_ADDR_DWORDS CEIL_DWORDS(VFC_RAM_ADDR_STRUCT_SIZE) 409c965db44STomer Tayar #define VFC_RAM_RESP_DWORDS CEIL_DWORDS(VFC_RAM_RESP_STRUCT_SIZE) 4107b6859fbSMintz, Yuval 411c965db44STomer Tayar #define NUM_VFC_RAM_TYPES 4 4127b6859fbSMintz, Yuval 413c965db44STomer Tayar #define VFC_CAM_NUM_ROWS 512 4147b6859fbSMintz, Yuval 415c965db44STomer Tayar #define VFC_OPCODE_CAM_RD 14 416c965db44STomer Tayar #define VFC_OPCODE_RAM_RD 0 4177b6859fbSMintz, Yuval 418c965db44STomer Tayar #define NUM_RSS_MEM_TYPES 5 4197b6859fbSMintz, Yuval 420c965db44STomer Tayar #define NUM_BIG_RAM_TYPES 3 4217b6859fbSMintz, Yuval 422c965db44STomer Tayar #define NUM_PHY_TBUS_ADDRESSES 2048 423c965db44STomer Tayar #define PHY_DUMP_SIZE_DWORDS (NUM_PHY_TBUS_ADDRESSES / 2) 4247b6859fbSMintz, Yuval 425c965db44STomer Tayar #define RESET_REG_UNRESET_OFFSET 4 4267b6859fbSMintz, Yuval 427c965db44STomer Tayar #define STALL_DELAY_MS 500 4287b6859fbSMintz, Yuval 429c965db44STomer Tayar #define STATIC_DEBUG_LINE_DWORDS 9 4307b6859fbSMintz, Yuval 431c965db44STomer Tayar #define NUM_COMMON_GLOBAL_PARAMS 8 4327b6859fbSMintz, Yuval 433c965db44STomer Tayar #define FW_IMG_MAIN 1 4347b6859fbSMintz, Yuval 435c965db44STomer Tayar #define REG_FIFO_ELEMENT_DWORDS 2 4367b6859fbSMintz, Yuval #define REG_FIFO_DEPTH_ELEMENTS 32 437c965db44STomer Tayar #define REG_FIFO_DEPTH_DWORDS \ 438c965db44STomer Tayar (REG_FIFO_ELEMENT_DWORDS * REG_FIFO_DEPTH_ELEMENTS) 4397b6859fbSMintz, Yuval 440c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORDS 4 4417b6859fbSMintz, Yuval #define IGU_FIFO_DEPTH_ELEMENTS 64 442c965db44STomer Tayar #define IGU_FIFO_DEPTH_DWORDS \ 443c965db44STomer Tayar (IGU_FIFO_ELEMENT_DWORDS * IGU_FIFO_DEPTH_ELEMENTS) 4447b6859fbSMintz, Yuval 445c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_DWORDS 2 4467b6859fbSMintz, Yuval #define PROTECTION_OVERRIDE_DEPTH_ELEMENTS 20 447c965db44STomer Tayar #define PROTECTION_OVERRIDE_DEPTH_DWORDS \ 448c965db44STomer Tayar (PROTECTION_OVERRIDE_DEPTH_ELEMENTS * \ 449c965db44STomer Tayar PROTECTION_OVERRIDE_ELEMENT_DWORDS) 4507b6859fbSMintz, Yuval 451c965db44STomer Tayar #define MCP_SPAD_TRACE_OFFSIZE_ADDR \ 452c965db44STomer Tayar (MCP_REG_SCRATCH + \ 453c965db44STomer Tayar offsetof(struct static_init, sections[SPAD_SECTION_TRACE])) 4547b6859fbSMintz, Yuval 455c965db44STomer Tayar #define EMPTY_FW_VERSION_STR "???_???_???_???" 456c965db44STomer Tayar #define EMPTY_FW_IMAGE_STR "???????????????" 457c965db44STomer Tayar 458c965db44STomer Tayar /***************************** Constant Arrays *******************************/ 459c965db44STomer Tayar 4607b6859fbSMintz, Yuval struct dbg_array { 4617b6859fbSMintz, Yuval const u32 *ptr; 4627b6859fbSMintz, Yuval u32 size_in_dwords; 4637b6859fbSMintz, Yuval }; 4647b6859fbSMintz, Yuval 465c965db44STomer Tayar /* Debug arrays */ 4667b6859fbSMintz, Yuval static struct dbg_array s_dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE] = { {NULL} }; 467c965db44STomer Tayar 468c965db44STomer Tayar /* Chip constant definitions array */ 469c965db44STomer Tayar static struct chip_defs s_chip_defs[MAX_CHIP_IDS] = { 4707b6859fbSMintz, Yuval { "bb", 4717b6859fbSMintz, Yuval {{MAX_NUM_PORTS_BB, MAX_NUM_PFS_BB, MAX_NUM_VFS_BB}, 4727b6859fbSMintz, Yuval {0, 0, 0}, 4737b6859fbSMintz, Yuval {0, 0, 0}, 4747b6859fbSMintz, Yuval {0, 0, 0} } }, 4757b6859fbSMintz, Yuval { "ah", 4767b6859fbSMintz, Yuval {{MAX_NUM_PORTS_K2, MAX_NUM_PFS_K2, MAX_NUM_VFS_K2}, 4777b6859fbSMintz, Yuval {0, 0, 0}, 4787b6859fbSMintz, Yuval {0, 0, 0}, 479da090917STomer Tayar {0, 0, 0} } }, 480da090917STomer Tayar { "reserved", 481da090917STomer Tayar {{0, 0, 0}, 482da090917STomer Tayar {0, 0, 0}, 483da090917STomer Tayar {0, 0, 0}, 4847b6859fbSMintz, Yuval {0, 0, 0} } } 485c965db44STomer Tayar }; 486c965db44STomer Tayar 487c965db44STomer Tayar /* Storm constant definitions array */ 488c965db44STomer Tayar static struct storm_defs s_storm_defs[] = { 489c965db44STomer Tayar /* Tstorm */ 490c965db44STomer Tayar {'T', BLOCK_TSEM, 491da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, 492da090917STomer Tayar DBG_BUS_CLIENT_RBCT}, true, 493c965db44STomer Tayar TSEM_REG_FAST_MEMORY, 4947b6859fbSMintz, Yuval TSEM_REG_DBG_FRAME_MODE_BB_K2, TSEM_REG_SLOW_DBG_ACTIVE_BB_K2, 4957b6859fbSMintz, Yuval TSEM_REG_SLOW_DBG_MODE_BB_K2, TSEM_REG_DBG_MODE1_CFG_BB_K2, 4967b6859fbSMintz, Yuval TSEM_REG_SYNC_DBG_EMPTY, TSEM_REG_SLOW_DBG_EMPTY_BB_K2, 497c965db44STomer Tayar TCM_REG_CTX_RBC_ACCS, 498c965db44STomer Tayar 4, TCM_REG_AGG_CON_CTX, 499c965db44STomer Tayar 16, TCM_REG_SM_CON_CTX, 500c965db44STomer Tayar 2, TCM_REG_AGG_TASK_CTX, 501c965db44STomer Tayar 4, TCM_REG_SM_TASK_CTX}, 5027b6859fbSMintz, Yuval 503c965db44STomer Tayar /* Mstorm */ 504c965db44STomer Tayar {'M', BLOCK_MSEM, 505da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, 506da090917STomer Tayar DBG_BUS_CLIENT_RBCM}, false, 507c965db44STomer Tayar MSEM_REG_FAST_MEMORY, 5087b6859fbSMintz, Yuval MSEM_REG_DBG_FRAME_MODE_BB_K2, MSEM_REG_SLOW_DBG_ACTIVE_BB_K2, 5097b6859fbSMintz, Yuval MSEM_REG_SLOW_DBG_MODE_BB_K2, MSEM_REG_DBG_MODE1_CFG_BB_K2, 5107b6859fbSMintz, Yuval MSEM_REG_SYNC_DBG_EMPTY, MSEM_REG_SLOW_DBG_EMPTY_BB_K2, 511c965db44STomer Tayar MCM_REG_CTX_RBC_ACCS, 512c965db44STomer Tayar 1, MCM_REG_AGG_CON_CTX, 513c965db44STomer Tayar 10, MCM_REG_SM_CON_CTX, 514c965db44STomer Tayar 2, MCM_REG_AGG_TASK_CTX, 515c965db44STomer Tayar 7, MCM_REG_SM_TASK_CTX}, 5167b6859fbSMintz, Yuval 517c965db44STomer Tayar /* Ustorm */ 518c965db44STomer Tayar {'U', BLOCK_USEM, 519da090917STomer Tayar {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, 520da090917STomer Tayar DBG_BUS_CLIENT_RBCU}, false, 521c965db44STomer Tayar USEM_REG_FAST_MEMORY, 5227b6859fbSMintz, Yuval USEM_REG_DBG_FRAME_MODE_BB_K2, USEM_REG_SLOW_DBG_ACTIVE_BB_K2, 5237b6859fbSMintz, Yuval USEM_REG_SLOW_DBG_MODE_BB_K2, USEM_REG_DBG_MODE1_CFG_BB_K2, 5247b6859fbSMintz, Yuval USEM_REG_SYNC_DBG_EMPTY, USEM_REG_SLOW_DBG_EMPTY_BB_K2, 525c965db44STomer Tayar UCM_REG_CTX_RBC_ACCS, 526c965db44STomer Tayar 2, UCM_REG_AGG_CON_CTX, 527c965db44STomer Tayar 13, UCM_REG_SM_CON_CTX, 528c965db44STomer Tayar 3, UCM_REG_AGG_TASK_CTX, 529c965db44STomer Tayar 3, UCM_REG_SM_TASK_CTX}, 5307b6859fbSMintz, Yuval 531c965db44STomer Tayar /* Xstorm */ 532c965db44STomer Tayar {'X', BLOCK_XSEM, 533da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, 534da090917STomer Tayar DBG_BUS_CLIENT_RBCX}, false, 535c965db44STomer Tayar XSEM_REG_FAST_MEMORY, 5367b6859fbSMintz, Yuval XSEM_REG_DBG_FRAME_MODE_BB_K2, XSEM_REG_SLOW_DBG_ACTIVE_BB_K2, 5377b6859fbSMintz, Yuval XSEM_REG_SLOW_DBG_MODE_BB_K2, XSEM_REG_DBG_MODE1_CFG_BB_K2, 5387b6859fbSMintz, Yuval XSEM_REG_SYNC_DBG_EMPTY, XSEM_REG_SLOW_DBG_EMPTY_BB_K2, 539c965db44STomer Tayar XCM_REG_CTX_RBC_ACCS, 540c965db44STomer Tayar 9, XCM_REG_AGG_CON_CTX, 541c965db44STomer Tayar 15, XCM_REG_SM_CON_CTX, 542c965db44STomer Tayar 0, 0, 543c965db44STomer Tayar 0, 0}, 5447b6859fbSMintz, Yuval 545c965db44STomer Tayar /* Ystorm */ 546c965db44STomer Tayar {'Y', BLOCK_YSEM, 547da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, 548da090917STomer Tayar DBG_BUS_CLIENT_RBCY}, false, 549c965db44STomer Tayar YSEM_REG_FAST_MEMORY, 5507b6859fbSMintz, Yuval YSEM_REG_DBG_FRAME_MODE_BB_K2, YSEM_REG_SLOW_DBG_ACTIVE_BB_K2, 5517b6859fbSMintz, Yuval YSEM_REG_SLOW_DBG_MODE_BB_K2, YSEM_REG_DBG_MODE1_CFG_BB_K2, 5527b6859fbSMintz, Yuval YSEM_REG_SYNC_DBG_EMPTY, TSEM_REG_SLOW_DBG_EMPTY_BB_K2, 553c965db44STomer Tayar YCM_REG_CTX_RBC_ACCS, 554c965db44STomer Tayar 2, YCM_REG_AGG_CON_CTX, 555c965db44STomer Tayar 3, YCM_REG_SM_CON_CTX, 556c965db44STomer Tayar 2, YCM_REG_AGG_TASK_CTX, 557c965db44STomer Tayar 12, YCM_REG_SM_TASK_CTX}, 5587b6859fbSMintz, Yuval 559c965db44STomer Tayar /* Pstorm */ 560c965db44STomer Tayar {'P', BLOCK_PSEM, 561da090917STomer Tayar {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, 562da090917STomer Tayar DBG_BUS_CLIENT_RBCS}, true, 563c965db44STomer Tayar PSEM_REG_FAST_MEMORY, 5647b6859fbSMintz, Yuval PSEM_REG_DBG_FRAME_MODE_BB_K2, PSEM_REG_SLOW_DBG_ACTIVE_BB_K2, 5657b6859fbSMintz, Yuval PSEM_REG_SLOW_DBG_MODE_BB_K2, PSEM_REG_DBG_MODE1_CFG_BB_K2, 5667b6859fbSMintz, Yuval PSEM_REG_SYNC_DBG_EMPTY, PSEM_REG_SLOW_DBG_EMPTY_BB_K2, 567c965db44STomer Tayar PCM_REG_CTX_RBC_ACCS, 568c965db44STomer Tayar 0, 0, 569c965db44STomer Tayar 10, PCM_REG_SM_CON_CTX, 570c965db44STomer Tayar 0, 0, 571c965db44STomer Tayar 0, 0} 572c965db44STomer Tayar }; 573c965db44STomer Tayar 574c965db44STomer Tayar /* Block definitions array */ 5757b6859fbSMintz, Yuval 576c965db44STomer Tayar static struct block_defs block_grc_defs = { 577be086e7cSMintz, Yuval "grc", 578da090917STomer Tayar {true, true, true}, false, 0, 579da090917STomer Tayar {DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN}, 580c965db44STomer Tayar GRC_REG_DBG_SELECT, GRC_REG_DBG_DWORD_ENABLE, 581c965db44STomer Tayar GRC_REG_DBG_SHIFT, GRC_REG_DBG_FORCE_VALID, 582c965db44STomer Tayar GRC_REG_DBG_FORCE_FRAME, 583c965db44STomer Tayar true, false, DBG_RESET_REG_MISC_PL_UA, 1 584c965db44STomer Tayar }; 585c965db44STomer Tayar 586c965db44STomer Tayar static struct block_defs block_miscs_defs = { 587da090917STomer Tayar "miscs", {true, true, true}, false, 0, 588da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 589c965db44STomer Tayar 0, 0, 0, 0, 0, 590c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 591c965db44STomer Tayar }; 592c965db44STomer Tayar 593c965db44STomer Tayar static struct block_defs block_misc_defs = { 594da090917STomer Tayar "misc", {true, true, true}, false, 0, 595da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 596c965db44STomer Tayar 0, 0, 0, 0, 0, 597c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 598c965db44STomer Tayar }; 599c965db44STomer Tayar 600c965db44STomer Tayar static struct block_defs block_dbu_defs = { 601da090917STomer Tayar "dbu", {true, true, true}, false, 0, 602da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 603c965db44STomer Tayar 0, 0, 0, 0, 0, 604c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 605c965db44STomer Tayar }; 606c965db44STomer Tayar 607c965db44STomer Tayar static struct block_defs block_pglue_b_defs = { 608be086e7cSMintz, Yuval "pglue_b", 609da090917STomer Tayar {true, true, true}, false, 0, 610da090917STomer Tayar {DBG_BUS_CLIENT_RBCH, DBG_BUS_CLIENT_RBCH, DBG_BUS_CLIENT_RBCH}, 611c965db44STomer Tayar PGLUE_B_REG_DBG_SELECT, PGLUE_B_REG_DBG_DWORD_ENABLE, 612c965db44STomer Tayar PGLUE_B_REG_DBG_SHIFT, PGLUE_B_REG_DBG_FORCE_VALID, 613c965db44STomer Tayar PGLUE_B_REG_DBG_FORCE_FRAME, 614c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV, 1 615c965db44STomer Tayar }; 616c965db44STomer Tayar 617c965db44STomer Tayar static struct block_defs block_cnig_defs = { 618be086e7cSMintz, Yuval "cnig", 619da090917STomer Tayar {true, true, true}, false, 0, 620da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW, 621da090917STomer Tayar DBG_BUS_CLIENT_RBCW}, 62221dd79e8STomer Tayar CNIG_REG_DBG_SELECT_K2_E5, CNIG_REG_DBG_DWORD_ENABLE_K2_E5, 62321dd79e8STomer Tayar CNIG_REG_DBG_SHIFT_K2_E5, CNIG_REG_DBG_FORCE_VALID_K2_E5, 62421dd79e8STomer Tayar CNIG_REG_DBG_FORCE_FRAME_K2_E5, 625c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV, 0 626c965db44STomer Tayar }; 627c965db44STomer Tayar 628c965db44STomer Tayar static struct block_defs block_cpmu_defs = { 629da090917STomer Tayar "cpmu", {true, true, true}, false, 0, 630da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 631c965db44STomer Tayar 0, 0, 0, 0, 0, 632c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV, 8 633c965db44STomer Tayar }; 634c965db44STomer Tayar 635c965db44STomer Tayar static struct block_defs block_ncsi_defs = { 636be086e7cSMintz, Yuval "ncsi", 637da090917STomer Tayar {true, true, true}, false, 0, 638da090917STomer Tayar {DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ}, 639c965db44STomer Tayar NCSI_REG_DBG_SELECT, NCSI_REG_DBG_DWORD_ENABLE, 640c965db44STomer Tayar NCSI_REG_DBG_SHIFT, NCSI_REG_DBG_FORCE_VALID, 641c965db44STomer Tayar NCSI_REG_DBG_FORCE_FRAME, 642c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV, 5 643c965db44STomer Tayar }; 644c965db44STomer Tayar 645c965db44STomer Tayar static struct block_defs block_opte_defs = { 646da090917STomer Tayar "opte", {true, true, false}, false, 0, 647da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 648c965db44STomer Tayar 0, 0, 0, 0, 0, 649c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV, 4 650c965db44STomer Tayar }; 651c965db44STomer Tayar 652c965db44STomer Tayar static struct block_defs block_bmb_defs = { 653be086e7cSMintz, Yuval "bmb", 654da090917STomer Tayar {true, true, true}, false, 0, 655da090917STomer Tayar {DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCB, DBG_BUS_CLIENT_RBCB}, 656c965db44STomer Tayar BMB_REG_DBG_SELECT, BMB_REG_DBG_DWORD_ENABLE, 657c965db44STomer Tayar BMB_REG_DBG_SHIFT, BMB_REG_DBG_FORCE_VALID, 658c965db44STomer Tayar BMB_REG_DBG_FORCE_FRAME, 659c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_UA, 7 660c965db44STomer Tayar }; 661c965db44STomer Tayar 662c965db44STomer Tayar static struct block_defs block_pcie_defs = { 663be086e7cSMintz, Yuval "pcie", 664da090917STomer Tayar {true, true, true}, false, 0, 665da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH, 666da090917STomer Tayar DBG_BUS_CLIENT_RBCH}, 66721dd79e8STomer Tayar PCIE_REG_DBG_COMMON_SELECT_K2_E5, 66821dd79e8STomer Tayar PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5, 66921dd79e8STomer Tayar PCIE_REG_DBG_COMMON_SHIFT_K2_E5, 67021dd79e8STomer Tayar PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5, 67121dd79e8STomer Tayar PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5, 672c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 673c965db44STomer Tayar }; 674c965db44STomer Tayar 675c965db44STomer Tayar static struct block_defs block_mcp_defs = { 676da090917STomer Tayar "mcp", {true, true, true}, false, 0, 677da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 678c965db44STomer Tayar 0, 0, 0, 0, 0, 679c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 680c965db44STomer Tayar }; 681c965db44STomer Tayar 682c965db44STomer Tayar static struct block_defs block_mcp2_defs = { 683be086e7cSMintz, Yuval "mcp2", 684da090917STomer Tayar {true, true, true}, false, 0, 685da090917STomer Tayar {DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ}, 686c965db44STomer Tayar MCP2_REG_DBG_SELECT, MCP2_REG_DBG_DWORD_ENABLE, 687c965db44STomer Tayar MCP2_REG_DBG_SHIFT, MCP2_REG_DBG_FORCE_VALID, 688c965db44STomer Tayar MCP2_REG_DBG_FORCE_FRAME, 689c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 690c965db44STomer Tayar }; 691c965db44STomer Tayar 692c965db44STomer Tayar static struct block_defs block_pswhst_defs = { 693be086e7cSMintz, Yuval "pswhst", 694da090917STomer Tayar {true, true, true}, false, 0, 695da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 696c965db44STomer Tayar PSWHST_REG_DBG_SELECT, PSWHST_REG_DBG_DWORD_ENABLE, 697c965db44STomer Tayar PSWHST_REG_DBG_SHIFT, PSWHST_REG_DBG_FORCE_VALID, 698c965db44STomer Tayar PSWHST_REG_DBG_FORCE_FRAME, 699c965db44STomer Tayar true, false, DBG_RESET_REG_MISC_PL_HV, 0 700c965db44STomer Tayar }; 701c965db44STomer Tayar 702c965db44STomer Tayar static struct block_defs block_pswhst2_defs = { 703be086e7cSMintz, Yuval "pswhst2", 704da090917STomer Tayar {true, true, true}, false, 0, 705da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 706c965db44STomer Tayar PSWHST2_REG_DBG_SELECT, PSWHST2_REG_DBG_DWORD_ENABLE, 707c965db44STomer Tayar PSWHST2_REG_DBG_SHIFT, PSWHST2_REG_DBG_FORCE_VALID, 708c965db44STomer Tayar PSWHST2_REG_DBG_FORCE_FRAME, 709c965db44STomer Tayar true, false, DBG_RESET_REG_MISC_PL_HV, 0 710c965db44STomer Tayar }; 711c965db44STomer Tayar 712c965db44STomer Tayar static struct block_defs block_pswrd_defs = { 713be086e7cSMintz, Yuval "pswrd", 714da090917STomer Tayar {true, true, true}, false, 0, 715da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 716c965db44STomer Tayar PSWRD_REG_DBG_SELECT, PSWRD_REG_DBG_DWORD_ENABLE, 717c965db44STomer Tayar PSWRD_REG_DBG_SHIFT, PSWRD_REG_DBG_FORCE_VALID, 718c965db44STomer Tayar PSWRD_REG_DBG_FORCE_FRAME, 719c965db44STomer Tayar true, false, DBG_RESET_REG_MISC_PL_HV, 2 720c965db44STomer Tayar }; 721c965db44STomer Tayar 722c965db44STomer Tayar static struct block_defs block_pswrd2_defs = { 723be086e7cSMintz, Yuval "pswrd2", 724da090917STomer Tayar {true, true, true}, false, 0, 725da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 726c965db44STomer Tayar PSWRD2_REG_DBG_SELECT, PSWRD2_REG_DBG_DWORD_ENABLE, 727c965db44STomer Tayar PSWRD2_REG_DBG_SHIFT, PSWRD2_REG_DBG_FORCE_VALID, 728c965db44STomer Tayar PSWRD2_REG_DBG_FORCE_FRAME, 729c965db44STomer Tayar true, false, DBG_RESET_REG_MISC_PL_HV, 2 730c965db44STomer Tayar }; 731c965db44STomer Tayar 732c965db44STomer Tayar static struct block_defs block_pswwr_defs = { 733be086e7cSMintz, Yuval "pswwr", 734da090917STomer Tayar {true, true, true}, false, 0, 735da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 736c965db44STomer Tayar PSWWR_REG_DBG_SELECT, PSWWR_REG_DBG_DWORD_ENABLE, 737c965db44STomer Tayar PSWWR_REG_DBG_SHIFT, PSWWR_REG_DBG_FORCE_VALID, 738c965db44STomer Tayar PSWWR_REG_DBG_FORCE_FRAME, 739c965db44STomer Tayar true, false, DBG_RESET_REG_MISC_PL_HV, 3 740c965db44STomer Tayar }; 741c965db44STomer Tayar 742c965db44STomer Tayar static struct block_defs block_pswwr2_defs = { 743da090917STomer Tayar "pswwr2", {true, true, true}, false, 0, 744da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 745c965db44STomer Tayar 0, 0, 0, 0, 0, 746c965db44STomer Tayar true, false, DBG_RESET_REG_MISC_PL_HV, 3 747c965db44STomer Tayar }; 748c965db44STomer Tayar 749c965db44STomer Tayar static struct block_defs block_pswrq_defs = { 750be086e7cSMintz, Yuval "pswrq", 751da090917STomer Tayar {true, true, true}, false, 0, 752da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 753c965db44STomer Tayar PSWRQ_REG_DBG_SELECT, PSWRQ_REG_DBG_DWORD_ENABLE, 754c965db44STomer Tayar PSWRQ_REG_DBG_SHIFT, PSWRQ_REG_DBG_FORCE_VALID, 755c965db44STomer Tayar PSWRQ_REG_DBG_FORCE_FRAME, 756c965db44STomer Tayar true, false, DBG_RESET_REG_MISC_PL_HV, 1 757c965db44STomer Tayar }; 758c965db44STomer Tayar 759c965db44STomer Tayar static struct block_defs block_pswrq2_defs = { 760be086e7cSMintz, Yuval "pswrq2", 761da090917STomer Tayar {true, true, true}, false, 0, 762da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 763c965db44STomer Tayar PSWRQ2_REG_DBG_SELECT, PSWRQ2_REG_DBG_DWORD_ENABLE, 764c965db44STomer Tayar PSWRQ2_REG_DBG_SHIFT, PSWRQ2_REG_DBG_FORCE_VALID, 765c965db44STomer Tayar PSWRQ2_REG_DBG_FORCE_FRAME, 766c965db44STomer Tayar true, false, DBG_RESET_REG_MISC_PL_HV, 1 767c965db44STomer Tayar }; 768c965db44STomer Tayar 769c965db44STomer Tayar static struct block_defs block_pglcs_defs = { 770be086e7cSMintz, Yuval "pglcs", 771da090917STomer Tayar {true, true, true}, false, 0, 772da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH, 773da090917STomer Tayar DBG_BUS_CLIENT_RBCH}, 77421dd79e8STomer Tayar PGLCS_REG_DBG_SELECT_K2_E5, PGLCS_REG_DBG_DWORD_ENABLE_K2_E5, 77521dd79e8STomer Tayar PGLCS_REG_DBG_SHIFT_K2_E5, PGLCS_REG_DBG_FORCE_VALID_K2_E5, 77621dd79e8STomer Tayar PGLCS_REG_DBG_FORCE_FRAME_K2_E5, 777c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV, 2 778c965db44STomer Tayar }; 779c965db44STomer Tayar 780c965db44STomer Tayar static struct block_defs block_ptu_defs = { 781be086e7cSMintz, Yuval "ptu", 782da090917STomer Tayar {true, true, true}, false, 0, 783da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 784c965db44STomer Tayar PTU_REG_DBG_SELECT, PTU_REG_DBG_DWORD_ENABLE, 785c965db44STomer Tayar PTU_REG_DBG_SHIFT, PTU_REG_DBG_FORCE_VALID, 786c965db44STomer Tayar PTU_REG_DBG_FORCE_FRAME, 787c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 20 788c965db44STomer Tayar }; 789c965db44STomer Tayar 790c965db44STomer Tayar static struct block_defs block_dmae_defs = { 791be086e7cSMintz, Yuval "dmae", 792da090917STomer Tayar {true, true, true}, false, 0, 793da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 794c965db44STomer Tayar DMAE_REG_DBG_SELECT, DMAE_REG_DBG_DWORD_ENABLE, 795c965db44STomer Tayar DMAE_REG_DBG_SHIFT, DMAE_REG_DBG_FORCE_VALID, 796c965db44STomer Tayar DMAE_REG_DBG_FORCE_FRAME, 797c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 28 798c965db44STomer Tayar }; 799c965db44STomer Tayar 800c965db44STomer Tayar static struct block_defs block_tcm_defs = { 801be086e7cSMintz, Yuval "tcm", 802da090917STomer Tayar {true, true, true}, true, DBG_TSTORM_ID, 803da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT}, 804c965db44STomer Tayar TCM_REG_DBG_SELECT, TCM_REG_DBG_DWORD_ENABLE, 805c965db44STomer Tayar TCM_REG_DBG_SHIFT, TCM_REG_DBG_FORCE_VALID, 806c965db44STomer Tayar TCM_REG_DBG_FORCE_FRAME, 807c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 5 808c965db44STomer Tayar }; 809c965db44STomer Tayar 810c965db44STomer Tayar static struct block_defs block_mcm_defs = { 811be086e7cSMintz, Yuval "mcm", 812da090917STomer Tayar {true, true, true}, true, DBG_MSTORM_ID, 813da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM}, 814c965db44STomer Tayar MCM_REG_DBG_SELECT, MCM_REG_DBG_DWORD_ENABLE, 815c965db44STomer Tayar MCM_REG_DBG_SHIFT, MCM_REG_DBG_FORCE_VALID, 816c965db44STomer Tayar MCM_REG_DBG_FORCE_FRAME, 817c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 3 818c965db44STomer Tayar }; 819c965db44STomer Tayar 820c965db44STomer Tayar static struct block_defs block_ucm_defs = { 821be086e7cSMintz, Yuval "ucm", 822da090917STomer Tayar {true, true, true}, true, DBG_USTORM_ID, 823da090917STomer Tayar {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU}, 824c965db44STomer Tayar UCM_REG_DBG_SELECT, UCM_REG_DBG_DWORD_ENABLE, 825c965db44STomer Tayar UCM_REG_DBG_SHIFT, UCM_REG_DBG_FORCE_VALID, 826c965db44STomer Tayar UCM_REG_DBG_FORCE_FRAME, 827c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 8 828c965db44STomer Tayar }; 829c965db44STomer Tayar 830c965db44STomer Tayar static struct block_defs block_xcm_defs = { 831be086e7cSMintz, Yuval "xcm", 832da090917STomer Tayar {true, true, true}, true, DBG_XSTORM_ID, 833da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX}, 834c965db44STomer Tayar XCM_REG_DBG_SELECT, XCM_REG_DBG_DWORD_ENABLE, 835c965db44STomer Tayar XCM_REG_DBG_SHIFT, XCM_REG_DBG_FORCE_VALID, 836c965db44STomer Tayar XCM_REG_DBG_FORCE_FRAME, 837c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 19 838c965db44STomer Tayar }; 839c965db44STomer Tayar 840c965db44STomer Tayar static struct block_defs block_ycm_defs = { 841be086e7cSMintz, Yuval "ycm", 842da090917STomer Tayar {true, true, true}, true, DBG_YSTORM_ID, 843da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY}, 844c965db44STomer Tayar YCM_REG_DBG_SELECT, YCM_REG_DBG_DWORD_ENABLE, 845c965db44STomer Tayar YCM_REG_DBG_SHIFT, YCM_REG_DBG_FORCE_VALID, 846c965db44STomer Tayar YCM_REG_DBG_FORCE_FRAME, 847c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 5 848c965db44STomer Tayar }; 849c965db44STomer Tayar 850c965db44STomer Tayar static struct block_defs block_pcm_defs = { 851be086e7cSMintz, Yuval "pcm", 852da090917STomer Tayar {true, true, true}, true, DBG_PSTORM_ID, 853da090917STomer Tayar {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS}, 854c965db44STomer Tayar PCM_REG_DBG_SELECT, PCM_REG_DBG_DWORD_ENABLE, 855c965db44STomer Tayar PCM_REG_DBG_SHIFT, PCM_REG_DBG_FORCE_VALID, 856c965db44STomer Tayar PCM_REG_DBG_FORCE_FRAME, 857c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 4 858c965db44STomer Tayar }; 859c965db44STomer Tayar 860c965db44STomer Tayar static struct block_defs block_qm_defs = { 861be086e7cSMintz, Yuval "qm", 862da090917STomer Tayar {true, true, true}, false, 0, 863da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCQ, DBG_BUS_CLIENT_RBCQ}, 864c965db44STomer Tayar QM_REG_DBG_SELECT, QM_REG_DBG_DWORD_ENABLE, 865c965db44STomer Tayar QM_REG_DBG_SHIFT, QM_REG_DBG_FORCE_VALID, 866c965db44STomer Tayar QM_REG_DBG_FORCE_FRAME, 867c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 16 868c965db44STomer Tayar }; 869c965db44STomer Tayar 870c965db44STomer Tayar static struct block_defs block_tm_defs = { 871be086e7cSMintz, Yuval "tm", 872da090917STomer Tayar {true, true, true}, false, 0, 873da090917STomer Tayar {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS}, 874c965db44STomer Tayar TM_REG_DBG_SELECT, TM_REG_DBG_DWORD_ENABLE, 875c965db44STomer Tayar TM_REG_DBG_SHIFT, TM_REG_DBG_FORCE_VALID, 876c965db44STomer Tayar TM_REG_DBG_FORCE_FRAME, 877c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 17 878c965db44STomer Tayar }; 879c965db44STomer Tayar 880c965db44STomer Tayar static struct block_defs block_dorq_defs = { 881be086e7cSMintz, Yuval "dorq", 882da090917STomer Tayar {true, true, true}, false, 0, 883da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY}, 884c965db44STomer Tayar DORQ_REG_DBG_SELECT, DORQ_REG_DBG_DWORD_ENABLE, 885c965db44STomer Tayar DORQ_REG_DBG_SHIFT, DORQ_REG_DBG_FORCE_VALID, 886c965db44STomer Tayar DORQ_REG_DBG_FORCE_FRAME, 887c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 18 888c965db44STomer Tayar }; 889c965db44STomer Tayar 890c965db44STomer Tayar static struct block_defs block_brb_defs = { 891be086e7cSMintz, Yuval "brb", 892da090917STomer Tayar {true, true, true}, false, 0, 893da090917STomer Tayar {DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR}, 894c965db44STomer Tayar BRB_REG_DBG_SELECT, BRB_REG_DBG_DWORD_ENABLE, 895c965db44STomer Tayar BRB_REG_DBG_SHIFT, BRB_REG_DBG_FORCE_VALID, 896c965db44STomer Tayar BRB_REG_DBG_FORCE_FRAME, 897c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 0 898c965db44STomer Tayar }; 899c965db44STomer Tayar 900c965db44STomer Tayar static struct block_defs block_src_defs = { 901be086e7cSMintz, Yuval "src", 902da090917STomer Tayar {true, true, true}, false, 0, 903da090917STomer Tayar {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF}, 904c965db44STomer Tayar SRC_REG_DBG_SELECT, SRC_REG_DBG_DWORD_ENABLE, 905c965db44STomer Tayar SRC_REG_DBG_SHIFT, SRC_REG_DBG_FORCE_VALID, 906c965db44STomer Tayar SRC_REG_DBG_FORCE_FRAME, 907c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 2 908c965db44STomer Tayar }; 909c965db44STomer Tayar 910c965db44STomer Tayar static struct block_defs block_prs_defs = { 911be086e7cSMintz, Yuval "prs", 912da090917STomer Tayar {true, true, true}, false, 0, 913da090917STomer Tayar {DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR}, 914c965db44STomer Tayar PRS_REG_DBG_SELECT, PRS_REG_DBG_DWORD_ENABLE, 915c965db44STomer Tayar PRS_REG_DBG_SHIFT, PRS_REG_DBG_FORCE_VALID, 916c965db44STomer Tayar PRS_REG_DBG_FORCE_FRAME, 917c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 1 918c965db44STomer Tayar }; 919c965db44STomer Tayar 920c965db44STomer Tayar static struct block_defs block_tsdm_defs = { 921be086e7cSMintz, Yuval "tsdm", 922da090917STomer Tayar {true, true, true}, true, DBG_TSTORM_ID, 923da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT}, 924c965db44STomer Tayar TSDM_REG_DBG_SELECT, TSDM_REG_DBG_DWORD_ENABLE, 925c965db44STomer Tayar TSDM_REG_DBG_SHIFT, TSDM_REG_DBG_FORCE_VALID, 926c965db44STomer Tayar TSDM_REG_DBG_FORCE_FRAME, 927c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 3 928c965db44STomer Tayar }; 929c965db44STomer Tayar 930c965db44STomer Tayar static struct block_defs block_msdm_defs = { 931be086e7cSMintz, Yuval "msdm", 932da090917STomer Tayar {true, true, true}, true, DBG_MSTORM_ID, 933da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM}, 934c965db44STomer Tayar MSDM_REG_DBG_SELECT, MSDM_REG_DBG_DWORD_ENABLE, 935c965db44STomer Tayar MSDM_REG_DBG_SHIFT, MSDM_REG_DBG_FORCE_VALID, 936c965db44STomer Tayar MSDM_REG_DBG_FORCE_FRAME, 937c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 6 938c965db44STomer Tayar }; 939c965db44STomer Tayar 940c965db44STomer Tayar static struct block_defs block_usdm_defs = { 941be086e7cSMintz, Yuval "usdm", 942da090917STomer Tayar {true, true, true}, true, DBG_USTORM_ID, 943da090917STomer Tayar {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU}, 944c965db44STomer Tayar USDM_REG_DBG_SELECT, USDM_REG_DBG_DWORD_ENABLE, 945c965db44STomer Tayar USDM_REG_DBG_SHIFT, USDM_REG_DBG_FORCE_VALID, 946c965db44STomer Tayar USDM_REG_DBG_FORCE_FRAME, 947c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 7 948c965db44STomer Tayar }; 949c965db44STomer Tayar 950c965db44STomer Tayar static struct block_defs block_xsdm_defs = { 951be086e7cSMintz, Yuval "xsdm", 952da090917STomer Tayar {true, true, true}, true, DBG_XSTORM_ID, 953da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX}, 954c965db44STomer Tayar XSDM_REG_DBG_SELECT, XSDM_REG_DBG_DWORD_ENABLE, 955c965db44STomer Tayar XSDM_REG_DBG_SHIFT, XSDM_REG_DBG_FORCE_VALID, 956c965db44STomer Tayar XSDM_REG_DBG_FORCE_FRAME, 957c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 20 958c965db44STomer Tayar }; 959c965db44STomer Tayar 960c965db44STomer Tayar static struct block_defs block_ysdm_defs = { 961be086e7cSMintz, Yuval "ysdm", 962da090917STomer Tayar {true, true, true}, true, DBG_YSTORM_ID, 963da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY}, 964c965db44STomer Tayar YSDM_REG_DBG_SELECT, YSDM_REG_DBG_DWORD_ENABLE, 965c965db44STomer Tayar YSDM_REG_DBG_SHIFT, YSDM_REG_DBG_FORCE_VALID, 966c965db44STomer Tayar YSDM_REG_DBG_FORCE_FRAME, 967c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 8 968c965db44STomer Tayar }; 969c965db44STomer Tayar 970c965db44STomer Tayar static struct block_defs block_psdm_defs = { 971be086e7cSMintz, Yuval "psdm", 972da090917STomer Tayar {true, true, true}, true, DBG_PSTORM_ID, 973da090917STomer Tayar {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS}, 974c965db44STomer Tayar PSDM_REG_DBG_SELECT, PSDM_REG_DBG_DWORD_ENABLE, 975c965db44STomer Tayar PSDM_REG_DBG_SHIFT, PSDM_REG_DBG_FORCE_VALID, 976c965db44STomer Tayar PSDM_REG_DBG_FORCE_FRAME, 977c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 7 978c965db44STomer Tayar }; 979c965db44STomer Tayar 980c965db44STomer Tayar static struct block_defs block_tsem_defs = { 981be086e7cSMintz, Yuval "tsem", 982da090917STomer Tayar {true, true, true}, true, DBG_TSTORM_ID, 983da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT}, 984c965db44STomer Tayar TSEM_REG_DBG_SELECT, TSEM_REG_DBG_DWORD_ENABLE, 985c965db44STomer Tayar TSEM_REG_DBG_SHIFT, TSEM_REG_DBG_FORCE_VALID, 986c965db44STomer Tayar TSEM_REG_DBG_FORCE_FRAME, 987c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 4 988c965db44STomer Tayar }; 989c965db44STomer Tayar 990c965db44STomer Tayar static struct block_defs block_msem_defs = { 991be086e7cSMintz, Yuval "msem", 992da090917STomer Tayar {true, true, true}, true, DBG_MSTORM_ID, 993da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM}, 994c965db44STomer Tayar MSEM_REG_DBG_SELECT, MSEM_REG_DBG_DWORD_ENABLE, 995c965db44STomer Tayar MSEM_REG_DBG_SHIFT, MSEM_REG_DBG_FORCE_VALID, 996c965db44STomer Tayar MSEM_REG_DBG_FORCE_FRAME, 997c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 9 998c965db44STomer Tayar }; 999c965db44STomer Tayar 1000c965db44STomer Tayar static struct block_defs block_usem_defs = { 1001be086e7cSMintz, Yuval "usem", 1002da090917STomer Tayar {true, true, true}, true, DBG_USTORM_ID, 1003da090917STomer Tayar {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU}, 1004c965db44STomer Tayar USEM_REG_DBG_SELECT, USEM_REG_DBG_DWORD_ENABLE, 1005c965db44STomer Tayar USEM_REG_DBG_SHIFT, USEM_REG_DBG_FORCE_VALID, 1006c965db44STomer Tayar USEM_REG_DBG_FORCE_FRAME, 1007c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 9 1008c965db44STomer Tayar }; 1009c965db44STomer Tayar 1010c965db44STomer Tayar static struct block_defs block_xsem_defs = { 1011be086e7cSMintz, Yuval "xsem", 1012da090917STomer Tayar {true, true, true}, true, DBG_XSTORM_ID, 1013da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX}, 1014c965db44STomer Tayar XSEM_REG_DBG_SELECT, XSEM_REG_DBG_DWORD_ENABLE, 1015c965db44STomer Tayar XSEM_REG_DBG_SHIFT, XSEM_REG_DBG_FORCE_VALID, 1016c965db44STomer Tayar XSEM_REG_DBG_FORCE_FRAME, 1017c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 21 1018c965db44STomer Tayar }; 1019c965db44STomer Tayar 1020c965db44STomer Tayar static struct block_defs block_ysem_defs = { 1021be086e7cSMintz, Yuval "ysem", 1022da090917STomer Tayar {true, true, true}, true, DBG_YSTORM_ID, 1023da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY}, 1024c965db44STomer Tayar YSEM_REG_DBG_SELECT, YSEM_REG_DBG_DWORD_ENABLE, 1025c965db44STomer Tayar YSEM_REG_DBG_SHIFT, YSEM_REG_DBG_FORCE_VALID, 1026c965db44STomer Tayar YSEM_REG_DBG_FORCE_FRAME, 1027c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 11 1028c965db44STomer Tayar }; 1029c965db44STomer Tayar 1030c965db44STomer Tayar static struct block_defs block_psem_defs = { 1031be086e7cSMintz, Yuval "psem", 1032da090917STomer Tayar {true, true, true}, true, DBG_PSTORM_ID, 1033da090917STomer Tayar {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS}, 1034c965db44STomer Tayar PSEM_REG_DBG_SELECT, PSEM_REG_DBG_DWORD_ENABLE, 1035c965db44STomer Tayar PSEM_REG_DBG_SHIFT, PSEM_REG_DBG_FORCE_VALID, 1036c965db44STomer Tayar PSEM_REG_DBG_FORCE_FRAME, 1037c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 10 1038c965db44STomer Tayar }; 1039c965db44STomer Tayar 1040c965db44STomer Tayar static struct block_defs block_rss_defs = { 1041be086e7cSMintz, Yuval "rss", 1042da090917STomer Tayar {true, true, true}, false, 0, 1043da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT}, 1044c965db44STomer Tayar RSS_REG_DBG_SELECT, RSS_REG_DBG_DWORD_ENABLE, 1045c965db44STomer Tayar RSS_REG_DBG_SHIFT, RSS_REG_DBG_FORCE_VALID, 1046c965db44STomer Tayar RSS_REG_DBG_FORCE_FRAME, 1047c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 18 1048c965db44STomer Tayar }; 1049c965db44STomer Tayar 1050c965db44STomer Tayar static struct block_defs block_tmld_defs = { 1051be086e7cSMintz, Yuval "tmld", 1052da090917STomer Tayar {true, true, true}, false, 0, 1053da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM}, 1054c965db44STomer Tayar TMLD_REG_DBG_SELECT, TMLD_REG_DBG_DWORD_ENABLE, 1055c965db44STomer Tayar TMLD_REG_DBG_SHIFT, TMLD_REG_DBG_FORCE_VALID, 1056c965db44STomer Tayar TMLD_REG_DBG_FORCE_FRAME, 1057c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 13 1058c965db44STomer Tayar }; 1059c965db44STomer Tayar 1060c965db44STomer Tayar static struct block_defs block_muld_defs = { 1061be086e7cSMintz, Yuval "muld", 1062da090917STomer Tayar {true, true, true}, false, 0, 1063da090917STomer Tayar {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU}, 1064c965db44STomer Tayar MULD_REG_DBG_SELECT, MULD_REG_DBG_DWORD_ENABLE, 1065c965db44STomer Tayar MULD_REG_DBG_SHIFT, MULD_REG_DBG_FORCE_VALID, 1066c965db44STomer Tayar MULD_REG_DBG_FORCE_FRAME, 1067c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 14 1068c965db44STomer Tayar }; 1069c965db44STomer Tayar 1070c965db44STomer Tayar static struct block_defs block_yuld_defs = { 1071be086e7cSMintz, Yuval "yuld", 1072da090917STomer Tayar {true, true, false}, false, 0, 1073da090917STomer Tayar {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, 1074da090917STomer Tayar MAX_DBG_BUS_CLIENTS}, 10757b6859fbSMintz, Yuval YULD_REG_DBG_SELECT_BB_K2, YULD_REG_DBG_DWORD_ENABLE_BB_K2, 10767b6859fbSMintz, Yuval YULD_REG_DBG_SHIFT_BB_K2, YULD_REG_DBG_FORCE_VALID_BB_K2, 10777b6859fbSMintz, Yuval YULD_REG_DBG_FORCE_FRAME_BB_K2, 10787b6859fbSMintz, Yuval true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 10797b6859fbSMintz, Yuval 15 1080c965db44STomer Tayar }; 1081c965db44STomer Tayar 1082c965db44STomer Tayar static struct block_defs block_xyld_defs = { 1083be086e7cSMintz, Yuval "xyld", 1084da090917STomer Tayar {true, true, true}, false, 0, 1085da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX}, 1086c965db44STomer Tayar XYLD_REG_DBG_SELECT, XYLD_REG_DBG_DWORD_ENABLE, 1087c965db44STomer Tayar XYLD_REG_DBG_SHIFT, XYLD_REG_DBG_FORCE_VALID, 1088c965db44STomer Tayar XYLD_REG_DBG_FORCE_FRAME, 1089c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 12 1090c965db44STomer Tayar }; 1091c965db44STomer Tayar 1092a2e7699eSTomer Tayar static struct block_defs block_ptld_defs = { 1093da090917STomer Tayar "ptld", 1094da090917STomer Tayar {false, false, true}, false, 0, 1095da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCT}, 1096da090917STomer Tayar PTLD_REG_DBG_SELECT_E5, PTLD_REG_DBG_DWORD_ENABLE_E5, 1097da090917STomer Tayar PTLD_REG_DBG_SHIFT_E5, PTLD_REG_DBG_FORCE_VALID_E5, 1098da090917STomer Tayar PTLD_REG_DBG_FORCE_FRAME_E5, 1099da090917STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 1100da090917STomer Tayar 28 1101a2e7699eSTomer Tayar }; 1102a2e7699eSTomer Tayar 1103a2e7699eSTomer Tayar static struct block_defs block_ypld_defs = { 1104da090917STomer Tayar "ypld", 1105da090917STomer Tayar {false, false, true}, false, 0, 1106da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCS}, 1107da090917STomer Tayar YPLD_REG_DBG_SELECT_E5, YPLD_REG_DBG_DWORD_ENABLE_E5, 1108da090917STomer Tayar YPLD_REG_DBG_SHIFT_E5, YPLD_REG_DBG_FORCE_VALID_E5, 1109da090917STomer Tayar YPLD_REG_DBG_FORCE_FRAME_E5, 1110da090917STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 1111da090917STomer Tayar 27 1112a2e7699eSTomer Tayar }; 1113a2e7699eSTomer Tayar 1114c965db44STomer Tayar static struct block_defs block_prm_defs = { 1115be086e7cSMintz, Yuval "prm", 1116da090917STomer Tayar {true, true, true}, false, 0, 1117da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM}, 1118c965db44STomer Tayar PRM_REG_DBG_SELECT, PRM_REG_DBG_DWORD_ENABLE, 1119c965db44STomer Tayar PRM_REG_DBG_SHIFT, PRM_REG_DBG_FORCE_VALID, 1120c965db44STomer Tayar PRM_REG_DBG_FORCE_FRAME, 1121c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 21 1122c965db44STomer Tayar }; 1123c965db44STomer Tayar 1124c965db44STomer Tayar static struct block_defs block_pbf_pb1_defs = { 1125be086e7cSMintz, Yuval "pbf_pb1", 1126da090917STomer Tayar {true, true, true}, false, 0, 1127da090917STomer Tayar {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV}, 1128c965db44STomer Tayar PBF_PB1_REG_DBG_SELECT, PBF_PB1_REG_DBG_DWORD_ENABLE, 1129c965db44STomer Tayar PBF_PB1_REG_DBG_SHIFT, PBF_PB1_REG_DBG_FORCE_VALID, 1130c965db44STomer Tayar PBF_PB1_REG_DBG_FORCE_FRAME, 1131c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 1132c965db44STomer Tayar 11 1133c965db44STomer Tayar }; 1134c965db44STomer Tayar 1135c965db44STomer Tayar static struct block_defs block_pbf_pb2_defs = { 1136be086e7cSMintz, Yuval "pbf_pb2", 1137da090917STomer Tayar {true, true, true}, false, 0, 1138da090917STomer Tayar {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV}, 1139c965db44STomer Tayar PBF_PB2_REG_DBG_SELECT, PBF_PB2_REG_DBG_DWORD_ENABLE, 1140c965db44STomer Tayar PBF_PB2_REG_DBG_SHIFT, PBF_PB2_REG_DBG_FORCE_VALID, 1141c965db44STomer Tayar PBF_PB2_REG_DBG_FORCE_FRAME, 1142c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 1143c965db44STomer Tayar 12 1144c965db44STomer Tayar }; 1145c965db44STomer Tayar 1146c965db44STomer Tayar static struct block_defs block_rpb_defs = { 1147be086e7cSMintz, Yuval "rpb", 1148da090917STomer Tayar {true, true, true}, false, 0, 1149da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM}, 1150c965db44STomer Tayar RPB_REG_DBG_SELECT, RPB_REG_DBG_DWORD_ENABLE, 1151c965db44STomer Tayar RPB_REG_DBG_SHIFT, RPB_REG_DBG_FORCE_VALID, 1152c965db44STomer Tayar RPB_REG_DBG_FORCE_FRAME, 1153c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 13 1154c965db44STomer Tayar }; 1155c965db44STomer Tayar 1156c965db44STomer Tayar static struct block_defs block_btb_defs = { 1157be086e7cSMintz, Yuval "btb", 1158da090917STomer Tayar {true, true, true}, false, 0, 1159da090917STomer Tayar {DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV}, 1160c965db44STomer Tayar BTB_REG_DBG_SELECT, BTB_REG_DBG_DWORD_ENABLE, 1161c965db44STomer Tayar BTB_REG_DBG_SHIFT, BTB_REG_DBG_FORCE_VALID, 1162c965db44STomer Tayar BTB_REG_DBG_FORCE_FRAME, 1163c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 10 1164c965db44STomer Tayar }; 1165c965db44STomer Tayar 1166c965db44STomer Tayar static struct block_defs block_pbf_defs = { 1167be086e7cSMintz, Yuval "pbf", 1168da090917STomer Tayar {true, true, true}, false, 0, 1169da090917STomer Tayar {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV}, 1170c965db44STomer Tayar PBF_REG_DBG_SELECT, PBF_REG_DBG_DWORD_ENABLE, 1171c965db44STomer Tayar PBF_REG_DBG_SHIFT, PBF_REG_DBG_FORCE_VALID, 1172c965db44STomer Tayar PBF_REG_DBG_FORCE_FRAME, 1173c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 15 1174c965db44STomer Tayar }; 1175c965db44STomer Tayar 1176c965db44STomer Tayar static struct block_defs block_rdif_defs = { 1177be086e7cSMintz, Yuval "rdif", 1178da090917STomer Tayar {true, true, true}, false, 0, 1179da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM}, 1180c965db44STomer Tayar RDIF_REG_DBG_SELECT, RDIF_REG_DBG_DWORD_ENABLE, 1181c965db44STomer Tayar RDIF_REG_DBG_SHIFT, RDIF_REG_DBG_FORCE_VALID, 1182c965db44STomer Tayar RDIF_REG_DBG_FORCE_FRAME, 1183c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 16 1184c965db44STomer Tayar }; 1185c965db44STomer Tayar 1186c965db44STomer Tayar static struct block_defs block_tdif_defs = { 1187be086e7cSMintz, Yuval "tdif", 1188da090917STomer Tayar {true, true, true}, false, 0, 1189da090917STomer Tayar {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS}, 1190c965db44STomer Tayar TDIF_REG_DBG_SELECT, TDIF_REG_DBG_DWORD_ENABLE, 1191c965db44STomer Tayar TDIF_REG_DBG_SHIFT, TDIF_REG_DBG_FORCE_VALID, 1192c965db44STomer Tayar TDIF_REG_DBG_FORCE_FRAME, 1193c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 17 1194c965db44STomer Tayar }; 1195c965db44STomer Tayar 1196c965db44STomer Tayar static struct block_defs block_cdu_defs = { 1197be086e7cSMintz, Yuval "cdu", 1198da090917STomer Tayar {true, true, true}, false, 0, 1199da090917STomer Tayar {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF}, 1200c965db44STomer Tayar CDU_REG_DBG_SELECT, CDU_REG_DBG_DWORD_ENABLE, 1201c965db44STomer Tayar CDU_REG_DBG_SHIFT, CDU_REG_DBG_FORCE_VALID, 1202c965db44STomer Tayar CDU_REG_DBG_FORCE_FRAME, 1203c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 23 1204c965db44STomer Tayar }; 1205c965db44STomer Tayar 1206c965db44STomer Tayar static struct block_defs block_ccfc_defs = { 1207be086e7cSMintz, Yuval "ccfc", 1208da090917STomer Tayar {true, true, true}, false, 0, 1209da090917STomer Tayar {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF}, 1210c965db44STomer Tayar CCFC_REG_DBG_SELECT, CCFC_REG_DBG_DWORD_ENABLE, 1211c965db44STomer Tayar CCFC_REG_DBG_SHIFT, CCFC_REG_DBG_FORCE_VALID, 1212c965db44STomer Tayar CCFC_REG_DBG_FORCE_FRAME, 1213c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 24 1214c965db44STomer Tayar }; 1215c965db44STomer Tayar 1216c965db44STomer Tayar static struct block_defs block_tcfc_defs = { 1217be086e7cSMintz, Yuval "tcfc", 1218da090917STomer Tayar {true, true, true}, false, 0, 1219da090917STomer Tayar {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF}, 1220c965db44STomer Tayar TCFC_REG_DBG_SELECT, TCFC_REG_DBG_DWORD_ENABLE, 1221c965db44STomer Tayar TCFC_REG_DBG_SHIFT, TCFC_REG_DBG_FORCE_VALID, 1222c965db44STomer Tayar TCFC_REG_DBG_FORCE_FRAME, 1223c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 25 1224c965db44STomer Tayar }; 1225c965db44STomer Tayar 1226c965db44STomer Tayar static struct block_defs block_igu_defs = { 1227be086e7cSMintz, Yuval "igu", 1228da090917STomer Tayar {true, true, true}, false, 0, 1229da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 1230c965db44STomer Tayar IGU_REG_DBG_SELECT, IGU_REG_DBG_DWORD_ENABLE, 1231c965db44STomer Tayar IGU_REG_DBG_SHIFT, IGU_REG_DBG_FORCE_VALID, 1232c965db44STomer Tayar IGU_REG_DBG_FORCE_FRAME, 1233c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 27 1234c965db44STomer Tayar }; 1235c965db44STomer Tayar 1236c965db44STomer Tayar static struct block_defs block_cau_defs = { 1237be086e7cSMintz, Yuval "cau", 1238da090917STomer Tayar {true, true, true}, false, 0, 1239da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 1240c965db44STomer Tayar CAU_REG_DBG_SELECT, CAU_REG_DBG_DWORD_ENABLE, 1241c965db44STomer Tayar CAU_REG_DBG_SHIFT, CAU_REG_DBG_FORCE_VALID, 1242c965db44STomer Tayar CAU_REG_DBG_FORCE_FRAME, 1243c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 19 1244c965db44STomer Tayar }; 1245c965db44STomer Tayar 1246a2e7699eSTomer Tayar static struct block_defs block_rgfs_defs = { 1247da090917STomer Tayar "rgfs", {false, false, true}, false, 0, 1248da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1249a2e7699eSTomer Tayar 0, 0, 0, 0, 0, 1250da090917STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 29 1251a2e7699eSTomer Tayar }; 1252a2e7699eSTomer Tayar 1253a2e7699eSTomer Tayar static struct block_defs block_rgsrc_defs = { 1254da090917STomer Tayar "rgsrc", 1255da090917STomer Tayar {false, false, true}, false, 0, 1256da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH}, 1257da090917STomer Tayar RGSRC_REG_DBG_SELECT_E5, RGSRC_REG_DBG_DWORD_ENABLE_E5, 1258da090917STomer Tayar RGSRC_REG_DBG_SHIFT_E5, RGSRC_REG_DBG_FORCE_VALID_E5, 1259da090917STomer Tayar RGSRC_REG_DBG_FORCE_FRAME_E5, 1260da090917STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 1261da090917STomer Tayar 30 1262a2e7699eSTomer Tayar }; 1263a2e7699eSTomer Tayar 1264a2e7699eSTomer Tayar static struct block_defs block_tgfs_defs = { 1265da090917STomer Tayar "tgfs", {false, false, true}, false, 0, 1266da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1267a2e7699eSTomer Tayar 0, 0, 0, 0, 0, 1268da090917STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 30 1269a2e7699eSTomer Tayar }; 1270a2e7699eSTomer Tayar 1271a2e7699eSTomer Tayar static struct block_defs block_tgsrc_defs = { 1272da090917STomer Tayar "tgsrc", 1273da090917STomer Tayar {false, false, true}, false, 0, 1274da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCV}, 1275da090917STomer Tayar TGSRC_REG_DBG_SELECT_E5, TGSRC_REG_DBG_DWORD_ENABLE_E5, 1276da090917STomer Tayar TGSRC_REG_DBG_SHIFT_E5, TGSRC_REG_DBG_FORCE_VALID_E5, 1277da090917STomer Tayar TGSRC_REG_DBG_FORCE_FRAME_E5, 1278da090917STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 1279da090917STomer Tayar 31 1280a2e7699eSTomer Tayar }; 1281a2e7699eSTomer Tayar 1282c965db44STomer Tayar static struct block_defs block_umac_defs = { 1283be086e7cSMintz, Yuval "umac", 1284da090917STomer Tayar {true, true, true}, false, 0, 1285da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ, 1286da090917STomer Tayar DBG_BUS_CLIENT_RBCZ}, 128721dd79e8STomer Tayar UMAC_REG_DBG_SELECT_K2_E5, UMAC_REG_DBG_DWORD_ENABLE_K2_E5, 128821dd79e8STomer Tayar UMAC_REG_DBG_SHIFT_K2_E5, UMAC_REG_DBG_FORCE_VALID_K2_E5, 128921dd79e8STomer Tayar UMAC_REG_DBG_FORCE_FRAME_K2_E5, 1290c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV, 6 1291c965db44STomer Tayar }; 1292c965db44STomer Tayar 1293c965db44STomer Tayar static struct block_defs block_xmac_defs = { 1294da090917STomer Tayar "xmac", {true, false, false}, false, 0, 1295da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1296c965db44STomer Tayar 0, 0, 0, 0, 0, 1297c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 1298c965db44STomer Tayar }; 1299c965db44STomer Tayar 1300c965db44STomer Tayar static struct block_defs block_dbg_defs = { 1301da090917STomer Tayar "dbg", {true, true, true}, false, 0, 1302da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1303c965db44STomer Tayar 0, 0, 0, 0, 0, 1304c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 3 1305c965db44STomer Tayar }; 1306c965db44STomer Tayar 1307c965db44STomer Tayar static struct block_defs block_nig_defs = { 1308be086e7cSMintz, Yuval "nig", 1309da090917STomer Tayar {true, true, true}, false, 0, 1310da090917STomer Tayar {DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN}, 1311c965db44STomer Tayar NIG_REG_DBG_SELECT, NIG_REG_DBG_DWORD_ENABLE, 1312c965db44STomer Tayar NIG_REG_DBG_SHIFT, NIG_REG_DBG_FORCE_VALID, 1313c965db44STomer Tayar NIG_REG_DBG_FORCE_FRAME, 1314c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 0 1315c965db44STomer Tayar }; 1316c965db44STomer Tayar 1317c965db44STomer Tayar static struct block_defs block_wol_defs = { 1318be086e7cSMintz, Yuval "wol", 1319da090917STomer Tayar {false, true, true}, false, 0, 1320da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ}, 132121dd79e8STomer Tayar WOL_REG_DBG_SELECT_K2_E5, WOL_REG_DBG_DWORD_ENABLE_K2_E5, 132221dd79e8STomer Tayar WOL_REG_DBG_SHIFT_K2_E5, WOL_REG_DBG_FORCE_VALID_K2_E5, 132321dd79e8STomer Tayar WOL_REG_DBG_FORCE_FRAME_K2_E5, 1324c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 7 1325c965db44STomer Tayar }; 1326c965db44STomer Tayar 1327c965db44STomer Tayar static struct block_defs block_bmbn_defs = { 1328be086e7cSMintz, Yuval "bmbn", 1329da090917STomer Tayar {false, true, true}, false, 0, 1330da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCB, 1331da090917STomer Tayar DBG_BUS_CLIENT_RBCB}, 133221dd79e8STomer Tayar BMBN_REG_DBG_SELECT_K2_E5, BMBN_REG_DBG_DWORD_ENABLE_K2_E5, 133321dd79e8STomer Tayar BMBN_REG_DBG_SHIFT_K2_E5, BMBN_REG_DBG_FORCE_VALID_K2_E5, 133421dd79e8STomer Tayar BMBN_REG_DBG_FORCE_FRAME_K2_E5, 1335c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 1336c965db44STomer Tayar }; 1337c965db44STomer Tayar 1338c965db44STomer Tayar static struct block_defs block_ipc_defs = { 1339da090917STomer Tayar "ipc", {true, true, true}, false, 0, 1340da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1341c965db44STomer Tayar 0, 0, 0, 0, 0, 1342c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_UA, 8 1343c965db44STomer Tayar }; 1344c965db44STomer Tayar 1345c965db44STomer Tayar static struct block_defs block_nwm_defs = { 1346be086e7cSMintz, Yuval "nwm", 1347da090917STomer Tayar {false, true, true}, false, 0, 1348da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW, DBG_BUS_CLIENT_RBCW}, 134921dd79e8STomer Tayar NWM_REG_DBG_SELECT_K2_E5, NWM_REG_DBG_DWORD_ENABLE_K2_E5, 135021dd79e8STomer Tayar NWM_REG_DBG_SHIFT_K2_E5, NWM_REG_DBG_FORCE_VALID_K2_E5, 135121dd79e8STomer Tayar NWM_REG_DBG_FORCE_FRAME_K2_E5, 1352c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV_2, 0 1353c965db44STomer Tayar }; 1354c965db44STomer Tayar 1355c965db44STomer Tayar static struct block_defs block_nws_defs = { 1356be086e7cSMintz, Yuval "nws", 1357da090917STomer Tayar {false, true, true}, false, 0, 1358da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW, DBG_BUS_CLIENT_RBCW}, 135921dd79e8STomer Tayar NWS_REG_DBG_SELECT_K2_E5, NWS_REG_DBG_DWORD_ENABLE_K2_E5, 136021dd79e8STomer Tayar NWS_REG_DBG_SHIFT_K2_E5, NWS_REG_DBG_FORCE_VALID_K2_E5, 136121dd79e8STomer Tayar NWS_REG_DBG_FORCE_FRAME_K2_E5, 1362c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV, 12 1363c965db44STomer Tayar }; 1364c965db44STomer Tayar 1365c965db44STomer Tayar static struct block_defs block_ms_defs = { 1366be086e7cSMintz, Yuval "ms", 1367da090917STomer Tayar {false, true, true}, false, 0, 1368da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ}, 136921dd79e8STomer Tayar MS_REG_DBG_SELECT_K2_E5, MS_REG_DBG_DWORD_ENABLE_K2_E5, 137021dd79e8STomer Tayar MS_REG_DBG_SHIFT_K2_E5, MS_REG_DBG_FORCE_VALID_K2_E5, 137121dd79e8STomer Tayar MS_REG_DBG_FORCE_FRAME_K2_E5, 1372c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV, 13 1373c965db44STomer Tayar }; 1374c965db44STomer Tayar 1375c965db44STomer Tayar static struct block_defs block_phy_pcie_defs = { 1376be086e7cSMintz, Yuval "phy_pcie", 1377da090917STomer Tayar {false, true, true}, false, 0, 1378da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH, 1379da090917STomer Tayar DBG_BUS_CLIENT_RBCH}, 138021dd79e8STomer Tayar PCIE_REG_DBG_COMMON_SELECT_K2_E5, 138121dd79e8STomer Tayar PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5, 138221dd79e8STomer Tayar PCIE_REG_DBG_COMMON_SHIFT_K2_E5, 138321dd79e8STomer Tayar PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5, 138421dd79e8STomer Tayar PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5, 1385c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 1386c965db44STomer Tayar }; 1387c965db44STomer Tayar 1388c965db44STomer Tayar static struct block_defs block_led_defs = { 1389da090917STomer Tayar "led", {false, true, true}, false, 0, 1390da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1391c965db44STomer Tayar 0, 0, 0, 0, 0, 1392be086e7cSMintz, Yuval true, false, DBG_RESET_REG_MISCS_PL_HV, 14 1393be086e7cSMintz, Yuval }; 1394be086e7cSMintz, Yuval 1395be086e7cSMintz, Yuval static struct block_defs block_avs_wrap_defs = { 1396da090917STomer Tayar "avs_wrap", {false, true, false}, false, 0, 1397da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1398be086e7cSMintz, Yuval 0, 0, 0, 0, 0, 1399be086e7cSMintz, Yuval true, false, DBG_RESET_REG_MISCS_PL_UA, 11 1400be086e7cSMintz, Yuval }; 1401be086e7cSMintz, Yuval 1402da090917STomer Tayar static struct block_defs block_pxpreqbus_defs = { 1403da090917STomer Tayar "pxpreqbus", {false, false, false}, false, 0, 1404da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1405da090917STomer Tayar 0, 0, 0, 0, 0, 1406da090917STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 1407da090917STomer Tayar }; 1408da090917STomer Tayar 1409c965db44STomer Tayar static struct block_defs block_misc_aeu_defs = { 1410da090917STomer Tayar "misc_aeu", {true, true, true}, false, 0, 1411da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1412c965db44STomer Tayar 0, 0, 0, 0, 0, 1413c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 1414c965db44STomer Tayar }; 1415c965db44STomer Tayar 1416c965db44STomer Tayar static struct block_defs block_bar0_map_defs = { 1417da090917STomer Tayar "bar0_map", {true, true, true}, false, 0, 1418da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1419c965db44STomer Tayar 0, 0, 0, 0, 0, 1420c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 1421c965db44STomer Tayar }; 1422c965db44STomer Tayar 1423c965db44STomer Tayar static struct block_defs *s_block_defs[MAX_BLOCK_ID] = { 1424c965db44STomer Tayar &block_grc_defs, 1425c965db44STomer Tayar &block_miscs_defs, 1426c965db44STomer Tayar &block_misc_defs, 1427c965db44STomer Tayar &block_dbu_defs, 1428c965db44STomer Tayar &block_pglue_b_defs, 1429c965db44STomer Tayar &block_cnig_defs, 1430c965db44STomer Tayar &block_cpmu_defs, 1431c965db44STomer Tayar &block_ncsi_defs, 1432c965db44STomer Tayar &block_opte_defs, 1433c965db44STomer Tayar &block_bmb_defs, 1434c965db44STomer Tayar &block_pcie_defs, 1435c965db44STomer Tayar &block_mcp_defs, 1436c965db44STomer Tayar &block_mcp2_defs, 1437c965db44STomer Tayar &block_pswhst_defs, 1438c965db44STomer Tayar &block_pswhst2_defs, 1439c965db44STomer Tayar &block_pswrd_defs, 1440c965db44STomer Tayar &block_pswrd2_defs, 1441c965db44STomer Tayar &block_pswwr_defs, 1442c965db44STomer Tayar &block_pswwr2_defs, 1443c965db44STomer Tayar &block_pswrq_defs, 1444c965db44STomer Tayar &block_pswrq2_defs, 1445c965db44STomer Tayar &block_pglcs_defs, 1446c965db44STomer Tayar &block_dmae_defs, 1447c965db44STomer Tayar &block_ptu_defs, 1448c965db44STomer Tayar &block_tcm_defs, 1449c965db44STomer Tayar &block_mcm_defs, 1450c965db44STomer Tayar &block_ucm_defs, 1451c965db44STomer Tayar &block_xcm_defs, 1452c965db44STomer Tayar &block_ycm_defs, 1453c965db44STomer Tayar &block_pcm_defs, 1454c965db44STomer Tayar &block_qm_defs, 1455c965db44STomer Tayar &block_tm_defs, 1456c965db44STomer Tayar &block_dorq_defs, 1457c965db44STomer Tayar &block_brb_defs, 1458c965db44STomer Tayar &block_src_defs, 1459c965db44STomer Tayar &block_prs_defs, 1460c965db44STomer Tayar &block_tsdm_defs, 1461c965db44STomer Tayar &block_msdm_defs, 1462c965db44STomer Tayar &block_usdm_defs, 1463c965db44STomer Tayar &block_xsdm_defs, 1464c965db44STomer Tayar &block_ysdm_defs, 1465c965db44STomer Tayar &block_psdm_defs, 1466c965db44STomer Tayar &block_tsem_defs, 1467c965db44STomer Tayar &block_msem_defs, 1468c965db44STomer Tayar &block_usem_defs, 1469c965db44STomer Tayar &block_xsem_defs, 1470c965db44STomer Tayar &block_ysem_defs, 1471c965db44STomer Tayar &block_psem_defs, 1472c965db44STomer Tayar &block_rss_defs, 1473c965db44STomer Tayar &block_tmld_defs, 1474c965db44STomer Tayar &block_muld_defs, 1475c965db44STomer Tayar &block_yuld_defs, 1476c965db44STomer Tayar &block_xyld_defs, 14777b6859fbSMintz, Yuval &block_ptld_defs, 14787b6859fbSMintz, Yuval &block_ypld_defs, 1479c965db44STomer Tayar &block_prm_defs, 1480c965db44STomer Tayar &block_pbf_pb1_defs, 1481c965db44STomer Tayar &block_pbf_pb2_defs, 1482c965db44STomer Tayar &block_rpb_defs, 1483c965db44STomer Tayar &block_btb_defs, 1484c965db44STomer Tayar &block_pbf_defs, 1485c965db44STomer Tayar &block_rdif_defs, 1486c965db44STomer Tayar &block_tdif_defs, 1487c965db44STomer Tayar &block_cdu_defs, 1488c965db44STomer Tayar &block_ccfc_defs, 1489c965db44STomer Tayar &block_tcfc_defs, 1490c965db44STomer Tayar &block_igu_defs, 1491c965db44STomer Tayar &block_cau_defs, 14927b6859fbSMintz, Yuval &block_rgfs_defs, 14937b6859fbSMintz, Yuval &block_rgsrc_defs, 14947b6859fbSMintz, Yuval &block_tgfs_defs, 14957b6859fbSMintz, Yuval &block_tgsrc_defs, 1496c965db44STomer Tayar &block_umac_defs, 1497c965db44STomer Tayar &block_xmac_defs, 1498c965db44STomer Tayar &block_dbg_defs, 1499c965db44STomer Tayar &block_nig_defs, 1500c965db44STomer Tayar &block_wol_defs, 1501c965db44STomer Tayar &block_bmbn_defs, 1502c965db44STomer Tayar &block_ipc_defs, 1503c965db44STomer Tayar &block_nwm_defs, 1504c965db44STomer Tayar &block_nws_defs, 1505c965db44STomer Tayar &block_ms_defs, 1506c965db44STomer Tayar &block_phy_pcie_defs, 1507c965db44STomer Tayar &block_led_defs, 1508be086e7cSMintz, Yuval &block_avs_wrap_defs, 1509da090917STomer Tayar &block_pxpreqbus_defs, 1510c965db44STomer Tayar &block_misc_aeu_defs, 1511c965db44STomer Tayar &block_bar0_map_defs, 1512c965db44STomer Tayar }; 1513c965db44STomer Tayar 1514c965db44STomer Tayar static struct platform_defs s_platform_defs[] = { 1515da090917STomer Tayar {"asic", 1, 256, 32768}, 1516da090917STomer Tayar {"reserved", 0, 0, 0}, 1517da090917STomer Tayar {"reserved2", 0, 0, 0}, 1518da090917STomer Tayar {"reserved3", 0, 0, 0} 1519c965db44STomer Tayar }; 1520c965db44STomer Tayar 1521c965db44STomer Tayar static struct grc_param_defs s_grc_param_defs[] = { 15227b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_TSTORM */ 1523da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 1, 1}, 15247b6859fbSMintz, Yuval 15257b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_MSTORM */ 1526da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 1, 1}, 15277b6859fbSMintz, Yuval 15287b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_USTORM */ 1529da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 1, 1}, 15307b6859fbSMintz, Yuval 15317b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_XSTORM */ 1532da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 1, 1}, 15337b6859fbSMintz, Yuval 15347b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_YSTORM */ 1535da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 1, 1}, 15367b6859fbSMintz, Yuval 15377b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_PSTORM */ 1538da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 1, 1}, 15397b6859fbSMintz, Yuval 15407b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_REGS */ 1541da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 0, 1}, 15427b6859fbSMintz, Yuval 15437b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_RAM */ 1544da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 0, 1}, 15457b6859fbSMintz, Yuval 15467b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_PBUF */ 1547da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 0, 1}, 15487b6859fbSMintz, Yuval 15497b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_IOR */ 1550da090917STomer Tayar {{0, 0, 0}, 0, 1, false, 0, 1}, 15517b6859fbSMintz, Yuval 15527b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_VFC */ 1553da090917STomer Tayar {{0, 0, 0}, 0, 1, false, 0, 1}, 15547b6859fbSMintz, Yuval 15557b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_CM_CTX */ 1556da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 0, 1}, 15577b6859fbSMintz, Yuval 15587b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_ILT */ 1559da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 0, 1}, 15607b6859fbSMintz, Yuval 15617b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_RSS */ 1562da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 0, 1}, 15637b6859fbSMintz, Yuval 15647b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_CAU */ 1565da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 0, 1}, 15667b6859fbSMintz, Yuval 15677b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_QM */ 1568da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 0, 1}, 15697b6859fbSMintz, Yuval 15707b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_MCP */ 1571da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 0, 1}, 15727b6859fbSMintz, Yuval 15737b6859fbSMintz, Yuval /* DBG_GRC_PARAM_RESERVED */ 1574da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 0, 1}, 15757b6859fbSMintz, Yuval 15767b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_CFC */ 1577da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 0, 1}, 15787b6859fbSMintz, Yuval 15797b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_IGU */ 1580da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 0, 1}, 15817b6859fbSMintz, Yuval 15827b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_BRB */ 1583da090917STomer Tayar {{0, 0, 0}, 0, 1, false, 0, 1}, 15847b6859fbSMintz, Yuval 15857b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_BTB */ 1586da090917STomer Tayar {{0, 0, 0}, 0, 1, false, 0, 1}, 15877b6859fbSMintz, Yuval 15887b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_BMB */ 1589da090917STomer Tayar {{0, 0, 0}, 0, 1, false, 0, 1}, 15907b6859fbSMintz, Yuval 15917b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_NIG */ 1592da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 0, 1}, 15937b6859fbSMintz, Yuval 15947b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_MULD */ 1595da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 0, 1}, 15967b6859fbSMintz, Yuval 15977b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_PRS */ 1598da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 0, 1}, 15997b6859fbSMintz, Yuval 16007b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_DMAE */ 1601da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 0, 1}, 16027b6859fbSMintz, Yuval 16037b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_TM */ 1604da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 0, 1}, 16057b6859fbSMintz, Yuval 16067b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_SDM */ 1607da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 0, 1}, 16087b6859fbSMintz, Yuval 16097b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_DIF */ 1610da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 0, 1}, 16117b6859fbSMintz, Yuval 16127b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_STATIC */ 1613da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 0, 1}, 16147b6859fbSMintz, Yuval 16157b6859fbSMintz, Yuval /* DBG_GRC_PARAM_UNSTALL */ 1616da090917STomer Tayar {{0, 0, 0}, 0, 1, false, 0, 0}, 16177b6859fbSMintz, Yuval 16187b6859fbSMintz, Yuval /* DBG_GRC_PARAM_NUM_LCIDS */ 1619da090917STomer Tayar {{MAX_LCIDS, MAX_LCIDS, MAX_LCIDS}, 1, MAX_LCIDS, false, MAX_LCIDS, 16207b6859fbSMintz, Yuval MAX_LCIDS}, 16217b6859fbSMintz, Yuval 16227b6859fbSMintz, Yuval /* DBG_GRC_PARAM_NUM_LTIDS */ 1623da090917STomer Tayar {{MAX_LTIDS, MAX_LTIDS, MAX_LTIDS}, 1, MAX_LTIDS, false, MAX_LTIDS, 16247b6859fbSMintz, Yuval MAX_LTIDS}, 16257b6859fbSMintz, Yuval 16267b6859fbSMintz, Yuval /* DBG_GRC_PARAM_EXCLUDE_ALL */ 1627da090917STomer Tayar {{0, 0, 0}, 0, 1, true, 0, 0}, 16287b6859fbSMintz, Yuval 16297b6859fbSMintz, Yuval /* DBG_GRC_PARAM_CRASH */ 1630da090917STomer Tayar {{0, 0, 0}, 0, 1, true, 0, 0}, 16317b6859fbSMintz, Yuval 16327b6859fbSMintz, Yuval /* DBG_GRC_PARAM_PARITY_SAFE */ 1633da090917STomer Tayar {{0, 0, 0}, 0, 1, false, 1, 0}, 16347b6859fbSMintz, Yuval 16357b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_CM */ 1636da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 0, 1}, 16377b6859fbSMintz, Yuval 16387b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_PHY */ 1639da090917STomer Tayar {{1, 1, 1}, 0, 1, false, 0, 1}, 16407b6859fbSMintz, Yuval 16417b6859fbSMintz, Yuval /* DBG_GRC_PARAM_NO_MCP */ 1642da090917STomer Tayar {{0, 0, 0}, 0, 1, false, 0, 0}, 16437b6859fbSMintz, Yuval 16447b6859fbSMintz, Yuval /* DBG_GRC_PARAM_NO_FW_VER */ 1645da090917STomer Tayar {{0, 0, 0}, 0, 1, false, 0, 0} 1646c965db44STomer Tayar }; 1647c965db44STomer Tayar 1648c965db44STomer Tayar static struct rss_mem_defs s_rss_mem_defs[] = { 1649da090917STomer Tayar { "rss_mem_cid", "rss_cid", 0, 32, 1650da090917STomer Tayar {256, 320, 512} }, 16517b6859fbSMintz, Yuval 1652da090917STomer Tayar { "rss_mem_key_msb", "rss_key", 1024, 256, 1653da090917STomer Tayar {128, 208, 257} }, 16547b6859fbSMintz, Yuval 1655da090917STomer Tayar { "rss_mem_key_lsb", "rss_key", 2048, 64, 1656da090917STomer Tayar {128, 208, 257} }, 16577b6859fbSMintz, Yuval 1658da090917STomer Tayar { "rss_mem_info", "rss_info", 3072, 16, 1659da090917STomer Tayar {128, 208, 256} }, 16607b6859fbSMintz, Yuval 1661da090917STomer Tayar { "rss_mem_ind", "rss_ind", 4096, 16, 1662da090917STomer Tayar {16384, 26624, 32768} } 1663c965db44STomer Tayar }; 1664c965db44STomer Tayar 1665c965db44STomer Tayar static struct vfc_ram_defs s_vfc_ram_defs[] = { 1666c965db44STomer Tayar {"vfc_ram_tt1", "vfc_ram", 0, 512}, 1667c965db44STomer Tayar {"vfc_ram_mtt2", "vfc_ram", 512, 128}, 1668c965db44STomer Tayar {"vfc_ram_stt2", "vfc_ram", 640, 32}, 1669c965db44STomer Tayar {"vfc_ram_ro_vect", "vfc_ram", 672, 32} 1670c965db44STomer Tayar }; 1671c965db44STomer Tayar 1672c965db44STomer Tayar static struct big_ram_defs s_big_ram_defs[] = { 1673c965db44STomer Tayar { "BRB", MEM_GROUP_BRB_MEM, MEM_GROUP_BRB_RAM, DBG_GRC_PARAM_DUMP_BRB, 1674c965db44STomer Tayar BRB_REG_BIG_RAM_ADDRESS, BRB_REG_BIG_RAM_DATA, 1675da090917STomer Tayar MISC_REG_BLOCK_256B_EN, {0, 0, 0}, 1676da090917STomer Tayar {153600, 180224, 282624} }, 16777b6859fbSMintz, Yuval 1678c965db44STomer Tayar { "BTB", MEM_GROUP_BTB_MEM, MEM_GROUP_BTB_RAM, DBG_GRC_PARAM_DUMP_BTB, 1679c965db44STomer Tayar BTB_REG_BIG_RAM_ADDRESS, BTB_REG_BIG_RAM_DATA, 1680da090917STomer Tayar MISC_REG_BLOCK_256B_EN, {0, 1, 1}, 1681da090917STomer Tayar {92160, 117760, 168960} }, 16827b6859fbSMintz, Yuval 1683c965db44STomer Tayar { "BMB", MEM_GROUP_BMB_MEM, MEM_GROUP_BMB_RAM, DBG_GRC_PARAM_DUMP_BMB, 1684c965db44STomer Tayar BMB_REG_BIG_RAM_ADDRESS, BMB_REG_BIG_RAM_DATA, 1685da090917STomer Tayar MISCS_REG_BLOCK_256B_EN, {0, 0, 0}, 1686da090917STomer Tayar {36864, 36864, 36864} } 1687c965db44STomer Tayar }; 1688c965db44STomer Tayar 1689c965db44STomer Tayar static struct reset_reg_defs s_reset_regs_defs[] = { 16907b6859fbSMintz, Yuval /* DBG_RESET_REG_MISCS_PL_UA */ 1691da090917STomer Tayar { MISCS_REG_RESET_PL_UA, 1692da090917STomer Tayar {true, true, true}, {0x0, 0x0, 0x0} }, 16937b6859fbSMintz, Yuval 16947b6859fbSMintz, Yuval /* DBG_RESET_REG_MISCS_PL_HV */ 1695da090917STomer Tayar { MISCS_REG_RESET_PL_HV, 1696da090917STomer Tayar {true, true, true}, {0x0, 0x400, 0x600} }, 16977b6859fbSMintz, Yuval 16987b6859fbSMintz, Yuval /* DBG_RESET_REG_MISCS_PL_HV_2 */ 1699da090917STomer Tayar { MISCS_REG_RESET_PL_HV_2_K2_E5, 1700da090917STomer Tayar {false, true, true}, {0x0, 0x0, 0x0} }, 17017b6859fbSMintz, Yuval 17027b6859fbSMintz, Yuval /* DBG_RESET_REG_MISC_PL_UA */ 1703da090917STomer Tayar { MISC_REG_RESET_PL_UA, 1704da090917STomer Tayar {true, true, true}, {0x0, 0x0, 0x0} }, 17057b6859fbSMintz, Yuval 17067b6859fbSMintz, Yuval /* DBG_RESET_REG_MISC_PL_HV */ 1707da090917STomer Tayar { MISC_REG_RESET_PL_HV, 1708da090917STomer Tayar {true, true, true}, {0x0, 0x0, 0x0} }, 17097b6859fbSMintz, Yuval 17107b6859fbSMintz, Yuval /* DBG_RESET_REG_MISC_PL_PDA_VMAIN_1 */ 1711da090917STomer Tayar { MISC_REG_RESET_PL_PDA_VMAIN_1, 1712da090917STomer Tayar {true, true, true}, {0x4404040, 0x4404040, 0x404040} }, 17137b6859fbSMintz, Yuval 17147b6859fbSMintz, Yuval /* DBG_RESET_REG_MISC_PL_PDA_VMAIN_2 */ 1715da090917STomer Tayar { MISC_REG_RESET_PL_PDA_VMAIN_2, 1716da090917STomer Tayar {true, true, true}, {0x7, 0x7c00007, 0x5c08007} }, 17177b6859fbSMintz, Yuval 17187b6859fbSMintz, Yuval /* DBG_RESET_REG_MISC_PL_PDA_VAUX */ 1719da090917STomer Tayar { MISC_REG_RESET_PL_PDA_VAUX, 1720da090917STomer Tayar {true, true, true}, {0x2, 0x2, 0x2} }, 1721c965db44STomer Tayar }; 1722c965db44STomer Tayar 1723c965db44STomer Tayar static struct phy_defs s_phy_defs[] = { 17247b6859fbSMintz, Yuval {"nw_phy", NWS_REG_NWS_CMU_K2, 172521dd79e8STomer Tayar PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2_E5, 172621dd79e8STomer Tayar PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2_E5, 172721dd79e8STomer Tayar PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2_E5, 172821dd79e8STomer Tayar PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2_E5}, 172921dd79e8STomer Tayar {"sgmii_phy", MS_REG_MS_CMU_K2_E5, 173021dd79e8STomer Tayar PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2_E5, 173121dd79e8STomer Tayar PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2_E5, 173221dd79e8STomer Tayar PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2_E5, 173321dd79e8STomer Tayar PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2_E5}, 173421dd79e8STomer Tayar {"pcie_phy0", PHY_PCIE_REG_PHY0_K2_E5, 173521dd79e8STomer Tayar PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5, 173621dd79e8STomer Tayar PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5, 173721dd79e8STomer Tayar PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5, 173821dd79e8STomer Tayar PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5}, 173921dd79e8STomer Tayar {"pcie_phy1", PHY_PCIE_REG_PHY1_K2_E5, 174021dd79e8STomer Tayar PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5, 174121dd79e8STomer Tayar PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5, 174221dd79e8STomer Tayar PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5, 174321dd79e8STomer Tayar PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5}, 1744c965db44STomer Tayar }; 1745c965db44STomer Tayar 1746c965db44STomer Tayar /**************************** Private Functions ******************************/ 1747c965db44STomer Tayar 1748c965db44STomer Tayar /* Reads and returns a single dword from the specified unaligned buffer */ 1749c965db44STomer Tayar static u32 qed_read_unaligned_dword(u8 *buf) 1750c965db44STomer Tayar { 1751c965db44STomer Tayar u32 dword; 1752c965db44STomer Tayar 1753c965db44STomer Tayar memcpy((u8 *)&dword, buf, sizeof(dword)); 1754c965db44STomer Tayar return dword; 1755c965db44STomer Tayar } 1756c965db44STomer Tayar 1757be086e7cSMintz, Yuval /* Returns the value of the specified GRC param */ 1758be086e7cSMintz, Yuval static u32 qed_grc_get_param(struct qed_hwfn *p_hwfn, 1759be086e7cSMintz, Yuval enum dbg_grc_params grc_param) 1760be086e7cSMintz, Yuval { 1761be086e7cSMintz, Yuval struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 1762be086e7cSMintz, Yuval 1763be086e7cSMintz, Yuval return dev_data->grc.param_val[grc_param]; 1764be086e7cSMintz, Yuval } 1765be086e7cSMintz, Yuval 1766be086e7cSMintz, Yuval /* Initializes the GRC parameters */ 1767be086e7cSMintz, Yuval static void qed_dbg_grc_init_params(struct qed_hwfn *p_hwfn) 1768be086e7cSMintz, Yuval { 1769be086e7cSMintz, Yuval struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 1770be086e7cSMintz, Yuval 1771be086e7cSMintz, Yuval if (!dev_data->grc.params_initialized) { 1772be086e7cSMintz, Yuval qed_dbg_grc_set_params_default(p_hwfn); 1773be086e7cSMintz, Yuval dev_data->grc.params_initialized = 1; 1774be086e7cSMintz, Yuval } 1775be086e7cSMintz, Yuval } 1776be086e7cSMintz, Yuval 1777c965db44STomer Tayar /* Initializes debug data for the specified device */ 1778c965db44STomer Tayar static enum dbg_status qed_dbg_dev_init(struct qed_hwfn *p_hwfn, 1779c965db44STomer Tayar struct qed_ptt *p_ptt) 1780c965db44STomer Tayar { 1781c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 1782c965db44STomer Tayar 1783c965db44STomer Tayar if (dev_data->initialized) 1784c965db44STomer Tayar return DBG_STATUS_OK; 1785c965db44STomer Tayar 1786c965db44STomer Tayar if (QED_IS_K2(p_hwfn->cdev)) { 1787c965db44STomer Tayar dev_data->chip_id = CHIP_K2; 1788c965db44STomer Tayar dev_data->mode_enable[MODE_K2] = 1; 1789c965db44STomer Tayar } else if (QED_IS_BB_B0(p_hwfn->cdev)) { 17907b6859fbSMintz, Yuval dev_data->chip_id = CHIP_BB; 17919c79ddaaSMintz, Yuval dev_data->mode_enable[MODE_BB] = 1; 1792c965db44STomer Tayar } else { 1793c965db44STomer Tayar return DBG_STATUS_UNKNOWN_CHIP; 1794c965db44STomer Tayar } 1795c965db44STomer Tayar 1796c965db44STomer Tayar dev_data->platform_id = PLATFORM_ASIC; 1797c965db44STomer Tayar dev_data->mode_enable[MODE_ASIC] = 1; 1798be086e7cSMintz, Yuval 1799be086e7cSMintz, Yuval /* Initializes the GRC parameters */ 1800be086e7cSMintz, Yuval qed_dbg_grc_init_params(p_hwfn); 1801be086e7cSMintz, Yuval 1802da090917STomer Tayar dev_data->use_dmae = true; 1803da090917STomer Tayar dev_data->num_regs_read = 0; 1804da090917STomer Tayar dev_data->initialized = 1; 18057b6859fbSMintz, Yuval 1806c965db44STomer Tayar return DBG_STATUS_OK; 1807c965db44STomer Tayar } 1808c965db44STomer Tayar 18097b6859fbSMintz, Yuval static struct dbg_bus_block *get_dbg_bus_block_desc(struct qed_hwfn *p_hwfn, 18107b6859fbSMintz, Yuval enum block_id block_id) 18117b6859fbSMintz, Yuval { 18127b6859fbSMintz, Yuval struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 18137b6859fbSMintz, Yuval 18147b6859fbSMintz, Yuval return (struct dbg_bus_block *)&dbg_bus_blocks[block_id * 18157b6859fbSMintz, Yuval MAX_CHIP_IDS + 18167b6859fbSMintz, Yuval dev_data->chip_id]; 18177b6859fbSMintz, Yuval } 18187b6859fbSMintz, Yuval 1819c965db44STomer Tayar /* Reads the FW info structure for the specified Storm from the chip, 1820c965db44STomer Tayar * and writes it to the specified fw_info pointer. 1821c965db44STomer Tayar */ 1822c965db44STomer Tayar static void qed_read_fw_info(struct qed_hwfn *p_hwfn, 1823c965db44STomer Tayar struct qed_ptt *p_ptt, 1824c965db44STomer Tayar u8 storm_id, struct fw_info *fw_info) 1825c965db44STomer Tayar { 18267b6859fbSMintz, Yuval struct storm_defs *storm = &s_storm_defs[storm_id]; 1827c965db44STomer Tayar struct fw_info_location fw_info_location; 18287b6859fbSMintz, Yuval u32 addr, i, *dest; 1829c965db44STomer Tayar 1830c965db44STomer Tayar memset(&fw_info_location, 0, sizeof(fw_info_location)); 1831c965db44STomer Tayar memset(fw_info, 0, sizeof(*fw_info)); 18327b6859fbSMintz, Yuval 18337b6859fbSMintz, Yuval /* Read first the address that points to fw_info location. 18347b6859fbSMintz, Yuval * The address is located in the last line of the Storm RAM. 18357b6859fbSMintz, Yuval */ 18367b6859fbSMintz, Yuval addr = storm->sem_fast_mem_addr + SEM_FAST_REG_INT_RAM + 183721dd79e8STomer Tayar DWORDS_TO_BYTES(SEM_FAST_REG_INT_RAM_SIZE_BB_K2) - 18387b6859fbSMintz, Yuval sizeof(fw_info_location); 18397b6859fbSMintz, Yuval dest = (u32 *)&fw_info_location; 18407b6859fbSMintz, Yuval 1841c965db44STomer Tayar for (i = 0; i < BYTES_TO_DWORDS(sizeof(fw_info_location)); 1842c965db44STomer Tayar i++, addr += BYTES_IN_DWORD) 1843c965db44STomer Tayar dest[i] = qed_rd(p_hwfn, p_ptt, addr); 18447b6859fbSMintz, Yuval 18457b6859fbSMintz, Yuval /* Read FW version info from Storm RAM */ 1846c965db44STomer Tayar if (fw_info_location.size > 0 && fw_info_location.size <= 1847c965db44STomer Tayar sizeof(*fw_info)) { 1848c965db44STomer Tayar addr = fw_info_location.grc_addr; 1849c965db44STomer Tayar dest = (u32 *)fw_info; 1850c965db44STomer Tayar for (i = 0; i < BYTES_TO_DWORDS(fw_info_location.size); 1851c965db44STomer Tayar i++, addr += BYTES_IN_DWORD) 1852c965db44STomer Tayar dest[i] = qed_rd(p_hwfn, p_ptt, addr); 1853c965db44STomer Tayar } 1854c965db44STomer Tayar } 1855c965db44STomer Tayar 18567b6859fbSMintz, Yuval /* Dumps the specified string to the specified buffer. 18577b6859fbSMintz, Yuval * Returns the dumped size in bytes. 1858c965db44STomer Tayar */ 1859c965db44STomer Tayar static u32 qed_dump_str(char *dump_buf, bool dump, const char *str) 1860c965db44STomer Tayar { 1861c965db44STomer Tayar if (dump) 1862c965db44STomer Tayar strcpy(dump_buf, str); 18637b6859fbSMintz, Yuval 1864c965db44STomer Tayar return (u32)strlen(str) + 1; 1865c965db44STomer Tayar } 1866c965db44STomer Tayar 18677b6859fbSMintz, Yuval /* Dumps zeros to align the specified buffer to dwords. 18687b6859fbSMintz, Yuval * Returns the dumped size in bytes. 1869c965db44STomer Tayar */ 1870c965db44STomer Tayar static u32 qed_dump_align(char *dump_buf, bool dump, u32 byte_offset) 1871c965db44STomer Tayar { 18727b6859fbSMintz, Yuval u8 offset_in_dword, align_size; 1873c965db44STomer Tayar 18747b6859fbSMintz, Yuval offset_in_dword = (u8)(byte_offset & 0x3); 1875c965db44STomer Tayar align_size = offset_in_dword ? BYTES_IN_DWORD - offset_in_dword : 0; 1876c965db44STomer Tayar 1877c965db44STomer Tayar if (dump && align_size) 1878c965db44STomer Tayar memset(dump_buf, 0, align_size); 18797b6859fbSMintz, Yuval 1880c965db44STomer Tayar return align_size; 1881c965db44STomer Tayar } 1882c965db44STomer Tayar 1883c965db44STomer Tayar /* Writes the specified string param to the specified buffer. 1884c965db44STomer Tayar * Returns the dumped size in dwords. 1885c965db44STomer Tayar */ 1886c965db44STomer Tayar static u32 qed_dump_str_param(u32 *dump_buf, 1887c965db44STomer Tayar bool dump, 1888c965db44STomer Tayar const char *param_name, const char *param_val) 1889c965db44STomer Tayar { 1890c965db44STomer Tayar char *char_buf = (char *)dump_buf; 1891c965db44STomer Tayar u32 offset = 0; 1892c965db44STomer Tayar 1893c965db44STomer Tayar /* Dump param name */ 1894c965db44STomer Tayar offset += qed_dump_str(char_buf + offset, dump, param_name); 1895c965db44STomer Tayar 1896c965db44STomer Tayar /* Indicate a string param value */ 1897c965db44STomer Tayar if (dump) 1898c965db44STomer Tayar *(char_buf + offset) = 1; 1899c965db44STomer Tayar offset++; 1900c965db44STomer Tayar 1901c965db44STomer Tayar /* Dump param value */ 1902c965db44STomer Tayar offset += qed_dump_str(char_buf + offset, dump, param_val); 1903c965db44STomer Tayar 1904c965db44STomer Tayar /* Align buffer to next dword */ 1905c965db44STomer Tayar offset += qed_dump_align(char_buf + offset, dump, offset); 19067b6859fbSMintz, Yuval 1907c965db44STomer Tayar return BYTES_TO_DWORDS(offset); 1908c965db44STomer Tayar } 1909c965db44STomer Tayar 1910c965db44STomer Tayar /* Writes the specified numeric param to the specified buffer. 1911c965db44STomer Tayar * Returns the dumped size in dwords. 1912c965db44STomer Tayar */ 1913c965db44STomer Tayar static u32 qed_dump_num_param(u32 *dump_buf, 1914c965db44STomer Tayar bool dump, const char *param_name, u32 param_val) 1915c965db44STomer Tayar { 1916c965db44STomer Tayar char *char_buf = (char *)dump_buf; 1917c965db44STomer Tayar u32 offset = 0; 1918c965db44STomer Tayar 1919c965db44STomer Tayar /* Dump param name */ 1920c965db44STomer Tayar offset += qed_dump_str(char_buf + offset, dump, param_name); 1921c965db44STomer Tayar 1922c965db44STomer Tayar /* Indicate a numeric param value */ 1923c965db44STomer Tayar if (dump) 1924c965db44STomer Tayar *(char_buf + offset) = 0; 1925c965db44STomer Tayar offset++; 1926c965db44STomer Tayar 1927c965db44STomer Tayar /* Align buffer to next dword */ 1928c965db44STomer Tayar offset += qed_dump_align(char_buf + offset, dump, offset); 1929c965db44STomer Tayar 1930c965db44STomer Tayar /* Dump param value (and change offset from bytes to dwords) */ 1931c965db44STomer Tayar offset = BYTES_TO_DWORDS(offset); 1932c965db44STomer Tayar if (dump) 1933c965db44STomer Tayar *(dump_buf + offset) = param_val; 1934c965db44STomer Tayar offset++; 19357b6859fbSMintz, Yuval 1936c965db44STomer Tayar return offset; 1937c965db44STomer Tayar } 1938c965db44STomer Tayar 1939c965db44STomer Tayar /* Reads the FW version and writes it as a param to the specified buffer. 1940c965db44STomer Tayar * Returns the dumped size in dwords. 1941c965db44STomer Tayar */ 1942c965db44STomer Tayar static u32 qed_dump_fw_ver_param(struct qed_hwfn *p_hwfn, 1943c965db44STomer Tayar struct qed_ptt *p_ptt, 1944c965db44STomer Tayar u32 *dump_buf, bool dump) 1945c965db44STomer Tayar { 1946c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 1947c965db44STomer Tayar char fw_ver_str[16] = EMPTY_FW_VERSION_STR; 1948c965db44STomer Tayar char fw_img_str[16] = EMPTY_FW_IMAGE_STR; 1949c965db44STomer Tayar struct fw_info fw_info = { {0}, {0} }; 1950c965db44STomer Tayar u32 offset = 0; 1951c965db44STomer Tayar 1952be086e7cSMintz, Yuval if (dump && !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_FW_VER)) { 1953c965db44STomer Tayar /* Read FW image/version from PRAM in a non-reset SEMI */ 1954c965db44STomer Tayar bool found = false; 1955c965db44STomer Tayar u8 storm_id; 1956c965db44STomer Tayar 1957c965db44STomer Tayar for (storm_id = 0; storm_id < MAX_DBG_STORMS && !found; 1958c965db44STomer Tayar storm_id++) { 19597b6859fbSMintz, Yuval struct storm_defs *storm = &s_storm_defs[storm_id]; 19607b6859fbSMintz, Yuval 1961c965db44STomer Tayar /* Read FW version/image */ 19627b6859fbSMintz, Yuval if (dev_data->block_in_reset[storm->block_id]) 19637b6859fbSMintz, Yuval continue; 19647b6859fbSMintz, Yuval 19657b6859fbSMintz, Yuval /* Read FW info for the current Storm */ 19667b6859fbSMintz, Yuval qed_read_fw_info(p_hwfn, p_ptt, storm_id, &fw_info); 1967c965db44STomer Tayar 1968c965db44STomer Tayar /* Create FW version/image strings */ 19697b6859fbSMintz, Yuval if (snprintf(fw_ver_str, sizeof(fw_ver_str), 19707b6859fbSMintz, Yuval "%d_%d_%d_%d", fw_info.ver.num.major, 19717b6859fbSMintz, Yuval fw_info.ver.num.minor, fw_info.ver.num.rev, 19727b6859fbSMintz, Yuval fw_info.ver.num.eng) < 0) 1973c965db44STomer Tayar DP_NOTICE(p_hwfn, 1974c965db44STomer Tayar "Unexpected debug error: invalid FW version string\n"); 1975c965db44STomer Tayar switch (fw_info.ver.image_id) { 1976c965db44STomer Tayar case FW_IMG_MAIN: 1977c965db44STomer Tayar strcpy(fw_img_str, "main"); 1978c965db44STomer Tayar break; 1979c965db44STomer Tayar default: 1980c965db44STomer Tayar strcpy(fw_img_str, "unknown"); 1981c965db44STomer Tayar break; 1982c965db44STomer Tayar } 1983c965db44STomer Tayar 1984c965db44STomer Tayar found = true; 1985c965db44STomer Tayar } 1986c965db44STomer Tayar } 1987c965db44STomer Tayar 1988c965db44STomer Tayar /* Dump FW version, image and timestamp */ 1989c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 1990c965db44STomer Tayar dump, "fw-version", fw_ver_str); 1991c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 1992c965db44STomer Tayar dump, "fw-image", fw_img_str); 1993c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 1994c965db44STomer Tayar dump, 1995c965db44STomer Tayar "fw-timestamp", fw_info.ver.timestamp); 19967b6859fbSMintz, Yuval 1997c965db44STomer Tayar return offset; 1998c965db44STomer Tayar } 1999c965db44STomer Tayar 2000c965db44STomer Tayar /* Reads the MFW version and writes it as a param to the specified buffer. 2001c965db44STomer Tayar * Returns the dumped size in dwords. 2002c965db44STomer Tayar */ 2003c965db44STomer Tayar static u32 qed_dump_mfw_ver_param(struct qed_hwfn *p_hwfn, 2004c965db44STomer Tayar struct qed_ptt *p_ptt, 2005c965db44STomer Tayar u32 *dump_buf, bool dump) 2006c965db44STomer Tayar { 2007c965db44STomer Tayar char mfw_ver_str[16] = EMPTY_FW_VERSION_STR; 2008c965db44STomer Tayar 20097b6859fbSMintz, Yuval if (dump && 20107b6859fbSMintz, Yuval !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_FW_VER)) { 2011c965db44STomer Tayar u32 global_section_offsize, global_section_addr, mfw_ver; 2012c965db44STomer Tayar u32 public_data_addr, global_section_offsize_addr; 2013c965db44STomer Tayar 20147b6859fbSMintz, Yuval /* Find MCP public data GRC address. Needs to be ORed with 20157b6859fbSMintz, Yuval * MCP_REG_SCRATCH due to a HW bug. 2016c965db44STomer Tayar */ 20177b6859fbSMintz, Yuval public_data_addr = qed_rd(p_hwfn, 20187b6859fbSMintz, Yuval p_ptt, 2019c965db44STomer Tayar MISC_REG_SHARED_MEM_ADDR) | 2020c965db44STomer Tayar MCP_REG_SCRATCH; 2021c965db44STomer Tayar 2022c965db44STomer Tayar /* Find MCP public global section offset */ 2023c965db44STomer Tayar global_section_offsize_addr = public_data_addr + 2024c965db44STomer Tayar offsetof(struct mcp_public_data, 2025c965db44STomer Tayar sections) + 2026c965db44STomer Tayar sizeof(offsize_t) * PUBLIC_GLOBAL; 2027c965db44STomer Tayar global_section_offsize = qed_rd(p_hwfn, p_ptt, 2028c965db44STomer Tayar global_section_offsize_addr); 20297b6859fbSMintz, Yuval global_section_addr = 20307b6859fbSMintz, Yuval MCP_REG_SCRATCH + 20317b6859fbSMintz, Yuval (global_section_offsize & OFFSIZE_OFFSET_MASK) * 4; 2032c965db44STomer Tayar 2033c965db44STomer Tayar /* Read MFW version from MCP public global section */ 2034c965db44STomer Tayar mfw_ver = qed_rd(p_hwfn, p_ptt, 2035c965db44STomer Tayar global_section_addr + 2036c965db44STomer Tayar offsetof(struct public_global, mfw_ver)); 2037c965db44STomer Tayar 2038c965db44STomer Tayar /* Dump MFW version param */ 20397b6859fbSMintz, Yuval if (snprintf(mfw_ver_str, sizeof(mfw_ver_str), "%d_%d_%d_%d", 20407b6859fbSMintz, Yuval (u8)(mfw_ver >> 24), (u8)(mfw_ver >> 16), 20417b6859fbSMintz, Yuval (u8)(mfw_ver >> 8), (u8)mfw_ver) < 0) 2042c965db44STomer Tayar DP_NOTICE(p_hwfn, 2043c965db44STomer Tayar "Unexpected debug error: invalid MFW version string\n"); 2044c965db44STomer Tayar } 2045c965db44STomer Tayar 2046c965db44STomer Tayar return qed_dump_str_param(dump_buf, dump, "mfw-version", mfw_ver_str); 2047c965db44STomer Tayar } 2048c965db44STomer Tayar 2049c965db44STomer Tayar /* Writes a section header to the specified buffer. 2050c965db44STomer Tayar * Returns the dumped size in dwords. 2051c965db44STomer Tayar */ 2052c965db44STomer Tayar static u32 qed_dump_section_hdr(u32 *dump_buf, 2053c965db44STomer Tayar bool dump, const char *name, u32 num_params) 2054c965db44STomer Tayar { 2055c965db44STomer Tayar return qed_dump_num_param(dump_buf, dump, name, num_params); 2056c965db44STomer Tayar } 2057c965db44STomer Tayar 2058c965db44STomer Tayar /* Writes the common global params to the specified buffer. 2059c965db44STomer Tayar * Returns the dumped size in dwords. 2060c965db44STomer Tayar */ 2061c965db44STomer Tayar static u32 qed_dump_common_global_params(struct qed_hwfn *p_hwfn, 2062c965db44STomer Tayar struct qed_ptt *p_ptt, 2063c965db44STomer Tayar u32 *dump_buf, 2064c965db44STomer Tayar bool dump, 2065c965db44STomer Tayar u8 num_specific_global_params) 2066c965db44STomer Tayar { 2067c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2068c965db44STomer Tayar u32 offset = 0; 20697b6859fbSMintz, Yuval u8 num_params; 2070c965db44STomer Tayar 20717b6859fbSMintz, Yuval /* Dump global params section header */ 20727b6859fbSMintz, Yuval num_params = NUM_COMMON_GLOBAL_PARAMS + num_specific_global_params; 2073c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, 2074be086e7cSMintz, Yuval dump, "global_params", num_params); 2075c965db44STomer Tayar 2076c965db44STomer Tayar /* Store params */ 2077c965db44STomer Tayar offset += qed_dump_fw_ver_param(p_hwfn, p_ptt, dump_buf + offset, dump); 2078c965db44STomer Tayar offset += qed_dump_mfw_ver_param(p_hwfn, 2079c965db44STomer Tayar p_ptt, dump_buf + offset, dump); 2080c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 2081c965db44STomer Tayar dump, "tools-version", TOOLS_VERSION); 2082c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 2083c965db44STomer Tayar dump, 2084c965db44STomer Tayar "chip", 2085c965db44STomer Tayar s_chip_defs[dev_data->chip_id].name); 2086c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 2087c965db44STomer Tayar dump, 2088c965db44STomer Tayar "platform", 2089c965db44STomer Tayar s_platform_defs[dev_data->platform_id]. 2090c965db44STomer Tayar name); 2091c965db44STomer Tayar offset += 2092c965db44STomer Tayar qed_dump_num_param(dump_buf + offset, dump, "pci-func", 2093c965db44STomer Tayar p_hwfn->abs_pf_id); 20947b6859fbSMintz, Yuval 2095c965db44STomer Tayar return offset; 2096c965db44STomer Tayar } 2097c965db44STomer Tayar 20987b6859fbSMintz, Yuval /* Writes the "last" section (including CRC) to the specified buffer at the 20997b6859fbSMintz, Yuval * given offset. Returns the dumped size in dwords. 2100c965db44STomer Tayar */ 2101da090917STomer Tayar static u32 qed_dump_last_section(u32 *dump_buf, u32 offset, bool dump) 2102c965db44STomer Tayar { 21037b6859fbSMintz, Yuval u32 start_offset = offset; 2104c965db44STomer Tayar 2105c965db44STomer Tayar /* Dump CRC section header */ 2106c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, dump, "last", 0); 2107c965db44STomer Tayar 21087b6859fbSMintz, Yuval /* Calculate CRC32 and add it to the dword after the "last" section */ 2109c965db44STomer Tayar if (dump) 21107b6859fbSMintz, Yuval *(dump_buf + offset) = ~crc32(0xffffffff, 21117b6859fbSMintz, Yuval (u8 *)dump_buf, 2112c965db44STomer Tayar DWORDS_TO_BYTES(offset)); 21137b6859fbSMintz, Yuval 2114c965db44STomer Tayar offset++; 21157b6859fbSMintz, Yuval 2116c965db44STomer Tayar return offset - start_offset; 2117c965db44STomer Tayar } 2118c965db44STomer Tayar 2119c965db44STomer Tayar /* Update blocks reset state */ 2120c965db44STomer Tayar static void qed_update_blocks_reset_state(struct qed_hwfn *p_hwfn, 2121c965db44STomer Tayar struct qed_ptt *p_ptt) 2122c965db44STomer Tayar { 2123c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2124c965db44STomer Tayar u32 reg_val[MAX_DBG_RESET_REGS] = { 0 }; 2125c965db44STomer Tayar u32 i; 2126c965db44STomer Tayar 2127c965db44STomer Tayar /* Read reset registers */ 2128c965db44STomer Tayar for (i = 0; i < MAX_DBG_RESET_REGS; i++) 2129c965db44STomer Tayar if (s_reset_regs_defs[i].exists[dev_data->chip_id]) 2130c965db44STomer Tayar reg_val[i] = qed_rd(p_hwfn, 2131c965db44STomer Tayar p_ptt, s_reset_regs_defs[i].addr); 2132c965db44STomer Tayar 2133c965db44STomer Tayar /* Check if blocks are in reset */ 21347b6859fbSMintz, Yuval for (i = 0; i < MAX_BLOCK_ID; i++) { 21357b6859fbSMintz, Yuval struct block_defs *block = s_block_defs[i]; 21367b6859fbSMintz, Yuval 21377b6859fbSMintz, Yuval dev_data->block_in_reset[i] = block->has_reset_bit && 21387b6859fbSMintz, Yuval !(reg_val[block->reset_reg] & BIT(block->reset_bit_offset)); 21397b6859fbSMintz, Yuval } 2140c965db44STomer Tayar } 2141c965db44STomer Tayar 2142c965db44STomer Tayar /* Enable / disable the Debug block */ 2143c965db44STomer Tayar static void qed_bus_enable_dbg_block(struct qed_hwfn *p_hwfn, 2144c965db44STomer Tayar struct qed_ptt *p_ptt, bool enable) 2145c965db44STomer Tayar { 2146c965db44STomer Tayar qed_wr(p_hwfn, p_ptt, DBG_REG_DBG_BLOCK_ON, enable ? 1 : 0); 2147c965db44STomer Tayar } 2148c965db44STomer Tayar 2149c965db44STomer Tayar /* Resets the Debug block */ 2150c965db44STomer Tayar static void qed_bus_reset_dbg_block(struct qed_hwfn *p_hwfn, 2151c965db44STomer Tayar struct qed_ptt *p_ptt) 2152c965db44STomer Tayar { 2153c965db44STomer Tayar u32 dbg_reset_reg_addr, old_reset_reg_val, new_reset_reg_val; 21547b6859fbSMintz, Yuval struct block_defs *dbg_block = s_block_defs[BLOCK_DBG]; 2155c965db44STomer Tayar 21567b6859fbSMintz, Yuval dbg_reset_reg_addr = s_reset_regs_defs[dbg_block->reset_reg].addr; 2157c965db44STomer Tayar old_reset_reg_val = qed_rd(p_hwfn, p_ptt, dbg_reset_reg_addr); 21587b6859fbSMintz, Yuval new_reset_reg_val = 21597b6859fbSMintz, Yuval old_reset_reg_val & ~BIT(dbg_block->reset_bit_offset); 2160c965db44STomer Tayar 2161c965db44STomer Tayar qed_wr(p_hwfn, p_ptt, dbg_reset_reg_addr, new_reset_reg_val); 2162c965db44STomer Tayar qed_wr(p_hwfn, p_ptt, dbg_reset_reg_addr, old_reset_reg_val); 2163c965db44STomer Tayar } 2164c965db44STomer Tayar 2165c965db44STomer Tayar static void qed_bus_set_framing_mode(struct qed_hwfn *p_hwfn, 2166c965db44STomer Tayar struct qed_ptt *p_ptt, 2167c965db44STomer Tayar enum dbg_bus_frame_modes mode) 2168c965db44STomer Tayar { 2169c965db44STomer Tayar qed_wr(p_hwfn, p_ptt, DBG_REG_FRAMING_MODE, (u8)mode); 2170c965db44STomer Tayar } 2171c965db44STomer Tayar 21727b6859fbSMintz, Yuval /* Enable / disable Debug Bus clients according to the specified mask 21737b6859fbSMintz, Yuval * (1 = enable, 0 = disable). 2174c965db44STomer Tayar */ 2175c965db44STomer Tayar static void qed_bus_enable_clients(struct qed_hwfn *p_hwfn, 2176c965db44STomer Tayar struct qed_ptt *p_ptt, u32 client_mask) 2177c965db44STomer Tayar { 2178c965db44STomer Tayar qed_wr(p_hwfn, p_ptt, DBG_REG_CLIENT_ENABLE, client_mask); 2179c965db44STomer Tayar } 2180c965db44STomer Tayar 2181c965db44STomer Tayar static bool qed_is_mode_match(struct qed_hwfn *p_hwfn, u16 *modes_buf_offset) 2182c965db44STomer Tayar { 2183c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2184c965db44STomer Tayar bool arg1, arg2; 21857b6859fbSMintz, Yuval const u32 *ptr; 21867b6859fbSMintz, Yuval u8 tree_val; 21877b6859fbSMintz, Yuval 21887b6859fbSMintz, Yuval /* Get next element from modes tree buffer */ 21897b6859fbSMintz, Yuval ptr = s_dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr; 21907b6859fbSMintz, Yuval tree_val = ((u8 *)ptr)[(*modes_buf_offset)++]; 2191c965db44STomer Tayar 2192c965db44STomer Tayar switch (tree_val) { 2193c965db44STomer Tayar case INIT_MODE_OP_NOT: 2194c965db44STomer Tayar return !qed_is_mode_match(p_hwfn, modes_buf_offset); 2195c965db44STomer Tayar case INIT_MODE_OP_OR: 2196c965db44STomer Tayar case INIT_MODE_OP_AND: 2197c965db44STomer Tayar arg1 = qed_is_mode_match(p_hwfn, modes_buf_offset); 2198c965db44STomer Tayar arg2 = qed_is_mode_match(p_hwfn, modes_buf_offset); 2199c965db44STomer Tayar return (tree_val == INIT_MODE_OP_OR) ? (arg1 || 2200c965db44STomer Tayar arg2) : (arg1 && arg2); 2201c965db44STomer Tayar default: 2202c965db44STomer Tayar return dev_data->mode_enable[tree_val - MAX_INIT_MODE_OPS] > 0; 2203c965db44STomer Tayar } 2204c965db44STomer Tayar } 2205c965db44STomer Tayar 2206c965db44STomer Tayar /* Returns true if the specified entity (indicated by GRC param) should be 2207c965db44STomer Tayar * included in the dump, false otherwise. 2208c965db44STomer Tayar */ 2209c965db44STomer Tayar static bool qed_grc_is_included(struct qed_hwfn *p_hwfn, 2210c965db44STomer Tayar enum dbg_grc_params grc_param) 2211c965db44STomer Tayar { 2212c965db44STomer Tayar return qed_grc_get_param(p_hwfn, grc_param) > 0; 2213c965db44STomer Tayar } 2214c965db44STomer Tayar 2215c965db44STomer Tayar /* Returns true of the specified Storm should be included in the dump, false 2216c965db44STomer Tayar * otherwise. 2217c965db44STomer Tayar */ 2218c965db44STomer Tayar static bool qed_grc_is_storm_included(struct qed_hwfn *p_hwfn, 2219c965db44STomer Tayar enum dbg_storms storm) 2220c965db44STomer Tayar { 2221c965db44STomer Tayar return qed_grc_get_param(p_hwfn, (enum dbg_grc_params)storm) > 0; 2222c965db44STomer Tayar } 2223c965db44STomer Tayar 2224c965db44STomer Tayar /* Returns true if the specified memory should be included in the dump, false 2225c965db44STomer Tayar * otherwise. 2226c965db44STomer Tayar */ 2227c965db44STomer Tayar static bool qed_grc_is_mem_included(struct qed_hwfn *p_hwfn, 2228c965db44STomer Tayar enum block_id block_id, u8 mem_group_id) 2229c965db44STomer Tayar { 22307b6859fbSMintz, Yuval struct block_defs *block = s_block_defs[block_id]; 2231c965db44STomer Tayar u8 i; 2232c965db44STomer Tayar 2233c965db44STomer Tayar /* Check Storm match */ 22347b6859fbSMintz, Yuval if (block->associated_to_storm && 2235c965db44STomer Tayar !qed_grc_is_storm_included(p_hwfn, 22367b6859fbSMintz, Yuval (enum dbg_storms)block->storm_id)) 2237c965db44STomer Tayar return false; 2238c965db44STomer Tayar 22397b6859fbSMintz, Yuval for (i = 0; i < NUM_BIG_RAM_TYPES; i++) { 22407b6859fbSMintz, Yuval struct big_ram_defs *big_ram = &s_big_ram_defs[i]; 2241c965db44STomer Tayar 22427b6859fbSMintz, Yuval if (mem_group_id == big_ram->mem_group_id || 22437b6859fbSMintz, Yuval mem_group_id == big_ram->ram_mem_group_id) 22447b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, big_ram->grc_param); 22457b6859fbSMintz, Yuval } 22467b6859fbSMintz, Yuval 22477b6859fbSMintz, Yuval switch (mem_group_id) { 22487b6859fbSMintz, Yuval case MEM_GROUP_PXP_ILT: 22497b6859fbSMintz, Yuval case MEM_GROUP_PXP_MEM: 22507b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_PXP); 22517b6859fbSMintz, Yuval case MEM_GROUP_RAM: 22527b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_RAM); 22537b6859fbSMintz, Yuval case MEM_GROUP_PBUF: 22547b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_PBUF); 22557b6859fbSMintz, Yuval case MEM_GROUP_CAU_MEM: 22567b6859fbSMintz, Yuval case MEM_GROUP_CAU_SB: 22577b6859fbSMintz, Yuval case MEM_GROUP_CAU_PI: 22587b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CAU); 22597b6859fbSMintz, Yuval case MEM_GROUP_QM_MEM: 22607b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_QM); 22617b6859fbSMintz, Yuval case MEM_GROUP_CFC_MEM: 22627b6859fbSMintz, Yuval case MEM_GROUP_CONN_CFC_MEM: 22637b6859fbSMintz, Yuval case MEM_GROUP_TASK_CFC_MEM: 2264da090917STomer Tayar return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CFC) || 2265da090917STomer Tayar qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CM_CTX); 22667b6859fbSMintz, Yuval case MEM_GROUP_IGU_MEM: 22677b6859fbSMintz, Yuval case MEM_GROUP_IGU_MSIX: 22687b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_IGU); 22697b6859fbSMintz, Yuval case MEM_GROUP_MULD_MEM: 22707b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_MULD); 22717b6859fbSMintz, Yuval case MEM_GROUP_PRS_MEM: 22727b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_PRS); 22737b6859fbSMintz, Yuval case MEM_GROUP_DMAE_MEM: 22747b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_DMAE); 22757b6859fbSMintz, Yuval case MEM_GROUP_TM_MEM: 22767b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_TM); 22777b6859fbSMintz, Yuval case MEM_GROUP_SDM_MEM: 22787b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_SDM); 22797b6859fbSMintz, Yuval case MEM_GROUP_TDIF_CTX: 22807b6859fbSMintz, Yuval case MEM_GROUP_RDIF_CTX: 22817b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_DIF); 22827b6859fbSMintz, Yuval case MEM_GROUP_CM_MEM: 22837b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CM); 22847b6859fbSMintz, Yuval case MEM_GROUP_IOR: 22857b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_IOR); 22867b6859fbSMintz, Yuval default: 2287c965db44STomer Tayar return true; 2288c965db44STomer Tayar } 22897b6859fbSMintz, Yuval } 2290c965db44STomer Tayar 2291c965db44STomer Tayar /* Stalls all Storms */ 2292c965db44STomer Tayar static void qed_grc_stall_storms(struct qed_hwfn *p_hwfn, 2293c965db44STomer Tayar struct qed_ptt *p_ptt, bool stall) 2294c965db44STomer Tayar { 22957b6859fbSMintz, Yuval u32 reg_addr; 2296c965db44STomer Tayar u8 storm_id; 2297c965db44STomer Tayar 2298c965db44STomer Tayar for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 22997b6859fbSMintz, Yuval if (!qed_grc_is_storm_included(p_hwfn, 23007b6859fbSMintz, Yuval (enum dbg_storms)storm_id)) 23017b6859fbSMintz, Yuval continue; 2302c965db44STomer Tayar 23037b6859fbSMintz, Yuval reg_addr = s_storm_defs[storm_id].sem_fast_mem_addr + 23047b6859fbSMintz, Yuval SEM_FAST_REG_STALL_0_BB_K2; 23057b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, reg_addr, stall ? 1 : 0); 2306c965db44STomer Tayar } 2307c965db44STomer Tayar 2308c965db44STomer Tayar msleep(STALL_DELAY_MS); 2309c965db44STomer Tayar } 2310c965db44STomer Tayar 2311c965db44STomer Tayar /* Takes all blocks out of reset */ 2312c965db44STomer Tayar static void qed_grc_unreset_blocks(struct qed_hwfn *p_hwfn, 2313c965db44STomer Tayar struct qed_ptt *p_ptt) 2314c965db44STomer Tayar { 2315c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2316c965db44STomer Tayar u32 reg_val[MAX_DBG_RESET_REGS] = { 0 }; 23177b6859fbSMintz, Yuval u32 block_id, i; 2318c965db44STomer Tayar 2319c965db44STomer Tayar /* Fill reset regs values */ 23207b6859fbSMintz, Yuval for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) { 23217b6859fbSMintz, Yuval struct block_defs *block = s_block_defs[block_id]; 23227b6859fbSMintz, Yuval 2323da090917STomer Tayar if (block->exists[dev_data->chip_id] && block->has_reset_bit && 2324da090917STomer Tayar block->unreset) 23257b6859fbSMintz, Yuval reg_val[block->reset_reg] |= 23267b6859fbSMintz, Yuval BIT(block->reset_bit_offset); 23277b6859fbSMintz, Yuval } 2328c965db44STomer Tayar 2329c965db44STomer Tayar /* Write reset registers */ 2330c965db44STomer Tayar for (i = 0; i < MAX_DBG_RESET_REGS; i++) { 23317b6859fbSMintz, Yuval if (!s_reset_regs_defs[i].exists[dev_data->chip_id]) 23327b6859fbSMintz, Yuval continue; 23337b6859fbSMintz, Yuval 2334da090917STomer Tayar reg_val[i] |= 2335da090917STomer Tayar s_reset_regs_defs[i].unreset_val[dev_data->chip_id]; 23367b6859fbSMintz, Yuval 2337c965db44STomer Tayar if (reg_val[i]) 2338c965db44STomer Tayar qed_wr(p_hwfn, 2339c965db44STomer Tayar p_ptt, 2340c965db44STomer Tayar s_reset_regs_defs[i].addr + 2341c965db44STomer Tayar RESET_REG_UNRESET_OFFSET, reg_val[i]); 2342c965db44STomer Tayar } 2343c965db44STomer Tayar } 2344c965db44STomer Tayar 2345be086e7cSMintz, Yuval /* Returns the attention block data of the specified block */ 2346c965db44STomer Tayar static const struct dbg_attn_block_type_data * 2347c965db44STomer Tayar qed_get_block_attn_data(enum block_id block_id, enum dbg_attn_type attn_type) 2348c965db44STomer Tayar { 2349c965db44STomer Tayar const struct dbg_attn_block *base_attn_block_arr = 2350c965db44STomer Tayar (const struct dbg_attn_block *) 2351c965db44STomer Tayar s_dbg_arrays[BIN_BUF_DBG_ATTN_BLOCKS].ptr; 2352c965db44STomer Tayar 2353c965db44STomer Tayar return &base_attn_block_arr[block_id].per_type_data[attn_type]; 2354c965db44STomer Tayar } 2355c965db44STomer Tayar 2356c965db44STomer Tayar /* Returns the attention registers of the specified block */ 2357c965db44STomer Tayar static const struct dbg_attn_reg * 2358c965db44STomer Tayar qed_get_block_attn_regs(enum block_id block_id, enum dbg_attn_type attn_type, 2359c965db44STomer Tayar u8 *num_attn_regs) 2360c965db44STomer Tayar { 2361c965db44STomer Tayar const struct dbg_attn_block_type_data *block_type_data = 2362c965db44STomer Tayar qed_get_block_attn_data(block_id, attn_type); 2363c965db44STomer Tayar 2364c965db44STomer Tayar *num_attn_regs = block_type_data->num_regs; 23657b6859fbSMintz, Yuval 2366c965db44STomer Tayar return &((const struct dbg_attn_reg *) 2367c965db44STomer Tayar s_dbg_arrays[BIN_BUF_DBG_ATTN_REGS].ptr)[block_type_data-> 2368c965db44STomer Tayar regs_offset]; 2369c965db44STomer Tayar } 2370c965db44STomer Tayar 2371c965db44STomer Tayar /* For each block, clear the status of all parities */ 2372c965db44STomer Tayar static void qed_grc_clear_all_prty(struct qed_hwfn *p_hwfn, 2373c965db44STomer Tayar struct qed_ptt *p_ptt) 2374c965db44STomer Tayar { 2375c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 23767b6859fbSMintz, Yuval const struct dbg_attn_reg *attn_reg_arr; 2377c965db44STomer Tayar u8 reg_idx, num_attn_regs; 2378c965db44STomer Tayar u32 block_id; 2379c965db44STomer Tayar 2380c965db44STomer Tayar for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) { 2381c965db44STomer Tayar if (dev_data->block_in_reset[block_id]) 2382c965db44STomer Tayar continue; 2383c965db44STomer Tayar 2384c965db44STomer Tayar attn_reg_arr = qed_get_block_attn_regs((enum block_id)block_id, 2385c965db44STomer Tayar ATTN_TYPE_PARITY, 2386c965db44STomer Tayar &num_attn_regs); 23877b6859fbSMintz, Yuval 2388c965db44STomer Tayar for (reg_idx = 0; reg_idx < num_attn_regs; reg_idx++) { 2389c965db44STomer Tayar const struct dbg_attn_reg *reg_data = 2390c965db44STomer Tayar &attn_reg_arr[reg_idx]; 23917b6859fbSMintz, Yuval u16 modes_buf_offset; 23927b6859fbSMintz, Yuval bool eval_mode; 2393c965db44STomer Tayar 2394c965db44STomer Tayar /* Check mode */ 23957b6859fbSMintz, Yuval eval_mode = GET_FIELD(reg_data->mode.data, 2396c965db44STomer Tayar DBG_MODE_HDR_EVAL_MODE) > 0; 23977b6859fbSMintz, Yuval modes_buf_offset = 2398c965db44STomer Tayar GET_FIELD(reg_data->mode.data, 2399c965db44STomer Tayar DBG_MODE_HDR_MODES_BUF_OFFSET); 2400c965db44STomer Tayar 24017b6859fbSMintz, Yuval /* If Mode match: clear parity status */ 2402c965db44STomer Tayar if (!eval_mode || 2403c965db44STomer Tayar qed_is_mode_match(p_hwfn, &modes_buf_offset)) 2404c965db44STomer Tayar qed_rd(p_hwfn, p_ptt, 2405c965db44STomer Tayar DWORDS_TO_BYTES(reg_data-> 2406c965db44STomer Tayar sts_clr_address)); 2407c965db44STomer Tayar } 2408c965db44STomer Tayar } 2409c965db44STomer Tayar } 2410c965db44STomer Tayar 2411c965db44STomer Tayar /* Dumps GRC registers section header. Returns the dumped size in dwords. 2412c965db44STomer Tayar * The following parameters are dumped: 24137b6859fbSMintz, Yuval * - count: no. of dumped entries 24147b6859fbSMintz, Yuval * - split: split type 24157b6859fbSMintz, Yuval * - id: split ID (dumped only if split_id >= 0) 24167b6859fbSMintz, Yuval * - param_name: user parameter value (dumped only if param_name != NULL 24177b6859fbSMintz, Yuval * and param_val != NULL). 2418c965db44STomer Tayar */ 2419c965db44STomer Tayar static u32 qed_grc_dump_regs_hdr(u32 *dump_buf, 2420c965db44STomer Tayar bool dump, 2421c965db44STomer Tayar u32 num_reg_entries, 2422c965db44STomer Tayar const char *split_type, 2423c965db44STomer Tayar int split_id, 2424c965db44STomer Tayar const char *param_name, const char *param_val) 2425c965db44STomer Tayar { 2426c965db44STomer Tayar u8 num_params = 2 + (split_id >= 0 ? 1 : 0) + (param_name ? 1 : 0); 2427c965db44STomer Tayar u32 offset = 0; 2428c965db44STomer Tayar 2429c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, 2430c965db44STomer Tayar dump, "grc_regs", num_params); 2431c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 2432c965db44STomer Tayar dump, "count", num_reg_entries); 2433c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 2434c965db44STomer Tayar dump, "split", split_type); 2435c965db44STomer Tayar if (split_id >= 0) 2436c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 2437c965db44STomer Tayar dump, "id", split_id); 2438c965db44STomer Tayar if (param_name && param_val) 2439c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 2440c965db44STomer Tayar dump, param_name, param_val); 24417b6859fbSMintz, Yuval 2442c965db44STomer Tayar return offset; 2443c965db44STomer Tayar } 2444c965db44STomer Tayar 2445da090917STomer Tayar /* Reads the specified registers into the specified buffer. 2446da090917STomer Tayar * The addr and len arguments are specified in dwords. 2447da090917STomer Tayar */ 2448da090917STomer Tayar void qed_read_regs(struct qed_hwfn *p_hwfn, 2449da090917STomer Tayar struct qed_ptt *p_ptt, u32 *buf, u32 addr, u32 len) 2450da090917STomer Tayar { 2451da090917STomer Tayar u32 i; 2452da090917STomer Tayar 2453da090917STomer Tayar for (i = 0; i < len; i++) 2454da090917STomer Tayar buf[i] = qed_rd(p_hwfn, p_ptt, DWORDS_TO_BYTES(addr + i)); 2455da090917STomer Tayar } 2456da090917STomer Tayar 2457be086e7cSMintz, Yuval /* Dumps the GRC registers in the specified address range. 2458be086e7cSMintz, Yuval * Returns the dumped size in dwords. 24597b6859fbSMintz, Yuval * The addr and len arguments are specified in dwords. 2460be086e7cSMintz, Yuval */ 2461be086e7cSMintz, Yuval static u32 qed_grc_dump_addr_range(struct qed_hwfn *p_hwfn, 24627b6859fbSMintz, Yuval struct qed_ptt *p_ptt, 24637b6859fbSMintz, Yuval u32 *dump_buf, 24647b6859fbSMintz, Yuval bool dump, u32 addr, u32 len, bool wide_bus) 2465be086e7cSMintz, Yuval { 2466da090917STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2467be086e7cSMintz, Yuval 24687b6859fbSMintz, Yuval if (!dump) 24697b6859fbSMintz, Yuval return len; 24707b6859fbSMintz, Yuval 2471da090917STomer Tayar /* Print log if needed */ 2472da090917STomer Tayar dev_data->num_regs_read += len; 2473da090917STomer Tayar if (dev_data->num_regs_read >= 2474da090917STomer Tayar s_platform_defs[dev_data->platform_id].log_thresh) { 2475da090917STomer Tayar DP_VERBOSE(p_hwfn, 2476da090917STomer Tayar QED_MSG_DEBUG, 2477da090917STomer Tayar "Dumping %d registers...\n", 2478da090917STomer Tayar dev_data->num_regs_read); 2479da090917STomer Tayar dev_data->num_regs_read = 0; 2480da090917STomer Tayar } 24817b6859fbSMintz, Yuval 2482da090917STomer Tayar /* Try reading using DMAE */ 2483da090917STomer Tayar if (dev_data->use_dmae && 2484da090917STomer Tayar (len >= s_platform_defs[dev_data->platform_id].dmae_thresh || 2485da090917STomer Tayar wide_bus)) { 2486da090917STomer Tayar if (!qed_dmae_grc2host(p_hwfn, p_ptt, DWORDS_TO_BYTES(addr), 2487da090917STomer Tayar (u64)(uintptr_t)(dump_buf), len, 0)) 2488da090917STomer Tayar return len; 2489da090917STomer Tayar dev_data->use_dmae = 0; 2490da090917STomer Tayar DP_VERBOSE(p_hwfn, 2491da090917STomer Tayar QED_MSG_DEBUG, 2492da090917STomer Tayar "Failed reading from chip using DMAE, using GRC instead\n"); 2493da090917STomer Tayar } 2494da090917STomer Tayar 2495da090917STomer Tayar /* Read registers */ 2496da090917STomer Tayar qed_read_regs(p_hwfn, p_ptt, dump_buf, addr, len); 2497da090917STomer Tayar 2498da090917STomer Tayar return len; 2499be086e7cSMintz, Yuval } 2500be086e7cSMintz, Yuval 25017b6859fbSMintz, Yuval /* Dumps GRC registers sequence header. Returns the dumped size in dwords. 25027b6859fbSMintz, Yuval * The addr and len arguments are specified in dwords. 25037b6859fbSMintz, Yuval */ 25047b6859fbSMintz, Yuval static u32 qed_grc_dump_reg_entry_hdr(u32 *dump_buf, 25057b6859fbSMintz, Yuval bool dump, u32 addr, u32 len) 2506be086e7cSMintz, Yuval { 2507be086e7cSMintz, Yuval if (dump) 2508be086e7cSMintz, Yuval *dump_buf = addr | (len << REG_DUMP_LEN_SHIFT); 25097b6859fbSMintz, Yuval 2510be086e7cSMintz, Yuval return 1; 2511be086e7cSMintz, Yuval } 2512be086e7cSMintz, Yuval 25137b6859fbSMintz, Yuval /* Dumps GRC registers sequence. Returns the dumped size in dwords. 25147b6859fbSMintz, Yuval * The addr and len arguments are specified in dwords. 25157b6859fbSMintz, Yuval */ 2516c965db44STomer Tayar static u32 qed_grc_dump_reg_entry(struct qed_hwfn *p_hwfn, 25177b6859fbSMintz, Yuval struct qed_ptt *p_ptt, 25187b6859fbSMintz, Yuval u32 *dump_buf, 25197b6859fbSMintz, Yuval bool dump, u32 addr, u32 len, bool wide_bus) 2520c965db44STomer Tayar { 2521be086e7cSMintz, Yuval u32 offset = 0; 2522c965db44STomer Tayar 2523be086e7cSMintz, Yuval offset += qed_grc_dump_reg_entry_hdr(dump_buf, dump, addr, len); 2524be086e7cSMintz, Yuval offset += qed_grc_dump_addr_range(p_hwfn, 2525c965db44STomer Tayar p_ptt, 25267b6859fbSMintz, Yuval dump_buf + offset, 25277b6859fbSMintz, Yuval dump, addr, len, wide_bus); 25287b6859fbSMintz, Yuval 2529be086e7cSMintz, Yuval return offset; 2530be086e7cSMintz, Yuval } 2531be086e7cSMintz, Yuval 2532be086e7cSMintz, Yuval /* Dumps GRC registers sequence with skip cycle. 2533be086e7cSMintz, Yuval * Returns the dumped size in dwords. 25347b6859fbSMintz, Yuval * - addr: start GRC address in dwords 25357b6859fbSMintz, Yuval * - total_len: total no. of dwords to dump 25367b6859fbSMintz, Yuval * - read_len: no. consecutive dwords to read 25377b6859fbSMintz, Yuval * - skip_len: no. of dwords to skip (and fill with zeros) 2538be086e7cSMintz, Yuval */ 2539be086e7cSMintz, Yuval static u32 qed_grc_dump_reg_entry_skip(struct qed_hwfn *p_hwfn, 25407b6859fbSMintz, Yuval struct qed_ptt *p_ptt, 25417b6859fbSMintz, Yuval u32 *dump_buf, 25427b6859fbSMintz, Yuval bool dump, 25437b6859fbSMintz, Yuval u32 addr, 25447b6859fbSMintz, Yuval u32 total_len, 2545be086e7cSMintz, Yuval u32 read_len, u32 skip_len) 2546be086e7cSMintz, Yuval { 2547be086e7cSMintz, Yuval u32 offset = 0, reg_offset = 0; 2548be086e7cSMintz, Yuval 2549be086e7cSMintz, Yuval offset += qed_grc_dump_reg_entry_hdr(dump_buf, dump, addr, total_len); 25507b6859fbSMintz, Yuval 25517b6859fbSMintz, Yuval if (!dump) 25527b6859fbSMintz, Yuval return offset + total_len; 25537b6859fbSMintz, Yuval 2554be086e7cSMintz, Yuval while (reg_offset < total_len) { 25557b6859fbSMintz, Yuval u32 curr_len = min_t(u32, read_len, total_len - reg_offset); 25567b6859fbSMintz, Yuval 2557be086e7cSMintz, Yuval offset += qed_grc_dump_addr_range(p_hwfn, 2558be086e7cSMintz, Yuval p_ptt, 2559be086e7cSMintz, Yuval dump_buf + offset, 25607b6859fbSMintz, Yuval dump, addr, curr_len, false); 2561be086e7cSMintz, Yuval reg_offset += curr_len; 2562be086e7cSMintz, Yuval addr += curr_len; 25637b6859fbSMintz, Yuval 2564be086e7cSMintz, Yuval if (reg_offset < total_len) { 25657b6859fbSMintz, Yuval curr_len = min_t(u32, skip_len, total_len - skip_len); 25667b6859fbSMintz, Yuval memset(dump_buf + offset, 0, DWORDS_TO_BYTES(curr_len)); 2567be086e7cSMintz, Yuval offset += curr_len; 2568be086e7cSMintz, Yuval reg_offset += curr_len; 2569be086e7cSMintz, Yuval addr += curr_len; 2570be086e7cSMintz, Yuval } 2571be086e7cSMintz, Yuval } 2572c965db44STomer Tayar 2573c965db44STomer Tayar return offset; 2574c965db44STomer Tayar } 2575c965db44STomer Tayar 2576c965db44STomer Tayar /* Dumps GRC registers entries. Returns the dumped size in dwords. */ 2577c965db44STomer Tayar static u32 qed_grc_dump_regs_entries(struct qed_hwfn *p_hwfn, 2578c965db44STomer Tayar struct qed_ptt *p_ptt, 2579c965db44STomer Tayar struct dbg_array input_regs_arr, 2580c965db44STomer Tayar u32 *dump_buf, 2581c965db44STomer Tayar bool dump, 2582c965db44STomer Tayar bool block_enable[MAX_BLOCK_ID], 2583c965db44STomer Tayar u32 *num_dumped_reg_entries) 2584c965db44STomer Tayar { 2585c965db44STomer Tayar u32 i, offset = 0, input_offset = 0; 2586c965db44STomer Tayar bool mode_match = true; 2587c965db44STomer Tayar 2588c965db44STomer Tayar *num_dumped_reg_entries = 0; 25897b6859fbSMintz, Yuval 2590c965db44STomer Tayar while (input_offset < input_regs_arr.size_in_dwords) { 2591c965db44STomer Tayar const struct dbg_dump_cond_hdr *cond_hdr = 2592c965db44STomer Tayar (const struct dbg_dump_cond_hdr *) 2593c965db44STomer Tayar &input_regs_arr.ptr[input_offset++]; 25947b6859fbSMintz, Yuval u16 modes_buf_offset; 25957b6859fbSMintz, Yuval bool eval_mode; 2596c965db44STomer Tayar 2597c965db44STomer Tayar /* Check mode/block */ 25987b6859fbSMintz, Yuval eval_mode = GET_FIELD(cond_hdr->mode.data, 25997b6859fbSMintz, Yuval DBG_MODE_HDR_EVAL_MODE) > 0; 2600c965db44STomer Tayar if (eval_mode) { 26017b6859fbSMintz, Yuval modes_buf_offset = 2602c965db44STomer Tayar GET_FIELD(cond_hdr->mode.data, 2603c965db44STomer Tayar DBG_MODE_HDR_MODES_BUF_OFFSET); 2604c965db44STomer Tayar mode_match = qed_is_mode_match(p_hwfn, 2605c965db44STomer Tayar &modes_buf_offset); 2606c965db44STomer Tayar } 2607c965db44STomer Tayar 26087b6859fbSMintz, Yuval if (!mode_match || !block_enable[cond_hdr->block_id]) { 26097b6859fbSMintz, Yuval input_offset += cond_hdr->data_size; 26107b6859fbSMintz, Yuval continue; 26117b6859fbSMintz, Yuval } 26127b6859fbSMintz, Yuval 26137b6859fbSMintz, Yuval for (i = 0; i < cond_hdr->data_size; i++, input_offset++) { 2614c965db44STomer Tayar const struct dbg_dump_reg *reg = 2615c965db44STomer Tayar (const struct dbg_dump_reg *) 2616c965db44STomer Tayar &input_regs_arr.ptr[input_offset]; 2617be086e7cSMintz, Yuval u32 addr, len; 26187b6859fbSMintz, Yuval bool wide_bus; 2619c965db44STomer Tayar 26207b6859fbSMintz, Yuval addr = GET_FIELD(reg->data, DBG_DUMP_REG_ADDRESS); 2621be086e7cSMintz, Yuval len = GET_FIELD(reg->data, DBG_DUMP_REG_LENGTH); 26227b6859fbSMintz, Yuval wide_bus = GET_FIELD(reg->data, DBG_DUMP_REG_WIDE_BUS); 26237b6859fbSMintz, Yuval offset += qed_grc_dump_reg_entry(p_hwfn, 26247b6859fbSMintz, Yuval p_ptt, 2625be086e7cSMintz, Yuval dump_buf + offset, 2626be086e7cSMintz, Yuval dump, 2627be086e7cSMintz, Yuval addr, 26287b6859fbSMintz, Yuval len, 26297b6859fbSMintz, Yuval wide_bus); 2630c965db44STomer Tayar (*num_dumped_reg_entries)++; 2631c965db44STomer Tayar } 2632c965db44STomer Tayar } 2633c965db44STomer Tayar 2634c965db44STomer Tayar return offset; 2635c965db44STomer Tayar } 2636c965db44STomer Tayar 2637c965db44STomer Tayar /* Dumps GRC registers entries. Returns the dumped size in dwords. */ 2638c965db44STomer Tayar static u32 qed_grc_dump_split_data(struct qed_hwfn *p_hwfn, 2639c965db44STomer Tayar struct qed_ptt *p_ptt, 2640c965db44STomer Tayar struct dbg_array input_regs_arr, 2641c965db44STomer Tayar u32 *dump_buf, 2642c965db44STomer Tayar bool dump, 2643c965db44STomer Tayar bool block_enable[MAX_BLOCK_ID], 2644c965db44STomer Tayar const char *split_type_name, 2645c965db44STomer Tayar u32 split_id, 2646c965db44STomer Tayar const char *param_name, 2647c965db44STomer Tayar const char *param_val) 2648c965db44STomer Tayar { 2649c965db44STomer Tayar u32 num_dumped_reg_entries, offset; 2650c965db44STomer Tayar 2651c965db44STomer Tayar /* Calculate register dump header size (and skip it for now) */ 2652c965db44STomer Tayar offset = qed_grc_dump_regs_hdr(dump_buf, 2653c965db44STomer Tayar false, 2654c965db44STomer Tayar 0, 2655c965db44STomer Tayar split_type_name, 2656c965db44STomer Tayar split_id, param_name, param_val); 2657c965db44STomer Tayar 2658c965db44STomer Tayar /* Dump registers */ 2659c965db44STomer Tayar offset += qed_grc_dump_regs_entries(p_hwfn, 2660c965db44STomer Tayar p_ptt, 2661c965db44STomer Tayar input_regs_arr, 2662c965db44STomer Tayar dump_buf + offset, 2663c965db44STomer Tayar dump, 2664c965db44STomer Tayar block_enable, 2665c965db44STomer Tayar &num_dumped_reg_entries); 2666c965db44STomer Tayar 2667c965db44STomer Tayar /* Write register dump header */ 2668c965db44STomer Tayar if (dump && num_dumped_reg_entries > 0) 2669c965db44STomer Tayar qed_grc_dump_regs_hdr(dump_buf, 2670c965db44STomer Tayar dump, 2671c965db44STomer Tayar num_dumped_reg_entries, 2672c965db44STomer Tayar split_type_name, 2673c965db44STomer Tayar split_id, param_name, param_val); 2674c965db44STomer Tayar 2675c965db44STomer Tayar return num_dumped_reg_entries > 0 ? offset : 0; 2676c965db44STomer Tayar } 2677c965db44STomer Tayar 26787b6859fbSMintz, Yuval /* Dumps registers according to the input registers array. Returns the dumped 26797b6859fbSMintz, Yuval * size in dwords. 2680c965db44STomer Tayar */ 2681c965db44STomer Tayar static u32 qed_grc_dump_registers(struct qed_hwfn *p_hwfn, 2682c965db44STomer Tayar struct qed_ptt *p_ptt, 2683c965db44STomer Tayar u32 *dump_buf, 2684c965db44STomer Tayar bool dump, 2685c965db44STomer Tayar bool block_enable[MAX_BLOCK_ID], 2686c965db44STomer Tayar const char *param_name, const char *param_val) 2687c965db44STomer Tayar { 2688c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 26897b6859fbSMintz, Yuval struct chip_platform_defs *chip_platform; 2690c965db44STomer Tayar u32 offset = 0, input_offset = 0; 26917b6859fbSMintz, Yuval struct chip_defs *chip; 2692be086e7cSMintz, Yuval u8 port_id, pf_id, vf_id; 2693be086e7cSMintz, Yuval u16 fid; 2694be086e7cSMintz, Yuval 26957b6859fbSMintz, Yuval chip = &s_chip_defs[dev_data->chip_id]; 26967b6859fbSMintz, Yuval chip_platform = &chip->per_platform[dev_data->platform_id]; 2697c965db44STomer Tayar 2698c965db44STomer Tayar while (input_offset < 2699c965db44STomer Tayar s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].size_in_dwords) { 27007b6859fbSMintz, Yuval const struct dbg_dump_split_hdr *split_hdr; 27017b6859fbSMintz, Yuval struct dbg_array curr_input_regs_arr; 27027b6859fbSMintz, Yuval u32 split_data_size; 27037b6859fbSMintz, Yuval u8 split_type_id; 27047b6859fbSMintz, Yuval 27057b6859fbSMintz, Yuval split_hdr = 2706c965db44STomer Tayar (const struct dbg_dump_split_hdr *) 2707c965db44STomer Tayar &s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].ptr[input_offset++]; 27087b6859fbSMintz, Yuval split_type_id = 27097b6859fbSMintz, Yuval GET_FIELD(split_hdr->hdr, 2710c965db44STomer Tayar DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID); 27117b6859fbSMintz, Yuval split_data_size = 27127b6859fbSMintz, Yuval GET_FIELD(split_hdr->hdr, 2713c965db44STomer Tayar DBG_DUMP_SPLIT_HDR_DATA_SIZE); 27147b6859fbSMintz, Yuval curr_input_regs_arr.ptr = 27157b6859fbSMintz, Yuval &s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].ptr[input_offset]; 27167b6859fbSMintz, Yuval curr_input_regs_arr.size_in_dwords = split_data_size; 2717c965db44STomer Tayar 2718c965db44STomer Tayar switch (split_type_id) { 2719c965db44STomer Tayar case SPLIT_TYPE_NONE: 2720c965db44STomer Tayar offset += qed_grc_dump_split_data(p_hwfn, 2721c965db44STomer Tayar p_ptt, 2722c965db44STomer Tayar curr_input_regs_arr, 2723c965db44STomer Tayar dump_buf + offset, 2724c965db44STomer Tayar dump, 2725c965db44STomer Tayar block_enable, 2726c965db44STomer Tayar "eng", 2727c965db44STomer Tayar (u32)(-1), 2728c965db44STomer Tayar param_name, 2729c965db44STomer Tayar param_val); 2730c965db44STomer Tayar break; 27317b6859fbSMintz, Yuval 2732c965db44STomer Tayar case SPLIT_TYPE_PORT: 27337b6859fbSMintz, Yuval for (port_id = 0; port_id < chip_platform->num_ports; 2734c965db44STomer Tayar port_id++) { 2735c965db44STomer Tayar if (dump) 2736c965db44STomer Tayar qed_port_pretend(p_hwfn, p_ptt, 2737c965db44STomer Tayar port_id); 2738c965db44STomer Tayar offset += 2739c965db44STomer Tayar qed_grc_dump_split_data(p_hwfn, p_ptt, 2740c965db44STomer Tayar curr_input_regs_arr, 2741c965db44STomer Tayar dump_buf + offset, 2742c965db44STomer Tayar dump, block_enable, 2743c965db44STomer Tayar "port", port_id, 2744c965db44STomer Tayar param_name, 2745c965db44STomer Tayar param_val); 2746c965db44STomer Tayar } 2747c965db44STomer Tayar break; 27487b6859fbSMintz, Yuval 2749c965db44STomer Tayar case SPLIT_TYPE_PF: 2750c965db44STomer Tayar case SPLIT_TYPE_PORT_PF: 27517b6859fbSMintz, Yuval for (pf_id = 0; pf_id < chip_platform->num_pfs; 2752c965db44STomer Tayar pf_id++) { 2753be086e7cSMintz, Yuval u8 pfid_shift = 2754be086e7cSMintz, Yuval PXP_PRETEND_CONCRETE_FID_PFID_SHIFT; 2755be086e7cSMintz, Yuval 2756be086e7cSMintz, Yuval if (dump) { 2757be086e7cSMintz, Yuval fid = pf_id << pfid_shift; 2758be086e7cSMintz, Yuval qed_fid_pretend(p_hwfn, p_ptt, fid); 2759be086e7cSMintz, Yuval } 2760be086e7cSMintz, Yuval 2761be086e7cSMintz, Yuval offset += 27627b6859fbSMintz, Yuval qed_grc_dump_split_data(p_hwfn, 27637b6859fbSMintz, Yuval p_ptt, 2764c965db44STomer Tayar curr_input_regs_arr, 2765c965db44STomer Tayar dump_buf + offset, 27667b6859fbSMintz, Yuval dump, 27677b6859fbSMintz, Yuval block_enable, 27687b6859fbSMintz, Yuval "pf", 27697b6859fbSMintz, Yuval pf_id, 2770be086e7cSMintz, Yuval param_name, 2771be086e7cSMintz, Yuval param_val); 2772be086e7cSMintz, Yuval } 2773be086e7cSMintz, Yuval break; 27747b6859fbSMintz, Yuval 2775be086e7cSMintz, Yuval case SPLIT_TYPE_VF: 27767b6859fbSMintz, Yuval for (vf_id = 0; vf_id < chip_platform->num_vfs; 2777be086e7cSMintz, Yuval vf_id++) { 2778be086e7cSMintz, Yuval u8 vfvalid_shift = 2779be086e7cSMintz, Yuval PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT; 2780be086e7cSMintz, Yuval u8 vfid_shift = 2781be086e7cSMintz, Yuval PXP_PRETEND_CONCRETE_FID_VFID_SHIFT; 2782be086e7cSMintz, Yuval 2783be086e7cSMintz, Yuval if (dump) { 2784be086e7cSMintz, Yuval fid = BIT(vfvalid_shift) | 2785be086e7cSMintz, Yuval (vf_id << vfid_shift); 2786be086e7cSMintz, Yuval qed_fid_pretend(p_hwfn, p_ptt, fid); 2787be086e7cSMintz, Yuval } 2788be086e7cSMintz, Yuval 2789be086e7cSMintz, Yuval offset += 2790be086e7cSMintz, Yuval qed_grc_dump_split_data(p_hwfn, p_ptt, 2791be086e7cSMintz, Yuval curr_input_regs_arr, 2792be086e7cSMintz, Yuval dump_buf + offset, 2793be086e7cSMintz, Yuval dump, block_enable, 2794be086e7cSMintz, Yuval "vf", vf_id, 2795be086e7cSMintz, Yuval param_name, 2796c965db44STomer Tayar param_val); 2797c965db44STomer Tayar } 2798c965db44STomer Tayar break; 27997b6859fbSMintz, Yuval 2800c965db44STomer Tayar default: 2801c965db44STomer Tayar break; 2802c965db44STomer Tayar } 2803c965db44STomer Tayar 2804c965db44STomer Tayar input_offset += split_data_size; 2805c965db44STomer Tayar } 2806c965db44STomer Tayar 2807c965db44STomer Tayar /* Pretend to original PF */ 2808be086e7cSMintz, Yuval if (dump) { 2809be086e7cSMintz, Yuval fid = p_hwfn->rel_pf_id << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT; 2810be086e7cSMintz, Yuval qed_fid_pretend(p_hwfn, p_ptt, fid); 2811be086e7cSMintz, Yuval } 2812be086e7cSMintz, Yuval 2813c965db44STomer Tayar return offset; 2814c965db44STomer Tayar } 2815c965db44STomer Tayar 2816c965db44STomer Tayar /* Dump reset registers. Returns the dumped size in dwords. */ 2817c965db44STomer Tayar static u32 qed_grc_dump_reset_regs(struct qed_hwfn *p_hwfn, 2818c965db44STomer Tayar struct qed_ptt *p_ptt, 2819c965db44STomer Tayar u32 *dump_buf, bool dump) 2820c965db44STomer Tayar { 2821c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2822c965db44STomer Tayar u32 i, offset = 0, num_regs = 0; 2823c965db44STomer Tayar 2824c965db44STomer Tayar /* Calculate header size */ 2825c965db44STomer Tayar offset += qed_grc_dump_regs_hdr(dump_buf, 2826c965db44STomer Tayar false, 0, "eng", -1, NULL, NULL); 2827c965db44STomer Tayar 2828c965db44STomer Tayar /* Write reset registers */ 2829c965db44STomer Tayar for (i = 0; i < MAX_DBG_RESET_REGS; i++) { 28307b6859fbSMintz, Yuval if (!s_reset_regs_defs[i].exists[dev_data->chip_id]) 28317b6859fbSMintz, Yuval continue; 2832be086e7cSMintz, Yuval 2833c965db44STomer Tayar offset += qed_grc_dump_reg_entry(p_hwfn, 2834c965db44STomer Tayar p_ptt, 2835c965db44STomer Tayar dump_buf + offset, 2836c965db44STomer Tayar dump, 28377b6859fbSMintz, Yuval BYTES_TO_DWORDS 28387b6859fbSMintz, Yuval (s_reset_regs_defs[i].addr), 1, 28397b6859fbSMintz, Yuval false); 2840c965db44STomer Tayar num_regs++; 2841c965db44STomer Tayar } 2842c965db44STomer Tayar 2843c965db44STomer Tayar /* Write header */ 2844c965db44STomer Tayar if (dump) 2845c965db44STomer Tayar qed_grc_dump_regs_hdr(dump_buf, 2846c965db44STomer Tayar true, num_regs, "eng", -1, NULL, NULL); 28477b6859fbSMintz, Yuval 2848c965db44STomer Tayar return offset; 2849c965db44STomer Tayar } 2850c965db44STomer Tayar 28517b6859fbSMintz, Yuval /* Dump registers that are modified during GRC Dump and therefore must be 28527b6859fbSMintz, Yuval * dumped first. Returns the dumped size in dwords. 2853c965db44STomer Tayar */ 2854c965db44STomer Tayar static u32 qed_grc_dump_modified_regs(struct qed_hwfn *p_hwfn, 2855c965db44STomer Tayar struct qed_ptt *p_ptt, 2856c965db44STomer Tayar u32 *dump_buf, bool dump) 2857c965db44STomer Tayar { 2858c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 28597b6859fbSMintz, Yuval u32 block_id, offset = 0, num_reg_entries = 0; 28607b6859fbSMintz, Yuval const struct dbg_attn_reg *attn_reg_arr; 2861c965db44STomer Tayar u8 storm_id, reg_idx, num_attn_regs; 2862c965db44STomer Tayar 2863c965db44STomer Tayar /* Calculate header size */ 2864c965db44STomer Tayar offset += qed_grc_dump_regs_hdr(dump_buf, 2865c965db44STomer Tayar false, 0, "eng", -1, NULL, NULL); 2866c965db44STomer Tayar 2867c965db44STomer Tayar /* Write parity registers */ 2868c965db44STomer Tayar for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) { 2869c965db44STomer Tayar if (dev_data->block_in_reset[block_id] && dump) 2870c965db44STomer Tayar continue; 2871c965db44STomer Tayar 2872c965db44STomer Tayar attn_reg_arr = qed_get_block_attn_regs((enum block_id)block_id, 2873c965db44STomer Tayar ATTN_TYPE_PARITY, 2874c965db44STomer Tayar &num_attn_regs); 28757b6859fbSMintz, Yuval 2876c965db44STomer Tayar for (reg_idx = 0; reg_idx < num_attn_regs; reg_idx++) { 2877c965db44STomer Tayar const struct dbg_attn_reg *reg_data = 2878c965db44STomer Tayar &attn_reg_arr[reg_idx]; 2879c965db44STomer Tayar u16 modes_buf_offset; 2880c965db44STomer Tayar bool eval_mode; 2881be086e7cSMintz, Yuval u32 addr; 2882c965db44STomer Tayar 2883c965db44STomer Tayar /* Check mode */ 2884c965db44STomer Tayar eval_mode = GET_FIELD(reg_data->mode.data, 2885c965db44STomer Tayar DBG_MODE_HDR_EVAL_MODE) > 0; 2886c965db44STomer Tayar modes_buf_offset = 2887c965db44STomer Tayar GET_FIELD(reg_data->mode.data, 2888c965db44STomer Tayar DBG_MODE_HDR_MODES_BUF_OFFSET); 28897b6859fbSMintz, Yuval if (eval_mode && 28907b6859fbSMintz, Yuval !qed_is_mode_match(p_hwfn, &modes_buf_offset)) 28917b6859fbSMintz, Yuval continue; 28927b6859fbSMintz, Yuval 28937b6859fbSMintz, Yuval /* Mode match: read & dump registers */ 2894be086e7cSMintz, Yuval addr = reg_data->mask_address; 28957b6859fbSMintz, Yuval offset += qed_grc_dump_reg_entry(p_hwfn, 2896c965db44STomer Tayar p_ptt, 2897c965db44STomer Tayar dump_buf + offset, 2898c965db44STomer Tayar dump, 2899be086e7cSMintz, Yuval addr, 29007b6859fbSMintz, Yuval 1, false); 2901be086e7cSMintz, Yuval addr = GET_FIELD(reg_data->data, 2902be086e7cSMintz, Yuval DBG_ATTN_REG_STS_ADDRESS); 29037b6859fbSMintz, Yuval offset += qed_grc_dump_reg_entry(p_hwfn, 2904c965db44STomer Tayar p_ptt, 2905c965db44STomer Tayar dump_buf + offset, 2906c965db44STomer Tayar dump, 2907be086e7cSMintz, Yuval addr, 29087b6859fbSMintz, Yuval 1, false); 2909c965db44STomer Tayar num_reg_entries += 2; 2910c965db44STomer Tayar } 2911c965db44STomer Tayar } 2912c965db44STomer Tayar 29137b6859fbSMintz, Yuval /* Write Storm stall status registers */ 2914c965db44STomer Tayar for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 29157b6859fbSMintz, Yuval struct storm_defs *storm = &s_storm_defs[storm_id]; 2916be086e7cSMintz, Yuval u32 addr; 2917be086e7cSMintz, Yuval 29187b6859fbSMintz, Yuval if (dev_data->block_in_reset[storm->block_id] && dump) 2919c965db44STomer Tayar continue; 2920c965db44STomer Tayar 2921be086e7cSMintz, Yuval addr = 2922be086e7cSMintz, Yuval BYTES_TO_DWORDS(s_storm_defs[storm_id].sem_fast_mem_addr + 2923be086e7cSMintz, Yuval SEM_FAST_REG_STALLED); 2924c965db44STomer Tayar offset += qed_grc_dump_reg_entry(p_hwfn, 2925c965db44STomer Tayar p_ptt, 2926c965db44STomer Tayar dump_buf + offset, 2927c965db44STomer Tayar dump, 2928be086e7cSMintz, Yuval addr, 29297b6859fbSMintz, Yuval 1, 29307b6859fbSMintz, Yuval false); 2931c965db44STomer Tayar num_reg_entries++; 2932c965db44STomer Tayar } 2933c965db44STomer Tayar 2934c965db44STomer Tayar /* Write header */ 2935c965db44STomer Tayar if (dump) 2936c965db44STomer Tayar qed_grc_dump_regs_hdr(dump_buf, 2937c965db44STomer Tayar true, 2938c965db44STomer Tayar num_reg_entries, "eng", -1, NULL, NULL); 29397b6859fbSMintz, Yuval 2940c965db44STomer Tayar return offset; 2941c965db44STomer Tayar } 2942c965db44STomer Tayar 2943be086e7cSMintz, Yuval /* Dumps registers that can't be represented in the debug arrays */ 2944be086e7cSMintz, Yuval static u32 qed_grc_dump_special_regs(struct qed_hwfn *p_hwfn, 2945be086e7cSMintz, Yuval struct qed_ptt *p_ptt, 2946be086e7cSMintz, Yuval u32 *dump_buf, bool dump) 2947be086e7cSMintz, Yuval { 2948be086e7cSMintz, Yuval u32 offset = 0, addr; 2949be086e7cSMintz, Yuval 2950be086e7cSMintz, Yuval offset += qed_grc_dump_regs_hdr(dump_buf, 2951be086e7cSMintz, Yuval dump, 2, "eng", -1, NULL, NULL); 2952be086e7cSMintz, Yuval 2953be086e7cSMintz, Yuval /* Dump R/TDIF_REG_DEBUG_ERROR_INFO_SIZE (every 8'th register should be 2954be086e7cSMintz, Yuval * skipped). 2955be086e7cSMintz, Yuval */ 2956be086e7cSMintz, Yuval addr = BYTES_TO_DWORDS(RDIF_REG_DEBUG_ERROR_INFO); 2957be086e7cSMintz, Yuval offset += qed_grc_dump_reg_entry_skip(p_hwfn, 2958be086e7cSMintz, Yuval p_ptt, 2959be086e7cSMintz, Yuval dump_buf + offset, 2960be086e7cSMintz, Yuval dump, 2961be086e7cSMintz, Yuval addr, 2962be086e7cSMintz, Yuval RDIF_REG_DEBUG_ERROR_INFO_SIZE, 2963be086e7cSMintz, Yuval 7, 2964be086e7cSMintz, Yuval 1); 2965be086e7cSMintz, Yuval addr = BYTES_TO_DWORDS(TDIF_REG_DEBUG_ERROR_INFO); 2966be086e7cSMintz, Yuval offset += 2967be086e7cSMintz, Yuval qed_grc_dump_reg_entry_skip(p_hwfn, 2968be086e7cSMintz, Yuval p_ptt, 2969be086e7cSMintz, Yuval dump_buf + offset, 2970be086e7cSMintz, Yuval dump, 2971be086e7cSMintz, Yuval addr, 2972be086e7cSMintz, Yuval TDIF_REG_DEBUG_ERROR_INFO_SIZE, 2973be086e7cSMintz, Yuval 7, 2974be086e7cSMintz, Yuval 1); 2975be086e7cSMintz, Yuval 2976be086e7cSMintz, Yuval return offset; 2977be086e7cSMintz, Yuval } 2978be086e7cSMintz, Yuval 29797b6859fbSMintz, Yuval /* Dumps a GRC memory header (section and params). Returns the dumped size in 29807b6859fbSMintz, Yuval * dwords. The following parameters are dumped: 29817b6859fbSMintz, Yuval * - name: dumped only if it's not NULL. 29827b6859fbSMintz, Yuval * - addr: in dwords, dumped only if name is NULL. 29837b6859fbSMintz, Yuval * - len: in dwords, always dumped. 29847b6859fbSMintz, Yuval * - width: dumped if it's not zero. 29857b6859fbSMintz, Yuval * - packed: dumped only if it's not false. 29867b6859fbSMintz, Yuval * - mem_group: always dumped. 29877b6859fbSMintz, Yuval * - is_storm: true only if the memory is related to a Storm. 29887b6859fbSMintz, Yuval * - storm_letter: valid only if is_storm is true. 29897b6859fbSMintz, Yuval * 2990c965db44STomer Tayar */ 2991c965db44STomer Tayar static u32 qed_grc_dump_mem_hdr(struct qed_hwfn *p_hwfn, 2992c965db44STomer Tayar u32 *dump_buf, 2993c965db44STomer Tayar bool dump, 2994c965db44STomer Tayar const char *name, 2995be086e7cSMintz, Yuval u32 addr, 2996be086e7cSMintz, Yuval u32 len, 2997c965db44STomer Tayar u32 bit_width, 2998c965db44STomer Tayar bool packed, 2999c965db44STomer Tayar const char *mem_group, 3000c965db44STomer Tayar bool is_storm, char storm_letter) 3001c965db44STomer Tayar { 3002c965db44STomer Tayar u8 num_params = 3; 3003c965db44STomer Tayar u32 offset = 0; 3004c965db44STomer Tayar char buf[64]; 3005c965db44STomer Tayar 3006be086e7cSMintz, Yuval if (!len) 3007c965db44STomer Tayar DP_NOTICE(p_hwfn, 3008c965db44STomer Tayar "Unexpected GRC Dump error: dumped memory size must be non-zero\n"); 30097b6859fbSMintz, Yuval 3010c965db44STomer Tayar if (bit_width) 3011c965db44STomer Tayar num_params++; 3012c965db44STomer Tayar if (packed) 3013c965db44STomer Tayar num_params++; 3014c965db44STomer Tayar 3015c965db44STomer Tayar /* Dump section header */ 3016c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, 3017c965db44STomer Tayar dump, "grc_mem", num_params); 30187b6859fbSMintz, Yuval 3019c965db44STomer Tayar if (name) { 3020c965db44STomer Tayar /* Dump name */ 3021c965db44STomer Tayar if (is_storm) { 3022c965db44STomer Tayar strcpy(buf, "?STORM_"); 3023c965db44STomer Tayar buf[0] = storm_letter; 3024c965db44STomer Tayar strcpy(buf + strlen(buf), name); 3025c965db44STomer Tayar } else { 3026c965db44STomer Tayar strcpy(buf, name); 3027c965db44STomer Tayar } 3028c965db44STomer Tayar 3029c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 3030c965db44STomer Tayar dump, "name", buf); 3031c965db44STomer Tayar } else { 3032c965db44STomer Tayar /* Dump address */ 30337b6859fbSMintz, Yuval u32 addr_in_bytes = DWORDS_TO_BYTES(addr); 30347b6859fbSMintz, Yuval 3035c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 30367b6859fbSMintz, Yuval dump, "addr", addr_in_bytes); 3037c965db44STomer Tayar } 3038c965db44STomer Tayar 3039c965db44STomer Tayar /* Dump len */ 3040be086e7cSMintz, Yuval offset += qed_dump_num_param(dump_buf + offset, dump, "len", len); 3041c965db44STomer Tayar 3042c965db44STomer Tayar /* Dump bit width */ 3043c965db44STomer Tayar if (bit_width) 3044c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 3045c965db44STomer Tayar dump, "width", bit_width); 3046c965db44STomer Tayar 3047c965db44STomer Tayar /* Dump packed */ 3048c965db44STomer Tayar if (packed) 3049c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 3050c965db44STomer Tayar dump, "packed", 1); 3051c965db44STomer Tayar 3052c965db44STomer Tayar /* Dump reg type */ 3053c965db44STomer Tayar if (is_storm) { 3054c965db44STomer Tayar strcpy(buf, "?STORM_"); 3055c965db44STomer Tayar buf[0] = storm_letter; 3056c965db44STomer Tayar strcpy(buf + strlen(buf), mem_group); 3057c965db44STomer Tayar } else { 3058c965db44STomer Tayar strcpy(buf, mem_group); 3059c965db44STomer Tayar } 3060c965db44STomer Tayar 3061c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, dump, "type", buf); 30627b6859fbSMintz, Yuval 3063c965db44STomer Tayar return offset; 3064c965db44STomer Tayar } 3065c965db44STomer Tayar 3066c965db44STomer Tayar /* Dumps a single GRC memory. If name is NULL, the memory is stored by address. 3067c965db44STomer Tayar * Returns the dumped size in dwords. 30687b6859fbSMintz, Yuval * The addr and len arguments are specified in dwords. 3069c965db44STomer Tayar */ 3070c965db44STomer Tayar static u32 qed_grc_dump_mem(struct qed_hwfn *p_hwfn, 3071c965db44STomer Tayar struct qed_ptt *p_ptt, 3072c965db44STomer Tayar u32 *dump_buf, 3073c965db44STomer Tayar bool dump, 3074c965db44STomer Tayar const char *name, 3075be086e7cSMintz, Yuval u32 addr, 3076be086e7cSMintz, Yuval u32 len, 30777b6859fbSMintz, Yuval bool wide_bus, 3078c965db44STomer Tayar u32 bit_width, 3079c965db44STomer Tayar bool packed, 3080c965db44STomer Tayar const char *mem_group, 3081c965db44STomer Tayar bool is_storm, char storm_letter) 3082c965db44STomer Tayar { 3083c965db44STomer Tayar u32 offset = 0; 3084c965db44STomer Tayar 3085c965db44STomer Tayar offset += qed_grc_dump_mem_hdr(p_hwfn, 3086c965db44STomer Tayar dump_buf + offset, 3087c965db44STomer Tayar dump, 3088c965db44STomer Tayar name, 3089be086e7cSMintz, Yuval addr, 3090be086e7cSMintz, Yuval len, 3091c965db44STomer Tayar bit_width, 3092c965db44STomer Tayar packed, 3093c965db44STomer Tayar mem_group, is_storm, storm_letter); 3094be086e7cSMintz, Yuval offset += qed_grc_dump_addr_range(p_hwfn, 3095be086e7cSMintz, Yuval p_ptt, 30967b6859fbSMintz, Yuval dump_buf + offset, 30977b6859fbSMintz, Yuval dump, addr, len, wide_bus); 30987b6859fbSMintz, Yuval 3099c965db44STomer Tayar return offset; 3100c965db44STomer Tayar } 3101c965db44STomer Tayar 3102c965db44STomer Tayar /* Dumps GRC memories entries. Returns the dumped size in dwords. */ 3103c965db44STomer Tayar static u32 qed_grc_dump_mem_entries(struct qed_hwfn *p_hwfn, 3104c965db44STomer Tayar struct qed_ptt *p_ptt, 3105c965db44STomer Tayar struct dbg_array input_mems_arr, 3106c965db44STomer Tayar u32 *dump_buf, bool dump) 3107c965db44STomer Tayar { 3108c965db44STomer Tayar u32 i, offset = 0, input_offset = 0; 3109c965db44STomer Tayar bool mode_match = true; 3110c965db44STomer Tayar 3111c965db44STomer Tayar while (input_offset < input_mems_arr.size_in_dwords) { 3112c965db44STomer Tayar const struct dbg_dump_cond_hdr *cond_hdr; 31137b6859fbSMintz, Yuval u16 modes_buf_offset; 3114c965db44STomer Tayar u32 num_entries; 3115c965db44STomer Tayar bool eval_mode; 3116c965db44STomer Tayar 3117c965db44STomer Tayar cond_hdr = (const struct dbg_dump_cond_hdr *) 3118c965db44STomer Tayar &input_mems_arr.ptr[input_offset++]; 31197b6859fbSMintz, Yuval num_entries = cond_hdr->data_size / MEM_DUMP_ENTRY_SIZE_DWORDS; 3120c965db44STomer Tayar 3121c965db44STomer Tayar /* Check required mode */ 31227b6859fbSMintz, Yuval eval_mode = GET_FIELD(cond_hdr->mode.data, 31237b6859fbSMintz, Yuval DBG_MODE_HDR_EVAL_MODE) > 0; 3124c965db44STomer Tayar if (eval_mode) { 31257b6859fbSMintz, Yuval modes_buf_offset = 3126c965db44STomer Tayar GET_FIELD(cond_hdr->mode.data, 3127c965db44STomer Tayar DBG_MODE_HDR_MODES_BUF_OFFSET); 3128c965db44STomer Tayar mode_match = qed_is_mode_match(p_hwfn, 3129c965db44STomer Tayar &modes_buf_offset); 3130c965db44STomer Tayar } 3131c965db44STomer Tayar 3132c965db44STomer Tayar if (!mode_match) { 3133c965db44STomer Tayar input_offset += cond_hdr->data_size; 3134c965db44STomer Tayar continue; 3135c965db44STomer Tayar } 3136c965db44STomer Tayar 3137c965db44STomer Tayar for (i = 0; i < num_entries; 3138c965db44STomer Tayar i++, input_offset += MEM_DUMP_ENTRY_SIZE_DWORDS) { 3139c965db44STomer Tayar const struct dbg_dump_mem *mem = 3140c965db44STomer Tayar (const struct dbg_dump_mem *) 3141c965db44STomer Tayar &input_mems_arr.ptr[input_offset]; 31427b6859fbSMintz, Yuval u8 mem_group_id = GET_FIELD(mem->dword0, 3143c965db44STomer Tayar DBG_DUMP_MEM_MEM_GROUP_ID); 31447b6859fbSMintz, Yuval bool is_storm = false, mem_wide_bus; 31457b6859fbSMintz, Yuval enum dbg_grc_params grc_param; 31467b6859fbSMintz, Yuval char storm_letter = 'a'; 31477b6859fbSMintz, Yuval enum block_id block_id; 31487b6859fbSMintz, Yuval u32 mem_addr, mem_len; 31497b6859fbSMintz, Yuval 3150c965db44STomer Tayar if (mem_group_id >= MEM_GROUPS_NUM) { 3151c965db44STomer Tayar DP_NOTICE(p_hwfn, "Invalid mem_group_id\n"); 3152c965db44STomer Tayar return 0; 3153c965db44STomer Tayar } 3154c965db44STomer Tayar 31557b6859fbSMintz, Yuval block_id = (enum block_id)cond_hdr->block_id; 31567b6859fbSMintz, Yuval if (!qed_grc_is_mem_included(p_hwfn, 31577b6859fbSMintz, Yuval block_id, 31587b6859fbSMintz, Yuval mem_group_id)) 31597b6859fbSMintz, Yuval continue; 31607b6859fbSMintz, Yuval 31617b6859fbSMintz, Yuval mem_addr = GET_FIELD(mem->dword0, DBG_DUMP_MEM_ADDRESS); 31627b6859fbSMintz, Yuval mem_len = GET_FIELD(mem->dword1, DBG_DUMP_MEM_LENGTH); 31637b6859fbSMintz, Yuval mem_wide_bus = GET_FIELD(mem->dword1, 31647b6859fbSMintz, Yuval DBG_DUMP_MEM_WIDE_BUS); 3165c965db44STomer Tayar 3166c965db44STomer Tayar /* Update memory length for CCFC/TCFC memories 3167c965db44STomer Tayar * according to number of LCIDs/LTIDs. 3168c965db44STomer Tayar */ 3169be086e7cSMintz, Yuval if (mem_group_id == MEM_GROUP_CONN_CFC_MEM) { 31707b6859fbSMintz, Yuval if (mem_len % MAX_LCIDS) { 3171be086e7cSMintz, Yuval DP_NOTICE(p_hwfn, 3172be086e7cSMintz, Yuval "Invalid CCFC connection memory size\n"); 3173be086e7cSMintz, Yuval return 0; 3174be086e7cSMintz, Yuval } 3175be086e7cSMintz, Yuval 3176be086e7cSMintz, Yuval grc_param = DBG_GRC_PARAM_NUM_LCIDS; 31777b6859fbSMintz, Yuval mem_len = qed_grc_get_param(p_hwfn, grc_param) * 3178be086e7cSMintz, Yuval (mem_len / MAX_LCIDS); 31797b6859fbSMintz, Yuval } else if (mem_group_id == MEM_GROUP_TASK_CFC_MEM) { 31807b6859fbSMintz, Yuval if (mem_len % MAX_LTIDS) { 3181be086e7cSMintz, Yuval DP_NOTICE(p_hwfn, 3182be086e7cSMintz, Yuval "Invalid TCFC task memory size\n"); 3183be086e7cSMintz, Yuval return 0; 3184be086e7cSMintz, Yuval } 3185be086e7cSMintz, Yuval 3186be086e7cSMintz, Yuval grc_param = DBG_GRC_PARAM_NUM_LTIDS; 31877b6859fbSMintz, Yuval mem_len = qed_grc_get_param(p_hwfn, grc_param) * 3188be086e7cSMintz, Yuval (mem_len / MAX_LTIDS); 3189be086e7cSMintz, Yuval } 3190c965db44STomer Tayar 31917b6859fbSMintz, Yuval /* If memory is associated with Storm, update Storm 31927b6859fbSMintz, Yuval * details. 3193c965db44STomer Tayar */ 31947b6859fbSMintz, Yuval if (s_block_defs 31957b6859fbSMintz, Yuval [cond_hdr->block_id]->associated_to_storm) { 3196c965db44STomer Tayar is_storm = true; 3197c965db44STomer Tayar storm_letter = 31987b6859fbSMintz, Yuval s_storm_defs[s_block_defs 31997b6859fbSMintz, Yuval [cond_hdr->block_id]-> 3200c965db44STomer Tayar storm_id].letter; 3201c965db44STomer Tayar } 3202c965db44STomer Tayar 3203c965db44STomer Tayar /* Dump memory */ 32047b6859fbSMintz, Yuval offset += qed_grc_dump_mem(p_hwfn, 32057b6859fbSMintz, Yuval p_ptt, 32067b6859fbSMintz, Yuval dump_buf + offset, 32077b6859fbSMintz, Yuval dump, 32087b6859fbSMintz, Yuval NULL, 32097b6859fbSMintz, Yuval mem_addr, 32107b6859fbSMintz, Yuval mem_len, 32117b6859fbSMintz, Yuval mem_wide_bus, 32127b6859fbSMintz, Yuval 0, 3213c965db44STomer Tayar false, 3214c965db44STomer Tayar s_mem_group_names[mem_group_id], 32157b6859fbSMintz, Yuval is_storm, 32167b6859fbSMintz, Yuval storm_letter); 3217c965db44STomer Tayar } 3218c965db44STomer Tayar } 3219c965db44STomer Tayar 3220c965db44STomer Tayar return offset; 3221c965db44STomer Tayar } 3222c965db44STomer Tayar 3223c965db44STomer Tayar /* Dumps GRC memories according to the input array dump_mem. 3224c965db44STomer Tayar * Returns the dumped size in dwords. 3225c965db44STomer Tayar */ 3226c965db44STomer Tayar static u32 qed_grc_dump_memories(struct qed_hwfn *p_hwfn, 3227c965db44STomer Tayar struct qed_ptt *p_ptt, 3228c965db44STomer Tayar u32 *dump_buf, bool dump) 3229c965db44STomer Tayar { 3230c965db44STomer Tayar u32 offset = 0, input_offset = 0; 3231c965db44STomer Tayar 3232c965db44STomer Tayar while (input_offset < 3233c965db44STomer Tayar s_dbg_arrays[BIN_BUF_DBG_DUMP_MEM].size_in_dwords) { 32347b6859fbSMintz, Yuval const struct dbg_dump_split_hdr *split_hdr; 32357b6859fbSMintz, Yuval struct dbg_array curr_input_mems_arr; 32367b6859fbSMintz, Yuval u32 split_data_size; 32377b6859fbSMintz, Yuval u8 split_type_id; 32387b6859fbSMintz, Yuval 32397b6859fbSMintz, Yuval split_hdr = (const struct dbg_dump_split_hdr *) 3240c965db44STomer Tayar &s_dbg_arrays[BIN_BUF_DBG_DUMP_MEM].ptr[input_offset++]; 32417b6859fbSMintz, Yuval split_type_id = 32427b6859fbSMintz, Yuval GET_FIELD(split_hdr->hdr, 3243c965db44STomer Tayar DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID); 32447b6859fbSMintz, Yuval split_data_size = 32457b6859fbSMintz, Yuval GET_FIELD(split_hdr->hdr, 3246c965db44STomer Tayar DBG_DUMP_SPLIT_HDR_DATA_SIZE); 32477b6859fbSMintz, Yuval curr_input_mems_arr.ptr = 32487b6859fbSMintz, Yuval &s_dbg_arrays[BIN_BUF_DBG_DUMP_MEM].ptr[input_offset]; 32497b6859fbSMintz, Yuval curr_input_mems_arr.size_in_dwords = split_data_size; 3250c965db44STomer Tayar 3251c965db44STomer Tayar switch (split_type_id) { 3252c965db44STomer Tayar case SPLIT_TYPE_NONE: 3253c965db44STomer Tayar offset += qed_grc_dump_mem_entries(p_hwfn, 3254c965db44STomer Tayar p_ptt, 3255c965db44STomer Tayar curr_input_mems_arr, 3256c965db44STomer Tayar dump_buf + offset, 3257c965db44STomer Tayar dump); 3258c965db44STomer Tayar break; 32597b6859fbSMintz, Yuval 3260c965db44STomer Tayar default: 3261c965db44STomer Tayar DP_NOTICE(p_hwfn, 3262c965db44STomer Tayar "Dumping split memories is currently not supported\n"); 3263c965db44STomer Tayar break; 3264c965db44STomer Tayar } 3265c965db44STomer Tayar 3266c965db44STomer Tayar input_offset += split_data_size; 3267c965db44STomer Tayar } 3268c965db44STomer Tayar 3269c965db44STomer Tayar return offset; 3270c965db44STomer Tayar } 3271c965db44STomer Tayar 3272c965db44STomer Tayar /* Dumps GRC context data for the specified Storm. 3273c965db44STomer Tayar * Returns the dumped size in dwords. 32747b6859fbSMintz, Yuval * The lid_size argument is specified in quad-regs. 3275c965db44STomer Tayar */ 3276c965db44STomer Tayar static u32 qed_grc_dump_ctx_data(struct qed_hwfn *p_hwfn, 3277c965db44STomer Tayar struct qed_ptt *p_ptt, 3278c965db44STomer Tayar u32 *dump_buf, 3279c965db44STomer Tayar bool dump, 3280c965db44STomer Tayar const char *name, 3281c965db44STomer Tayar u32 num_lids, 3282c965db44STomer Tayar u32 lid_size, 3283c965db44STomer Tayar u32 rd_reg_addr, 3284c965db44STomer Tayar u8 storm_id) 3285c965db44STomer Tayar { 32867b6859fbSMintz, Yuval struct storm_defs *storm = &s_storm_defs[storm_id]; 32877b6859fbSMintz, Yuval u32 i, lid, total_size, offset = 0; 3288c965db44STomer Tayar 3289c965db44STomer Tayar if (!lid_size) 3290c965db44STomer Tayar return 0; 32917b6859fbSMintz, Yuval 3292c965db44STomer Tayar lid_size *= BYTES_IN_DWORD; 3293c965db44STomer Tayar total_size = num_lids * lid_size; 32947b6859fbSMintz, Yuval 3295c965db44STomer Tayar offset += qed_grc_dump_mem_hdr(p_hwfn, 3296c965db44STomer Tayar dump_buf + offset, 3297c965db44STomer Tayar dump, 3298c965db44STomer Tayar name, 3299c965db44STomer Tayar 0, 3300c965db44STomer Tayar total_size, 3301c965db44STomer Tayar lid_size * 32, 33027b6859fbSMintz, Yuval false, name, true, storm->letter); 33037b6859fbSMintz, Yuval 33047b6859fbSMintz, Yuval if (!dump) 33057b6859fbSMintz, Yuval return offset + total_size; 3306c965db44STomer Tayar 3307c965db44STomer Tayar /* Dump context data */ 3308c965db44STomer Tayar for (lid = 0; lid < num_lids; lid++) { 3309c965db44STomer Tayar for (i = 0; i < lid_size; i++, offset++) { 3310c965db44STomer Tayar qed_wr(p_hwfn, 33117b6859fbSMintz, Yuval p_ptt, storm->cm_ctx_wr_addr, (i << 9) | lid); 3312c965db44STomer Tayar *(dump_buf + offset) = qed_rd(p_hwfn, 33137b6859fbSMintz, Yuval p_ptt, rd_reg_addr); 3314c965db44STomer Tayar } 3315c965db44STomer Tayar } 3316c965db44STomer Tayar 3317c965db44STomer Tayar return offset; 3318c965db44STomer Tayar } 3319c965db44STomer Tayar 3320c965db44STomer Tayar /* Dumps GRC contexts. Returns the dumped size in dwords. */ 3321c965db44STomer Tayar static u32 qed_grc_dump_ctx(struct qed_hwfn *p_hwfn, 3322c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *dump_buf, bool dump) 3323c965db44STomer Tayar { 33247b6859fbSMintz, Yuval enum dbg_grc_params grc_param; 3325c965db44STomer Tayar u32 offset = 0; 3326c965db44STomer Tayar u8 storm_id; 3327c965db44STomer Tayar 3328c965db44STomer Tayar for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 33297b6859fbSMintz, Yuval struct storm_defs *storm = &s_storm_defs[storm_id]; 33307b6859fbSMintz, Yuval 3331c965db44STomer Tayar if (!qed_grc_is_storm_included(p_hwfn, 3332c965db44STomer Tayar (enum dbg_storms)storm_id)) 3333c965db44STomer Tayar continue; 3334c965db44STomer Tayar 3335c965db44STomer Tayar /* Dump Conn AG context size */ 33367b6859fbSMintz, Yuval grc_param = DBG_GRC_PARAM_NUM_LCIDS; 3337c965db44STomer Tayar offset += 3338c965db44STomer Tayar qed_grc_dump_ctx_data(p_hwfn, 3339c965db44STomer Tayar p_ptt, 3340c965db44STomer Tayar dump_buf + offset, 3341c965db44STomer Tayar dump, 3342c965db44STomer Tayar "CONN_AG_CTX", 3343c965db44STomer Tayar qed_grc_get_param(p_hwfn, 33447b6859fbSMintz, Yuval grc_param), 33457b6859fbSMintz, Yuval storm->cm_conn_ag_ctx_lid_size, 33467b6859fbSMintz, Yuval storm->cm_conn_ag_ctx_rd_addr, 3347c965db44STomer Tayar storm_id); 3348c965db44STomer Tayar 3349c965db44STomer Tayar /* Dump Conn ST context size */ 33507b6859fbSMintz, Yuval grc_param = DBG_GRC_PARAM_NUM_LCIDS; 3351c965db44STomer Tayar offset += 3352c965db44STomer Tayar qed_grc_dump_ctx_data(p_hwfn, 3353c965db44STomer Tayar p_ptt, 3354c965db44STomer Tayar dump_buf + offset, 3355c965db44STomer Tayar dump, 3356c965db44STomer Tayar "CONN_ST_CTX", 3357c965db44STomer Tayar qed_grc_get_param(p_hwfn, 33587b6859fbSMintz, Yuval grc_param), 33597b6859fbSMintz, Yuval storm->cm_conn_st_ctx_lid_size, 33607b6859fbSMintz, Yuval storm->cm_conn_st_ctx_rd_addr, 3361c965db44STomer Tayar storm_id); 3362c965db44STomer Tayar 3363c965db44STomer Tayar /* Dump Task AG context size */ 33647b6859fbSMintz, Yuval grc_param = DBG_GRC_PARAM_NUM_LTIDS; 3365c965db44STomer Tayar offset += 3366c965db44STomer Tayar qed_grc_dump_ctx_data(p_hwfn, 3367c965db44STomer Tayar p_ptt, 3368c965db44STomer Tayar dump_buf + offset, 3369c965db44STomer Tayar dump, 3370c965db44STomer Tayar "TASK_AG_CTX", 3371c965db44STomer Tayar qed_grc_get_param(p_hwfn, 33727b6859fbSMintz, Yuval grc_param), 33737b6859fbSMintz, Yuval storm->cm_task_ag_ctx_lid_size, 33747b6859fbSMintz, Yuval storm->cm_task_ag_ctx_rd_addr, 3375c965db44STomer Tayar storm_id); 3376c965db44STomer Tayar 3377c965db44STomer Tayar /* Dump Task ST context size */ 33787b6859fbSMintz, Yuval grc_param = DBG_GRC_PARAM_NUM_LTIDS; 3379c965db44STomer Tayar offset += 3380c965db44STomer Tayar qed_grc_dump_ctx_data(p_hwfn, 3381c965db44STomer Tayar p_ptt, 3382c965db44STomer Tayar dump_buf + offset, 3383c965db44STomer Tayar dump, 3384c965db44STomer Tayar "TASK_ST_CTX", 3385c965db44STomer Tayar qed_grc_get_param(p_hwfn, 33867b6859fbSMintz, Yuval grc_param), 33877b6859fbSMintz, Yuval storm->cm_task_st_ctx_lid_size, 33887b6859fbSMintz, Yuval storm->cm_task_st_ctx_rd_addr, 3389c965db44STomer Tayar storm_id); 3390c965db44STomer Tayar } 3391c965db44STomer Tayar 3392c965db44STomer Tayar return offset; 3393c965db44STomer Tayar } 3394c965db44STomer Tayar 3395c965db44STomer Tayar /* Dumps GRC IORs data. Returns the dumped size in dwords. */ 3396c965db44STomer Tayar static u32 qed_grc_dump_iors(struct qed_hwfn *p_hwfn, 3397c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *dump_buf, bool dump) 3398c965db44STomer Tayar { 3399c965db44STomer Tayar char buf[10] = "IOR_SET_?"; 34007b6859fbSMintz, Yuval u32 addr, offset = 0; 3401c965db44STomer Tayar u8 storm_id, set_id; 3402c965db44STomer Tayar 3403c965db44STomer Tayar for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 3404be086e7cSMintz, Yuval struct storm_defs *storm = &s_storm_defs[storm_id]; 3405c965db44STomer Tayar 3406be086e7cSMintz, Yuval if (!qed_grc_is_storm_included(p_hwfn, 3407be086e7cSMintz, Yuval (enum dbg_storms)storm_id)) 3408be086e7cSMintz, Yuval continue; 3409be086e7cSMintz, Yuval 3410be086e7cSMintz, Yuval for (set_id = 0; set_id < NUM_IOR_SETS; set_id++) { 34117b6859fbSMintz, Yuval addr = BYTES_TO_DWORDS(storm->sem_fast_mem_addr + 34127b6859fbSMintz, Yuval SEM_FAST_REG_STORM_REG_FILE) + 34137b6859fbSMintz, Yuval IOR_SET_OFFSET(set_id); 3414c965db44STomer Tayar buf[strlen(buf) - 1] = '0' + set_id; 3415c965db44STomer Tayar offset += qed_grc_dump_mem(p_hwfn, 3416c965db44STomer Tayar p_ptt, 3417c965db44STomer Tayar dump_buf + offset, 3418c965db44STomer Tayar dump, 3419c965db44STomer Tayar buf, 3420c965db44STomer Tayar addr, 3421c965db44STomer Tayar IORS_PER_SET, 34227b6859fbSMintz, Yuval false, 3423c965db44STomer Tayar 32, 3424c965db44STomer Tayar false, 3425c965db44STomer Tayar "ior", 3426c965db44STomer Tayar true, 3427be086e7cSMintz, Yuval storm->letter); 3428c965db44STomer Tayar } 3429c965db44STomer Tayar } 3430c965db44STomer Tayar 3431c965db44STomer Tayar return offset; 3432c965db44STomer Tayar } 3433c965db44STomer Tayar 3434c965db44STomer Tayar /* Dump VFC CAM. Returns the dumped size in dwords. */ 3435c965db44STomer Tayar static u32 qed_grc_dump_vfc_cam(struct qed_hwfn *p_hwfn, 3436c965db44STomer Tayar struct qed_ptt *p_ptt, 3437c965db44STomer Tayar u32 *dump_buf, bool dump, u8 storm_id) 3438c965db44STomer Tayar { 3439c965db44STomer Tayar u32 total_size = VFC_CAM_NUM_ROWS * VFC_CAM_RESP_DWORDS; 34407b6859fbSMintz, Yuval struct storm_defs *storm = &s_storm_defs[storm_id]; 3441c965db44STomer Tayar u32 cam_addr[VFC_CAM_ADDR_DWORDS] = { 0 }; 3442c965db44STomer Tayar u32 cam_cmd[VFC_CAM_CMD_DWORDS] = { 0 }; 34437b6859fbSMintz, Yuval u32 row, i, offset = 0; 3444c965db44STomer Tayar 3445c965db44STomer Tayar offset += qed_grc_dump_mem_hdr(p_hwfn, 3446c965db44STomer Tayar dump_buf + offset, 3447c965db44STomer Tayar dump, 3448c965db44STomer Tayar "vfc_cam", 3449c965db44STomer Tayar 0, 3450c965db44STomer Tayar total_size, 3451c965db44STomer Tayar 256, 34527b6859fbSMintz, Yuval false, "vfc_cam", true, storm->letter); 34537b6859fbSMintz, Yuval 34547b6859fbSMintz, Yuval if (!dump) 34557b6859fbSMintz, Yuval return offset + total_size; 34567b6859fbSMintz, Yuval 3457c965db44STomer Tayar /* Prepare CAM address */ 3458c965db44STomer Tayar SET_VAR_FIELD(cam_addr, VFC_CAM_ADDR, OP, VFC_OPCODE_CAM_RD); 34597b6859fbSMintz, Yuval 3460c965db44STomer Tayar for (row = 0; row < VFC_CAM_NUM_ROWS; 3461c965db44STomer Tayar row++, offset += VFC_CAM_RESP_DWORDS) { 3462c965db44STomer Tayar /* Write VFC CAM command */ 3463c965db44STomer Tayar SET_VAR_FIELD(cam_cmd, VFC_CAM_CMD, ROW, row); 3464c965db44STomer Tayar ARR_REG_WR(p_hwfn, 3465c965db44STomer Tayar p_ptt, 34667b6859fbSMintz, Yuval storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_WR, 3467c965db44STomer Tayar cam_cmd, VFC_CAM_CMD_DWORDS); 3468c965db44STomer Tayar 3469c965db44STomer Tayar /* Write VFC CAM address */ 3470c965db44STomer Tayar ARR_REG_WR(p_hwfn, 3471c965db44STomer Tayar p_ptt, 34727b6859fbSMintz, Yuval storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_ADDR, 3473c965db44STomer Tayar cam_addr, VFC_CAM_ADDR_DWORDS); 3474c965db44STomer Tayar 3475c965db44STomer Tayar /* Read VFC CAM read response */ 3476c965db44STomer Tayar ARR_REG_RD(p_hwfn, 3477c965db44STomer Tayar p_ptt, 34787b6859fbSMintz, Yuval storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_RD, 3479c965db44STomer Tayar dump_buf + offset, VFC_CAM_RESP_DWORDS); 3480c965db44STomer Tayar } 3481c965db44STomer Tayar 3482c965db44STomer Tayar return offset; 3483c965db44STomer Tayar } 3484c965db44STomer Tayar 3485c965db44STomer Tayar /* Dump VFC RAM. Returns the dumped size in dwords. */ 3486c965db44STomer Tayar static u32 qed_grc_dump_vfc_ram(struct qed_hwfn *p_hwfn, 3487c965db44STomer Tayar struct qed_ptt *p_ptt, 3488c965db44STomer Tayar u32 *dump_buf, 3489c965db44STomer Tayar bool dump, 3490c965db44STomer Tayar u8 storm_id, struct vfc_ram_defs *ram_defs) 3491c965db44STomer Tayar { 3492c965db44STomer Tayar u32 total_size = ram_defs->num_rows * VFC_RAM_RESP_DWORDS; 34937b6859fbSMintz, Yuval struct storm_defs *storm = &s_storm_defs[storm_id]; 3494c965db44STomer Tayar u32 ram_addr[VFC_RAM_ADDR_DWORDS] = { 0 }; 3495c965db44STomer Tayar u32 ram_cmd[VFC_RAM_CMD_DWORDS] = { 0 }; 34967b6859fbSMintz, Yuval u32 row, i, offset = 0; 3497c965db44STomer Tayar 3498c965db44STomer Tayar offset += qed_grc_dump_mem_hdr(p_hwfn, 3499c965db44STomer Tayar dump_buf + offset, 3500c965db44STomer Tayar dump, 3501c965db44STomer Tayar ram_defs->mem_name, 3502c965db44STomer Tayar 0, 3503c965db44STomer Tayar total_size, 3504c965db44STomer Tayar 256, 3505c965db44STomer Tayar false, 3506c965db44STomer Tayar ram_defs->type_name, 35077b6859fbSMintz, Yuval true, storm->letter); 3508c965db44STomer Tayar 3509c965db44STomer Tayar /* Prepare RAM address */ 3510c965db44STomer Tayar SET_VAR_FIELD(ram_addr, VFC_RAM_ADDR, OP, VFC_OPCODE_RAM_RD); 3511c965db44STomer Tayar 3512c965db44STomer Tayar if (!dump) 3513c965db44STomer Tayar return offset + total_size; 3514c965db44STomer Tayar 3515c965db44STomer Tayar for (row = ram_defs->base_row; 3516c965db44STomer Tayar row < ram_defs->base_row + ram_defs->num_rows; 3517c965db44STomer Tayar row++, offset += VFC_RAM_RESP_DWORDS) { 3518c965db44STomer Tayar /* Write VFC RAM command */ 3519c965db44STomer Tayar ARR_REG_WR(p_hwfn, 3520c965db44STomer Tayar p_ptt, 35217b6859fbSMintz, Yuval storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_WR, 3522c965db44STomer Tayar ram_cmd, VFC_RAM_CMD_DWORDS); 3523c965db44STomer Tayar 3524c965db44STomer Tayar /* Write VFC RAM address */ 3525c965db44STomer Tayar SET_VAR_FIELD(ram_addr, VFC_RAM_ADDR, ROW, row); 3526c965db44STomer Tayar ARR_REG_WR(p_hwfn, 3527c965db44STomer Tayar p_ptt, 35287b6859fbSMintz, Yuval storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_ADDR, 3529c965db44STomer Tayar ram_addr, VFC_RAM_ADDR_DWORDS); 3530c965db44STomer Tayar 3531c965db44STomer Tayar /* Read VFC RAM read response */ 3532c965db44STomer Tayar ARR_REG_RD(p_hwfn, 3533c965db44STomer Tayar p_ptt, 35347b6859fbSMintz, Yuval storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_RD, 3535c965db44STomer Tayar dump_buf + offset, VFC_RAM_RESP_DWORDS); 3536c965db44STomer Tayar } 3537c965db44STomer Tayar 3538c965db44STomer Tayar return offset; 3539c965db44STomer Tayar } 3540c965db44STomer Tayar 3541c965db44STomer Tayar /* Dumps GRC VFC data. Returns the dumped size in dwords. */ 3542c965db44STomer Tayar static u32 qed_grc_dump_vfc(struct qed_hwfn *p_hwfn, 3543c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *dump_buf, bool dump) 3544c965db44STomer Tayar { 3545c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 3546c965db44STomer Tayar u8 storm_id, i; 3547c965db44STomer Tayar u32 offset = 0; 3548c965db44STomer Tayar 3549c965db44STomer Tayar for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 35507b6859fbSMintz, Yuval if (!qed_grc_is_storm_included(p_hwfn, 35517b6859fbSMintz, Yuval (enum dbg_storms)storm_id) || 35527b6859fbSMintz, Yuval !s_storm_defs[storm_id].has_vfc || 35537b6859fbSMintz, Yuval (storm_id == DBG_PSTORM_ID && dev_data->platform_id != 35547b6859fbSMintz, Yuval PLATFORM_ASIC)) 35557b6859fbSMintz, Yuval continue; 35567b6859fbSMintz, Yuval 3557c965db44STomer Tayar /* Read CAM */ 3558c965db44STomer Tayar offset += qed_grc_dump_vfc_cam(p_hwfn, 3559c965db44STomer Tayar p_ptt, 3560c965db44STomer Tayar dump_buf + offset, 3561c965db44STomer Tayar dump, storm_id); 3562c965db44STomer Tayar 3563c965db44STomer Tayar /* Read RAM */ 3564c965db44STomer Tayar for (i = 0; i < NUM_VFC_RAM_TYPES; i++) 3565c965db44STomer Tayar offset += qed_grc_dump_vfc_ram(p_hwfn, 3566c965db44STomer Tayar p_ptt, 35677b6859fbSMintz, Yuval dump_buf + offset, 3568c965db44STomer Tayar dump, 3569c965db44STomer Tayar storm_id, 35707b6859fbSMintz, Yuval &s_vfc_ram_defs[i]); 3571c965db44STomer Tayar } 3572c965db44STomer Tayar 3573c965db44STomer Tayar return offset; 3574c965db44STomer Tayar } 3575c965db44STomer Tayar 3576c965db44STomer Tayar /* Dumps GRC RSS data. Returns the dumped size in dwords. */ 3577c965db44STomer Tayar static u32 qed_grc_dump_rss(struct qed_hwfn *p_hwfn, 3578c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *dump_buf, bool dump) 3579c965db44STomer Tayar { 3580c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 3581c965db44STomer Tayar u32 offset = 0; 3582c965db44STomer Tayar u8 rss_mem_id; 3583c965db44STomer Tayar 3584c965db44STomer Tayar for (rss_mem_id = 0; rss_mem_id < NUM_RSS_MEM_TYPES; rss_mem_id++) { 3585da090917STomer Tayar u32 rss_addr, num_entries, total_dwords; 35867b6859fbSMintz, Yuval struct rss_mem_defs *rss_defs; 3587da090917STomer Tayar u32 addr, num_dwords_to_read; 35887b6859fbSMintz, Yuval bool packed; 35897b6859fbSMintz, Yuval 35907b6859fbSMintz, Yuval rss_defs = &s_rss_mem_defs[rss_mem_id]; 35917b6859fbSMintz, Yuval rss_addr = rss_defs->addr; 35927b6859fbSMintz, Yuval num_entries = rss_defs->num_entries[dev_data->chip_id]; 3593da090917STomer Tayar total_dwords = (num_entries * rss_defs->entry_width) / 32; 3594da090917STomer Tayar packed = (rss_defs->entry_width == 16); 3595c965db44STomer Tayar 3596c965db44STomer Tayar offset += qed_grc_dump_mem_hdr(p_hwfn, 3597c965db44STomer Tayar dump_buf + offset, 3598c965db44STomer Tayar dump, 3599c965db44STomer Tayar rss_defs->mem_name, 3600be086e7cSMintz, Yuval 0, 3601be086e7cSMintz, Yuval total_dwords, 3602da090917STomer Tayar rss_defs->entry_width, 3603c965db44STomer Tayar packed, 3604c965db44STomer Tayar rss_defs->type_name, false, 0); 3605c965db44STomer Tayar 36067b6859fbSMintz, Yuval /* Dump RSS data */ 3607c965db44STomer Tayar if (!dump) { 3608be086e7cSMintz, Yuval offset += total_dwords; 3609c965db44STomer Tayar continue; 3610c965db44STomer Tayar } 3611c965db44STomer Tayar 3612be086e7cSMintz, Yuval addr = BYTES_TO_DWORDS(RSS_REG_RSS_RAM_DATA); 3613da090917STomer Tayar while (total_dwords) { 3614da090917STomer Tayar num_dwords_to_read = min_t(u32, 3615da090917STomer Tayar RSS_REG_RSS_RAM_DATA_SIZE, 3616da090917STomer Tayar total_dwords); 3617be086e7cSMintz, Yuval qed_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_ADDR, rss_addr); 3618be086e7cSMintz, Yuval offset += qed_grc_dump_addr_range(p_hwfn, 3619be086e7cSMintz, Yuval p_ptt, 36207b6859fbSMintz, Yuval dump_buf + offset, 3621be086e7cSMintz, Yuval dump, 3622be086e7cSMintz, Yuval addr, 3623da090917STomer Tayar num_dwords_to_read, 36247b6859fbSMintz, Yuval false); 3625da090917STomer Tayar total_dwords -= num_dwords_to_read; 3626da090917STomer Tayar rss_addr++; 3627c965db44STomer Tayar } 3628c965db44STomer Tayar } 3629c965db44STomer Tayar 3630c965db44STomer Tayar return offset; 3631c965db44STomer Tayar } 3632c965db44STomer Tayar 3633c965db44STomer Tayar /* Dumps GRC Big RAM. Returns the dumped size in dwords. */ 3634c965db44STomer Tayar static u32 qed_grc_dump_big_ram(struct qed_hwfn *p_hwfn, 3635c965db44STomer Tayar struct qed_ptt *p_ptt, 3636c965db44STomer Tayar u32 *dump_buf, bool dump, u8 big_ram_id) 3637c965db44STomer Tayar { 3638c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 3639da090917STomer Tayar u32 block_size, ram_size, offset = 0, reg_val, i; 3640c965db44STomer Tayar char mem_name[12] = "???_BIG_RAM"; 3641c965db44STomer Tayar char type_name[8] = "???_RAM"; 3642be086e7cSMintz, Yuval struct big_ram_defs *big_ram; 3643c965db44STomer Tayar 3644be086e7cSMintz, Yuval big_ram = &s_big_ram_defs[big_ram_id]; 3645da090917STomer Tayar ram_size = big_ram->ram_size[dev_data->chip_id]; 3646da090917STomer Tayar 3647da090917STomer Tayar reg_val = qed_rd(p_hwfn, p_ptt, big_ram->is_256b_reg_addr); 3648da090917STomer Tayar block_size = reg_val & 3649da090917STomer Tayar BIT(big_ram->is_256b_bit_offset[dev_data->chip_id]) ? 256 3650da090917STomer Tayar : 128; 3651c965db44STomer Tayar 3652be086e7cSMintz, Yuval strncpy(type_name, big_ram->instance_name, 3653be086e7cSMintz, Yuval strlen(big_ram->instance_name)); 3654be086e7cSMintz, Yuval strncpy(mem_name, big_ram->instance_name, 3655be086e7cSMintz, Yuval strlen(big_ram->instance_name)); 3656c965db44STomer Tayar 3657c965db44STomer Tayar /* Dump memory header */ 3658c965db44STomer Tayar offset += qed_grc_dump_mem_hdr(p_hwfn, 3659c965db44STomer Tayar dump_buf + offset, 3660c965db44STomer Tayar dump, 3661c965db44STomer Tayar mem_name, 3662c965db44STomer Tayar 0, 3663c965db44STomer Tayar ram_size, 3664da090917STomer Tayar block_size * 8, 3665c965db44STomer Tayar false, type_name, false, 0); 3666c965db44STomer Tayar 36677b6859fbSMintz, Yuval /* Read and dump Big RAM data */ 3668c965db44STomer Tayar if (!dump) 3669c965db44STomer Tayar return offset + ram_size; 3670c965db44STomer Tayar 36717b6859fbSMintz, Yuval /* Dump Big RAM */ 3672da090917STomer Tayar for (i = 0; i < DIV_ROUND_UP(ram_size, BRB_REG_BIG_RAM_DATA_SIZE); 3673da090917STomer Tayar i++) { 3674be086e7cSMintz, Yuval u32 addr, len; 3675be086e7cSMintz, Yuval 3676be086e7cSMintz, Yuval qed_wr(p_hwfn, p_ptt, big_ram->addr_reg_addr, i); 3677be086e7cSMintz, Yuval addr = BYTES_TO_DWORDS(big_ram->data_reg_addr); 3678da090917STomer Tayar len = BRB_REG_BIG_RAM_DATA_SIZE; 3679be086e7cSMintz, Yuval offset += qed_grc_dump_addr_range(p_hwfn, 3680be086e7cSMintz, Yuval p_ptt, 3681be086e7cSMintz, Yuval dump_buf + offset, 3682be086e7cSMintz, Yuval dump, 3683be086e7cSMintz, Yuval addr, 36847b6859fbSMintz, Yuval len, 36857b6859fbSMintz, Yuval false); 3686c965db44STomer Tayar } 3687c965db44STomer Tayar 3688c965db44STomer Tayar return offset; 3689c965db44STomer Tayar } 3690c965db44STomer Tayar 3691c965db44STomer Tayar static u32 qed_grc_dump_mcp(struct qed_hwfn *p_hwfn, 3692c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *dump_buf, bool dump) 3693c965db44STomer Tayar { 3694c965db44STomer Tayar bool block_enable[MAX_BLOCK_ID] = { 0 }; 3695be086e7cSMintz, Yuval u32 offset = 0, addr; 3696c965db44STomer Tayar bool halted = false; 3697c965db44STomer Tayar 3698c965db44STomer Tayar /* Halt MCP */ 3699be086e7cSMintz, Yuval if (dump && !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_MCP)) { 3700c965db44STomer Tayar halted = !qed_mcp_halt(p_hwfn, p_ptt); 3701c965db44STomer Tayar if (!halted) 3702c965db44STomer Tayar DP_NOTICE(p_hwfn, "MCP halt failed!\n"); 3703c965db44STomer Tayar } 3704c965db44STomer Tayar 3705c965db44STomer Tayar /* Dump MCP scratchpad */ 3706c965db44STomer Tayar offset += qed_grc_dump_mem(p_hwfn, 3707c965db44STomer Tayar p_ptt, 3708c965db44STomer Tayar dump_buf + offset, 3709c965db44STomer Tayar dump, 3710c965db44STomer Tayar NULL, 3711be086e7cSMintz, Yuval BYTES_TO_DWORDS(MCP_REG_SCRATCH), 371221dd79e8STomer Tayar MCP_REG_SCRATCH_SIZE_BB_K2, 37137b6859fbSMintz, Yuval false, 0, false, "MCP", false, 0); 3714c965db44STomer Tayar 3715c965db44STomer Tayar /* Dump MCP cpu_reg_file */ 3716c965db44STomer Tayar offset += qed_grc_dump_mem(p_hwfn, 3717c965db44STomer Tayar p_ptt, 3718c965db44STomer Tayar dump_buf + offset, 3719c965db44STomer Tayar dump, 3720c965db44STomer Tayar NULL, 3721be086e7cSMintz, Yuval BYTES_TO_DWORDS(MCP_REG_CPU_REG_FILE), 3722c965db44STomer Tayar MCP_REG_CPU_REG_FILE_SIZE, 37237b6859fbSMintz, Yuval false, 0, false, "MCP", false, 0); 3724c965db44STomer Tayar 3725c965db44STomer Tayar /* Dump MCP registers */ 3726c965db44STomer Tayar block_enable[BLOCK_MCP] = true; 3727c965db44STomer Tayar offset += qed_grc_dump_registers(p_hwfn, 3728c965db44STomer Tayar p_ptt, 3729c965db44STomer Tayar dump_buf + offset, 3730c965db44STomer Tayar dump, block_enable, "block", "MCP"); 3731c965db44STomer Tayar 3732c965db44STomer Tayar /* Dump required non-MCP registers */ 3733c965db44STomer Tayar offset += qed_grc_dump_regs_hdr(dump_buf + offset, 3734c965db44STomer Tayar dump, 1, "eng", -1, "block", "MCP"); 3735be086e7cSMintz, Yuval addr = BYTES_TO_DWORDS(MISC_REG_SHARED_MEM_ADDR); 3736c965db44STomer Tayar offset += qed_grc_dump_reg_entry(p_hwfn, 3737c965db44STomer Tayar p_ptt, 3738c965db44STomer Tayar dump_buf + offset, 3739c965db44STomer Tayar dump, 3740be086e7cSMintz, Yuval addr, 37417b6859fbSMintz, Yuval 1, 37427b6859fbSMintz, Yuval false); 3743c965db44STomer Tayar 3744c965db44STomer Tayar /* Release MCP */ 3745c965db44STomer Tayar if (halted && qed_mcp_resume(p_hwfn, p_ptt)) 3746c965db44STomer Tayar DP_NOTICE(p_hwfn, "Failed to resume MCP after halt!\n"); 37477b6859fbSMintz, Yuval 3748c965db44STomer Tayar return offset; 3749c965db44STomer Tayar } 3750c965db44STomer Tayar 3751c965db44STomer Tayar /* Dumps the tbus indirect memory for all PHYs. */ 3752c965db44STomer Tayar static u32 qed_grc_dump_phy(struct qed_hwfn *p_hwfn, 3753c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *dump_buf, bool dump) 3754c965db44STomer Tayar { 3755c965db44STomer Tayar u32 offset = 0, tbus_lo_offset, tbus_hi_offset; 3756c965db44STomer Tayar char mem_name[32]; 3757c965db44STomer Tayar u8 phy_id; 3758c965db44STomer Tayar 3759c965db44STomer Tayar for (phy_id = 0; phy_id < ARRAY_SIZE(s_phy_defs); phy_id++) { 37607b6859fbSMintz, Yuval u32 addr_lo_addr, addr_hi_addr, data_lo_addr, data_hi_addr; 37617b6859fbSMintz, Yuval struct phy_defs *phy_defs; 37627b6859fbSMintz, Yuval u8 *bytes_buf; 3763c965db44STomer Tayar 37647b6859fbSMintz, Yuval phy_defs = &s_phy_defs[phy_id]; 37657b6859fbSMintz, Yuval addr_lo_addr = phy_defs->base_addr + 37667b6859fbSMintz, Yuval phy_defs->tbus_addr_lo_addr; 37677b6859fbSMintz, Yuval addr_hi_addr = phy_defs->base_addr + 37687b6859fbSMintz, Yuval phy_defs->tbus_addr_hi_addr; 37697b6859fbSMintz, Yuval data_lo_addr = phy_defs->base_addr + 37707b6859fbSMintz, Yuval phy_defs->tbus_data_lo_addr; 37717b6859fbSMintz, Yuval data_hi_addr = phy_defs->base_addr + 37727b6859fbSMintz, Yuval phy_defs->tbus_data_hi_addr; 37737b6859fbSMintz, Yuval 37747b6859fbSMintz, Yuval if (snprintf(mem_name, sizeof(mem_name), "tbus_%s", 37757b6859fbSMintz, Yuval phy_defs->phy_name) < 0) 3776c965db44STomer Tayar DP_NOTICE(p_hwfn, 3777c965db44STomer Tayar "Unexpected debug error: invalid PHY memory name\n"); 37787b6859fbSMintz, Yuval 3779c965db44STomer Tayar offset += qed_grc_dump_mem_hdr(p_hwfn, 3780c965db44STomer Tayar dump_buf + offset, 3781c965db44STomer Tayar dump, 3782c965db44STomer Tayar mem_name, 3783c965db44STomer Tayar 0, 3784c965db44STomer Tayar PHY_DUMP_SIZE_DWORDS, 3785c965db44STomer Tayar 16, true, mem_name, false, 0); 37867b6859fbSMintz, Yuval 37877b6859fbSMintz, Yuval if (!dump) { 37887b6859fbSMintz, Yuval offset += PHY_DUMP_SIZE_DWORDS; 37897b6859fbSMintz, Yuval continue; 37907b6859fbSMintz, Yuval } 3791c965db44STomer Tayar 3792da090917STomer Tayar bytes_buf = (u8 *)(dump_buf + offset); 3793c965db44STomer Tayar for (tbus_hi_offset = 0; 3794c965db44STomer Tayar tbus_hi_offset < (NUM_PHY_TBUS_ADDRESSES >> 8); 3795c965db44STomer Tayar tbus_hi_offset++) { 37967b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, addr_hi_addr, tbus_hi_offset); 3797c965db44STomer Tayar for (tbus_lo_offset = 0; tbus_lo_offset < 256; 3798c965db44STomer Tayar tbus_lo_offset++) { 3799c965db44STomer Tayar qed_wr(p_hwfn, 38007b6859fbSMintz, Yuval p_ptt, addr_lo_addr, tbus_lo_offset); 38017b6859fbSMintz, Yuval *(bytes_buf++) = (u8)qed_rd(p_hwfn, 3802c965db44STomer Tayar p_ptt, 3803c965db44STomer Tayar data_lo_addr); 38047b6859fbSMintz, Yuval *(bytes_buf++) = (u8)qed_rd(p_hwfn, 38057b6859fbSMintz, Yuval p_ptt, 3806c965db44STomer Tayar data_hi_addr); 3807c965db44STomer Tayar } 3808c965db44STomer Tayar } 3809c965db44STomer Tayar 3810c965db44STomer Tayar offset += PHY_DUMP_SIZE_DWORDS; 3811c965db44STomer Tayar } 3812c965db44STomer Tayar 3813c965db44STomer Tayar return offset; 3814c965db44STomer Tayar } 3815c965db44STomer Tayar 3816c965db44STomer Tayar static void qed_config_dbg_line(struct qed_hwfn *p_hwfn, 3817c965db44STomer Tayar struct qed_ptt *p_ptt, 3818c965db44STomer Tayar enum block_id block_id, 3819c965db44STomer Tayar u8 line_id, 38207b6859fbSMintz, Yuval u8 enable_mask, 38217b6859fbSMintz, Yuval u8 right_shift, 38227b6859fbSMintz, Yuval u8 force_valid_mask, u8 force_frame_mask) 3823c965db44STomer Tayar { 38247b6859fbSMintz, Yuval struct block_defs *block = s_block_defs[block_id]; 3825c965db44STomer Tayar 38267b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, block->dbg_select_addr, line_id); 38277b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, block->dbg_enable_addr, enable_mask); 38287b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, block->dbg_shift_addr, right_shift); 38297b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, block->dbg_force_valid_addr, force_valid_mask); 38307b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, block->dbg_force_frame_addr, force_frame_mask); 3831c965db44STomer Tayar } 3832c965db44STomer Tayar 3833c965db44STomer Tayar /* Dumps Static Debug data. Returns the dumped size in dwords. */ 3834c965db44STomer Tayar static u32 qed_grc_dump_static_debug(struct qed_hwfn *p_hwfn, 3835c965db44STomer Tayar struct qed_ptt *p_ptt, 3836c965db44STomer Tayar u32 *dump_buf, bool dump) 3837c965db44STomer Tayar { 3838c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 38397b6859fbSMintz, Yuval u32 block_id, line_id, offset = 0; 38407b6859fbSMintz, Yuval 3841da090917STomer Tayar /* Don't dump static debug if a debug bus recording is in progress */ 3842da090917STomer Tayar if (dump && qed_rd(p_hwfn, p_ptt, DBG_REG_DBG_BLOCK_ON)) 38437b6859fbSMintz, Yuval return 0; 3844c965db44STomer Tayar 3845c965db44STomer Tayar if (dump) { 3846c965db44STomer Tayar /* Disable all blocks debug output */ 3847c965db44STomer Tayar for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) { 38487b6859fbSMintz, Yuval struct block_defs *block = s_block_defs[block_id]; 3849c965db44STomer Tayar 3850da090917STomer Tayar if (block->dbg_client_id[dev_data->chip_id] != 3851da090917STomer Tayar MAX_DBG_BUS_CLIENTS) 38527b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, block->dbg_enable_addr, 38537b6859fbSMintz, Yuval 0); 3854c965db44STomer Tayar } 3855c965db44STomer Tayar 3856c965db44STomer Tayar qed_bus_reset_dbg_block(p_hwfn, p_ptt); 3857c965db44STomer Tayar qed_bus_set_framing_mode(p_hwfn, 3858c965db44STomer Tayar p_ptt, DBG_BUS_FRAME_MODE_8HW_0ST); 3859c965db44STomer Tayar qed_wr(p_hwfn, 3860c965db44STomer Tayar p_ptt, DBG_REG_DEBUG_TARGET, DBG_BUS_TARGET_ID_INT_BUF); 3861c965db44STomer Tayar qed_wr(p_hwfn, p_ptt, DBG_REG_FULL_MODE, 1); 3862c965db44STomer Tayar qed_bus_enable_dbg_block(p_hwfn, p_ptt, true); 3863c965db44STomer Tayar } 3864c965db44STomer Tayar 3865c965db44STomer Tayar /* Dump all static debug lines for each relevant block */ 3866c965db44STomer Tayar for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) { 38677b6859fbSMintz, Yuval struct block_defs *block = s_block_defs[block_id]; 38687b6859fbSMintz, Yuval struct dbg_bus_block *block_desc; 38697b6859fbSMintz, Yuval u32 block_dwords, addr, len; 38707b6859fbSMintz, Yuval u8 dbg_client_id; 3871c965db44STomer Tayar 3872da090917STomer Tayar if (block->dbg_client_id[dev_data->chip_id] == 3873da090917STomer Tayar MAX_DBG_BUS_CLIENTS) 3874c965db44STomer Tayar continue; 3875c965db44STomer Tayar 3876da090917STomer Tayar block_desc = get_dbg_bus_block_desc(p_hwfn, 38777b6859fbSMintz, Yuval (enum block_id)block_id); 38787b6859fbSMintz, Yuval block_dwords = NUM_DBG_LINES(block_desc) * 38797b6859fbSMintz, Yuval STATIC_DEBUG_LINE_DWORDS; 38807b6859fbSMintz, Yuval 3881c965db44STomer Tayar /* Dump static section params */ 3882c965db44STomer Tayar offset += qed_grc_dump_mem_hdr(p_hwfn, 3883c965db44STomer Tayar dump_buf + offset, 3884c965db44STomer Tayar dump, 38857b6859fbSMintz, Yuval block->name, 38867b6859fbSMintz, Yuval 0, 38877b6859fbSMintz, Yuval block_dwords, 38887b6859fbSMintz, Yuval 32, false, "STATIC", false, 0); 3889c965db44STomer Tayar 38907b6859fbSMintz, Yuval if (!dump) { 38917b6859fbSMintz, Yuval offset += block_dwords; 38927b6859fbSMintz, Yuval continue; 38937b6859fbSMintz, Yuval } 38947b6859fbSMintz, Yuval 38957b6859fbSMintz, Yuval /* If all lines are invalid - dump zeros */ 38967b6859fbSMintz, Yuval if (dev_data->block_in_reset[block_id]) { 38977b6859fbSMintz, Yuval memset(dump_buf + offset, 0, 38987b6859fbSMintz, Yuval DWORDS_TO_BYTES(block_dwords)); 38997b6859fbSMintz, Yuval offset += block_dwords; 39007b6859fbSMintz, Yuval continue; 39017b6859fbSMintz, Yuval } 3902c965db44STomer Tayar 3903c965db44STomer Tayar /* Enable block's client */ 39047b6859fbSMintz, Yuval dbg_client_id = block->dbg_client_id[dev_data->chip_id]; 39057b6859fbSMintz, Yuval qed_bus_enable_clients(p_hwfn, 39067b6859fbSMintz, Yuval p_ptt, 3907c965db44STomer Tayar BIT(dbg_client_id)); 3908c965db44STomer Tayar 39097b6859fbSMintz, Yuval addr = BYTES_TO_DWORDS(DBG_REG_CALENDAR_OUT_DATA); 39107b6859fbSMintz, Yuval len = STATIC_DEBUG_LINE_DWORDS; 39117b6859fbSMintz, Yuval for (line_id = 0; line_id < (u32)NUM_DBG_LINES(block_desc); 3912c965db44STomer Tayar line_id++) { 3913c965db44STomer Tayar /* Configure debug line ID */ 3914c965db44STomer Tayar qed_config_dbg_line(p_hwfn, 3915c965db44STomer Tayar p_ptt, 3916c965db44STomer Tayar (enum block_id)block_id, 39177b6859fbSMintz, Yuval (u8)line_id, 0xf, 0, 0, 0); 3918c965db44STomer Tayar 3919c965db44STomer Tayar /* Read debug line info */ 39207b6859fbSMintz, Yuval offset += qed_grc_dump_addr_range(p_hwfn, 3921be086e7cSMintz, Yuval p_ptt, 3922be086e7cSMintz, Yuval dump_buf + offset, 3923be086e7cSMintz, Yuval dump, 3924be086e7cSMintz, Yuval addr, 39257b6859fbSMintz, Yuval len, 39267b6859fbSMintz, Yuval true); 3927c965db44STomer Tayar } 3928c965db44STomer Tayar 3929c965db44STomer Tayar /* Disable block's client and debug output */ 3930c965db44STomer Tayar qed_bus_enable_clients(p_hwfn, p_ptt, 0); 39317b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, block->dbg_enable_addr, 0); 3932c965db44STomer Tayar } 3933c965db44STomer Tayar 3934c965db44STomer Tayar if (dump) { 3935c965db44STomer Tayar qed_bus_enable_dbg_block(p_hwfn, p_ptt, false); 3936c965db44STomer Tayar qed_bus_enable_clients(p_hwfn, p_ptt, 0); 3937c965db44STomer Tayar } 3938c965db44STomer Tayar 3939c965db44STomer Tayar return offset; 3940c965db44STomer Tayar } 3941c965db44STomer Tayar 3942c965db44STomer Tayar /* Performs GRC Dump to the specified buffer. 3943c965db44STomer Tayar * Returns the dumped size in dwords. 3944c965db44STomer Tayar */ 3945c965db44STomer Tayar static enum dbg_status qed_grc_dump(struct qed_hwfn *p_hwfn, 3946c965db44STomer Tayar struct qed_ptt *p_ptt, 3947c965db44STomer Tayar u32 *dump_buf, 3948c965db44STomer Tayar bool dump, u32 *num_dumped_dwords) 3949c965db44STomer Tayar { 3950c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 3951c965db44STomer Tayar bool parities_masked = false; 3952c965db44STomer Tayar u8 i, port_mode = 0; 3953c965db44STomer Tayar u32 offset = 0; 3954c965db44STomer Tayar 3955c965db44STomer Tayar *num_dumped_dwords = 0; 3956c965db44STomer Tayar 3957c965db44STomer Tayar if (dump) { 39587b6859fbSMintz, Yuval /* Find port mode */ 3959c965db44STomer Tayar switch (qed_rd(p_hwfn, p_ptt, MISC_REG_PORT_MODE)) { 3960c965db44STomer Tayar case 0: 3961c965db44STomer Tayar port_mode = 1; 3962c965db44STomer Tayar break; 3963c965db44STomer Tayar case 1: 3964c965db44STomer Tayar port_mode = 2; 3965c965db44STomer Tayar break; 3966c965db44STomer Tayar case 2: 3967c965db44STomer Tayar port_mode = 4; 3968c965db44STomer Tayar break; 3969c965db44STomer Tayar } 3970c965db44STomer Tayar 3971c965db44STomer Tayar /* Update reset state */ 3972c965db44STomer Tayar qed_update_blocks_reset_state(p_hwfn, p_ptt); 39737b6859fbSMintz, Yuval } 3974c965db44STomer Tayar 3975c965db44STomer Tayar /* Dump global params */ 3976c965db44STomer Tayar offset += qed_dump_common_global_params(p_hwfn, 3977c965db44STomer Tayar p_ptt, 3978c965db44STomer Tayar dump_buf + offset, dump, 4); 3979c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 3980c965db44STomer Tayar dump, "dump-type", "grc-dump"); 3981c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 3982c965db44STomer Tayar dump, 3983c965db44STomer Tayar "num-lcids", 3984c965db44STomer Tayar qed_grc_get_param(p_hwfn, 3985c965db44STomer Tayar DBG_GRC_PARAM_NUM_LCIDS)); 3986c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 3987c965db44STomer Tayar dump, 3988c965db44STomer Tayar "num-ltids", 3989c965db44STomer Tayar qed_grc_get_param(p_hwfn, 3990c965db44STomer Tayar DBG_GRC_PARAM_NUM_LTIDS)); 3991c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 3992c965db44STomer Tayar dump, "num-ports", port_mode); 3993c965db44STomer Tayar 3994c965db44STomer Tayar /* Dump reset registers (dumped before taking blocks out of reset ) */ 3995c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_REGS)) 3996c965db44STomer Tayar offset += qed_grc_dump_reset_regs(p_hwfn, 3997c965db44STomer Tayar p_ptt, 3998c965db44STomer Tayar dump_buf + offset, dump); 3999c965db44STomer Tayar 4000c965db44STomer Tayar /* Take all blocks out of reset (using reset registers) */ 4001c965db44STomer Tayar if (dump) { 4002c965db44STomer Tayar qed_grc_unreset_blocks(p_hwfn, p_ptt); 4003c965db44STomer Tayar qed_update_blocks_reset_state(p_hwfn, p_ptt); 4004c965db44STomer Tayar } 4005c965db44STomer Tayar 4006c965db44STomer Tayar /* Disable all parities using MFW command */ 40077b6859fbSMintz, Yuval if (dump && 40087b6859fbSMintz, Yuval !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_MCP)) { 4009c965db44STomer Tayar parities_masked = !qed_mcp_mask_parities(p_hwfn, p_ptt, 1); 4010c965db44STomer Tayar if (!parities_masked) { 4011be086e7cSMintz, Yuval DP_NOTICE(p_hwfn, 4012be086e7cSMintz, Yuval "Failed to mask parities using MFW\n"); 4013c965db44STomer Tayar if (qed_grc_get_param 4014c965db44STomer Tayar (p_hwfn, DBG_GRC_PARAM_PARITY_SAFE)) 4015c965db44STomer Tayar return DBG_STATUS_MCP_COULD_NOT_MASK_PRTY; 4016c965db44STomer Tayar } 4017c965db44STomer Tayar } 4018c965db44STomer Tayar 4019c965db44STomer Tayar /* Dump modified registers (dumped before modifying them) */ 4020c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_REGS)) 4021c965db44STomer Tayar offset += qed_grc_dump_modified_regs(p_hwfn, 4022c965db44STomer Tayar p_ptt, 4023c965db44STomer Tayar dump_buf + offset, dump); 4024c965db44STomer Tayar 4025c965db44STomer Tayar /* Stall storms */ 4026c965db44STomer Tayar if (dump && 4027c965db44STomer Tayar (qed_grc_is_included(p_hwfn, 4028c965db44STomer Tayar DBG_GRC_PARAM_DUMP_IOR) || 4029c965db44STomer Tayar qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_VFC))) 4030c965db44STomer Tayar qed_grc_stall_storms(p_hwfn, p_ptt, true); 4031c965db44STomer Tayar 4032c965db44STomer Tayar /* Dump all regs */ 4033c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_REGS)) { 4034c965db44STomer Tayar bool block_enable[MAX_BLOCK_ID]; 4035c965db44STomer Tayar 40367b6859fbSMintz, Yuval /* Dump all blocks except MCP */ 4037c965db44STomer Tayar for (i = 0; i < MAX_BLOCK_ID; i++) 4038c965db44STomer Tayar block_enable[i] = true; 4039c965db44STomer Tayar block_enable[BLOCK_MCP] = false; 4040c965db44STomer Tayar offset += qed_grc_dump_registers(p_hwfn, 4041c965db44STomer Tayar p_ptt, 4042c965db44STomer Tayar dump_buf + 4043c965db44STomer Tayar offset, 4044c965db44STomer Tayar dump, 4045c965db44STomer Tayar block_enable, NULL, NULL); 4046be086e7cSMintz, Yuval 4047be086e7cSMintz, Yuval /* Dump special registers */ 4048be086e7cSMintz, Yuval offset += qed_grc_dump_special_regs(p_hwfn, 4049be086e7cSMintz, Yuval p_ptt, 4050be086e7cSMintz, Yuval dump_buf + offset, dump); 4051c965db44STomer Tayar } 4052c965db44STomer Tayar 4053c965db44STomer Tayar /* Dump memories */ 4054c965db44STomer Tayar offset += qed_grc_dump_memories(p_hwfn, p_ptt, dump_buf + offset, dump); 4055c965db44STomer Tayar 4056c965db44STomer Tayar /* Dump MCP */ 4057c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_MCP)) 4058c965db44STomer Tayar offset += qed_grc_dump_mcp(p_hwfn, 4059c965db44STomer Tayar p_ptt, dump_buf + offset, dump); 4060c965db44STomer Tayar 4061c965db44STomer Tayar /* Dump context */ 4062c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CM_CTX)) 4063c965db44STomer Tayar offset += qed_grc_dump_ctx(p_hwfn, 4064c965db44STomer Tayar p_ptt, dump_buf + offset, dump); 4065c965db44STomer Tayar 4066c965db44STomer Tayar /* Dump RSS memories */ 4067c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_RSS)) 4068c965db44STomer Tayar offset += qed_grc_dump_rss(p_hwfn, 4069c965db44STomer Tayar p_ptt, dump_buf + offset, dump); 4070c965db44STomer Tayar 4071c965db44STomer Tayar /* Dump Big RAM */ 4072c965db44STomer Tayar for (i = 0; i < NUM_BIG_RAM_TYPES; i++) 4073c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, s_big_ram_defs[i].grc_param)) 4074c965db44STomer Tayar offset += qed_grc_dump_big_ram(p_hwfn, 4075c965db44STomer Tayar p_ptt, 4076c965db44STomer Tayar dump_buf + offset, 4077c965db44STomer Tayar dump, i); 4078c965db44STomer Tayar 4079c965db44STomer Tayar /* Dump IORs */ 4080c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_IOR)) 4081c965db44STomer Tayar offset += qed_grc_dump_iors(p_hwfn, 4082c965db44STomer Tayar p_ptt, dump_buf + offset, dump); 4083c965db44STomer Tayar 4084c965db44STomer Tayar /* Dump VFC */ 4085c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_VFC)) 4086c965db44STomer Tayar offset += qed_grc_dump_vfc(p_hwfn, 4087c965db44STomer Tayar p_ptt, dump_buf + offset, dump); 4088c965db44STomer Tayar 4089c965db44STomer Tayar /* Dump PHY tbus */ 4090c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, 4091c965db44STomer Tayar DBG_GRC_PARAM_DUMP_PHY) && dev_data->chip_id == 4092c965db44STomer Tayar CHIP_K2 && dev_data->platform_id == PLATFORM_ASIC) 4093c965db44STomer Tayar offset += qed_grc_dump_phy(p_hwfn, 4094c965db44STomer Tayar p_ptt, dump_buf + offset, dump); 4095c965db44STomer Tayar 4096c965db44STomer Tayar /* Dump static debug data */ 4097c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, 4098c965db44STomer Tayar DBG_GRC_PARAM_DUMP_STATIC) && 4099c965db44STomer Tayar dev_data->bus.state == DBG_BUS_STATE_IDLE) 4100c965db44STomer Tayar offset += qed_grc_dump_static_debug(p_hwfn, 4101c965db44STomer Tayar p_ptt, 4102c965db44STomer Tayar dump_buf + offset, dump); 4103c965db44STomer Tayar 4104c965db44STomer Tayar /* Dump last section */ 4105da090917STomer Tayar offset += qed_dump_last_section(dump_buf, offset, dump); 41067b6859fbSMintz, Yuval 4107c965db44STomer Tayar if (dump) { 4108c965db44STomer Tayar /* Unstall storms */ 4109c965db44STomer Tayar if (qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_UNSTALL)) 4110c965db44STomer Tayar qed_grc_stall_storms(p_hwfn, p_ptt, false); 4111c965db44STomer Tayar 4112c965db44STomer Tayar /* Clear parity status */ 4113c965db44STomer Tayar qed_grc_clear_all_prty(p_hwfn, p_ptt); 4114c965db44STomer Tayar 4115c965db44STomer Tayar /* Enable all parities using MFW command */ 4116c965db44STomer Tayar if (parities_masked) 4117c965db44STomer Tayar qed_mcp_mask_parities(p_hwfn, p_ptt, 0); 4118c965db44STomer Tayar } 4119c965db44STomer Tayar 4120c965db44STomer Tayar *num_dumped_dwords = offset; 4121c965db44STomer Tayar 4122c965db44STomer Tayar return DBG_STATUS_OK; 4123c965db44STomer Tayar } 4124c965db44STomer Tayar 4125c965db44STomer Tayar /* Writes the specified failing Idle Check rule to the specified buffer. 4126c965db44STomer Tayar * Returns the dumped size in dwords. 4127c965db44STomer Tayar */ 4128c965db44STomer Tayar static u32 qed_idle_chk_dump_failure(struct qed_hwfn *p_hwfn, 4129c965db44STomer Tayar struct qed_ptt *p_ptt, 4130c965db44STomer Tayar u32 * 4131c965db44STomer Tayar dump_buf, 4132c965db44STomer Tayar bool dump, 4133c965db44STomer Tayar u16 rule_id, 4134c965db44STomer Tayar const struct dbg_idle_chk_rule *rule, 4135c965db44STomer Tayar u16 fail_entry_id, u32 *cond_reg_values) 4136c965db44STomer Tayar { 4137c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 41387b6859fbSMintz, Yuval const struct dbg_idle_chk_cond_reg *cond_regs; 41397b6859fbSMintz, Yuval const struct dbg_idle_chk_info_reg *info_regs; 41407b6859fbSMintz, Yuval u32 i, next_reg_offset = 0, offset = 0; 41417b6859fbSMintz, Yuval struct dbg_idle_chk_result_hdr *hdr; 41427b6859fbSMintz, Yuval const union dbg_idle_chk_reg *regs; 4143c965db44STomer Tayar u8 reg_id; 4144c965db44STomer Tayar 41457b6859fbSMintz, Yuval hdr = (struct dbg_idle_chk_result_hdr *)dump_buf; 41467b6859fbSMintz, Yuval regs = &((const union dbg_idle_chk_reg *) 41477b6859fbSMintz, Yuval s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_REGS].ptr)[rule->reg_offset]; 41487b6859fbSMintz, Yuval cond_regs = ®s[0].cond_reg; 41497b6859fbSMintz, Yuval info_regs = ®s[rule->num_cond_regs].info_reg; 41507b6859fbSMintz, Yuval 4151c965db44STomer Tayar /* Dump rule data */ 4152c965db44STomer Tayar if (dump) { 4153c965db44STomer Tayar memset(hdr, 0, sizeof(*hdr)); 4154c965db44STomer Tayar hdr->rule_id = rule_id; 4155c965db44STomer Tayar hdr->mem_entry_id = fail_entry_id; 4156c965db44STomer Tayar hdr->severity = rule->severity; 4157c965db44STomer Tayar hdr->num_dumped_cond_regs = rule->num_cond_regs; 4158c965db44STomer Tayar } 4159c965db44STomer Tayar 4160c965db44STomer Tayar offset += IDLE_CHK_RESULT_HDR_DWORDS; 4161c965db44STomer Tayar 4162c965db44STomer Tayar /* Dump condition register values */ 4163c965db44STomer Tayar for (reg_id = 0; reg_id < rule->num_cond_regs; reg_id++) { 4164c965db44STomer Tayar const struct dbg_idle_chk_cond_reg *reg = &cond_regs[reg_id]; 41657b6859fbSMintz, Yuval struct dbg_idle_chk_result_reg_hdr *reg_hdr; 41667b6859fbSMintz, Yuval 41677b6859fbSMintz, Yuval reg_hdr = (struct dbg_idle_chk_result_reg_hdr *) 41687b6859fbSMintz, Yuval (dump_buf + offset); 4169c965db44STomer Tayar 4170c965db44STomer Tayar /* Write register header */ 41717b6859fbSMintz, Yuval if (!dump) { 41727b6859fbSMintz, Yuval offset += IDLE_CHK_RESULT_REG_HDR_DWORDS + 41737b6859fbSMintz, Yuval reg->entry_size; 41747b6859fbSMintz, Yuval continue; 41757b6859fbSMintz, Yuval } 41767b6859fbSMintz, Yuval 4177c965db44STomer Tayar offset += IDLE_CHK_RESULT_REG_HDR_DWORDS; 41787b6859fbSMintz, Yuval memset(reg_hdr, 0, sizeof(*reg_hdr)); 4179c965db44STomer Tayar reg_hdr->start_entry = reg->start_entry; 4180c965db44STomer Tayar reg_hdr->size = reg->entry_size; 4181c965db44STomer Tayar SET_FIELD(reg_hdr->data, 4182c965db44STomer Tayar DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM, 41837b6859fbSMintz, Yuval reg->num_entries > 1 || reg->start_entry > 0 ? 1 : 0); 4184c965db44STomer Tayar SET_FIELD(reg_hdr->data, 4185c965db44STomer Tayar DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID, reg_id); 4186c965db44STomer Tayar 4187c965db44STomer Tayar /* Write register values */ 41887b6859fbSMintz, Yuval for (i = 0; i < reg_hdr->size; i++, next_reg_offset++, offset++) 41897b6859fbSMintz, Yuval dump_buf[offset] = cond_reg_values[next_reg_offset]; 4190c965db44STomer Tayar } 4191c965db44STomer Tayar 4192c965db44STomer Tayar /* Dump info register values */ 4193c965db44STomer Tayar for (reg_id = 0; reg_id < rule->num_info_regs; reg_id++) { 4194c965db44STomer Tayar const struct dbg_idle_chk_info_reg *reg = &info_regs[reg_id]; 4195c965db44STomer Tayar u32 block_id; 4196c965db44STomer Tayar 41977b6859fbSMintz, Yuval /* Check if register's block is in reset */ 4198c965db44STomer Tayar if (!dump) { 4199c965db44STomer Tayar offset += IDLE_CHK_RESULT_REG_HDR_DWORDS + reg->size; 4200c965db44STomer Tayar continue; 4201c965db44STomer Tayar } 4202c965db44STomer Tayar 4203c965db44STomer Tayar block_id = GET_FIELD(reg->data, DBG_IDLE_CHK_INFO_REG_BLOCK_ID); 4204c965db44STomer Tayar if (block_id >= MAX_BLOCK_ID) { 4205c965db44STomer Tayar DP_NOTICE(p_hwfn, "Invalid block_id\n"); 4206c965db44STomer Tayar return 0; 4207c965db44STomer Tayar } 4208c965db44STomer Tayar 4209c965db44STomer Tayar if (!dev_data->block_in_reset[block_id]) { 42107b6859fbSMintz, Yuval struct dbg_idle_chk_result_reg_hdr *reg_hdr; 42117b6859fbSMintz, Yuval bool wide_bus, eval_mode, mode_match = true; 42127b6859fbSMintz, Yuval u16 modes_buf_offset; 42137b6859fbSMintz, Yuval u32 addr; 42147b6859fbSMintz, Yuval 42157b6859fbSMintz, Yuval reg_hdr = (struct dbg_idle_chk_result_reg_hdr *) 42167b6859fbSMintz, Yuval (dump_buf + offset); 4217c965db44STomer Tayar 4218c965db44STomer Tayar /* Check mode */ 42197b6859fbSMintz, Yuval eval_mode = GET_FIELD(reg->mode.data, 42207b6859fbSMintz, Yuval DBG_MODE_HDR_EVAL_MODE) > 0; 4221c965db44STomer Tayar if (eval_mode) { 42227b6859fbSMintz, Yuval modes_buf_offset = 4223c965db44STomer Tayar GET_FIELD(reg->mode.data, 4224c965db44STomer Tayar DBG_MODE_HDR_MODES_BUF_OFFSET); 4225c965db44STomer Tayar mode_match = 4226c965db44STomer Tayar qed_is_mode_match(p_hwfn, 4227c965db44STomer Tayar &modes_buf_offset); 4228c965db44STomer Tayar } 4229c965db44STomer Tayar 42307b6859fbSMintz, Yuval if (!mode_match) 42317b6859fbSMintz, Yuval continue; 42327b6859fbSMintz, Yuval 42337b6859fbSMintz, Yuval addr = GET_FIELD(reg->data, 4234be086e7cSMintz, Yuval DBG_IDLE_CHK_INFO_REG_ADDRESS); 42357b6859fbSMintz, Yuval wide_bus = GET_FIELD(reg->data, 42367b6859fbSMintz, Yuval DBG_IDLE_CHK_INFO_REG_WIDE_BUS); 4237c965db44STomer Tayar 4238c965db44STomer Tayar /* Write register header */ 4239c965db44STomer Tayar offset += IDLE_CHK_RESULT_REG_HDR_DWORDS; 4240c965db44STomer Tayar hdr->num_dumped_info_regs++; 4241c965db44STomer Tayar memset(reg_hdr, 0, sizeof(*reg_hdr)); 4242c965db44STomer Tayar reg_hdr->size = reg->size; 4243c965db44STomer Tayar SET_FIELD(reg_hdr->data, 4244c965db44STomer Tayar DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID, 4245c965db44STomer Tayar rule->num_cond_regs + reg_id); 4246c965db44STomer Tayar 4247c965db44STomer Tayar /* Write register values */ 42487b6859fbSMintz, Yuval offset += qed_grc_dump_addr_range(p_hwfn, 4249be086e7cSMintz, Yuval p_ptt, 4250be086e7cSMintz, Yuval dump_buf + offset, 4251be086e7cSMintz, Yuval dump, 4252be086e7cSMintz, Yuval addr, 42537b6859fbSMintz, Yuval reg->size, wide_bus); 4254c965db44STomer Tayar } 4255c965db44STomer Tayar } 4256c965db44STomer Tayar 4257c965db44STomer Tayar return offset; 4258c965db44STomer Tayar } 4259c965db44STomer Tayar 4260c965db44STomer Tayar /* Dumps idle check rule entries. Returns the dumped size in dwords. */ 4261c965db44STomer Tayar static u32 4262c965db44STomer Tayar qed_idle_chk_dump_rule_entries(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 4263c965db44STomer Tayar u32 *dump_buf, bool dump, 4264c965db44STomer Tayar const struct dbg_idle_chk_rule *input_rules, 4265c965db44STomer Tayar u32 num_input_rules, u32 *num_failing_rules) 4266c965db44STomer Tayar { 4267c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 4268c965db44STomer Tayar u32 cond_reg_values[IDLE_CHK_MAX_ENTRIES_SIZE]; 4269be086e7cSMintz, Yuval u32 i, offset = 0; 4270c965db44STomer Tayar u16 entry_id; 4271c965db44STomer Tayar u8 reg_id; 4272c965db44STomer Tayar 4273c965db44STomer Tayar *num_failing_rules = 0; 42747b6859fbSMintz, Yuval 4275c965db44STomer Tayar for (i = 0; i < num_input_rules; i++) { 4276c965db44STomer Tayar const struct dbg_idle_chk_cond_reg *cond_regs; 4277c965db44STomer Tayar const struct dbg_idle_chk_rule *rule; 4278c965db44STomer Tayar const union dbg_idle_chk_reg *regs; 4279c965db44STomer Tayar u16 num_reg_entries = 1; 4280c965db44STomer Tayar bool check_rule = true; 4281c965db44STomer Tayar const u32 *imm_values; 4282c965db44STomer Tayar 4283c965db44STomer Tayar rule = &input_rules[i]; 4284c965db44STomer Tayar regs = &((const union dbg_idle_chk_reg *) 4285c965db44STomer Tayar s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_REGS].ptr) 4286c965db44STomer Tayar [rule->reg_offset]; 4287c965db44STomer Tayar cond_regs = ®s[0].cond_reg; 4288c965db44STomer Tayar imm_values = &s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_IMMS].ptr 4289c965db44STomer Tayar [rule->imm_offset]; 4290c965db44STomer Tayar 4291c965db44STomer Tayar /* Check if all condition register blocks are out of reset, and 4292c965db44STomer Tayar * find maximal number of entries (all condition registers that 4293c965db44STomer Tayar * are memories must have the same size, which is > 1). 4294c965db44STomer Tayar */ 4295c965db44STomer Tayar for (reg_id = 0; reg_id < rule->num_cond_regs && check_rule; 4296c965db44STomer Tayar reg_id++) { 42977b6859fbSMintz, Yuval u32 block_id = 42987b6859fbSMintz, Yuval GET_FIELD(cond_regs[reg_id].data, 4299c965db44STomer Tayar DBG_IDLE_CHK_COND_REG_BLOCK_ID); 4300c965db44STomer Tayar 4301c965db44STomer Tayar if (block_id >= MAX_BLOCK_ID) { 4302c965db44STomer Tayar DP_NOTICE(p_hwfn, "Invalid block_id\n"); 4303c965db44STomer Tayar return 0; 4304c965db44STomer Tayar } 4305c965db44STomer Tayar 4306c965db44STomer Tayar check_rule = !dev_data->block_in_reset[block_id]; 4307c965db44STomer Tayar if (cond_regs[reg_id].num_entries > num_reg_entries) 4308c965db44STomer Tayar num_reg_entries = cond_regs[reg_id].num_entries; 4309c965db44STomer Tayar } 4310c965db44STomer Tayar 4311c965db44STomer Tayar if (!check_rule && dump) 4312c965db44STomer Tayar continue; 4313c965db44STomer Tayar 4314be086e7cSMintz, Yuval if (!dump) { 4315da090917STomer Tayar u32 entry_dump_size = 4316da090917STomer Tayar qed_idle_chk_dump_failure(p_hwfn, 4317be086e7cSMintz, Yuval p_ptt, 4318be086e7cSMintz, Yuval dump_buf + offset, 4319be086e7cSMintz, Yuval false, 4320be086e7cSMintz, Yuval rule->rule_id, 4321be086e7cSMintz, Yuval rule, 4322da090917STomer Tayar 0, 4323be086e7cSMintz, Yuval NULL); 4324da090917STomer Tayar 4325da090917STomer Tayar offset += num_reg_entries * entry_dump_size; 4326da090917STomer Tayar (*num_failing_rules) += num_reg_entries; 4327da090917STomer Tayar continue; 4328be086e7cSMintz, Yuval } 4329be086e7cSMintz, Yuval 4330da090917STomer Tayar /* Go over all register entries (number of entries is the same 4331da090917STomer Tayar * for all condition registers). 4332da090917STomer Tayar */ 4333da090917STomer Tayar for (entry_id = 0; entry_id < num_reg_entries; entry_id++) { 4334da090917STomer Tayar u32 next_reg_offset = 0; 4335da090917STomer Tayar 4336c965db44STomer Tayar /* Read current entry of all condition registers */ 4337be086e7cSMintz, Yuval for (reg_id = 0; reg_id < rule->num_cond_regs; 4338c965db44STomer Tayar reg_id++) { 4339be086e7cSMintz, Yuval const struct dbg_idle_chk_cond_reg *reg = 4340be086e7cSMintz, Yuval &cond_regs[reg_id]; 43417b6859fbSMintz, Yuval u32 padded_entry_size, addr; 43427b6859fbSMintz, Yuval bool wide_bus; 4343c965db44STomer Tayar 4344be086e7cSMintz, Yuval /* Find GRC address (if it's a memory, the 4345be086e7cSMintz, Yuval * address of the specific entry is calculated). 4346c965db44STomer Tayar */ 43477b6859fbSMintz, Yuval addr = GET_FIELD(reg->data, 4348be086e7cSMintz, Yuval DBG_IDLE_CHK_COND_REG_ADDRESS); 43497b6859fbSMintz, Yuval wide_bus = 43507b6859fbSMintz, Yuval GET_FIELD(reg->data, 43517b6859fbSMintz, Yuval DBG_IDLE_CHK_COND_REG_WIDE_BUS); 4352c965db44STomer Tayar if (reg->num_entries > 1 || 4353c965db44STomer Tayar reg->start_entry > 0) { 43547b6859fbSMintz, Yuval padded_entry_size = 4355c965db44STomer Tayar reg->entry_size > 1 ? 4356da090917STomer Tayar roundup_pow_of_two(reg->entry_size) : 4357da090917STomer Tayar 1; 4358be086e7cSMintz, Yuval addr += (reg->start_entry + entry_id) * 4359be086e7cSMintz, Yuval padded_entry_size; 4360c965db44STomer Tayar } 4361c965db44STomer Tayar 4362c965db44STomer Tayar /* Read registers */ 4363c965db44STomer Tayar if (next_reg_offset + reg->entry_size >= 4364c965db44STomer Tayar IDLE_CHK_MAX_ENTRIES_SIZE) { 4365c965db44STomer Tayar DP_NOTICE(p_hwfn, 4366c965db44STomer Tayar "idle check registers entry is too large\n"); 4367c965db44STomer Tayar return 0; 4368c965db44STomer Tayar } 4369c965db44STomer Tayar 4370be086e7cSMintz, Yuval next_reg_offset += 43717b6859fbSMintz, Yuval qed_grc_dump_addr_range(p_hwfn, p_ptt, 4372be086e7cSMintz, Yuval cond_reg_values + 4373be086e7cSMintz, Yuval next_reg_offset, 4374be086e7cSMintz, Yuval dump, addr, 43757b6859fbSMintz, Yuval reg->entry_size, 43767b6859fbSMintz, Yuval wide_bus); 4377c965db44STomer Tayar } 4378c965db44STomer Tayar 43797b6859fbSMintz, Yuval /* Call rule condition function. 43807b6859fbSMintz, Yuval * If returns true, it's a failure. 4381c965db44STomer Tayar */ 4382c965db44STomer Tayar if ((*cond_arr[rule->cond_id]) (cond_reg_values, 4383be086e7cSMintz, Yuval imm_values)) { 43847b6859fbSMintz, Yuval offset += qed_idle_chk_dump_failure(p_hwfn, 4385c965db44STomer Tayar p_ptt, 4386c965db44STomer Tayar dump_buf + offset, 4387c965db44STomer Tayar dump, 4388c965db44STomer Tayar rule->rule_id, 4389c965db44STomer Tayar rule, 4390c965db44STomer Tayar entry_id, 4391c965db44STomer Tayar cond_reg_values); 4392c965db44STomer Tayar (*num_failing_rules)++; 4393c965db44STomer Tayar } 4394c965db44STomer Tayar } 4395c965db44STomer Tayar } 4396c965db44STomer Tayar 4397c965db44STomer Tayar return offset; 4398c965db44STomer Tayar } 4399c965db44STomer Tayar 4400c965db44STomer Tayar /* Performs Idle Check Dump to the specified buffer. 4401c965db44STomer Tayar * Returns the dumped size in dwords. 4402c965db44STomer Tayar */ 4403c965db44STomer Tayar static u32 qed_idle_chk_dump(struct qed_hwfn *p_hwfn, 4404c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *dump_buf, bool dump) 4405c965db44STomer Tayar { 44067b6859fbSMintz, Yuval u32 num_failing_rules_offset, offset = 0, input_offset = 0; 44077b6859fbSMintz, Yuval u32 num_failing_rules = 0; 4408c965db44STomer Tayar 4409c965db44STomer Tayar /* Dump global params */ 4410c965db44STomer Tayar offset += qed_dump_common_global_params(p_hwfn, 4411c965db44STomer Tayar p_ptt, 4412c965db44STomer Tayar dump_buf + offset, dump, 1); 4413c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 4414c965db44STomer Tayar dump, "dump-type", "idle-chk"); 4415c965db44STomer Tayar 4416c965db44STomer Tayar /* Dump idle check section header with a single parameter */ 4417c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, dump, "idle_chk", 1); 4418c965db44STomer Tayar num_failing_rules_offset = offset; 4419c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, dump, "num_rules", 0); 44207b6859fbSMintz, Yuval 4421c965db44STomer Tayar while (input_offset < 4422c965db44STomer Tayar s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES].size_in_dwords) { 4423c965db44STomer Tayar const struct dbg_idle_chk_cond_hdr *cond_hdr = 4424c965db44STomer Tayar (const struct dbg_idle_chk_cond_hdr *) 4425c965db44STomer Tayar &s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES].ptr 4426c965db44STomer Tayar [input_offset++]; 44277b6859fbSMintz, Yuval bool eval_mode, mode_match = true; 44287b6859fbSMintz, Yuval u32 curr_failing_rules; 44297b6859fbSMintz, Yuval u16 modes_buf_offset; 4430c965db44STomer Tayar 4431c965db44STomer Tayar /* Check mode */ 44327b6859fbSMintz, Yuval eval_mode = GET_FIELD(cond_hdr->mode.data, 44337b6859fbSMintz, Yuval DBG_MODE_HDR_EVAL_MODE) > 0; 4434c965db44STomer Tayar if (eval_mode) { 44357b6859fbSMintz, Yuval modes_buf_offset = 4436c965db44STomer Tayar GET_FIELD(cond_hdr->mode.data, 4437c965db44STomer Tayar DBG_MODE_HDR_MODES_BUF_OFFSET); 4438c965db44STomer Tayar mode_match = qed_is_mode_match(p_hwfn, 4439c965db44STomer Tayar &modes_buf_offset); 4440c965db44STomer Tayar } 4441c965db44STomer Tayar 4442c965db44STomer Tayar if (mode_match) { 4443c965db44STomer Tayar offset += 4444c965db44STomer Tayar qed_idle_chk_dump_rule_entries(p_hwfn, 4445c965db44STomer Tayar p_ptt, 4446c965db44STomer Tayar dump_buf + offset, 4447c965db44STomer Tayar dump, 4448c965db44STomer Tayar (const struct dbg_idle_chk_rule *) 4449c965db44STomer Tayar &s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES]. 4450c965db44STomer Tayar ptr[input_offset], 4451c965db44STomer Tayar cond_hdr->data_size / IDLE_CHK_RULE_SIZE_DWORDS, 4452c965db44STomer Tayar &curr_failing_rules); 4453c965db44STomer Tayar num_failing_rules += curr_failing_rules; 4454c965db44STomer Tayar } 4455c965db44STomer Tayar 4456c965db44STomer Tayar input_offset += cond_hdr->data_size; 4457c965db44STomer Tayar } 4458c965db44STomer Tayar 4459c965db44STomer Tayar /* Overwrite num_rules parameter */ 4460c965db44STomer Tayar if (dump) 4461c965db44STomer Tayar qed_dump_num_param(dump_buf + num_failing_rules_offset, 4462c965db44STomer Tayar dump, "num_rules", num_failing_rules); 4463c965db44STomer Tayar 44647b6859fbSMintz, Yuval /* Dump last section */ 4465da090917STomer Tayar offset += qed_dump_last_section(dump_buf, offset, dump); 44667b6859fbSMintz, Yuval 4467c965db44STomer Tayar return offset; 4468c965db44STomer Tayar } 4469c965db44STomer Tayar 44707b6859fbSMintz, Yuval /* Finds the meta data image in NVRAM */ 4471c965db44STomer Tayar static enum dbg_status qed_find_nvram_image(struct qed_hwfn *p_hwfn, 4472c965db44STomer Tayar struct qed_ptt *p_ptt, 4473c965db44STomer Tayar u32 image_type, 4474c965db44STomer Tayar u32 *nvram_offset_bytes, 4475c965db44STomer Tayar u32 *nvram_size_bytes) 4476c965db44STomer Tayar { 4477c965db44STomer Tayar u32 ret_mcp_resp, ret_mcp_param, ret_txn_size; 4478c965db44STomer Tayar struct mcp_file_att file_att; 44797b6859fbSMintz, Yuval int nvm_result; 4480c965db44STomer Tayar 4481c965db44STomer Tayar /* Call NVRAM get file command */ 44827b6859fbSMintz, Yuval nvm_result = qed_mcp_nvm_rd_cmd(p_hwfn, 4483be086e7cSMintz, Yuval p_ptt, 4484be086e7cSMintz, Yuval DRV_MSG_CODE_NVM_GET_FILE_ATT, 4485be086e7cSMintz, Yuval image_type, 4486be086e7cSMintz, Yuval &ret_mcp_resp, 4487be086e7cSMintz, Yuval &ret_mcp_param, 44887b6859fbSMintz, Yuval &ret_txn_size, (u32 *)&file_att); 4489c965db44STomer Tayar 4490c965db44STomer Tayar /* Check response */ 4491be086e7cSMintz, Yuval if (nvm_result || 4492be086e7cSMintz, Yuval (ret_mcp_resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_NVM_OK) 4493c965db44STomer Tayar return DBG_STATUS_NVRAM_GET_IMAGE_FAILED; 4494c965db44STomer Tayar 4495c965db44STomer Tayar /* Update return values */ 4496c965db44STomer Tayar *nvram_offset_bytes = file_att.nvm_start_addr; 4497c965db44STomer Tayar *nvram_size_bytes = file_att.len; 44987b6859fbSMintz, Yuval 4499c965db44STomer Tayar DP_VERBOSE(p_hwfn, 4500c965db44STomer Tayar QED_MSG_DEBUG, 4501c965db44STomer Tayar "find_nvram_image: found NVRAM image of type %d in NVRAM offset %d bytes with size %d bytes\n", 4502c965db44STomer Tayar image_type, *nvram_offset_bytes, *nvram_size_bytes); 4503c965db44STomer Tayar 4504c965db44STomer Tayar /* Check alignment */ 4505c965db44STomer Tayar if (*nvram_size_bytes & 0x3) 4506c965db44STomer Tayar return DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE; 45077b6859fbSMintz, Yuval 4508c965db44STomer Tayar return DBG_STATUS_OK; 4509c965db44STomer Tayar } 4510c965db44STomer Tayar 45117b6859fbSMintz, Yuval /* Reads data from NVRAM */ 4512c965db44STomer Tayar static enum dbg_status qed_nvram_read(struct qed_hwfn *p_hwfn, 4513c965db44STomer Tayar struct qed_ptt *p_ptt, 4514c965db44STomer Tayar u32 nvram_offset_bytes, 4515c965db44STomer Tayar u32 nvram_size_bytes, u32 *ret_buf) 4516c965db44STomer Tayar { 45177b6859fbSMintz, Yuval u32 ret_mcp_resp, ret_mcp_param, ret_read_size, bytes_to_copy; 4518c965db44STomer Tayar s32 bytes_left = nvram_size_bytes; 45197b6859fbSMintz, Yuval u32 read_offset = 0; 4520c965db44STomer Tayar 4521c965db44STomer Tayar DP_VERBOSE(p_hwfn, 4522c965db44STomer Tayar QED_MSG_DEBUG, 4523c965db44STomer Tayar "nvram_read: reading image of size %d bytes from NVRAM\n", 4524c965db44STomer Tayar nvram_size_bytes); 45257b6859fbSMintz, Yuval 4526c965db44STomer Tayar do { 4527c965db44STomer Tayar bytes_to_copy = 4528c965db44STomer Tayar (bytes_left > 4529c965db44STomer Tayar MCP_DRV_NVM_BUF_LEN) ? MCP_DRV_NVM_BUF_LEN : bytes_left; 4530c965db44STomer Tayar 4531c965db44STomer Tayar /* Call NVRAM read command */ 4532c965db44STomer Tayar if (qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 4533c965db44STomer Tayar DRV_MSG_CODE_NVM_READ_NVRAM, 4534c965db44STomer Tayar (nvram_offset_bytes + 4535c965db44STomer Tayar read_offset) | 4536c965db44STomer Tayar (bytes_to_copy << 4537da090917STomer Tayar DRV_MB_PARAM_NVM_LEN_OFFSET), 4538c965db44STomer Tayar &ret_mcp_resp, &ret_mcp_param, 4539c965db44STomer Tayar &ret_read_size, 45407b6859fbSMintz, Yuval (u32 *)((u8 *)ret_buf + read_offset))) 4541c965db44STomer Tayar return DBG_STATUS_NVRAM_READ_FAILED; 4542c965db44STomer Tayar 4543c965db44STomer Tayar /* Check response */ 4544c965db44STomer Tayar if ((ret_mcp_resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_NVM_OK) 4545c965db44STomer Tayar return DBG_STATUS_NVRAM_READ_FAILED; 4546c965db44STomer Tayar 4547c965db44STomer Tayar /* Update read offset */ 4548c965db44STomer Tayar read_offset += ret_read_size; 4549c965db44STomer Tayar bytes_left -= ret_read_size; 4550c965db44STomer Tayar } while (bytes_left > 0); 4551c965db44STomer Tayar 4552c965db44STomer Tayar return DBG_STATUS_OK; 4553c965db44STomer Tayar } 4554c965db44STomer Tayar 4555c965db44STomer Tayar /* Get info on the MCP Trace data in the scratchpad: 45567b6859fbSMintz, Yuval * - trace_data_grc_addr (OUT): trace data GRC address in bytes 45577b6859fbSMintz, Yuval * - trace_data_size (OUT): trace data size in bytes (without the header) 4558c965db44STomer Tayar */ 4559c965db44STomer Tayar static enum dbg_status qed_mcp_trace_get_data_info(struct qed_hwfn *p_hwfn, 4560c965db44STomer Tayar struct qed_ptt *p_ptt, 4561c965db44STomer Tayar u32 *trace_data_grc_addr, 45627b6859fbSMintz, Yuval u32 *trace_data_size) 4563c965db44STomer Tayar { 45647b6859fbSMintz, Yuval u32 spad_trace_offsize, signature; 4565c965db44STomer Tayar 45667b6859fbSMintz, Yuval /* Read trace section offsize structure from MCP scratchpad */ 45677b6859fbSMintz, Yuval spad_trace_offsize = qed_rd(p_hwfn, p_ptt, MCP_SPAD_TRACE_OFFSIZE_ADDR); 45687b6859fbSMintz, Yuval 45697b6859fbSMintz, Yuval /* Extract trace section address from offsize (in scratchpad) */ 4570c965db44STomer Tayar *trace_data_grc_addr = 4571c965db44STomer Tayar MCP_REG_SCRATCH + SECTION_OFFSET(spad_trace_offsize); 4572c965db44STomer Tayar 4573c965db44STomer Tayar /* Read signature from MCP trace section */ 4574c965db44STomer Tayar signature = qed_rd(p_hwfn, p_ptt, 4575c965db44STomer Tayar *trace_data_grc_addr + 4576c965db44STomer Tayar offsetof(struct mcp_trace, signature)); 45777b6859fbSMintz, Yuval 4578c965db44STomer Tayar if (signature != MFW_TRACE_SIGNATURE) 4579c965db44STomer Tayar return DBG_STATUS_INVALID_TRACE_SIGNATURE; 4580c965db44STomer Tayar 4581c965db44STomer Tayar /* Read trace size from MCP trace section */ 45827b6859fbSMintz, Yuval *trace_data_size = qed_rd(p_hwfn, 4583c965db44STomer Tayar p_ptt, 4584c965db44STomer Tayar *trace_data_grc_addr + 4585c965db44STomer Tayar offsetof(struct mcp_trace, size)); 45867b6859fbSMintz, Yuval 4587c965db44STomer Tayar return DBG_STATUS_OK; 4588c965db44STomer Tayar } 4589c965db44STomer Tayar 45907b6859fbSMintz, Yuval /* Reads MCP trace meta data image from NVRAM 45917b6859fbSMintz, Yuval * - running_bundle_id (OUT): running bundle ID (invalid when loaded from file) 45927b6859fbSMintz, Yuval * - trace_meta_offset (OUT): trace meta offset in NVRAM in bytes (invalid when 45937b6859fbSMintz, Yuval * loaded from file). 45947b6859fbSMintz, Yuval * - trace_meta_size (OUT): size in bytes of the trace meta data. 4595c965db44STomer Tayar */ 4596c965db44STomer Tayar static enum dbg_status qed_mcp_trace_get_meta_info(struct qed_hwfn *p_hwfn, 4597c965db44STomer Tayar struct qed_ptt *p_ptt, 4598c965db44STomer Tayar u32 trace_data_size_bytes, 4599c965db44STomer Tayar u32 *running_bundle_id, 46007b6859fbSMintz, Yuval u32 *trace_meta_offset, 46017b6859fbSMintz, Yuval u32 *trace_meta_size) 4602c965db44STomer Tayar { 46037b6859fbSMintz, Yuval u32 spad_trace_offsize, nvram_image_type, running_mfw_addr; 46047b6859fbSMintz, Yuval 4605c965db44STomer Tayar /* Read MCP trace section offsize structure from MCP scratchpad */ 46067b6859fbSMintz, Yuval spad_trace_offsize = qed_rd(p_hwfn, p_ptt, MCP_SPAD_TRACE_OFFSIZE_ADDR); 4607c965db44STomer Tayar 4608c965db44STomer Tayar /* Find running bundle ID */ 46097b6859fbSMintz, Yuval running_mfw_addr = 4610c965db44STomer Tayar MCP_REG_SCRATCH + SECTION_OFFSET(spad_trace_offsize) + 4611c965db44STomer Tayar QED_SECTION_SIZE(spad_trace_offsize) + trace_data_size_bytes; 4612c965db44STomer Tayar *running_bundle_id = qed_rd(p_hwfn, p_ptt, running_mfw_addr); 4613c965db44STomer Tayar if (*running_bundle_id > 1) 4614c965db44STomer Tayar return DBG_STATUS_INVALID_NVRAM_BUNDLE; 4615c965db44STomer Tayar 4616c965db44STomer Tayar /* Find image in NVRAM */ 4617c965db44STomer Tayar nvram_image_type = 4618c965db44STomer Tayar (*running_bundle_id == 4619c965db44STomer Tayar DIR_ID_1) ? NVM_TYPE_MFW_TRACE1 : NVM_TYPE_MFW_TRACE2; 4620be086e7cSMintz, Yuval return qed_find_nvram_image(p_hwfn, 4621c965db44STomer Tayar p_ptt, 4622c965db44STomer Tayar nvram_image_type, 46237b6859fbSMintz, Yuval trace_meta_offset, trace_meta_size); 4624c965db44STomer Tayar } 4625c965db44STomer Tayar 46267b6859fbSMintz, Yuval /* Reads the MCP Trace meta data from NVRAM into the specified buffer */ 4627c965db44STomer Tayar static enum dbg_status qed_mcp_trace_read_meta(struct qed_hwfn *p_hwfn, 4628c965db44STomer Tayar struct qed_ptt *p_ptt, 4629c965db44STomer Tayar u32 nvram_offset_in_bytes, 4630c965db44STomer Tayar u32 size_in_bytes, u32 *buf) 4631c965db44STomer Tayar { 46327b6859fbSMintz, Yuval u8 modules_num, module_len, i, *byte_buf = (u8 *)buf; 46337b6859fbSMintz, Yuval enum dbg_status status; 4634c965db44STomer Tayar u32 signature; 4635c965db44STomer Tayar 4636c965db44STomer Tayar /* Read meta data from NVRAM */ 46377b6859fbSMintz, Yuval status = qed_nvram_read(p_hwfn, 4638c965db44STomer Tayar p_ptt, 46397b6859fbSMintz, Yuval nvram_offset_in_bytes, size_in_bytes, buf); 4640c965db44STomer Tayar if (status != DBG_STATUS_OK) 4641c965db44STomer Tayar return status; 4642c965db44STomer Tayar 4643c965db44STomer Tayar /* Extract and check first signature */ 4644c965db44STomer Tayar signature = qed_read_unaligned_dword(byte_buf); 46457b6859fbSMintz, Yuval byte_buf += sizeof(signature); 46467b6859fbSMintz, Yuval if (signature != NVM_MAGIC_VALUE) 4647c965db44STomer Tayar return DBG_STATUS_INVALID_TRACE_SIGNATURE; 4648c965db44STomer Tayar 4649c965db44STomer Tayar /* Extract number of modules */ 4650c965db44STomer Tayar modules_num = *(byte_buf++); 4651c965db44STomer Tayar 4652c965db44STomer Tayar /* Skip all modules */ 4653c965db44STomer Tayar for (i = 0; i < modules_num; i++) { 46547b6859fbSMintz, Yuval module_len = *(byte_buf++); 4655c965db44STomer Tayar byte_buf += module_len; 4656c965db44STomer Tayar } 4657c965db44STomer Tayar 4658c965db44STomer Tayar /* Extract and check second signature */ 4659c965db44STomer Tayar signature = qed_read_unaligned_dword(byte_buf); 46607b6859fbSMintz, Yuval byte_buf += sizeof(signature); 46617b6859fbSMintz, Yuval if (signature != NVM_MAGIC_VALUE) 4662c965db44STomer Tayar return DBG_STATUS_INVALID_TRACE_SIGNATURE; 46637b6859fbSMintz, Yuval 4664c965db44STomer Tayar return DBG_STATUS_OK; 4665c965db44STomer Tayar } 4666c965db44STomer Tayar 4667c965db44STomer Tayar /* Dump MCP Trace */ 46688c93beafSYuval Mintz static enum dbg_status qed_mcp_trace_dump(struct qed_hwfn *p_hwfn, 4669c965db44STomer Tayar struct qed_ptt *p_ptt, 4670c965db44STomer Tayar u32 *dump_buf, 4671c965db44STomer Tayar bool dump, u32 *num_dumped_dwords) 4672c965db44STomer Tayar { 4673c965db44STomer Tayar u32 trace_data_grc_addr, trace_data_size_bytes, trace_data_size_dwords; 4674be086e7cSMintz, Yuval u32 trace_meta_size_dwords = 0, running_bundle_id, offset = 0; 4675be086e7cSMintz, Yuval u32 trace_meta_offset_bytes = 0, trace_meta_size_bytes = 0; 4676c965db44STomer Tayar enum dbg_status status; 4677be086e7cSMintz, Yuval bool mcp_access; 4678c965db44STomer Tayar int halted = 0; 4679c965db44STomer Tayar 4680c965db44STomer Tayar *num_dumped_dwords = 0; 4681c965db44STomer Tayar 46827b6859fbSMintz, Yuval mcp_access = !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_MCP); 46837b6859fbSMintz, Yuval 4684c965db44STomer Tayar /* Get trace data info */ 4685c965db44STomer Tayar status = qed_mcp_trace_get_data_info(p_hwfn, 4686c965db44STomer Tayar p_ptt, 4687c965db44STomer Tayar &trace_data_grc_addr, 4688c965db44STomer Tayar &trace_data_size_bytes); 4689c965db44STomer Tayar if (status != DBG_STATUS_OK) 4690c965db44STomer Tayar return status; 4691c965db44STomer Tayar 4692c965db44STomer Tayar /* Dump global params */ 4693c965db44STomer Tayar offset += qed_dump_common_global_params(p_hwfn, 4694c965db44STomer Tayar p_ptt, 4695c965db44STomer Tayar dump_buf + offset, dump, 1); 4696c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 4697c965db44STomer Tayar dump, "dump-type", "mcp-trace"); 4698c965db44STomer Tayar 4699c965db44STomer Tayar /* Halt MCP while reading from scratchpad so the read data will be 47007b6859fbSMintz, Yuval * consistent. if halt fails, MCP trace is taken anyway, with a small 4701c965db44STomer Tayar * risk that it may be corrupt. 4702c965db44STomer Tayar */ 4703be086e7cSMintz, Yuval if (dump && mcp_access) { 4704c965db44STomer Tayar halted = !qed_mcp_halt(p_hwfn, p_ptt); 4705c965db44STomer Tayar if (!halted) 4706c965db44STomer Tayar DP_NOTICE(p_hwfn, "MCP halt failed!\n"); 4707c965db44STomer Tayar } 4708c965db44STomer Tayar 4709c965db44STomer Tayar /* Find trace data size */ 4710c965db44STomer Tayar trace_data_size_dwords = 4711c965db44STomer Tayar DIV_ROUND_UP(trace_data_size_bytes + sizeof(struct mcp_trace), 4712c965db44STomer Tayar BYTES_IN_DWORD); 4713c965db44STomer Tayar 4714c965db44STomer Tayar /* Dump trace data section header and param */ 4715c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, 4716c965db44STomer Tayar dump, "mcp_trace_data", 1); 4717c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 4718c965db44STomer Tayar dump, "size", trace_data_size_dwords); 4719c965db44STomer Tayar 4720c965db44STomer Tayar /* Read trace data from scratchpad into dump buffer */ 4721be086e7cSMintz, Yuval offset += qed_grc_dump_addr_range(p_hwfn, 4722c965db44STomer Tayar p_ptt, 4723be086e7cSMintz, Yuval dump_buf + offset, 4724be086e7cSMintz, Yuval dump, 4725be086e7cSMintz, Yuval BYTES_TO_DWORDS(trace_data_grc_addr), 47267b6859fbSMintz, Yuval trace_data_size_dwords, false); 4727c965db44STomer Tayar 4728c965db44STomer Tayar /* Resume MCP (only if halt succeeded) */ 47297b6859fbSMintz, Yuval if (halted && qed_mcp_resume(p_hwfn, p_ptt)) 4730c965db44STomer Tayar DP_NOTICE(p_hwfn, "Failed to resume MCP after halt!\n"); 4731c965db44STomer Tayar 4732c965db44STomer Tayar /* Dump trace meta section header */ 4733c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, 4734c965db44STomer Tayar dump, "mcp_trace_meta", 1); 4735c965db44STomer Tayar 47367b6859fbSMintz, Yuval /* Read trace meta info (trace_meta_size_bytes is dword-aligned) */ 4737be086e7cSMintz, Yuval if (mcp_access) { 4738c965db44STomer Tayar status = qed_mcp_trace_get_meta_info(p_hwfn, 4739c965db44STomer Tayar p_ptt, 4740c965db44STomer Tayar trace_data_size_bytes, 4741c965db44STomer Tayar &running_bundle_id, 4742c965db44STomer Tayar &trace_meta_offset_bytes, 4743c965db44STomer Tayar &trace_meta_size_bytes); 4744be086e7cSMintz, Yuval if (status == DBG_STATUS_OK) 4745be086e7cSMintz, Yuval trace_meta_size_dwords = 4746be086e7cSMintz, Yuval BYTES_TO_DWORDS(trace_meta_size_bytes); 4747be086e7cSMintz, Yuval } 4748c965db44STomer Tayar 4749be086e7cSMintz, Yuval /* Dump trace meta size param */ 4750be086e7cSMintz, Yuval offset += qed_dump_num_param(dump_buf + offset, 4751be086e7cSMintz, Yuval dump, "size", trace_meta_size_dwords); 4752c965db44STomer Tayar 4753c965db44STomer Tayar /* Read trace meta image into dump buffer */ 4754be086e7cSMintz, Yuval if (dump && trace_meta_size_dwords) 4755c965db44STomer Tayar status = qed_mcp_trace_read_meta(p_hwfn, 4756c965db44STomer Tayar p_ptt, 4757c965db44STomer Tayar trace_meta_offset_bytes, 4758c965db44STomer Tayar trace_meta_size_bytes, 4759c965db44STomer Tayar dump_buf + offset); 4760be086e7cSMintz, Yuval if (status == DBG_STATUS_OK) 4761c965db44STomer Tayar offset += trace_meta_size_dwords; 4762c965db44STomer Tayar 47637b6859fbSMintz, Yuval /* Dump last section */ 4764da090917STomer Tayar offset += qed_dump_last_section(dump_buf, offset, dump); 47657b6859fbSMintz, Yuval 4766c965db44STomer Tayar *num_dumped_dwords = offset; 4767c965db44STomer Tayar 4768be086e7cSMintz, Yuval /* If no mcp access, indicate that the dump doesn't contain the meta 4769be086e7cSMintz, Yuval * data from NVRAM. 4770be086e7cSMintz, Yuval */ 4771be086e7cSMintz, Yuval return mcp_access ? status : DBG_STATUS_NVRAM_GET_IMAGE_FAILED; 4772c965db44STomer Tayar } 4773c965db44STomer Tayar 4774c965db44STomer Tayar /* Dump GRC FIFO */ 47758c93beafSYuval Mintz static enum dbg_status qed_reg_fifo_dump(struct qed_hwfn *p_hwfn, 4776c965db44STomer Tayar struct qed_ptt *p_ptt, 4777c965db44STomer Tayar u32 *dump_buf, 4778c965db44STomer Tayar bool dump, u32 *num_dumped_dwords) 4779c965db44STomer Tayar { 4780da090917STomer Tayar u32 dwords_read, size_param_offset, offset = 0, addr, len; 4781c965db44STomer Tayar bool fifo_has_data; 4782c965db44STomer Tayar 4783c965db44STomer Tayar *num_dumped_dwords = 0; 4784c965db44STomer Tayar 4785c965db44STomer Tayar /* Dump global params */ 4786c965db44STomer Tayar offset += qed_dump_common_global_params(p_hwfn, 4787c965db44STomer Tayar p_ptt, 4788c965db44STomer Tayar dump_buf + offset, dump, 1); 4789c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 4790c965db44STomer Tayar dump, "dump-type", "reg-fifo"); 4791c965db44STomer Tayar 47927b6859fbSMintz, Yuval /* Dump fifo data section header and param. The size param is 0 for 47937b6859fbSMintz, Yuval * now, and is overwritten after reading the FIFO. 4794c965db44STomer Tayar */ 4795c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, 4796c965db44STomer Tayar dump, "reg_fifo_data", 1); 4797c965db44STomer Tayar size_param_offset = offset; 4798c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, dump, "size", 0); 4799c965db44STomer Tayar 4800c965db44STomer Tayar if (!dump) { 4801c965db44STomer Tayar /* FIFO max size is REG_FIFO_DEPTH_DWORDS. There is no way to 4802c965db44STomer Tayar * test how much data is available, except for reading it. 4803c965db44STomer Tayar */ 4804c965db44STomer Tayar offset += REG_FIFO_DEPTH_DWORDS; 48057b6859fbSMintz, Yuval goto out; 4806c965db44STomer Tayar } 4807c965db44STomer Tayar 4808c965db44STomer Tayar fifo_has_data = qed_rd(p_hwfn, p_ptt, 4809c965db44STomer Tayar GRC_REG_TRACE_FIFO_VALID_DATA) > 0; 4810c965db44STomer Tayar 4811c965db44STomer Tayar /* Pull available data from fifo. Use DMAE since this is widebus memory 4812c965db44STomer Tayar * and must be accessed atomically. Test for dwords_read not passing 4813c965db44STomer Tayar * buffer size since more entries could be added to the buffer as we are 4814c965db44STomer Tayar * emptying it. 4815c965db44STomer Tayar */ 4816da090917STomer Tayar addr = BYTES_TO_DWORDS(GRC_REG_TRACE_FIFO); 4817da090917STomer Tayar len = REG_FIFO_ELEMENT_DWORDS; 4818c965db44STomer Tayar for (dwords_read = 0; 4819c965db44STomer Tayar fifo_has_data && dwords_read < REG_FIFO_DEPTH_DWORDS; 4820da090917STomer Tayar dwords_read += REG_FIFO_ELEMENT_DWORDS) { 4821da090917STomer Tayar offset += qed_grc_dump_addr_range(p_hwfn, 4822da090917STomer Tayar p_ptt, 4823da090917STomer Tayar dump_buf + offset, 4824da090917STomer Tayar true, 4825da090917STomer Tayar addr, 4826da090917STomer Tayar len, 4827da090917STomer Tayar true); 4828c965db44STomer Tayar fifo_has_data = qed_rd(p_hwfn, p_ptt, 4829c965db44STomer Tayar GRC_REG_TRACE_FIFO_VALID_DATA) > 0; 4830c965db44STomer Tayar } 4831c965db44STomer Tayar 4832c965db44STomer Tayar qed_dump_num_param(dump_buf + size_param_offset, dump, "size", 4833c965db44STomer Tayar dwords_read); 48347b6859fbSMintz, Yuval out: 48357b6859fbSMintz, Yuval /* Dump last section */ 4836da090917STomer Tayar offset += qed_dump_last_section(dump_buf, offset, dump); 4837c965db44STomer Tayar 4838c965db44STomer Tayar *num_dumped_dwords = offset; 48397b6859fbSMintz, Yuval 4840c965db44STomer Tayar return DBG_STATUS_OK; 4841c965db44STomer Tayar } 4842c965db44STomer Tayar 4843c965db44STomer Tayar /* Dump IGU FIFO */ 48448c93beafSYuval Mintz static enum dbg_status qed_igu_fifo_dump(struct qed_hwfn *p_hwfn, 4845c965db44STomer Tayar struct qed_ptt *p_ptt, 4846c965db44STomer Tayar u32 *dump_buf, 4847c965db44STomer Tayar bool dump, u32 *num_dumped_dwords) 4848c965db44STomer Tayar { 4849da090917STomer Tayar u32 dwords_read, size_param_offset, offset = 0, addr, len; 4850c965db44STomer Tayar bool fifo_has_data; 4851c965db44STomer Tayar 4852c965db44STomer Tayar *num_dumped_dwords = 0; 4853c965db44STomer Tayar 4854c965db44STomer Tayar /* Dump global params */ 4855c965db44STomer Tayar offset += qed_dump_common_global_params(p_hwfn, 4856c965db44STomer Tayar p_ptt, 4857c965db44STomer Tayar dump_buf + offset, dump, 1); 4858c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 4859c965db44STomer Tayar dump, "dump-type", "igu-fifo"); 4860c965db44STomer Tayar 48617b6859fbSMintz, Yuval /* Dump fifo data section header and param. The size param is 0 for 48627b6859fbSMintz, Yuval * now, and is overwritten after reading the FIFO. 4863c965db44STomer Tayar */ 4864c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, 4865c965db44STomer Tayar dump, "igu_fifo_data", 1); 4866c965db44STomer Tayar size_param_offset = offset; 4867c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, dump, "size", 0); 4868c965db44STomer Tayar 4869c965db44STomer Tayar if (!dump) { 4870c965db44STomer Tayar /* FIFO max size is IGU_FIFO_DEPTH_DWORDS. There is no way to 4871c965db44STomer Tayar * test how much data is available, except for reading it. 4872c965db44STomer Tayar */ 4873c965db44STomer Tayar offset += IGU_FIFO_DEPTH_DWORDS; 48747b6859fbSMintz, Yuval goto out; 4875c965db44STomer Tayar } 4876c965db44STomer Tayar 4877c965db44STomer Tayar fifo_has_data = qed_rd(p_hwfn, p_ptt, 4878c965db44STomer Tayar IGU_REG_ERROR_HANDLING_DATA_VALID) > 0; 4879c965db44STomer Tayar 4880c965db44STomer Tayar /* Pull available data from fifo. Use DMAE since this is widebus memory 4881c965db44STomer Tayar * and must be accessed atomically. Test for dwords_read not passing 4882c965db44STomer Tayar * buffer size since more entries could be added to the buffer as we are 4883c965db44STomer Tayar * emptying it. 4884c965db44STomer Tayar */ 4885da090917STomer Tayar addr = BYTES_TO_DWORDS(IGU_REG_ERROR_HANDLING_MEMORY); 4886da090917STomer Tayar len = IGU_FIFO_ELEMENT_DWORDS; 4887c965db44STomer Tayar for (dwords_read = 0; 4888c965db44STomer Tayar fifo_has_data && dwords_read < IGU_FIFO_DEPTH_DWORDS; 4889da090917STomer Tayar dwords_read += IGU_FIFO_ELEMENT_DWORDS) { 4890da090917STomer Tayar offset += qed_grc_dump_addr_range(p_hwfn, 4891da090917STomer Tayar p_ptt, 4892da090917STomer Tayar dump_buf + offset, 4893da090917STomer Tayar true, 4894da090917STomer Tayar addr, 4895da090917STomer Tayar len, 4896da090917STomer Tayar true); 4897c965db44STomer Tayar fifo_has_data = qed_rd(p_hwfn, p_ptt, 4898c965db44STomer Tayar IGU_REG_ERROR_HANDLING_DATA_VALID) > 0; 4899c965db44STomer Tayar } 4900c965db44STomer Tayar 4901c965db44STomer Tayar qed_dump_num_param(dump_buf + size_param_offset, dump, "size", 4902c965db44STomer Tayar dwords_read); 49037b6859fbSMintz, Yuval out: 49047b6859fbSMintz, Yuval /* Dump last section */ 4905da090917STomer Tayar offset += qed_dump_last_section(dump_buf, offset, dump); 4906c965db44STomer Tayar 4907c965db44STomer Tayar *num_dumped_dwords = offset; 49087b6859fbSMintz, Yuval 4909c965db44STomer Tayar return DBG_STATUS_OK; 4910c965db44STomer Tayar } 4911c965db44STomer Tayar 4912c965db44STomer Tayar /* Protection Override dump */ 49138c93beafSYuval Mintz static enum dbg_status qed_protection_override_dump(struct qed_hwfn *p_hwfn, 4914c965db44STomer Tayar struct qed_ptt *p_ptt, 4915c965db44STomer Tayar u32 *dump_buf, 49168c93beafSYuval Mintz bool dump, 49178c93beafSYuval Mintz u32 *num_dumped_dwords) 4918c965db44STomer Tayar { 4919da090917STomer Tayar u32 size_param_offset, override_window_dwords, offset = 0, addr; 4920c965db44STomer Tayar 4921c965db44STomer Tayar *num_dumped_dwords = 0; 4922c965db44STomer Tayar 4923c965db44STomer Tayar /* Dump global params */ 4924c965db44STomer Tayar offset += qed_dump_common_global_params(p_hwfn, 4925c965db44STomer Tayar p_ptt, 4926c965db44STomer Tayar dump_buf + offset, dump, 1); 4927c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 4928c965db44STomer Tayar dump, "dump-type", "protection-override"); 4929c965db44STomer Tayar 49307b6859fbSMintz, Yuval /* Dump data section header and param. The size param is 0 for now, 49317b6859fbSMintz, Yuval * and is overwritten after reading the data. 4932c965db44STomer Tayar */ 4933c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, 4934c965db44STomer Tayar dump, "protection_override_data", 1); 4935c965db44STomer Tayar size_param_offset = offset; 4936c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, dump, "size", 0); 4937c965db44STomer Tayar 4938c965db44STomer Tayar if (!dump) { 4939c965db44STomer Tayar offset += PROTECTION_OVERRIDE_DEPTH_DWORDS; 49407b6859fbSMintz, Yuval goto out; 4941c965db44STomer Tayar } 4942c965db44STomer Tayar 4943c965db44STomer Tayar /* Add override window info to buffer */ 4944c965db44STomer Tayar override_window_dwords = 4945da090917STomer Tayar qed_rd(p_hwfn, p_ptt, GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW) * 4946c965db44STomer Tayar PROTECTION_OVERRIDE_ELEMENT_DWORDS; 4947da090917STomer Tayar addr = BYTES_TO_DWORDS(GRC_REG_PROTECTION_OVERRIDE_WINDOW); 4948da090917STomer Tayar offset += qed_grc_dump_addr_range(p_hwfn, 4949da090917STomer Tayar p_ptt, 4950da090917STomer Tayar dump_buf + offset, 4951da090917STomer Tayar true, 4952da090917STomer Tayar addr, 4953da090917STomer Tayar override_window_dwords, 4954da090917STomer Tayar true); 4955c965db44STomer Tayar qed_dump_num_param(dump_buf + size_param_offset, dump, "size", 4956c965db44STomer Tayar override_window_dwords); 49577b6859fbSMintz, Yuval out: 49587b6859fbSMintz, Yuval /* Dump last section */ 4959da090917STomer Tayar offset += qed_dump_last_section(dump_buf, offset, dump); 4960c965db44STomer Tayar 4961c965db44STomer Tayar *num_dumped_dwords = offset; 49627b6859fbSMintz, Yuval 4963c965db44STomer Tayar return DBG_STATUS_OK; 4964c965db44STomer Tayar } 4965c965db44STomer Tayar 4966c965db44STomer Tayar /* Performs FW Asserts Dump to the specified buffer. 4967c965db44STomer Tayar * Returns the dumped size in dwords. 4968c965db44STomer Tayar */ 4969c965db44STomer Tayar static u32 qed_fw_asserts_dump(struct qed_hwfn *p_hwfn, 4970c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *dump_buf, bool dump) 4971c965db44STomer Tayar { 4972c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 4973be086e7cSMintz, Yuval struct fw_asserts_ram_section *asserts; 4974c965db44STomer Tayar char storm_letter_str[2] = "?"; 4975c965db44STomer Tayar struct fw_info fw_info; 4976be086e7cSMintz, Yuval u32 offset = 0; 4977c965db44STomer Tayar u8 storm_id; 4978c965db44STomer Tayar 4979c965db44STomer Tayar /* Dump global params */ 4980c965db44STomer Tayar offset += qed_dump_common_global_params(p_hwfn, 4981c965db44STomer Tayar p_ptt, 4982c965db44STomer Tayar dump_buf + offset, dump, 1); 4983c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 4984c965db44STomer Tayar dump, "dump-type", "fw-asserts"); 49857b6859fbSMintz, Yuval 49867b6859fbSMintz, Yuval /* Find Storm dump size */ 4987c965db44STomer Tayar for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 4988be086e7cSMintz, Yuval u32 fw_asserts_section_addr, next_list_idx_addr, next_list_idx; 49897b6859fbSMintz, Yuval struct storm_defs *storm = &s_storm_defs[storm_id]; 4990be086e7cSMintz, Yuval u32 last_list_idx, addr; 4991c965db44STomer Tayar 49927b6859fbSMintz, Yuval if (dev_data->block_in_reset[storm->block_id]) 4993c965db44STomer Tayar continue; 4994c965db44STomer Tayar 4995c965db44STomer Tayar /* Read FW info for the current Storm */ 4996c965db44STomer Tayar qed_read_fw_info(p_hwfn, p_ptt, storm_id, &fw_info); 4997c965db44STomer Tayar 4998be086e7cSMintz, Yuval asserts = &fw_info.fw_asserts_section; 4999be086e7cSMintz, Yuval 5000c965db44STomer Tayar /* Dump FW Asserts section header and params */ 50017b6859fbSMintz, Yuval storm_letter_str[0] = storm->letter; 50027b6859fbSMintz, Yuval offset += qed_dump_section_hdr(dump_buf + offset, 50037b6859fbSMintz, Yuval dump, "fw_asserts", 2); 50047b6859fbSMintz, Yuval offset += qed_dump_str_param(dump_buf + offset, 50057b6859fbSMintz, Yuval dump, "storm", storm_letter_str); 50067b6859fbSMintz, Yuval offset += qed_dump_num_param(dump_buf + offset, 50077b6859fbSMintz, Yuval dump, 50087b6859fbSMintz, Yuval "size", 5009be086e7cSMintz, Yuval asserts->list_element_dword_size); 5010c965db44STomer Tayar 50117b6859fbSMintz, Yuval /* Read and dump FW Asserts data */ 5012c965db44STomer Tayar if (!dump) { 5013be086e7cSMintz, Yuval offset += asserts->list_element_dword_size; 5014c965db44STomer Tayar continue; 5015c965db44STomer Tayar } 5016c965db44STomer Tayar 50177b6859fbSMintz, Yuval fw_asserts_section_addr = storm->sem_fast_mem_addr + 5018c965db44STomer Tayar SEM_FAST_REG_INT_RAM + 5019be086e7cSMintz, Yuval RAM_LINES_TO_BYTES(asserts->section_ram_line_offset); 50207b6859fbSMintz, Yuval next_list_idx_addr = fw_asserts_section_addr + 5021be086e7cSMintz, Yuval DWORDS_TO_BYTES(asserts->list_next_index_dword_offset); 5022c965db44STomer Tayar next_list_idx = qed_rd(p_hwfn, p_ptt, next_list_idx_addr); 5023da090917STomer Tayar last_list_idx = (next_list_idx > 0 ? 5024da090917STomer Tayar next_list_idx : 5025da090917STomer Tayar asserts->list_num_elements) - 1; 5026be086e7cSMintz, Yuval addr = BYTES_TO_DWORDS(fw_asserts_section_addr) + 5027be086e7cSMintz, Yuval asserts->list_dword_offset + 5028be086e7cSMintz, Yuval last_list_idx * asserts->list_element_dword_size; 5029be086e7cSMintz, Yuval offset += 5030be086e7cSMintz, Yuval qed_grc_dump_addr_range(p_hwfn, p_ptt, 5031be086e7cSMintz, Yuval dump_buf + offset, 5032be086e7cSMintz, Yuval dump, addr, 50337b6859fbSMintz, Yuval asserts->list_element_dword_size, 50347b6859fbSMintz, Yuval false); 5035c965db44STomer Tayar } 5036c965db44STomer Tayar 5037c965db44STomer Tayar /* Dump last section */ 5038da090917STomer Tayar offset += qed_dump_last_section(dump_buf, offset, dump); 50397b6859fbSMintz, Yuval 5040c965db44STomer Tayar return offset; 5041c965db44STomer Tayar } 5042c965db44STomer Tayar 5043c965db44STomer Tayar /***************************** Public Functions *******************************/ 5044c965db44STomer Tayar 5045c965db44STomer Tayar enum dbg_status qed_dbg_set_bin_ptr(const u8 * const bin_ptr) 5046c965db44STomer Tayar { 5047be086e7cSMintz, Yuval struct bin_buffer_hdr *buf_array = (struct bin_buffer_hdr *)bin_ptr; 5048c965db44STomer Tayar u8 buf_id; 5049c965db44STomer Tayar 50507b6859fbSMintz, Yuval /* convert binary data to debug arrays */ 5051be086e7cSMintz, Yuval for (buf_id = 0; buf_id < MAX_BIN_DBG_BUFFER_TYPE; buf_id++) { 5052c965db44STomer Tayar s_dbg_arrays[buf_id].ptr = 5053c965db44STomer Tayar (u32 *)(bin_ptr + buf_array[buf_id].offset); 5054c965db44STomer Tayar s_dbg_arrays[buf_id].size_in_dwords = 5055c965db44STomer Tayar BYTES_TO_DWORDS(buf_array[buf_id].length); 5056c965db44STomer Tayar } 5057c965db44STomer Tayar 5058c965db44STomer Tayar return DBG_STATUS_OK; 5059c965db44STomer Tayar } 5060c965db44STomer Tayar 5061be086e7cSMintz, Yuval /* Assign default GRC param values */ 5062be086e7cSMintz, Yuval void qed_dbg_grc_set_params_default(struct qed_hwfn *p_hwfn) 5063be086e7cSMintz, Yuval { 5064be086e7cSMintz, Yuval struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5065be086e7cSMintz, Yuval u32 i; 5066be086e7cSMintz, Yuval 5067be086e7cSMintz, Yuval for (i = 0; i < MAX_DBG_GRC_PARAMS; i++) 5068be086e7cSMintz, Yuval dev_data->grc.param_val[i] = 5069be086e7cSMintz, Yuval s_grc_param_defs[i].default_val[dev_data->chip_id]; 5070be086e7cSMintz, Yuval } 5071be086e7cSMintz, Yuval 5072c965db44STomer Tayar enum dbg_status qed_dbg_grc_get_dump_buf_size(struct qed_hwfn *p_hwfn, 5073c965db44STomer Tayar struct qed_ptt *p_ptt, 5074c965db44STomer Tayar u32 *buf_size) 5075c965db44STomer Tayar { 5076c965db44STomer Tayar enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt); 5077c965db44STomer Tayar 5078c965db44STomer Tayar *buf_size = 0; 50797b6859fbSMintz, Yuval 5080c965db44STomer Tayar if (status != DBG_STATUS_OK) 5081c965db44STomer Tayar return status; 50827b6859fbSMintz, Yuval 5083c965db44STomer Tayar if (!s_dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr || 5084c965db44STomer Tayar !s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].ptr || 5085c965db44STomer Tayar !s_dbg_arrays[BIN_BUF_DBG_DUMP_MEM].ptr || 5086c965db44STomer Tayar !s_dbg_arrays[BIN_BUF_DBG_ATTN_BLOCKS].ptr || 5087c965db44STomer Tayar !s_dbg_arrays[BIN_BUF_DBG_ATTN_REGS].ptr) 5088c965db44STomer Tayar return DBG_STATUS_DBG_ARRAY_NOT_SET; 50897b6859fbSMintz, Yuval 5090c965db44STomer Tayar return qed_grc_dump(p_hwfn, p_ptt, NULL, false, buf_size); 5091c965db44STomer Tayar } 5092c965db44STomer Tayar 5093c965db44STomer Tayar enum dbg_status qed_dbg_grc_dump(struct qed_hwfn *p_hwfn, 5094c965db44STomer Tayar struct qed_ptt *p_ptt, 5095c965db44STomer Tayar u32 *dump_buf, 5096c965db44STomer Tayar u32 buf_size_in_dwords, 5097c965db44STomer Tayar u32 *num_dumped_dwords) 5098c965db44STomer Tayar { 5099c965db44STomer Tayar u32 needed_buf_size_in_dwords; 5100c965db44STomer Tayar enum dbg_status status; 5101c965db44STomer Tayar 5102c965db44STomer Tayar *num_dumped_dwords = 0; 51037b6859fbSMintz, Yuval 51047b6859fbSMintz, Yuval status = qed_dbg_grc_get_dump_buf_size(p_hwfn, 51057b6859fbSMintz, Yuval p_ptt, 51067b6859fbSMintz, Yuval &needed_buf_size_in_dwords); 5107c965db44STomer Tayar if (status != DBG_STATUS_OK) 5108c965db44STomer Tayar return status; 51097b6859fbSMintz, Yuval 5110c965db44STomer Tayar if (buf_size_in_dwords < needed_buf_size_in_dwords) 5111c965db44STomer Tayar return DBG_STATUS_DUMP_BUF_TOO_SMALL; 5112c965db44STomer Tayar 5113c965db44STomer Tayar /* GRC Dump */ 5114c965db44STomer Tayar status = qed_grc_dump(p_hwfn, p_ptt, dump_buf, true, num_dumped_dwords); 5115c965db44STomer Tayar 5116be086e7cSMintz, Yuval /* Revert GRC params to their default */ 5117be086e7cSMintz, Yuval qed_dbg_grc_set_params_default(p_hwfn); 5118be086e7cSMintz, Yuval 5119c965db44STomer Tayar return status; 5120c965db44STomer Tayar } 5121c965db44STomer Tayar 5122c965db44STomer Tayar enum dbg_status qed_dbg_idle_chk_get_dump_buf_size(struct qed_hwfn *p_hwfn, 5123c965db44STomer Tayar struct qed_ptt *p_ptt, 5124c965db44STomer Tayar u32 *buf_size) 5125c965db44STomer Tayar { 5126c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 51277b6859fbSMintz, Yuval struct idle_chk_data *idle_chk; 51287b6859fbSMintz, Yuval enum dbg_status status; 5129c965db44STomer Tayar 51307b6859fbSMintz, Yuval idle_chk = &dev_data->idle_chk; 5131c965db44STomer Tayar *buf_size = 0; 51327b6859fbSMintz, Yuval 51337b6859fbSMintz, Yuval status = qed_dbg_dev_init(p_hwfn, p_ptt); 5134c965db44STomer Tayar if (status != DBG_STATUS_OK) 5135c965db44STomer Tayar return status; 51367b6859fbSMintz, Yuval 5137c965db44STomer Tayar if (!s_dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr || 5138c965db44STomer Tayar !s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_REGS].ptr || 5139c965db44STomer Tayar !s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_IMMS].ptr || 5140c965db44STomer Tayar !s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES].ptr) 5141c965db44STomer Tayar return DBG_STATUS_DBG_ARRAY_NOT_SET; 51427b6859fbSMintz, Yuval 51437b6859fbSMintz, Yuval if (!idle_chk->buf_size_set) { 51447b6859fbSMintz, Yuval idle_chk->buf_size = qed_idle_chk_dump(p_hwfn, 51457b6859fbSMintz, Yuval p_ptt, NULL, false); 51467b6859fbSMintz, Yuval idle_chk->buf_size_set = true; 5147c965db44STomer Tayar } 5148c965db44STomer Tayar 51497b6859fbSMintz, Yuval *buf_size = idle_chk->buf_size; 51507b6859fbSMintz, Yuval 5151c965db44STomer Tayar return DBG_STATUS_OK; 5152c965db44STomer Tayar } 5153c965db44STomer Tayar 5154c965db44STomer Tayar enum dbg_status qed_dbg_idle_chk_dump(struct qed_hwfn *p_hwfn, 5155c965db44STomer Tayar struct qed_ptt *p_ptt, 5156c965db44STomer Tayar u32 *dump_buf, 5157c965db44STomer Tayar u32 buf_size_in_dwords, 5158c965db44STomer Tayar u32 *num_dumped_dwords) 5159c965db44STomer Tayar { 5160c965db44STomer Tayar u32 needed_buf_size_in_dwords; 5161c965db44STomer Tayar enum dbg_status status; 5162c965db44STomer Tayar 5163c965db44STomer Tayar *num_dumped_dwords = 0; 51647b6859fbSMintz, Yuval 51657b6859fbSMintz, Yuval status = qed_dbg_idle_chk_get_dump_buf_size(p_hwfn, 51667b6859fbSMintz, Yuval p_ptt, 51677b6859fbSMintz, Yuval &needed_buf_size_in_dwords); 5168c965db44STomer Tayar if (status != DBG_STATUS_OK) 5169c965db44STomer Tayar return status; 51707b6859fbSMintz, Yuval 5171c965db44STomer Tayar if (buf_size_in_dwords < needed_buf_size_in_dwords) 5172c965db44STomer Tayar return DBG_STATUS_DUMP_BUF_TOO_SMALL; 5173c965db44STomer Tayar 5174c965db44STomer Tayar /* Update reset state */ 5175c965db44STomer Tayar qed_update_blocks_reset_state(p_hwfn, p_ptt); 5176c965db44STomer Tayar 5177c965db44STomer Tayar /* Idle Check Dump */ 5178c965db44STomer Tayar *num_dumped_dwords = qed_idle_chk_dump(p_hwfn, p_ptt, dump_buf, true); 5179be086e7cSMintz, Yuval 5180be086e7cSMintz, Yuval /* Revert GRC params to their default */ 5181be086e7cSMintz, Yuval qed_dbg_grc_set_params_default(p_hwfn); 5182be086e7cSMintz, Yuval 5183c965db44STomer Tayar return DBG_STATUS_OK; 5184c965db44STomer Tayar } 5185c965db44STomer Tayar 5186c965db44STomer Tayar enum dbg_status qed_dbg_mcp_trace_get_dump_buf_size(struct qed_hwfn *p_hwfn, 5187c965db44STomer Tayar struct qed_ptt *p_ptt, 5188c965db44STomer Tayar u32 *buf_size) 5189c965db44STomer Tayar { 5190c965db44STomer Tayar enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt); 5191c965db44STomer Tayar 5192c965db44STomer Tayar *buf_size = 0; 51937b6859fbSMintz, Yuval 5194c965db44STomer Tayar if (status != DBG_STATUS_OK) 5195c965db44STomer Tayar return status; 51967b6859fbSMintz, Yuval 5197c965db44STomer Tayar return qed_mcp_trace_dump(p_hwfn, p_ptt, NULL, false, buf_size); 5198c965db44STomer Tayar } 5199c965db44STomer Tayar 5200c965db44STomer Tayar enum dbg_status qed_dbg_mcp_trace_dump(struct qed_hwfn *p_hwfn, 5201c965db44STomer Tayar struct qed_ptt *p_ptt, 5202c965db44STomer Tayar u32 *dump_buf, 5203c965db44STomer Tayar u32 buf_size_in_dwords, 5204c965db44STomer Tayar u32 *num_dumped_dwords) 5205c965db44STomer Tayar { 5206c965db44STomer Tayar u32 needed_buf_size_in_dwords; 5207c965db44STomer Tayar enum dbg_status status; 5208c965db44STomer Tayar 5209be086e7cSMintz, Yuval status = 52107b6859fbSMintz, Yuval qed_dbg_mcp_trace_get_dump_buf_size(p_hwfn, 52117b6859fbSMintz, Yuval p_ptt, 5212c965db44STomer Tayar &needed_buf_size_in_dwords); 52137b6859fbSMintz, Yuval if (status != DBG_STATUS_OK && status != 52147b6859fbSMintz, Yuval DBG_STATUS_NVRAM_GET_IMAGE_FAILED) 5215c965db44STomer Tayar return status; 5216be086e7cSMintz, Yuval 5217c965db44STomer Tayar if (buf_size_in_dwords < needed_buf_size_in_dwords) 5218c965db44STomer Tayar return DBG_STATUS_DUMP_BUF_TOO_SMALL; 5219c965db44STomer Tayar 5220c965db44STomer Tayar /* Update reset state */ 5221c965db44STomer Tayar qed_update_blocks_reset_state(p_hwfn, p_ptt); 5222c965db44STomer Tayar 5223c965db44STomer Tayar /* Perform dump */ 5224be086e7cSMintz, Yuval status = qed_mcp_trace_dump(p_hwfn, 5225c965db44STomer Tayar p_ptt, dump_buf, true, num_dumped_dwords); 5226be086e7cSMintz, Yuval 5227be086e7cSMintz, Yuval /* Revert GRC params to their default */ 5228be086e7cSMintz, Yuval qed_dbg_grc_set_params_default(p_hwfn); 5229be086e7cSMintz, Yuval 5230be086e7cSMintz, Yuval return status; 5231c965db44STomer Tayar } 5232c965db44STomer Tayar 5233c965db44STomer Tayar enum dbg_status qed_dbg_reg_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn, 5234c965db44STomer Tayar struct qed_ptt *p_ptt, 5235c965db44STomer Tayar u32 *buf_size) 5236c965db44STomer Tayar { 5237c965db44STomer Tayar enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt); 5238c965db44STomer Tayar 5239c965db44STomer Tayar *buf_size = 0; 52407b6859fbSMintz, Yuval 5241c965db44STomer Tayar if (status != DBG_STATUS_OK) 5242c965db44STomer Tayar return status; 52437b6859fbSMintz, Yuval 5244c965db44STomer Tayar return qed_reg_fifo_dump(p_hwfn, p_ptt, NULL, false, buf_size); 5245c965db44STomer Tayar } 5246c965db44STomer Tayar 5247c965db44STomer Tayar enum dbg_status qed_dbg_reg_fifo_dump(struct qed_hwfn *p_hwfn, 5248c965db44STomer Tayar struct qed_ptt *p_ptt, 5249c965db44STomer Tayar u32 *dump_buf, 5250c965db44STomer Tayar u32 buf_size_in_dwords, 5251c965db44STomer Tayar u32 *num_dumped_dwords) 5252c965db44STomer Tayar { 5253c965db44STomer Tayar u32 needed_buf_size_in_dwords; 5254c965db44STomer Tayar enum dbg_status status; 5255c965db44STomer Tayar 5256c965db44STomer Tayar *num_dumped_dwords = 0; 52577b6859fbSMintz, Yuval 52587b6859fbSMintz, Yuval status = qed_dbg_reg_fifo_get_dump_buf_size(p_hwfn, 52597b6859fbSMintz, Yuval p_ptt, 52607b6859fbSMintz, Yuval &needed_buf_size_in_dwords); 5261c965db44STomer Tayar if (status != DBG_STATUS_OK) 5262c965db44STomer Tayar return status; 52637b6859fbSMintz, Yuval 5264c965db44STomer Tayar if (buf_size_in_dwords < needed_buf_size_in_dwords) 5265c965db44STomer Tayar return DBG_STATUS_DUMP_BUF_TOO_SMALL; 5266c965db44STomer Tayar 5267c965db44STomer Tayar /* Update reset state */ 5268c965db44STomer Tayar qed_update_blocks_reset_state(p_hwfn, p_ptt); 5269be086e7cSMintz, Yuval 5270be086e7cSMintz, Yuval status = qed_reg_fifo_dump(p_hwfn, 5271c965db44STomer Tayar p_ptt, dump_buf, true, num_dumped_dwords); 5272be086e7cSMintz, Yuval 5273be086e7cSMintz, Yuval /* Revert GRC params to their default */ 5274be086e7cSMintz, Yuval qed_dbg_grc_set_params_default(p_hwfn); 5275be086e7cSMintz, Yuval 5276be086e7cSMintz, Yuval return status; 5277c965db44STomer Tayar } 5278c965db44STomer Tayar 5279c965db44STomer Tayar enum dbg_status qed_dbg_igu_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn, 5280c965db44STomer Tayar struct qed_ptt *p_ptt, 5281c965db44STomer Tayar u32 *buf_size) 5282c965db44STomer Tayar { 5283c965db44STomer Tayar enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt); 5284c965db44STomer Tayar 5285c965db44STomer Tayar *buf_size = 0; 52867b6859fbSMintz, Yuval 5287c965db44STomer Tayar if (status != DBG_STATUS_OK) 5288c965db44STomer Tayar return status; 52897b6859fbSMintz, Yuval 5290c965db44STomer Tayar return qed_igu_fifo_dump(p_hwfn, p_ptt, NULL, false, buf_size); 5291c965db44STomer Tayar } 5292c965db44STomer Tayar 5293c965db44STomer Tayar enum dbg_status qed_dbg_igu_fifo_dump(struct qed_hwfn *p_hwfn, 5294c965db44STomer Tayar struct qed_ptt *p_ptt, 5295c965db44STomer Tayar u32 *dump_buf, 5296c965db44STomer Tayar u32 buf_size_in_dwords, 5297c965db44STomer Tayar u32 *num_dumped_dwords) 5298c965db44STomer Tayar { 5299c965db44STomer Tayar u32 needed_buf_size_in_dwords; 5300c965db44STomer Tayar enum dbg_status status; 5301c965db44STomer Tayar 5302c965db44STomer Tayar *num_dumped_dwords = 0; 53037b6859fbSMintz, Yuval 53047b6859fbSMintz, Yuval status = qed_dbg_igu_fifo_get_dump_buf_size(p_hwfn, 53057b6859fbSMintz, Yuval p_ptt, 53067b6859fbSMintz, Yuval &needed_buf_size_in_dwords); 5307c965db44STomer Tayar if (status != DBG_STATUS_OK) 5308c965db44STomer Tayar return status; 53097b6859fbSMintz, Yuval 5310c965db44STomer Tayar if (buf_size_in_dwords < needed_buf_size_in_dwords) 5311c965db44STomer Tayar return DBG_STATUS_DUMP_BUF_TOO_SMALL; 5312c965db44STomer Tayar 5313c965db44STomer Tayar /* Update reset state */ 5314c965db44STomer Tayar qed_update_blocks_reset_state(p_hwfn, p_ptt); 5315be086e7cSMintz, Yuval 5316be086e7cSMintz, Yuval status = qed_igu_fifo_dump(p_hwfn, 5317c965db44STomer Tayar p_ptt, dump_buf, true, num_dumped_dwords); 5318be086e7cSMintz, Yuval /* Revert GRC params to their default */ 5319be086e7cSMintz, Yuval qed_dbg_grc_set_params_default(p_hwfn); 5320be086e7cSMintz, Yuval 5321be086e7cSMintz, Yuval return status; 5322c965db44STomer Tayar } 5323c965db44STomer Tayar 5324c965db44STomer Tayar enum dbg_status 5325c965db44STomer Tayar qed_dbg_protection_override_get_dump_buf_size(struct qed_hwfn *p_hwfn, 5326c965db44STomer Tayar struct qed_ptt *p_ptt, 5327c965db44STomer Tayar u32 *buf_size) 5328c965db44STomer Tayar { 5329c965db44STomer Tayar enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt); 5330c965db44STomer Tayar 5331c965db44STomer Tayar *buf_size = 0; 53327b6859fbSMintz, Yuval 5333c965db44STomer Tayar if (status != DBG_STATUS_OK) 5334c965db44STomer Tayar return status; 53357b6859fbSMintz, Yuval 5336c965db44STomer Tayar return qed_protection_override_dump(p_hwfn, 5337c965db44STomer Tayar p_ptt, NULL, false, buf_size); 5338c965db44STomer Tayar } 5339c965db44STomer Tayar 5340c965db44STomer Tayar enum dbg_status qed_dbg_protection_override_dump(struct qed_hwfn *p_hwfn, 5341c965db44STomer Tayar struct qed_ptt *p_ptt, 5342c965db44STomer Tayar u32 *dump_buf, 5343c965db44STomer Tayar u32 buf_size_in_dwords, 5344c965db44STomer Tayar u32 *num_dumped_dwords) 5345c965db44STomer Tayar { 53467b6859fbSMintz, Yuval u32 needed_buf_size_in_dwords, *p_size = &needed_buf_size_in_dwords; 5347c965db44STomer Tayar enum dbg_status status; 5348c965db44STomer Tayar 5349c965db44STomer Tayar *num_dumped_dwords = 0; 53507b6859fbSMintz, Yuval 53517b6859fbSMintz, Yuval status = 53527b6859fbSMintz, Yuval qed_dbg_protection_override_get_dump_buf_size(p_hwfn, 53537b6859fbSMintz, Yuval p_ptt, 53547b6859fbSMintz, Yuval p_size); 5355c965db44STomer Tayar if (status != DBG_STATUS_OK) 5356c965db44STomer Tayar return status; 53577b6859fbSMintz, Yuval 5358c965db44STomer Tayar if (buf_size_in_dwords < needed_buf_size_in_dwords) 5359c965db44STomer Tayar return DBG_STATUS_DUMP_BUF_TOO_SMALL; 5360c965db44STomer Tayar 5361c965db44STomer Tayar /* Update reset state */ 5362c965db44STomer Tayar qed_update_blocks_reset_state(p_hwfn, p_ptt); 5363be086e7cSMintz, Yuval 5364be086e7cSMintz, Yuval status = qed_protection_override_dump(p_hwfn, 5365c965db44STomer Tayar p_ptt, 5366be086e7cSMintz, Yuval dump_buf, 5367be086e7cSMintz, Yuval true, num_dumped_dwords); 5368be086e7cSMintz, Yuval 5369be086e7cSMintz, Yuval /* Revert GRC params to their default */ 5370be086e7cSMintz, Yuval qed_dbg_grc_set_params_default(p_hwfn); 5371be086e7cSMintz, Yuval 5372be086e7cSMintz, Yuval return status; 5373c965db44STomer Tayar } 5374c965db44STomer Tayar 5375c965db44STomer Tayar enum dbg_status qed_dbg_fw_asserts_get_dump_buf_size(struct qed_hwfn *p_hwfn, 5376c965db44STomer Tayar struct qed_ptt *p_ptt, 5377c965db44STomer Tayar u32 *buf_size) 5378c965db44STomer Tayar { 5379c965db44STomer Tayar enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt); 5380c965db44STomer Tayar 5381c965db44STomer Tayar *buf_size = 0; 53827b6859fbSMintz, Yuval 5383c965db44STomer Tayar if (status != DBG_STATUS_OK) 5384c965db44STomer Tayar return status; 5385c965db44STomer Tayar 5386c965db44STomer Tayar /* Update reset state */ 5387c965db44STomer Tayar qed_update_blocks_reset_state(p_hwfn, p_ptt); 53887b6859fbSMintz, Yuval 5389c965db44STomer Tayar *buf_size = qed_fw_asserts_dump(p_hwfn, p_ptt, NULL, false); 53907b6859fbSMintz, Yuval 5391c965db44STomer Tayar return DBG_STATUS_OK; 5392c965db44STomer Tayar } 5393c965db44STomer Tayar 5394c965db44STomer Tayar enum dbg_status qed_dbg_fw_asserts_dump(struct qed_hwfn *p_hwfn, 5395c965db44STomer Tayar struct qed_ptt *p_ptt, 5396c965db44STomer Tayar u32 *dump_buf, 5397c965db44STomer Tayar u32 buf_size_in_dwords, 5398c965db44STomer Tayar u32 *num_dumped_dwords) 5399c965db44STomer Tayar { 54007b6859fbSMintz, Yuval u32 needed_buf_size_in_dwords, *p_size = &needed_buf_size_in_dwords; 5401c965db44STomer Tayar enum dbg_status status; 5402c965db44STomer Tayar 5403c965db44STomer Tayar *num_dumped_dwords = 0; 54047b6859fbSMintz, Yuval 54057b6859fbSMintz, Yuval status = 54067b6859fbSMintz, Yuval qed_dbg_fw_asserts_get_dump_buf_size(p_hwfn, 54077b6859fbSMintz, Yuval p_ptt, 54087b6859fbSMintz, Yuval p_size); 5409c965db44STomer Tayar if (status != DBG_STATUS_OK) 5410c965db44STomer Tayar return status; 54117b6859fbSMintz, Yuval 5412c965db44STomer Tayar if (buf_size_in_dwords < needed_buf_size_in_dwords) 5413c965db44STomer Tayar return DBG_STATUS_DUMP_BUF_TOO_SMALL; 5414c965db44STomer Tayar 5415c965db44STomer Tayar *num_dumped_dwords = qed_fw_asserts_dump(p_hwfn, p_ptt, dump_buf, true); 54167b6859fbSMintz, Yuval 54177b6859fbSMintz, Yuval /* Revert GRC params to their default */ 54187b6859fbSMintz, Yuval qed_dbg_grc_set_params_default(p_hwfn); 54197b6859fbSMintz, Yuval 5420c965db44STomer Tayar return DBG_STATUS_OK; 5421c965db44STomer Tayar } 5422c965db44STomer Tayar 54230ebbd1c8SMintz, Yuval enum dbg_status qed_dbg_read_attn(struct qed_hwfn *p_hwfn, 54240ebbd1c8SMintz, Yuval struct qed_ptt *p_ptt, 54250ebbd1c8SMintz, Yuval enum block_id block_id, 54260ebbd1c8SMintz, Yuval enum dbg_attn_type attn_type, 54270ebbd1c8SMintz, Yuval bool clear_status, 54280ebbd1c8SMintz, Yuval struct dbg_attn_block_result *results) 54290ebbd1c8SMintz, Yuval { 54300ebbd1c8SMintz, Yuval enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt); 54310ebbd1c8SMintz, Yuval u8 reg_idx, num_attn_regs, num_result_regs = 0; 54320ebbd1c8SMintz, Yuval const struct dbg_attn_reg *attn_reg_arr; 54330ebbd1c8SMintz, Yuval 54340ebbd1c8SMintz, Yuval if (status != DBG_STATUS_OK) 54350ebbd1c8SMintz, Yuval return status; 54360ebbd1c8SMintz, Yuval 54370ebbd1c8SMintz, Yuval if (!s_dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr || 54380ebbd1c8SMintz, Yuval !s_dbg_arrays[BIN_BUF_DBG_ATTN_BLOCKS].ptr || 54390ebbd1c8SMintz, Yuval !s_dbg_arrays[BIN_BUF_DBG_ATTN_REGS].ptr) 54400ebbd1c8SMintz, Yuval return DBG_STATUS_DBG_ARRAY_NOT_SET; 54410ebbd1c8SMintz, Yuval 54420ebbd1c8SMintz, Yuval attn_reg_arr = qed_get_block_attn_regs(block_id, 54430ebbd1c8SMintz, Yuval attn_type, &num_attn_regs); 54440ebbd1c8SMintz, Yuval 54450ebbd1c8SMintz, Yuval for (reg_idx = 0; reg_idx < num_attn_regs; reg_idx++) { 54460ebbd1c8SMintz, Yuval const struct dbg_attn_reg *reg_data = &attn_reg_arr[reg_idx]; 54470ebbd1c8SMintz, Yuval struct dbg_attn_reg_result *reg_result; 54480ebbd1c8SMintz, Yuval u32 sts_addr, sts_val; 54490ebbd1c8SMintz, Yuval u16 modes_buf_offset; 54500ebbd1c8SMintz, Yuval bool eval_mode; 54510ebbd1c8SMintz, Yuval 54520ebbd1c8SMintz, Yuval /* Check mode */ 54530ebbd1c8SMintz, Yuval eval_mode = GET_FIELD(reg_data->mode.data, 54540ebbd1c8SMintz, Yuval DBG_MODE_HDR_EVAL_MODE) > 0; 54550ebbd1c8SMintz, Yuval modes_buf_offset = GET_FIELD(reg_data->mode.data, 54560ebbd1c8SMintz, Yuval DBG_MODE_HDR_MODES_BUF_OFFSET); 54570ebbd1c8SMintz, Yuval if (eval_mode && !qed_is_mode_match(p_hwfn, &modes_buf_offset)) 54580ebbd1c8SMintz, Yuval continue; 54590ebbd1c8SMintz, Yuval 54600ebbd1c8SMintz, Yuval /* Mode match - read attention status register */ 54610ebbd1c8SMintz, Yuval sts_addr = DWORDS_TO_BYTES(clear_status ? 54620ebbd1c8SMintz, Yuval reg_data->sts_clr_address : 54630ebbd1c8SMintz, Yuval GET_FIELD(reg_data->data, 54640ebbd1c8SMintz, Yuval DBG_ATTN_REG_STS_ADDRESS)); 54650ebbd1c8SMintz, Yuval sts_val = qed_rd(p_hwfn, p_ptt, sts_addr); 54660ebbd1c8SMintz, Yuval if (!sts_val) 54670ebbd1c8SMintz, Yuval continue; 54680ebbd1c8SMintz, Yuval 54690ebbd1c8SMintz, Yuval /* Non-zero attention status - add to results */ 54700ebbd1c8SMintz, Yuval reg_result = &results->reg_results[num_result_regs]; 54710ebbd1c8SMintz, Yuval SET_FIELD(reg_result->data, 54720ebbd1c8SMintz, Yuval DBG_ATTN_REG_RESULT_STS_ADDRESS, sts_addr); 54730ebbd1c8SMintz, Yuval SET_FIELD(reg_result->data, 54740ebbd1c8SMintz, Yuval DBG_ATTN_REG_RESULT_NUM_REG_ATTN, 54750ebbd1c8SMintz, Yuval GET_FIELD(reg_data->data, DBG_ATTN_REG_NUM_REG_ATTN)); 54760ebbd1c8SMintz, Yuval reg_result->block_attn_offset = reg_data->block_attn_offset; 54770ebbd1c8SMintz, Yuval reg_result->sts_val = sts_val; 54780ebbd1c8SMintz, Yuval reg_result->mask_val = qed_rd(p_hwfn, 54790ebbd1c8SMintz, Yuval p_ptt, 54800ebbd1c8SMintz, Yuval DWORDS_TO_BYTES 54810ebbd1c8SMintz, Yuval (reg_data->mask_address)); 54820ebbd1c8SMintz, Yuval num_result_regs++; 54830ebbd1c8SMintz, Yuval } 54840ebbd1c8SMintz, Yuval 54850ebbd1c8SMintz, Yuval results->block_id = (u8)block_id; 54860ebbd1c8SMintz, Yuval results->names_offset = 54870ebbd1c8SMintz, Yuval qed_get_block_attn_data(block_id, attn_type)->names_offset; 54880ebbd1c8SMintz, Yuval SET_FIELD(results->data, DBG_ATTN_BLOCK_RESULT_ATTN_TYPE, attn_type); 54890ebbd1c8SMintz, Yuval SET_FIELD(results->data, 54900ebbd1c8SMintz, Yuval DBG_ATTN_BLOCK_RESULT_NUM_REGS, num_result_regs); 54910ebbd1c8SMintz, Yuval 54920ebbd1c8SMintz, Yuval return DBG_STATUS_OK; 54930ebbd1c8SMintz, Yuval } 54940ebbd1c8SMintz, Yuval 5495c965db44STomer Tayar /******************************* Data Types **********************************/ 5496c965db44STomer Tayar 54970ebbd1c8SMintz, Yuval struct block_info { 54980ebbd1c8SMintz, Yuval const char *name; 54990ebbd1c8SMintz, Yuval enum block_id id; 55000ebbd1c8SMintz, Yuval }; 55010ebbd1c8SMintz, Yuval 5502c965db44STomer Tayar struct mcp_trace_format { 5503c965db44STomer Tayar u32 data; 5504c965db44STomer Tayar #define MCP_TRACE_FORMAT_MODULE_MASK 0x0000ffff 5505c965db44STomer Tayar #define MCP_TRACE_FORMAT_MODULE_SHIFT 0 5506c965db44STomer Tayar #define MCP_TRACE_FORMAT_LEVEL_MASK 0x00030000 5507c965db44STomer Tayar #define MCP_TRACE_FORMAT_LEVEL_SHIFT 16 5508c965db44STomer Tayar #define MCP_TRACE_FORMAT_P1_SIZE_MASK 0x000c0000 5509c965db44STomer Tayar #define MCP_TRACE_FORMAT_P1_SIZE_SHIFT 18 5510c965db44STomer Tayar #define MCP_TRACE_FORMAT_P2_SIZE_MASK 0x00300000 5511c965db44STomer Tayar #define MCP_TRACE_FORMAT_P2_SIZE_SHIFT 20 5512c965db44STomer Tayar #define MCP_TRACE_FORMAT_P3_SIZE_MASK 0x00c00000 5513c965db44STomer Tayar #define MCP_TRACE_FORMAT_P3_SIZE_SHIFT 22 5514c965db44STomer Tayar #define MCP_TRACE_FORMAT_LEN_MASK 0xff000000 5515c965db44STomer Tayar #define MCP_TRACE_FORMAT_LEN_SHIFT 24 55167b6859fbSMintz, Yuval 5517c965db44STomer Tayar char *format_str; 5518c965db44STomer Tayar }; 5519c965db44STomer Tayar 55207b6859fbSMintz, Yuval /* Meta data structure, generated by a perl script during MFW build. therefore, 55217b6859fbSMintz, Yuval * the structs mcp_trace_meta and mcp_trace_format are duplicated in the perl 55227b6859fbSMintz, Yuval * script. 55237b6859fbSMintz, Yuval */ 5524c965db44STomer Tayar struct mcp_trace_meta { 5525c965db44STomer Tayar u32 modules_num; 5526c965db44STomer Tayar char **modules; 5527c965db44STomer Tayar u32 formats_num; 5528c965db44STomer Tayar struct mcp_trace_format *formats; 5529c965db44STomer Tayar }; 5530c965db44STomer Tayar 55317b6859fbSMintz, Yuval /* REG fifo element */ 5532c965db44STomer Tayar struct reg_fifo_element { 5533c965db44STomer Tayar u64 data; 5534c965db44STomer Tayar #define REG_FIFO_ELEMENT_ADDRESS_SHIFT 0 5535c965db44STomer Tayar #define REG_FIFO_ELEMENT_ADDRESS_MASK 0x7fffff 5536c965db44STomer Tayar #define REG_FIFO_ELEMENT_ACCESS_SHIFT 23 5537c965db44STomer Tayar #define REG_FIFO_ELEMENT_ACCESS_MASK 0x1 5538c965db44STomer Tayar #define REG_FIFO_ELEMENT_PF_SHIFT 24 5539c965db44STomer Tayar #define REG_FIFO_ELEMENT_PF_MASK 0xf 5540c965db44STomer Tayar #define REG_FIFO_ELEMENT_VF_SHIFT 28 5541c965db44STomer Tayar #define REG_FIFO_ELEMENT_VF_MASK 0xff 5542c965db44STomer Tayar #define REG_FIFO_ELEMENT_PORT_SHIFT 36 5543c965db44STomer Tayar #define REG_FIFO_ELEMENT_PORT_MASK 0x3 5544c965db44STomer Tayar #define REG_FIFO_ELEMENT_PRIVILEGE_SHIFT 38 5545c965db44STomer Tayar #define REG_FIFO_ELEMENT_PRIVILEGE_MASK 0x3 5546c965db44STomer Tayar #define REG_FIFO_ELEMENT_PROTECTION_SHIFT 40 5547c965db44STomer Tayar #define REG_FIFO_ELEMENT_PROTECTION_MASK 0x7 5548c965db44STomer Tayar #define REG_FIFO_ELEMENT_MASTER_SHIFT 43 5549c965db44STomer Tayar #define REG_FIFO_ELEMENT_MASTER_MASK 0xf 5550c965db44STomer Tayar #define REG_FIFO_ELEMENT_ERROR_SHIFT 47 5551c965db44STomer Tayar #define REG_FIFO_ELEMENT_ERROR_MASK 0x1f 5552c965db44STomer Tayar }; 5553c965db44STomer Tayar 5554c965db44STomer Tayar /* IGU fifo element */ 5555c965db44STomer Tayar struct igu_fifo_element { 5556c965db44STomer Tayar u32 dword0; 5557c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_FID_SHIFT 0 5558c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_FID_MASK 0xff 5559c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_IS_PF_SHIFT 8 5560c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_IS_PF_MASK 0x1 5561c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_SOURCE_SHIFT 9 5562c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_SOURCE_MASK 0xf 5563c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_ERR_TYPE_SHIFT 13 5564c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_ERR_TYPE_MASK 0xf 5565c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_CMD_ADDR_SHIFT 17 5566c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_CMD_ADDR_MASK 0x7fff 5567c965db44STomer Tayar u32 dword1; 5568c965db44STomer Tayar u32 dword2; 5569c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD12_IS_WR_CMD_SHIFT 0 5570c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD12_IS_WR_CMD_MASK 0x1 5571c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD12_WR_DATA_SHIFT 1 5572c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD12_WR_DATA_MASK 0xffffffff 5573c965db44STomer Tayar u32 reserved; 5574c965db44STomer Tayar }; 5575c965db44STomer Tayar 5576c965db44STomer Tayar struct igu_fifo_wr_data { 5577c965db44STomer Tayar u32 data; 5578c965db44STomer Tayar #define IGU_FIFO_WR_DATA_PROD_CONS_SHIFT 0 5579c965db44STomer Tayar #define IGU_FIFO_WR_DATA_PROD_CONS_MASK 0xffffff 5580c965db44STomer Tayar #define IGU_FIFO_WR_DATA_UPDATE_FLAG_SHIFT 24 5581c965db44STomer Tayar #define IGU_FIFO_WR_DATA_UPDATE_FLAG_MASK 0x1 5582c965db44STomer Tayar #define IGU_FIFO_WR_DATA_EN_DIS_INT_FOR_SB_SHIFT 25 5583c965db44STomer Tayar #define IGU_FIFO_WR_DATA_EN_DIS_INT_FOR_SB_MASK 0x3 5584c965db44STomer Tayar #define IGU_FIFO_WR_DATA_SEGMENT_SHIFT 27 5585c965db44STomer Tayar #define IGU_FIFO_WR_DATA_SEGMENT_MASK 0x1 5586c965db44STomer Tayar #define IGU_FIFO_WR_DATA_TIMER_MASK_SHIFT 28 5587c965db44STomer Tayar #define IGU_FIFO_WR_DATA_TIMER_MASK_MASK 0x1 5588c965db44STomer Tayar #define IGU_FIFO_WR_DATA_CMD_TYPE_SHIFT 31 5589c965db44STomer Tayar #define IGU_FIFO_WR_DATA_CMD_TYPE_MASK 0x1 5590c965db44STomer Tayar }; 5591c965db44STomer Tayar 5592c965db44STomer Tayar struct igu_fifo_cleanup_wr_data { 5593c965db44STomer Tayar u32 data; 5594c965db44STomer Tayar #define IGU_FIFO_CLEANUP_WR_DATA_RESERVED_SHIFT 0 5595c965db44STomer Tayar #define IGU_FIFO_CLEANUP_WR_DATA_RESERVED_MASK 0x7ffffff 5596c965db44STomer Tayar #define IGU_FIFO_CLEANUP_WR_DATA_CLEANUP_VAL_SHIFT 27 5597c965db44STomer Tayar #define IGU_FIFO_CLEANUP_WR_DATA_CLEANUP_VAL_MASK 0x1 5598c965db44STomer Tayar #define IGU_FIFO_CLEANUP_WR_DATA_CLEANUP_TYPE_SHIFT 28 5599c965db44STomer Tayar #define IGU_FIFO_CLEANUP_WR_DATA_CLEANUP_TYPE_MASK 0x7 5600c965db44STomer Tayar #define IGU_FIFO_CLEANUP_WR_DATA_CMD_TYPE_SHIFT 31 5601c965db44STomer Tayar #define IGU_FIFO_CLEANUP_WR_DATA_CMD_TYPE_MASK 0x1 5602c965db44STomer Tayar }; 5603c965db44STomer Tayar 5604c965db44STomer Tayar /* Protection override element */ 5605c965db44STomer Tayar struct protection_override_element { 5606c965db44STomer Tayar u64 data; 5607c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_ADDRESS_SHIFT 0 5608c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_ADDRESS_MASK 0x7fffff 5609c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_WINDOW_SIZE_SHIFT 23 5610c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_WINDOW_SIZE_MASK 0xffffff 5611c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_READ_SHIFT 47 5612c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_READ_MASK 0x1 5613c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_WRITE_SHIFT 48 5614c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_WRITE_MASK 0x1 5615c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_READ_PROTECTION_SHIFT 49 5616c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_READ_PROTECTION_MASK 0x7 5617c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_WRITE_PROTECTION_SHIFT 52 5618c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_WRITE_PROTECTION_MASK 0x7 5619c965db44STomer Tayar }; 5620c965db44STomer Tayar 5621c965db44STomer Tayar enum igu_fifo_sources { 5622c965db44STomer Tayar IGU_SRC_PXP0, 5623c965db44STomer Tayar IGU_SRC_PXP1, 5624c965db44STomer Tayar IGU_SRC_PXP2, 5625c965db44STomer Tayar IGU_SRC_PXP3, 5626c965db44STomer Tayar IGU_SRC_PXP4, 5627c965db44STomer Tayar IGU_SRC_PXP5, 5628c965db44STomer Tayar IGU_SRC_PXP6, 5629c965db44STomer Tayar IGU_SRC_PXP7, 5630c965db44STomer Tayar IGU_SRC_CAU, 5631c965db44STomer Tayar IGU_SRC_ATTN, 5632c965db44STomer Tayar IGU_SRC_GRC 5633c965db44STomer Tayar }; 5634c965db44STomer Tayar 5635c965db44STomer Tayar enum igu_fifo_addr_types { 5636c965db44STomer Tayar IGU_ADDR_TYPE_MSIX_MEM, 5637c965db44STomer Tayar IGU_ADDR_TYPE_WRITE_PBA, 5638c965db44STomer Tayar IGU_ADDR_TYPE_WRITE_INT_ACK, 5639c965db44STomer Tayar IGU_ADDR_TYPE_WRITE_ATTN_BITS, 5640c965db44STomer Tayar IGU_ADDR_TYPE_READ_INT, 5641c965db44STomer Tayar IGU_ADDR_TYPE_WRITE_PROD_UPDATE, 5642c965db44STomer Tayar IGU_ADDR_TYPE_RESERVED 5643c965db44STomer Tayar }; 5644c965db44STomer Tayar 5645c965db44STomer Tayar struct igu_fifo_addr_data { 5646c965db44STomer Tayar u16 start_addr; 5647c965db44STomer Tayar u16 end_addr; 5648c965db44STomer Tayar char *desc; 5649c965db44STomer Tayar char *vf_desc; 5650c965db44STomer Tayar enum igu_fifo_addr_types type; 5651c965db44STomer Tayar }; 5652c965db44STomer Tayar 5653c965db44STomer Tayar /******************************** Constants **********************************/ 5654c965db44STomer Tayar 5655c965db44STomer Tayar #define MAX_MSG_LEN 1024 56567b6859fbSMintz, Yuval 5657c965db44STomer Tayar #define MCP_TRACE_MAX_MODULE_LEN 8 5658c965db44STomer Tayar #define MCP_TRACE_FORMAT_MAX_PARAMS 3 5659c965db44STomer Tayar #define MCP_TRACE_FORMAT_PARAM_WIDTH \ 5660c965db44STomer Tayar (MCP_TRACE_FORMAT_P2_SIZE_SHIFT - MCP_TRACE_FORMAT_P1_SIZE_SHIFT) 56617b6859fbSMintz, Yuval 5662c965db44STomer Tayar #define REG_FIFO_ELEMENT_ADDR_FACTOR 4 5663c965db44STomer Tayar #define REG_FIFO_ELEMENT_IS_PF_VF_VAL 127 56647b6859fbSMintz, Yuval 5665c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_ADDR_FACTOR 4 5666c965db44STomer Tayar 5667c965db44STomer Tayar /***************************** Constant Arrays *******************************/ 5668c965db44STomer Tayar 56697b6859fbSMintz, Yuval struct user_dbg_array { 56707b6859fbSMintz, Yuval const u32 *ptr; 56717b6859fbSMintz, Yuval u32 size_in_dwords; 56727b6859fbSMintz, Yuval }; 56737b6859fbSMintz, Yuval 56747b6859fbSMintz, Yuval /* Debug arrays */ 56757b6859fbSMintz, Yuval static struct user_dbg_array 56767b6859fbSMintz, Yuval s_user_dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE] = { {NULL} }; 56777b6859fbSMintz, Yuval 56780ebbd1c8SMintz, Yuval /* Block names array */ 56790ebbd1c8SMintz, Yuval static struct block_info s_block_info_arr[] = { 56800ebbd1c8SMintz, Yuval {"grc", BLOCK_GRC}, 56810ebbd1c8SMintz, Yuval {"miscs", BLOCK_MISCS}, 56820ebbd1c8SMintz, Yuval {"misc", BLOCK_MISC}, 56830ebbd1c8SMintz, Yuval {"dbu", BLOCK_DBU}, 56840ebbd1c8SMintz, Yuval {"pglue_b", BLOCK_PGLUE_B}, 56850ebbd1c8SMintz, Yuval {"cnig", BLOCK_CNIG}, 56860ebbd1c8SMintz, Yuval {"cpmu", BLOCK_CPMU}, 56870ebbd1c8SMintz, Yuval {"ncsi", BLOCK_NCSI}, 56880ebbd1c8SMintz, Yuval {"opte", BLOCK_OPTE}, 56890ebbd1c8SMintz, Yuval {"bmb", BLOCK_BMB}, 56900ebbd1c8SMintz, Yuval {"pcie", BLOCK_PCIE}, 56910ebbd1c8SMintz, Yuval {"mcp", BLOCK_MCP}, 56920ebbd1c8SMintz, Yuval {"mcp2", BLOCK_MCP2}, 56930ebbd1c8SMintz, Yuval {"pswhst", BLOCK_PSWHST}, 56940ebbd1c8SMintz, Yuval {"pswhst2", BLOCK_PSWHST2}, 56950ebbd1c8SMintz, Yuval {"pswrd", BLOCK_PSWRD}, 56960ebbd1c8SMintz, Yuval {"pswrd2", BLOCK_PSWRD2}, 56970ebbd1c8SMintz, Yuval {"pswwr", BLOCK_PSWWR}, 56980ebbd1c8SMintz, Yuval {"pswwr2", BLOCK_PSWWR2}, 56990ebbd1c8SMintz, Yuval {"pswrq", BLOCK_PSWRQ}, 57000ebbd1c8SMintz, Yuval {"pswrq2", BLOCK_PSWRQ2}, 57010ebbd1c8SMintz, Yuval {"pglcs", BLOCK_PGLCS}, 57020ebbd1c8SMintz, Yuval {"ptu", BLOCK_PTU}, 57030ebbd1c8SMintz, Yuval {"dmae", BLOCK_DMAE}, 57040ebbd1c8SMintz, Yuval {"tcm", BLOCK_TCM}, 57050ebbd1c8SMintz, Yuval {"mcm", BLOCK_MCM}, 57060ebbd1c8SMintz, Yuval {"ucm", BLOCK_UCM}, 57070ebbd1c8SMintz, Yuval {"xcm", BLOCK_XCM}, 57080ebbd1c8SMintz, Yuval {"ycm", BLOCK_YCM}, 57090ebbd1c8SMintz, Yuval {"pcm", BLOCK_PCM}, 57100ebbd1c8SMintz, Yuval {"qm", BLOCK_QM}, 57110ebbd1c8SMintz, Yuval {"tm", BLOCK_TM}, 57120ebbd1c8SMintz, Yuval {"dorq", BLOCK_DORQ}, 57130ebbd1c8SMintz, Yuval {"brb", BLOCK_BRB}, 57140ebbd1c8SMintz, Yuval {"src", BLOCK_SRC}, 57150ebbd1c8SMintz, Yuval {"prs", BLOCK_PRS}, 57160ebbd1c8SMintz, Yuval {"tsdm", BLOCK_TSDM}, 57170ebbd1c8SMintz, Yuval {"msdm", BLOCK_MSDM}, 57180ebbd1c8SMintz, Yuval {"usdm", BLOCK_USDM}, 57190ebbd1c8SMintz, Yuval {"xsdm", BLOCK_XSDM}, 57200ebbd1c8SMintz, Yuval {"ysdm", BLOCK_YSDM}, 57210ebbd1c8SMintz, Yuval {"psdm", BLOCK_PSDM}, 57220ebbd1c8SMintz, Yuval {"tsem", BLOCK_TSEM}, 57230ebbd1c8SMintz, Yuval {"msem", BLOCK_MSEM}, 57240ebbd1c8SMintz, Yuval {"usem", BLOCK_USEM}, 57250ebbd1c8SMintz, Yuval {"xsem", BLOCK_XSEM}, 57260ebbd1c8SMintz, Yuval {"ysem", BLOCK_YSEM}, 57270ebbd1c8SMintz, Yuval {"psem", BLOCK_PSEM}, 57280ebbd1c8SMintz, Yuval {"rss", BLOCK_RSS}, 57290ebbd1c8SMintz, Yuval {"tmld", BLOCK_TMLD}, 57300ebbd1c8SMintz, Yuval {"muld", BLOCK_MULD}, 57310ebbd1c8SMintz, Yuval {"yuld", BLOCK_YULD}, 57320ebbd1c8SMintz, Yuval {"xyld", BLOCK_XYLD}, 57330ebbd1c8SMintz, Yuval {"ptld", BLOCK_PTLD}, 57340ebbd1c8SMintz, Yuval {"ypld", BLOCK_YPLD}, 57350ebbd1c8SMintz, Yuval {"prm", BLOCK_PRM}, 57360ebbd1c8SMintz, Yuval {"pbf_pb1", BLOCK_PBF_PB1}, 57370ebbd1c8SMintz, Yuval {"pbf_pb2", BLOCK_PBF_PB2}, 57380ebbd1c8SMintz, Yuval {"rpb", BLOCK_RPB}, 57390ebbd1c8SMintz, Yuval {"btb", BLOCK_BTB}, 57400ebbd1c8SMintz, Yuval {"pbf", BLOCK_PBF}, 57410ebbd1c8SMintz, Yuval {"rdif", BLOCK_RDIF}, 57420ebbd1c8SMintz, Yuval {"tdif", BLOCK_TDIF}, 57430ebbd1c8SMintz, Yuval {"cdu", BLOCK_CDU}, 57440ebbd1c8SMintz, Yuval {"ccfc", BLOCK_CCFC}, 57450ebbd1c8SMintz, Yuval {"tcfc", BLOCK_TCFC}, 57460ebbd1c8SMintz, Yuval {"igu", BLOCK_IGU}, 57470ebbd1c8SMintz, Yuval {"cau", BLOCK_CAU}, 57480ebbd1c8SMintz, Yuval {"rgfs", BLOCK_RGFS}, 57490ebbd1c8SMintz, Yuval {"rgsrc", BLOCK_RGSRC}, 57500ebbd1c8SMintz, Yuval {"tgfs", BLOCK_TGFS}, 57510ebbd1c8SMintz, Yuval {"tgsrc", BLOCK_TGSRC}, 57520ebbd1c8SMintz, Yuval {"umac", BLOCK_UMAC}, 57530ebbd1c8SMintz, Yuval {"xmac", BLOCK_XMAC}, 57540ebbd1c8SMintz, Yuval {"dbg", BLOCK_DBG}, 57550ebbd1c8SMintz, Yuval {"nig", BLOCK_NIG}, 57560ebbd1c8SMintz, Yuval {"wol", BLOCK_WOL}, 57570ebbd1c8SMintz, Yuval {"bmbn", BLOCK_BMBN}, 57580ebbd1c8SMintz, Yuval {"ipc", BLOCK_IPC}, 57590ebbd1c8SMintz, Yuval {"nwm", BLOCK_NWM}, 57600ebbd1c8SMintz, Yuval {"nws", BLOCK_NWS}, 57610ebbd1c8SMintz, Yuval {"ms", BLOCK_MS}, 57620ebbd1c8SMintz, Yuval {"phy_pcie", BLOCK_PHY_PCIE}, 57630ebbd1c8SMintz, Yuval {"led", BLOCK_LED}, 57640ebbd1c8SMintz, Yuval {"avs_wrap", BLOCK_AVS_WRAP}, 5765da090917STomer Tayar {"pxpreqbus", BLOCK_PXPREQBUS}, 57660ebbd1c8SMintz, Yuval {"misc_aeu", BLOCK_MISC_AEU}, 57670ebbd1c8SMintz, Yuval {"bar0_map", BLOCK_BAR0_MAP} 57680ebbd1c8SMintz, Yuval }; 57690ebbd1c8SMintz, Yuval 5770c965db44STomer Tayar /* Status string array */ 5771c965db44STomer Tayar static const char * const s_status_str[] = { 57727b6859fbSMintz, Yuval /* DBG_STATUS_OK */ 5773c965db44STomer Tayar "Operation completed successfully", 57747b6859fbSMintz, Yuval 57757b6859fbSMintz, Yuval /* DBG_STATUS_APP_VERSION_NOT_SET */ 5776c965db44STomer Tayar "Debug application version wasn't set", 57777b6859fbSMintz, Yuval 57787b6859fbSMintz, Yuval /* DBG_STATUS_UNSUPPORTED_APP_VERSION */ 5779c965db44STomer Tayar "Unsupported debug application version", 57807b6859fbSMintz, Yuval 57817b6859fbSMintz, Yuval /* DBG_STATUS_DBG_BLOCK_NOT_RESET */ 5782c965db44STomer Tayar "The debug block wasn't reset since the last recording", 57837b6859fbSMintz, Yuval 57847b6859fbSMintz, Yuval /* DBG_STATUS_INVALID_ARGS */ 5785c965db44STomer Tayar "Invalid arguments", 57867b6859fbSMintz, Yuval 57877b6859fbSMintz, Yuval /* DBG_STATUS_OUTPUT_ALREADY_SET */ 5788c965db44STomer Tayar "The debug output was already set", 57897b6859fbSMintz, Yuval 57907b6859fbSMintz, Yuval /* DBG_STATUS_INVALID_PCI_BUF_SIZE */ 5791c965db44STomer Tayar "Invalid PCI buffer size", 57927b6859fbSMintz, Yuval 57937b6859fbSMintz, Yuval /* DBG_STATUS_PCI_BUF_ALLOC_FAILED */ 5794c965db44STomer Tayar "PCI buffer allocation failed", 57957b6859fbSMintz, Yuval 57967b6859fbSMintz, Yuval /* DBG_STATUS_PCI_BUF_NOT_ALLOCATED */ 5797c965db44STomer Tayar "A PCI buffer wasn't allocated", 57987b6859fbSMintz, Yuval 57997b6859fbSMintz, Yuval /* DBG_STATUS_TOO_MANY_INPUTS */ 5800c965db44STomer Tayar "Too many inputs were enabled. Enabled less inputs, or set 'unifyInputs' to true", 58017b6859fbSMintz, Yuval 58027b6859fbSMintz, Yuval /* DBG_STATUS_INPUT_OVERLAP */ 58037b6859fbSMintz, Yuval "Overlapping debug bus inputs", 58047b6859fbSMintz, Yuval 58057b6859fbSMintz, Yuval /* DBG_STATUS_HW_ONLY_RECORDING */ 5806c965db44STomer Tayar "Cannot record Storm data since the entire recording cycle is used by HW", 58077b6859fbSMintz, Yuval 58087b6859fbSMintz, Yuval /* DBG_STATUS_STORM_ALREADY_ENABLED */ 5809c965db44STomer Tayar "The Storm was already enabled", 58107b6859fbSMintz, Yuval 58117b6859fbSMintz, Yuval /* DBG_STATUS_STORM_NOT_ENABLED */ 5812c965db44STomer Tayar "The specified Storm wasn't enabled", 58137b6859fbSMintz, Yuval 58147b6859fbSMintz, Yuval /* DBG_STATUS_BLOCK_ALREADY_ENABLED */ 5815c965db44STomer Tayar "The block was already enabled", 58167b6859fbSMintz, Yuval 58177b6859fbSMintz, Yuval /* DBG_STATUS_BLOCK_NOT_ENABLED */ 5818c965db44STomer Tayar "The specified block wasn't enabled", 58197b6859fbSMintz, Yuval 58207b6859fbSMintz, Yuval /* DBG_STATUS_NO_INPUT_ENABLED */ 5821c965db44STomer Tayar "No input was enabled for recording", 58227b6859fbSMintz, Yuval 58237b6859fbSMintz, Yuval /* DBG_STATUS_NO_FILTER_TRIGGER_64B */ 5824c965db44STomer Tayar "Filters and triggers are not allowed when recording in 64b units", 58257b6859fbSMintz, Yuval 58267b6859fbSMintz, Yuval /* DBG_STATUS_FILTER_ALREADY_ENABLED */ 5827c965db44STomer Tayar "The filter was already enabled", 58287b6859fbSMintz, Yuval 58297b6859fbSMintz, Yuval /* DBG_STATUS_TRIGGER_ALREADY_ENABLED */ 5830c965db44STomer Tayar "The trigger was already enabled", 58317b6859fbSMintz, Yuval 58327b6859fbSMintz, Yuval /* DBG_STATUS_TRIGGER_NOT_ENABLED */ 5833c965db44STomer Tayar "The trigger wasn't enabled", 58347b6859fbSMintz, Yuval 58357b6859fbSMintz, Yuval /* DBG_STATUS_CANT_ADD_CONSTRAINT */ 5836c965db44STomer Tayar "A constraint can be added only after a filter was enabled or a trigger state was added", 58377b6859fbSMintz, Yuval 58387b6859fbSMintz, Yuval /* DBG_STATUS_TOO_MANY_TRIGGER_STATES */ 5839c965db44STomer Tayar "Cannot add more than 3 trigger states", 58407b6859fbSMintz, Yuval 58417b6859fbSMintz, Yuval /* DBG_STATUS_TOO_MANY_CONSTRAINTS */ 5842c965db44STomer Tayar "Cannot add more than 4 constraints per filter or trigger state", 58437b6859fbSMintz, Yuval 58447b6859fbSMintz, Yuval /* DBG_STATUS_RECORDING_NOT_STARTED */ 5845c965db44STomer Tayar "The recording wasn't started", 58467b6859fbSMintz, Yuval 58477b6859fbSMintz, Yuval /* DBG_STATUS_DATA_DIDNT_TRIGGER */ 5848c965db44STomer Tayar "A trigger was configured, but it didn't trigger", 58497b6859fbSMintz, Yuval 58507b6859fbSMintz, Yuval /* DBG_STATUS_NO_DATA_RECORDED */ 5851c965db44STomer Tayar "No data was recorded", 58527b6859fbSMintz, Yuval 58537b6859fbSMintz, Yuval /* DBG_STATUS_DUMP_BUF_TOO_SMALL */ 5854c965db44STomer Tayar "Dump buffer is too small", 58557b6859fbSMintz, Yuval 58567b6859fbSMintz, Yuval /* DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED */ 5857c965db44STomer Tayar "Dumped data is not aligned to chunks", 58587b6859fbSMintz, Yuval 58597b6859fbSMintz, Yuval /* DBG_STATUS_UNKNOWN_CHIP */ 5860c965db44STomer Tayar "Unknown chip", 58617b6859fbSMintz, Yuval 58627b6859fbSMintz, Yuval /* DBG_STATUS_VIRT_MEM_ALLOC_FAILED */ 5863c965db44STomer Tayar "Failed allocating virtual memory", 58647b6859fbSMintz, Yuval 58657b6859fbSMintz, Yuval /* DBG_STATUS_BLOCK_IN_RESET */ 5866c965db44STomer Tayar "The input block is in reset", 58677b6859fbSMintz, Yuval 58687b6859fbSMintz, Yuval /* DBG_STATUS_INVALID_TRACE_SIGNATURE */ 5869c965db44STomer Tayar "Invalid MCP trace signature found in NVRAM", 58707b6859fbSMintz, Yuval 58717b6859fbSMintz, Yuval /* DBG_STATUS_INVALID_NVRAM_BUNDLE */ 5872c965db44STomer Tayar "Invalid bundle ID found in NVRAM", 58737b6859fbSMintz, Yuval 58747b6859fbSMintz, Yuval /* DBG_STATUS_NVRAM_GET_IMAGE_FAILED */ 5875c965db44STomer Tayar "Failed getting NVRAM image", 58767b6859fbSMintz, Yuval 58777b6859fbSMintz, Yuval /* DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE */ 5878c965db44STomer Tayar "NVRAM image is not dword-aligned", 58797b6859fbSMintz, Yuval 58807b6859fbSMintz, Yuval /* DBG_STATUS_NVRAM_READ_FAILED */ 5881c965db44STomer Tayar "Failed reading from NVRAM", 58827b6859fbSMintz, Yuval 58837b6859fbSMintz, Yuval /* DBG_STATUS_IDLE_CHK_PARSE_FAILED */ 5884c965db44STomer Tayar "Idle check parsing failed", 58857b6859fbSMintz, Yuval 58867b6859fbSMintz, Yuval /* DBG_STATUS_MCP_TRACE_BAD_DATA */ 5887c965db44STomer Tayar "MCP Trace data is corrupt", 58887b6859fbSMintz, Yuval 58897b6859fbSMintz, Yuval /* DBG_STATUS_MCP_TRACE_NO_META */ 58907b6859fbSMintz, Yuval "Dump doesn't contain meta data - it must be provided in image file", 58917b6859fbSMintz, Yuval 58927b6859fbSMintz, Yuval /* DBG_STATUS_MCP_COULD_NOT_HALT */ 5893c965db44STomer Tayar "Failed to halt MCP", 58947b6859fbSMintz, Yuval 58957b6859fbSMintz, Yuval /* DBG_STATUS_MCP_COULD_NOT_RESUME */ 5896c965db44STomer Tayar "Failed to resume MCP after halt", 58977b6859fbSMintz, Yuval 5898da090917STomer Tayar /* DBG_STATUS_RESERVED2 */ 5899da090917STomer Tayar "Reserved debug status - shouldn't be returned", 59007b6859fbSMintz, Yuval 59017b6859fbSMintz, Yuval /* DBG_STATUS_SEMI_FIFO_NOT_EMPTY */ 5902c965db44STomer Tayar "Failed to empty SEMI sync FIFO", 59037b6859fbSMintz, Yuval 59047b6859fbSMintz, Yuval /* DBG_STATUS_IGU_FIFO_BAD_DATA */ 5905c965db44STomer Tayar "IGU FIFO data is corrupt", 59067b6859fbSMintz, Yuval 59077b6859fbSMintz, Yuval /* DBG_STATUS_MCP_COULD_NOT_MASK_PRTY */ 5908c965db44STomer Tayar "MCP failed to mask parities", 59097b6859fbSMintz, Yuval 59107b6859fbSMintz, Yuval /* DBG_STATUS_FW_ASSERTS_PARSE_FAILED */ 5911c965db44STomer Tayar "FW Asserts parsing failed", 59127b6859fbSMintz, Yuval 59137b6859fbSMintz, Yuval /* DBG_STATUS_REG_FIFO_BAD_DATA */ 5914c965db44STomer Tayar "GRC FIFO data is corrupt", 59157b6859fbSMintz, Yuval 59167b6859fbSMintz, Yuval /* DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA */ 5917c965db44STomer Tayar "Protection Override data is corrupt", 59187b6859fbSMintz, Yuval 59197b6859fbSMintz, Yuval /* DBG_STATUS_DBG_ARRAY_NOT_SET */ 5920c965db44STomer Tayar "Debug arrays were not set (when using binary files, dbg_set_bin_ptr must be called)", 59217b6859fbSMintz, Yuval 59227b6859fbSMintz, Yuval /* DBG_STATUS_FILTER_BUG */ 59237b6859fbSMintz, Yuval "Debug Bus filtering requires the -unifyInputs option (due to a HW bug)", 59247b6859fbSMintz, Yuval 59257b6859fbSMintz, Yuval /* DBG_STATUS_NON_MATCHING_LINES */ 59267b6859fbSMintz, Yuval "Non-matching debug lines - all lines must be of the same type (either 128b or 256b)", 59277b6859fbSMintz, Yuval 59287b6859fbSMintz, Yuval /* DBG_STATUS_INVALID_TRIGGER_DWORD_OFFSET */ 59297b6859fbSMintz, Yuval "The selected trigger dword offset wasn't enabled in the recorded HW block", 59307b6859fbSMintz, Yuval 59317b6859fbSMintz, Yuval /* DBG_STATUS_DBG_BUS_IN_USE */ 59327b6859fbSMintz, Yuval "The debug bus is in use" 5933c965db44STomer Tayar }; 5934c965db44STomer Tayar 5935c965db44STomer Tayar /* Idle check severity names array */ 5936c965db44STomer Tayar static const char * const s_idle_chk_severity_str[] = { 5937c965db44STomer Tayar "Error", 5938c965db44STomer Tayar "Error if no traffic", 5939c965db44STomer Tayar "Warning" 5940c965db44STomer Tayar }; 5941c965db44STomer Tayar 5942c965db44STomer Tayar /* MCP Trace level names array */ 5943c965db44STomer Tayar static const char * const s_mcp_trace_level_str[] = { 5944c965db44STomer Tayar "ERROR", 5945c965db44STomer Tayar "TRACE", 5946c965db44STomer Tayar "DEBUG" 5947c965db44STomer Tayar }; 5948c965db44STomer Tayar 59497b6859fbSMintz, Yuval /* Access type names array */ 5950c965db44STomer Tayar static const char * const s_access_strs[] = { 5951c965db44STomer Tayar "read", 5952c965db44STomer Tayar "write" 5953c965db44STomer Tayar }; 5954c965db44STomer Tayar 59557b6859fbSMintz, Yuval /* Privilege type names array */ 5956c965db44STomer Tayar static const char * const s_privilege_strs[] = { 5957c965db44STomer Tayar "VF", 5958c965db44STomer Tayar "PDA", 5959c965db44STomer Tayar "HV", 5960c965db44STomer Tayar "UA" 5961c965db44STomer Tayar }; 5962c965db44STomer Tayar 59637b6859fbSMintz, Yuval /* Protection type names array */ 5964c965db44STomer Tayar static const char * const s_protection_strs[] = { 5965c965db44STomer Tayar "(default)", 5966c965db44STomer Tayar "(default)", 5967c965db44STomer Tayar "(default)", 5968c965db44STomer Tayar "(default)", 5969c965db44STomer Tayar "override VF", 5970c965db44STomer Tayar "override PDA", 5971c965db44STomer Tayar "override HV", 5972c965db44STomer Tayar "override UA" 5973c965db44STomer Tayar }; 5974c965db44STomer Tayar 59757b6859fbSMintz, Yuval /* Master type names array */ 5976c965db44STomer Tayar static const char * const s_master_strs[] = { 5977c965db44STomer Tayar "???", 5978c965db44STomer Tayar "pxp", 5979c965db44STomer Tayar "mcp", 5980c965db44STomer Tayar "msdm", 5981c965db44STomer Tayar "psdm", 5982c965db44STomer Tayar "ysdm", 5983c965db44STomer Tayar "usdm", 5984c965db44STomer Tayar "tsdm", 5985c965db44STomer Tayar "xsdm", 5986c965db44STomer Tayar "dbu", 5987c965db44STomer Tayar "dmae", 5988c965db44STomer Tayar "???", 5989c965db44STomer Tayar "???", 5990c965db44STomer Tayar "???", 5991c965db44STomer Tayar "???", 5992c965db44STomer Tayar "???" 5993c965db44STomer Tayar }; 5994c965db44STomer Tayar 59957b6859fbSMintz, Yuval /* REG FIFO error messages array */ 5996c965db44STomer Tayar static const char * const s_reg_fifo_error_strs[] = { 5997c965db44STomer Tayar "grc timeout", 5998c965db44STomer Tayar "address doesn't belong to any block", 5999c965db44STomer Tayar "reserved address in block or write to read-only address", 6000c965db44STomer Tayar "privilege/protection mismatch", 6001c965db44STomer Tayar "path isolation error" 6002c965db44STomer Tayar }; 6003c965db44STomer Tayar 60047b6859fbSMintz, Yuval /* IGU FIFO sources array */ 6005c965db44STomer Tayar static const char * const s_igu_fifo_source_strs[] = { 6006c965db44STomer Tayar "TSTORM", 6007c965db44STomer Tayar "MSTORM", 6008c965db44STomer Tayar "USTORM", 6009c965db44STomer Tayar "XSTORM", 6010c965db44STomer Tayar "YSTORM", 6011c965db44STomer Tayar "PSTORM", 6012c965db44STomer Tayar "PCIE", 6013c965db44STomer Tayar "NIG_QM_PBF", 6014c965db44STomer Tayar "CAU", 6015c965db44STomer Tayar "ATTN", 6016c965db44STomer Tayar "GRC", 6017c965db44STomer Tayar }; 6018c965db44STomer Tayar 60197b6859fbSMintz, Yuval /* IGU FIFO error messages */ 6020c965db44STomer Tayar static const char * const s_igu_fifo_error_strs[] = { 6021c965db44STomer Tayar "no error", 6022c965db44STomer Tayar "length error", 6023c965db44STomer Tayar "function disabled", 6024c965db44STomer Tayar "VF sent command to attnetion address", 6025c965db44STomer Tayar "host sent prod update command", 6026c965db44STomer Tayar "read of during interrupt register while in MIMD mode", 6027c965db44STomer Tayar "access to PXP BAR reserved address", 6028c965db44STomer Tayar "producer update command to attention index", 6029c965db44STomer Tayar "unknown error", 6030c965db44STomer Tayar "SB index not valid", 6031c965db44STomer Tayar "SB relative index and FID not found", 6032c965db44STomer Tayar "FID not match", 6033c965db44STomer Tayar "command with error flag asserted (PCI error or CAU discard)", 6034c965db44STomer Tayar "VF sent cleanup and RF cleanup is disabled", 6035c965db44STomer Tayar "cleanup command on type bigger than 4" 6036c965db44STomer Tayar }; 6037c965db44STomer Tayar 6038c965db44STomer Tayar /* IGU FIFO address data */ 6039c965db44STomer Tayar static const struct igu_fifo_addr_data s_igu_fifo_addr_data[] = { 60407b6859fbSMintz, Yuval {0x0, 0x101, "MSI-X Memory", NULL, 60417b6859fbSMintz, Yuval IGU_ADDR_TYPE_MSIX_MEM}, 60427b6859fbSMintz, Yuval {0x102, 0x1ff, "reserved", NULL, 60437b6859fbSMintz, Yuval IGU_ADDR_TYPE_RESERVED}, 60447b6859fbSMintz, Yuval {0x200, 0x200, "Write PBA[0:63]", NULL, 60457b6859fbSMintz, Yuval IGU_ADDR_TYPE_WRITE_PBA}, 6046c965db44STomer Tayar {0x201, 0x201, "Write PBA[64:127]", "reserved", 6047c965db44STomer Tayar IGU_ADDR_TYPE_WRITE_PBA}, 60487b6859fbSMintz, Yuval {0x202, 0x202, "Write PBA[128]", "reserved", 60497b6859fbSMintz, Yuval IGU_ADDR_TYPE_WRITE_PBA}, 60507b6859fbSMintz, Yuval {0x203, 0x3ff, "reserved", NULL, 60517b6859fbSMintz, Yuval IGU_ADDR_TYPE_RESERVED}, 6052c965db44STomer Tayar {0x400, 0x5ef, "Write interrupt acknowledgment", NULL, 6053c965db44STomer Tayar IGU_ADDR_TYPE_WRITE_INT_ACK}, 6054c965db44STomer Tayar {0x5f0, 0x5f0, "Attention bits update", NULL, 6055c965db44STomer Tayar IGU_ADDR_TYPE_WRITE_ATTN_BITS}, 6056c965db44STomer Tayar {0x5f1, 0x5f1, "Attention bits set", NULL, 6057c965db44STomer Tayar IGU_ADDR_TYPE_WRITE_ATTN_BITS}, 6058c965db44STomer Tayar {0x5f2, 0x5f2, "Attention bits clear", NULL, 6059c965db44STomer Tayar IGU_ADDR_TYPE_WRITE_ATTN_BITS}, 6060c965db44STomer Tayar {0x5f3, 0x5f3, "Read interrupt 0:63 with mask", NULL, 6061c965db44STomer Tayar IGU_ADDR_TYPE_READ_INT}, 6062c965db44STomer Tayar {0x5f4, 0x5f4, "Read interrupt 0:31 with mask", NULL, 6063c965db44STomer Tayar IGU_ADDR_TYPE_READ_INT}, 6064c965db44STomer Tayar {0x5f5, 0x5f5, "Read interrupt 32:63 with mask", NULL, 6065c965db44STomer Tayar IGU_ADDR_TYPE_READ_INT}, 6066c965db44STomer Tayar {0x5f6, 0x5f6, "Read interrupt 0:63 without mask", NULL, 6067c965db44STomer Tayar IGU_ADDR_TYPE_READ_INT}, 60687b6859fbSMintz, Yuval {0x5f7, 0x5ff, "reserved", NULL, 60697b6859fbSMintz, Yuval IGU_ADDR_TYPE_RESERVED}, 60707b6859fbSMintz, Yuval {0x600, 0x7ff, "Producer update", NULL, 60717b6859fbSMintz, Yuval IGU_ADDR_TYPE_WRITE_PROD_UPDATE} 6072c965db44STomer Tayar }; 6073c965db44STomer Tayar 6074c965db44STomer Tayar /******************************** Variables **********************************/ 6075c965db44STomer Tayar 6076c965db44STomer Tayar /* MCP Trace meta data - used in case the dump doesn't contain the meta data 6077c965db44STomer Tayar * (e.g. due to no NVRAM access). 6078c965db44STomer Tayar */ 60797b6859fbSMintz, Yuval static struct user_dbg_array s_mcp_trace_meta = { NULL, 0 }; 6080c965db44STomer Tayar 6081c965db44STomer Tayar /* Temporary buffer, used for print size calculations */ 6082c965db44STomer Tayar static char s_temp_buf[MAX_MSG_LEN]; 6083c965db44STomer Tayar 60847b6859fbSMintz, Yuval /**************************** Private Functions ******************************/ 6085c965db44STomer Tayar 6086c965db44STomer Tayar static u32 qed_cyclic_add(u32 a, u32 b, u32 size) 6087c965db44STomer Tayar { 6088c965db44STomer Tayar return (a + b) % size; 6089c965db44STomer Tayar } 6090c965db44STomer Tayar 6091c965db44STomer Tayar static u32 qed_cyclic_sub(u32 a, u32 b, u32 size) 6092c965db44STomer Tayar { 6093c965db44STomer Tayar return (size + a - b) % size; 6094c965db44STomer Tayar } 6095c965db44STomer Tayar 6096c965db44STomer Tayar /* Reads the specified number of bytes from the specified cyclic buffer (up to 4 6097c965db44STomer Tayar * bytes) and returns them as a dword value. the specified buffer offset is 6098c965db44STomer Tayar * updated. 6099c965db44STomer Tayar */ 6100c965db44STomer Tayar static u32 qed_read_from_cyclic_buf(void *buf, 6101c965db44STomer Tayar u32 *offset, 6102c965db44STomer Tayar u32 buf_size, u8 num_bytes_to_read) 6103c965db44STomer Tayar { 61047b6859fbSMintz, Yuval u8 i, *val_ptr, *bytes_buf = (u8 *)buf; 6105c965db44STomer Tayar u32 val = 0; 6106c965db44STomer Tayar 6107c965db44STomer Tayar val_ptr = (u8 *)&val; 6108c965db44STomer Tayar 6109c965db44STomer Tayar for (i = 0; i < num_bytes_to_read; i++) { 6110c965db44STomer Tayar val_ptr[i] = bytes_buf[*offset]; 6111c965db44STomer Tayar *offset = qed_cyclic_add(*offset, 1, buf_size); 6112c965db44STomer Tayar } 6113c965db44STomer Tayar 6114c965db44STomer Tayar return val; 6115c965db44STomer Tayar } 6116c965db44STomer Tayar 6117c965db44STomer Tayar /* Reads and returns the next byte from the specified buffer. 6118c965db44STomer Tayar * The specified buffer offset is updated. 6119c965db44STomer Tayar */ 6120c965db44STomer Tayar static u8 qed_read_byte_from_buf(void *buf, u32 *offset) 6121c965db44STomer Tayar { 6122c965db44STomer Tayar return ((u8 *)buf)[(*offset)++]; 6123c965db44STomer Tayar } 6124c965db44STomer Tayar 6125c965db44STomer Tayar /* Reads and returns the next dword from the specified buffer. 6126c965db44STomer Tayar * The specified buffer offset is updated. 6127c965db44STomer Tayar */ 6128c965db44STomer Tayar static u32 qed_read_dword_from_buf(void *buf, u32 *offset) 6129c965db44STomer Tayar { 6130c965db44STomer Tayar u32 dword_val = *(u32 *)&((u8 *)buf)[*offset]; 6131c965db44STomer Tayar 6132c965db44STomer Tayar *offset += 4; 61337b6859fbSMintz, Yuval 6134c965db44STomer Tayar return dword_val; 6135c965db44STomer Tayar } 6136c965db44STomer Tayar 6137c965db44STomer Tayar /* Reads the next string from the specified buffer, and copies it to the 6138c965db44STomer Tayar * specified pointer. The specified buffer offset is updated. 6139c965db44STomer Tayar */ 6140c965db44STomer Tayar static void qed_read_str_from_buf(void *buf, u32 *offset, u32 size, char *dest) 6141c965db44STomer Tayar { 6142c965db44STomer Tayar const char *source_str = &((const char *)buf)[*offset]; 6143c965db44STomer Tayar 6144c965db44STomer Tayar strncpy(dest, source_str, size); 6145c965db44STomer Tayar dest[size - 1] = '\0'; 6146c965db44STomer Tayar *offset += size; 6147c965db44STomer Tayar } 6148c965db44STomer Tayar 6149c965db44STomer Tayar /* Returns a pointer to the specified offset (in bytes) of the specified buffer. 6150c965db44STomer Tayar * If the specified buffer in NULL, a temporary buffer pointer is returned. 6151c965db44STomer Tayar */ 6152c965db44STomer Tayar static char *qed_get_buf_ptr(void *buf, u32 offset) 6153c965db44STomer Tayar { 6154c965db44STomer Tayar return buf ? (char *)buf + offset : s_temp_buf; 6155c965db44STomer Tayar } 6156c965db44STomer Tayar 6157c965db44STomer Tayar /* Reads a param from the specified buffer. Returns the number of dwords read. 6158c965db44STomer Tayar * If the returned str_param is NULL, the param is numeric and its value is 6159c965db44STomer Tayar * returned in num_param. 6160c965db44STomer Tayar * Otheriwise, the param is a string and its pointer is returned in str_param. 6161c965db44STomer Tayar */ 6162c965db44STomer Tayar static u32 qed_read_param(u32 *dump_buf, 6163c965db44STomer Tayar const char **param_name, 6164c965db44STomer Tayar const char **param_str_val, u32 *param_num_val) 6165c965db44STomer Tayar { 6166c965db44STomer Tayar char *char_buf = (char *)dump_buf; 61677b6859fbSMintz, Yuval size_t offset = 0; 6168c965db44STomer Tayar 6169c965db44STomer Tayar /* Extract param name */ 6170c965db44STomer Tayar *param_name = char_buf; 6171c965db44STomer Tayar offset += strlen(*param_name) + 1; 6172c965db44STomer Tayar 6173c965db44STomer Tayar /* Check param type */ 6174c965db44STomer Tayar if (*(char_buf + offset++)) { 6175c965db44STomer Tayar /* String param */ 6176c965db44STomer Tayar *param_str_val = char_buf + offset; 6177da090917STomer Tayar *param_num_val = 0; 6178c965db44STomer Tayar offset += strlen(*param_str_val) + 1; 6179c965db44STomer Tayar if (offset & 0x3) 6180c965db44STomer Tayar offset += (4 - (offset & 0x3)); 6181c965db44STomer Tayar } else { 6182c965db44STomer Tayar /* Numeric param */ 6183c965db44STomer Tayar *param_str_val = NULL; 6184c965db44STomer Tayar if (offset & 0x3) 6185c965db44STomer Tayar offset += (4 - (offset & 0x3)); 6186c965db44STomer Tayar *param_num_val = *(u32 *)(char_buf + offset); 6187c965db44STomer Tayar offset += 4; 6188c965db44STomer Tayar } 6189c965db44STomer Tayar 6190c965db44STomer Tayar return offset / 4; 6191c965db44STomer Tayar } 6192c965db44STomer Tayar 6193c965db44STomer Tayar /* Reads a section header from the specified buffer. 6194c965db44STomer Tayar * Returns the number of dwords read. 6195c965db44STomer Tayar */ 6196c965db44STomer Tayar static u32 qed_read_section_hdr(u32 *dump_buf, 6197c965db44STomer Tayar const char **section_name, 6198c965db44STomer Tayar u32 *num_section_params) 6199c965db44STomer Tayar { 6200c965db44STomer Tayar const char *param_str_val; 6201c965db44STomer Tayar 6202c965db44STomer Tayar return qed_read_param(dump_buf, 6203c965db44STomer Tayar section_name, ¶m_str_val, num_section_params); 6204c965db44STomer Tayar } 6205c965db44STomer Tayar 6206c965db44STomer Tayar /* Reads section params from the specified buffer and prints them to the results 6207c965db44STomer Tayar * buffer. Returns the number of dwords read. 6208c965db44STomer Tayar */ 6209c965db44STomer Tayar static u32 qed_print_section_params(u32 *dump_buf, 6210c965db44STomer Tayar u32 num_section_params, 6211c965db44STomer Tayar char *results_buf, u32 *num_chars_printed) 6212c965db44STomer Tayar { 6213c965db44STomer Tayar u32 i, dump_offset = 0, results_offset = 0; 6214c965db44STomer Tayar 6215c965db44STomer Tayar for (i = 0; i < num_section_params; i++) { 62167b6859fbSMintz, Yuval const char *param_name, *param_str_val; 6217c965db44STomer Tayar u32 param_num_val = 0; 6218c965db44STomer Tayar 6219c965db44STomer Tayar dump_offset += qed_read_param(dump_buf + dump_offset, 6220c965db44STomer Tayar ¶m_name, 6221c965db44STomer Tayar ¶m_str_val, ¶m_num_val); 62227b6859fbSMintz, Yuval 6223c965db44STomer Tayar if (param_str_val) 6224c965db44STomer Tayar results_offset += 6225c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6226c965db44STomer Tayar results_offset), 6227c965db44STomer Tayar "%s: %s\n", param_name, param_str_val); 6228c965db44STomer Tayar else if (strcmp(param_name, "fw-timestamp")) 6229c965db44STomer Tayar results_offset += 6230c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6231c965db44STomer Tayar results_offset), 6232c965db44STomer Tayar "%s: %d\n", param_name, param_num_val); 6233c965db44STomer Tayar } 6234c965db44STomer Tayar 62357b6859fbSMintz, Yuval results_offset += sprintf(qed_get_buf_ptr(results_buf, results_offset), 62367b6859fbSMintz, Yuval "\n"); 6237c965db44STomer Tayar 62387b6859fbSMintz, Yuval *num_chars_printed = results_offset; 62397b6859fbSMintz, Yuval 62407b6859fbSMintz, Yuval return dump_offset; 6241c965db44STomer Tayar } 6242c965db44STomer Tayar 6243c965db44STomer Tayar /* Parses the idle check rules and returns the number of characters printed. 6244c965db44STomer Tayar * In case of parsing error, returns 0. 6245c965db44STomer Tayar */ 6246da090917STomer Tayar static u32 qed_parse_idle_chk_dump_rules(u32 *dump_buf, 6247c965db44STomer Tayar u32 *dump_buf_end, 6248c965db44STomer Tayar u32 num_rules, 6249c965db44STomer Tayar bool print_fw_idle_chk, 6250c965db44STomer Tayar char *results_buf, 6251c965db44STomer Tayar u32 *num_errors, u32 *num_warnings) 6252c965db44STomer Tayar { 62537b6859fbSMintz, Yuval /* Offset in results_buf in bytes */ 62547b6859fbSMintz, Yuval u32 results_offset = 0; 62557b6859fbSMintz, Yuval 62567b6859fbSMintz, Yuval u32 rule_idx; 6257c965db44STomer Tayar u16 i, j; 6258c965db44STomer Tayar 6259c965db44STomer Tayar *num_errors = 0; 6260c965db44STomer Tayar *num_warnings = 0; 6261c965db44STomer Tayar 6262c965db44STomer Tayar /* Go over dumped results */ 6263c965db44STomer Tayar for (rule_idx = 0; rule_idx < num_rules && dump_buf < dump_buf_end; 6264c965db44STomer Tayar rule_idx++) { 6265c965db44STomer Tayar const struct dbg_idle_chk_rule_parsing_data *rule_parsing_data; 6266c965db44STomer Tayar struct dbg_idle_chk_result_hdr *hdr; 62677b6859fbSMintz, Yuval const char *parsing_str, *lsi_msg; 6268c965db44STomer Tayar u32 parsing_str_offset; 6269c965db44STomer Tayar bool has_fw_msg; 62707b6859fbSMintz, Yuval u8 curr_reg_id; 6271c965db44STomer Tayar 6272c965db44STomer Tayar hdr = (struct dbg_idle_chk_result_hdr *)dump_buf; 6273c965db44STomer Tayar rule_parsing_data = 6274c965db44STomer Tayar (const struct dbg_idle_chk_rule_parsing_data *) 62757b6859fbSMintz, Yuval &s_user_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_PARSING_DATA]. 6276c965db44STomer Tayar ptr[hdr->rule_id]; 6277c965db44STomer Tayar parsing_str_offset = 6278c965db44STomer Tayar GET_FIELD(rule_parsing_data->data, 6279c965db44STomer Tayar DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET); 6280c965db44STomer Tayar has_fw_msg = 6281c965db44STomer Tayar GET_FIELD(rule_parsing_data->data, 6282c965db44STomer Tayar DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG) > 0; 62837b6859fbSMintz, Yuval parsing_str = 62847b6859fbSMintz, Yuval &((const char *) 62857b6859fbSMintz, Yuval s_user_dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS].ptr) 6286c965db44STomer Tayar [parsing_str_offset]; 6287c965db44STomer Tayar lsi_msg = parsing_str; 62887b6859fbSMintz, Yuval curr_reg_id = 0; 6289c965db44STomer Tayar 6290c965db44STomer Tayar if (hdr->severity >= MAX_DBG_IDLE_CHK_SEVERITY_TYPES) 6291c965db44STomer Tayar return 0; 6292c965db44STomer Tayar 6293c965db44STomer Tayar /* Skip rule header */ 62947b6859fbSMintz, Yuval dump_buf += BYTES_TO_DWORDS(sizeof(*hdr)); 6295c965db44STomer Tayar 6296c965db44STomer Tayar /* Update errors/warnings count */ 6297c965db44STomer Tayar if (hdr->severity == IDLE_CHK_SEVERITY_ERROR || 6298c965db44STomer Tayar hdr->severity == IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC) 6299c965db44STomer Tayar (*num_errors)++; 6300c965db44STomer Tayar else 6301c965db44STomer Tayar (*num_warnings)++; 6302c965db44STomer Tayar 6303c965db44STomer Tayar /* Print rule severity */ 6304c965db44STomer Tayar results_offset += 6305c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6306c965db44STomer Tayar results_offset), "%s: ", 6307c965db44STomer Tayar s_idle_chk_severity_str[hdr->severity]); 6308c965db44STomer Tayar 6309c965db44STomer Tayar /* Print rule message */ 6310c965db44STomer Tayar if (has_fw_msg) 6311c965db44STomer Tayar parsing_str += strlen(parsing_str) + 1; 6312c965db44STomer Tayar results_offset += 6313c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6314c965db44STomer Tayar results_offset), "%s.", 6315c965db44STomer Tayar has_fw_msg && 6316c965db44STomer Tayar print_fw_idle_chk ? parsing_str : lsi_msg); 6317c965db44STomer Tayar parsing_str += strlen(parsing_str) + 1; 6318c965db44STomer Tayar 6319c965db44STomer Tayar /* Print register values */ 6320c965db44STomer Tayar results_offset += 6321c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6322c965db44STomer Tayar results_offset), " Registers:"); 6323c965db44STomer Tayar for (i = 0; 6324c965db44STomer Tayar i < hdr->num_dumped_cond_regs + hdr->num_dumped_info_regs; 6325c965db44STomer Tayar i++) { 63267b6859fbSMintz, Yuval struct dbg_idle_chk_result_reg_hdr *reg_hdr; 63277b6859fbSMintz, Yuval bool is_mem; 63287b6859fbSMintz, Yuval u8 reg_id; 63297b6859fbSMintz, Yuval 63307b6859fbSMintz, Yuval reg_hdr = 63317b6859fbSMintz, Yuval (struct dbg_idle_chk_result_reg_hdr *)dump_buf; 63327b6859fbSMintz, Yuval is_mem = GET_FIELD(reg_hdr->data, 6333c965db44STomer Tayar DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM); 63347b6859fbSMintz, Yuval reg_id = GET_FIELD(reg_hdr->data, 6335c965db44STomer Tayar DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID); 6336c965db44STomer Tayar 6337c965db44STomer Tayar /* Skip reg header */ 63387b6859fbSMintz, Yuval dump_buf += BYTES_TO_DWORDS(sizeof(*reg_hdr)); 6339c965db44STomer Tayar 6340c965db44STomer Tayar /* Skip register names until the required reg_id is 6341c965db44STomer Tayar * reached. 6342c965db44STomer Tayar */ 6343c965db44STomer Tayar for (; reg_id > curr_reg_id; 6344c965db44STomer Tayar curr_reg_id++, 6345c965db44STomer Tayar parsing_str += strlen(parsing_str) + 1); 6346c965db44STomer Tayar 6347c965db44STomer Tayar results_offset += 6348c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6349c965db44STomer Tayar results_offset), " %s", 6350c965db44STomer Tayar parsing_str); 6351c965db44STomer Tayar if (i < hdr->num_dumped_cond_regs && is_mem) 6352c965db44STomer Tayar results_offset += 6353c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6354c965db44STomer Tayar results_offset), 6355c965db44STomer Tayar "[%d]", hdr->mem_entry_id + 6356c965db44STomer Tayar reg_hdr->start_entry); 6357c965db44STomer Tayar results_offset += 6358c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6359c965db44STomer Tayar results_offset), "="); 6360c965db44STomer Tayar for (j = 0; j < reg_hdr->size; j++, dump_buf++) { 6361c965db44STomer Tayar results_offset += 6362c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6363c965db44STomer Tayar results_offset), 6364c965db44STomer Tayar "0x%x", *dump_buf); 6365c965db44STomer Tayar if (j < reg_hdr->size - 1) 6366c965db44STomer Tayar results_offset += 6367c965db44STomer Tayar sprintf(qed_get_buf_ptr 6368c965db44STomer Tayar (results_buf, 6369c965db44STomer Tayar results_offset), ","); 6370c965db44STomer Tayar } 6371c965db44STomer Tayar } 6372c965db44STomer Tayar 6373c965db44STomer Tayar results_offset += 6374c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, results_offset), "\n"); 6375c965db44STomer Tayar } 6376c965db44STomer Tayar 6377c965db44STomer Tayar /* Check if end of dump buffer was exceeded */ 6378c965db44STomer Tayar if (dump_buf > dump_buf_end) 6379c965db44STomer Tayar return 0; 63807b6859fbSMintz, Yuval 6381c965db44STomer Tayar return results_offset; 6382c965db44STomer Tayar } 6383c965db44STomer Tayar 6384c965db44STomer Tayar /* Parses an idle check dump buffer. 6385c965db44STomer Tayar * If result_buf is not NULL, the idle check results are printed to it. 6386c965db44STomer Tayar * In any case, the required results buffer size is assigned to 6387c965db44STomer Tayar * parsed_results_bytes. 6388c965db44STomer Tayar * The parsing status is returned. 6389c965db44STomer Tayar */ 6390da090917STomer Tayar static enum dbg_status qed_parse_idle_chk_dump(u32 *dump_buf, 6391c965db44STomer Tayar u32 num_dumped_dwords, 6392c965db44STomer Tayar char *results_buf, 6393c965db44STomer Tayar u32 *parsed_results_bytes, 6394c965db44STomer Tayar u32 *num_errors, 6395c965db44STomer Tayar u32 *num_warnings) 6396c965db44STomer Tayar { 6397c965db44STomer Tayar const char *section_name, *param_name, *param_str_val; 6398c965db44STomer Tayar u32 *dump_buf_end = dump_buf + num_dumped_dwords; 6399c965db44STomer Tayar u32 num_section_params = 0, num_rules; 64007b6859fbSMintz, Yuval 64017b6859fbSMintz, Yuval /* Offset in results_buf in bytes */ 64027b6859fbSMintz, Yuval u32 results_offset = 0; 6403c965db44STomer Tayar 6404c965db44STomer Tayar *parsed_results_bytes = 0; 6405c965db44STomer Tayar *num_errors = 0; 6406c965db44STomer Tayar *num_warnings = 0; 64077b6859fbSMintz, Yuval 64087b6859fbSMintz, Yuval if (!s_user_dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS].ptr || 64097b6859fbSMintz, Yuval !s_user_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_PARSING_DATA].ptr) 6410c965db44STomer Tayar return DBG_STATUS_DBG_ARRAY_NOT_SET; 6411c965db44STomer Tayar 6412c965db44STomer Tayar /* Read global_params section */ 6413c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 6414c965db44STomer Tayar §ion_name, &num_section_params); 6415c965db44STomer Tayar if (strcmp(section_name, "global_params")) 6416c965db44STomer Tayar return DBG_STATUS_IDLE_CHK_PARSE_FAILED; 6417c965db44STomer Tayar 6418c965db44STomer Tayar /* Print global params */ 6419c965db44STomer Tayar dump_buf += qed_print_section_params(dump_buf, 6420c965db44STomer Tayar num_section_params, 6421c965db44STomer Tayar results_buf, &results_offset); 6422c965db44STomer Tayar 6423c965db44STomer Tayar /* Read idle_chk section */ 6424c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 6425c965db44STomer Tayar §ion_name, &num_section_params); 6426c965db44STomer Tayar if (strcmp(section_name, "idle_chk") || num_section_params != 1) 6427c965db44STomer Tayar return DBG_STATUS_IDLE_CHK_PARSE_FAILED; 6428c965db44STomer Tayar dump_buf += qed_read_param(dump_buf, 6429c965db44STomer Tayar ¶m_name, ¶m_str_val, &num_rules); 64307b6859fbSMintz, Yuval if (strcmp(param_name, "num_rules")) 6431c965db44STomer Tayar return DBG_STATUS_IDLE_CHK_PARSE_FAILED; 6432c965db44STomer Tayar 6433c965db44STomer Tayar if (num_rules) { 6434c965db44STomer Tayar u32 rules_print_size; 6435c965db44STomer Tayar 6436c965db44STomer Tayar /* Print FW output */ 6437c965db44STomer Tayar results_offset += 6438c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6439c965db44STomer Tayar results_offset), 6440c965db44STomer Tayar "FW_IDLE_CHECK:\n"); 6441c965db44STomer Tayar rules_print_size = 6442da090917STomer Tayar qed_parse_idle_chk_dump_rules(dump_buf, 6443da090917STomer Tayar dump_buf_end, 6444da090917STomer Tayar num_rules, 6445c965db44STomer Tayar true, 6446c965db44STomer Tayar results_buf ? 6447c965db44STomer Tayar results_buf + 6448da090917STomer Tayar results_offset : 6449da090917STomer Tayar NULL, 6450da090917STomer Tayar num_errors, 6451da090917STomer Tayar num_warnings); 6452c965db44STomer Tayar results_offset += rules_print_size; 64537b6859fbSMintz, Yuval if (!rules_print_size) 6454c965db44STomer Tayar return DBG_STATUS_IDLE_CHK_PARSE_FAILED; 6455c965db44STomer Tayar 6456c965db44STomer Tayar /* Print LSI output */ 6457c965db44STomer Tayar results_offset += 6458c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6459c965db44STomer Tayar results_offset), 6460c965db44STomer Tayar "\nLSI_IDLE_CHECK:\n"); 6461c965db44STomer Tayar rules_print_size = 6462da090917STomer Tayar qed_parse_idle_chk_dump_rules(dump_buf, 6463da090917STomer Tayar dump_buf_end, 6464da090917STomer Tayar num_rules, 6465c965db44STomer Tayar false, 6466c965db44STomer Tayar results_buf ? 6467c965db44STomer Tayar results_buf + 6468da090917STomer Tayar results_offset : 6469da090917STomer Tayar NULL, 6470da090917STomer Tayar num_errors, 6471da090917STomer Tayar num_warnings); 6472c965db44STomer Tayar results_offset += rules_print_size; 64737b6859fbSMintz, Yuval if (!rules_print_size) 6474c965db44STomer Tayar return DBG_STATUS_IDLE_CHK_PARSE_FAILED; 6475c965db44STomer Tayar } 6476c965db44STomer Tayar 6477c965db44STomer Tayar /* Print errors/warnings count */ 64787b6859fbSMintz, Yuval if (*num_errors) 6479c965db44STomer Tayar results_offset += 6480c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6481c965db44STomer Tayar results_offset), 6482c965db44STomer Tayar "\nIdle Check failed!!! (with %d errors and %d warnings)\n", 6483c965db44STomer Tayar *num_errors, *num_warnings); 64847b6859fbSMintz, Yuval else if (*num_warnings) 6485c965db44STomer Tayar results_offset += 6486c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6487c965db44STomer Tayar results_offset), 64887b6859fbSMintz, Yuval "\nIdle Check completed successfully (with %d warnings)\n", 6489c965db44STomer Tayar *num_warnings); 64907b6859fbSMintz, Yuval else 6491c965db44STomer Tayar results_offset += 6492c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6493c965db44STomer Tayar results_offset), 64947b6859fbSMintz, Yuval "\nIdle Check completed successfully\n"); 6495c965db44STomer Tayar 6496c965db44STomer Tayar /* Add 1 for string NULL termination */ 6497c965db44STomer Tayar *parsed_results_bytes = results_offset + 1; 64987b6859fbSMintz, Yuval 6499c965db44STomer Tayar return DBG_STATUS_OK; 6500c965db44STomer Tayar } 6501c965db44STomer Tayar 6502c965db44STomer Tayar /* Frees the specified MCP Trace meta data */ 6503c965db44STomer Tayar static void qed_mcp_trace_free_meta(struct qed_hwfn *p_hwfn, 6504c965db44STomer Tayar struct mcp_trace_meta *meta) 6505c965db44STomer Tayar { 6506c965db44STomer Tayar u32 i; 6507c965db44STomer Tayar 6508c965db44STomer Tayar /* Release modules */ 6509c965db44STomer Tayar if (meta->modules) { 6510c965db44STomer Tayar for (i = 0; i < meta->modules_num; i++) 6511c965db44STomer Tayar kfree(meta->modules[i]); 6512c965db44STomer Tayar kfree(meta->modules); 6513c965db44STomer Tayar } 6514c965db44STomer Tayar 6515c965db44STomer Tayar /* Release formats */ 6516c965db44STomer Tayar if (meta->formats) { 6517c965db44STomer Tayar for (i = 0; i < meta->formats_num; i++) 6518c965db44STomer Tayar kfree(meta->formats[i].format_str); 6519c965db44STomer Tayar kfree(meta->formats); 6520c965db44STomer Tayar } 6521c965db44STomer Tayar } 6522c965db44STomer Tayar 6523c965db44STomer Tayar /* Allocates and fills MCP Trace meta data based on the specified meta data 6524c965db44STomer Tayar * dump buffer. 6525c965db44STomer Tayar * Returns debug status code. 6526c965db44STomer Tayar */ 6527c965db44STomer Tayar static enum dbg_status qed_mcp_trace_alloc_meta(struct qed_hwfn *p_hwfn, 6528c965db44STomer Tayar const u32 *meta_buf, 6529c965db44STomer Tayar struct mcp_trace_meta *meta) 6530c965db44STomer Tayar { 6531c965db44STomer Tayar u8 *meta_buf_bytes = (u8 *)meta_buf; 6532c965db44STomer Tayar u32 offset = 0, signature, i; 6533c965db44STomer Tayar 6534c965db44STomer Tayar memset(meta, 0, sizeof(*meta)); 6535c965db44STomer Tayar 6536c965db44STomer Tayar /* Read first signature */ 6537c965db44STomer Tayar signature = qed_read_dword_from_buf(meta_buf_bytes, &offset); 65387b6859fbSMintz, Yuval if (signature != NVM_MAGIC_VALUE) 6539c965db44STomer Tayar return DBG_STATUS_INVALID_TRACE_SIGNATURE; 6540c965db44STomer Tayar 65417b6859fbSMintz, Yuval /* Read no. of modules and allocate memory for their pointers */ 6542c965db44STomer Tayar meta->modules_num = qed_read_byte_from_buf(meta_buf_bytes, &offset); 6543c965db44STomer Tayar meta->modules = kzalloc(meta->modules_num * sizeof(char *), GFP_KERNEL); 6544c965db44STomer Tayar if (!meta->modules) 6545c965db44STomer Tayar return DBG_STATUS_VIRT_MEM_ALLOC_FAILED; 6546c965db44STomer Tayar 6547c965db44STomer Tayar /* Allocate and read all module strings */ 6548c965db44STomer Tayar for (i = 0; i < meta->modules_num; i++) { 6549c965db44STomer Tayar u8 module_len = qed_read_byte_from_buf(meta_buf_bytes, &offset); 6550c965db44STomer Tayar 6551c965db44STomer Tayar *(meta->modules + i) = kzalloc(module_len, GFP_KERNEL); 6552c965db44STomer Tayar if (!(*(meta->modules + i))) { 6553c965db44STomer Tayar /* Update number of modules to be released */ 6554c965db44STomer Tayar meta->modules_num = i ? i - 1 : 0; 6555c965db44STomer Tayar return DBG_STATUS_VIRT_MEM_ALLOC_FAILED; 6556c965db44STomer Tayar } 6557c965db44STomer Tayar 6558c965db44STomer Tayar qed_read_str_from_buf(meta_buf_bytes, &offset, module_len, 6559c965db44STomer Tayar *(meta->modules + i)); 6560c965db44STomer Tayar if (module_len > MCP_TRACE_MAX_MODULE_LEN) 6561c965db44STomer Tayar (*(meta->modules + i))[MCP_TRACE_MAX_MODULE_LEN] = '\0'; 6562c965db44STomer Tayar } 6563c965db44STomer Tayar 6564c965db44STomer Tayar /* Read second signature */ 6565c965db44STomer Tayar signature = qed_read_dword_from_buf(meta_buf_bytes, &offset); 65667b6859fbSMintz, Yuval if (signature != NVM_MAGIC_VALUE) 6567c965db44STomer Tayar return DBG_STATUS_INVALID_TRACE_SIGNATURE; 6568c965db44STomer Tayar 6569c965db44STomer Tayar /* Read number of formats and allocate memory for all formats */ 6570c965db44STomer Tayar meta->formats_num = qed_read_dword_from_buf(meta_buf_bytes, &offset); 6571c965db44STomer Tayar meta->formats = kzalloc(meta->formats_num * 6572c965db44STomer Tayar sizeof(struct mcp_trace_format), 6573c965db44STomer Tayar GFP_KERNEL); 6574c965db44STomer Tayar if (!meta->formats) 6575c965db44STomer Tayar return DBG_STATUS_VIRT_MEM_ALLOC_FAILED; 6576c965db44STomer Tayar 6577c965db44STomer Tayar /* Allocate and read all strings */ 6578c965db44STomer Tayar for (i = 0; i < meta->formats_num; i++) { 6579c965db44STomer Tayar struct mcp_trace_format *format_ptr = &meta->formats[i]; 6580c965db44STomer Tayar u8 format_len; 6581c965db44STomer Tayar 6582c965db44STomer Tayar format_ptr->data = qed_read_dword_from_buf(meta_buf_bytes, 6583c965db44STomer Tayar &offset); 6584c965db44STomer Tayar format_len = 6585c965db44STomer Tayar (format_ptr->data & 6586c965db44STomer Tayar MCP_TRACE_FORMAT_LEN_MASK) >> MCP_TRACE_FORMAT_LEN_SHIFT; 6587c965db44STomer Tayar format_ptr->format_str = kzalloc(format_len, GFP_KERNEL); 6588c965db44STomer Tayar if (!format_ptr->format_str) { 6589c965db44STomer Tayar /* Update number of modules to be released */ 6590c965db44STomer Tayar meta->formats_num = i ? i - 1 : 0; 6591c965db44STomer Tayar return DBG_STATUS_VIRT_MEM_ALLOC_FAILED; 6592c965db44STomer Tayar } 6593c965db44STomer Tayar 6594c965db44STomer Tayar qed_read_str_from_buf(meta_buf_bytes, 6595c965db44STomer Tayar &offset, 6596c965db44STomer Tayar format_len, format_ptr->format_str); 6597c965db44STomer Tayar } 6598c965db44STomer Tayar 6599c965db44STomer Tayar return DBG_STATUS_OK; 6600c965db44STomer Tayar } 6601c965db44STomer Tayar 6602c965db44STomer Tayar /* Parses an MCP Trace dump buffer. 6603c965db44STomer Tayar * If result_buf is not NULL, the MCP Trace results are printed to it. 6604c965db44STomer Tayar * In any case, the required results buffer size is assigned to 6605c965db44STomer Tayar * parsed_results_bytes. 6606c965db44STomer Tayar * The parsing status is returned. 6607c965db44STomer Tayar */ 6608c965db44STomer Tayar static enum dbg_status qed_parse_mcp_trace_dump(struct qed_hwfn *p_hwfn, 6609c965db44STomer Tayar u32 *dump_buf, 6610c965db44STomer Tayar char *results_buf, 6611c965db44STomer Tayar u32 *parsed_results_bytes) 6612c965db44STomer Tayar { 66137b6859fbSMintz, Yuval u32 end_offset, bytes_left, trace_data_dwords, trace_meta_dwords; 66147b6859fbSMintz, Yuval u32 param_mask, param_shift, param_num_val, num_section_params; 6615c965db44STomer Tayar const char *section_name, *param_name, *param_str_val; 66167b6859fbSMintz, Yuval u32 offset, results_offset = 0; 6617c965db44STomer Tayar struct mcp_trace_meta meta; 6618c965db44STomer Tayar struct mcp_trace *trace; 6619c965db44STomer Tayar enum dbg_status status; 6620c965db44STomer Tayar const u32 *meta_buf; 6621c965db44STomer Tayar u8 *trace_buf; 6622c965db44STomer Tayar 6623c965db44STomer Tayar *parsed_results_bytes = 0; 6624c965db44STomer Tayar 6625c965db44STomer Tayar /* Read global_params section */ 6626c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 6627c965db44STomer Tayar §ion_name, &num_section_params); 6628c965db44STomer Tayar if (strcmp(section_name, "global_params")) 6629c965db44STomer Tayar return DBG_STATUS_MCP_TRACE_BAD_DATA; 6630c965db44STomer Tayar 6631c965db44STomer Tayar /* Print global params */ 6632c965db44STomer Tayar dump_buf += qed_print_section_params(dump_buf, 6633c965db44STomer Tayar num_section_params, 6634c965db44STomer Tayar results_buf, &results_offset); 6635c965db44STomer Tayar 6636c965db44STomer Tayar /* Read trace_data section */ 6637c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 6638c965db44STomer Tayar §ion_name, &num_section_params); 6639c965db44STomer Tayar if (strcmp(section_name, "mcp_trace_data") || num_section_params != 1) 6640c965db44STomer Tayar return DBG_STATUS_MCP_TRACE_BAD_DATA; 6641c965db44STomer Tayar dump_buf += qed_read_param(dump_buf, 6642c965db44STomer Tayar ¶m_name, ¶m_str_val, ¶m_num_val); 6643c965db44STomer Tayar if (strcmp(param_name, "size")) 6644c965db44STomer Tayar return DBG_STATUS_MCP_TRACE_BAD_DATA; 6645c965db44STomer Tayar trace_data_dwords = param_num_val; 6646c965db44STomer Tayar 6647c965db44STomer Tayar /* Prepare trace info */ 6648c965db44STomer Tayar trace = (struct mcp_trace *)dump_buf; 66497b6859fbSMintz, Yuval trace_buf = (u8 *)dump_buf + sizeof(*trace); 6650c965db44STomer Tayar offset = trace->trace_oldest; 6651c965db44STomer Tayar end_offset = trace->trace_prod; 6652c965db44STomer Tayar bytes_left = qed_cyclic_sub(end_offset, offset, trace->size); 6653c965db44STomer Tayar dump_buf += trace_data_dwords; 6654c965db44STomer Tayar 6655c965db44STomer Tayar /* Read meta_data section */ 6656c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 6657c965db44STomer Tayar §ion_name, &num_section_params); 6658c965db44STomer Tayar if (strcmp(section_name, "mcp_trace_meta")) 6659c965db44STomer Tayar return DBG_STATUS_MCP_TRACE_BAD_DATA; 6660c965db44STomer Tayar dump_buf += qed_read_param(dump_buf, 6661c965db44STomer Tayar ¶m_name, ¶m_str_val, ¶m_num_val); 66627b6859fbSMintz, Yuval if (strcmp(param_name, "size")) 6663c965db44STomer Tayar return DBG_STATUS_MCP_TRACE_BAD_DATA; 6664c965db44STomer Tayar trace_meta_dwords = param_num_val; 6665c965db44STomer Tayar 6666c965db44STomer Tayar /* Choose meta data buffer */ 6667c965db44STomer Tayar if (!trace_meta_dwords) { 6668c965db44STomer Tayar /* Dump doesn't include meta data */ 6669c965db44STomer Tayar if (!s_mcp_trace_meta.ptr) 6670c965db44STomer Tayar return DBG_STATUS_MCP_TRACE_NO_META; 6671c965db44STomer Tayar meta_buf = s_mcp_trace_meta.ptr; 6672c965db44STomer Tayar } else { 6673c965db44STomer Tayar /* Dump includes meta data */ 6674c965db44STomer Tayar meta_buf = dump_buf; 6675c965db44STomer Tayar } 6676c965db44STomer Tayar 6677c965db44STomer Tayar /* Allocate meta data memory */ 6678c965db44STomer Tayar status = qed_mcp_trace_alloc_meta(p_hwfn, meta_buf, &meta); 6679c965db44STomer Tayar if (status != DBG_STATUS_OK) 6680c965db44STomer Tayar goto free_mem; 6681c965db44STomer Tayar 6682c965db44STomer Tayar /* Ignore the level and modules masks - just print everything that is 6683c965db44STomer Tayar * already in the buffer. 6684c965db44STomer Tayar */ 6685c965db44STomer Tayar while (bytes_left) { 6686c965db44STomer Tayar struct mcp_trace_format *format_ptr; 6687c965db44STomer Tayar u8 format_level, format_module; 6688c965db44STomer Tayar u32 params[3] = { 0, 0, 0 }; 6689c965db44STomer Tayar u32 header, format_idx, i; 6690c965db44STomer Tayar 6691c965db44STomer Tayar if (bytes_left < MFW_TRACE_ENTRY_SIZE) { 6692c965db44STomer Tayar status = DBG_STATUS_MCP_TRACE_BAD_DATA; 6693c965db44STomer Tayar goto free_mem; 6694c965db44STomer Tayar } 6695c965db44STomer Tayar 6696c965db44STomer Tayar header = qed_read_from_cyclic_buf(trace_buf, 6697c965db44STomer Tayar &offset, 6698c965db44STomer Tayar trace->size, 6699c965db44STomer Tayar MFW_TRACE_ENTRY_SIZE); 6700c965db44STomer Tayar bytes_left -= MFW_TRACE_ENTRY_SIZE; 6701c965db44STomer Tayar format_idx = header & MFW_TRACE_EVENTID_MASK; 6702c965db44STomer Tayar 6703c965db44STomer Tayar /* Skip message if its index doesn't exist in the meta data */ 6704c965db44STomer Tayar if (format_idx > meta.formats_num) { 6705c965db44STomer Tayar u8 format_size = 6706c965db44STomer Tayar (u8)((header & 6707c965db44STomer Tayar MFW_TRACE_PRM_SIZE_MASK) >> 6708c965db44STomer Tayar MFW_TRACE_PRM_SIZE_SHIFT); 6709c965db44STomer Tayar 6710c965db44STomer Tayar if (bytes_left < format_size) { 6711c965db44STomer Tayar status = DBG_STATUS_MCP_TRACE_BAD_DATA; 6712c965db44STomer Tayar goto free_mem; 6713c965db44STomer Tayar } 6714c965db44STomer Tayar 6715c965db44STomer Tayar offset = qed_cyclic_add(offset, 6716c965db44STomer Tayar format_size, trace->size); 6717c965db44STomer Tayar bytes_left -= format_size; 6718c965db44STomer Tayar continue; 6719c965db44STomer Tayar } 6720c965db44STomer Tayar 6721c965db44STomer Tayar format_ptr = &meta.formats[format_idx]; 67227b6859fbSMintz, Yuval 6723c965db44STomer Tayar for (i = 0, 6724c965db44STomer Tayar param_mask = MCP_TRACE_FORMAT_P1_SIZE_MASK, param_shift = 6725c965db44STomer Tayar MCP_TRACE_FORMAT_P1_SIZE_SHIFT; 6726c965db44STomer Tayar i < MCP_TRACE_FORMAT_MAX_PARAMS; 6727c965db44STomer Tayar i++, param_mask <<= MCP_TRACE_FORMAT_PARAM_WIDTH, 6728c965db44STomer Tayar param_shift += MCP_TRACE_FORMAT_PARAM_WIDTH) { 6729c965db44STomer Tayar /* Extract param size (0..3) */ 6730c965db44STomer Tayar u8 param_size = 6731c965db44STomer Tayar (u8)((format_ptr->data & 6732c965db44STomer Tayar param_mask) >> param_shift); 6733c965db44STomer Tayar 6734c965db44STomer Tayar /* If the param size is zero, there are no other 6735c965db44STomer Tayar * parameters. 6736c965db44STomer Tayar */ 6737c965db44STomer Tayar if (!param_size) 6738c965db44STomer Tayar break; 6739c965db44STomer Tayar 6740c965db44STomer Tayar /* Size is encoded using 2 bits, where 3 is used to 6741c965db44STomer Tayar * encode 4. 6742c965db44STomer Tayar */ 6743c965db44STomer Tayar if (param_size == 3) 6744c965db44STomer Tayar param_size = 4; 67457b6859fbSMintz, Yuval 6746c965db44STomer Tayar if (bytes_left < param_size) { 6747c965db44STomer Tayar status = DBG_STATUS_MCP_TRACE_BAD_DATA; 6748c965db44STomer Tayar goto free_mem; 6749c965db44STomer Tayar } 6750c965db44STomer Tayar 6751c965db44STomer Tayar params[i] = qed_read_from_cyclic_buf(trace_buf, 6752c965db44STomer Tayar &offset, 6753c965db44STomer Tayar trace->size, 6754c965db44STomer Tayar param_size); 67557b6859fbSMintz, Yuval 6756c965db44STomer Tayar bytes_left -= param_size; 6757c965db44STomer Tayar } 6758c965db44STomer Tayar 6759c965db44STomer Tayar format_level = 6760c965db44STomer Tayar (u8)((format_ptr->data & 6761c965db44STomer Tayar MCP_TRACE_FORMAT_LEVEL_MASK) >> 6762c965db44STomer Tayar MCP_TRACE_FORMAT_LEVEL_SHIFT); 6763c965db44STomer Tayar format_module = 6764c965db44STomer Tayar (u8)((format_ptr->data & 6765c965db44STomer Tayar MCP_TRACE_FORMAT_MODULE_MASK) >> 6766c965db44STomer Tayar MCP_TRACE_FORMAT_MODULE_SHIFT); 6767c965db44STomer Tayar if (format_level >= ARRAY_SIZE(s_mcp_trace_level_str)) { 6768c965db44STomer Tayar status = DBG_STATUS_MCP_TRACE_BAD_DATA; 6769c965db44STomer Tayar goto free_mem; 6770c965db44STomer Tayar } 6771c965db44STomer Tayar 6772c965db44STomer Tayar /* Print current message to results buffer */ 6773c965db44STomer Tayar results_offset += 6774c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6775c965db44STomer Tayar results_offset), "%s %-8s: ", 6776c965db44STomer Tayar s_mcp_trace_level_str[format_level], 6777c965db44STomer Tayar meta.modules[format_module]); 6778c965db44STomer Tayar results_offset += 6779c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6780c965db44STomer Tayar results_offset), 6781c965db44STomer Tayar format_ptr->format_str, params[0], params[1], 6782c965db44STomer Tayar params[2]); 6783c965db44STomer Tayar } 6784c965db44STomer Tayar 6785c965db44STomer Tayar free_mem: 6786c965db44STomer Tayar *parsed_results_bytes = results_offset + 1; 6787c965db44STomer Tayar qed_mcp_trace_free_meta(p_hwfn, &meta); 6788c965db44STomer Tayar return status; 6789c965db44STomer Tayar } 6790c965db44STomer Tayar 6791c965db44STomer Tayar /* Parses a Reg FIFO dump buffer. 6792c965db44STomer Tayar * If result_buf is not NULL, the Reg FIFO results are printed to it. 6793c965db44STomer Tayar * In any case, the required results buffer size is assigned to 6794c965db44STomer Tayar * parsed_results_bytes. 6795c965db44STomer Tayar * The parsing status is returned. 6796c965db44STomer Tayar */ 6797da090917STomer Tayar static enum dbg_status qed_parse_reg_fifo_dump(u32 *dump_buf, 6798c965db44STomer Tayar char *results_buf, 6799c965db44STomer Tayar u32 *parsed_results_bytes) 6800c965db44STomer Tayar { 6801c965db44STomer Tayar const char *section_name, *param_name, *param_str_val; 68027b6859fbSMintz, Yuval u32 param_num_val, num_section_params, num_elements; 6803c965db44STomer Tayar struct reg_fifo_element *elements; 6804c965db44STomer Tayar u8 i, j, err_val, vf_val; 68057b6859fbSMintz, Yuval u32 results_offset = 0; 6806c965db44STomer Tayar char vf_str[4]; 6807c965db44STomer Tayar 6808c965db44STomer Tayar /* Read global_params section */ 6809c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 6810c965db44STomer Tayar §ion_name, &num_section_params); 6811c965db44STomer Tayar if (strcmp(section_name, "global_params")) 6812c965db44STomer Tayar return DBG_STATUS_REG_FIFO_BAD_DATA; 6813c965db44STomer Tayar 6814c965db44STomer Tayar /* Print global params */ 6815c965db44STomer Tayar dump_buf += qed_print_section_params(dump_buf, 6816c965db44STomer Tayar num_section_params, 6817c965db44STomer Tayar results_buf, &results_offset); 6818c965db44STomer Tayar 6819c965db44STomer Tayar /* Read reg_fifo_data section */ 6820c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 6821c965db44STomer Tayar §ion_name, &num_section_params); 6822c965db44STomer Tayar if (strcmp(section_name, "reg_fifo_data")) 6823c965db44STomer Tayar return DBG_STATUS_REG_FIFO_BAD_DATA; 6824c965db44STomer Tayar dump_buf += qed_read_param(dump_buf, 6825c965db44STomer Tayar ¶m_name, ¶m_str_val, ¶m_num_val); 6826c965db44STomer Tayar if (strcmp(param_name, "size")) 6827c965db44STomer Tayar return DBG_STATUS_REG_FIFO_BAD_DATA; 6828c965db44STomer Tayar if (param_num_val % REG_FIFO_ELEMENT_DWORDS) 6829c965db44STomer Tayar return DBG_STATUS_REG_FIFO_BAD_DATA; 6830c965db44STomer Tayar num_elements = param_num_val / REG_FIFO_ELEMENT_DWORDS; 6831c965db44STomer Tayar elements = (struct reg_fifo_element *)dump_buf; 6832c965db44STomer Tayar 6833c965db44STomer Tayar /* Decode elements */ 6834c965db44STomer Tayar for (i = 0; i < num_elements; i++) { 6835c965db44STomer Tayar bool err_printed = false; 6836c965db44STomer Tayar 6837c965db44STomer Tayar /* Discover if element belongs to a VF or a PF */ 6838c965db44STomer Tayar vf_val = GET_FIELD(elements[i].data, REG_FIFO_ELEMENT_VF); 6839c965db44STomer Tayar if (vf_val == REG_FIFO_ELEMENT_IS_PF_VF_VAL) 6840c965db44STomer Tayar sprintf(vf_str, "%s", "N/A"); 6841c965db44STomer Tayar else 6842c965db44STomer Tayar sprintf(vf_str, "%d", vf_val); 6843c965db44STomer Tayar 6844c965db44STomer Tayar /* Add parsed element to parsed buffer */ 6845c965db44STomer Tayar results_offset += 6846c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6847c965db44STomer Tayar results_offset), 6848be086e7cSMintz, Yuval "raw: 0x%016llx, address: 0x%07x, access: %-5s, pf: %2d, vf: %s, port: %d, privilege: %-3s, protection: %-12s, master: %-4s, errors: ", 6849c965db44STomer Tayar elements[i].data, 6850be086e7cSMintz, Yuval (u32)GET_FIELD(elements[i].data, 6851c965db44STomer Tayar REG_FIFO_ELEMENT_ADDRESS) * 6852c965db44STomer Tayar REG_FIFO_ELEMENT_ADDR_FACTOR, 6853c965db44STomer Tayar s_access_strs[GET_FIELD(elements[i].data, 6854c965db44STomer Tayar REG_FIFO_ELEMENT_ACCESS)], 6855be086e7cSMintz, Yuval (u32)GET_FIELD(elements[i].data, 68567b6859fbSMintz, Yuval REG_FIFO_ELEMENT_PF), 68577b6859fbSMintz, Yuval vf_str, 6858be086e7cSMintz, Yuval (u32)GET_FIELD(elements[i].data, 6859c965db44STomer Tayar REG_FIFO_ELEMENT_PORT), 68607b6859fbSMintz, Yuval s_privilege_strs[GET_FIELD(elements[i].data, 6861c965db44STomer Tayar REG_FIFO_ELEMENT_PRIVILEGE)], 6862c965db44STomer Tayar s_protection_strs[GET_FIELD(elements[i].data, 6863c965db44STomer Tayar REG_FIFO_ELEMENT_PROTECTION)], 6864c965db44STomer Tayar s_master_strs[GET_FIELD(elements[i].data, 6865c965db44STomer Tayar REG_FIFO_ELEMENT_MASTER)]); 6866c965db44STomer Tayar 6867c965db44STomer Tayar /* Print errors */ 6868c965db44STomer Tayar for (j = 0, 6869c965db44STomer Tayar err_val = GET_FIELD(elements[i].data, 6870c965db44STomer Tayar REG_FIFO_ELEMENT_ERROR); 6871c965db44STomer Tayar j < ARRAY_SIZE(s_reg_fifo_error_strs); 6872c965db44STomer Tayar j++, err_val >>= 1) { 68737b6859fbSMintz, Yuval if (err_val & 0x1) { 6874c965db44STomer Tayar if (err_printed) 6875c965db44STomer Tayar results_offset += 68767b6859fbSMintz, Yuval sprintf(qed_get_buf_ptr 68777b6859fbSMintz, Yuval (results_buf, 68787b6859fbSMintz, Yuval results_offset), ", "); 6879c965db44STomer Tayar results_offset += 68807b6859fbSMintz, Yuval sprintf(qed_get_buf_ptr 68817b6859fbSMintz, Yuval (results_buf, results_offset), "%s", 6882c965db44STomer Tayar s_reg_fifo_error_strs[j]); 6883c965db44STomer Tayar err_printed = true; 6884c965db44STomer Tayar } 68857b6859fbSMintz, Yuval } 6886c965db44STomer Tayar 6887c965db44STomer Tayar results_offset += 6888c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, results_offset), "\n"); 6889c965db44STomer Tayar } 6890c965db44STomer Tayar 6891c965db44STomer Tayar results_offset += sprintf(qed_get_buf_ptr(results_buf, 6892c965db44STomer Tayar results_offset), 6893c965db44STomer Tayar "fifo contained %d elements", num_elements); 6894c965db44STomer Tayar 6895c965db44STomer Tayar /* Add 1 for string NULL termination */ 6896c965db44STomer Tayar *parsed_results_bytes = results_offset + 1; 68977b6859fbSMintz, Yuval 6898c965db44STomer Tayar return DBG_STATUS_OK; 6899c965db44STomer Tayar } 6900c965db44STomer Tayar 69017b6859fbSMintz, Yuval static enum dbg_status qed_parse_igu_fifo_element(struct igu_fifo_element 69027b6859fbSMintz, Yuval *element, char 69037b6859fbSMintz, Yuval *results_buf, 6904da090917STomer Tayar u32 *results_offset) 6905c965db44STomer Tayar { 69067b6859fbSMintz, Yuval const struct igu_fifo_addr_data *found_addr = NULL; 69077b6859fbSMintz, Yuval u8 source, err_type, i, is_cleanup; 69087b6859fbSMintz, Yuval char parsed_addr_data[32]; 69097b6859fbSMintz, Yuval char parsed_wr_data[256]; 69107b6859fbSMintz, Yuval u32 wr_data, prod_cons; 69117b6859fbSMintz, Yuval bool is_wr_cmd, is_pf; 69127b6859fbSMintz, Yuval u16 cmd_addr; 69137b6859fbSMintz, Yuval u64 dword12; 69147b6859fbSMintz, Yuval 69157b6859fbSMintz, Yuval /* Dword12 (dword index 1 and 2) contains bits 32..95 of the 69167b6859fbSMintz, Yuval * FIFO element. 69177b6859fbSMintz, Yuval */ 69187b6859fbSMintz, Yuval dword12 = ((u64)element->dword2 << 32) | element->dword1; 69197b6859fbSMintz, Yuval is_wr_cmd = GET_FIELD(dword12, IGU_FIFO_ELEMENT_DWORD12_IS_WR_CMD); 69207b6859fbSMintz, Yuval is_pf = GET_FIELD(element->dword0, IGU_FIFO_ELEMENT_DWORD0_IS_PF); 69217b6859fbSMintz, Yuval cmd_addr = GET_FIELD(element->dword0, IGU_FIFO_ELEMENT_DWORD0_CMD_ADDR); 69227b6859fbSMintz, Yuval source = GET_FIELD(element->dword0, IGU_FIFO_ELEMENT_DWORD0_SOURCE); 69237b6859fbSMintz, Yuval err_type = GET_FIELD(element->dword0, IGU_FIFO_ELEMENT_DWORD0_ERR_TYPE); 69247b6859fbSMintz, Yuval 69257b6859fbSMintz, Yuval if (source >= ARRAY_SIZE(s_igu_fifo_source_strs)) 69267b6859fbSMintz, Yuval return DBG_STATUS_IGU_FIFO_BAD_DATA; 69277b6859fbSMintz, Yuval if (err_type >= ARRAY_SIZE(s_igu_fifo_error_strs)) 69287b6859fbSMintz, Yuval return DBG_STATUS_IGU_FIFO_BAD_DATA; 69297b6859fbSMintz, Yuval 69307b6859fbSMintz, Yuval /* Find address data */ 69317b6859fbSMintz, Yuval for (i = 0; i < ARRAY_SIZE(s_igu_fifo_addr_data) && !found_addr; i++) { 69327b6859fbSMintz, Yuval const struct igu_fifo_addr_data *curr_addr = 69337b6859fbSMintz, Yuval &s_igu_fifo_addr_data[i]; 69347b6859fbSMintz, Yuval 69357b6859fbSMintz, Yuval if (cmd_addr >= curr_addr->start_addr && cmd_addr <= 69367b6859fbSMintz, Yuval curr_addr->end_addr) 69377b6859fbSMintz, Yuval found_addr = curr_addr; 6938c965db44STomer Tayar } 6939c965db44STomer Tayar 69407b6859fbSMintz, Yuval if (!found_addr) 69417b6859fbSMintz, Yuval return DBG_STATUS_IGU_FIFO_BAD_DATA; 6942c965db44STomer Tayar 69437b6859fbSMintz, Yuval /* Prepare parsed address data */ 69447b6859fbSMintz, Yuval switch (found_addr->type) { 69457b6859fbSMintz, Yuval case IGU_ADDR_TYPE_MSIX_MEM: 69467b6859fbSMintz, Yuval sprintf(parsed_addr_data, " vector_num = 0x%x", cmd_addr / 2); 69477b6859fbSMintz, Yuval break; 69487b6859fbSMintz, Yuval case IGU_ADDR_TYPE_WRITE_INT_ACK: 69497b6859fbSMintz, Yuval case IGU_ADDR_TYPE_WRITE_PROD_UPDATE: 69507b6859fbSMintz, Yuval sprintf(parsed_addr_data, 69517b6859fbSMintz, Yuval " SB = 0x%x", cmd_addr - found_addr->start_addr); 69527b6859fbSMintz, Yuval break; 69537b6859fbSMintz, Yuval default: 69547b6859fbSMintz, Yuval parsed_addr_data[0] = '\0'; 69557b6859fbSMintz, Yuval } 69567b6859fbSMintz, Yuval 69577b6859fbSMintz, Yuval if (!is_wr_cmd) { 69587b6859fbSMintz, Yuval parsed_wr_data[0] = '\0'; 69597b6859fbSMintz, Yuval goto out; 69607b6859fbSMintz, Yuval } 69617b6859fbSMintz, Yuval 69627b6859fbSMintz, Yuval /* Prepare parsed write data */ 69637b6859fbSMintz, Yuval wr_data = GET_FIELD(dword12, IGU_FIFO_ELEMENT_DWORD12_WR_DATA); 69647b6859fbSMintz, Yuval prod_cons = GET_FIELD(wr_data, IGU_FIFO_WR_DATA_PROD_CONS); 69657b6859fbSMintz, Yuval is_cleanup = GET_FIELD(wr_data, IGU_FIFO_WR_DATA_CMD_TYPE); 69667b6859fbSMintz, Yuval 69677b6859fbSMintz, Yuval if (source == IGU_SRC_ATTN) { 69687b6859fbSMintz, Yuval sprintf(parsed_wr_data, "prod: 0x%x, ", prod_cons); 69697b6859fbSMintz, Yuval } else { 69707b6859fbSMintz, Yuval if (is_cleanup) { 69717b6859fbSMintz, Yuval u8 cleanup_val, cleanup_type; 69727b6859fbSMintz, Yuval 69737b6859fbSMintz, Yuval cleanup_val = 69747b6859fbSMintz, Yuval GET_FIELD(wr_data, 69757b6859fbSMintz, Yuval IGU_FIFO_CLEANUP_WR_DATA_CLEANUP_VAL); 69767b6859fbSMintz, Yuval cleanup_type = 69777b6859fbSMintz, Yuval GET_FIELD(wr_data, 69787b6859fbSMintz, Yuval IGU_FIFO_CLEANUP_WR_DATA_CLEANUP_TYPE); 69797b6859fbSMintz, Yuval 69807b6859fbSMintz, Yuval sprintf(parsed_wr_data, 69817b6859fbSMintz, Yuval "cmd_type: cleanup, cleanup_val: %s, cleanup_type : %d, ", 69827b6859fbSMintz, Yuval cleanup_val ? "set" : "clear", 69837b6859fbSMintz, Yuval cleanup_type); 69847b6859fbSMintz, Yuval } else { 69857b6859fbSMintz, Yuval u8 update_flag, en_dis_int_for_sb, segment; 69867b6859fbSMintz, Yuval u8 timer_mask; 69877b6859fbSMintz, Yuval 69887b6859fbSMintz, Yuval update_flag = GET_FIELD(wr_data, 69897b6859fbSMintz, Yuval IGU_FIFO_WR_DATA_UPDATE_FLAG); 69907b6859fbSMintz, Yuval en_dis_int_for_sb = 69917b6859fbSMintz, Yuval GET_FIELD(wr_data, 69927b6859fbSMintz, Yuval IGU_FIFO_WR_DATA_EN_DIS_INT_FOR_SB); 69937b6859fbSMintz, Yuval segment = GET_FIELD(wr_data, 69947b6859fbSMintz, Yuval IGU_FIFO_WR_DATA_SEGMENT); 69957b6859fbSMintz, Yuval timer_mask = GET_FIELD(wr_data, 69967b6859fbSMintz, Yuval IGU_FIFO_WR_DATA_TIMER_MASK); 69977b6859fbSMintz, Yuval 69987b6859fbSMintz, Yuval sprintf(parsed_wr_data, 69997b6859fbSMintz, Yuval "cmd_type: prod/cons update, prod/cons: 0x%x, update_flag: %s, en_dis_int_for_sb : %s, segment : %s, timer_mask = %d, ", 70007b6859fbSMintz, Yuval prod_cons, 70017b6859fbSMintz, Yuval update_flag ? "update" : "nop", 7002da090917STomer Tayar en_dis_int_for_sb ? 7003da090917STomer Tayar (en_dis_int_for_sb == 1 ? "disable" : "nop") : 7004da090917STomer Tayar "enable", 70057b6859fbSMintz, Yuval segment ? "attn" : "regular", 70067b6859fbSMintz, Yuval timer_mask); 70077b6859fbSMintz, Yuval } 70087b6859fbSMintz, Yuval } 70097b6859fbSMintz, Yuval out: 70107b6859fbSMintz, Yuval /* Add parsed element to parsed buffer */ 70117b6859fbSMintz, Yuval *results_offset += sprintf(qed_get_buf_ptr(results_buf, 70127b6859fbSMintz, Yuval *results_offset), 70137b6859fbSMintz, Yuval "raw: 0x%01x%08x%08x, %s: %d, source : %s, type : %s, cmd_addr : 0x%x(%s%s), %serror: %s\n", 70147b6859fbSMintz, Yuval element->dword2, element->dword1, 70157b6859fbSMintz, Yuval element->dword0, 70167b6859fbSMintz, Yuval is_pf ? "pf" : "vf", 70177b6859fbSMintz, Yuval GET_FIELD(element->dword0, 70187b6859fbSMintz, Yuval IGU_FIFO_ELEMENT_DWORD0_FID), 70197b6859fbSMintz, Yuval s_igu_fifo_source_strs[source], 70207b6859fbSMintz, Yuval is_wr_cmd ? "wr" : "rd", 70217b6859fbSMintz, Yuval cmd_addr, 70227b6859fbSMintz, Yuval (!is_pf && found_addr->vf_desc) 70237b6859fbSMintz, Yuval ? found_addr->vf_desc 70247b6859fbSMintz, Yuval : found_addr->desc, 70257b6859fbSMintz, Yuval parsed_addr_data, 70267b6859fbSMintz, Yuval parsed_wr_data, 70277b6859fbSMintz, Yuval s_igu_fifo_error_strs[err_type]); 70287b6859fbSMintz, Yuval 70297b6859fbSMintz, Yuval return DBG_STATUS_OK; 7030c965db44STomer Tayar } 7031c965db44STomer Tayar 7032c965db44STomer Tayar /* Parses an IGU FIFO dump buffer. 7033c965db44STomer Tayar * If result_buf is not NULL, the IGU FIFO results are printed to it. 7034c965db44STomer Tayar * In any case, the required results buffer size is assigned to 7035c965db44STomer Tayar * parsed_results_bytes. 7036c965db44STomer Tayar * The parsing status is returned. 7037c965db44STomer Tayar */ 7038da090917STomer Tayar static enum dbg_status qed_parse_igu_fifo_dump(u32 *dump_buf, 7039c965db44STomer Tayar char *results_buf, 7040c965db44STomer Tayar u32 *parsed_results_bytes) 7041c965db44STomer Tayar { 7042c965db44STomer Tayar const char *section_name, *param_name, *param_str_val; 70437b6859fbSMintz, Yuval u32 param_num_val, num_section_params, num_elements; 7044c965db44STomer Tayar struct igu_fifo_element *elements; 70457b6859fbSMintz, Yuval enum dbg_status status; 70467b6859fbSMintz, Yuval u32 results_offset = 0; 70477b6859fbSMintz, Yuval u8 i; 7048c965db44STomer Tayar 7049c965db44STomer Tayar /* Read global_params section */ 7050c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 7051c965db44STomer Tayar §ion_name, &num_section_params); 7052c965db44STomer Tayar if (strcmp(section_name, "global_params")) 7053c965db44STomer Tayar return DBG_STATUS_IGU_FIFO_BAD_DATA; 7054c965db44STomer Tayar 7055c965db44STomer Tayar /* Print global params */ 7056c965db44STomer Tayar dump_buf += qed_print_section_params(dump_buf, 7057c965db44STomer Tayar num_section_params, 7058c965db44STomer Tayar results_buf, &results_offset); 7059c965db44STomer Tayar 7060c965db44STomer Tayar /* Read igu_fifo_data section */ 7061c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 7062c965db44STomer Tayar §ion_name, &num_section_params); 7063c965db44STomer Tayar if (strcmp(section_name, "igu_fifo_data")) 7064c965db44STomer Tayar return DBG_STATUS_IGU_FIFO_BAD_DATA; 7065c965db44STomer Tayar dump_buf += qed_read_param(dump_buf, 7066c965db44STomer Tayar ¶m_name, ¶m_str_val, ¶m_num_val); 7067c965db44STomer Tayar if (strcmp(param_name, "size")) 7068c965db44STomer Tayar return DBG_STATUS_IGU_FIFO_BAD_DATA; 7069c965db44STomer Tayar if (param_num_val % IGU_FIFO_ELEMENT_DWORDS) 7070c965db44STomer Tayar return DBG_STATUS_IGU_FIFO_BAD_DATA; 7071c965db44STomer Tayar num_elements = param_num_val / IGU_FIFO_ELEMENT_DWORDS; 7072c965db44STomer Tayar elements = (struct igu_fifo_element *)dump_buf; 7073c965db44STomer Tayar 7074c965db44STomer Tayar /* Decode elements */ 7075c965db44STomer Tayar for (i = 0; i < num_elements; i++) { 70767b6859fbSMintz, Yuval status = qed_parse_igu_fifo_element(&elements[i], 70777b6859fbSMintz, Yuval results_buf, 7078da090917STomer Tayar &results_offset); 70797b6859fbSMintz, Yuval if (status != DBG_STATUS_OK) 70807b6859fbSMintz, Yuval return status; 7081c965db44STomer Tayar } 7082c965db44STomer Tayar 7083c965db44STomer Tayar results_offset += sprintf(qed_get_buf_ptr(results_buf, 7084c965db44STomer Tayar results_offset), 7085c965db44STomer Tayar "fifo contained %d elements", num_elements); 7086c965db44STomer Tayar 7087c965db44STomer Tayar /* Add 1 for string NULL termination */ 7088c965db44STomer Tayar *parsed_results_bytes = results_offset + 1; 70897b6859fbSMintz, Yuval 7090c965db44STomer Tayar return DBG_STATUS_OK; 7091c965db44STomer Tayar } 7092c965db44STomer Tayar 7093c965db44STomer Tayar static enum dbg_status 7094da090917STomer Tayar qed_parse_protection_override_dump(u32 *dump_buf, 7095c965db44STomer Tayar char *results_buf, 7096c965db44STomer Tayar u32 *parsed_results_bytes) 7097c965db44STomer Tayar { 7098c965db44STomer Tayar const char *section_name, *param_name, *param_str_val; 70997b6859fbSMintz, Yuval u32 param_num_val, num_section_params, num_elements; 7100c965db44STomer Tayar struct protection_override_element *elements; 71017b6859fbSMintz, Yuval u32 results_offset = 0; 7102c965db44STomer Tayar u8 i; 7103c965db44STomer Tayar 7104c965db44STomer Tayar /* Read global_params section */ 7105c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 7106c965db44STomer Tayar §ion_name, &num_section_params); 7107c965db44STomer Tayar if (strcmp(section_name, "global_params")) 7108c965db44STomer Tayar return DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA; 7109c965db44STomer Tayar 7110c965db44STomer Tayar /* Print global params */ 7111c965db44STomer Tayar dump_buf += qed_print_section_params(dump_buf, 7112c965db44STomer Tayar num_section_params, 7113c965db44STomer Tayar results_buf, &results_offset); 7114c965db44STomer Tayar 7115c965db44STomer Tayar /* Read protection_override_data section */ 7116c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 7117c965db44STomer Tayar §ion_name, &num_section_params); 7118c965db44STomer Tayar if (strcmp(section_name, "protection_override_data")) 7119c965db44STomer Tayar return DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA; 7120c965db44STomer Tayar dump_buf += qed_read_param(dump_buf, 7121c965db44STomer Tayar ¶m_name, ¶m_str_val, ¶m_num_val); 7122c965db44STomer Tayar if (strcmp(param_name, "size")) 7123c965db44STomer Tayar return DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA; 71247b6859fbSMintz, Yuval if (param_num_val % PROTECTION_OVERRIDE_ELEMENT_DWORDS) 7125c965db44STomer Tayar return DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA; 7126c965db44STomer Tayar num_elements = param_num_val / PROTECTION_OVERRIDE_ELEMENT_DWORDS; 7127c965db44STomer Tayar elements = (struct protection_override_element *)dump_buf; 7128c965db44STomer Tayar 7129c965db44STomer Tayar /* Decode elements */ 7130c965db44STomer Tayar for (i = 0; i < num_elements; i++) { 7131c965db44STomer Tayar u32 address = GET_FIELD(elements[i].data, 7132c965db44STomer Tayar PROTECTION_OVERRIDE_ELEMENT_ADDRESS) * 7133c965db44STomer Tayar PROTECTION_OVERRIDE_ELEMENT_ADDR_FACTOR; 7134c965db44STomer Tayar 7135c965db44STomer Tayar results_offset += 7136c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 7137c965db44STomer Tayar results_offset), 7138be086e7cSMintz, Yuval "window %2d, address: 0x%07x, size: %7d regs, read: %d, write: %d, read protection: %-12s, write protection: %-12s\n", 7139c965db44STomer Tayar i, address, 7140be086e7cSMintz, Yuval (u32)GET_FIELD(elements[i].data, 7141c965db44STomer Tayar PROTECTION_OVERRIDE_ELEMENT_WINDOW_SIZE), 7142be086e7cSMintz, Yuval (u32)GET_FIELD(elements[i].data, 7143c965db44STomer Tayar PROTECTION_OVERRIDE_ELEMENT_READ), 7144be086e7cSMintz, Yuval (u32)GET_FIELD(elements[i].data, 7145c965db44STomer Tayar PROTECTION_OVERRIDE_ELEMENT_WRITE), 7146c965db44STomer Tayar s_protection_strs[GET_FIELD(elements[i].data, 7147c965db44STomer Tayar PROTECTION_OVERRIDE_ELEMENT_READ_PROTECTION)], 7148c965db44STomer Tayar s_protection_strs[GET_FIELD(elements[i].data, 7149c965db44STomer Tayar PROTECTION_OVERRIDE_ELEMENT_WRITE_PROTECTION)]); 7150c965db44STomer Tayar } 7151c965db44STomer Tayar 7152c965db44STomer Tayar results_offset += sprintf(qed_get_buf_ptr(results_buf, 7153c965db44STomer Tayar results_offset), 7154c965db44STomer Tayar "protection override contained %d elements", 7155c965db44STomer Tayar num_elements); 7156c965db44STomer Tayar 7157c965db44STomer Tayar /* Add 1 for string NULL termination */ 7158c965db44STomer Tayar *parsed_results_bytes = results_offset + 1; 71597b6859fbSMintz, Yuval 7160c965db44STomer Tayar return DBG_STATUS_OK; 7161c965db44STomer Tayar } 7162c965db44STomer Tayar 71637b6859fbSMintz, Yuval /* Parses a FW Asserts dump buffer. 71647b6859fbSMintz, Yuval * If result_buf is not NULL, the FW Asserts results are printed to it. 71657b6859fbSMintz, Yuval * In any case, the required results buffer size is assigned to 71667b6859fbSMintz, Yuval * parsed_results_bytes. 71677b6859fbSMintz, Yuval * The parsing status is returned. 71687b6859fbSMintz, Yuval */ 7169da090917STomer Tayar static enum dbg_status qed_parse_fw_asserts_dump(u32 *dump_buf, 71707b6859fbSMintz, Yuval char *results_buf, 71717b6859fbSMintz, Yuval u32 *parsed_results_bytes) 71727b6859fbSMintz, Yuval { 71737b6859fbSMintz, Yuval u32 num_section_params, param_num_val, i, results_offset = 0; 71747b6859fbSMintz, Yuval const char *param_name, *param_str_val, *section_name; 71757b6859fbSMintz, Yuval bool last_section_found = false; 71767b6859fbSMintz, Yuval 71777b6859fbSMintz, Yuval *parsed_results_bytes = 0; 71787b6859fbSMintz, Yuval 71797b6859fbSMintz, Yuval /* Read global_params section */ 71807b6859fbSMintz, Yuval dump_buf += qed_read_section_hdr(dump_buf, 71817b6859fbSMintz, Yuval §ion_name, &num_section_params); 71827b6859fbSMintz, Yuval if (strcmp(section_name, "global_params")) 71837b6859fbSMintz, Yuval return DBG_STATUS_FW_ASSERTS_PARSE_FAILED; 71847b6859fbSMintz, Yuval 71857b6859fbSMintz, Yuval /* Print global params */ 71867b6859fbSMintz, Yuval dump_buf += qed_print_section_params(dump_buf, 71877b6859fbSMintz, Yuval num_section_params, 71887b6859fbSMintz, Yuval results_buf, &results_offset); 71897b6859fbSMintz, Yuval 71907b6859fbSMintz, Yuval while (!last_section_found) { 71917b6859fbSMintz, Yuval dump_buf += qed_read_section_hdr(dump_buf, 71927b6859fbSMintz, Yuval §ion_name, 71937b6859fbSMintz, Yuval &num_section_params); 71947b6859fbSMintz, Yuval if (!strcmp(section_name, "fw_asserts")) { 71957b6859fbSMintz, Yuval /* Extract params */ 71967b6859fbSMintz, Yuval const char *storm_letter = NULL; 71977b6859fbSMintz, Yuval u32 storm_dump_size = 0; 71987b6859fbSMintz, Yuval 71997b6859fbSMintz, Yuval for (i = 0; i < num_section_params; i++) { 72007b6859fbSMintz, Yuval dump_buf += qed_read_param(dump_buf, 72017b6859fbSMintz, Yuval ¶m_name, 72027b6859fbSMintz, Yuval ¶m_str_val, 72037b6859fbSMintz, Yuval ¶m_num_val); 72047b6859fbSMintz, Yuval if (!strcmp(param_name, "storm")) 72057b6859fbSMintz, Yuval storm_letter = param_str_val; 72067b6859fbSMintz, Yuval else if (!strcmp(param_name, "size")) 72077b6859fbSMintz, Yuval storm_dump_size = param_num_val; 72087b6859fbSMintz, Yuval else 72097b6859fbSMintz, Yuval return 72107b6859fbSMintz, Yuval DBG_STATUS_FW_ASSERTS_PARSE_FAILED; 72117b6859fbSMintz, Yuval } 72127b6859fbSMintz, Yuval 72137b6859fbSMintz, Yuval if (!storm_letter || !storm_dump_size) 72147b6859fbSMintz, Yuval return DBG_STATUS_FW_ASSERTS_PARSE_FAILED; 72157b6859fbSMintz, Yuval 72167b6859fbSMintz, Yuval /* Print data */ 72177b6859fbSMintz, Yuval results_offset += 72187b6859fbSMintz, Yuval sprintf(qed_get_buf_ptr(results_buf, 72197b6859fbSMintz, Yuval results_offset), 72207b6859fbSMintz, Yuval "\n%sSTORM_ASSERT: size=%d\n", 72217b6859fbSMintz, Yuval storm_letter, storm_dump_size); 72227b6859fbSMintz, Yuval for (i = 0; i < storm_dump_size; i++, dump_buf++) 72237b6859fbSMintz, Yuval results_offset += 72247b6859fbSMintz, Yuval sprintf(qed_get_buf_ptr(results_buf, 72257b6859fbSMintz, Yuval results_offset), 72267b6859fbSMintz, Yuval "%08x\n", *dump_buf); 72277b6859fbSMintz, Yuval } else if (!strcmp(section_name, "last")) { 72287b6859fbSMintz, Yuval last_section_found = true; 72297b6859fbSMintz, Yuval } else { 72307b6859fbSMintz, Yuval return DBG_STATUS_FW_ASSERTS_PARSE_FAILED; 72317b6859fbSMintz, Yuval } 72327b6859fbSMintz, Yuval } 72337b6859fbSMintz, Yuval 72347b6859fbSMintz, Yuval /* Add 1 for string NULL termination */ 72357b6859fbSMintz, Yuval *parsed_results_bytes = results_offset + 1; 72367b6859fbSMintz, Yuval 72377b6859fbSMintz, Yuval return DBG_STATUS_OK; 72387b6859fbSMintz, Yuval } 72397b6859fbSMintz, Yuval 72407b6859fbSMintz, Yuval /***************************** Public Functions *******************************/ 72417b6859fbSMintz, Yuval 72427b6859fbSMintz, Yuval enum dbg_status qed_dbg_user_set_bin_ptr(const u8 * const bin_ptr) 72437b6859fbSMintz, Yuval { 72447b6859fbSMintz, Yuval struct bin_buffer_hdr *buf_array = (struct bin_buffer_hdr *)bin_ptr; 72457b6859fbSMintz, Yuval u8 buf_id; 72467b6859fbSMintz, Yuval 72477b6859fbSMintz, Yuval /* Convert binary data to debug arrays */ 72487b6859fbSMintz, Yuval for (buf_id = 0; buf_id < MAX_BIN_DBG_BUFFER_TYPE; buf_id++) { 72497b6859fbSMintz, Yuval s_user_dbg_arrays[buf_id].ptr = 72507b6859fbSMintz, Yuval (u32 *)(bin_ptr + buf_array[buf_id].offset); 72517b6859fbSMintz, Yuval s_user_dbg_arrays[buf_id].size_in_dwords = 72527b6859fbSMintz, Yuval BYTES_TO_DWORDS(buf_array[buf_id].length); 72537b6859fbSMintz, Yuval } 72547b6859fbSMintz, Yuval 72557b6859fbSMintz, Yuval return DBG_STATUS_OK; 72567b6859fbSMintz, Yuval } 72577b6859fbSMintz, Yuval 72587b6859fbSMintz, Yuval const char *qed_dbg_get_status_str(enum dbg_status status) 72597b6859fbSMintz, Yuval { 72607b6859fbSMintz, Yuval return (status < 72617b6859fbSMintz, Yuval MAX_DBG_STATUS) ? s_status_str[status] : "Invalid debug status"; 72627b6859fbSMintz, Yuval } 72637b6859fbSMintz, Yuval 72647b6859fbSMintz, Yuval enum dbg_status qed_get_idle_chk_results_buf_size(struct qed_hwfn *p_hwfn, 72657b6859fbSMintz, Yuval u32 *dump_buf, 72667b6859fbSMintz, Yuval u32 num_dumped_dwords, 72677b6859fbSMintz, Yuval u32 *results_buf_size) 72687b6859fbSMintz, Yuval { 72697b6859fbSMintz, Yuval u32 num_errors, num_warnings; 72707b6859fbSMintz, Yuval 7271da090917STomer Tayar return qed_parse_idle_chk_dump(dump_buf, 72727b6859fbSMintz, Yuval num_dumped_dwords, 72737b6859fbSMintz, Yuval NULL, 72747b6859fbSMintz, Yuval results_buf_size, 72757b6859fbSMintz, Yuval &num_errors, &num_warnings); 72767b6859fbSMintz, Yuval } 72777b6859fbSMintz, Yuval 72787b6859fbSMintz, Yuval enum dbg_status qed_print_idle_chk_results(struct qed_hwfn *p_hwfn, 72797b6859fbSMintz, Yuval u32 *dump_buf, 72807b6859fbSMintz, Yuval u32 num_dumped_dwords, 72817b6859fbSMintz, Yuval char *results_buf, 7282da090917STomer Tayar u32 *num_errors, 7283da090917STomer Tayar u32 *num_warnings) 72847b6859fbSMintz, Yuval { 72857b6859fbSMintz, Yuval u32 parsed_buf_size; 72867b6859fbSMintz, Yuval 7287da090917STomer Tayar return qed_parse_idle_chk_dump(dump_buf, 72887b6859fbSMintz, Yuval num_dumped_dwords, 72897b6859fbSMintz, Yuval results_buf, 72907b6859fbSMintz, Yuval &parsed_buf_size, 72917b6859fbSMintz, Yuval num_errors, num_warnings); 72927b6859fbSMintz, Yuval } 72937b6859fbSMintz, Yuval 72947b6859fbSMintz, Yuval void qed_dbg_mcp_trace_set_meta_data(u32 *data, u32 size) 72957b6859fbSMintz, Yuval { 72967b6859fbSMintz, Yuval s_mcp_trace_meta.ptr = data; 72977b6859fbSMintz, Yuval s_mcp_trace_meta.size_in_dwords = size; 72987b6859fbSMintz, Yuval } 72997b6859fbSMintz, Yuval 73007b6859fbSMintz, Yuval enum dbg_status qed_get_mcp_trace_results_buf_size(struct qed_hwfn *p_hwfn, 73017b6859fbSMintz, Yuval u32 *dump_buf, 73027b6859fbSMintz, Yuval u32 num_dumped_dwords, 73037b6859fbSMintz, Yuval u32 *results_buf_size) 73047b6859fbSMintz, Yuval { 73057b6859fbSMintz, Yuval return qed_parse_mcp_trace_dump(p_hwfn, 7306da090917STomer Tayar dump_buf, NULL, results_buf_size); 73077b6859fbSMintz, Yuval } 73087b6859fbSMintz, Yuval 73097b6859fbSMintz, Yuval enum dbg_status qed_print_mcp_trace_results(struct qed_hwfn *p_hwfn, 73107b6859fbSMintz, Yuval u32 *dump_buf, 73117b6859fbSMintz, Yuval u32 num_dumped_dwords, 73127b6859fbSMintz, Yuval char *results_buf) 73137b6859fbSMintz, Yuval { 73147b6859fbSMintz, Yuval u32 parsed_buf_size; 73157b6859fbSMintz, Yuval 73167b6859fbSMintz, Yuval return qed_parse_mcp_trace_dump(p_hwfn, 73177b6859fbSMintz, Yuval dump_buf, 73187b6859fbSMintz, Yuval results_buf, &parsed_buf_size); 73197b6859fbSMintz, Yuval } 73207b6859fbSMintz, Yuval 73217b6859fbSMintz, Yuval enum dbg_status qed_get_reg_fifo_results_buf_size(struct qed_hwfn *p_hwfn, 73227b6859fbSMintz, Yuval u32 *dump_buf, 73237b6859fbSMintz, Yuval u32 num_dumped_dwords, 73247b6859fbSMintz, Yuval u32 *results_buf_size) 73257b6859fbSMintz, Yuval { 7326da090917STomer Tayar return qed_parse_reg_fifo_dump(dump_buf, NULL, results_buf_size); 73277b6859fbSMintz, Yuval } 73287b6859fbSMintz, Yuval 73297b6859fbSMintz, Yuval enum dbg_status qed_print_reg_fifo_results(struct qed_hwfn *p_hwfn, 73307b6859fbSMintz, Yuval u32 *dump_buf, 73317b6859fbSMintz, Yuval u32 num_dumped_dwords, 73327b6859fbSMintz, Yuval char *results_buf) 73337b6859fbSMintz, Yuval { 73347b6859fbSMintz, Yuval u32 parsed_buf_size; 73357b6859fbSMintz, Yuval 7336da090917STomer Tayar return qed_parse_reg_fifo_dump(dump_buf, results_buf, &parsed_buf_size); 73377b6859fbSMintz, Yuval } 73387b6859fbSMintz, Yuval 73397b6859fbSMintz, Yuval enum dbg_status qed_get_igu_fifo_results_buf_size(struct qed_hwfn *p_hwfn, 73407b6859fbSMintz, Yuval u32 *dump_buf, 73417b6859fbSMintz, Yuval u32 num_dumped_dwords, 73427b6859fbSMintz, Yuval u32 *results_buf_size) 73437b6859fbSMintz, Yuval { 7344da090917STomer Tayar return qed_parse_igu_fifo_dump(dump_buf, NULL, results_buf_size); 73457b6859fbSMintz, Yuval } 73467b6859fbSMintz, Yuval 73477b6859fbSMintz, Yuval enum dbg_status qed_print_igu_fifo_results(struct qed_hwfn *p_hwfn, 73487b6859fbSMintz, Yuval u32 *dump_buf, 73497b6859fbSMintz, Yuval u32 num_dumped_dwords, 73507b6859fbSMintz, Yuval char *results_buf) 73517b6859fbSMintz, Yuval { 73527b6859fbSMintz, Yuval u32 parsed_buf_size; 73537b6859fbSMintz, Yuval 7354da090917STomer Tayar return qed_parse_igu_fifo_dump(dump_buf, results_buf, &parsed_buf_size); 73557b6859fbSMintz, Yuval } 73567b6859fbSMintz, Yuval 7357c965db44STomer Tayar enum dbg_status 7358c965db44STomer Tayar qed_get_protection_override_results_buf_size(struct qed_hwfn *p_hwfn, 7359c965db44STomer Tayar u32 *dump_buf, 7360c965db44STomer Tayar u32 num_dumped_dwords, 7361c965db44STomer Tayar u32 *results_buf_size) 7362c965db44STomer Tayar { 7363da090917STomer Tayar return qed_parse_protection_override_dump(dump_buf, 7364c965db44STomer Tayar NULL, results_buf_size); 7365c965db44STomer Tayar } 7366c965db44STomer Tayar 7367c965db44STomer Tayar enum dbg_status qed_print_protection_override_results(struct qed_hwfn *p_hwfn, 7368c965db44STomer Tayar u32 *dump_buf, 7369c965db44STomer Tayar u32 num_dumped_dwords, 7370c965db44STomer Tayar char *results_buf) 7371c965db44STomer Tayar { 7372c965db44STomer Tayar u32 parsed_buf_size; 7373c965db44STomer Tayar 7374da090917STomer Tayar return qed_parse_protection_override_dump(dump_buf, 7375c965db44STomer Tayar results_buf, 7376c965db44STomer Tayar &parsed_buf_size); 7377c965db44STomer Tayar } 7378c965db44STomer Tayar 7379c965db44STomer Tayar enum dbg_status qed_get_fw_asserts_results_buf_size(struct qed_hwfn *p_hwfn, 7380c965db44STomer Tayar u32 *dump_buf, 7381c965db44STomer Tayar u32 num_dumped_dwords, 7382c965db44STomer Tayar u32 *results_buf_size) 7383c965db44STomer Tayar { 7384da090917STomer Tayar return qed_parse_fw_asserts_dump(dump_buf, NULL, results_buf_size); 7385c965db44STomer Tayar } 7386c965db44STomer Tayar 7387c965db44STomer Tayar enum dbg_status qed_print_fw_asserts_results(struct qed_hwfn *p_hwfn, 7388c965db44STomer Tayar u32 *dump_buf, 7389c965db44STomer Tayar u32 num_dumped_dwords, 7390c965db44STomer Tayar char *results_buf) 7391c965db44STomer Tayar { 7392c965db44STomer Tayar u32 parsed_buf_size; 7393c965db44STomer Tayar 7394da090917STomer Tayar return qed_parse_fw_asserts_dump(dump_buf, 7395c965db44STomer Tayar results_buf, &parsed_buf_size); 7396c965db44STomer Tayar } 7397c965db44STomer Tayar 73980ebbd1c8SMintz, Yuval enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn, 73990ebbd1c8SMintz, Yuval struct dbg_attn_block_result *results) 74000ebbd1c8SMintz, Yuval { 74010ebbd1c8SMintz, Yuval struct user_dbg_array *block_attn, *pstrings; 74020ebbd1c8SMintz, Yuval const u32 *block_attn_name_offsets; 74030ebbd1c8SMintz, Yuval enum dbg_attn_type attn_type; 74040ebbd1c8SMintz, Yuval const char *block_name; 74050ebbd1c8SMintz, Yuval u8 num_regs, i, j; 74060ebbd1c8SMintz, Yuval 74070ebbd1c8SMintz, Yuval num_regs = GET_FIELD(results->data, DBG_ATTN_BLOCK_RESULT_NUM_REGS); 74080ebbd1c8SMintz, Yuval attn_type = (enum dbg_attn_type) 74090ebbd1c8SMintz, Yuval GET_FIELD(results->data, 74100ebbd1c8SMintz, Yuval DBG_ATTN_BLOCK_RESULT_ATTN_TYPE); 74110ebbd1c8SMintz, Yuval block_name = s_block_info_arr[results->block_id].name; 74120ebbd1c8SMintz, Yuval 74130ebbd1c8SMintz, Yuval if (!s_user_dbg_arrays[BIN_BUF_DBG_ATTN_INDEXES].ptr || 74140ebbd1c8SMintz, Yuval !s_user_dbg_arrays[BIN_BUF_DBG_ATTN_NAME_OFFSETS].ptr || 74150ebbd1c8SMintz, Yuval !s_user_dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS].ptr) 74160ebbd1c8SMintz, Yuval return DBG_STATUS_DBG_ARRAY_NOT_SET; 74170ebbd1c8SMintz, Yuval 74180ebbd1c8SMintz, Yuval block_attn = &s_user_dbg_arrays[BIN_BUF_DBG_ATTN_NAME_OFFSETS]; 74190ebbd1c8SMintz, Yuval block_attn_name_offsets = &block_attn->ptr[results->names_offset]; 74200ebbd1c8SMintz, Yuval 74210ebbd1c8SMintz, Yuval /* Go over registers with a non-zero attention status */ 74220ebbd1c8SMintz, Yuval for (i = 0; i < num_regs; i++) { 7423da090917STomer Tayar struct dbg_attn_bit_mapping *bit_mapping; 74240ebbd1c8SMintz, Yuval struct dbg_attn_reg_result *reg_result; 74250ebbd1c8SMintz, Yuval u8 num_reg_attn, bit_idx = 0; 74260ebbd1c8SMintz, Yuval 74270ebbd1c8SMintz, Yuval reg_result = &results->reg_results[i]; 74280ebbd1c8SMintz, Yuval num_reg_attn = GET_FIELD(reg_result->data, 74290ebbd1c8SMintz, Yuval DBG_ATTN_REG_RESULT_NUM_REG_ATTN); 74300ebbd1c8SMintz, Yuval block_attn = &s_user_dbg_arrays[BIN_BUF_DBG_ATTN_INDEXES]; 7431da090917STomer Tayar bit_mapping = &((struct dbg_attn_bit_mapping *) 74320ebbd1c8SMintz, Yuval block_attn->ptr)[reg_result->block_attn_offset]; 74330ebbd1c8SMintz, Yuval 74340ebbd1c8SMintz, Yuval pstrings = &s_user_dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS]; 74350ebbd1c8SMintz, Yuval 74360ebbd1c8SMintz, Yuval /* Go over attention status bits */ 74370ebbd1c8SMintz, Yuval for (j = 0; j < num_reg_attn; j++) { 7438da090917STomer Tayar u16 attn_idx_val = GET_FIELD(bit_mapping[j].data, 74390ebbd1c8SMintz, Yuval DBG_ATTN_BIT_MAPPING_VAL); 74400ebbd1c8SMintz, Yuval const char *attn_name, *attn_type_str, *masked_str; 7441da090917STomer Tayar u32 attn_name_offset, sts_addr; 74420ebbd1c8SMintz, Yuval 74430ebbd1c8SMintz, Yuval /* Check if bit mask should be advanced (due to unused 74440ebbd1c8SMintz, Yuval * bits). 74450ebbd1c8SMintz, Yuval */ 7446da090917STomer Tayar if (GET_FIELD(bit_mapping[j].data, 74470ebbd1c8SMintz, Yuval DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT)) { 74480ebbd1c8SMintz, Yuval bit_idx += (u8)attn_idx_val; 74490ebbd1c8SMintz, Yuval continue; 74500ebbd1c8SMintz, Yuval } 74510ebbd1c8SMintz, Yuval 74520ebbd1c8SMintz, Yuval /* Check current bit index */ 74530ebbd1c8SMintz, Yuval if (!(reg_result->sts_val & BIT(bit_idx))) { 74540ebbd1c8SMintz, Yuval bit_idx++; 74550ebbd1c8SMintz, Yuval continue; 74560ebbd1c8SMintz, Yuval } 74570ebbd1c8SMintz, Yuval 74580ebbd1c8SMintz, Yuval /* Find attention name */ 7459da090917STomer Tayar attn_name_offset = 7460da090917STomer Tayar block_attn_name_offsets[attn_idx_val]; 74610ebbd1c8SMintz, Yuval attn_name = &((const char *) 7462da090917STomer Tayar pstrings->ptr)[attn_name_offset]; 74630ebbd1c8SMintz, Yuval attn_type_str = attn_type == ATTN_TYPE_INTERRUPT ? 74640ebbd1c8SMintz, Yuval "Interrupt" : "Parity"; 74650ebbd1c8SMintz, Yuval masked_str = reg_result->mask_val & BIT(bit_idx) ? 74660ebbd1c8SMintz, Yuval " [masked]" : ""; 74670ebbd1c8SMintz, Yuval sts_addr = GET_FIELD(reg_result->data, 74680ebbd1c8SMintz, Yuval DBG_ATTN_REG_RESULT_STS_ADDRESS); 74690ebbd1c8SMintz, Yuval DP_NOTICE(p_hwfn, 74700ebbd1c8SMintz, Yuval "%s (%s) : %s [address 0x%08x, bit %d]%s\n", 74710ebbd1c8SMintz, Yuval block_name, attn_type_str, attn_name, 74720ebbd1c8SMintz, Yuval sts_addr, bit_idx, masked_str); 74730ebbd1c8SMintz, Yuval 74740ebbd1c8SMintz, Yuval bit_idx++; 74750ebbd1c8SMintz, Yuval } 74760ebbd1c8SMintz, Yuval } 74770ebbd1c8SMintz, Yuval 74780ebbd1c8SMintz, Yuval return DBG_STATUS_OK; 74790ebbd1c8SMintz, Yuval } 74800ebbd1c8SMintz, Yuval 7481c965db44STomer Tayar /* Wrapper for unifying the idle_chk and mcp_trace api */ 74828c93beafSYuval Mintz static enum dbg_status 74838c93beafSYuval Mintz qed_print_idle_chk_results_wrapper(struct qed_hwfn *p_hwfn, 7484c965db44STomer Tayar u32 *dump_buf, 7485c965db44STomer Tayar u32 num_dumped_dwords, 7486c965db44STomer Tayar char *results_buf) 7487c965db44STomer Tayar { 7488c965db44STomer Tayar u32 num_errors, num_warnnings; 7489c965db44STomer Tayar 7490c965db44STomer Tayar return qed_print_idle_chk_results(p_hwfn, dump_buf, num_dumped_dwords, 7491c965db44STomer Tayar results_buf, &num_errors, 7492c965db44STomer Tayar &num_warnnings); 7493c965db44STomer Tayar } 7494c965db44STomer Tayar 7495c965db44STomer Tayar /* Feature meta data lookup table */ 7496c965db44STomer Tayar static struct { 7497c965db44STomer Tayar char *name; 7498c965db44STomer Tayar enum dbg_status (*get_size)(struct qed_hwfn *p_hwfn, 7499c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *size); 7500c965db44STomer Tayar enum dbg_status (*perform_dump)(struct qed_hwfn *p_hwfn, 7501c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *dump_buf, 7502c965db44STomer Tayar u32 buf_size, u32 *dumped_dwords); 7503c965db44STomer Tayar enum dbg_status (*print_results)(struct qed_hwfn *p_hwfn, 7504c965db44STomer Tayar u32 *dump_buf, u32 num_dumped_dwords, 7505c965db44STomer Tayar char *results_buf); 7506c965db44STomer Tayar enum dbg_status (*results_buf_size)(struct qed_hwfn *p_hwfn, 7507c965db44STomer Tayar u32 *dump_buf, 7508c965db44STomer Tayar u32 num_dumped_dwords, 7509c965db44STomer Tayar u32 *results_buf_size); 7510c965db44STomer Tayar } qed_features_lookup[] = { 7511c965db44STomer Tayar { 7512c965db44STomer Tayar "grc", qed_dbg_grc_get_dump_buf_size, 7513c965db44STomer Tayar qed_dbg_grc_dump, NULL, NULL}, { 7514c965db44STomer Tayar "idle_chk", 7515c965db44STomer Tayar qed_dbg_idle_chk_get_dump_buf_size, 7516c965db44STomer Tayar qed_dbg_idle_chk_dump, 7517c965db44STomer Tayar qed_print_idle_chk_results_wrapper, 7518c965db44STomer Tayar qed_get_idle_chk_results_buf_size}, { 7519c965db44STomer Tayar "mcp_trace", 7520c965db44STomer Tayar qed_dbg_mcp_trace_get_dump_buf_size, 7521c965db44STomer Tayar qed_dbg_mcp_trace_dump, qed_print_mcp_trace_results, 7522c965db44STomer Tayar qed_get_mcp_trace_results_buf_size}, { 7523c965db44STomer Tayar "reg_fifo", 7524c965db44STomer Tayar qed_dbg_reg_fifo_get_dump_buf_size, 7525c965db44STomer Tayar qed_dbg_reg_fifo_dump, qed_print_reg_fifo_results, 7526c965db44STomer Tayar qed_get_reg_fifo_results_buf_size}, { 7527c965db44STomer Tayar "igu_fifo", 7528c965db44STomer Tayar qed_dbg_igu_fifo_get_dump_buf_size, 7529c965db44STomer Tayar qed_dbg_igu_fifo_dump, qed_print_igu_fifo_results, 7530c965db44STomer Tayar qed_get_igu_fifo_results_buf_size}, { 7531c965db44STomer Tayar "protection_override", 7532c965db44STomer Tayar qed_dbg_protection_override_get_dump_buf_size, 7533c965db44STomer Tayar qed_dbg_protection_override_dump, 7534c965db44STomer Tayar qed_print_protection_override_results, 7535c965db44STomer Tayar qed_get_protection_override_results_buf_size}, { 7536c965db44STomer Tayar "fw_asserts", 7537c965db44STomer Tayar qed_dbg_fw_asserts_get_dump_buf_size, 7538c965db44STomer Tayar qed_dbg_fw_asserts_dump, 7539c965db44STomer Tayar qed_print_fw_asserts_results, 7540c965db44STomer Tayar qed_get_fw_asserts_results_buf_size},}; 7541c965db44STomer Tayar 7542c965db44STomer Tayar static void qed_dbg_print_feature(u8 *p_text_buf, u32 text_size) 7543c965db44STomer Tayar { 7544c965db44STomer Tayar u32 i, precision = 80; 7545c965db44STomer Tayar 7546c965db44STomer Tayar if (!p_text_buf) 7547c965db44STomer Tayar return; 7548c965db44STomer Tayar 7549c965db44STomer Tayar pr_notice("\n%.*s", precision, p_text_buf); 7550c965db44STomer Tayar for (i = precision; i < text_size; i += precision) 7551c965db44STomer Tayar pr_cont("%.*s", precision, p_text_buf + i); 7552c965db44STomer Tayar pr_cont("\n"); 7553c965db44STomer Tayar } 7554c965db44STomer Tayar 7555c965db44STomer Tayar #define QED_RESULTS_BUF_MIN_SIZE 16 7556c965db44STomer Tayar /* Generic function for decoding debug feature info */ 75578c93beafSYuval Mintz static enum dbg_status format_feature(struct qed_hwfn *p_hwfn, 7558c965db44STomer Tayar enum qed_dbg_features feature_idx) 7559c965db44STomer Tayar { 7560c965db44STomer Tayar struct qed_dbg_feature *feature = 7561c965db44STomer Tayar &p_hwfn->cdev->dbg_params.features[feature_idx]; 7562c965db44STomer Tayar u32 text_size_bytes, null_char_pos, i; 7563c965db44STomer Tayar enum dbg_status rc; 7564c965db44STomer Tayar char *text_buf; 7565c965db44STomer Tayar 7566c965db44STomer Tayar /* Check if feature supports formatting capability */ 7567c965db44STomer Tayar if (!qed_features_lookup[feature_idx].results_buf_size) 7568c965db44STomer Tayar return DBG_STATUS_OK; 7569c965db44STomer Tayar 7570c965db44STomer Tayar /* Obtain size of formatted output */ 7571c965db44STomer Tayar rc = qed_features_lookup[feature_idx]. 7572c965db44STomer Tayar results_buf_size(p_hwfn, (u32 *)feature->dump_buf, 7573c965db44STomer Tayar feature->dumped_dwords, &text_size_bytes); 7574c965db44STomer Tayar if (rc != DBG_STATUS_OK) 7575c965db44STomer Tayar return rc; 7576c965db44STomer Tayar 7577c965db44STomer Tayar /* Make sure that the allocated size is a multiple of dword (4 bytes) */ 7578c965db44STomer Tayar null_char_pos = text_size_bytes - 1; 7579c965db44STomer Tayar text_size_bytes = (text_size_bytes + 3) & ~0x3; 7580c965db44STomer Tayar 7581c965db44STomer Tayar if (text_size_bytes < QED_RESULTS_BUF_MIN_SIZE) { 7582c965db44STomer Tayar DP_NOTICE(p_hwfn->cdev, 7583c965db44STomer Tayar "formatted size of feature was too small %d. Aborting\n", 7584c965db44STomer Tayar text_size_bytes); 7585c965db44STomer Tayar return DBG_STATUS_INVALID_ARGS; 7586c965db44STomer Tayar } 7587c965db44STomer Tayar 7588c965db44STomer Tayar /* Allocate temp text buf */ 7589c965db44STomer Tayar text_buf = vzalloc(text_size_bytes); 7590c965db44STomer Tayar if (!text_buf) 7591c965db44STomer Tayar return DBG_STATUS_VIRT_MEM_ALLOC_FAILED; 7592c965db44STomer Tayar 7593c965db44STomer Tayar /* Decode feature opcodes to string on temp buf */ 7594c965db44STomer Tayar rc = qed_features_lookup[feature_idx]. 7595c965db44STomer Tayar print_results(p_hwfn, (u32 *)feature->dump_buf, 7596c965db44STomer Tayar feature->dumped_dwords, text_buf); 7597c965db44STomer Tayar if (rc != DBG_STATUS_OK) { 7598c965db44STomer Tayar vfree(text_buf); 7599c965db44STomer Tayar return rc; 7600c965db44STomer Tayar } 7601c965db44STomer Tayar 7602c965db44STomer Tayar /* Replace the original null character with a '\n' character. 7603c965db44STomer Tayar * The bytes that were added as a result of the dword alignment are also 7604c965db44STomer Tayar * padded with '\n' characters. 7605c965db44STomer Tayar */ 7606c965db44STomer Tayar for (i = null_char_pos; i < text_size_bytes; i++) 7607c965db44STomer Tayar text_buf[i] = '\n'; 7608c965db44STomer Tayar 7609c965db44STomer Tayar /* Dump printable feature to log */ 7610c965db44STomer Tayar if (p_hwfn->cdev->dbg_params.print_data) 7611c965db44STomer Tayar qed_dbg_print_feature(text_buf, text_size_bytes); 7612c965db44STomer Tayar 7613c965db44STomer Tayar /* Free the old dump_buf and point the dump_buf to the newly allocagted 7614c965db44STomer Tayar * and formatted text buffer. 7615c965db44STomer Tayar */ 7616c965db44STomer Tayar vfree(feature->dump_buf); 7617c965db44STomer Tayar feature->dump_buf = text_buf; 7618c965db44STomer Tayar feature->buf_size = text_size_bytes; 7619c965db44STomer Tayar feature->dumped_dwords = text_size_bytes / 4; 7620c965db44STomer Tayar return rc; 7621c965db44STomer Tayar } 7622c965db44STomer Tayar 7623c965db44STomer Tayar /* Generic function for performing the dump of a debug feature. */ 76248c93beafSYuval Mintz static enum dbg_status qed_dbg_dump(struct qed_hwfn *p_hwfn, 76258c93beafSYuval Mintz struct qed_ptt *p_ptt, 7626c965db44STomer Tayar enum qed_dbg_features feature_idx) 7627c965db44STomer Tayar { 7628c965db44STomer Tayar struct qed_dbg_feature *feature = 7629c965db44STomer Tayar &p_hwfn->cdev->dbg_params.features[feature_idx]; 7630c965db44STomer Tayar u32 buf_size_dwords; 7631c965db44STomer Tayar enum dbg_status rc; 7632c965db44STomer Tayar 7633c965db44STomer Tayar DP_NOTICE(p_hwfn->cdev, "Collecting a debug feature [\"%s\"]\n", 7634c965db44STomer Tayar qed_features_lookup[feature_idx].name); 7635c965db44STomer Tayar 7636c965db44STomer Tayar /* Dump_buf was already allocated need to free (this can happen if dump 7637c965db44STomer Tayar * was called but file was never read). 7638c965db44STomer Tayar * We can't use the buffer as is since size may have changed. 7639c965db44STomer Tayar */ 7640c965db44STomer Tayar if (feature->dump_buf) { 7641c965db44STomer Tayar vfree(feature->dump_buf); 7642c965db44STomer Tayar feature->dump_buf = NULL; 7643c965db44STomer Tayar } 7644c965db44STomer Tayar 7645c965db44STomer Tayar /* Get buffer size from hsi, allocate accordingly, and perform the 7646c965db44STomer Tayar * dump. 7647c965db44STomer Tayar */ 7648c965db44STomer Tayar rc = qed_features_lookup[feature_idx].get_size(p_hwfn, p_ptt, 7649c965db44STomer Tayar &buf_size_dwords); 7650be086e7cSMintz, Yuval if (rc != DBG_STATUS_OK && rc != DBG_STATUS_NVRAM_GET_IMAGE_FAILED) 7651c965db44STomer Tayar return rc; 7652c965db44STomer Tayar feature->buf_size = buf_size_dwords * sizeof(u32); 7653c965db44STomer Tayar feature->dump_buf = vmalloc(feature->buf_size); 7654c965db44STomer Tayar if (!feature->dump_buf) 7655c965db44STomer Tayar return DBG_STATUS_VIRT_MEM_ALLOC_FAILED; 7656c965db44STomer Tayar 7657c965db44STomer Tayar rc = qed_features_lookup[feature_idx]. 7658c965db44STomer Tayar perform_dump(p_hwfn, p_ptt, (u32 *)feature->dump_buf, 7659c965db44STomer Tayar feature->buf_size / sizeof(u32), 7660c965db44STomer Tayar &feature->dumped_dwords); 7661c965db44STomer Tayar 7662c965db44STomer Tayar /* If mcp is stuck we get DBG_STATUS_NVRAM_GET_IMAGE_FAILED error. 7663c965db44STomer Tayar * In this case the buffer holds valid binary data, but we wont able 7664c965db44STomer Tayar * to parse it (since parsing relies on data in NVRAM which is only 7665c965db44STomer Tayar * accessible when MFW is responsive). skip the formatting but return 7666c965db44STomer Tayar * success so that binary data is provided. 7667c965db44STomer Tayar */ 7668c965db44STomer Tayar if (rc == DBG_STATUS_NVRAM_GET_IMAGE_FAILED) 7669c965db44STomer Tayar return DBG_STATUS_OK; 7670c965db44STomer Tayar 7671c965db44STomer Tayar if (rc != DBG_STATUS_OK) 7672c965db44STomer Tayar return rc; 7673c965db44STomer Tayar 7674c965db44STomer Tayar /* Format output */ 7675c965db44STomer Tayar rc = format_feature(p_hwfn, feature_idx); 7676c965db44STomer Tayar return rc; 7677c965db44STomer Tayar } 7678c965db44STomer Tayar 7679c965db44STomer Tayar int qed_dbg_grc(struct qed_dev *cdev, void *buffer, u32 *num_dumped_bytes) 7680c965db44STomer Tayar { 7681c965db44STomer Tayar return qed_dbg_feature(cdev, buffer, DBG_FEATURE_GRC, num_dumped_bytes); 7682c965db44STomer Tayar } 7683c965db44STomer Tayar 7684c965db44STomer Tayar int qed_dbg_grc_size(struct qed_dev *cdev) 7685c965db44STomer Tayar { 7686c965db44STomer Tayar return qed_dbg_feature_size(cdev, DBG_FEATURE_GRC); 7687c965db44STomer Tayar } 7688c965db44STomer Tayar 7689c965db44STomer Tayar int qed_dbg_idle_chk(struct qed_dev *cdev, void *buffer, u32 *num_dumped_bytes) 7690c965db44STomer Tayar { 7691c965db44STomer Tayar return qed_dbg_feature(cdev, buffer, DBG_FEATURE_IDLE_CHK, 7692c965db44STomer Tayar num_dumped_bytes); 7693c965db44STomer Tayar } 7694c965db44STomer Tayar 7695c965db44STomer Tayar int qed_dbg_idle_chk_size(struct qed_dev *cdev) 7696c965db44STomer Tayar { 7697c965db44STomer Tayar return qed_dbg_feature_size(cdev, DBG_FEATURE_IDLE_CHK); 7698c965db44STomer Tayar } 7699c965db44STomer Tayar 7700c965db44STomer Tayar int qed_dbg_reg_fifo(struct qed_dev *cdev, void *buffer, u32 *num_dumped_bytes) 7701c965db44STomer Tayar { 7702c965db44STomer Tayar return qed_dbg_feature(cdev, buffer, DBG_FEATURE_REG_FIFO, 7703c965db44STomer Tayar num_dumped_bytes); 7704c965db44STomer Tayar } 7705c965db44STomer Tayar 7706c965db44STomer Tayar int qed_dbg_reg_fifo_size(struct qed_dev *cdev) 7707c965db44STomer Tayar { 7708c965db44STomer Tayar return qed_dbg_feature_size(cdev, DBG_FEATURE_REG_FIFO); 7709c965db44STomer Tayar } 7710c965db44STomer Tayar 7711c965db44STomer Tayar int qed_dbg_igu_fifo(struct qed_dev *cdev, void *buffer, u32 *num_dumped_bytes) 7712c965db44STomer Tayar { 7713c965db44STomer Tayar return qed_dbg_feature(cdev, buffer, DBG_FEATURE_IGU_FIFO, 7714c965db44STomer Tayar num_dumped_bytes); 7715c965db44STomer Tayar } 7716c965db44STomer Tayar 7717c965db44STomer Tayar int qed_dbg_igu_fifo_size(struct qed_dev *cdev) 7718c965db44STomer Tayar { 7719c965db44STomer Tayar return qed_dbg_feature_size(cdev, DBG_FEATURE_IGU_FIFO); 7720c965db44STomer Tayar } 7721c965db44STomer Tayar 7722c965db44STomer Tayar int qed_dbg_protection_override(struct qed_dev *cdev, void *buffer, 7723c965db44STomer Tayar u32 *num_dumped_bytes) 7724c965db44STomer Tayar { 7725c965db44STomer Tayar return qed_dbg_feature(cdev, buffer, DBG_FEATURE_PROTECTION_OVERRIDE, 7726c965db44STomer Tayar num_dumped_bytes); 7727c965db44STomer Tayar } 7728c965db44STomer Tayar 7729c965db44STomer Tayar int qed_dbg_protection_override_size(struct qed_dev *cdev) 7730c965db44STomer Tayar { 7731c965db44STomer Tayar return qed_dbg_feature_size(cdev, DBG_FEATURE_PROTECTION_OVERRIDE); 7732c965db44STomer Tayar } 7733c965db44STomer Tayar 7734c965db44STomer Tayar int qed_dbg_fw_asserts(struct qed_dev *cdev, void *buffer, 7735c965db44STomer Tayar u32 *num_dumped_bytes) 7736c965db44STomer Tayar { 7737c965db44STomer Tayar return qed_dbg_feature(cdev, buffer, DBG_FEATURE_FW_ASSERTS, 7738c965db44STomer Tayar num_dumped_bytes); 7739c965db44STomer Tayar } 7740c965db44STomer Tayar 7741c965db44STomer Tayar int qed_dbg_fw_asserts_size(struct qed_dev *cdev) 7742c965db44STomer Tayar { 7743c965db44STomer Tayar return qed_dbg_feature_size(cdev, DBG_FEATURE_FW_ASSERTS); 7744c965db44STomer Tayar } 7745c965db44STomer Tayar 7746c965db44STomer Tayar int qed_dbg_mcp_trace(struct qed_dev *cdev, void *buffer, 7747c965db44STomer Tayar u32 *num_dumped_bytes) 7748c965db44STomer Tayar { 7749c965db44STomer Tayar return qed_dbg_feature(cdev, buffer, DBG_FEATURE_MCP_TRACE, 7750c965db44STomer Tayar num_dumped_bytes); 7751c965db44STomer Tayar } 7752c965db44STomer Tayar 7753c965db44STomer Tayar int qed_dbg_mcp_trace_size(struct qed_dev *cdev) 7754c965db44STomer Tayar { 7755c965db44STomer Tayar return qed_dbg_feature_size(cdev, DBG_FEATURE_MCP_TRACE); 7756c965db44STomer Tayar } 7757c965db44STomer Tayar 7758c965db44STomer Tayar /* Defines the amount of bytes allocated for recording the length of debugfs 7759c965db44STomer Tayar * feature buffer. 7760c965db44STomer Tayar */ 7761c965db44STomer Tayar #define REGDUMP_HEADER_SIZE sizeof(u32) 7762c965db44STomer Tayar #define REGDUMP_HEADER_FEATURE_SHIFT 24 7763c965db44STomer Tayar #define REGDUMP_HEADER_ENGINE_SHIFT 31 7764c965db44STomer Tayar #define REGDUMP_HEADER_OMIT_ENGINE_SHIFT 30 7765c965db44STomer Tayar enum debug_print_features { 7766c965db44STomer Tayar OLD_MODE = 0, 7767c965db44STomer Tayar IDLE_CHK = 1, 7768c965db44STomer Tayar GRC_DUMP = 2, 7769c965db44STomer Tayar MCP_TRACE = 3, 7770c965db44STomer Tayar REG_FIFO = 4, 7771c965db44STomer Tayar PROTECTION_OVERRIDE = 5, 7772c965db44STomer Tayar IGU_FIFO = 6, 7773c965db44STomer Tayar PHY = 7, 7774c965db44STomer Tayar FW_ASSERTS = 8, 7775c965db44STomer Tayar }; 7776c965db44STomer Tayar 7777c965db44STomer Tayar static u32 qed_calc_regdump_header(enum debug_print_features feature, 7778c965db44STomer Tayar int engine, u32 feature_size, u8 omit_engine) 7779c965db44STomer Tayar { 7780c965db44STomer Tayar /* Insert the engine, feature and mode inside the header and combine it 7781c965db44STomer Tayar * with feature size. 7782c965db44STomer Tayar */ 7783c965db44STomer Tayar return feature_size | (feature << REGDUMP_HEADER_FEATURE_SHIFT) | 7784c965db44STomer Tayar (omit_engine << REGDUMP_HEADER_OMIT_ENGINE_SHIFT) | 7785c965db44STomer Tayar (engine << REGDUMP_HEADER_ENGINE_SHIFT); 7786c965db44STomer Tayar } 7787c965db44STomer Tayar 7788c965db44STomer Tayar int qed_dbg_all_data(struct qed_dev *cdev, void *buffer) 7789c965db44STomer Tayar { 7790c965db44STomer Tayar u8 cur_engine, omit_engine = 0, org_engine; 7791c965db44STomer Tayar u32 offset = 0, feature_size; 7792c965db44STomer Tayar int rc; 7793c965db44STomer Tayar 7794c965db44STomer Tayar if (cdev->num_hwfns == 1) 7795c965db44STomer Tayar omit_engine = 1; 7796c965db44STomer Tayar 7797c965db44STomer Tayar org_engine = qed_get_debug_engine(cdev); 7798c965db44STomer Tayar for (cur_engine = 0; cur_engine < cdev->num_hwfns; cur_engine++) { 7799c965db44STomer Tayar /* Collect idle_chks and grcDump for each hw function */ 7800c965db44STomer Tayar DP_VERBOSE(cdev, QED_MSG_DEBUG, 7801c965db44STomer Tayar "obtaining idle_chk and grcdump for current engine\n"); 7802c965db44STomer Tayar qed_set_debug_engine(cdev, cur_engine); 7803c965db44STomer Tayar 7804c965db44STomer Tayar /* First idle_chk */ 7805c965db44STomer Tayar rc = qed_dbg_idle_chk(cdev, (u8 *)buffer + offset + 7806c965db44STomer Tayar REGDUMP_HEADER_SIZE, &feature_size); 7807c965db44STomer Tayar if (!rc) { 7808c965db44STomer Tayar *(u32 *)((u8 *)buffer + offset) = 7809c965db44STomer Tayar qed_calc_regdump_header(IDLE_CHK, cur_engine, 7810c965db44STomer Tayar feature_size, omit_engine); 7811c965db44STomer Tayar offset += (feature_size + REGDUMP_HEADER_SIZE); 7812c965db44STomer Tayar } else { 7813c965db44STomer Tayar DP_ERR(cdev, "qed_dbg_idle_chk failed. rc = %d\n", rc); 7814c965db44STomer Tayar } 7815c965db44STomer Tayar 7816c965db44STomer Tayar /* Second idle_chk */ 7817c965db44STomer Tayar rc = qed_dbg_idle_chk(cdev, (u8 *)buffer + offset + 7818c965db44STomer Tayar REGDUMP_HEADER_SIZE, &feature_size); 7819c965db44STomer Tayar if (!rc) { 7820c965db44STomer Tayar *(u32 *)((u8 *)buffer + offset) = 7821c965db44STomer Tayar qed_calc_regdump_header(IDLE_CHK, cur_engine, 7822c965db44STomer Tayar feature_size, omit_engine); 7823c965db44STomer Tayar offset += (feature_size + REGDUMP_HEADER_SIZE); 7824c965db44STomer Tayar } else { 7825c965db44STomer Tayar DP_ERR(cdev, "qed_dbg_idle_chk failed. rc = %d\n", rc); 7826c965db44STomer Tayar } 7827c965db44STomer Tayar 7828c965db44STomer Tayar /* reg_fifo dump */ 7829c965db44STomer Tayar rc = qed_dbg_reg_fifo(cdev, (u8 *)buffer + offset + 7830c965db44STomer Tayar REGDUMP_HEADER_SIZE, &feature_size); 7831c965db44STomer Tayar if (!rc) { 7832c965db44STomer Tayar *(u32 *)((u8 *)buffer + offset) = 7833c965db44STomer Tayar qed_calc_regdump_header(REG_FIFO, cur_engine, 7834c965db44STomer Tayar feature_size, omit_engine); 7835c965db44STomer Tayar offset += (feature_size + REGDUMP_HEADER_SIZE); 7836c965db44STomer Tayar } else { 7837c965db44STomer Tayar DP_ERR(cdev, "qed_dbg_reg_fifo failed. rc = %d\n", rc); 7838c965db44STomer Tayar } 7839c965db44STomer Tayar 7840c965db44STomer Tayar /* igu_fifo dump */ 7841c965db44STomer Tayar rc = qed_dbg_igu_fifo(cdev, (u8 *)buffer + offset + 7842c965db44STomer Tayar REGDUMP_HEADER_SIZE, &feature_size); 7843c965db44STomer Tayar if (!rc) { 7844c965db44STomer Tayar *(u32 *)((u8 *)buffer + offset) = 7845c965db44STomer Tayar qed_calc_regdump_header(IGU_FIFO, cur_engine, 7846c965db44STomer Tayar feature_size, omit_engine); 7847c965db44STomer Tayar offset += (feature_size + REGDUMP_HEADER_SIZE); 7848c965db44STomer Tayar } else { 7849c965db44STomer Tayar DP_ERR(cdev, "qed_dbg_igu_fifo failed. rc = %d", rc); 7850c965db44STomer Tayar } 7851c965db44STomer Tayar 7852c965db44STomer Tayar /* protection_override dump */ 7853c965db44STomer Tayar rc = qed_dbg_protection_override(cdev, (u8 *)buffer + offset + 7854c965db44STomer Tayar REGDUMP_HEADER_SIZE, 7855c965db44STomer Tayar &feature_size); 7856c965db44STomer Tayar if (!rc) { 7857c965db44STomer Tayar *(u32 *)((u8 *)buffer + offset) = 7858c965db44STomer Tayar qed_calc_regdump_header(PROTECTION_OVERRIDE, 7859c965db44STomer Tayar cur_engine, 7860c965db44STomer Tayar feature_size, omit_engine); 7861c965db44STomer Tayar offset += (feature_size + REGDUMP_HEADER_SIZE); 7862c965db44STomer Tayar } else { 7863c965db44STomer Tayar DP_ERR(cdev, 7864c965db44STomer Tayar "qed_dbg_protection_override failed. rc = %d\n", 7865c965db44STomer Tayar rc); 7866c965db44STomer Tayar } 7867c965db44STomer Tayar 7868c965db44STomer Tayar /* fw_asserts dump */ 7869c965db44STomer Tayar rc = qed_dbg_fw_asserts(cdev, (u8 *)buffer + offset + 7870c965db44STomer Tayar REGDUMP_HEADER_SIZE, &feature_size); 7871c965db44STomer Tayar if (!rc) { 7872c965db44STomer Tayar *(u32 *)((u8 *)buffer + offset) = 7873c965db44STomer Tayar qed_calc_regdump_header(FW_ASSERTS, cur_engine, 7874c965db44STomer Tayar feature_size, omit_engine); 7875c965db44STomer Tayar offset += (feature_size + REGDUMP_HEADER_SIZE); 7876c965db44STomer Tayar } else { 7877c965db44STomer Tayar DP_ERR(cdev, "qed_dbg_fw_asserts failed. rc = %d\n", 7878c965db44STomer Tayar rc); 7879c965db44STomer Tayar } 7880c965db44STomer Tayar 7881c965db44STomer Tayar /* GRC dump - must be last because when mcp stuck it will 7882c965db44STomer Tayar * clutter idle_chk, reg_fifo, ... 7883c965db44STomer Tayar */ 7884c965db44STomer Tayar rc = qed_dbg_grc(cdev, (u8 *)buffer + offset + 7885c965db44STomer Tayar REGDUMP_HEADER_SIZE, &feature_size); 7886c965db44STomer Tayar if (!rc) { 7887c965db44STomer Tayar *(u32 *)((u8 *)buffer + offset) = 7888c965db44STomer Tayar qed_calc_regdump_header(GRC_DUMP, cur_engine, 7889c965db44STomer Tayar feature_size, omit_engine); 7890c965db44STomer Tayar offset += (feature_size + REGDUMP_HEADER_SIZE); 7891c965db44STomer Tayar } else { 7892c965db44STomer Tayar DP_ERR(cdev, "qed_dbg_grc failed. rc = %d", rc); 7893c965db44STomer Tayar } 7894c965db44STomer Tayar } 7895c965db44STomer Tayar 7896c965db44STomer Tayar /* mcp_trace */ 7897c965db44STomer Tayar rc = qed_dbg_mcp_trace(cdev, (u8 *)buffer + offset + 7898c965db44STomer Tayar REGDUMP_HEADER_SIZE, &feature_size); 7899c965db44STomer Tayar if (!rc) { 7900c965db44STomer Tayar *(u32 *)((u8 *)buffer + offset) = 7901c965db44STomer Tayar qed_calc_regdump_header(MCP_TRACE, cur_engine, 7902c965db44STomer Tayar feature_size, omit_engine); 7903c965db44STomer Tayar offset += (feature_size + REGDUMP_HEADER_SIZE); 7904c965db44STomer Tayar } else { 7905c965db44STomer Tayar DP_ERR(cdev, "qed_dbg_mcp_trace failed. rc = %d\n", rc); 7906c965db44STomer Tayar } 7907c965db44STomer Tayar 7908c965db44STomer Tayar qed_set_debug_engine(cdev, org_engine); 7909c965db44STomer Tayar 7910c965db44STomer Tayar return 0; 7911c965db44STomer Tayar } 7912c965db44STomer Tayar 7913c965db44STomer Tayar int qed_dbg_all_data_size(struct qed_dev *cdev) 7914c965db44STomer Tayar { 7915c965db44STomer Tayar u8 cur_engine, org_engine; 7916c965db44STomer Tayar u32 regs_len = 0; 7917c965db44STomer Tayar 7918c965db44STomer Tayar org_engine = qed_get_debug_engine(cdev); 7919c965db44STomer Tayar for (cur_engine = 0; cur_engine < cdev->num_hwfns; cur_engine++) { 7920c965db44STomer Tayar /* Engine specific */ 7921c965db44STomer Tayar DP_VERBOSE(cdev, QED_MSG_DEBUG, 7922c965db44STomer Tayar "calculating idle_chk and grcdump register length for current engine\n"); 7923c965db44STomer Tayar qed_set_debug_engine(cdev, cur_engine); 7924c965db44STomer Tayar regs_len += REGDUMP_HEADER_SIZE + qed_dbg_idle_chk_size(cdev) + 7925c965db44STomer Tayar REGDUMP_HEADER_SIZE + qed_dbg_idle_chk_size(cdev) + 7926c965db44STomer Tayar REGDUMP_HEADER_SIZE + qed_dbg_grc_size(cdev) + 7927c965db44STomer Tayar REGDUMP_HEADER_SIZE + qed_dbg_reg_fifo_size(cdev) + 7928c965db44STomer Tayar REGDUMP_HEADER_SIZE + qed_dbg_igu_fifo_size(cdev) + 7929c965db44STomer Tayar REGDUMP_HEADER_SIZE + 7930c965db44STomer Tayar qed_dbg_protection_override_size(cdev) + 7931c965db44STomer Tayar REGDUMP_HEADER_SIZE + qed_dbg_fw_asserts_size(cdev); 7932c965db44STomer Tayar } 7933c965db44STomer Tayar 7934c965db44STomer Tayar /* Engine common */ 7935c965db44STomer Tayar regs_len += REGDUMP_HEADER_SIZE + qed_dbg_mcp_trace_size(cdev); 7936c965db44STomer Tayar qed_set_debug_engine(cdev, org_engine); 7937c965db44STomer Tayar 7938c965db44STomer Tayar return regs_len; 7939c965db44STomer Tayar } 7940c965db44STomer Tayar 7941c965db44STomer Tayar int qed_dbg_feature(struct qed_dev *cdev, void *buffer, 7942c965db44STomer Tayar enum qed_dbg_features feature, u32 *num_dumped_bytes) 7943c965db44STomer Tayar { 7944c965db44STomer Tayar struct qed_hwfn *p_hwfn = 7945c965db44STomer Tayar &cdev->hwfns[cdev->dbg_params.engine_for_debug]; 7946c965db44STomer Tayar struct qed_dbg_feature *qed_feature = 7947c965db44STomer Tayar &cdev->dbg_params.features[feature]; 7948c965db44STomer Tayar enum dbg_status dbg_rc; 7949c965db44STomer Tayar struct qed_ptt *p_ptt; 7950c965db44STomer Tayar int rc = 0; 7951c965db44STomer Tayar 7952c965db44STomer Tayar /* Acquire ptt */ 7953c965db44STomer Tayar p_ptt = qed_ptt_acquire(p_hwfn); 7954c965db44STomer Tayar if (!p_ptt) 7955c965db44STomer Tayar return -EINVAL; 7956c965db44STomer Tayar 7957c965db44STomer Tayar /* Get dump */ 7958c965db44STomer Tayar dbg_rc = qed_dbg_dump(p_hwfn, p_ptt, feature); 7959c965db44STomer Tayar if (dbg_rc != DBG_STATUS_OK) { 7960c965db44STomer Tayar DP_VERBOSE(cdev, QED_MSG_DEBUG, "%s\n", 7961c965db44STomer Tayar qed_dbg_get_status_str(dbg_rc)); 7962c965db44STomer Tayar *num_dumped_bytes = 0; 7963c965db44STomer Tayar rc = -EINVAL; 7964c965db44STomer Tayar goto out; 7965c965db44STomer Tayar } 7966c965db44STomer Tayar 7967c965db44STomer Tayar DP_VERBOSE(cdev, QED_MSG_DEBUG, 7968c965db44STomer Tayar "copying debugfs feature to external buffer\n"); 7969c965db44STomer Tayar memcpy(buffer, qed_feature->dump_buf, qed_feature->buf_size); 7970c965db44STomer Tayar *num_dumped_bytes = cdev->dbg_params.features[feature].dumped_dwords * 7971c965db44STomer Tayar 4; 7972c965db44STomer Tayar 7973c965db44STomer Tayar out: 7974c965db44STomer Tayar qed_ptt_release(p_hwfn, p_ptt); 7975c965db44STomer Tayar return rc; 7976c965db44STomer Tayar } 7977c965db44STomer Tayar 7978c965db44STomer Tayar int qed_dbg_feature_size(struct qed_dev *cdev, enum qed_dbg_features feature) 7979c965db44STomer Tayar { 7980c965db44STomer Tayar struct qed_hwfn *p_hwfn = 7981c965db44STomer Tayar &cdev->hwfns[cdev->dbg_params.engine_for_debug]; 7982c965db44STomer Tayar struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn); 7983c965db44STomer Tayar struct qed_dbg_feature *qed_feature = 7984c965db44STomer Tayar &cdev->dbg_params.features[feature]; 7985c965db44STomer Tayar u32 buf_size_dwords; 7986c965db44STomer Tayar enum dbg_status rc; 7987c965db44STomer Tayar 7988c965db44STomer Tayar if (!p_ptt) 7989c965db44STomer Tayar return -EINVAL; 7990c965db44STomer Tayar 7991c965db44STomer Tayar rc = qed_features_lookup[feature].get_size(p_hwfn, p_ptt, 7992c965db44STomer Tayar &buf_size_dwords); 7993c965db44STomer Tayar if (rc != DBG_STATUS_OK) 7994c965db44STomer Tayar buf_size_dwords = 0; 7995c965db44STomer Tayar 7996c965db44STomer Tayar qed_ptt_release(p_hwfn, p_ptt); 7997c965db44STomer Tayar qed_feature->buf_size = buf_size_dwords * sizeof(u32); 7998c965db44STomer Tayar return qed_feature->buf_size; 7999c965db44STomer Tayar } 8000c965db44STomer Tayar 8001c965db44STomer Tayar u8 qed_get_debug_engine(struct qed_dev *cdev) 8002c965db44STomer Tayar { 8003c965db44STomer Tayar return cdev->dbg_params.engine_for_debug; 8004c965db44STomer Tayar } 8005c965db44STomer Tayar 8006c965db44STomer Tayar void qed_set_debug_engine(struct qed_dev *cdev, int engine_number) 8007c965db44STomer Tayar { 8008c965db44STomer Tayar DP_VERBOSE(cdev, QED_MSG_DEBUG, "set debug engine to %d\n", 8009c965db44STomer Tayar engine_number); 8010c965db44STomer Tayar cdev->dbg_params.engine_for_debug = engine_number; 8011c965db44STomer Tayar } 8012c965db44STomer Tayar 8013c965db44STomer Tayar void qed_dbg_pf_init(struct qed_dev *cdev) 8014c965db44STomer Tayar { 8015c965db44STomer Tayar const u8 *dbg_values; 8016c965db44STomer Tayar 8017c965db44STomer Tayar /* Debug values are after init values. 8018c965db44STomer Tayar * The offset is the first dword of the file. 8019c965db44STomer Tayar */ 8020c965db44STomer Tayar dbg_values = cdev->firmware->data + *(u32 *)cdev->firmware->data; 8021c965db44STomer Tayar qed_dbg_set_bin_ptr((u8 *)dbg_values); 8022c965db44STomer Tayar qed_dbg_user_set_bin_ptr((u8 *)dbg_values); 8023c965db44STomer Tayar } 8024c965db44STomer Tayar 8025c965db44STomer Tayar void qed_dbg_pf_exit(struct qed_dev *cdev) 8026c965db44STomer Tayar { 8027c965db44STomer Tayar struct qed_dbg_feature *feature = NULL; 8028c965db44STomer Tayar enum qed_dbg_features feature_idx; 8029c965db44STomer Tayar 8030c965db44STomer Tayar /* Debug features' buffers may be allocated if debug feature was used 8031c965db44STomer Tayar * but dump wasn't called. 8032c965db44STomer Tayar */ 8033c965db44STomer Tayar for (feature_idx = 0; feature_idx < DBG_FEATURE_NUM; feature_idx++) { 8034c965db44STomer Tayar feature = &cdev->dbg_params.features[feature_idx]; 8035c965db44STomer Tayar if (feature->dump_buf) { 8036c965db44STomer Tayar vfree(feature->dump_buf); 8037c965db44STomer Tayar feature->dump_buf = NULL; 8038c965db44STomer Tayar } 8039c965db44STomer Tayar } 8040c965db44STomer Tayar } 8041