1c965db44STomer Tayar /* QLogic qed NIC Driver 2c965db44STomer Tayar * Copyright (c) 2015 QLogic Corporation 3c965db44STomer Tayar * 4c965db44STomer Tayar * This software is available under the terms of the GNU General Public License 5c965db44STomer Tayar * (GPL) Version 2, available from the file COPYING in the main directory of 6c965db44STomer Tayar * this source tree. 7c965db44STomer Tayar */ 8c965db44STomer Tayar 9c965db44STomer Tayar #include <linux/module.h> 10c965db44STomer Tayar #include <linux/vmalloc.h> 11c965db44STomer Tayar #include <linux/crc32.h> 12c965db44STomer Tayar #include "qed.h" 13c965db44STomer Tayar #include "qed_hsi.h" 14c965db44STomer Tayar #include "qed_hw.h" 15c965db44STomer Tayar #include "qed_mcp.h" 16c965db44STomer Tayar #include "qed_reg_addr.h" 17c965db44STomer Tayar 18c965db44STomer Tayar /* Memory groups enum */ 19c965db44STomer Tayar enum mem_groups { 20c965db44STomer Tayar MEM_GROUP_PXP_MEM, 21c965db44STomer Tayar MEM_GROUP_DMAE_MEM, 22c965db44STomer Tayar MEM_GROUP_CM_MEM, 23c965db44STomer Tayar MEM_GROUP_QM_MEM, 24da090917STomer Tayar MEM_GROUP_DORQ_MEM, 25c965db44STomer Tayar MEM_GROUP_BRB_RAM, 26c965db44STomer Tayar MEM_GROUP_BRB_MEM, 27c965db44STomer Tayar MEM_GROUP_PRS_MEM, 28c965db44STomer Tayar MEM_GROUP_IOR, 29c965db44STomer Tayar MEM_GROUP_BTB_RAM, 30c965db44STomer Tayar MEM_GROUP_CONN_CFC_MEM, 31c965db44STomer Tayar MEM_GROUP_TASK_CFC_MEM, 32c965db44STomer Tayar MEM_GROUP_CAU_PI, 33c965db44STomer Tayar MEM_GROUP_CAU_MEM, 34c965db44STomer Tayar MEM_GROUP_PXP_ILT, 35da090917STomer Tayar MEM_GROUP_TM_MEM, 36da090917STomer Tayar MEM_GROUP_SDM_MEM, 377b6859fbSMintz, Yuval MEM_GROUP_PBUF, 38da090917STomer Tayar MEM_GROUP_RAM, 39c965db44STomer Tayar MEM_GROUP_MULD_MEM, 40c965db44STomer Tayar MEM_GROUP_BTB_MEM, 41da090917STomer Tayar MEM_GROUP_RDIF_CTX, 42da090917STomer Tayar MEM_GROUP_TDIF_CTX, 43da090917STomer Tayar MEM_GROUP_CFC_MEM, 44c965db44STomer Tayar MEM_GROUP_IGU_MEM, 45c965db44STomer Tayar MEM_GROUP_IGU_MSIX, 46c965db44STomer Tayar MEM_GROUP_CAU_SB, 47c965db44STomer Tayar MEM_GROUP_BMB_RAM, 48c965db44STomer Tayar MEM_GROUP_BMB_MEM, 49c965db44STomer Tayar MEM_GROUPS_NUM 50c965db44STomer Tayar }; 51c965db44STomer Tayar 52c965db44STomer Tayar /* Memory groups names */ 53c965db44STomer Tayar static const char * const s_mem_group_names[] = { 54c965db44STomer Tayar "PXP_MEM", 55c965db44STomer Tayar "DMAE_MEM", 56c965db44STomer Tayar "CM_MEM", 57c965db44STomer Tayar "QM_MEM", 58da090917STomer Tayar "DORQ_MEM", 59c965db44STomer Tayar "BRB_RAM", 60c965db44STomer Tayar "BRB_MEM", 61c965db44STomer Tayar "PRS_MEM", 62c965db44STomer Tayar "IOR", 63c965db44STomer Tayar "BTB_RAM", 64c965db44STomer Tayar "CONN_CFC_MEM", 65c965db44STomer Tayar "TASK_CFC_MEM", 66c965db44STomer Tayar "CAU_PI", 67c965db44STomer Tayar "CAU_MEM", 68c965db44STomer Tayar "PXP_ILT", 69da090917STomer Tayar "TM_MEM", 70da090917STomer Tayar "SDM_MEM", 717b6859fbSMintz, Yuval "PBUF", 72da090917STomer Tayar "RAM", 73c965db44STomer Tayar "MULD_MEM", 74c965db44STomer Tayar "BTB_MEM", 75da090917STomer Tayar "RDIF_CTX", 76da090917STomer Tayar "TDIF_CTX", 77da090917STomer Tayar "CFC_MEM", 78c965db44STomer Tayar "IGU_MEM", 79c965db44STomer Tayar "IGU_MSIX", 80c965db44STomer Tayar "CAU_SB", 81c965db44STomer Tayar "BMB_RAM", 82c965db44STomer Tayar "BMB_MEM", 83c965db44STomer Tayar }; 84c965db44STomer Tayar 85c965db44STomer Tayar /* Idle check conditions */ 867b6859fbSMintz, Yuval 877b6859fbSMintz, Yuval static u32 cond5(const u32 *r, const u32 *imm) 88c965db44STomer Tayar { 89c965db44STomer Tayar return ((r[0] & imm[0]) != imm[1]) && ((r[1] & imm[2]) != imm[3]); 90c965db44STomer Tayar } 91c965db44STomer Tayar 927b6859fbSMintz, Yuval static u32 cond7(const u32 *r, const u32 *imm) 93c965db44STomer Tayar { 94c965db44STomer Tayar return ((r[0] >> imm[0]) & imm[1]) != imm[2]; 95c965db44STomer Tayar } 96c965db44STomer Tayar 977b6859fbSMintz, Yuval static u32 cond6(const u32 *r, const u32 *imm) 98c965db44STomer Tayar { 99c965db44STomer Tayar return (r[0] & imm[0]) != imm[1]; 100c965db44STomer Tayar } 101c965db44STomer Tayar 1027b6859fbSMintz, Yuval static u32 cond9(const u32 *r, const u32 *imm) 103c965db44STomer Tayar { 104c965db44STomer Tayar return ((r[0] & imm[0]) >> imm[1]) != 105c965db44STomer Tayar (((r[0] & imm[2]) >> imm[3]) | ((r[1] & imm[4]) << imm[5])); 106c965db44STomer Tayar } 107c965db44STomer Tayar 1087b6859fbSMintz, Yuval static u32 cond10(const u32 *r, const u32 *imm) 109c965db44STomer Tayar { 110c965db44STomer Tayar return ((r[0] & imm[0]) >> imm[1]) != (r[0] & imm[2]); 111c965db44STomer Tayar } 112c965db44STomer Tayar 1137b6859fbSMintz, Yuval static u32 cond4(const u32 *r, const u32 *imm) 114c965db44STomer Tayar { 115c965db44STomer Tayar return (r[0] & ~imm[0]) != imm[1]; 116c965db44STomer Tayar } 117c965db44STomer Tayar 118c965db44STomer Tayar static u32 cond0(const u32 *r, const u32 *imm) 119c965db44STomer Tayar { 1207b6859fbSMintz, Yuval return (r[0] & ~r[1]) != imm[0]; 1217b6859fbSMintz, Yuval } 1227b6859fbSMintz, Yuval 1237b6859fbSMintz, Yuval static u32 cond1(const u32 *r, const u32 *imm) 1247b6859fbSMintz, Yuval { 125c965db44STomer Tayar return r[0] != imm[0]; 126c965db44STomer Tayar } 127c965db44STomer Tayar 1287b6859fbSMintz, Yuval static u32 cond11(const u32 *r, const u32 *imm) 129c965db44STomer Tayar { 130c965db44STomer Tayar return r[0] != r[1] && r[2] == imm[0]; 131c965db44STomer Tayar } 132c965db44STomer Tayar 1337b6859fbSMintz, Yuval static u32 cond12(const u32 *r, const u32 *imm) 134c965db44STomer Tayar { 135c965db44STomer Tayar return r[0] != r[1] && r[2] > imm[0]; 136c965db44STomer Tayar } 137c965db44STomer Tayar 138c965db44STomer Tayar static u32 cond3(const u32 *r, const u32 *imm) 139c965db44STomer Tayar { 140c965db44STomer Tayar return r[0] != r[1]; 141c965db44STomer Tayar } 142c965db44STomer Tayar 1437b6859fbSMintz, Yuval static u32 cond13(const u32 *r, const u32 *imm) 144c965db44STomer Tayar { 145c965db44STomer Tayar return r[0] & imm[0]; 146c965db44STomer Tayar } 147c965db44STomer Tayar 1487b6859fbSMintz, Yuval static u32 cond8(const u32 *r, const u32 *imm) 149c965db44STomer Tayar { 150c965db44STomer Tayar return r[0] < (r[1] - imm[0]); 151c965db44STomer Tayar } 152c965db44STomer Tayar 153c965db44STomer Tayar static u32 cond2(const u32 *r, const u32 *imm) 154c965db44STomer Tayar { 155c965db44STomer Tayar return r[0] > imm[0]; 156c965db44STomer Tayar } 157c965db44STomer Tayar 158c965db44STomer Tayar /* Array of Idle Check conditions */ 159c965db44STomer Tayar static u32(*cond_arr[]) (const u32 *r, const u32 *imm) = { 160c965db44STomer Tayar cond0, 161c965db44STomer Tayar cond1, 162c965db44STomer Tayar cond2, 163c965db44STomer Tayar cond3, 164c965db44STomer Tayar cond4, 165c965db44STomer Tayar cond5, 166c965db44STomer Tayar cond6, 167c965db44STomer Tayar cond7, 168c965db44STomer Tayar cond8, 169c965db44STomer Tayar cond9, 170c965db44STomer Tayar cond10, 171c965db44STomer Tayar cond11, 172c965db44STomer Tayar cond12, 1737b6859fbSMintz, Yuval cond13, 174c965db44STomer Tayar }; 175c965db44STomer Tayar 176c965db44STomer Tayar /******************************* Data Types **********************************/ 177c965db44STomer Tayar 178c965db44STomer Tayar enum platform_ids { 179c965db44STomer Tayar PLATFORM_ASIC, 180c965db44STomer Tayar PLATFORM_RESERVED, 181c965db44STomer Tayar PLATFORM_RESERVED2, 182c965db44STomer Tayar PLATFORM_RESERVED3, 183c965db44STomer Tayar MAX_PLATFORM_IDS 184c965db44STomer Tayar }; 185c965db44STomer Tayar 186c965db44STomer Tayar /* Chip constant definitions */ 187c965db44STomer Tayar struct chip_defs { 188c965db44STomer Tayar const char *name; 189c965db44STomer Tayar }; 190c965db44STomer Tayar 191c965db44STomer Tayar /* Platform constant definitions */ 192c965db44STomer Tayar struct platform_defs { 193c965db44STomer Tayar const char *name; 194c965db44STomer Tayar u32 delay_factor; 195da090917STomer Tayar u32 dmae_thresh; 196da090917STomer Tayar u32 log_thresh; 197c965db44STomer Tayar }; 198c965db44STomer Tayar 1997b6859fbSMintz, Yuval /* Storm constant definitions. 2007b6859fbSMintz, Yuval * Addresses are in bytes, sizes are in quad-regs. 2017b6859fbSMintz, Yuval */ 202c965db44STomer Tayar struct storm_defs { 203c965db44STomer Tayar char letter; 204c965db44STomer Tayar enum block_id block_id; 205c965db44STomer Tayar enum dbg_bus_clients dbg_client_id[MAX_CHIP_IDS]; 206c965db44STomer Tayar bool has_vfc; 207c965db44STomer Tayar u32 sem_fast_mem_addr; 208c965db44STomer Tayar u32 sem_frame_mode_addr; 209c965db44STomer Tayar u32 sem_slow_enable_addr; 210c965db44STomer Tayar u32 sem_slow_mode_addr; 211c965db44STomer Tayar u32 sem_slow_mode1_conf_addr; 212c965db44STomer Tayar u32 sem_sync_dbg_empty_addr; 213c965db44STomer Tayar u32 sem_slow_dbg_empty_addr; 214c965db44STomer Tayar u32 cm_ctx_wr_addr; 2157b6859fbSMintz, Yuval u32 cm_conn_ag_ctx_lid_size; 216c965db44STomer Tayar u32 cm_conn_ag_ctx_rd_addr; 2177b6859fbSMintz, Yuval u32 cm_conn_st_ctx_lid_size; 218c965db44STomer Tayar u32 cm_conn_st_ctx_rd_addr; 2197b6859fbSMintz, Yuval u32 cm_task_ag_ctx_lid_size; 220c965db44STomer Tayar u32 cm_task_ag_ctx_rd_addr; 2217b6859fbSMintz, Yuval u32 cm_task_st_ctx_lid_size; 222c965db44STomer Tayar u32 cm_task_st_ctx_rd_addr; 223c965db44STomer Tayar }; 224c965db44STomer Tayar 225c965db44STomer Tayar /* Block constant definitions */ 226c965db44STomer Tayar struct block_defs { 227c965db44STomer Tayar const char *name; 228da090917STomer Tayar bool exists[MAX_CHIP_IDS]; 229c965db44STomer Tayar bool associated_to_storm; 2307b6859fbSMintz, Yuval 2317b6859fbSMintz, Yuval /* Valid only if associated_to_storm is true */ 2327b6859fbSMintz, Yuval u32 storm_id; 233c965db44STomer Tayar enum dbg_bus_clients dbg_client_id[MAX_CHIP_IDS]; 234c965db44STomer Tayar u32 dbg_select_addr; 2357b6859fbSMintz, Yuval u32 dbg_enable_addr; 236c965db44STomer Tayar u32 dbg_shift_addr; 237c965db44STomer Tayar u32 dbg_force_valid_addr; 238c965db44STomer Tayar u32 dbg_force_frame_addr; 239c965db44STomer Tayar bool has_reset_bit; 2407b6859fbSMintz, Yuval 2417b6859fbSMintz, Yuval /* If true, block is taken out of reset before dump */ 2427b6859fbSMintz, Yuval bool unreset; 243c965db44STomer Tayar enum dbg_reset_regs reset_reg; 2447b6859fbSMintz, Yuval 2457b6859fbSMintz, Yuval /* Bit offset in reset register */ 2467b6859fbSMintz, Yuval u8 reset_bit_offset; 247c965db44STomer Tayar }; 248c965db44STomer Tayar 249c965db44STomer Tayar /* Reset register definitions */ 250c965db44STomer Tayar struct reset_reg_defs { 251c965db44STomer Tayar u32 addr; 252c965db44STomer Tayar bool exists[MAX_CHIP_IDS]; 253da090917STomer Tayar u32 unreset_val[MAX_CHIP_IDS]; 254c965db44STomer Tayar }; 255c965db44STomer Tayar 256c965db44STomer Tayar struct grc_param_defs { 257c965db44STomer Tayar u32 default_val[MAX_CHIP_IDS]; 258c965db44STomer Tayar u32 min; 259c965db44STomer Tayar u32 max; 260c965db44STomer Tayar bool is_preset; 26150bc60cbSMichal Kalderon bool is_persistent; 262c965db44STomer Tayar u32 exclude_all_preset_val; 263c965db44STomer Tayar u32 crash_preset_val; 264c965db44STomer Tayar }; 265c965db44STomer Tayar 2667b6859fbSMintz, Yuval /* Address is in 128b units. Width is in bits. */ 267c965db44STomer Tayar struct rss_mem_defs { 268c965db44STomer Tayar const char *mem_name; 269c965db44STomer Tayar const char *type_name; 2707b6859fbSMintz, Yuval u32 addr; 271da090917STomer Tayar u32 entry_width; 272c965db44STomer Tayar u32 num_entries[MAX_CHIP_IDS]; 273c965db44STomer Tayar }; 274c965db44STomer Tayar 275c965db44STomer Tayar struct vfc_ram_defs { 276c965db44STomer Tayar const char *mem_name; 277c965db44STomer Tayar const char *type_name; 278c965db44STomer Tayar u32 base_row; 279c965db44STomer Tayar u32 num_rows; 280c965db44STomer Tayar }; 281c965db44STomer Tayar 282c965db44STomer Tayar struct big_ram_defs { 283c965db44STomer Tayar const char *instance_name; 284c965db44STomer Tayar enum mem_groups mem_group_id; 285c965db44STomer Tayar enum mem_groups ram_mem_group_id; 286c965db44STomer Tayar enum dbg_grc_params grc_param; 287c965db44STomer Tayar u32 addr_reg_addr; 288c965db44STomer Tayar u32 data_reg_addr; 289da090917STomer Tayar u32 is_256b_reg_addr; 290da090917STomer Tayar u32 is_256b_bit_offset[MAX_CHIP_IDS]; 291da090917STomer Tayar u32 ram_size[MAX_CHIP_IDS]; /* In dwords */ 292c965db44STomer Tayar }; 293c965db44STomer Tayar 294c965db44STomer Tayar struct phy_defs { 295c965db44STomer Tayar const char *phy_name; 2967b6859fbSMintz, Yuval 2977b6859fbSMintz, Yuval /* PHY base GRC address */ 298c965db44STomer Tayar u32 base_addr; 2997b6859fbSMintz, Yuval 3007b6859fbSMintz, Yuval /* Relative address of indirect TBUS address register (bits 0..7) */ 301c965db44STomer Tayar u32 tbus_addr_lo_addr; 3027b6859fbSMintz, Yuval 3037b6859fbSMintz, Yuval /* Relative address of indirect TBUS address register (bits 8..10) */ 304c965db44STomer Tayar u32 tbus_addr_hi_addr; 3057b6859fbSMintz, Yuval 3067b6859fbSMintz, Yuval /* Relative address of indirect TBUS data register (bits 0..7) */ 307c965db44STomer Tayar u32 tbus_data_lo_addr; 3087b6859fbSMintz, Yuval 3097b6859fbSMintz, Yuval /* Relative address of indirect TBUS data register (bits 8..11) */ 310c965db44STomer Tayar u32 tbus_data_hi_addr; 311c965db44STomer Tayar }; 312c965db44STomer Tayar 313d52c89f1SMichal Kalderon /* Split type definitions */ 314d52c89f1SMichal Kalderon struct split_type_defs { 315d52c89f1SMichal Kalderon const char *name; 316d52c89f1SMichal Kalderon }; 317d52c89f1SMichal Kalderon 318c965db44STomer Tayar /******************************** Constants **********************************/ 319c965db44STomer Tayar 320c965db44STomer Tayar #define MAX_LCIDS 320 321c965db44STomer Tayar #define MAX_LTIDS 320 3227b6859fbSMintz, Yuval 323c965db44STomer Tayar #define NUM_IOR_SETS 2 324c965db44STomer Tayar #define IORS_PER_SET 176 325c965db44STomer Tayar #define IOR_SET_OFFSET(set_id) ((set_id) * 256) 3267b6859fbSMintz, Yuval 327c965db44STomer Tayar #define BYTES_IN_DWORD sizeof(u32) 328c965db44STomer Tayar 329c965db44STomer Tayar /* In the macros below, size and offset are specified in bits */ 330c965db44STomer Tayar #define CEIL_DWORDS(size) DIV_ROUND_UP(size, 32) 331c965db44STomer Tayar #define FIELD_BIT_OFFSET(type, field) type ## _ ## field ## _ ## OFFSET 332c965db44STomer Tayar #define FIELD_BIT_SIZE(type, field) type ## _ ## field ## _ ## SIZE 333c965db44STomer Tayar #define FIELD_DWORD_OFFSET(type, field) \ 334c965db44STomer Tayar (int)(FIELD_BIT_OFFSET(type, field) / 32) 335c965db44STomer Tayar #define FIELD_DWORD_SHIFT(type, field) (FIELD_BIT_OFFSET(type, field) % 32) 336c965db44STomer Tayar #define FIELD_BIT_MASK(type, field) \ 337c965db44STomer Tayar (((1 << FIELD_BIT_SIZE(type, field)) - 1) << \ 338c965db44STomer Tayar FIELD_DWORD_SHIFT(type, field)) 3397b6859fbSMintz, Yuval 340c965db44STomer Tayar #define SET_VAR_FIELD(var, type, field, val) \ 341c965db44STomer Tayar do { \ 342c965db44STomer Tayar var[FIELD_DWORD_OFFSET(type, field)] &= \ 343c965db44STomer Tayar (~FIELD_BIT_MASK(type, field)); \ 344c965db44STomer Tayar var[FIELD_DWORD_OFFSET(type, field)] |= \ 345c965db44STomer Tayar (val) << FIELD_DWORD_SHIFT(type, field); \ 346c965db44STomer Tayar } while (0) 3477b6859fbSMintz, Yuval 348c965db44STomer Tayar #define ARR_REG_WR(dev, ptt, addr, arr, arr_size) \ 349c965db44STomer Tayar do { \ 350c965db44STomer Tayar for (i = 0; i < (arr_size); i++) \ 351c965db44STomer Tayar qed_wr(dev, ptt, addr, (arr)[i]); \ 352c965db44STomer Tayar } while (0) 3537b6859fbSMintz, Yuval 354c965db44STomer Tayar #define ARR_REG_RD(dev, ptt, addr, arr, arr_size) \ 355c965db44STomer Tayar do { \ 356c965db44STomer Tayar for (i = 0; i < (arr_size); i++) \ 357c965db44STomer Tayar (arr)[i] = qed_rd(dev, ptt, addr); \ 358c965db44STomer Tayar } while (0) 359c965db44STomer Tayar 360c965db44STomer Tayar #define DWORDS_TO_BYTES(dwords) ((dwords) * BYTES_IN_DWORD) 361c965db44STomer Tayar #define BYTES_TO_DWORDS(bytes) ((bytes) / BYTES_IN_DWORD) 3627b6859fbSMintz, Yuval 363a2e7699eSTomer Tayar /* Extra lines include a signature line + optional latency events line */ 3647b6859fbSMintz, Yuval #define NUM_EXTRA_DBG_LINES(block_desc) \ 3657b6859fbSMintz, Yuval (1 + ((block_desc)->has_latency_events ? 1 : 0)) 3667b6859fbSMintz, Yuval #define NUM_DBG_LINES(block_desc) \ 3677b6859fbSMintz, Yuval ((block_desc)->num_of_lines + NUM_EXTRA_DBG_LINES(block_desc)) 3687b6859fbSMintz, Yuval 369c965db44STomer Tayar #define RAM_LINES_TO_DWORDS(lines) ((lines) * 2) 370c965db44STomer Tayar #define RAM_LINES_TO_BYTES(lines) \ 371c965db44STomer Tayar DWORDS_TO_BYTES(RAM_LINES_TO_DWORDS(lines)) 3727b6859fbSMintz, Yuval 373c965db44STomer Tayar #define REG_DUMP_LEN_SHIFT 24 374c965db44STomer Tayar #define MEM_DUMP_ENTRY_SIZE_DWORDS \ 375c965db44STomer Tayar BYTES_TO_DWORDS(sizeof(struct dbg_dump_mem)) 3767b6859fbSMintz, Yuval 377c965db44STomer Tayar #define IDLE_CHK_RULE_SIZE_DWORDS \ 378c965db44STomer Tayar BYTES_TO_DWORDS(sizeof(struct dbg_idle_chk_rule)) 3797b6859fbSMintz, Yuval 380c965db44STomer Tayar #define IDLE_CHK_RESULT_HDR_DWORDS \ 381c965db44STomer Tayar BYTES_TO_DWORDS(sizeof(struct dbg_idle_chk_result_hdr)) 3827b6859fbSMintz, Yuval 383c965db44STomer Tayar #define IDLE_CHK_RESULT_REG_HDR_DWORDS \ 384c965db44STomer Tayar BYTES_TO_DWORDS(sizeof(struct dbg_idle_chk_result_reg_hdr)) 3857b6859fbSMintz, Yuval 386c965db44STomer Tayar #define IDLE_CHK_MAX_ENTRIES_SIZE 32 387c965db44STomer Tayar 388c965db44STomer Tayar /* The sizes and offsets below are specified in bits */ 389c965db44STomer Tayar #define VFC_CAM_CMD_STRUCT_SIZE 64 390c965db44STomer Tayar #define VFC_CAM_CMD_ROW_OFFSET 48 391c965db44STomer Tayar #define VFC_CAM_CMD_ROW_SIZE 9 392c965db44STomer Tayar #define VFC_CAM_ADDR_STRUCT_SIZE 16 393c965db44STomer Tayar #define VFC_CAM_ADDR_OP_OFFSET 0 394c965db44STomer Tayar #define VFC_CAM_ADDR_OP_SIZE 4 395c965db44STomer Tayar #define VFC_CAM_RESP_STRUCT_SIZE 256 396c965db44STomer Tayar #define VFC_RAM_ADDR_STRUCT_SIZE 16 397c965db44STomer Tayar #define VFC_RAM_ADDR_OP_OFFSET 0 398c965db44STomer Tayar #define VFC_RAM_ADDR_OP_SIZE 2 399c965db44STomer Tayar #define VFC_RAM_ADDR_ROW_OFFSET 2 400c965db44STomer Tayar #define VFC_RAM_ADDR_ROW_SIZE 10 401c965db44STomer Tayar #define VFC_RAM_RESP_STRUCT_SIZE 256 4027b6859fbSMintz, Yuval 403c965db44STomer Tayar #define VFC_CAM_CMD_DWORDS CEIL_DWORDS(VFC_CAM_CMD_STRUCT_SIZE) 404c965db44STomer Tayar #define VFC_CAM_ADDR_DWORDS CEIL_DWORDS(VFC_CAM_ADDR_STRUCT_SIZE) 405c965db44STomer Tayar #define VFC_CAM_RESP_DWORDS CEIL_DWORDS(VFC_CAM_RESP_STRUCT_SIZE) 406c965db44STomer Tayar #define VFC_RAM_CMD_DWORDS VFC_CAM_CMD_DWORDS 407c965db44STomer Tayar #define VFC_RAM_ADDR_DWORDS CEIL_DWORDS(VFC_RAM_ADDR_STRUCT_SIZE) 408c965db44STomer Tayar #define VFC_RAM_RESP_DWORDS CEIL_DWORDS(VFC_RAM_RESP_STRUCT_SIZE) 4097b6859fbSMintz, Yuval 410c965db44STomer Tayar #define NUM_VFC_RAM_TYPES 4 4117b6859fbSMintz, Yuval 412c965db44STomer Tayar #define VFC_CAM_NUM_ROWS 512 4137b6859fbSMintz, Yuval 414c965db44STomer Tayar #define VFC_OPCODE_CAM_RD 14 415c965db44STomer Tayar #define VFC_OPCODE_RAM_RD 0 4167b6859fbSMintz, Yuval 417c965db44STomer Tayar #define NUM_RSS_MEM_TYPES 5 4187b6859fbSMintz, Yuval 419c965db44STomer Tayar #define NUM_BIG_RAM_TYPES 3 420c7d852e3SDenis Bolotin #define BIG_RAM_NAME_LEN 3 4217b6859fbSMintz, Yuval 422c965db44STomer Tayar #define NUM_PHY_TBUS_ADDRESSES 2048 423c965db44STomer Tayar #define PHY_DUMP_SIZE_DWORDS (NUM_PHY_TBUS_ADDRESSES / 2) 4247b6859fbSMintz, Yuval 425c965db44STomer Tayar #define RESET_REG_UNRESET_OFFSET 4 4267b6859fbSMintz, Yuval 427c965db44STomer Tayar #define STALL_DELAY_MS 500 4287b6859fbSMintz, Yuval 429c965db44STomer Tayar #define STATIC_DEBUG_LINE_DWORDS 9 4307b6859fbSMintz, Yuval 431c965db44STomer Tayar #define NUM_COMMON_GLOBAL_PARAMS 8 4327b6859fbSMintz, Yuval 433c965db44STomer Tayar #define FW_IMG_MAIN 1 4347b6859fbSMintz, Yuval 435c965db44STomer Tayar #define REG_FIFO_ELEMENT_DWORDS 2 4367b6859fbSMintz, Yuval #define REG_FIFO_DEPTH_ELEMENTS 32 437c965db44STomer Tayar #define REG_FIFO_DEPTH_DWORDS \ 438c965db44STomer Tayar (REG_FIFO_ELEMENT_DWORDS * REG_FIFO_DEPTH_ELEMENTS) 4397b6859fbSMintz, Yuval 440c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORDS 4 4417b6859fbSMintz, Yuval #define IGU_FIFO_DEPTH_ELEMENTS 64 442c965db44STomer Tayar #define IGU_FIFO_DEPTH_DWORDS \ 443c965db44STomer Tayar (IGU_FIFO_ELEMENT_DWORDS * IGU_FIFO_DEPTH_ELEMENTS) 4447b6859fbSMintz, Yuval 445c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_DWORDS 2 4467b6859fbSMintz, Yuval #define PROTECTION_OVERRIDE_DEPTH_ELEMENTS 20 447c965db44STomer Tayar #define PROTECTION_OVERRIDE_DEPTH_DWORDS \ 448c965db44STomer Tayar (PROTECTION_OVERRIDE_DEPTH_ELEMENTS * \ 449c965db44STomer Tayar PROTECTION_OVERRIDE_ELEMENT_DWORDS) 4507b6859fbSMintz, Yuval 451c965db44STomer Tayar #define MCP_SPAD_TRACE_OFFSIZE_ADDR \ 452c965db44STomer Tayar (MCP_REG_SCRATCH + \ 453c965db44STomer Tayar offsetof(struct static_init, sections[SPAD_SECTION_TRACE])) 4547b6859fbSMintz, Yuval 455c965db44STomer Tayar #define EMPTY_FW_VERSION_STR "???_???_???_???" 456c965db44STomer Tayar #define EMPTY_FW_IMAGE_STR "???????????????" 457c965db44STomer Tayar 458c965db44STomer Tayar /***************************** Constant Arrays *******************************/ 459c965db44STomer Tayar 4607b6859fbSMintz, Yuval struct dbg_array { 4617b6859fbSMintz, Yuval const u32 *ptr; 4627b6859fbSMintz, Yuval u32 size_in_dwords; 4637b6859fbSMintz, Yuval }; 4647b6859fbSMintz, Yuval 465c965db44STomer Tayar /* Debug arrays */ 4667b6859fbSMintz, Yuval static struct dbg_array s_dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE] = { {NULL} }; 467c965db44STomer Tayar 468c965db44STomer Tayar /* Chip constant definitions array */ 469c965db44STomer Tayar static struct chip_defs s_chip_defs[MAX_CHIP_IDS] = { 470d52c89f1SMichal Kalderon {"bb"}, 471d52c89f1SMichal Kalderon {"ah"}, 472d52c89f1SMichal Kalderon {"reserved"}, 473c965db44STomer Tayar }; 474c965db44STomer Tayar 475c965db44STomer Tayar /* Storm constant definitions array */ 476c965db44STomer Tayar static struct storm_defs s_storm_defs[] = { 477c965db44STomer Tayar /* Tstorm */ 478c965db44STomer Tayar {'T', BLOCK_TSEM, 479da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, 480da090917STomer Tayar DBG_BUS_CLIENT_RBCT}, true, 481c965db44STomer Tayar TSEM_REG_FAST_MEMORY, 4827b6859fbSMintz, Yuval TSEM_REG_DBG_FRAME_MODE_BB_K2, TSEM_REG_SLOW_DBG_ACTIVE_BB_K2, 4837b6859fbSMintz, Yuval TSEM_REG_SLOW_DBG_MODE_BB_K2, TSEM_REG_DBG_MODE1_CFG_BB_K2, 4847b6859fbSMintz, Yuval TSEM_REG_SYNC_DBG_EMPTY, TSEM_REG_SLOW_DBG_EMPTY_BB_K2, 485c965db44STomer Tayar TCM_REG_CTX_RBC_ACCS, 486c965db44STomer Tayar 4, TCM_REG_AGG_CON_CTX, 487c965db44STomer Tayar 16, TCM_REG_SM_CON_CTX, 488c965db44STomer Tayar 2, TCM_REG_AGG_TASK_CTX, 489c965db44STomer Tayar 4, TCM_REG_SM_TASK_CTX}, 4907b6859fbSMintz, Yuval 491c965db44STomer Tayar /* Mstorm */ 492c965db44STomer Tayar {'M', BLOCK_MSEM, 493da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, 494da090917STomer Tayar DBG_BUS_CLIENT_RBCM}, false, 495c965db44STomer Tayar MSEM_REG_FAST_MEMORY, 4967b6859fbSMintz, Yuval MSEM_REG_DBG_FRAME_MODE_BB_K2, MSEM_REG_SLOW_DBG_ACTIVE_BB_K2, 4977b6859fbSMintz, Yuval MSEM_REG_SLOW_DBG_MODE_BB_K2, MSEM_REG_DBG_MODE1_CFG_BB_K2, 4987b6859fbSMintz, Yuval MSEM_REG_SYNC_DBG_EMPTY, MSEM_REG_SLOW_DBG_EMPTY_BB_K2, 499c965db44STomer Tayar MCM_REG_CTX_RBC_ACCS, 500c965db44STomer Tayar 1, MCM_REG_AGG_CON_CTX, 501c965db44STomer Tayar 10, MCM_REG_SM_CON_CTX, 502c965db44STomer Tayar 2, MCM_REG_AGG_TASK_CTX, 503c965db44STomer Tayar 7, MCM_REG_SM_TASK_CTX}, 5047b6859fbSMintz, Yuval 505c965db44STomer Tayar /* Ustorm */ 506c965db44STomer Tayar {'U', BLOCK_USEM, 507da090917STomer Tayar {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, 508da090917STomer Tayar DBG_BUS_CLIENT_RBCU}, false, 509c965db44STomer Tayar USEM_REG_FAST_MEMORY, 5107b6859fbSMintz, Yuval USEM_REG_DBG_FRAME_MODE_BB_K2, USEM_REG_SLOW_DBG_ACTIVE_BB_K2, 5117b6859fbSMintz, Yuval USEM_REG_SLOW_DBG_MODE_BB_K2, USEM_REG_DBG_MODE1_CFG_BB_K2, 5127b6859fbSMintz, Yuval USEM_REG_SYNC_DBG_EMPTY, USEM_REG_SLOW_DBG_EMPTY_BB_K2, 513c965db44STomer Tayar UCM_REG_CTX_RBC_ACCS, 514c965db44STomer Tayar 2, UCM_REG_AGG_CON_CTX, 515c965db44STomer Tayar 13, UCM_REG_SM_CON_CTX, 516c965db44STomer Tayar 3, UCM_REG_AGG_TASK_CTX, 517c965db44STomer Tayar 3, UCM_REG_SM_TASK_CTX}, 5187b6859fbSMintz, Yuval 519c965db44STomer Tayar /* Xstorm */ 520c965db44STomer Tayar {'X', BLOCK_XSEM, 521da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, 522da090917STomer Tayar DBG_BUS_CLIENT_RBCX}, false, 523c965db44STomer Tayar XSEM_REG_FAST_MEMORY, 5247b6859fbSMintz, Yuval XSEM_REG_DBG_FRAME_MODE_BB_K2, XSEM_REG_SLOW_DBG_ACTIVE_BB_K2, 5257b6859fbSMintz, Yuval XSEM_REG_SLOW_DBG_MODE_BB_K2, XSEM_REG_DBG_MODE1_CFG_BB_K2, 5267b6859fbSMintz, Yuval XSEM_REG_SYNC_DBG_EMPTY, XSEM_REG_SLOW_DBG_EMPTY_BB_K2, 527c965db44STomer Tayar XCM_REG_CTX_RBC_ACCS, 528c965db44STomer Tayar 9, XCM_REG_AGG_CON_CTX, 529c965db44STomer Tayar 15, XCM_REG_SM_CON_CTX, 530c965db44STomer Tayar 0, 0, 531c965db44STomer Tayar 0, 0}, 5327b6859fbSMintz, Yuval 533c965db44STomer Tayar /* Ystorm */ 534c965db44STomer Tayar {'Y', BLOCK_YSEM, 535da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, 536da090917STomer Tayar DBG_BUS_CLIENT_RBCY}, false, 537c965db44STomer Tayar YSEM_REG_FAST_MEMORY, 5387b6859fbSMintz, Yuval YSEM_REG_DBG_FRAME_MODE_BB_K2, YSEM_REG_SLOW_DBG_ACTIVE_BB_K2, 5397b6859fbSMintz, Yuval YSEM_REG_SLOW_DBG_MODE_BB_K2, YSEM_REG_DBG_MODE1_CFG_BB_K2, 5407b6859fbSMintz, Yuval YSEM_REG_SYNC_DBG_EMPTY, TSEM_REG_SLOW_DBG_EMPTY_BB_K2, 541c965db44STomer Tayar YCM_REG_CTX_RBC_ACCS, 542c965db44STomer Tayar 2, YCM_REG_AGG_CON_CTX, 543c965db44STomer Tayar 3, YCM_REG_SM_CON_CTX, 544c965db44STomer Tayar 2, YCM_REG_AGG_TASK_CTX, 545c965db44STomer Tayar 12, YCM_REG_SM_TASK_CTX}, 5467b6859fbSMintz, Yuval 547c965db44STomer Tayar /* Pstorm */ 548c965db44STomer Tayar {'P', BLOCK_PSEM, 549da090917STomer Tayar {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, 550da090917STomer Tayar DBG_BUS_CLIENT_RBCS}, true, 551c965db44STomer Tayar PSEM_REG_FAST_MEMORY, 5527b6859fbSMintz, Yuval PSEM_REG_DBG_FRAME_MODE_BB_K2, PSEM_REG_SLOW_DBG_ACTIVE_BB_K2, 5537b6859fbSMintz, Yuval PSEM_REG_SLOW_DBG_MODE_BB_K2, PSEM_REG_DBG_MODE1_CFG_BB_K2, 5547b6859fbSMintz, Yuval PSEM_REG_SYNC_DBG_EMPTY, PSEM_REG_SLOW_DBG_EMPTY_BB_K2, 555c965db44STomer Tayar PCM_REG_CTX_RBC_ACCS, 556c965db44STomer Tayar 0, 0, 557c965db44STomer Tayar 10, PCM_REG_SM_CON_CTX, 558c965db44STomer Tayar 0, 0, 559c965db44STomer Tayar 0, 0} 560c965db44STomer Tayar }; 561c965db44STomer Tayar 562c965db44STomer Tayar /* Block definitions array */ 5637b6859fbSMintz, Yuval 564c965db44STomer Tayar static struct block_defs block_grc_defs = { 565be086e7cSMintz, Yuval "grc", 566da090917STomer Tayar {true, true, true}, false, 0, 567da090917STomer Tayar {DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN}, 568c965db44STomer Tayar GRC_REG_DBG_SELECT, GRC_REG_DBG_DWORD_ENABLE, 569c965db44STomer Tayar GRC_REG_DBG_SHIFT, GRC_REG_DBG_FORCE_VALID, 570c965db44STomer Tayar GRC_REG_DBG_FORCE_FRAME, 571c965db44STomer Tayar true, false, DBG_RESET_REG_MISC_PL_UA, 1 572c965db44STomer Tayar }; 573c965db44STomer Tayar 574c965db44STomer Tayar static struct block_defs block_miscs_defs = { 575da090917STomer Tayar "miscs", {true, true, true}, false, 0, 576da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 577c965db44STomer Tayar 0, 0, 0, 0, 0, 578c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 579c965db44STomer Tayar }; 580c965db44STomer Tayar 581c965db44STomer Tayar static struct block_defs block_misc_defs = { 582da090917STomer Tayar "misc", {true, true, true}, false, 0, 583da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 584c965db44STomer Tayar 0, 0, 0, 0, 0, 585c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 586c965db44STomer Tayar }; 587c965db44STomer Tayar 588c965db44STomer Tayar static struct block_defs block_dbu_defs = { 589da090917STomer Tayar "dbu", {true, true, true}, false, 0, 590da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 591c965db44STomer Tayar 0, 0, 0, 0, 0, 592c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 593c965db44STomer Tayar }; 594c965db44STomer Tayar 595c965db44STomer Tayar static struct block_defs block_pglue_b_defs = { 596be086e7cSMintz, Yuval "pglue_b", 597da090917STomer Tayar {true, true, true}, false, 0, 598da090917STomer Tayar {DBG_BUS_CLIENT_RBCH, DBG_BUS_CLIENT_RBCH, DBG_BUS_CLIENT_RBCH}, 599c965db44STomer Tayar PGLUE_B_REG_DBG_SELECT, PGLUE_B_REG_DBG_DWORD_ENABLE, 600c965db44STomer Tayar PGLUE_B_REG_DBG_SHIFT, PGLUE_B_REG_DBG_FORCE_VALID, 601c965db44STomer Tayar PGLUE_B_REG_DBG_FORCE_FRAME, 602c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV, 1 603c965db44STomer Tayar }; 604c965db44STomer Tayar 605c965db44STomer Tayar static struct block_defs block_cnig_defs = { 606be086e7cSMintz, Yuval "cnig", 607da090917STomer Tayar {true, true, true}, false, 0, 608da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW, 609da090917STomer Tayar DBG_BUS_CLIENT_RBCW}, 61021dd79e8STomer Tayar CNIG_REG_DBG_SELECT_K2_E5, CNIG_REG_DBG_DWORD_ENABLE_K2_E5, 61121dd79e8STomer Tayar CNIG_REG_DBG_SHIFT_K2_E5, CNIG_REG_DBG_FORCE_VALID_K2_E5, 61221dd79e8STomer Tayar CNIG_REG_DBG_FORCE_FRAME_K2_E5, 613c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV, 0 614c965db44STomer Tayar }; 615c965db44STomer Tayar 616c965db44STomer Tayar static struct block_defs block_cpmu_defs = { 617da090917STomer Tayar "cpmu", {true, true, true}, false, 0, 618da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 619c965db44STomer Tayar 0, 0, 0, 0, 0, 620c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV, 8 621c965db44STomer Tayar }; 622c965db44STomer Tayar 623c965db44STomer Tayar static struct block_defs block_ncsi_defs = { 624be086e7cSMintz, Yuval "ncsi", 625da090917STomer Tayar {true, true, true}, false, 0, 626da090917STomer Tayar {DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ}, 627c965db44STomer Tayar NCSI_REG_DBG_SELECT, NCSI_REG_DBG_DWORD_ENABLE, 628c965db44STomer Tayar NCSI_REG_DBG_SHIFT, NCSI_REG_DBG_FORCE_VALID, 629c965db44STomer Tayar NCSI_REG_DBG_FORCE_FRAME, 630c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV, 5 631c965db44STomer Tayar }; 632c965db44STomer Tayar 633c965db44STomer Tayar static struct block_defs block_opte_defs = { 634da090917STomer Tayar "opte", {true, true, false}, false, 0, 635da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 636c965db44STomer Tayar 0, 0, 0, 0, 0, 637c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV, 4 638c965db44STomer Tayar }; 639c965db44STomer Tayar 640c965db44STomer Tayar static struct block_defs block_bmb_defs = { 641be086e7cSMintz, Yuval "bmb", 642da090917STomer Tayar {true, true, true}, false, 0, 643da090917STomer Tayar {DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCB, DBG_BUS_CLIENT_RBCB}, 644c965db44STomer Tayar BMB_REG_DBG_SELECT, BMB_REG_DBG_DWORD_ENABLE, 645c965db44STomer Tayar BMB_REG_DBG_SHIFT, BMB_REG_DBG_FORCE_VALID, 646c965db44STomer Tayar BMB_REG_DBG_FORCE_FRAME, 647c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_UA, 7 648c965db44STomer Tayar }; 649c965db44STomer Tayar 650c965db44STomer Tayar static struct block_defs block_pcie_defs = { 651be086e7cSMintz, Yuval "pcie", 652da090917STomer Tayar {true, true, true}, false, 0, 653da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH, 654da090917STomer Tayar DBG_BUS_CLIENT_RBCH}, 65521dd79e8STomer Tayar PCIE_REG_DBG_COMMON_SELECT_K2_E5, 65621dd79e8STomer Tayar PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5, 65721dd79e8STomer Tayar PCIE_REG_DBG_COMMON_SHIFT_K2_E5, 65821dd79e8STomer Tayar PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5, 65921dd79e8STomer Tayar PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5, 660c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 661c965db44STomer Tayar }; 662c965db44STomer Tayar 663c965db44STomer Tayar static struct block_defs block_mcp_defs = { 664da090917STomer Tayar "mcp", {true, true, true}, false, 0, 665da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 666c965db44STomer Tayar 0, 0, 0, 0, 0, 667c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 668c965db44STomer Tayar }; 669c965db44STomer Tayar 670c965db44STomer Tayar static struct block_defs block_mcp2_defs = { 671be086e7cSMintz, Yuval "mcp2", 672da090917STomer Tayar {true, true, true}, false, 0, 673da090917STomer Tayar {DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ}, 674c965db44STomer Tayar MCP2_REG_DBG_SELECT, MCP2_REG_DBG_DWORD_ENABLE, 675c965db44STomer Tayar MCP2_REG_DBG_SHIFT, MCP2_REG_DBG_FORCE_VALID, 676c965db44STomer Tayar MCP2_REG_DBG_FORCE_FRAME, 677c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 678c965db44STomer Tayar }; 679c965db44STomer Tayar 680c965db44STomer Tayar static struct block_defs block_pswhst_defs = { 681be086e7cSMintz, Yuval "pswhst", 682da090917STomer Tayar {true, true, true}, false, 0, 683da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 684c965db44STomer Tayar PSWHST_REG_DBG_SELECT, PSWHST_REG_DBG_DWORD_ENABLE, 685c965db44STomer Tayar PSWHST_REG_DBG_SHIFT, PSWHST_REG_DBG_FORCE_VALID, 686c965db44STomer Tayar PSWHST_REG_DBG_FORCE_FRAME, 687c965db44STomer Tayar true, false, DBG_RESET_REG_MISC_PL_HV, 0 688c965db44STomer Tayar }; 689c965db44STomer Tayar 690c965db44STomer Tayar static struct block_defs block_pswhst2_defs = { 691be086e7cSMintz, Yuval "pswhst2", 692da090917STomer Tayar {true, true, true}, false, 0, 693da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 694c965db44STomer Tayar PSWHST2_REG_DBG_SELECT, PSWHST2_REG_DBG_DWORD_ENABLE, 695c965db44STomer Tayar PSWHST2_REG_DBG_SHIFT, PSWHST2_REG_DBG_FORCE_VALID, 696c965db44STomer Tayar PSWHST2_REG_DBG_FORCE_FRAME, 697c965db44STomer Tayar true, false, DBG_RESET_REG_MISC_PL_HV, 0 698c965db44STomer Tayar }; 699c965db44STomer Tayar 700c965db44STomer Tayar static struct block_defs block_pswrd_defs = { 701be086e7cSMintz, Yuval "pswrd", 702da090917STomer Tayar {true, true, true}, false, 0, 703da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 704c965db44STomer Tayar PSWRD_REG_DBG_SELECT, PSWRD_REG_DBG_DWORD_ENABLE, 705c965db44STomer Tayar PSWRD_REG_DBG_SHIFT, PSWRD_REG_DBG_FORCE_VALID, 706c965db44STomer Tayar PSWRD_REG_DBG_FORCE_FRAME, 707c965db44STomer Tayar true, false, DBG_RESET_REG_MISC_PL_HV, 2 708c965db44STomer Tayar }; 709c965db44STomer Tayar 710c965db44STomer Tayar static struct block_defs block_pswrd2_defs = { 711be086e7cSMintz, Yuval "pswrd2", 712da090917STomer Tayar {true, true, true}, false, 0, 713da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 714c965db44STomer Tayar PSWRD2_REG_DBG_SELECT, PSWRD2_REG_DBG_DWORD_ENABLE, 715c965db44STomer Tayar PSWRD2_REG_DBG_SHIFT, PSWRD2_REG_DBG_FORCE_VALID, 716c965db44STomer Tayar PSWRD2_REG_DBG_FORCE_FRAME, 717c965db44STomer Tayar true, false, DBG_RESET_REG_MISC_PL_HV, 2 718c965db44STomer Tayar }; 719c965db44STomer Tayar 720c965db44STomer Tayar static struct block_defs block_pswwr_defs = { 721be086e7cSMintz, Yuval "pswwr", 722da090917STomer Tayar {true, true, true}, false, 0, 723da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 724c965db44STomer Tayar PSWWR_REG_DBG_SELECT, PSWWR_REG_DBG_DWORD_ENABLE, 725c965db44STomer Tayar PSWWR_REG_DBG_SHIFT, PSWWR_REG_DBG_FORCE_VALID, 726c965db44STomer Tayar PSWWR_REG_DBG_FORCE_FRAME, 727c965db44STomer Tayar true, false, DBG_RESET_REG_MISC_PL_HV, 3 728c965db44STomer Tayar }; 729c965db44STomer Tayar 730c965db44STomer Tayar static struct block_defs block_pswwr2_defs = { 731da090917STomer Tayar "pswwr2", {true, true, true}, false, 0, 732da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 733c965db44STomer Tayar 0, 0, 0, 0, 0, 734c965db44STomer Tayar true, false, DBG_RESET_REG_MISC_PL_HV, 3 735c965db44STomer Tayar }; 736c965db44STomer Tayar 737c965db44STomer Tayar static struct block_defs block_pswrq_defs = { 738be086e7cSMintz, Yuval "pswrq", 739da090917STomer Tayar {true, true, true}, false, 0, 740da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 741c965db44STomer Tayar PSWRQ_REG_DBG_SELECT, PSWRQ_REG_DBG_DWORD_ENABLE, 742c965db44STomer Tayar PSWRQ_REG_DBG_SHIFT, PSWRQ_REG_DBG_FORCE_VALID, 743c965db44STomer Tayar PSWRQ_REG_DBG_FORCE_FRAME, 744c965db44STomer Tayar true, false, DBG_RESET_REG_MISC_PL_HV, 1 745c965db44STomer Tayar }; 746c965db44STomer Tayar 747c965db44STomer Tayar static struct block_defs block_pswrq2_defs = { 748be086e7cSMintz, Yuval "pswrq2", 749da090917STomer Tayar {true, true, true}, false, 0, 750da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 751c965db44STomer Tayar PSWRQ2_REG_DBG_SELECT, PSWRQ2_REG_DBG_DWORD_ENABLE, 752c965db44STomer Tayar PSWRQ2_REG_DBG_SHIFT, PSWRQ2_REG_DBG_FORCE_VALID, 753c965db44STomer Tayar PSWRQ2_REG_DBG_FORCE_FRAME, 754c965db44STomer Tayar true, false, DBG_RESET_REG_MISC_PL_HV, 1 755c965db44STomer Tayar }; 756c965db44STomer Tayar 757c965db44STomer Tayar static struct block_defs block_pglcs_defs = { 758be086e7cSMintz, Yuval "pglcs", 759da090917STomer Tayar {true, true, true}, false, 0, 760da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH, 761da090917STomer Tayar DBG_BUS_CLIENT_RBCH}, 76221dd79e8STomer Tayar PGLCS_REG_DBG_SELECT_K2_E5, PGLCS_REG_DBG_DWORD_ENABLE_K2_E5, 76321dd79e8STomer Tayar PGLCS_REG_DBG_SHIFT_K2_E5, PGLCS_REG_DBG_FORCE_VALID_K2_E5, 76421dd79e8STomer Tayar PGLCS_REG_DBG_FORCE_FRAME_K2_E5, 765c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV, 2 766c965db44STomer Tayar }; 767c965db44STomer Tayar 768c965db44STomer Tayar static struct block_defs block_ptu_defs = { 769be086e7cSMintz, Yuval "ptu", 770da090917STomer Tayar {true, true, true}, false, 0, 771da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 772c965db44STomer Tayar PTU_REG_DBG_SELECT, PTU_REG_DBG_DWORD_ENABLE, 773c965db44STomer Tayar PTU_REG_DBG_SHIFT, PTU_REG_DBG_FORCE_VALID, 774c965db44STomer Tayar PTU_REG_DBG_FORCE_FRAME, 775c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 20 776c965db44STomer Tayar }; 777c965db44STomer Tayar 778c965db44STomer Tayar static struct block_defs block_dmae_defs = { 779be086e7cSMintz, Yuval "dmae", 780da090917STomer Tayar {true, true, true}, false, 0, 781da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 782c965db44STomer Tayar DMAE_REG_DBG_SELECT, DMAE_REG_DBG_DWORD_ENABLE, 783c965db44STomer Tayar DMAE_REG_DBG_SHIFT, DMAE_REG_DBG_FORCE_VALID, 784c965db44STomer Tayar DMAE_REG_DBG_FORCE_FRAME, 785c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 28 786c965db44STomer Tayar }; 787c965db44STomer Tayar 788c965db44STomer Tayar static struct block_defs block_tcm_defs = { 789be086e7cSMintz, Yuval "tcm", 790da090917STomer Tayar {true, true, true}, true, DBG_TSTORM_ID, 791da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT}, 792c965db44STomer Tayar TCM_REG_DBG_SELECT, TCM_REG_DBG_DWORD_ENABLE, 793c965db44STomer Tayar TCM_REG_DBG_SHIFT, TCM_REG_DBG_FORCE_VALID, 794c965db44STomer Tayar TCM_REG_DBG_FORCE_FRAME, 795c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 5 796c965db44STomer Tayar }; 797c965db44STomer Tayar 798c965db44STomer Tayar static struct block_defs block_mcm_defs = { 799be086e7cSMintz, Yuval "mcm", 800da090917STomer Tayar {true, true, true}, true, DBG_MSTORM_ID, 801da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM}, 802c965db44STomer Tayar MCM_REG_DBG_SELECT, MCM_REG_DBG_DWORD_ENABLE, 803c965db44STomer Tayar MCM_REG_DBG_SHIFT, MCM_REG_DBG_FORCE_VALID, 804c965db44STomer Tayar MCM_REG_DBG_FORCE_FRAME, 805c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 3 806c965db44STomer Tayar }; 807c965db44STomer Tayar 808c965db44STomer Tayar static struct block_defs block_ucm_defs = { 809be086e7cSMintz, Yuval "ucm", 810da090917STomer Tayar {true, true, true}, true, DBG_USTORM_ID, 811da090917STomer Tayar {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU}, 812c965db44STomer Tayar UCM_REG_DBG_SELECT, UCM_REG_DBG_DWORD_ENABLE, 813c965db44STomer Tayar UCM_REG_DBG_SHIFT, UCM_REG_DBG_FORCE_VALID, 814c965db44STomer Tayar UCM_REG_DBG_FORCE_FRAME, 815c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 8 816c965db44STomer Tayar }; 817c965db44STomer Tayar 818c965db44STomer Tayar static struct block_defs block_xcm_defs = { 819be086e7cSMintz, Yuval "xcm", 820da090917STomer Tayar {true, true, true}, true, DBG_XSTORM_ID, 821da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX}, 822c965db44STomer Tayar XCM_REG_DBG_SELECT, XCM_REG_DBG_DWORD_ENABLE, 823c965db44STomer Tayar XCM_REG_DBG_SHIFT, XCM_REG_DBG_FORCE_VALID, 824c965db44STomer Tayar XCM_REG_DBG_FORCE_FRAME, 825c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 19 826c965db44STomer Tayar }; 827c965db44STomer Tayar 828c965db44STomer Tayar static struct block_defs block_ycm_defs = { 829be086e7cSMintz, Yuval "ycm", 830da090917STomer Tayar {true, true, true}, true, DBG_YSTORM_ID, 831da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY}, 832c965db44STomer Tayar YCM_REG_DBG_SELECT, YCM_REG_DBG_DWORD_ENABLE, 833c965db44STomer Tayar YCM_REG_DBG_SHIFT, YCM_REG_DBG_FORCE_VALID, 834c965db44STomer Tayar YCM_REG_DBG_FORCE_FRAME, 835c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 5 836c965db44STomer Tayar }; 837c965db44STomer Tayar 838c965db44STomer Tayar static struct block_defs block_pcm_defs = { 839be086e7cSMintz, Yuval "pcm", 840da090917STomer Tayar {true, true, true}, true, DBG_PSTORM_ID, 841da090917STomer Tayar {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS}, 842c965db44STomer Tayar PCM_REG_DBG_SELECT, PCM_REG_DBG_DWORD_ENABLE, 843c965db44STomer Tayar PCM_REG_DBG_SHIFT, PCM_REG_DBG_FORCE_VALID, 844c965db44STomer Tayar PCM_REG_DBG_FORCE_FRAME, 845c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 4 846c965db44STomer Tayar }; 847c965db44STomer Tayar 848c965db44STomer Tayar static struct block_defs block_qm_defs = { 849be086e7cSMintz, Yuval "qm", 850da090917STomer Tayar {true, true, true}, false, 0, 851da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCQ, DBG_BUS_CLIENT_RBCQ}, 852c965db44STomer Tayar QM_REG_DBG_SELECT, QM_REG_DBG_DWORD_ENABLE, 853c965db44STomer Tayar QM_REG_DBG_SHIFT, QM_REG_DBG_FORCE_VALID, 854c965db44STomer Tayar QM_REG_DBG_FORCE_FRAME, 855c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 16 856c965db44STomer Tayar }; 857c965db44STomer Tayar 858c965db44STomer Tayar static struct block_defs block_tm_defs = { 859be086e7cSMintz, Yuval "tm", 860da090917STomer Tayar {true, true, true}, false, 0, 861da090917STomer Tayar {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS}, 862c965db44STomer Tayar TM_REG_DBG_SELECT, TM_REG_DBG_DWORD_ENABLE, 863c965db44STomer Tayar TM_REG_DBG_SHIFT, TM_REG_DBG_FORCE_VALID, 864c965db44STomer Tayar TM_REG_DBG_FORCE_FRAME, 865c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 17 866c965db44STomer Tayar }; 867c965db44STomer Tayar 868c965db44STomer Tayar static struct block_defs block_dorq_defs = { 869be086e7cSMintz, Yuval "dorq", 870da090917STomer Tayar {true, true, true}, false, 0, 871da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY}, 872c965db44STomer Tayar DORQ_REG_DBG_SELECT, DORQ_REG_DBG_DWORD_ENABLE, 873c965db44STomer Tayar DORQ_REG_DBG_SHIFT, DORQ_REG_DBG_FORCE_VALID, 874c965db44STomer Tayar DORQ_REG_DBG_FORCE_FRAME, 875c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 18 876c965db44STomer Tayar }; 877c965db44STomer Tayar 878c965db44STomer Tayar static struct block_defs block_brb_defs = { 879be086e7cSMintz, Yuval "brb", 880da090917STomer Tayar {true, true, true}, false, 0, 881da090917STomer Tayar {DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR}, 882c965db44STomer Tayar BRB_REG_DBG_SELECT, BRB_REG_DBG_DWORD_ENABLE, 883c965db44STomer Tayar BRB_REG_DBG_SHIFT, BRB_REG_DBG_FORCE_VALID, 884c965db44STomer Tayar BRB_REG_DBG_FORCE_FRAME, 885c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 0 886c965db44STomer Tayar }; 887c965db44STomer Tayar 888c965db44STomer Tayar static struct block_defs block_src_defs = { 889be086e7cSMintz, Yuval "src", 890da090917STomer Tayar {true, true, true}, false, 0, 891da090917STomer Tayar {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF}, 892c965db44STomer Tayar SRC_REG_DBG_SELECT, SRC_REG_DBG_DWORD_ENABLE, 893c965db44STomer Tayar SRC_REG_DBG_SHIFT, SRC_REG_DBG_FORCE_VALID, 894c965db44STomer Tayar SRC_REG_DBG_FORCE_FRAME, 895c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 2 896c965db44STomer Tayar }; 897c965db44STomer Tayar 898c965db44STomer Tayar static struct block_defs block_prs_defs = { 899be086e7cSMintz, Yuval "prs", 900da090917STomer Tayar {true, true, true}, false, 0, 901da090917STomer Tayar {DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR}, 902c965db44STomer Tayar PRS_REG_DBG_SELECT, PRS_REG_DBG_DWORD_ENABLE, 903c965db44STomer Tayar PRS_REG_DBG_SHIFT, PRS_REG_DBG_FORCE_VALID, 904c965db44STomer Tayar PRS_REG_DBG_FORCE_FRAME, 905c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 1 906c965db44STomer Tayar }; 907c965db44STomer Tayar 908c965db44STomer Tayar static struct block_defs block_tsdm_defs = { 909be086e7cSMintz, Yuval "tsdm", 910da090917STomer Tayar {true, true, true}, true, DBG_TSTORM_ID, 911da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT}, 912c965db44STomer Tayar TSDM_REG_DBG_SELECT, TSDM_REG_DBG_DWORD_ENABLE, 913c965db44STomer Tayar TSDM_REG_DBG_SHIFT, TSDM_REG_DBG_FORCE_VALID, 914c965db44STomer Tayar TSDM_REG_DBG_FORCE_FRAME, 915c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 3 916c965db44STomer Tayar }; 917c965db44STomer Tayar 918c965db44STomer Tayar static struct block_defs block_msdm_defs = { 919be086e7cSMintz, Yuval "msdm", 920da090917STomer Tayar {true, true, true}, true, DBG_MSTORM_ID, 921da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM}, 922c965db44STomer Tayar MSDM_REG_DBG_SELECT, MSDM_REG_DBG_DWORD_ENABLE, 923c965db44STomer Tayar MSDM_REG_DBG_SHIFT, MSDM_REG_DBG_FORCE_VALID, 924c965db44STomer Tayar MSDM_REG_DBG_FORCE_FRAME, 925c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 6 926c965db44STomer Tayar }; 927c965db44STomer Tayar 928c965db44STomer Tayar static struct block_defs block_usdm_defs = { 929be086e7cSMintz, Yuval "usdm", 930da090917STomer Tayar {true, true, true}, true, DBG_USTORM_ID, 931da090917STomer Tayar {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU}, 932c965db44STomer Tayar USDM_REG_DBG_SELECT, USDM_REG_DBG_DWORD_ENABLE, 933c965db44STomer Tayar USDM_REG_DBG_SHIFT, USDM_REG_DBG_FORCE_VALID, 934c965db44STomer Tayar USDM_REG_DBG_FORCE_FRAME, 935c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 7 936c965db44STomer Tayar }; 937c965db44STomer Tayar 938c965db44STomer Tayar static struct block_defs block_xsdm_defs = { 939be086e7cSMintz, Yuval "xsdm", 940da090917STomer Tayar {true, true, true}, true, DBG_XSTORM_ID, 941da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX}, 942c965db44STomer Tayar XSDM_REG_DBG_SELECT, XSDM_REG_DBG_DWORD_ENABLE, 943c965db44STomer Tayar XSDM_REG_DBG_SHIFT, XSDM_REG_DBG_FORCE_VALID, 944c965db44STomer Tayar XSDM_REG_DBG_FORCE_FRAME, 945c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 20 946c965db44STomer Tayar }; 947c965db44STomer Tayar 948c965db44STomer Tayar static struct block_defs block_ysdm_defs = { 949be086e7cSMintz, Yuval "ysdm", 950da090917STomer Tayar {true, true, true}, true, DBG_YSTORM_ID, 951da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY}, 952c965db44STomer Tayar YSDM_REG_DBG_SELECT, YSDM_REG_DBG_DWORD_ENABLE, 953c965db44STomer Tayar YSDM_REG_DBG_SHIFT, YSDM_REG_DBG_FORCE_VALID, 954c965db44STomer Tayar YSDM_REG_DBG_FORCE_FRAME, 955c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 8 956c965db44STomer Tayar }; 957c965db44STomer Tayar 958c965db44STomer Tayar static struct block_defs block_psdm_defs = { 959be086e7cSMintz, Yuval "psdm", 960da090917STomer Tayar {true, true, true}, true, DBG_PSTORM_ID, 961da090917STomer Tayar {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS}, 962c965db44STomer Tayar PSDM_REG_DBG_SELECT, PSDM_REG_DBG_DWORD_ENABLE, 963c965db44STomer Tayar PSDM_REG_DBG_SHIFT, PSDM_REG_DBG_FORCE_VALID, 964c965db44STomer Tayar PSDM_REG_DBG_FORCE_FRAME, 965c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 7 966c965db44STomer Tayar }; 967c965db44STomer Tayar 968c965db44STomer Tayar static struct block_defs block_tsem_defs = { 969be086e7cSMintz, Yuval "tsem", 970da090917STomer Tayar {true, true, true}, true, DBG_TSTORM_ID, 971da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT}, 972c965db44STomer Tayar TSEM_REG_DBG_SELECT, TSEM_REG_DBG_DWORD_ENABLE, 973c965db44STomer Tayar TSEM_REG_DBG_SHIFT, TSEM_REG_DBG_FORCE_VALID, 974c965db44STomer Tayar TSEM_REG_DBG_FORCE_FRAME, 975c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 4 976c965db44STomer Tayar }; 977c965db44STomer Tayar 978c965db44STomer Tayar static struct block_defs block_msem_defs = { 979be086e7cSMintz, Yuval "msem", 980da090917STomer Tayar {true, true, true}, true, DBG_MSTORM_ID, 981da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM}, 982c965db44STomer Tayar MSEM_REG_DBG_SELECT, MSEM_REG_DBG_DWORD_ENABLE, 983c965db44STomer Tayar MSEM_REG_DBG_SHIFT, MSEM_REG_DBG_FORCE_VALID, 984c965db44STomer Tayar MSEM_REG_DBG_FORCE_FRAME, 985c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 9 986c965db44STomer Tayar }; 987c965db44STomer Tayar 988c965db44STomer Tayar static struct block_defs block_usem_defs = { 989be086e7cSMintz, Yuval "usem", 990da090917STomer Tayar {true, true, true}, true, DBG_USTORM_ID, 991da090917STomer Tayar {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU}, 992c965db44STomer Tayar USEM_REG_DBG_SELECT, USEM_REG_DBG_DWORD_ENABLE, 993c965db44STomer Tayar USEM_REG_DBG_SHIFT, USEM_REG_DBG_FORCE_VALID, 994c965db44STomer Tayar USEM_REG_DBG_FORCE_FRAME, 995c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 9 996c965db44STomer Tayar }; 997c965db44STomer Tayar 998c965db44STomer Tayar static struct block_defs block_xsem_defs = { 999be086e7cSMintz, Yuval "xsem", 1000da090917STomer Tayar {true, true, true}, true, DBG_XSTORM_ID, 1001da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX}, 1002c965db44STomer Tayar XSEM_REG_DBG_SELECT, XSEM_REG_DBG_DWORD_ENABLE, 1003c965db44STomer Tayar XSEM_REG_DBG_SHIFT, XSEM_REG_DBG_FORCE_VALID, 1004c965db44STomer Tayar XSEM_REG_DBG_FORCE_FRAME, 1005c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 21 1006c965db44STomer Tayar }; 1007c965db44STomer Tayar 1008c965db44STomer Tayar static struct block_defs block_ysem_defs = { 1009be086e7cSMintz, Yuval "ysem", 1010da090917STomer Tayar {true, true, true}, true, DBG_YSTORM_ID, 1011da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY}, 1012c965db44STomer Tayar YSEM_REG_DBG_SELECT, YSEM_REG_DBG_DWORD_ENABLE, 1013c965db44STomer Tayar YSEM_REG_DBG_SHIFT, YSEM_REG_DBG_FORCE_VALID, 1014c965db44STomer Tayar YSEM_REG_DBG_FORCE_FRAME, 1015c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 11 1016c965db44STomer Tayar }; 1017c965db44STomer Tayar 1018c965db44STomer Tayar static struct block_defs block_psem_defs = { 1019be086e7cSMintz, Yuval "psem", 1020da090917STomer Tayar {true, true, true}, true, DBG_PSTORM_ID, 1021da090917STomer Tayar {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS}, 1022c965db44STomer Tayar PSEM_REG_DBG_SELECT, PSEM_REG_DBG_DWORD_ENABLE, 1023c965db44STomer Tayar PSEM_REG_DBG_SHIFT, PSEM_REG_DBG_FORCE_VALID, 1024c965db44STomer Tayar PSEM_REG_DBG_FORCE_FRAME, 1025c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 10 1026c965db44STomer Tayar }; 1027c965db44STomer Tayar 1028c965db44STomer Tayar static struct block_defs block_rss_defs = { 1029be086e7cSMintz, Yuval "rss", 1030da090917STomer Tayar {true, true, true}, false, 0, 1031da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT}, 1032c965db44STomer Tayar RSS_REG_DBG_SELECT, RSS_REG_DBG_DWORD_ENABLE, 1033c965db44STomer Tayar RSS_REG_DBG_SHIFT, RSS_REG_DBG_FORCE_VALID, 1034c965db44STomer Tayar RSS_REG_DBG_FORCE_FRAME, 1035c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 18 1036c965db44STomer Tayar }; 1037c965db44STomer Tayar 1038c965db44STomer Tayar static struct block_defs block_tmld_defs = { 1039be086e7cSMintz, Yuval "tmld", 1040da090917STomer Tayar {true, true, true}, false, 0, 1041da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM}, 1042c965db44STomer Tayar TMLD_REG_DBG_SELECT, TMLD_REG_DBG_DWORD_ENABLE, 1043c965db44STomer Tayar TMLD_REG_DBG_SHIFT, TMLD_REG_DBG_FORCE_VALID, 1044c965db44STomer Tayar TMLD_REG_DBG_FORCE_FRAME, 1045c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 13 1046c965db44STomer Tayar }; 1047c965db44STomer Tayar 1048c965db44STomer Tayar static struct block_defs block_muld_defs = { 1049be086e7cSMintz, Yuval "muld", 1050da090917STomer Tayar {true, true, true}, false, 0, 1051da090917STomer Tayar {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU}, 1052c965db44STomer Tayar MULD_REG_DBG_SELECT, MULD_REG_DBG_DWORD_ENABLE, 1053c965db44STomer Tayar MULD_REG_DBG_SHIFT, MULD_REG_DBG_FORCE_VALID, 1054c965db44STomer Tayar MULD_REG_DBG_FORCE_FRAME, 1055c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 14 1056c965db44STomer Tayar }; 1057c965db44STomer Tayar 1058c965db44STomer Tayar static struct block_defs block_yuld_defs = { 1059be086e7cSMintz, Yuval "yuld", 1060da090917STomer Tayar {true, true, false}, false, 0, 1061da090917STomer Tayar {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, 1062da090917STomer Tayar MAX_DBG_BUS_CLIENTS}, 10637b6859fbSMintz, Yuval YULD_REG_DBG_SELECT_BB_K2, YULD_REG_DBG_DWORD_ENABLE_BB_K2, 10647b6859fbSMintz, Yuval YULD_REG_DBG_SHIFT_BB_K2, YULD_REG_DBG_FORCE_VALID_BB_K2, 10657b6859fbSMintz, Yuval YULD_REG_DBG_FORCE_FRAME_BB_K2, 10667b6859fbSMintz, Yuval true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 10677b6859fbSMintz, Yuval 15 1068c965db44STomer Tayar }; 1069c965db44STomer Tayar 1070c965db44STomer Tayar static struct block_defs block_xyld_defs = { 1071be086e7cSMintz, Yuval "xyld", 1072da090917STomer Tayar {true, true, true}, false, 0, 1073da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX}, 1074c965db44STomer Tayar XYLD_REG_DBG_SELECT, XYLD_REG_DBG_DWORD_ENABLE, 1075c965db44STomer Tayar XYLD_REG_DBG_SHIFT, XYLD_REG_DBG_FORCE_VALID, 1076c965db44STomer Tayar XYLD_REG_DBG_FORCE_FRAME, 1077c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 12 1078c965db44STomer Tayar }; 1079c965db44STomer Tayar 1080a2e7699eSTomer Tayar static struct block_defs block_ptld_defs = { 1081da090917STomer Tayar "ptld", 1082da090917STomer Tayar {false, false, true}, false, 0, 1083da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCT}, 1084da090917STomer Tayar PTLD_REG_DBG_SELECT_E5, PTLD_REG_DBG_DWORD_ENABLE_E5, 1085da090917STomer Tayar PTLD_REG_DBG_SHIFT_E5, PTLD_REG_DBG_FORCE_VALID_E5, 1086da090917STomer Tayar PTLD_REG_DBG_FORCE_FRAME_E5, 1087da090917STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 1088da090917STomer Tayar 28 1089a2e7699eSTomer Tayar }; 1090a2e7699eSTomer Tayar 1091a2e7699eSTomer Tayar static struct block_defs block_ypld_defs = { 1092da090917STomer Tayar "ypld", 1093da090917STomer Tayar {false, false, true}, false, 0, 1094da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCS}, 1095da090917STomer Tayar YPLD_REG_DBG_SELECT_E5, YPLD_REG_DBG_DWORD_ENABLE_E5, 1096da090917STomer Tayar YPLD_REG_DBG_SHIFT_E5, YPLD_REG_DBG_FORCE_VALID_E5, 1097da090917STomer Tayar YPLD_REG_DBG_FORCE_FRAME_E5, 1098da090917STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 1099da090917STomer Tayar 27 1100a2e7699eSTomer Tayar }; 1101a2e7699eSTomer Tayar 1102c965db44STomer Tayar static struct block_defs block_prm_defs = { 1103be086e7cSMintz, Yuval "prm", 1104da090917STomer Tayar {true, true, true}, false, 0, 1105da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM}, 1106c965db44STomer Tayar PRM_REG_DBG_SELECT, PRM_REG_DBG_DWORD_ENABLE, 1107c965db44STomer Tayar PRM_REG_DBG_SHIFT, PRM_REG_DBG_FORCE_VALID, 1108c965db44STomer Tayar PRM_REG_DBG_FORCE_FRAME, 1109c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 21 1110c965db44STomer Tayar }; 1111c965db44STomer Tayar 1112c965db44STomer Tayar static struct block_defs block_pbf_pb1_defs = { 1113be086e7cSMintz, Yuval "pbf_pb1", 1114da090917STomer Tayar {true, true, true}, false, 0, 1115da090917STomer Tayar {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV}, 1116c965db44STomer Tayar PBF_PB1_REG_DBG_SELECT, PBF_PB1_REG_DBG_DWORD_ENABLE, 1117c965db44STomer Tayar PBF_PB1_REG_DBG_SHIFT, PBF_PB1_REG_DBG_FORCE_VALID, 1118c965db44STomer Tayar PBF_PB1_REG_DBG_FORCE_FRAME, 1119c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 1120c965db44STomer Tayar 11 1121c965db44STomer Tayar }; 1122c965db44STomer Tayar 1123c965db44STomer Tayar static struct block_defs block_pbf_pb2_defs = { 1124be086e7cSMintz, Yuval "pbf_pb2", 1125da090917STomer Tayar {true, true, true}, false, 0, 1126da090917STomer Tayar {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV}, 1127c965db44STomer Tayar PBF_PB2_REG_DBG_SELECT, PBF_PB2_REG_DBG_DWORD_ENABLE, 1128c965db44STomer Tayar PBF_PB2_REG_DBG_SHIFT, PBF_PB2_REG_DBG_FORCE_VALID, 1129c965db44STomer Tayar PBF_PB2_REG_DBG_FORCE_FRAME, 1130c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 1131c965db44STomer Tayar 12 1132c965db44STomer Tayar }; 1133c965db44STomer Tayar 1134c965db44STomer Tayar static struct block_defs block_rpb_defs = { 1135be086e7cSMintz, Yuval "rpb", 1136da090917STomer Tayar {true, true, true}, false, 0, 1137da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM}, 1138c965db44STomer Tayar RPB_REG_DBG_SELECT, RPB_REG_DBG_DWORD_ENABLE, 1139c965db44STomer Tayar RPB_REG_DBG_SHIFT, RPB_REG_DBG_FORCE_VALID, 1140c965db44STomer Tayar RPB_REG_DBG_FORCE_FRAME, 1141c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 13 1142c965db44STomer Tayar }; 1143c965db44STomer Tayar 1144c965db44STomer Tayar static struct block_defs block_btb_defs = { 1145be086e7cSMintz, Yuval "btb", 1146da090917STomer Tayar {true, true, true}, false, 0, 1147da090917STomer Tayar {DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV}, 1148c965db44STomer Tayar BTB_REG_DBG_SELECT, BTB_REG_DBG_DWORD_ENABLE, 1149c965db44STomer Tayar BTB_REG_DBG_SHIFT, BTB_REG_DBG_FORCE_VALID, 1150c965db44STomer Tayar BTB_REG_DBG_FORCE_FRAME, 1151c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 10 1152c965db44STomer Tayar }; 1153c965db44STomer Tayar 1154c965db44STomer Tayar static struct block_defs block_pbf_defs = { 1155be086e7cSMintz, Yuval "pbf", 1156da090917STomer Tayar {true, true, true}, false, 0, 1157da090917STomer Tayar {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV}, 1158c965db44STomer Tayar PBF_REG_DBG_SELECT, PBF_REG_DBG_DWORD_ENABLE, 1159c965db44STomer Tayar PBF_REG_DBG_SHIFT, PBF_REG_DBG_FORCE_VALID, 1160c965db44STomer Tayar PBF_REG_DBG_FORCE_FRAME, 1161c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 15 1162c965db44STomer Tayar }; 1163c965db44STomer Tayar 1164c965db44STomer Tayar static struct block_defs block_rdif_defs = { 1165be086e7cSMintz, Yuval "rdif", 1166da090917STomer Tayar {true, true, true}, false, 0, 1167da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM}, 1168c965db44STomer Tayar RDIF_REG_DBG_SELECT, RDIF_REG_DBG_DWORD_ENABLE, 1169c965db44STomer Tayar RDIF_REG_DBG_SHIFT, RDIF_REG_DBG_FORCE_VALID, 1170c965db44STomer Tayar RDIF_REG_DBG_FORCE_FRAME, 1171c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 16 1172c965db44STomer Tayar }; 1173c965db44STomer Tayar 1174c965db44STomer Tayar static struct block_defs block_tdif_defs = { 1175be086e7cSMintz, Yuval "tdif", 1176da090917STomer Tayar {true, true, true}, false, 0, 1177da090917STomer Tayar {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS}, 1178c965db44STomer Tayar TDIF_REG_DBG_SELECT, TDIF_REG_DBG_DWORD_ENABLE, 1179c965db44STomer Tayar TDIF_REG_DBG_SHIFT, TDIF_REG_DBG_FORCE_VALID, 1180c965db44STomer Tayar TDIF_REG_DBG_FORCE_FRAME, 1181c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 17 1182c965db44STomer Tayar }; 1183c965db44STomer Tayar 1184c965db44STomer Tayar static struct block_defs block_cdu_defs = { 1185be086e7cSMintz, Yuval "cdu", 1186da090917STomer Tayar {true, true, true}, false, 0, 1187da090917STomer Tayar {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF}, 1188c965db44STomer Tayar CDU_REG_DBG_SELECT, CDU_REG_DBG_DWORD_ENABLE, 1189c965db44STomer Tayar CDU_REG_DBG_SHIFT, CDU_REG_DBG_FORCE_VALID, 1190c965db44STomer Tayar CDU_REG_DBG_FORCE_FRAME, 1191c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 23 1192c965db44STomer Tayar }; 1193c965db44STomer Tayar 1194c965db44STomer Tayar static struct block_defs block_ccfc_defs = { 1195be086e7cSMintz, Yuval "ccfc", 1196da090917STomer Tayar {true, true, true}, false, 0, 1197da090917STomer Tayar {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF}, 1198c965db44STomer Tayar CCFC_REG_DBG_SELECT, CCFC_REG_DBG_DWORD_ENABLE, 1199c965db44STomer Tayar CCFC_REG_DBG_SHIFT, CCFC_REG_DBG_FORCE_VALID, 1200c965db44STomer Tayar CCFC_REG_DBG_FORCE_FRAME, 1201c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 24 1202c965db44STomer Tayar }; 1203c965db44STomer Tayar 1204c965db44STomer Tayar static struct block_defs block_tcfc_defs = { 1205be086e7cSMintz, Yuval "tcfc", 1206da090917STomer Tayar {true, true, true}, false, 0, 1207da090917STomer Tayar {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF}, 1208c965db44STomer Tayar TCFC_REG_DBG_SELECT, TCFC_REG_DBG_DWORD_ENABLE, 1209c965db44STomer Tayar TCFC_REG_DBG_SHIFT, TCFC_REG_DBG_FORCE_VALID, 1210c965db44STomer Tayar TCFC_REG_DBG_FORCE_FRAME, 1211c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 25 1212c965db44STomer Tayar }; 1213c965db44STomer Tayar 1214c965db44STomer Tayar static struct block_defs block_igu_defs = { 1215be086e7cSMintz, Yuval "igu", 1216da090917STomer Tayar {true, true, true}, false, 0, 1217da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 1218c965db44STomer Tayar IGU_REG_DBG_SELECT, IGU_REG_DBG_DWORD_ENABLE, 1219c965db44STomer Tayar IGU_REG_DBG_SHIFT, IGU_REG_DBG_FORCE_VALID, 1220c965db44STomer Tayar IGU_REG_DBG_FORCE_FRAME, 1221c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 27 1222c965db44STomer Tayar }; 1223c965db44STomer Tayar 1224c965db44STomer Tayar static struct block_defs block_cau_defs = { 1225be086e7cSMintz, Yuval "cau", 1226da090917STomer Tayar {true, true, true}, false, 0, 1227da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 1228c965db44STomer Tayar CAU_REG_DBG_SELECT, CAU_REG_DBG_DWORD_ENABLE, 1229c965db44STomer Tayar CAU_REG_DBG_SHIFT, CAU_REG_DBG_FORCE_VALID, 1230c965db44STomer Tayar CAU_REG_DBG_FORCE_FRAME, 1231c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 19 1232c965db44STomer Tayar }; 1233c965db44STomer Tayar 1234a2e7699eSTomer Tayar static struct block_defs block_rgfs_defs = { 1235da090917STomer Tayar "rgfs", {false, false, true}, false, 0, 1236da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1237a2e7699eSTomer Tayar 0, 0, 0, 0, 0, 1238da090917STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 29 1239a2e7699eSTomer Tayar }; 1240a2e7699eSTomer Tayar 1241a2e7699eSTomer Tayar static struct block_defs block_rgsrc_defs = { 1242da090917STomer Tayar "rgsrc", 1243da090917STomer Tayar {false, false, true}, false, 0, 1244da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH}, 1245da090917STomer Tayar RGSRC_REG_DBG_SELECT_E5, RGSRC_REG_DBG_DWORD_ENABLE_E5, 1246da090917STomer Tayar RGSRC_REG_DBG_SHIFT_E5, RGSRC_REG_DBG_FORCE_VALID_E5, 1247da090917STomer Tayar RGSRC_REG_DBG_FORCE_FRAME_E5, 1248da090917STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 1249da090917STomer Tayar 30 1250a2e7699eSTomer Tayar }; 1251a2e7699eSTomer Tayar 1252a2e7699eSTomer Tayar static struct block_defs block_tgfs_defs = { 1253da090917STomer Tayar "tgfs", {false, false, true}, false, 0, 1254da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1255a2e7699eSTomer Tayar 0, 0, 0, 0, 0, 1256da090917STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 30 1257a2e7699eSTomer Tayar }; 1258a2e7699eSTomer Tayar 1259a2e7699eSTomer Tayar static struct block_defs block_tgsrc_defs = { 1260da090917STomer Tayar "tgsrc", 1261da090917STomer Tayar {false, false, true}, false, 0, 1262da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCV}, 1263da090917STomer Tayar TGSRC_REG_DBG_SELECT_E5, TGSRC_REG_DBG_DWORD_ENABLE_E5, 1264da090917STomer Tayar TGSRC_REG_DBG_SHIFT_E5, TGSRC_REG_DBG_FORCE_VALID_E5, 1265da090917STomer Tayar TGSRC_REG_DBG_FORCE_FRAME_E5, 1266da090917STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 1267da090917STomer Tayar 31 1268a2e7699eSTomer Tayar }; 1269a2e7699eSTomer Tayar 1270c965db44STomer Tayar static struct block_defs block_umac_defs = { 1271be086e7cSMintz, Yuval "umac", 1272da090917STomer Tayar {true, true, true}, false, 0, 1273da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ, 1274da090917STomer Tayar DBG_BUS_CLIENT_RBCZ}, 127521dd79e8STomer Tayar UMAC_REG_DBG_SELECT_K2_E5, UMAC_REG_DBG_DWORD_ENABLE_K2_E5, 127621dd79e8STomer Tayar UMAC_REG_DBG_SHIFT_K2_E5, UMAC_REG_DBG_FORCE_VALID_K2_E5, 127721dd79e8STomer Tayar UMAC_REG_DBG_FORCE_FRAME_K2_E5, 1278c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV, 6 1279c965db44STomer Tayar }; 1280c965db44STomer Tayar 1281c965db44STomer Tayar static struct block_defs block_xmac_defs = { 1282da090917STomer Tayar "xmac", {true, false, false}, false, 0, 1283da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1284c965db44STomer Tayar 0, 0, 0, 0, 0, 1285c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 1286c965db44STomer Tayar }; 1287c965db44STomer Tayar 1288c965db44STomer Tayar static struct block_defs block_dbg_defs = { 1289da090917STomer Tayar "dbg", {true, true, true}, false, 0, 1290da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1291c965db44STomer Tayar 0, 0, 0, 0, 0, 1292c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 3 1293c965db44STomer Tayar }; 1294c965db44STomer Tayar 1295c965db44STomer Tayar static struct block_defs block_nig_defs = { 1296be086e7cSMintz, Yuval "nig", 1297da090917STomer Tayar {true, true, true}, false, 0, 1298da090917STomer Tayar {DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN}, 1299c965db44STomer Tayar NIG_REG_DBG_SELECT, NIG_REG_DBG_DWORD_ENABLE, 1300c965db44STomer Tayar NIG_REG_DBG_SHIFT, NIG_REG_DBG_FORCE_VALID, 1301c965db44STomer Tayar NIG_REG_DBG_FORCE_FRAME, 1302c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 0 1303c965db44STomer Tayar }; 1304c965db44STomer Tayar 1305c965db44STomer Tayar static struct block_defs block_wol_defs = { 1306be086e7cSMintz, Yuval "wol", 1307da090917STomer Tayar {false, true, true}, false, 0, 1308da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ}, 130921dd79e8STomer Tayar WOL_REG_DBG_SELECT_K2_E5, WOL_REG_DBG_DWORD_ENABLE_K2_E5, 131021dd79e8STomer Tayar WOL_REG_DBG_SHIFT_K2_E5, WOL_REG_DBG_FORCE_VALID_K2_E5, 131121dd79e8STomer Tayar WOL_REG_DBG_FORCE_FRAME_K2_E5, 1312c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 7 1313c965db44STomer Tayar }; 1314c965db44STomer Tayar 1315c965db44STomer Tayar static struct block_defs block_bmbn_defs = { 1316be086e7cSMintz, Yuval "bmbn", 1317da090917STomer Tayar {false, true, true}, false, 0, 1318da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCB, 1319da090917STomer Tayar DBG_BUS_CLIENT_RBCB}, 132021dd79e8STomer Tayar BMBN_REG_DBG_SELECT_K2_E5, BMBN_REG_DBG_DWORD_ENABLE_K2_E5, 132121dd79e8STomer Tayar BMBN_REG_DBG_SHIFT_K2_E5, BMBN_REG_DBG_FORCE_VALID_K2_E5, 132221dd79e8STomer Tayar BMBN_REG_DBG_FORCE_FRAME_K2_E5, 1323c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 1324c965db44STomer Tayar }; 1325c965db44STomer Tayar 1326c965db44STomer Tayar static struct block_defs block_ipc_defs = { 1327da090917STomer Tayar "ipc", {true, true, true}, false, 0, 1328da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1329c965db44STomer Tayar 0, 0, 0, 0, 0, 1330c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_UA, 8 1331c965db44STomer Tayar }; 1332c965db44STomer Tayar 1333c965db44STomer Tayar static struct block_defs block_nwm_defs = { 1334be086e7cSMintz, Yuval "nwm", 1335da090917STomer Tayar {false, true, true}, false, 0, 1336da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW, DBG_BUS_CLIENT_RBCW}, 133721dd79e8STomer Tayar NWM_REG_DBG_SELECT_K2_E5, NWM_REG_DBG_DWORD_ENABLE_K2_E5, 133821dd79e8STomer Tayar NWM_REG_DBG_SHIFT_K2_E5, NWM_REG_DBG_FORCE_VALID_K2_E5, 133921dd79e8STomer Tayar NWM_REG_DBG_FORCE_FRAME_K2_E5, 1340c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV_2, 0 1341c965db44STomer Tayar }; 1342c965db44STomer Tayar 1343c965db44STomer Tayar static struct block_defs block_nws_defs = { 1344be086e7cSMintz, Yuval "nws", 1345da090917STomer Tayar {false, true, true}, false, 0, 1346da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW, DBG_BUS_CLIENT_RBCW}, 134721dd79e8STomer Tayar NWS_REG_DBG_SELECT_K2_E5, NWS_REG_DBG_DWORD_ENABLE_K2_E5, 134821dd79e8STomer Tayar NWS_REG_DBG_SHIFT_K2_E5, NWS_REG_DBG_FORCE_VALID_K2_E5, 134921dd79e8STomer Tayar NWS_REG_DBG_FORCE_FRAME_K2_E5, 1350c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV, 12 1351c965db44STomer Tayar }; 1352c965db44STomer Tayar 1353c965db44STomer Tayar static struct block_defs block_ms_defs = { 1354be086e7cSMintz, Yuval "ms", 1355da090917STomer Tayar {false, true, true}, false, 0, 1356da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ}, 135721dd79e8STomer Tayar MS_REG_DBG_SELECT_K2_E5, MS_REG_DBG_DWORD_ENABLE_K2_E5, 135821dd79e8STomer Tayar MS_REG_DBG_SHIFT_K2_E5, MS_REG_DBG_FORCE_VALID_K2_E5, 135921dd79e8STomer Tayar MS_REG_DBG_FORCE_FRAME_K2_E5, 1360c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV, 13 1361c965db44STomer Tayar }; 1362c965db44STomer Tayar 1363c965db44STomer Tayar static struct block_defs block_phy_pcie_defs = { 1364be086e7cSMintz, Yuval "phy_pcie", 1365da090917STomer Tayar {false, true, true}, false, 0, 1366da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH, 1367da090917STomer Tayar DBG_BUS_CLIENT_RBCH}, 136821dd79e8STomer Tayar PCIE_REG_DBG_COMMON_SELECT_K2_E5, 136921dd79e8STomer Tayar PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5, 137021dd79e8STomer Tayar PCIE_REG_DBG_COMMON_SHIFT_K2_E5, 137121dd79e8STomer Tayar PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5, 137221dd79e8STomer Tayar PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5, 1373c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 1374c965db44STomer Tayar }; 1375c965db44STomer Tayar 1376c965db44STomer Tayar static struct block_defs block_led_defs = { 1377da090917STomer Tayar "led", {false, true, true}, false, 0, 1378da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1379c965db44STomer Tayar 0, 0, 0, 0, 0, 1380be086e7cSMintz, Yuval true, false, DBG_RESET_REG_MISCS_PL_HV, 14 1381be086e7cSMintz, Yuval }; 1382be086e7cSMintz, Yuval 1383be086e7cSMintz, Yuval static struct block_defs block_avs_wrap_defs = { 1384da090917STomer Tayar "avs_wrap", {false, true, false}, false, 0, 1385da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1386be086e7cSMintz, Yuval 0, 0, 0, 0, 0, 1387be086e7cSMintz, Yuval true, false, DBG_RESET_REG_MISCS_PL_UA, 11 1388be086e7cSMintz, Yuval }; 1389be086e7cSMintz, Yuval 1390da090917STomer Tayar static struct block_defs block_pxpreqbus_defs = { 1391da090917STomer Tayar "pxpreqbus", {false, false, false}, false, 0, 1392da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1393da090917STomer Tayar 0, 0, 0, 0, 0, 1394da090917STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 1395da090917STomer Tayar }; 1396da090917STomer Tayar 1397c965db44STomer Tayar static struct block_defs block_misc_aeu_defs = { 1398da090917STomer Tayar "misc_aeu", {true, true, true}, false, 0, 1399da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1400c965db44STomer Tayar 0, 0, 0, 0, 0, 1401c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 1402c965db44STomer Tayar }; 1403c965db44STomer Tayar 1404c965db44STomer Tayar static struct block_defs block_bar0_map_defs = { 1405da090917STomer Tayar "bar0_map", {true, true, true}, false, 0, 1406da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1407c965db44STomer Tayar 0, 0, 0, 0, 0, 1408c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 1409c965db44STomer Tayar }; 1410c965db44STomer Tayar 1411c965db44STomer Tayar static struct block_defs *s_block_defs[MAX_BLOCK_ID] = { 1412c965db44STomer Tayar &block_grc_defs, 1413c965db44STomer Tayar &block_miscs_defs, 1414c965db44STomer Tayar &block_misc_defs, 1415c965db44STomer Tayar &block_dbu_defs, 1416c965db44STomer Tayar &block_pglue_b_defs, 1417c965db44STomer Tayar &block_cnig_defs, 1418c965db44STomer Tayar &block_cpmu_defs, 1419c965db44STomer Tayar &block_ncsi_defs, 1420c965db44STomer Tayar &block_opte_defs, 1421c965db44STomer Tayar &block_bmb_defs, 1422c965db44STomer Tayar &block_pcie_defs, 1423c965db44STomer Tayar &block_mcp_defs, 1424c965db44STomer Tayar &block_mcp2_defs, 1425c965db44STomer Tayar &block_pswhst_defs, 1426c965db44STomer Tayar &block_pswhst2_defs, 1427c965db44STomer Tayar &block_pswrd_defs, 1428c965db44STomer Tayar &block_pswrd2_defs, 1429c965db44STomer Tayar &block_pswwr_defs, 1430c965db44STomer Tayar &block_pswwr2_defs, 1431c965db44STomer Tayar &block_pswrq_defs, 1432c965db44STomer Tayar &block_pswrq2_defs, 1433c965db44STomer Tayar &block_pglcs_defs, 1434c965db44STomer Tayar &block_dmae_defs, 1435c965db44STomer Tayar &block_ptu_defs, 1436c965db44STomer Tayar &block_tcm_defs, 1437c965db44STomer Tayar &block_mcm_defs, 1438c965db44STomer Tayar &block_ucm_defs, 1439c965db44STomer Tayar &block_xcm_defs, 1440c965db44STomer Tayar &block_ycm_defs, 1441c965db44STomer Tayar &block_pcm_defs, 1442c965db44STomer Tayar &block_qm_defs, 1443c965db44STomer Tayar &block_tm_defs, 1444c965db44STomer Tayar &block_dorq_defs, 1445c965db44STomer Tayar &block_brb_defs, 1446c965db44STomer Tayar &block_src_defs, 1447c965db44STomer Tayar &block_prs_defs, 1448c965db44STomer Tayar &block_tsdm_defs, 1449c965db44STomer Tayar &block_msdm_defs, 1450c965db44STomer Tayar &block_usdm_defs, 1451c965db44STomer Tayar &block_xsdm_defs, 1452c965db44STomer Tayar &block_ysdm_defs, 1453c965db44STomer Tayar &block_psdm_defs, 1454c965db44STomer Tayar &block_tsem_defs, 1455c965db44STomer Tayar &block_msem_defs, 1456c965db44STomer Tayar &block_usem_defs, 1457c965db44STomer Tayar &block_xsem_defs, 1458c965db44STomer Tayar &block_ysem_defs, 1459c965db44STomer Tayar &block_psem_defs, 1460c965db44STomer Tayar &block_rss_defs, 1461c965db44STomer Tayar &block_tmld_defs, 1462c965db44STomer Tayar &block_muld_defs, 1463c965db44STomer Tayar &block_yuld_defs, 1464c965db44STomer Tayar &block_xyld_defs, 14657b6859fbSMintz, Yuval &block_ptld_defs, 14667b6859fbSMintz, Yuval &block_ypld_defs, 1467c965db44STomer Tayar &block_prm_defs, 1468c965db44STomer Tayar &block_pbf_pb1_defs, 1469c965db44STomer Tayar &block_pbf_pb2_defs, 1470c965db44STomer Tayar &block_rpb_defs, 1471c965db44STomer Tayar &block_btb_defs, 1472c965db44STomer Tayar &block_pbf_defs, 1473c965db44STomer Tayar &block_rdif_defs, 1474c965db44STomer Tayar &block_tdif_defs, 1475c965db44STomer Tayar &block_cdu_defs, 1476c965db44STomer Tayar &block_ccfc_defs, 1477c965db44STomer Tayar &block_tcfc_defs, 1478c965db44STomer Tayar &block_igu_defs, 1479c965db44STomer Tayar &block_cau_defs, 14807b6859fbSMintz, Yuval &block_rgfs_defs, 14817b6859fbSMintz, Yuval &block_rgsrc_defs, 14827b6859fbSMintz, Yuval &block_tgfs_defs, 14837b6859fbSMintz, Yuval &block_tgsrc_defs, 1484c965db44STomer Tayar &block_umac_defs, 1485c965db44STomer Tayar &block_xmac_defs, 1486c965db44STomer Tayar &block_dbg_defs, 1487c965db44STomer Tayar &block_nig_defs, 1488c965db44STomer Tayar &block_wol_defs, 1489c965db44STomer Tayar &block_bmbn_defs, 1490c965db44STomer Tayar &block_ipc_defs, 1491c965db44STomer Tayar &block_nwm_defs, 1492c965db44STomer Tayar &block_nws_defs, 1493c965db44STomer Tayar &block_ms_defs, 1494c965db44STomer Tayar &block_phy_pcie_defs, 1495c965db44STomer Tayar &block_led_defs, 1496be086e7cSMintz, Yuval &block_avs_wrap_defs, 1497da090917STomer Tayar &block_pxpreqbus_defs, 1498c965db44STomer Tayar &block_misc_aeu_defs, 1499c965db44STomer Tayar &block_bar0_map_defs, 1500c965db44STomer Tayar }; 1501c965db44STomer Tayar 1502c965db44STomer Tayar static struct platform_defs s_platform_defs[] = { 1503da090917STomer Tayar {"asic", 1, 256, 32768}, 1504da090917STomer Tayar {"reserved", 0, 0, 0}, 1505da090917STomer Tayar {"reserved2", 0, 0, 0}, 1506da090917STomer Tayar {"reserved3", 0, 0, 0} 1507c965db44STomer Tayar }; 1508c965db44STomer Tayar 1509c965db44STomer Tayar static struct grc_param_defs s_grc_param_defs[] = { 15107b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_TSTORM */ 151150bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 1, 1}, 15127b6859fbSMintz, Yuval 15137b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_MSTORM */ 151450bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 1, 1}, 15157b6859fbSMintz, Yuval 15167b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_USTORM */ 151750bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 1, 1}, 15187b6859fbSMintz, Yuval 15197b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_XSTORM */ 152050bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 1, 1}, 15217b6859fbSMintz, Yuval 15227b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_YSTORM */ 152350bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 1, 1}, 15247b6859fbSMintz, Yuval 15257b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_PSTORM */ 152650bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 1, 1}, 15277b6859fbSMintz, Yuval 15287b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_REGS */ 152950bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15307b6859fbSMintz, Yuval 15317b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_RAM */ 153250bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15337b6859fbSMintz, Yuval 15347b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_PBUF */ 153550bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15367b6859fbSMintz, Yuval 15377b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_IOR */ 153850bc60cbSMichal Kalderon {{0, 0, 0}, 0, 1, false, false, 0, 1}, 15397b6859fbSMintz, Yuval 15407b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_VFC */ 154150bc60cbSMichal Kalderon {{0, 0, 0}, 0, 1, false, false, 0, 1}, 15427b6859fbSMintz, Yuval 15437b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_CM_CTX */ 154450bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15457b6859fbSMintz, Yuval 15467b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_ILT */ 154750bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15487b6859fbSMintz, Yuval 15497b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_RSS */ 155050bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15517b6859fbSMintz, Yuval 15527b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_CAU */ 155350bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15547b6859fbSMintz, Yuval 15557b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_QM */ 155650bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15577b6859fbSMintz, Yuval 15587b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_MCP */ 155950bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15607b6859fbSMintz, Yuval 156150bc60cbSMichal Kalderon /* DBG_GRC_PARAM_MCP_TRACE_META_SIZE */ 156250bc60cbSMichal Kalderon {{1, 1, 1}, 1, 0xffffffff, false, true, 0, 1}, 15637b6859fbSMintz, Yuval 15647b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_CFC */ 156550bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15667b6859fbSMintz, Yuval 15677b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_IGU */ 156850bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15697b6859fbSMintz, Yuval 15707b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_BRB */ 157150bc60cbSMichal Kalderon {{0, 0, 0}, 0, 1, false, false, 0, 1}, 15727b6859fbSMintz, Yuval 15737b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_BTB */ 157450bc60cbSMichal Kalderon {{0, 0, 0}, 0, 1, false, false, 0, 1}, 15757b6859fbSMintz, Yuval 15767b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_BMB */ 1577d52c89f1SMichal Kalderon {{0, 0, 0}, 0, 1, false, false, 0, 0}, 15787b6859fbSMintz, Yuval 15797b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_NIG */ 158050bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15817b6859fbSMintz, Yuval 15827b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_MULD */ 158350bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15847b6859fbSMintz, Yuval 15857b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_PRS */ 158650bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15877b6859fbSMintz, Yuval 15887b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_DMAE */ 158950bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15907b6859fbSMintz, Yuval 15917b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_TM */ 159250bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15937b6859fbSMintz, Yuval 15947b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_SDM */ 159550bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15967b6859fbSMintz, Yuval 15977b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_DIF */ 159850bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15997b6859fbSMintz, Yuval 16007b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_STATIC */ 160150bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 16027b6859fbSMintz, Yuval 16037b6859fbSMintz, Yuval /* DBG_GRC_PARAM_UNSTALL */ 160450bc60cbSMichal Kalderon {{0, 0, 0}, 0, 1, false, false, 0, 0}, 16057b6859fbSMintz, Yuval 16067b6859fbSMintz, Yuval /* DBG_GRC_PARAM_NUM_LCIDS */ 160750bc60cbSMichal Kalderon {{MAX_LCIDS, MAX_LCIDS, MAX_LCIDS}, 1, MAX_LCIDS, false, false, 160850bc60cbSMichal Kalderon MAX_LCIDS, MAX_LCIDS}, 16097b6859fbSMintz, Yuval 16107b6859fbSMintz, Yuval /* DBG_GRC_PARAM_NUM_LTIDS */ 161150bc60cbSMichal Kalderon {{MAX_LTIDS, MAX_LTIDS, MAX_LTIDS}, 1, MAX_LTIDS, false, false, 161250bc60cbSMichal Kalderon MAX_LTIDS, MAX_LTIDS}, 16137b6859fbSMintz, Yuval 16147b6859fbSMintz, Yuval /* DBG_GRC_PARAM_EXCLUDE_ALL */ 161550bc60cbSMichal Kalderon {{0, 0, 0}, 0, 1, true, false, 0, 0}, 16167b6859fbSMintz, Yuval 16177b6859fbSMintz, Yuval /* DBG_GRC_PARAM_CRASH */ 161850bc60cbSMichal Kalderon {{0, 0, 0}, 0, 1, true, false, 0, 0}, 16197b6859fbSMintz, Yuval 16207b6859fbSMintz, Yuval /* DBG_GRC_PARAM_PARITY_SAFE */ 162150bc60cbSMichal Kalderon {{0, 0, 0}, 0, 1, false, false, 1, 0}, 16227b6859fbSMintz, Yuval 16237b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_CM */ 162450bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 16257b6859fbSMintz, Yuval 16267b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_PHY */ 162750bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 16287b6859fbSMintz, Yuval 16297b6859fbSMintz, Yuval /* DBG_GRC_PARAM_NO_MCP */ 163050bc60cbSMichal Kalderon {{0, 0, 0}, 0, 1, false, false, 0, 0}, 16317b6859fbSMintz, Yuval 16327b6859fbSMintz, Yuval /* DBG_GRC_PARAM_NO_FW_VER */ 163350bc60cbSMichal Kalderon {{0, 0, 0}, 0, 1, false, false, 0, 0} 1634c965db44STomer Tayar }; 1635c965db44STomer Tayar 1636c965db44STomer Tayar static struct rss_mem_defs s_rss_mem_defs[] = { 1637da090917STomer Tayar { "rss_mem_cid", "rss_cid", 0, 32, 1638da090917STomer Tayar {256, 320, 512} }, 16397b6859fbSMintz, Yuval 1640da090917STomer Tayar { "rss_mem_key_msb", "rss_key", 1024, 256, 1641da090917STomer Tayar {128, 208, 257} }, 16427b6859fbSMintz, Yuval 1643da090917STomer Tayar { "rss_mem_key_lsb", "rss_key", 2048, 64, 1644da090917STomer Tayar {128, 208, 257} }, 16457b6859fbSMintz, Yuval 1646da090917STomer Tayar { "rss_mem_info", "rss_info", 3072, 16, 1647da090917STomer Tayar {128, 208, 256} }, 16487b6859fbSMintz, Yuval 1649da090917STomer Tayar { "rss_mem_ind", "rss_ind", 4096, 16, 1650da090917STomer Tayar {16384, 26624, 32768} } 1651c965db44STomer Tayar }; 1652c965db44STomer Tayar 1653c965db44STomer Tayar static struct vfc_ram_defs s_vfc_ram_defs[] = { 1654c965db44STomer Tayar {"vfc_ram_tt1", "vfc_ram", 0, 512}, 1655c965db44STomer Tayar {"vfc_ram_mtt2", "vfc_ram", 512, 128}, 1656c965db44STomer Tayar {"vfc_ram_stt2", "vfc_ram", 640, 32}, 1657c965db44STomer Tayar {"vfc_ram_ro_vect", "vfc_ram", 672, 32} 1658c965db44STomer Tayar }; 1659c965db44STomer Tayar 1660c965db44STomer Tayar static struct big_ram_defs s_big_ram_defs[] = { 1661c965db44STomer Tayar { "BRB", MEM_GROUP_BRB_MEM, MEM_GROUP_BRB_RAM, DBG_GRC_PARAM_DUMP_BRB, 1662c965db44STomer Tayar BRB_REG_BIG_RAM_ADDRESS, BRB_REG_BIG_RAM_DATA, 1663da090917STomer Tayar MISC_REG_BLOCK_256B_EN, {0, 0, 0}, 1664da090917STomer Tayar {153600, 180224, 282624} }, 16657b6859fbSMintz, Yuval 1666c965db44STomer Tayar { "BTB", MEM_GROUP_BTB_MEM, MEM_GROUP_BTB_RAM, DBG_GRC_PARAM_DUMP_BTB, 1667c965db44STomer Tayar BTB_REG_BIG_RAM_ADDRESS, BTB_REG_BIG_RAM_DATA, 1668da090917STomer Tayar MISC_REG_BLOCK_256B_EN, {0, 1, 1}, 1669da090917STomer Tayar {92160, 117760, 168960} }, 16707b6859fbSMintz, Yuval 1671c965db44STomer Tayar { "BMB", MEM_GROUP_BMB_MEM, MEM_GROUP_BMB_RAM, DBG_GRC_PARAM_DUMP_BMB, 1672c965db44STomer Tayar BMB_REG_BIG_RAM_ADDRESS, BMB_REG_BIG_RAM_DATA, 1673da090917STomer Tayar MISCS_REG_BLOCK_256B_EN, {0, 0, 0}, 1674da090917STomer Tayar {36864, 36864, 36864} } 1675c965db44STomer Tayar }; 1676c965db44STomer Tayar 1677c965db44STomer Tayar static struct reset_reg_defs s_reset_regs_defs[] = { 16787b6859fbSMintz, Yuval /* DBG_RESET_REG_MISCS_PL_UA */ 1679da090917STomer Tayar { MISCS_REG_RESET_PL_UA, 1680da090917STomer Tayar {true, true, true}, {0x0, 0x0, 0x0} }, 16817b6859fbSMintz, Yuval 16827b6859fbSMintz, Yuval /* DBG_RESET_REG_MISCS_PL_HV */ 1683da090917STomer Tayar { MISCS_REG_RESET_PL_HV, 1684da090917STomer Tayar {true, true, true}, {0x0, 0x400, 0x600} }, 16857b6859fbSMintz, Yuval 16867b6859fbSMintz, Yuval /* DBG_RESET_REG_MISCS_PL_HV_2 */ 1687da090917STomer Tayar { MISCS_REG_RESET_PL_HV_2_K2_E5, 1688da090917STomer Tayar {false, true, true}, {0x0, 0x0, 0x0} }, 16897b6859fbSMintz, Yuval 16907b6859fbSMintz, Yuval /* DBG_RESET_REG_MISC_PL_UA */ 1691da090917STomer Tayar { MISC_REG_RESET_PL_UA, 1692da090917STomer Tayar {true, true, true}, {0x0, 0x0, 0x0} }, 16937b6859fbSMintz, Yuval 16947b6859fbSMintz, Yuval /* DBG_RESET_REG_MISC_PL_HV */ 1695da090917STomer Tayar { MISC_REG_RESET_PL_HV, 1696da090917STomer Tayar {true, true, true}, {0x0, 0x0, 0x0} }, 16977b6859fbSMintz, Yuval 16987b6859fbSMintz, Yuval /* DBG_RESET_REG_MISC_PL_PDA_VMAIN_1 */ 1699da090917STomer Tayar { MISC_REG_RESET_PL_PDA_VMAIN_1, 1700da090917STomer Tayar {true, true, true}, {0x4404040, 0x4404040, 0x404040} }, 17017b6859fbSMintz, Yuval 17027b6859fbSMintz, Yuval /* DBG_RESET_REG_MISC_PL_PDA_VMAIN_2 */ 1703da090917STomer Tayar { MISC_REG_RESET_PL_PDA_VMAIN_2, 1704da090917STomer Tayar {true, true, true}, {0x7, 0x7c00007, 0x5c08007} }, 17057b6859fbSMintz, Yuval 17067b6859fbSMintz, Yuval /* DBG_RESET_REG_MISC_PL_PDA_VAUX */ 1707da090917STomer Tayar { MISC_REG_RESET_PL_PDA_VAUX, 1708da090917STomer Tayar {true, true, true}, {0x2, 0x2, 0x2} }, 1709c965db44STomer Tayar }; 1710c965db44STomer Tayar 1711c965db44STomer Tayar static struct phy_defs s_phy_defs[] = { 17127b6859fbSMintz, Yuval {"nw_phy", NWS_REG_NWS_CMU_K2, 171321dd79e8STomer Tayar PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2_E5, 171421dd79e8STomer Tayar PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2_E5, 171521dd79e8STomer Tayar PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2_E5, 171621dd79e8STomer Tayar PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2_E5}, 171721dd79e8STomer Tayar {"sgmii_phy", MS_REG_MS_CMU_K2_E5, 171821dd79e8STomer Tayar PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2_E5, 171921dd79e8STomer Tayar PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2_E5, 172021dd79e8STomer Tayar PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2_E5, 172121dd79e8STomer Tayar PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2_E5}, 172221dd79e8STomer Tayar {"pcie_phy0", PHY_PCIE_REG_PHY0_K2_E5, 172321dd79e8STomer Tayar PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5, 172421dd79e8STomer Tayar PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5, 172521dd79e8STomer Tayar PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5, 172621dd79e8STomer Tayar PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5}, 172721dd79e8STomer Tayar {"pcie_phy1", PHY_PCIE_REG_PHY1_K2_E5, 172821dd79e8STomer Tayar PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5, 172921dd79e8STomer Tayar PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5, 173021dd79e8STomer Tayar PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5, 173121dd79e8STomer Tayar PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5}, 1732c965db44STomer Tayar }; 1733c965db44STomer Tayar 1734d52c89f1SMichal Kalderon static struct split_type_defs s_split_type_defs[] = { 1735d52c89f1SMichal Kalderon /* SPLIT_TYPE_NONE */ 1736d52c89f1SMichal Kalderon {"eng"}, 1737d52c89f1SMichal Kalderon 1738d52c89f1SMichal Kalderon /* SPLIT_TYPE_PORT */ 1739d52c89f1SMichal Kalderon {"port"}, 1740d52c89f1SMichal Kalderon 1741d52c89f1SMichal Kalderon /* SPLIT_TYPE_PF */ 1742d52c89f1SMichal Kalderon {"pf"}, 1743d52c89f1SMichal Kalderon 1744d52c89f1SMichal Kalderon /* SPLIT_TYPE_PORT_PF */ 1745d52c89f1SMichal Kalderon {"port"}, 1746d52c89f1SMichal Kalderon 1747d52c89f1SMichal Kalderon /* SPLIT_TYPE_VF */ 1748d52c89f1SMichal Kalderon {"vf"} 1749d52c89f1SMichal Kalderon }; 1750d52c89f1SMichal Kalderon 1751c965db44STomer Tayar /**************************** Private Functions ******************************/ 1752c965db44STomer Tayar 1753c965db44STomer Tayar /* Reads and returns a single dword from the specified unaligned buffer */ 1754c965db44STomer Tayar static u32 qed_read_unaligned_dword(u8 *buf) 1755c965db44STomer Tayar { 1756c965db44STomer Tayar u32 dword; 1757c965db44STomer Tayar 1758c965db44STomer Tayar memcpy((u8 *)&dword, buf, sizeof(dword)); 1759c965db44STomer Tayar return dword; 1760c965db44STomer Tayar } 1761c965db44STomer Tayar 1762be086e7cSMintz, Yuval /* Returns the value of the specified GRC param */ 1763be086e7cSMintz, Yuval static u32 qed_grc_get_param(struct qed_hwfn *p_hwfn, 1764be086e7cSMintz, Yuval enum dbg_grc_params grc_param) 1765be086e7cSMintz, Yuval { 1766be086e7cSMintz, Yuval struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 1767be086e7cSMintz, Yuval 1768be086e7cSMintz, Yuval return dev_data->grc.param_val[grc_param]; 1769be086e7cSMintz, Yuval } 1770be086e7cSMintz, Yuval 1771be086e7cSMintz, Yuval /* Initializes the GRC parameters */ 1772be086e7cSMintz, Yuval static void qed_dbg_grc_init_params(struct qed_hwfn *p_hwfn) 1773be086e7cSMintz, Yuval { 1774be086e7cSMintz, Yuval struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 1775be086e7cSMintz, Yuval 1776be086e7cSMintz, Yuval if (!dev_data->grc.params_initialized) { 1777be086e7cSMintz, Yuval qed_dbg_grc_set_params_default(p_hwfn); 1778be086e7cSMintz, Yuval dev_data->grc.params_initialized = 1; 1779be086e7cSMintz, Yuval } 1780be086e7cSMintz, Yuval } 1781be086e7cSMintz, Yuval 1782c965db44STomer Tayar /* Initializes debug data for the specified device */ 1783c965db44STomer Tayar static enum dbg_status qed_dbg_dev_init(struct qed_hwfn *p_hwfn, 1784c965db44STomer Tayar struct qed_ptt *p_ptt) 1785c965db44STomer Tayar { 1786c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 1787d52c89f1SMichal Kalderon u8 num_pfs = 0, max_pfs_per_port = 0; 1788c965db44STomer Tayar 1789c965db44STomer Tayar if (dev_data->initialized) 1790c965db44STomer Tayar return DBG_STATUS_OK; 1791c965db44STomer Tayar 1792d52c89f1SMichal Kalderon /* Set chip */ 1793c965db44STomer Tayar if (QED_IS_K2(p_hwfn->cdev)) { 1794c965db44STomer Tayar dev_data->chip_id = CHIP_K2; 1795c965db44STomer Tayar dev_data->mode_enable[MODE_K2] = 1; 1796d52c89f1SMichal Kalderon dev_data->num_vfs = MAX_NUM_VFS_K2; 1797d52c89f1SMichal Kalderon num_pfs = MAX_NUM_PFS_K2; 1798d52c89f1SMichal Kalderon max_pfs_per_port = MAX_NUM_PFS_K2 / 2; 1799c965db44STomer Tayar } else if (QED_IS_BB_B0(p_hwfn->cdev)) { 18007b6859fbSMintz, Yuval dev_data->chip_id = CHIP_BB; 18019c79ddaaSMintz, Yuval dev_data->mode_enable[MODE_BB] = 1; 1802d52c89f1SMichal Kalderon dev_data->num_vfs = MAX_NUM_VFS_BB; 1803d52c89f1SMichal Kalderon num_pfs = MAX_NUM_PFS_BB; 1804d52c89f1SMichal Kalderon max_pfs_per_port = MAX_NUM_PFS_BB; 1805c965db44STomer Tayar } else { 1806c965db44STomer Tayar return DBG_STATUS_UNKNOWN_CHIP; 1807c965db44STomer Tayar } 1808c965db44STomer Tayar 1809d52c89f1SMichal Kalderon /* Set platofrm */ 1810c965db44STomer Tayar dev_data->platform_id = PLATFORM_ASIC; 1811c965db44STomer Tayar dev_data->mode_enable[MODE_ASIC] = 1; 1812be086e7cSMintz, Yuval 1813d52c89f1SMichal Kalderon /* Set port mode */ 1814d52c89f1SMichal Kalderon switch (qed_rd(p_hwfn, p_ptt, MISC_REG_PORT_MODE)) { 1815d52c89f1SMichal Kalderon case 0: 1816d52c89f1SMichal Kalderon dev_data->mode_enable[MODE_PORTS_PER_ENG_1] = 1; 1817d52c89f1SMichal Kalderon break; 1818d52c89f1SMichal Kalderon case 1: 1819d52c89f1SMichal Kalderon dev_data->mode_enable[MODE_PORTS_PER_ENG_2] = 1; 1820d52c89f1SMichal Kalderon break; 1821d52c89f1SMichal Kalderon case 2: 1822d52c89f1SMichal Kalderon dev_data->mode_enable[MODE_PORTS_PER_ENG_4] = 1; 1823d52c89f1SMichal Kalderon break; 1824d52c89f1SMichal Kalderon } 1825d52c89f1SMichal Kalderon 1826d52c89f1SMichal Kalderon /* Set 100G mode */ 1827d52c89f1SMichal Kalderon if (dev_data->chip_id == CHIP_BB && 1828d52c89f1SMichal Kalderon qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB) == 2) 1829d52c89f1SMichal Kalderon dev_data->mode_enable[MODE_100G] = 1; 1830d52c89f1SMichal Kalderon 1831d52c89f1SMichal Kalderon /* Set number of ports */ 1832d52c89f1SMichal Kalderon if (dev_data->mode_enable[MODE_PORTS_PER_ENG_1] || 1833d52c89f1SMichal Kalderon dev_data->mode_enable[MODE_100G]) 1834d52c89f1SMichal Kalderon dev_data->num_ports = 1; 1835d52c89f1SMichal Kalderon else if (dev_data->mode_enable[MODE_PORTS_PER_ENG_2]) 1836d52c89f1SMichal Kalderon dev_data->num_ports = 2; 1837d52c89f1SMichal Kalderon else if (dev_data->mode_enable[MODE_PORTS_PER_ENG_4]) 1838d52c89f1SMichal Kalderon dev_data->num_ports = 4; 1839d52c89f1SMichal Kalderon 1840d52c89f1SMichal Kalderon /* Set number of PFs per port */ 1841d52c89f1SMichal Kalderon dev_data->num_pfs_per_port = min_t(u32, 1842d52c89f1SMichal Kalderon num_pfs / dev_data->num_ports, 1843d52c89f1SMichal Kalderon max_pfs_per_port); 1844d52c89f1SMichal Kalderon 1845be086e7cSMintz, Yuval /* Initializes the GRC parameters */ 1846be086e7cSMintz, Yuval qed_dbg_grc_init_params(p_hwfn); 1847be086e7cSMintz, Yuval 1848da090917STomer Tayar dev_data->use_dmae = true; 1849da090917STomer Tayar dev_data->initialized = 1; 18507b6859fbSMintz, Yuval 1851c965db44STomer Tayar return DBG_STATUS_OK; 1852c965db44STomer Tayar } 1853c965db44STomer Tayar 18547b6859fbSMintz, Yuval static struct dbg_bus_block *get_dbg_bus_block_desc(struct qed_hwfn *p_hwfn, 18557b6859fbSMintz, Yuval enum block_id block_id) 18567b6859fbSMintz, Yuval { 18577b6859fbSMintz, Yuval struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 18587b6859fbSMintz, Yuval 18597b6859fbSMintz, Yuval return (struct dbg_bus_block *)&dbg_bus_blocks[block_id * 18607b6859fbSMintz, Yuval MAX_CHIP_IDS + 18617b6859fbSMintz, Yuval dev_data->chip_id]; 18627b6859fbSMintz, Yuval } 18637b6859fbSMintz, Yuval 1864c965db44STomer Tayar /* Reads the FW info structure for the specified Storm from the chip, 1865c965db44STomer Tayar * and writes it to the specified fw_info pointer. 1866c965db44STomer Tayar */ 1867d52c89f1SMichal Kalderon static void qed_read_storm_fw_info(struct qed_hwfn *p_hwfn, 1868c965db44STomer Tayar struct qed_ptt *p_ptt, 1869c965db44STomer Tayar u8 storm_id, struct fw_info *fw_info) 1870c965db44STomer Tayar { 18717b6859fbSMintz, Yuval struct storm_defs *storm = &s_storm_defs[storm_id]; 1872c965db44STomer Tayar struct fw_info_location fw_info_location; 18737b6859fbSMintz, Yuval u32 addr, i, *dest; 1874c965db44STomer Tayar 1875c965db44STomer Tayar memset(&fw_info_location, 0, sizeof(fw_info_location)); 1876c965db44STomer Tayar memset(fw_info, 0, sizeof(*fw_info)); 18777b6859fbSMintz, Yuval 18787b6859fbSMintz, Yuval /* Read first the address that points to fw_info location. 18797b6859fbSMintz, Yuval * The address is located in the last line of the Storm RAM. 18807b6859fbSMintz, Yuval */ 18817b6859fbSMintz, Yuval addr = storm->sem_fast_mem_addr + SEM_FAST_REG_INT_RAM + 188221dd79e8STomer Tayar DWORDS_TO_BYTES(SEM_FAST_REG_INT_RAM_SIZE_BB_K2) - 18837b6859fbSMintz, Yuval sizeof(fw_info_location); 18847b6859fbSMintz, Yuval dest = (u32 *)&fw_info_location; 18857b6859fbSMintz, Yuval 1886c965db44STomer Tayar for (i = 0; i < BYTES_TO_DWORDS(sizeof(fw_info_location)); 1887c965db44STomer Tayar i++, addr += BYTES_IN_DWORD) 1888c965db44STomer Tayar dest[i] = qed_rd(p_hwfn, p_ptt, addr); 18897b6859fbSMintz, Yuval 18907b6859fbSMintz, Yuval /* Read FW version info from Storm RAM */ 1891c965db44STomer Tayar if (fw_info_location.size > 0 && fw_info_location.size <= 1892c965db44STomer Tayar sizeof(*fw_info)) { 1893c965db44STomer Tayar addr = fw_info_location.grc_addr; 1894c965db44STomer Tayar dest = (u32 *)fw_info; 1895c965db44STomer Tayar for (i = 0; i < BYTES_TO_DWORDS(fw_info_location.size); 1896c965db44STomer Tayar i++, addr += BYTES_IN_DWORD) 1897c965db44STomer Tayar dest[i] = qed_rd(p_hwfn, p_ptt, addr); 1898c965db44STomer Tayar } 1899c965db44STomer Tayar } 1900c965db44STomer Tayar 19017b6859fbSMintz, Yuval /* Dumps the specified string to the specified buffer. 19027b6859fbSMintz, Yuval * Returns the dumped size in bytes. 1903c965db44STomer Tayar */ 1904c965db44STomer Tayar static u32 qed_dump_str(char *dump_buf, bool dump, const char *str) 1905c965db44STomer Tayar { 1906c965db44STomer Tayar if (dump) 1907c965db44STomer Tayar strcpy(dump_buf, str); 19087b6859fbSMintz, Yuval 1909c965db44STomer Tayar return (u32)strlen(str) + 1; 1910c965db44STomer Tayar } 1911c965db44STomer Tayar 19127b6859fbSMintz, Yuval /* Dumps zeros to align the specified buffer to dwords. 19137b6859fbSMintz, Yuval * Returns the dumped size in bytes. 1914c965db44STomer Tayar */ 1915c965db44STomer Tayar static u32 qed_dump_align(char *dump_buf, bool dump, u32 byte_offset) 1916c965db44STomer Tayar { 19177b6859fbSMintz, Yuval u8 offset_in_dword, align_size; 1918c965db44STomer Tayar 19197b6859fbSMintz, Yuval offset_in_dword = (u8)(byte_offset & 0x3); 1920c965db44STomer Tayar align_size = offset_in_dword ? BYTES_IN_DWORD - offset_in_dword : 0; 1921c965db44STomer Tayar 1922c965db44STomer Tayar if (dump && align_size) 1923c965db44STomer Tayar memset(dump_buf, 0, align_size); 19247b6859fbSMintz, Yuval 1925c965db44STomer Tayar return align_size; 1926c965db44STomer Tayar } 1927c965db44STomer Tayar 1928c965db44STomer Tayar /* Writes the specified string param to the specified buffer. 1929c965db44STomer Tayar * Returns the dumped size in dwords. 1930c965db44STomer Tayar */ 1931c965db44STomer Tayar static u32 qed_dump_str_param(u32 *dump_buf, 1932c965db44STomer Tayar bool dump, 1933c965db44STomer Tayar const char *param_name, const char *param_val) 1934c965db44STomer Tayar { 1935c965db44STomer Tayar char *char_buf = (char *)dump_buf; 1936c965db44STomer Tayar u32 offset = 0; 1937c965db44STomer Tayar 1938c965db44STomer Tayar /* Dump param name */ 1939c965db44STomer Tayar offset += qed_dump_str(char_buf + offset, dump, param_name); 1940c965db44STomer Tayar 1941c965db44STomer Tayar /* Indicate a string param value */ 1942c965db44STomer Tayar if (dump) 1943c965db44STomer Tayar *(char_buf + offset) = 1; 1944c965db44STomer Tayar offset++; 1945c965db44STomer Tayar 1946c965db44STomer Tayar /* Dump param value */ 1947c965db44STomer Tayar offset += qed_dump_str(char_buf + offset, dump, param_val); 1948c965db44STomer Tayar 1949c965db44STomer Tayar /* Align buffer to next dword */ 1950c965db44STomer Tayar offset += qed_dump_align(char_buf + offset, dump, offset); 19517b6859fbSMintz, Yuval 1952c965db44STomer Tayar return BYTES_TO_DWORDS(offset); 1953c965db44STomer Tayar } 1954c965db44STomer Tayar 1955c965db44STomer Tayar /* Writes the specified numeric param to the specified buffer. 1956c965db44STomer Tayar * Returns the dumped size in dwords. 1957c965db44STomer Tayar */ 1958c965db44STomer Tayar static u32 qed_dump_num_param(u32 *dump_buf, 1959c965db44STomer Tayar bool dump, const char *param_name, u32 param_val) 1960c965db44STomer Tayar { 1961c965db44STomer Tayar char *char_buf = (char *)dump_buf; 1962c965db44STomer Tayar u32 offset = 0; 1963c965db44STomer Tayar 1964c965db44STomer Tayar /* Dump param name */ 1965c965db44STomer Tayar offset += qed_dump_str(char_buf + offset, dump, param_name); 1966c965db44STomer Tayar 1967c965db44STomer Tayar /* Indicate a numeric param value */ 1968c965db44STomer Tayar if (dump) 1969c965db44STomer Tayar *(char_buf + offset) = 0; 1970c965db44STomer Tayar offset++; 1971c965db44STomer Tayar 1972c965db44STomer Tayar /* Align buffer to next dword */ 1973c965db44STomer Tayar offset += qed_dump_align(char_buf + offset, dump, offset); 1974c965db44STomer Tayar 1975c965db44STomer Tayar /* Dump param value (and change offset from bytes to dwords) */ 1976c965db44STomer Tayar offset = BYTES_TO_DWORDS(offset); 1977c965db44STomer Tayar if (dump) 1978c965db44STomer Tayar *(dump_buf + offset) = param_val; 1979c965db44STomer Tayar offset++; 19807b6859fbSMintz, Yuval 1981c965db44STomer Tayar return offset; 1982c965db44STomer Tayar } 1983c965db44STomer Tayar 1984c965db44STomer Tayar /* Reads the FW version and writes it as a param to the specified buffer. 1985c965db44STomer Tayar * Returns the dumped size in dwords. 1986c965db44STomer Tayar */ 1987c965db44STomer Tayar static u32 qed_dump_fw_ver_param(struct qed_hwfn *p_hwfn, 1988c965db44STomer Tayar struct qed_ptt *p_ptt, 1989c965db44STomer Tayar u32 *dump_buf, bool dump) 1990c965db44STomer Tayar { 1991c965db44STomer Tayar char fw_ver_str[16] = EMPTY_FW_VERSION_STR; 1992c965db44STomer Tayar char fw_img_str[16] = EMPTY_FW_IMAGE_STR; 1993c965db44STomer Tayar struct fw_info fw_info = { {0}, {0} }; 1994c965db44STomer Tayar u32 offset = 0; 1995c965db44STomer Tayar 1996be086e7cSMintz, Yuval if (dump && !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_FW_VER)) { 1997d52c89f1SMichal Kalderon /* Read FW info from chip */ 1998d52c89f1SMichal Kalderon qed_read_fw_info(p_hwfn, p_ptt, &fw_info); 1999c965db44STomer Tayar 2000c965db44STomer Tayar /* Create FW version/image strings */ 20017b6859fbSMintz, Yuval if (snprintf(fw_ver_str, sizeof(fw_ver_str), 20027b6859fbSMintz, Yuval "%d_%d_%d_%d", fw_info.ver.num.major, 20037b6859fbSMintz, Yuval fw_info.ver.num.minor, fw_info.ver.num.rev, 20047b6859fbSMintz, Yuval fw_info.ver.num.eng) < 0) 2005c965db44STomer Tayar DP_NOTICE(p_hwfn, 2006c965db44STomer Tayar "Unexpected debug error: invalid FW version string\n"); 2007c965db44STomer Tayar switch (fw_info.ver.image_id) { 2008c965db44STomer Tayar case FW_IMG_MAIN: 2009c965db44STomer Tayar strcpy(fw_img_str, "main"); 2010c965db44STomer Tayar break; 2011c965db44STomer Tayar default: 2012c965db44STomer Tayar strcpy(fw_img_str, "unknown"); 2013c965db44STomer Tayar break; 2014c965db44STomer Tayar } 2015c965db44STomer Tayar } 2016c965db44STomer Tayar 2017c965db44STomer Tayar /* Dump FW version, image and timestamp */ 2018c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 2019c965db44STomer Tayar dump, "fw-version", fw_ver_str); 2020c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 2021c965db44STomer Tayar dump, "fw-image", fw_img_str); 2022c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 2023c965db44STomer Tayar dump, 2024c965db44STomer Tayar "fw-timestamp", fw_info.ver.timestamp); 20257b6859fbSMintz, Yuval 2026c965db44STomer Tayar return offset; 2027c965db44STomer Tayar } 2028c965db44STomer Tayar 2029c965db44STomer Tayar /* Reads the MFW version and writes it as a param to the specified buffer. 2030c965db44STomer Tayar * Returns the dumped size in dwords. 2031c965db44STomer Tayar */ 2032c965db44STomer Tayar static u32 qed_dump_mfw_ver_param(struct qed_hwfn *p_hwfn, 2033c965db44STomer Tayar struct qed_ptt *p_ptt, 2034c965db44STomer Tayar u32 *dump_buf, bool dump) 2035c965db44STomer Tayar { 2036c965db44STomer Tayar char mfw_ver_str[16] = EMPTY_FW_VERSION_STR; 2037c965db44STomer Tayar 20387b6859fbSMintz, Yuval if (dump && 20397b6859fbSMintz, Yuval !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_FW_VER)) { 2040c965db44STomer Tayar u32 global_section_offsize, global_section_addr, mfw_ver; 2041c965db44STomer Tayar u32 public_data_addr, global_section_offsize_addr; 2042c965db44STomer Tayar 20437b6859fbSMintz, Yuval /* Find MCP public data GRC address. Needs to be ORed with 20447b6859fbSMintz, Yuval * MCP_REG_SCRATCH due to a HW bug. 2045c965db44STomer Tayar */ 20467b6859fbSMintz, Yuval public_data_addr = qed_rd(p_hwfn, 20477b6859fbSMintz, Yuval p_ptt, 2048c965db44STomer Tayar MISC_REG_SHARED_MEM_ADDR) | 2049c965db44STomer Tayar MCP_REG_SCRATCH; 2050c965db44STomer Tayar 2051c965db44STomer Tayar /* Find MCP public global section offset */ 2052c965db44STomer Tayar global_section_offsize_addr = public_data_addr + 2053c965db44STomer Tayar offsetof(struct mcp_public_data, 2054c965db44STomer Tayar sections) + 2055c965db44STomer Tayar sizeof(offsize_t) * PUBLIC_GLOBAL; 2056c965db44STomer Tayar global_section_offsize = qed_rd(p_hwfn, p_ptt, 2057c965db44STomer Tayar global_section_offsize_addr); 20587b6859fbSMintz, Yuval global_section_addr = 20597b6859fbSMintz, Yuval MCP_REG_SCRATCH + 20607b6859fbSMintz, Yuval (global_section_offsize & OFFSIZE_OFFSET_MASK) * 4; 2061c965db44STomer Tayar 2062c965db44STomer Tayar /* Read MFW version from MCP public global section */ 2063c965db44STomer Tayar mfw_ver = qed_rd(p_hwfn, p_ptt, 2064c965db44STomer Tayar global_section_addr + 2065c965db44STomer Tayar offsetof(struct public_global, mfw_ver)); 2066c965db44STomer Tayar 2067c965db44STomer Tayar /* Dump MFW version param */ 20687b6859fbSMintz, Yuval if (snprintf(mfw_ver_str, sizeof(mfw_ver_str), "%d_%d_%d_%d", 20697b6859fbSMintz, Yuval (u8)(mfw_ver >> 24), (u8)(mfw_ver >> 16), 20707b6859fbSMintz, Yuval (u8)(mfw_ver >> 8), (u8)mfw_ver) < 0) 2071c965db44STomer Tayar DP_NOTICE(p_hwfn, 2072c965db44STomer Tayar "Unexpected debug error: invalid MFW version string\n"); 2073c965db44STomer Tayar } 2074c965db44STomer Tayar 2075c965db44STomer Tayar return qed_dump_str_param(dump_buf, dump, "mfw-version", mfw_ver_str); 2076c965db44STomer Tayar } 2077c965db44STomer Tayar 2078c965db44STomer Tayar /* Writes a section header to the specified buffer. 2079c965db44STomer Tayar * Returns the dumped size in dwords. 2080c965db44STomer Tayar */ 2081c965db44STomer Tayar static u32 qed_dump_section_hdr(u32 *dump_buf, 2082c965db44STomer Tayar bool dump, const char *name, u32 num_params) 2083c965db44STomer Tayar { 2084c965db44STomer Tayar return qed_dump_num_param(dump_buf, dump, name, num_params); 2085c965db44STomer Tayar } 2086c965db44STomer Tayar 2087c965db44STomer Tayar /* Writes the common global params to the specified buffer. 2088c965db44STomer Tayar * Returns the dumped size in dwords. 2089c965db44STomer Tayar */ 2090c965db44STomer Tayar static u32 qed_dump_common_global_params(struct qed_hwfn *p_hwfn, 2091c965db44STomer Tayar struct qed_ptt *p_ptt, 2092c965db44STomer Tayar u32 *dump_buf, 2093c965db44STomer Tayar bool dump, 2094c965db44STomer Tayar u8 num_specific_global_params) 2095c965db44STomer Tayar { 2096c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2097c965db44STomer Tayar u32 offset = 0; 20987b6859fbSMintz, Yuval u8 num_params; 2099c965db44STomer Tayar 21007b6859fbSMintz, Yuval /* Dump global params section header */ 21017b6859fbSMintz, Yuval num_params = NUM_COMMON_GLOBAL_PARAMS + num_specific_global_params; 2102c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, 2103be086e7cSMintz, Yuval dump, "global_params", num_params); 2104c965db44STomer Tayar 2105c965db44STomer Tayar /* Store params */ 2106c965db44STomer Tayar offset += qed_dump_fw_ver_param(p_hwfn, p_ptt, dump_buf + offset, dump); 2107c965db44STomer Tayar offset += qed_dump_mfw_ver_param(p_hwfn, 2108c965db44STomer Tayar p_ptt, dump_buf + offset, dump); 2109c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 2110c965db44STomer Tayar dump, "tools-version", TOOLS_VERSION); 2111c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 2112c965db44STomer Tayar dump, 2113c965db44STomer Tayar "chip", 2114c965db44STomer Tayar s_chip_defs[dev_data->chip_id].name); 2115c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 2116c965db44STomer Tayar dump, 2117c965db44STomer Tayar "platform", 2118c965db44STomer Tayar s_platform_defs[dev_data->platform_id]. 2119c965db44STomer Tayar name); 2120c965db44STomer Tayar offset += 2121c965db44STomer Tayar qed_dump_num_param(dump_buf + offset, dump, "pci-func", 2122c965db44STomer Tayar p_hwfn->abs_pf_id); 21237b6859fbSMintz, Yuval 2124c965db44STomer Tayar return offset; 2125c965db44STomer Tayar } 2126c965db44STomer Tayar 21277b6859fbSMintz, Yuval /* Writes the "last" section (including CRC) to the specified buffer at the 21287b6859fbSMintz, Yuval * given offset. Returns the dumped size in dwords. 2129c965db44STomer Tayar */ 2130da090917STomer Tayar static u32 qed_dump_last_section(u32 *dump_buf, u32 offset, bool dump) 2131c965db44STomer Tayar { 21327b6859fbSMintz, Yuval u32 start_offset = offset; 2133c965db44STomer Tayar 2134c965db44STomer Tayar /* Dump CRC section header */ 2135c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, dump, "last", 0); 2136c965db44STomer Tayar 21377b6859fbSMintz, Yuval /* Calculate CRC32 and add it to the dword after the "last" section */ 2138c965db44STomer Tayar if (dump) 21397b6859fbSMintz, Yuval *(dump_buf + offset) = ~crc32(0xffffffff, 21407b6859fbSMintz, Yuval (u8 *)dump_buf, 2141c965db44STomer Tayar DWORDS_TO_BYTES(offset)); 21427b6859fbSMintz, Yuval 2143c965db44STomer Tayar offset++; 21447b6859fbSMintz, Yuval 2145c965db44STomer Tayar return offset - start_offset; 2146c965db44STomer Tayar } 2147c965db44STomer Tayar 2148c965db44STomer Tayar /* Update blocks reset state */ 2149c965db44STomer Tayar static void qed_update_blocks_reset_state(struct qed_hwfn *p_hwfn, 2150c965db44STomer Tayar struct qed_ptt *p_ptt) 2151c965db44STomer Tayar { 2152c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2153c965db44STomer Tayar u32 reg_val[MAX_DBG_RESET_REGS] = { 0 }; 2154c965db44STomer Tayar u32 i; 2155c965db44STomer Tayar 2156c965db44STomer Tayar /* Read reset registers */ 2157c965db44STomer Tayar for (i = 0; i < MAX_DBG_RESET_REGS; i++) 2158c965db44STomer Tayar if (s_reset_regs_defs[i].exists[dev_data->chip_id]) 2159c965db44STomer Tayar reg_val[i] = qed_rd(p_hwfn, 2160c965db44STomer Tayar p_ptt, s_reset_regs_defs[i].addr); 2161c965db44STomer Tayar 2162c965db44STomer Tayar /* Check if blocks are in reset */ 21637b6859fbSMintz, Yuval for (i = 0; i < MAX_BLOCK_ID; i++) { 21647b6859fbSMintz, Yuval struct block_defs *block = s_block_defs[i]; 21657b6859fbSMintz, Yuval 21667b6859fbSMintz, Yuval dev_data->block_in_reset[i] = block->has_reset_bit && 21677b6859fbSMintz, Yuval !(reg_val[block->reset_reg] & BIT(block->reset_bit_offset)); 21687b6859fbSMintz, Yuval } 2169c965db44STomer Tayar } 2170c965db44STomer Tayar 2171c965db44STomer Tayar /* Enable / disable the Debug block */ 2172c965db44STomer Tayar static void qed_bus_enable_dbg_block(struct qed_hwfn *p_hwfn, 2173c965db44STomer Tayar struct qed_ptt *p_ptt, bool enable) 2174c965db44STomer Tayar { 2175c965db44STomer Tayar qed_wr(p_hwfn, p_ptt, DBG_REG_DBG_BLOCK_ON, enable ? 1 : 0); 2176c965db44STomer Tayar } 2177c965db44STomer Tayar 2178c965db44STomer Tayar /* Resets the Debug block */ 2179c965db44STomer Tayar static void qed_bus_reset_dbg_block(struct qed_hwfn *p_hwfn, 2180c965db44STomer Tayar struct qed_ptt *p_ptt) 2181c965db44STomer Tayar { 2182c965db44STomer Tayar u32 dbg_reset_reg_addr, old_reset_reg_val, new_reset_reg_val; 21837b6859fbSMintz, Yuval struct block_defs *dbg_block = s_block_defs[BLOCK_DBG]; 2184c965db44STomer Tayar 21857b6859fbSMintz, Yuval dbg_reset_reg_addr = s_reset_regs_defs[dbg_block->reset_reg].addr; 2186c965db44STomer Tayar old_reset_reg_val = qed_rd(p_hwfn, p_ptt, dbg_reset_reg_addr); 21877b6859fbSMintz, Yuval new_reset_reg_val = 21887b6859fbSMintz, Yuval old_reset_reg_val & ~BIT(dbg_block->reset_bit_offset); 2189c965db44STomer Tayar 2190c965db44STomer Tayar qed_wr(p_hwfn, p_ptt, dbg_reset_reg_addr, new_reset_reg_val); 2191c965db44STomer Tayar qed_wr(p_hwfn, p_ptt, dbg_reset_reg_addr, old_reset_reg_val); 2192c965db44STomer Tayar } 2193c965db44STomer Tayar 2194c965db44STomer Tayar static void qed_bus_set_framing_mode(struct qed_hwfn *p_hwfn, 2195c965db44STomer Tayar struct qed_ptt *p_ptt, 2196c965db44STomer Tayar enum dbg_bus_frame_modes mode) 2197c965db44STomer Tayar { 2198c965db44STomer Tayar qed_wr(p_hwfn, p_ptt, DBG_REG_FRAMING_MODE, (u8)mode); 2199c965db44STomer Tayar } 2200c965db44STomer Tayar 22017b6859fbSMintz, Yuval /* Enable / disable Debug Bus clients according to the specified mask 22027b6859fbSMintz, Yuval * (1 = enable, 0 = disable). 2203c965db44STomer Tayar */ 2204c965db44STomer Tayar static void qed_bus_enable_clients(struct qed_hwfn *p_hwfn, 2205c965db44STomer Tayar struct qed_ptt *p_ptt, u32 client_mask) 2206c965db44STomer Tayar { 2207c965db44STomer Tayar qed_wr(p_hwfn, p_ptt, DBG_REG_CLIENT_ENABLE, client_mask); 2208c965db44STomer Tayar } 2209c965db44STomer Tayar 2210c965db44STomer Tayar static bool qed_is_mode_match(struct qed_hwfn *p_hwfn, u16 *modes_buf_offset) 2211c965db44STomer Tayar { 2212c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2213c965db44STomer Tayar bool arg1, arg2; 22147b6859fbSMintz, Yuval const u32 *ptr; 22157b6859fbSMintz, Yuval u8 tree_val; 22167b6859fbSMintz, Yuval 22177b6859fbSMintz, Yuval /* Get next element from modes tree buffer */ 22187b6859fbSMintz, Yuval ptr = s_dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr; 22197b6859fbSMintz, Yuval tree_val = ((u8 *)ptr)[(*modes_buf_offset)++]; 2220c965db44STomer Tayar 2221c965db44STomer Tayar switch (tree_val) { 2222c965db44STomer Tayar case INIT_MODE_OP_NOT: 2223c965db44STomer Tayar return !qed_is_mode_match(p_hwfn, modes_buf_offset); 2224c965db44STomer Tayar case INIT_MODE_OP_OR: 2225c965db44STomer Tayar case INIT_MODE_OP_AND: 2226c965db44STomer Tayar arg1 = qed_is_mode_match(p_hwfn, modes_buf_offset); 2227c965db44STomer Tayar arg2 = qed_is_mode_match(p_hwfn, modes_buf_offset); 2228c965db44STomer Tayar return (tree_val == INIT_MODE_OP_OR) ? (arg1 || 2229c965db44STomer Tayar arg2) : (arg1 && arg2); 2230c965db44STomer Tayar default: 2231c965db44STomer Tayar return dev_data->mode_enable[tree_val - MAX_INIT_MODE_OPS] > 0; 2232c965db44STomer Tayar } 2233c965db44STomer Tayar } 2234c965db44STomer Tayar 2235c965db44STomer Tayar /* Returns true if the specified entity (indicated by GRC param) should be 2236c965db44STomer Tayar * included in the dump, false otherwise. 2237c965db44STomer Tayar */ 2238c965db44STomer Tayar static bool qed_grc_is_included(struct qed_hwfn *p_hwfn, 2239c965db44STomer Tayar enum dbg_grc_params grc_param) 2240c965db44STomer Tayar { 2241c965db44STomer Tayar return qed_grc_get_param(p_hwfn, grc_param) > 0; 2242c965db44STomer Tayar } 2243c965db44STomer Tayar 2244c965db44STomer Tayar /* Returns true of the specified Storm should be included in the dump, false 2245c965db44STomer Tayar * otherwise. 2246c965db44STomer Tayar */ 2247c965db44STomer Tayar static bool qed_grc_is_storm_included(struct qed_hwfn *p_hwfn, 2248c965db44STomer Tayar enum dbg_storms storm) 2249c965db44STomer Tayar { 2250c965db44STomer Tayar return qed_grc_get_param(p_hwfn, (enum dbg_grc_params)storm) > 0; 2251c965db44STomer Tayar } 2252c965db44STomer Tayar 2253c965db44STomer Tayar /* Returns true if the specified memory should be included in the dump, false 2254c965db44STomer Tayar * otherwise. 2255c965db44STomer Tayar */ 2256c965db44STomer Tayar static bool qed_grc_is_mem_included(struct qed_hwfn *p_hwfn, 2257c965db44STomer Tayar enum block_id block_id, u8 mem_group_id) 2258c965db44STomer Tayar { 22597b6859fbSMintz, Yuval struct block_defs *block = s_block_defs[block_id]; 2260c965db44STomer Tayar u8 i; 2261c965db44STomer Tayar 2262c965db44STomer Tayar /* Check Storm match */ 22637b6859fbSMintz, Yuval if (block->associated_to_storm && 2264c965db44STomer Tayar !qed_grc_is_storm_included(p_hwfn, 22657b6859fbSMintz, Yuval (enum dbg_storms)block->storm_id)) 2266c965db44STomer Tayar return false; 2267c965db44STomer Tayar 22687b6859fbSMintz, Yuval for (i = 0; i < NUM_BIG_RAM_TYPES; i++) { 22697b6859fbSMintz, Yuval struct big_ram_defs *big_ram = &s_big_ram_defs[i]; 2270c965db44STomer Tayar 22717b6859fbSMintz, Yuval if (mem_group_id == big_ram->mem_group_id || 22727b6859fbSMintz, Yuval mem_group_id == big_ram->ram_mem_group_id) 22737b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, big_ram->grc_param); 22747b6859fbSMintz, Yuval } 22757b6859fbSMintz, Yuval 22767b6859fbSMintz, Yuval switch (mem_group_id) { 22777b6859fbSMintz, Yuval case MEM_GROUP_PXP_ILT: 22787b6859fbSMintz, Yuval case MEM_GROUP_PXP_MEM: 22797b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_PXP); 22807b6859fbSMintz, Yuval case MEM_GROUP_RAM: 22817b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_RAM); 22827b6859fbSMintz, Yuval case MEM_GROUP_PBUF: 22837b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_PBUF); 22847b6859fbSMintz, Yuval case MEM_GROUP_CAU_MEM: 22857b6859fbSMintz, Yuval case MEM_GROUP_CAU_SB: 22867b6859fbSMintz, Yuval case MEM_GROUP_CAU_PI: 22877b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CAU); 22887b6859fbSMintz, Yuval case MEM_GROUP_QM_MEM: 22897b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_QM); 22907b6859fbSMintz, Yuval case MEM_GROUP_CFC_MEM: 22917b6859fbSMintz, Yuval case MEM_GROUP_CONN_CFC_MEM: 22927b6859fbSMintz, Yuval case MEM_GROUP_TASK_CFC_MEM: 2293da090917STomer Tayar return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CFC) || 2294da090917STomer Tayar qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CM_CTX); 22957b6859fbSMintz, Yuval case MEM_GROUP_IGU_MEM: 22967b6859fbSMintz, Yuval case MEM_GROUP_IGU_MSIX: 22977b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_IGU); 22987b6859fbSMintz, Yuval case MEM_GROUP_MULD_MEM: 22997b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_MULD); 23007b6859fbSMintz, Yuval case MEM_GROUP_PRS_MEM: 23017b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_PRS); 23027b6859fbSMintz, Yuval case MEM_GROUP_DMAE_MEM: 23037b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_DMAE); 23047b6859fbSMintz, Yuval case MEM_GROUP_TM_MEM: 23057b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_TM); 23067b6859fbSMintz, Yuval case MEM_GROUP_SDM_MEM: 23077b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_SDM); 23087b6859fbSMintz, Yuval case MEM_GROUP_TDIF_CTX: 23097b6859fbSMintz, Yuval case MEM_GROUP_RDIF_CTX: 23107b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_DIF); 23117b6859fbSMintz, Yuval case MEM_GROUP_CM_MEM: 23127b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CM); 23137b6859fbSMintz, Yuval case MEM_GROUP_IOR: 23147b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_IOR); 23157b6859fbSMintz, Yuval default: 2316c965db44STomer Tayar return true; 2317c965db44STomer Tayar } 23187b6859fbSMintz, Yuval } 2319c965db44STomer Tayar 2320c965db44STomer Tayar /* Stalls all Storms */ 2321c965db44STomer Tayar static void qed_grc_stall_storms(struct qed_hwfn *p_hwfn, 2322c965db44STomer Tayar struct qed_ptt *p_ptt, bool stall) 2323c965db44STomer Tayar { 23247b6859fbSMintz, Yuval u32 reg_addr; 2325c965db44STomer Tayar u8 storm_id; 2326c965db44STomer Tayar 2327c965db44STomer Tayar for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 23287b6859fbSMintz, Yuval if (!qed_grc_is_storm_included(p_hwfn, 23297b6859fbSMintz, Yuval (enum dbg_storms)storm_id)) 23307b6859fbSMintz, Yuval continue; 2331c965db44STomer Tayar 23327b6859fbSMintz, Yuval reg_addr = s_storm_defs[storm_id].sem_fast_mem_addr + 23337b6859fbSMintz, Yuval SEM_FAST_REG_STALL_0_BB_K2; 23347b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, reg_addr, stall ? 1 : 0); 2335c965db44STomer Tayar } 2336c965db44STomer Tayar 2337c965db44STomer Tayar msleep(STALL_DELAY_MS); 2338c965db44STomer Tayar } 2339c965db44STomer Tayar 2340c965db44STomer Tayar /* Takes all blocks out of reset */ 2341c965db44STomer Tayar static void qed_grc_unreset_blocks(struct qed_hwfn *p_hwfn, 2342c965db44STomer Tayar struct qed_ptt *p_ptt) 2343c965db44STomer Tayar { 2344c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2345c965db44STomer Tayar u32 reg_val[MAX_DBG_RESET_REGS] = { 0 }; 23467b6859fbSMintz, Yuval u32 block_id, i; 2347c965db44STomer Tayar 2348c965db44STomer Tayar /* Fill reset regs values */ 23497b6859fbSMintz, Yuval for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) { 23507b6859fbSMintz, Yuval struct block_defs *block = s_block_defs[block_id]; 23517b6859fbSMintz, Yuval 2352da090917STomer Tayar if (block->exists[dev_data->chip_id] && block->has_reset_bit && 2353da090917STomer Tayar block->unreset) 23547b6859fbSMintz, Yuval reg_val[block->reset_reg] |= 23557b6859fbSMintz, Yuval BIT(block->reset_bit_offset); 23567b6859fbSMintz, Yuval } 2357c965db44STomer Tayar 2358c965db44STomer Tayar /* Write reset registers */ 2359c965db44STomer Tayar for (i = 0; i < MAX_DBG_RESET_REGS; i++) { 23607b6859fbSMintz, Yuval if (!s_reset_regs_defs[i].exists[dev_data->chip_id]) 23617b6859fbSMintz, Yuval continue; 23627b6859fbSMintz, Yuval 2363da090917STomer Tayar reg_val[i] |= 2364da090917STomer Tayar s_reset_regs_defs[i].unreset_val[dev_data->chip_id]; 23657b6859fbSMintz, Yuval 2366c965db44STomer Tayar if (reg_val[i]) 2367c965db44STomer Tayar qed_wr(p_hwfn, 2368c965db44STomer Tayar p_ptt, 2369c965db44STomer Tayar s_reset_regs_defs[i].addr + 2370c965db44STomer Tayar RESET_REG_UNRESET_OFFSET, reg_val[i]); 2371c965db44STomer Tayar } 2372c965db44STomer Tayar } 2373c965db44STomer Tayar 2374be086e7cSMintz, Yuval /* Returns the attention block data of the specified block */ 2375c965db44STomer Tayar static const struct dbg_attn_block_type_data * 2376c965db44STomer Tayar qed_get_block_attn_data(enum block_id block_id, enum dbg_attn_type attn_type) 2377c965db44STomer Tayar { 2378c965db44STomer Tayar const struct dbg_attn_block *base_attn_block_arr = 2379c965db44STomer Tayar (const struct dbg_attn_block *) 2380c965db44STomer Tayar s_dbg_arrays[BIN_BUF_DBG_ATTN_BLOCKS].ptr; 2381c965db44STomer Tayar 2382c965db44STomer Tayar return &base_attn_block_arr[block_id].per_type_data[attn_type]; 2383c965db44STomer Tayar } 2384c965db44STomer Tayar 2385c965db44STomer Tayar /* Returns the attention registers of the specified block */ 2386c965db44STomer Tayar static const struct dbg_attn_reg * 2387c965db44STomer Tayar qed_get_block_attn_regs(enum block_id block_id, enum dbg_attn_type attn_type, 2388c965db44STomer Tayar u8 *num_attn_regs) 2389c965db44STomer Tayar { 2390c965db44STomer Tayar const struct dbg_attn_block_type_data *block_type_data = 2391c965db44STomer Tayar qed_get_block_attn_data(block_id, attn_type); 2392c965db44STomer Tayar 2393c965db44STomer Tayar *num_attn_regs = block_type_data->num_regs; 23947b6859fbSMintz, Yuval 2395c965db44STomer Tayar return &((const struct dbg_attn_reg *) 2396c965db44STomer Tayar s_dbg_arrays[BIN_BUF_DBG_ATTN_REGS].ptr)[block_type_data-> 2397c965db44STomer Tayar regs_offset]; 2398c965db44STomer Tayar } 2399c965db44STomer Tayar 2400c965db44STomer Tayar /* For each block, clear the status of all parities */ 2401c965db44STomer Tayar static void qed_grc_clear_all_prty(struct qed_hwfn *p_hwfn, 2402c965db44STomer Tayar struct qed_ptt *p_ptt) 2403c965db44STomer Tayar { 2404c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 24057b6859fbSMintz, Yuval const struct dbg_attn_reg *attn_reg_arr; 2406c965db44STomer Tayar u8 reg_idx, num_attn_regs; 2407c965db44STomer Tayar u32 block_id; 2408c965db44STomer Tayar 2409c965db44STomer Tayar for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) { 2410c965db44STomer Tayar if (dev_data->block_in_reset[block_id]) 2411c965db44STomer Tayar continue; 2412c965db44STomer Tayar 2413c965db44STomer Tayar attn_reg_arr = qed_get_block_attn_regs((enum block_id)block_id, 2414c965db44STomer Tayar ATTN_TYPE_PARITY, 2415c965db44STomer Tayar &num_attn_regs); 24167b6859fbSMintz, Yuval 2417c965db44STomer Tayar for (reg_idx = 0; reg_idx < num_attn_regs; reg_idx++) { 2418c965db44STomer Tayar const struct dbg_attn_reg *reg_data = 2419c965db44STomer Tayar &attn_reg_arr[reg_idx]; 24207b6859fbSMintz, Yuval u16 modes_buf_offset; 24217b6859fbSMintz, Yuval bool eval_mode; 2422c965db44STomer Tayar 2423c965db44STomer Tayar /* Check mode */ 24247b6859fbSMintz, Yuval eval_mode = GET_FIELD(reg_data->mode.data, 2425c965db44STomer Tayar DBG_MODE_HDR_EVAL_MODE) > 0; 24267b6859fbSMintz, Yuval modes_buf_offset = 2427c965db44STomer Tayar GET_FIELD(reg_data->mode.data, 2428c965db44STomer Tayar DBG_MODE_HDR_MODES_BUF_OFFSET); 2429c965db44STomer Tayar 24307b6859fbSMintz, Yuval /* If Mode match: clear parity status */ 2431c965db44STomer Tayar if (!eval_mode || 2432c965db44STomer Tayar qed_is_mode_match(p_hwfn, &modes_buf_offset)) 2433c965db44STomer Tayar qed_rd(p_hwfn, p_ptt, 2434c965db44STomer Tayar DWORDS_TO_BYTES(reg_data-> 2435c965db44STomer Tayar sts_clr_address)); 2436c965db44STomer Tayar } 2437c965db44STomer Tayar } 2438c965db44STomer Tayar } 2439c965db44STomer Tayar 2440c965db44STomer Tayar /* Dumps GRC registers section header. Returns the dumped size in dwords. 2441c965db44STomer Tayar * The following parameters are dumped: 24427b6859fbSMintz, Yuval * - count: no. of dumped entries 2443d52c89f1SMichal Kalderon * - split_type: split type 2444d52c89f1SMichal Kalderon * - split_id: split ID (dumped only if split_id != SPLIT_TYPE_NONE) 24457b6859fbSMintz, Yuval * - param_name: user parameter value (dumped only if param_name != NULL 24467b6859fbSMintz, Yuval * and param_val != NULL). 2447c965db44STomer Tayar */ 2448c965db44STomer Tayar static u32 qed_grc_dump_regs_hdr(u32 *dump_buf, 2449c965db44STomer Tayar bool dump, 2450c965db44STomer Tayar u32 num_reg_entries, 2451d52c89f1SMichal Kalderon enum init_split_types split_type, 2452d52c89f1SMichal Kalderon u8 split_id, 2453c965db44STomer Tayar const char *param_name, const char *param_val) 2454c965db44STomer Tayar { 2455d52c89f1SMichal Kalderon u8 num_params = 2 + 2456d52c89f1SMichal Kalderon (split_type != SPLIT_TYPE_NONE ? 1 : 0) + (param_name ? 1 : 0); 2457c965db44STomer Tayar u32 offset = 0; 2458c965db44STomer Tayar 2459c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, 2460c965db44STomer Tayar dump, "grc_regs", num_params); 2461c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 2462c965db44STomer Tayar dump, "count", num_reg_entries); 2463c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 2464d52c89f1SMichal Kalderon dump, "split", 2465d52c89f1SMichal Kalderon s_split_type_defs[split_type].name); 2466d52c89f1SMichal Kalderon if (split_type != SPLIT_TYPE_NONE) 2467c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 2468c965db44STomer Tayar dump, "id", split_id); 2469c965db44STomer Tayar if (param_name && param_val) 2470c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 2471c965db44STomer Tayar dump, param_name, param_val); 24727b6859fbSMintz, Yuval 2473c965db44STomer Tayar return offset; 2474c965db44STomer Tayar } 2475c965db44STomer Tayar 2476da090917STomer Tayar /* Reads the specified registers into the specified buffer. 2477da090917STomer Tayar * The addr and len arguments are specified in dwords. 2478da090917STomer Tayar */ 2479da090917STomer Tayar void qed_read_regs(struct qed_hwfn *p_hwfn, 2480da090917STomer Tayar struct qed_ptt *p_ptt, u32 *buf, u32 addr, u32 len) 2481da090917STomer Tayar { 2482da090917STomer Tayar u32 i; 2483da090917STomer Tayar 2484da090917STomer Tayar for (i = 0; i < len; i++) 2485da090917STomer Tayar buf[i] = qed_rd(p_hwfn, p_ptt, DWORDS_TO_BYTES(addr + i)); 2486da090917STomer Tayar } 2487da090917STomer Tayar 2488be086e7cSMintz, Yuval /* Dumps the GRC registers in the specified address range. 2489be086e7cSMintz, Yuval * Returns the dumped size in dwords. 24907b6859fbSMintz, Yuval * The addr and len arguments are specified in dwords. 2491be086e7cSMintz, Yuval */ 2492be086e7cSMintz, Yuval static u32 qed_grc_dump_addr_range(struct qed_hwfn *p_hwfn, 24937b6859fbSMintz, Yuval struct qed_ptt *p_ptt, 24947b6859fbSMintz, Yuval u32 *dump_buf, 2495d52c89f1SMichal Kalderon bool dump, u32 addr, u32 len, bool wide_bus, 2496d52c89f1SMichal Kalderon enum init_split_types split_type, 2497d52c89f1SMichal Kalderon u8 split_id) 2498be086e7cSMintz, Yuval { 2499da090917STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2500d52c89f1SMichal Kalderon u8 port_id = 0, pf_id = 0, vf_id = 0, fid = 0; 2501be086e7cSMintz, Yuval 25027b6859fbSMintz, Yuval if (!dump) 25037b6859fbSMintz, Yuval return len; 25047b6859fbSMintz, Yuval 2505da090917STomer Tayar /* Print log if needed */ 2506da090917STomer Tayar dev_data->num_regs_read += len; 2507da090917STomer Tayar if (dev_data->num_regs_read >= 2508da090917STomer Tayar s_platform_defs[dev_data->platform_id].log_thresh) { 2509da090917STomer Tayar DP_VERBOSE(p_hwfn, 2510da090917STomer Tayar QED_MSG_DEBUG, 2511da090917STomer Tayar "Dumping %d registers...\n", 2512da090917STomer Tayar dev_data->num_regs_read); 2513da090917STomer Tayar dev_data->num_regs_read = 0; 2514da090917STomer Tayar } 25157b6859fbSMintz, Yuval 2516d52c89f1SMichal Kalderon switch (split_type) { 2517d52c89f1SMichal Kalderon case SPLIT_TYPE_PORT: 2518d52c89f1SMichal Kalderon port_id = split_id; 2519d52c89f1SMichal Kalderon break; 2520d52c89f1SMichal Kalderon case SPLIT_TYPE_PF: 2521d52c89f1SMichal Kalderon pf_id = split_id; 2522d52c89f1SMichal Kalderon break; 2523d52c89f1SMichal Kalderon case SPLIT_TYPE_PORT_PF: 2524d52c89f1SMichal Kalderon port_id = split_id / dev_data->num_pfs_per_port; 2525d52c89f1SMichal Kalderon pf_id = port_id + dev_data->num_ports * 2526d52c89f1SMichal Kalderon (split_id % dev_data->num_pfs_per_port); 2527d52c89f1SMichal Kalderon break; 2528d52c89f1SMichal Kalderon case SPLIT_TYPE_VF: 2529d52c89f1SMichal Kalderon vf_id = split_id; 2530d52c89f1SMichal Kalderon break; 2531d52c89f1SMichal Kalderon default: 2532d52c89f1SMichal Kalderon break; 2533d52c89f1SMichal Kalderon } 2534d52c89f1SMichal Kalderon 2535da090917STomer Tayar /* Try reading using DMAE */ 2536d52c89f1SMichal Kalderon if (dev_data->use_dmae && split_type == SPLIT_TYPE_NONE && 2537da090917STomer Tayar (len >= s_platform_defs[dev_data->platform_id].dmae_thresh || 2538da090917STomer Tayar wide_bus)) { 2539da090917STomer Tayar if (!qed_dmae_grc2host(p_hwfn, p_ptt, DWORDS_TO_BYTES(addr), 2540da090917STomer Tayar (u64)(uintptr_t)(dump_buf), len, 0)) 2541da090917STomer Tayar return len; 2542da090917STomer Tayar dev_data->use_dmae = 0; 2543da090917STomer Tayar DP_VERBOSE(p_hwfn, 2544da090917STomer Tayar QED_MSG_DEBUG, 2545da090917STomer Tayar "Failed reading from chip using DMAE, using GRC instead\n"); 2546da090917STomer Tayar } 2547da090917STomer Tayar 2548d52c89f1SMichal Kalderon /* If not read using DMAE, read using GRC */ 2549d52c89f1SMichal Kalderon 2550d52c89f1SMichal Kalderon /* Set pretend */ 2551d52c89f1SMichal Kalderon if (split_type != dev_data->pretend.split_type || split_id != 2552d52c89f1SMichal Kalderon dev_data->pretend.split_id) { 2553d52c89f1SMichal Kalderon switch (split_type) { 2554d52c89f1SMichal Kalderon case SPLIT_TYPE_PORT: 2555d52c89f1SMichal Kalderon qed_port_pretend(p_hwfn, p_ptt, port_id); 2556d52c89f1SMichal Kalderon break; 2557d52c89f1SMichal Kalderon case SPLIT_TYPE_PF: 2558d52c89f1SMichal Kalderon fid = pf_id << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT; 2559d52c89f1SMichal Kalderon qed_fid_pretend(p_hwfn, p_ptt, fid); 2560d52c89f1SMichal Kalderon break; 2561d52c89f1SMichal Kalderon case SPLIT_TYPE_PORT_PF: 2562d52c89f1SMichal Kalderon fid = pf_id << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT; 2563d52c89f1SMichal Kalderon qed_port_fid_pretend(p_hwfn, p_ptt, port_id, fid); 2564d52c89f1SMichal Kalderon break; 2565d52c89f1SMichal Kalderon case SPLIT_TYPE_VF: 2566d52c89f1SMichal Kalderon fid = BIT(PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT) | 2567d52c89f1SMichal Kalderon (vf_id << PXP_PRETEND_CONCRETE_FID_VFID_SHIFT); 2568d52c89f1SMichal Kalderon qed_fid_pretend(p_hwfn, p_ptt, fid); 2569d52c89f1SMichal Kalderon break; 2570d52c89f1SMichal Kalderon default: 2571d52c89f1SMichal Kalderon break; 2572d52c89f1SMichal Kalderon } 2573d52c89f1SMichal Kalderon 2574d52c89f1SMichal Kalderon dev_data->pretend.split_type = (u8)split_type; 2575d52c89f1SMichal Kalderon dev_data->pretend.split_id = split_id; 2576d52c89f1SMichal Kalderon } 2577d52c89f1SMichal Kalderon 2578d52c89f1SMichal Kalderon /* Read registers using GRC */ 2579da090917STomer Tayar qed_read_regs(p_hwfn, p_ptt, dump_buf, addr, len); 2580da090917STomer Tayar 2581da090917STomer Tayar return len; 2582be086e7cSMintz, Yuval } 2583be086e7cSMintz, Yuval 25847b6859fbSMintz, Yuval /* Dumps GRC registers sequence header. Returns the dumped size in dwords. 25857b6859fbSMintz, Yuval * The addr and len arguments are specified in dwords. 25867b6859fbSMintz, Yuval */ 25877b6859fbSMintz, Yuval static u32 qed_grc_dump_reg_entry_hdr(u32 *dump_buf, 25887b6859fbSMintz, Yuval bool dump, u32 addr, u32 len) 2589be086e7cSMintz, Yuval { 2590be086e7cSMintz, Yuval if (dump) 2591be086e7cSMintz, Yuval *dump_buf = addr | (len << REG_DUMP_LEN_SHIFT); 25927b6859fbSMintz, Yuval 2593be086e7cSMintz, Yuval return 1; 2594be086e7cSMintz, Yuval } 2595be086e7cSMintz, Yuval 25967b6859fbSMintz, Yuval /* Dumps GRC registers sequence. Returns the dumped size in dwords. 25977b6859fbSMintz, Yuval * The addr and len arguments are specified in dwords. 25987b6859fbSMintz, Yuval */ 2599c965db44STomer Tayar static u32 qed_grc_dump_reg_entry(struct qed_hwfn *p_hwfn, 26007b6859fbSMintz, Yuval struct qed_ptt *p_ptt, 26017b6859fbSMintz, Yuval u32 *dump_buf, 2602d52c89f1SMichal Kalderon bool dump, u32 addr, u32 len, bool wide_bus, 2603d52c89f1SMichal Kalderon enum init_split_types split_type, u8 split_id) 2604c965db44STomer Tayar { 2605be086e7cSMintz, Yuval u32 offset = 0; 2606c965db44STomer Tayar 2607be086e7cSMintz, Yuval offset += qed_grc_dump_reg_entry_hdr(dump_buf, dump, addr, len); 2608be086e7cSMintz, Yuval offset += qed_grc_dump_addr_range(p_hwfn, 2609c965db44STomer Tayar p_ptt, 26107b6859fbSMintz, Yuval dump_buf + offset, 2611d52c89f1SMichal Kalderon dump, addr, len, wide_bus, 2612d52c89f1SMichal Kalderon split_type, split_id); 26137b6859fbSMintz, Yuval 2614be086e7cSMintz, Yuval return offset; 2615be086e7cSMintz, Yuval } 2616be086e7cSMintz, Yuval 2617be086e7cSMintz, Yuval /* Dumps GRC registers sequence with skip cycle. 2618be086e7cSMintz, Yuval * Returns the dumped size in dwords. 26197b6859fbSMintz, Yuval * - addr: start GRC address in dwords 26207b6859fbSMintz, Yuval * - total_len: total no. of dwords to dump 26217b6859fbSMintz, Yuval * - read_len: no. consecutive dwords to read 26227b6859fbSMintz, Yuval * - skip_len: no. of dwords to skip (and fill with zeros) 2623be086e7cSMintz, Yuval */ 2624be086e7cSMintz, Yuval static u32 qed_grc_dump_reg_entry_skip(struct qed_hwfn *p_hwfn, 26257b6859fbSMintz, Yuval struct qed_ptt *p_ptt, 26267b6859fbSMintz, Yuval u32 *dump_buf, 26277b6859fbSMintz, Yuval bool dump, 26287b6859fbSMintz, Yuval u32 addr, 26297b6859fbSMintz, Yuval u32 total_len, 2630be086e7cSMintz, Yuval u32 read_len, u32 skip_len) 2631be086e7cSMintz, Yuval { 2632be086e7cSMintz, Yuval u32 offset = 0, reg_offset = 0; 2633be086e7cSMintz, Yuval 2634be086e7cSMintz, Yuval offset += qed_grc_dump_reg_entry_hdr(dump_buf, dump, addr, total_len); 26357b6859fbSMintz, Yuval 26367b6859fbSMintz, Yuval if (!dump) 26377b6859fbSMintz, Yuval return offset + total_len; 26387b6859fbSMintz, Yuval 2639be086e7cSMintz, Yuval while (reg_offset < total_len) { 26407b6859fbSMintz, Yuval u32 curr_len = min_t(u32, read_len, total_len - reg_offset); 26417b6859fbSMintz, Yuval 2642be086e7cSMintz, Yuval offset += qed_grc_dump_addr_range(p_hwfn, 2643be086e7cSMintz, Yuval p_ptt, 2644be086e7cSMintz, Yuval dump_buf + offset, 2645d52c89f1SMichal Kalderon dump, addr, curr_len, false, 2646d52c89f1SMichal Kalderon SPLIT_TYPE_NONE, 0); 2647be086e7cSMintz, Yuval reg_offset += curr_len; 2648be086e7cSMintz, Yuval addr += curr_len; 26497b6859fbSMintz, Yuval 2650be086e7cSMintz, Yuval if (reg_offset < total_len) { 26517b6859fbSMintz, Yuval curr_len = min_t(u32, skip_len, total_len - skip_len); 26527b6859fbSMintz, Yuval memset(dump_buf + offset, 0, DWORDS_TO_BYTES(curr_len)); 2653be086e7cSMintz, Yuval offset += curr_len; 2654be086e7cSMintz, Yuval reg_offset += curr_len; 2655be086e7cSMintz, Yuval addr += curr_len; 2656be086e7cSMintz, Yuval } 2657be086e7cSMintz, Yuval } 2658c965db44STomer Tayar 2659c965db44STomer Tayar return offset; 2660c965db44STomer Tayar } 2661c965db44STomer Tayar 2662c965db44STomer Tayar /* Dumps GRC registers entries. Returns the dumped size in dwords. */ 2663c965db44STomer Tayar static u32 qed_grc_dump_regs_entries(struct qed_hwfn *p_hwfn, 2664c965db44STomer Tayar struct qed_ptt *p_ptt, 2665c965db44STomer Tayar struct dbg_array input_regs_arr, 2666c965db44STomer Tayar u32 *dump_buf, 2667c965db44STomer Tayar bool dump, 2668d52c89f1SMichal Kalderon enum init_split_types split_type, 2669d52c89f1SMichal Kalderon u8 split_id, 2670c965db44STomer Tayar bool block_enable[MAX_BLOCK_ID], 2671c965db44STomer Tayar u32 *num_dumped_reg_entries) 2672c965db44STomer Tayar { 2673c965db44STomer Tayar u32 i, offset = 0, input_offset = 0; 2674c965db44STomer Tayar bool mode_match = true; 2675c965db44STomer Tayar 2676c965db44STomer Tayar *num_dumped_reg_entries = 0; 26777b6859fbSMintz, Yuval 2678c965db44STomer Tayar while (input_offset < input_regs_arr.size_in_dwords) { 2679c965db44STomer Tayar const struct dbg_dump_cond_hdr *cond_hdr = 2680c965db44STomer Tayar (const struct dbg_dump_cond_hdr *) 2681c965db44STomer Tayar &input_regs_arr.ptr[input_offset++]; 26827b6859fbSMintz, Yuval u16 modes_buf_offset; 26837b6859fbSMintz, Yuval bool eval_mode; 2684c965db44STomer Tayar 2685c965db44STomer Tayar /* Check mode/block */ 26867b6859fbSMintz, Yuval eval_mode = GET_FIELD(cond_hdr->mode.data, 26877b6859fbSMintz, Yuval DBG_MODE_HDR_EVAL_MODE) > 0; 2688c965db44STomer Tayar if (eval_mode) { 26897b6859fbSMintz, Yuval modes_buf_offset = 2690c965db44STomer Tayar GET_FIELD(cond_hdr->mode.data, 2691c965db44STomer Tayar DBG_MODE_HDR_MODES_BUF_OFFSET); 2692c965db44STomer Tayar mode_match = qed_is_mode_match(p_hwfn, 2693c965db44STomer Tayar &modes_buf_offset); 2694c965db44STomer Tayar } 2695c965db44STomer Tayar 26967b6859fbSMintz, Yuval if (!mode_match || !block_enable[cond_hdr->block_id]) { 26977b6859fbSMintz, Yuval input_offset += cond_hdr->data_size; 26987b6859fbSMintz, Yuval continue; 26997b6859fbSMintz, Yuval } 27007b6859fbSMintz, Yuval 27017b6859fbSMintz, Yuval for (i = 0; i < cond_hdr->data_size; i++, input_offset++) { 2702c965db44STomer Tayar const struct dbg_dump_reg *reg = 2703c965db44STomer Tayar (const struct dbg_dump_reg *) 2704c965db44STomer Tayar &input_regs_arr.ptr[input_offset]; 2705be086e7cSMintz, Yuval u32 addr, len; 27067b6859fbSMintz, Yuval bool wide_bus; 2707c965db44STomer Tayar 27087b6859fbSMintz, Yuval addr = GET_FIELD(reg->data, DBG_DUMP_REG_ADDRESS); 2709be086e7cSMintz, Yuval len = GET_FIELD(reg->data, DBG_DUMP_REG_LENGTH); 27107b6859fbSMintz, Yuval wide_bus = GET_FIELD(reg->data, DBG_DUMP_REG_WIDE_BUS); 27117b6859fbSMintz, Yuval offset += qed_grc_dump_reg_entry(p_hwfn, 27127b6859fbSMintz, Yuval p_ptt, 2713be086e7cSMintz, Yuval dump_buf + offset, 2714be086e7cSMintz, Yuval dump, 2715be086e7cSMintz, Yuval addr, 27167b6859fbSMintz, Yuval len, 2717d52c89f1SMichal Kalderon wide_bus, 2718d52c89f1SMichal Kalderon split_type, split_id); 2719c965db44STomer Tayar (*num_dumped_reg_entries)++; 2720c965db44STomer Tayar } 2721c965db44STomer Tayar } 2722c965db44STomer Tayar 2723c965db44STomer Tayar return offset; 2724c965db44STomer Tayar } 2725c965db44STomer Tayar 2726c965db44STomer Tayar /* Dumps GRC registers entries. Returns the dumped size in dwords. */ 2727c965db44STomer Tayar static u32 qed_grc_dump_split_data(struct qed_hwfn *p_hwfn, 2728c965db44STomer Tayar struct qed_ptt *p_ptt, 2729c965db44STomer Tayar struct dbg_array input_regs_arr, 2730c965db44STomer Tayar u32 *dump_buf, 2731c965db44STomer Tayar bool dump, 2732c965db44STomer Tayar bool block_enable[MAX_BLOCK_ID], 2733d52c89f1SMichal Kalderon enum init_split_types split_type, 2734d52c89f1SMichal Kalderon u8 split_id, 2735c965db44STomer Tayar const char *param_name, 2736c965db44STomer Tayar const char *param_val) 2737c965db44STomer Tayar { 2738d52c89f1SMichal Kalderon struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2739d52c89f1SMichal Kalderon enum init_split_types hdr_split_type = split_type; 2740c965db44STomer Tayar u32 num_dumped_reg_entries, offset; 2741d52c89f1SMichal Kalderon u8 hdr_split_id = split_id; 2742d52c89f1SMichal Kalderon 2743d52c89f1SMichal Kalderon /* In PORT_PF split type, print a port split header */ 2744d52c89f1SMichal Kalderon if (split_type == SPLIT_TYPE_PORT_PF) { 2745d52c89f1SMichal Kalderon hdr_split_type = SPLIT_TYPE_PORT; 2746d52c89f1SMichal Kalderon hdr_split_id = split_id / dev_data->num_pfs_per_port; 2747d52c89f1SMichal Kalderon } 2748c965db44STomer Tayar 2749c965db44STomer Tayar /* Calculate register dump header size (and skip it for now) */ 2750c965db44STomer Tayar offset = qed_grc_dump_regs_hdr(dump_buf, 2751c965db44STomer Tayar false, 2752c965db44STomer Tayar 0, 2753d52c89f1SMichal Kalderon hdr_split_type, 2754d52c89f1SMichal Kalderon hdr_split_id, param_name, param_val); 2755c965db44STomer Tayar 2756c965db44STomer Tayar /* Dump registers */ 2757c965db44STomer Tayar offset += qed_grc_dump_regs_entries(p_hwfn, 2758c965db44STomer Tayar p_ptt, 2759c965db44STomer Tayar input_regs_arr, 2760c965db44STomer Tayar dump_buf + offset, 2761c965db44STomer Tayar dump, 2762d52c89f1SMichal Kalderon split_type, 2763d52c89f1SMichal Kalderon split_id, 2764c965db44STomer Tayar block_enable, 2765c965db44STomer Tayar &num_dumped_reg_entries); 2766c965db44STomer Tayar 2767c965db44STomer Tayar /* Write register dump header */ 2768c965db44STomer Tayar if (dump && num_dumped_reg_entries > 0) 2769c965db44STomer Tayar qed_grc_dump_regs_hdr(dump_buf, 2770c965db44STomer Tayar dump, 2771c965db44STomer Tayar num_dumped_reg_entries, 2772d52c89f1SMichal Kalderon hdr_split_type, 2773d52c89f1SMichal Kalderon hdr_split_id, param_name, param_val); 2774c965db44STomer Tayar 2775c965db44STomer Tayar return num_dumped_reg_entries > 0 ? offset : 0; 2776c965db44STomer Tayar } 2777c965db44STomer Tayar 27787b6859fbSMintz, Yuval /* Dumps registers according to the input registers array. Returns the dumped 27797b6859fbSMintz, Yuval * size in dwords. 2780c965db44STomer Tayar */ 2781c965db44STomer Tayar static u32 qed_grc_dump_registers(struct qed_hwfn *p_hwfn, 2782c965db44STomer Tayar struct qed_ptt *p_ptt, 2783c965db44STomer Tayar u32 *dump_buf, 2784c965db44STomer Tayar bool dump, 2785c965db44STomer Tayar bool block_enable[MAX_BLOCK_ID], 2786c965db44STomer Tayar const char *param_name, const char *param_val) 2787c965db44STomer Tayar { 2788c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2789c965db44STomer Tayar u32 offset = 0, input_offset = 0; 2790be086e7cSMintz, Yuval u16 fid; 2791c965db44STomer Tayar while (input_offset < 2792c965db44STomer Tayar s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].size_in_dwords) { 27937b6859fbSMintz, Yuval const struct dbg_dump_split_hdr *split_hdr; 27947b6859fbSMintz, Yuval struct dbg_array curr_input_regs_arr; 2795d52c89f1SMichal Kalderon enum init_split_types split_type; 2796d52c89f1SMichal Kalderon u16 split_count = 0; 27977b6859fbSMintz, Yuval u32 split_data_size; 2798d52c89f1SMichal Kalderon u8 split_id; 27997b6859fbSMintz, Yuval 28007b6859fbSMintz, Yuval split_hdr = 2801c965db44STomer Tayar (const struct dbg_dump_split_hdr *) 2802c965db44STomer Tayar &s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].ptr[input_offset++]; 2803d52c89f1SMichal Kalderon split_type = 28047b6859fbSMintz, Yuval GET_FIELD(split_hdr->hdr, 2805c965db44STomer Tayar DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID); 28067b6859fbSMintz, Yuval split_data_size = 28077b6859fbSMintz, Yuval GET_FIELD(split_hdr->hdr, 2808c965db44STomer Tayar DBG_DUMP_SPLIT_HDR_DATA_SIZE); 28097b6859fbSMintz, Yuval curr_input_regs_arr.ptr = 28107b6859fbSMintz, Yuval &s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].ptr[input_offset]; 28117b6859fbSMintz, Yuval curr_input_regs_arr.size_in_dwords = split_data_size; 2812c965db44STomer Tayar 2813d52c89f1SMichal Kalderon switch (split_type) { 2814c965db44STomer Tayar case SPLIT_TYPE_NONE: 2815d52c89f1SMichal Kalderon split_count = 1; 2816c965db44STomer Tayar break; 2817c965db44STomer Tayar case SPLIT_TYPE_PORT: 2818d52c89f1SMichal Kalderon split_count = dev_data->num_ports; 2819c965db44STomer Tayar break; 2820c965db44STomer Tayar case SPLIT_TYPE_PF: 2821c965db44STomer Tayar case SPLIT_TYPE_PORT_PF: 2822d52c89f1SMichal Kalderon split_count = dev_data->num_ports * 2823d52c89f1SMichal Kalderon dev_data->num_pfs_per_port; 2824be086e7cSMintz, Yuval break; 2825be086e7cSMintz, Yuval case SPLIT_TYPE_VF: 2826d52c89f1SMichal Kalderon split_count = dev_data->num_vfs; 2827d52c89f1SMichal Kalderon break; 2828d52c89f1SMichal Kalderon default: 2829d52c89f1SMichal Kalderon return 0; 2830be086e7cSMintz, Yuval } 2831be086e7cSMintz, Yuval 2832d52c89f1SMichal Kalderon for (split_id = 0; split_id < split_count; split_id++) 2833d52c89f1SMichal Kalderon offset += qed_grc_dump_split_data(p_hwfn, p_ptt, 2834be086e7cSMintz, Yuval curr_input_regs_arr, 2835be086e7cSMintz, Yuval dump_buf + offset, 2836be086e7cSMintz, Yuval dump, block_enable, 2837d52c89f1SMichal Kalderon split_type, 2838d52c89f1SMichal Kalderon split_id, 2839be086e7cSMintz, Yuval param_name, 2840c965db44STomer Tayar param_val); 2841c965db44STomer Tayar 2842c965db44STomer Tayar input_offset += split_data_size; 2843c965db44STomer Tayar } 2844c965db44STomer Tayar 2845d52c89f1SMichal Kalderon /* Cancel pretends (pretend to original PF) */ 2846be086e7cSMintz, Yuval if (dump) { 2847be086e7cSMintz, Yuval fid = p_hwfn->rel_pf_id << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT; 2848be086e7cSMintz, Yuval qed_fid_pretend(p_hwfn, p_ptt, fid); 2849d52c89f1SMichal Kalderon dev_data->pretend.split_type = SPLIT_TYPE_NONE; 2850d52c89f1SMichal Kalderon dev_data->pretend.split_id = 0; 2851be086e7cSMintz, Yuval } 2852be086e7cSMintz, Yuval 2853c965db44STomer Tayar return offset; 2854c965db44STomer Tayar } 2855c965db44STomer Tayar 2856c965db44STomer Tayar /* Dump reset registers. Returns the dumped size in dwords. */ 2857c965db44STomer Tayar static u32 qed_grc_dump_reset_regs(struct qed_hwfn *p_hwfn, 2858c965db44STomer Tayar struct qed_ptt *p_ptt, 2859c965db44STomer Tayar u32 *dump_buf, bool dump) 2860c965db44STomer Tayar { 2861c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2862c965db44STomer Tayar u32 i, offset = 0, num_regs = 0; 2863c965db44STomer Tayar 2864c965db44STomer Tayar /* Calculate header size */ 2865c965db44STomer Tayar offset += qed_grc_dump_regs_hdr(dump_buf, 2866d52c89f1SMichal Kalderon false, 0, 2867d52c89f1SMichal Kalderon SPLIT_TYPE_NONE, 0, NULL, NULL); 2868c965db44STomer Tayar 2869c965db44STomer Tayar /* Write reset registers */ 2870c965db44STomer Tayar for (i = 0; i < MAX_DBG_RESET_REGS; i++) { 28717b6859fbSMintz, Yuval if (!s_reset_regs_defs[i].exists[dev_data->chip_id]) 28727b6859fbSMintz, Yuval continue; 2873be086e7cSMintz, Yuval 2874c965db44STomer Tayar offset += qed_grc_dump_reg_entry(p_hwfn, 2875c965db44STomer Tayar p_ptt, 2876c965db44STomer Tayar dump_buf + offset, 2877c965db44STomer Tayar dump, 28787b6859fbSMintz, Yuval BYTES_TO_DWORDS 28797b6859fbSMintz, Yuval (s_reset_regs_defs[i].addr), 1, 2880d52c89f1SMichal Kalderon false, SPLIT_TYPE_NONE, 0); 2881c965db44STomer Tayar num_regs++; 2882c965db44STomer Tayar } 2883c965db44STomer Tayar 2884c965db44STomer Tayar /* Write header */ 2885c965db44STomer Tayar if (dump) 2886c965db44STomer Tayar qed_grc_dump_regs_hdr(dump_buf, 2887d52c89f1SMichal Kalderon true, num_regs, SPLIT_TYPE_NONE, 2888d52c89f1SMichal Kalderon 0, NULL, NULL); 28897b6859fbSMintz, Yuval 2890c965db44STomer Tayar return offset; 2891c965db44STomer Tayar } 2892c965db44STomer Tayar 28937b6859fbSMintz, Yuval /* Dump registers that are modified during GRC Dump and therefore must be 28947b6859fbSMintz, Yuval * dumped first. Returns the dumped size in dwords. 2895c965db44STomer Tayar */ 2896c965db44STomer Tayar static u32 qed_grc_dump_modified_regs(struct qed_hwfn *p_hwfn, 2897c965db44STomer Tayar struct qed_ptt *p_ptt, 2898c965db44STomer Tayar u32 *dump_buf, bool dump) 2899c965db44STomer Tayar { 2900c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 29017b6859fbSMintz, Yuval u32 block_id, offset = 0, num_reg_entries = 0; 29027b6859fbSMintz, Yuval const struct dbg_attn_reg *attn_reg_arr; 2903c965db44STomer Tayar u8 storm_id, reg_idx, num_attn_regs; 2904c965db44STomer Tayar 2905c965db44STomer Tayar /* Calculate header size */ 2906c965db44STomer Tayar offset += qed_grc_dump_regs_hdr(dump_buf, 2907d52c89f1SMichal Kalderon false, 0, SPLIT_TYPE_NONE, 2908d52c89f1SMichal Kalderon 0, NULL, NULL); 2909c965db44STomer Tayar 2910c965db44STomer Tayar /* Write parity registers */ 2911c965db44STomer Tayar for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) { 2912c965db44STomer Tayar if (dev_data->block_in_reset[block_id] && dump) 2913c965db44STomer Tayar continue; 2914c965db44STomer Tayar 2915c965db44STomer Tayar attn_reg_arr = qed_get_block_attn_regs((enum block_id)block_id, 2916c965db44STomer Tayar ATTN_TYPE_PARITY, 2917c965db44STomer Tayar &num_attn_regs); 29187b6859fbSMintz, Yuval 2919c965db44STomer Tayar for (reg_idx = 0; reg_idx < num_attn_regs; reg_idx++) { 2920c965db44STomer Tayar const struct dbg_attn_reg *reg_data = 2921c965db44STomer Tayar &attn_reg_arr[reg_idx]; 2922c965db44STomer Tayar u16 modes_buf_offset; 2923c965db44STomer Tayar bool eval_mode; 2924be086e7cSMintz, Yuval u32 addr; 2925c965db44STomer Tayar 2926c965db44STomer Tayar /* Check mode */ 2927c965db44STomer Tayar eval_mode = GET_FIELD(reg_data->mode.data, 2928c965db44STomer Tayar DBG_MODE_HDR_EVAL_MODE) > 0; 2929c965db44STomer Tayar modes_buf_offset = 2930c965db44STomer Tayar GET_FIELD(reg_data->mode.data, 2931c965db44STomer Tayar DBG_MODE_HDR_MODES_BUF_OFFSET); 29327b6859fbSMintz, Yuval if (eval_mode && 29337b6859fbSMintz, Yuval !qed_is_mode_match(p_hwfn, &modes_buf_offset)) 29347b6859fbSMintz, Yuval continue; 29357b6859fbSMintz, Yuval 29367b6859fbSMintz, Yuval /* Mode match: read & dump registers */ 2937be086e7cSMintz, Yuval addr = reg_data->mask_address; 29387b6859fbSMintz, Yuval offset += qed_grc_dump_reg_entry(p_hwfn, 2939c965db44STomer Tayar p_ptt, 2940c965db44STomer Tayar dump_buf + offset, 2941c965db44STomer Tayar dump, 2942be086e7cSMintz, Yuval addr, 2943d52c89f1SMichal Kalderon 1, false, 2944d52c89f1SMichal Kalderon SPLIT_TYPE_NONE, 0); 2945be086e7cSMintz, Yuval addr = GET_FIELD(reg_data->data, 2946be086e7cSMintz, Yuval DBG_ATTN_REG_STS_ADDRESS); 29477b6859fbSMintz, Yuval offset += qed_grc_dump_reg_entry(p_hwfn, 2948c965db44STomer Tayar p_ptt, 2949c965db44STomer Tayar dump_buf + offset, 2950c965db44STomer Tayar dump, 2951be086e7cSMintz, Yuval addr, 2952d52c89f1SMichal Kalderon 1, false, 2953d52c89f1SMichal Kalderon SPLIT_TYPE_NONE, 0); 2954c965db44STomer Tayar num_reg_entries += 2; 2955c965db44STomer Tayar } 2956c965db44STomer Tayar } 2957c965db44STomer Tayar 29587b6859fbSMintz, Yuval /* Write Storm stall status registers */ 2959c965db44STomer Tayar for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 29607b6859fbSMintz, Yuval struct storm_defs *storm = &s_storm_defs[storm_id]; 2961be086e7cSMintz, Yuval u32 addr; 2962be086e7cSMintz, Yuval 29637b6859fbSMintz, Yuval if (dev_data->block_in_reset[storm->block_id] && dump) 2964c965db44STomer Tayar continue; 2965c965db44STomer Tayar 2966be086e7cSMintz, Yuval addr = 2967be086e7cSMintz, Yuval BYTES_TO_DWORDS(s_storm_defs[storm_id].sem_fast_mem_addr + 2968be086e7cSMintz, Yuval SEM_FAST_REG_STALLED); 2969c965db44STomer Tayar offset += qed_grc_dump_reg_entry(p_hwfn, 2970c965db44STomer Tayar p_ptt, 2971c965db44STomer Tayar dump_buf + offset, 2972c965db44STomer Tayar dump, 2973be086e7cSMintz, Yuval addr, 29747b6859fbSMintz, Yuval 1, 2975d52c89f1SMichal Kalderon false, SPLIT_TYPE_NONE, 0); 2976c965db44STomer Tayar num_reg_entries++; 2977c965db44STomer Tayar } 2978c965db44STomer Tayar 2979c965db44STomer Tayar /* Write header */ 2980c965db44STomer Tayar if (dump) 2981c965db44STomer Tayar qed_grc_dump_regs_hdr(dump_buf, 2982c965db44STomer Tayar true, 2983d52c89f1SMichal Kalderon num_reg_entries, SPLIT_TYPE_NONE, 2984d52c89f1SMichal Kalderon 0, NULL, NULL); 29857b6859fbSMintz, Yuval 2986c965db44STomer Tayar return offset; 2987c965db44STomer Tayar } 2988c965db44STomer Tayar 2989be086e7cSMintz, Yuval /* Dumps registers that can't be represented in the debug arrays */ 2990be086e7cSMintz, Yuval static u32 qed_grc_dump_special_regs(struct qed_hwfn *p_hwfn, 2991be086e7cSMintz, Yuval struct qed_ptt *p_ptt, 2992be086e7cSMintz, Yuval u32 *dump_buf, bool dump) 2993be086e7cSMintz, Yuval { 2994be086e7cSMintz, Yuval u32 offset = 0, addr; 2995be086e7cSMintz, Yuval 2996be086e7cSMintz, Yuval offset += qed_grc_dump_regs_hdr(dump_buf, 2997d52c89f1SMichal Kalderon dump, 2, SPLIT_TYPE_NONE, 0, 2998d52c89f1SMichal Kalderon NULL, NULL); 2999be086e7cSMintz, Yuval 3000be086e7cSMintz, Yuval /* Dump R/TDIF_REG_DEBUG_ERROR_INFO_SIZE (every 8'th register should be 3001be086e7cSMintz, Yuval * skipped). 3002be086e7cSMintz, Yuval */ 3003be086e7cSMintz, Yuval addr = BYTES_TO_DWORDS(RDIF_REG_DEBUG_ERROR_INFO); 3004be086e7cSMintz, Yuval offset += qed_grc_dump_reg_entry_skip(p_hwfn, 3005be086e7cSMintz, Yuval p_ptt, 3006be086e7cSMintz, Yuval dump_buf + offset, 3007be086e7cSMintz, Yuval dump, 3008be086e7cSMintz, Yuval addr, 3009be086e7cSMintz, Yuval RDIF_REG_DEBUG_ERROR_INFO_SIZE, 3010be086e7cSMintz, Yuval 7, 3011be086e7cSMintz, Yuval 1); 3012be086e7cSMintz, Yuval addr = BYTES_TO_DWORDS(TDIF_REG_DEBUG_ERROR_INFO); 3013be086e7cSMintz, Yuval offset += 3014be086e7cSMintz, Yuval qed_grc_dump_reg_entry_skip(p_hwfn, 3015be086e7cSMintz, Yuval p_ptt, 3016be086e7cSMintz, Yuval dump_buf + offset, 3017be086e7cSMintz, Yuval dump, 3018be086e7cSMintz, Yuval addr, 3019be086e7cSMintz, Yuval TDIF_REG_DEBUG_ERROR_INFO_SIZE, 3020be086e7cSMintz, Yuval 7, 3021be086e7cSMintz, Yuval 1); 3022be086e7cSMintz, Yuval 3023be086e7cSMintz, Yuval return offset; 3024be086e7cSMintz, Yuval } 3025be086e7cSMintz, Yuval 30267b6859fbSMintz, Yuval /* Dumps a GRC memory header (section and params). Returns the dumped size in 30277b6859fbSMintz, Yuval * dwords. The following parameters are dumped: 30287b6859fbSMintz, Yuval * - name: dumped only if it's not NULL. 30297b6859fbSMintz, Yuval * - addr: in dwords, dumped only if name is NULL. 30307b6859fbSMintz, Yuval * - len: in dwords, always dumped. 30317b6859fbSMintz, Yuval * - width: dumped if it's not zero. 30327b6859fbSMintz, Yuval * - packed: dumped only if it's not false. 30337b6859fbSMintz, Yuval * - mem_group: always dumped. 30347b6859fbSMintz, Yuval * - is_storm: true only if the memory is related to a Storm. 30357b6859fbSMintz, Yuval * - storm_letter: valid only if is_storm is true. 30367b6859fbSMintz, Yuval * 3037c965db44STomer Tayar */ 3038c965db44STomer Tayar static u32 qed_grc_dump_mem_hdr(struct qed_hwfn *p_hwfn, 3039c965db44STomer Tayar u32 *dump_buf, 3040c965db44STomer Tayar bool dump, 3041c965db44STomer Tayar const char *name, 3042be086e7cSMintz, Yuval u32 addr, 3043be086e7cSMintz, Yuval u32 len, 3044c965db44STomer Tayar u32 bit_width, 3045c965db44STomer Tayar bool packed, 3046c965db44STomer Tayar const char *mem_group, 3047c965db44STomer Tayar bool is_storm, char storm_letter) 3048c965db44STomer Tayar { 3049c965db44STomer Tayar u8 num_params = 3; 3050c965db44STomer Tayar u32 offset = 0; 3051c965db44STomer Tayar char buf[64]; 3052c965db44STomer Tayar 3053be086e7cSMintz, Yuval if (!len) 3054c965db44STomer Tayar DP_NOTICE(p_hwfn, 3055c965db44STomer Tayar "Unexpected GRC Dump error: dumped memory size must be non-zero\n"); 30567b6859fbSMintz, Yuval 3057c965db44STomer Tayar if (bit_width) 3058c965db44STomer Tayar num_params++; 3059c965db44STomer Tayar if (packed) 3060c965db44STomer Tayar num_params++; 3061c965db44STomer Tayar 3062c965db44STomer Tayar /* Dump section header */ 3063c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, 3064c965db44STomer Tayar dump, "grc_mem", num_params); 30657b6859fbSMintz, Yuval 3066c965db44STomer Tayar if (name) { 3067c965db44STomer Tayar /* Dump name */ 3068c965db44STomer Tayar if (is_storm) { 3069c965db44STomer Tayar strcpy(buf, "?STORM_"); 3070c965db44STomer Tayar buf[0] = storm_letter; 3071c965db44STomer Tayar strcpy(buf + strlen(buf), name); 3072c965db44STomer Tayar } else { 3073c965db44STomer Tayar strcpy(buf, name); 3074c965db44STomer Tayar } 3075c965db44STomer Tayar 3076c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 3077c965db44STomer Tayar dump, "name", buf); 3078c965db44STomer Tayar } else { 3079c965db44STomer Tayar /* Dump address */ 30807b6859fbSMintz, Yuval u32 addr_in_bytes = DWORDS_TO_BYTES(addr); 30817b6859fbSMintz, Yuval 3082c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 30837b6859fbSMintz, Yuval dump, "addr", addr_in_bytes); 3084c965db44STomer Tayar } 3085c965db44STomer Tayar 3086c965db44STomer Tayar /* Dump len */ 3087be086e7cSMintz, Yuval offset += qed_dump_num_param(dump_buf + offset, dump, "len", len); 3088c965db44STomer Tayar 3089c965db44STomer Tayar /* Dump bit width */ 3090c965db44STomer Tayar if (bit_width) 3091c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 3092c965db44STomer Tayar dump, "width", bit_width); 3093c965db44STomer Tayar 3094c965db44STomer Tayar /* Dump packed */ 3095c965db44STomer Tayar if (packed) 3096c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 3097c965db44STomer Tayar dump, "packed", 1); 3098c965db44STomer Tayar 3099c965db44STomer Tayar /* Dump reg type */ 3100c965db44STomer Tayar if (is_storm) { 3101c965db44STomer Tayar strcpy(buf, "?STORM_"); 3102c965db44STomer Tayar buf[0] = storm_letter; 3103c965db44STomer Tayar strcpy(buf + strlen(buf), mem_group); 3104c965db44STomer Tayar } else { 3105c965db44STomer Tayar strcpy(buf, mem_group); 3106c965db44STomer Tayar } 3107c965db44STomer Tayar 3108c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, dump, "type", buf); 31097b6859fbSMintz, Yuval 3110c965db44STomer Tayar return offset; 3111c965db44STomer Tayar } 3112c965db44STomer Tayar 3113c965db44STomer Tayar /* Dumps a single GRC memory. If name is NULL, the memory is stored by address. 3114c965db44STomer Tayar * Returns the dumped size in dwords. 31157b6859fbSMintz, Yuval * The addr and len arguments are specified in dwords. 3116c965db44STomer Tayar */ 3117c965db44STomer Tayar static u32 qed_grc_dump_mem(struct qed_hwfn *p_hwfn, 3118c965db44STomer Tayar struct qed_ptt *p_ptt, 3119c965db44STomer Tayar u32 *dump_buf, 3120c965db44STomer Tayar bool dump, 3121c965db44STomer Tayar const char *name, 3122be086e7cSMintz, Yuval u32 addr, 3123be086e7cSMintz, Yuval u32 len, 31247b6859fbSMintz, Yuval bool wide_bus, 3125c965db44STomer Tayar u32 bit_width, 3126c965db44STomer Tayar bool packed, 3127c965db44STomer Tayar const char *mem_group, 3128c965db44STomer Tayar bool is_storm, char storm_letter) 3129c965db44STomer Tayar { 3130c965db44STomer Tayar u32 offset = 0; 3131c965db44STomer Tayar 3132c965db44STomer Tayar offset += qed_grc_dump_mem_hdr(p_hwfn, 3133c965db44STomer Tayar dump_buf + offset, 3134c965db44STomer Tayar dump, 3135c965db44STomer Tayar name, 3136be086e7cSMintz, Yuval addr, 3137be086e7cSMintz, Yuval len, 3138c965db44STomer Tayar bit_width, 3139c965db44STomer Tayar packed, 3140c965db44STomer Tayar mem_group, is_storm, storm_letter); 3141be086e7cSMintz, Yuval offset += qed_grc_dump_addr_range(p_hwfn, 3142be086e7cSMintz, Yuval p_ptt, 31437b6859fbSMintz, Yuval dump_buf + offset, 3144d52c89f1SMichal Kalderon dump, addr, len, wide_bus, 3145d52c89f1SMichal Kalderon SPLIT_TYPE_NONE, 0); 31467b6859fbSMintz, Yuval 3147c965db44STomer Tayar return offset; 3148c965db44STomer Tayar } 3149c965db44STomer Tayar 3150c965db44STomer Tayar /* Dumps GRC memories entries. Returns the dumped size in dwords. */ 3151c965db44STomer Tayar static u32 qed_grc_dump_mem_entries(struct qed_hwfn *p_hwfn, 3152c965db44STomer Tayar struct qed_ptt *p_ptt, 3153c965db44STomer Tayar struct dbg_array input_mems_arr, 3154c965db44STomer Tayar u32 *dump_buf, bool dump) 3155c965db44STomer Tayar { 3156c965db44STomer Tayar u32 i, offset = 0, input_offset = 0; 3157c965db44STomer Tayar bool mode_match = true; 3158c965db44STomer Tayar 3159c965db44STomer Tayar while (input_offset < input_mems_arr.size_in_dwords) { 3160c965db44STomer Tayar const struct dbg_dump_cond_hdr *cond_hdr; 31617b6859fbSMintz, Yuval u16 modes_buf_offset; 3162c965db44STomer Tayar u32 num_entries; 3163c965db44STomer Tayar bool eval_mode; 3164c965db44STomer Tayar 3165c965db44STomer Tayar cond_hdr = (const struct dbg_dump_cond_hdr *) 3166c965db44STomer Tayar &input_mems_arr.ptr[input_offset++]; 31677b6859fbSMintz, Yuval num_entries = cond_hdr->data_size / MEM_DUMP_ENTRY_SIZE_DWORDS; 3168c965db44STomer Tayar 3169c965db44STomer Tayar /* Check required mode */ 31707b6859fbSMintz, Yuval eval_mode = GET_FIELD(cond_hdr->mode.data, 31717b6859fbSMintz, Yuval DBG_MODE_HDR_EVAL_MODE) > 0; 3172c965db44STomer Tayar if (eval_mode) { 31737b6859fbSMintz, Yuval modes_buf_offset = 3174c965db44STomer Tayar GET_FIELD(cond_hdr->mode.data, 3175c965db44STomer Tayar DBG_MODE_HDR_MODES_BUF_OFFSET); 3176c965db44STomer Tayar mode_match = qed_is_mode_match(p_hwfn, 3177c965db44STomer Tayar &modes_buf_offset); 3178c965db44STomer Tayar } 3179c965db44STomer Tayar 3180c965db44STomer Tayar if (!mode_match) { 3181c965db44STomer Tayar input_offset += cond_hdr->data_size; 3182c965db44STomer Tayar continue; 3183c965db44STomer Tayar } 3184c965db44STomer Tayar 3185c965db44STomer Tayar for (i = 0; i < num_entries; 3186c965db44STomer Tayar i++, input_offset += MEM_DUMP_ENTRY_SIZE_DWORDS) { 3187c965db44STomer Tayar const struct dbg_dump_mem *mem = 3188c965db44STomer Tayar (const struct dbg_dump_mem *) 3189c965db44STomer Tayar &input_mems_arr.ptr[input_offset]; 31907b6859fbSMintz, Yuval u8 mem_group_id = GET_FIELD(mem->dword0, 3191c965db44STomer Tayar DBG_DUMP_MEM_MEM_GROUP_ID); 31927b6859fbSMintz, Yuval bool is_storm = false, mem_wide_bus; 31937b6859fbSMintz, Yuval enum dbg_grc_params grc_param; 31947b6859fbSMintz, Yuval char storm_letter = 'a'; 31957b6859fbSMintz, Yuval enum block_id block_id; 31967b6859fbSMintz, Yuval u32 mem_addr, mem_len; 31977b6859fbSMintz, Yuval 3198c965db44STomer Tayar if (mem_group_id >= MEM_GROUPS_NUM) { 3199c965db44STomer Tayar DP_NOTICE(p_hwfn, "Invalid mem_group_id\n"); 3200c965db44STomer Tayar return 0; 3201c965db44STomer Tayar } 3202c965db44STomer Tayar 32037b6859fbSMintz, Yuval block_id = (enum block_id)cond_hdr->block_id; 32047b6859fbSMintz, Yuval if (!qed_grc_is_mem_included(p_hwfn, 32057b6859fbSMintz, Yuval block_id, 32067b6859fbSMintz, Yuval mem_group_id)) 32077b6859fbSMintz, Yuval continue; 32087b6859fbSMintz, Yuval 32097b6859fbSMintz, Yuval mem_addr = GET_FIELD(mem->dword0, DBG_DUMP_MEM_ADDRESS); 32107b6859fbSMintz, Yuval mem_len = GET_FIELD(mem->dword1, DBG_DUMP_MEM_LENGTH); 32117b6859fbSMintz, Yuval mem_wide_bus = GET_FIELD(mem->dword1, 32127b6859fbSMintz, Yuval DBG_DUMP_MEM_WIDE_BUS); 3213c965db44STomer Tayar 3214c965db44STomer Tayar /* Update memory length for CCFC/TCFC memories 3215c965db44STomer Tayar * according to number of LCIDs/LTIDs. 3216c965db44STomer Tayar */ 3217be086e7cSMintz, Yuval if (mem_group_id == MEM_GROUP_CONN_CFC_MEM) { 32187b6859fbSMintz, Yuval if (mem_len % MAX_LCIDS) { 3219be086e7cSMintz, Yuval DP_NOTICE(p_hwfn, 3220be086e7cSMintz, Yuval "Invalid CCFC connection memory size\n"); 3221be086e7cSMintz, Yuval return 0; 3222be086e7cSMintz, Yuval } 3223be086e7cSMintz, Yuval 3224be086e7cSMintz, Yuval grc_param = DBG_GRC_PARAM_NUM_LCIDS; 32257b6859fbSMintz, Yuval mem_len = qed_grc_get_param(p_hwfn, grc_param) * 3226be086e7cSMintz, Yuval (mem_len / MAX_LCIDS); 32277b6859fbSMintz, Yuval } else if (mem_group_id == MEM_GROUP_TASK_CFC_MEM) { 32287b6859fbSMintz, Yuval if (mem_len % MAX_LTIDS) { 3229be086e7cSMintz, Yuval DP_NOTICE(p_hwfn, 3230be086e7cSMintz, Yuval "Invalid TCFC task memory size\n"); 3231be086e7cSMintz, Yuval return 0; 3232be086e7cSMintz, Yuval } 3233be086e7cSMintz, Yuval 3234be086e7cSMintz, Yuval grc_param = DBG_GRC_PARAM_NUM_LTIDS; 32357b6859fbSMintz, Yuval mem_len = qed_grc_get_param(p_hwfn, grc_param) * 3236be086e7cSMintz, Yuval (mem_len / MAX_LTIDS); 3237be086e7cSMintz, Yuval } 3238c965db44STomer Tayar 32397b6859fbSMintz, Yuval /* If memory is associated with Storm, update Storm 32407b6859fbSMintz, Yuval * details. 3241c965db44STomer Tayar */ 32427b6859fbSMintz, Yuval if (s_block_defs 32437b6859fbSMintz, Yuval [cond_hdr->block_id]->associated_to_storm) { 3244c965db44STomer Tayar is_storm = true; 3245c965db44STomer Tayar storm_letter = 32467b6859fbSMintz, Yuval s_storm_defs[s_block_defs 32477b6859fbSMintz, Yuval [cond_hdr->block_id]-> 3248c965db44STomer Tayar storm_id].letter; 3249c965db44STomer Tayar } 3250c965db44STomer Tayar 3251c965db44STomer Tayar /* Dump memory */ 32527b6859fbSMintz, Yuval offset += qed_grc_dump_mem(p_hwfn, 32537b6859fbSMintz, Yuval p_ptt, 32547b6859fbSMintz, Yuval dump_buf + offset, 32557b6859fbSMintz, Yuval dump, 32567b6859fbSMintz, Yuval NULL, 32577b6859fbSMintz, Yuval mem_addr, 32587b6859fbSMintz, Yuval mem_len, 32597b6859fbSMintz, Yuval mem_wide_bus, 32607b6859fbSMintz, Yuval 0, 3261c965db44STomer Tayar false, 3262c965db44STomer Tayar s_mem_group_names[mem_group_id], 32637b6859fbSMintz, Yuval is_storm, 32647b6859fbSMintz, Yuval storm_letter); 3265c965db44STomer Tayar } 3266c965db44STomer Tayar } 3267c965db44STomer Tayar 3268c965db44STomer Tayar return offset; 3269c965db44STomer Tayar } 3270c965db44STomer Tayar 3271c965db44STomer Tayar /* Dumps GRC memories according to the input array dump_mem. 3272c965db44STomer Tayar * Returns the dumped size in dwords. 3273c965db44STomer Tayar */ 3274c965db44STomer Tayar static u32 qed_grc_dump_memories(struct qed_hwfn *p_hwfn, 3275c965db44STomer Tayar struct qed_ptt *p_ptt, 3276c965db44STomer Tayar u32 *dump_buf, bool dump) 3277c965db44STomer Tayar { 3278c965db44STomer Tayar u32 offset = 0, input_offset = 0; 3279c965db44STomer Tayar 3280c965db44STomer Tayar while (input_offset < 3281c965db44STomer Tayar s_dbg_arrays[BIN_BUF_DBG_DUMP_MEM].size_in_dwords) { 32827b6859fbSMintz, Yuval const struct dbg_dump_split_hdr *split_hdr; 32837b6859fbSMintz, Yuval struct dbg_array curr_input_mems_arr; 3284d52c89f1SMichal Kalderon enum init_split_types split_type; 32857b6859fbSMintz, Yuval u32 split_data_size; 32867b6859fbSMintz, Yuval 32877b6859fbSMintz, Yuval split_hdr = (const struct dbg_dump_split_hdr *) 3288c965db44STomer Tayar &s_dbg_arrays[BIN_BUF_DBG_DUMP_MEM].ptr[input_offset++]; 3289d52c89f1SMichal Kalderon split_type = 32907b6859fbSMintz, Yuval GET_FIELD(split_hdr->hdr, 3291c965db44STomer Tayar DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID); 32927b6859fbSMintz, Yuval split_data_size = 32937b6859fbSMintz, Yuval GET_FIELD(split_hdr->hdr, 3294c965db44STomer Tayar DBG_DUMP_SPLIT_HDR_DATA_SIZE); 32957b6859fbSMintz, Yuval curr_input_mems_arr.ptr = 32967b6859fbSMintz, Yuval &s_dbg_arrays[BIN_BUF_DBG_DUMP_MEM].ptr[input_offset]; 32977b6859fbSMintz, Yuval curr_input_mems_arr.size_in_dwords = split_data_size; 3298c965db44STomer Tayar 3299d52c89f1SMichal Kalderon if (split_type == SPLIT_TYPE_NONE) 3300c965db44STomer Tayar offset += qed_grc_dump_mem_entries(p_hwfn, 3301c965db44STomer Tayar p_ptt, 3302c965db44STomer Tayar curr_input_mems_arr, 3303c965db44STomer Tayar dump_buf + offset, 3304c965db44STomer Tayar dump); 3305d52c89f1SMichal Kalderon else 3306c965db44STomer Tayar DP_NOTICE(p_hwfn, 3307c965db44STomer Tayar "Dumping split memories is currently not supported\n"); 3308c965db44STomer Tayar 3309c965db44STomer Tayar input_offset += split_data_size; 3310c965db44STomer Tayar } 3311c965db44STomer Tayar 3312c965db44STomer Tayar return offset; 3313c965db44STomer Tayar } 3314c965db44STomer Tayar 3315c965db44STomer Tayar /* Dumps GRC context data for the specified Storm. 3316c965db44STomer Tayar * Returns the dumped size in dwords. 33177b6859fbSMintz, Yuval * The lid_size argument is specified in quad-regs. 3318c965db44STomer Tayar */ 3319c965db44STomer Tayar static u32 qed_grc_dump_ctx_data(struct qed_hwfn *p_hwfn, 3320c965db44STomer Tayar struct qed_ptt *p_ptt, 3321c965db44STomer Tayar u32 *dump_buf, 3322c965db44STomer Tayar bool dump, 3323c965db44STomer Tayar const char *name, 3324c965db44STomer Tayar u32 num_lids, 3325c965db44STomer Tayar u32 lid_size, 3326c965db44STomer Tayar u32 rd_reg_addr, 3327c965db44STomer Tayar u8 storm_id) 3328c965db44STomer Tayar { 33297b6859fbSMintz, Yuval struct storm_defs *storm = &s_storm_defs[storm_id]; 33307b6859fbSMintz, Yuval u32 i, lid, total_size, offset = 0; 3331c965db44STomer Tayar 3332c965db44STomer Tayar if (!lid_size) 3333c965db44STomer Tayar return 0; 33347b6859fbSMintz, Yuval 3335c965db44STomer Tayar lid_size *= BYTES_IN_DWORD; 3336c965db44STomer Tayar total_size = num_lids * lid_size; 33377b6859fbSMintz, Yuval 3338c965db44STomer Tayar offset += qed_grc_dump_mem_hdr(p_hwfn, 3339c965db44STomer Tayar dump_buf + offset, 3340c965db44STomer Tayar dump, 3341c965db44STomer Tayar name, 3342c965db44STomer Tayar 0, 3343c965db44STomer Tayar total_size, 3344c965db44STomer Tayar lid_size * 32, 33457b6859fbSMintz, Yuval false, name, true, storm->letter); 33467b6859fbSMintz, Yuval 33477b6859fbSMintz, Yuval if (!dump) 33487b6859fbSMintz, Yuval return offset + total_size; 3349c965db44STomer Tayar 3350c965db44STomer Tayar /* Dump context data */ 3351c965db44STomer Tayar for (lid = 0; lid < num_lids; lid++) { 3352c965db44STomer Tayar for (i = 0; i < lid_size; i++, offset++) { 3353c965db44STomer Tayar qed_wr(p_hwfn, 33547b6859fbSMintz, Yuval p_ptt, storm->cm_ctx_wr_addr, (i << 9) | lid); 3355c965db44STomer Tayar *(dump_buf + offset) = qed_rd(p_hwfn, 33567b6859fbSMintz, Yuval p_ptt, rd_reg_addr); 3357c965db44STomer Tayar } 3358c965db44STomer Tayar } 3359c965db44STomer Tayar 3360c965db44STomer Tayar return offset; 3361c965db44STomer Tayar } 3362c965db44STomer Tayar 3363c965db44STomer Tayar /* Dumps GRC contexts. Returns the dumped size in dwords. */ 3364c965db44STomer Tayar static u32 qed_grc_dump_ctx(struct qed_hwfn *p_hwfn, 3365c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *dump_buf, bool dump) 3366c965db44STomer Tayar { 33677b6859fbSMintz, Yuval enum dbg_grc_params grc_param; 3368c965db44STomer Tayar u32 offset = 0; 3369c965db44STomer Tayar u8 storm_id; 3370c965db44STomer Tayar 3371c965db44STomer Tayar for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 33727b6859fbSMintz, Yuval struct storm_defs *storm = &s_storm_defs[storm_id]; 33737b6859fbSMintz, Yuval 3374c965db44STomer Tayar if (!qed_grc_is_storm_included(p_hwfn, 3375c965db44STomer Tayar (enum dbg_storms)storm_id)) 3376c965db44STomer Tayar continue; 3377c965db44STomer Tayar 3378c965db44STomer Tayar /* Dump Conn AG context size */ 33797b6859fbSMintz, Yuval grc_param = DBG_GRC_PARAM_NUM_LCIDS; 3380c965db44STomer Tayar offset += 3381c965db44STomer Tayar qed_grc_dump_ctx_data(p_hwfn, 3382c965db44STomer Tayar p_ptt, 3383c965db44STomer Tayar dump_buf + offset, 3384c965db44STomer Tayar dump, 3385c965db44STomer Tayar "CONN_AG_CTX", 3386c965db44STomer Tayar qed_grc_get_param(p_hwfn, 33877b6859fbSMintz, Yuval grc_param), 33887b6859fbSMintz, Yuval storm->cm_conn_ag_ctx_lid_size, 33897b6859fbSMintz, Yuval storm->cm_conn_ag_ctx_rd_addr, 3390c965db44STomer Tayar storm_id); 3391c965db44STomer Tayar 3392c965db44STomer Tayar /* Dump Conn ST context size */ 33937b6859fbSMintz, Yuval grc_param = DBG_GRC_PARAM_NUM_LCIDS; 3394c965db44STomer Tayar offset += 3395c965db44STomer Tayar qed_grc_dump_ctx_data(p_hwfn, 3396c965db44STomer Tayar p_ptt, 3397c965db44STomer Tayar dump_buf + offset, 3398c965db44STomer Tayar dump, 3399c965db44STomer Tayar "CONN_ST_CTX", 3400c965db44STomer Tayar qed_grc_get_param(p_hwfn, 34017b6859fbSMintz, Yuval grc_param), 34027b6859fbSMintz, Yuval storm->cm_conn_st_ctx_lid_size, 34037b6859fbSMintz, Yuval storm->cm_conn_st_ctx_rd_addr, 3404c965db44STomer Tayar storm_id); 3405c965db44STomer Tayar 3406c965db44STomer Tayar /* Dump Task AG context size */ 34077b6859fbSMintz, Yuval grc_param = DBG_GRC_PARAM_NUM_LTIDS; 3408c965db44STomer Tayar offset += 3409c965db44STomer Tayar qed_grc_dump_ctx_data(p_hwfn, 3410c965db44STomer Tayar p_ptt, 3411c965db44STomer Tayar dump_buf + offset, 3412c965db44STomer Tayar dump, 3413c965db44STomer Tayar "TASK_AG_CTX", 3414c965db44STomer Tayar qed_grc_get_param(p_hwfn, 34157b6859fbSMintz, Yuval grc_param), 34167b6859fbSMintz, Yuval storm->cm_task_ag_ctx_lid_size, 34177b6859fbSMintz, Yuval storm->cm_task_ag_ctx_rd_addr, 3418c965db44STomer Tayar storm_id); 3419c965db44STomer Tayar 3420c965db44STomer Tayar /* Dump Task ST context size */ 34217b6859fbSMintz, Yuval grc_param = DBG_GRC_PARAM_NUM_LTIDS; 3422c965db44STomer Tayar offset += 3423c965db44STomer Tayar qed_grc_dump_ctx_data(p_hwfn, 3424c965db44STomer Tayar p_ptt, 3425c965db44STomer Tayar dump_buf + offset, 3426c965db44STomer Tayar dump, 3427c965db44STomer Tayar "TASK_ST_CTX", 3428c965db44STomer Tayar qed_grc_get_param(p_hwfn, 34297b6859fbSMintz, Yuval grc_param), 34307b6859fbSMintz, Yuval storm->cm_task_st_ctx_lid_size, 34317b6859fbSMintz, Yuval storm->cm_task_st_ctx_rd_addr, 3432c965db44STomer Tayar storm_id); 3433c965db44STomer Tayar } 3434c965db44STomer Tayar 3435c965db44STomer Tayar return offset; 3436c965db44STomer Tayar } 3437c965db44STomer Tayar 3438c965db44STomer Tayar /* Dumps GRC IORs data. Returns the dumped size in dwords. */ 3439c965db44STomer Tayar static u32 qed_grc_dump_iors(struct qed_hwfn *p_hwfn, 3440c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *dump_buf, bool dump) 3441c965db44STomer Tayar { 3442c965db44STomer Tayar char buf[10] = "IOR_SET_?"; 34437b6859fbSMintz, Yuval u32 addr, offset = 0; 3444c965db44STomer Tayar u8 storm_id, set_id; 3445c965db44STomer Tayar 3446c965db44STomer Tayar for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 3447be086e7cSMintz, Yuval struct storm_defs *storm = &s_storm_defs[storm_id]; 3448c965db44STomer Tayar 3449be086e7cSMintz, Yuval if (!qed_grc_is_storm_included(p_hwfn, 3450be086e7cSMintz, Yuval (enum dbg_storms)storm_id)) 3451be086e7cSMintz, Yuval continue; 3452be086e7cSMintz, Yuval 3453be086e7cSMintz, Yuval for (set_id = 0; set_id < NUM_IOR_SETS; set_id++) { 34547b6859fbSMintz, Yuval addr = BYTES_TO_DWORDS(storm->sem_fast_mem_addr + 34557b6859fbSMintz, Yuval SEM_FAST_REG_STORM_REG_FILE) + 34567b6859fbSMintz, Yuval IOR_SET_OFFSET(set_id); 3457c965db44STomer Tayar buf[strlen(buf) - 1] = '0' + set_id; 3458c965db44STomer Tayar offset += qed_grc_dump_mem(p_hwfn, 3459c965db44STomer Tayar p_ptt, 3460c965db44STomer Tayar dump_buf + offset, 3461c965db44STomer Tayar dump, 3462c965db44STomer Tayar buf, 3463c965db44STomer Tayar addr, 3464c965db44STomer Tayar IORS_PER_SET, 34657b6859fbSMintz, Yuval false, 3466c965db44STomer Tayar 32, 3467c965db44STomer Tayar false, 3468c965db44STomer Tayar "ior", 3469c965db44STomer Tayar true, 3470be086e7cSMintz, Yuval storm->letter); 3471c965db44STomer Tayar } 3472c965db44STomer Tayar } 3473c965db44STomer Tayar 3474c965db44STomer Tayar return offset; 3475c965db44STomer Tayar } 3476c965db44STomer Tayar 3477c965db44STomer Tayar /* Dump VFC CAM. Returns the dumped size in dwords. */ 3478c965db44STomer Tayar static u32 qed_grc_dump_vfc_cam(struct qed_hwfn *p_hwfn, 3479c965db44STomer Tayar struct qed_ptt *p_ptt, 3480c965db44STomer Tayar u32 *dump_buf, bool dump, u8 storm_id) 3481c965db44STomer Tayar { 3482c965db44STomer Tayar u32 total_size = VFC_CAM_NUM_ROWS * VFC_CAM_RESP_DWORDS; 34837b6859fbSMintz, Yuval struct storm_defs *storm = &s_storm_defs[storm_id]; 3484c965db44STomer Tayar u32 cam_addr[VFC_CAM_ADDR_DWORDS] = { 0 }; 3485c965db44STomer Tayar u32 cam_cmd[VFC_CAM_CMD_DWORDS] = { 0 }; 34867b6859fbSMintz, Yuval u32 row, i, offset = 0; 3487c965db44STomer Tayar 3488c965db44STomer Tayar offset += qed_grc_dump_mem_hdr(p_hwfn, 3489c965db44STomer Tayar dump_buf + offset, 3490c965db44STomer Tayar dump, 3491c965db44STomer Tayar "vfc_cam", 3492c965db44STomer Tayar 0, 3493c965db44STomer Tayar total_size, 3494c965db44STomer Tayar 256, 34957b6859fbSMintz, Yuval false, "vfc_cam", true, storm->letter); 34967b6859fbSMintz, Yuval 34977b6859fbSMintz, Yuval if (!dump) 34987b6859fbSMintz, Yuval return offset + total_size; 34997b6859fbSMintz, Yuval 3500c965db44STomer Tayar /* Prepare CAM address */ 3501c965db44STomer Tayar SET_VAR_FIELD(cam_addr, VFC_CAM_ADDR, OP, VFC_OPCODE_CAM_RD); 35027b6859fbSMintz, Yuval 3503c965db44STomer Tayar for (row = 0; row < VFC_CAM_NUM_ROWS; 3504c965db44STomer Tayar row++, offset += VFC_CAM_RESP_DWORDS) { 3505c965db44STomer Tayar /* Write VFC CAM command */ 3506c965db44STomer Tayar SET_VAR_FIELD(cam_cmd, VFC_CAM_CMD, ROW, row); 3507c965db44STomer Tayar ARR_REG_WR(p_hwfn, 3508c965db44STomer Tayar p_ptt, 35097b6859fbSMintz, Yuval storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_WR, 3510c965db44STomer Tayar cam_cmd, VFC_CAM_CMD_DWORDS); 3511c965db44STomer Tayar 3512c965db44STomer Tayar /* Write VFC CAM address */ 3513c965db44STomer Tayar ARR_REG_WR(p_hwfn, 3514c965db44STomer Tayar p_ptt, 35157b6859fbSMintz, Yuval storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_ADDR, 3516c965db44STomer Tayar cam_addr, VFC_CAM_ADDR_DWORDS); 3517c965db44STomer Tayar 3518c965db44STomer Tayar /* Read VFC CAM read response */ 3519c965db44STomer Tayar ARR_REG_RD(p_hwfn, 3520c965db44STomer Tayar p_ptt, 35217b6859fbSMintz, Yuval storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_RD, 3522c965db44STomer Tayar dump_buf + offset, VFC_CAM_RESP_DWORDS); 3523c965db44STomer Tayar } 3524c965db44STomer Tayar 3525c965db44STomer Tayar return offset; 3526c965db44STomer Tayar } 3527c965db44STomer Tayar 3528c965db44STomer Tayar /* Dump VFC RAM. Returns the dumped size in dwords. */ 3529c965db44STomer Tayar static u32 qed_grc_dump_vfc_ram(struct qed_hwfn *p_hwfn, 3530c965db44STomer Tayar struct qed_ptt *p_ptt, 3531c965db44STomer Tayar u32 *dump_buf, 3532c965db44STomer Tayar bool dump, 3533c965db44STomer Tayar u8 storm_id, struct vfc_ram_defs *ram_defs) 3534c965db44STomer Tayar { 3535c965db44STomer Tayar u32 total_size = ram_defs->num_rows * VFC_RAM_RESP_DWORDS; 35367b6859fbSMintz, Yuval struct storm_defs *storm = &s_storm_defs[storm_id]; 3537c965db44STomer Tayar u32 ram_addr[VFC_RAM_ADDR_DWORDS] = { 0 }; 3538c965db44STomer Tayar u32 ram_cmd[VFC_RAM_CMD_DWORDS] = { 0 }; 35397b6859fbSMintz, Yuval u32 row, i, offset = 0; 3540c965db44STomer Tayar 3541c965db44STomer Tayar offset += qed_grc_dump_mem_hdr(p_hwfn, 3542c965db44STomer Tayar dump_buf + offset, 3543c965db44STomer Tayar dump, 3544c965db44STomer Tayar ram_defs->mem_name, 3545c965db44STomer Tayar 0, 3546c965db44STomer Tayar total_size, 3547c965db44STomer Tayar 256, 3548c965db44STomer Tayar false, 3549c965db44STomer Tayar ram_defs->type_name, 35507b6859fbSMintz, Yuval true, storm->letter); 3551c965db44STomer Tayar 3552c965db44STomer Tayar /* Prepare RAM address */ 3553c965db44STomer Tayar SET_VAR_FIELD(ram_addr, VFC_RAM_ADDR, OP, VFC_OPCODE_RAM_RD); 3554c965db44STomer Tayar 3555c965db44STomer Tayar if (!dump) 3556c965db44STomer Tayar return offset + total_size; 3557c965db44STomer Tayar 3558c965db44STomer Tayar for (row = ram_defs->base_row; 3559c965db44STomer Tayar row < ram_defs->base_row + ram_defs->num_rows; 3560c965db44STomer Tayar row++, offset += VFC_RAM_RESP_DWORDS) { 3561c965db44STomer Tayar /* Write VFC RAM command */ 3562c965db44STomer Tayar ARR_REG_WR(p_hwfn, 3563c965db44STomer Tayar p_ptt, 35647b6859fbSMintz, Yuval storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_WR, 3565c965db44STomer Tayar ram_cmd, VFC_RAM_CMD_DWORDS); 3566c965db44STomer Tayar 3567c965db44STomer Tayar /* Write VFC RAM address */ 3568c965db44STomer Tayar SET_VAR_FIELD(ram_addr, VFC_RAM_ADDR, ROW, row); 3569c965db44STomer Tayar ARR_REG_WR(p_hwfn, 3570c965db44STomer Tayar p_ptt, 35717b6859fbSMintz, Yuval storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_ADDR, 3572c965db44STomer Tayar ram_addr, VFC_RAM_ADDR_DWORDS); 3573c965db44STomer Tayar 3574c965db44STomer Tayar /* Read VFC RAM read response */ 3575c965db44STomer Tayar ARR_REG_RD(p_hwfn, 3576c965db44STomer Tayar p_ptt, 35777b6859fbSMintz, Yuval storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_RD, 3578c965db44STomer Tayar dump_buf + offset, VFC_RAM_RESP_DWORDS); 3579c965db44STomer Tayar } 3580c965db44STomer Tayar 3581c965db44STomer Tayar return offset; 3582c965db44STomer Tayar } 3583c965db44STomer Tayar 3584c965db44STomer Tayar /* Dumps GRC VFC data. Returns the dumped size in dwords. */ 3585c965db44STomer Tayar static u32 qed_grc_dump_vfc(struct qed_hwfn *p_hwfn, 3586c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *dump_buf, bool dump) 3587c965db44STomer Tayar { 3588c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 3589c965db44STomer Tayar u8 storm_id, i; 3590c965db44STomer Tayar u32 offset = 0; 3591c965db44STomer Tayar 3592c965db44STomer Tayar for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 35937b6859fbSMintz, Yuval if (!qed_grc_is_storm_included(p_hwfn, 35947b6859fbSMintz, Yuval (enum dbg_storms)storm_id) || 35957b6859fbSMintz, Yuval !s_storm_defs[storm_id].has_vfc || 35967b6859fbSMintz, Yuval (storm_id == DBG_PSTORM_ID && dev_data->platform_id != 35977b6859fbSMintz, Yuval PLATFORM_ASIC)) 35987b6859fbSMintz, Yuval continue; 35997b6859fbSMintz, Yuval 3600c965db44STomer Tayar /* Read CAM */ 3601c965db44STomer Tayar offset += qed_grc_dump_vfc_cam(p_hwfn, 3602c965db44STomer Tayar p_ptt, 3603c965db44STomer Tayar dump_buf + offset, 3604c965db44STomer Tayar dump, storm_id); 3605c965db44STomer Tayar 3606c965db44STomer Tayar /* Read RAM */ 3607c965db44STomer Tayar for (i = 0; i < NUM_VFC_RAM_TYPES; i++) 3608c965db44STomer Tayar offset += qed_grc_dump_vfc_ram(p_hwfn, 3609c965db44STomer Tayar p_ptt, 36107b6859fbSMintz, Yuval dump_buf + offset, 3611c965db44STomer Tayar dump, 3612c965db44STomer Tayar storm_id, 36137b6859fbSMintz, Yuval &s_vfc_ram_defs[i]); 3614c965db44STomer Tayar } 3615c965db44STomer Tayar 3616c965db44STomer Tayar return offset; 3617c965db44STomer Tayar } 3618c965db44STomer Tayar 3619c965db44STomer Tayar /* Dumps GRC RSS data. Returns the dumped size in dwords. */ 3620c965db44STomer Tayar static u32 qed_grc_dump_rss(struct qed_hwfn *p_hwfn, 3621c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *dump_buf, bool dump) 3622c965db44STomer Tayar { 3623c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 3624c965db44STomer Tayar u32 offset = 0; 3625c965db44STomer Tayar u8 rss_mem_id; 3626c965db44STomer Tayar 3627c965db44STomer Tayar for (rss_mem_id = 0; rss_mem_id < NUM_RSS_MEM_TYPES; rss_mem_id++) { 3628da090917STomer Tayar u32 rss_addr, num_entries, total_dwords; 36297b6859fbSMintz, Yuval struct rss_mem_defs *rss_defs; 3630da090917STomer Tayar u32 addr, num_dwords_to_read; 36317b6859fbSMintz, Yuval bool packed; 36327b6859fbSMintz, Yuval 36337b6859fbSMintz, Yuval rss_defs = &s_rss_mem_defs[rss_mem_id]; 36347b6859fbSMintz, Yuval rss_addr = rss_defs->addr; 36357b6859fbSMintz, Yuval num_entries = rss_defs->num_entries[dev_data->chip_id]; 3636da090917STomer Tayar total_dwords = (num_entries * rss_defs->entry_width) / 32; 3637da090917STomer Tayar packed = (rss_defs->entry_width == 16); 3638c965db44STomer Tayar 3639c965db44STomer Tayar offset += qed_grc_dump_mem_hdr(p_hwfn, 3640c965db44STomer Tayar dump_buf + offset, 3641c965db44STomer Tayar dump, 3642c965db44STomer Tayar rss_defs->mem_name, 3643be086e7cSMintz, Yuval 0, 3644be086e7cSMintz, Yuval total_dwords, 3645da090917STomer Tayar rss_defs->entry_width, 3646c965db44STomer Tayar packed, 3647c965db44STomer Tayar rss_defs->type_name, false, 0); 3648c965db44STomer Tayar 36497b6859fbSMintz, Yuval /* Dump RSS data */ 3650c965db44STomer Tayar if (!dump) { 3651be086e7cSMintz, Yuval offset += total_dwords; 3652c965db44STomer Tayar continue; 3653c965db44STomer Tayar } 3654c965db44STomer Tayar 3655be086e7cSMintz, Yuval addr = BYTES_TO_DWORDS(RSS_REG_RSS_RAM_DATA); 3656da090917STomer Tayar while (total_dwords) { 3657da090917STomer Tayar num_dwords_to_read = min_t(u32, 3658da090917STomer Tayar RSS_REG_RSS_RAM_DATA_SIZE, 3659da090917STomer Tayar total_dwords); 3660be086e7cSMintz, Yuval qed_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_ADDR, rss_addr); 3661be086e7cSMintz, Yuval offset += qed_grc_dump_addr_range(p_hwfn, 3662be086e7cSMintz, Yuval p_ptt, 36637b6859fbSMintz, Yuval dump_buf + offset, 3664be086e7cSMintz, Yuval dump, 3665be086e7cSMintz, Yuval addr, 3666da090917STomer Tayar num_dwords_to_read, 3667d52c89f1SMichal Kalderon false, 3668d52c89f1SMichal Kalderon SPLIT_TYPE_NONE, 0); 3669da090917STomer Tayar total_dwords -= num_dwords_to_read; 3670da090917STomer Tayar rss_addr++; 3671c965db44STomer Tayar } 3672c965db44STomer Tayar } 3673c965db44STomer Tayar 3674c965db44STomer Tayar return offset; 3675c965db44STomer Tayar } 3676c965db44STomer Tayar 3677c965db44STomer Tayar /* Dumps GRC Big RAM. Returns the dumped size in dwords. */ 3678c965db44STomer Tayar static u32 qed_grc_dump_big_ram(struct qed_hwfn *p_hwfn, 3679c965db44STomer Tayar struct qed_ptt *p_ptt, 3680c965db44STomer Tayar u32 *dump_buf, bool dump, u8 big_ram_id) 3681c965db44STomer Tayar { 3682c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 3683da090917STomer Tayar u32 block_size, ram_size, offset = 0, reg_val, i; 3684c965db44STomer Tayar char mem_name[12] = "???_BIG_RAM"; 3685c965db44STomer Tayar char type_name[8] = "???_RAM"; 3686be086e7cSMintz, Yuval struct big_ram_defs *big_ram; 3687c965db44STomer Tayar 3688be086e7cSMintz, Yuval big_ram = &s_big_ram_defs[big_ram_id]; 3689da090917STomer Tayar ram_size = big_ram->ram_size[dev_data->chip_id]; 3690da090917STomer Tayar 3691da090917STomer Tayar reg_val = qed_rd(p_hwfn, p_ptt, big_ram->is_256b_reg_addr); 3692da090917STomer Tayar block_size = reg_val & 3693da090917STomer Tayar BIT(big_ram->is_256b_bit_offset[dev_data->chip_id]) ? 256 3694da090917STomer Tayar : 128; 3695c965db44STomer Tayar 3696c7d852e3SDenis Bolotin strncpy(type_name, big_ram->instance_name, BIG_RAM_NAME_LEN); 3697c7d852e3SDenis Bolotin strncpy(mem_name, big_ram->instance_name, BIG_RAM_NAME_LEN); 3698c965db44STomer Tayar 3699c965db44STomer Tayar /* Dump memory header */ 3700c965db44STomer Tayar offset += qed_grc_dump_mem_hdr(p_hwfn, 3701c965db44STomer Tayar dump_buf + offset, 3702c965db44STomer Tayar dump, 3703c965db44STomer Tayar mem_name, 3704c965db44STomer Tayar 0, 3705c965db44STomer Tayar ram_size, 3706da090917STomer Tayar block_size * 8, 3707c965db44STomer Tayar false, type_name, false, 0); 3708c965db44STomer Tayar 37097b6859fbSMintz, Yuval /* Read and dump Big RAM data */ 3710c965db44STomer Tayar if (!dump) 3711c965db44STomer Tayar return offset + ram_size; 3712c965db44STomer Tayar 37137b6859fbSMintz, Yuval /* Dump Big RAM */ 3714da090917STomer Tayar for (i = 0; i < DIV_ROUND_UP(ram_size, BRB_REG_BIG_RAM_DATA_SIZE); 3715da090917STomer Tayar i++) { 3716be086e7cSMintz, Yuval u32 addr, len; 3717be086e7cSMintz, Yuval 3718be086e7cSMintz, Yuval qed_wr(p_hwfn, p_ptt, big_ram->addr_reg_addr, i); 3719be086e7cSMintz, Yuval addr = BYTES_TO_DWORDS(big_ram->data_reg_addr); 3720da090917STomer Tayar len = BRB_REG_BIG_RAM_DATA_SIZE; 3721be086e7cSMintz, Yuval offset += qed_grc_dump_addr_range(p_hwfn, 3722be086e7cSMintz, Yuval p_ptt, 3723be086e7cSMintz, Yuval dump_buf + offset, 3724be086e7cSMintz, Yuval dump, 3725be086e7cSMintz, Yuval addr, 37267b6859fbSMintz, Yuval len, 3727d52c89f1SMichal Kalderon false, SPLIT_TYPE_NONE, 0); 3728c965db44STomer Tayar } 3729c965db44STomer Tayar 3730c965db44STomer Tayar return offset; 3731c965db44STomer Tayar } 3732c965db44STomer Tayar 3733c965db44STomer Tayar static u32 qed_grc_dump_mcp(struct qed_hwfn *p_hwfn, 3734c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *dump_buf, bool dump) 3735c965db44STomer Tayar { 3736c965db44STomer Tayar bool block_enable[MAX_BLOCK_ID] = { 0 }; 3737be086e7cSMintz, Yuval u32 offset = 0, addr; 3738c965db44STomer Tayar bool halted = false; 3739c965db44STomer Tayar 3740c965db44STomer Tayar /* Halt MCP */ 3741be086e7cSMintz, Yuval if (dump && !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_MCP)) { 3742c965db44STomer Tayar halted = !qed_mcp_halt(p_hwfn, p_ptt); 3743c965db44STomer Tayar if (!halted) 3744c965db44STomer Tayar DP_NOTICE(p_hwfn, "MCP halt failed!\n"); 3745c965db44STomer Tayar } 3746c965db44STomer Tayar 3747c965db44STomer Tayar /* Dump MCP scratchpad */ 3748c965db44STomer Tayar offset += qed_grc_dump_mem(p_hwfn, 3749c965db44STomer Tayar p_ptt, 3750c965db44STomer Tayar dump_buf + offset, 3751c965db44STomer Tayar dump, 3752c965db44STomer Tayar NULL, 3753be086e7cSMintz, Yuval BYTES_TO_DWORDS(MCP_REG_SCRATCH), 375421dd79e8STomer Tayar MCP_REG_SCRATCH_SIZE_BB_K2, 37557b6859fbSMintz, Yuval false, 0, false, "MCP", false, 0); 3756c965db44STomer Tayar 3757c965db44STomer Tayar /* Dump MCP cpu_reg_file */ 3758c965db44STomer Tayar offset += qed_grc_dump_mem(p_hwfn, 3759c965db44STomer Tayar p_ptt, 3760c965db44STomer Tayar dump_buf + offset, 3761c965db44STomer Tayar dump, 3762c965db44STomer Tayar NULL, 3763be086e7cSMintz, Yuval BYTES_TO_DWORDS(MCP_REG_CPU_REG_FILE), 3764c965db44STomer Tayar MCP_REG_CPU_REG_FILE_SIZE, 37657b6859fbSMintz, Yuval false, 0, false, "MCP", false, 0); 3766c965db44STomer Tayar 3767c965db44STomer Tayar /* Dump MCP registers */ 3768c965db44STomer Tayar block_enable[BLOCK_MCP] = true; 3769c965db44STomer Tayar offset += qed_grc_dump_registers(p_hwfn, 3770c965db44STomer Tayar p_ptt, 3771c965db44STomer Tayar dump_buf + offset, 3772c965db44STomer Tayar dump, block_enable, "block", "MCP"); 3773c965db44STomer Tayar 3774c965db44STomer Tayar /* Dump required non-MCP registers */ 3775c965db44STomer Tayar offset += qed_grc_dump_regs_hdr(dump_buf + offset, 3776d52c89f1SMichal Kalderon dump, 1, SPLIT_TYPE_NONE, 0, 3777d52c89f1SMichal Kalderon "block", "MCP"); 3778be086e7cSMintz, Yuval addr = BYTES_TO_DWORDS(MISC_REG_SHARED_MEM_ADDR); 3779c965db44STomer Tayar offset += qed_grc_dump_reg_entry(p_hwfn, 3780c965db44STomer Tayar p_ptt, 3781c965db44STomer Tayar dump_buf + offset, 3782c965db44STomer Tayar dump, 3783be086e7cSMintz, Yuval addr, 37847b6859fbSMintz, Yuval 1, 3785d52c89f1SMichal Kalderon false, SPLIT_TYPE_NONE, 0); 3786c965db44STomer Tayar 3787c965db44STomer Tayar /* Release MCP */ 3788c965db44STomer Tayar if (halted && qed_mcp_resume(p_hwfn, p_ptt)) 3789c965db44STomer Tayar DP_NOTICE(p_hwfn, "Failed to resume MCP after halt!\n"); 37907b6859fbSMintz, Yuval 3791c965db44STomer Tayar return offset; 3792c965db44STomer Tayar } 3793c965db44STomer Tayar 3794c965db44STomer Tayar /* Dumps the tbus indirect memory for all PHYs. */ 3795c965db44STomer Tayar static u32 qed_grc_dump_phy(struct qed_hwfn *p_hwfn, 3796c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *dump_buf, bool dump) 3797c965db44STomer Tayar { 3798c965db44STomer Tayar u32 offset = 0, tbus_lo_offset, tbus_hi_offset; 3799c965db44STomer Tayar char mem_name[32]; 3800c965db44STomer Tayar u8 phy_id; 3801c965db44STomer Tayar 3802c965db44STomer Tayar for (phy_id = 0; phy_id < ARRAY_SIZE(s_phy_defs); phy_id++) { 38037b6859fbSMintz, Yuval u32 addr_lo_addr, addr_hi_addr, data_lo_addr, data_hi_addr; 38047b6859fbSMintz, Yuval struct phy_defs *phy_defs; 38057b6859fbSMintz, Yuval u8 *bytes_buf; 3806c965db44STomer Tayar 38077b6859fbSMintz, Yuval phy_defs = &s_phy_defs[phy_id]; 38087b6859fbSMintz, Yuval addr_lo_addr = phy_defs->base_addr + 38097b6859fbSMintz, Yuval phy_defs->tbus_addr_lo_addr; 38107b6859fbSMintz, Yuval addr_hi_addr = phy_defs->base_addr + 38117b6859fbSMintz, Yuval phy_defs->tbus_addr_hi_addr; 38127b6859fbSMintz, Yuval data_lo_addr = phy_defs->base_addr + 38137b6859fbSMintz, Yuval phy_defs->tbus_data_lo_addr; 38147b6859fbSMintz, Yuval data_hi_addr = phy_defs->base_addr + 38157b6859fbSMintz, Yuval phy_defs->tbus_data_hi_addr; 38167b6859fbSMintz, Yuval 38177b6859fbSMintz, Yuval if (snprintf(mem_name, sizeof(mem_name), "tbus_%s", 38187b6859fbSMintz, Yuval phy_defs->phy_name) < 0) 3819c965db44STomer Tayar DP_NOTICE(p_hwfn, 3820c965db44STomer Tayar "Unexpected debug error: invalid PHY memory name\n"); 38217b6859fbSMintz, Yuval 3822c965db44STomer Tayar offset += qed_grc_dump_mem_hdr(p_hwfn, 3823c965db44STomer Tayar dump_buf + offset, 3824c965db44STomer Tayar dump, 3825c965db44STomer Tayar mem_name, 3826c965db44STomer Tayar 0, 3827c965db44STomer Tayar PHY_DUMP_SIZE_DWORDS, 3828c965db44STomer Tayar 16, true, mem_name, false, 0); 38297b6859fbSMintz, Yuval 38307b6859fbSMintz, Yuval if (!dump) { 38317b6859fbSMintz, Yuval offset += PHY_DUMP_SIZE_DWORDS; 38327b6859fbSMintz, Yuval continue; 38337b6859fbSMintz, Yuval } 3834c965db44STomer Tayar 3835da090917STomer Tayar bytes_buf = (u8 *)(dump_buf + offset); 3836c965db44STomer Tayar for (tbus_hi_offset = 0; 3837c965db44STomer Tayar tbus_hi_offset < (NUM_PHY_TBUS_ADDRESSES >> 8); 3838c965db44STomer Tayar tbus_hi_offset++) { 38397b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, addr_hi_addr, tbus_hi_offset); 3840c965db44STomer Tayar for (tbus_lo_offset = 0; tbus_lo_offset < 256; 3841c965db44STomer Tayar tbus_lo_offset++) { 3842c965db44STomer Tayar qed_wr(p_hwfn, 38437b6859fbSMintz, Yuval p_ptt, addr_lo_addr, tbus_lo_offset); 38447b6859fbSMintz, Yuval *(bytes_buf++) = (u8)qed_rd(p_hwfn, 3845c965db44STomer Tayar p_ptt, 3846c965db44STomer Tayar data_lo_addr); 38477b6859fbSMintz, Yuval *(bytes_buf++) = (u8)qed_rd(p_hwfn, 38487b6859fbSMintz, Yuval p_ptt, 3849c965db44STomer Tayar data_hi_addr); 3850c965db44STomer Tayar } 3851c965db44STomer Tayar } 3852c965db44STomer Tayar 3853c965db44STomer Tayar offset += PHY_DUMP_SIZE_DWORDS; 3854c965db44STomer Tayar } 3855c965db44STomer Tayar 3856c965db44STomer Tayar return offset; 3857c965db44STomer Tayar } 3858c965db44STomer Tayar 3859c965db44STomer Tayar static void qed_config_dbg_line(struct qed_hwfn *p_hwfn, 3860c965db44STomer Tayar struct qed_ptt *p_ptt, 3861c965db44STomer Tayar enum block_id block_id, 3862c965db44STomer Tayar u8 line_id, 38637b6859fbSMintz, Yuval u8 enable_mask, 38647b6859fbSMintz, Yuval u8 right_shift, 38657b6859fbSMintz, Yuval u8 force_valid_mask, u8 force_frame_mask) 3866c965db44STomer Tayar { 38677b6859fbSMintz, Yuval struct block_defs *block = s_block_defs[block_id]; 3868c965db44STomer Tayar 38697b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, block->dbg_select_addr, line_id); 38707b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, block->dbg_enable_addr, enable_mask); 38717b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, block->dbg_shift_addr, right_shift); 38727b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, block->dbg_force_valid_addr, force_valid_mask); 38737b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, block->dbg_force_frame_addr, force_frame_mask); 3874c965db44STomer Tayar } 3875c965db44STomer Tayar 3876c965db44STomer Tayar /* Dumps Static Debug data. Returns the dumped size in dwords. */ 3877c965db44STomer Tayar static u32 qed_grc_dump_static_debug(struct qed_hwfn *p_hwfn, 3878c965db44STomer Tayar struct qed_ptt *p_ptt, 3879c965db44STomer Tayar u32 *dump_buf, bool dump) 3880c965db44STomer Tayar { 3881c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 38827b6859fbSMintz, Yuval u32 block_id, line_id, offset = 0; 38837b6859fbSMintz, Yuval 3884da090917STomer Tayar /* Don't dump static debug if a debug bus recording is in progress */ 3885da090917STomer Tayar if (dump && qed_rd(p_hwfn, p_ptt, DBG_REG_DBG_BLOCK_ON)) 38867b6859fbSMintz, Yuval return 0; 3887c965db44STomer Tayar 3888c965db44STomer Tayar if (dump) { 3889c965db44STomer Tayar /* Disable all blocks debug output */ 3890c965db44STomer Tayar for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) { 38917b6859fbSMintz, Yuval struct block_defs *block = s_block_defs[block_id]; 3892c965db44STomer Tayar 3893da090917STomer Tayar if (block->dbg_client_id[dev_data->chip_id] != 3894da090917STomer Tayar MAX_DBG_BUS_CLIENTS) 38957b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, block->dbg_enable_addr, 38967b6859fbSMintz, Yuval 0); 3897c965db44STomer Tayar } 3898c965db44STomer Tayar 3899c965db44STomer Tayar qed_bus_reset_dbg_block(p_hwfn, p_ptt); 3900c965db44STomer Tayar qed_bus_set_framing_mode(p_hwfn, 3901c965db44STomer Tayar p_ptt, DBG_BUS_FRAME_MODE_8HW_0ST); 3902c965db44STomer Tayar qed_wr(p_hwfn, 3903c965db44STomer Tayar p_ptt, DBG_REG_DEBUG_TARGET, DBG_BUS_TARGET_ID_INT_BUF); 3904c965db44STomer Tayar qed_wr(p_hwfn, p_ptt, DBG_REG_FULL_MODE, 1); 3905c965db44STomer Tayar qed_bus_enable_dbg_block(p_hwfn, p_ptt, true); 3906c965db44STomer Tayar } 3907c965db44STomer Tayar 3908c965db44STomer Tayar /* Dump all static debug lines for each relevant block */ 3909c965db44STomer Tayar for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) { 39107b6859fbSMintz, Yuval struct block_defs *block = s_block_defs[block_id]; 39117b6859fbSMintz, Yuval struct dbg_bus_block *block_desc; 39127b6859fbSMintz, Yuval u32 block_dwords, addr, len; 39137b6859fbSMintz, Yuval u8 dbg_client_id; 3914c965db44STomer Tayar 3915da090917STomer Tayar if (block->dbg_client_id[dev_data->chip_id] == 3916da090917STomer Tayar MAX_DBG_BUS_CLIENTS) 3917c965db44STomer Tayar continue; 3918c965db44STomer Tayar 3919da090917STomer Tayar block_desc = get_dbg_bus_block_desc(p_hwfn, 39207b6859fbSMintz, Yuval (enum block_id)block_id); 39217b6859fbSMintz, Yuval block_dwords = NUM_DBG_LINES(block_desc) * 39227b6859fbSMintz, Yuval STATIC_DEBUG_LINE_DWORDS; 39237b6859fbSMintz, Yuval 3924c965db44STomer Tayar /* Dump static section params */ 3925c965db44STomer Tayar offset += qed_grc_dump_mem_hdr(p_hwfn, 3926c965db44STomer Tayar dump_buf + offset, 3927c965db44STomer Tayar dump, 39287b6859fbSMintz, Yuval block->name, 39297b6859fbSMintz, Yuval 0, 39307b6859fbSMintz, Yuval block_dwords, 39317b6859fbSMintz, Yuval 32, false, "STATIC", false, 0); 3932c965db44STomer Tayar 39337b6859fbSMintz, Yuval if (!dump) { 39347b6859fbSMintz, Yuval offset += block_dwords; 39357b6859fbSMintz, Yuval continue; 39367b6859fbSMintz, Yuval } 39377b6859fbSMintz, Yuval 39387b6859fbSMintz, Yuval /* If all lines are invalid - dump zeros */ 39397b6859fbSMintz, Yuval if (dev_data->block_in_reset[block_id]) { 39407b6859fbSMintz, Yuval memset(dump_buf + offset, 0, 39417b6859fbSMintz, Yuval DWORDS_TO_BYTES(block_dwords)); 39427b6859fbSMintz, Yuval offset += block_dwords; 39437b6859fbSMintz, Yuval continue; 39447b6859fbSMintz, Yuval } 3945c965db44STomer Tayar 3946c965db44STomer Tayar /* Enable block's client */ 39477b6859fbSMintz, Yuval dbg_client_id = block->dbg_client_id[dev_data->chip_id]; 39487b6859fbSMintz, Yuval qed_bus_enable_clients(p_hwfn, 39497b6859fbSMintz, Yuval p_ptt, 3950c965db44STomer Tayar BIT(dbg_client_id)); 3951c965db44STomer Tayar 39527b6859fbSMintz, Yuval addr = BYTES_TO_DWORDS(DBG_REG_CALENDAR_OUT_DATA); 39537b6859fbSMintz, Yuval len = STATIC_DEBUG_LINE_DWORDS; 39547b6859fbSMintz, Yuval for (line_id = 0; line_id < (u32)NUM_DBG_LINES(block_desc); 3955c965db44STomer Tayar line_id++) { 3956c965db44STomer Tayar /* Configure debug line ID */ 3957c965db44STomer Tayar qed_config_dbg_line(p_hwfn, 3958c965db44STomer Tayar p_ptt, 3959c965db44STomer Tayar (enum block_id)block_id, 39607b6859fbSMintz, Yuval (u8)line_id, 0xf, 0, 0, 0); 3961c965db44STomer Tayar 3962c965db44STomer Tayar /* Read debug line info */ 39637b6859fbSMintz, Yuval offset += qed_grc_dump_addr_range(p_hwfn, 3964be086e7cSMintz, Yuval p_ptt, 3965be086e7cSMintz, Yuval dump_buf + offset, 3966be086e7cSMintz, Yuval dump, 3967be086e7cSMintz, Yuval addr, 39687b6859fbSMintz, Yuval len, 3969d52c89f1SMichal Kalderon true, SPLIT_TYPE_NONE, 3970d52c89f1SMichal Kalderon 0); 3971c965db44STomer Tayar } 3972c965db44STomer Tayar 3973c965db44STomer Tayar /* Disable block's client and debug output */ 3974c965db44STomer Tayar qed_bus_enable_clients(p_hwfn, p_ptt, 0); 39757b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, block->dbg_enable_addr, 0); 3976c965db44STomer Tayar } 3977c965db44STomer Tayar 3978c965db44STomer Tayar if (dump) { 3979c965db44STomer Tayar qed_bus_enable_dbg_block(p_hwfn, p_ptt, false); 3980c965db44STomer Tayar qed_bus_enable_clients(p_hwfn, p_ptt, 0); 3981c965db44STomer Tayar } 3982c965db44STomer Tayar 3983c965db44STomer Tayar return offset; 3984c965db44STomer Tayar } 3985c965db44STomer Tayar 3986c965db44STomer Tayar /* Performs GRC Dump to the specified buffer. 3987c965db44STomer Tayar * Returns the dumped size in dwords. 3988c965db44STomer Tayar */ 3989c965db44STomer Tayar static enum dbg_status qed_grc_dump(struct qed_hwfn *p_hwfn, 3990c965db44STomer Tayar struct qed_ptt *p_ptt, 3991c965db44STomer Tayar u32 *dump_buf, 3992c965db44STomer Tayar bool dump, u32 *num_dumped_dwords) 3993c965db44STomer Tayar { 3994c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 3995c965db44STomer Tayar bool parities_masked = false; 3996c965db44STomer Tayar u32 offset = 0; 3997d52c89f1SMichal Kalderon u8 i; 3998c965db44STomer Tayar 3999c965db44STomer Tayar *num_dumped_dwords = 0; 4000d52c89f1SMichal Kalderon dev_data->num_regs_read = 0; 4001c965db44STomer Tayar 4002c965db44STomer Tayar /* Update reset state */ 4003d52c89f1SMichal Kalderon if (dump) 4004c965db44STomer Tayar qed_update_blocks_reset_state(p_hwfn, p_ptt); 4005c965db44STomer Tayar 4006c965db44STomer Tayar /* Dump global params */ 4007c965db44STomer Tayar offset += qed_dump_common_global_params(p_hwfn, 4008c965db44STomer Tayar p_ptt, 4009c965db44STomer Tayar dump_buf + offset, dump, 4); 4010c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 4011c965db44STomer Tayar dump, "dump-type", "grc-dump"); 4012c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 4013c965db44STomer Tayar dump, 4014c965db44STomer Tayar "num-lcids", 4015c965db44STomer Tayar qed_grc_get_param(p_hwfn, 4016c965db44STomer Tayar DBG_GRC_PARAM_NUM_LCIDS)); 4017c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 4018c965db44STomer Tayar dump, 4019c965db44STomer Tayar "num-ltids", 4020c965db44STomer Tayar qed_grc_get_param(p_hwfn, 4021c965db44STomer Tayar DBG_GRC_PARAM_NUM_LTIDS)); 4022c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 4023d52c89f1SMichal Kalderon dump, "num-ports", dev_data->num_ports); 4024c965db44STomer Tayar 4025c965db44STomer Tayar /* Dump reset registers (dumped before taking blocks out of reset ) */ 4026c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_REGS)) 4027c965db44STomer Tayar offset += qed_grc_dump_reset_regs(p_hwfn, 4028c965db44STomer Tayar p_ptt, 4029c965db44STomer Tayar dump_buf + offset, dump); 4030c965db44STomer Tayar 4031c965db44STomer Tayar /* Take all blocks out of reset (using reset registers) */ 4032c965db44STomer Tayar if (dump) { 4033c965db44STomer Tayar qed_grc_unreset_blocks(p_hwfn, p_ptt); 4034c965db44STomer Tayar qed_update_blocks_reset_state(p_hwfn, p_ptt); 4035c965db44STomer Tayar } 4036c965db44STomer Tayar 4037c965db44STomer Tayar /* Disable all parities using MFW command */ 40387b6859fbSMintz, Yuval if (dump && 40397b6859fbSMintz, Yuval !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_MCP)) { 4040c965db44STomer Tayar parities_masked = !qed_mcp_mask_parities(p_hwfn, p_ptt, 1); 4041c965db44STomer Tayar if (!parities_masked) { 4042be086e7cSMintz, Yuval DP_NOTICE(p_hwfn, 4043be086e7cSMintz, Yuval "Failed to mask parities using MFW\n"); 4044c965db44STomer Tayar if (qed_grc_get_param 4045c965db44STomer Tayar (p_hwfn, DBG_GRC_PARAM_PARITY_SAFE)) 4046c965db44STomer Tayar return DBG_STATUS_MCP_COULD_NOT_MASK_PRTY; 4047c965db44STomer Tayar } 4048c965db44STomer Tayar } 4049c965db44STomer Tayar 4050c965db44STomer Tayar /* Dump modified registers (dumped before modifying them) */ 4051c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_REGS)) 4052c965db44STomer Tayar offset += qed_grc_dump_modified_regs(p_hwfn, 4053c965db44STomer Tayar p_ptt, 4054c965db44STomer Tayar dump_buf + offset, dump); 4055c965db44STomer Tayar 4056c965db44STomer Tayar /* Stall storms */ 4057c965db44STomer Tayar if (dump && 4058c965db44STomer Tayar (qed_grc_is_included(p_hwfn, 4059c965db44STomer Tayar DBG_GRC_PARAM_DUMP_IOR) || 4060c965db44STomer Tayar qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_VFC))) 4061c965db44STomer Tayar qed_grc_stall_storms(p_hwfn, p_ptt, true); 4062c965db44STomer Tayar 4063c965db44STomer Tayar /* Dump all regs */ 4064c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_REGS)) { 4065c965db44STomer Tayar bool block_enable[MAX_BLOCK_ID]; 4066c965db44STomer Tayar 40677b6859fbSMintz, Yuval /* Dump all blocks except MCP */ 4068c965db44STomer Tayar for (i = 0; i < MAX_BLOCK_ID; i++) 4069c965db44STomer Tayar block_enable[i] = true; 4070c965db44STomer Tayar block_enable[BLOCK_MCP] = false; 4071c965db44STomer Tayar offset += qed_grc_dump_registers(p_hwfn, 4072c965db44STomer Tayar p_ptt, 4073c965db44STomer Tayar dump_buf + 4074c965db44STomer Tayar offset, 4075c965db44STomer Tayar dump, 4076c965db44STomer Tayar block_enable, NULL, NULL); 4077be086e7cSMintz, Yuval 4078be086e7cSMintz, Yuval /* Dump special registers */ 4079be086e7cSMintz, Yuval offset += qed_grc_dump_special_regs(p_hwfn, 4080be086e7cSMintz, Yuval p_ptt, 4081be086e7cSMintz, Yuval dump_buf + offset, dump); 4082c965db44STomer Tayar } 4083c965db44STomer Tayar 4084c965db44STomer Tayar /* Dump memories */ 4085c965db44STomer Tayar offset += qed_grc_dump_memories(p_hwfn, p_ptt, dump_buf + offset, dump); 4086c965db44STomer Tayar 4087c965db44STomer Tayar /* Dump MCP */ 4088c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_MCP)) 4089c965db44STomer Tayar offset += qed_grc_dump_mcp(p_hwfn, 4090c965db44STomer Tayar p_ptt, dump_buf + offset, dump); 4091c965db44STomer Tayar 4092c965db44STomer Tayar /* Dump context */ 4093c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CM_CTX)) 4094c965db44STomer Tayar offset += qed_grc_dump_ctx(p_hwfn, 4095c965db44STomer Tayar p_ptt, dump_buf + offset, dump); 4096c965db44STomer Tayar 4097c965db44STomer Tayar /* Dump RSS memories */ 4098c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_RSS)) 4099c965db44STomer Tayar offset += qed_grc_dump_rss(p_hwfn, 4100c965db44STomer Tayar p_ptt, dump_buf + offset, dump); 4101c965db44STomer Tayar 4102c965db44STomer Tayar /* Dump Big RAM */ 4103c965db44STomer Tayar for (i = 0; i < NUM_BIG_RAM_TYPES; i++) 4104c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, s_big_ram_defs[i].grc_param)) 4105c965db44STomer Tayar offset += qed_grc_dump_big_ram(p_hwfn, 4106c965db44STomer Tayar p_ptt, 4107c965db44STomer Tayar dump_buf + offset, 4108c965db44STomer Tayar dump, i); 4109c965db44STomer Tayar 4110c965db44STomer Tayar /* Dump IORs */ 4111c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_IOR)) 4112c965db44STomer Tayar offset += qed_grc_dump_iors(p_hwfn, 4113c965db44STomer Tayar p_ptt, dump_buf + offset, dump); 4114c965db44STomer Tayar 4115c965db44STomer Tayar /* Dump VFC */ 4116c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_VFC)) 4117c965db44STomer Tayar offset += qed_grc_dump_vfc(p_hwfn, 4118c965db44STomer Tayar p_ptt, dump_buf + offset, dump); 4119c965db44STomer Tayar 4120c965db44STomer Tayar /* Dump PHY tbus */ 4121c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, 4122c965db44STomer Tayar DBG_GRC_PARAM_DUMP_PHY) && dev_data->chip_id == 4123c965db44STomer Tayar CHIP_K2 && dev_data->platform_id == PLATFORM_ASIC) 4124c965db44STomer Tayar offset += qed_grc_dump_phy(p_hwfn, 4125c965db44STomer Tayar p_ptt, dump_buf + offset, dump); 4126c965db44STomer Tayar 4127d52c89f1SMichal Kalderon /* Dump static debug data (only if not during debug bus recording) */ 4128c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, 4129c965db44STomer Tayar DBG_GRC_PARAM_DUMP_STATIC) && 4130d52c89f1SMichal Kalderon (!dump || dev_data->bus.state == DBG_BUS_STATE_IDLE)) 4131c965db44STomer Tayar offset += qed_grc_dump_static_debug(p_hwfn, 4132c965db44STomer Tayar p_ptt, 4133c965db44STomer Tayar dump_buf + offset, dump); 4134c965db44STomer Tayar 4135c965db44STomer Tayar /* Dump last section */ 4136da090917STomer Tayar offset += qed_dump_last_section(dump_buf, offset, dump); 41377b6859fbSMintz, Yuval 4138c965db44STomer Tayar if (dump) { 4139c965db44STomer Tayar /* Unstall storms */ 4140c965db44STomer Tayar if (qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_UNSTALL)) 4141c965db44STomer Tayar qed_grc_stall_storms(p_hwfn, p_ptt, false); 4142c965db44STomer Tayar 4143c965db44STomer Tayar /* Clear parity status */ 4144c965db44STomer Tayar qed_grc_clear_all_prty(p_hwfn, p_ptt); 4145c965db44STomer Tayar 4146c965db44STomer Tayar /* Enable all parities using MFW command */ 4147c965db44STomer Tayar if (parities_masked) 4148c965db44STomer Tayar qed_mcp_mask_parities(p_hwfn, p_ptt, 0); 4149c965db44STomer Tayar } 4150c965db44STomer Tayar 4151c965db44STomer Tayar *num_dumped_dwords = offset; 4152c965db44STomer Tayar 4153c965db44STomer Tayar return DBG_STATUS_OK; 4154c965db44STomer Tayar } 4155c965db44STomer Tayar 4156c965db44STomer Tayar /* Writes the specified failing Idle Check rule to the specified buffer. 4157c965db44STomer Tayar * Returns the dumped size in dwords. 4158c965db44STomer Tayar */ 4159c965db44STomer Tayar static u32 qed_idle_chk_dump_failure(struct qed_hwfn *p_hwfn, 4160c965db44STomer Tayar struct qed_ptt *p_ptt, 4161c965db44STomer Tayar u32 * 4162c965db44STomer Tayar dump_buf, 4163c965db44STomer Tayar bool dump, 4164c965db44STomer Tayar u16 rule_id, 4165c965db44STomer Tayar const struct dbg_idle_chk_rule *rule, 4166c965db44STomer Tayar u16 fail_entry_id, u32 *cond_reg_values) 4167c965db44STomer Tayar { 4168c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 41697b6859fbSMintz, Yuval const struct dbg_idle_chk_cond_reg *cond_regs; 41707b6859fbSMintz, Yuval const struct dbg_idle_chk_info_reg *info_regs; 41717b6859fbSMintz, Yuval u32 i, next_reg_offset = 0, offset = 0; 41727b6859fbSMintz, Yuval struct dbg_idle_chk_result_hdr *hdr; 41737b6859fbSMintz, Yuval const union dbg_idle_chk_reg *regs; 4174c965db44STomer Tayar u8 reg_id; 4175c965db44STomer Tayar 41767b6859fbSMintz, Yuval hdr = (struct dbg_idle_chk_result_hdr *)dump_buf; 41777b6859fbSMintz, Yuval regs = &((const union dbg_idle_chk_reg *) 41787b6859fbSMintz, Yuval s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_REGS].ptr)[rule->reg_offset]; 41797b6859fbSMintz, Yuval cond_regs = ®s[0].cond_reg; 41807b6859fbSMintz, Yuval info_regs = ®s[rule->num_cond_regs].info_reg; 41817b6859fbSMintz, Yuval 4182c965db44STomer Tayar /* Dump rule data */ 4183c965db44STomer Tayar if (dump) { 4184c965db44STomer Tayar memset(hdr, 0, sizeof(*hdr)); 4185c965db44STomer Tayar hdr->rule_id = rule_id; 4186c965db44STomer Tayar hdr->mem_entry_id = fail_entry_id; 4187c965db44STomer Tayar hdr->severity = rule->severity; 4188c965db44STomer Tayar hdr->num_dumped_cond_regs = rule->num_cond_regs; 4189c965db44STomer Tayar } 4190c965db44STomer Tayar 4191c965db44STomer Tayar offset += IDLE_CHK_RESULT_HDR_DWORDS; 4192c965db44STomer Tayar 4193c965db44STomer Tayar /* Dump condition register values */ 4194c965db44STomer Tayar for (reg_id = 0; reg_id < rule->num_cond_regs; reg_id++) { 4195c965db44STomer Tayar const struct dbg_idle_chk_cond_reg *reg = &cond_regs[reg_id]; 41967b6859fbSMintz, Yuval struct dbg_idle_chk_result_reg_hdr *reg_hdr; 41977b6859fbSMintz, Yuval 41987b6859fbSMintz, Yuval reg_hdr = (struct dbg_idle_chk_result_reg_hdr *) 41997b6859fbSMintz, Yuval (dump_buf + offset); 4200c965db44STomer Tayar 4201c965db44STomer Tayar /* Write register header */ 42027b6859fbSMintz, Yuval if (!dump) { 42037b6859fbSMintz, Yuval offset += IDLE_CHK_RESULT_REG_HDR_DWORDS + 42047b6859fbSMintz, Yuval reg->entry_size; 42057b6859fbSMintz, Yuval continue; 42067b6859fbSMintz, Yuval } 42077b6859fbSMintz, Yuval 4208c965db44STomer Tayar offset += IDLE_CHK_RESULT_REG_HDR_DWORDS; 42097b6859fbSMintz, Yuval memset(reg_hdr, 0, sizeof(*reg_hdr)); 4210c965db44STomer Tayar reg_hdr->start_entry = reg->start_entry; 4211c965db44STomer Tayar reg_hdr->size = reg->entry_size; 4212c965db44STomer Tayar SET_FIELD(reg_hdr->data, 4213c965db44STomer Tayar DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM, 42147b6859fbSMintz, Yuval reg->num_entries > 1 || reg->start_entry > 0 ? 1 : 0); 4215c965db44STomer Tayar SET_FIELD(reg_hdr->data, 4216c965db44STomer Tayar DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID, reg_id); 4217c965db44STomer Tayar 4218c965db44STomer Tayar /* Write register values */ 42197b6859fbSMintz, Yuval for (i = 0; i < reg_hdr->size; i++, next_reg_offset++, offset++) 42207b6859fbSMintz, Yuval dump_buf[offset] = cond_reg_values[next_reg_offset]; 4221c965db44STomer Tayar } 4222c965db44STomer Tayar 4223c965db44STomer Tayar /* Dump info register values */ 4224c965db44STomer Tayar for (reg_id = 0; reg_id < rule->num_info_regs; reg_id++) { 4225c965db44STomer Tayar const struct dbg_idle_chk_info_reg *reg = &info_regs[reg_id]; 4226c965db44STomer Tayar u32 block_id; 4227c965db44STomer Tayar 42287b6859fbSMintz, Yuval /* Check if register's block is in reset */ 4229c965db44STomer Tayar if (!dump) { 4230c965db44STomer Tayar offset += IDLE_CHK_RESULT_REG_HDR_DWORDS + reg->size; 4231c965db44STomer Tayar continue; 4232c965db44STomer Tayar } 4233c965db44STomer Tayar 4234c965db44STomer Tayar block_id = GET_FIELD(reg->data, DBG_IDLE_CHK_INFO_REG_BLOCK_ID); 4235c965db44STomer Tayar if (block_id >= MAX_BLOCK_ID) { 4236c965db44STomer Tayar DP_NOTICE(p_hwfn, "Invalid block_id\n"); 4237c965db44STomer Tayar return 0; 4238c965db44STomer Tayar } 4239c965db44STomer Tayar 4240c965db44STomer Tayar if (!dev_data->block_in_reset[block_id]) { 42417b6859fbSMintz, Yuval struct dbg_idle_chk_result_reg_hdr *reg_hdr; 42427b6859fbSMintz, Yuval bool wide_bus, eval_mode, mode_match = true; 42437b6859fbSMintz, Yuval u16 modes_buf_offset; 42447b6859fbSMintz, Yuval u32 addr; 42457b6859fbSMintz, Yuval 42467b6859fbSMintz, Yuval reg_hdr = (struct dbg_idle_chk_result_reg_hdr *) 42477b6859fbSMintz, Yuval (dump_buf + offset); 4248c965db44STomer Tayar 4249c965db44STomer Tayar /* Check mode */ 42507b6859fbSMintz, Yuval eval_mode = GET_FIELD(reg->mode.data, 42517b6859fbSMintz, Yuval DBG_MODE_HDR_EVAL_MODE) > 0; 4252c965db44STomer Tayar if (eval_mode) { 42537b6859fbSMintz, Yuval modes_buf_offset = 4254c965db44STomer Tayar GET_FIELD(reg->mode.data, 4255c965db44STomer Tayar DBG_MODE_HDR_MODES_BUF_OFFSET); 4256c965db44STomer Tayar mode_match = 4257c965db44STomer Tayar qed_is_mode_match(p_hwfn, 4258c965db44STomer Tayar &modes_buf_offset); 4259c965db44STomer Tayar } 4260c965db44STomer Tayar 42617b6859fbSMintz, Yuval if (!mode_match) 42627b6859fbSMintz, Yuval continue; 42637b6859fbSMintz, Yuval 42647b6859fbSMintz, Yuval addr = GET_FIELD(reg->data, 4265be086e7cSMintz, Yuval DBG_IDLE_CHK_INFO_REG_ADDRESS); 42667b6859fbSMintz, Yuval wide_bus = GET_FIELD(reg->data, 42677b6859fbSMintz, Yuval DBG_IDLE_CHK_INFO_REG_WIDE_BUS); 4268c965db44STomer Tayar 4269c965db44STomer Tayar /* Write register header */ 4270c965db44STomer Tayar offset += IDLE_CHK_RESULT_REG_HDR_DWORDS; 4271c965db44STomer Tayar hdr->num_dumped_info_regs++; 4272c965db44STomer Tayar memset(reg_hdr, 0, sizeof(*reg_hdr)); 4273c965db44STomer Tayar reg_hdr->size = reg->size; 4274c965db44STomer Tayar SET_FIELD(reg_hdr->data, 4275c965db44STomer Tayar DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID, 4276c965db44STomer Tayar rule->num_cond_regs + reg_id); 4277c965db44STomer Tayar 4278c965db44STomer Tayar /* Write register values */ 42797b6859fbSMintz, Yuval offset += qed_grc_dump_addr_range(p_hwfn, 4280be086e7cSMintz, Yuval p_ptt, 4281be086e7cSMintz, Yuval dump_buf + offset, 4282be086e7cSMintz, Yuval dump, 4283be086e7cSMintz, Yuval addr, 4284d52c89f1SMichal Kalderon reg->size, wide_bus, 4285d52c89f1SMichal Kalderon SPLIT_TYPE_NONE, 0); 4286c965db44STomer Tayar } 4287c965db44STomer Tayar } 4288c965db44STomer Tayar 4289c965db44STomer Tayar return offset; 4290c965db44STomer Tayar } 4291c965db44STomer Tayar 4292c965db44STomer Tayar /* Dumps idle check rule entries. Returns the dumped size in dwords. */ 4293c965db44STomer Tayar static u32 4294c965db44STomer Tayar qed_idle_chk_dump_rule_entries(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 4295c965db44STomer Tayar u32 *dump_buf, bool dump, 4296c965db44STomer Tayar const struct dbg_idle_chk_rule *input_rules, 4297c965db44STomer Tayar u32 num_input_rules, u32 *num_failing_rules) 4298c965db44STomer Tayar { 4299c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 4300c965db44STomer Tayar u32 cond_reg_values[IDLE_CHK_MAX_ENTRIES_SIZE]; 4301be086e7cSMintz, Yuval u32 i, offset = 0; 4302c965db44STomer Tayar u16 entry_id; 4303c965db44STomer Tayar u8 reg_id; 4304c965db44STomer Tayar 4305c965db44STomer Tayar *num_failing_rules = 0; 43067b6859fbSMintz, Yuval 4307c965db44STomer Tayar for (i = 0; i < num_input_rules; i++) { 4308c965db44STomer Tayar const struct dbg_idle_chk_cond_reg *cond_regs; 4309c965db44STomer Tayar const struct dbg_idle_chk_rule *rule; 4310c965db44STomer Tayar const union dbg_idle_chk_reg *regs; 4311c965db44STomer Tayar u16 num_reg_entries = 1; 4312c965db44STomer Tayar bool check_rule = true; 4313c965db44STomer Tayar const u32 *imm_values; 4314c965db44STomer Tayar 4315c965db44STomer Tayar rule = &input_rules[i]; 4316c965db44STomer Tayar regs = &((const union dbg_idle_chk_reg *) 4317c965db44STomer Tayar s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_REGS].ptr) 4318c965db44STomer Tayar [rule->reg_offset]; 4319c965db44STomer Tayar cond_regs = ®s[0].cond_reg; 4320c965db44STomer Tayar imm_values = &s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_IMMS].ptr 4321c965db44STomer Tayar [rule->imm_offset]; 4322c965db44STomer Tayar 4323c965db44STomer Tayar /* Check if all condition register blocks are out of reset, and 4324c965db44STomer Tayar * find maximal number of entries (all condition registers that 4325c965db44STomer Tayar * are memories must have the same size, which is > 1). 4326c965db44STomer Tayar */ 4327c965db44STomer Tayar for (reg_id = 0; reg_id < rule->num_cond_regs && check_rule; 4328c965db44STomer Tayar reg_id++) { 43297b6859fbSMintz, Yuval u32 block_id = 43307b6859fbSMintz, Yuval GET_FIELD(cond_regs[reg_id].data, 4331c965db44STomer Tayar DBG_IDLE_CHK_COND_REG_BLOCK_ID); 4332c965db44STomer Tayar 4333c965db44STomer Tayar if (block_id >= MAX_BLOCK_ID) { 4334c965db44STomer Tayar DP_NOTICE(p_hwfn, "Invalid block_id\n"); 4335c965db44STomer Tayar return 0; 4336c965db44STomer Tayar } 4337c965db44STomer Tayar 4338c965db44STomer Tayar check_rule = !dev_data->block_in_reset[block_id]; 4339c965db44STomer Tayar if (cond_regs[reg_id].num_entries > num_reg_entries) 4340c965db44STomer Tayar num_reg_entries = cond_regs[reg_id].num_entries; 4341c965db44STomer Tayar } 4342c965db44STomer Tayar 4343c965db44STomer Tayar if (!check_rule && dump) 4344c965db44STomer Tayar continue; 4345c965db44STomer Tayar 4346be086e7cSMintz, Yuval if (!dump) { 4347da090917STomer Tayar u32 entry_dump_size = 4348da090917STomer Tayar qed_idle_chk_dump_failure(p_hwfn, 4349be086e7cSMintz, Yuval p_ptt, 4350be086e7cSMintz, Yuval dump_buf + offset, 4351be086e7cSMintz, Yuval false, 4352be086e7cSMintz, Yuval rule->rule_id, 4353be086e7cSMintz, Yuval rule, 4354da090917STomer Tayar 0, 4355be086e7cSMintz, Yuval NULL); 4356da090917STomer Tayar 4357da090917STomer Tayar offset += num_reg_entries * entry_dump_size; 4358da090917STomer Tayar (*num_failing_rules) += num_reg_entries; 4359da090917STomer Tayar continue; 4360be086e7cSMintz, Yuval } 4361be086e7cSMintz, Yuval 4362da090917STomer Tayar /* Go over all register entries (number of entries is the same 4363da090917STomer Tayar * for all condition registers). 4364da090917STomer Tayar */ 4365da090917STomer Tayar for (entry_id = 0; entry_id < num_reg_entries; entry_id++) { 4366da090917STomer Tayar u32 next_reg_offset = 0; 4367da090917STomer Tayar 4368c965db44STomer Tayar /* Read current entry of all condition registers */ 4369be086e7cSMintz, Yuval for (reg_id = 0; reg_id < rule->num_cond_regs; 4370c965db44STomer Tayar reg_id++) { 4371be086e7cSMintz, Yuval const struct dbg_idle_chk_cond_reg *reg = 4372be086e7cSMintz, Yuval &cond_regs[reg_id]; 43737b6859fbSMintz, Yuval u32 padded_entry_size, addr; 43747b6859fbSMintz, Yuval bool wide_bus; 4375c965db44STomer Tayar 4376be086e7cSMintz, Yuval /* Find GRC address (if it's a memory, the 4377be086e7cSMintz, Yuval * address of the specific entry is calculated). 4378c965db44STomer Tayar */ 43797b6859fbSMintz, Yuval addr = GET_FIELD(reg->data, 4380be086e7cSMintz, Yuval DBG_IDLE_CHK_COND_REG_ADDRESS); 43817b6859fbSMintz, Yuval wide_bus = 43827b6859fbSMintz, Yuval GET_FIELD(reg->data, 43837b6859fbSMintz, Yuval DBG_IDLE_CHK_COND_REG_WIDE_BUS); 4384c965db44STomer Tayar if (reg->num_entries > 1 || 4385c965db44STomer Tayar reg->start_entry > 0) { 43867b6859fbSMintz, Yuval padded_entry_size = 4387c965db44STomer Tayar reg->entry_size > 1 ? 4388da090917STomer Tayar roundup_pow_of_two(reg->entry_size) : 4389da090917STomer Tayar 1; 4390be086e7cSMintz, Yuval addr += (reg->start_entry + entry_id) * 4391be086e7cSMintz, Yuval padded_entry_size; 4392c965db44STomer Tayar } 4393c965db44STomer Tayar 4394c965db44STomer Tayar /* Read registers */ 4395c965db44STomer Tayar if (next_reg_offset + reg->entry_size >= 4396c965db44STomer Tayar IDLE_CHK_MAX_ENTRIES_SIZE) { 4397c965db44STomer Tayar DP_NOTICE(p_hwfn, 4398c965db44STomer Tayar "idle check registers entry is too large\n"); 4399c965db44STomer Tayar return 0; 4400c965db44STomer Tayar } 4401c965db44STomer Tayar 4402be086e7cSMintz, Yuval next_reg_offset += 44037b6859fbSMintz, Yuval qed_grc_dump_addr_range(p_hwfn, p_ptt, 4404be086e7cSMintz, Yuval cond_reg_values + 4405be086e7cSMintz, Yuval next_reg_offset, 4406be086e7cSMintz, Yuval dump, addr, 44077b6859fbSMintz, Yuval reg->entry_size, 4408d52c89f1SMichal Kalderon wide_bus, 4409d52c89f1SMichal Kalderon SPLIT_TYPE_NONE, 0); 4410c965db44STomer Tayar } 4411c965db44STomer Tayar 44127b6859fbSMintz, Yuval /* Call rule condition function. 44137b6859fbSMintz, Yuval * If returns true, it's a failure. 4414c965db44STomer Tayar */ 4415c965db44STomer Tayar if ((*cond_arr[rule->cond_id]) (cond_reg_values, 4416be086e7cSMintz, Yuval imm_values)) { 44177b6859fbSMintz, Yuval offset += qed_idle_chk_dump_failure(p_hwfn, 4418c965db44STomer Tayar p_ptt, 4419c965db44STomer Tayar dump_buf + offset, 4420c965db44STomer Tayar dump, 4421c965db44STomer Tayar rule->rule_id, 4422c965db44STomer Tayar rule, 4423c965db44STomer Tayar entry_id, 4424c965db44STomer Tayar cond_reg_values); 4425c965db44STomer Tayar (*num_failing_rules)++; 4426c965db44STomer Tayar } 4427c965db44STomer Tayar } 4428c965db44STomer Tayar } 4429c965db44STomer Tayar 4430c965db44STomer Tayar return offset; 4431c965db44STomer Tayar } 4432c965db44STomer Tayar 4433c965db44STomer Tayar /* Performs Idle Check Dump to the specified buffer. 4434c965db44STomer Tayar * Returns the dumped size in dwords. 4435c965db44STomer Tayar */ 4436c965db44STomer Tayar static u32 qed_idle_chk_dump(struct qed_hwfn *p_hwfn, 4437c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *dump_buf, bool dump) 4438c965db44STomer Tayar { 44397b6859fbSMintz, Yuval u32 num_failing_rules_offset, offset = 0, input_offset = 0; 44407b6859fbSMintz, Yuval u32 num_failing_rules = 0; 4441c965db44STomer Tayar 4442c965db44STomer Tayar /* Dump global params */ 4443c965db44STomer Tayar offset += qed_dump_common_global_params(p_hwfn, 4444c965db44STomer Tayar p_ptt, 4445c965db44STomer Tayar dump_buf + offset, dump, 1); 4446c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 4447c965db44STomer Tayar dump, "dump-type", "idle-chk"); 4448c965db44STomer Tayar 4449c965db44STomer Tayar /* Dump idle check section header with a single parameter */ 4450c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, dump, "idle_chk", 1); 4451c965db44STomer Tayar num_failing_rules_offset = offset; 4452c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, dump, "num_rules", 0); 44537b6859fbSMintz, Yuval 4454c965db44STomer Tayar while (input_offset < 4455c965db44STomer Tayar s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES].size_in_dwords) { 4456c965db44STomer Tayar const struct dbg_idle_chk_cond_hdr *cond_hdr = 4457c965db44STomer Tayar (const struct dbg_idle_chk_cond_hdr *) 4458c965db44STomer Tayar &s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES].ptr 4459c965db44STomer Tayar [input_offset++]; 44607b6859fbSMintz, Yuval bool eval_mode, mode_match = true; 44617b6859fbSMintz, Yuval u32 curr_failing_rules; 44627b6859fbSMintz, Yuval u16 modes_buf_offset; 4463c965db44STomer Tayar 4464c965db44STomer Tayar /* Check mode */ 44657b6859fbSMintz, Yuval eval_mode = GET_FIELD(cond_hdr->mode.data, 44667b6859fbSMintz, Yuval DBG_MODE_HDR_EVAL_MODE) > 0; 4467c965db44STomer Tayar if (eval_mode) { 44687b6859fbSMintz, Yuval modes_buf_offset = 4469c965db44STomer Tayar GET_FIELD(cond_hdr->mode.data, 4470c965db44STomer Tayar DBG_MODE_HDR_MODES_BUF_OFFSET); 4471c965db44STomer Tayar mode_match = qed_is_mode_match(p_hwfn, 4472c965db44STomer Tayar &modes_buf_offset); 4473c965db44STomer Tayar } 4474c965db44STomer Tayar 4475c965db44STomer Tayar if (mode_match) { 4476c965db44STomer Tayar offset += 4477c965db44STomer Tayar qed_idle_chk_dump_rule_entries(p_hwfn, 4478c965db44STomer Tayar p_ptt, 4479c965db44STomer Tayar dump_buf + offset, 4480c965db44STomer Tayar dump, 4481c965db44STomer Tayar (const struct dbg_idle_chk_rule *) 4482c965db44STomer Tayar &s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES]. 4483c965db44STomer Tayar ptr[input_offset], 4484c965db44STomer Tayar cond_hdr->data_size / IDLE_CHK_RULE_SIZE_DWORDS, 4485c965db44STomer Tayar &curr_failing_rules); 4486c965db44STomer Tayar num_failing_rules += curr_failing_rules; 4487c965db44STomer Tayar } 4488c965db44STomer Tayar 4489c965db44STomer Tayar input_offset += cond_hdr->data_size; 4490c965db44STomer Tayar } 4491c965db44STomer Tayar 4492c965db44STomer Tayar /* Overwrite num_rules parameter */ 4493c965db44STomer Tayar if (dump) 4494c965db44STomer Tayar qed_dump_num_param(dump_buf + num_failing_rules_offset, 4495c965db44STomer Tayar dump, "num_rules", num_failing_rules); 4496c965db44STomer Tayar 44977b6859fbSMintz, Yuval /* Dump last section */ 4498da090917STomer Tayar offset += qed_dump_last_section(dump_buf, offset, dump); 44997b6859fbSMintz, Yuval 4500c965db44STomer Tayar return offset; 4501c965db44STomer Tayar } 4502c965db44STomer Tayar 45037b6859fbSMintz, Yuval /* Finds the meta data image in NVRAM */ 4504c965db44STomer Tayar static enum dbg_status qed_find_nvram_image(struct qed_hwfn *p_hwfn, 4505c965db44STomer Tayar struct qed_ptt *p_ptt, 4506c965db44STomer Tayar u32 image_type, 4507c965db44STomer Tayar u32 *nvram_offset_bytes, 4508c965db44STomer Tayar u32 *nvram_size_bytes) 4509c965db44STomer Tayar { 4510c965db44STomer Tayar u32 ret_mcp_resp, ret_mcp_param, ret_txn_size; 4511c965db44STomer Tayar struct mcp_file_att file_att; 45127b6859fbSMintz, Yuval int nvm_result; 4513c965db44STomer Tayar 4514c965db44STomer Tayar /* Call NVRAM get file command */ 45157b6859fbSMintz, Yuval nvm_result = qed_mcp_nvm_rd_cmd(p_hwfn, 4516be086e7cSMintz, Yuval p_ptt, 4517be086e7cSMintz, Yuval DRV_MSG_CODE_NVM_GET_FILE_ATT, 4518be086e7cSMintz, Yuval image_type, 4519be086e7cSMintz, Yuval &ret_mcp_resp, 4520be086e7cSMintz, Yuval &ret_mcp_param, 45217b6859fbSMintz, Yuval &ret_txn_size, (u32 *)&file_att); 4522c965db44STomer Tayar 4523c965db44STomer Tayar /* Check response */ 4524be086e7cSMintz, Yuval if (nvm_result || 4525be086e7cSMintz, Yuval (ret_mcp_resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_NVM_OK) 4526c965db44STomer Tayar return DBG_STATUS_NVRAM_GET_IMAGE_FAILED; 4527c965db44STomer Tayar 4528c965db44STomer Tayar /* Update return values */ 4529c965db44STomer Tayar *nvram_offset_bytes = file_att.nvm_start_addr; 4530c965db44STomer Tayar *nvram_size_bytes = file_att.len; 45317b6859fbSMintz, Yuval 4532c965db44STomer Tayar DP_VERBOSE(p_hwfn, 4533c965db44STomer Tayar QED_MSG_DEBUG, 4534c965db44STomer Tayar "find_nvram_image: found NVRAM image of type %d in NVRAM offset %d bytes with size %d bytes\n", 4535c965db44STomer Tayar image_type, *nvram_offset_bytes, *nvram_size_bytes); 4536c965db44STomer Tayar 4537c965db44STomer Tayar /* Check alignment */ 4538c965db44STomer Tayar if (*nvram_size_bytes & 0x3) 4539c965db44STomer Tayar return DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE; 45407b6859fbSMintz, Yuval 4541c965db44STomer Tayar return DBG_STATUS_OK; 4542c965db44STomer Tayar } 4543c965db44STomer Tayar 45447b6859fbSMintz, Yuval /* Reads data from NVRAM */ 4545c965db44STomer Tayar static enum dbg_status qed_nvram_read(struct qed_hwfn *p_hwfn, 4546c965db44STomer Tayar struct qed_ptt *p_ptt, 4547c965db44STomer Tayar u32 nvram_offset_bytes, 4548c965db44STomer Tayar u32 nvram_size_bytes, u32 *ret_buf) 4549c965db44STomer Tayar { 45507b6859fbSMintz, Yuval u32 ret_mcp_resp, ret_mcp_param, ret_read_size, bytes_to_copy; 4551c965db44STomer Tayar s32 bytes_left = nvram_size_bytes; 45527b6859fbSMintz, Yuval u32 read_offset = 0; 4553c965db44STomer Tayar 4554c965db44STomer Tayar DP_VERBOSE(p_hwfn, 4555c965db44STomer Tayar QED_MSG_DEBUG, 4556c965db44STomer Tayar "nvram_read: reading image of size %d bytes from NVRAM\n", 4557c965db44STomer Tayar nvram_size_bytes); 45587b6859fbSMintz, Yuval 4559c965db44STomer Tayar do { 4560c965db44STomer Tayar bytes_to_copy = 4561c965db44STomer Tayar (bytes_left > 4562c965db44STomer Tayar MCP_DRV_NVM_BUF_LEN) ? MCP_DRV_NVM_BUF_LEN : bytes_left; 4563c965db44STomer Tayar 4564c965db44STomer Tayar /* Call NVRAM read command */ 4565c965db44STomer Tayar if (qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 4566c965db44STomer Tayar DRV_MSG_CODE_NVM_READ_NVRAM, 4567c965db44STomer Tayar (nvram_offset_bytes + 4568c965db44STomer Tayar read_offset) | 4569c965db44STomer Tayar (bytes_to_copy << 4570da090917STomer Tayar DRV_MB_PARAM_NVM_LEN_OFFSET), 4571c965db44STomer Tayar &ret_mcp_resp, &ret_mcp_param, 4572c965db44STomer Tayar &ret_read_size, 45737b6859fbSMintz, Yuval (u32 *)((u8 *)ret_buf + read_offset))) 4574c965db44STomer Tayar return DBG_STATUS_NVRAM_READ_FAILED; 4575c965db44STomer Tayar 4576c965db44STomer Tayar /* Check response */ 4577c965db44STomer Tayar if ((ret_mcp_resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_NVM_OK) 4578c965db44STomer Tayar return DBG_STATUS_NVRAM_READ_FAILED; 4579c965db44STomer Tayar 4580c965db44STomer Tayar /* Update read offset */ 4581c965db44STomer Tayar read_offset += ret_read_size; 4582c965db44STomer Tayar bytes_left -= ret_read_size; 4583c965db44STomer Tayar } while (bytes_left > 0); 4584c965db44STomer Tayar 4585c965db44STomer Tayar return DBG_STATUS_OK; 4586c965db44STomer Tayar } 4587c965db44STomer Tayar 4588c965db44STomer Tayar /* Get info on the MCP Trace data in the scratchpad: 45897b6859fbSMintz, Yuval * - trace_data_grc_addr (OUT): trace data GRC address in bytes 45907b6859fbSMintz, Yuval * - trace_data_size (OUT): trace data size in bytes (without the header) 4591c965db44STomer Tayar */ 4592c965db44STomer Tayar static enum dbg_status qed_mcp_trace_get_data_info(struct qed_hwfn *p_hwfn, 4593c965db44STomer Tayar struct qed_ptt *p_ptt, 4594c965db44STomer Tayar u32 *trace_data_grc_addr, 45957b6859fbSMintz, Yuval u32 *trace_data_size) 4596c965db44STomer Tayar { 45977b6859fbSMintz, Yuval u32 spad_trace_offsize, signature; 4598c965db44STomer Tayar 45997b6859fbSMintz, Yuval /* Read trace section offsize structure from MCP scratchpad */ 46007b6859fbSMintz, Yuval spad_trace_offsize = qed_rd(p_hwfn, p_ptt, MCP_SPAD_TRACE_OFFSIZE_ADDR); 46017b6859fbSMintz, Yuval 46027b6859fbSMintz, Yuval /* Extract trace section address from offsize (in scratchpad) */ 4603c965db44STomer Tayar *trace_data_grc_addr = 4604c965db44STomer Tayar MCP_REG_SCRATCH + SECTION_OFFSET(spad_trace_offsize); 4605c965db44STomer Tayar 4606c965db44STomer Tayar /* Read signature from MCP trace section */ 4607c965db44STomer Tayar signature = qed_rd(p_hwfn, p_ptt, 4608c965db44STomer Tayar *trace_data_grc_addr + 4609c965db44STomer Tayar offsetof(struct mcp_trace, signature)); 46107b6859fbSMintz, Yuval 4611c965db44STomer Tayar if (signature != MFW_TRACE_SIGNATURE) 4612c965db44STomer Tayar return DBG_STATUS_INVALID_TRACE_SIGNATURE; 4613c965db44STomer Tayar 4614c965db44STomer Tayar /* Read trace size from MCP trace section */ 46157b6859fbSMintz, Yuval *trace_data_size = qed_rd(p_hwfn, 4616c965db44STomer Tayar p_ptt, 4617c965db44STomer Tayar *trace_data_grc_addr + 4618c965db44STomer Tayar offsetof(struct mcp_trace, size)); 46197b6859fbSMintz, Yuval 4620c965db44STomer Tayar return DBG_STATUS_OK; 4621c965db44STomer Tayar } 4622c965db44STomer Tayar 46237b6859fbSMintz, Yuval /* Reads MCP trace meta data image from NVRAM 46247b6859fbSMintz, Yuval * - running_bundle_id (OUT): running bundle ID (invalid when loaded from file) 46257b6859fbSMintz, Yuval * - trace_meta_offset (OUT): trace meta offset in NVRAM in bytes (invalid when 46267b6859fbSMintz, Yuval * loaded from file). 46277b6859fbSMintz, Yuval * - trace_meta_size (OUT): size in bytes of the trace meta data. 4628c965db44STomer Tayar */ 4629c965db44STomer Tayar static enum dbg_status qed_mcp_trace_get_meta_info(struct qed_hwfn *p_hwfn, 4630c965db44STomer Tayar struct qed_ptt *p_ptt, 4631c965db44STomer Tayar u32 trace_data_size_bytes, 4632c965db44STomer Tayar u32 *running_bundle_id, 46337b6859fbSMintz, Yuval u32 *trace_meta_offset, 46347b6859fbSMintz, Yuval u32 *trace_meta_size) 4635c965db44STomer Tayar { 46367b6859fbSMintz, Yuval u32 spad_trace_offsize, nvram_image_type, running_mfw_addr; 46377b6859fbSMintz, Yuval 4638c965db44STomer Tayar /* Read MCP trace section offsize structure from MCP scratchpad */ 46397b6859fbSMintz, Yuval spad_trace_offsize = qed_rd(p_hwfn, p_ptt, MCP_SPAD_TRACE_OFFSIZE_ADDR); 4640c965db44STomer Tayar 4641c965db44STomer Tayar /* Find running bundle ID */ 46427b6859fbSMintz, Yuval running_mfw_addr = 4643c965db44STomer Tayar MCP_REG_SCRATCH + SECTION_OFFSET(spad_trace_offsize) + 4644c965db44STomer Tayar QED_SECTION_SIZE(spad_trace_offsize) + trace_data_size_bytes; 4645c965db44STomer Tayar *running_bundle_id = qed_rd(p_hwfn, p_ptt, running_mfw_addr); 4646c965db44STomer Tayar if (*running_bundle_id > 1) 4647c965db44STomer Tayar return DBG_STATUS_INVALID_NVRAM_BUNDLE; 4648c965db44STomer Tayar 4649c965db44STomer Tayar /* Find image in NVRAM */ 4650c965db44STomer Tayar nvram_image_type = 4651c965db44STomer Tayar (*running_bundle_id == 4652c965db44STomer Tayar DIR_ID_1) ? NVM_TYPE_MFW_TRACE1 : NVM_TYPE_MFW_TRACE2; 4653be086e7cSMintz, Yuval return qed_find_nvram_image(p_hwfn, 4654c965db44STomer Tayar p_ptt, 4655c965db44STomer Tayar nvram_image_type, 46567b6859fbSMintz, Yuval trace_meta_offset, trace_meta_size); 4657c965db44STomer Tayar } 4658c965db44STomer Tayar 46597b6859fbSMintz, Yuval /* Reads the MCP Trace meta data from NVRAM into the specified buffer */ 4660c965db44STomer Tayar static enum dbg_status qed_mcp_trace_read_meta(struct qed_hwfn *p_hwfn, 4661c965db44STomer Tayar struct qed_ptt *p_ptt, 4662c965db44STomer Tayar u32 nvram_offset_in_bytes, 4663c965db44STomer Tayar u32 size_in_bytes, u32 *buf) 4664c965db44STomer Tayar { 46657b6859fbSMintz, Yuval u8 modules_num, module_len, i, *byte_buf = (u8 *)buf; 46667b6859fbSMintz, Yuval enum dbg_status status; 4667c965db44STomer Tayar u32 signature; 4668c965db44STomer Tayar 4669c965db44STomer Tayar /* Read meta data from NVRAM */ 46707b6859fbSMintz, Yuval status = qed_nvram_read(p_hwfn, 4671c965db44STomer Tayar p_ptt, 46727b6859fbSMintz, Yuval nvram_offset_in_bytes, size_in_bytes, buf); 4673c965db44STomer Tayar if (status != DBG_STATUS_OK) 4674c965db44STomer Tayar return status; 4675c965db44STomer Tayar 4676c965db44STomer Tayar /* Extract and check first signature */ 4677c965db44STomer Tayar signature = qed_read_unaligned_dword(byte_buf); 46787b6859fbSMintz, Yuval byte_buf += sizeof(signature); 46797b6859fbSMintz, Yuval if (signature != NVM_MAGIC_VALUE) 4680c965db44STomer Tayar return DBG_STATUS_INVALID_TRACE_SIGNATURE; 4681c965db44STomer Tayar 4682c965db44STomer Tayar /* Extract number of modules */ 4683c965db44STomer Tayar modules_num = *(byte_buf++); 4684c965db44STomer Tayar 4685c965db44STomer Tayar /* Skip all modules */ 4686c965db44STomer Tayar for (i = 0; i < modules_num; i++) { 46877b6859fbSMintz, Yuval module_len = *(byte_buf++); 4688c965db44STomer Tayar byte_buf += module_len; 4689c965db44STomer Tayar } 4690c965db44STomer Tayar 4691c965db44STomer Tayar /* Extract and check second signature */ 4692c965db44STomer Tayar signature = qed_read_unaligned_dword(byte_buf); 46937b6859fbSMintz, Yuval byte_buf += sizeof(signature); 46947b6859fbSMintz, Yuval if (signature != NVM_MAGIC_VALUE) 4695c965db44STomer Tayar return DBG_STATUS_INVALID_TRACE_SIGNATURE; 46967b6859fbSMintz, Yuval 4697c965db44STomer Tayar return DBG_STATUS_OK; 4698c965db44STomer Tayar } 4699c965db44STomer Tayar 4700c965db44STomer Tayar /* Dump MCP Trace */ 47018c93beafSYuval Mintz static enum dbg_status qed_mcp_trace_dump(struct qed_hwfn *p_hwfn, 4702c965db44STomer Tayar struct qed_ptt *p_ptt, 4703c965db44STomer Tayar u32 *dump_buf, 4704c965db44STomer Tayar bool dump, u32 *num_dumped_dwords) 4705c965db44STomer Tayar { 4706c965db44STomer Tayar u32 trace_data_grc_addr, trace_data_size_bytes, trace_data_size_dwords; 4707be086e7cSMintz, Yuval u32 trace_meta_size_dwords = 0, running_bundle_id, offset = 0; 4708be086e7cSMintz, Yuval u32 trace_meta_offset_bytes = 0, trace_meta_size_bytes = 0; 4709c965db44STomer Tayar enum dbg_status status; 4710be086e7cSMintz, Yuval bool mcp_access; 4711c965db44STomer Tayar int halted = 0; 4712c965db44STomer Tayar 4713c965db44STomer Tayar *num_dumped_dwords = 0; 4714c965db44STomer Tayar 47157b6859fbSMintz, Yuval mcp_access = !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_MCP); 47167b6859fbSMintz, Yuval 4717c965db44STomer Tayar /* Get trace data info */ 4718c965db44STomer Tayar status = qed_mcp_trace_get_data_info(p_hwfn, 4719c965db44STomer Tayar p_ptt, 4720c965db44STomer Tayar &trace_data_grc_addr, 4721c965db44STomer Tayar &trace_data_size_bytes); 4722c965db44STomer Tayar if (status != DBG_STATUS_OK) 4723c965db44STomer Tayar return status; 4724c965db44STomer Tayar 4725c965db44STomer Tayar /* Dump global params */ 4726c965db44STomer Tayar offset += qed_dump_common_global_params(p_hwfn, 4727c965db44STomer Tayar p_ptt, 4728c965db44STomer Tayar dump_buf + offset, dump, 1); 4729c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 4730c965db44STomer Tayar dump, "dump-type", "mcp-trace"); 4731c965db44STomer Tayar 4732c965db44STomer Tayar /* Halt MCP while reading from scratchpad so the read data will be 47337b6859fbSMintz, Yuval * consistent. if halt fails, MCP trace is taken anyway, with a small 4734c965db44STomer Tayar * risk that it may be corrupt. 4735c965db44STomer Tayar */ 4736be086e7cSMintz, Yuval if (dump && mcp_access) { 4737c965db44STomer Tayar halted = !qed_mcp_halt(p_hwfn, p_ptt); 4738c965db44STomer Tayar if (!halted) 4739c965db44STomer Tayar DP_NOTICE(p_hwfn, "MCP halt failed!\n"); 4740c965db44STomer Tayar } 4741c965db44STomer Tayar 4742c965db44STomer Tayar /* Find trace data size */ 4743c965db44STomer Tayar trace_data_size_dwords = 4744c965db44STomer Tayar DIV_ROUND_UP(trace_data_size_bytes + sizeof(struct mcp_trace), 4745c965db44STomer Tayar BYTES_IN_DWORD); 4746c965db44STomer Tayar 4747c965db44STomer Tayar /* Dump trace data section header and param */ 4748c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, 4749c965db44STomer Tayar dump, "mcp_trace_data", 1); 4750c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 4751c965db44STomer Tayar dump, "size", trace_data_size_dwords); 4752c965db44STomer Tayar 4753c965db44STomer Tayar /* Read trace data from scratchpad into dump buffer */ 4754be086e7cSMintz, Yuval offset += qed_grc_dump_addr_range(p_hwfn, 4755c965db44STomer Tayar p_ptt, 4756be086e7cSMintz, Yuval dump_buf + offset, 4757be086e7cSMintz, Yuval dump, 4758be086e7cSMintz, Yuval BYTES_TO_DWORDS(trace_data_grc_addr), 4759d52c89f1SMichal Kalderon trace_data_size_dwords, false, 4760d52c89f1SMichal Kalderon SPLIT_TYPE_NONE, 0); 4761c965db44STomer Tayar 4762c965db44STomer Tayar /* Resume MCP (only if halt succeeded) */ 47637b6859fbSMintz, Yuval if (halted && qed_mcp_resume(p_hwfn, p_ptt)) 4764c965db44STomer Tayar DP_NOTICE(p_hwfn, "Failed to resume MCP after halt!\n"); 4765c965db44STomer Tayar 4766c965db44STomer Tayar /* Dump trace meta section header */ 4767c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, 4768c965db44STomer Tayar dump, "mcp_trace_meta", 1); 4769c965db44STomer Tayar 477050bc60cbSMichal Kalderon /* If MCP Trace meta size parameter was set, use it. 477150bc60cbSMichal Kalderon * Otherwise, read trace meta. 477250bc60cbSMichal Kalderon * trace_meta_size_bytes is dword-aligned. 477350bc60cbSMichal Kalderon */ 477450bc60cbSMichal Kalderon trace_meta_size_bytes = 477550bc60cbSMichal Kalderon qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_MCP_TRACE_META_SIZE); 477650bc60cbSMichal Kalderon if ((!trace_meta_size_bytes || dump) && mcp_access) { 4777c965db44STomer Tayar status = qed_mcp_trace_get_meta_info(p_hwfn, 4778c965db44STomer Tayar p_ptt, 4779c965db44STomer Tayar trace_data_size_bytes, 4780c965db44STomer Tayar &running_bundle_id, 4781c965db44STomer Tayar &trace_meta_offset_bytes, 4782c965db44STomer Tayar &trace_meta_size_bytes); 4783be086e7cSMintz, Yuval if (status == DBG_STATUS_OK) 4784be086e7cSMintz, Yuval trace_meta_size_dwords = 4785be086e7cSMintz, Yuval BYTES_TO_DWORDS(trace_meta_size_bytes); 4786be086e7cSMintz, Yuval } 4787c965db44STomer Tayar 4788be086e7cSMintz, Yuval /* Dump trace meta size param */ 4789be086e7cSMintz, Yuval offset += qed_dump_num_param(dump_buf + offset, 4790be086e7cSMintz, Yuval dump, "size", trace_meta_size_dwords); 4791c965db44STomer Tayar 4792c965db44STomer Tayar /* Read trace meta image into dump buffer */ 4793be086e7cSMintz, Yuval if (dump && trace_meta_size_dwords) 4794c965db44STomer Tayar status = qed_mcp_trace_read_meta(p_hwfn, 4795c965db44STomer Tayar p_ptt, 4796c965db44STomer Tayar trace_meta_offset_bytes, 4797c965db44STomer Tayar trace_meta_size_bytes, 4798c965db44STomer Tayar dump_buf + offset); 4799be086e7cSMintz, Yuval if (status == DBG_STATUS_OK) 4800c965db44STomer Tayar offset += trace_meta_size_dwords; 4801c965db44STomer Tayar 48027b6859fbSMintz, Yuval /* Dump last section */ 4803da090917STomer Tayar offset += qed_dump_last_section(dump_buf, offset, dump); 48047b6859fbSMintz, Yuval 4805c965db44STomer Tayar *num_dumped_dwords = offset; 4806c965db44STomer Tayar 4807be086e7cSMintz, Yuval /* If no mcp access, indicate that the dump doesn't contain the meta 4808be086e7cSMintz, Yuval * data from NVRAM. 4809be086e7cSMintz, Yuval */ 4810be086e7cSMintz, Yuval return mcp_access ? status : DBG_STATUS_NVRAM_GET_IMAGE_FAILED; 4811c965db44STomer Tayar } 4812c965db44STomer Tayar 4813c965db44STomer Tayar /* Dump GRC FIFO */ 48148c93beafSYuval Mintz static enum dbg_status qed_reg_fifo_dump(struct qed_hwfn *p_hwfn, 4815c965db44STomer Tayar struct qed_ptt *p_ptt, 4816c965db44STomer Tayar u32 *dump_buf, 4817c965db44STomer Tayar bool dump, u32 *num_dumped_dwords) 4818c965db44STomer Tayar { 4819da090917STomer Tayar u32 dwords_read, size_param_offset, offset = 0, addr, len; 4820c965db44STomer Tayar bool fifo_has_data; 4821c965db44STomer Tayar 4822c965db44STomer Tayar *num_dumped_dwords = 0; 4823c965db44STomer Tayar 4824c965db44STomer Tayar /* Dump global params */ 4825c965db44STomer Tayar offset += qed_dump_common_global_params(p_hwfn, 4826c965db44STomer Tayar p_ptt, 4827c965db44STomer Tayar dump_buf + offset, dump, 1); 4828c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 4829c965db44STomer Tayar dump, "dump-type", "reg-fifo"); 4830c965db44STomer Tayar 48317b6859fbSMintz, Yuval /* Dump fifo data section header and param. The size param is 0 for 48327b6859fbSMintz, Yuval * now, and is overwritten after reading the FIFO. 4833c965db44STomer Tayar */ 4834c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, 4835c965db44STomer Tayar dump, "reg_fifo_data", 1); 4836c965db44STomer Tayar size_param_offset = offset; 4837c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, dump, "size", 0); 4838c965db44STomer Tayar 4839c965db44STomer Tayar if (!dump) { 4840c965db44STomer Tayar /* FIFO max size is REG_FIFO_DEPTH_DWORDS. There is no way to 4841c965db44STomer Tayar * test how much data is available, except for reading it. 4842c965db44STomer Tayar */ 4843c965db44STomer Tayar offset += REG_FIFO_DEPTH_DWORDS; 48447b6859fbSMintz, Yuval goto out; 4845c965db44STomer Tayar } 4846c965db44STomer Tayar 4847c965db44STomer Tayar fifo_has_data = qed_rd(p_hwfn, p_ptt, 4848c965db44STomer Tayar GRC_REG_TRACE_FIFO_VALID_DATA) > 0; 4849c965db44STomer Tayar 4850c965db44STomer Tayar /* Pull available data from fifo. Use DMAE since this is widebus memory 4851c965db44STomer Tayar * and must be accessed atomically. Test for dwords_read not passing 4852c965db44STomer Tayar * buffer size since more entries could be added to the buffer as we are 4853c965db44STomer Tayar * emptying it. 4854c965db44STomer Tayar */ 4855da090917STomer Tayar addr = BYTES_TO_DWORDS(GRC_REG_TRACE_FIFO); 4856da090917STomer Tayar len = REG_FIFO_ELEMENT_DWORDS; 4857c965db44STomer Tayar for (dwords_read = 0; 4858c965db44STomer Tayar fifo_has_data && dwords_read < REG_FIFO_DEPTH_DWORDS; 4859da090917STomer Tayar dwords_read += REG_FIFO_ELEMENT_DWORDS) { 4860da090917STomer Tayar offset += qed_grc_dump_addr_range(p_hwfn, 4861da090917STomer Tayar p_ptt, 4862da090917STomer Tayar dump_buf + offset, 4863da090917STomer Tayar true, 4864da090917STomer Tayar addr, 4865da090917STomer Tayar len, 4866d52c89f1SMichal Kalderon true, SPLIT_TYPE_NONE, 4867d52c89f1SMichal Kalderon 0); 4868c965db44STomer Tayar fifo_has_data = qed_rd(p_hwfn, p_ptt, 4869c965db44STomer Tayar GRC_REG_TRACE_FIFO_VALID_DATA) > 0; 4870c965db44STomer Tayar } 4871c965db44STomer Tayar 4872c965db44STomer Tayar qed_dump_num_param(dump_buf + size_param_offset, dump, "size", 4873c965db44STomer Tayar dwords_read); 48747b6859fbSMintz, Yuval out: 48757b6859fbSMintz, Yuval /* Dump last section */ 4876da090917STomer Tayar offset += qed_dump_last_section(dump_buf, offset, dump); 4877c965db44STomer Tayar 4878c965db44STomer Tayar *num_dumped_dwords = offset; 48797b6859fbSMintz, Yuval 4880c965db44STomer Tayar return DBG_STATUS_OK; 4881c965db44STomer Tayar } 4882c965db44STomer Tayar 4883c965db44STomer Tayar /* Dump IGU FIFO */ 48848c93beafSYuval Mintz static enum dbg_status qed_igu_fifo_dump(struct qed_hwfn *p_hwfn, 4885c965db44STomer Tayar struct qed_ptt *p_ptt, 4886c965db44STomer Tayar u32 *dump_buf, 4887c965db44STomer Tayar bool dump, u32 *num_dumped_dwords) 4888c965db44STomer Tayar { 4889da090917STomer Tayar u32 dwords_read, size_param_offset, offset = 0, addr, len; 4890c965db44STomer Tayar bool fifo_has_data; 4891c965db44STomer Tayar 4892c965db44STomer Tayar *num_dumped_dwords = 0; 4893c965db44STomer Tayar 4894c965db44STomer Tayar /* Dump global params */ 4895c965db44STomer Tayar offset += qed_dump_common_global_params(p_hwfn, 4896c965db44STomer Tayar p_ptt, 4897c965db44STomer Tayar dump_buf + offset, dump, 1); 4898c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 4899c965db44STomer Tayar dump, "dump-type", "igu-fifo"); 4900c965db44STomer Tayar 49017b6859fbSMintz, Yuval /* Dump fifo data section header and param. The size param is 0 for 49027b6859fbSMintz, Yuval * now, and is overwritten after reading the FIFO. 4903c965db44STomer Tayar */ 4904c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, 4905c965db44STomer Tayar dump, "igu_fifo_data", 1); 4906c965db44STomer Tayar size_param_offset = offset; 4907c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, dump, "size", 0); 4908c965db44STomer Tayar 4909c965db44STomer Tayar if (!dump) { 4910c965db44STomer Tayar /* FIFO max size is IGU_FIFO_DEPTH_DWORDS. There is no way to 4911c965db44STomer Tayar * test how much data is available, except for reading it. 4912c965db44STomer Tayar */ 4913c965db44STomer Tayar offset += IGU_FIFO_DEPTH_DWORDS; 49147b6859fbSMintz, Yuval goto out; 4915c965db44STomer Tayar } 4916c965db44STomer Tayar 4917c965db44STomer Tayar fifo_has_data = qed_rd(p_hwfn, p_ptt, 4918c965db44STomer Tayar IGU_REG_ERROR_HANDLING_DATA_VALID) > 0; 4919c965db44STomer Tayar 4920c965db44STomer Tayar /* Pull available data from fifo. Use DMAE since this is widebus memory 4921c965db44STomer Tayar * and must be accessed atomically. Test for dwords_read not passing 4922c965db44STomer Tayar * buffer size since more entries could be added to the buffer as we are 4923c965db44STomer Tayar * emptying it. 4924c965db44STomer Tayar */ 4925da090917STomer Tayar addr = BYTES_TO_DWORDS(IGU_REG_ERROR_HANDLING_MEMORY); 4926da090917STomer Tayar len = IGU_FIFO_ELEMENT_DWORDS; 4927c965db44STomer Tayar for (dwords_read = 0; 4928c965db44STomer Tayar fifo_has_data && dwords_read < IGU_FIFO_DEPTH_DWORDS; 4929da090917STomer Tayar dwords_read += IGU_FIFO_ELEMENT_DWORDS) { 4930da090917STomer Tayar offset += qed_grc_dump_addr_range(p_hwfn, 4931da090917STomer Tayar p_ptt, 4932da090917STomer Tayar dump_buf + offset, 4933da090917STomer Tayar true, 4934da090917STomer Tayar addr, 4935da090917STomer Tayar len, 4936d52c89f1SMichal Kalderon true, SPLIT_TYPE_NONE, 4937d52c89f1SMichal Kalderon 0); 4938c965db44STomer Tayar fifo_has_data = qed_rd(p_hwfn, p_ptt, 4939c965db44STomer Tayar IGU_REG_ERROR_HANDLING_DATA_VALID) > 0; 4940c965db44STomer Tayar } 4941c965db44STomer Tayar 4942c965db44STomer Tayar qed_dump_num_param(dump_buf + size_param_offset, dump, "size", 4943c965db44STomer Tayar dwords_read); 49447b6859fbSMintz, Yuval out: 49457b6859fbSMintz, Yuval /* Dump last section */ 4946da090917STomer Tayar offset += qed_dump_last_section(dump_buf, offset, dump); 4947c965db44STomer Tayar 4948c965db44STomer Tayar *num_dumped_dwords = offset; 49497b6859fbSMintz, Yuval 4950c965db44STomer Tayar return DBG_STATUS_OK; 4951c965db44STomer Tayar } 4952c965db44STomer Tayar 4953c965db44STomer Tayar /* Protection Override dump */ 49548c93beafSYuval Mintz static enum dbg_status qed_protection_override_dump(struct qed_hwfn *p_hwfn, 4955c965db44STomer Tayar struct qed_ptt *p_ptt, 4956c965db44STomer Tayar u32 *dump_buf, 49578c93beafSYuval Mintz bool dump, 49588c93beafSYuval Mintz u32 *num_dumped_dwords) 4959c965db44STomer Tayar { 4960da090917STomer Tayar u32 size_param_offset, override_window_dwords, offset = 0, addr; 4961c965db44STomer Tayar 4962c965db44STomer Tayar *num_dumped_dwords = 0; 4963c965db44STomer Tayar 4964c965db44STomer Tayar /* Dump global params */ 4965c965db44STomer Tayar offset += qed_dump_common_global_params(p_hwfn, 4966c965db44STomer Tayar p_ptt, 4967c965db44STomer Tayar dump_buf + offset, dump, 1); 4968c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 4969c965db44STomer Tayar dump, "dump-type", "protection-override"); 4970c965db44STomer Tayar 49717b6859fbSMintz, Yuval /* Dump data section header and param. The size param is 0 for now, 49727b6859fbSMintz, Yuval * and is overwritten after reading the data. 4973c965db44STomer Tayar */ 4974c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, 4975c965db44STomer Tayar dump, "protection_override_data", 1); 4976c965db44STomer Tayar size_param_offset = offset; 4977c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, dump, "size", 0); 4978c965db44STomer Tayar 4979c965db44STomer Tayar if (!dump) { 4980c965db44STomer Tayar offset += PROTECTION_OVERRIDE_DEPTH_DWORDS; 49817b6859fbSMintz, Yuval goto out; 4982c965db44STomer Tayar } 4983c965db44STomer Tayar 4984c965db44STomer Tayar /* Add override window info to buffer */ 4985c965db44STomer Tayar override_window_dwords = 4986da090917STomer Tayar qed_rd(p_hwfn, p_ptt, GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW) * 4987c965db44STomer Tayar PROTECTION_OVERRIDE_ELEMENT_DWORDS; 4988da090917STomer Tayar addr = BYTES_TO_DWORDS(GRC_REG_PROTECTION_OVERRIDE_WINDOW); 4989da090917STomer Tayar offset += qed_grc_dump_addr_range(p_hwfn, 4990da090917STomer Tayar p_ptt, 4991da090917STomer Tayar dump_buf + offset, 4992da090917STomer Tayar true, 4993da090917STomer Tayar addr, 4994da090917STomer Tayar override_window_dwords, 4995d52c89f1SMichal Kalderon true, SPLIT_TYPE_NONE, 0); 4996c965db44STomer Tayar qed_dump_num_param(dump_buf + size_param_offset, dump, "size", 4997c965db44STomer Tayar override_window_dwords); 49987b6859fbSMintz, Yuval out: 49997b6859fbSMintz, Yuval /* Dump last section */ 5000da090917STomer Tayar offset += qed_dump_last_section(dump_buf, offset, dump); 5001c965db44STomer Tayar 5002c965db44STomer Tayar *num_dumped_dwords = offset; 50037b6859fbSMintz, Yuval 5004c965db44STomer Tayar return DBG_STATUS_OK; 5005c965db44STomer Tayar } 5006c965db44STomer Tayar 5007c965db44STomer Tayar /* Performs FW Asserts Dump to the specified buffer. 5008c965db44STomer Tayar * Returns the dumped size in dwords. 5009c965db44STomer Tayar */ 5010c965db44STomer Tayar static u32 qed_fw_asserts_dump(struct qed_hwfn *p_hwfn, 5011c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *dump_buf, bool dump) 5012c965db44STomer Tayar { 5013c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5014be086e7cSMintz, Yuval struct fw_asserts_ram_section *asserts; 5015c965db44STomer Tayar char storm_letter_str[2] = "?"; 5016c965db44STomer Tayar struct fw_info fw_info; 5017be086e7cSMintz, Yuval u32 offset = 0; 5018c965db44STomer Tayar u8 storm_id; 5019c965db44STomer Tayar 5020c965db44STomer Tayar /* Dump global params */ 5021c965db44STomer Tayar offset += qed_dump_common_global_params(p_hwfn, 5022c965db44STomer Tayar p_ptt, 5023c965db44STomer Tayar dump_buf + offset, dump, 1); 5024c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 5025c965db44STomer Tayar dump, "dump-type", "fw-asserts"); 50267b6859fbSMintz, Yuval 50277b6859fbSMintz, Yuval /* Find Storm dump size */ 5028c965db44STomer Tayar for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 5029be086e7cSMintz, Yuval u32 fw_asserts_section_addr, next_list_idx_addr, next_list_idx; 50307b6859fbSMintz, Yuval struct storm_defs *storm = &s_storm_defs[storm_id]; 5031be086e7cSMintz, Yuval u32 last_list_idx, addr; 5032c965db44STomer Tayar 50337b6859fbSMintz, Yuval if (dev_data->block_in_reset[storm->block_id]) 5034c965db44STomer Tayar continue; 5035c965db44STomer Tayar 5036c965db44STomer Tayar /* Read FW info for the current Storm */ 5037d52c89f1SMichal Kalderon qed_read_storm_fw_info(p_hwfn, p_ptt, storm_id, &fw_info); 5038c965db44STomer Tayar 5039be086e7cSMintz, Yuval asserts = &fw_info.fw_asserts_section; 5040be086e7cSMintz, Yuval 5041c965db44STomer Tayar /* Dump FW Asserts section header and params */ 50427b6859fbSMintz, Yuval storm_letter_str[0] = storm->letter; 50437b6859fbSMintz, Yuval offset += qed_dump_section_hdr(dump_buf + offset, 50447b6859fbSMintz, Yuval dump, "fw_asserts", 2); 50457b6859fbSMintz, Yuval offset += qed_dump_str_param(dump_buf + offset, 50467b6859fbSMintz, Yuval dump, "storm", storm_letter_str); 50477b6859fbSMintz, Yuval offset += qed_dump_num_param(dump_buf + offset, 50487b6859fbSMintz, Yuval dump, 50497b6859fbSMintz, Yuval "size", 5050be086e7cSMintz, Yuval asserts->list_element_dword_size); 5051c965db44STomer Tayar 50527b6859fbSMintz, Yuval /* Read and dump FW Asserts data */ 5053c965db44STomer Tayar if (!dump) { 5054be086e7cSMintz, Yuval offset += asserts->list_element_dword_size; 5055c965db44STomer Tayar continue; 5056c965db44STomer Tayar } 5057c965db44STomer Tayar 50587b6859fbSMintz, Yuval fw_asserts_section_addr = storm->sem_fast_mem_addr + 5059c965db44STomer Tayar SEM_FAST_REG_INT_RAM + 5060be086e7cSMintz, Yuval RAM_LINES_TO_BYTES(asserts->section_ram_line_offset); 50617b6859fbSMintz, Yuval next_list_idx_addr = fw_asserts_section_addr + 5062be086e7cSMintz, Yuval DWORDS_TO_BYTES(asserts->list_next_index_dword_offset); 5063c965db44STomer Tayar next_list_idx = qed_rd(p_hwfn, p_ptt, next_list_idx_addr); 5064da090917STomer Tayar last_list_idx = (next_list_idx > 0 ? 5065da090917STomer Tayar next_list_idx : 5066da090917STomer Tayar asserts->list_num_elements) - 1; 5067be086e7cSMintz, Yuval addr = BYTES_TO_DWORDS(fw_asserts_section_addr) + 5068be086e7cSMintz, Yuval asserts->list_dword_offset + 5069be086e7cSMintz, Yuval last_list_idx * asserts->list_element_dword_size; 5070be086e7cSMintz, Yuval offset += 5071be086e7cSMintz, Yuval qed_grc_dump_addr_range(p_hwfn, p_ptt, 5072be086e7cSMintz, Yuval dump_buf + offset, 5073be086e7cSMintz, Yuval dump, addr, 50747b6859fbSMintz, Yuval asserts->list_element_dword_size, 5075d52c89f1SMichal Kalderon false, SPLIT_TYPE_NONE, 0); 5076c965db44STomer Tayar } 5077c965db44STomer Tayar 5078c965db44STomer Tayar /* Dump last section */ 5079da090917STomer Tayar offset += qed_dump_last_section(dump_buf, offset, dump); 50807b6859fbSMintz, Yuval 5081c965db44STomer Tayar return offset; 5082c965db44STomer Tayar } 5083c965db44STomer Tayar 5084c965db44STomer Tayar /***************************** Public Functions *******************************/ 5085c965db44STomer Tayar 5086c965db44STomer Tayar enum dbg_status qed_dbg_set_bin_ptr(const u8 * const bin_ptr) 5087c965db44STomer Tayar { 5088be086e7cSMintz, Yuval struct bin_buffer_hdr *buf_array = (struct bin_buffer_hdr *)bin_ptr; 5089c965db44STomer Tayar u8 buf_id; 5090c965db44STomer Tayar 50917b6859fbSMintz, Yuval /* convert binary data to debug arrays */ 5092be086e7cSMintz, Yuval for (buf_id = 0; buf_id < MAX_BIN_DBG_BUFFER_TYPE; buf_id++) { 5093c965db44STomer Tayar s_dbg_arrays[buf_id].ptr = 5094c965db44STomer Tayar (u32 *)(bin_ptr + buf_array[buf_id].offset); 5095c965db44STomer Tayar s_dbg_arrays[buf_id].size_in_dwords = 5096c965db44STomer Tayar BYTES_TO_DWORDS(buf_array[buf_id].length); 5097c965db44STomer Tayar } 5098c965db44STomer Tayar 5099c965db44STomer Tayar return DBG_STATUS_OK; 5100c965db44STomer Tayar } 5101c965db44STomer Tayar 5102d52c89f1SMichal Kalderon bool qed_read_fw_info(struct qed_hwfn *p_hwfn, 5103d52c89f1SMichal Kalderon struct qed_ptt *p_ptt, struct fw_info *fw_info) 5104d52c89f1SMichal Kalderon { 5105d52c89f1SMichal Kalderon struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5106d52c89f1SMichal Kalderon u8 storm_id; 5107d52c89f1SMichal Kalderon 5108d52c89f1SMichal Kalderon for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 5109d52c89f1SMichal Kalderon struct storm_defs *storm = &s_storm_defs[storm_id]; 5110d52c89f1SMichal Kalderon 5111d52c89f1SMichal Kalderon /* Skip Storm if it's in reset */ 5112d52c89f1SMichal Kalderon if (dev_data->block_in_reset[storm->block_id]) 5113d52c89f1SMichal Kalderon continue; 5114d52c89f1SMichal Kalderon 5115d52c89f1SMichal Kalderon /* Read FW info for the current Storm */ 5116d52c89f1SMichal Kalderon qed_read_storm_fw_info(p_hwfn, p_ptt, storm_id, fw_info); 5117d52c89f1SMichal Kalderon 5118d52c89f1SMichal Kalderon return true; 5119d52c89f1SMichal Kalderon } 5120d52c89f1SMichal Kalderon 5121d52c89f1SMichal Kalderon return false; 5122d52c89f1SMichal Kalderon } 5123d52c89f1SMichal Kalderon 5124be086e7cSMintz, Yuval /* Assign default GRC param values */ 5125be086e7cSMintz, Yuval void qed_dbg_grc_set_params_default(struct qed_hwfn *p_hwfn) 5126be086e7cSMintz, Yuval { 5127be086e7cSMintz, Yuval struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5128be086e7cSMintz, Yuval u32 i; 5129be086e7cSMintz, Yuval 5130be086e7cSMintz, Yuval for (i = 0; i < MAX_DBG_GRC_PARAMS; i++) 513150bc60cbSMichal Kalderon if (!s_grc_param_defs[i].is_persistent) 5132be086e7cSMintz, Yuval dev_data->grc.param_val[i] = 5133be086e7cSMintz, Yuval s_grc_param_defs[i].default_val[dev_data->chip_id]; 5134be086e7cSMintz, Yuval } 5135be086e7cSMintz, Yuval 5136c965db44STomer Tayar enum dbg_status qed_dbg_grc_get_dump_buf_size(struct qed_hwfn *p_hwfn, 5137c965db44STomer Tayar struct qed_ptt *p_ptt, 5138c965db44STomer Tayar u32 *buf_size) 5139c965db44STomer Tayar { 5140c965db44STomer Tayar enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt); 5141c965db44STomer Tayar 5142c965db44STomer Tayar *buf_size = 0; 51437b6859fbSMintz, Yuval 5144c965db44STomer Tayar if (status != DBG_STATUS_OK) 5145c965db44STomer Tayar return status; 51467b6859fbSMintz, Yuval 5147c965db44STomer Tayar if (!s_dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr || 5148c965db44STomer Tayar !s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].ptr || 5149c965db44STomer Tayar !s_dbg_arrays[BIN_BUF_DBG_DUMP_MEM].ptr || 5150c965db44STomer Tayar !s_dbg_arrays[BIN_BUF_DBG_ATTN_BLOCKS].ptr || 5151c965db44STomer Tayar !s_dbg_arrays[BIN_BUF_DBG_ATTN_REGS].ptr) 5152c965db44STomer Tayar return DBG_STATUS_DBG_ARRAY_NOT_SET; 51537b6859fbSMintz, Yuval 5154c965db44STomer Tayar return qed_grc_dump(p_hwfn, p_ptt, NULL, false, buf_size); 5155c965db44STomer Tayar } 5156c965db44STomer Tayar 5157c965db44STomer Tayar enum dbg_status qed_dbg_grc_dump(struct qed_hwfn *p_hwfn, 5158c965db44STomer Tayar struct qed_ptt *p_ptt, 5159c965db44STomer Tayar u32 *dump_buf, 5160c965db44STomer Tayar u32 buf_size_in_dwords, 5161c965db44STomer Tayar u32 *num_dumped_dwords) 5162c965db44STomer Tayar { 5163c965db44STomer Tayar u32 needed_buf_size_in_dwords; 5164c965db44STomer Tayar enum dbg_status status; 5165c965db44STomer Tayar 5166c965db44STomer Tayar *num_dumped_dwords = 0; 51677b6859fbSMintz, Yuval 51687b6859fbSMintz, Yuval status = qed_dbg_grc_get_dump_buf_size(p_hwfn, 51697b6859fbSMintz, Yuval p_ptt, 51707b6859fbSMintz, Yuval &needed_buf_size_in_dwords); 5171c965db44STomer Tayar if (status != DBG_STATUS_OK) 5172c965db44STomer Tayar return status; 51737b6859fbSMintz, Yuval 5174c965db44STomer Tayar if (buf_size_in_dwords < needed_buf_size_in_dwords) 5175c965db44STomer Tayar return DBG_STATUS_DUMP_BUF_TOO_SMALL; 5176c965db44STomer Tayar 5177c965db44STomer Tayar /* GRC Dump */ 5178c965db44STomer Tayar status = qed_grc_dump(p_hwfn, p_ptt, dump_buf, true, num_dumped_dwords); 5179c965db44STomer Tayar 5180be086e7cSMintz, Yuval /* Revert GRC params to their default */ 5181be086e7cSMintz, Yuval qed_dbg_grc_set_params_default(p_hwfn); 5182be086e7cSMintz, Yuval 5183c965db44STomer Tayar return status; 5184c965db44STomer Tayar } 5185c965db44STomer Tayar 5186c965db44STomer Tayar enum dbg_status qed_dbg_idle_chk_get_dump_buf_size(struct qed_hwfn *p_hwfn, 5187c965db44STomer Tayar struct qed_ptt *p_ptt, 5188c965db44STomer Tayar u32 *buf_size) 5189c965db44STomer Tayar { 5190c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 51917b6859fbSMintz, Yuval struct idle_chk_data *idle_chk; 51927b6859fbSMintz, Yuval enum dbg_status status; 5193c965db44STomer Tayar 51947b6859fbSMintz, Yuval idle_chk = &dev_data->idle_chk; 5195c965db44STomer Tayar *buf_size = 0; 51967b6859fbSMintz, Yuval 51977b6859fbSMintz, Yuval status = qed_dbg_dev_init(p_hwfn, p_ptt); 5198c965db44STomer Tayar if (status != DBG_STATUS_OK) 5199c965db44STomer Tayar return status; 52007b6859fbSMintz, Yuval 5201c965db44STomer Tayar if (!s_dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr || 5202c965db44STomer Tayar !s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_REGS].ptr || 5203c965db44STomer Tayar !s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_IMMS].ptr || 5204c965db44STomer Tayar !s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES].ptr) 5205c965db44STomer Tayar return DBG_STATUS_DBG_ARRAY_NOT_SET; 52067b6859fbSMintz, Yuval 52077b6859fbSMintz, Yuval if (!idle_chk->buf_size_set) { 52087b6859fbSMintz, Yuval idle_chk->buf_size = qed_idle_chk_dump(p_hwfn, 52097b6859fbSMintz, Yuval p_ptt, NULL, false); 52107b6859fbSMintz, Yuval idle_chk->buf_size_set = true; 5211c965db44STomer Tayar } 5212c965db44STomer Tayar 52137b6859fbSMintz, Yuval *buf_size = idle_chk->buf_size; 52147b6859fbSMintz, Yuval 5215c965db44STomer Tayar return DBG_STATUS_OK; 5216c965db44STomer Tayar } 5217c965db44STomer Tayar 5218c965db44STomer Tayar enum dbg_status qed_dbg_idle_chk_dump(struct qed_hwfn *p_hwfn, 5219c965db44STomer Tayar struct qed_ptt *p_ptt, 5220c965db44STomer Tayar u32 *dump_buf, 5221c965db44STomer Tayar u32 buf_size_in_dwords, 5222c965db44STomer Tayar u32 *num_dumped_dwords) 5223c965db44STomer Tayar { 5224c965db44STomer Tayar u32 needed_buf_size_in_dwords; 5225c965db44STomer Tayar enum dbg_status status; 5226c965db44STomer Tayar 5227c965db44STomer Tayar *num_dumped_dwords = 0; 52287b6859fbSMintz, Yuval 52297b6859fbSMintz, Yuval status = qed_dbg_idle_chk_get_dump_buf_size(p_hwfn, 52307b6859fbSMintz, Yuval p_ptt, 52317b6859fbSMintz, Yuval &needed_buf_size_in_dwords); 5232c965db44STomer Tayar if (status != DBG_STATUS_OK) 5233c965db44STomer Tayar return status; 52347b6859fbSMintz, Yuval 5235c965db44STomer Tayar if (buf_size_in_dwords < needed_buf_size_in_dwords) 5236c965db44STomer Tayar return DBG_STATUS_DUMP_BUF_TOO_SMALL; 5237c965db44STomer Tayar 5238c965db44STomer Tayar /* Update reset state */ 5239c965db44STomer Tayar qed_update_blocks_reset_state(p_hwfn, p_ptt); 5240c965db44STomer Tayar 5241c965db44STomer Tayar /* Idle Check Dump */ 5242c965db44STomer Tayar *num_dumped_dwords = qed_idle_chk_dump(p_hwfn, p_ptt, dump_buf, true); 5243be086e7cSMintz, Yuval 5244be086e7cSMintz, Yuval /* Revert GRC params to their default */ 5245be086e7cSMintz, Yuval qed_dbg_grc_set_params_default(p_hwfn); 5246be086e7cSMintz, Yuval 5247c965db44STomer Tayar return DBG_STATUS_OK; 5248c965db44STomer Tayar } 5249c965db44STomer Tayar 5250c965db44STomer Tayar enum dbg_status qed_dbg_mcp_trace_get_dump_buf_size(struct qed_hwfn *p_hwfn, 5251c965db44STomer Tayar struct qed_ptt *p_ptt, 5252c965db44STomer Tayar u32 *buf_size) 5253c965db44STomer Tayar { 5254c965db44STomer Tayar enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt); 5255c965db44STomer Tayar 5256c965db44STomer Tayar *buf_size = 0; 52577b6859fbSMintz, Yuval 5258c965db44STomer Tayar if (status != DBG_STATUS_OK) 5259c965db44STomer Tayar return status; 52607b6859fbSMintz, Yuval 5261c965db44STomer Tayar return qed_mcp_trace_dump(p_hwfn, p_ptt, NULL, false, buf_size); 5262c965db44STomer Tayar } 5263c965db44STomer Tayar 5264c965db44STomer Tayar enum dbg_status qed_dbg_mcp_trace_dump(struct qed_hwfn *p_hwfn, 5265c965db44STomer Tayar struct qed_ptt *p_ptt, 5266c965db44STomer Tayar u32 *dump_buf, 5267c965db44STomer Tayar u32 buf_size_in_dwords, 5268c965db44STomer Tayar u32 *num_dumped_dwords) 5269c965db44STomer Tayar { 5270c965db44STomer Tayar u32 needed_buf_size_in_dwords; 5271c965db44STomer Tayar enum dbg_status status; 5272c965db44STomer Tayar 5273be086e7cSMintz, Yuval status = 52747b6859fbSMintz, Yuval qed_dbg_mcp_trace_get_dump_buf_size(p_hwfn, 52757b6859fbSMintz, Yuval p_ptt, 5276c965db44STomer Tayar &needed_buf_size_in_dwords); 52777b6859fbSMintz, Yuval if (status != DBG_STATUS_OK && status != 52787b6859fbSMintz, Yuval DBG_STATUS_NVRAM_GET_IMAGE_FAILED) 5279c965db44STomer Tayar return status; 5280be086e7cSMintz, Yuval 5281c965db44STomer Tayar if (buf_size_in_dwords < needed_buf_size_in_dwords) 5282c965db44STomer Tayar return DBG_STATUS_DUMP_BUF_TOO_SMALL; 5283c965db44STomer Tayar 5284c965db44STomer Tayar /* Update reset state */ 5285c965db44STomer Tayar qed_update_blocks_reset_state(p_hwfn, p_ptt); 5286c965db44STomer Tayar 5287c965db44STomer Tayar /* Perform dump */ 5288be086e7cSMintz, Yuval status = qed_mcp_trace_dump(p_hwfn, 5289c965db44STomer Tayar p_ptt, dump_buf, true, num_dumped_dwords); 5290be086e7cSMintz, Yuval 5291be086e7cSMintz, Yuval /* Revert GRC params to their default */ 5292be086e7cSMintz, Yuval qed_dbg_grc_set_params_default(p_hwfn); 5293be086e7cSMintz, Yuval 5294be086e7cSMintz, Yuval return status; 5295c965db44STomer Tayar } 5296c965db44STomer Tayar 5297c965db44STomer Tayar enum dbg_status qed_dbg_reg_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn, 5298c965db44STomer Tayar struct qed_ptt *p_ptt, 5299c965db44STomer Tayar u32 *buf_size) 5300c965db44STomer Tayar { 5301c965db44STomer Tayar enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt); 5302c965db44STomer Tayar 5303c965db44STomer Tayar *buf_size = 0; 53047b6859fbSMintz, Yuval 5305c965db44STomer Tayar if (status != DBG_STATUS_OK) 5306c965db44STomer Tayar return status; 53077b6859fbSMintz, Yuval 5308c965db44STomer Tayar return qed_reg_fifo_dump(p_hwfn, p_ptt, NULL, false, buf_size); 5309c965db44STomer Tayar } 5310c965db44STomer Tayar 5311c965db44STomer Tayar enum dbg_status qed_dbg_reg_fifo_dump(struct qed_hwfn *p_hwfn, 5312c965db44STomer Tayar struct qed_ptt *p_ptt, 5313c965db44STomer Tayar u32 *dump_buf, 5314c965db44STomer Tayar u32 buf_size_in_dwords, 5315c965db44STomer Tayar u32 *num_dumped_dwords) 5316c965db44STomer Tayar { 5317c965db44STomer Tayar u32 needed_buf_size_in_dwords; 5318c965db44STomer Tayar enum dbg_status status; 5319c965db44STomer Tayar 5320c965db44STomer Tayar *num_dumped_dwords = 0; 53217b6859fbSMintz, Yuval 53227b6859fbSMintz, Yuval status = qed_dbg_reg_fifo_get_dump_buf_size(p_hwfn, 53237b6859fbSMintz, Yuval p_ptt, 53247b6859fbSMintz, Yuval &needed_buf_size_in_dwords); 5325c965db44STomer Tayar if (status != DBG_STATUS_OK) 5326c965db44STomer Tayar return status; 53277b6859fbSMintz, Yuval 5328c965db44STomer Tayar if (buf_size_in_dwords < needed_buf_size_in_dwords) 5329c965db44STomer Tayar return DBG_STATUS_DUMP_BUF_TOO_SMALL; 5330c965db44STomer Tayar 5331c965db44STomer Tayar /* Update reset state */ 5332c965db44STomer Tayar qed_update_blocks_reset_state(p_hwfn, p_ptt); 5333be086e7cSMintz, Yuval 5334be086e7cSMintz, Yuval status = qed_reg_fifo_dump(p_hwfn, 5335c965db44STomer Tayar p_ptt, dump_buf, true, num_dumped_dwords); 5336be086e7cSMintz, Yuval 5337be086e7cSMintz, Yuval /* Revert GRC params to their default */ 5338be086e7cSMintz, Yuval qed_dbg_grc_set_params_default(p_hwfn); 5339be086e7cSMintz, Yuval 5340be086e7cSMintz, Yuval return status; 5341c965db44STomer Tayar } 5342c965db44STomer Tayar 5343c965db44STomer Tayar enum dbg_status qed_dbg_igu_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn, 5344c965db44STomer Tayar struct qed_ptt *p_ptt, 5345c965db44STomer Tayar u32 *buf_size) 5346c965db44STomer Tayar { 5347c965db44STomer Tayar enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt); 5348c965db44STomer Tayar 5349c965db44STomer Tayar *buf_size = 0; 53507b6859fbSMintz, Yuval 5351c965db44STomer Tayar if (status != DBG_STATUS_OK) 5352c965db44STomer Tayar return status; 53537b6859fbSMintz, Yuval 5354c965db44STomer Tayar return qed_igu_fifo_dump(p_hwfn, p_ptt, NULL, false, buf_size); 5355c965db44STomer Tayar } 5356c965db44STomer Tayar 5357c965db44STomer Tayar enum dbg_status qed_dbg_igu_fifo_dump(struct qed_hwfn *p_hwfn, 5358c965db44STomer Tayar struct qed_ptt *p_ptt, 5359c965db44STomer Tayar u32 *dump_buf, 5360c965db44STomer Tayar u32 buf_size_in_dwords, 5361c965db44STomer Tayar u32 *num_dumped_dwords) 5362c965db44STomer Tayar { 5363c965db44STomer Tayar u32 needed_buf_size_in_dwords; 5364c965db44STomer Tayar enum dbg_status status; 5365c965db44STomer Tayar 5366c965db44STomer Tayar *num_dumped_dwords = 0; 53677b6859fbSMintz, Yuval 53687b6859fbSMintz, Yuval status = qed_dbg_igu_fifo_get_dump_buf_size(p_hwfn, 53697b6859fbSMintz, Yuval p_ptt, 53707b6859fbSMintz, Yuval &needed_buf_size_in_dwords); 5371c965db44STomer Tayar if (status != DBG_STATUS_OK) 5372c965db44STomer Tayar return status; 53737b6859fbSMintz, Yuval 5374c965db44STomer Tayar if (buf_size_in_dwords < needed_buf_size_in_dwords) 5375c965db44STomer Tayar return DBG_STATUS_DUMP_BUF_TOO_SMALL; 5376c965db44STomer Tayar 5377c965db44STomer Tayar /* Update reset state */ 5378c965db44STomer Tayar qed_update_blocks_reset_state(p_hwfn, p_ptt); 5379be086e7cSMintz, Yuval 5380be086e7cSMintz, Yuval status = qed_igu_fifo_dump(p_hwfn, 5381c965db44STomer Tayar p_ptt, dump_buf, true, num_dumped_dwords); 5382be086e7cSMintz, Yuval /* Revert GRC params to their default */ 5383be086e7cSMintz, Yuval qed_dbg_grc_set_params_default(p_hwfn); 5384be086e7cSMintz, Yuval 5385be086e7cSMintz, Yuval return status; 5386c965db44STomer Tayar } 5387c965db44STomer Tayar 5388c965db44STomer Tayar enum dbg_status 5389c965db44STomer Tayar qed_dbg_protection_override_get_dump_buf_size(struct qed_hwfn *p_hwfn, 5390c965db44STomer Tayar struct qed_ptt *p_ptt, 5391c965db44STomer Tayar u32 *buf_size) 5392c965db44STomer Tayar { 5393c965db44STomer Tayar enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt); 5394c965db44STomer Tayar 5395c965db44STomer Tayar *buf_size = 0; 53967b6859fbSMintz, Yuval 5397c965db44STomer Tayar if (status != DBG_STATUS_OK) 5398c965db44STomer Tayar return status; 53997b6859fbSMintz, Yuval 5400c965db44STomer Tayar return qed_protection_override_dump(p_hwfn, 5401c965db44STomer Tayar p_ptt, NULL, false, buf_size); 5402c965db44STomer Tayar } 5403c965db44STomer Tayar 5404c965db44STomer Tayar enum dbg_status qed_dbg_protection_override_dump(struct qed_hwfn *p_hwfn, 5405c965db44STomer Tayar struct qed_ptt *p_ptt, 5406c965db44STomer Tayar u32 *dump_buf, 5407c965db44STomer Tayar u32 buf_size_in_dwords, 5408c965db44STomer Tayar u32 *num_dumped_dwords) 5409c965db44STomer Tayar { 54107b6859fbSMintz, Yuval u32 needed_buf_size_in_dwords, *p_size = &needed_buf_size_in_dwords; 5411c965db44STomer Tayar enum dbg_status status; 5412c965db44STomer Tayar 5413c965db44STomer Tayar *num_dumped_dwords = 0; 54147b6859fbSMintz, Yuval 54157b6859fbSMintz, Yuval status = 54167b6859fbSMintz, Yuval qed_dbg_protection_override_get_dump_buf_size(p_hwfn, 54177b6859fbSMintz, Yuval p_ptt, 54187b6859fbSMintz, Yuval p_size); 5419c965db44STomer Tayar if (status != DBG_STATUS_OK) 5420c965db44STomer Tayar return status; 54217b6859fbSMintz, Yuval 5422c965db44STomer Tayar if (buf_size_in_dwords < needed_buf_size_in_dwords) 5423c965db44STomer Tayar return DBG_STATUS_DUMP_BUF_TOO_SMALL; 5424c965db44STomer Tayar 5425c965db44STomer Tayar /* Update reset state */ 5426c965db44STomer Tayar qed_update_blocks_reset_state(p_hwfn, p_ptt); 5427be086e7cSMintz, Yuval 5428be086e7cSMintz, Yuval status = qed_protection_override_dump(p_hwfn, 5429c965db44STomer Tayar p_ptt, 5430be086e7cSMintz, Yuval dump_buf, 5431be086e7cSMintz, Yuval true, num_dumped_dwords); 5432be086e7cSMintz, Yuval 5433be086e7cSMintz, Yuval /* Revert GRC params to their default */ 5434be086e7cSMintz, Yuval qed_dbg_grc_set_params_default(p_hwfn); 5435be086e7cSMintz, Yuval 5436be086e7cSMintz, Yuval return status; 5437c965db44STomer Tayar } 5438c965db44STomer Tayar 5439c965db44STomer Tayar enum dbg_status qed_dbg_fw_asserts_get_dump_buf_size(struct qed_hwfn *p_hwfn, 5440c965db44STomer Tayar struct qed_ptt *p_ptt, 5441c965db44STomer Tayar u32 *buf_size) 5442c965db44STomer Tayar { 5443c965db44STomer Tayar enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt); 5444c965db44STomer Tayar 5445c965db44STomer Tayar *buf_size = 0; 54467b6859fbSMintz, Yuval 5447c965db44STomer Tayar if (status != DBG_STATUS_OK) 5448c965db44STomer Tayar return status; 5449c965db44STomer Tayar 5450c965db44STomer Tayar /* Update reset state */ 5451c965db44STomer Tayar qed_update_blocks_reset_state(p_hwfn, p_ptt); 54527b6859fbSMintz, Yuval 5453c965db44STomer Tayar *buf_size = qed_fw_asserts_dump(p_hwfn, p_ptt, NULL, false); 54547b6859fbSMintz, Yuval 5455c965db44STomer Tayar return DBG_STATUS_OK; 5456c965db44STomer Tayar } 5457c965db44STomer Tayar 5458c965db44STomer Tayar enum dbg_status qed_dbg_fw_asserts_dump(struct qed_hwfn *p_hwfn, 5459c965db44STomer Tayar struct qed_ptt *p_ptt, 5460c965db44STomer Tayar u32 *dump_buf, 5461c965db44STomer Tayar u32 buf_size_in_dwords, 5462c965db44STomer Tayar u32 *num_dumped_dwords) 5463c965db44STomer Tayar { 54647b6859fbSMintz, Yuval u32 needed_buf_size_in_dwords, *p_size = &needed_buf_size_in_dwords; 5465c965db44STomer Tayar enum dbg_status status; 5466c965db44STomer Tayar 5467c965db44STomer Tayar *num_dumped_dwords = 0; 54687b6859fbSMintz, Yuval 54697b6859fbSMintz, Yuval status = 54707b6859fbSMintz, Yuval qed_dbg_fw_asserts_get_dump_buf_size(p_hwfn, 54717b6859fbSMintz, Yuval p_ptt, 54727b6859fbSMintz, Yuval p_size); 5473c965db44STomer Tayar if (status != DBG_STATUS_OK) 5474c965db44STomer Tayar return status; 54757b6859fbSMintz, Yuval 5476c965db44STomer Tayar if (buf_size_in_dwords < needed_buf_size_in_dwords) 5477c965db44STomer Tayar return DBG_STATUS_DUMP_BUF_TOO_SMALL; 5478c965db44STomer Tayar 5479c965db44STomer Tayar *num_dumped_dwords = qed_fw_asserts_dump(p_hwfn, p_ptt, dump_buf, true); 54807b6859fbSMintz, Yuval 54817b6859fbSMintz, Yuval /* Revert GRC params to their default */ 54827b6859fbSMintz, Yuval qed_dbg_grc_set_params_default(p_hwfn); 54837b6859fbSMintz, Yuval 5484c965db44STomer Tayar return DBG_STATUS_OK; 5485c965db44STomer Tayar } 5486c965db44STomer Tayar 54870ebbd1c8SMintz, Yuval enum dbg_status qed_dbg_read_attn(struct qed_hwfn *p_hwfn, 54880ebbd1c8SMintz, Yuval struct qed_ptt *p_ptt, 54890ebbd1c8SMintz, Yuval enum block_id block_id, 54900ebbd1c8SMintz, Yuval enum dbg_attn_type attn_type, 54910ebbd1c8SMintz, Yuval bool clear_status, 54920ebbd1c8SMintz, Yuval struct dbg_attn_block_result *results) 54930ebbd1c8SMintz, Yuval { 54940ebbd1c8SMintz, Yuval enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt); 54950ebbd1c8SMintz, Yuval u8 reg_idx, num_attn_regs, num_result_regs = 0; 54960ebbd1c8SMintz, Yuval const struct dbg_attn_reg *attn_reg_arr; 54970ebbd1c8SMintz, Yuval 54980ebbd1c8SMintz, Yuval if (status != DBG_STATUS_OK) 54990ebbd1c8SMintz, Yuval return status; 55000ebbd1c8SMintz, Yuval 55010ebbd1c8SMintz, Yuval if (!s_dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr || 55020ebbd1c8SMintz, Yuval !s_dbg_arrays[BIN_BUF_DBG_ATTN_BLOCKS].ptr || 55030ebbd1c8SMintz, Yuval !s_dbg_arrays[BIN_BUF_DBG_ATTN_REGS].ptr) 55040ebbd1c8SMintz, Yuval return DBG_STATUS_DBG_ARRAY_NOT_SET; 55050ebbd1c8SMintz, Yuval 55060ebbd1c8SMintz, Yuval attn_reg_arr = qed_get_block_attn_regs(block_id, 55070ebbd1c8SMintz, Yuval attn_type, &num_attn_regs); 55080ebbd1c8SMintz, Yuval 55090ebbd1c8SMintz, Yuval for (reg_idx = 0; reg_idx < num_attn_regs; reg_idx++) { 55100ebbd1c8SMintz, Yuval const struct dbg_attn_reg *reg_data = &attn_reg_arr[reg_idx]; 55110ebbd1c8SMintz, Yuval struct dbg_attn_reg_result *reg_result; 55120ebbd1c8SMintz, Yuval u32 sts_addr, sts_val; 55130ebbd1c8SMintz, Yuval u16 modes_buf_offset; 55140ebbd1c8SMintz, Yuval bool eval_mode; 55150ebbd1c8SMintz, Yuval 55160ebbd1c8SMintz, Yuval /* Check mode */ 55170ebbd1c8SMintz, Yuval eval_mode = GET_FIELD(reg_data->mode.data, 55180ebbd1c8SMintz, Yuval DBG_MODE_HDR_EVAL_MODE) > 0; 55190ebbd1c8SMintz, Yuval modes_buf_offset = GET_FIELD(reg_data->mode.data, 55200ebbd1c8SMintz, Yuval DBG_MODE_HDR_MODES_BUF_OFFSET); 55210ebbd1c8SMintz, Yuval if (eval_mode && !qed_is_mode_match(p_hwfn, &modes_buf_offset)) 55220ebbd1c8SMintz, Yuval continue; 55230ebbd1c8SMintz, Yuval 55240ebbd1c8SMintz, Yuval /* Mode match - read attention status register */ 55250ebbd1c8SMintz, Yuval sts_addr = DWORDS_TO_BYTES(clear_status ? 55260ebbd1c8SMintz, Yuval reg_data->sts_clr_address : 55270ebbd1c8SMintz, Yuval GET_FIELD(reg_data->data, 55280ebbd1c8SMintz, Yuval DBG_ATTN_REG_STS_ADDRESS)); 55290ebbd1c8SMintz, Yuval sts_val = qed_rd(p_hwfn, p_ptt, sts_addr); 55300ebbd1c8SMintz, Yuval if (!sts_val) 55310ebbd1c8SMintz, Yuval continue; 55320ebbd1c8SMintz, Yuval 55330ebbd1c8SMintz, Yuval /* Non-zero attention status - add to results */ 55340ebbd1c8SMintz, Yuval reg_result = &results->reg_results[num_result_regs]; 55350ebbd1c8SMintz, Yuval SET_FIELD(reg_result->data, 55360ebbd1c8SMintz, Yuval DBG_ATTN_REG_RESULT_STS_ADDRESS, sts_addr); 55370ebbd1c8SMintz, Yuval SET_FIELD(reg_result->data, 55380ebbd1c8SMintz, Yuval DBG_ATTN_REG_RESULT_NUM_REG_ATTN, 55390ebbd1c8SMintz, Yuval GET_FIELD(reg_data->data, DBG_ATTN_REG_NUM_REG_ATTN)); 55400ebbd1c8SMintz, Yuval reg_result->block_attn_offset = reg_data->block_attn_offset; 55410ebbd1c8SMintz, Yuval reg_result->sts_val = sts_val; 55420ebbd1c8SMintz, Yuval reg_result->mask_val = qed_rd(p_hwfn, 55430ebbd1c8SMintz, Yuval p_ptt, 55440ebbd1c8SMintz, Yuval DWORDS_TO_BYTES 55450ebbd1c8SMintz, Yuval (reg_data->mask_address)); 55460ebbd1c8SMintz, Yuval num_result_regs++; 55470ebbd1c8SMintz, Yuval } 55480ebbd1c8SMintz, Yuval 55490ebbd1c8SMintz, Yuval results->block_id = (u8)block_id; 55500ebbd1c8SMintz, Yuval results->names_offset = 55510ebbd1c8SMintz, Yuval qed_get_block_attn_data(block_id, attn_type)->names_offset; 55520ebbd1c8SMintz, Yuval SET_FIELD(results->data, DBG_ATTN_BLOCK_RESULT_ATTN_TYPE, attn_type); 55530ebbd1c8SMintz, Yuval SET_FIELD(results->data, 55540ebbd1c8SMintz, Yuval DBG_ATTN_BLOCK_RESULT_NUM_REGS, num_result_regs); 55550ebbd1c8SMintz, Yuval 55560ebbd1c8SMintz, Yuval return DBG_STATUS_OK; 55570ebbd1c8SMintz, Yuval } 55580ebbd1c8SMintz, Yuval 5559c965db44STomer Tayar /******************************* Data Types **********************************/ 5560c965db44STomer Tayar 55610ebbd1c8SMintz, Yuval struct block_info { 55620ebbd1c8SMintz, Yuval const char *name; 55630ebbd1c8SMintz, Yuval enum block_id id; 55640ebbd1c8SMintz, Yuval }; 55650ebbd1c8SMintz, Yuval 5566c965db44STomer Tayar struct mcp_trace_format { 5567c965db44STomer Tayar u32 data; 5568c965db44STomer Tayar #define MCP_TRACE_FORMAT_MODULE_MASK 0x0000ffff 5569c965db44STomer Tayar #define MCP_TRACE_FORMAT_MODULE_SHIFT 0 5570c965db44STomer Tayar #define MCP_TRACE_FORMAT_LEVEL_MASK 0x00030000 5571c965db44STomer Tayar #define MCP_TRACE_FORMAT_LEVEL_SHIFT 16 5572c965db44STomer Tayar #define MCP_TRACE_FORMAT_P1_SIZE_MASK 0x000c0000 5573c965db44STomer Tayar #define MCP_TRACE_FORMAT_P1_SIZE_SHIFT 18 5574c965db44STomer Tayar #define MCP_TRACE_FORMAT_P2_SIZE_MASK 0x00300000 5575c965db44STomer Tayar #define MCP_TRACE_FORMAT_P2_SIZE_SHIFT 20 5576c965db44STomer Tayar #define MCP_TRACE_FORMAT_P3_SIZE_MASK 0x00c00000 5577c965db44STomer Tayar #define MCP_TRACE_FORMAT_P3_SIZE_SHIFT 22 5578c965db44STomer Tayar #define MCP_TRACE_FORMAT_LEN_MASK 0xff000000 5579c965db44STomer Tayar #define MCP_TRACE_FORMAT_LEN_SHIFT 24 55807b6859fbSMintz, Yuval 5581c965db44STomer Tayar char *format_str; 5582c965db44STomer Tayar }; 5583c965db44STomer Tayar 55847b6859fbSMintz, Yuval /* Meta data structure, generated by a perl script during MFW build. therefore, 55857b6859fbSMintz, Yuval * the structs mcp_trace_meta and mcp_trace_format are duplicated in the perl 55867b6859fbSMintz, Yuval * script. 55877b6859fbSMintz, Yuval */ 5588c965db44STomer Tayar struct mcp_trace_meta { 5589c965db44STomer Tayar u32 modules_num; 5590c965db44STomer Tayar char **modules; 5591c965db44STomer Tayar u32 formats_num; 5592c965db44STomer Tayar struct mcp_trace_format *formats; 5593c965db44STomer Tayar }; 5594c965db44STomer Tayar 55957b6859fbSMintz, Yuval /* REG fifo element */ 5596c965db44STomer Tayar struct reg_fifo_element { 5597c965db44STomer Tayar u64 data; 5598c965db44STomer Tayar #define REG_FIFO_ELEMENT_ADDRESS_SHIFT 0 5599c965db44STomer Tayar #define REG_FIFO_ELEMENT_ADDRESS_MASK 0x7fffff 5600c965db44STomer Tayar #define REG_FIFO_ELEMENT_ACCESS_SHIFT 23 5601c965db44STomer Tayar #define REG_FIFO_ELEMENT_ACCESS_MASK 0x1 5602c965db44STomer Tayar #define REG_FIFO_ELEMENT_PF_SHIFT 24 5603c965db44STomer Tayar #define REG_FIFO_ELEMENT_PF_MASK 0xf 5604c965db44STomer Tayar #define REG_FIFO_ELEMENT_VF_SHIFT 28 5605c965db44STomer Tayar #define REG_FIFO_ELEMENT_VF_MASK 0xff 5606c965db44STomer Tayar #define REG_FIFO_ELEMENT_PORT_SHIFT 36 5607c965db44STomer Tayar #define REG_FIFO_ELEMENT_PORT_MASK 0x3 5608c965db44STomer Tayar #define REG_FIFO_ELEMENT_PRIVILEGE_SHIFT 38 5609c965db44STomer Tayar #define REG_FIFO_ELEMENT_PRIVILEGE_MASK 0x3 5610c965db44STomer Tayar #define REG_FIFO_ELEMENT_PROTECTION_SHIFT 40 5611c965db44STomer Tayar #define REG_FIFO_ELEMENT_PROTECTION_MASK 0x7 5612c965db44STomer Tayar #define REG_FIFO_ELEMENT_MASTER_SHIFT 43 5613c965db44STomer Tayar #define REG_FIFO_ELEMENT_MASTER_MASK 0xf 5614c965db44STomer Tayar #define REG_FIFO_ELEMENT_ERROR_SHIFT 47 5615c965db44STomer Tayar #define REG_FIFO_ELEMENT_ERROR_MASK 0x1f 5616c965db44STomer Tayar }; 5617c965db44STomer Tayar 5618c965db44STomer Tayar /* IGU fifo element */ 5619c965db44STomer Tayar struct igu_fifo_element { 5620c965db44STomer Tayar u32 dword0; 5621c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_FID_SHIFT 0 5622c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_FID_MASK 0xff 5623c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_IS_PF_SHIFT 8 5624c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_IS_PF_MASK 0x1 5625c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_SOURCE_SHIFT 9 5626c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_SOURCE_MASK 0xf 5627c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_ERR_TYPE_SHIFT 13 5628c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_ERR_TYPE_MASK 0xf 5629c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_CMD_ADDR_SHIFT 17 5630c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_CMD_ADDR_MASK 0x7fff 5631c965db44STomer Tayar u32 dword1; 5632c965db44STomer Tayar u32 dword2; 5633c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD12_IS_WR_CMD_SHIFT 0 5634c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD12_IS_WR_CMD_MASK 0x1 5635c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD12_WR_DATA_SHIFT 1 5636c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD12_WR_DATA_MASK 0xffffffff 5637c965db44STomer Tayar u32 reserved; 5638c965db44STomer Tayar }; 5639c965db44STomer Tayar 5640c965db44STomer Tayar struct igu_fifo_wr_data { 5641c965db44STomer Tayar u32 data; 5642c965db44STomer Tayar #define IGU_FIFO_WR_DATA_PROD_CONS_SHIFT 0 5643c965db44STomer Tayar #define IGU_FIFO_WR_DATA_PROD_CONS_MASK 0xffffff 5644c965db44STomer Tayar #define IGU_FIFO_WR_DATA_UPDATE_FLAG_SHIFT 24 5645c965db44STomer Tayar #define IGU_FIFO_WR_DATA_UPDATE_FLAG_MASK 0x1 5646c965db44STomer Tayar #define IGU_FIFO_WR_DATA_EN_DIS_INT_FOR_SB_SHIFT 25 5647c965db44STomer Tayar #define IGU_FIFO_WR_DATA_EN_DIS_INT_FOR_SB_MASK 0x3 5648c965db44STomer Tayar #define IGU_FIFO_WR_DATA_SEGMENT_SHIFT 27 5649c965db44STomer Tayar #define IGU_FIFO_WR_DATA_SEGMENT_MASK 0x1 5650c965db44STomer Tayar #define IGU_FIFO_WR_DATA_TIMER_MASK_SHIFT 28 5651c965db44STomer Tayar #define IGU_FIFO_WR_DATA_TIMER_MASK_MASK 0x1 5652c965db44STomer Tayar #define IGU_FIFO_WR_DATA_CMD_TYPE_SHIFT 31 5653c965db44STomer Tayar #define IGU_FIFO_WR_DATA_CMD_TYPE_MASK 0x1 5654c965db44STomer Tayar }; 5655c965db44STomer Tayar 5656c965db44STomer Tayar struct igu_fifo_cleanup_wr_data { 5657c965db44STomer Tayar u32 data; 5658c965db44STomer Tayar #define IGU_FIFO_CLEANUP_WR_DATA_RESERVED_SHIFT 0 5659c965db44STomer Tayar #define IGU_FIFO_CLEANUP_WR_DATA_RESERVED_MASK 0x7ffffff 5660c965db44STomer Tayar #define IGU_FIFO_CLEANUP_WR_DATA_CLEANUP_VAL_SHIFT 27 5661c965db44STomer Tayar #define IGU_FIFO_CLEANUP_WR_DATA_CLEANUP_VAL_MASK 0x1 5662c965db44STomer Tayar #define IGU_FIFO_CLEANUP_WR_DATA_CLEANUP_TYPE_SHIFT 28 5663c965db44STomer Tayar #define IGU_FIFO_CLEANUP_WR_DATA_CLEANUP_TYPE_MASK 0x7 5664c965db44STomer Tayar #define IGU_FIFO_CLEANUP_WR_DATA_CMD_TYPE_SHIFT 31 5665c965db44STomer Tayar #define IGU_FIFO_CLEANUP_WR_DATA_CMD_TYPE_MASK 0x1 5666c965db44STomer Tayar }; 5667c965db44STomer Tayar 5668c965db44STomer Tayar /* Protection override element */ 5669c965db44STomer Tayar struct protection_override_element { 5670c965db44STomer Tayar u64 data; 5671c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_ADDRESS_SHIFT 0 5672c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_ADDRESS_MASK 0x7fffff 5673c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_WINDOW_SIZE_SHIFT 23 5674c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_WINDOW_SIZE_MASK 0xffffff 5675c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_READ_SHIFT 47 5676c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_READ_MASK 0x1 5677c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_WRITE_SHIFT 48 5678c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_WRITE_MASK 0x1 5679c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_READ_PROTECTION_SHIFT 49 5680c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_READ_PROTECTION_MASK 0x7 5681c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_WRITE_PROTECTION_SHIFT 52 5682c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_WRITE_PROTECTION_MASK 0x7 5683c965db44STomer Tayar }; 5684c965db44STomer Tayar 5685c965db44STomer Tayar enum igu_fifo_sources { 5686c965db44STomer Tayar IGU_SRC_PXP0, 5687c965db44STomer Tayar IGU_SRC_PXP1, 5688c965db44STomer Tayar IGU_SRC_PXP2, 5689c965db44STomer Tayar IGU_SRC_PXP3, 5690c965db44STomer Tayar IGU_SRC_PXP4, 5691c965db44STomer Tayar IGU_SRC_PXP5, 5692c965db44STomer Tayar IGU_SRC_PXP6, 5693c965db44STomer Tayar IGU_SRC_PXP7, 5694c965db44STomer Tayar IGU_SRC_CAU, 5695c965db44STomer Tayar IGU_SRC_ATTN, 5696c965db44STomer Tayar IGU_SRC_GRC 5697c965db44STomer Tayar }; 5698c965db44STomer Tayar 5699c965db44STomer Tayar enum igu_fifo_addr_types { 5700c965db44STomer Tayar IGU_ADDR_TYPE_MSIX_MEM, 5701c965db44STomer Tayar IGU_ADDR_TYPE_WRITE_PBA, 5702c965db44STomer Tayar IGU_ADDR_TYPE_WRITE_INT_ACK, 5703c965db44STomer Tayar IGU_ADDR_TYPE_WRITE_ATTN_BITS, 5704c965db44STomer Tayar IGU_ADDR_TYPE_READ_INT, 5705c965db44STomer Tayar IGU_ADDR_TYPE_WRITE_PROD_UPDATE, 5706c965db44STomer Tayar IGU_ADDR_TYPE_RESERVED 5707c965db44STomer Tayar }; 5708c965db44STomer Tayar 5709c965db44STomer Tayar struct igu_fifo_addr_data { 5710c965db44STomer Tayar u16 start_addr; 5711c965db44STomer Tayar u16 end_addr; 5712c965db44STomer Tayar char *desc; 5713c965db44STomer Tayar char *vf_desc; 5714c965db44STomer Tayar enum igu_fifo_addr_types type; 5715c965db44STomer Tayar }; 5716c965db44STomer Tayar 5717c965db44STomer Tayar /******************************** Constants **********************************/ 5718c965db44STomer Tayar 5719c965db44STomer Tayar #define MAX_MSG_LEN 1024 57207b6859fbSMintz, Yuval 5721c965db44STomer Tayar #define MCP_TRACE_MAX_MODULE_LEN 8 5722c965db44STomer Tayar #define MCP_TRACE_FORMAT_MAX_PARAMS 3 5723c965db44STomer Tayar #define MCP_TRACE_FORMAT_PARAM_WIDTH \ 5724c965db44STomer Tayar (MCP_TRACE_FORMAT_P2_SIZE_SHIFT - MCP_TRACE_FORMAT_P1_SIZE_SHIFT) 57257b6859fbSMintz, Yuval 5726c965db44STomer Tayar #define REG_FIFO_ELEMENT_ADDR_FACTOR 4 5727c965db44STomer Tayar #define REG_FIFO_ELEMENT_IS_PF_VF_VAL 127 57287b6859fbSMintz, Yuval 5729c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_ADDR_FACTOR 4 5730c965db44STomer Tayar 5731c965db44STomer Tayar /***************************** Constant Arrays *******************************/ 5732c965db44STomer Tayar 57337b6859fbSMintz, Yuval struct user_dbg_array { 57347b6859fbSMintz, Yuval const u32 *ptr; 57357b6859fbSMintz, Yuval u32 size_in_dwords; 57367b6859fbSMintz, Yuval }; 57377b6859fbSMintz, Yuval 57387b6859fbSMintz, Yuval /* Debug arrays */ 57397b6859fbSMintz, Yuval static struct user_dbg_array 57407b6859fbSMintz, Yuval s_user_dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE] = { {NULL} }; 57417b6859fbSMintz, Yuval 57420ebbd1c8SMintz, Yuval /* Block names array */ 57430ebbd1c8SMintz, Yuval static struct block_info s_block_info_arr[] = { 57440ebbd1c8SMintz, Yuval {"grc", BLOCK_GRC}, 57450ebbd1c8SMintz, Yuval {"miscs", BLOCK_MISCS}, 57460ebbd1c8SMintz, Yuval {"misc", BLOCK_MISC}, 57470ebbd1c8SMintz, Yuval {"dbu", BLOCK_DBU}, 57480ebbd1c8SMintz, Yuval {"pglue_b", BLOCK_PGLUE_B}, 57490ebbd1c8SMintz, Yuval {"cnig", BLOCK_CNIG}, 57500ebbd1c8SMintz, Yuval {"cpmu", BLOCK_CPMU}, 57510ebbd1c8SMintz, Yuval {"ncsi", BLOCK_NCSI}, 57520ebbd1c8SMintz, Yuval {"opte", BLOCK_OPTE}, 57530ebbd1c8SMintz, Yuval {"bmb", BLOCK_BMB}, 57540ebbd1c8SMintz, Yuval {"pcie", BLOCK_PCIE}, 57550ebbd1c8SMintz, Yuval {"mcp", BLOCK_MCP}, 57560ebbd1c8SMintz, Yuval {"mcp2", BLOCK_MCP2}, 57570ebbd1c8SMintz, Yuval {"pswhst", BLOCK_PSWHST}, 57580ebbd1c8SMintz, Yuval {"pswhst2", BLOCK_PSWHST2}, 57590ebbd1c8SMintz, Yuval {"pswrd", BLOCK_PSWRD}, 57600ebbd1c8SMintz, Yuval {"pswrd2", BLOCK_PSWRD2}, 57610ebbd1c8SMintz, Yuval {"pswwr", BLOCK_PSWWR}, 57620ebbd1c8SMintz, Yuval {"pswwr2", BLOCK_PSWWR2}, 57630ebbd1c8SMintz, Yuval {"pswrq", BLOCK_PSWRQ}, 57640ebbd1c8SMintz, Yuval {"pswrq2", BLOCK_PSWRQ2}, 57650ebbd1c8SMintz, Yuval {"pglcs", BLOCK_PGLCS}, 57660ebbd1c8SMintz, Yuval {"ptu", BLOCK_PTU}, 57670ebbd1c8SMintz, Yuval {"dmae", BLOCK_DMAE}, 57680ebbd1c8SMintz, Yuval {"tcm", BLOCK_TCM}, 57690ebbd1c8SMintz, Yuval {"mcm", BLOCK_MCM}, 57700ebbd1c8SMintz, Yuval {"ucm", BLOCK_UCM}, 57710ebbd1c8SMintz, Yuval {"xcm", BLOCK_XCM}, 57720ebbd1c8SMintz, Yuval {"ycm", BLOCK_YCM}, 57730ebbd1c8SMintz, Yuval {"pcm", BLOCK_PCM}, 57740ebbd1c8SMintz, Yuval {"qm", BLOCK_QM}, 57750ebbd1c8SMintz, Yuval {"tm", BLOCK_TM}, 57760ebbd1c8SMintz, Yuval {"dorq", BLOCK_DORQ}, 57770ebbd1c8SMintz, Yuval {"brb", BLOCK_BRB}, 57780ebbd1c8SMintz, Yuval {"src", BLOCK_SRC}, 57790ebbd1c8SMintz, Yuval {"prs", BLOCK_PRS}, 57800ebbd1c8SMintz, Yuval {"tsdm", BLOCK_TSDM}, 57810ebbd1c8SMintz, Yuval {"msdm", BLOCK_MSDM}, 57820ebbd1c8SMintz, Yuval {"usdm", BLOCK_USDM}, 57830ebbd1c8SMintz, Yuval {"xsdm", BLOCK_XSDM}, 57840ebbd1c8SMintz, Yuval {"ysdm", BLOCK_YSDM}, 57850ebbd1c8SMintz, Yuval {"psdm", BLOCK_PSDM}, 57860ebbd1c8SMintz, Yuval {"tsem", BLOCK_TSEM}, 57870ebbd1c8SMintz, Yuval {"msem", BLOCK_MSEM}, 57880ebbd1c8SMintz, Yuval {"usem", BLOCK_USEM}, 57890ebbd1c8SMintz, Yuval {"xsem", BLOCK_XSEM}, 57900ebbd1c8SMintz, Yuval {"ysem", BLOCK_YSEM}, 57910ebbd1c8SMintz, Yuval {"psem", BLOCK_PSEM}, 57920ebbd1c8SMintz, Yuval {"rss", BLOCK_RSS}, 57930ebbd1c8SMintz, Yuval {"tmld", BLOCK_TMLD}, 57940ebbd1c8SMintz, Yuval {"muld", BLOCK_MULD}, 57950ebbd1c8SMintz, Yuval {"yuld", BLOCK_YULD}, 57960ebbd1c8SMintz, Yuval {"xyld", BLOCK_XYLD}, 57970ebbd1c8SMintz, Yuval {"ptld", BLOCK_PTLD}, 57980ebbd1c8SMintz, Yuval {"ypld", BLOCK_YPLD}, 57990ebbd1c8SMintz, Yuval {"prm", BLOCK_PRM}, 58000ebbd1c8SMintz, Yuval {"pbf_pb1", BLOCK_PBF_PB1}, 58010ebbd1c8SMintz, Yuval {"pbf_pb2", BLOCK_PBF_PB2}, 58020ebbd1c8SMintz, Yuval {"rpb", BLOCK_RPB}, 58030ebbd1c8SMintz, Yuval {"btb", BLOCK_BTB}, 58040ebbd1c8SMintz, Yuval {"pbf", BLOCK_PBF}, 58050ebbd1c8SMintz, Yuval {"rdif", BLOCK_RDIF}, 58060ebbd1c8SMintz, Yuval {"tdif", BLOCK_TDIF}, 58070ebbd1c8SMintz, Yuval {"cdu", BLOCK_CDU}, 58080ebbd1c8SMintz, Yuval {"ccfc", BLOCK_CCFC}, 58090ebbd1c8SMintz, Yuval {"tcfc", BLOCK_TCFC}, 58100ebbd1c8SMintz, Yuval {"igu", BLOCK_IGU}, 58110ebbd1c8SMintz, Yuval {"cau", BLOCK_CAU}, 58120ebbd1c8SMintz, Yuval {"rgfs", BLOCK_RGFS}, 58130ebbd1c8SMintz, Yuval {"rgsrc", BLOCK_RGSRC}, 58140ebbd1c8SMintz, Yuval {"tgfs", BLOCK_TGFS}, 58150ebbd1c8SMintz, Yuval {"tgsrc", BLOCK_TGSRC}, 58160ebbd1c8SMintz, Yuval {"umac", BLOCK_UMAC}, 58170ebbd1c8SMintz, Yuval {"xmac", BLOCK_XMAC}, 58180ebbd1c8SMintz, Yuval {"dbg", BLOCK_DBG}, 58190ebbd1c8SMintz, Yuval {"nig", BLOCK_NIG}, 58200ebbd1c8SMintz, Yuval {"wol", BLOCK_WOL}, 58210ebbd1c8SMintz, Yuval {"bmbn", BLOCK_BMBN}, 58220ebbd1c8SMintz, Yuval {"ipc", BLOCK_IPC}, 58230ebbd1c8SMintz, Yuval {"nwm", BLOCK_NWM}, 58240ebbd1c8SMintz, Yuval {"nws", BLOCK_NWS}, 58250ebbd1c8SMintz, Yuval {"ms", BLOCK_MS}, 58260ebbd1c8SMintz, Yuval {"phy_pcie", BLOCK_PHY_PCIE}, 58270ebbd1c8SMintz, Yuval {"led", BLOCK_LED}, 58280ebbd1c8SMintz, Yuval {"avs_wrap", BLOCK_AVS_WRAP}, 5829da090917STomer Tayar {"pxpreqbus", BLOCK_PXPREQBUS}, 58300ebbd1c8SMintz, Yuval {"misc_aeu", BLOCK_MISC_AEU}, 58310ebbd1c8SMintz, Yuval {"bar0_map", BLOCK_BAR0_MAP} 58320ebbd1c8SMintz, Yuval }; 58330ebbd1c8SMintz, Yuval 5834c965db44STomer Tayar /* Status string array */ 5835c965db44STomer Tayar static const char * const s_status_str[] = { 58367b6859fbSMintz, Yuval /* DBG_STATUS_OK */ 5837c965db44STomer Tayar "Operation completed successfully", 58387b6859fbSMintz, Yuval 58397b6859fbSMintz, Yuval /* DBG_STATUS_APP_VERSION_NOT_SET */ 5840c965db44STomer Tayar "Debug application version wasn't set", 58417b6859fbSMintz, Yuval 58427b6859fbSMintz, Yuval /* DBG_STATUS_UNSUPPORTED_APP_VERSION */ 5843c965db44STomer Tayar "Unsupported debug application version", 58447b6859fbSMintz, Yuval 58457b6859fbSMintz, Yuval /* DBG_STATUS_DBG_BLOCK_NOT_RESET */ 5846c965db44STomer Tayar "The debug block wasn't reset since the last recording", 58477b6859fbSMintz, Yuval 58487b6859fbSMintz, Yuval /* DBG_STATUS_INVALID_ARGS */ 5849c965db44STomer Tayar "Invalid arguments", 58507b6859fbSMintz, Yuval 58517b6859fbSMintz, Yuval /* DBG_STATUS_OUTPUT_ALREADY_SET */ 5852c965db44STomer Tayar "The debug output was already set", 58537b6859fbSMintz, Yuval 58547b6859fbSMintz, Yuval /* DBG_STATUS_INVALID_PCI_BUF_SIZE */ 5855c965db44STomer Tayar "Invalid PCI buffer size", 58567b6859fbSMintz, Yuval 58577b6859fbSMintz, Yuval /* DBG_STATUS_PCI_BUF_ALLOC_FAILED */ 5858c965db44STomer Tayar "PCI buffer allocation failed", 58597b6859fbSMintz, Yuval 58607b6859fbSMintz, Yuval /* DBG_STATUS_PCI_BUF_NOT_ALLOCATED */ 5861c965db44STomer Tayar "A PCI buffer wasn't allocated", 58627b6859fbSMintz, Yuval 58637b6859fbSMintz, Yuval /* DBG_STATUS_TOO_MANY_INPUTS */ 5864c965db44STomer Tayar "Too many inputs were enabled. Enabled less inputs, or set 'unifyInputs' to true", 58657b6859fbSMintz, Yuval 58667b6859fbSMintz, Yuval /* DBG_STATUS_INPUT_OVERLAP */ 58677b6859fbSMintz, Yuval "Overlapping debug bus inputs", 58687b6859fbSMintz, Yuval 58697b6859fbSMintz, Yuval /* DBG_STATUS_HW_ONLY_RECORDING */ 5870c965db44STomer Tayar "Cannot record Storm data since the entire recording cycle is used by HW", 58717b6859fbSMintz, Yuval 58727b6859fbSMintz, Yuval /* DBG_STATUS_STORM_ALREADY_ENABLED */ 5873c965db44STomer Tayar "The Storm was already enabled", 58747b6859fbSMintz, Yuval 58757b6859fbSMintz, Yuval /* DBG_STATUS_STORM_NOT_ENABLED */ 5876c965db44STomer Tayar "The specified Storm wasn't enabled", 58777b6859fbSMintz, Yuval 58787b6859fbSMintz, Yuval /* DBG_STATUS_BLOCK_ALREADY_ENABLED */ 5879c965db44STomer Tayar "The block was already enabled", 58807b6859fbSMintz, Yuval 58817b6859fbSMintz, Yuval /* DBG_STATUS_BLOCK_NOT_ENABLED */ 5882c965db44STomer Tayar "The specified block wasn't enabled", 58837b6859fbSMintz, Yuval 58847b6859fbSMintz, Yuval /* DBG_STATUS_NO_INPUT_ENABLED */ 5885c965db44STomer Tayar "No input was enabled for recording", 58867b6859fbSMintz, Yuval 58877b6859fbSMintz, Yuval /* DBG_STATUS_NO_FILTER_TRIGGER_64B */ 5888c965db44STomer Tayar "Filters and triggers are not allowed when recording in 64b units", 58897b6859fbSMintz, Yuval 58907b6859fbSMintz, Yuval /* DBG_STATUS_FILTER_ALREADY_ENABLED */ 5891c965db44STomer Tayar "The filter was already enabled", 58927b6859fbSMintz, Yuval 58937b6859fbSMintz, Yuval /* DBG_STATUS_TRIGGER_ALREADY_ENABLED */ 5894c965db44STomer Tayar "The trigger was already enabled", 58957b6859fbSMintz, Yuval 58967b6859fbSMintz, Yuval /* DBG_STATUS_TRIGGER_NOT_ENABLED */ 5897c965db44STomer Tayar "The trigger wasn't enabled", 58987b6859fbSMintz, Yuval 58997b6859fbSMintz, Yuval /* DBG_STATUS_CANT_ADD_CONSTRAINT */ 5900c965db44STomer Tayar "A constraint can be added only after a filter was enabled or a trigger state was added", 59017b6859fbSMintz, Yuval 59027b6859fbSMintz, Yuval /* DBG_STATUS_TOO_MANY_TRIGGER_STATES */ 5903c965db44STomer Tayar "Cannot add more than 3 trigger states", 59047b6859fbSMintz, Yuval 59057b6859fbSMintz, Yuval /* DBG_STATUS_TOO_MANY_CONSTRAINTS */ 5906c965db44STomer Tayar "Cannot add more than 4 constraints per filter or trigger state", 59077b6859fbSMintz, Yuval 59087b6859fbSMintz, Yuval /* DBG_STATUS_RECORDING_NOT_STARTED */ 5909c965db44STomer Tayar "The recording wasn't started", 59107b6859fbSMintz, Yuval 59117b6859fbSMintz, Yuval /* DBG_STATUS_DATA_DIDNT_TRIGGER */ 5912c965db44STomer Tayar "A trigger was configured, but it didn't trigger", 59137b6859fbSMintz, Yuval 59147b6859fbSMintz, Yuval /* DBG_STATUS_NO_DATA_RECORDED */ 5915c965db44STomer Tayar "No data was recorded", 59167b6859fbSMintz, Yuval 59177b6859fbSMintz, Yuval /* DBG_STATUS_DUMP_BUF_TOO_SMALL */ 5918c965db44STomer Tayar "Dump buffer is too small", 59197b6859fbSMintz, Yuval 59207b6859fbSMintz, Yuval /* DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED */ 5921c965db44STomer Tayar "Dumped data is not aligned to chunks", 59227b6859fbSMintz, Yuval 59237b6859fbSMintz, Yuval /* DBG_STATUS_UNKNOWN_CHIP */ 5924c965db44STomer Tayar "Unknown chip", 59257b6859fbSMintz, Yuval 59267b6859fbSMintz, Yuval /* DBG_STATUS_VIRT_MEM_ALLOC_FAILED */ 5927c965db44STomer Tayar "Failed allocating virtual memory", 59287b6859fbSMintz, Yuval 59297b6859fbSMintz, Yuval /* DBG_STATUS_BLOCK_IN_RESET */ 5930c965db44STomer Tayar "The input block is in reset", 59317b6859fbSMintz, Yuval 59327b6859fbSMintz, Yuval /* DBG_STATUS_INVALID_TRACE_SIGNATURE */ 5933c965db44STomer Tayar "Invalid MCP trace signature found in NVRAM", 59347b6859fbSMintz, Yuval 59357b6859fbSMintz, Yuval /* DBG_STATUS_INVALID_NVRAM_BUNDLE */ 5936c965db44STomer Tayar "Invalid bundle ID found in NVRAM", 59377b6859fbSMintz, Yuval 59387b6859fbSMintz, Yuval /* DBG_STATUS_NVRAM_GET_IMAGE_FAILED */ 5939c965db44STomer Tayar "Failed getting NVRAM image", 59407b6859fbSMintz, Yuval 59417b6859fbSMintz, Yuval /* DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE */ 5942c965db44STomer Tayar "NVRAM image is not dword-aligned", 59437b6859fbSMintz, Yuval 59447b6859fbSMintz, Yuval /* DBG_STATUS_NVRAM_READ_FAILED */ 5945c965db44STomer Tayar "Failed reading from NVRAM", 59467b6859fbSMintz, Yuval 59477b6859fbSMintz, Yuval /* DBG_STATUS_IDLE_CHK_PARSE_FAILED */ 5948c965db44STomer Tayar "Idle check parsing failed", 59497b6859fbSMintz, Yuval 59507b6859fbSMintz, Yuval /* DBG_STATUS_MCP_TRACE_BAD_DATA */ 5951c965db44STomer Tayar "MCP Trace data is corrupt", 59527b6859fbSMintz, Yuval 59537b6859fbSMintz, Yuval /* DBG_STATUS_MCP_TRACE_NO_META */ 59547b6859fbSMintz, Yuval "Dump doesn't contain meta data - it must be provided in image file", 59557b6859fbSMintz, Yuval 59567b6859fbSMintz, Yuval /* DBG_STATUS_MCP_COULD_NOT_HALT */ 5957c965db44STomer Tayar "Failed to halt MCP", 59587b6859fbSMintz, Yuval 59597b6859fbSMintz, Yuval /* DBG_STATUS_MCP_COULD_NOT_RESUME */ 5960c965db44STomer Tayar "Failed to resume MCP after halt", 59617b6859fbSMintz, Yuval 5962da090917STomer Tayar /* DBG_STATUS_RESERVED2 */ 5963da090917STomer Tayar "Reserved debug status - shouldn't be returned", 59647b6859fbSMintz, Yuval 59657b6859fbSMintz, Yuval /* DBG_STATUS_SEMI_FIFO_NOT_EMPTY */ 5966c965db44STomer Tayar "Failed to empty SEMI sync FIFO", 59677b6859fbSMintz, Yuval 59687b6859fbSMintz, Yuval /* DBG_STATUS_IGU_FIFO_BAD_DATA */ 5969c965db44STomer Tayar "IGU FIFO data is corrupt", 59707b6859fbSMintz, Yuval 59717b6859fbSMintz, Yuval /* DBG_STATUS_MCP_COULD_NOT_MASK_PRTY */ 5972c965db44STomer Tayar "MCP failed to mask parities", 59737b6859fbSMintz, Yuval 59747b6859fbSMintz, Yuval /* DBG_STATUS_FW_ASSERTS_PARSE_FAILED */ 5975c965db44STomer Tayar "FW Asserts parsing failed", 59767b6859fbSMintz, Yuval 59777b6859fbSMintz, Yuval /* DBG_STATUS_REG_FIFO_BAD_DATA */ 5978c965db44STomer Tayar "GRC FIFO data is corrupt", 59797b6859fbSMintz, Yuval 59807b6859fbSMintz, Yuval /* DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA */ 5981c965db44STomer Tayar "Protection Override data is corrupt", 59827b6859fbSMintz, Yuval 59837b6859fbSMintz, Yuval /* DBG_STATUS_DBG_ARRAY_NOT_SET */ 5984c965db44STomer Tayar "Debug arrays were not set (when using binary files, dbg_set_bin_ptr must be called)", 59857b6859fbSMintz, Yuval 59867b6859fbSMintz, Yuval /* DBG_STATUS_FILTER_BUG */ 59877b6859fbSMintz, Yuval "Debug Bus filtering requires the -unifyInputs option (due to a HW bug)", 59887b6859fbSMintz, Yuval 59897b6859fbSMintz, Yuval /* DBG_STATUS_NON_MATCHING_LINES */ 59907b6859fbSMintz, Yuval "Non-matching debug lines - all lines must be of the same type (either 128b or 256b)", 59917b6859fbSMintz, Yuval 59927b6859fbSMintz, Yuval /* DBG_STATUS_INVALID_TRIGGER_DWORD_OFFSET */ 59937b6859fbSMintz, Yuval "The selected trigger dword offset wasn't enabled in the recorded HW block", 59947b6859fbSMintz, Yuval 59957b6859fbSMintz, Yuval /* DBG_STATUS_DBG_BUS_IN_USE */ 59967b6859fbSMintz, Yuval "The debug bus is in use" 5997c965db44STomer Tayar }; 5998c965db44STomer Tayar 5999c965db44STomer Tayar /* Idle check severity names array */ 6000c965db44STomer Tayar static const char * const s_idle_chk_severity_str[] = { 6001c965db44STomer Tayar "Error", 6002c965db44STomer Tayar "Error if no traffic", 6003c965db44STomer Tayar "Warning" 6004c965db44STomer Tayar }; 6005c965db44STomer Tayar 6006c965db44STomer Tayar /* MCP Trace level names array */ 6007c965db44STomer Tayar static const char * const s_mcp_trace_level_str[] = { 6008c965db44STomer Tayar "ERROR", 6009c965db44STomer Tayar "TRACE", 6010c965db44STomer Tayar "DEBUG" 6011c965db44STomer Tayar }; 6012c965db44STomer Tayar 60137b6859fbSMintz, Yuval /* Access type names array */ 6014c965db44STomer Tayar static const char * const s_access_strs[] = { 6015c965db44STomer Tayar "read", 6016c965db44STomer Tayar "write" 6017c965db44STomer Tayar }; 6018c965db44STomer Tayar 60197b6859fbSMintz, Yuval /* Privilege type names array */ 6020c965db44STomer Tayar static const char * const s_privilege_strs[] = { 6021c965db44STomer Tayar "VF", 6022c965db44STomer Tayar "PDA", 6023c965db44STomer Tayar "HV", 6024c965db44STomer Tayar "UA" 6025c965db44STomer Tayar }; 6026c965db44STomer Tayar 60277b6859fbSMintz, Yuval /* Protection type names array */ 6028c965db44STomer Tayar static const char * const s_protection_strs[] = { 6029c965db44STomer Tayar "(default)", 6030c965db44STomer Tayar "(default)", 6031c965db44STomer Tayar "(default)", 6032c965db44STomer Tayar "(default)", 6033c965db44STomer Tayar "override VF", 6034c965db44STomer Tayar "override PDA", 6035c965db44STomer Tayar "override HV", 6036c965db44STomer Tayar "override UA" 6037c965db44STomer Tayar }; 6038c965db44STomer Tayar 60397b6859fbSMintz, Yuval /* Master type names array */ 6040c965db44STomer Tayar static const char * const s_master_strs[] = { 6041c965db44STomer Tayar "???", 6042c965db44STomer Tayar "pxp", 6043c965db44STomer Tayar "mcp", 6044c965db44STomer Tayar "msdm", 6045c965db44STomer Tayar "psdm", 6046c965db44STomer Tayar "ysdm", 6047c965db44STomer Tayar "usdm", 6048c965db44STomer Tayar "tsdm", 6049c965db44STomer Tayar "xsdm", 6050c965db44STomer Tayar "dbu", 6051c965db44STomer Tayar "dmae", 6052c965db44STomer Tayar "???", 6053c965db44STomer Tayar "???", 6054c965db44STomer Tayar "???", 6055c965db44STomer Tayar "???", 6056c965db44STomer Tayar "???" 6057c965db44STomer Tayar }; 6058c965db44STomer Tayar 60597b6859fbSMintz, Yuval /* REG FIFO error messages array */ 6060c965db44STomer Tayar static const char * const s_reg_fifo_error_strs[] = { 6061c965db44STomer Tayar "grc timeout", 6062c965db44STomer Tayar "address doesn't belong to any block", 6063c965db44STomer Tayar "reserved address in block or write to read-only address", 6064c965db44STomer Tayar "privilege/protection mismatch", 6065c965db44STomer Tayar "path isolation error" 6066c965db44STomer Tayar }; 6067c965db44STomer Tayar 60687b6859fbSMintz, Yuval /* IGU FIFO sources array */ 6069c965db44STomer Tayar static const char * const s_igu_fifo_source_strs[] = { 6070c965db44STomer Tayar "TSTORM", 6071c965db44STomer Tayar "MSTORM", 6072c965db44STomer Tayar "USTORM", 6073c965db44STomer Tayar "XSTORM", 6074c965db44STomer Tayar "YSTORM", 6075c965db44STomer Tayar "PSTORM", 6076c965db44STomer Tayar "PCIE", 6077c965db44STomer Tayar "NIG_QM_PBF", 6078c965db44STomer Tayar "CAU", 6079c965db44STomer Tayar "ATTN", 6080c965db44STomer Tayar "GRC", 6081c965db44STomer Tayar }; 6082c965db44STomer Tayar 60837b6859fbSMintz, Yuval /* IGU FIFO error messages */ 6084c965db44STomer Tayar static const char * const s_igu_fifo_error_strs[] = { 6085c965db44STomer Tayar "no error", 6086c965db44STomer Tayar "length error", 6087c965db44STomer Tayar "function disabled", 6088c965db44STomer Tayar "VF sent command to attnetion address", 6089c965db44STomer Tayar "host sent prod update command", 6090c965db44STomer Tayar "read of during interrupt register while in MIMD mode", 6091c965db44STomer Tayar "access to PXP BAR reserved address", 6092c965db44STomer Tayar "producer update command to attention index", 6093c965db44STomer Tayar "unknown error", 6094c965db44STomer Tayar "SB index not valid", 6095c965db44STomer Tayar "SB relative index and FID not found", 6096c965db44STomer Tayar "FID not match", 6097c965db44STomer Tayar "command with error flag asserted (PCI error or CAU discard)", 6098c965db44STomer Tayar "VF sent cleanup and RF cleanup is disabled", 6099c965db44STomer Tayar "cleanup command on type bigger than 4" 6100c965db44STomer Tayar }; 6101c965db44STomer Tayar 6102c965db44STomer Tayar /* IGU FIFO address data */ 6103c965db44STomer Tayar static const struct igu_fifo_addr_data s_igu_fifo_addr_data[] = { 61047b6859fbSMintz, Yuval {0x0, 0x101, "MSI-X Memory", NULL, 61057b6859fbSMintz, Yuval IGU_ADDR_TYPE_MSIX_MEM}, 61067b6859fbSMintz, Yuval {0x102, 0x1ff, "reserved", NULL, 61077b6859fbSMintz, Yuval IGU_ADDR_TYPE_RESERVED}, 61087b6859fbSMintz, Yuval {0x200, 0x200, "Write PBA[0:63]", NULL, 61097b6859fbSMintz, Yuval IGU_ADDR_TYPE_WRITE_PBA}, 6110c965db44STomer Tayar {0x201, 0x201, "Write PBA[64:127]", "reserved", 6111c965db44STomer Tayar IGU_ADDR_TYPE_WRITE_PBA}, 61127b6859fbSMintz, Yuval {0x202, 0x202, "Write PBA[128]", "reserved", 61137b6859fbSMintz, Yuval IGU_ADDR_TYPE_WRITE_PBA}, 61147b6859fbSMintz, Yuval {0x203, 0x3ff, "reserved", NULL, 61157b6859fbSMintz, Yuval IGU_ADDR_TYPE_RESERVED}, 6116c965db44STomer Tayar {0x400, 0x5ef, "Write interrupt acknowledgment", NULL, 6117c965db44STomer Tayar IGU_ADDR_TYPE_WRITE_INT_ACK}, 6118c965db44STomer Tayar {0x5f0, 0x5f0, "Attention bits update", NULL, 6119c965db44STomer Tayar IGU_ADDR_TYPE_WRITE_ATTN_BITS}, 6120c965db44STomer Tayar {0x5f1, 0x5f1, "Attention bits set", NULL, 6121c965db44STomer Tayar IGU_ADDR_TYPE_WRITE_ATTN_BITS}, 6122c965db44STomer Tayar {0x5f2, 0x5f2, "Attention bits clear", NULL, 6123c965db44STomer Tayar IGU_ADDR_TYPE_WRITE_ATTN_BITS}, 6124c965db44STomer Tayar {0x5f3, 0x5f3, "Read interrupt 0:63 with mask", NULL, 6125c965db44STomer Tayar IGU_ADDR_TYPE_READ_INT}, 6126c965db44STomer Tayar {0x5f4, 0x5f4, "Read interrupt 0:31 with mask", NULL, 6127c965db44STomer Tayar IGU_ADDR_TYPE_READ_INT}, 6128c965db44STomer Tayar {0x5f5, 0x5f5, "Read interrupt 32:63 with mask", NULL, 6129c965db44STomer Tayar IGU_ADDR_TYPE_READ_INT}, 6130c965db44STomer Tayar {0x5f6, 0x5f6, "Read interrupt 0:63 without mask", NULL, 6131c965db44STomer Tayar IGU_ADDR_TYPE_READ_INT}, 61327b6859fbSMintz, Yuval {0x5f7, 0x5ff, "reserved", NULL, 61337b6859fbSMintz, Yuval IGU_ADDR_TYPE_RESERVED}, 61347b6859fbSMintz, Yuval {0x600, 0x7ff, "Producer update", NULL, 61357b6859fbSMintz, Yuval IGU_ADDR_TYPE_WRITE_PROD_UPDATE} 6136c965db44STomer Tayar }; 6137c965db44STomer Tayar 6138c965db44STomer Tayar /******************************** Variables **********************************/ 6139c965db44STomer Tayar 614050bc60cbSMichal Kalderon /* MCP Trace meta data array - used in case the dump doesn't contain the 614150bc60cbSMichal Kalderon * meta data (e.g. due to no NVRAM access). 6142c965db44STomer Tayar */ 614350bc60cbSMichal Kalderon static struct user_dbg_array s_mcp_trace_meta_arr = { NULL, 0 }; 614450bc60cbSMichal Kalderon 614550bc60cbSMichal Kalderon /* Parsed MCP Trace meta data info, based on MCP trace meta array */ 614650bc60cbSMichal Kalderon static struct mcp_trace_meta s_mcp_trace_meta; 614750bc60cbSMichal Kalderon static bool s_mcp_trace_meta_valid; 6148c965db44STomer Tayar 6149c965db44STomer Tayar /* Temporary buffer, used for print size calculations */ 6150c965db44STomer Tayar static char s_temp_buf[MAX_MSG_LEN]; 6151c965db44STomer Tayar 61527b6859fbSMintz, Yuval /**************************** Private Functions ******************************/ 6153c965db44STomer Tayar 6154c965db44STomer Tayar static u32 qed_cyclic_add(u32 a, u32 b, u32 size) 6155c965db44STomer Tayar { 6156c965db44STomer Tayar return (a + b) % size; 6157c965db44STomer Tayar } 6158c965db44STomer Tayar 6159c965db44STomer Tayar static u32 qed_cyclic_sub(u32 a, u32 b, u32 size) 6160c965db44STomer Tayar { 6161c965db44STomer Tayar return (size + a - b) % size; 6162c965db44STomer Tayar } 6163c965db44STomer Tayar 6164c965db44STomer Tayar /* Reads the specified number of bytes from the specified cyclic buffer (up to 4 6165c965db44STomer Tayar * bytes) and returns them as a dword value. the specified buffer offset is 6166c965db44STomer Tayar * updated. 6167c965db44STomer Tayar */ 6168c965db44STomer Tayar static u32 qed_read_from_cyclic_buf(void *buf, 6169c965db44STomer Tayar u32 *offset, 6170c965db44STomer Tayar u32 buf_size, u8 num_bytes_to_read) 6171c965db44STomer Tayar { 61727b6859fbSMintz, Yuval u8 i, *val_ptr, *bytes_buf = (u8 *)buf; 6173c965db44STomer Tayar u32 val = 0; 6174c965db44STomer Tayar 6175c965db44STomer Tayar val_ptr = (u8 *)&val; 6176c965db44STomer Tayar 617750bc60cbSMichal Kalderon /* Assume running on a LITTLE ENDIAN and the buffer is network order 617850bc60cbSMichal Kalderon * (BIG ENDIAN), as high order bytes are placed in lower memory address. 617950bc60cbSMichal Kalderon */ 6180c965db44STomer Tayar for (i = 0; i < num_bytes_to_read; i++) { 6181c965db44STomer Tayar val_ptr[i] = bytes_buf[*offset]; 6182c965db44STomer Tayar *offset = qed_cyclic_add(*offset, 1, buf_size); 6183c965db44STomer Tayar } 6184c965db44STomer Tayar 6185c965db44STomer Tayar return val; 6186c965db44STomer Tayar } 6187c965db44STomer Tayar 6188c965db44STomer Tayar /* Reads and returns the next byte from the specified buffer. 6189c965db44STomer Tayar * The specified buffer offset is updated. 6190c965db44STomer Tayar */ 6191c965db44STomer Tayar static u8 qed_read_byte_from_buf(void *buf, u32 *offset) 6192c965db44STomer Tayar { 6193c965db44STomer Tayar return ((u8 *)buf)[(*offset)++]; 6194c965db44STomer Tayar } 6195c965db44STomer Tayar 6196c965db44STomer Tayar /* Reads and returns the next dword from the specified buffer. 6197c965db44STomer Tayar * The specified buffer offset is updated. 6198c965db44STomer Tayar */ 6199c965db44STomer Tayar static u32 qed_read_dword_from_buf(void *buf, u32 *offset) 6200c965db44STomer Tayar { 6201c965db44STomer Tayar u32 dword_val = *(u32 *)&((u8 *)buf)[*offset]; 6202c965db44STomer Tayar 6203c965db44STomer Tayar *offset += 4; 62047b6859fbSMintz, Yuval 6205c965db44STomer Tayar return dword_val; 6206c965db44STomer Tayar } 6207c965db44STomer Tayar 6208c965db44STomer Tayar /* Reads the next string from the specified buffer, and copies it to the 6209c965db44STomer Tayar * specified pointer. The specified buffer offset is updated. 6210c965db44STomer Tayar */ 6211c965db44STomer Tayar static void qed_read_str_from_buf(void *buf, u32 *offset, u32 size, char *dest) 6212c965db44STomer Tayar { 6213c965db44STomer Tayar const char *source_str = &((const char *)buf)[*offset]; 6214c965db44STomer Tayar 6215c965db44STomer Tayar strncpy(dest, source_str, size); 6216c965db44STomer Tayar dest[size - 1] = '\0'; 6217c965db44STomer Tayar *offset += size; 6218c965db44STomer Tayar } 6219c965db44STomer Tayar 6220c965db44STomer Tayar /* Returns a pointer to the specified offset (in bytes) of the specified buffer. 6221c965db44STomer Tayar * If the specified buffer in NULL, a temporary buffer pointer is returned. 6222c965db44STomer Tayar */ 6223c965db44STomer Tayar static char *qed_get_buf_ptr(void *buf, u32 offset) 6224c965db44STomer Tayar { 6225c965db44STomer Tayar return buf ? (char *)buf + offset : s_temp_buf; 6226c965db44STomer Tayar } 6227c965db44STomer Tayar 6228c965db44STomer Tayar /* Reads a param from the specified buffer. Returns the number of dwords read. 6229c965db44STomer Tayar * If the returned str_param is NULL, the param is numeric and its value is 6230c965db44STomer Tayar * returned in num_param. 6231c965db44STomer Tayar * Otheriwise, the param is a string and its pointer is returned in str_param. 6232c965db44STomer Tayar */ 6233c965db44STomer Tayar static u32 qed_read_param(u32 *dump_buf, 6234c965db44STomer Tayar const char **param_name, 6235c965db44STomer Tayar const char **param_str_val, u32 *param_num_val) 6236c965db44STomer Tayar { 6237c965db44STomer Tayar char *char_buf = (char *)dump_buf; 62387b6859fbSMintz, Yuval size_t offset = 0; 6239c965db44STomer Tayar 6240c965db44STomer Tayar /* Extract param name */ 6241c965db44STomer Tayar *param_name = char_buf; 6242c965db44STomer Tayar offset += strlen(*param_name) + 1; 6243c965db44STomer Tayar 6244c965db44STomer Tayar /* Check param type */ 6245c965db44STomer Tayar if (*(char_buf + offset++)) { 6246c965db44STomer Tayar /* String param */ 6247c965db44STomer Tayar *param_str_val = char_buf + offset; 6248da090917STomer Tayar *param_num_val = 0; 6249c965db44STomer Tayar offset += strlen(*param_str_val) + 1; 6250c965db44STomer Tayar if (offset & 0x3) 6251c965db44STomer Tayar offset += (4 - (offset & 0x3)); 6252c965db44STomer Tayar } else { 6253c965db44STomer Tayar /* Numeric param */ 6254c965db44STomer Tayar *param_str_val = NULL; 6255c965db44STomer Tayar if (offset & 0x3) 6256c965db44STomer Tayar offset += (4 - (offset & 0x3)); 6257c965db44STomer Tayar *param_num_val = *(u32 *)(char_buf + offset); 6258c965db44STomer Tayar offset += 4; 6259c965db44STomer Tayar } 6260c965db44STomer Tayar 626150bc60cbSMichal Kalderon return (u32)offset / 4; 6262c965db44STomer Tayar } 6263c965db44STomer Tayar 6264c965db44STomer Tayar /* Reads a section header from the specified buffer. 6265c965db44STomer Tayar * Returns the number of dwords read. 6266c965db44STomer Tayar */ 6267c965db44STomer Tayar static u32 qed_read_section_hdr(u32 *dump_buf, 6268c965db44STomer Tayar const char **section_name, 6269c965db44STomer Tayar u32 *num_section_params) 6270c965db44STomer Tayar { 6271c965db44STomer Tayar const char *param_str_val; 6272c965db44STomer Tayar 6273c965db44STomer Tayar return qed_read_param(dump_buf, 6274c965db44STomer Tayar section_name, ¶m_str_val, num_section_params); 6275c965db44STomer Tayar } 6276c965db44STomer Tayar 6277c965db44STomer Tayar /* Reads section params from the specified buffer and prints them to the results 6278c965db44STomer Tayar * buffer. Returns the number of dwords read. 6279c965db44STomer Tayar */ 6280c965db44STomer Tayar static u32 qed_print_section_params(u32 *dump_buf, 6281c965db44STomer Tayar u32 num_section_params, 6282c965db44STomer Tayar char *results_buf, u32 *num_chars_printed) 6283c965db44STomer Tayar { 6284c965db44STomer Tayar u32 i, dump_offset = 0, results_offset = 0; 6285c965db44STomer Tayar 6286c965db44STomer Tayar for (i = 0; i < num_section_params; i++) { 62877b6859fbSMintz, Yuval const char *param_name, *param_str_val; 6288c965db44STomer Tayar u32 param_num_val = 0; 6289c965db44STomer Tayar 6290c965db44STomer Tayar dump_offset += qed_read_param(dump_buf + dump_offset, 6291c965db44STomer Tayar ¶m_name, 6292c965db44STomer Tayar ¶m_str_val, ¶m_num_val); 62937b6859fbSMintz, Yuval 6294c965db44STomer Tayar if (param_str_val) 6295c965db44STomer Tayar results_offset += 6296c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6297c965db44STomer Tayar results_offset), 6298c965db44STomer Tayar "%s: %s\n", param_name, param_str_val); 6299c965db44STomer Tayar else if (strcmp(param_name, "fw-timestamp")) 6300c965db44STomer Tayar results_offset += 6301c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6302c965db44STomer Tayar results_offset), 6303c965db44STomer Tayar "%s: %d\n", param_name, param_num_val); 6304c965db44STomer Tayar } 6305c965db44STomer Tayar 63067b6859fbSMintz, Yuval results_offset += sprintf(qed_get_buf_ptr(results_buf, results_offset), 63077b6859fbSMintz, Yuval "\n"); 6308c965db44STomer Tayar 63097b6859fbSMintz, Yuval *num_chars_printed = results_offset; 63107b6859fbSMintz, Yuval 63117b6859fbSMintz, Yuval return dump_offset; 6312c965db44STomer Tayar } 6313c965db44STomer Tayar 6314c965db44STomer Tayar /* Parses the idle check rules and returns the number of characters printed. 6315c965db44STomer Tayar * In case of parsing error, returns 0. 6316c965db44STomer Tayar */ 6317da090917STomer Tayar static u32 qed_parse_idle_chk_dump_rules(u32 *dump_buf, 6318c965db44STomer Tayar u32 *dump_buf_end, 6319c965db44STomer Tayar u32 num_rules, 6320c965db44STomer Tayar bool print_fw_idle_chk, 6321c965db44STomer Tayar char *results_buf, 6322c965db44STomer Tayar u32 *num_errors, u32 *num_warnings) 6323c965db44STomer Tayar { 63247b6859fbSMintz, Yuval /* Offset in results_buf in bytes */ 63257b6859fbSMintz, Yuval u32 results_offset = 0; 63267b6859fbSMintz, Yuval 63277b6859fbSMintz, Yuval u32 rule_idx; 6328c965db44STomer Tayar u16 i, j; 6329c965db44STomer Tayar 6330c965db44STomer Tayar *num_errors = 0; 6331c965db44STomer Tayar *num_warnings = 0; 6332c965db44STomer Tayar 6333c965db44STomer Tayar /* Go over dumped results */ 6334c965db44STomer Tayar for (rule_idx = 0; rule_idx < num_rules && dump_buf < dump_buf_end; 6335c965db44STomer Tayar rule_idx++) { 6336c965db44STomer Tayar const struct dbg_idle_chk_rule_parsing_data *rule_parsing_data; 6337c965db44STomer Tayar struct dbg_idle_chk_result_hdr *hdr; 63387b6859fbSMintz, Yuval const char *parsing_str, *lsi_msg; 6339c965db44STomer Tayar u32 parsing_str_offset; 6340c965db44STomer Tayar bool has_fw_msg; 63417b6859fbSMintz, Yuval u8 curr_reg_id; 6342c965db44STomer Tayar 6343c965db44STomer Tayar hdr = (struct dbg_idle_chk_result_hdr *)dump_buf; 6344c965db44STomer Tayar rule_parsing_data = 6345c965db44STomer Tayar (const struct dbg_idle_chk_rule_parsing_data *) 63467b6859fbSMintz, Yuval &s_user_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_PARSING_DATA]. 6347c965db44STomer Tayar ptr[hdr->rule_id]; 6348c965db44STomer Tayar parsing_str_offset = 6349c965db44STomer Tayar GET_FIELD(rule_parsing_data->data, 6350c965db44STomer Tayar DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET); 6351c965db44STomer Tayar has_fw_msg = 6352c965db44STomer Tayar GET_FIELD(rule_parsing_data->data, 6353c965db44STomer Tayar DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG) > 0; 63547b6859fbSMintz, Yuval parsing_str = 63557b6859fbSMintz, Yuval &((const char *) 63567b6859fbSMintz, Yuval s_user_dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS].ptr) 6357c965db44STomer Tayar [parsing_str_offset]; 6358c965db44STomer Tayar lsi_msg = parsing_str; 63597b6859fbSMintz, Yuval curr_reg_id = 0; 6360c965db44STomer Tayar 6361c965db44STomer Tayar if (hdr->severity >= MAX_DBG_IDLE_CHK_SEVERITY_TYPES) 6362c965db44STomer Tayar return 0; 6363c965db44STomer Tayar 6364c965db44STomer Tayar /* Skip rule header */ 63657b6859fbSMintz, Yuval dump_buf += BYTES_TO_DWORDS(sizeof(*hdr)); 6366c965db44STomer Tayar 6367c965db44STomer Tayar /* Update errors/warnings count */ 6368c965db44STomer Tayar if (hdr->severity == IDLE_CHK_SEVERITY_ERROR || 6369c965db44STomer Tayar hdr->severity == IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC) 6370c965db44STomer Tayar (*num_errors)++; 6371c965db44STomer Tayar else 6372c965db44STomer Tayar (*num_warnings)++; 6373c965db44STomer Tayar 6374c965db44STomer Tayar /* Print rule severity */ 6375c965db44STomer Tayar results_offset += 6376c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6377c965db44STomer Tayar results_offset), "%s: ", 6378c965db44STomer Tayar s_idle_chk_severity_str[hdr->severity]); 6379c965db44STomer Tayar 6380c965db44STomer Tayar /* Print rule message */ 6381c965db44STomer Tayar if (has_fw_msg) 6382c965db44STomer Tayar parsing_str += strlen(parsing_str) + 1; 6383c965db44STomer Tayar results_offset += 6384c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6385c965db44STomer Tayar results_offset), "%s.", 6386c965db44STomer Tayar has_fw_msg && 6387c965db44STomer Tayar print_fw_idle_chk ? parsing_str : lsi_msg); 6388c965db44STomer Tayar parsing_str += strlen(parsing_str) + 1; 6389c965db44STomer Tayar 6390c965db44STomer Tayar /* Print register values */ 6391c965db44STomer Tayar results_offset += 6392c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6393c965db44STomer Tayar results_offset), " Registers:"); 6394c965db44STomer Tayar for (i = 0; 6395c965db44STomer Tayar i < hdr->num_dumped_cond_regs + hdr->num_dumped_info_regs; 6396c965db44STomer Tayar i++) { 63977b6859fbSMintz, Yuval struct dbg_idle_chk_result_reg_hdr *reg_hdr; 63987b6859fbSMintz, Yuval bool is_mem; 63997b6859fbSMintz, Yuval u8 reg_id; 64007b6859fbSMintz, Yuval 64017b6859fbSMintz, Yuval reg_hdr = 64027b6859fbSMintz, Yuval (struct dbg_idle_chk_result_reg_hdr *)dump_buf; 64037b6859fbSMintz, Yuval is_mem = GET_FIELD(reg_hdr->data, 6404c965db44STomer Tayar DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM); 64057b6859fbSMintz, Yuval reg_id = GET_FIELD(reg_hdr->data, 6406c965db44STomer Tayar DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID); 6407c965db44STomer Tayar 6408c965db44STomer Tayar /* Skip reg header */ 64097b6859fbSMintz, Yuval dump_buf += BYTES_TO_DWORDS(sizeof(*reg_hdr)); 6410c965db44STomer Tayar 6411c965db44STomer Tayar /* Skip register names until the required reg_id is 6412c965db44STomer Tayar * reached. 6413c965db44STomer Tayar */ 6414c965db44STomer Tayar for (; reg_id > curr_reg_id; 6415c965db44STomer Tayar curr_reg_id++, 6416c965db44STomer Tayar parsing_str += strlen(parsing_str) + 1); 6417c965db44STomer Tayar 6418c965db44STomer Tayar results_offset += 6419c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6420c965db44STomer Tayar results_offset), " %s", 6421c965db44STomer Tayar parsing_str); 6422c965db44STomer Tayar if (i < hdr->num_dumped_cond_regs && is_mem) 6423c965db44STomer Tayar results_offset += 6424c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6425c965db44STomer Tayar results_offset), 6426c965db44STomer Tayar "[%d]", hdr->mem_entry_id + 6427c965db44STomer Tayar reg_hdr->start_entry); 6428c965db44STomer Tayar results_offset += 6429c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6430c965db44STomer Tayar results_offset), "="); 6431c965db44STomer Tayar for (j = 0; j < reg_hdr->size; j++, dump_buf++) { 6432c965db44STomer Tayar results_offset += 6433c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6434c965db44STomer Tayar results_offset), 6435c965db44STomer Tayar "0x%x", *dump_buf); 6436c965db44STomer Tayar if (j < reg_hdr->size - 1) 6437c965db44STomer Tayar results_offset += 6438c965db44STomer Tayar sprintf(qed_get_buf_ptr 6439c965db44STomer Tayar (results_buf, 6440c965db44STomer Tayar results_offset), ","); 6441c965db44STomer Tayar } 6442c965db44STomer Tayar } 6443c965db44STomer Tayar 6444c965db44STomer Tayar results_offset += 6445c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, results_offset), "\n"); 6446c965db44STomer Tayar } 6447c965db44STomer Tayar 6448c965db44STomer Tayar /* Check if end of dump buffer was exceeded */ 6449c965db44STomer Tayar if (dump_buf > dump_buf_end) 6450c965db44STomer Tayar return 0; 64517b6859fbSMintz, Yuval 6452c965db44STomer Tayar return results_offset; 6453c965db44STomer Tayar } 6454c965db44STomer Tayar 6455c965db44STomer Tayar /* Parses an idle check dump buffer. 6456c965db44STomer Tayar * If result_buf is not NULL, the idle check results are printed to it. 6457c965db44STomer Tayar * In any case, the required results buffer size is assigned to 6458c965db44STomer Tayar * parsed_results_bytes. 6459c965db44STomer Tayar * The parsing status is returned. 6460c965db44STomer Tayar */ 6461da090917STomer Tayar static enum dbg_status qed_parse_idle_chk_dump(u32 *dump_buf, 6462c965db44STomer Tayar u32 num_dumped_dwords, 6463c965db44STomer Tayar char *results_buf, 6464c965db44STomer Tayar u32 *parsed_results_bytes, 6465c965db44STomer Tayar u32 *num_errors, 6466c965db44STomer Tayar u32 *num_warnings) 6467c965db44STomer Tayar { 6468c965db44STomer Tayar const char *section_name, *param_name, *param_str_val; 6469c965db44STomer Tayar u32 *dump_buf_end = dump_buf + num_dumped_dwords; 6470c965db44STomer Tayar u32 num_section_params = 0, num_rules; 64717b6859fbSMintz, Yuval 64727b6859fbSMintz, Yuval /* Offset in results_buf in bytes */ 64737b6859fbSMintz, Yuval u32 results_offset = 0; 6474c965db44STomer Tayar 6475c965db44STomer Tayar *parsed_results_bytes = 0; 6476c965db44STomer Tayar *num_errors = 0; 6477c965db44STomer Tayar *num_warnings = 0; 64787b6859fbSMintz, Yuval 64797b6859fbSMintz, Yuval if (!s_user_dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS].ptr || 64807b6859fbSMintz, Yuval !s_user_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_PARSING_DATA].ptr) 6481c965db44STomer Tayar return DBG_STATUS_DBG_ARRAY_NOT_SET; 6482c965db44STomer Tayar 6483c965db44STomer Tayar /* Read global_params section */ 6484c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 6485c965db44STomer Tayar §ion_name, &num_section_params); 6486c965db44STomer Tayar if (strcmp(section_name, "global_params")) 6487c965db44STomer Tayar return DBG_STATUS_IDLE_CHK_PARSE_FAILED; 6488c965db44STomer Tayar 6489c965db44STomer Tayar /* Print global params */ 6490c965db44STomer Tayar dump_buf += qed_print_section_params(dump_buf, 6491c965db44STomer Tayar num_section_params, 6492c965db44STomer Tayar results_buf, &results_offset); 6493c965db44STomer Tayar 6494c965db44STomer Tayar /* Read idle_chk section */ 6495c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 6496c965db44STomer Tayar §ion_name, &num_section_params); 6497c965db44STomer Tayar if (strcmp(section_name, "idle_chk") || num_section_params != 1) 6498c965db44STomer Tayar return DBG_STATUS_IDLE_CHK_PARSE_FAILED; 6499c965db44STomer Tayar dump_buf += qed_read_param(dump_buf, 6500c965db44STomer Tayar ¶m_name, ¶m_str_val, &num_rules); 65017b6859fbSMintz, Yuval if (strcmp(param_name, "num_rules")) 6502c965db44STomer Tayar return DBG_STATUS_IDLE_CHK_PARSE_FAILED; 6503c965db44STomer Tayar 6504c965db44STomer Tayar if (num_rules) { 6505c965db44STomer Tayar u32 rules_print_size; 6506c965db44STomer Tayar 6507c965db44STomer Tayar /* Print FW output */ 6508c965db44STomer Tayar results_offset += 6509c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6510c965db44STomer Tayar results_offset), 6511c965db44STomer Tayar "FW_IDLE_CHECK:\n"); 6512c965db44STomer Tayar rules_print_size = 6513da090917STomer Tayar qed_parse_idle_chk_dump_rules(dump_buf, 6514da090917STomer Tayar dump_buf_end, 6515da090917STomer Tayar num_rules, 6516c965db44STomer Tayar true, 6517c965db44STomer Tayar results_buf ? 6518c965db44STomer Tayar results_buf + 6519da090917STomer Tayar results_offset : 6520da090917STomer Tayar NULL, 6521da090917STomer Tayar num_errors, 6522da090917STomer Tayar num_warnings); 6523c965db44STomer Tayar results_offset += rules_print_size; 65247b6859fbSMintz, Yuval if (!rules_print_size) 6525c965db44STomer Tayar return DBG_STATUS_IDLE_CHK_PARSE_FAILED; 6526c965db44STomer Tayar 6527c965db44STomer Tayar /* Print LSI output */ 6528c965db44STomer Tayar results_offset += 6529c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6530c965db44STomer Tayar results_offset), 6531c965db44STomer Tayar "\nLSI_IDLE_CHECK:\n"); 6532c965db44STomer Tayar rules_print_size = 6533da090917STomer Tayar qed_parse_idle_chk_dump_rules(dump_buf, 6534da090917STomer Tayar dump_buf_end, 6535da090917STomer Tayar num_rules, 6536c965db44STomer Tayar false, 6537c965db44STomer Tayar results_buf ? 6538c965db44STomer Tayar results_buf + 6539da090917STomer Tayar results_offset : 6540da090917STomer Tayar NULL, 6541da090917STomer Tayar num_errors, 6542da090917STomer Tayar num_warnings); 6543c965db44STomer Tayar results_offset += rules_print_size; 65447b6859fbSMintz, Yuval if (!rules_print_size) 6545c965db44STomer Tayar return DBG_STATUS_IDLE_CHK_PARSE_FAILED; 6546c965db44STomer Tayar } 6547c965db44STomer Tayar 6548c965db44STomer Tayar /* Print errors/warnings count */ 65497b6859fbSMintz, Yuval if (*num_errors) 6550c965db44STomer Tayar results_offset += 6551c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6552c965db44STomer Tayar results_offset), 6553c965db44STomer Tayar "\nIdle Check failed!!! (with %d errors and %d warnings)\n", 6554c965db44STomer Tayar *num_errors, *num_warnings); 65557b6859fbSMintz, Yuval else if (*num_warnings) 6556c965db44STomer Tayar results_offset += 6557c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6558c965db44STomer Tayar results_offset), 65597b6859fbSMintz, Yuval "\nIdle Check completed successfully (with %d warnings)\n", 6560c965db44STomer Tayar *num_warnings); 65617b6859fbSMintz, Yuval else 6562c965db44STomer Tayar results_offset += 6563c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6564c965db44STomer Tayar results_offset), 65657b6859fbSMintz, Yuval "\nIdle Check completed successfully\n"); 6566c965db44STomer Tayar 6567c965db44STomer Tayar /* Add 1 for string NULL termination */ 6568c965db44STomer Tayar *parsed_results_bytes = results_offset + 1; 65697b6859fbSMintz, Yuval 6570c965db44STomer Tayar return DBG_STATUS_OK; 6571c965db44STomer Tayar } 6572c965db44STomer Tayar 6573c965db44STomer Tayar /* Frees the specified MCP Trace meta data */ 6574c965db44STomer Tayar static void qed_mcp_trace_free_meta(struct qed_hwfn *p_hwfn, 6575c965db44STomer Tayar struct mcp_trace_meta *meta) 6576c965db44STomer Tayar { 6577c965db44STomer Tayar u32 i; 6578c965db44STomer Tayar 657950bc60cbSMichal Kalderon s_mcp_trace_meta_valid = false; 658050bc60cbSMichal Kalderon 6581c965db44STomer Tayar /* Release modules */ 6582c965db44STomer Tayar if (meta->modules) { 6583c965db44STomer Tayar for (i = 0; i < meta->modules_num; i++) 6584c965db44STomer Tayar kfree(meta->modules[i]); 6585c965db44STomer Tayar kfree(meta->modules); 6586c965db44STomer Tayar } 6587c965db44STomer Tayar 6588c965db44STomer Tayar /* Release formats */ 6589c965db44STomer Tayar if (meta->formats) { 6590c965db44STomer Tayar for (i = 0; i < meta->formats_num; i++) 6591c965db44STomer Tayar kfree(meta->formats[i].format_str); 6592c965db44STomer Tayar kfree(meta->formats); 6593c965db44STomer Tayar } 6594c965db44STomer Tayar } 6595c965db44STomer Tayar 6596c965db44STomer Tayar /* Allocates and fills MCP Trace meta data based on the specified meta data 6597c965db44STomer Tayar * dump buffer. 6598c965db44STomer Tayar * Returns debug status code. 6599c965db44STomer Tayar */ 6600c965db44STomer Tayar static enum dbg_status qed_mcp_trace_alloc_meta(struct qed_hwfn *p_hwfn, 6601c965db44STomer Tayar const u32 *meta_buf, 6602c965db44STomer Tayar struct mcp_trace_meta *meta) 6603c965db44STomer Tayar { 6604c965db44STomer Tayar u8 *meta_buf_bytes = (u8 *)meta_buf; 6605c965db44STomer Tayar u32 offset = 0, signature, i; 6606c965db44STomer Tayar 660750bc60cbSMichal Kalderon /* Free the previous meta before loading a new one. */ 660850bc60cbSMichal Kalderon if (s_mcp_trace_meta_valid) 660950bc60cbSMichal Kalderon qed_mcp_trace_free_meta(p_hwfn, meta); 661050bc60cbSMichal Kalderon 6611c965db44STomer Tayar memset(meta, 0, sizeof(*meta)); 6612c965db44STomer Tayar 6613c965db44STomer Tayar /* Read first signature */ 6614c965db44STomer Tayar signature = qed_read_dword_from_buf(meta_buf_bytes, &offset); 66157b6859fbSMintz, Yuval if (signature != NVM_MAGIC_VALUE) 6616c965db44STomer Tayar return DBG_STATUS_INVALID_TRACE_SIGNATURE; 6617c965db44STomer Tayar 66187b6859fbSMintz, Yuval /* Read no. of modules and allocate memory for their pointers */ 6619c965db44STomer Tayar meta->modules_num = qed_read_byte_from_buf(meta_buf_bytes, &offset); 66206396bb22SKees Cook meta->modules = kcalloc(meta->modules_num, sizeof(char *), 66216396bb22SKees Cook GFP_KERNEL); 6622c965db44STomer Tayar if (!meta->modules) 6623c965db44STomer Tayar return DBG_STATUS_VIRT_MEM_ALLOC_FAILED; 6624c965db44STomer Tayar 6625c965db44STomer Tayar /* Allocate and read all module strings */ 6626c965db44STomer Tayar for (i = 0; i < meta->modules_num; i++) { 6627c965db44STomer Tayar u8 module_len = qed_read_byte_from_buf(meta_buf_bytes, &offset); 6628c965db44STomer Tayar 6629c965db44STomer Tayar *(meta->modules + i) = kzalloc(module_len, GFP_KERNEL); 6630c965db44STomer Tayar if (!(*(meta->modules + i))) { 6631c965db44STomer Tayar /* Update number of modules to be released */ 6632c965db44STomer Tayar meta->modules_num = i ? i - 1 : 0; 6633c965db44STomer Tayar return DBG_STATUS_VIRT_MEM_ALLOC_FAILED; 6634c965db44STomer Tayar } 6635c965db44STomer Tayar 6636c965db44STomer Tayar qed_read_str_from_buf(meta_buf_bytes, &offset, module_len, 6637c965db44STomer Tayar *(meta->modules + i)); 6638c965db44STomer Tayar if (module_len > MCP_TRACE_MAX_MODULE_LEN) 6639c965db44STomer Tayar (*(meta->modules + i))[MCP_TRACE_MAX_MODULE_LEN] = '\0'; 6640c965db44STomer Tayar } 6641c965db44STomer Tayar 6642c965db44STomer Tayar /* Read second signature */ 6643c965db44STomer Tayar signature = qed_read_dword_from_buf(meta_buf_bytes, &offset); 66447b6859fbSMintz, Yuval if (signature != NVM_MAGIC_VALUE) 6645c965db44STomer Tayar return DBG_STATUS_INVALID_TRACE_SIGNATURE; 6646c965db44STomer Tayar 6647c965db44STomer Tayar /* Read number of formats and allocate memory for all formats */ 6648c965db44STomer Tayar meta->formats_num = qed_read_dword_from_buf(meta_buf_bytes, &offset); 66496396bb22SKees Cook meta->formats = kcalloc(meta->formats_num, 6650c965db44STomer Tayar sizeof(struct mcp_trace_format), 6651c965db44STomer Tayar GFP_KERNEL); 6652c965db44STomer Tayar if (!meta->formats) 6653c965db44STomer Tayar return DBG_STATUS_VIRT_MEM_ALLOC_FAILED; 6654c965db44STomer Tayar 6655c965db44STomer Tayar /* Allocate and read all strings */ 6656c965db44STomer Tayar for (i = 0; i < meta->formats_num; i++) { 6657c965db44STomer Tayar struct mcp_trace_format *format_ptr = &meta->formats[i]; 6658c965db44STomer Tayar u8 format_len; 6659c965db44STomer Tayar 6660c965db44STomer Tayar format_ptr->data = qed_read_dword_from_buf(meta_buf_bytes, 6661c965db44STomer Tayar &offset); 6662c965db44STomer Tayar format_len = 6663c965db44STomer Tayar (format_ptr->data & 6664c965db44STomer Tayar MCP_TRACE_FORMAT_LEN_MASK) >> MCP_TRACE_FORMAT_LEN_SHIFT; 6665c965db44STomer Tayar format_ptr->format_str = kzalloc(format_len, GFP_KERNEL); 6666c965db44STomer Tayar if (!format_ptr->format_str) { 6667c965db44STomer Tayar /* Update number of modules to be released */ 6668c965db44STomer Tayar meta->formats_num = i ? i - 1 : 0; 6669c965db44STomer Tayar return DBG_STATUS_VIRT_MEM_ALLOC_FAILED; 6670c965db44STomer Tayar } 6671c965db44STomer Tayar 6672c965db44STomer Tayar qed_read_str_from_buf(meta_buf_bytes, 6673c965db44STomer Tayar &offset, 6674c965db44STomer Tayar format_len, format_ptr->format_str); 6675c965db44STomer Tayar } 6676c965db44STomer Tayar 667750bc60cbSMichal Kalderon s_mcp_trace_meta_valid = true; 6678c965db44STomer Tayar return DBG_STATUS_OK; 6679c965db44STomer Tayar } 6680c965db44STomer Tayar 668150bc60cbSMichal Kalderon /* Parses an MCP trace buffer. If result_buf is not NULL, the MCP Trace results 668250bc60cbSMichal Kalderon * are printed to it. The parsing status is returned. 668350bc60cbSMichal Kalderon * Arguments: 668450bc60cbSMichal Kalderon * trace_buf - MCP trace cyclic buffer 668550bc60cbSMichal Kalderon * trace_buf_size - MCP trace cyclic buffer size in bytes 668650bc60cbSMichal Kalderon * data_offset - offset in bytes of the data to parse in the MCP trace cyclic 668750bc60cbSMichal Kalderon * buffer. 668850bc60cbSMichal Kalderon * data_size - size in bytes of data to parse. 668950bc60cbSMichal Kalderon * parsed_buf - destination buffer for parsed data. 669050bc60cbSMichal Kalderon * parsed_bytes - size of parsed data in bytes. 669150bc60cbSMichal Kalderon */ 669250bc60cbSMichal Kalderon static enum dbg_status qed_parse_mcp_trace_buf(u8 *trace_buf, 669350bc60cbSMichal Kalderon u32 trace_buf_size, 669450bc60cbSMichal Kalderon u32 data_offset, 669550bc60cbSMichal Kalderon u32 data_size, 669650bc60cbSMichal Kalderon char *parsed_buf, 669750bc60cbSMichal Kalderon u32 *parsed_bytes) 669850bc60cbSMichal Kalderon { 669950bc60cbSMichal Kalderon u32 param_mask, param_shift; 670050bc60cbSMichal Kalderon enum dbg_status status; 670150bc60cbSMichal Kalderon 670250bc60cbSMichal Kalderon *parsed_bytes = 0; 670350bc60cbSMichal Kalderon 670450bc60cbSMichal Kalderon if (!s_mcp_trace_meta_valid) 670550bc60cbSMichal Kalderon return DBG_STATUS_MCP_TRACE_BAD_DATA; 670650bc60cbSMichal Kalderon 670750bc60cbSMichal Kalderon status = DBG_STATUS_OK; 670850bc60cbSMichal Kalderon 670950bc60cbSMichal Kalderon while (data_size) { 671050bc60cbSMichal Kalderon struct mcp_trace_format *format_ptr; 671150bc60cbSMichal Kalderon u8 format_level, format_module; 671250bc60cbSMichal Kalderon u32 params[3] = { 0, 0, 0 }; 671350bc60cbSMichal Kalderon u32 header, format_idx, i; 671450bc60cbSMichal Kalderon 671550bc60cbSMichal Kalderon if (data_size < MFW_TRACE_ENTRY_SIZE) 671650bc60cbSMichal Kalderon return DBG_STATUS_MCP_TRACE_BAD_DATA; 671750bc60cbSMichal Kalderon 671850bc60cbSMichal Kalderon header = qed_read_from_cyclic_buf(trace_buf, 671950bc60cbSMichal Kalderon &data_offset, 672050bc60cbSMichal Kalderon trace_buf_size, 672150bc60cbSMichal Kalderon MFW_TRACE_ENTRY_SIZE); 672250bc60cbSMichal Kalderon data_size -= MFW_TRACE_ENTRY_SIZE; 672350bc60cbSMichal Kalderon format_idx = header & MFW_TRACE_EVENTID_MASK; 672450bc60cbSMichal Kalderon 672550bc60cbSMichal Kalderon /* Skip message if its index doesn't exist in the meta data */ 672650bc60cbSMichal Kalderon if (format_idx > s_mcp_trace_meta.formats_num) { 672750bc60cbSMichal Kalderon u8 format_size = 672850bc60cbSMichal Kalderon (u8)((header & MFW_TRACE_PRM_SIZE_MASK) >> 672950bc60cbSMichal Kalderon MFW_TRACE_PRM_SIZE_SHIFT); 673050bc60cbSMichal Kalderon 673150bc60cbSMichal Kalderon if (data_size < format_size) 673250bc60cbSMichal Kalderon return DBG_STATUS_MCP_TRACE_BAD_DATA; 673350bc60cbSMichal Kalderon 673450bc60cbSMichal Kalderon data_offset = qed_cyclic_add(data_offset, 673550bc60cbSMichal Kalderon format_size, 673650bc60cbSMichal Kalderon trace_buf_size); 673750bc60cbSMichal Kalderon data_size -= format_size; 673850bc60cbSMichal Kalderon continue; 673950bc60cbSMichal Kalderon } 674050bc60cbSMichal Kalderon 674150bc60cbSMichal Kalderon format_ptr = &s_mcp_trace_meta.formats[format_idx]; 674250bc60cbSMichal Kalderon 674350bc60cbSMichal Kalderon for (i = 0, 674450bc60cbSMichal Kalderon param_mask = MCP_TRACE_FORMAT_P1_SIZE_MASK, 674550bc60cbSMichal Kalderon param_shift = MCP_TRACE_FORMAT_P1_SIZE_SHIFT; 674650bc60cbSMichal Kalderon i < MCP_TRACE_FORMAT_MAX_PARAMS; 674750bc60cbSMichal Kalderon i++, 674850bc60cbSMichal Kalderon param_mask <<= MCP_TRACE_FORMAT_PARAM_WIDTH, 674950bc60cbSMichal Kalderon param_shift += MCP_TRACE_FORMAT_PARAM_WIDTH) { 675050bc60cbSMichal Kalderon /* Extract param size (0..3) */ 675150bc60cbSMichal Kalderon u8 param_size = (u8)((format_ptr->data & param_mask) >> 675250bc60cbSMichal Kalderon param_shift); 675350bc60cbSMichal Kalderon 675450bc60cbSMichal Kalderon /* If the param size is zero, there are no other 675550bc60cbSMichal Kalderon * parameters. 675650bc60cbSMichal Kalderon */ 675750bc60cbSMichal Kalderon if (!param_size) 675850bc60cbSMichal Kalderon break; 675950bc60cbSMichal Kalderon 676050bc60cbSMichal Kalderon /* Size is encoded using 2 bits, where 3 is used to 676150bc60cbSMichal Kalderon * encode 4. 676250bc60cbSMichal Kalderon */ 676350bc60cbSMichal Kalderon if (param_size == 3) 676450bc60cbSMichal Kalderon param_size = 4; 676550bc60cbSMichal Kalderon 676650bc60cbSMichal Kalderon if (data_size < param_size) 676750bc60cbSMichal Kalderon return DBG_STATUS_MCP_TRACE_BAD_DATA; 676850bc60cbSMichal Kalderon 676950bc60cbSMichal Kalderon params[i] = qed_read_from_cyclic_buf(trace_buf, 677050bc60cbSMichal Kalderon &data_offset, 677150bc60cbSMichal Kalderon trace_buf_size, 677250bc60cbSMichal Kalderon param_size); 677350bc60cbSMichal Kalderon data_size -= param_size; 677450bc60cbSMichal Kalderon } 677550bc60cbSMichal Kalderon 677650bc60cbSMichal Kalderon format_level = (u8)((format_ptr->data & 677750bc60cbSMichal Kalderon MCP_TRACE_FORMAT_LEVEL_MASK) >> 677850bc60cbSMichal Kalderon MCP_TRACE_FORMAT_LEVEL_SHIFT); 677950bc60cbSMichal Kalderon format_module = (u8)((format_ptr->data & 678050bc60cbSMichal Kalderon MCP_TRACE_FORMAT_MODULE_MASK) >> 678150bc60cbSMichal Kalderon MCP_TRACE_FORMAT_MODULE_SHIFT); 678250bc60cbSMichal Kalderon if (format_level >= ARRAY_SIZE(s_mcp_trace_level_str)) 678350bc60cbSMichal Kalderon return DBG_STATUS_MCP_TRACE_BAD_DATA; 678450bc60cbSMichal Kalderon 678550bc60cbSMichal Kalderon /* Print current message to results buffer */ 678650bc60cbSMichal Kalderon *parsed_bytes += 678750bc60cbSMichal Kalderon sprintf(qed_get_buf_ptr(parsed_buf, *parsed_bytes), 678850bc60cbSMichal Kalderon "%s %-8s: ", 678950bc60cbSMichal Kalderon s_mcp_trace_level_str[format_level], 679050bc60cbSMichal Kalderon s_mcp_trace_meta.modules[format_module]); 679150bc60cbSMichal Kalderon *parsed_bytes += 679250bc60cbSMichal Kalderon sprintf(qed_get_buf_ptr(parsed_buf, *parsed_bytes), 679350bc60cbSMichal Kalderon format_ptr->format_str, 679450bc60cbSMichal Kalderon params[0], params[1], params[2]); 679550bc60cbSMichal Kalderon } 679650bc60cbSMichal Kalderon 679750bc60cbSMichal Kalderon /* Add string NULL terminator */ 679850bc60cbSMichal Kalderon (*parsed_bytes)++; 679950bc60cbSMichal Kalderon 680050bc60cbSMichal Kalderon return status; 680150bc60cbSMichal Kalderon } 680250bc60cbSMichal Kalderon 6803c965db44STomer Tayar /* Parses an MCP Trace dump buffer. 6804c965db44STomer Tayar * If result_buf is not NULL, the MCP Trace results are printed to it. 6805c965db44STomer Tayar * In any case, the required results buffer size is assigned to 680650bc60cbSMichal Kalderon * parsed_bytes. 6807c965db44STomer Tayar * The parsing status is returned. 6808c965db44STomer Tayar */ 6809c965db44STomer Tayar static enum dbg_status qed_parse_mcp_trace_dump(struct qed_hwfn *p_hwfn, 6810c965db44STomer Tayar u32 *dump_buf, 681150bc60cbSMichal Kalderon char *parsed_buf, 681250bc60cbSMichal Kalderon u32 *parsed_bytes) 6813c965db44STomer Tayar { 6814c965db44STomer Tayar const char *section_name, *param_name, *param_str_val; 681550bc60cbSMichal Kalderon u32 data_size, trace_data_dwords, trace_meta_dwords; 681650bc60cbSMichal Kalderon u32 offset, results_offset, parsed_buf_bytes; 681750bc60cbSMichal Kalderon u32 param_num_val, num_section_params; 6818c965db44STomer Tayar struct mcp_trace *trace; 6819c965db44STomer Tayar enum dbg_status status; 6820c965db44STomer Tayar const u32 *meta_buf; 6821c965db44STomer Tayar u8 *trace_buf; 6822c965db44STomer Tayar 682350bc60cbSMichal Kalderon *parsed_bytes = 0; 6824c965db44STomer Tayar 6825c965db44STomer Tayar /* Read global_params section */ 6826c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 6827c965db44STomer Tayar §ion_name, &num_section_params); 6828c965db44STomer Tayar if (strcmp(section_name, "global_params")) 6829c965db44STomer Tayar return DBG_STATUS_MCP_TRACE_BAD_DATA; 6830c965db44STomer Tayar 6831c965db44STomer Tayar /* Print global params */ 6832c965db44STomer Tayar dump_buf += qed_print_section_params(dump_buf, 6833c965db44STomer Tayar num_section_params, 683450bc60cbSMichal Kalderon parsed_buf, &results_offset); 6835c965db44STomer Tayar 6836c965db44STomer Tayar /* Read trace_data section */ 6837c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 6838c965db44STomer Tayar §ion_name, &num_section_params); 6839c965db44STomer Tayar if (strcmp(section_name, "mcp_trace_data") || num_section_params != 1) 6840c965db44STomer Tayar return DBG_STATUS_MCP_TRACE_BAD_DATA; 6841c965db44STomer Tayar dump_buf += qed_read_param(dump_buf, 6842c965db44STomer Tayar ¶m_name, ¶m_str_val, ¶m_num_val); 6843c965db44STomer Tayar if (strcmp(param_name, "size")) 6844c965db44STomer Tayar return DBG_STATUS_MCP_TRACE_BAD_DATA; 6845c965db44STomer Tayar trace_data_dwords = param_num_val; 6846c965db44STomer Tayar 6847c965db44STomer Tayar /* Prepare trace info */ 6848c965db44STomer Tayar trace = (struct mcp_trace *)dump_buf; 68497b6859fbSMintz, Yuval trace_buf = (u8 *)dump_buf + sizeof(*trace); 6850c965db44STomer Tayar offset = trace->trace_oldest; 685150bc60cbSMichal Kalderon data_size = qed_cyclic_sub(trace->trace_prod, offset, trace->size); 6852c965db44STomer Tayar dump_buf += trace_data_dwords; 6853c965db44STomer Tayar 6854c965db44STomer Tayar /* Read meta_data section */ 6855c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 6856c965db44STomer Tayar §ion_name, &num_section_params); 6857c965db44STomer Tayar if (strcmp(section_name, "mcp_trace_meta")) 6858c965db44STomer Tayar return DBG_STATUS_MCP_TRACE_BAD_DATA; 6859c965db44STomer Tayar dump_buf += qed_read_param(dump_buf, 6860c965db44STomer Tayar ¶m_name, ¶m_str_val, ¶m_num_val); 68617b6859fbSMintz, Yuval if (strcmp(param_name, "size")) 6862c965db44STomer Tayar return DBG_STATUS_MCP_TRACE_BAD_DATA; 6863c965db44STomer Tayar trace_meta_dwords = param_num_val; 6864c965db44STomer Tayar 6865c965db44STomer Tayar /* Choose meta data buffer */ 6866c965db44STomer Tayar if (!trace_meta_dwords) { 6867c965db44STomer Tayar /* Dump doesn't include meta data */ 686850bc60cbSMichal Kalderon if (!s_mcp_trace_meta_arr.ptr) 6869c965db44STomer Tayar return DBG_STATUS_MCP_TRACE_NO_META; 687050bc60cbSMichal Kalderon meta_buf = s_mcp_trace_meta_arr.ptr; 6871c965db44STomer Tayar } else { 6872c965db44STomer Tayar /* Dump includes meta data */ 6873c965db44STomer Tayar meta_buf = dump_buf; 6874c965db44STomer Tayar } 6875c965db44STomer Tayar 6876c965db44STomer Tayar /* Allocate meta data memory */ 687750bc60cbSMichal Kalderon status = qed_mcp_trace_alloc_meta(p_hwfn, meta_buf, &s_mcp_trace_meta); 6878c965db44STomer Tayar if (status != DBG_STATUS_OK) 6879c965db44STomer Tayar return status; 688050bc60cbSMichal Kalderon 688150bc60cbSMichal Kalderon status = qed_parse_mcp_trace_buf(trace_buf, 688250bc60cbSMichal Kalderon trace->size, 688350bc60cbSMichal Kalderon offset, 688450bc60cbSMichal Kalderon data_size, 688550bc60cbSMichal Kalderon parsed_buf ? 688650bc60cbSMichal Kalderon parsed_buf + results_offset : 688750bc60cbSMichal Kalderon NULL, 688850bc60cbSMichal Kalderon &parsed_buf_bytes); 688950bc60cbSMichal Kalderon if (status != DBG_STATUS_OK) 689050bc60cbSMichal Kalderon return status; 689150bc60cbSMichal Kalderon 689250bc60cbSMichal Kalderon *parsed_bytes = results_offset + parsed_buf_bytes; 689350bc60cbSMichal Kalderon 689450bc60cbSMichal Kalderon return DBG_STATUS_OK; 6895c965db44STomer Tayar } 6896c965db44STomer Tayar 6897c965db44STomer Tayar /* Parses a Reg FIFO dump buffer. 6898c965db44STomer Tayar * If result_buf is not NULL, the Reg FIFO results are printed to it. 6899c965db44STomer Tayar * In any case, the required results buffer size is assigned to 6900c965db44STomer Tayar * parsed_results_bytes. 6901c965db44STomer Tayar * The parsing status is returned. 6902c965db44STomer Tayar */ 6903da090917STomer Tayar static enum dbg_status qed_parse_reg_fifo_dump(u32 *dump_buf, 6904c965db44STomer Tayar char *results_buf, 6905c965db44STomer Tayar u32 *parsed_results_bytes) 6906c965db44STomer Tayar { 6907c965db44STomer Tayar const char *section_name, *param_name, *param_str_val; 69087b6859fbSMintz, Yuval u32 param_num_val, num_section_params, num_elements; 6909c965db44STomer Tayar struct reg_fifo_element *elements; 6910c965db44STomer Tayar u8 i, j, err_val, vf_val; 69117b6859fbSMintz, Yuval u32 results_offset = 0; 6912c965db44STomer Tayar char vf_str[4]; 6913c965db44STomer Tayar 6914c965db44STomer Tayar /* Read global_params section */ 6915c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 6916c965db44STomer Tayar §ion_name, &num_section_params); 6917c965db44STomer Tayar if (strcmp(section_name, "global_params")) 6918c965db44STomer Tayar return DBG_STATUS_REG_FIFO_BAD_DATA; 6919c965db44STomer Tayar 6920c965db44STomer Tayar /* Print global params */ 6921c965db44STomer Tayar dump_buf += qed_print_section_params(dump_buf, 6922c965db44STomer Tayar num_section_params, 6923c965db44STomer Tayar results_buf, &results_offset); 6924c965db44STomer Tayar 6925c965db44STomer Tayar /* Read reg_fifo_data section */ 6926c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 6927c965db44STomer Tayar §ion_name, &num_section_params); 6928c965db44STomer Tayar if (strcmp(section_name, "reg_fifo_data")) 6929c965db44STomer Tayar return DBG_STATUS_REG_FIFO_BAD_DATA; 6930c965db44STomer Tayar dump_buf += qed_read_param(dump_buf, 6931c965db44STomer Tayar ¶m_name, ¶m_str_val, ¶m_num_val); 6932c965db44STomer Tayar if (strcmp(param_name, "size")) 6933c965db44STomer Tayar return DBG_STATUS_REG_FIFO_BAD_DATA; 6934c965db44STomer Tayar if (param_num_val % REG_FIFO_ELEMENT_DWORDS) 6935c965db44STomer Tayar return DBG_STATUS_REG_FIFO_BAD_DATA; 6936c965db44STomer Tayar num_elements = param_num_val / REG_FIFO_ELEMENT_DWORDS; 6937c965db44STomer Tayar elements = (struct reg_fifo_element *)dump_buf; 6938c965db44STomer Tayar 6939c965db44STomer Tayar /* Decode elements */ 6940c965db44STomer Tayar for (i = 0; i < num_elements; i++) { 6941c965db44STomer Tayar bool err_printed = false; 6942c965db44STomer Tayar 6943c965db44STomer Tayar /* Discover if element belongs to a VF or a PF */ 6944c965db44STomer Tayar vf_val = GET_FIELD(elements[i].data, REG_FIFO_ELEMENT_VF); 6945c965db44STomer Tayar if (vf_val == REG_FIFO_ELEMENT_IS_PF_VF_VAL) 6946c965db44STomer Tayar sprintf(vf_str, "%s", "N/A"); 6947c965db44STomer Tayar else 6948c965db44STomer Tayar sprintf(vf_str, "%d", vf_val); 6949c965db44STomer Tayar 6950c965db44STomer Tayar /* Add parsed element to parsed buffer */ 6951c965db44STomer Tayar results_offset += 6952c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6953c965db44STomer Tayar results_offset), 6954be086e7cSMintz, Yuval "raw: 0x%016llx, address: 0x%07x, access: %-5s, pf: %2d, vf: %s, port: %d, privilege: %-3s, protection: %-12s, master: %-4s, errors: ", 6955c965db44STomer Tayar elements[i].data, 6956be086e7cSMintz, Yuval (u32)GET_FIELD(elements[i].data, 6957c965db44STomer Tayar REG_FIFO_ELEMENT_ADDRESS) * 6958c965db44STomer Tayar REG_FIFO_ELEMENT_ADDR_FACTOR, 6959c965db44STomer Tayar s_access_strs[GET_FIELD(elements[i].data, 6960c965db44STomer Tayar REG_FIFO_ELEMENT_ACCESS)], 6961be086e7cSMintz, Yuval (u32)GET_FIELD(elements[i].data, 69627b6859fbSMintz, Yuval REG_FIFO_ELEMENT_PF), 69637b6859fbSMintz, Yuval vf_str, 6964be086e7cSMintz, Yuval (u32)GET_FIELD(elements[i].data, 6965c965db44STomer Tayar REG_FIFO_ELEMENT_PORT), 69667b6859fbSMintz, Yuval s_privilege_strs[GET_FIELD(elements[i].data, 6967c965db44STomer Tayar REG_FIFO_ELEMENT_PRIVILEGE)], 6968c965db44STomer Tayar s_protection_strs[GET_FIELD(elements[i].data, 6969c965db44STomer Tayar REG_FIFO_ELEMENT_PROTECTION)], 6970c965db44STomer Tayar s_master_strs[GET_FIELD(elements[i].data, 6971c965db44STomer Tayar REG_FIFO_ELEMENT_MASTER)]); 6972c965db44STomer Tayar 6973c965db44STomer Tayar /* Print errors */ 6974c965db44STomer Tayar for (j = 0, 6975c965db44STomer Tayar err_val = GET_FIELD(elements[i].data, 6976c965db44STomer Tayar REG_FIFO_ELEMENT_ERROR); 6977c965db44STomer Tayar j < ARRAY_SIZE(s_reg_fifo_error_strs); 6978c965db44STomer Tayar j++, err_val >>= 1) { 69797b6859fbSMintz, Yuval if (err_val & 0x1) { 6980c965db44STomer Tayar if (err_printed) 6981c965db44STomer Tayar results_offset += 69827b6859fbSMintz, Yuval sprintf(qed_get_buf_ptr 69837b6859fbSMintz, Yuval (results_buf, 69847b6859fbSMintz, Yuval results_offset), ", "); 6985c965db44STomer Tayar results_offset += 69867b6859fbSMintz, Yuval sprintf(qed_get_buf_ptr 69877b6859fbSMintz, Yuval (results_buf, results_offset), "%s", 6988c965db44STomer Tayar s_reg_fifo_error_strs[j]); 6989c965db44STomer Tayar err_printed = true; 6990c965db44STomer Tayar } 69917b6859fbSMintz, Yuval } 6992c965db44STomer Tayar 6993c965db44STomer Tayar results_offset += 6994c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, results_offset), "\n"); 6995c965db44STomer Tayar } 6996c965db44STomer Tayar 6997c965db44STomer Tayar results_offset += sprintf(qed_get_buf_ptr(results_buf, 6998c965db44STomer Tayar results_offset), 6999c965db44STomer Tayar "fifo contained %d elements", num_elements); 7000c965db44STomer Tayar 7001c965db44STomer Tayar /* Add 1 for string NULL termination */ 7002c965db44STomer Tayar *parsed_results_bytes = results_offset + 1; 70037b6859fbSMintz, Yuval 7004c965db44STomer Tayar return DBG_STATUS_OK; 7005c965db44STomer Tayar } 7006c965db44STomer Tayar 70077b6859fbSMintz, Yuval static enum dbg_status qed_parse_igu_fifo_element(struct igu_fifo_element 70087b6859fbSMintz, Yuval *element, char 70097b6859fbSMintz, Yuval *results_buf, 7010da090917STomer Tayar u32 *results_offset) 7011c965db44STomer Tayar { 70127b6859fbSMintz, Yuval const struct igu_fifo_addr_data *found_addr = NULL; 70137b6859fbSMintz, Yuval u8 source, err_type, i, is_cleanup; 70147b6859fbSMintz, Yuval char parsed_addr_data[32]; 70157b6859fbSMintz, Yuval char parsed_wr_data[256]; 70167b6859fbSMintz, Yuval u32 wr_data, prod_cons; 70177b6859fbSMintz, Yuval bool is_wr_cmd, is_pf; 70187b6859fbSMintz, Yuval u16 cmd_addr; 70197b6859fbSMintz, Yuval u64 dword12; 70207b6859fbSMintz, Yuval 70217b6859fbSMintz, Yuval /* Dword12 (dword index 1 and 2) contains bits 32..95 of the 70227b6859fbSMintz, Yuval * FIFO element. 70237b6859fbSMintz, Yuval */ 70247b6859fbSMintz, Yuval dword12 = ((u64)element->dword2 << 32) | element->dword1; 70257b6859fbSMintz, Yuval is_wr_cmd = GET_FIELD(dword12, IGU_FIFO_ELEMENT_DWORD12_IS_WR_CMD); 70267b6859fbSMintz, Yuval is_pf = GET_FIELD(element->dword0, IGU_FIFO_ELEMENT_DWORD0_IS_PF); 70277b6859fbSMintz, Yuval cmd_addr = GET_FIELD(element->dword0, IGU_FIFO_ELEMENT_DWORD0_CMD_ADDR); 70287b6859fbSMintz, Yuval source = GET_FIELD(element->dword0, IGU_FIFO_ELEMENT_DWORD0_SOURCE); 70297b6859fbSMintz, Yuval err_type = GET_FIELD(element->dword0, IGU_FIFO_ELEMENT_DWORD0_ERR_TYPE); 70307b6859fbSMintz, Yuval 70317b6859fbSMintz, Yuval if (source >= ARRAY_SIZE(s_igu_fifo_source_strs)) 70327b6859fbSMintz, Yuval return DBG_STATUS_IGU_FIFO_BAD_DATA; 70337b6859fbSMintz, Yuval if (err_type >= ARRAY_SIZE(s_igu_fifo_error_strs)) 70347b6859fbSMintz, Yuval return DBG_STATUS_IGU_FIFO_BAD_DATA; 70357b6859fbSMintz, Yuval 70367b6859fbSMintz, Yuval /* Find address data */ 70377b6859fbSMintz, Yuval for (i = 0; i < ARRAY_SIZE(s_igu_fifo_addr_data) && !found_addr; i++) { 70387b6859fbSMintz, Yuval const struct igu_fifo_addr_data *curr_addr = 70397b6859fbSMintz, Yuval &s_igu_fifo_addr_data[i]; 70407b6859fbSMintz, Yuval 70417b6859fbSMintz, Yuval if (cmd_addr >= curr_addr->start_addr && cmd_addr <= 70427b6859fbSMintz, Yuval curr_addr->end_addr) 70437b6859fbSMintz, Yuval found_addr = curr_addr; 7044c965db44STomer Tayar } 7045c965db44STomer Tayar 70467b6859fbSMintz, Yuval if (!found_addr) 70477b6859fbSMintz, Yuval return DBG_STATUS_IGU_FIFO_BAD_DATA; 7048c965db44STomer Tayar 70497b6859fbSMintz, Yuval /* Prepare parsed address data */ 70507b6859fbSMintz, Yuval switch (found_addr->type) { 70517b6859fbSMintz, Yuval case IGU_ADDR_TYPE_MSIX_MEM: 70527b6859fbSMintz, Yuval sprintf(parsed_addr_data, " vector_num = 0x%x", cmd_addr / 2); 70537b6859fbSMintz, Yuval break; 70547b6859fbSMintz, Yuval case IGU_ADDR_TYPE_WRITE_INT_ACK: 70557b6859fbSMintz, Yuval case IGU_ADDR_TYPE_WRITE_PROD_UPDATE: 70567b6859fbSMintz, Yuval sprintf(parsed_addr_data, 70577b6859fbSMintz, Yuval " SB = 0x%x", cmd_addr - found_addr->start_addr); 70587b6859fbSMintz, Yuval break; 70597b6859fbSMintz, Yuval default: 70607b6859fbSMintz, Yuval parsed_addr_data[0] = '\0'; 70617b6859fbSMintz, Yuval } 70627b6859fbSMintz, Yuval 70637b6859fbSMintz, Yuval if (!is_wr_cmd) { 70647b6859fbSMintz, Yuval parsed_wr_data[0] = '\0'; 70657b6859fbSMintz, Yuval goto out; 70667b6859fbSMintz, Yuval } 70677b6859fbSMintz, Yuval 70687b6859fbSMintz, Yuval /* Prepare parsed write data */ 70697b6859fbSMintz, Yuval wr_data = GET_FIELD(dword12, IGU_FIFO_ELEMENT_DWORD12_WR_DATA); 70707b6859fbSMintz, Yuval prod_cons = GET_FIELD(wr_data, IGU_FIFO_WR_DATA_PROD_CONS); 70717b6859fbSMintz, Yuval is_cleanup = GET_FIELD(wr_data, IGU_FIFO_WR_DATA_CMD_TYPE); 70727b6859fbSMintz, Yuval 70737b6859fbSMintz, Yuval if (source == IGU_SRC_ATTN) { 70747b6859fbSMintz, Yuval sprintf(parsed_wr_data, "prod: 0x%x, ", prod_cons); 70757b6859fbSMintz, Yuval } else { 70767b6859fbSMintz, Yuval if (is_cleanup) { 70777b6859fbSMintz, Yuval u8 cleanup_val, cleanup_type; 70787b6859fbSMintz, Yuval 70797b6859fbSMintz, Yuval cleanup_val = 70807b6859fbSMintz, Yuval GET_FIELD(wr_data, 70817b6859fbSMintz, Yuval IGU_FIFO_CLEANUP_WR_DATA_CLEANUP_VAL); 70827b6859fbSMintz, Yuval cleanup_type = 70837b6859fbSMintz, Yuval GET_FIELD(wr_data, 70847b6859fbSMintz, Yuval IGU_FIFO_CLEANUP_WR_DATA_CLEANUP_TYPE); 70857b6859fbSMintz, Yuval 70867b6859fbSMintz, Yuval sprintf(parsed_wr_data, 70877b6859fbSMintz, Yuval "cmd_type: cleanup, cleanup_val: %s, cleanup_type : %d, ", 70887b6859fbSMintz, Yuval cleanup_val ? "set" : "clear", 70897b6859fbSMintz, Yuval cleanup_type); 70907b6859fbSMintz, Yuval } else { 70917b6859fbSMintz, Yuval u8 update_flag, en_dis_int_for_sb, segment; 70927b6859fbSMintz, Yuval u8 timer_mask; 70937b6859fbSMintz, Yuval 70947b6859fbSMintz, Yuval update_flag = GET_FIELD(wr_data, 70957b6859fbSMintz, Yuval IGU_FIFO_WR_DATA_UPDATE_FLAG); 70967b6859fbSMintz, Yuval en_dis_int_for_sb = 70977b6859fbSMintz, Yuval GET_FIELD(wr_data, 70987b6859fbSMintz, Yuval IGU_FIFO_WR_DATA_EN_DIS_INT_FOR_SB); 70997b6859fbSMintz, Yuval segment = GET_FIELD(wr_data, 71007b6859fbSMintz, Yuval IGU_FIFO_WR_DATA_SEGMENT); 71017b6859fbSMintz, Yuval timer_mask = GET_FIELD(wr_data, 71027b6859fbSMintz, Yuval IGU_FIFO_WR_DATA_TIMER_MASK); 71037b6859fbSMintz, Yuval 71047b6859fbSMintz, Yuval sprintf(parsed_wr_data, 71057b6859fbSMintz, Yuval "cmd_type: prod/cons update, prod/cons: 0x%x, update_flag: %s, en_dis_int_for_sb : %s, segment : %s, timer_mask = %d, ", 71067b6859fbSMintz, Yuval prod_cons, 71077b6859fbSMintz, Yuval update_flag ? "update" : "nop", 7108da090917STomer Tayar en_dis_int_for_sb ? 7109da090917STomer Tayar (en_dis_int_for_sb == 1 ? "disable" : "nop") : 7110da090917STomer Tayar "enable", 71117b6859fbSMintz, Yuval segment ? "attn" : "regular", 71127b6859fbSMintz, Yuval timer_mask); 71137b6859fbSMintz, Yuval } 71147b6859fbSMintz, Yuval } 71157b6859fbSMintz, Yuval out: 71167b6859fbSMintz, Yuval /* Add parsed element to parsed buffer */ 71177b6859fbSMintz, Yuval *results_offset += sprintf(qed_get_buf_ptr(results_buf, 71187b6859fbSMintz, Yuval *results_offset), 71197b6859fbSMintz, Yuval "raw: 0x%01x%08x%08x, %s: %d, source : %s, type : %s, cmd_addr : 0x%x(%s%s), %serror: %s\n", 71207b6859fbSMintz, Yuval element->dword2, element->dword1, 71217b6859fbSMintz, Yuval element->dword0, 71227b6859fbSMintz, Yuval is_pf ? "pf" : "vf", 71237b6859fbSMintz, Yuval GET_FIELD(element->dword0, 71247b6859fbSMintz, Yuval IGU_FIFO_ELEMENT_DWORD0_FID), 71257b6859fbSMintz, Yuval s_igu_fifo_source_strs[source], 71267b6859fbSMintz, Yuval is_wr_cmd ? "wr" : "rd", 71277b6859fbSMintz, Yuval cmd_addr, 71287b6859fbSMintz, Yuval (!is_pf && found_addr->vf_desc) 71297b6859fbSMintz, Yuval ? found_addr->vf_desc 71307b6859fbSMintz, Yuval : found_addr->desc, 71317b6859fbSMintz, Yuval parsed_addr_data, 71327b6859fbSMintz, Yuval parsed_wr_data, 71337b6859fbSMintz, Yuval s_igu_fifo_error_strs[err_type]); 71347b6859fbSMintz, Yuval 71357b6859fbSMintz, Yuval return DBG_STATUS_OK; 7136c965db44STomer Tayar } 7137c965db44STomer Tayar 7138c965db44STomer Tayar /* Parses an IGU FIFO dump buffer. 7139c965db44STomer Tayar * If result_buf is not NULL, the IGU FIFO results are printed to it. 7140c965db44STomer Tayar * In any case, the required results buffer size is assigned to 7141c965db44STomer Tayar * parsed_results_bytes. 7142c965db44STomer Tayar * The parsing status is returned. 7143c965db44STomer Tayar */ 7144da090917STomer Tayar static enum dbg_status qed_parse_igu_fifo_dump(u32 *dump_buf, 7145c965db44STomer Tayar char *results_buf, 7146c965db44STomer Tayar u32 *parsed_results_bytes) 7147c965db44STomer Tayar { 7148c965db44STomer Tayar const char *section_name, *param_name, *param_str_val; 71497b6859fbSMintz, Yuval u32 param_num_val, num_section_params, num_elements; 7150c965db44STomer Tayar struct igu_fifo_element *elements; 71517b6859fbSMintz, Yuval enum dbg_status status; 71527b6859fbSMintz, Yuval u32 results_offset = 0; 71537b6859fbSMintz, Yuval u8 i; 7154c965db44STomer Tayar 7155c965db44STomer Tayar /* Read global_params section */ 7156c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 7157c965db44STomer Tayar §ion_name, &num_section_params); 7158c965db44STomer Tayar if (strcmp(section_name, "global_params")) 7159c965db44STomer Tayar return DBG_STATUS_IGU_FIFO_BAD_DATA; 7160c965db44STomer Tayar 7161c965db44STomer Tayar /* Print global params */ 7162c965db44STomer Tayar dump_buf += qed_print_section_params(dump_buf, 7163c965db44STomer Tayar num_section_params, 7164c965db44STomer Tayar results_buf, &results_offset); 7165c965db44STomer Tayar 7166c965db44STomer Tayar /* Read igu_fifo_data section */ 7167c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 7168c965db44STomer Tayar §ion_name, &num_section_params); 7169c965db44STomer Tayar if (strcmp(section_name, "igu_fifo_data")) 7170c965db44STomer Tayar return DBG_STATUS_IGU_FIFO_BAD_DATA; 7171c965db44STomer Tayar dump_buf += qed_read_param(dump_buf, 7172c965db44STomer Tayar ¶m_name, ¶m_str_val, ¶m_num_val); 7173c965db44STomer Tayar if (strcmp(param_name, "size")) 7174c965db44STomer Tayar return DBG_STATUS_IGU_FIFO_BAD_DATA; 7175c965db44STomer Tayar if (param_num_val % IGU_FIFO_ELEMENT_DWORDS) 7176c965db44STomer Tayar return DBG_STATUS_IGU_FIFO_BAD_DATA; 7177c965db44STomer Tayar num_elements = param_num_val / IGU_FIFO_ELEMENT_DWORDS; 7178c965db44STomer Tayar elements = (struct igu_fifo_element *)dump_buf; 7179c965db44STomer Tayar 7180c965db44STomer Tayar /* Decode elements */ 7181c965db44STomer Tayar for (i = 0; i < num_elements; i++) { 71827b6859fbSMintz, Yuval status = qed_parse_igu_fifo_element(&elements[i], 71837b6859fbSMintz, Yuval results_buf, 7184da090917STomer Tayar &results_offset); 71857b6859fbSMintz, Yuval if (status != DBG_STATUS_OK) 71867b6859fbSMintz, Yuval return status; 7187c965db44STomer Tayar } 7188c965db44STomer Tayar 7189c965db44STomer Tayar results_offset += sprintf(qed_get_buf_ptr(results_buf, 7190c965db44STomer Tayar results_offset), 7191c965db44STomer Tayar "fifo contained %d elements", num_elements); 7192c965db44STomer Tayar 7193c965db44STomer Tayar /* Add 1 for string NULL termination */ 7194c965db44STomer Tayar *parsed_results_bytes = results_offset + 1; 71957b6859fbSMintz, Yuval 7196c965db44STomer Tayar return DBG_STATUS_OK; 7197c965db44STomer Tayar } 7198c965db44STomer Tayar 7199c965db44STomer Tayar static enum dbg_status 7200da090917STomer Tayar qed_parse_protection_override_dump(u32 *dump_buf, 7201c965db44STomer Tayar char *results_buf, 7202c965db44STomer Tayar u32 *parsed_results_bytes) 7203c965db44STomer Tayar { 7204c965db44STomer Tayar const char *section_name, *param_name, *param_str_val; 72057b6859fbSMintz, Yuval u32 param_num_val, num_section_params, num_elements; 7206c965db44STomer Tayar struct protection_override_element *elements; 72077b6859fbSMintz, Yuval u32 results_offset = 0; 7208c965db44STomer Tayar u8 i; 7209c965db44STomer Tayar 7210c965db44STomer Tayar /* Read global_params section */ 7211c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 7212c965db44STomer Tayar §ion_name, &num_section_params); 7213c965db44STomer Tayar if (strcmp(section_name, "global_params")) 7214c965db44STomer Tayar return DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA; 7215c965db44STomer Tayar 7216c965db44STomer Tayar /* Print global params */ 7217c965db44STomer Tayar dump_buf += qed_print_section_params(dump_buf, 7218c965db44STomer Tayar num_section_params, 7219c965db44STomer Tayar results_buf, &results_offset); 7220c965db44STomer Tayar 7221c965db44STomer Tayar /* Read protection_override_data section */ 7222c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 7223c965db44STomer Tayar §ion_name, &num_section_params); 7224c965db44STomer Tayar if (strcmp(section_name, "protection_override_data")) 7225c965db44STomer Tayar return DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA; 7226c965db44STomer Tayar dump_buf += qed_read_param(dump_buf, 7227c965db44STomer Tayar ¶m_name, ¶m_str_val, ¶m_num_val); 7228c965db44STomer Tayar if (strcmp(param_name, "size")) 7229c965db44STomer Tayar return DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA; 72307b6859fbSMintz, Yuval if (param_num_val % PROTECTION_OVERRIDE_ELEMENT_DWORDS) 7231c965db44STomer Tayar return DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA; 7232c965db44STomer Tayar num_elements = param_num_val / PROTECTION_OVERRIDE_ELEMENT_DWORDS; 7233c965db44STomer Tayar elements = (struct protection_override_element *)dump_buf; 7234c965db44STomer Tayar 7235c965db44STomer Tayar /* Decode elements */ 7236c965db44STomer Tayar for (i = 0; i < num_elements; i++) { 7237c965db44STomer Tayar u32 address = GET_FIELD(elements[i].data, 7238c965db44STomer Tayar PROTECTION_OVERRIDE_ELEMENT_ADDRESS) * 7239c965db44STomer Tayar PROTECTION_OVERRIDE_ELEMENT_ADDR_FACTOR; 7240c965db44STomer Tayar 7241c965db44STomer Tayar results_offset += 7242c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 7243c965db44STomer Tayar results_offset), 7244be086e7cSMintz, Yuval "window %2d, address: 0x%07x, size: %7d regs, read: %d, write: %d, read protection: %-12s, write protection: %-12s\n", 7245c965db44STomer Tayar i, address, 7246be086e7cSMintz, Yuval (u32)GET_FIELD(elements[i].data, 7247c965db44STomer Tayar PROTECTION_OVERRIDE_ELEMENT_WINDOW_SIZE), 7248be086e7cSMintz, Yuval (u32)GET_FIELD(elements[i].data, 7249c965db44STomer Tayar PROTECTION_OVERRIDE_ELEMENT_READ), 7250be086e7cSMintz, Yuval (u32)GET_FIELD(elements[i].data, 7251c965db44STomer Tayar PROTECTION_OVERRIDE_ELEMENT_WRITE), 7252c965db44STomer Tayar s_protection_strs[GET_FIELD(elements[i].data, 7253c965db44STomer Tayar PROTECTION_OVERRIDE_ELEMENT_READ_PROTECTION)], 7254c965db44STomer Tayar s_protection_strs[GET_FIELD(elements[i].data, 7255c965db44STomer Tayar PROTECTION_OVERRIDE_ELEMENT_WRITE_PROTECTION)]); 7256c965db44STomer Tayar } 7257c965db44STomer Tayar 7258c965db44STomer Tayar results_offset += sprintf(qed_get_buf_ptr(results_buf, 7259c965db44STomer Tayar results_offset), 7260c965db44STomer Tayar "protection override contained %d elements", 7261c965db44STomer Tayar num_elements); 7262c965db44STomer Tayar 7263c965db44STomer Tayar /* Add 1 for string NULL termination */ 7264c965db44STomer Tayar *parsed_results_bytes = results_offset + 1; 72657b6859fbSMintz, Yuval 7266c965db44STomer Tayar return DBG_STATUS_OK; 7267c965db44STomer Tayar } 7268c965db44STomer Tayar 72697b6859fbSMintz, Yuval /* Parses a FW Asserts dump buffer. 72707b6859fbSMintz, Yuval * If result_buf is not NULL, the FW Asserts results are printed to it. 72717b6859fbSMintz, Yuval * In any case, the required results buffer size is assigned to 72727b6859fbSMintz, Yuval * parsed_results_bytes. 72737b6859fbSMintz, Yuval * The parsing status is returned. 72747b6859fbSMintz, Yuval */ 7275da090917STomer Tayar static enum dbg_status qed_parse_fw_asserts_dump(u32 *dump_buf, 72767b6859fbSMintz, Yuval char *results_buf, 72777b6859fbSMintz, Yuval u32 *parsed_results_bytes) 72787b6859fbSMintz, Yuval { 72797b6859fbSMintz, Yuval u32 num_section_params, param_num_val, i, results_offset = 0; 72807b6859fbSMintz, Yuval const char *param_name, *param_str_val, *section_name; 72817b6859fbSMintz, Yuval bool last_section_found = false; 72827b6859fbSMintz, Yuval 72837b6859fbSMintz, Yuval *parsed_results_bytes = 0; 72847b6859fbSMintz, Yuval 72857b6859fbSMintz, Yuval /* Read global_params section */ 72867b6859fbSMintz, Yuval dump_buf += qed_read_section_hdr(dump_buf, 72877b6859fbSMintz, Yuval §ion_name, &num_section_params); 72887b6859fbSMintz, Yuval if (strcmp(section_name, "global_params")) 72897b6859fbSMintz, Yuval return DBG_STATUS_FW_ASSERTS_PARSE_FAILED; 72907b6859fbSMintz, Yuval 72917b6859fbSMintz, Yuval /* Print global params */ 72927b6859fbSMintz, Yuval dump_buf += qed_print_section_params(dump_buf, 72937b6859fbSMintz, Yuval num_section_params, 72947b6859fbSMintz, Yuval results_buf, &results_offset); 72957b6859fbSMintz, Yuval 72967b6859fbSMintz, Yuval while (!last_section_found) { 72977b6859fbSMintz, Yuval dump_buf += qed_read_section_hdr(dump_buf, 72987b6859fbSMintz, Yuval §ion_name, 72997b6859fbSMintz, Yuval &num_section_params); 73007b6859fbSMintz, Yuval if (!strcmp(section_name, "fw_asserts")) { 73017b6859fbSMintz, Yuval /* Extract params */ 73027b6859fbSMintz, Yuval const char *storm_letter = NULL; 73037b6859fbSMintz, Yuval u32 storm_dump_size = 0; 73047b6859fbSMintz, Yuval 73057b6859fbSMintz, Yuval for (i = 0; i < num_section_params; i++) { 73067b6859fbSMintz, Yuval dump_buf += qed_read_param(dump_buf, 73077b6859fbSMintz, Yuval ¶m_name, 73087b6859fbSMintz, Yuval ¶m_str_val, 73097b6859fbSMintz, Yuval ¶m_num_val); 73107b6859fbSMintz, Yuval if (!strcmp(param_name, "storm")) 73117b6859fbSMintz, Yuval storm_letter = param_str_val; 73127b6859fbSMintz, Yuval else if (!strcmp(param_name, "size")) 73137b6859fbSMintz, Yuval storm_dump_size = param_num_val; 73147b6859fbSMintz, Yuval else 73157b6859fbSMintz, Yuval return 73167b6859fbSMintz, Yuval DBG_STATUS_FW_ASSERTS_PARSE_FAILED; 73177b6859fbSMintz, Yuval } 73187b6859fbSMintz, Yuval 73197b6859fbSMintz, Yuval if (!storm_letter || !storm_dump_size) 73207b6859fbSMintz, Yuval return DBG_STATUS_FW_ASSERTS_PARSE_FAILED; 73217b6859fbSMintz, Yuval 73227b6859fbSMintz, Yuval /* Print data */ 73237b6859fbSMintz, Yuval results_offset += 73247b6859fbSMintz, Yuval sprintf(qed_get_buf_ptr(results_buf, 73257b6859fbSMintz, Yuval results_offset), 73267b6859fbSMintz, Yuval "\n%sSTORM_ASSERT: size=%d\n", 73277b6859fbSMintz, Yuval storm_letter, storm_dump_size); 73287b6859fbSMintz, Yuval for (i = 0; i < storm_dump_size; i++, dump_buf++) 73297b6859fbSMintz, Yuval results_offset += 73307b6859fbSMintz, Yuval sprintf(qed_get_buf_ptr(results_buf, 73317b6859fbSMintz, Yuval results_offset), 73327b6859fbSMintz, Yuval "%08x\n", *dump_buf); 73337b6859fbSMintz, Yuval } else if (!strcmp(section_name, "last")) { 73347b6859fbSMintz, Yuval last_section_found = true; 73357b6859fbSMintz, Yuval } else { 73367b6859fbSMintz, Yuval return DBG_STATUS_FW_ASSERTS_PARSE_FAILED; 73377b6859fbSMintz, Yuval } 73387b6859fbSMintz, Yuval } 73397b6859fbSMintz, Yuval 73407b6859fbSMintz, Yuval /* Add 1 for string NULL termination */ 73417b6859fbSMintz, Yuval *parsed_results_bytes = results_offset + 1; 73427b6859fbSMintz, Yuval 73437b6859fbSMintz, Yuval return DBG_STATUS_OK; 73447b6859fbSMintz, Yuval } 73457b6859fbSMintz, Yuval 73467b6859fbSMintz, Yuval /***************************** Public Functions *******************************/ 73477b6859fbSMintz, Yuval 73487b6859fbSMintz, Yuval enum dbg_status qed_dbg_user_set_bin_ptr(const u8 * const bin_ptr) 73497b6859fbSMintz, Yuval { 73507b6859fbSMintz, Yuval struct bin_buffer_hdr *buf_array = (struct bin_buffer_hdr *)bin_ptr; 73517b6859fbSMintz, Yuval u8 buf_id; 73527b6859fbSMintz, Yuval 73537b6859fbSMintz, Yuval /* Convert binary data to debug arrays */ 73547b6859fbSMintz, Yuval for (buf_id = 0; buf_id < MAX_BIN_DBG_BUFFER_TYPE; buf_id++) { 73557b6859fbSMintz, Yuval s_user_dbg_arrays[buf_id].ptr = 73567b6859fbSMintz, Yuval (u32 *)(bin_ptr + buf_array[buf_id].offset); 73577b6859fbSMintz, Yuval s_user_dbg_arrays[buf_id].size_in_dwords = 73587b6859fbSMintz, Yuval BYTES_TO_DWORDS(buf_array[buf_id].length); 73597b6859fbSMintz, Yuval } 73607b6859fbSMintz, Yuval 73617b6859fbSMintz, Yuval return DBG_STATUS_OK; 73627b6859fbSMintz, Yuval } 73637b6859fbSMintz, Yuval 73647b6859fbSMintz, Yuval const char *qed_dbg_get_status_str(enum dbg_status status) 73657b6859fbSMintz, Yuval { 73667b6859fbSMintz, Yuval return (status < 73677b6859fbSMintz, Yuval MAX_DBG_STATUS) ? s_status_str[status] : "Invalid debug status"; 73687b6859fbSMintz, Yuval } 73697b6859fbSMintz, Yuval 73707b6859fbSMintz, Yuval enum dbg_status qed_get_idle_chk_results_buf_size(struct qed_hwfn *p_hwfn, 73717b6859fbSMintz, Yuval u32 *dump_buf, 73727b6859fbSMintz, Yuval u32 num_dumped_dwords, 73737b6859fbSMintz, Yuval u32 *results_buf_size) 73747b6859fbSMintz, Yuval { 73757b6859fbSMintz, Yuval u32 num_errors, num_warnings; 73767b6859fbSMintz, Yuval 7377da090917STomer Tayar return qed_parse_idle_chk_dump(dump_buf, 73787b6859fbSMintz, Yuval num_dumped_dwords, 73797b6859fbSMintz, Yuval NULL, 73807b6859fbSMintz, Yuval results_buf_size, 73817b6859fbSMintz, Yuval &num_errors, &num_warnings); 73827b6859fbSMintz, Yuval } 73837b6859fbSMintz, Yuval 73847b6859fbSMintz, Yuval enum dbg_status qed_print_idle_chk_results(struct qed_hwfn *p_hwfn, 73857b6859fbSMintz, Yuval u32 *dump_buf, 73867b6859fbSMintz, Yuval u32 num_dumped_dwords, 73877b6859fbSMintz, Yuval char *results_buf, 7388da090917STomer Tayar u32 *num_errors, 7389da090917STomer Tayar u32 *num_warnings) 73907b6859fbSMintz, Yuval { 73917b6859fbSMintz, Yuval u32 parsed_buf_size; 73927b6859fbSMintz, Yuval 7393da090917STomer Tayar return qed_parse_idle_chk_dump(dump_buf, 73947b6859fbSMintz, Yuval num_dumped_dwords, 73957b6859fbSMintz, Yuval results_buf, 73967b6859fbSMintz, Yuval &parsed_buf_size, 73977b6859fbSMintz, Yuval num_errors, num_warnings); 73987b6859fbSMintz, Yuval } 73997b6859fbSMintz, Yuval 74007b6859fbSMintz, Yuval void qed_dbg_mcp_trace_set_meta_data(u32 *data, u32 size) 74017b6859fbSMintz, Yuval { 740250bc60cbSMichal Kalderon s_mcp_trace_meta_arr.ptr = data; 740350bc60cbSMichal Kalderon s_mcp_trace_meta_arr.size_in_dwords = size; 74047b6859fbSMintz, Yuval } 74057b6859fbSMintz, Yuval 74067b6859fbSMintz, Yuval enum dbg_status qed_get_mcp_trace_results_buf_size(struct qed_hwfn *p_hwfn, 74077b6859fbSMintz, Yuval u32 *dump_buf, 74087b6859fbSMintz, Yuval u32 num_dumped_dwords, 74097b6859fbSMintz, Yuval u32 *results_buf_size) 74107b6859fbSMintz, Yuval { 74117b6859fbSMintz, Yuval return qed_parse_mcp_trace_dump(p_hwfn, 7412da090917STomer Tayar dump_buf, NULL, results_buf_size); 74137b6859fbSMintz, Yuval } 74147b6859fbSMintz, Yuval 74157b6859fbSMintz, Yuval enum dbg_status qed_print_mcp_trace_results(struct qed_hwfn *p_hwfn, 74167b6859fbSMintz, Yuval u32 *dump_buf, 74177b6859fbSMintz, Yuval u32 num_dumped_dwords, 74187b6859fbSMintz, Yuval char *results_buf) 74197b6859fbSMintz, Yuval { 74207b6859fbSMintz, Yuval u32 parsed_buf_size; 74217b6859fbSMintz, Yuval 74227b6859fbSMintz, Yuval return qed_parse_mcp_trace_dump(p_hwfn, 74237b6859fbSMintz, Yuval dump_buf, 74247b6859fbSMintz, Yuval results_buf, &parsed_buf_size); 74257b6859fbSMintz, Yuval } 74267b6859fbSMintz, Yuval 742750bc60cbSMichal Kalderon enum dbg_status qed_print_mcp_trace_line(u8 *dump_buf, 742850bc60cbSMichal Kalderon u32 num_dumped_bytes, 742950bc60cbSMichal Kalderon char *results_buf) 743050bc60cbSMichal Kalderon { 743150bc60cbSMichal Kalderon u32 parsed_bytes; 743250bc60cbSMichal Kalderon 743350bc60cbSMichal Kalderon return qed_parse_mcp_trace_buf(dump_buf, 743450bc60cbSMichal Kalderon num_dumped_bytes, 743550bc60cbSMichal Kalderon 0, 743650bc60cbSMichal Kalderon num_dumped_bytes, 743750bc60cbSMichal Kalderon results_buf, &parsed_bytes); 743850bc60cbSMichal Kalderon } 743950bc60cbSMichal Kalderon 74407b6859fbSMintz, Yuval enum dbg_status qed_get_reg_fifo_results_buf_size(struct qed_hwfn *p_hwfn, 74417b6859fbSMintz, Yuval u32 *dump_buf, 74427b6859fbSMintz, Yuval u32 num_dumped_dwords, 74437b6859fbSMintz, Yuval u32 *results_buf_size) 74447b6859fbSMintz, Yuval { 7445da090917STomer Tayar return qed_parse_reg_fifo_dump(dump_buf, NULL, results_buf_size); 74467b6859fbSMintz, Yuval } 74477b6859fbSMintz, Yuval 74487b6859fbSMintz, Yuval enum dbg_status qed_print_reg_fifo_results(struct qed_hwfn *p_hwfn, 74497b6859fbSMintz, Yuval u32 *dump_buf, 74507b6859fbSMintz, Yuval u32 num_dumped_dwords, 74517b6859fbSMintz, Yuval char *results_buf) 74527b6859fbSMintz, Yuval { 74537b6859fbSMintz, Yuval u32 parsed_buf_size; 74547b6859fbSMintz, Yuval 7455da090917STomer Tayar return qed_parse_reg_fifo_dump(dump_buf, results_buf, &parsed_buf_size); 74567b6859fbSMintz, Yuval } 74577b6859fbSMintz, Yuval 74587b6859fbSMintz, Yuval enum dbg_status qed_get_igu_fifo_results_buf_size(struct qed_hwfn *p_hwfn, 74597b6859fbSMintz, Yuval u32 *dump_buf, 74607b6859fbSMintz, Yuval u32 num_dumped_dwords, 74617b6859fbSMintz, Yuval u32 *results_buf_size) 74627b6859fbSMintz, Yuval { 7463da090917STomer Tayar return qed_parse_igu_fifo_dump(dump_buf, NULL, results_buf_size); 74647b6859fbSMintz, Yuval } 74657b6859fbSMintz, Yuval 74667b6859fbSMintz, Yuval enum dbg_status qed_print_igu_fifo_results(struct qed_hwfn *p_hwfn, 74677b6859fbSMintz, Yuval u32 *dump_buf, 74687b6859fbSMintz, Yuval u32 num_dumped_dwords, 74697b6859fbSMintz, Yuval char *results_buf) 74707b6859fbSMintz, Yuval { 74717b6859fbSMintz, Yuval u32 parsed_buf_size; 74727b6859fbSMintz, Yuval 7473da090917STomer Tayar return qed_parse_igu_fifo_dump(dump_buf, results_buf, &parsed_buf_size); 74747b6859fbSMintz, Yuval } 74757b6859fbSMintz, Yuval 7476c965db44STomer Tayar enum dbg_status 7477c965db44STomer Tayar qed_get_protection_override_results_buf_size(struct qed_hwfn *p_hwfn, 7478c965db44STomer Tayar u32 *dump_buf, 7479c965db44STomer Tayar u32 num_dumped_dwords, 7480c965db44STomer Tayar u32 *results_buf_size) 7481c965db44STomer Tayar { 7482da090917STomer Tayar return qed_parse_protection_override_dump(dump_buf, 7483c965db44STomer Tayar NULL, results_buf_size); 7484c965db44STomer Tayar } 7485c965db44STomer Tayar 7486c965db44STomer Tayar enum dbg_status qed_print_protection_override_results(struct qed_hwfn *p_hwfn, 7487c965db44STomer Tayar u32 *dump_buf, 7488c965db44STomer Tayar u32 num_dumped_dwords, 7489c965db44STomer Tayar char *results_buf) 7490c965db44STomer Tayar { 7491c965db44STomer Tayar u32 parsed_buf_size; 7492c965db44STomer Tayar 7493da090917STomer Tayar return qed_parse_protection_override_dump(dump_buf, 7494c965db44STomer Tayar results_buf, 7495c965db44STomer Tayar &parsed_buf_size); 7496c965db44STomer Tayar } 7497c965db44STomer Tayar 7498c965db44STomer Tayar enum dbg_status qed_get_fw_asserts_results_buf_size(struct qed_hwfn *p_hwfn, 7499c965db44STomer Tayar u32 *dump_buf, 7500c965db44STomer Tayar u32 num_dumped_dwords, 7501c965db44STomer Tayar u32 *results_buf_size) 7502c965db44STomer Tayar { 7503da090917STomer Tayar return qed_parse_fw_asserts_dump(dump_buf, NULL, results_buf_size); 7504c965db44STomer Tayar } 7505c965db44STomer Tayar 7506c965db44STomer Tayar enum dbg_status qed_print_fw_asserts_results(struct qed_hwfn *p_hwfn, 7507c965db44STomer Tayar u32 *dump_buf, 7508c965db44STomer Tayar u32 num_dumped_dwords, 7509c965db44STomer Tayar char *results_buf) 7510c965db44STomer Tayar { 7511c965db44STomer Tayar u32 parsed_buf_size; 7512c965db44STomer Tayar 7513da090917STomer Tayar return qed_parse_fw_asserts_dump(dump_buf, 7514c965db44STomer Tayar results_buf, &parsed_buf_size); 7515c965db44STomer Tayar } 7516c965db44STomer Tayar 75170ebbd1c8SMintz, Yuval enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn, 75180ebbd1c8SMintz, Yuval struct dbg_attn_block_result *results) 75190ebbd1c8SMintz, Yuval { 75200ebbd1c8SMintz, Yuval struct user_dbg_array *block_attn, *pstrings; 75210ebbd1c8SMintz, Yuval const u32 *block_attn_name_offsets; 75220ebbd1c8SMintz, Yuval enum dbg_attn_type attn_type; 75230ebbd1c8SMintz, Yuval const char *block_name; 75240ebbd1c8SMintz, Yuval u8 num_regs, i, j; 75250ebbd1c8SMintz, Yuval 75260ebbd1c8SMintz, Yuval num_regs = GET_FIELD(results->data, DBG_ATTN_BLOCK_RESULT_NUM_REGS); 75270ebbd1c8SMintz, Yuval attn_type = (enum dbg_attn_type) 75280ebbd1c8SMintz, Yuval GET_FIELD(results->data, 75290ebbd1c8SMintz, Yuval DBG_ATTN_BLOCK_RESULT_ATTN_TYPE); 75300ebbd1c8SMintz, Yuval block_name = s_block_info_arr[results->block_id].name; 75310ebbd1c8SMintz, Yuval 75320ebbd1c8SMintz, Yuval if (!s_user_dbg_arrays[BIN_BUF_DBG_ATTN_INDEXES].ptr || 75330ebbd1c8SMintz, Yuval !s_user_dbg_arrays[BIN_BUF_DBG_ATTN_NAME_OFFSETS].ptr || 75340ebbd1c8SMintz, Yuval !s_user_dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS].ptr) 75350ebbd1c8SMintz, Yuval return DBG_STATUS_DBG_ARRAY_NOT_SET; 75360ebbd1c8SMintz, Yuval 75370ebbd1c8SMintz, Yuval block_attn = &s_user_dbg_arrays[BIN_BUF_DBG_ATTN_NAME_OFFSETS]; 75380ebbd1c8SMintz, Yuval block_attn_name_offsets = &block_attn->ptr[results->names_offset]; 75390ebbd1c8SMintz, Yuval 75400ebbd1c8SMintz, Yuval /* Go over registers with a non-zero attention status */ 75410ebbd1c8SMintz, Yuval for (i = 0; i < num_regs; i++) { 7542da090917STomer Tayar struct dbg_attn_bit_mapping *bit_mapping; 75430ebbd1c8SMintz, Yuval struct dbg_attn_reg_result *reg_result; 75440ebbd1c8SMintz, Yuval u8 num_reg_attn, bit_idx = 0; 75450ebbd1c8SMintz, Yuval 75460ebbd1c8SMintz, Yuval reg_result = &results->reg_results[i]; 75470ebbd1c8SMintz, Yuval num_reg_attn = GET_FIELD(reg_result->data, 75480ebbd1c8SMintz, Yuval DBG_ATTN_REG_RESULT_NUM_REG_ATTN); 75490ebbd1c8SMintz, Yuval block_attn = &s_user_dbg_arrays[BIN_BUF_DBG_ATTN_INDEXES]; 7550da090917STomer Tayar bit_mapping = &((struct dbg_attn_bit_mapping *) 75510ebbd1c8SMintz, Yuval block_attn->ptr)[reg_result->block_attn_offset]; 75520ebbd1c8SMintz, Yuval 75530ebbd1c8SMintz, Yuval pstrings = &s_user_dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS]; 75540ebbd1c8SMintz, Yuval 75550ebbd1c8SMintz, Yuval /* Go over attention status bits */ 75560ebbd1c8SMintz, Yuval for (j = 0; j < num_reg_attn; j++) { 7557da090917STomer Tayar u16 attn_idx_val = GET_FIELD(bit_mapping[j].data, 75580ebbd1c8SMintz, Yuval DBG_ATTN_BIT_MAPPING_VAL); 75590ebbd1c8SMintz, Yuval const char *attn_name, *attn_type_str, *masked_str; 7560da090917STomer Tayar u32 attn_name_offset, sts_addr; 75610ebbd1c8SMintz, Yuval 75620ebbd1c8SMintz, Yuval /* Check if bit mask should be advanced (due to unused 75630ebbd1c8SMintz, Yuval * bits). 75640ebbd1c8SMintz, Yuval */ 7565da090917STomer Tayar if (GET_FIELD(bit_mapping[j].data, 75660ebbd1c8SMintz, Yuval DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT)) { 75670ebbd1c8SMintz, Yuval bit_idx += (u8)attn_idx_val; 75680ebbd1c8SMintz, Yuval continue; 75690ebbd1c8SMintz, Yuval } 75700ebbd1c8SMintz, Yuval 75710ebbd1c8SMintz, Yuval /* Check current bit index */ 75720ebbd1c8SMintz, Yuval if (!(reg_result->sts_val & BIT(bit_idx))) { 75730ebbd1c8SMintz, Yuval bit_idx++; 75740ebbd1c8SMintz, Yuval continue; 75750ebbd1c8SMintz, Yuval } 75760ebbd1c8SMintz, Yuval 75770ebbd1c8SMintz, Yuval /* Find attention name */ 7578da090917STomer Tayar attn_name_offset = 7579da090917STomer Tayar block_attn_name_offsets[attn_idx_val]; 75800ebbd1c8SMintz, Yuval attn_name = &((const char *) 7581da090917STomer Tayar pstrings->ptr)[attn_name_offset]; 75820ebbd1c8SMintz, Yuval attn_type_str = attn_type == ATTN_TYPE_INTERRUPT ? 75830ebbd1c8SMintz, Yuval "Interrupt" : "Parity"; 75840ebbd1c8SMintz, Yuval masked_str = reg_result->mask_val & BIT(bit_idx) ? 75850ebbd1c8SMintz, Yuval " [masked]" : ""; 75860ebbd1c8SMintz, Yuval sts_addr = GET_FIELD(reg_result->data, 75870ebbd1c8SMintz, Yuval DBG_ATTN_REG_RESULT_STS_ADDRESS); 75880ebbd1c8SMintz, Yuval DP_NOTICE(p_hwfn, 75890ebbd1c8SMintz, Yuval "%s (%s) : %s [address 0x%08x, bit %d]%s\n", 75900ebbd1c8SMintz, Yuval block_name, attn_type_str, attn_name, 75910ebbd1c8SMintz, Yuval sts_addr, bit_idx, masked_str); 75920ebbd1c8SMintz, Yuval 75930ebbd1c8SMintz, Yuval bit_idx++; 75940ebbd1c8SMintz, Yuval } 75950ebbd1c8SMintz, Yuval } 75960ebbd1c8SMintz, Yuval 75970ebbd1c8SMintz, Yuval return DBG_STATUS_OK; 75980ebbd1c8SMintz, Yuval } 75990ebbd1c8SMintz, Yuval 7600c965db44STomer Tayar /* Wrapper for unifying the idle_chk and mcp_trace api */ 76018c93beafSYuval Mintz static enum dbg_status 76028c93beafSYuval Mintz qed_print_idle_chk_results_wrapper(struct qed_hwfn *p_hwfn, 7603c965db44STomer Tayar u32 *dump_buf, 7604c965db44STomer Tayar u32 num_dumped_dwords, 7605c965db44STomer Tayar char *results_buf) 7606c965db44STomer Tayar { 7607c965db44STomer Tayar u32 num_errors, num_warnnings; 7608c965db44STomer Tayar 7609c965db44STomer Tayar return qed_print_idle_chk_results(p_hwfn, dump_buf, num_dumped_dwords, 7610c965db44STomer Tayar results_buf, &num_errors, 7611c965db44STomer Tayar &num_warnnings); 7612c965db44STomer Tayar } 7613c965db44STomer Tayar 7614c965db44STomer Tayar /* Feature meta data lookup table */ 7615c965db44STomer Tayar static struct { 7616c965db44STomer Tayar char *name; 7617c965db44STomer Tayar enum dbg_status (*get_size)(struct qed_hwfn *p_hwfn, 7618c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *size); 7619c965db44STomer Tayar enum dbg_status (*perform_dump)(struct qed_hwfn *p_hwfn, 7620c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *dump_buf, 7621c965db44STomer Tayar u32 buf_size, u32 *dumped_dwords); 7622c965db44STomer Tayar enum dbg_status (*print_results)(struct qed_hwfn *p_hwfn, 7623c965db44STomer Tayar u32 *dump_buf, u32 num_dumped_dwords, 7624c965db44STomer Tayar char *results_buf); 7625c965db44STomer Tayar enum dbg_status (*results_buf_size)(struct qed_hwfn *p_hwfn, 7626c965db44STomer Tayar u32 *dump_buf, 7627c965db44STomer Tayar u32 num_dumped_dwords, 7628c965db44STomer Tayar u32 *results_buf_size); 7629c965db44STomer Tayar } qed_features_lookup[] = { 7630c965db44STomer Tayar { 7631c965db44STomer Tayar "grc", qed_dbg_grc_get_dump_buf_size, 7632c965db44STomer Tayar qed_dbg_grc_dump, NULL, NULL}, { 7633c965db44STomer Tayar "idle_chk", 7634c965db44STomer Tayar qed_dbg_idle_chk_get_dump_buf_size, 7635c965db44STomer Tayar qed_dbg_idle_chk_dump, 7636c965db44STomer Tayar qed_print_idle_chk_results_wrapper, 7637c965db44STomer Tayar qed_get_idle_chk_results_buf_size}, { 7638c965db44STomer Tayar "mcp_trace", 7639c965db44STomer Tayar qed_dbg_mcp_trace_get_dump_buf_size, 7640c965db44STomer Tayar qed_dbg_mcp_trace_dump, qed_print_mcp_trace_results, 7641c965db44STomer Tayar qed_get_mcp_trace_results_buf_size}, { 7642c965db44STomer Tayar "reg_fifo", 7643c965db44STomer Tayar qed_dbg_reg_fifo_get_dump_buf_size, 7644c965db44STomer Tayar qed_dbg_reg_fifo_dump, qed_print_reg_fifo_results, 7645c965db44STomer Tayar qed_get_reg_fifo_results_buf_size}, { 7646c965db44STomer Tayar "igu_fifo", 7647c965db44STomer Tayar qed_dbg_igu_fifo_get_dump_buf_size, 7648c965db44STomer Tayar qed_dbg_igu_fifo_dump, qed_print_igu_fifo_results, 7649c965db44STomer Tayar qed_get_igu_fifo_results_buf_size}, { 7650c965db44STomer Tayar "protection_override", 7651c965db44STomer Tayar qed_dbg_protection_override_get_dump_buf_size, 7652c965db44STomer Tayar qed_dbg_protection_override_dump, 7653c965db44STomer Tayar qed_print_protection_override_results, 7654c965db44STomer Tayar qed_get_protection_override_results_buf_size}, { 7655c965db44STomer Tayar "fw_asserts", 7656c965db44STomer Tayar qed_dbg_fw_asserts_get_dump_buf_size, 7657c965db44STomer Tayar qed_dbg_fw_asserts_dump, 7658c965db44STomer Tayar qed_print_fw_asserts_results, 7659c965db44STomer Tayar qed_get_fw_asserts_results_buf_size},}; 7660c965db44STomer Tayar 7661c965db44STomer Tayar static void qed_dbg_print_feature(u8 *p_text_buf, u32 text_size) 7662c965db44STomer Tayar { 7663c965db44STomer Tayar u32 i, precision = 80; 7664c965db44STomer Tayar 7665c965db44STomer Tayar if (!p_text_buf) 7666c965db44STomer Tayar return; 7667c965db44STomer Tayar 7668c965db44STomer Tayar pr_notice("\n%.*s", precision, p_text_buf); 7669c965db44STomer Tayar for (i = precision; i < text_size; i += precision) 7670c965db44STomer Tayar pr_cont("%.*s", precision, p_text_buf + i); 7671c965db44STomer Tayar pr_cont("\n"); 7672c965db44STomer Tayar } 7673c965db44STomer Tayar 7674c965db44STomer Tayar #define QED_RESULTS_BUF_MIN_SIZE 16 7675c965db44STomer Tayar /* Generic function for decoding debug feature info */ 76768c93beafSYuval Mintz static enum dbg_status format_feature(struct qed_hwfn *p_hwfn, 7677c965db44STomer Tayar enum qed_dbg_features feature_idx) 7678c965db44STomer Tayar { 7679c965db44STomer Tayar struct qed_dbg_feature *feature = 7680c965db44STomer Tayar &p_hwfn->cdev->dbg_params.features[feature_idx]; 7681c965db44STomer Tayar u32 text_size_bytes, null_char_pos, i; 7682c965db44STomer Tayar enum dbg_status rc; 7683c965db44STomer Tayar char *text_buf; 7684c965db44STomer Tayar 7685c965db44STomer Tayar /* Check if feature supports formatting capability */ 7686c965db44STomer Tayar if (!qed_features_lookup[feature_idx].results_buf_size) 7687c965db44STomer Tayar return DBG_STATUS_OK; 7688c965db44STomer Tayar 7689c965db44STomer Tayar /* Obtain size of formatted output */ 7690c965db44STomer Tayar rc = qed_features_lookup[feature_idx]. 7691c965db44STomer Tayar results_buf_size(p_hwfn, (u32 *)feature->dump_buf, 7692c965db44STomer Tayar feature->dumped_dwords, &text_size_bytes); 7693c965db44STomer Tayar if (rc != DBG_STATUS_OK) 7694c965db44STomer Tayar return rc; 7695c965db44STomer Tayar 7696c965db44STomer Tayar /* Make sure that the allocated size is a multiple of dword (4 bytes) */ 7697c965db44STomer Tayar null_char_pos = text_size_bytes - 1; 7698c965db44STomer Tayar text_size_bytes = (text_size_bytes + 3) & ~0x3; 7699c965db44STomer Tayar 7700c965db44STomer Tayar if (text_size_bytes < QED_RESULTS_BUF_MIN_SIZE) { 7701c965db44STomer Tayar DP_NOTICE(p_hwfn->cdev, 7702c965db44STomer Tayar "formatted size of feature was too small %d. Aborting\n", 7703c965db44STomer Tayar text_size_bytes); 7704c965db44STomer Tayar return DBG_STATUS_INVALID_ARGS; 7705c965db44STomer Tayar } 7706c965db44STomer Tayar 7707c965db44STomer Tayar /* Allocate temp text buf */ 7708c965db44STomer Tayar text_buf = vzalloc(text_size_bytes); 7709c965db44STomer Tayar if (!text_buf) 7710c965db44STomer Tayar return DBG_STATUS_VIRT_MEM_ALLOC_FAILED; 7711c965db44STomer Tayar 7712c965db44STomer Tayar /* Decode feature opcodes to string on temp buf */ 7713c965db44STomer Tayar rc = qed_features_lookup[feature_idx]. 7714c965db44STomer Tayar print_results(p_hwfn, (u32 *)feature->dump_buf, 7715c965db44STomer Tayar feature->dumped_dwords, text_buf); 7716c965db44STomer Tayar if (rc != DBG_STATUS_OK) { 7717c965db44STomer Tayar vfree(text_buf); 7718c965db44STomer Tayar return rc; 7719c965db44STomer Tayar } 7720c965db44STomer Tayar 7721c965db44STomer Tayar /* Replace the original null character with a '\n' character. 7722c965db44STomer Tayar * The bytes that were added as a result of the dword alignment are also 7723c965db44STomer Tayar * padded with '\n' characters. 7724c965db44STomer Tayar */ 7725c965db44STomer Tayar for (i = null_char_pos; i < text_size_bytes; i++) 7726c965db44STomer Tayar text_buf[i] = '\n'; 7727c965db44STomer Tayar 7728c965db44STomer Tayar /* Dump printable feature to log */ 7729c965db44STomer Tayar if (p_hwfn->cdev->dbg_params.print_data) 7730c965db44STomer Tayar qed_dbg_print_feature(text_buf, text_size_bytes); 7731c965db44STomer Tayar 7732c965db44STomer Tayar /* Free the old dump_buf and point the dump_buf to the newly allocagted 7733c965db44STomer Tayar * and formatted text buffer. 7734c965db44STomer Tayar */ 7735c965db44STomer Tayar vfree(feature->dump_buf); 7736c965db44STomer Tayar feature->dump_buf = text_buf; 7737c965db44STomer Tayar feature->buf_size = text_size_bytes; 7738c965db44STomer Tayar feature->dumped_dwords = text_size_bytes / 4; 7739c965db44STomer Tayar return rc; 7740c965db44STomer Tayar } 7741c965db44STomer Tayar 7742c965db44STomer Tayar /* Generic function for performing the dump of a debug feature. */ 77438c93beafSYuval Mintz static enum dbg_status qed_dbg_dump(struct qed_hwfn *p_hwfn, 77448c93beafSYuval Mintz struct qed_ptt *p_ptt, 7745c965db44STomer Tayar enum qed_dbg_features feature_idx) 7746c965db44STomer Tayar { 7747c965db44STomer Tayar struct qed_dbg_feature *feature = 7748c965db44STomer Tayar &p_hwfn->cdev->dbg_params.features[feature_idx]; 7749c965db44STomer Tayar u32 buf_size_dwords; 7750c965db44STomer Tayar enum dbg_status rc; 7751c965db44STomer Tayar 7752c965db44STomer Tayar DP_NOTICE(p_hwfn->cdev, "Collecting a debug feature [\"%s\"]\n", 7753c965db44STomer Tayar qed_features_lookup[feature_idx].name); 7754c965db44STomer Tayar 7755c965db44STomer Tayar /* Dump_buf was already allocated need to free (this can happen if dump 7756c965db44STomer Tayar * was called but file was never read). 7757c965db44STomer Tayar * We can't use the buffer as is since size may have changed. 7758c965db44STomer Tayar */ 7759c965db44STomer Tayar if (feature->dump_buf) { 7760c965db44STomer Tayar vfree(feature->dump_buf); 7761c965db44STomer Tayar feature->dump_buf = NULL; 7762c965db44STomer Tayar } 7763c965db44STomer Tayar 7764c965db44STomer Tayar /* Get buffer size from hsi, allocate accordingly, and perform the 7765c965db44STomer Tayar * dump. 7766c965db44STomer Tayar */ 7767c965db44STomer Tayar rc = qed_features_lookup[feature_idx].get_size(p_hwfn, p_ptt, 7768c965db44STomer Tayar &buf_size_dwords); 7769be086e7cSMintz, Yuval if (rc != DBG_STATUS_OK && rc != DBG_STATUS_NVRAM_GET_IMAGE_FAILED) 7770c965db44STomer Tayar return rc; 7771c965db44STomer Tayar feature->buf_size = buf_size_dwords * sizeof(u32); 7772c965db44STomer Tayar feature->dump_buf = vmalloc(feature->buf_size); 7773c965db44STomer Tayar if (!feature->dump_buf) 7774c965db44STomer Tayar return DBG_STATUS_VIRT_MEM_ALLOC_FAILED; 7775c965db44STomer Tayar 7776c965db44STomer Tayar rc = qed_features_lookup[feature_idx]. 7777c965db44STomer Tayar perform_dump(p_hwfn, p_ptt, (u32 *)feature->dump_buf, 7778c965db44STomer Tayar feature->buf_size / sizeof(u32), 7779c965db44STomer Tayar &feature->dumped_dwords); 7780c965db44STomer Tayar 7781c965db44STomer Tayar /* If mcp is stuck we get DBG_STATUS_NVRAM_GET_IMAGE_FAILED error. 7782c965db44STomer Tayar * In this case the buffer holds valid binary data, but we wont able 7783c965db44STomer Tayar * to parse it (since parsing relies on data in NVRAM which is only 7784c965db44STomer Tayar * accessible when MFW is responsive). skip the formatting but return 7785c965db44STomer Tayar * success so that binary data is provided. 7786c965db44STomer Tayar */ 7787c965db44STomer Tayar if (rc == DBG_STATUS_NVRAM_GET_IMAGE_FAILED) 7788c965db44STomer Tayar return DBG_STATUS_OK; 7789c965db44STomer Tayar 7790c965db44STomer Tayar if (rc != DBG_STATUS_OK) 7791c965db44STomer Tayar return rc; 7792c965db44STomer Tayar 7793c965db44STomer Tayar /* Format output */ 7794c965db44STomer Tayar rc = format_feature(p_hwfn, feature_idx); 7795c965db44STomer Tayar return rc; 7796c965db44STomer Tayar } 7797c965db44STomer Tayar 7798c965db44STomer Tayar int qed_dbg_grc(struct qed_dev *cdev, void *buffer, u32 *num_dumped_bytes) 7799c965db44STomer Tayar { 7800c965db44STomer Tayar return qed_dbg_feature(cdev, buffer, DBG_FEATURE_GRC, num_dumped_bytes); 7801c965db44STomer Tayar } 7802c965db44STomer Tayar 7803c965db44STomer Tayar int qed_dbg_grc_size(struct qed_dev *cdev) 7804c965db44STomer Tayar { 7805c965db44STomer Tayar return qed_dbg_feature_size(cdev, DBG_FEATURE_GRC); 7806c965db44STomer Tayar } 7807c965db44STomer Tayar 7808c965db44STomer Tayar int qed_dbg_idle_chk(struct qed_dev *cdev, void *buffer, u32 *num_dumped_bytes) 7809c965db44STomer Tayar { 7810c965db44STomer Tayar return qed_dbg_feature(cdev, buffer, DBG_FEATURE_IDLE_CHK, 7811c965db44STomer Tayar num_dumped_bytes); 7812c965db44STomer Tayar } 7813c965db44STomer Tayar 7814c965db44STomer Tayar int qed_dbg_idle_chk_size(struct qed_dev *cdev) 7815c965db44STomer Tayar { 7816c965db44STomer Tayar return qed_dbg_feature_size(cdev, DBG_FEATURE_IDLE_CHK); 7817c965db44STomer Tayar } 7818c965db44STomer Tayar 7819c965db44STomer Tayar int qed_dbg_reg_fifo(struct qed_dev *cdev, void *buffer, u32 *num_dumped_bytes) 7820c965db44STomer Tayar { 7821c965db44STomer Tayar return qed_dbg_feature(cdev, buffer, DBG_FEATURE_REG_FIFO, 7822c965db44STomer Tayar num_dumped_bytes); 7823c965db44STomer Tayar } 7824c965db44STomer Tayar 7825c965db44STomer Tayar int qed_dbg_reg_fifo_size(struct qed_dev *cdev) 7826c965db44STomer Tayar { 7827c965db44STomer Tayar return qed_dbg_feature_size(cdev, DBG_FEATURE_REG_FIFO); 7828c965db44STomer Tayar } 7829c965db44STomer Tayar 7830c965db44STomer Tayar int qed_dbg_igu_fifo(struct qed_dev *cdev, void *buffer, u32 *num_dumped_bytes) 7831c965db44STomer Tayar { 7832c965db44STomer Tayar return qed_dbg_feature(cdev, buffer, DBG_FEATURE_IGU_FIFO, 7833c965db44STomer Tayar num_dumped_bytes); 7834c965db44STomer Tayar } 7835c965db44STomer Tayar 7836c965db44STomer Tayar int qed_dbg_igu_fifo_size(struct qed_dev *cdev) 7837c965db44STomer Tayar { 7838c965db44STomer Tayar return qed_dbg_feature_size(cdev, DBG_FEATURE_IGU_FIFO); 7839c965db44STomer Tayar } 7840c965db44STomer Tayar 78411ac4329aSDenis Bolotin int qed_dbg_nvm_image_length(struct qed_hwfn *p_hwfn, 78421ac4329aSDenis Bolotin enum qed_nvm_images image_id, u32 *length) 78431ac4329aSDenis Bolotin { 78441ac4329aSDenis Bolotin struct qed_nvm_image_att image_att; 78451ac4329aSDenis Bolotin int rc; 78461ac4329aSDenis Bolotin 78471ac4329aSDenis Bolotin *length = 0; 78481ac4329aSDenis Bolotin rc = qed_mcp_get_nvm_image_att(p_hwfn, image_id, &image_att); 78491ac4329aSDenis Bolotin if (rc) 78501ac4329aSDenis Bolotin return rc; 78511ac4329aSDenis Bolotin 78521ac4329aSDenis Bolotin *length = image_att.length; 78531ac4329aSDenis Bolotin 78541ac4329aSDenis Bolotin return rc; 78551ac4329aSDenis Bolotin } 78561ac4329aSDenis Bolotin 78571ac4329aSDenis Bolotin int qed_dbg_nvm_image(struct qed_dev *cdev, void *buffer, 78581ac4329aSDenis Bolotin u32 *num_dumped_bytes, enum qed_nvm_images image_id) 78591ac4329aSDenis Bolotin { 78601ac4329aSDenis Bolotin struct qed_hwfn *p_hwfn = 78611ac4329aSDenis Bolotin &cdev->hwfns[cdev->dbg_params.engine_for_debug]; 78621ac4329aSDenis Bolotin u32 len_rounded, i; 78631ac4329aSDenis Bolotin __be32 val; 78641ac4329aSDenis Bolotin int rc; 78651ac4329aSDenis Bolotin 78661ac4329aSDenis Bolotin *num_dumped_bytes = 0; 78671ac4329aSDenis Bolotin rc = qed_dbg_nvm_image_length(p_hwfn, image_id, &len_rounded); 78681ac4329aSDenis Bolotin if (rc) 78691ac4329aSDenis Bolotin return rc; 78701ac4329aSDenis Bolotin 78711ac4329aSDenis Bolotin DP_NOTICE(p_hwfn->cdev, 78721ac4329aSDenis Bolotin "Collecting a debug feature [\"nvram image %d\"]\n", 78731ac4329aSDenis Bolotin image_id); 78741ac4329aSDenis Bolotin 78751ac4329aSDenis Bolotin len_rounded = roundup(len_rounded, sizeof(u32)); 78761ac4329aSDenis Bolotin rc = qed_mcp_get_nvm_image(p_hwfn, image_id, buffer, len_rounded); 78771ac4329aSDenis Bolotin if (rc) 78781ac4329aSDenis Bolotin return rc; 78791ac4329aSDenis Bolotin 78801ac4329aSDenis Bolotin /* QED_NVM_IMAGE_NVM_META image is not swapped like other images */ 78811ac4329aSDenis Bolotin if (image_id != QED_NVM_IMAGE_NVM_META) 78821ac4329aSDenis Bolotin for (i = 0; i < len_rounded; i += 4) { 78831ac4329aSDenis Bolotin val = cpu_to_be32(*(u32 *)(buffer + i)); 78841ac4329aSDenis Bolotin *(u32 *)(buffer + i) = val; 78851ac4329aSDenis Bolotin } 78861ac4329aSDenis Bolotin 78871ac4329aSDenis Bolotin *num_dumped_bytes = len_rounded; 78881ac4329aSDenis Bolotin 78891ac4329aSDenis Bolotin return rc; 78901ac4329aSDenis Bolotin } 78911ac4329aSDenis Bolotin 7892c965db44STomer Tayar int qed_dbg_protection_override(struct qed_dev *cdev, void *buffer, 7893c965db44STomer Tayar u32 *num_dumped_bytes) 7894c965db44STomer Tayar { 7895c965db44STomer Tayar return qed_dbg_feature(cdev, buffer, DBG_FEATURE_PROTECTION_OVERRIDE, 7896c965db44STomer Tayar num_dumped_bytes); 7897c965db44STomer Tayar } 7898c965db44STomer Tayar 7899c965db44STomer Tayar int qed_dbg_protection_override_size(struct qed_dev *cdev) 7900c965db44STomer Tayar { 7901c965db44STomer Tayar return qed_dbg_feature_size(cdev, DBG_FEATURE_PROTECTION_OVERRIDE); 7902c965db44STomer Tayar } 7903c965db44STomer Tayar 7904c965db44STomer Tayar int qed_dbg_fw_asserts(struct qed_dev *cdev, void *buffer, 7905c965db44STomer Tayar u32 *num_dumped_bytes) 7906c965db44STomer Tayar { 7907c965db44STomer Tayar return qed_dbg_feature(cdev, buffer, DBG_FEATURE_FW_ASSERTS, 7908c965db44STomer Tayar num_dumped_bytes); 7909c965db44STomer Tayar } 7910c965db44STomer Tayar 7911c965db44STomer Tayar int qed_dbg_fw_asserts_size(struct qed_dev *cdev) 7912c965db44STomer Tayar { 7913c965db44STomer Tayar return qed_dbg_feature_size(cdev, DBG_FEATURE_FW_ASSERTS); 7914c965db44STomer Tayar } 7915c965db44STomer Tayar 7916c965db44STomer Tayar int qed_dbg_mcp_trace(struct qed_dev *cdev, void *buffer, 7917c965db44STomer Tayar u32 *num_dumped_bytes) 7918c965db44STomer Tayar { 7919c965db44STomer Tayar return qed_dbg_feature(cdev, buffer, DBG_FEATURE_MCP_TRACE, 7920c965db44STomer Tayar num_dumped_bytes); 7921c965db44STomer Tayar } 7922c965db44STomer Tayar 7923c965db44STomer Tayar int qed_dbg_mcp_trace_size(struct qed_dev *cdev) 7924c965db44STomer Tayar { 7925c965db44STomer Tayar return qed_dbg_feature_size(cdev, DBG_FEATURE_MCP_TRACE); 7926c965db44STomer Tayar } 7927c965db44STomer Tayar 7928c965db44STomer Tayar /* Defines the amount of bytes allocated for recording the length of debugfs 7929c965db44STomer Tayar * feature buffer. 7930c965db44STomer Tayar */ 7931c965db44STomer Tayar #define REGDUMP_HEADER_SIZE sizeof(u32) 7932c965db44STomer Tayar #define REGDUMP_HEADER_FEATURE_SHIFT 24 7933c965db44STomer Tayar #define REGDUMP_HEADER_ENGINE_SHIFT 31 7934c965db44STomer Tayar #define REGDUMP_HEADER_OMIT_ENGINE_SHIFT 30 7935c965db44STomer Tayar enum debug_print_features { 7936c965db44STomer Tayar OLD_MODE = 0, 7937c965db44STomer Tayar IDLE_CHK = 1, 7938c965db44STomer Tayar GRC_DUMP = 2, 7939c965db44STomer Tayar MCP_TRACE = 3, 7940c965db44STomer Tayar REG_FIFO = 4, 7941c965db44STomer Tayar PROTECTION_OVERRIDE = 5, 7942c965db44STomer Tayar IGU_FIFO = 6, 7943c965db44STomer Tayar PHY = 7, 7944c965db44STomer Tayar FW_ASSERTS = 8, 79451ac4329aSDenis Bolotin NVM_CFG1 = 9, 79461ac4329aSDenis Bolotin DEFAULT_CFG = 10, 79471ac4329aSDenis Bolotin NVM_META = 11, 7948c965db44STomer Tayar }; 7949c965db44STomer Tayar 7950c965db44STomer Tayar static u32 qed_calc_regdump_header(enum debug_print_features feature, 7951c965db44STomer Tayar int engine, u32 feature_size, u8 omit_engine) 7952c965db44STomer Tayar { 7953c965db44STomer Tayar /* Insert the engine, feature and mode inside the header and combine it 7954c965db44STomer Tayar * with feature size. 7955c965db44STomer Tayar */ 7956c965db44STomer Tayar return feature_size | (feature << REGDUMP_HEADER_FEATURE_SHIFT) | 7957c965db44STomer Tayar (omit_engine << REGDUMP_HEADER_OMIT_ENGINE_SHIFT) | 7958c965db44STomer Tayar (engine << REGDUMP_HEADER_ENGINE_SHIFT); 7959c965db44STomer Tayar } 7960c965db44STomer Tayar 7961c965db44STomer Tayar int qed_dbg_all_data(struct qed_dev *cdev, void *buffer) 7962c965db44STomer Tayar { 7963c965db44STomer Tayar u8 cur_engine, omit_engine = 0, org_engine; 7964c965db44STomer Tayar u32 offset = 0, feature_size; 7965c965db44STomer Tayar int rc; 7966c965db44STomer Tayar 7967c965db44STomer Tayar if (cdev->num_hwfns == 1) 7968c965db44STomer Tayar omit_engine = 1; 7969c965db44STomer Tayar 7970c965db44STomer Tayar org_engine = qed_get_debug_engine(cdev); 7971c965db44STomer Tayar for (cur_engine = 0; cur_engine < cdev->num_hwfns; cur_engine++) { 7972c965db44STomer Tayar /* Collect idle_chks and grcDump for each hw function */ 7973c965db44STomer Tayar DP_VERBOSE(cdev, QED_MSG_DEBUG, 7974c965db44STomer Tayar "obtaining idle_chk and grcdump for current engine\n"); 7975c965db44STomer Tayar qed_set_debug_engine(cdev, cur_engine); 7976c965db44STomer Tayar 7977c965db44STomer Tayar /* First idle_chk */ 7978c965db44STomer Tayar rc = qed_dbg_idle_chk(cdev, (u8 *)buffer + offset + 7979c965db44STomer Tayar REGDUMP_HEADER_SIZE, &feature_size); 7980c965db44STomer Tayar if (!rc) { 7981c965db44STomer Tayar *(u32 *)((u8 *)buffer + offset) = 7982c965db44STomer Tayar qed_calc_regdump_header(IDLE_CHK, cur_engine, 7983c965db44STomer Tayar feature_size, omit_engine); 7984c965db44STomer Tayar offset += (feature_size + REGDUMP_HEADER_SIZE); 7985c965db44STomer Tayar } else { 7986c965db44STomer Tayar DP_ERR(cdev, "qed_dbg_idle_chk failed. rc = %d\n", rc); 7987c965db44STomer Tayar } 7988c965db44STomer Tayar 7989c965db44STomer Tayar /* Second idle_chk */ 7990c965db44STomer Tayar rc = qed_dbg_idle_chk(cdev, (u8 *)buffer + offset + 7991c965db44STomer Tayar REGDUMP_HEADER_SIZE, &feature_size); 7992c965db44STomer Tayar if (!rc) { 7993c965db44STomer Tayar *(u32 *)((u8 *)buffer + offset) = 7994c965db44STomer Tayar qed_calc_regdump_header(IDLE_CHK, cur_engine, 7995c965db44STomer Tayar feature_size, omit_engine); 7996c965db44STomer Tayar offset += (feature_size + REGDUMP_HEADER_SIZE); 7997c965db44STomer Tayar } else { 7998c965db44STomer Tayar DP_ERR(cdev, "qed_dbg_idle_chk failed. rc = %d\n", rc); 7999c965db44STomer Tayar } 8000c965db44STomer Tayar 8001c965db44STomer Tayar /* reg_fifo dump */ 8002c965db44STomer Tayar rc = qed_dbg_reg_fifo(cdev, (u8 *)buffer + offset + 8003c965db44STomer Tayar REGDUMP_HEADER_SIZE, &feature_size); 8004c965db44STomer Tayar if (!rc) { 8005c965db44STomer Tayar *(u32 *)((u8 *)buffer + offset) = 8006c965db44STomer Tayar qed_calc_regdump_header(REG_FIFO, cur_engine, 8007c965db44STomer Tayar feature_size, omit_engine); 8008c965db44STomer Tayar offset += (feature_size + REGDUMP_HEADER_SIZE); 8009c965db44STomer Tayar } else { 8010c965db44STomer Tayar DP_ERR(cdev, "qed_dbg_reg_fifo failed. rc = %d\n", rc); 8011c965db44STomer Tayar } 8012c965db44STomer Tayar 8013c965db44STomer Tayar /* igu_fifo dump */ 8014c965db44STomer Tayar rc = qed_dbg_igu_fifo(cdev, (u8 *)buffer + offset + 8015c965db44STomer Tayar REGDUMP_HEADER_SIZE, &feature_size); 8016c965db44STomer Tayar if (!rc) { 8017c965db44STomer Tayar *(u32 *)((u8 *)buffer + offset) = 8018c965db44STomer Tayar qed_calc_regdump_header(IGU_FIFO, cur_engine, 8019c965db44STomer Tayar feature_size, omit_engine); 8020c965db44STomer Tayar offset += (feature_size + REGDUMP_HEADER_SIZE); 8021c965db44STomer Tayar } else { 8022c965db44STomer Tayar DP_ERR(cdev, "qed_dbg_igu_fifo failed. rc = %d", rc); 8023c965db44STomer Tayar } 8024c965db44STomer Tayar 8025c965db44STomer Tayar /* protection_override dump */ 8026c965db44STomer Tayar rc = qed_dbg_protection_override(cdev, (u8 *)buffer + offset + 8027c965db44STomer Tayar REGDUMP_HEADER_SIZE, 8028c965db44STomer Tayar &feature_size); 8029c965db44STomer Tayar if (!rc) { 8030c965db44STomer Tayar *(u32 *)((u8 *)buffer + offset) = 8031c965db44STomer Tayar qed_calc_regdump_header(PROTECTION_OVERRIDE, 8032c965db44STomer Tayar cur_engine, 8033c965db44STomer Tayar feature_size, omit_engine); 8034c965db44STomer Tayar offset += (feature_size + REGDUMP_HEADER_SIZE); 8035c965db44STomer Tayar } else { 8036c965db44STomer Tayar DP_ERR(cdev, 8037c965db44STomer Tayar "qed_dbg_protection_override failed. rc = %d\n", 8038c965db44STomer Tayar rc); 8039c965db44STomer Tayar } 8040c965db44STomer Tayar 8041c965db44STomer Tayar /* fw_asserts dump */ 8042c965db44STomer Tayar rc = qed_dbg_fw_asserts(cdev, (u8 *)buffer + offset + 8043c965db44STomer Tayar REGDUMP_HEADER_SIZE, &feature_size); 8044c965db44STomer Tayar if (!rc) { 8045c965db44STomer Tayar *(u32 *)((u8 *)buffer + offset) = 8046c965db44STomer Tayar qed_calc_regdump_header(FW_ASSERTS, cur_engine, 8047c965db44STomer Tayar feature_size, omit_engine); 8048c965db44STomer Tayar offset += (feature_size + REGDUMP_HEADER_SIZE); 8049c965db44STomer Tayar } else { 8050c965db44STomer Tayar DP_ERR(cdev, "qed_dbg_fw_asserts failed. rc = %d\n", 8051c965db44STomer Tayar rc); 8052c965db44STomer Tayar } 8053c965db44STomer Tayar 8054c965db44STomer Tayar /* GRC dump - must be last because when mcp stuck it will 8055c965db44STomer Tayar * clutter idle_chk, reg_fifo, ... 8056c965db44STomer Tayar */ 8057c965db44STomer Tayar rc = qed_dbg_grc(cdev, (u8 *)buffer + offset + 8058c965db44STomer Tayar REGDUMP_HEADER_SIZE, &feature_size); 8059c965db44STomer Tayar if (!rc) { 8060c965db44STomer Tayar *(u32 *)((u8 *)buffer + offset) = 8061c965db44STomer Tayar qed_calc_regdump_header(GRC_DUMP, cur_engine, 8062c965db44STomer Tayar feature_size, omit_engine); 8063c965db44STomer Tayar offset += (feature_size + REGDUMP_HEADER_SIZE); 8064c965db44STomer Tayar } else { 8065c965db44STomer Tayar DP_ERR(cdev, "qed_dbg_grc failed. rc = %d", rc); 8066c965db44STomer Tayar } 8067c965db44STomer Tayar } 8068c965db44STomer Tayar 806950bc60cbSMichal Kalderon qed_set_debug_engine(cdev, org_engine); 8070c965db44STomer Tayar /* mcp_trace */ 8071c965db44STomer Tayar rc = qed_dbg_mcp_trace(cdev, (u8 *)buffer + offset + 8072c965db44STomer Tayar REGDUMP_HEADER_SIZE, &feature_size); 8073c965db44STomer Tayar if (!rc) { 8074c965db44STomer Tayar *(u32 *)((u8 *)buffer + offset) = 8075c965db44STomer Tayar qed_calc_regdump_header(MCP_TRACE, cur_engine, 8076c965db44STomer Tayar feature_size, omit_engine); 8077c965db44STomer Tayar offset += (feature_size + REGDUMP_HEADER_SIZE); 8078c965db44STomer Tayar } else { 8079c965db44STomer Tayar DP_ERR(cdev, "qed_dbg_mcp_trace failed. rc = %d\n", rc); 8080c965db44STomer Tayar } 8081c965db44STomer Tayar 80821ac4329aSDenis Bolotin /* nvm cfg1 */ 80831ac4329aSDenis Bolotin rc = qed_dbg_nvm_image(cdev, 80841ac4329aSDenis Bolotin (u8 *)buffer + offset + REGDUMP_HEADER_SIZE, 80851ac4329aSDenis Bolotin &feature_size, QED_NVM_IMAGE_NVM_CFG1); 80861ac4329aSDenis Bolotin if (!rc) { 80871ac4329aSDenis Bolotin *(u32 *)((u8 *)buffer + offset) = 80881ac4329aSDenis Bolotin qed_calc_regdump_header(NVM_CFG1, cur_engine, 80891ac4329aSDenis Bolotin feature_size, omit_engine); 80901ac4329aSDenis Bolotin offset += (feature_size + REGDUMP_HEADER_SIZE); 80911ac4329aSDenis Bolotin } else if (rc != -ENOENT) { 80921ac4329aSDenis Bolotin DP_ERR(cdev, 80931ac4329aSDenis Bolotin "qed_dbg_nvm_image failed for image %d (%s), rc = %d\n", 80941ac4329aSDenis Bolotin QED_NVM_IMAGE_NVM_CFG1, "QED_NVM_IMAGE_NVM_CFG1", rc); 80951ac4329aSDenis Bolotin } 80961ac4329aSDenis Bolotin 80971ac4329aSDenis Bolotin /* nvm default */ 80981ac4329aSDenis Bolotin rc = qed_dbg_nvm_image(cdev, 80991ac4329aSDenis Bolotin (u8 *)buffer + offset + REGDUMP_HEADER_SIZE, 81001ac4329aSDenis Bolotin &feature_size, QED_NVM_IMAGE_DEFAULT_CFG); 81011ac4329aSDenis Bolotin if (!rc) { 81021ac4329aSDenis Bolotin *(u32 *)((u8 *)buffer + offset) = 81031ac4329aSDenis Bolotin qed_calc_regdump_header(DEFAULT_CFG, cur_engine, 81041ac4329aSDenis Bolotin feature_size, omit_engine); 81051ac4329aSDenis Bolotin offset += (feature_size + REGDUMP_HEADER_SIZE); 81061ac4329aSDenis Bolotin } else if (rc != -ENOENT) { 81071ac4329aSDenis Bolotin DP_ERR(cdev, 81081ac4329aSDenis Bolotin "qed_dbg_nvm_image failed for image %d (%s), rc = %d\n", 81091ac4329aSDenis Bolotin QED_NVM_IMAGE_DEFAULT_CFG, "QED_NVM_IMAGE_DEFAULT_CFG", 81101ac4329aSDenis Bolotin rc); 81111ac4329aSDenis Bolotin } 81121ac4329aSDenis Bolotin 81131ac4329aSDenis Bolotin /* nvm meta */ 81141ac4329aSDenis Bolotin rc = qed_dbg_nvm_image(cdev, 81151ac4329aSDenis Bolotin (u8 *)buffer + offset + REGDUMP_HEADER_SIZE, 81161ac4329aSDenis Bolotin &feature_size, QED_NVM_IMAGE_NVM_META); 81171ac4329aSDenis Bolotin if (!rc) { 81181ac4329aSDenis Bolotin *(u32 *)((u8 *)buffer + offset) = 81191ac4329aSDenis Bolotin qed_calc_regdump_header(NVM_META, cur_engine, 81201ac4329aSDenis Bolotin feature_size, omit_engine); 81211ac4329aSDenis Bolotin offset += (feature_size + REGDUMP_HEADER_SIZE); 81221ac4329aSDenis Bolotin } else if (rc != -ENOENT) { 81231ac4329aSDenis Bolotin DP_ERR(cdev, 81241ac4329aSDenis Bolotin "qed_dbg_nvm_image failed for image %d (%s), rc = %d\n", 81251ac4329aSDenis Bolotin QED_NVM_IMAGE_NVM_META, "QED_NVM_IMAGE_NVM_META", rc); 81261ac4329aSDenis Bolotin } 81271ac4329aSDenis Bolotin 8128c965db44STomer Tayar return 0; 8129c965db44STomer Tayar } 8130c965db44STomer Tayar 8131c965db44STomer Tayar int qed_dbg_all_data_size(struct qed_dev *cdev) 8132c965db44STomer Tayar { 81331ac4329aSDenis Bolotin struct qed_hwfn *p_hwfn = 81341ac4329aSDenis Bolotin &cdev->hwfns[cdev->dbg_params.engine_for_debug]; 81351ac4329aSDenis Bolotin u32 regs_len = 0, image_len = 0; 8136c965db44STomer Tayar u8 cur_engine, org_engine; 8137c965db44STomer Tayar 8138c965db44STomer Tayar org_engine = qed_get_debug_engine(cdev); 8139c965db44STomer Tayar for (cur_engine = 0; cur_engine < cdev->num_hwfns; cur_engine++) { 8140c965db44STomer Tayar /* Engine specific */ 8141c965db44STomer Tayar DP_VERBOSE(cdev, QED_MSG_DEBUG, 8142c965db44STomer Tayar "calculating idle_chk and grcdump register length for current engine\n"); 8143c965db44STomer Tayar qed_set_debug_engine(cdev, cur_engine); 8144c965db44STomer Tayar regs_len += REGDUMP_HEADER_SIZE + qed_dbg_idle_chk_size(cdev) + 8145c965db44STomer Tayar REGDUMP_HEADER_SIZE + qed_dbg_idle_chk_size(cdev) + 8146c965db44STomer Tayar REGDUMP_HEADER_SIZE + qed_dbg_grc_size(cdev) + 8147c965db44STomer Tayar REGDUMP_HEADER_SIZE + qed_dbg_reg_fifo_size(cdev) + 8148c965db44STomer Tayar REGDUMP_HEADER_SIZE + qed_dbg_igu_fifo_size(cdev) + 8149c965db44STomer Tayar REGDUMP_HEADER_SIZE + 8150c965db44STomer Tayar qed_dbg_protection_override_size(cdev) + 8151c965db44STomer Tayar REGDUMP_HEADER_SIZE + qed_dbg_fw_asserts_size(cdev); 8152c965db44STomer Tayar } 8153c965db44STomer Tayar 815450bc60cbSMichal Kalderon qed_set_debug_engine(cdev, org_engine); 815550bc60cbSMichal Kalderon 8156c965db44STomer Tayar /* Engine common */ 8157c965db44STomer Tayar regs_len += REGDUMP_HEADER_SIZE + qed_dbg_mcp_trace_size(cdev); 81581ac4329aSDenis Bolotin qed_dbg_nvm_image_length(p_hwfn, QED_NVM_IMAGE_NVM_CFG1, &image_len); 81591ac4329aSDenis Bolotin if (image_len) 81601ac4329aSDenis Bolotin regs_len += REGDUMP_HEADER_SIZE + image_len; 81611ac4329aSDenis Bolotin qed_dbg_nvm_image_length(p_hwfn, QED_NVM_IMAGE_DEFAULT_CFG, &image_len); 81621ac4329aSDenis Bolotin if (image_len) 81631ac4329aSDenis Bolotin regs_len += REGDUMP_HEADER_SIZE + image_len; 81641ac4329aSDenis Bolotin qed_dbg_nvm_image_length(p_hwfn, QED_NVM_IMAGE_NVM_META, &image_len); 81651ac4329aSDenis Bolotin if (image_len) 81661ac4329aSDenis Bolotin regs_len += REGDUMP_HEADER_SIZE + image_len; 8167c965db44STomer Tayar 8168c965db44STomer Tayar return regs_len; 8169c965db44STomer Tayar } 8170c965db44STomer Tayar 8171c965db44STomer Tayar int qed_dbg_feature(struct qed_dev *cdev, void *buffer, 8172c965db44STomer Tayar enum qed_dbg_features feature, u32 *num_dumped_bytes) 8173c965db44STomer Tayar { 8174c965db44STomer Tayar struct qed_hwfn *p_hwfn = 8175c965db44STomer Tayar &cdev->hwfns[cdev->dbg_params.engine_for_debug]; 8176c965db44STomer Tayar struct qed_dbg_feature *qed_feature = 8177c965db44STomer Tayar &cdev->dbg_params.features[feature]; 8178c965db44STomer Tayar enum dbg_status dbg_rc; 8179c965db44STomer Tayar struct qed_ptt *p_ptt; 8180c965db44STomer Tayar int rc = 0; 8181c965db44STomer Tayar 8182c965db44STomer Tayar /* Acquire ptt */ 8183c965db44STomer Tayar p_ptt = qed_ptt_acquire(p_hwfn); 8184c965db44STomer Tayar if (!p_ptt) 8185c965db44STomer Tayar return -EINVAL; 8186c965db44STomer Tayar 8187c965db44STomer Tayar /* Get dump */ 8188c965db44STomer Tayar dbg_rc = qed_dbg_dump(p_hwfn, p_ptt, feature); 8189c965db44STomer Tayar if (dbg_rc != DBG_STATUS_OK) { 8190c965db44STomer Tayar DP_VERBOSE(cdev, QED_MSG_DEBUG, "%s\n", 8191c965db44STomer Tayar qed_dbg_get_status_str(dbg_rc)); 8192c965db44STomer Tayar *num_dumped_bytes = 0; 8193c965db44STomer Tayar rc = -EINVAL; 8194c965db44STomer Tayar goto out; 8195c965db44STomer Tayar } 8196c965db44STomer Tayar 8197c965db44STomer Tayar DP_VERBOSE(cdev, QED_MSG_DEBUG, 8198c965db44STomer Tayar "copying debugfs feature to external buffer\n"); 8199c965db44STomer Tayar memcpy(buffer, qed_feature->dump_buf, qed_feature->buf_size); 8200c965db44STomer Tayar *num_dumped_bytes = cdev->dbg_params.features[feature].dumped_dwords * 8201c965db44STomer Tayar 4; 8202c965db44STomer Tayar 8203c965db44STomer Tayar out: 8204c965db44STomer Tayar qed_ptt_release(p_hwfn, p_ptt); 8205c965db44STomer Tayar return rc; 8206c965db44STomer Tayar } 8207c965db44STomer Tayar 8208c965db44STomer Tayar int qed_dbg_feature_size(struct qed_dev *cdev, enum qed_dbg_features feature) 8209c965db44STomer Tayar { 8210c965db44STomer Tayar struct qed_hwfn *p_hwfn = 8211c965db44STomer Tayar &cdev->hwfns[cdev->dbg_params.engine_for_debug]; 8212c965db44STomer Tayar struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn); 8213c965db44STomer Tayar struct qed_dbg_feature *qed_feature = 8214c965db44STomer Tayar &cdev->dbg_params.features[feature]; 8215c965db44STomer Tayar u32 buf_size_dwords; 8216c965db44STomer Tayar enum dbg_status rc; 8217c965db44STomer Tayar 8218c965db44STomer Tayar if (!p_ptt) 8219c965db44STomer Tayar return -EINVAL; 8220c965db44STomer Tayar 8221c965db44STomer Tayar rc = qed_features_lookup[feature].get_size(p_hwfn, p_ptt, 8222c965db44STomer Tayar &buf_size_dwords); 8223c965db44STomer Tayar if (rc != DBG_STATUS_OK) 8224c965db44STomer Tayar buf_size_dwords = 0; 8225c965db44STomer Tayar 8226c965db44STomer Tayar qed_ptt_release(p_hwfn, p_ptt); 8227c965db44STomer Tayar qed_feature->buf_size = buf_size_dwords * sizeof(u32); 8228c965db44STomer Tayar return qed_feature->buf_size; 8229c965db44STomer Tayar } 8230c965db44STomer Tayar 8231c965db44STomer Tayar u8 qed_get_debug_engine(struct qed_dev *cdev) 8232c965db44STomer Tayar { 8233c965db44STomer Tayar return cdev->dbg_params.engine_for_debug; 8234c965db44STomer Tayar } 8235c965db44STomer Tayar 8236c965db44STomer Tayar void qed_set_debug_engine(struct qed_dev *cdev, int engine_number) 8237c965db44STomer Tayar { 8238c965db44STomer Tayar DP_VERBOSE(cdev, QED_MSG_DEBUG, "set debug engine to %d\n", 8239c965db44STomer Tayar engine_number); 8240c965db44STomer Tayar cdev->dbg_params.engine_for_debug = engine_number; 8241c965db44STomer Tayar } 8242c965db44STomer Tayar 8243c965db44STomer Tayar void qed_dbg_pf_init(struct qed_dev *cdev) 8244c965db44STomer Tayar { 8245c965db44STomer Tayar const u8 *dbg_values; 8246c965db44STomer Tayar 8247c965db44STomer Tayar /* Debug values are after init values. 8248c965db44STomer Tayar * The offset is the first dword of the file. 8249c965db44STomer Tayar */ 8250c965db44STomer Tayar dbg_values = cdev->firmware->data + *(u32 *)cdev->firmware->data; 8251c965db44STomer Tayar qed_dbg_set_bin_ptr((u8 *)dbg_values); 8252c965db44STomer Tayar qed_dbg_user_set_bin_ptr((u8 *)dbg_values); 8253c965db44STomer Tayar } 8254c965db44STomer Tayar 8255c965db44STomer Tayar void qed_dbg_pf_exit(struct qed_dev *cdev) 8256c965db44STomer Tayar { 8257c965db44STomer Tayar struct qed_dbg_feature *feature = NULL; 8258c965db44STomer Tayar enum qed_dbg_features feature_idx; 8259c965db44STomer Tayar 8260c965db44STomer Tayar /* Debug features' buffers may be allocated if debug feature was used 8261c965db44STomer Tayar * but dump wasn't called. 8262c965db44STomer Tayar */ 8263c965db44STomer Tayar for (feature_idx = 0; feature_idx < DBG_FEATURE_NUM; feature_idx++) { 8264c965db44STomer Tayar feature = &cdev->dbg_params.features[feature_idx]; 8265c965db44STomer Tayar if (feature->dump_buf) { 8266c965db44STomer Tayar vfree(feature->dump_buf); 8267c965db44STomer Tayar feature->dump_buf = NULL; 8268c965db44STomer Tayar } 8269c965db44STomer Tayar } 8270c965db44STomer Tayar } 8271