13287e96aSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2c965db44STomer Tayar /* QLogic qed NIC Driver 3c965db44STomer Tayar * Copyright (c) 2015 QLogic Corporation 4c965db44STomer Tayar */ 5c965db44STomer Tayar 6c965db44STomer Tayar #include <linux/module.h> 7c965db44STomer Tayar #include <linux/vmalloc.h> 8c965db44STomer Tayar #include <linux/crc32.h> 9c965db44STomer Tayar #include "qed.h" 10c965db44STomer Tayar #include "qed_hsi.h" 11c965db44STomer Tayar #include "qed_hw.h" 12c965db44STomer Tayar #include "qed_mcp.h" 13c965db44STomer Tayar #include "qed_reg_addr.h" 14c965db44STomer Tayar 15c965db44STomer Tayar /* Memory groups enum */ 16c965db44STomer Tayar enum mem_groups { 17c965db44STomer Tayar MEM_GROUP_PXP_MEM, 18c965db44STomer Tayar MEM_GROUP_DMAE_MEM, 19c965db44STomer Tayar MEM_GROUP_CM_MEM, 20c965db44STomer Tayar MEM_GROUP_QM_MEM, 21da090917STomer Tayar MEM_GROUP_DORQ_MEM, 22c965db44STomer Tayar MEM_GROUP_BRB_RAM, 23c965db44STomer Tayar MEM_GROUP_BRB_MEM, 24c965db44STomer Tayar MEM_GROUP_PRS_MEM, 25c965db44STomer Tayar MEM_GROUP_IOR, 26c965db44STomer Tayar MEM_GROUP_BTB_RAM, 27c965db44STomer Tayar MEM_GROUP_CONN_CFC_MEM, 28c965db44STomer Tayar MEM_GROUP_TASK_CFC_MEM, 29c965db44STomer Tayar MEM_GROUP_CAU_PI, 30c965db44STomer Tayar MEM_GROUP_CAU_MEM, 31c965db44STomer Tayar MEM_GROUP_PXP_ILT, 32da090917STomer Tayar MEM_GROUP_TM_MEM, 33da090917STomer Tayar MEM_GROUP_SDM_MEM, 347b6859fbSMintz, Yuval MEM_GROUP_PBUF, 35da090917STomer Tayar MEM_GROUP_RAM, 36c965db44STomer Tayar MEM_GROUP_MULD_MEM, 37c965db44STomer Tayar MEM_GROUP_BTB_MEM, 38da090917STomer Tayar MEM_GROUP_RDIF_CTX, 39da090917STomer Tayar MEM_GROUP_TDIF_CTX, 40da090917STomer Tayar MEM_GROUP_CFC_MEM, 41c965db44STomer Tayar MEM_GROUP_IGU_MEM, 42c965db44STomer Tayar MEM_GROUP_IGU_MSIX, 43c965db44STomer Tayar MEM_GROUP_CAU_SB, 44c965db44STomer Tayar MEM_GROUP_BMB_RAM, 45c965db44STomer Tayar MEM_GROUP_BMB_MEM, 46c965db44STomer Tayar MEM_GROUPS_NUM 47c965db44STomer Tayar }; 48c965db44STomer Tayar 49c965db44STomer Tayar /* Memory groups names */ 50c965db44STomer Tayar static const char * const s_mem_group_names[] = { 51c965db44STomer Tayar "PXP_MEM", 52c965db44STomer Tayar "DMAE_MEM", 53c965db44STomer Tayar "CM_MEM", 54c965db44STomer Tayar "QM_MEM", 55da090917STomer Tayar "DORQ_MEM", 56c965db44STomer Tayar "BRB_RAM", 57c965db44STomer Tayar "BRB_MEM", 58c965db44STomer Tayar "PRS_MEM", 59c965db44STomer Tayar "IOR", 60c965db44STomer Tayar "BTB_RAM", 61c965db44STomer Tayar "CONN_CFC_MEM", 62c965db44STomer Tayar "TASK_CFC_MEM", 63c965db44STomer Tayar "CAU_PI", 64c965db44STomer Tayar "CAU_MEM", 65c965db44STomer Tayar "PXP_ILT", 66da090917STomer Tayar "TM_MEM", 67da090917STomer Tayar "SDM_MEM", 687b6859fbSMintz, Yuval "PBUF", 69da090917STomer Tayar "RAM", 70c965db44STomer Tayar "MULD_MEM", 71c965db44STomer Tayar "BTB_MEM", 72da090917STomer Tayar "RDIF_CTX", 73da090917STomer Tayar "TDIF_CTX", 74da090917STomer Tayar "CFC_MEM", 75c965db44STomer Tayar "IGU_MEM", 76c965db44STomer Tayar "IGU_MSIX", 77c965db44STomer Tayar "CAU_SB", 78c965db44STomer Tayar "BMB_RAM", 79c965db44STomer Tayar "BMB_MEM", 80c965db44STomer Tayar }; 81c965db44STomer Tayar 82c965db44STomer Tayar /* Idle check conditions */ 837b6859fbSMintz, Yuval 847b6859fbSMintz, Yuval static u32 cond5(const u32 *r, const u32 *imm) 85c965db44STomer Tayar { 86c965db44STomer Tayar return ((r[0] & imm[0]) != imm[1]) && ((r[1] & imm[2]) != imm[3]); 87c965db44STomer Tayar } 88c965db44STomer Tayar 897b6859fbSMintz, Yuval static u32 cond7(const u32 *r, const u32 *imm) 90c965db44STomer Tayar { 91c965db44STomer Tayar return ((r[0] >> imm[0]) & imm[1]) != imm[2]; 92c965db44STomer Tayar } 93c965db44STomer Tayar 947b6859fbSMintz, Yuval static u32 cond6(const u32 *r, const u32 *imm) 95c965db44STomer Tayar { 96c965db44STomer Tayar return (r[0] & imm[0]) != imm[1]; 97c965db44STomer Tayar } 98c965db44STomer Tayar 997b6859fbSMintz, Yuval static u32 cond9(const u32 *r, const u32 *imm) 100c965db44STomer Tayar { 101c965db44STomer Tayar return ((r[0] & imm[0]) >> imm[1]) != 102c965db44STomer Tayar (((r[0] & imm[2]) >> imm[3]) | ((r[1] & imm[4]) << imm[5])); 103c965db44STomer Tayar } 104c965db44STomer Tayar 1057b6859fbSMintz, Yuval static u32 cond10(const u32 *r, const u32 *imm) 106c965db44STomer Tayar { 107c965db44STomer Tayar return ((r[0] & imm[0]) >> imm[1]) != (r[0] & imm[2]); 108c965db44STomer Tayar } 109c965db44STomer Tayar 1107b6859fbSMintz, Yuval static u32 cond4(const u32 *r, const u32 *imm) 111c965db44STomer Tayar { 112c965db44STomer Tayar return (r[0] & ~imm[0]) != imm[1]; 113c965db44STomer Tayar } 114c965db44STomer Tayar 115c965db44STomer Tayar static u32 cond0(const u32 *r, const u32 *imm) 116c965db44STomer Tayar { 1177b6859fbSMintz, Yuval return (r[0] & ~r[1]) != imm[0]; 1187b6859fbSMintz, Yuval } 1197b6859fbSMintz, Yuval 1207b6859fbSMintz, Yuval static u32 cond1(const u32 *r, const u32 *imm) 1217b6859fbSMintz, Yuval { 122c965db44STomer Tayar return r[0] != imm[0]; 123c965db44STomer Tayar } 124c965db44STomer Tayar 1257b6859fbSMintz, Yuval static u32 cond11(const u32 *r, const u32 *imm) 126c965db44STomer Tayar { 127c965db44STomer Tayar return r[0] != r[1] && r[2] == imm[0]; 128c965db44STomer Tayar } 129c965db44STomer Tayar 1307b6859fbSMintz, Yuval static u32 cond12(const u32 *r, const u32 *imm) 131c965db44STomer Tayar { 132c965db44STomer Tayar return r[0] != r[1] && r[2] > imm[0]; 133c965db44STomer Tayar } 134c965db44STomer Tayar 135c965db44STomer Tayar static u32 cond3(const u32 *r, const u32 *imm) 136c965db44STomer Tayar { 137c965db44STomer Tayar return r[0] != r[1]; 138c965db44STomer Tayar } 139c965db44STomer Tayar 1407b6859fbSMintz, Yuval static u32 cond13(const u32 *r, const u32 *imm) 141c965db44STomer Tayar { 142c965db44STomer Tayar return r[0] & imm[0]; 143c965db44STomer Tayar } 144c965db44STomer Tayar 1457b6859fbSMintz, Yuval static u32 cond8(const u32 *r, const u32 *imm) 146c965db44STomer Tayar { 147c965db44STomer Tayar return r[0] < (r[1] - imm[0]); 148c965db44STomer Tayar } 149c965db44STomer Tayar 150c965db44STomer Tayar static u32 cond2(const u32 *r, const u32 *imm) 151c965db44STomer Tayar { 152c965db44STomer Tayar return r[0] > imm[0]; 153c965db44STomer Tayar } 154c965db44STomer Tayar 155c965db44STomer Tayar /* Array of Idle Check conditions */ 156c965db44STomer Tayar static u32(*cond_arr[]) (const u32 *r, const u32 *imm) = { 157c965db44STomer Tayar cond0, 158c965db44STomer Tayar cond1, 159c965db44STomer Tayar cond2, 160c965db44STomer Tayar cond3, 161c965db44STomer Tayar cond4, 162c965db44STomer Tayar cond5, 163c965db44STomer Tayar cond6, 164c965db44STomer Tayar cond7, 165c965db44STomer Tayar cond8, 166c965db44STomer Tayar cond9, 167c965db44STomer Tayar cond10, 168c965db44STomer Tayar cond11, 169c965db44STomer Tayar cond12, 1707b6859fbSMintz, Yuval cond13, 171c965db44STomer Tayar }; 172c965db44STomer Tayar 173c965db44STomer Tayar /******************************* Data Types **********************************/ 174c965db44STomer Tayar 175c965db44STomer Tayar enum platform_ids { 176c965db44STomer Tayar PLATFORM_ASIC, 177c965db44STomer Tayar PLATFORM_RESERVED, 178c965db44STomer Tayar PLATFORM_RESERVED2, 179c965db44STomer Tayar PLATFORM_RESERVED3, 180c965db44STomer Tayar MAX_PLATFORM_IDS 181c965db44STomer Tayar }; 182c965db44STomer Tayar 183c965db44STomer Tayar /* Chip constant definitions */ 184c965db44STomer Tayar struct chip_defs { 185c965db44STomer Tayar const char *name; 186c965db44STomer Tayar }; 187c965db44STomer Tayar 188c965db44STomer Tayar /* Platform constant definitions */ 189c965db44STomer Tayar struct platform_defs { 190c965db44STomer Tayar const char *name; 191c965db44STomer Tayar u32 delay_factor; 192da090917STomer Tayar u32 dmae_thresh; 193da090917STomer Tayar u32 log_thresh; 194c965db44STomer Tayar }; 195c965db44STomer Tayar 1967b6859fbSMintz, Yuval /* Storm constant definitions. 1977b6859fbSMintz, Yuval * Addresses are in bytes, sizes are in quad-regs. 1987b6859fbSMintz, Yuval */ 199c965db44STomer Tayar struct storm_defs { 200c965db44STomer Tayar char letter; 201c965db44STomer Tayar enum block_id block_id; 202c965db44STomer Tayar enum dbg_bus_clients dbg_client_id[MAX_CHIP_IDS]; 203c965db44STomer Tayar bool has_vfc; 204c965db44STomer Tayar u32 sem_fast_mem_addr; 205c965db44STomer Tayar u32 sem_frame_mode_addr; 206c965db44STomer Tayar u32 sem_slow_enable_addr; 207c965db44STomer Tayar u32 sem_slow_mode_addr; 208c965db44STomer Tayar u32 sem_slow_mode1_conf_addr; 209c965db44STomer Tayar u32 sem_sync_dbg_empty_addr; 210c965db44STomer Tayar u32 sem_slow_dbg_empty_addr; 211c965db44STomer Tayar u32 cm_ctx_wr_addr; 2127b6859fbSMintz, Yuval u32 cm_conn_ag_ctx_lid_size; 213c965db44STomer Tayar u32 cm_conn_ag_ctx_rd_addr; 2147b6859fbSMintz, Yuval u32 cm_conn_st_ctx_lid_size; 215c965db44STomer Tayar u32 cm_conn_st_ctx_rd_addr; 2167b6859fbSMintz, Yuval u32 cm_task_ag_ctx_lid_size; 217c965db44STomer Tayar u32 cm_task_ag_ctx_rd_addr; 2187b6859fbSMintz, Yuval u32 cm_task_st_ctx_lid_size; 219c965db44STomer Tayar u32 cm_task_st_ctx_rd_addr; 220c965db44STomer Tayar }; 221c965db44STomer Tayar 222c965db44STomer Tayar /* Block constant definitions */ 223c965db44STomer Tayar struct block_defs { 224c965db44STomer Tayar const char *name; 225da090917STomer Tayar bool exists[MAX_CHIP_IDS]; 226c965db44STomer Tayar bool associated_to_storm; 2277b6859fbSMintz, Yuval 2287b6859fbSMintz, Yuval /* Valid only if associated_to_storm is true */ 2297b6859fbSMintz, Yuval u32 storm_id; 230c965db44STomer Tayar enum dbg_bus_clients dbg_client_id[MAX_CHIP_IDS]; 231c965db44STomer Tayar u32 dbg_select_addr; 2327b6859fbSMintz, Yuval u32 dbg_enable_addr; 233c965db44STomer Tayar u32 dbg_shift_addr; 234c965db44STomer Tayar u32 dbg_force_valid_addr; 235c965db44STomer Tayar u32 dbg_force_frame_addr; 236c965db44STomer Tayar bool has_reset_bit; 2377b6859fbSMintz, Yuval 2387b6859fbSMintz, Yuval /* If true, block is taken out of reset before dump */ 2397b6859fbSMintz, Yuval bool unreset; 240c965db44STomer Tayar enum dbg_reset_regs reset_reg; 2417b6859fbSMintz, Yuval 2427b6859fbSMintz, Yuval /* Bit offset in reset register */ 2437b6859fbSMintz, Yuval u8 reset_bit_offset; 244c965db44STomer Tayar }; 245c965db44STomer Tayar 246c965db44STomer Tayar /* Reset register definitions */ 247c965db44STomer Tayar struct reset_reg_defs { 248c965db44STomer Tayar u32 addr; 249c965db44STomer Tayar bool exists[MAX_CHIP_IDS]; 250da090917STomer Tayar u32 unreset_val[MAX_CHIP_IDS]; 251c965db44STomer Tayar }; 252c965db44STomer Tayar 253c965db44STomer Tayar struct grc_param_defs { 254c965db44STomer Tayar u32 default_val[MAX_CHIP_IDS]; 255c965db44STomer Tayar u32 min; 256c965db44STomer Tayar u32 max; 257c965db44STomer Tayar bool is_preset; 25850bc60cbSMichal Kalderon bool is_persistent; 259c965db44STomer Tayar u32 exclude_all_preset_val; 260c965db44STomer Tayar u32 crash_preset_val; 261c965db44STomer Tayar }; 262c965db44STomer Tayar 2637b6859fbSMintz, Yuval /* Address is in 128b units. Width is in bits. */ 264c965db44STomer Tayar struct rss_mem_defs { 265c965db44STomer Tayar const char *mem_name; 266c965db44STomer Tayar const char *type_name; 2677b6859fbSMintz, Yuval u32 addr; 268da090917STomer Tayar u32 entry_width; 269c965db44STomer Tayar u32 num_entries[MAX_CHIP_IDS]; 270c965db44STomer Tayar }; 271c965db44STomer Tayar 272c965db44STomer Tayar struct vfc_ram_defs { 273c965db44STomer Tayar const char *mem_name; 274c965db44STomer Tayar const char *type_name; 275c965db44STomer Tayar u32 base_row; 276c965db44STomer Tayar u32 num_rows; 277c965db44STomer Tayar }; 278c965db44STomer Tayar 279c965db44STomer Tayar struct big_ram_defs { 280c965db44STomer Tayar const char *instance_name; 281c965db44STomer Tayar enum mem_groups mem_group_id; 282c965db44STomer Tayar enum mem_groups ram_mem_group_id; 283c965db44STomer Tayar enum dbg_grc_params grc_param; 284c965db44STomer Tayar u32 addr_reg_addr; 285c965db44STomer Tayar u32 data_reg_addr; 286da090917STomer Tayar u32 is_256b_reg_addr; 287da090917STomer Tayar u32 is_256b_bit_offset[MAX_CHIP_IDS]; 288da090917STomer Tayar u32 ram_size[MAX_CHIP_IDS]; /* In dwords */ 289c965db44STomer Tayar }; 290c965db44STomer Tayar 291c965db44STomer Tayar struct phy_defs { 292c965db44STomer Tayar const char *phy_name; 2937b6859fbSMintz, Yuval 2947b6859fbSMintz, Yuval /* PHY base GRC address */ 295c965db44STomer Tayar u32 base_addr; 2967b6859fbSMintz, Yuval 2977b6859fbSMintz, Yuval /* Relative address of indirect TBUS address register (bits 0..7) */ 298c965db44STomer Tayar u32 tbus_addr_lo_addr; 2997b6859fbSMintz, Yuval 3007b6859fbSMintz, Yuval /* Relative address of indirect TBUS address register (bits 8..10) */ 301c965db44STomer Tayar u32 tbus_addr_hi_addr; 3027b6859fbSMintz, Yuval 3037b6859fbSMintz, Yuval /* Relative address of indirect TBUS data register (bits 0..7) */ 304c965db44STomer Tayar u32 tbus_data_lo_addr; 3057b6859fbSMintz, Yuval 3067b6859fbSMintz, Yuval /* Relative address of indirect TBUS data register (bits 8..11) */ 307c965db44STomer Tayar u32 tbus_data_hi_addr; 308c965db44STomer Tayar }; 309c965db44STomer Tayar 310d52c89f1SMichal Kalderon /* Split type definitions */ 311d52c89f1SMichal Kalderon struct split_type_defs { 312d52c89f1SMichal Kalderon const char *name; 313d52c89f1SMichal Kalderon }; 314d52c89f1SMichal Kalderon 315c965db44STomer Tayar /******************************** Constants **********************************/ 316c965db44STomer Tayar 317c965db44STomer Tayar #define MAX_LCIDS 320 318c965db44STomer Tayar #define MAX_LTIDS 320 3197b6859fbSMintz, Yuval 320c965db44STomer Tayar #define NUM_IOR_SETS 2 321c965db44STomer Tayar #define IORS_PER_SET 176 322c965db44STomer Tayar #define IOR_SET_OFFSET(set_id) ((set_id) * 256) 3237b6859fbSMintz, Yuval 324c965db44STomer Tayar #define BYTES_IN_DWORD sizeof(u32) 325c965db44STomer Tayar 326c965db44STomer Tayar /* In the macros below, size and offset are specified in bits */ 327c965db44STomer Tayar #define CEIL_DWORDS(size) DIV_ROUND_UP(size, 32) 328c965db44STomer Tayar #define FIELD_BIT_OFFSET(type, field) type ## _ ## field ## _ ## OFFSET 329c965db44STomer Tayar #define FIELD_BIT_SIZE(type, field) type ## _ ## field ## _ ## SIZE 330c965db44STomer Tayar #define FIELD_DWORD_OFFSET(type, field) \ 331c965db44STomer Tayar (int)(FIELD_BIT_OFFSET(type, field) / 32) 332c965db44STomer Tayar #define FIELD_DWORD_SHIFT(type, field) (FIELD_BIT_OFFSET(type, field) % 32) 333c965db44STomer Tayar #define FIELD_BIT_MASK(type, field) \ 334c965db44STomer Tayar (((1 << FIELD_BIT_SIZE(type, field)) - 1) << \ 335c965db44STomer Tayar FIELD_DWORD_SHIFT(type, field)) 3367b6859fbSMintz, Yuval 337c965db44STomer Tayar #define SET_VAR_FIELD(var, type, field, val) \ 338c965db44STomer Tayar do { \ 339c965db44STomer Tayar var[FIELD_DWORD_OFFSET(type, field)] &= \ 340c965db44STomer Tayar (~FIELD_BIT_MASK(type, field)); \ 341c965db44STomer Tayar var[FIELD_DWORD_OFFSET(type, field)] |= \ 342c965db44STomer Tayar (val) << FIELD_DWORD_SHIFT(type, field); \ 343c965db44STomer Tayar } while (0) 3447b6859fbSMintz, Yuval 345c965db44STomer Tayar #define ARR_REG_WR(dev, ptt, addr, arr, arr_size) \ 346c965db44STomer Tayar do { \ 347c965db44STomer Tayar for (i = 0; i < (arr_size); i++) \ 348c965db44STomer Tayar qed_wr(dev, ptt, addr, (arr)[i]); \ 349c965db44STomer Tayar } while (0) 3507b6859fbSMintz, Yuval 351c965db44STomer Tayar #define ARR_REG_RD(dev, ptt, addr, arr, arr_size) \ 352c965db44STomer Tayar do { \ 353c965db44STomer Tayar for (i = 0; i < (arr_size); i++) \ 354c965db44STomer Tayar (arr)[i] = qed_rd(dev, ptt, addr); \ 355c965db44STomer Tayar } while (0) 356c965db44STomer Tayar 357c965db44STomer Tayar #define DWORDS_TO_BYTES(dwords) ((dwords) * BYTES_IN_DWORD) 358c965db44STomer Tayar #define BYTES_TO_DWORDS(bytes) ((bytes) / BYTES_IN_DWORD) 3597b6859fbSMintz, Yuval 360a2e7699eSTomer Tayar /* Extra lines include a signature line + optional latency events line */ 3617b6859fbSMintz, Yuval #define NUM_EXTRA_DBG_LINES(block_desc) \ 3627b6859fbSMintz, Yuval (1 + ((block_desc)->has_latency_events ? 1 : 0)) 3637b6859fbSMintz, Yuval #define NUM_DBG_LINES(block_desc) \ 3647b6859fbSMintz, Yuval ((block_desc)->num_of_lines + NUM_EXTRA_DBG_LINES(block_desc)) 3657b6859fbSMintz, Yuval 366c965db44STomer Tayar #define RAM_LINES_TO_DWORDS(lines) ((lines) * 2) 367c965db44STomer Tayar #define RAM_LINES_TO_BYTES(lines) \ 368c965db44STomer Tayar DWORDS_TO_BYTES(RAM_LINES_TO_DWORDS(lines)) 3697b6859fbSMintz, Yuval 370c965db44STomer Tayar #define REG_DUMP_LEN_SHIFT 24 371c965db44STomer Tayar #define MEM_DUMP_ENTRY_SIZE_DWORDS \ 372c965db44STomer Tayar BYTES_TO_DWORDS(sizeof(struct dbg_dump_mem)) 3737b6859fbSMintz, Yuval 374c965db44STomer Tayar #define IDLE_CHK_RULE_SIZE_DWORDS \ 375c965db44STomer Tayar BYTES_TO_DWORDS(sizeof(struct dbg_idle_chk_rule)) 3767b6859fbSMintz, Yuval 377c965db44STomer Tayar #define IDLE_CHK_RESULT_HDR_DWORDS \ 378c965db44STomer Tayar BYTES_TO_DWORDS(sizeof(struct dbg_idle_chk_result_hdr)) 3797b6859fbSMintz, Yuval 380c965db44STomer Tayar #define IDLE_CHK_RESULT_REG_HDR_DWORDS \ 381c965db44STomer Tayar BYTES_TO_DWORDS(sizeof(struct dbg_idle_chk_result_reg_hdr)) 3827b6859fbSMintz, Yuval 383c965db44STomer Tayar #define IDLE_CHK_MAX_ENTRIES_SIZE 32 384c965db44STomer Tayar 385c965db44STomer Tayar /* The sizes and offsets below are specified in bits */ 386c965db44STomer Tayar #define VFC_CAM_CMD_STRUCT_SIZE 64 387c965db44STomer Tayar #define VFC_CAM_CMD_ROW_OFFSET 48 388c965db44STomer Tayar #define VFC_CAM_CMD_ROW_SIZE 9 389c965db44STomer Tayar #define VFC_CAM_ADDR_STRUCT_SIZE 16 390c965db44STomer Tayar #define VFC_CAM_ADDR_OP_OFFSET 0 391c965db44STomer Tayar #define VFC_CAM_ADDR_OP_SIZE 4 392c965db44STomer Tayar #define VFC_CAM_RESP_STRUCT_SIZE 256 393c965db44STomer Tayar #define VFC_RAM_ADDR_STRUCT_SIZE 16 394c965db44STomer Tayar #define VFC_RAM_ADDR_OP_OFFSET 0 395c965db44STomer Tayar #define VFC_RAM_ADDR_OP_SIZE 2 396c965db44STomer Tayar #define VFC_RAM_ADDR_ROW_OFFSET 2 397c965db44STomer Tayar #define VFC_RAM_ADDR_ROW_SIZE 10 398c965db44STomer Tayar #define VFC_RAM_RESP_STRUCT_SIZE 256 3997b6859fbSMintz, Yuval 400c965db44STomer Tayar #define VFC_CAM_CMD_DWORDS CEIL_DWORDS(VFC_CAM_CMD_STRUCT_SIZE) 401c965db44STomer Tayar #define VFC_CAM_ADDR_DWORDS CEIL_DWORDS(VFC_CAM_ADDR_STRUCT_SIZE) 402c965db44STomer Tayar #define VFC_CAM_RESP_DWORDS CEIL_DWORDS(VFC_CAM_RESP_STRUCT_SIZE) 403c965db44STomer Tayar #define VFC_RAM_CMD_DWORDS VFC_CAM_CMD_DWORDS 404c965db44STomer Tayar #define VFC_RAM_ADDR_DWORDS CEIL_DWORDS(VFC_RAM_ADDR_STRUCT_SIZE) 405c965db44STomer Tayar #define VFC_RAM_RESP_DWORDS CEIL_DWORDS(VFC_RAM_RESP_STRUCT_SIZE) 4067b6859fbSMintz, Yuval 407c965db44STomer Tayar #define NUM_VFC_RAM_TYPES 4 4087b6859fbSMintz, Yuval 409c965db44STomer Tayar #define VFC_CAM_NUM_ROWS 512 4107b6859fbSMintz, Yuval 411c965db44STomer Tayar #define VFC_OPCODE_CAM_RD 14 412c965db44STomer Tayar #define VFC_OPCODE_RAM_RD 0 4137b6859fbSMintz, Yuval 414c965db44STomer Tayar #define NUM_RSS_MEM_TYPES 5 4157b6859fbSMintz, Yuval 416c965db44STomer Tayar #define NUM_BIG_RAM_TYPES 3 417c7d852e3SDenis Bolotin #define BIG_RAM_NAME_LEN 3 4187b6859fbSMintz, Yuval 419c965db44STomer Tayar #define NUM_PHY_TBUS_ADDRESSES 2048 420c965db44STomer Tayar #define PHY_DUMP_SIZE_DWORDS (NUM_PHY_TBUS_ADDRESSES / 2) 4217b6859fbSMintz, Yuval 422c965db44STomer Tayar #define RESET_REG_UNRESET_OFFSET 4 4237b6859fbSMintz, Yuval 424c965db44STomer Tayar #define STALL_DELAY_MS 500 4257b6859fbSMintz, Yuval 426c965db44STomer Tayar #define STATIC_DEBUG_LINE_DWORDS 9 4277b6859fbSMintz, Yuval 428c965db44STomer Tayar #define NUM_COMMON_GLOBAL_PARAMS 8 4297b6859fbSMintz, Yuval 430c965db44STomer Tayar #define FW_IMG_MAIN 1 4317b6859fbSMintz, Yuval 432c965db44STomer Tayar #define REG_FIFO_ELEMENT_DWORDS 2 4337b6859fbSMintz, Yuval #define REG_FIFO_DEPTH_ELEMENTS 32 434c965db44STomer Tayar #define REG_FIFO_DEPTH_DWORDS \ 435c965db44STomer Tayar (REG_FIFO_ELEMENT_DWORDS * REG_FIFO_DEPTH_ELEMENTS) 4367b6859fbSMintz, Yuval 437c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORDS 4 4387b6859fbSMintz, Yuval #define IGU_FIFO_DEPTH_ELEMENTS 64 439c965db44STomer Tayar #define IGU_FIFO_DEPTH_DWORDS \ 440c965db44STomer Tayar (IGU_FIFO_ELEMENT_DWORDS * IGU_FIFO_DEPTH_ELEMENTS) 4417b6859fbSMintz, Yuval 442c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_DWORDS 2 4437b6859fbSMintz, Yuval #define PROTECTION_OVERRIDE_DEPTH_ELEMENTS 20 444c965db44STomer Tayar #define PROTECTION_OVERRIDE_DEPTH_DWORDS \ 445c965db44STomer Tayar (PROTECTION_OVERRIDE_DEPTH_ELEMENTS * \ 446c965db44STomer Tayar PROTECTION_OVERRIDE_ELEMENT_DWORDS) 4477b6859fbSMintz, Yuval 448c965db44STomer Tayar #define MCP_SPAD_TRACE_OFFSIZE_ADDR \ 449c965db44STomer Tayar (MCP_REG_SCRATCH + \ 450c965db44STomer Tayar offsetof(struct static_init, sections[SPAD_SECTION_TRACE])) 4517b6859fbSMintz, Yuval 452c965db44STomer Tayar #define EMPTY_FW_VERSION_STR "???_???_???_???" 453c965db44STomer Tayar #define EMPTY_FW_IMAGE_STR "???????????????" 454c965db44STomer Tayar 455c965db44STomer Tayar /***************************** Constant Arrays *******************************/ 456c965db44STomer Tayar 4577b6859fbSMintz, Yuval struct dbg_array { 4587b6859fbSMintz, Yuval const u32 *ptr; 4597b6859fbSMintz, Yuval u32 size_in_dwords; 4607b6859fbSMintz, Yuval }; 4617b6859fbSMintz, Yuval 462c965db44STomer Tayar /* Debug arrays */ 4637b6859fbSMintz, Yuval static struct dbg_array s_dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE] = { {NULL} }; 464c965db44STomer Tayar 465c965db44STomer Tayar /* Chip constant definitions array */ 466c965db44STomer Tayar static struct chip_defs s_chip_defs[MAX_CHIP_IDS] = { 467d52c89f1SMichal Kalderon {"bb"}, 468d52c89f1SMichal Kalderon {"ah"}, 469d52c89f1SMichal Kalderon {"reserved"}, 470c965db44STomer Tayar }; 471c965db44STomer Tayar 472c965db44STomer Tayar /* Storm constant definitions array */ 473c965db44STomer Tayar static struct storm_defs s_storm_defs[] = { 474c965db44STomer Tayar /* Tstorm */ 475c965db44STomer Tayar {'T', BLOCK_TSEM, 476da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, 477da090917STomer Tayar DBG_BUS_CLIENT_RBCT}, true, 478c965db44STomer Tayar TSEM_REG_FAST_MEMORY, 4797b6859fbSMintz, Yuval TSEM_REG_DBG_FRAME_MODE_BB_K2, TSEM_REG_SLOW_DBG_ACTIVE_BB_K2, 4807b6859fbSMintz, Yuval TSEM_REG_SLOW_DBG_MODE_BB_K2, TSEM_REG_DBG_MODE1_CFG_BB_K2, 4817b6859fbSMintz, Yuval TSEM_REG_SYNC_DBG_EMPTY, TSEM_REG_SLOW_DBG_EMPTY_BB_K2, 482c965db44STomer Tayar TCM_REG_CTX_RBC_ACCS, 483c965db44STomer Tayar 4, TCM_REG_AGG_CON_CTX, 484c965db44STomer Tayar 16, TCM_REG_SM_CON_CTX, 485c965db44STomer Tayar 2, TCM_REG_AGG_TASK_CTX, 486c965db44STomer Tayar 4, TCM_REG_SM_TASK_CTX}, 4877b6859fbSMintz, Yuval 488c965db44STomer Tayar /* Mstorm */ 489c965db44STomer Tayar {'M', BLOCK_MSEM, 490da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, 491da090917STomer Tayar DBG_BUS_CLIENT_RBCM}, false, 492c965db44STomer Tayar MSEM_REG_FAST_MEMORY, 4937b6859fbSMintz, Yuval MSEM_REG_DBG_FRAME_MODE_BB_K2, MSEM_REG_SLOW_DBG_ACTIVE_BB_K2, 4947b6859fbSMintz, Yuval MSEM_REG_SLOW_DBG_MODE_BB_K2, MSEM_REG_DBG_MODE1_CFG_BB_K2, 4957b6859fbSMintz, Yuval MSEM_REG_SYNC_DBG_EMPTY, MSEM_REG_SLOW_DBG_EMPTY_BB_K2, 496c965db44STomer Tayar MCM_REG_CTX_RBC_ACCS, 497c965db44STomer Tayar 1, MCM_REG_AGG_CON_CTX, 498c965db44STomer Tayar 10, MCM_REG_SM_CON_CTX, 499c965db44STomer Tayar 2, MCM_REG_AGG_TASK_CTX, 500c965db44STomer Tayar 7, MCM_REG_SM_TASK_CTX}, 5017b6859fbSMintz, Yuval 502c965db44STomer Tayar /* Ustorm */ 503c965db44STomer Tayar {'U', BLOCK_USEM, 504da090917STomer Tayar {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, 505da090917STomer Tayar DBG_BUS_CLIENT_RBCU}, false, 506c965db44STomer Tayar USEM_REG_FAST_MEMORY, 5077b6859fbSMintz, Yuval USEM_REG_DBG_FRAME_MODE_BB_K2, USEM_REG_SLOW_DBG_ACTIVE_BB_K2, 5087b6859fbSMintz, Yuval USEM_REG_SLOW_DBG_MODE_BB_K2, USEM_REG_DBG_MODE1_CFG_BB_K2, 5097b6859fbSMintz, Yuval USEM_REG_SYNC_DBG_EMPTY, USEM_REG_SLOW_DBG_EMPTY_BB_K2, 510c965db44STomer Tayar UCM_REG_CTX_RBC_ACCS, 511c965db44STomer Tayar 2, UCM_REG_AGG_CON_CTX, 512c965db44STomer Tayar 13, UCM_REG_SM_CON_CTX, 513c965db44STomer Tayar 3, UCM_REG_AGG_TASK_CTX, 514c965db44STomer Tayar 3, UCM_REG_SM_TASK_CTX}, 5157b6859fbSMintz, Yuval 516c965db44STomer Tayar /* Xstorm */ 517c965db44STomer Tayar {'X', BLOCK_XSEM, 518da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, 519da090917STomer Tayar DBG_BUS_CLIENT_RBCX}, false, 520c965db44STomer Tayar XSEM_REG_FAST_MEMORY, 5217b6859fbSMintz, Yuval XSEM_REG_DBG_FRAME_MODE_BB_K2, XSEM_REG_SLOW_DBG_ACTIVE_BB_K2, 5227b6859fbSMintz, Yuval XSEM_REG_SLOW_DBG_MODE_BB_K2, XSEM_REG_DBG_MODE1_CFG_BB_K2, 5237b6859fbSMintz, Yuval XSEM_REG_SYNC_DBG_EMPTY, XSEM_REG_SLOW_DBG_EMPTY_BB_K2, 524c965db44STomer Tayar XCM_REG_CTX_RBC_ACCS, 525c965db44STomer Tayar 9, XCM_REG_AGG_CON_CTX, 526c965db44STomer Tayar 15, XCM_REG_SM_CON_CTX, 527c965db44STomer Tayar 0, 0, 528c965db44STomer Tayar 0, 0}, 5297b6859fbSMintz, Yuval 530c965db44STomer Tayar /* Ystorm */ 531c965db44STomer Tayar {'Y', BLOCK_YSEM, 532da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, 533da090917STomer Tayar DBG_BUS_CLIENT_RBCY}, false, 534c965db44STomer Tayar YSEM_REG_FAST_MEMORY, 5357b6859fbSMintz, Yuval YSEM_REG_DBG_FRAME_MODE_BB_K2, YSEM_REG_SLOW_DBG_ACTIVE_BB_K2, 5367b6859fbSMintz, Yuval YSEM_REG_SLOW_DBG_MODE_BB_K2, YSEM_REG_DBG_MODE1_CFG_BB_K2, 5377b6859fbSMintz, Yuval YSEM_REG_SYNC_DBG_EMPTY, TSEM_REG_SLOW_DBG_EMPTY_BB_K2, 538c965db44STomer Tayar YCM_REG_CTX_RBC_ACCS, 539c965db44STomer Tayar 2, YCM_REG_AGG_CON_CTX, 540c965db44STomer Tayar 3, YCM_REG_SM_CON_CTX, 541c965db44STomer Tayar 2, YCM_REG_AGG_TASK_CTX, 542c965db44STomer Tayar 12, YCM_REG_SM_TASK_CTX}, 5437b6859fbSMintz, Yuval 544c965db44STomer Tayar /* Pstorm */ 545c965db44STomer Tayar {'P', BLOCK_PSEM, 546da090917STomer Tayar {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, 547da090917STomer Tayar DBG_BUS_CLIENT_RBCS}, true, 548c965db44STomer Tayar PSEM_REG_FAST_MEMORY, 5497b6859fbSMintz, Yuval PSEM_REG_DBG_FRAME_MODE_BB_K2, PSEM_REG_SLOW_DBG_ACTIVE_BB_K2, 5507b6859fbSMintz, Yuval PSEM_REG_SLOW_DBG_MODE_BB_K2, PSEM_REG_DBG_MODE1_CFG_BB_K2, 5517b6859fbSMintz, Yuval PSEM_REG_SYNC_DBG_EMPTY, PSEM_REG_SLOW_DBG_EMPTY_BB_K2, 552c965db44STomer Tayar PCM_REG_CTX_RBC_ACCS, 553c965db44STomer Tayar 0, 0, 554c965db44STomer Tayar 10, PCM_REG_SM_CON_CTX, 555c965db44STomer Tayar 0, 0, 556c965db44STomer Tayar 0, 0} 557c965db44STomer Tayar }; 558c965db44STomer Tayar 559c965db44STomer Tayar /* Block definitions array */ 5607b6859fbSMintz, Yuval 561c965db44STomer Tayar static struct block_defs block_grc_defs = { 562be086e7cSMintz, Yuval "grc", 563da090917STomer Tayar {true, true, true}, false, 0, 564da090917STomer Tayar {DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN}, 565c965db44STomer Tayar GRC_REG_DBG_SELECT, GRC_REG_DBG_DWORD_ENABLE, 566c965db44STomer Tayar GRC_REG_DBG_SHIFT, GRC_REG_DBG_FORCE_VALID, 567c965db44STomer Tayar GRC_REG_DBG_FORCE_FRAME, 568c965db44STomer Tayar true, false, DBG_RESET_REG_MISC_PL_UA, 1 569c965db44STomer Tayar }; 570c965db44STomer Tayar 571c965db44STomer Tayar static struct block_defs block_miscs_defs = { 572da090917STomer Tayar "miscs", {true, true, true}, false, 0, 573da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 574c965db44STomer Tayar 0, 0, 0, 0, 0, 575c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 576c965db44STomer Tayar }; 577c965db44STomer Tayar 578c965db44STomer Tayar static struct block_defs block_misc_defs = { 579da090917STomer Tayar "misc", {true, true, true}, false, 0, 580da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 581c965db44STomer Tayar 0, 0, 0, 0, 0, 582c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 583c965db44STomer Tayar }; 584c965db44STomer Tayar 585c965db44STomer Tayar static struct block_defs block_dbu_defs = { 586da090917STomer Tayar "dbu", {true, true, true}, false, 0, 587da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 588c965db44STomer Tayar 0, 0, 0, 0, 0, 589c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 590c965db44STomer Tayar }; 591c965db44STomer Tayar 592c965db44STomer Tayar static struct block_defs block_pglue_b_defs = { 593be086e7cSMintz, Yuval "pglue_b", 594da090917STomer Tayar {true, true, true}, false, 0, 595da090917STomer Tayar {DBG_BUS_CLIENT_RBCH, DBG_BUS_CLIENT_RBCH, DBG_BUS_CLIENT_RBCH}, 596c965db44STomer Tayar PGLUE_B_REG_DBG_SELECT, PGLUE_B_REG_DBG_DWORD_ENABLE, 597c965db44STomer Tayar PGLUE_B_REG_DBG_SHIFT, PGLUE_B_REG_DBG_FORCE_VALID, 598c965db44STomer Tayar PGLUE_B_REG_DBG_FORCE_FRAME, 599c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV, 1 600c965db44STomer Tayar }; 601c965db44STomer Tayar 602c965db44STomer Tayar static struct block_defs block_cnig_defs = { 603be086e7cSMintz, Yuval "cnig", 604da090917STomer Tayar {true, true, true}, false, 0, 605da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW, 606da090917STomer Tayar DBG_BUS_CLIENT_RBCW}, 60721dd79e8STomer Tayar CNIG_REG_DBG_SELECT_K2_E5, CNIG_REG_DBG_DWORD_ENABLE_K2_E5, 60821dd79e8STomer Tayar CNIG_REG_DBG_SHIFT_K2_E5, CNIG_REG_DBG_FORCE_VALID_K2_E5, 60921dd79e8STomer Tayar CNIG_REG_DBG_FORCE_FRAME_K2_E5, 610c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV, 0 611c965db44STomer Tayar }; 612c965db44STomer Tayar 613c965db44STomer Tayar static struct block_defs block_cpmu_defs = { 614da090917STomer Tayar "cpmu", {true, true, true}, false, 0, 615da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 616c965db44STomer Tayar 0, 0, 0, 0, 0, 617c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV, 8 618c965db44STomer Tayar }; 619c965db44STomer Tayar 620c965db44STomer Tayar static struct block_defs block_ncsi_defs = { 621be086e7cSMintz, Yuval "ncsi", 622da090917STomer Tayar {true, true, true}, false, 0, 623da090917STomer Tayar {DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ}, 624c965db44STomer Tayar NCSI_REG_DBG_SELECT, NCSI_REG_DBG_DWORD_ENABLE, 625c965db44STomer Tayar NCSI_REG_DBG_SHIFT, NCSI_REG_DBG_FORCE_VALID, 626c965db44STomer Tayar NCSI_REG_DBG_FORCE_FRAME, 627c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV, 5 628c965db44STomer Tayar }; 629c965db44STomer Tayar 630c965db44STomer Tayar static struct block_defs block_opte_defs = { 631da090917STomer Tayar "opte", {true, true, false}, false, 0, 632da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 633c965db44STomer Tayar 0, 0, 0, 0, 0, 634c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV, 4 635c965db44STomer Tayar }; 636c965db44STomer Tayar 637c965db44STomer Tayar static struct block_defs block_bmb_defs = { 638be086e7cSMintz, Yuval "bmb", 639da090917STomer Tayar {true, true, true}, false, 0, 640da090917STomer Tayar {DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCB, DBG_BUS_CLIENT_RBCB}, 641c965db44STomer Tayar BMB_REG_DBG_SELECT, BMB_REG_DBG_DWORD_ENABLE, 642c965db44STomer Tayar BMB_REG_DBG_SHIFT, BMB_REG_DBG_FORCE_VALID, 643c965db44STomer Tayar BMB_REG_DBG_FORCE_FRAME, 644c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_UA, 7 645c965db44STomer Tayar }; 646c965db44STomer Tayar 647c965db44STomer Tayar static struct block_defs block_pcie_defs = { 648be086e7cSMintz, Yuval "pcie", 649da090917STomer Tayar {true, true, true}, false, 0, 650da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH, 651da090917STomer Tayar DBG_BUS_CLIENT_RBCH}, 65221dd79e8STomer Tayar PCIE_REG_DBG_COMMON_SELECT_K2_E5, 65321dd79e8STomer Tayar PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5, 65421dd79e8STomer Tayar PCIE_REG_DBG_COMMON_SHIFT_K2_E5, 65521dd79e8STomer Tayar PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5, 65621dd79e8STomer Tayar PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5, 657c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 658c965db44STomer Tayar }; 659c965db44STomer Tayar 660c965db44STomer Tayar static struct block_defs block_mcp_defs = { 661da090917STomer Tayar "mcp", {true, true, true}, false, 0, 662da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 663c965db44STomer Tayar 0, 0, 0, 0, 0, 664c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 665c965db44STomer Tayar }; 666c965db44STomer Tayar 667c965db44STomer Tayar static struct block_defs block_mcp2_defs = { 668be086e7cSMintz, Yuval "mcp2", 669da090917STomer Tayar {true, true, true}, false, 0, 670da090917STomer Tayar {DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ}, 671c965db44STomer Tayar MCP2_REG_DBG_SELECT, MCP2_REG_DBG_DWORD_ENABLE, 672c965db44STomer Tayar MCP2_REG_DBG_SHIFT, MCP2_REG_DBG_FORCE_VALID, 673c965db44STomer Tayar MCP2_REG_DBG_FORCE_FRAME, 674c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 675c965db44STomer Tayar }; 676c965db44STomer Tayar 677c965db44STomer Tayar static struct block_defs block_pswhst_defs = { 678be086e7cSMintz, Yuval "pswhst", 679da090917STomer Tayar {true, true, true}, false, 0, 680da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 681c965db44STomer Tayar PSWHST_REG_DBG_SELECT, PSWHST_REG_DBG_DWORD_ENABLE, 682c965db44STomer Tayar PSWHST_REG_DBG_SHIFT, PSWHST_REG_DBG_FORCE_VALID, 683c965db44STomer Tayar PSWHST_REG_DBG_FORCE_FRAME, 684c965db44STomer Tayar true, false, DBG_RESET_REG_MISC_PL_HV, 0 685c965db44STomer Tayar }; 686c965db44STomer Tayar 687c965db44STomer Tayar static struct block_defs block_pswhst2_defs = { 688be086e7cSMintz, Yuval "pswhst2", 689da090917STomer Tayar {true, true, true}, false, 0, 690da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 691c965db44STomer Tayar PSWHST2_REG_DBG_SELECT, PSWHST2_REG_DBG_DWORD_ENABLE, 692c965db44STomer Tayar PSWHST2_REG_DBG_SHIFT, PSWHST2_REG_DBG_FORCE_VALID, 693c965db44STomer Tayar PSWHST2_REG_DBG_FORCE_FRAME, 694c965db44STomer Tayar true, false, DBG_RESET_REG_MISC_PL_HV, 0 695c965db44STomer Tayar }; 696c965db44STomer Tayar 697c965db44STomer Tayar static struct block_defs block_pswrd_defs = { 698be086e7cSMintz, Yuval "pswrd", 699da090917STomer Tayar {true, true, true}, false, 0, 700da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 701c965db44STomer Tayar PSWRD_REG_DBG_SELECT, PSWRD_REG_DBG_DWORD_ENABLE, 702c965db44STomer Tayar PSWRD_REG_DBG_SHIFT, PSWRD_REG_DBG_FORCE_VALID, 703c965db44STomer Tayar PSWRD_REG_DBG_FORCE_FRAME, 704c965db44STomer Tayar true, false, DBG_RESET_REG_MISC_PL_HV, 2 705c965db44STomer Tayar }; 706c965db44STomer Tayar 707c965db44STomer Tayar static struct block_defs block_pswrd2_defs = { 708be086e7cSMintz, Yuval "pswrd2", 709da090917STomer Tayar {true, true, true}, false, 0, 710da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 711c965db44STomer Tayar PSWRD2_REG_DBG_SELECT, PSWRD2_REG_DBG_DWORD_ENABLE, 712c965db44STomer Tayar PSWRD2_REG_DBG_SHIFT, PSWRD2_REG_DBG_FORCE_VALID, 713c965db44STomer Tayar PSWRD2_REG_DBG_FORCE_FRAME, 714c965db44STomer Tayar true, false, DBG_RESET_REG_MISC_PL_HV, 2 715c965db44STomer Tayar }; 716c965db44STomer Tayar 717c965db44STomer Tayar static struct block_defs block_pswwr_defs = { 718be086e7cSMintz, Yuval "pswwr", 719da090917STomer Tayar {true, true, true}, false, 0, 720da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 721c965db44STomer Tayar PSWWR_REG_DBG_SELECT, PSWWR_REG_DBG_DWORD_ENABLE, 722c965db44STomer Tayar PSWWR_REG_DBG_SHIFT, PSWWR_REG_DBG_FORCE_VALID, 723c965db44STomer Tayar PSWWR_REG_DBG_FORCE_FRAME, 724c965db44STomer Tayar true, false, DBG_RESET_REG_MISC_PL_HV, 3 725c965db44STomer Tayar }; 726c965db44STomer Tayar 727c965db44STomer Tayar static struct block_defs block_pswwr2_defs = { 728da090917STomer Tayar "pswwr2", {true, true, true}, false, 0, 729da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 730c965db44STomer Tayar 0, 0, 0, 0, 0, 731c965db44STomer Tayar true, false, DBG_RESET_REG_MISC_PL_HV, 3 732c965db44STomer Tayar }; 733c965db44STomer Tayar 734c965db44STomer Tayar static struct block_defs block_pswrq_defs = { 735be086e7cSMintz, Yuval "pswrq", 736da090917STomer Tayar {true, true, true}, false, 0, 737da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 738c965db44STomer Tayar PSWRQ_REG_DBG_SELECT, PSWRQ_REG_DBG_DWORD_ENABLE, 739c965db44STomer Tayar PSWRQ_REG_DBG_SHIFT, PSWRQ_REG_DBG_FORCE_VALID, 740c965db44STomer Tayar PSWRQ_REG_DBG_FORCE_FRAME, 741c965db44STomer Tayar true, false, DBG_RESET_REG_MISC_PL_HV, 1 742c965db44STomer Tayar }; 743c965db44STomer Tayar 744c965db44STomer Tayar static struct block_defs block_pswrq2_defs = { 745be086e7cSMintz, Yuval "pswrq2", 746da090917STomer Tayar {true, true, true}, false, 0, 747da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 748c965db44STomer Tayar PSWRQ2_REG_DBG_SELECT, PSWRQ2_REG_DBG_DWORD_ENABLE, 749c965db44STomer Tayar PSWRQ2_REG_DBG_SHIFT, PSWRQ2_REG_DBG_FORCE_VALID, 750c965db44STomer Tayar PSWRQ2_REG_DBG_FORCE_FRAME, 751c965db44STomer Tayar true, false, DBG_RESET_REG_MISC_PL_HV, 1 752c965db44STomer Tayar }; 753c965db44STomer Tayar 754c965db44STomer Tayar static struct block_defs block_pglcs_defs = { 755be086e7cSMintz, Yuval "pglcs", 756da090917STomer Tayar {true, true, true}, false, 0, 757da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH, 758da090917STomer Tayar DBG_BUS_CLIENT_RBCH}, 75921dd79e8STomer Tayar PGLCS_REG_DBG_SELECT_K2_E5, PGLCS_REG_DBG_DWORD_ENABLE_K2_E5, 76021dd79e8STomer Tayar PGLCS_REG_DBG_SHIFT_K2_E5, PGLCS_REG_DBG_FORCE_VALID_K2_E5, 76121dd79e8STomer Tayar PGLCS_REG_DBG_FORCE_FRAME_K2_E5, 762c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV, 2 763c965db44STomer Tayar }; 764c965db44STomer Tayar 765c965db44STomer Tayar static struct block_defs block_ptu_defs = { 766be086e7cSMintz, Yuval "ptu", 767da090917STomer Tayar {true, true, true}, false, 0, 768da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 769c965db44STomer Tayar PTU_REG_DBG_SELECT, PTU_REG_DBG_DWORD_ENABLE, 770c965db44STomer Tayar PTU_REG_DBG_SHIFT, PTU_REG_DBG_FORCE_VALID, 771c965db44STomer Tayar PTU_REG_DBG_FORCE_FRAME, 772c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 20 773c965db44STomer Tayar }; 774c965db44STomer Tayar 775c965db44STomer Tayar static struct block_defs block_dmae_defs = { 776be086e7cSMintz, Yuval "dmae", 777da090917STomer Tayar {true, true, true}, false, 0, 778da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 779c965db44STomer Tayar DMAE_REG_DBG_SELECT, DMAE_REG_DBG_DWORD_ENABLE, 780c965db44STomer Tayar DMAE_REG_DBG_SHIFT, DMAE_REG_DBG_FORCE_VALID, 781c965db44STomer Tayar DMAE_REG_DBG_FORCE_FRAME, 782c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 28 783c965db44STomer Tayar }; 784c965db44STomer Tayar 785c965db44STomer Tayar static struct block_defs block_tcm_defs = { 786be086e7cSMintz, Yuval "tcm", 787da090917STomer Tayar {true, true, true}, true, DBG_TSTORM_ID, 788da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT}, 789c965db44STomer Tayar TCM_REG_DBG_SELECT, TCM_REG_DBG_DWORD_ENABLE, 790c965db44STomer Tayar TCM_REG_DBG_SHIFT, TCM_REG_DBG_FORCE_VALID, 791c965db44STomer Tayar TCM_REG_DBG_FORCE_FRAME, 792c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 5 793c965db44STomer Tayar }; 794c965db44STomer Tayar 795c965db44STomer Tayar static struct block_defs block_mcm_defs = { 796be086e7cSMintz, Yuval "mcm", 797da090917STomer Tayar {true, true, true}, true, DBG_MSTORM_ID, 798da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM}, 799c965db44STomer Tayar MCM_REG_DBG_SELECT, MCM_REG_DBG_DWORD_ENABLE, 800c965db44STomer Tayar MCM_REG_DBG_SHIFT, MCM_REG_DBG_FORCE_VALID, 801c965db44STomer Tayar MCM_REG_DBG_FORCE_FRAME, 802c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 3 803c965db44STomer Tayar }; 804c965db44STomer Tayar 805c965db44STomer Tayar static struct block_defs block_ucm_defs = { 806be086e7cSMintz, Yuval "ucm", 807da090917STomer Tayar {true, true, true}, true, DBG_USTORM_ID, 808da090917STomer Tayar {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU}, 809c965db44STomer Tayar UCM_REG_DBG_SELECT, UCM_REG_DBG_DWORD_ENABLE, 810c965db44STomer Tayar UCM_REG_DBG_SHIFT, UCM_REG_DBG_FORCE_VALID, 811c965db44STomer Tayar UCM_REG_DBG_FORCE_FRAME, 812c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 8 813c965db44STomer Tayar }; 814c965db44STomer Tayar 815c965db44STomer Tayar static struct block_defs block_xcm_defs = { 816be086e7cSMintz, Yuval "xcm", 817da090917STomer Tayar {true, true, true}, true, DBG_XSTORM_ID, 818da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX}, 819c965db44STomer Tayar XCM_REG_DBG_SELECT, XCM_REG_DBG_DWORD_ENABLE, 820c965db44STomer Tayar XCM_REG_DBG_SHIFT, XCM_REG_DBG_FORCE_VALID, 821c965db44STomer Tayar XCM_REG_DBG_FORCE_FRAME, 822c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 19 823c965db44STomer Tayar }; 824c965db44STomer Tayar 825c965db44STomer Tayar static struct block_defs block_ycm_defs = { 826be086e7cSMintz, Yuval "ycm", 827da090917STomer Tayar {true, true, true}, true, DBG_YSTORM_ID, 828da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY}, 829c965db44STomer Tayar YCM_REG_DBG_SELECT, YCM_REG_DBG_DWORD_ENABLE, 830c965db44STomer Tayar YCM_REG_DBG_SHIFT, YCM_REG_DBG_FORCE_VALID, 831c965db44STomer Tayar YCM_REG_DBG_FORCE_FRAME, 832c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 5 833c965db44STomer Tayar }; 834c965db44STomer Tayar 835c965db44STomer Tayar static struct block_defs block_pcm_defs = { 836be086e7cSMintz, Yuval "pcm", 837da090917STomer Tayar {true, true, true}, true, DBG_PSTORM_ID, 838da090917STomer Tayar {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS}, 839c965db44STomer Tayar PCM_REG_DBG_SELECT, PCM_REG_DBG_DWORD_ENABLE, 840c965db44STomer Tayar PCM_REG_DBG_SHIFT, PCM_REG_DBG_FORCE_VALID, 841c965db44STomer Tayar PCM_REG_DBG_FORCE_FRAME, 842c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 4 843c965db44STomer Tayar }; 844c965db44STomer Tayar 845c965db44STomer Tayar static struct block_defs block_qm_defs = { 846be086e7cSMintz, Yuval "qm", 847da090917STomer Tayar {true, true, true}, false, 0, 848da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCQ, DBG_BUS_CLIENT_RBCQ}, 849c965db44STomer Tayar QM_REG_DBG_SELECT, QM_REG_DBG_DWORD_ENABLE, 850c965db44STomer Tayar QM_REG_DBG_SHIFT, QM_REG_DBG_FORCE_VALID, 851c965db44STomer Tayar QM_REG_DBG_FORCE_FRAME, 852c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 16 853c965db44STomer Tayar }; 854c965db44STomer Tayar 855c965db44STomer Tayar static struct block_defs block_tm_defs = { 856be086e7cSMintz, Yuval "tm", 857da090917STomer Tayar {true, true, true}, false, 0, 858da090917STomer Tayar {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS}, 859c965db44STomer Tayar TM_REG_DBG_SELECT, TM_REG_DBG_DWORD_ENABLE, 860c965db44STomer Tayar TM_REG_DBG_SHIFT, TM_REG_DBG_FORCE_VALID, 861c965db44STomer Tayar TM_REG_DBG_FORCE_FRAME, 862c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 17 863c965db44STomer Tayar }; 864c965db44STomer Tayar 865c965db44STomer Tayar static struct block_defs block_dorq_defs = { 866be086e7cSMintz, Yuval "dorq", 867da090917STomer Tayar {true, true, true}, false, 0, 868da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY}, 869c965db44STomer Tayar DORQ_REG_DBG_SELECT, DORQ_REG_DBG_DWORD_ENABLE, 870c965db44STomer Tayar DORQ_REG_DBG_SHIFT, DORQ_REG_DBG_FORCE_VALID, 871c965db44STomer Tayar DORQ_REG_DBG_FORCE_FRAME, 872c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 18 873c965db44STomer Tayar }; 874c965db44STomer Tayar 875c965db44STomer Tayar static struct block_defs block_brb_defs = { 876be086e7cSMintz, Yuval "brb", 877da090917STomer Tayar {true, true, true}, false, 0, 878da090917STomer Tayar {DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR}, 879c965db44STomer Tayar BRB_REG_DBG_SELECT, BRB_REG_DBG_DWORD_ENABLE, 880c965db44STomer Tayar BRB_REG_DBG_SHIFT, BRB_REG_DBG_FORCE_VALID, 881c965db44STomer Tayar BRB_REG_DBG_FORCE_FRAME, 882c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 0 883c965db44STomer Tayar }; 884c965db44STomer Tayar 885c965db44STomer Tayar static struct block_defs block_src_defs = { 886be086e7cSMintz, Yuval "src", 887da090917STomer Tayar {true, true, true}, false, 0, 888da090917STomer Tayar {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF}, 889c965db44STomer Tayar SRC_REG_DBG_SELECT, SRC_REG_DBG_DWORD_ENABLE, 890c965db44STomer Tayar SRC_REG_DBG_SHIFT, SRC_REG_DBG_FORCE_VALID, 891c965db44STomer Tayar SRC_REG_DBG_FORCE_FRAME, 892c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 2 893c965db44STomer Tayar }; 894c965db44STomer Tayar 895c965db44STomer Tayar static struct block_defs block_prs_defs = { 896be086e7cSMintz, Yuval "prs", 897da090917STomer Tayar {true, true, true}, false, 0, 898da090917STomer Tayar {DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCR}, 899c965db44STomer Tayar PRS_REG_DBG_SELECT, PRS_REG_DBG_DWORD_ENABLE, 900c965db44STomer Tayar PRS_REG_DBG_SHIFT, PRS_REG_DBG_FORCE_VALID, 901c965db44STomer Tayar PRS_REG_DBG_FORCE_FRAME, 902c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 1 903c965db44STomer Tayar }; 904c965db44STomer Tayar 905c965db44STomer Tayar static struct block_defs block_tsdm_defs = { 906be086e7cSMintz, Yuval "tsdm", 907da090917STomer Tayar {true, true, true}, true, DBG_TSTORM_ID, 908da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT}, 909c965db44STomer Tayar TSDM_REG_DBG_SELECT, TSDM_REG_DBG_DWORD_ENABLE, 910c965db44STomer Tayar TSDM_REG_DBG_SHIFT, TSDM_REG_DBG_FORCE_VALID, 911c965db44STomer Tayar TSDM_REG_DBG_FORCE_FRAME, 912c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 3 913c965db44STomer Tayar }; 914c965db44STomer Tayar 915c965db44STomer Tayar static struct block_defs block_msdm_defs = { 916be086e7cSMintz, Yuval "msdm", 917da090917STomer Tayar {true, true, true}, true, DBG_MSTORM_ID, 918da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM}, 919c965db44STomer Tayar MSDM_REG_DBG_SELECT, MSDM_REG_DBG_DWORD_ENABLE, 920c965db44STomer Tayar MSDM_REG_DBG_SHIFT, MSDM_REG_DBG_FORCE_VALID, 921c965db44STomer Tayar MSDM_REG_DBG_FORCE_FRAME, 922c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 6 923c965db44STomer Tayar }; 924c965db44STomer Tayar 925c965db44STomer Tayar static struct block_defs block_usdm_defs = { 926be086e7cSMintz, Yuval "usdm", 927da090917STomer Tayar {true, true, true}, true, DBG_USTORM_ID, 928da090917STomer Tayar {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU}, 929c965db44STomer Tayar USDM_REG_DBG_SELECT, USDM_REG_DBG_DWORD_ENABLE, 930c965db44STomer Tayar USDM_REG_DBG_SHIFT, USDM_REG_DBG_FORCE_VALID, 931c965db44STomer Tayar USDM_REG_DBG_FORCE_FRAME, 932c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 7 933c965db44STomer Tayar }; 934c965db44STomer Tayar 935c965db44STomer Tayar static struct block_defs block_xsdm_defs = { 936be086e7cSMintz, Yuval "xsdm", 937da090917STomer Tayar {true, true, true}, true, DBG_XSTORM_ID, 938da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX}, 939c965db44STomer Tayar XSDM_REG_DBG_SELECT, XSDM_REG_DBG_DWORD_ENABLE, 940c965db44STomer Tayar XSDM_REG_DBG_SHIFT, XSDM_REG_DBG_FORCE_VALID, 941c965db44STomer Tayar XSDM_REG_DBG_FORCE_FRAME, 942c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 20 943c965db44STomer Tayar }; 944c965db44STomer Tayar 945c965db44STomer Tayar static struct block_defs block_ysdm_defs = { 946be086e7cSMintz, Yuval "ysdm", 947da090917STomer Tayar {true, true, true}, true, DBG_YSTORM_ID, 948da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY}, 949c965db44STomer Tayar YSDM_REG_DBG_SELECT, YSDM_REG_DBG_DWORD_ENABLE, 950c965db44STomer Tayar YSDM_REG_DBG_SHIFT, YSDM_REG_DBG_FORCE_VALID, 951c965db44STomer Tayar YSDM_REG_DBG_FORCE_FRAME, 952c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 8 953c965db44STomer Tayar }; 954c965db44STomer Tayar 955c965db44STomer Tayar static struct block_defs block_psdm_defs = { 956be086e7cSMintz, Yuval "psdm", 957da090917STomer Tayar {true, true, true}, true, DBG_PSTORM_ID, 958da090917STomer Tayar {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS}, 959c965db44STomer Tayar PSDM_REG_DBG_SELECT, PSDM_REG_DBG_DWORD_ENABLE, 960c965db44STomer Tayar PSDM_REG_DBG_SHIFT, PSDM_REG_DBG_FORCE_VALID, 961c965db44STomer Tayar PSDM_REG_DBG_FORCE_FRAME, 962c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 7 963c965db44STomer Tayar }; 964c965db44STomer Tayar 965c965db44STomer Tayar static struct block_defs block_tsem_defs = { 966be086e7cSMintz, Yuval "tsem", 967da090917STomer Tayar {true, true, true}, true, DBG_TSTORM_ID, 968da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT}, 969c965db44STomer Tayar TSEM_REG_DBG_SELECT, TSEM_REG_DBG_DWORD_ENABLE, 970c965db44STomer Tayar TSEM_REG_DBG_SHIFT, TSEM_REG_DBG_FORCE_VALID, 971c965db44STomer Tayar TSEM_REG_DBG_FORCE_FRAME, 972c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 4 973c965db44STomer Tayar }; 974c965db44STomer Tayar 975c965db44STomer Tayar static struct block_defs block_msem_defs = { 976be086e7cSMintz, Yuval "msem", 977da090917STomer Tayar {true, true, true}, true, DBG_MSTORM_ID, 978da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM}, 979c965db44STomer Tayar MSEM_REG_DBG_SELECT, MSEM_REG_DBG_DWORD_ENABLE, 980c965db44STomer Tayar MSEM_REG_DBG_SHIFT, MSEM_REG_DBG_FORCE_VALID, 981c965db44STomer Tayar MSEM_REG_DBG_FORCE_FRAME, 982c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 9 983c965db44STomer Tayar }; 984c965db44STomer Tayar 985c965db44STomer Tayar static struct block_defs block_usem_defs = { 986be086e7cSMintz, Yuval "usem", 987da090917STomer Tayar {true, true, true}, true, DBG_USTORM_ID, 988da090917STomer Tayar {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU}, 989c965db44STomer Tayar USEM_REG_DBG_SELECT, USEM_REG_DBG_DWORD_ENABLE, 990c965db44STomer Tayar USEM_REG_DBG_SHIFT, USEM_REG_DBG_FORCE_VALID, 991c965db44STomer Tayar USEM_REG_DBG_FORCE_FRAME, 992c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 9 993c965db44STomer Tayar }; 994c965db44STomer Tayar 995c965db44STomer Tayar static struct block_defs block_xsem_defs = { 996be086e7cSMintz, Yuval "xsem", 997da090917STomer Tayar {true, true, true}, true, DBG_XSTORM_ID, 998da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX}, 999c965db44STomer Tayar XSEM_REG_DBG_SELECT, XSEM_REG_DBG_DWORD_ENABLE, 1000c965db44STomer Tayar XSEM_REG_DBG_SHIFT, XSEM_REG_DBG_FORCE_VALID, 1001c965db44STomer Tayar XSEM_REG_DBG_FORCE_FRAME, 1002c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 21 1003c965db44STomer Tayar }; 1004c965db44STomer Tayar 1005c965db44STomer Tayar static struct block_defs block_ysem_defs = { 1006be086e7cSMintz, Yuval "ysem", 1007da090917STomer Tayar {true, true, true}, true, DBG_YSTORM_ID, 1008da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCY, DBG_BUS_CLIENT_RBCY}, 1009c965db44STomer Tayar YSEM_REG_DBG_SELECT, YSEM_REG_DBG_DWORD_ENABLE, 1010c965db44STomer Tayar YSEM_REG_DBG_SHIFT, YSEM_REG_DBG_FORCE_VALID, 1011c965db44STomer Tayar YSEM_REG_DBG_FORCE_FRAME, 1012c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 11 1013c965db44STomer Tayar }; 1014c965db44STomer Tayar 1015c965db44STomer Tayar static struct block_defs block_psem_defs = { 1016be086e7cSMintz, Yuval "psem", 1017da090917STomer Tayar {true, true, true}, true, DBG_PSTORM_ID, 1018da090917STomer Tayar {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS}, 1019c965db44STomer Tayar PSEM_REG_DBG_SELECT, PSEM_REG_DBG_DWORD_ENABLE, 1020c965db44STomer Tayar PSEM_REG_DBG_SHIFT, PSEM_REG_DBG_FORCE_VALID, 1021c965db44STomer Tayar PSEM_REG_DBG_FORCE_FRAME, 1022c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 10 1023c965db44STomer Tayar }; 1024c965db44STomer Tayar 1025c965db44STomer Tayar static struct block_defs block_rss_defs = { 1026be086e7cSMintz, Yuval "rss", 1027da090917STomer Tayar {true, true, true}, false, 0, 1028da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCT}, 1029c965db44STomer Tayar RSS_REG_DBG_SELECT, RSS_REG_DBG_DWORD_ENABLE, 1030c965db44STomer Tayar RSS_REG_DBG_SHIFT, RSS_REG_DBG_FORCE_VALID, 1031c965db44STomer Tayar RSS_REG_DBG_FORCE_FRAME, 1032c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 18 1033c965db44STomer Tayar }; 1034c965db44STomer Tayar 1035c965db44STomer Tayar static struct block_defs block_tmld_defs = { 1036be086e7cSMintz, Yuval "tmld", 1037da090917STomer Tayar {true, true, true}, false, 0, 1038da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM}, 1039c965db44STomer Tayar TMLD_REG_DBG_SELECT, TMLD_REG_DBG_DWORD_ENABLE, 1040c965db44STomer Tayar TMLD_REG_DBG_SHIFT, TMLD_REG_DBG_FORCE_VALID, 1041c965db44STomer Tayar TMLD_REG_DBG_FORCE_FRAME, 1042c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 13 1043c965db44STomer Tayar }; 1044c965db44STomer Tayar 1045c965db44STomer Tayar static struct block_defs block_muld_defs = { 1046be086e7cSMintz, Yuval "muld", 1047da090917STomer Tayar {true, true, true}, false, 0, 1048da090917STomer Tayar {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU}, 1049c965db44STomer Tayar MULD_REG_DBG_SELECT, MULD_REG_DBG_DWORD_ENABLE, 1050c965db44STomer Tayar MULD_REG_DBG_SHIFT, MULD_REG_DBG_FORCE_VALID, 1051c965db44STomer Tayar MULD_REG_DBG_FORCE_FRAME, 1052c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 14 1053c965db44STomer Tayar }; 1054c965db44STomer Tayar 1055c965db44STomer Tayar static struct block_defs block_yuld_defs = { 1056be086e7cSMintz, Yuval "yuld", 1057da090917STomer Tayar {true, true, false}, false, 0, 1058da090917STomer Tayar {DBG_BUS_CLIENT_RBCU, DBG_BUS_CLIENT_RBCU, 1059da090917STomer Tayar MAX_DBG_BUS_CLIENTS}, 10607b6859fbSMintz, Yuval YULD_REG_DBG_SELECT_BB_K2, YULD_REG_DBG_DWORD_ENABLE_BB_K2, 10617b6859fbSMintz, Yuval YULD_REG_DBG_SHIFT_BB_K2, YULD_REG_DBG_FORCE_VALID_BB_K2, 10627b6859fbSMintz, Yuval YULD_REG_DBG_FORCE_FRAME_BB_K2, 10637b6859fbSMintz, Yuval true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 10647b6859fbSMintz, Yuval 15 1065c965db44STomer Tayar }; 1066c965db44STomer Tayar 1067c965db44STomer Tayar static struct block_defs block_xyld_defs = { 1068be086e7cSMintz, Yuval "xyld", 1069da090917STomer Tayar {true, true, true}, false, 0, 1070da090917STomer Tayar {DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX, DBG_BUS_CLIENT_RBCX}, 1071c965db44STomer Tayar XYLD_REG_DBG_SELECT, XYLD_REG_DBG_DWORD_ENABLE, 1072c965db44STomer Tayar XYLD_REG_DBG_SHIFT, XYLD_REG_DBG_FORCE_VALID, 1073c965db44STomer Tayar XYLD_REG_DBG_FORCE_FRAME, 1074c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 12 1075c965db44STomer Tayar }; 1076c965db44STomer Tayar 1077a2e7699eSTomer Tayar static struct block_defs block_ptld_defs = { 1078da090917STomer Tayar "ptld", 1079da090917STomer Tayar {false, false, true}, false, 0, 1080da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCT}, 1081da090917STomer Tayar PTLD_REG_DBG_SELECT_E5, PTLD_REG_DBG_DWORD_ENABLE_E5, 1082da090917STomer Tayar PTLD_REG_DBG_SHIFT_E5, PTLD_REG_DBG_FORCE_VALID_E5, 1083da090917STomer Tayar PTLD_REG_DBG_FORCE_FRAME_E5, 1084da090917STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 1085da090917STomer Tayar 28 1086a2e7699eSTomer Tayar }; 1087a2e7699eSTomer Tayar 1088a2e7699eSTomer Tayar static struct block_defs block_ypld_defs = { 1089da090917STomer Tayar "ypld", 1090da090917STomer Tayar {false, false, true}, false, 0, 1091da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCS}, 1092da090917STomer Tayar YPLD_REG_DBG_SELECT_E5, YPLD_REG_DBG_DWORD_ENABLE_E5, 1093da090917STomer Tayar YPLD_REG_DBG_SHIFT_E5, YPLD_REG_DBG_FORCE_VALID_E5, 1094da090917STomer Tayar YPLD_REG_DBG_FORCE_FRAME_E5, 1095da090917STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 1096da090917STomer Tayar 27 1097a2e7699eSTomer Tayar }; 1098a2e7699eSTomer Tayar 1099c965db44STomer Tayar static struct block_defs block_prm_defs = { 1100be086e7cSMintz, Yuval "prm", 1101da090917STomer Tayar {true, true, true}, false, 0, 1102da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM}, 1103c965db44STomer Tayar PRM_REG_DBG_SELECT, PRM_REG_DBG_DWORD_ENABLE, 1104c965db44STomer Tayar PRM_REG_DBG_SHIFT, PRM_REG_DBG_FORCE_VALID, 1105c965db44STomer Tayar PRM_REG_DBG_FORCE_FRAME, 1106c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 21 1107c965db44STomer Tayar }; 1108c965db44STomer Tayar 1109c965db44STomer Tayar static struct block_defs block_pbf_pb1_defs = { 1110be086e7cSMintz, Yuval "pbf_pb1", 1111da090917STomer Tayar {true, true, true}, false, 0, 1112da090917STomer Tayar {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV}, 1113c965db44STomer Tayar PBF_PB1_REG_DBG_SELECT, PBF_PB1_REG_DBG_DWORD_ENABLE, 1114c965db44STomer Tayar PBF_PB1_REG_DBG_SHIFT, PBF_PB1_REG_DBG_FORCE_VALID, 1115c965db44STomer Tayar PBF_PB1_REG_DBG_FORCE_FRAME, 1116c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 1117c965db44STomer Tayar 11 1118c965db44STomer Tayar }; 1119c965db44STomer Tayar 1120c965db44STomer Tayar static struct block_defs block_pbf_pb2_defs = { 1121be086e7cSMintz, Yuval "pbf_pb2", 1122da090917STomer Tayar {true, true, true}, false, 0, 1123da090917STomer Tayar {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV}, 1124c965db44STomer Tayar PBF_PB2_REG_DBG_SELECT, PBF_PB2_REG_DBG_DWORD_ENABLE, 1125c965db44STomer Tayar PBF_PB2_REG_DBG_SHIFT, PBF_PB2_REG_DBG_FORCE_VALID, 1126c965db44STomer Tayar PBF_PB2_REG_DBG_FORCE_FRAME, 1127c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 1128c965db44STomer Tayar 12 1129c965db44STomer Tayar }; 1130c965db44STomer Tayar 1131c965db44STomer Tayar static struct block_defs block_rpb_defs = { 1132be086e7cSMintz, Yuval "rpb", 1133da090917STomer Tayar {true, true, true}, false, 0, 1134da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM}, 1135c965db44STomer Tayar RPB_REG_DBG_SELECT, RPB_REG_DBG_DWORD_ENABLE, 1136c965db44STomer Tayar RPB_REG_DBG_SHIFT, RPB_REG_DBG_FORCE_VALID, 1137c965db44STomer Tayar RPB_REG_DBG_FORCE_FRAME, 1138c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 13 1139c965db44STomer Tayar }; 1140c965db44STomer Tayar 1141c965db44STomer Tayar static struct block_defs block_btb_defs = { 1142be086e7cSMintz, Yuval "btb", 1143da090917STomer Tayar {true, true, true}, false, 0, 1144da090917STomer Tayar {DBG_BUS_CLIENT_RBCR, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV}, 1145c965db44STomer Tayar BTB_REG_DBG_SELECT, BTB_REG_DBG_DWORD_ENABLE, 1146c965db44STomer Tayar BTB_REG_DBG_SHIFT, BTB_REG_DBG_FORCE_VALID, 1147c965db44STomer Tayar BTB_REG_DBG_FORCE_FRAME, 1148c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 10 1149c965db44STomer Tayar }; 1150c965db44STomer Tayar 1151c965db44STomer Tayar static struct block_defs block_pbf_defs = { 1152be086e7cSMintz, Yuval "pbf", 1153da090917STomer Tayar {true, true, true}, false, 0, 1154da090917STomer Tayar {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCV, DBG_BUS_CLIENT_RBCV}, 1155c965db44STomer Tayar PBF_REG_DBG_SELECT, PBF_REG_DBG_DWORD_ENABLE, 1156c965db44STomer Tayar PBF_REG_DBG_SHIFT, PBF_REG_DBG_FORCE_VALID, 1157c965db44STomer Tayar PBF_REG_DBG_FORCE_FRAME, 1158c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 15 1159c965db44STomer Tayar }; 1160c965db44STomer Tayar 1161c965db44STomer Tayar static struct block_defs block_rdif_defs = { 1162be086e7cSMintz, Yuval "rdif", 1163da090917STomer Tayar {true, true, true}, false, 0, 1164da090917STomer Tayar {DBG_BUS_CLIENT_RBCT, DBG_BUS_CLIENT_RBCM, DBG_BUS_CLIENT_RBCM}, 1165c965db44STomer Tayar RDIF_REG_DBG_SELECT, RDIF_REG_DBG_DWORD_ENABLE, 1166c965db44STomer Tayar RDIF_REG_DBG_SHIFT, RDIF_REG_DBG_FORCE_VALID, 1167c965db44STomer Tayar RDIF_REG_DBG_FORCE_FRAME, 1168c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 16 1169c965db44STomer Tayar }; 1170c965db44STomer Tayar 1171c965db44STomer Tayar static struct block_defs block_tdif_defs = { 1172be086e7cSMintz, Yuval "tdif", 1173da090917STomer Tayar {true, true, true}, false, 0, 1174da090917STomer Tayar {DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS, DBG_BUS_CLIENT_RBCS}, 1175c965db44STomer Tayar TDIF_REG_DBG_SELECT, TDIF_REG_DBG_DWORD_ENABLE, 1176c965db44STomer Tayar TDIF_REG_DBG_SHIFT, TDIF_REG_DBG_FORCE_VALID, 1177c965db44STomer Tayar TDIF_REG_DBG_FORCE_FRAME, 1178c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 17 1179c965db44STomer Tayar }; 1180c965db44STomer Tayar 1181c965db44STomer Tayar static struct block_defs block_cdu_defs = { 1182be086e7cSMintz, Yuval "cdu", 1183da090917STomer Tayar {true, true, true}, false, 0, 1184da090917STomer Tayar {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF}, 1185c965db44STomer Tayar CDU_REG_DBG_SELECT, CDU_REG_DBG_DWORD_ENABLE, 1186c965db44STomer Tayar CDU_REG_DBG_SHIFT, CDU_REG_DBG_FORCE_VALID, 1187c965db44STomer Tayar CDU_REG_DBG_FORCE_FRAME, 1188c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 23 1189c965db44STomer Tayar }; 1190c965db44STomer Tayar 1191c965db44STomer Tayar static struct block_defs block_ccfc_defs = { 1192be086e7cSMintz, Yuval "ccfc", 1193da090917STomer Tayar {true, true, true}, false, 0, 1194da090917STomer Tayar {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF}, 1195c965db44STomer Tayar CCFC_REG_DBG_SELECT, CCFC_REG_DBG_DWORD_ENABLE, 1196c965db44STomer Tayar CCFC_REG_DBG_SHIFT, CCFC_REG_DBG_FORCE_VALID, 1197c965db44STomer Tayar CCFC_REG_DBG_FORCE_FRAME, 1198c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 24 1199c965db44STomer Tayar }; 1200c965db44STomer Tayar 1201c965db44STomer Tayar static struct block_defs block_tcfc_defs = { 1202be086e7cSMintz, Yuval "tcfc", 1203da090917STomer Tayar {true, true, true}, false, 0, 1204da090917STomer Tayar {DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF, DBG_BUS_CLIENT_RBCF}, 1205c965db44STomer Tayar TCFC_REG_DBG_SELECT, TCFC_REG_DBG_DWORD_ENABLE, 1206c965db44STomer Tayar TCFC_REG_DBG_SHIFT, TCFC_REG_DBG_FORCE_VALID, 1207c965db44STomer Tayar TCFC_REG_DBG_FORCE_FRAME, 1208c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 25 1209c965db44STomer Tayar }; 1210c965db44STomer Tayar 1211c965db44STomer Tayar static struct block_defs block_igu_defs = { 1212be086e7cSMintz, Yuval "igu", 1213da090917STomer Tayar {true, true, true}, false, 0, 1214da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 1215c965db44STomer Tayar IGU_REG_DBG_SELECT, IGU_REG_DBG_DWORD_ENABLE, 1216c965db44STomer Tayar IGU_REG_DBG_SHIFT, IGU_REG_DBG_FORCE_VALID, 1217c965db44STomer Tayar IGU_REG_DBG_FORCE_FRAME, 1218c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 27 1219c965db44STomer Tayar }; 1220c965db44STomer Tayar 1221c965db44STomer Tayar static struct block_defs block_cau_defs = { 1222be086e7cSMintz, Yuval "cau", 1223da090917STomer Tayar {true, true, true}, false, 0, 1224da090917STomer Tayar {DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP, DBG_BUS_CLIENT_RBCP}, 1225c965db44STomer Tayar CAU_REG_DBG_SELECT, CAU_REG_DBG_DWORD_ENABLE, 1226c965db44STomer Tayar CAU_REG_DBG_SHIFT, CAU_REG_DBG_FORCE_VALID, 1227c965db44STomer Tayar CAU_REG_DBG_FORCE_FRAME, 1228c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 19 1229c965db44STomer Tayar }; 1230c965db44STomer Tayar 1231a2e7699eSTomer Tayar static struct block_defs block_rgfs_defs = { 1232da090917STomer Tayar "rgfs", {false, false, true}, false, 0, 1233da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1234a2e7699eSTomer Tayar 0, 0, 0, 0, 0, 1235da090917STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 29 1236a2e7699eSTomer Tayar }; 1237a2e7699eSTomer Tayar 1238a2e7699eSTomer Tayar static struct block_defs block_rgsrc_defs = { 1239da090917STomer Tayar "rgsrc", 1240da090917STomer Tayar {false, false, true}, false, 0, 1241da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH}, 1242da090917STomer Tayar RGSRC_REG_DBG_SELECT_E5, RGSRC_REG_DBG_DWORD_ENABLE_E5, 1243da090917STomer Tayar RGSRC_REG_DBG_SHIFT_E5, RGSRC_REG_DBG_FORCE_VALID_E5, 1244da090917STomer Tayar RGSRC_REG_DBG_FORCE_FRAME_E5, 1245da090917STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 1246da090917STomer Tayar 30 1247a2e7699eSTomer Tayar }; 1248a2e7699eSTomer Tayar 1249a2e7699eSTomer Tayar static struct block_defs block_tgfs_defs = { 1250da090917STomer Tayar "tgfs", {false, false, true}, false, 0, 1251da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1252a2e7699eSTomer Tayar 0, 0, 0, 0, 0, 1253da090917STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 30 1254a2e7699eSTomer Tayar }; 1255a2e7699eSTomer Tayar 1256a2e7699eSTomer Tayar static struct block_defs block_tgsrc_defs = { 1257da090917STomer Tayar "tgsrc", 1258da090917STomer Tayar {false, false, true}, false, 0, 1259da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCV}, 1260da090917STomer Tayar TGSRC_REG_DBG_SELECT_E5, TGSRC_REG_DBG_DWORD_ENABLE_E5, 1261da090917STomer Tayar TGSRC_REG_DBG_SHIFT_E5, TGSRC_REG_DBG_FORCE_VALID_E5, 1262da090917STomer Tayar TGSRC_REG_DBG_FORCE_FRAME_E5, 1263da090917STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 1264da090917STomer Tayar 31 1265a2e7699eSTomer Tayar }; 1266a2e7699eSTomer Tayar 1267c965db44STomer Tayar static struct block_defs block_umac_defs = { 1268be086e7cSMintz, Yuval "umac", 1269da090917STomer Tayar {true, true, true}, false, 0, 1270da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ, 1271da090917STomer Tayar DBG_BUS_CLIENT_RBCZ}, 127221dd79e8STomer Tayar UMAC_REG_DBG_SELECT_K2_E5, UMAC_REG_DBG_DWORD_ENABLE_K2_E5, 127321dd79e8STomer Tayar UMAC_REG_DBG_SHIFT_K2_E5, UMAC_REG_DBG_FORCE_VALID_K2_E5, 127421dd79e8STomer Tayar UMAC_REG_DBG_FORCE_FRAME_K2_E5, 1275c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV, 6 1276c965db44STomer Tayar }; 1277c965db44STomer Tayar 1278c965db44STomer Tayar static struct block_defs block_xmac_defs = { 1279da090917STomer Tayar "xmac", {true, false, false}, false, 0, 1280da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1281c965db44STomer Tayar 0, 0, 0, 0, 0, 1282c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 1283c965db44STomer Tayar }; 1284c965db44STomer Tayar 1285c965db44STomer Tayar static struct block_defs block_dbg_defs = { 1286da090917STomer Tayar "dbg", {true, true, true}, false, 0, 1287da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1288c965db44STomer Tayar 0, 0, 0, 0, 0, 1289c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 3 1290c965db44STomer Tayar }; 1291c965db44STomer Tayar 1292c965db44STomer Tayar static struct block_defs block_nig_defs = { 1293be086e7cSMintz, Yuval "nig", 1294da090917STomer Tayar {true, true, true}, false, 0, 1295da090917STomer Tayar {DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN, DBG_BUS_CLIENT_RBCN}, 1296c965db44STomer Tayar NIG_REG_DBG_SELECT, NIG_REG_DBG_DWORD_ENABLE, 1297c965db44STomer Tayar NIG_REG_DBG_SHIFT, NIG_REG_DBG_FORCE_VALID, 1298c965db44STomer Tayar NIG_REG_DBG_FORCE_FRAME, 1299c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 0 1300c965db44STomer Tayar }; 1301c965db44STomer Tayar 1302c965db44STomer Tayar static struct block_defs block_wol_defs = { 1303be086e7cSMintz, Yuval "wol", 1304da090917STomer Tayar {false, true, true}, false, 0, 1305da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ}, 130621dd79e8STomer Tayar WOL_REG_DBG_SELECT_K2_E5, WOL_REG_DBG_DWORD_ENABLE_K2_E5, 130721dd79e8STomer Tayar WOL_REG_DBG_SHIFT_K2_E5, WOL_REG_DBG_FORCE_VALID_K2_E5, 130821dd79e8STomer Tayar WOL_REG_DBG_FORCE_FRAME_K2_E5, 1309c965db44STomer Tayar true, true, DBG_RESET_REG_MISC_PL_PDA_VAUX, 7 1310c965db44STomer Tayar }; 1311c965db44STomer Tayar 1312c965db44STomer Tayar static struct block_defs block_bmbn_defs = { 1313be086e7cSMintz, Yuval "bmbn", 1314da090917STomer Tayar {false, true, true}, false, 0, 1315da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCB, 1316da090917STomer Tayar DBG_BUS_CLIENT_RBCB}, 131721dd79e8STomer Tayar BMBN_REG_DBG_SELECT_K2_E5, BMBN_REG_DBG_DWORD_ENABLE_K2_E5, 131821dd79e8STomer Tayar BMBN_REG_DBG_SHIFT_K2_E5, BMBN_REG_DBG_FORCE_VALID_K2_E5, 131921dd79e8STomer Tayar BMBN_REG_DBG_FORCE_FRAME_K2_E5, 1320c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 1321c965db44STomer Tayar }; 1322c965db44STomer Tayar 1323c965db44STomer Tayar static struct block_defs block_ipc_defs = { 1324da090917STomer Tayar "ipc", {true, true, true}, false, 0, 1325da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1326c965db44STomer Tayar 0, 0, 0, 0, 0, 1327c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_UA, 8 1328c965db44STomer Tayar }; 1329c965db44STomer Tayar 1330c965db44STomer Tayar static struct block_defs block_nwm_defs = { 1331be086e7cSMintz, Yuval "nwm", 1332da090917STomer Tayar {false, true, true}, false, 0, 1333da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW, DBG_BUS_CLIENT_RBCW}, 133421dd79e8STomer Tayar NWM_REG_DBG_SELECT_K2_E5, NWM_REG_DBG_DWORD_ENABLE_K2_E5, 133521dd79e8STomer Tayar NWM_REG_DBG_SHIFT_K2_E5, NWM_REG_DBG_FORCE_VALID_K2_E5, 133621dd79e8STomer Tayar NWM_REG_DBG_FORCE_FRAME_K2_E5, 1337c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV_2, 0 1338c965db44STomer Tayar }; 1339c965db44STomer Tayar 1340c965db44STomer Tayar static struct block_defs block_nws_defs = { 1341be086e7cSMintz, Yuval "nws", 1342da090917STomer Tayar {false, true, true}, false, 0, 1343da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCW, DBG_BUS_CLIENT_RBCW}, 134421dd79e8STomer Tayar NWS_REG_DBG_SELECT_K2_E5, NWS_REG_DBG_DWORD_ENABLE_K2_E5, 134521dd79e8STomer Tayar NWS_REG_DBG_SHIFT_K2_E5, NWS_REG_DBG_FORCE_VALID_K2_E5, 134621dd79e8STomer Tayar NWS_REG_DBG_FORCE_FRAME_K2_E5, 1347c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV, 12 1348c965db44STomer Tayar }; 1349c965db44STomer Tayar 1350c965db44STomer Tayar static struct block_defs block_ms_defs = { 1351be086e7cSMintz, Yuval "ms", 1352da090917STomer Tayar {false, true, true}, false, 0, 1353da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCZ, DBG_BUS_CLIENT_RBCZ}, 135421dd79e8STomer Tayar MS_REG_DBG_SELECT_K2_E5, MS_REG_DBG_DWORD_ENABLE_K2_E5, 135521dd79e8STomer Tayar MS_REG_DBG_SHIFT_K2_E5, MS_REG_DBG_FORCE_VALID_K2_E5, 135621dd79e8STomer Tayar MS_REG_DBG_FORCE_FRAME_K2_E5, 1357c965db44STomer Tayar true, false, DBG_RESET_REG_MISCS_PL_HV, 13 1358c965db44STomer Tayar }; 1359c965db44STomer Tayar 1360c965db44STomer Tayar static struct block_defs block_phy_pcie_defs = { 1361be086e7cSMintz, Yuval "phy_pcie", 1362da090917STomer Tayar {false, true, true}, false, 0, 1363da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, DBG_BUS_CLIENT_RBCH, 1364da090917STomer Tayar DBG_BUS_CLIENT_RBCH}, 136521dd79e8STomer Tayar PCIE_REG_DBG_COMMON_SELECT_K2_E5, 136621dd79e8STomer Tayar PCIE_REG_DBG_COMMON_DWORD_ENABLE_K2_E5, 136721dd79e8STomer Tayar PCIE_REG_DBG_COMMON_SHIFT_K2_E5, 136821dd79e8STomer Tayar PCIE_REG_DBG_COMMON_FORCE_VALID_K2_E5, 136921dd79e8STomer Tayar PCIE_REG_DBG_COMMON_FORCE_FRAME_K2_E5, 1370c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 1371c965db44STomer Tayar }; 1372c965db44STomer Tayar 1373c965db44STomer Tayar static struct block_defs block_led_defs = { 1374da090917STomer Tayar "led", {false, true, true}, false, 0, 1375da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1376c965db44STomer Tayar 0, 0, 0, 0, 0, 1377be086e7cSMintz, Yuval true, false, DBG_RESET_REG_MISCS_PL_HV, 14 1378be086e7cSMintz, Yuval }; 1379be086e7cSMintz, Yuval 1380be086e7cSMintz, Yuval static struct block_defs block_avs_wrap_defs = { 1381da090917STomer Tayar "avs_wrap", {false, true, false}, false, 0, 1382da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1383be086e7cSMintz, Yuval 0, 0, 0, 0, 0, 1384be086e7cSMintz, Yuval true, false, DBG_RESET_REG_MISCS_PL_UA, 11 1385be086e7cSMintz, Yuval }; 1386be086e7cSMintz, Yuval 1387da090917STomer Tayar static struct block_defs block_pxpreqbus_defs = { 1388da090917STomer Tayar "pxpreqbus", {false, false, false}, false, 0, 1389da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1390da090917STomer Tayar 0, 0, 0, 0, 0, 1391da090917STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 1392da090917STomer Tayar }; 1393da090917STomer Tayar 1394c965db44STomer Tayar static struct block_defs block_misc_aeu_defs = { 1395da090917STomer Tayar "misc_aeu", {true, true, true}, false, 0, 1396da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1397c965db44STomer Tayar 0, 0, 0, 0, 0, 1398c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 1399c965db44STomer Tayar }; 1400c965db44STomer Tayar 1401c965db44STomer Tayar static struct block_defs block_bar0_map_defs = { 1402da090917STomer Tayar "bar0_map", {true, true, true}, false, 0, 1403da090917STomer Tayar {MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS, MAX_DBG_BUS_CLIENTS}, 1404c965db44STomer Tayar 0, 0, 0, 0, 0, 1405c965db44STomer Tayar false, false, MAX_DBG_RESET_REGS, 0 1406c965db44STomer Tayar }; 1407c965db44STomer Tayar 1408c965db44STomer Tayar static struct block_defs *s_block_defs[MAX_BLOCK_ID] = { 1409c965db44STomer Tayar &block_grc_defs, 1410c965db44STomer Tayar &block_miscs_defs, 1411c965db44STomer Tayar &block_misc_defs, 1412c965db44STomer Tayar &block_dbu_defs, 1413c965db44STomer Tayar &block_pglue_b_defs, 1414c965db44STomer Tayar &block_cnig_defs, 1415c965db44STomer Tayar &block_cpmu_defs, 1416c965db44STomer Tayar &block_ncsi_defs, 1417c965db44STomer Tayar &block_opte_defs, 1418c965db44STomer Tayar &block_bmb_defs, 1419c965db44STomer Tayar &block_pcie_defs, 1420c965db44STomer Tayar &block_mcp_defs, 1421c965db44STomer Tayar &block_mcp2_defs, 1422c965db44STomer Tayar &block_pswhst_defs, 1423c965db44STomer Tayar &block_pswhst2_defs, 1424c965db44STomer Tayar &block_pswrd_defs, 1425c965db44STomer Tayar &block_pswrd2_defs, 1426c965db44STomer Tayar &block_pswwr_defs, 1427c965db44STomer Tayar &block_pswwr2_defs, 1428c965db44STomer Tayar &block_pswrq_defs, 1429c965db44STomer Tayar &block_pswrq2_defs, 1430c965db44STomer Tayar &block_pglcs_defs, 1431c965db44STomer Tayar &block_dmae_defs, 1432c965db44STomer Tayar &block_ptu_defs, 1433c965db44STomer Tayar &block_tcm_defs, 1434c965db44STomer Tayar &block_mcm_defs, 1435c965db44STomer Tayar &block_ucm_defs, 1436c965db44STomer Tayar &block_xcm_defs, 1437c965db44STomer Tayar &block_ycm_defs, 1438c965db44STomer Tayar &block_pcm_defs, 1439c965db44STomer Tayar &block_qm_defs, 1440c965db44STomer Tayar &block_tm_defs, 1441c965db44STomer Tayar &block_dorq_defs, 1442c965db44STomer Tayar &block_brb_defs, 1443c965db44STomer Tayar &block_src_defs, 1444c965db44STomer Tayar &block_prs_defs, 1445c965db44STomer Tayar &block_tsdm_defs, 1446c965db44STomer Tayar &block_msdm_defs, 1447c965db44STomer Tayar &block_usdm_defs, 1448c965db44STomer Tayar &block_xsdm_defs, 1449c965db44STomer Tayar &block_ysdm_defs, 1450c965db44STomer Tayar &block_psdm_defs, 1451c965db44STomer Tayar &block_tsem_defs, 1452c965db44STomer Tayar &block_msem_defs, 1453c965db44STomer Tayar &block_usem_defs, 1454c965db44STomer Tayar &block_xsem_defs, 1455c965db44STomer Tayar &block_ysem_defs, 1456c965db44STomer Tayar &block_psem_defs, 1457c965db44STomer Tayar &block_rss_defs, 1458c965db44STomer Tayar &block_tmld_defs, 1459c965db44STomer Tayar &block_muld_defs, 1460c965db44STomer Tayar &block_yuld_defs, 1461c965db44STomer Tayar &block_xyld_defs, 14627b6859fbSMintz, Yuval &block_ptld_defs, 14637b6859fbSMintz, Yuval &block_ypld_defs, 1464c965db44STomer Tayar &block_prm_defs, 1465c965db44STomer Tayar &block_pbf_pb1_defs, 1466c965db44STomer Tayar &block_pbf_pb2_defs, 1467c965db44STomer Tayar &block_rpb_defs, 1468c965db44STomer Tayar &block_btb_defs, 1469c965db44STomer Tayar &block_pbf_defs, 1470c965db44STomer Tayar &block_rdif_defs, 1471c965db44STomer Tayar &block_tdif_defs, 1472c965db44STomer Tayar &block_cdu_defs, 1473c965db44STomer Tayar &block_ccfc_defs, 1474c965db44STomer Tayar &block_tcfc_defs, 1475c965db44STomer Tayar &block_igu_defs, 1476c965db44STomer Tayar &block_cau_defs, 14777b6859fbSMintz, Yuval &block_rgfs_defs, 14787b6859fbSMintz, Yuval &block_rgsrc_defs, 14797b6859fbSMintz, Yuval &block_tgfs_defs, 14807b6859fbSMintz, Yuval &block_tgsrc_defs, 1481c965db44STomer Tayar &block_umac_defs, 1482c965db44STomer Tayar &block_xmac_defs, 1483c965db44STomer Tayar &block_dbg_defs, 1484c965db44STomer Tayar &block_nig_defs, 1485c965db44STomer Tayar &block_wol_defs, 1486c965db44STomer Tayar &block_bmbn_defs, 1487c965db44STomer Tayar &block_ipc_defs, 1488c965db44STomer Tayar &block_nwm_defs, 1489c965db44STomer Tayar &block_nws_defs, 1490c965db44STomer Tayar &block_ms_defs, 1491c965db44STomer Tayar &block_phy_pcie_defs, 1492c965db44STomer Tayar &block_led_defs, 1493be086e7cSMintz, Yuval &block_avs_wrap_defs, 1494da090917STomer Tayar &block_pxpreqbus_defs, 1495c965db44STomer Tayar &block_misc_aeu_defs, 1496c965db44STomer Tayar &block_bar0_map_defs, 1497c965db44STomer Tayar }; 1498c965db44STomer Tayar 1499c965db44STomer Tayar static struct platform_defs s_platform_defs[] = { 1500da090917STomer Tayar {"asic", 1, 256, 32768}, 1501da090917STomer Tayar {"reserved", 0, 0, 0}, 1502da090917STomer Tayar {"reserved2", 0, 0, 0}, 1503da090917STomer Tayar {"reserved3", 0, 0, 0} 1504c965db44STomer Tayar }; 1505c965db44STomer Tayar 1506c965db44STomer Tayar static struct grc_param_defs s_grc_param_defs[] = { 15077b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_TSTORM */ 150850bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 1, 1}, 15097b6859fbSMintz, Yuval 15107b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_MSTORM */ 151150bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 1, 1}, 15127b6859fbSMintz, Yuval 15137b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_USTORM */ 151450bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 1, 1}, 15157b6859fbSMintz, Yuval 15167b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_XSTORM */ 151750bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 1, 1}, 15187b6859fbSMintz, Yuval 15197b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_YSTORM */ 152050bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 1, 1}, 15217b6859fbSMintz, Yuval 15227b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_PSTORM */ 152350bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 1, 1}, 15247b6859fbSMintz, Yuval 15257b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_REGS */ 152650bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15277b6859fbSMintz, Yuval 15287b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_RAM */ 152950bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15307b6859fbSMintz, Yuval 15317b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_PBUF */ 153250bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15337b6859fbSMintz, Yuval 15347b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_IOR */ 153550bc60cbSMichal Kalderon {{0, 0, 0}, 0, 1, false, false, 0, 1}, 15367b6859fbSMintz, Yuval 15377b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_VFC */ 153850bc60cbSMichal Kalderon {{0, 0, 0}, 0, 1, false, false, 0, 1}, 15397b6859fbSMintz, Yuval 15407b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_CM_CTX */ 154150bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15427b6859fbSMintz, Yuval 15437b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_ILT */ 154450bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15457b6859fbSMintz, Yuval 15467b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_RSS */ 154750bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15487b6859fbSMintz, Yuval 15497b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_CAU */ 155050bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15517b6859fbSMintz, Yuval 15527b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_QM */ 155350bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15547b6859fbSMintz, Yuval 15557b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_MCP */ 155650bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15577b6859fbSMintz, Yuval 155850bc60cbSMichal Kalderon /* DBG_GRC_PARAM_MCP_TRACE_META_SIZE */ 155950bc60cbSMichal Kalderon {{1, 1, 1}, 1, 0xffffffff, false, true, 0, 1}, 15607b6859fbSMintz, Yuval 15617b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_CFC */ 156250bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15637b6859fbSMintz, Yuval 15647b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_IGU */ 156550bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15667b6859fbSMintz, Yuval 15677b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_BRB */ 156850bc60cbSMichal Kalderon {{0, 0, 0}, 0, 1, false, false, 0, 1}, 15697b6859fbSMintz, Yuval 15707b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_BTB */ 157150bc60cbSMichal Kalderon {{0, 0, 0}, 0, 1, false, false, 0, 1}, 15727b6859fbSMintz, Yuval 15737b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_BMB */ 1574d52c89f1SMichal Kalderon {{0, 0, 0}, 0, 1, false, false, 0, 0}, 15757b6859fbSMintz, Yuval 15767b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_NIG */ 157750bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15787b6859fbSMintz, Yuval 15797b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_MULD */ 158050bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15817b6859fbSMintz, Yuval 15827b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_PRS */ 158350bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15847b6859fbSMintz, Yuval 15857b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_DMAE */ 158650bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15877b6859fbSMintz, Yuval 15887b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_TM */ 158950bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15907b6859fbSMintz, Yuval 15917b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_SDM */ 159250bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15937b6859fbSMintz, Yuval 15947b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_DIF */ 159550bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15967b6859fbSMintz, Yuval 15977b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_STATIC */ 159850bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 15997b6859fbSMintz, Yuval 16007b6859fbSMintz, Yuval /* DBG_GRC_PARAM_UNSTALL */ 160150bc60cbSMichal Kalderon {{0, 0, 0}, 0, 1, false, false, 0, 0}, 16027b6859fbSMintz, Yuval 16037b6859fbSMintz, Yuval /* DBG_GRC_PARAM_NUM_LCIDS */ 160450bc60cbSMichal Kalderon {{MAX_LCIDS, MAX_LCIDS, MAX_LCIDS}, 1, MAX_LCIDS, false, false, 160550bc60cbSMichal Kalderon MAX_LCIDS, MAX_LCIDS}, 16067b6859fbSMintz, Yuval 16077b6859fbSMintz, Yuval /* DBG_GRC_PARAM_NUM_LTIDS */ 160850bc60cbSMichal Kalderon {{MAX_LTIDS, MAX_LTIDS, MAX_LTIDS}, 1, MAX_LTIDS, false, false, 160950bc60cbSMichal Kalderon MAX_LTIDS, MAX_LTIDS}, 16107b6859fbSMintz, Yuval 16117b6859fbSMintz, Yuval /* DBG_GRC_PARAM_EXCLUDE_ALL */ 161250bc60cbSMichal Kalderon {{0, 0, 0}, 0, 1, true, false, 0, 0}, 16137b6859fbSMintz, Yuval 16147b6859fbSMintz, Yuval /* DBG_GRC_PARAM_CRASH */ 161550bc60cbSMichal Kalderon {{0, 0, 0}, 0, 1, true, false, 0, 0}, 16167b6859fbSMintz, Yuval 16177b6859fbSMintz, Yuval /* DBG_GRC_PARAM_PARITY_SAFE */ 161850bc60cbSMichal Kalderon {{0, 0, 0}, 0, 1, false, false, 1, 0}, 16197b6859fbSMintz, Yuval 16207b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_CM */ 162150bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 16227b6859fbSMintz, Yuval 16237b6859fbSMintz, Yuval /* DBG_GRC_PARAM_DUMP_PHY */ 162450bc60cbSMichal Kalderon {{1, 1, 1}, 0, 1, false, false, 0, 1}, 16257b6859fbSMintz, Yuval 16267b6859fbSMintz, Yuval /* DBG_GRC_PARAM_NO_MCP */ 162750bc60cbSMichal Kalderon {{0, 0, 0}, 0, 1, false, false, 0, 0}, 16287b6859fbSMintz, Yuval 16297b6859fbSMintz, Yuval /* DBG_GRC_PARAM_NO_FW_VER */ 163050bc60cbSMichal Kalderon {{0, 0, 0}, 0, 1, false, false, 0, 0} 1631c965db44STomer Tayar }; 1632c965db44STomer Tayar 1633c965db44STomer Tayar static struct rss_mem_defs s_rss_mem_defs[] = { 1634da090917STomer Tayar { "rss_mem_cid", "rss_cid", 0, 32, 1635da090917STomer Tayar {256, 320, 512} }, 16367b6859fbSMintz, Yuval 1637da090917STomer Tayar { "rss_mem_key_msb", "rss_key", 1024, 256, 1638da090917STomer Tayar {128, 208, 257} }, 16397b6859fbSMintz, Yuval 1640da090917STomer Tayar { "rss_mem_key_lsb", "rss_key", 2048, 64, 1641da090917STomer Tayar {128, 208, 257} }, 16427b6859fbSMintz, Yuval 1643da090917STomer Tayar { "rss_mem_info", "rss_info", 3072, 16, 1644da090917STomer Tayar {128, 208, 256} }, 16457b6859fbSMintz, Yuval 1646da090917STomer Tayar { "rss_mem_ind", "rss_ind", 4096, 16, 1647da090917STomer Tayar {16384, 26624, 32768} } 1648c965db44STomer Tayar }; 1649c965db44STomer Tayar 1650c965db44STomer Tayar static struct vfc_ram_defs s_vfc_ram_defs[] = { 1651c965db44STomer Tayar {"vfc_ram_tt1", "vfc_ram", 0, 512}, 1652c965db44STomer Tayar {"vfc_ram_mtt2", "vfc_ram", 512, 128}, 1653c965db44STomer Tayar {"vfc_ram_stt2", "vfc_ram", 640, 32}, 1654c965db44STomer Tayar {"vfc_ram_ro_vect", "vfc_ram", 672, 32} 1655c965db44STomer Tayar }; 1656c965db44STomer Tayar 1657c965db44STomer Tayar static struct big_ram_defs s_big_ram_defs[] = { 1658c965db44STomer Tayar { "BRB", MEM_GROUP_BRB_MEM, MEM_GROUP_BRB_RAM, DBG_GRC_PARAM_DUMP_BRB, 1659c965db44STomer Tayar BRB_REG_BIG_RAM_ADDRESS, BRB_REG_BIG_RAM_DATA, 1660da090917STomer Tayar MISC_REG_BLOCK_256B_EN, {0, 0, 0}, 1661da090917STomer Tayar {153600, 180224, 282624} }, 16627b6859fbSMintz, Yuval 1663c965db44STomer Tayar { "BTB", MEM_GROUP_BTB_MEM, MEM_GROUP_BTB_RAM, DBG_GRC_PARAM_DUMP_BTB, 1664c965db44STomer Tayar BTB_REG_BIG_RAM_ADDRESS, BTB_REG_BIG_RAM_DATA, 1665da090917STomer Tayar MISC_REG_BLOCK_256B_EN, {0, 1, 1}, 1666da090917STomer Tayar {92160, 117760, 168960} }, 16677b6859fbSMintz, Yuval 1668c965db44STomer Tayar { "BMB", MEM_GROUP_BMB_MEM, MEM_GROUP_BMB_RAM, DBG_GRC_PARAM_DUMP_BMB, 1669c965db44STomer Tayar BMB_REG_BIG_RAM_ADDRESS, BMB_REG_BIG_RAM_DATA, 1670da090917STomer Tayar MISCS_REG_BLOCK_256B_EN, {0, 0, 0}, 1671da090917STomer Tayar {36864, 36864, 36864} } 1672c965db44STomer Tayar }; 1673c965db44STomer Tayar 1674c965db44STomer Tayar static struct reset_reg_defs s_reset_regs_defs[] = { 16757b6859fbSMintz, Yuval /* DBG_RESET_REG_MISCS_PL_UA */ 1676da090917STomer Tayar { MISCS_REG_RESET_PL_UA, 1677da090917STomer Tayar {true, true, true}, {0x0, 0x0, 0x0} }, 16787b6859fbSMintz, Yuval 16797b6859fbSMintz, Yuval /* DBG_RESET_REG_MISCS_PL_HV */ 1680da090917STomer Tayar { MISCS_REG_RESET_PL_HV, 1681da090917STomer Tayar {true, true, true}, {0x0, 0x400, 0x600} }, 16827b6859fbSMintz, Yuval 16837b6859fbSMintz, Yuval /* DBG_RESET_REG_MISCS_PL_HV_2 */ 1684da090917STomer Tayar { MISCS_REG_RESET_PL_HV_2_K2_E5, 1685da090917STomer Tayar {false, true, true}, {0x0, 0x0, 0x0} }, 16867b6859fbSMintz, Yuval 16877b6859fbSMintz, Yuval /* DBG_RESET_REG_MISC_PL_UA */ 1688da090917STomer Tayar { MISC_REG_RESET_PL_UA, 1689da090917STomer Tayar {true, true, true}, {0x0, 0x0, 0x0} }, 16907b6859fbSMintz, Yuval 16917b6859fbSMintz, Yuval /* DBG_RESET_REG_MISC_PL_HV */ 1692da090917STomer Tayar { MISC_REG_RESET_PL_HV, 1693da090917STomer Tayar {true, true, true}, {0x0, 0x0, 0x0} }, 16947b6859fbSMintz, Yuval 16957b6859fbSMintz, Yuval /* DBG_RESET_REG_MISC_PL_PDA_VMAIN_1 */ 1696da090917STomer Tayar { MISC_REG_RESET_PL_PDA_VMAIN_1, 1697da090917STomer Tayar {true, true, true}, {0x4404040, 0x4404040, 0x404040} }, 16987b6859fbSMintz, Yuval 16997b6859fbSMintz, Yuval /* DBG_RESET_REG_MISC_PL_PDA_VMAIN_2 */ 1700da090917STomer Tayar { MISC_REG_RESET_PL_PDA_VMAIN_2, 1701da090917STomer Tayar {true, true, true}, {0x7, 0x7c00007, 0x5c08007} }, 17027b6859fbSMintz, Yuval 17037b6859fbSMintz, Yuval /* DBG_RESET_REG_MISC_PL_PDA_VAUX */ 1704da090917STomer Tayar { MISC_REG_RESET_PL_PDA_VAUX, 1705da090917STomer Tayar {true, true, true}, {0x2, 0x2, 0x2} }, 1706c965db44STomer Tayar }; 1707c965db44STomer Tayar 1708c965db44STomer Tayar static struct phy_defs s_phy_defs[] = { 17097b6859fbSMintz, Yuval {"nw_phy", NWS_REG_NWS_CMU_K2, 171021dd79e8STomer Tayar PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_7_0_K2_E5, 171121dd79e8STomer Tayar PHY_NW_IP_REG_PHY0_TOP_TBUS_ADDR_15_8_K2_E5, 171221dd79e8STomer Tayar PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_7_0_K2_E5, 171321dd79e8STomer Tayar PHY_NW_IP_REG_PHY0_TOP_TBUS_DATA_11_8_K2_E5}, 171421dd79e8STomer Tayar {"sgmii_phy", MS_REG_MS_CMU_K2_E5, 171521dd79e8STomer Tayar PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X132_K2_E5, 171621dd79e8STomer Tayar PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X133_K2_E5, 171721dd79e8STomer Tayar PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X130_K2_E5, 171821dd79e8STomer Tayar PHY_SGMII_IP_REG_AHB_CMU_CSR_0_X131_K2_E5}, 171921dd79e8STomer Tayar {"pcie_phy0", PHY_PCIE_REG_PHY0_K2_E5, 172021dd79e8STomer Tayar PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5, 172121dd79e8STomer Tayar PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5, 172221dd79e8STomer Tayar PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5, 172321dd79e8STomer Tayar PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5}, 172421dd79e8STomer Tayar {"pcie_phy1", PHY_PCIE_REG_PHY1_K2_E5, 172521dd79e8STomer Tayar PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X132_K2_E5, 172621dd79e8STomer Tayar PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X133_K2_E5, 172721dd79e8STomer Tayar PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X130_K2_E5, 172821dd79e8STomer Tayar PHY_PCIE_IP_REG_AHB_CMU_CSR_0_X131_K2_E5}, 1729c965db44STomer Tayar }; 1730c965db44STomer Tayar 1731d52c89f1SMichal Kalderon static struct split_type_defs s_split_type_defs[] = { 1732d52c89f1SMichal Kalderon /* SPLIT_TYPE_NONE */ 1733d52c89f1SMichal Kalderon {"eng"}, 1734d52c89f1SMichal Kalderon 1735d52c89f1SMichal Kalderon /* SPLIT_TYPE_PORT */ 1736d52c89f1SMichal Kalderon {"port"}, 1737d52c89f1SMichal Kalderon 1738d52c89f1SMichal Kalderon /* SPLIT_TYPE_PF */ 1739d52c89f1SMichal Kalderon {"pf"}, 1740d52c89f1SMichal Kalderon 1741d52c89f1SMichal Kalderon /* SPLIT_TYPE_PORT_PF */ 1742d52c89f1SMichal Kalderon {"port"}, 1743d52c89f1SMichal Kalderon 1744d52c89f1SMichal Kalderon /* SPLIT_TYPE_VF */ 1745d52c89f1SMichal Kalderon {"vf"} 1746d52c89f1SMichal Kalderon }; 1747d52c89f1SMichal Kalderon 1748c965db44STomer Tayar /**************************** Private Functions ******************************/ 1749c965db44STomer Tayar 1750c965db44STomer Tayar /* Reads and returns a single dword from the specified unaligned buffer */ 1751c965db44STomer Tayar static u32 qed_read_unaligned_dword(u8 *buf) 1752c965db44STomer Tayar { 1753c965db44STomer Tayar u32 dword; 1754c965db44STomer Tayar 1755c965db44STomer Tayar memcpy((u8 *)&dword, buf, sizeof(dword)); 1756c965db44STomer Tayar return dword; 1757c965db44STomer Tayar } 1758c965db44STomer Tayar 17593b86bd07SSudarsana Reddy Kalluru /* Sets the value of the specified GRC param */ 17603b86bd07SSudarsana Reddy Kalluru static void qed_grc_set_param(struct qed_hwfn *p_hwfn, 17613b86bd07SSudarsana Reddy Kalluru enum dbg_grc_params grc_param, u32 val) 17623b86bd07SSudarsana Reddy Kalluru { 17633b86bd07SSudarsana Reddy Kalluru struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 17643b86bd07SSudarsana Reddy Kalluru 17653b86bd07SSudarsana Reddy Kalluru dev_data->grc.param_val[grc_param] = val; 17663b86bd07SSudarsana Reddy Kalluru } 17673b86bd07SSudarsana Reddy Kalluru 1768be086e7cSMintz, Yuval /* Returns the value of the specified GRC param */ 1769be086e7cSMintz, Yuval static u32 qed_grc_get_param(struct qed_hwfn *p_hwfn, 1770be086e7cSMintz, Yuval enum dbg_grc_params grc_param) 1771be086e7cSMintz, Yuval { 1772be086e7cSMintz, Yuval struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 1773be086e7cSMintz, Yuval 1774be086e7cSMintz, Yuval return dev_data->grc.param_val[grc_param]; 1775be086e7cSMintz, Yuval } 1776be086e7cSMintz, Yuval 1777be086e7cSMintz, Yuval /* Initializes the GRC parameters */ 1778be086e7cSMintz, Yuval static void qed_dbg_grc_init_params(struct qed_hwfn *p_hwfn) 1779be086e7cSMintz, Yuval { 1780be086e7cSMintz, Yuval struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 1781be086e7cSMintz, Yuval 1782be086e7cSMintz, Yuval if (!dev_data->grc.params_initialized) { 1783be086e7cSMintz, Yuval qed_dbg_grc_set_params_default(p_hwfn); 1784be086e7cSMintz, Yuval dev_data->grc.params_initialized = 1; 1785be086e7cSMintz, Yuval } 1786be086e7cSMintz, Yuval } 1787be086e7cSMintz, Yuval 1788c965db44STomer Tayar /* Initializes debug data for the specified device */ 1789c965db44STomer Tayar static enum dbg_status qed_dbg_dev_init(struct qed_hwfn *p_hwfn, 1790c965db44STomer Tayar struct qed_ptt *p_ptt) 1791c965db44STomer Tayar { 1792c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 1793d52c89f1SMichal Kalderon u8 num_pfs = 0, max_pfs_per_port = 0; 1794c965db44STomer Tayar 1795c965db44STomer Tayar if (dev_data->initialized) 1796c965db44STomer Tayar return DBG_STATUS_OK; 1797c965db44STomer Tayar 1798d52c89f1SMichal Kalderon /* Set chip */ 1799c965db44STomer Tayar if (QED_IS_K2(p_hwfn->cdev)) { 1800c965db44STomer Tayar dev_data->chip_id = CHIP_K2; 1801c965db44STomer Tayar dev_data->mode_enable[MODE_K2] = 1; 1802d52c89f1SMichal Kalderon dev_data->num_vfs = MAX_NUM_VFS_K2; 1803d52c89f1SMichal Kalderon num_pfs = MAX_NUM_PFS_K2; 1804d52c89f1SMichal Kalderon max_pfs_per_port = MAX_NUM_PFS_K2 / 2; 1805c965db44STomer Tayar } else if (QED_IS_BB_B0(p_hwfn->cdev)) { 18067b6859fbSMintz, Yuval dev_data->chip_id = CHIP_BB; 18079c79ddaaSMintz, Yuval dev_data->mode_enable[MODE_BB] = 1; 1808d52c89f1SMichal Kalderon dev_data->num_vfs = MAX_NUM_VFS_BB; 1809d52c89f1SMichal Kalderon num_pfs = MAX_NUM_PFS_BB; 1810d52c89f1SMichal Kalderon max_pfs_per_port = MAX_NUM_PFS_BB; 1811c965db44STomer Tayar } else { 1812c965db44STomer Tayar return DBG_STATUS_UNKNOWN_CHIP; 1813c965db44STomer Tayar } 1814c965db44STomer Tayar 1815d52c89f1SMichal Kalderon /* Set platofrm */ 1816c965db44STomer Tayar dev_data->platform_id = PLATFORM_ASIC; 1817c965db44STomer Tayar dev_data->mode_enable[MODE_ASIC] = 1; 1818be086e7cSMintz, Yuval 1819d52c89f1SMichal Kalderon /* Set port mode */ 1820d52c89f1SMichal Kalderon switch (qed_rd(p_hwfn, p_ptt, MISC_REG_PORT_MODE)) { 1821d52c89f1SMichal Kalderon case 0: 1822d52c89f1SMichal Kalderon dev_data->mode_enable[MODE_PORTS_PER_ENG_1] = 1; 1823d52c89f1SMichal Kalderon break; 1824d52c89f1SMichal Kalderon case 1: 1825d52c89f1SMichal Kalderon dev_data->mode_enable[MODE_PORTS_PER_ENG_2] = 1; 1826d52c89f1SMichal Kalderon break; 1827d52c89f1SMichal Kalderon case 2: 1828d52c89f1SMichal Kalderon dev_data->mode_enable[MODE_PORTS_PER_ENG_4] = 1; 1829d52c89f1SMichal Kalderon break; 1830d52c89f1SMichal Kalderon } 1831d52c89f1SMichal Kalderon 1832d52c89f1SMichal Kalderon /* Set 100G mode */ 1833d52c89f1SMichal Kalderon if (dev_data->chip_id == CHIP_BB && 1834d52c89f1SMichal Kalderon qed_rd(p_hwfn, p_ptt, CNIG_REG_NW_PORT_MODE_BB) == 2) 1835d52c89f1SMichal Kalderon dev_data->mode_enable[MODE_100G] = 1; 1836d52c89f1SMichal Kalderon 1837d52c89f1SMichal Kalderon /* Set number of ports */ 1838d52c89f1SMichal Kalderon if (dev_data->mode_enable[MODE_PORTS_PER_ENG_1] || 1839d52c89f1SMichal Kalderon dev_data->mode_enable[MODE_100G]) 1840d52c89f1SMichal Kalderon dev_data->num_ports = 1; 1841d52c89f1SMichal Kalderon else if (dev_data->mode_enable[MODE_PORTS_PER_ENG_2]) 1842d52c89f1SMichal Kalderon dev_data->num_ports = 2; 1843d52c89f1SMichal Kalderon else if (dev_data->mode_enable[MODE_PORTS_PER_ENG_4]) 1844d52c89f1SMichal Kalderon dev_data->num_ports = 4; 1845d52c89f1SMichal Kalderon 1846d52c89f1SMichal Kalderon /* Set number of PFs per port */ 1847d52c89f1SMichal Kalderon dev_data->num_pfs_per_port = min_t(u32, 1848d52c89f1SMichal Kalderon num_pfs / dev_data->num_ports, 1849d52c89f1SMichal Kalderon max_pfs_per_port); 1850d52c89f1SMichal Kalderon 1851be086e7cSMintz, Yuval /* Initializes the GRC parameters */ 1852be086e7cSMintz, Yuval qed_dbg_grc_init_params(p_hwfn); 1853be086e7cSMintz, Yuval 1854da090917STomer Tayar dev_data->use_dmae = true; 1855da090917STomer Tayar dev_data->initialized = 1; 18567b6859fbSMintz, Yuval 1857c965db44STomer Tayar return DBG_STATUS_OK; 1858c965db44STomer Tayar } 1859c965db44STomer Tayar 18607b6859fbSMintz, Yuval static struct dbg_bus_block *get_dbg_bus_block_desc(struct qed_hwfn *p_hwfn, 18617b6859fbSMintz, Yuval enum block_id block_id) 18627b6859fbSMintz, Yuval { 18637b6859fbSMintz, Yuval struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 18647b6859fbSMintz, Yuval 18657b6859fbSMintz, Yuval return (struct dbg_bus_block *)&dbg_bus_blocks[block_id * 18667b6859fbSMintz, Yuval MAX_CHIP_IDS + 18677b6859fbSMintz, Yuval dev_data->chip_id]; 18687b6859fbSMintz, Yuval } 18697b6859fbSMintz, Yuval 1870c965db44STomer Tayar /* Reads the FW info structure for the specified Storm from the chip, 1871c965db44STomer Tayar * and writes it to the specified fw_info pointer. 1872c965db44STomer Tayar */ 1873d52c89f1SMichal Kalderon static void qed_read_storm_fw_info(struct qed_hwfn *p_hwfn, 1874c965db44STomer Tayar struct qed_ptt *p_ptt, 1875c965db44STomer Tayar u8 storm_id, struct fw_info *fw_info) 1876c965db44STomer Tayar { 18777b6859fbSMintz, Yuval struct storm_defs *storm = &s_storm_defs[storm_id]; 1878c965db44STomer Tayar struct fw_info_location fw_info_location; 18797b6859fbSMintz, Yuval u32 addr, i, *dest; 1880c965db44STomer Tayar 1881c965db44STomer Tayar memset(&fw_info_location, 0, sizeof(fw_info_location)); 1882c965db44STomer Tayar memset(fw_info, 0, sizeof(*fw_info)); 18837b6859fbSMintz, Yuval 18847b6859fbSMintz, Yuval /* Read first the address that points to fw_info location. 18857b6859fbSMintz, Yuval * The address is located in the last line of the Storm RAM. 18867b6859fbSMintz, Yuval */ 18877b6859fbSMintz, Yuval addr = storm->sem_fast_mem_addr + SEM_FAST_REG_INT_RAM + 188821dd79e8STomer Tayar DWORDS_TO_BYTES(SEM_FAST_REG_INT_RAM_SIZE_BB_K2) - 18897b6859fbSMintz, Yuval sizeof(fw_info_location); 18907b6859fbSMintz, Yuval dest = (u32 *)&fw_info_location; 18917b6859fbSMintz, Yuval 1892c965db44STomer Tayar for (i = 0; i < BYTES_TO_DWORDS(sizeof(fw_info_location)); 1893c965db44STomer Tayar i++, addr += BYTES_IN_DWORD) 1894c965db44STomer Tayar dest[i] = qed_rd(p_hwfn, p_ptt, addr); 18957b6859fbSMintz, Yuval 18967b6859fbSMintz, Yuval /* Read FW version info from Storm RAM */ 1897c965db44STomer Tayar if (fw_info_location.size > 0 && fw_info_location.size <= 1898c965db44STomer Tayar sizeof(*fw_info)) { 1899c965db44STomer Tayar addr = fw_info_location.grc_addr; 1900c965db44STomer Tayar dest = (u32 *)fw_info; 1901c965db44STomer Tayar for (i = 0; i < BYTES_TO_DWORDS(fw_info_location.size); 1902c965db44STomer Tayar i++, addr += BYTES_IN_DWORD) 1903c965db44STomer Tayar dest[i] = qed_rd(p_hwfn, p_ptt, addr); 1904c965db44STomer Tayar } 1905c965db44STomer Tayar } 1906c965db44STomer Tayar 19077b6859fbSMintz, Yuval /* Dumps the specified string to the specified buffer. 19087b6859fbSMintz, Yuval * Returns the dumped size in bytes. 1909c965db44STomer Tayar */ 1910c965db44STomer Tayar static u32 qed_dump_str(char *dump_buf, bool dump, const char *str) 1911c965db44STomer Tayar { 1912c965db44STomer Tayar if (dump) 1913c965db44STomer Tayar strcpy(dump_buf, str); 19147b6859fbSMintz, Yuval 1915c965db44STomer Tayar return (u32)strlen(str) + 1; 1916c965db44STomer Tayar } 1917c965db44STomer Tayar 19187b6859fbSMintz, Yuval /* Dumps zeros to align the specified buffer to dwords. 19197b6859fbSMintz, Yuval * Returns the dumped size in bytes. 1920c965db44STomer Tayar */ 1921c965db44STomer Tayar static u32 qed_dump_align(char *dump_buf, bool dump, u32 byte_offset) 1922c965db44STomer Tayar { 19237b6859fbSMintz, Yuval u8 offset_in_dword, align_size; 1924c965db44STomer Tayar 19257b6859fbSMintz, Yuval offset_in_dword = (u8)(byte_offset & 0x3); 1926c965db44STomer Tayar align_size = offset_in_dword ? BYTES_IN_DWORD - offset_in_dword : 0; 1927c965db44STomer Tayar 1928c965db44STomer Tayar if (dump && align_size) 1929c965db44STomer Tayar memset(dump_buf, 0, align_size); 19307b6859fbSMintz, Yuval 1931c965db44STomer Tayar return align_size; 1932c965db44STomer Tayar } 1933c965db44STomer Tayar 1934c965db44STomer Tayar /* Writes the specified string param to the specified buffer. 1935c965db44STomer Tayar * Returns the dumped size in dwords. 1936c965db44STomer Tayar */ 1937c965db44STomer Tayar static u32 qed_dump_str_param(u32 *dump_buf, 1938c965db44STomer Tayar bool dump, 1939c965db44STomer Tayar const char *param_name, const char *param_val) 1940c965db44STomer Tayar { 1941c965db44STomer Tayar char *char_buf = (char *)dump_buf; 1942c965db44STomer Tayar u32 offset = 0; 1943c965db44STomer Tayar 1944c965db44STomer Tayar /* Dump param name */ 1945c965db44STomer Tayar offset += qed_dump_str(char_buf + offset, dump, param_name); 1946c965db44STomer Tayar 1947c965db44STomer Tayar /* Indicate a string param value */ 1948c965db44STomer Tayar if (dump) 1949c965db44STomer Tayar *(char_buf + offset) = 1; 1950c965db44STomer Tayar offset++; 1951c965db44STomer Tayar 1952c965db44STomer Tayar /* Dump param value */ 1953c965db44STomer Tayar offset += qed_dump_str(char_buf + offset, dump, param_val); 1954c965db44STomer Tayar 1955c965db44STomer Tayar /* Align buffer to next dword */ 1956c965db44STomer Tayar offset += qed_dump_align(char_buf + offset, dump, offset); 19577b6859fbSMintz, Yuval 1958c965db44STomer Tayar return BYTES_TO_DWORDS(offset); 1959c965db44STomer Tayar } 1960c965db44STomer Tayar 1961c965db44STomer Tayar /* Writes the specified numeric param to the specified buffer. 1962c965db44STomer Tayar * Returns the dumped size in dwords. 1963c965db44STomer Tayar */ 1964c965db44STomer Tayar static u32 qed_dump_num_param(u32 *dump_buf, 1965c965db44STomer Tayar bool dump, const char *param_name, u32 param_val) 1966c965db44STomer Tayar { 1967c965db44STomer Tayar char *char_buf = (char *)dump_buf; 1968c965db44STomer Tayar u32 offset = 0; 1969c965db44STomer Tayar 1970c965db44STomer Tayar /* Dump param name */ 1971c965db44STomer Tayar offset += qed_dump_str(char_buf + offset, dump, param_name); 1972c965db44STomer Tayar 1973c965db44STomer Tayar /* Indicate a numeric param value */ 1974c965db44STomer Tayar if (dump) 1975c965db44STomer Tayar *(char_buf + offset) = 0; 1976c965db44STomer Tayar offset++; 1977c965db44STomer Tayar 1978c965db44STomer Tayar /* Align buffer to next dword */ 1979c965db44STomer Tayar offset += qed_dump_align(char_buf + offset, dump, offset); 1980c965db44STomer Tayar 1981c965db44STomer Tayar /* Dump param value (and change offset from bytes to dwords) */ 1982c965db44STomer Tayar offset = BYTES_TO_DWORDS(offset); 1983c965db44STomer Tayar if (dump) 1984c965db44STomer Tayar *(dump_buf + offset) = param_val; 1985c965db44STomer Tayar offset++; 19867b6859fbSMintz, Yuval 1987c965db44STomer Tayar return offset; 1988c965db44STomer Tayar } 1989c965db44STomer Tayar 1990c965db44STomer Tayar /* Reads the FW version and writes it as a param to the specified buffer. 1991c965db44STomer Tayar * Returns the dumped size in dwords. 1992c965db44STomer Tayar */ 1993c965db44STomer Tayar static u32 qed_dump_fw_ver_param(struct qed_hwfn *p_hwfn, 1994c965db44STomer Tayar struct qed_ptt *p_ptt, 1995c965db44STomer Tayar u32 *dump_buf, bool dump) 1996c965db44STomer Tayar { 1997c965db44STomer Tayar char fw_ver_str[16] = EMPTY_FW_VERSION_STR; 1998c965db44STomer Tayar char fw_img_str[16] = EMPTY_FW_IMAGE_STR; 1999c965db44STomer Tayar struct fw_info fw_info = { {0}, {0} }; 2000c965db44STomer Tayar u32 offset = 0; 2001c965db44STomer Tayar 2002be086e7cSMintz, Yuval if (dump && !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_FW_VER)) { 2003d52c89f1SMichal Kalderon /* Read FW info from chip */ 2004d52c89f1SMichal Kalderon qed_read_fw_info(p_hwfn, p_ptt, &fw_info); 2005c965db44STomer Tayar 2006c965db44STomer Tayar /* Create FW version/image strings */ 20077b6859fbSMintz, Yuval if (snprintf(fw_ver_str, sizeof(fw_ver_str), 20087b6859fbSMintz, Yuval "%d_%d_%d_%d", fw_info.ver.num.major, 20097b6859fbSMintz, Yuval fw_info.ver.num.minor, fw_info.ver.num.rev, 20107b6859fbSMintz, Yuval fw_info.ver.num.eng) < 0) 2011c965db44STomer Tayar DP_NOTICE(p_hwfn, 2012c965db44STomer Tayar "Unexpected debug error: invalid FW version string\n"); 2013c965db44STomer Tayar switch (fw_info.ver.image_id) { 2014c965db44STomer Tayar case FW_IMG_MAIN: 2015c965db44STomer Tayar strcpy(fw_img_str, "main"); 2016c965db44STomer Tayar break; 2017c965db44STomer Tayar default: 2018c965db44STomer Tayar strcpy(fw_img_str, "unknown"); 2019c965db44STomer Tayar break; 2020c965db44STomer Tayar } 2021c965db44STomer Tayar } 2022c965db44STomer Tayar 2023c965db44STomer Tayar /* Dump FW version, image and timestamp */ 2024c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 2025c965db44STomer Tayar dump, "fw-version", fw_ver_str); 2026c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 2027c965db44STomer Tayar dump, "fw-image", fw_img_str); 2028c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 2029c965db44STomer Tayar dump, 2030c965db44STomer Tayar "fw-timestamp", fw_info.ver.timestamp); 20317b6859fbSMintz, Yuval 2032c965db44STomer Tayar return offset; 2033c965db44STomer Tayar } 2034c965db44STomer Tayar 2035c965db44STomer Tayar /* Reads the MFW version and writes it as a param to the specified buffer. 2036c965db44STomer Tayar * Returns the dumped size in dwords. 2037c965db44STomer Tayar */ 2038c965db44STomer Tayar static u32 qed_dump_mfw_ver_param(struct qed_hwfn *p_hwfn, 2039c965db44STomer Tayar struct qed_ptt *p_ptt, 2040c965db44STomer Tayar u32 *dump_buf, bool dump) 2041c965db44STomer Tayar { 2042c965db44STomer Tayar char mfw_ver_str[16] = EMPTY_FW_VERSION_STR; 2043c965db44STomer Tayar 20447b6859fbSMintz, Yuval if (dump && 20457b6859fbSMintz, Yuval !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_FW_VER)) { 2046c965db44STomer Tayar u32 global_section_offsize, global_section_addr, mfw_ver; 2047c965db44STomer Tayar u32 public_data_addr, global_section_offsize_addr; 2048c965db44STomer Tayar 20497b6859fbSMintz, Yuval /* Find MCP public data GRC address. Needs to be ORed with 20507b6859fbSMintz, Yuval * MCP_REG_SCRATCH due to a HW bug. 2051c965db44STomer Tayar */ 20527b6859fbSMintz, Yuval public_data_addr = qed_rd(p_hwfn, 20537b6859fbSMintz, Yuval p_ptt, 2054c965db44STomer Tayar MISC_REG_SHARED_MEM_ADDR) | 2055c965db44STomer Tayar MCP_REG_SCRATCH; 2056c965db44STomer Tayar 2057c965db44STomer Tayar /* Find MCP public global section offset */ 2058c965db44STomer Tayar global_section_offsize_addr = public_data_addr + 2059c965db44STomer Tayar offsetof(struct mcp_public_data, 2060c965db44STomer Tayar sections) + 2061c965db44STomer Tayar sizeof(offsize_t) * PUBLIC_GLOBAL; 2062c965db44STomer Tayar global_section_offsize = qed_rd(p_hwfn, p_ptt, 2063c965db44STomer Tayar global_section_offsize_addr); 20647b6859fbSMintz, Yuval global_section_addr = 20657b6859fbSMintz, Yuval MCP_REG_SCRATCH + 20667b6859fbSMintz, Yuval (global_section_offsize & OFFSIZE_OFFSET_MASK) * 4; 2067c965db44STomer Tayar 2068c965db44STomer Tayar /* Read MFW version from MCP public global section */ 2069c965db44STomer Tayar mfw_ver = qed_rd(p_hwfn, p_ptt, 2070c965db44STomer Tayar global_section_addr + 2071c965db44STomer Tayar offsetof(struct public_global, mfw_ver)); 2072c965db44STomer Tayar 2073c965db44STomer Tayar /* Dump MFW version param */ 20747b6859fbSMintz, Yuval if (snprintf(mfw_ver_str, sizeof(mfw_ver_str), "%d_%d_%d_%d", 20757b6859fbSMintz, Yuval (u8)(mfw_ver >> 24), (u8)(mfw_ver >> 16), 20767b6859fbSMintz, Yuval (u8)(mfw_ver >> 8), (u8)mfw_ver) < 0) 2077c965db44STomer Tayar DP_NOTICE(p_hwfn, 2078c965db44STomer Tayar "Unexpected debug error: invalid MFW version string\n"); 2079c965db44STomer Tayar } 2080c965db44STomer Tayar 2081c965db44STomer Tayar return qed_dump_str_param(dump_buf, dump, "mfw-version", mfw_ver_str); 2082c965db44STomer Tayar } 2083c965db44STomer Tayar 2084c965db44STomer Tayar /* Writes a section header to the specified buffer. 2085c965db44STomer Tayar * Returns the dumped size in dwords. 2086c965db44STomer Tayar */ 2087c965db44STomer Tayar static u32 qed_dump_section_hdr(u32 *dump_buf, 2088c965db44STomer Tayar bool dump, const char *name, u32 num_params) 2089c965db44STomer Tayar { 2090c965db44STomer Tayar return qed_dump_num_param(dump_buf, dump, name, num_params); 2091c965db44STomer Tayar } 2092c965db44STomer Tayar 2093c965db44STomer Tayar /* Writes the common global params to the specified buffer. 2094c965db44STomer Tayar * Returns the dumped size in dwords. 2095c965db44STomer Tayar */ 2096c965db44STomer Tayar static u32 qed_dump_common_global_params(struct qed_hwfn *p_hwfn, 2097c965db44STomer Tayar struct qed_ptt *p_ptt, 2098c965db44STomer Tayar u32 *dump_buf, 2099c965db44STomer Tayar bool dump, 2100c965db44STomer Tayar u8 num_specific_global_params) 2101c965db44STomer Tayar { 2102c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2103c965db44STomer Tayar u32 offset = 0; 21047b6859fbSMintz, Yuval u8 num_params; 2105c965db44STomer Tayar 21067b6859fbSMintz, Yuval /* Dump global params section header */ 21077b6859fbSMintz, Yuval num_params = NUM_COMMON_GLOBAL_PARAMS + num_specific_global_params; 2108c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, 2109be086e7cSMintz, Yuval dump, "global_params", num_params); 2110c965db44STomer Tayar 2111c965db44STomer Tayar /* Store params */ 2112c965db44STomer Tayar offset += qed_dump_fw_ver_param(p_hwfn, p_ptt, dump_buf + offset, dump); 2113c965db44STomer Tayar offset += qed_dump_mfw_ver_param(p_hwfn, 2114c965db44STomer Tayar p_ptt, dump_buf + offset, dump); 2115c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 2116c965db44STomer Tayar dump, "tools-version", TOOLS_VERSION); 2117c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 2118c965db44STomer Tayar dump, 2119c965db44STomer Tayar "chip", 2120c965db44STomer Tayar s_chip_defs[dev_data->chip_id].name); 2121c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 2122c965db44STomer Tayar dump, 2123c965db44STomer Tayar "platform", 2124c965db44STomer Tayar s_platform_defs[dev_data->platform_id]. 2125c965db44STomer Tayar name); 2126c965db44STomer Tayar offset += 2127c965db44STomer Tayar qed_dump_num_param(dump_buf + offset, dump, "pci-func", 2128c965db44STomer Tayar p_hwfn->abs_pf_id); 21297b6859fbSMintz, Yuval 2130c965db44STomer Tayar return offset; 2131c965db44STomer Tayar } 2132c965db44STomer Tayar 21337b6859fbSMintz, Yuval /* Writes the "last" section (including CRC) to the specified buffer at the 21347b6859fbSMintz, Yuval * given offset. Returns the dumped size in dwords. 2135c965db44STomer Tayar */ 2136da090917STomer Tayar static u32 qed_dump_last_section(u32 *dump_buf, u32 offset, bool dump) 2137c965db44STomer Tayar { 21387b6859fbSMintz, Yuval u32 start_offset = offset; 2139c965db44STomer Tayar 2140c965db44STomer Tayar /* Dump CRC section header */ 2141c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, dump, "last", 0); 2142c965db44STomer Tayar 21437b6859fbSMintz, Yuval /* Calculate CRC32 and add it to the dword after the "last" section */ 2144c965db44STomer Tayar if (dump) 21457b6859fbSMintz, Yuval *(dump_buf + offset) = ~crc32(0xffffffff, 21467b6859fbSMintz, Yuval (u8 *)dump_buf, 2147c965db44STomer Tayar DWORDS_TO_BYTES(offset)); 21487b6859fbSMintz, Yuval 2149c965db44STomer Tayar offset++; 21507b6859fbSMintz, Yuval 2151c965db44STomer Tayar return offset - start_offset; 2152c965db44STomer Tayar } 2153c965db44STomer Tayar 2154c965db44STomer Tayar /* Update blocks reset state */ 2155c965db44STomer Tayar static void qed_update_blocks_reset_state(struct qed_hwfn *p_hwfn, 2156c965db44STomer Tayar struct qed_ptt *p_ptt) 2157c965db44STomer Tayar { 2158c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2159c965db44STomer Tayar u32 reg_val[MAX_DBG_RESET_REGS] = { 0 }; 2160c965db44STomer Tayar u32 i; 2161c965db44STomer Tayar 2162c965db44STomer Tayar /* Read reset registers */ 2163c965db44STomer Tayar for (i = 0; i < MAX_DBG_RESET_REGS; i++) 2164c965db44STomer Tayar if (s_reset_regs_defs[i].exists[dev_data->chip_id]) 2165c965db44STomer Tayar reg_val[i] = qed_rd(p_hwfn, 2166c965db44STomer Tayar p_ptt, s_reset_regs_defs[i].addr); 2167c965db44STomer Tayar 2168c965db44STomer Tayar /* Check if blocks are in reset */ 21697b6859fbSMintz, Yuval for (i = 0; i < MAX_BLOCK_ID; i++) { 21707b6859fbSMintz, Yuval struct block_defs *block = s_block_defs[i]; 21717b6859fbSMintz, Yuval 21727b6859fbSMintz, Yuval dev_data->block_in_reset[i] = block->has_reset_bit && 21737b6859fbSMintz, Yuval !(reg_val[block->reset_reg] & BIT(block->reset_bit_offset)); 21747b6859fbSMintz, Yuval } 2175c965db44STomer Tayar } 2176c965db44STomer Tayar 2177c965db44STomer Tayar /* Enable / disable the Debug block */ 2178c965db44STomer Tayar static void qed_bus_enable_dbg_block(struct qed_hwfn *p_hwfn, 2179c965db44STomer Tayar struct qed_ptt *p_ptt, bool enable) 2180c965db44STomer Tayar { 2181c965db44STomer Tayar qed_wr(p_hwfn, p_ptt, DBG_REG_DBG_BLOCK_ON, enable ? 1 : 0); 2182c965db44STomer Tayar } 2183c965db44STomer Tayar 2184c965db44STomer Tayar /* Resets the Debug block */ 2185c965db44STomer Tayar static void qed_bus_reset_dbg_block(struct qed_hwfn *p_hwfn, 2186c965db44STomer Tayar struct qed_ptt *p_ptt) 2187c965db44STomer Tayar { 2188c965db44STomer Tayar u32 dbg_reset_reg_addr, old_reset_reg_val, new_reset_reg_val; 21897b6859fbSMintz, Yuval struct block_defs *dbg_block = s_block_defs[BLOCK_DBG]; 2190c965db44STomer Tayar 21917b6859fbSMintz, Yuval dbg_reset_reg_addr = s_reset_regs_defs[dbg_block->reset_reg].addr; 2192c965db44STomer Tayar old_reset_reg_val = qed_rd(p_hwfn, p_ptt, dbg_reset_reg_addr); 21937b6859fbSMintz, Yuval new_reset_reg_val = 21947b6859fbSMintz, Yuval old_reset_reg_val & ~BIT(dbg_block->reset_bit_offset); 2195c965db44STomer Tayar 2196c965db44STomer Tayar qed_wr(p_hwfn, p_ptt, dbg_reset_reg_addr, new_reset_reg_val); 2197c965db44STomer Tayar qed_wr(p_hwfn, p_ptt, dbg_reset_reg_addr, old_reset_reg_val); 2198c965db44STomer Tayar } 2199c965db44STomer Tayar 2200c965db44STomer Tayar static void qed_bus_set_framing_mode(struct qed_hwfn *p_hwfn, 2201c965db44STomer Tayar struct qed_ptt *p_ptt, 2202c965db44STomer Tayar enum dbg_bus_frame_modes mode) 2203c965db44STomer Tayar { 2204c965db44STomer Tayar qed_wr(p_hwfn, p_ptt, DBG_REG_FRAMING_MODE, (u8)mode); 2205c965db44STomer Tayar } 2206c965db44STomer Tayar 22077b6859fbSMintz, Yuval /* Enable / disable Debug Bus clients according to the specified mask 22087b6859fbSMintz, Yuval * (1 = enable, 0 = disable). 2209c965db44STomer Tayar */ 2210c965db44STomer Tayar static void qed_bus_enable_clients(struct qed_hwfn *p_hwfn, 2211c965db44STomer Tayar struct qed_ptt *p_ptt, u32 client_mask) 2212c965db44STomer Tayar { 2213c965db44STomer Tayar qed_wr(p_hwfn, p_ptt, DBG_REG_CLIENT_ENABLE, client_mask); 2214c965db44STomer Tayar } 2215c965db44STomer Tayar 2216c965db44STomer Tayar static bool qed_is_mode_match(struct qed_hwfn *p_hwfn, u16 *modes_buf_offset) 2217c965db44STomer Tayar { 2218c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2219c965db44STomer Tayar bool arg1, arg2; 22207b6859fbSMintz, Yuval const u32 *ptr; 22217b6859fbSMintz, Yuval u8 tree_val; 22227b6859fbSMintz, Yuval 22237b6859fbSMintz, Yuval /* Get next element from modes tree buffer */ 22247b6859fbSMintz, Yuval ptr = s_dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr; 22257b6859fbSMintz, Yuval tree_val = ((u8 *)ptr)[(*modes_buf_offset)++]; 2226c965db44STomer Tayar 2227c965db44STomer Tayar switch (tree_val) { 2228c965db44STomer Tayar case INIT_MODE_OP_NOT: 2229c965db44STomer Tayar return !qed_is_mode_match(p_hwfn, modes_buf_offset); 2230c965db44STomer Tayar case INIT_MODE_OP_OR: 2231c965db44STomer Tayar case INIT_MODE_OP_AND: 2232c965db44STomer Tayar arg1 = qed_is_mode_match(p_hwfn, modes_buf_offset); 2233c965db44STomer Tayar arg2 = qed_is_mode_match(p_hwfn, modes_buf_offset); 2234c965db44STomer Tayar return (tree_val == INIT_MODE_OP_OR) ? (arg1 || 2235c965db44STomer Tayar arg2) : (arg1 && arg2); 2236c965db44STomer Tayar default: 2237c965db44STomer Tayar return dev_data->mode_enable[tree_val - MAX_INIT_MODE_OPS] > 0; 2238c965db44STomer Tayar } 2239c965db44STomer Tayar } 2240c965db44STomer Tayar 2241c965db44STomer Tayar /* Returns true if the specified entity (indicated by GRC param) should be 2242c965db44STomer Tayar * included in the dump, false otherwise. 2243c965db44STomer Tayar */ 2244c965db44STomer Tayar static bool qed_grc_is_included(struct qed_hwfn *p_hwfn, 2245c965db44STomer Tayar enum dbg_grc_params grc_param) 2246c965db44STomer Tayar { 2247c965db44STomer Tayar return qed_grc_get_param(p_hwfn, grc_param) > 0; 2248c965db44STomer Tayar } 2249c965db44STomer Tayar 2250c965db44STomer Tayar /* Returns true of the specified Storm should be included in the dump, false 2251c965db44STomer Tayar * otherwise. 2252c965db44STomer Tayar */ 2253c965db44STomer Tayar static bool qed_grc_is_storm_included(struct qed_hwfn *p_hwfn, 2254c965db44STomer Tayar enum dbg_storms storm) 2255c965db44STomer Tayar { 2256c965db44STomer Tayar return qed_grc_get_param(p_hwfn, (enum dbg_grc_params)storm) > 0; 2257c965db44STomer Tayar } 2258c965db44STomer Tayar 2259c965db44STomer Tayar /* Returns true if the specified memory should be included in the dump, false 2260c965db44STomer Tayar * otherwise. 2261c965db44STomer Tayar */ 2262c965db44STomer Tayar static bool qed_grc_is_mem_included(struct qed_hwfn *p_hwfn, 2263c965db44STomer Tayar enum block_id block_id, u8 mem_group_id) 2264c965db44STomer Tayar { 22657b6859fbSMintz, Yuval struct block_defs *block = s_block_defs[block_id]; 2266c965db44STomer Tayar u8 i; 2267c965db44STomer Tayar 2268c965db44STomer Tayar /* Check Storm match */ 22697b6859fbSMintz, Yuval if (block->associated_to_storm && 2270c965db44STomer Tayar !qed_grc_is_storm_included(p_hwfn, 22717b6859fbSMintz, Yuval (enum dbg_storms)block->storm_id)) 2272c965db44STomer Tayar return false; 2273c965db44STomer Tayar 22747b6859fbSMintz, Yuval for (i = 0; i < NUM_BIG_RAM_TYPES; i++) { 22757b6859fbSMintz, Yuval struct big_ram_defs *big_ram = &s_big_ram_defs[i]; 2276c965db44STomer Tayar 22777b6859fbSMintz, Yuval if (mem_group_id == big_ram->mem_group_id || 22787b6859fbSMintz, Yuval mem_group_id == big_ram->ram_mem_group_id) 22797b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, big_ram->grc_param); 22807b6859fbSMintz, Yuval } 22817b6859fbSMintz, Yuval 22827b6859fbSMintz, Yuval switch (mem_group_id) { 22837b6859fbSMintz, Yuval case MEM_GROUP_PXP_ILT: 22847b6859fbSMintz, Yuval case MEM_GROUP_PXP_MEM: 22857b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_PXP); 22867b6859fbSMintz, Yuval case MEM_GROUP_RAM: 22877b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_RAM); 22887b6859fbSMintz, Yuval case MEM_GROUP_PBUF: 22897b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_PBUF); 22907b6859fbSMintz, Yuval case MEM_GROUP_CAU_MEM: 22917b6859fbSMintz, Yuval case MEM_GROUP_CAU_SB: 22927b6859fbSMintz, Yuval case MEM_GROUP_CAU_PI: 22937b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CAU); 22947b6859fbSMintz, Yuval case MEM_GROUP_QM_MEM: 22957b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_QM); 22967b6859fbSMintz, Yuval case MEM_GROUP_CFC_MEM: 22977b6859fbSMintz, Yuval case MEM_GROUP_CONN_CFC_MEM: 22987b6859fbSMintz, Yuval case MEM_GROUP_TASK_CFC_MEM: 2299da090917STomer Tayar return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CFC) || 2300da090917STomer Tayar qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CM_CTX); 23017b6859fbSMintz, Yuval case MEM_GROUP_IGU_MEM: 23027b6859fbSMintz, Yuval case MEM_GROUP_IGU_MSIX: 23037b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_IGU); 23047b6859fbSMintz, Yuval case MEM_GROUP_MULD_MEM: 23057b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_MULD); 23067b6859fbSMintz, Yuval case MEM_GROUP_PRS_MEM: 23077b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_PRS); 23087b6859fbSMintz, Yuval case MEM_GROUP_DMAE_MEM: 23097b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_DMAE); 23107b6859fbSMintz, Yuval case MEM_GROUP_TM_MEM: 23117b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_TM); 23127b6859fbSMintz, Yuval case MEM_GROUP_SDM_MEM: 23137b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_SDM); 23147b6859fbSMintz, Yuval case MEM_GROUP_TDIF_CTX: 23157b6859fbSMintz, Yuval case MEM_GROUP_RDIF_CTX: 23167b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_DIF); 23177b6859fbSMintz, Yuval case MEM_GROUP_CM_MEM: 23187b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CM); 23197b6859fbSMintz, Yuval case MEM_GROUP_IOR: 23207b6859fbSMintz, Yuval return qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_IOR); 23217b6859fbSMintz, Yuval default: 2322c965db44STomer Tayar return true; 2323c965db44STomer Tayar } 23247b6859fbSMintz, Yuval } 2325c965db44STomer Tayar 2326c965db44STomer Tayar /* Stalls all Storms */ 2327c965db44STomer Tayar static void qed_grc_stall_storms(struct qed_hwfn *p_hwfn, 2328c965db44STomer Tayar struct qed_ptt *p_ptt, bool stall) 2329c965db44STomer Tayar { 23307b6859fbSMintz, Yuval u32 reg_addr; 2331c965db44STomer Tayar u8 storm_id; 2332c965db44STomer Tayar 2333c965db44STomer Tayar for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 23347b6859fbSMintz, Yuval if (!qed_grc_is_storm_included(p_hwfn, 23357b6859fbSMintz, Yuval (enum dbg_storms)storm_id)) 23367b6859fbSMintz, Yuval continue; 2337c965db44STomer Tayar 23387b6859fbSMintz, Yuval reg_addr = s_storm_defs[storm_id].sem_fast_mem_addr + 23397b6859fbSMintz, Yuval SEM_FAST_REG_STALL_0_BB_K2; 23407b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, reg_addr, stall ? 1 : 0); 2341c965db44STomer Tayar } 2342c965db44STomer Tayar 2343c965db44STomer Tayar msleep(STALL_DELAY_MS); 2344c965db44STomer Tayar } 2345c965db44STomer Tayar 2346c965db44STomer Tayar /* Takes all blocks out of reset */ 2347c965db44STomer Tayar static void qed_grc_unreset_blocks(struct qed_hwfn *p_hwfn, 2348c965db44STomer Tayar struct qed_ptt *p_ptt) 2349c965db44STomer Tayar { 2350c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2351c965db44STomer Tayar u32 reg_val[MAX_DBG_RESET_REGS] = { 0 }; 23527b6859fbSMintz, Yuval u32 block_id, i; 2353c965db44STomer Tayar 2354c965db44STomer Tayar /* Fill reset regs values */ 23557b6859fbSMintz, Yuval for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) { 23567b6859fbSMintz, Yuval struct block_defs *block = s_block_defs[block_id]; 23577b6859fbSMintz, Yuval 2358da090917STomer Tayar if (block->exists[dev_data->chip_id] && block->has_reset_bit && 2359da090917STomer Tayar block->unreset) 23607b6859fbSMintz, Yuval reg_val[block->reset_reg] |= 23617b6859fbSMintz, Yuval BIT(block->reset_bit_offset); 23627b6859fbSMintz, Yuval } 2363c965db44STomer Tayar 2364c965db44STomer Tayar /* Write reset registers */ 2365c965db44STomer Tayar for (i = 0; i < MAX_DBG_RESET_REGS; i++) { 23667b6859fbSMintz, Yuval if (!s_reset_regs_defs[i].exists[dev_data->chip_id]) 23677b6859fbSMintz, Yuval continue; 23687b6859fbSMintz, Yuval 2369da090917STomer Tayar reg_val[i] |= 2370da090917STomer Tayar s_reset_regs_defs[i].unreset_val[dev_data->chip_id]; 23717b6859fbSMintz, Yuval 2372c965db44STomer Tayar if (reg_val[i]) 2373c965db44STomer Tayar qed_wr(p_hwfn, 2374c965db44STomer Tayar p_ptt, 2375c965db44STomer Tayar s_reset_regs_defs[i].addr + 2376c965db44STomer Tayar RESET_REG_UNRESET_OFFSET, reg_val[i]); 2377c965db44STomer Tayar } 2378c965db44STomer Tayar } 2379c965db44STomer Tayar 2380be086e7cSMintz, Yuval /* Returns the attention block data of the specified block */ 2381c965db44STomer Tayar static const struct dbg_attn_block_type_data * 2382c965db44STomer Tayar qed_get_block_attn_data(enum block_id block_id, enum dbg_attn_type attn_type) 2383c965db44STomer Tayar { 2384c965db44STomer Tayar const struct dbg_attn_block *base_attn_block_arr = 2385c965db44STomer Tayar (const struct dbg_attn_block *) 2386c965db44STomer Tayar s_dbg_arrays[BIN_BUF_DBG_ATTN_BLOCKS].ptr; 2387c965db44STomer Tayar 2388c965db44STomer Tayar return &base_attn_block_arr[block_id].per_type_data[attn_type]; 2389c965db44STomer Tayar } 2390c965db44STomer Tayar 2391c965db44STomer Tayar /* Returns the attention registers of the specified block */ 2392c965db44STomer Tayar static const struct dbg_attn_reg * 2393c965db44STomer Tayar qed_get_block_attn_regs(enum block_id block_id, enum dbg_attn_type attn_type, 2394c965db44STomer Tayar u8 *num_attn_regs) 2395c965db44STomer Tayar { 2396c965db44STomer Tayar const struct dbg_attn_block_type_data *block_type_data = 2397c965db44STomer Tayar qed_get_block_attn_data(block_id, attn_type); 2398c965db44STomer Tayar 2399c965db44STomer Tayar *num_attn_regs = block_type_data->num_regs; 24007b6859fbSMintz, Yuval 2401c965db44STomer Tayar return &((const struct dbg_attn_reg *) 2402c965db44STomer Tayar s_dbg_arrays[BIN_BUF_DBG_ATTN_REGS].ptr)[block_type_data-> 2403c965db44STomer Tayar regs_offset]; 2404c965db44STomer Tayar } 2405c965db44STomer Tayar 2406c965db44STomer Tayar /* For each block, clear the status of all parities */ 2407c965db44STomer Tayar static void qed_grc_clear_all_prty(struct qed_hwfn *p_hwfn, 2408c965db44STomer Tayar struct qed_ptt *p_ptt) 2409c965db44STomer Tayar { 2410c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 24117b6859fbSMintz, Yuval const struct dbg_attn_reg *attn_reg_arr; 2412c965db44STomer Tayar u8 reg_idx, num_attn_regs; 2413c965db44STomer Tayar u32 block_id; 2414c965db44STomer Tayar 2415c965db44STomer Tayar for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) { 2416c965db44STomer Tayar if (dev_data->block_in_reset[block_id]) 2417c965db44STomer Tayar continue; 2418c965db44STomer Tayar 2419c965db44STomer Tayar attn_reg_arr = qed_get_block_attn_regs((enum block_id)block_id, 2420c965db44STomer Tayar ATTN_TYPE_PARITY, 2421c965db44STomer Tayar &num_attn_regs); 24227b6859fbSMintz, Yuval 2423c965db44STomer Tayar for (reg_idx = 0; reg_idx < num_attn_regs; reg_idx++) { 2424c965db44STomer Tayar const struct dbg_attn_reg *reg_data = 2425c965db44STomer Tayar &attn_reg_arr[reg_idx]; 24267b6859fbSMintz, Yuval u16 modes_buf_offset; 24277b6859fbSMintz, Yuval bool eval_mode; 2428c965db44STomer Tayar 2429c965db44STomer Tayar /* Check mode */ 24307b6859fbSMintz, Yuval eval_mode = GET_FIELD(reg_data->mode.data, 2431c965db44STomer Tayar DBG_MODE_HDR_EVAL_MODE) > 0; 24327b6859fbSMintz, Yuval modes_buf_offset = 2433c965db44STomer Tayar GET_FIELD(reg_data->mode.data, 2434c965db44STomer Tayar DBG_MODE_HDR_MODES_BUF_OFFSET); 2435c965db44STomer Tayar 24367b6859fbSMintz, Yuval /* If Mode match: clear parity status */ 2437c965db44STomer Tayar if (!eval_mode || 2438c965db44STomer Tayar qed_is_mode_match(p_hwfn, &modes_buf_offset)) 2439c965db44STomer Tayar qed_rd(p_hwfn, p_ptt, 2440c965db44STomer Tayar DWORDS_TO_BYTES(reg_data-> 2441c965db44STomer Tayar sts_clr_address)); 2442c965db44STomer Tayar } 2443c965db44STomer Tayar } 2444c965db44STomer Tayar } 2445c965db44STomer Tayar 2446c965db44STomer Tayar /* Dumps GRC registers section header. Returns the dumped size in dwords. 2447c965db44STomer Tayar * The following parameters are dumped: 24487b6859fbSMintz, Yuval * - count: no. of dumped entries 2449d52c89f1SMichal Kalderon * - split_type: split type 2450d52c89f1SMichal Kalderon * - split_id: split ID (dumped only if split_id != SPLIT_TYPE_NONE) 24517b6859fbSMintz, Yuval * - param_name: user parameter value (dumped only if param_name != NULL 24527b6859fbSMintz, Yuval * and param_val != NULL). 2453c965db44STomer Tayar */ 2454c965db44STomer Tayar static u32 qed_grc_dump_regs_hdr(u32 *dump_buf, 2455c965db44STomer Tayar bool dump, 2456c965db44STomer Tayar u32 num_reg_entries, 2457d52c89f1SMichal Kalderon enum init_split_types split_type, 2458d52c89f1SMichal Kalderon u8 split_id, 2459c965db44STomer Tayar const char *param_name, const char *param_val) 2460c965db44STomer Tayar { 2461d52c89f1SMichal Kalderon u8 num_params = 2 + 2462d52c89f1SMichal Kalderon (split_type != SPLIT_TYPE_NONE ? 1 : 0) + (param_name ? 1 : 0); 2463c965db44STomer Tayar u32 offset = 0; 2464c965db44STomer Tayar 2465c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, 2466c965db44STomer Tayar dump, "grc_regs", num_params); 2467c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 2468c965db44STomer Tayar dump, "count", num_reg_entries); 2469c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 2470d52c89f1SMichal Kalderon dump, "split", 2471d52c89f1SMichal Kalderon s_split_type_defs[split_type].name); 2472d52c89f1SMichal Kalderon if (split_type != SPLIT_TYPE_NONE) 2473c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 2474c965db44STomer Tayar dump, "id", split_id); 2475c965db44STomer Tayar if (param_name && param_val) 2476c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 2477c965db44STomer Tayar dump, param_name, param_val); 24787b6859fbSMintz, Yuval 2479c965db44STomer Tayar return offset; 2480c965db44STomer Tayar } 2481c965db44STomer Tayar 2482da090917STomer Tayar /* Reads the specified registers into the specified buffer. 2483da090917STomer Tayar * The addr and len arguments are specified in dwords. 2484da090917STomer Tayar */ 2485da090917STomer Tayar void qed_read_regs(struct qed_hwfn *p_hwfn, 2486da090917STomer Tayar struct qed_ptt *p_ptt, u32 *buf, u32 addr, u32 len) 2487da090917STomer Tayar { 2488da090917STomer Tayar u32 i; 2489da090917STomer Tayar 2490da090917STomer Tayar for (i = 0; i < len; i++) 2491da090917STomer Tayar buf[i] = qed_rd(p_hwfn, p_ptt, DWORDS_TO_BYTES(addr + i)); 2492da090917STomer Tayar } 2493da090917STomer Tayar 2494be086e7cSMintz, Yuval /* Dumps the GRC registers in the specified address range. 2495be086e7cSMintz, Yuval * Returns the dumped size in dwords. 24967b6859fbSMintz, Yuval * The addr and len arguments are specified in dwords. 2497be086e7cSMintz, Yuval */ 2498be086e7cSMintz, Yuval static u32 qed_grc_dump_addr_range(struct qed_hwfn *p_hwfn, 24997b6859fbSMintz, Yuval struct qed_ptt *p_ptt, 25007b6859fbSMintz, Yuval u32 *dump_buf, 2501d52c89f1SMichal Kalderon bool dump, u32 addr, u32 len, bool wide_bus, 2502d52c89f1SMichal Kalderon enum init_split_types split_type, 2503d52c89f1SMichal Kalderon u8 split_id) 2504be086e7cSMintz, Yuval { 2505da090917STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2506d52c89f1SMichal Kalderon u8 port_id = 0, pf_id = 0, vf_id = 0, fid = 0; 2507be086e7cSMintz, Yuval 25087b6859fbSMintz, Yuval if (!dump) 25097b6859fbSMintz, Yuval return len; 25107b6859fbSMintz, Yuval 2511da090917STomer Tayar /* Print log if needed */ 2512da090917STomer Tayar dev_data->num_regs_read += len; 2513da090917STomer Tayar if (dev_data->num_regs_read >= 2514da090917STomer Tayar s_platform_defs[dev_data->platform_id].log_thresh) { 2515da090917STomer Tayar DP_VERBOSE(p_hwfn, 2516da090917STomer Tayar QED_MSG_DEBUG, 2517da090917STomer Tayar "Dumping %d registers...\n", 2518da090917STomer Tayar dev_data->num_regs_read); 2519da090917STomer Tayar dev_data->num_regs_read = 0; 2520da090917STomer Tayar } 25217b6859fbSMintz, Yuval 2522d52c89f1SMichal Kalderon switch (split_type) { 2523d52c89f1SMichal Kalderon case SPLIT_TYPE_PORT: 2524d52c89f1SMichal Kalderon port_id = split_id; 2525d52c89f1SMichal Kalderon break; 2526d52c89f1SMichal Kalderon case SPLIT_TYPE_PF: 2527d52c89f1SMichal Kalderon pf_id = split_id; 2528d52c89f1SMichal Kalderon break; 2529d52c89f1SMichal Kalderon case SPLIT_TYPE_PORT_PF: 2530d52c89f1SMichal Kalderon port_id = split_id / dev_data->num_pfs_per_port; 2531d52c89f1SMichal Kalderon pf_id = port_id + dev_data->num_ports * 2532d52c89f1SMichal Kalderon (split_id % dev_data->num_pfs_per_port); 2533d52c89f1SMichal Kalderon break; 2534d52c89f1SMichal Kalderon case SPLIT_TYPE_VF: 2535d52c89f1SMichal Kalderon vf_id = split_id; 2536d52c89f1SMichal Kalderon break; 2537d52c89f1SMichal Kalderon default: 2538d52c89f1SMichal Kalderon break; 2539d52c89f1SMichal Kalderon } 2540d52c89f1SMichal Kalderon 2541da090917STomer Tayar /* Try reading using DMAE */ 2542d52c89f1SMichal Kalderon if (dev_data->use_dmae && split_type == SPLIT_TYPE_NONE && 2543da090917STomer Tayar (len >= s_platform_defs[dev_data->platform_id].dmae_thresh || 2544da090917STomer Tayar wide_bus)) { 2545da090917STomer Tayar if (!qed_dmae_grc2host(p_hwfn, p_ptt, DWORDS_TO_BYTES(addr), 254683bf76e3SMichal Kalderon (u64)(uintptr_t)(dump_buf), len, NULL)) 2547da090917STomer Tayar return len; 2548da090917STomer Tayar dev_data->use_dmae = 0; 2549da090917STomer Tayar DP_VERBOSE(p_hwfn, 2550da090917STomer Tayar QED_MSG_DEBUG, 2551da090917STomer Tayar "Failed reading from chip using DMAE, using GRC instead\n"); 2552da090917STomer Tayar } 2553da090917STomer Tayar 2554d52c89f1SMichal Kalderon /* If not read using DMAE, read using GRC */ 2555d52c89f1SMichal Kalderon 2556d52c89f1SMichal Kalderon /* Set pretend */ 2557d52c89f1SMichal Kalderon if (split_type != dev_data->pretend.split_type || split_id != 2558d52c89f1SMichal Kalderon dev_data->pretend.split_id) { 2559d52c89f1SMichal Kalderon switch (split_type) { 2560d52c89f1SMichal Kalderon case SPLIT_TYPE_PORT: 2561d52c89f1SMichal Kalderon qed_port_pretend(p_hwfn, p_ptt, port_id); 2562d52c89f1SMichal Kalderon break; 2563d52c89f1SMichal Kalderon case SPLIT_TYPE_PF: 2564d52c89f1SMichal Kalderon fid = pf_id << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT; 2565d52c89f1SMichal Kalderon qed_fid_pretend(p_hwfn, p_ptt, fid); 2566d52c89f1SMichal Kalderon break; 2567d52c89f1SMichal Kalderon case SPLIT_TYPE_PORT_PF: 2568d52c89f1SMichal Kalderon fid = pf_id << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT; 2569d52c89f1SMichal Kalderon qed_port_fid_pretend(p_hwfn, p_ptt, port_id, fid); 2570d52c89f1SMichal Kalderon break; 2571d52c89f1SMichal Kalderon case SPLIT_TYPE_VF: 2572d52c89f1SMichal Kalderon fid = BIT(PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT) | 2573d52c89f1SMichal Kalderon (vf_id << PXP_PRETEND_CONCRETE_FID_VFID_SHIFT); 2574d52c89f1SMichal Kalderon qed_fid_pretend(p_hwfn, p_ptt, fid); 2575d52c89f1SMichal Kalderon break; 2576d52c89f1SMichal Kalderon default: 2577d52c89f1SMichal Kalderon break; 2578d52c89f1SMichal Kalderon } 2579d52c89f1SMichal Kalderon 2580d52c89f1SMichal Kalderon dev_data->pretend.split_type = (u8)split_type; 2581d52c89f1SMichal Kalderon dev_data->pretend.split_id = split_id; 2582d52c89f1SMichal Kalderon } 2583d52c89f1SMichal Kalderon 2584d52c89f1SMichal Kalderon /* Read registers using GRC */ 2585da090917STomer Tayar qed_read_regs(p_hwfn, p_ptt, dump_buf, addr, len); 2586da090917STomer Tayar 2587da090917STomer Tayar return len; 2588be086e7cSMintz, Yuval } 2589be086e7cSMintz, Yuval 25907b6859fbSMintz, Yuval /* Dumps GRC registers sequence header. Returns the dumped size in dwords. 25917b6859fbSMintz, Yuval * The addr and len arguments are specified in dwords. 25927b6859fbSMintz, Yuval */ 25937b6859fbSMintz, Yuval static u32 qed_grc_dump_reg_entry_hdr(u32 *dump_buf, 25947b6859fbSMintz, Yuval bool dump, u32 addr, u32 len) 2595be086e7cSMintz, Yuval { 2596be086e7cSMintz, Yuval if (dump) 2597be086e7cSMintz, Yuval *dump_buf = addr | (len << REG_DUMP_LEN_SHIFT); 25987b6859fbSMintz, Yuval 2599be086e7cSMintz, Yuval return 1; 2600be086e7cSMintz, Yuval } 2601be086e7cSMintz, Yuval 26027b6859fbSMintz, Yuval /* Dumps GRC registers sequence. Returns the dumped size in dwords. 26037b6859fbSMintz, Yuval * The addr and len arguments are specified in dwords. 26047b6859fbSMintz, Yuval */ 2605c965db44STomer Tayar static u32 qed_grc_dump_reg_entry(struct qed_hwfn *p_hwfn, 26067b6859fbSMintz, Yuval struct qed_ptt *p_ptt, 26077b6859fbSMintz, Yuval u32 *dump_buf, 2608d52c89f1SMichal Kalderon bool dump, u32 addr, u32 len, bool wide_bus, 2609d52c89f1SMichal Kalderon enum init_split_types split_type, u8 split_id) 2610c965db44STomer Tayar { 2611be086e7cSMintz, Yuval u32 offset = 0; 2612c965db44STomer Tayar 2613be086e7cSMintz, Yuval offset += qed_grc_dump_reg_entry_hdr(dump_buf, dump, addr, len); 2614be086e7cSMintz, Yuval offset += qed_grc_dump_addr_range(p_hwfn, 2615c965db44STomer Tayar p_ptt, 26167b6859fbSMintz, Yuval dump_buf + offset, 2617d52c89f1SMichal Kalderon dump, addr, len, wide_bus, 2618d52c89f1SMichal Kalderon split_type, split_id); 26197b6859fbSMintz, Yuval 2620be086e7cSMintz, Yuval return offset; 2621be086e7cSMintz, Yuval } 2622be086e7cSMintz, Yuval 2623be086e7cSMintz, Yuval /* Dumps GRC registers sequence with skip cycle. 2624be086e7cSMintz, Yuval * Returns the dumped size in dwords. 26257b6859fbSMintz, Yuval * - addr: start GRC address in dwords 26267b6859fbSMintz, Yuval * - total_len: total no. of dwords to dump 26277b6859fbSMintz, Yuval * - read_len: no. consecutive dwords to read 26287b6859fbSMintz, Yuval * - skip_len: no. of dwords to skip (and fill with zeros) 2629be086e7cSMintz, Yuval */ 2630be086e7cSMintz, Yuval static u32 qed_grc_dump_reg_entry_skip(struct qed_hwfn *p_hwfn, 26317b6859fbSMintz, Yuval struct qed_ptt *p_ptt, 26327b6859fbSMintz, Yuval u32 *dump_buf, 26337b6859fbSMintz, Yuval bool dump, 26347b6859fbSMintz, Yuval u32 addr, 26357b6859fbSMintz, Yuval u32 total_len, 2636be086e7cSMintz, Yuval u32 read_len, u32 skip_len) 2637be086e7cSMintz, Yuval { 2638be086e7cSMintz, Yuval u32 offset = 0, reg_offset = 0; 2639be086e7cSMintz, Yuval 2640be086e7cSMintz, Yuval offset += qed_grc_dump_reg_entry_hdr(dump_buf, dump, addr, total_len); 26417b6859fbSMintz, Yuval 26427b6859fbSMintz, Yuval if (!dump) 26437b6859fbSMintz, Yuval return offset + total_len; 26447b6859fbSMintz, Yuval 2645be086e7cSMintz, Yuval while (reg_offset < total_len) { 26467b6859fbSMintz, Yuval u32 curr_len = min_t(u32, read_len, total_len - reg_offset); 26477b6859fbSMintz, Yuval 2648be086e7cSMintz, Yuval offset += qed_grc_dump_addr_range(p_hwfn, 2649be086e7cSMintz, Yuval p_ptt, 2650be086e7cSMintz, Yuval dump_buf + offset, 2651d52c89f1SMichal Kalderon dump, addr, curr_len, false, 2652d52c89f1SMichal Kalderon SPLIT_TYPE_NONE, 0); 2653be086e7cSMintz, Yuval reg_offset += curr_len; 2654be086e7cSMintz, Yuval addr += curr_len; 26557b6859fbSMintz, Yuval 2656be086e7cSMintz, Yuval if (reg_offset < total_len) { 26577b6859fbSMintz, Yuval curr_len = min_t(u32, skip_len, total_len - skip_len); 26587b6859fbSMintz, Yuval memset(dump_buf + offset, 0, DWORDS_TO_BYTES(curr_len)); 2659be086e7cSMintz, Yuval offset += curr_len; 2660be086e7cSMintz, Yuval reg_offset += curr_len; 2661be086e7cSMintz, Yuval addr += curr_len; 2662be086e7cSMintz, Yuval } 2663be086e7cSMintz, Yuval } 2664c965db44STomer Tayar 2665c965db44STomer Tayar return offset; 2666c965db44STomer Tayar } 2667c965db44STomer Tayar 2668c965db44STomer Tayar /* Dumps GRC registers entries. Returns the dumped size in dwords. */ 2669c965db44STomer Tayar static u32 qed_grc_dump_regs_entries(struct qed_hwfn *p_hwfn, 2670c965db44STomer Tayar struct qed_ptt *p_ptt, 2671c965db44STomer Tayar struct dbg_array input_regs_arr, 2672c965db44STomer Tayar u32 *dump_buf, 2673c965db44STomer Tayar bool dump, 2674d52c89f1SMichal Kalderon enum init_split_types split_type, 2675d52c89f1SMichal Kalderon u8 split_id, 2676c965db44STomer Tayar bool block_enable[MAX_BLOCK_ID], 2677c965db44STomer Tayar u32 *num_dumped_reg_entries) 2678c965db44STomer Tayar { 2679c965db44STomer Tayar u32 i, offset = 0, input_offset = 0; 2680c965db44STomer Tayar bool mode_match = true; 2681c965db44STomer Tayar 2682c965db44STomer Tayar *num_dumped_reg_entries = 0; 26837b6859fbSMintz, Yuval 2684c965db44STomer Tayar while (input_offset < input_regs_arr.size_in_dwords) { 2685c965db44STomer Tayar const struct dbg_dump_cond_hdr *cond_hdr = 2686c965db44STomer Tayar (const struct dbg_dump_cond_hdr *) 2687c965db44STomer Tayar &input_regs_arr.ptr[input_offset++]; 26887b6859fbSMintz, Yuval u16 modes_buf_offset; 26897b6859fbSMintz, Yuval bool eval_mode; 2690c965db44STomer Tayar 2691c965db44STomer Tayar /* Check mode/block */ 26927b6859fbSMintz, Yuval eval_mode = GET_FIELD(cond_hdr->mode.data, 26937b6859fbSMintz, Yuval DBG_MODE_HDR_EVAL_MODE) > 0; 2694c965db44STomer Tayar if (eval_mode) { 26957b6859fbSMintz, Yuval modes_buf_offset = 2696c965db44STomer Tayar GET_FIELD(cond_hdr->mode.data, 2697c965db44STomer Tayar DBG_MODE_HDR_MODES_BUF_OFFSET); 2698c965db44STomer Tayar mode_match = qed_is_mode_match(p_hwfn, 2699c965db44STomer Tayar &modes_buf_offset); 2700c965db44STomer Tayar } 2701c965db44STomer Tayar 27027b6859fbSMintz, Yuval if (!mode_match || !block_enable[cond_hdr->block_id]) { 27037b6859fbSMintz, Yuval input_offset += cond_hdr->data_size; 27047b6859fbSMintz, Yuval continue; 27057b6859fbSMintz, Yuval } 27067b6859fbSMintz, Yuval 27077b6859fbSMintz, Yuval for (i = 0; i < cond_hdr->data_size; i++, input_offset++) { 2708c965db44STomer Tayar const struct dbg_dump_reg *reg = 2709c965db44STomer Tayar (const struct dbg_dump_reg *) 2710c965db44STomer Tayar &input_regs_arr.ptr[input_offset]; 2711be086e7cSMintz, Yuval u32 addr, len; 27127b6859fbSMintz, Yuval bool wide_bus; 2713c965db44STomer Tayar 27147b6859fbSMintz, Yuval addr = GET_FIELD(reg->data, DBG_DUMP_REG_ADDRESS); 2715be086e7cSMintz, Yuval len = GET_FIELD(reg->data, DBG_DUMP_REG_LENGTH); 27167b6859fbSMintz, Yuval wide_bus = GET_FIELD(reg->data, DBG_DUMP_REG_WIDE_BUS); 27177b6859fbSMintz, Yuval offset += qed_grc_dump_reg_entry(p_hwfn, 27187b6859fbSMintz, Yuval p_ptt, 2719be086e7cSMintz, Yuval dump_buf + offset, 2720be086e7cSMintz, Yuval dump, 2721be086e7cSMintz, Yuval addr, 27227b6859fbSMintz, Yuval len, 2723d52c89f1SMichal Kalderon wide_bus, 2724d52c89f1SMichal Kalderon split_type, split_id); 2725c965db44STomer Tayar (*num_dumped_reg_entries)++; 2726c965db44STomer Tayar } 2727c965db44STomer Tayar } 2728c965db44STomer Tayar 2729c965db44STomer Tayar return offset; 2730c965db44STomer Tayar } 2731c965db44STomer Tayar 2732c965db44STomer Tayar /* Dumps GRC registers entries. Returns the dumped size in dwords. */ 2733c965db44STomer Tayar static u32 qed_grc_dump_split_data(struct qed_hwfn *p_hwfn, 2734c965db44STomer Tayar struct qed_ptt *p_ptt, 2735c965db44STomer Tayar struct dbg_array input_regs_arr, 2736c965db44STomer Tayar u32 *dump_buf, 2737c965db44STomer Tayar bool dump, 2738c965db44STomer Tayar bool block_enable[MAX_BLOCK_ID], 2739d52c89f1SMichal Kalderon enum init_split_types split_type, 2740d52c89f1SMichal Kalderon u8 split_id, 2741c965db44STomer Tayar const char *param_name, 2742c965db44STomer Tayar const char *param_val) 2743c965db44STomer Tayar { 2744d52c89f1SMichal Kalderon struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2745d52c89f1SMichal Kalderon enum init_split_types hdr_split_type = split_type; 2746c965db44STomer Tayar u32 num_dumped_reg_entries, offset; 2747d52c89f1SMichal Kalderon u8 hdr_split_id = split_id; 2748d52c89f1SMichal Kalderon 2749d52c89f1SMichal Kalderon /* In PORT_PF split type, print a port split header */ 2750d52c89f1SMichal Kalderon if (split_type == SPLIT_TYPE_PORT_PF) { 2751d52c89f1SMichal Kalderon hdr_split_type = SPLIT_TYPE_PORT; 2752d52c89f1SMichal Kalderon hdr_split_id = split_id / dev_data->num_pfs_per_port; 2753d52c89f1SMichal Kalderon } 2754c965db44STomer Tayar 2755c965db44STomer Tayar /* Calculate register dump header size (and skip it for now) */ 2756c965db44STomer Tayar offset = qed_grc_dump_regs_hdr(dump_buf, 2757c965db44STomer Tayar false, 2758c965db44STomer Tayar 0, 2759d52c89f1SMichal Kalderon hdr_split_type, 2760d52c89f1SMichal Kalderon hdr_split_id, param_name, param_val); 2761c965db44STomer Tayar 2762c965db44STomer Tayar /* Dump registers */ 2763c965db44STomer Tayar offset += qed_grc_dump_regs_entries(p_hwfn, 2764c965db44STomer Tayar p_ptt, 2765c965db44STomer Tayar input_regs_arr, 2766c965db44STomer Tayar dump_buf + offset, 2767c965db44STomer Tayar dump, 2768d52c89f1SMichal Kalderon split_type, 2769d52c89f1SMichal Kalderon split_id, 2770c965db44STomer Tayar block_enable, 2771c965db44STomer Tayar &num_dumped_reg_entries); 2772c965db44STomer Tayar 2773c965db44STomer Tayar /* Write register dump header */ 2774c965db44STomer Tayar if (dump && num_dumped_reg_entries > 0) 2775c965db44STomer Tayar qed_grc_dump_regs_hdr(dump_buf, 2776c965db44STomer Tayar dump, 2777c965db44STomer Tayar num_dumped_reg_entries, 2778d52c89f1SMichal Kalderon hdr_split_type, 2779d52c89f1SMichal Kalderon hdr_split_id, param_name, param_val); 2780c965db44STomer Tayar 2781c965db44STomer Tayar return num_dumped_reg_entries > 0 ? offset : 0; 2782c965db44STomer Tayar } 2783c965db44STomer Tayar 27847b6859fbSMintz, Yuval /* Dumps registers according to the input registers array. Returns the dumped 27857b6859fbSMintz, Yuval * size in dwords. 2786c965db44STomer Tayar */ 2787c965db44STomer Tayar static u32 qed_grc_dump_registers(struct qed_hwfn *p_hwfn, 2788c965db44STomer Tayar struct qed_ptt *p_ptt, 2789c965db44STomer Tayar u32 *dump_buf, 2790c965db44STomer Tayar bool dump, 2791c965db44STomer Tayar bool block_enable[MAX_BLOCK_ID], 2792c965db44STomer Tayar const char *param_name, const char *param_val) 2793c965db44STomer Tayar { 2794c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2795c965db44STomer Tayar u32 offset = 0, input_offset = 0; 2796be086e7cSMintz, Yuval u16 fid; 2797c965db44STomer Tayar while (input_offset < 2798c965db44STomer Tayar s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].size_in_dwords) { 27997b6859fbSMintz, Yuval const struct dbg_dump_split_hdr *split_hdr; 28007b6859fbSMintz, Yuval struct dbg_array curr_input_regs_arr; 2801d52c89f1SMichal Kalderon enum init_split_types split_type; 2802d52c89f1SMichal Kalderon u16 split_count = 0; 28037b6859fbSMintz, Yuval u32 split_data_size; 2804d52c89f1SMichal Kalderon u8 split_id; 28057b6859fbSMintz, Yuval 28067b6859fbSMintz, Yuval split_hdr = 2807c965db44STomer Tayar (const struct dbg_dump_split_hdr *) 2808c965db44STomer Tayar &s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].ptr[input_offset++]; 2809d52c89f1SMichal Kalderon split_type = 28107b6859fbSMintz, Yuval GET_FIELD(split_hdr->hdr, 2811c965db44STomer Tayar DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID); 28127b6859fbSMintz, Yuval split_data_size = 28137b6859fbSMintz, Yuval GET_FIELD(split_hdr->hdr, 2814c965db44STomer Tayar DBG_DUMP_SPLIT_HDR_DATA_SIZE); 28157b6859fbSMintz, Yuval curr_input_regs_arr.ptr = 28167b6859fbSMintz, Yuval &s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].ptr[input_offset]; 28177b6859fbSMintz, Yuval curr_input_regs_arr.size_in_dwords = split_data_size; 2818c965db44STomer Tayar 2819d52c89f1SMichal Kalderon switch (split_type) { 2820c965db44STomer Tayar case SPLIT_TYPE_NONE: 2821d52c89f1SMichal Kalderon split_count = 1; 2822c965db44STomer Tayar break; 2823c965db44STomer Tayar case SPLIT_TYPE_PORT: 2824d52c89f1SMichal Kalderon split_count = dev_data->num_ports; 2825c965db44STomer Tayar break; 2826c965db44STomer Tayar case SPLIT_TYPE_PF: 2827c965db44STomer Tayar case SPLIT_TYPE_PORT_PF: 2828d52c89f1SMichal Kalderon split_count = dev_data->num_ports * 2829d52c89f1SMichal Kalderon dev_data->num_pfs_per_port; 2830be086e7cSMintz, Yuval break; 2831be086e7cSMintz, Yuval case SPLIT_TYPE_VF: 2832d52c89f1SMichal Kalderon split_count = dev_data->num_vfs; 2833d52c89f1SMichal Kalderon break; 2834d52c89f1SMichal Kalderon default: 2835d52c89f1SMichal Kalderon return 0; 2836be086e7cSMintz, Yuval } 2837be086e7cSMintz, Yuval 2838d52c89f1SMichal Kalderon for (split_id = 0; split_id < split_count; split_id++) 2839d52c89f1SMichal Kalderon offset += qed_grc_dump_split_data(p_hwfn, p_ptt, 2840be086e7cSMintz, Yuval curr_input_regs_arr, 2841be086e7cSMintz, Yuval dump_buf + offset, 2842be086e7cSMintz, Yuval dump, block_enable, 2843d52c89f1SMichal Kalderon split_type, 2844d52c89f1SMichal Kalderon split_id, 2845be086e7cSMintz, Yuval param_name, 2846c965db44STomer Tayar param_val); 2847c965db44STomer Tayar 2848c965db44STomer Tayar input_offset += split_data_size; 2849c965db44STomer Tayar } 2850c965db44STomer Tayar 2851d52c89f1SMichal Kalderon /* Cancel pretends (pretend to original PF) */ 2852be086e7cSMintz, Yuval if (dump) { 2853be086e7cSMintz, Yuval fid = p_hwfn->rel_pf_id << PXP_PRETEND_CONCRETE_FID_PFID_SHIFT; 2854be086e7cSMintz, Yuval qed_fid_pretend(p_hwfn, p_ptt, fid); 2855d52c89f1SMichal Kalderon dev_data->pretend.split_type = SPLIT_TYPE_NONE; 2856d52c89f1SMichal Kalderon dev_data->pretend.split_id = 0; 2857be086e7cSMintz, Yuval } 2858be086e7cSMintz, Yuval 2859c965db44STomer Tayar return offset; 2860c965db44STomer Tayar } 2861c965db44STomer Tayar 2862c965db44STomer Tayar /* Dump reset registers. Returns the dumped size in dwords. */ 2863c965db44STomer Tayar static u32 qed_grc_dump_reset_regs(struct qed_hwfn *p_hwfn, 2864c965db44STomer Tayar struct qed_ptt *p_ptt, 2865c965db44STomer Tayar u32 *dump_buf, bool dump) 2866c965db44STomer Tayar { 2867c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 2868c965db44STomer Tayar u32 i, offset = 0, num_regs = 0; 2869c965db44STomer Tayar 2870c965db44STomer Tayar /* Calculate header size */ 2871c965db44STomer Tayar offset += qed_grc_dump_regs_hdr(dump_buf, 2872d52c89f1SMichal Kalderon false, 0, 2873d52c89f1SMichal Kalderon SPLIT_TYPE_NONE, 0, NULL, NULL); 2874c965db44STomer Tayar 2875c965db44STomer Tayar /* Write reset registers */ 2876c965db44STomer Tayar for (i = 0; i < MAX_DBG_RESET_REGS; i++) { 28777b6859fbSMintz, Yuval if (!s_reset_regs_defs[i].exists[dev_data->chip_id]) 28787b6859fbSMintz, Yuval continue; 2879be086e7cSMintz, Yuval 2880c965db44STomer Tayar offset += qed_grc_dump_reg_entry(p_hwfn, 2881c965db44STomer Tayar p_ptt, 2882c965db44STomer Tayar dump_buf + offset, 2883c965db44STomer Tayar dump, 28847b6859fbSMintz, Yuval BYTES_TO_DWORDS 28857b6859fbSMintz, Yuval (s_reset_regs_defs[i].addr), 1, 2886d52c89f1SMichal Kalderon false, SPLIT_TYPE_NONE, 0); 2887c965db44STomer Tayar num_regs++; 2888c965db44STomer Tayar } 2889c965db44STomer Tayar 2890c965db44STomer Tayar /* Write header */ 2891c965db44STomer Tayar if (dump) 2892c965db44STomer Tayar qed_grc_dump_regs_hdr(dump_buf, 2893d52c89f1SMichal Kalderon true, num_regs, SPLIT_TYPE_NONE, 2894d52c89f1SMichal Kalderon 0, NULL, NULL); 28957b6859fbSMintz, Yuval 2896c965db44STomer Tayar return offset; 2897c965db44STomer Tayar } 2898c965db44STomer Tayar 28997b6859fbSMintz, Yuval /* Dump registers that are modified during GRC Dump and therefore must be 29007b6859fbSMintz, Yuval * dumped first. Returns the dumped size in dwords. 2901c965db44STomer Tayar */ 2902c965db44STomer Tayar static u32 qed_grc_dump_modified_regs(struct qed_hwfn *p_hwfn, 2903c965db44STomer Tayar struct qed_ptt *p_ptt, 2904c965db44STomer Tayar u32 *dump_buf, bool dump) 2905c965db44STomer Tayar { 2906c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 29077b6859fbSMintz, Yuval u32 block_id, offset = 0, num_reg_entries = 0; 29087b6859fbSMintz, Yuval const struct dbg_attn_reg *attn_reg_arr; 2909c965db44STomer Tayar u8 storm_id, reg_idx, num_attn_regs; 2910c965db44STomer Tayar 2911c965db44STomer Tayar /* Calculate header size */ 2912c965db44STomer Tayar offset += qed_grc_dump_regs_hdr(dump_buf, 2913d52c89f1SMichal Kalderon false, 0, SPLIT_TYPE_NONE, 2914d52c89f1SMichal Kalderon 0, NULL, NULL); 2915c965db44STomer Tayar 2916c965db44STomer Tayar /* Write parity registers */ 2917c965db44STomer Tayar for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) { 2918c965db44STomer Tayar if (dev_data->block_in_reset[block_id] && dump) 2919c965db44STomer Tayar continue; 2920c965db44STomer Tayar 2921c965db44STomer Tayar attn_reg_arr = qed_get_block_attn_regs((enum block_id)block_id, 2922c965db44STomer Tayar ATTN_TYPE_PARITY, 2923c965db44STomer Tayar &num_attn_regs); 29247b6859fbSMintz, Yuval 2925c965db44STomer Tayar for (reg_idx = 0; reg_idx < num_attn_regs; reg_idx++) { 2926c965db44STomer Tayar const struct dbg_attn_reg *reg_data = 2927c965db44STomer Tayar &attn_reg_arr[reg_idx]; 2928c965db44STomer Tayar u16 modes_buf_offset; 2929c965db44STomer Tayar bool eval_mode; 2930be086e7cSMintz, Yuval u32 addr; 2931c965db44STomer Tayar 2932c965db44STomer Tayar /* Check mode */ 2933c965db44STomer Tayar eval_mode = GET_FIELD(reg_data->mode.data, 2934c965db44STomer Tayar DBG_MODE_HDR_EVAL_MODE) > 0; 2935c965db44STomer Tayar modes_buf_offset = 2936c965db44STomer Tayar GET_FIELD(reg_data->mode.data, 2937c965db44STomer Tayar DBG_MODE_HDR_MODES_BUF_OFFSET); 29387b6859fbSMintz, Yuval if (eval_mode && 29397b6859fbSMintz, Yuval !qed_is_mode_match(p_hwfn, &modes_buf_offset)) 29407b6859fbSMintz, Yuval continue; 29417b6859fbSMintz, Yuval 29427b6859fbSMintz, Yuval /* Mode match: read & dump registers */ 2943be086e7cSMintz, Yuval addr = reg_data->mask_address; 29447b6859fbSMintz, Yuval offset += qed_grc_dump_reg_entry(p_hwfn, 2945c965db44STomer Tayar p_ptt, 2946c965db44STomer Tayar dump_buf + offset, 2947c965db44STomer Tayar dump, 2948be086e7cSMintz, Yuval addr, 2949d52c89f1SMichal Kalderon 1, false, 2950d52c89f1SMichal Kalderon SPLIT_TYPE_NONE, 0); 2951be086e7cSMintz, Yuval addr = GET_FIELD(reg_data->data, 2952be086e7cSMintz, Yuval DBG_ATTN_REG_STS_ADDRESS); 29537b6859fbSMintz, Yuval offset += qed_grc_dump_reg_entry(p_hwfn, 2954c965db44STomer Tayar p_ptt, 2955c965db44STomer Tayar dump_buf + offset, 2956c965db44STomer Tayar dump, 2957be086e7cSMintz, Yuval addr, 2958d52c89f1SMichal Kalderon 1, false, 2959d52c89f1SMichal Kalderon SPLIT_TYPE_NONE, 0); 2960c965db44STomer Tayar num_reg_entries += 2; 2961c965db44STomer Tayar } 2962c965db44STomer Tayar } 2963c965db44STomer Tayar 29647b6859fbSMintz, Yuval /* Write Storm stall status registers */ 2965c965db44STomer Tayar for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 29667b6859fbSMintz, Yuval struct storm_defs *storm = &s_storm_defs[storm_id]; 2967be086e7cSMintz, Yuval u32 addr; 2968be086e7cSMintz, Yuval 29697b6859fbSMintz, Yuval if (dev_data->block_in_reset[storm->block_id] && dump) 2970c965db44STomer Tayar continue; 2971c965db44STomer Tayar 2972be086e7cSMintz, Yuval addr = 2973be086e7cSMintz, Yuval BYTES_TO_DWORDS(s_storm_defs[storm_id].sem_fast_mem_addr + 2974be086e7cSMintz, Yuval SEM_FAST_REG_STALLED); 2975c965db44STomer Tayar offset += qed_grc_dump_reg_entry(p_hwfn, 2976c965db44STomer Tayar p_ptt, 2977c965db44STomer Tayar dump_buf + offset, 2978c965db44STomer Tayar dump, 2979be086e7cSMintz, Yuval addr, 29807b6859fbSMintz, Yuval 1, 2981d52c89f1SMichal Kalderon false, SPLIT_TYPE_NONE, 0); 2982c965db44STomer Tayar num_reg_entries++; 2983c965db44STomer Tayar } 2984c965db44STomer Tayar 2985c965db44STomer Tayar /* Write header */ 2986c965db44STomer Tayar if (dump) 2987c965db44STomer Tayar qed_grc_dump_regs_hdr(dump_buf, 2988c965db44STomer Tayar true, 2989d52c89f1SMichal Kalderon num_reg_entries, SPLIT_TYPE_NONE, 2990d52c89f1SMichal Kalderon 0, NULL, NULL); 29917b6859fbSMintz, Yuval 2992c965db44STomer Tayar return offset; 2993c965db44STomer Tayar } 2994c965db44STomer Tayar 2995be086e7cSMintz, Yuval /* Dumps registers that can't be represented in the debug arrays */ 2996be086e7cSMintz, Yuval static u32 qed_grc_dump_special_regs(struct qed_hwfn *p_hwfn, 2997be086e7cSMintz, Yuval struct qed_ptt *p_ptt, 2998be086e7cSMintz, Yuval u32 *dump_buf, bool dump) 2999be086e7cSMintz, Yuval { 3000be086e7cSMintz, Yuval u32 offset = 0, addr; 3001be086e7cSMintz, Yuval 3002be086e7cSMintz, Yuval offset += qed_grc_dump_regs_hdr(dump_buf, 3003d52c89f1SMichal Kalderon dump, 2, SPLIT_TYPE_NONE, 0, 3004d52c89f1SMichal Kalderon NULL, NULL); 3005be086e7cSMintz, Yuval 3006be086e7cSMintz, Yuval /* Dump R/TDIF_REG_DEBUG_ERROR_INFO_SIZE (every 8'th register should be 3007be086e7cSMintz, Yuval * skipped). 3008be086e7cSMintz, Yuval */ 3009be086e7cSMintz, Yuval addr = BYTES_TO_DWORDS(RDIF_REG_DEBUG_ERROR_INFO); 3010be086e7cSMintz, Yuval offset += qed_grc_dump_reg_entry_skip(p_hwfn, 3011be086e7cSMintz, Yuval p_ptt, 3012be086e7cSMintz, Yuval dump_buf + offset, 3013be086e7cSMintz, Yuval dump, 3014be086e7cSMintz, Yuval addr, 3015be086e7cSMintz, Yuval RDIF_REG_DEBUG_ERROR_INFO_SIZE, 3016be086e7cSMintz, Yuval 7, 3017be086e7cSMintz, Yuval 1); 3018be086e7cSMintz, Yuval addr = BYTES_TO_DWORDS(TDIF_REG_DEBUG_ERROR_INFO); 3019be086e7cSMintz, Yuval offset += 3020be086e7cSMintz, Yuval qed_grc_dump_reg_entry_skip(p_hwfn, 3021be086e7cSMintz, Yuval p_ptt, 3022be086e7cSMintz, Yuval dump_buf + offset, 3023be086e7cSMintz, Yuval dump, 3024be086e7cSMintz, Yuval addr, 3025be086e7cSMintz, Yuval TDIF_REG_DEBUG_ERROR_INFO_SIZE, 3026be086e7cSMintz, Yuval 7, 3027be086e7cSMintz, Yuval 1); 3028be086e7cSMintz, Yuval 3029be086e7cSMintz, Yuval return offset; 3030be086e7cSMintz, Yuval } 3031be086e7cSMintz, Yuval 30327b6859fbSMintz, Yuval /* Dumps a GRC memory header (section and params). Returns the dumped size in 30337b6859fbSMintz, Yuval * dwords. The following parameters are dumped: 30347b6859fbSMintz, Yuval * - name: dumped only if it's not NULL. 30357b6859fbSMintz, Yuval * - addr: in dwords, dumped only if name is NULL. 30367b6859fbSMintz, Yuval * - len: in dwords, always dumped. 30377b6859fbSMintz, Yuval * - width: dumped if it's not zero. 30387b6859fbSMintz, Yuval * - packed: dumped only if it's not false. 30397b6859fbSMintz, Yuval * - mem_group: always dumped. 30407b6859fbSMintz, Yuval * - is_storm: true only if the memory is related to a Storm. 30417b6859fbSMintz, Yuval * - storm_letter: valid only if is_storm is true. 30427b6859fbSMintz, Yuval * 3043c965db44STomer Tayar */ 3044c965db44STomer Tayar static u32 qed_grc_dump_mem_hdr(struct qed_hwfn *p_hwfn, 3045c965db44STomer Tayar u32 *dump_buf, 3046c965db44STomer Tayar bool dump, 3047c965db44STomer Tayar const char *name, 3048be086e7cSMintz, Yuval u32 addr, 3049be086e7cSMintz, Yuval u32 len, 3050c965db44STomer Tayar u32 bit_width, 3051c965db44STomer Tayar bool packed, 3052c965db44STomer Tayar const char *mem_group, 3053c965db44STomer Tayar bool is_storm, char storm_letter) 3054c965db44STomer Tayar { 3055c965db44STomer Tayar u8 num_params = 3; 3056c965db44STomer Tayar u32 offset = 0; 3057c965db44STomer Tayar char buf[64]; 3058c965db44STomer Tayar 3059be086e7cSMintz, Yuval if (!len) 3060c965db44STomer Tayar DP_NOTICE(p_hwfn, 3061c965db44STomer Tayar "Unexpected GRC Dump error: dumped memory size must be non-zero\n"); 30627b6859fbSMintz, Yuval 3063c965db44STomer Tayar if (bit_width) 3064c965db44STomer Tayar num_params++; 3065c965db44STomer Tayar if (packed) 3066c965db44STomer Tayar num_params++; 3067c965db44STomer Tayar 3068c965db44STomer Tayar /* Dump section header */ 3069c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, 3070c965db44STomer Tayar dump, "grc_mem", num_params); 30717b6859fbSMintz, Yuval 3072c965db44STomer Tayar if (name) { 3073c965db44STomer Tayar /* Dump name */ 3074c965db44STomer Tayar if (is_storm) { 3075c965db44STomer Tayar strcpy(buf, "?STORM_"); 3076c965db44STomer Tayar buf[0] = storm_letter; 3077c965db44STomer Tayar strcpy(buf + strlen(buf), name); 3078c965db44STomer Tayar } else { 3079c965db44STomer Tayar strcpy(buf, name); 3080c965db44STomer Tayar } 3081c965db44STomer Tayar 3082c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 3083c965db44STomer Tayar dump, "name", buf); 3084c965db44STomer Tayar } else { 3085c965db44STomer Tayar /* Dump address */ 30867b6859fbSMintz, Yuval u32 addr_in_bytes = DWORDS_TO_BYTES(addr); 30877b6859fbSMintz, Yuval 3088c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 30897b6859fbSMintz, Yuval dump, "addr", addr_in_bytes); 3090c965db44STomer Tayar } 3091c965db44STomer Tayar 3092c965db44STomer Tayar /* Dump len */ 3093be086e7cSMintz, Yuval offset += qed_dump_num_param(dump_buf + offset, dump, "len", len); 3094c965db44STomer Tayar 3095c965db44STomer Tayar /* Dump bit width */ 3096c965db44STomer Tayar if (bit_width) 3097c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 3098c965db44STomer Tayar dump, "width", bit_width); 3099c965db44STomer Tayar 3100c965db44STomer Tayar /* Dump packed */ 3101c965db44STomer Tayar if (packed) 3102c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 3103c965db44STomer Tayar dump, "packed", 1); 3104c965db44STomer Tayar 3105c965db44STomer Tayar /* Dump reg type */ 3106c965db44STomer Tayar if (is_storm) { 3107c965db44STomer Tayar strcpy(buf, "?STORM_"); 3108c965db44STomer Tayar buf[0] = storm_letter; 3109c965db44STomer Tayar strcpy(buf + strlen(buf), mem_group); 3110c965db44STomer Tayar } else { 3111c965db44STomer Tayar strcpy(buf, mem_group); 3112c965db44STomer Tayar } 3113c965db44STomer Tayar 3114c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, dump, "type", buf); 31157b6859fbSMintz, Yuval 3116c965db44STomer Tayar return offset; 3117c965db44STomer Tayar } 3118c965db44STomer Tayar 3119c965db44STomer Tayar /* Dumps a single GRC memory. If name is NULL, the memory is stored by address. 3120c965db44STomer Tayar * Returns the dumped size in dwords. 31217b6859fbSMintz, Yuval * The addr and len arguments are specified in dwords. 3122c965db44STomer Tayar */ 3123c965db44STomer Tayar static u32 qed_grc_dump_mem(struct qed_hwfn *p_hwfn, 3124c965db44STomer Tayar struct qed_ptt *p_ptt, 3125c965db44STomer Tayar u32 *dump_buf, 3126c965db44STomer Tayar bool dump, 3127c965db44STomer Tayar const char *name, 3128be086e7cSMintz, Yuval u32 addr, 3129be086e7cSMintz, Yuval u32 len, 31307b6859fbSMintz, Yuval bool wide_bus, 3131c965db44STomer Tayar u32 bit_width, 3132c965db44STomer Tayar bool packed, 3133c965db44STomer Tayar const char *mem_group, 3134c965db44STomer Tayar bool is_storm, char storm_letter) 3135c965db44STomer Tayar { 3136c965db44STomer Tayar u32 offset = 0; 3137c965db44STomer Tayar 3138c965db44STomer Tayar offset += qed_grc_dump_mem_hdr(p_hwfn, 3139c965db44STomer Tayar dump_buf + offset, 3140c965db44STomer Tayar dump, 3141c965db44STomer Tayar name, 3142be086e7cSMintz, Yuval addr, 3143be086e7cSMintz, Yuval len, 3144c965db44STomer Tayar bit_width, 3145c965db44STomer Tayar packed, 3146c965db44STomer Tayar mem_group, is_storm, storm_letter); 3147be086e7cSMintz, Yuval offset += qed_grc_dump_addr_range(p_hwfn, 3148be086e7cSMintz, Yuval p_ptt, 31497b6859fbSMintz, Yuval dump_buf + offset, 3150d52c89f1SMichal Kalderon dump, addr, len, wide_bus, 3151d52c89f1SMichal Kalderon SPLIT_TYPE_NONE, 0); 31527b6859fbSMintz, Yuval 3153c965db44STomer Tayar return offset; 3154c965db44STomer Tayar } 3155c965db44STomer Tayar 3156c965db44STomer Tayar /* Dumps GRC memories entries. Returns the dumped size in dwords. */ 3157c965db44STomer Tayar static u32 qed_grc_dump_mem_entries(struct qed_hwfn *p_hwfn, 3158c965db44STomer Tayar struct qed_ptt *p_ptt, 3159c965db44STomer Tayar struct dbg_array input_mems_arr, 3160c965db44STomer Tayar u32 *dump_buf, bool dump) 3161c965db44STomer Tayar { 3162c965db44STomer Tayar u32 i, offset = 0, input_offset = 0; 3163c965db44STomer Tayar bool mode_match = true; 3164c965db44STomer Tayar 3165c965db44STomer Tayar while (input_offset < input_mems_arr.size_in_dwords) { 3166c965db44STomer Tayar const struct dbg_dump_cond_hdr *cond_hdr; 31677b6859fbSMintz, Yuval u16 modes_buf_offset; 3168c965db44STomer Tayar u32 num_entries; 3169c965db44STomer Tayar bool eval_mode; 3170c965db44STomer Tayar 3171c965db44STomer Tayar cond_hdr = (const struct dbg_dump_cond_hdr *) 3172c965db44STomer Tayar &input_mems_arr.ptr[input_offset++]; 31737b6859fbSMintz, Yuval num_entries = cond_hdr->data_size / MEM_DUMP_ENTRY_SIZE_DWORDS; 3174c965db44STomer Tayar 3175c965db44STomer Tayar /* Check required mode */ 31767b6859fbSMintz, Yuval eval_mode = GET_FIELD(cond_hdr->mode.data, 31777b6859fbSMintz, Yuval DBG_MODE_HDR_EVAL_MODE) > 0; 3178c965db44STomer Tayar if (eval_mode) { 31797b6859fbSMintz, Yuval modes_buf_offset = 3180c965db44STomer Tayar GET_FIELD(cond_hdr->mode.data, 3181c965db44STomer Tayar DBG_MODE_HDR_MODES_BUF_OFFSET); 3182c965db44STomer Tayar mode_match = qed_is_mode_match(p_hwfn, 3183c965db44STomer Tayar &modes_buf_offset); 3184c965db44STomer Tayar } 3185c965db44STomer Tayar 3186c965db44STomer Tayar if (!mode_match) { 3187c965db44STomer Tayar input_offset += cond_hdr->data_size; 3188c965db44STomer Tayar continue; 3189c965db44STomer Tayar } 3190c965db44STomer Tayar 3191c965db44STomer Tayar for (i = 0; i < num_entries; 3192c965db44STomer Tayar i++, input_offset += MEM_DUMP_ENTRY_SIZE_DWORDS) { 3193c965db44STomer Tayar const struct dbg_dump_mem *mem = 3194c965db44STomer Tayar (const struct dbg_dump_mem *) 3195c965db44STomer Tayar &input_mems_arr.ptr[input_offset]; 31967b6859fbSMintz, Yuval u8 mem_group_id = GET_FIELD(mem->dword0, 3197c965db44STomer Tayar DBG_DUMP_MEM_MEM_GROUP_ID); 31987b6859fbSMintz, Yuval bool is_storm = false, mem_wide_bus; 31997b6859fbSMintz, Yuval enum dbg_grc_params grc_param; 32007b6859fbSMintz, Yuval char storm_letter = 'a'; 32017b6859fbSMintz, Yuval enum block_id block_id; 32027b6859fbSMintz, Yuval u32 mem_addr, mem_len; 32037b6859fbSMintz, Yuval 3204c965db44STomer Tayar if (mem_group_id >= MEM_GROUPS_NUM) { 3205c965db44STomer Tayar DP_NOTICE(p_hwfn, "Invalid mem_group_id\n"); 3206c965db44STomer Tayar return 0; 3207c965db44STomer Tayar } 3208c965db44STomer Tayar 32097b6859fbSMintz, Yuval block_id = (enum block_id)cond_hdr->block_id; 32107b6859fbSMintz, Yuval if (!qed_grc_is_mem_included(p_hwfn, 32117b6859fbSMintz, Yuval block_id, 32127b6859fbSMintz, Yuval mem_group_id)) 32137b6859fbSMintz, Yuval continue; 32147b6859fbSMintz, Yuval 32157b6859fbSMintz, Yuval mem_addr = GET_FIELD(mem->dword0, DBG_DUMP_MEM_ADDRESS); 32167b6859fbSMintz, Yuval mem_len = GET_FIELD(mem->dword1, DBG_DUMP_MEM_LENGTH); 32177b6859fbSMintz, Yuval mem_wide_bus = GET_FIELD(mem->dword1, 32187b6859fbSMintz, Yuval DBG_DUMP_MEM_WIDE_BUS); 3219c965db44STomer Tayar 3220c965db44STomer Tayar /* Update memory length for CCFC/TCFC memories 3221c965db44STomer Tayar * according to number of LCIDs/LTIDs. 3222c965db44STomer Tayar */ 3223be086e7cSMintz, Yuval if (mem_group_id == MEM_GROUP_CONN_CFC_MEM) { 32247b6859fbSMintz, Yuval if (mem_len % MAX_LCIDS) { 3225be086e7cSMintz, Yuval DP_NOTICE(p_hwfn, 3226be086e7cSMintz, Yuval "Invalid CCFC connection memory size\n"); 3227be086e7cSMintz, Yuval return 0; 3228be086e7cSMintz, Yuval } 3229be086e7cSMintz, Yuval 3230be086e7cSMintz, Yuval grc_param = DBG_GRC_PARAM_NUM_LCIDS; 32317b6859fbSMintz, Yuval mem_len = qed_grc_get_param(p_hwfn, grc_param) * 3232be086e7cSMintz, Yuval (mem_len / MAX_LCIDS); 32337b6859fbSMintz, Yuval } else if (mem_group_id == MEM_GROUP_TASK_CFC_MEM) { 32347b6859fbSMintz, Yuval if (mem_len % MAX_LTIDS) { 3235be086e7cSMintz, Yuval DP_NOTICE(p_hwfn, 3236be086e7cSMintz, Yuval "Invalid TCFC task memory size\n"); 3237be086e7cSMintz, Yuval return 0; 3238be086e7cSMintz, Yuval } 3239be086e7cSMintz, Yuval 3240be086e7cSMintz, Yuval grc_param = DBG_GRC_PARAM_NUM_LTIDS; 32417b6859fbSMintz, Yuval mem_len = qed_grc_get_param(p_hwfn, grc_param) * 3242be086e7cSMintz, Yuval (mem_len / MAX_LTIDS); 3243be086e7cSMintz, Yuval } 3244c965db44STomer Tayar 32457b6859fbSMintz, Yuval /* If memory is associated with Storm, update Storm 32467b6859fbSMintz, Yuval * details. 3247c965db44STomer Tayar */ 32487b6859fbSMintz, Yuval if (s_block_defs 32497b6859fbSMintz, Yuval [cond_hdr->block_id]->associated_to_storm) { 3250c965db44STomer Tayar is_storm = true; 3251c965db44STomer Tayar storm_letter = 32527b6859fbSMintz, Yuval s_storm_defs[s_block_defs 32537b6859fbSMintz, Yuval [cond_hdr->block_id]-> 3254c965db44STomer Tayar storm_id].letter; 3255c965db44STomer Tayar } 3256c965db44STomer Tayar 3257c965db44STomer Tayar /* Dump memory */ 32587b6859fbSMintz, Yuval offset += qed_grc_dump_mem(p_hwfn, 32597b6859fbSMintz, Yuval p_ptt, 32607b6859fbSMintz, Yuval dump_buf + offset, 32617b6859fbSMintz, Yuval dump, 32627b6859fbSMintz, Yuval NULL, 32637b6859fbSMintz, Yuval mem_addr, 32647b6859fbSMintz, Yuval mem_len, 32657b6859fbSMintz, Yuval mem_wide_bus, 32667b6859fbSMintz, Yuval 0, 3267c965db44STomer Tayar false, 3268c965db44STomer Tayar s_mem_group_names[mem_group_id], 32697b6859fbSMintz, Yuval is_storm, 32707b6859fbSMintz, Yuval storm_letter); 3271c965db44STomer Tayar } 3272c965db44STomer Tayar } 3273c965db44STomer Tayar 3274c965db44STomer Tayar return offset; 3275c965db44STomer Tayar } 3276c965db44STomer Tayar 3277c965db44STomer Tayar /* Dumps GRC memories according to the input array dump_mem. 3278c965db44STomer Tayar * Returns the dumped size in dwords. 3279c965db44STomer Tayar */ 3280c965db44STomer Tayar static u32 qed_grc_dump_memories(struct qed_hwfn *p_hwfn, 3281c965db44STomer Tayar struct qed_ptt *p_ptt, 3282c965db44STomer Tayar u32 *dump_buf, bool dump) 3283c965db44STomer Tayar { 3284c965db44STomer Tayar u32 offset = 0, input_offset = 0; 3285c965db44STomer Tayar 3286c965db44STomer Tayar while (input_offset < 3287c965db44STomer Tayar s_dbg_arrays[BIN_BUF_DBG_DUMP_MEM].size_in_dwords) { 32887b6859fbSMintz, Yuval const struct dbg_dump_split_hdr *split_hdr; 32897b6859fbSMintz, Yuval struct dbg_array curr_input_mems_arr; 3290d52c89f1SMichal Kalderon enum init_split_types split_type; 32917b6859fbSMintz, Yuval u32 split_data_size; 32927b6859fbSMintz, Yuval 32937b6859fbSMintz, Yuval split_hdr = (const struct dbg_dump_split_hdr *) 3294c965db44STomer Tayar &s_dbg_arrays[BIN_BUF_DBG_DUMP_MEM].ptr[input_offset++]; 3295d52c89f1SMichal Kalderon split_type = 32967b6859fbSMintz, Yuval GET_FIELD(split_hdr->hdr, 3297c965db44STomer Tayar DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID); 32987b6859fbSMintz, Yuval split_data_size = 32997b6859fbSMintz, Yuval GET_FIELD(split_hdr->hdr, 3300c965db44STomer Tayar DBG_DUMP_SPLIT_HDR_DATA_SIZE); 33017b6859fbSMintz, Yuval curr_input_mems_arr.ptr = 33027b6859fbSMintz, Yuval &s_dbg_arrays[BIN_BUF_DBG_DUMP_MEM].ptr[input_offset]; 33037b6859fbSMintz, Yuval curr_input_mems_arr.size_in_dwords = split_data_size; 3304c965db44STomer Tayar 3305d52c89f1SMichal Kalderon if (split_type == SPLIT_TYPE_NONE) 3306c965db44STomer Tayar offset += qed_grc_dump_mem_entries(p_hwfn, 3307c965db44STomer Tayar p_ptt, 3308c965db44STomer Tayar curr_input_mems_arr, 3309c965db44STomer Tayar dump_buf + offset, 3310c965db44STomer Tayar dump); 3311d52c89f1SMichal Kalderon else 3312c965db44STomer Tayar DP_NOTICE(p_hwfn, 3313c965db44STomer Tayar "Dumping split memories is currently not supported\n"); 3314c965db44STomer Tayar 3315c965db44STomer Tayar input_offset += split_data_size; 3316c965db44STomer Tayar } 3317c965db44STomer Tayar 3318c965db44STomer Tayar return offset; 3319c965db44STomer Tayar } 3320c965db44STomer Tayar 3321c965db44STomer Tayar /* Dumps GRC context data for the specified Storm. 3322c965db44STomer Tayar * Returns the dumped size in dwords. 33237b6859fbSMintz, Yuval * The lid_size argument is specified in quad-regs. 3324c965db44STomer Tayar */ 3325c965db44STomer Tayar static u32 qed_grc_dump_ctx_data(struct qed_hwfn *p_hwfn, 3326c965db44STomer Tayar struct qed_ptt *p_ptt, 3327c965db44STomer Tayar u32 *dump_buf, 3328c965db44STomer Tayar bool dump, 3329c965db44STomer Tayar const char *name, 3330c965db44STomer Tayar u32 num_lids, 3331c965db44STomer Tayar u32 lid_size, 3332c965db44STomer Tayar u32 rd_reg_addr, 3333c965db44STomer Tayar u8 storm_id) 3334c965db44STomer Tayar { 33357b6859fbSMintz, Yuval struct storm_defs *storm = &s_storm_defs[storm_id]; 33367b6859fbSMintz, Yuval u32 i, lid, total_size, offset = 0; 3337c965db44STomer Tayar 3338c965db44STomer Tayar if (!lid_size) 3339c965db44STomer Tayar return 0; 33407b6859fbSMintz, Yuval 3341c965db44STomer Tayar lid_size *= BYTES_IN_DWORD; 3342c965db44STomer Tayar total_size = num_lids * lid_size; 33437b6859fbSMintz, Yuval 3344c965db44STomer Tayar offset += qed_grc_dump_mem_hdr(p_hwfn, 3345c965db44STomer Tayar dump_buf + offset, 3346c965db44STomer Tayar dump, 3347c965db44STomer Tayar name, 3348c965db44STomer Tayar 0, 3349c965db44STomer Tayar total_size, 3350c965db44STomer Tayar lid_size * 32, 33517b6859fbSMintz, Yuval false, name, true, storm->letter); 33527b6859fbSMintz, Yuval 33537b6859fbSMintz, Yuval if (!dump) 33547b6859fbSMintz, Yuval return offset + total_size; 3355c965db44STomer Tayar 3356c965db44STomer Tayar /* Dump context data */ 3357c965db44STomer Tayar for (lid = 0; lid < num_lids; lid++) { 3358c965db44STomer Tayar for (i = 0; i < lid_size; i++, offset++) { 3359c965db44STomer Tayar qed_wr(p_hwfn, 33607b6859fbSMintz, Yuval p_ptt, storm->cm_ctx_wr_addr, (i << 9) | lid); 3361c965db44STomer Tayar *(dump_buf + offset) = qed_rd(p_hwfn, 33627b6859fbSMintz, Yuval p_ptt, rd_reg_addr); 3363c965db44STomer Tayar } 3364c965db44STomer Tayar } 3365c965db44STomer Tayar 3366c965db44STomer Tayar return offset; 3367c965db44STomer Tayar } 3368c965db44STomer Tayar 3369c965db44STomer Tayar /* Dumps GRC contexts. Returns the dumped size in dwords. */ 3370c965db44STomer Tayar static u32 qed_grc_dump_ctx(struct qed_hwfn *p_hwfn, 3371c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *dump_buf, bool dump) 3372c965db44STomer Tayar { 33737b6859fbSMintz, Yuval enum dbg_grc_params grc_param; 3374c965db44STomer Tayar u32 offset = 0; 3375c965db44STomer Tayar u8 storm_id; 3376c965db44STomer Tayar 3377c965db44STomer Tayar for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 33787b6859fbSMintz, Yuval struct storm_defs *storm = &s_storm_defs[storm_id]; 33797b6859fbSMintz, Yuval 3380c965db44STomer Tayar if (!qed_grc_is_storm_included(p_hwfn, 3381c965db44STomer Tayar (enum dbg_storms)storm_id)) 3382c965db44STomer Tayar continue; 3383c965db44STomer Tayar 3384c965db44STomer Tayar /* Dump Conn AG context size */ 33857b6859fbSMintz, Yuval grc_param = DBG_GRC_PARAM_NUM_LCIDS; 3386c965db44STomer Tayar offset += 3387c965db44STomer Tayar qed_grc_dump_ctx_data(p_hwfn, 3388c965db44STomer Tayar p_ptt, 3389c965db44STomer Tayar dump_buf + offset, 3390c965db44STomer Tayar dump, 3391c965db44STomer Tayar "CONN_AG_CTX", 3392c965db44STomer Tayar qed_grc_get_param(p_hwfn, 33937b6859fbSMintz, Yuval grc_param), 33947b6859fbSMintz, Yuval storm->cm_conn_ag_ctx_lid_size, 33957b6859fbSMintz, Yuval storm->cm_conn_ag_ctx_rd_addr, 3396c965db44STomer Tayar storm_id); 3397c965db44STomer Tayar 3398c965db44STomer Tayar /* Dump Conn ST context size */ 33997b6859fbSMintz, Yuval grc_param = DBG_GRC_PARAM_NUM_LCIDS; 3400c965db44STomer Tayar offset += 3401c965db44STomer Tayar qed_grc_dump_ctx_data(p_hwfn, 3402c965db44STomer Tayar p_ptt, 3403c965db44STomer Tayar dump_buf + offset, 3404c965db44STomer Tayar dump, 3405c965db44STomer Tayar "CONN_ST_CTX", 3406c965db44STomer Tayar qed_grc_get_param(p_hwfn, 34077b6859fbSMintz, Yuval grc_param), 34087b6859fbSMintz, Yuval storm->cm_conn_st_ctx_lid_size, 34097b6859fbSMintz, Yuval storm->cm_conn_st_ctx_rd_addr, 3410c965db44STomer Tayar storm_id); 3411c965db44STomer Tayar 3412c965db44STomer Tayar /* Dump Task AG context size */ 34137b6859fbSMintz, Yuval grc_param = DBG_GRC_PARAM_NUM_LTIDS; 3414c965db44STomer Tayar offset += 3415c965db44STomer Tayar qed_grc_dump_ctx_data(p_hwfn, 3416c965db44STomer Tayar p_ptt, 3417c965db44STomer Tayar dump_buf + offset, 3418c965db44STomer Tayar dump, 3419c965db44STomer Tayar "TASK_AG_CTX", 3420c965db44STomer Tayar qed_grc_get_param(p_hwfn, 34217b6859fbSMintz, Yuval grc_param), 34227b6859fbSMintz, Yuval storm->cm_task_ag_ctx_lid_size, 34237b6859fbSMintz, Yuval storm->cm_task_ag_ctx_rd_addr, 3424c965db44STomer Tayar storm_id); 3425c965db44STomer Tayar 3426c965db44STomer Tayar /* Dump Task ST context size */ 34277b6859fbSMintz, Yuval grc_param = DBG_GRC_PARAM_NUM_LTIDS; 3428c965db44STomer Tayar offset += 3429c965db44STomer Tayar qed_grc_dump_ctx_data(p_hwfn, 3430c965db44STomer Tayar p_ptt, 3431c965db44STomer Tayar dump_buf + offset, 3432c965db44STomer Tayar dump, 3433c965db44STomer Tayar "TASK_ST_CTX", 3434c965db44STomer Tayar qed_grc_get_param(p_hwfn, 34357b6859fbSMintz, Yuval grc_param), 34367b6859fbSMintz, Yuval storm->cm_task_st_ctx_lid_size, 34377b6859fbSMintz, Yuval storm->cm_task_st_ctx_rd_addr, 3438c965db44STomer Tayar storm_id); 3439c965db44STomer Tayar } 3440c965db44STomer Tayar 3441c965db44STomer Tayar return offset; 3442c965db44STomer Tayar } 3443c965db44STomer Tayar 3444c965db44STomer Tayar /* Dumps GRC IORs data. Returns the dumped size in dwords. */ 3445c965db44STomer Tayar static u32 qed_grc_dump_iors(struct qed_hwfn *p_hwfn, 3446c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *dump_buf, bool dump) 3447c965db44STomer Tayar { 3448c965db44STomer Tayar char buf[10] = "IOR_SET_?"; 34497b6859fbSMintz, Yuval u32 addr, offset = 0; 3450c965db44STomer Tayar u8 storm_id, set_id; 3451c965db44STomer Tayar 3452c965db44STomer Tayar for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 3453be086e7cSMintz, Yuval struct storm_defs *storm = &s_storm_defs[storm_id]; 3454c965db44STomer Tayar 3455be086e7cSMintz, Yuval if (!qed_grc_is_storm_included(p_hwfn, 3456be086e7cSMintz, Yuval (enum dbg_storms)storm_id)) 3457be086e7cSMintz, Yuval continue; 3458be086e7cSMintz, Yuval 3459be086e7cSMintz, Yuval for (set_id = 0; set_id < NUM_IOR_SETS; set_id++) { 34607b6859fbSMintz, Yuval addr = BYTES_TO_DWORDS(storm->sem_fast_mem_addr + 34617b6859fbSMintz, Yuval SEM_FAST_REG_STORM_REG_FILE) + 34627b6859fbSMintz, Yuval IOR_SET_OFFSET(set_id); 3463a3f72307SDenis Bolotin if (strlen(buf) > 0) 3464c965db44STomer Tayar buf[strlen(buf) - 1] = '0' + set_id; 3465c965db44STomer Tayar offset += qed_grc_dump_mem(p_hwfn, 3466c965db44STomer Tayar p_ptt, 3467c965db44STomer Tayar dump_buf + offset, 3468c965db44STomer Tayar dump, 3469c965db44STomer Tayar buf, 3470c965db44STomer Tayar addr, 3471c965db44STomer Tayar IORS_PER_SET, 34727b6859fbSMintz, Yuval false, 3473c965db44STomer Tayar 32, 3474c965db44STomer Tayar false, 3475c965db44STomer Tayar "ior", 3476c965db44STomer Tayar true, 3477be086e7cSMintz, Yuval storm->letter); 3478c965db44STomer Tayar } 3479c965db44STomer Tayar } 3480c965db44STomer Tayar 3481c965db44STomer Tayar return offset; 3482c965db44STomer Tayar } 3483c965db44STomer Tayar 3484c965db44STomer Tayar /* Dump VFC CAM. Returns the dumped size in dwords. */ 3485c965db44STomer Tayar static u32 qed_grc_dump_vfc_cam(struct qed_hwfn *p_hwfn, 3486c965db44STomer Tayar struct qed_ptt *p_ptt, 3487c965db44STomer Tayar u32 *dump_buf, bool dump, u8 storm_id) 3488c965db44STomer Tayar { 3489c965db44STomer Tayar u32 total_size = VFC_CAM_NUM_ROWS * VFC_CAM_RESP_DWORDS; 34907b6859fbSMintz, Yuval struct storm_defs *storm = &s_storm_defs[storm_id]; 3491c965db44STomer Tayar u32 cam_addr[VFC_CAM_ADDR_DWORDS] = { 0 }; 3492c965db44STomer Tayar u32 cam_cmd[VFC_CAM_CMD_DWORDS] = { 0 }; 34937b6859fbSMintz, Yuval u32 row, i, offset = 0; 3494c965db44STomer Tayar 3495c965db44STomer Tayar offset += qed_grc_dump_mem_hdr(p_hwfn, 3496c965db44STomer Tayar dump_buf + offset, 3497c965db44STomer Tayar dump, 3498c965db44STomer Tayar "vfc_cam", 3499c965db44STomer Tayar 0, 3500c965db44STomer Tayar total_size, 3501c965db44STomer Tayar 256, 35027b6859fbSMintz, Yuval false, "vfc_cam", true, storm->letter); 35037b6859fbSMintz, Yuval 35047b6859fbSMintz, Yuval if (!dump) 35057b6859fbSMintz, Yuval return offset + total_size; 35067b6859fbSMintz, Yuval 3507c965db44STomer Tayar /* Prepare CAM address */ 3508c965db44STomer Tayar SET_VAR_FIELD(cam_addr, VFC_CAM_ADDR, OP, VFC_OPCODE_CAM_RD); 35097b6859fbSMintz, Yuval 3510c965db44STomer Tayar for (row = 0; row < VFC_CAM_NUM_ROWS; 3511c965db44STomer Tayar row++, offset += VFC_CAM_RESP_DWORDS) { 3512c965db44STomer Tayar /* Write VFC CAM command */ 3513c965db44STomer Tayar SET_VAR_FIELD(cam_cmd, VFC_CAM_CMD, ROW, row); 3514c965db44STomer Tayar ARR_REG_WR(p_hwfn, 3515c965db44STomer Tayar p_ptt, 35167b6859fbSMintz, Yuval storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_WR, 3517c965db44STomer Tayar cam_cmd, VFC_CAM_CMD_DWORDS); 3518c965db44STomer Tayar 3519c965db44STomer Tayar /* Write VFC CAM address */ 3520c965db44STomer Tayar ARR_REG_WR(p_hwfn, 3521c965db44STomer Tayar p_ptt, 35227b6859fbSMintz, Yuval storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_ADDR, 3523c965db44STomer Tayar cam_addr, VFC_CAM_ADDR_DWORDS); 3524c965db44STomer Tayar 3525c965db44STomer Tayar /* Read VFC CAM read response */ 3526c965db44STomer Tayar ARR_REG_RD(p_hwfn, 3527c965db44STomer Tayar p_ptt, 35287b6859fbSMintz, Yuval storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_RD, 3529c965db44STomer Tayar dump_buf + offset, VFC_CAM_RESP_DWORDS); 3530c965db44STomer Tayar } 3531c965db44STomer Tayar 3532c965db44STomer Tayar return offset; 3533c965db44STomer Tayar } 3534c965db44STomer Tayar 3535c965db44STomer Tayar /* Dump VFC RAM. Returns the dumped size in dwords. */ 3536c965db44STomer Tayar static u32 qed_grc_dump_vfc_ram(struct qed_hwfn *p_hwfn, 3537c965db44STomer Tayar struct qed_ptt *p_ptt, 3538c965db44STomer Tayar u32 *dump_buf, 3539c965db44STomer Tayar bool dump, 3540c965db44STomer Tayar u8 storm_id, struct vfc_ram_defs *ram_defs) 3541c965db44STomer Tayar { 3542c965db44STomer Tayar u32 total_size = ram_defs->num_rows * VFC_RAM_RESP_DWORDS; 35437b6859fbSMintz, Yuval struct storm_defs *storm = &s_storm_defs[storm_id]; 3544c965db44STomer Tayar u32 ram_addr[VFC_RAM_ADDR_DWORDS] = { 0 }; 3545c965db44STomer Tayar u32 ram_cmd[VFC_RAM_CMD_DWORDS] = { 0 }; 35467b6859fbSMintz, Yuval u32 row, i, offset = 0; 3547c965db44STomer Tayar 3548c965db44STomer Tayar offset += qed_grc_dump_mem_hdr(p_hwfn, 3549c965db44STomer Tayar dump_buf + offset, 3550c965db44STomer Tayar dump, 3551c965db44STomer Tayar ram_defs->mem_name, 3552c965db44STomer Tayar 0, 3553c965db44STomer Tayar total_size, 3554c965db44STomer Tayar 256, 3555c965db44STomer Tayar false, 3556c965db44STomer Tayar ram_defs->type_name, 35577b6859fbSMintz, Yuval true, storm->letter); 3558c965db44STomer Tayar 3559c965db44STomer Tayar /* Prepare RAM address */ 3560c965db44STomer Tayar SET_VAR_FIELD(ram_addr, VFC_RAM_ADDR, OP, VFC_OPCODE_RAM_RD); 3561c965db44STomer Tayar 3562c965db44STomer Tayar if (!dump) 3563c965db44STomer Tayar return offset + total_size; 3564c965db44STomer Tayar 3565c965db44STomer Tayar for (row = ram_defs->base_row; 3566c965db44STomer Tayar row < ram_defs->base_row + ram_defs->num_rows; 3567c965db44STomer Tayar row++, offset += VFC_RAM_RESP_DWORDS) { 3568c965db44STomer Tayar /* Write VFC RAM command */ 3569c965db44STomer Tayar ARR_REG_WR(p_hwfn, 3570c965db44STomer Tayar p_ptt, 35717b6859fbSMintz, Yuval storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_WR, 3572c965db44STomer Tayar ram_cmd, VFC_RAM_CMD_DWORDS); 3573c965db44STomer Tayar 3574c965db44STomer Tayar /* Write VFC RAM address */ 3575c965db44STomer Tayar SET_VAR_FIELD(ram_addr, VFC_RAM_ADDR, ROW, row); 3576c965db44STomer Tayar ARR_REG_WR(p_hwfn, 3577c965db44STomer Tayar p_ptt, 35787b6859fbSMintz, Yuval storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_ADDR, 3579c965db44STomer Tayar ram_addr, VFC_RAM_ADDR_DWORDS); 3580c965db44STomer Tayar 3581c965db44STomer Tayar /* Read VFC RAM read response */ 3582c965db44STomer Tayar ARR_REG_RD(p_hwfn, 3583c965db44STomer Tayar p_ptt, 35847b6859fbSMintz, Yuval storm->sem_fast_mem_addr + SEM_FAST_REG_VFC_DATA_RD, 3585c965db44STomer Tayar dump_buf + offset, VFC_RAM_RESP_DWORDS); 3586c965db44STomer Tayar } 3587c965db44STomer Tayar 3588c965db44STomer Tayar return offset; 3589c965db44STomer Tayar } 3590c965db44STomer Tayar 3591c965db44STomer Tayar /* Dumps GRC VFC data. Returns the dumped size in dwords. */ 3592c965db44STomer Tayar static u32 qed_grc_dump_vfc(struct qed_hwfn *p_hwfn, 3593c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *dump_buf, bool dump) 3594c965db44STomer Tayar { 3595c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 3596c965db44STomer Tayar u8 storm_id, i; 3597c965db44STomer Tayar u32 offset = 0; 3598c965db44STomer Tayar 3599c965db44STomer Tayar for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 36007b6859fbSMintz, Yuval if (!qed_grc_is_storm_included(p_hwfn, 36017b6859fbSMintz, Yuval (enum dbg_storms)storm_id) || 36027b6859fbSMintz, Yuval !s_storm_defs[storm_id].has_vfc || 36037b6859fbSMintz, Yuval (storm_id == DBG_PSTORM_ID && dev_data->platform_id != 36047b6859fbSMintz, Yuval PLATFORM_ASIC)) 36057b6859fbSMintz, Yuval continue; 36067b6859fbSMintz, Yuval 3607c965db44STomer Tayar /* Read CAM */ 3608c965db44STomer Tayar offset += qed_grc_dump_vfc_cam(p_hwfn, 3609c965db44STomer Tayar p_ptt, 3610c965db44STomer Tayar dump_buf + offset, 3611c965db44STomer Tayar dump, storm_id); 3612c965db44STomer Tayar 3613c965db44STomer Tayar /* Read RAM */ 3614c965db44STomer Tayar for (i = 0; i < NUM_VFC_RAM_TYPES; i++) 3615c965db44STomer Tayar offset += qed_grc_dump_vfc_ram(p_hwfn, 3616c965db44STomer Tayar p_ptt, 36177b6859fbSMintz, Yuval dump_buf + offset, 3618c965db44STomer Tayar dump, 3619c965db44STomer Tayar storm_id, 36207b6859fbSMintz, Yuval &s_vfc_ram_defs[i]); 3621c965db44STomer Tayar } 3622c965db44STomer Tayar 3623c965db44STomer Tayar return offset; 3624c965db44STomer Tayar } 3625c965db44STomer Tayar 3626c965db44STomer Tayar /* Dumps GRC RSS data. Returns the dumped size in dwords. */ 3627c965db44STomer Tayar static u32 qed_grc_dump_rss(struct qed_hwfn *p_hwfn, 3628c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *dump_buf, bool dump) 3629c965db44STomer Tayar { 3630c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 3631c965db44STomer Tayar u32 offset = 0; 3632c965db44STomer Tayar u8 rss_mem_id; 3633c965db44STomer Tayar 3634c965db44STomer Tayar for (rss_mem_id = 0; rss_mem_id < NUM_RSS_MEM_TYPES; rss_mem_id++) { 3635da090917STomer Tayar u32 rss_addr, num_entries, total_dwords; 36367b6859fbSMintz, Yuval struct rss_mem_defs *rss_defs; 3637da090917STomer Tayar u32 addr, num_dwords_to_read; 36387b6859fbSMintz, Yuval bool packed; 36397b6859fbSMintz, Yuval 36407b6859fbSMintz, Yuval rss_defs = &s_rss_mem_defs[rss_mem_id]; 36417b6859fbSMintz, Yuval rss_addr = rss_defs->addr; 36427b6859fbSMintz, Yuval num_entries = rss_defs->num_entries[dev_data->chip_id]; 3643da090917STomer Tayar total_dwords = (num_entries * rss_defs->entry_width) / 32; 3644da090917STomer Tayar packed = (rss_defs->entry_width == 16); 3645c965db44STomer Tayar 3646c965db44STomer Tayar offset += qed_grc_dump_mem_hdr(p_hwfn, 3647c965db44STomer Tayar dump_buf + offset, 3648c965db44STomer Tayar dump, 3649c965db44STomer Tayar rss_defs->mem_name, 3650be086e7cSMintz, Yuval 0, 3651be086e7cSMintz, Yuval total_dwords, 3652da090917STomer Tayar rss_defs->entry_width, 3653c965db44STomer Tayar packed, 3654c965db44STomer Tayar rss_defs->type_name, false, 0); 3655c965db44STomer Tayar 36567b6859fbSMintz, Yuval /* Dump RSS data */ 3657c965db44STomer Tayar if (!dump) { 3658be086e7cSMintz, Yuval offset += total_dwords; 3659c965db44STomer Tayar continue; 3660c965db44STomer Tayar } 3661c965db44STomer Tayar 3662be086e7cSMintz, Yuval addr = BYTES_TO_DWORDS(RSS_REG_RSS_RAM_DATA); 3663da090917STomer Tayar while (total_dwords) { 3664da090917STomer Tayar num_dwords_to_read = min_t(u32, 3665da090917STomer Tayar RSS_REG_RSS_RAM_DATA_SIZE, 3666da090917STomer Tayar total_dwords); 3667be086e7cSMintz, Yuval qed_wr(p_hwfn, p_ptt, RSS_REG_RSS_RAM_ADDR, rss_addr); 3668be086e7cSMintz, Yuval offset += qed_grc_dump_addr_range(p_hwfn, 3669be086e7cSMintz, Yuval p_ptt, 36707b6859fbSMintz, Yuval dump_buf + offset, 3671be086e7cSMintz, Yuval dump, 3672be086e7cSMintz, Yuval addr, 3673da090917STomer Tayar num_dwords_to_read, 3674d52c89f1SMichal Kalderon false, 3675d52c89f1SMichal Kalderon SPLIT_TYPE_NONE, 0); 3676da090917STomer Tayar total_dwords -= num_dwords_to_read; 3677da090917STomer Tayar rss_addr++; 3678c965db44STomer Tayar } 3679c965db44STomer Tayar } 3680c965db44STomer Tayar 3681c965db44STomer Tayar return offset; 3682c965db44STomer Tayar } 3683c965db44STomer Tayar 3684c965db44STomer Tayar /* Dumps GRC Big RAM. Returns the dumped size in dwords. */ 3685c965db44STomer Tayar static u32 qed_grc_dump_big_ram(struct qed_hwfn *p_hwfn, 3686c965db44STomer Tayar struct qed_ptt *p_ptt, 3687c965db44STomer Tayar u32 *dump_buf, bool dump, u8 big_ram_id) 3688c965db44STomer Tayar { 3689c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 3690da090917STomer Tayar u32 block_size, ram_size, offset = 0, reg_val, i; 3691c965db44STomer Tayar char mem_name[12] = "???_BIG_RAM"; 3692c965db44STomer Tayar char type_name[8] = "???_RAM"; 3693be086e7cSMintz, Yuval struct big_ram_defs *big_ram; 3694c965db44STomer Tayar 3695be086e7cSMintz, Yuval big_ram = &s_big_ram_defs[big_ram_id]; 3696da090917STomer Tayar ram_size = big_ram->ram_size[dev_data->chip_id]; 3697da090917STomer Tayar 3698da090917STomer Tayar reg_val = qed_rd(p_hwfn, p_ptt, big_ram->is_256b_reg_addr); 3699da090917STomer Tayar block_size = reg_val & 3700da090917STomer Tayar BIT(big_ram->is_256b_bit_offset[dev_data->chip_id]) ? 256 3701da090917STomer Tayar : 128; 3702c965db44STomer Tayar 3703c7d852e3SDenis Bolotin strncpy(type_name, big_ram->instance_name, BIG_RAM_NAME_LEN); 3704c7d852e3SDenis Bolotin strncpy(mem_name, big_ram->instance_name, BIG_RAM_NAME_LEN); 3705c965db44STomer Tayar 3706c965db44STomer Tayar /* Dump memory header */ 3707c965db44STomer Tayar offset += qed_grc_dump_mem_hdr(p_hwfn, 3708c965db44STomer Tayar dump_buf + offset, 3709c965db44STomer Tayar dump, 3710c965db44STomer Tayar mem_name, 3711c965db44STomer Tayar 0, 3712c965db44STomer Tayar ram_size, 3713da090917STomer Tayar block_size * 8, 3714c965db44STomer Tayar false, type_name, false, 0); 3715c965db44STomer Tayar 37167b6859fbSMintz, Yuval /* Read and dump Big RAM data */ 3717c965db44STomer Tayar if (!dump) 3718c965db44STomer Tayar return offset + ram_size; 3719c965db44STomer Tayar 37207b6859fbSMintz, Yuval /* Dump Big RAM */ 3721da090917STomer Tayar for (i = 0; i < DIV_ROUND_UP(ram_size, BRB_REG_BIG_RAM_DATA_SIZE); 3722da090917STomer Tayar i++) { 3723be086e7cSMintz, Yuval u32 addr, len; 3724be086e7cSMintz, Yuval 3725be086e7cSMintz, Yuval qed_wr(p_hwfn, p_ptt, big_ram->addr_reg_addr, i); 3726be086e7cSMintz, Yuval addr = BYTES_TO_DWORDS(big_ram->data_reg_addr); 3727da090917STomer Tayar len = BRB_REG_BIG_RAM_DATA_SIZE; 3728be086e7cSMintz, Yuval offset += qed_grc_dump_addr_range(p_hwfn, 3729be086e7cSMintz, Yuval p_ptt, 3730be086e7cSMintz, Yuval dump_buf + offset, 3731be086e7cSMintz, Yuval dump, 3732be086e7cSMintz, Yuval addr, 37337b6859fbSMintz, Yuval len, 3734d52c89f1SMichal Kalderon false, SPLIT_TYPE_NONE, 0); 3735c965db44STomer Tayar } 3736c965db44STomer Tayar 3737c965db44STomer Tayar return offset; 3738c965db44STomer Tayar } 3739c965db44STomer Tayar 3740c965db44STomer Tayar static u32 qed_grc_dump_mcp(struct qed_hwfn *p_hwfn, 3741c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *dump_buf, bool dump) 3742c965db44STomer Tayar { 3743c965db44STomer Tayar bool block_enable[MAX_BLOCK_ID] = { 0 }; 3744be086e7cSMintz, Yuval u32 offset = 0, addr; 3745c965db44STomer Tayar bool halted = false; 3746c965db44STomer Tayar 3747c965db44STomer Tayar /* Halt MCP */ 3748be086e7cSMintz, Yuval if (dump && !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_MCP)) { 3749c965db44STomer Tayar halted = !qed_mcp_halt(p_hwfn, p_ptt); 3750c965db44STomer Tayar if (!halted) 3751c965db44STomer Tayar DP_NOTICE(p_hwfn, "MCP halt failed!\n"); 3752c965db44STomer Tayar } 3753c965db44STomer Tayar 3754c965db44STomer Tayar /* Dump MCP scratchpad */ 3755c965db44STomer Tayar offset += qed_grc_dump_mem(p_hwfn, 3756c965db44STomer Tayar p_ptt, 3757c965db44STomer Tayar dump_buf + offset, 3758c965db44STomer Tayar dump, 3759c965db44STomer Tayar NULL, 3760be086e7cSMintz, Yuval BYTES_TO_DWORDS(MCP_REG_SCRATCH), 376121dd79e8STomer Tayar MCP_REG_SCRATCH_SIZE_BB_K2, 37627b6859fbSMintz, Yuval false, 0, false, "MCP", false, 0); 3763c965db44STomer Tayar 3764c965db44STomer Tayar /* Dump MCP cpu_reg_file */ 3765c965db44STomer Tayar offset += qed_grc_dump_mem(p_hwfn, 3766c965db44STomer Tayar p_ptt, 3767c965db44STomer Tayar dump_buf + offset, 3768c965db44STomer Tayar dump, 3769c965db44STomer Tayar NULL, 3770be086e7cSMintz, Yuval BYTES_TO_DWORDS(MCP_REG_CPU_REG_FILE), 3771c965db44STomer Tayar MCP_REG_CPU_REG_FILE_SIZE, 37727b6859fbSMintz, Yuval false, 0, false, "MCP", false, 0); 3773c965db44STomer Tayar 3774c965db44STomer Tayar /* Dump MCP registers */ 3775c965db44STomer Tayar block_enable[BLOCK_MCP] = true; 3776c965db44STomer Tayar offset += qed_grc_dump_registers(p_hwfn, 3777c965db44STomer Tayar p_ptt, 3778c965db44STomer Tayar dump_buf + offset, 3779c965db44STomer Tayar dump, block_enable, "block", "MCP"); 3780c965db44STomer Tayar 3781c965db44STomer Tayar /* Dump required non-MCP registers */ 3782c965db44STomer Tayar offset += qed_grc_dump_regs_hdr(dump_buf + offset, 3783d52c89f1SMichal Kalderon dump, 1, SPLIT_TYPE_NONE, 0, 3784d52c89f1SMichal Kalderon "block", "MCP"); 3785be086e7cSMintz, Yuval addr = BYTES_TO_DWORDS(MISC_REG_SHARED_MEM_ADDR); 3786c965db44STomer Tayar offset += qed_grc_dump_reg_entry(p_hwfn, 3787c965db44STomer Tayar p_ptt, 3788c965db44STomer Tayar dump_buf + offset, 3789c965db44STomer Tayar dump, 3790be086e7cSMintz, Yuval addr, 37917b6859fbSMintz, Yuval 1, 3792d52c89f1SMichal Kalderon false, SPLIT_TYPE_NONE, 0); 3793c965db44STomer Tayar 3794c965db44STomer Tayar /* Release MCP */ 3795c965db44STomer Tayar if (halted && qed_mcp_resume(p_hwfn, p_ptt)) 3796c965db44STomer Tayar DP_NOTICE(p_hwfn, "Failed to resume MCP after halt!\n"); 37977b6859fbSMintz, Yuval 3798c965db44STomer Tayar return offset; 3799c965db44STomer Tayar } 3800c965db44STomer Tayar 3801c965db44STomer Tayar /* Dumps the tbus indirect memory for all PHYs. */ 3802c965db44STomer Tayar static u32 qed_grc_dump_phy(struct qed_hwfn *p_hwfn, 3803c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *dump_buf, bool dump) 3804c965db44STomer Tayar { 3805c965db44STomer Tayar u32 offset = 0, tbus_lo_offset, tbus_hi_offset; 3806c965db44STomer Tayar char mem_name[32]; 3807c965db44STomer Tayar u8 phy_id; 3808c965db44STomer Tayar 3809c965db44STomer Tayar for (phy_id = 0; phy_id < ARRAY_SIZE(s_phy_defs); phy_id++) { 38107b6859fbSMintz, Yuval u32 addr_lo_addr, addr_hi_addr, data_lo_addr, data_hi_addr; 38117b6859fbSMintz, Yuval struct phy_defs *phy_defs; 38127b6859fbSMintz, Yuval u8 *bytes_buf; 3813c965db44STomer Tayar 38147b6859fbSMintz, Yuval phy_defs = &s_phy_defs[phy_id]; 38157b6859fbSMintz, Yuval addr_lo_addr = phy_defs->base_addr + 38167b6859fbSMintz, Yuval phy_defs->tbus_addr_lo_addr; 38177b6859fbSMintz, Yuval addr_hi_addr = phy_defs->base_addr + 38187b6859fbSMintz, Yuval phy_defs->tbus_addr_hi_addr; 38197b6859fbSMintz, Yuval data_lo_addr = phy_defs->base_addr + 38207b6859fbSMintz, Yuval phy_defs->tbus_data_lo_addr; 38217b6859fbSMintz, Yuval data_hi_addr = phy_defs->base_addr + 38227b6859fbSMintz, Yuval phy_defs->tbus_data_hi_addr; 38237b6859fbSMintz, Yuval 38247b6859fbSMintz, Yuval if (snprintf(mem_name, sizeof(mem_name), "tbus_%s", 38257b6859fbSMintz, Yuval phy_defs->phy_name) < 0) 3826c965db44STomer Tayar DP_NOTICE(p_hwfn, 3827c965db44STomer Tayar "Unexpected debug error: invalid PHY memory name\n"); 38287b6859fbSMintz, Yuval 3829c965db44STomer Tayar offset += qed_grc_dump_mem_hdr(p_hwfn, 3830c965db44STomer Tayar dump_buf + offset, 3831c965db44STomer Tayar dump, 3832c965db44STomer Tayar mem_name, 3833c965db44STomer Tayar 0, 3834c965db44STomer Tayar PHY_DUMP_SIZE_DWORDS, 3835c965db44STomer Tayar 16, true, mem_name, false, 0); 38367b6859fbSMintz, Yuval 38377b6859fbSMintz, Yuval if (!dump) { 38387b6859fbSMintz, Yuval offset += PHY_DUMP_SIZE_DWORDS; 38397b6859fbSMintz, Yuval continue; 38407b6859fbSMintz, Yuval } 3841c965db44STomer Tayar 3842da090917STomer Tayar bytes_buf = (u8 *)(dump_buf + offset); 3843c965db44STomer Tayar for (tbus_hi_offset = 0; 3844c965db44STomer Tayar tbus_hi_offset < (NUM_PHY_TBUS_ADDRESSES >> 8); 3845c965db44STomer Tayar tbus_hi_offset++) { 38467b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, addr_hi_addr, tbus_hi_offset); 3847c965db44STomer Tayar for (tbus_lo_offset = 0; tbus_lo_offset < 256; 3848c965db44STomer Tayar tbus_lo_offset++) { 3849c965db44STomer Tayar qed_wr(p_hwfn, 38507b6859fbSMintz, Yuval p_ptt, addr_lo_addr, tbus_lo_offset); 38517b6859fbSMintz, Yuval *(bytes_buf++) = (u8)qed_rd(p_hwfn, 3852c965db44STomer Tayar p_ptt, 3853c965db44STomer Tayar data_lo_addr); 38547b6859fbSMintz, Yuval *(bytes_buf++) = (u8)qed_rd(p_hwfn, 38557b6859fbSMintz, Yuval p_ptt, 3856c965db44STomer Tayar data_hi_addr); 3857c965db44STomer Tayar } 3858c965db44STomer Tayar } 3859c965db44STomer Tayar 3860c965db44STomer Tayar offset += PHY_DUMP_SIZE_DWORDS; 3861c965db44STomer Tayar } 3862c965db44STomer Tayar 3863c965db44STomer Tayar return offset; 3864c965db44STomer Tayar } 3865c965db44STomer Tayar 3866c965db44STomer Tayar static void qed_config_dbg_line(struct qed_hwfn *p_hwfn, 3867c965db44STomer Tayar struct qed_ptt *p_ptt, 3868c965db44STomer Tayar enum block_id block_id, 3869c965db44STomer Tayar u8 line_id, 38707b6859fbSMintz, Yuval u8 enable_mask, 38717b6859fbSMintz, Yuval u8 right_shift, 38727b6859fbSMintz, Yuval u8 force_valid_mask, u8 force_frame_mask) 3873c965db44STomer Tayar { 38747b6859fbSMintz, Yuval struct block_defs *block = s_block_defs[block_id]; 3875c965db44STomer Tayar 38767b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, block->dbg_select_addr, line_id); 38777b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, block->dbg_enable_addr, enable_mask); 38787b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, block->dbg_shift_addr, right_shift); 38797b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, block->dbg_force_valid_addr, force_valid_mask); 38807b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, block->dbg_force_frame_addr, force_frame_mask); 3881c965db44STomer Tayar } 3882c965db44STomer Tayar 3883c965db44STomer Tayar /* Dumps Static Debug data. Returns the dumped size in dwords. */ 3884c965db44STomer Tayar static u32 qed_grc_dump_static_debug(struct qed_hwfn *p_hwfn, 3885c965db44STomer Tayar struct qed_ptt *p_ptt, 3886c965db44STomer Tayar u32 *dump_buf, bool dump) 3887c965db44STomer Tayar { 3888c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 38897b6859fbSMintz, Yuval u32 block_id, line_id, offset = 0; 38907b6859fbSMintz, Yuval 3891da090917STomer Tayar /* Don't dump static debug if a debug bus recording is in progress */ 3892da090917STomer Tayar if (dump && qed_rd(p_hwfn, p_ptt, DBG_REG_DBG_BLOCK_ON)) 38937b6859fbSMintz, Yuval return 0; 3894c965db44STomer Tayar 3895c965db44STomer Tayar if (dump) { 3896c965db44STomer Tayar /* Disable all blocks debug output */ 3897c965db44STomer Tayar for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) { 38987b6859fbSMintz, Yuval struct block_defs *block = s_block_defs[block_id]; 3899c965db44STomer Tayar 3900da090917STomer Tayar if (block->dbg_client_id[dev_data->chip_id] != 3901da090917STomer Tayar MAX_DBG_BUS_CLIENTS) 39027b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, block->dbg_enable_addr, 39037b6859fbSMintz, Yuval 0); 3904c965db44STomer Tayar } 3905c965db44STomer Tayar 3906c965db44STomer Tayar qed_bus_reset_dbg_block(p_hwfn, p_ptt); 3907c965db44STomer Tayar qed_bus_set_framing_mode(p_hwfn, 3908c965db44STomer Tayar p_ptt, DBG_BUS_FRAME_MODE_8HW_0ST); 3909c965db44STomer Tayar qed_wr(p_hwfn, 3910c965db44STomer Tayar p_ptt, DBG_REG_DEBUG_TARGET, DBG_BUS_TARGET_ID_INT_BUF); 3911c965db44STomer Tayar qed_wr(p_hwfn, p_ptt, DBG_REG_FULL_MODE, 1); 3912c965db44STomer Tayar qed_bus_enable_dbg_block(p_hwfn, p_ptt, true); 3913c965db44STomer Tayar } 3914c965db44STomer Tayar 3915c965db44STomer Tayar /* Dump all static debug lines for each relevant block */ 3916c965db44STomer Tayar for (block_id = 0; block_id < MAX_BLOCK_ID; block_id++) { 39177b6859fbSMintz, Yuval struct block_defs *block = s_block_defs[block_id]; 39187b6859fbSMintz, Yuval struct dbg_bus_block *block_desc; 39197b6859fbSMintz, Yuval u32 block_dwords, addr, len; 39207b6859fbSMintz, Yuval u8 dbg_client_id; 3921c965db44STomer Tayar 3922da090917STomer Tayar if (block->dbg_client_id[dev_data->chip_id] == 3923da090917STomer Tayar MAX_DBG_BUS_CLIENTS) 3924c965db44STomer Tayar continue; 3925c965db44STomer Tayar 3926da090917STomer Tayar block_desc = get_dbg_bus_block_desc(p_hwfn, 39277b6859fbSMintz, Yuval (enum block_id)block_id); 39287b6859fbSMintz, Yuval block_dwords = NUM_DBG_LINES(block_desc) * 39297b6859fbSMintz, Yuval STATIC_DEBUG_LINE_DWORDS; 39307b6859fbSMintz, Yuval 3931c965db44STomer Tayar /* Dump static section params */ 3932c965db44STomer Tayar offset += qed_grc_dump_mem_hdr(p_hwfn, 3933c965db44STomer Tayar dump_buf + offset, 3934c965db44STomer Tayar dump, 39357b6859fbSMintz, Yuval block->name, 39367b6859fbSMintz, Yuval 0, 39377b6859fbSMintz, Yuval block_dwords, 39387b6859fbSMintz, Yuval 32, false, "STATIC", false, 0); 3939c965db44STomer Tayar 39407b6859fbSMintz, Yuval if (!dump) { 39417b6859fbSMintz, Yuval offset += block_dwords; 39427b6859fbSMintz, Yuval continue; 39437b6859fbSMintz, Yuval } 39447b6859fbSMintz, Yuval 39457b6859fbSMintz, Yuval /* If all lines are invalid - dump zeros */ 39467b6859fbSMintz, Yuval if (dev_data->block_in_reset[block_id]) { 39477b6859fbSMintz, Yuval memset(dump_buf + offset, 0, 39487b6859fbSMintz, Yuval DWORDS_TO_BYTES(block_dwords)); 39497b6859fbSMintz, Yuval offset += block_dwords; 39507b6859fbSMintz, Yuval continue; 39517b6859fbSMintz, Yuval } 3952c965db44STomer Tayar 3953c965db44STomer Tayar /* Enable block's client */ 39547b6859fbSMintz, Yuval dbg_client_id = block->dbg_client_id[dev_data->chip_id]; 39557b6859fbSMintz, Yuval qed_bus_enable_clients(p_hwfn, 39567b6859fbSMintz, Yuval p_ptt, 3957c965db44STomer Tayar BIT(dbg_client_id)); 3958c965db44STomer Tayar 39597b6859fbSMintz, Yuval addr = BYTES_TO_DWORDS(DBG_REG_CALENDAR_OUT_DATA); 39607b6859fbSMintz, Yuval len = STATIC_DEBUG_LINE_DWORDS; 39617b6859fbSMintz, Yuval for (line_id = 0; line_id < (u32)NUM_DBG_LINES(block_desc); 3962c965db44STomer Tayar line_id++) { 3963c965db44STomer Tayar /* Configure debug line ID */ 3964c965db44STomer Tayar qed_config_dbg_line(p_hwfn, 3965c965db44STomer Tayar p_ptt, 3966c965db44STomer Tayar (enum block_id)block_id, 39677b6859fbSMintz, Yuval (u8)line_id, 0xf, 0, 0, 0); 3968c965db44STomer Tayar 3969c965db44STomer Tayar /* Read debug line info */ 39707b6859fbSMintz, Yuval offset += qed_grc_dump_addr_range(p_hwfn, 3971be086e7cSMintz, Yuval p_ptt, 3972be086e7cSMintz, Yuval dump_buf + offset, 3973be086e7cSMintz, Yuval dump, 3974be086e7cSMintz, Yuval addr, 39757b6859fbSMintz, Yuval len, 3976d52c89f1SMichal Kalderon true, SPLIT_TYPE_NONE, 3977d52c89f1SMichal Kalderon 0); 3978c965db44STomer Tayar } 3979c965db44STomer Tayar 3980c965db44STomer Tayar /* Disable block's client and debug output */ 3981c965db44STomer Tayar qed_bus_enable_clients(p_hwfn, p_ptt, 0); 39827b6859fbSMintz, Yuval qed_wr(p_hwfn, p_ptt, block->dbg_enable_addr, 0); 3983c965db44STomer Tayar } 3984c965db44STomer Tayar 3985c965db44STomer Tayar if (dump) { 3986c965db44STomer Tayar qed_bus_enable_dbg_block(p_hwfn, p_ptt, false); 3987c965db44STomer Tayar qed_bus_enable_clients(p_hwfn, p_ptt, 0); 3988c965db44STomer Tayar } 3989c965db44STomer Tayar 3990c965db44STomer Tayar return offset; 3991c965db44STomer Tayar } 3992c965db44STomer Tayar 3993c965db44STomer Tayar /* Performs GRC Dump to the specified buffer. 3994c965db44STomer Tayar * Returns the dumped size in dwords. 3995c965db44STomer Tayar */ 3996c965db44STomer Tayar static enum dbg_status qed_grc_dump(struct qed_hwfn *p_hwfn, 3997c965db44STomer Tayar struct qed_ptt *p_ptt, 3998c965db44STomer Tayar u32 *dump_buf, 3999c965db44STomer Tayar bool dump, u32 *num_dumped_dwords) 4000c965db44STomer Tayar { 4001c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 4002c965db44STomer Tayar bool parities_masked = false; 4003c965db44STomer Tayar u32 offset = 0; 4004d52c89f1SMichal Kalderon u8 i; 4005c965db44STomer Tayar 4006c965db44STomer Tayar *num_dumped_dwords = 0; 4007d52c89f1SMichal Kalderon dev_data->num_regs_read = 0; 4008c965db44STomer Tayar 4009c965db44STomer Tayar /* Update reset state */ 4010d52c89f1SMichal Kalderon if (dump) 4011c965db44STomer Tayar qed_update_blocks_reset_state(p_hwfn, p_ptt); 4012c965db44STomer Tayar 4013c965db44STomer Tayar /* Dump global params */ 4014c965db44STomer Tayar offset += qed_dump_common_global_params(p_hwfn, 4015c965db44STomer Tayar p_ptt, 4016c965db44STomer Tayar dump_buf + offset, dump, 4); 4017c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 4018c965db44STomer Tayar dump, "dump-type", "grc-dump"); 4019c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 4020c965db44STomer Tayar dump, 4021c965db44STomer Tayar "num-lcids", 4022c965db44STomer Tayar qed_grc_get_param(p_hwfn, 4023c965db44STomer Tayar DBG_GRC_PARAM_NUM_LCIDS)); 4024c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 4025c965db44STomer Tayar dump, 4026c965db44STomer Tayar "num-ltids", 4027c965db44STomer Tayar qed_grc_get_param(p_hwfn, 4028c965db44STomer Tayar DBG_GRC_PARAM_NUM_LTIDS)); 4029c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 4030d52c89f1SMichal Kalderon dump, "num-ports", dev_data->num_ports); 4031c965db44STomer Tayar 4032c965db44STomer Tayar /* Dump reset registers (dumped before taking blocks out of reset ) */ 4033c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_REGS)) 4034c965db44STomer Tayar offset += qed_grc_dump_reset_regs(p_hwfn, 4035c965db44STomer Tayar p_ptt, 4036c965db44STomer Tayar dump_buf + offset, dump); 4037c965db44STomer Tayar 4038c965db44STomer Tayar /* Take all blocks out of reset (using reset registers) */ 4039c965db44STomer Tayar if (dump) { 4040c965db44STomer Tayar qed_grc_unreset_blocks(p_hwfn, p_ptt); 4041c965db44STomer Tayar qed_update_blocks_reset_state(p_hwfn, p_ptt); 4042c965db44STomer Tayar } 4043c965db44STomer Tayar 4044c965db44STomer Tayar /* Disable all parities using MFW command */ 40457b6859fbSMintz, Yuval if (dump && 40467b6859fbSMintz, Yuval !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_MCP)) { 4047c965db44STomer Tayar parities_masked = !qed_mcp_mask_parities(p_hwfn, p_ptt, 1); 4048c965db44STomer Tayar if (!parities_masked) { 4049be086e7cSMintz, Yuval DP_NOTICE(p_hwfn, 4050be086e7cSMintz, Yuval "Failed to mask parities using MFW\n"); 4051c965db44STomer Tayar if (qed_grc_get_param 4052c965db44STomer Tayar (p_hwfn, DBG_GRC_PARAM_PARITY_SAFE)) 4053c965db44STomer Tayar return DBG_STATUS_MCP_COULD_NOT_MASK_PRTY; 4054c965db44STomer Tayar } 4055c965db44STomer Tayar } 4056c965db44STomer Tayar 4057c965db44STomer Tayar /* Dump modified registers (dumped before modifying them) */ 4058c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_REGS)) 4059c965db44STomer Tayar offset += qed_grc_dump_modified_regs(p_hwfn, 4060c965db44STomer Tayar p_ptt, 4061c965db44STomer Tayar dump_buf + offset, dump); 4062c965db44STomer Tayar 4063c965db44STomer Tayar /* Stall storms */ 4064c965db44STomer Tayar if (dump && 4065c965db44STomer Tayar (qed_grc_is_included(p_hwfn, 4066c965db44STomer Tayar DBG_GRC_PARAM_DUMP_IOR) || 4067c965db44STomer Tayar qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_VFC))) 4068c965db44STomer Tayar qed_grc_stall_storms(p_hwfn, p_ptt, true); 4069c965db44STomer Tayar 4070c965db44STomer Tayar /* Dump all regs */ 4071c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_REGS)) { 4072c965db44STomer Tayar bool block_enable[MAX_BLOCK_ID]; 4073c965db44STomer Tayar 40747b6859fbSMintz, Yuval /* Dump all blocks except MCP */ 4075c965db44STomer Tayar for (i = 0; i < MAX_BLOCK_ID; i++) 4076c965db44STomer Tayar block_enable[i] = true; 4077c965db44STomer Tayar block_enable[BLOCK_MCP] = false; 4078c965db44STomer Tayar offset += qed_grc_dump_registers(p_hwfn, 4079c965db44STomer Tayar p_ptt, 4080c965db44STomer Tayar dump_buf + 4081c965db44STomer Tayar offset, 4082c965db44STomer Tayar dump, 4083c965db44STomer Tayar block_enable, NULL, NULL); 4084be086e7cSMintz, Yuval 4085be086e7cSMintz, Yuval /* Dump special registers */ 4086be086e7cSMintz, Yuval offset += qed_grc_dump_special_regs(p_hwfn, 4087be086e7cSMintz, Yuval p_ptt, 4088be086e7cSMintz, Yuval dump_buf + offset, dump); 4089c965db44STomer Tayar } 4090c965db44STomer Tayar 4091c965db44STomer Tayar /* Dump memories */ 4092c965db44STomer Tayar offset += qed_grc_dump_memories(p_hwfn, p_ptt, dump_buf + offset, dump); 4093c965db44STomer Tayar 4094c965db44STomer Tayar /* Dump MCP */ 4095c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_MCP)) 4096c965db44STomer Tayar offset += qed_grc_dump_mcp(p_hwfn, 4097c965db44STomer Tayar p_ptt, dump_buf + offset, dump); 4098c965db44STomer Tayar 4099c965db44STomer Tayar /* Dump context */ 4100c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_CM_CTX)) 4101c965db44STomer Tayar offset += qed_grc_dump_ctx(p_hwfn, 4102c965db44STomer Tayar p_ptt, dump_buf + offset, dump); 4103c965db44STomer Tayar 4104c965db44STomer Tayar /* Dump RSS memories */ 4105c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_RSS)) 4106c965db44STomer Tayar offset += qed_grc_dump_rss(p_hwfn, 4107c965db44STomer Tayar p_ptt, dump_buf + offset, dump); 4108c965db44STomer Tayar 4109c965db44STomer Tayar /* Dump Big RAM */ 4110c965db44STomer Tayar for (i = 0; i < NUM_BIG_RAM_TYPES; i++) 4111c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, s_big_ram_defs[i].grc_param)) 4112c965db44STomer Tayar offset += qed_grc_dump_big_ram(p_hwfn, 4113c965db44STomer Tayar p_ptt, 4114c965db44STomer Tayar dump_buf + offset, 4115c965db44STomer Tayar dump, i); 4116c965db44STomer Tayar 4117c965db44STomer Tayar /* Dump IORs */ 4118c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_IOR)) 4119c965db44STomer Tayar offset += qed_grc_dump_iors(p_hwfn, 4120c965db44STomer Tayar p_ptt, dump_buf + offset, dump); 4121c965db44STomer Tayar 4122c965db44STomer Tayar /* Dump VFC */ 4123c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, DBG_GRC_PARAM_DUMP_VFC)) 4124c965db44STomer Tayar offset += qed_grc_dump_vfc(p_hwfn, 4125c965db44STomer Tayar p_ptt, dump_buf + offset, dump); 4126c965db44STomer Tayar 4127c965db44STomer Tayar /* Dump PHY tbus */ 4128c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, 4129c965db44STomer Tayar DBG_GRC_PARAM_DUMP_PHY) && dev_data->chip_id == 4130c965db44STomer Tayar CHIP_K2 && dev_data->platform_id == PLATFORM_ASIC) 4131c965db44STomer Tayar offset += qed_grc_dump_phy(p_hwfn, 4132c965db44STomer Tayar p_ptt, dump_buf + offset, dump); 4133c965db44STomer Tayar 4134d52c89f1SMichal Kalderon /* Dump static debug data (only if not during debug bus recording) */ 4135c965db44STomer Tayar if (qed_grc_is_included(p_hwfn, 4136c965db44STomer Tayar DBG_GRC_PARAM_DUMP_STATIC) && 4137d52c89f1SMichal Kalderon (!dump || dev_data->bus.state == DBG_BUS_STATE_IDLE)) 4138c965db44STomer Tayar offset += qed_grc_dump_static_debug(p_hwfn, 4139c965db44STomer Tayar p_ptt, 4140c965db44STomer Tayar dump_buf + offset, dump); 4141c965db44STomer Tayar 4142c965db44STomer Tayar /* Dump last section */ 4143da090917STomer Tayar offset += qed_dump_last_section(dump_buf, offset, dump); 41447b6859fbSMintz, Yuval 4145c965db44STomer Tayar if (dump) { 4146c965db44STomer Tayar /* Unstall storms */ 4147c965db44STomer Tayar if (qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_UNSTALL)) 4148c965db44STomer Tayar qed_grc_stall_storms(p_hwfn, p_ptt, false); 4149c965db44STomer Tayar 4150c965db44STomer Tayar /* Clear parity status */ 4151c965db44STomer Tayar qed_grc_clear_all_prty(p_hwfn, p_ptt); 4152c965db44STomer Tayar 4153c965db44STomer Tayar /* Enable all parities using MFW command */ 4154c965db44STomer Tayar if (parities_masked) 4155c965db44STomer Tayar qed_mcp_mask_parities(p_hwfn, p_ptt, 0); 4156c965db44STomer Tayar } 4157c965db44STomer Tayar 4158c965db44STomer Tayar *num_dumped_dwords = offset; 4159c965db44STomer Tayar 4160c965db44STomer Tayar return DBG_STATUS_OK; 4161c965db44STomer Tayar } 4162c965db44STomer Tayar 4163c965db44STomer Tayar /* Writes the specified failing Idle Check rule to the specified buffer. 4164c965db44STomer Tayar * Returns the dumped size in dwords. 4165c965db44STomer Tayar */ 4166c965db44STomer Tayar static u32 qed_idle_chk_dump_failure(struct qed_hwfn *p_hwfn, 4167c965db44STomer Tayar struct qed_ptt *p_ptt, 4168c965db44STomer Tayar u32 * 4169c965db44STomer Tayar dump_buf, 4170c965db44STomer Tayar bool dump, 4171c965db44STomer Tayar u16 rule_id, 4172c965db44STomer Tayar const struct dbg_idle_chk_rule *rule, 4173c965db44STomer Tayar u16 fail_entry_id, u32 *cond_reg_values) 4174c965db44STomer Tayar { 4175c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 41767b6859fbSMintz, Yuval const struct dbg_idle_chk_cond_reg *cond_regs; 41777b6859fbSMintz, Yuval const struct dbg_idle_chk_info_reg *info_regs; 41787b6859fbSMintz, Yuval u32 i, next_reg_offset = 0, offset = 0; 41797b6859fbSMintz, Yuval struct dbg_idle_chk_result_hdr *hdr; 41807b6859fbSMintz, Yuval const union dbg_idle_chk_reg *regs; 4181c965db44STomer Tayar u8 reg_id; 4182c965db44STomer Tayar 41837b6859fbSMintz, Yuval hdr = (struct dbg_idle_chk_result_hdr *)dump_buf; 41847b6859fbSMintz, Yuval regs = &((const union dbg_idle_chk_reg *) 41857b6859fbSMintz, Yuval s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_REGS].ptr)[rule->reg_offset]; 41867b6859fbSMintz, Yuval cond_regs = ®s[0].cond_reg; 41877b6859fbSMintz, Yuval info_regs = ®s[rule->num_cond_regs].info_reg; 41887b6859fbSMintz, Yuval 4189c965db44STomer Tayar /* Dump rule data */ 4190c965db44STomer Tayar if (dump) { 4191c965db44STomer Tayar memset(hdr, 0, sizeof(*hdr)); 4192c965db44STomer Tayar hdr->rule_id = rule_id; 4193c965db44STomer Tayar hdr->mem_entry_id = fail_entry_id; 4194c965db44STomer Tayar hdr->severity = rule->severity; 4195c965db44STomer Tayar hdr->num_dumped_cond_regs = rule->num_cond_regs; 4196c965db44STomer Tayar } 4197c965db44STomer Tayar 4198c965db44STomer Tayar offset += IDLE_CHK_RESULT_HDR_DWORDS; 4199c965db44STomer Tayar 4200c965db44STomer Tayar /* Dump condition register values */ 4201c965db44STomer Tayar for (reg_id = 0; reg_id < rule->num_cond_regs; reg_id++) { 4202c965db44STomer Tayar const struct dbg_idle_chk_cond_reg *reg = &cond_regs[reg_id]; 42037b6859fbSMintz, Yuval struct dbg_idle_chk_result_reg_hdr *reg_hdr; 42047b6859fbSMintz, Yuval 42057b6859fbSMintz, Yuval reg_hdr = (struct dbg_idle_chk_result_reg_hdr *) 42067b6859fbSMintz, Yuval (dump_buf + offset); 4207c965db44STomer Tayar 4208c965db44STomer Tayar /* Write register header */ 42097b6859fbSMintz, Yuval if (!dump) { 42107b6859fbSMintz, Yuval offset += IDLE_CHK_RESULT_REG_HDR_DWORDS + 42117b6859fbSMintz, Yuval reg->entry_size; 42127b6859fbSMintz, Yuval continue; 42137b6859fbSMintz, Yuval } 42147b6859fbSMintz, Yuval 4215c965db44STomer Tayar offset += IDLE_CHK_RESULT_REG_HDR_DWORDS; 42167b6859fbSMintz, Yuval memset(reg_hdr, 0, sizeof(*reg_hdr)); 4217c965db44STomer Tayar reg_hdr->start_entry = reg->start_entry; 4218c965db44STomer Tayar reg_hdr->size = reg->entry_size; 4219c965db44STomer Tayar SET_FIELD(reg_hdr->data, 4220c965db44STomer Tayar DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM, 42217b6859fbSMintz, Yuval reg->num_entries > 1 || reg->start_entry > 0 ? 1 : 0); 4222c965db44STomer Tayar SET_FIELD(reg_hdr->data, 4223c965db44STomer Tayar DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID, reg_id); 4224c965db44STomer Tayar 4225c965db44STomer Tayar /* Write register values */ 42267b6859fbSMintz, Yuval for (i = 0; i < reg_hdr->size; i++, next_reg_offset++, offset++) 42277b6859fbSMintz, Yuval dump_buf[offset] = cond_reg_values[next_reg_offset]; 4228c965db44STomer Tayar } 4229c965db44STomer Tayar 4230c965db44STomer Tayar /* Dump info register values */ 4231c965db44STomer Tayar for (reg_id = 0; reg_id < rule->num_info_regs; reg_id++) { 4232c965db44STomer Tayar const struct dbg_idle_chk_info_reg *reg = &info_regs[reg_id]; 4233c965db44STomer Tayar u32 block_id; 4234c965db44STomer Tayar 42357b6859fbSMintz, Yuval /* Check if register's block is in reset */ 4236c965db44STomer Tayar if (!dump) { 4237c965db44STomer Tayar offset += IDLE_CHK_RESULT_REG_HDR_DWORDS + reg->size; 4238c965db44STomer Tayar continue; 4239c965db44STomer Tayar } 4240c965db44STomer Tayar 4241c965db44STomer Tayar block_id = GET_FIELD(reg->data, DBG_IDLE_CHK_INFO_REG_BLOCK_ID); 4242c965db44STomer Tayar if (block_id >= MAX_BLOCK_ID) { 4243c965db44STomer Tayar DP_NOTICE(p_hwfn, "Invalid block_id\n"); 4244c965db44STomer Tayar return 0; 4245c965db44STomer Tayar } 4246c965db44STomer Tayar 4247c965db44STomer Tayar if (!dev_data->block_in_reset[block_id]) { 42487b6859fbSMintz, Yuval struct dbg_idle_chk_result_reg_hdr *reg_hdr; 42497b6859fbSMintz, Yuval bool wide_bus, eval_mode, mode_match = true; 42507b6859fbSMintz, Yuval u16 modes_buf_offset; 42517b6859fbSMintz, Yuval u32 addr; 42527b6859fbSMintz, Yuval 42537b6859fbSMintz, Yuval reg_hdr = (struct dbg_idle_chk_result_reg_hdr *) 42547b6859fbSMintz, Yuval (dump_buf + offset); 4255c965db44STomer Tayar 4256c965db44STomer Tayar /* Check mode */ 42577b6859fbSMintz, Yuval eval_mode = GET_FIELD(reg->mode.data, 42587b6859fbSMintz, Yuval DBG_MODE_HDR_EVAL_MODE) > 0; 4259c965db44STomer Tayar if (eval_mode) { 42607b6859fbSMintz, Yuval modes_buf_offset = 4261c965db44STomer Tayar GET_FIELD(reg->mode.data, 4262c965db44STomer Tayar DBG_MODE_HDR_MODES_BUF_OFFSET); 4263c965db44STomer Tayar mode_match = 4264c965db44STomer Tayar qed_is_mode_match(p_hwfn, 4265c965db44STomer Tayar &modes_buf_offset); 4266c965db44STomer Tayar } 4267c965db44STomer Tayar 42687b6859fbSMintz, Yuval if (!mode_match) 42697b6859fbSMintz, Yuval continue; 42707b6859fbSMintz, Yuval 42717b6859fbSMintz, Yuval addr = GET_FIELD(reg->data, 4272be086e7cSMintz, Yuval DBG_IDLE_CHK_INFO_REG_ADDRESS); 42737b6859fbSMintz, Yuval wide_bus = GET_FIELD(reg->data, 42747b6859fbSMintz, Yuval DBG_IDLE_CHK_INFO_REG_WIDE_BUS); 4275c965db44STomer Tayar 4276c965db44STomer Tayar /* Write register header */ 4277c965db44STomer Tayar offset += IDLE_CHK_RESULT_REG_HDR_DWORDS; 4278c965db44STomer Tayar hdr->num_dumped_info_regs++; 4279c965db44STomer Tayar memset(reg_hdr, 0, sizeof(*reg_hdr)); 4280c965db44STomer Tayar reg_hdr->size = reg->size; 4281c965db44STomer Tayar SET_FIELD(reg_hdr->data, 4282c965db44STomer Tayar DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID, 4283c965db44STomer Tayar rule->num_cond_regs + reg_id); 4284c965db44STomer Tayar 4285c965db44STomer Tayar /* Write register values */ 42867b6859fbSMintz, Yuval offset += qed_grc_dump_addr_range(p_hwfn, 4287be086e7cSMintz, Yuval p_ptt, 4288be086e7cSMintz, Yuval dump_buf + offset, 4289be086e7cSMintz, Yuval dump, 4290be086e7cSMintz, Yuval addr, 4291d52c89f1SMichal Kalderon reg->size, wide_bus, 4292d52c89f1SMichal Kalderon SPLIT_TYPE_NONE, 0); 4293c965db44STomer Tayar } 4294c965db44STomer Tayar } 4295c965db44STomer Tayar 4296c965db44STomer Tayar return offset; 4297c965db44STomer Tayar } 4298c965db44STomer Tayar 4299c965db44STomer Tayar /* Dumps idle check rule entries. Returns the dumped size in dwords. */ 4300c965db44STomer Tayar static u32 4301c965db44STomer Tayar qed_idle_chk_dump_rule_entries(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, 4302c965db44STomer Tayar u32 *dump_buf, bool dump, 4303c965db44STomer Tayar const struct dbg_idle_chk_rule *input_rules, 4304c965db44STomer Tayar u32 num_input_rules, u32 *num_failing_rules) 4305c965db44STomer Tayar { 4306c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 4307c965db44STomer Tayar u32 cond_reg_values[IDLE_CHK_MAX_ENTRIES_SIZE]; 4308be086e7cSMintz, Yuval u32 i, offset = 0; 4309c965db44STomer Tayar u16 entry_id; 4310c965db44STomer Tayar u8 reg_id; 4311c965db44STomer Tayar 4312c965db44STomer Tayar *num_failing_rules = 0; 43137b6859fbSMintz, Yuval 4314c965db44STomer Tayar for (i = 0; i < num_input_rules; i++) { 4315c965db44STomer Tayar const struct dbg_idle_chk_cond_reg *cond_regs; 4316c965db44STomer Tayar const struct dbg_idle_chk_rule *rule; 4317c965db44STomer Tayar const union dbg_idle_chk_reg *regs; 4318c965db44STomer Tayar u16 num_reg_entries = 1; 4319c965db44STomer Tayar bool check_rule = true; 4320c965db44STomer Tayar const u32 *imm_values; 4321c965db44STomer Tayar 4322c965db44STomer Tayar rule = &input_rules[i]; 4323c965db44STomer Tayar regs = &((const union dbg_idle_chk_reg *) 4324c965db44STomer Tayar s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_REGS].ptr) 4325c965db44STomer Tayar [rule->reg_offset]; 4326c965db44STomer Tayar cond_regs = ®s[0].cond_reg; 4327c965db44STomer Tayar imm_values = &s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_IMMS].ptr 4328c965db44STomer Tayar [rule->imm_offset]; 4329c965db44STomer Tayar 4330c965db44STomer Tayar /* Check if all condition register blocks are out of reset, and 4331c965db44STomer Tayar * find maximal number of entries (all condition registers that 4332c965db44STomer Tayar * are memories must have the same size, which is > 1). 4333c965db44STomer Tayar */ 4334c965db44STomer Tayar for (reg_id = 0; reg_id < rule->num_cond_regs && check_rule; 4335c965db44STomer Tayar reg_id++) { 43367b6859fbSMintz, Yuval u32 block_id = 43377b6859fbSMintz, Yuval GET_FIELD(cond_regs[reg_id].data, 4338c965db44STomer Tayar DBG_IDLE_CHK_COND_REG_BLOCK_ID); 4339c965db44STomer Tayar 4340c965db44STomer Tayar if (block_id >= MAX_BLOCK_ID) { 4341c965db44STomer Tayar DP_NOTICE(p_hwfn, "Invalid block_id\n"); 4342c965db44STomer Tayar return 0; 4343c965db44STomer Tayar } 4344c965db44STomer Tayar 4345c965db44STomer Tayar check_rule = !dev_data->block_in_reset[block_id]; 4346c965db44STomer Tayar if (cond_regs[reg_id].num_entries > num_reg_entries) 4347c965db44STomer Tayar num_reg_entries = cond_regs[reg_id].num_entries; 4348c965db44STomer Tayar } 4349c965db44STomer Tayar 4350c965db44STomer Tayar if (!check_rule && dump) 4351c965db44STomer Tayar continue; 4352c965db44STomer Tayar 4353be086e7cSMintz, Yuval if (!dump) { 4354da090917STomer Tayar u32 entry_dump_size = 4355da090917STomer Tayar qed_idle_chk_dump_failure(p_hwfn, 4356be086e7cSMintz, Yuval p_ptt, 4357be086e7cSMintz, Yuval dump_buf + offset, 4358be086e7cSMintz, Yuval false, 4359be086e7cSMintz, Yuval rule->rule_id, 4360be086e7cSMintz, Yuval rule, 4361da090917STomer Tayar 0, 4362be086e7cSMintz, Yuval NULL); 4363da090917STomer Tayar 4364da090917STomer Tayar offset += num_reg_entries * entry_dump_size; 4365da090917STomer Tayar (*num_failing_rules) += num_reg_entries; 4366da090917STomer Tayar continue; 4367be086e7cSMintz, Yuval } 4368be086e7cSMintz, Yuval 4369da090917STomer Tayar /* Go over all register entries (number of entries is the same 4370da090917STomer Tayar * for all condition registers). 4371da090917STomer Tayar */ 4372da090917STomer Tayar for (entry_id = 0; entry_id < num_reg_entries; entry_id++) { 4373da090917STomer Tayar u32 next_reg_offset = 0; 4374da090917STomer Tayar 4375c965db44STomer Tayar /* Read current entry of all condition registers */ 4376be086e7cSMintz, Yuval for (reg_id = 0; reg_id < rule->num_cond_regs; 4377c965db44STomer Tayar reg_id++) { 4378be086e7cSMintz, Yuval const struct dbg_idle_chk_cond_reg *reg = 4379be086e7cSMintz, Yuval &cond_regs[reg_id]; 43807b6859fbSMintz, Yuval u32 padded_entry_size, addr; 43817b6859fbSMintz, Yuval bool wide_bus; 4382c965db44STomer Tayar 4383be086e7cSMintz, Yuval /* Find GRC address (if it's a memory, the 4384be086e7cSMintz, Yuval * address of the specific entry is calculated). 4385c965db44STomer Tayar */ 43867b6859fbSMintz, Yuval addr = GET_FIELD(reg->data, 4387be086e7cSMintz, Yuval DBG_IDLE_CHK_COND_REG_ADDRESS); 43887b6859fbSMintz, Yuval wide_bus = 43897b6859fbSMintz, Yuval GET_FIELD(reg->data, 43907b6859fbSMintz, Yuval DBG_IDLE_CHK_COND_REG_WIDE_BUS); 4391c965db44STomer Tayar if (reg->num_entries > 1 || 4392c965db44STomer Tayar reg->start_entry > 0) { 43937b6859fbSMintz, Yuval padded_entry_size = 4394c965db44STomer Tayar reg->entry_size > 1 ? 4395da090917STomer Tayar roundup_pow_of_two(reg->entry_size) : 4396da090917STomer Tayar 1; 4397be086e7cSMintz, Yuval addr += (reg->start_entry + entry_id) * 4398be086e7cSMintz, Yuval padded_entry_size; 4399c965db44STomer Tayar } 4400c965db44STomer Tayar 4401c965db44STomer Tayar /* Read registers */ 4402c965db44STomer Tayar if (next_reg_offset + reg->entry_size >= 4403c965db44STomer Tayar IDLE_CHK_MAX_ENTRIES_SIZE) { 4404c965db44STomer Tayar DP_NOTICE(p_hwfn, 4405c965db44STomer Tayar "idle check registers entry is too large\n"); 4406c965db44STomer Tayar return 0; 4407c965db44STomer Tayar } 4408c965db44STomer Tayar 4409be086e7cSMintz, Yuval next_reg_offset += 44107b6859fbSMintz, Yuval qed_grc_dump_addr_range(p_hwfn, p_ptt, 4411be086e7cSMintz, Yuval cond_reg_values + 4412be086e7cSMintz, Yuval next_reg_offset, 4413be086e7cSMintz, Yuval dump, addr, 44147b6859fbSMintz, Yuval reg->entry_size, 4415d52c89f1SMichal Kalderon wide_bus, 4416d52c89f1SMichal Kalderon SPLIT_TYPE_NONE, 0); 4417c965db44STomer Tayar } 4418c965db44STomer Tayar 44197b6859fbSMintz, Yuval /* Call rule condition function. 44207b6859fbSMintz, Yuval * If returns true, it's a failure. 4421c965db44STomer Tayar */ 4422c965db44STomer Tayar if ((*cond_arr[rule->cond_id]) (cond_reg_values, 4423be086e7cSMintz, Yuval imm_values)) { 44247b6859fbSMintz, Yuval offset += qed_idle_chk_dump_failure(p_hwfn, 4425c965db44STomer Tayar p_ptt, 4426c965db44STomer Tayar dump_buf + offset, 4427c965db44STomer Tayar dump, 4428c965db44STomer Tayar rule->rule_id, 4429c965db44STomer Tayar rule, 4430c965db44STomer Tayar entry_id, 4431c965db44STomer Tayar cond_reg_values); 4432c965db44STomer Tayar (*num_failing_rules)++; 4433c965db44STomer Tayar } 4434c965db44STomer Tayar } 4435c965db44STomer Tayar } 4436c965db44STomer Tayar 4437c965db44STomer Tayar return offset; 4438c965db44STomer Tayar } 4439c965db44STomer Tayar 4440c965db44STomer Tayar /* Performs Idle Check Dump to the specified buffer. 4441c965db44STomer Tayar * Returns the dumped size in dwords. 4442c965db44STomer Tayar */ 4443c965db44STomer Tayar static u32 qed_idle_chk_dump(struct qed_hwfn *p_hwfn, 4444c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *dump_buf, bool dump) 4445c965db44STomer Tayar { 44467b6859fbSMintz, Yuval u32 num_failing_rules_offset, offset = 0, input_offset = 0; 44477b6859fbSMintz, Yuval u32 num_failing_rules = 0; 4448c965db44STomer Tayar 4449c965db44STomer Tayar /* Dump global params */ 4450c965db44STomer Tayar offset += qed_dump_common_global_params(p_hwfn, 4451c965db44STomer Tayar p_ptt, 4452c965db44STomer Tayar dump_buf + offset, dump, 1); 4453c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 4454c965db44STomer Tayar dump, "dump-type", "idle-chk"); 4455c965db44STomer Tayar 4456c965db44STomer Tayar /* Dump idle check section header with a single parameter */ 4457c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, dump, "idle_chk", 1); 4458c965db44STomer Tayar num_failing_rules_offset = offset; 4459c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, dump, "num_rules", 0); 44607b6859fbSMintz, Yuval 4461c965db44STomer Tayar while (input_offset < 4462c965db44STomer Tayar s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES].size_in_dwords) { 4463c965db44STomer Tayar const struct dbg_idle_chk_cond_hdr *cond_hdr = 4464c965db44STomer Tayar (const struct dbg_idle_chk_cond_hdr *) 4465c965db44STomer Tayar &s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES].ptr 4466c965db44STomer Tayar [input_offset++]; 44677b6859fbSMintz, Yuval bool eval_mode, mode_match = true; 44687b6859fbSMintz, Yuval u32 curr_failing_rules; 44697b6859fbSMintz, Yuval u16 modes_buf_offset; 4470c965db44STomer Tayar 4471c965db44STomer Tayar /* Check mode */ 44727b6859fbSMintz, Yuval eval_mode = GET_FIELD(cond_hdr->mode.data, 44737b6859fbSMintz, Yuval DBG_MODE_HDR_EVAL_MODE) > 0; 4474c965db44STomer Tayar if (eval_mode) { 44757b6859fbSMintz, Yuval modes_buf_offset = 4476c965db44STomer Tayar GET_FIELD(cond_hdr->mode.data, 4477c965db44STomer Tayar DBG_MODE_HDR_MODES_BUF_OFFSET); 4478c965db44STomer Tayar mode_match = qed_is_mode_match(p_hwfn, 4479c965db44STomer Tayar &modes_buf_offset); 4480c965db44STomer Tayar } 4481c965db44STomer Tayar 4482c965db44STomer Tayar if (mode_match) { 4483c965db44STomer Tayar offset += 4484c965db44STomer Tayar qed_idle_chk_dump_rule_entries(p_hwfn, 4485c965db44STomer Tayar p_ptt, 4486c965db44STomer Tayar dump_buf + offset, 4487c965db44STomer Tayar dump, 4488c965db44STomer Tayar (const struct dbg_idle_chk_rule *) 4489c965db44STomer Tayar &s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES]. 4490c965db44STomer Tayar ptr[input_offset], 4491c965db44STomer Tayar cond_hdr->data_size / IDLE_CHK_RULE_SIZE_DWORDS, 4492c965db44STomer Tayar &curr_failing_rules); 4493c965db44STomer Tayar num_failing_rules += curr_failing_rules; 4494c965db44STomer Tayar } 4495c965db44STomer Tayar 4496c965db44STomer Tayar input_offset += cond_hdr->data_size; 4497c965db44STomer Tayar } 4498c965db44STomer Tayar 4499c965db44STomer Tayar /* Overwrite num_rules parameter */ 4500c965db44STomer Tayar if (dump) 4501c965db44STomer Tayar qed_dump_num_param(dump_buf + num_failing_rules_offset, 4502c965db44STomer Tayar dump, "num_rules", num_failing_rules); 4503c965db44STomer Tayar 45047b6859fbSMintz, Yuval /* Dump last section */ 4505da090917STomer Tayar offset += qed_dump_last_section(dump_buf, offset, dump); 45067b6859fbSMintz, Yuval 4507c965db44STomer Tayar return offset; 4508c965db44STomer Tayar } 4509c965db44STomer Tayar 45107b6859fbSMintz, Yuval /* Finds the meta data image in NVRAM */ 4511c965db44STomer Tayar static enum dbg_status qed_find_nvram_image(struct qed_hwfn *p_hwfn, 4512c965db44STomer Tayar struct qed_ptt *p_ptt, 4513c965db44STomer Tayar u32 image_type, 4514c965db44STomer Tayar u32 *nvram_offset_bytes, 4515c965db44STomer Tayar u32 *nvram_size_bytes) 4516c965db44STomer Tayar { 4517c965db44STomer Tayar u32 ret_mcp_resp, ret_mcp_param, ret_txn_size; 4518c965db44STomer Tayar struct mcp_file_att file_att; 45197b6859fbSMintz, Yuval int nvm_result; 4520c965db44STomer Tayar 4521c965db44STomer Tayar /* Call NVRAM get file command */ 45227b6859fbSMintz, Yuval nvm_result = qed_mcp_nvm_rd_cmd(p_hwfn, 4523be086e7cSMintz, Yuval p_ptt, 4524be086e7cSMintz, Yuval DRV_MSG_CODE_NVM_GET_FILE_ATT, 4525be086e7cSMintz, Yuval image_type, 4526be086e7cSMintz, Yuval &ret_mcp_resp, 4527be086e7cSMintz, Yuval &ret_mcp_param, 45287b6859fbSMintz, Yuval &ret_txn_size, (u32 *)&file_att); 4529c965db44STomer Tayar 4530c965db44STomer Tayar /* Check response */ 4531be086e7cSMintz, Yuval if (nvm_result || 4532be086e7cSMintz, Yuval (ret_mcp_resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_NVM_OK) 4533c965db44STomer Tayar return DBG_STATUS_NVRAM_GET_IMAGE_FAILED; 4534c965db44STomer Tayar 4535c965db44STomer Tayar /* Update return values */ 4536c965db44STomer Tayar *nvram_offset_bytes = file_att.nvm_start_addr; 4537c965db44STomer Tayar *nvram_size_bytes = file_att.len; 45387b6859fbSMintz, Yuval 4539c965db44STomer Tayar DP_VERBOSE(p_hwfn, 4540c965db44STomer Tayar QED_MSG_DEBUG, 4541c965db44STomer Tayar "find_nvram_image: found NVRAM image of type %d in NVRAM offset %d bytes with size %d bytes\n", 4542c965db44STomer Tayar image_type, *nvram_offset_bytes, *nvram_size_bytes); 4543c965db44STomer Tayar 4544c965db44STomer Tayar /* Check alignment */ 4545c965db44STomer Tayar if (*nvram_size_bytes & 0x3) 4546c965db44STomer Tayar return DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE; 45477b6859fbSMintz, Yuval 4548c965db44STomer Tayar return DBG_STATUS_OK; 4549c965db44STomer Tayar } 4550c965db44STomer Tayar 45517b6859fbSMintz, Yuval /* Reads data from NVRAM */ 4552c965db44STomer Tayar static enum dbg_status qed_nvram_read(struct qed_hwfn *p_hwfn, 4553c965db44STomer Tayar struct qed_ptt *p_ptt, 4554c965db44STomer Tayar u32 nvram_offset_bytes, 4555c965db44STomer Tayar u32 nvram_size_bytes, u32 *ret_buf) 4556c965db44STomer Tayar { 45577b6859fbSMintz, Yuval u32 ret_mcp_resp, ret_mcp_param, ret_read_size, bytes_to_copy; 4558c965db44STomer Tayar s32 bytes_left = nvram_size_bytes; 45597b6859fbSMintz, Yuval u32 read_offset = 0; 4560c965db44STomer Tayar 4561c965db44STomer Tayar DP_VERBOSE(p_hwfn, 4562c965db44STomer Tayar QED_MSG_DEBUG, 4563c965db44STomer Tayar "nvram_read: reading image of size %d bytes from NVRAM\n", 4564c965db44STomer Tayar nvram_size_bytes); 45657b6859fbSMintz, Yuval 4566c965db44STomer Tayar do { 4567c965db44STomer Tayar bytes_to_copy = 4568c965db44STomer Tayar (bytes_left > 4569c965db44STomer Tayar MCP_DRV_NVM_BUF_LEN) ? MCP_DRV_NVM_BUF_LEN : bytes_left; 4570c965db44STomer Tayar 4571c965db44STomer Tayar /* Call NVRAM read command */ 4572c965db44STomer Tayar if (qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt, 4573c965db44STomer Tayar DRV_MSG_CODE_NVM_READ_NVRAM, 4574c965db44STomer Tayar (nvram_offset_bytes + 4575c965db44STomer Tayar read_offset) | 4576c965db44STomer Tayar (bytes_to_copy << 4577da090917STomer Tayar DRV_MB_PARAM_NVM_LEN_OFFSET), 4578c965db44STomer Tayar &ret_mcp_resp, &ret_mcp_param, 4579c965db44STomer Tayar &ret_read_size, 45807b6859fbSMintz, Yuval (u32 *)((u8 *)ret_buf + read_offset))) 4581c965db44STomer Tayar return DBG_STATUS_NVRAM_READ_FAILED; 4582c965db44STomer Tayar 4583c965db44STomer Tayar /* Check response */ 4584c965db44STomer Tayar if ((ret_mcp_resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_NVM_OK) 4585c965db44STomer Tayar return DBG_STATUS_NVRAM_READ_FAILED; 4586c965db44STomer Tayar 4587c965db44STomer Tayar /* Update read offset */ 4588c965db44STomer Tayar read_offset += ret_read_size; 4589c965db44STomer Tayar bytes_left -= ret_read_size; 4590c965db44STomer Tayar } while (bytes_left > 0); 4591c965db44STomer Tayar 4592c965db44STomer Tayar return DBG_STATUS_OK; 4593c965db44STomer Tayar } 4594c965db44STomer Tayar 4595c965db44STomer Tayar /* Get info on the MCP Trace data in the scratchpad: 45967b6859fbSMintz, Yuval * - trace_data_grc_addr (OUT): trace data GRC address in bytes 45977b6859fbSMintz, Yuval * - trace_data_size (OUT): trace data size in bytes (without the header) 4598c965db44STomer Tayar */ 4599c965db44STomer Tayar static enum dbg_status qed_mcp_trace_get_data_info(struct qed_hwfn *p_hwfn, 4600c965db44STomer Tayar struct qed_ptt *p_ptt, 4601c965db44STomer Tayar u32 *trace_data_grc_addr, 46027b6859fbSMintz, Yuval u32 *trace_data_size) 4603c965db44STomer Tayar { 46047b6859fbSMintz, Yuval u32 spad_trace_offsize, signature; 4605c965db44STomer Tayar 46067b6859fbSMintz, Yuval /* Read trace section offsize structure from MCP scratchpad */ 46077b6859fbSMintz, Yuval spad_trace_offsize = qed_rd(p_hwfn, p_ptt, MCP_SPAD_TRACE_OFFSIZE_ADDR); 46087b6859fbSMintz, Yuval 46097b6859fbSMintz, Yuval /* Extract trace section address from offsize (in scratchpad) */ 4610c965db44STomer Tayar *trace_data_grc_addr = 4611c965db44STomer Tayar MCP_REG_SCRATCH + SECTION_OFFSET(spad_trace_offsize); 4612c965db44STomer Tayar 4613c965db44STomer Tayar /* Read signature from MCP trace section */ 4614c965db44STomer Tayar signature = qed_rd(p_hwfn, p_ptt, 4615c965db44STomer Tayar *trace_data_grc_addr + 4616c965db44STomer Tayar offsetof(struct mcp_trace, signature)); 46177b6859fbSMintz, Yuval 4618c965db44STomer Tayar if (signature != MFW_TRACE_SIGNATURE) 4619c965db44STomer Tayar return DBG_STATUS_INVALID_TRACE_SIGNATURE; 4620c965db44STomer Tayar 4621c965db44STomer Tayar /* Read trace size from MCP trace section */ 46227b6859fbSMintz, Yuval *trace_data_size = qed_rd(p_hwfn, 4623c965db44STomer Tayar p_ptt, 4624c965db44STomer Tayar *trace_data_grc_addr + 4625c965db44STomer Tayar offsetof(struct mcp_trace, size)); 46267b6859fbSMintz, Yuval 4627c965db44STomer Tayar return DBG_STATUS_OK; 4628c965db44STomer Tayar } 4629c965db44STomer Tayar 46307b6859fbSMintz, Yuval /* Reads MCP trace meta data image from NVRAM 46317b6859fbSMintz, Yuval * - running_bundle_id (OUT): running bundle ID (invalid when loaded from file) 46327b6859fbSMintz, Yuval * - trace_meta_offset (OUT): trace meta offset in NVRAM in bytes (invalid when 46337b6859fbSMintz, Yuval * loaded from file). 46347b6859fbSMintz, Yuval * - trace_meta_size (OUT): size in bytes of the trace meta data. 4635c965db44STomer Tayar */ 4636c965db44STomer Tayar static enum dbg_status qed_mcp_trace_get_meta_info(struct qed_hwfn *p_hwfn, 4637c965db44STomer Tayar struct qed_ptt *p_ptt, 4638c965db44STomer Tayar u32 trace_data_size_bytes, 4639c965db44STomer Tayar u32 *running_bundle_id, 46407b6859fbSMintz, Yuval u32 *trace_meta_offset, 46417b6859fbSMintz, Yuval u32 *trace_meta_size) 4642c965db44STomer Tayar { 46437b6859fbSMintz, Yuval u32 spad_trace_offsize, nvram_image_type, running_mfw_addr; 46447b6859fbSMintz, Yuval 4645c965db44STomer Tayar /* Read MCP trace section offsize structure from MCP scratchpad */ 46467b6859fbSMintz, Yuval spad_trace_offsize = qed_rd(p_hwfn, p_ptt, MCP_SPAD_TRACE_OFFSIZE_ADDR); 4647c965db44STomer Tayar 4648c965db44STomer Tayar /* Find running bundle ID */ 46497b6859fbSMintz, Yuval running_mfw_addr = 4650c965db44STomer Tayar MCP_REG_SCRATCH + SECTION_OFFSET(spad_trace_offsize) + 4651c965db44STomer Tayar QED_SECTION_SIZE(spad_trace_offsize) + trace_data_size_bytes; 4652c965db44STomer Tayar *running_bundle_id = qed_rd(p_hwfn, p_ptt, running_mfw_addr); 4653c965db44STomer Tayar if (*running_bundle_id > 1) 4654c965db44STomer Tayar return DBG_STATUS_INVALID_NVRAM_BUNDLE; 4655c965db44STomer Tayar 4656c965db44STomer Tayar /* Find image in NVRAM */ 4657c965db44STomer Tayar nvram_image_type = 4658c965db44STomer Tayar (*running_bundle_id == 4659c965db44STomer Tayar DIR_ID_1) ? NVM_TYPE_MFW_TRACE1 : NVM_TYPE_MFW_TRACE2; 4660be086e7cSMintz, Yuval return qed_find_nvram_image(p_hwfn, 4661c965db44STomer Tayar p_ptt, 4662c965db44STomer Tayar nvram_image_type, 46637b6859fbSMintz, Yuval trace_meta_offset, trace_meta_size); 4664c965db44STomer Tayar } 4665c965db44STomer Tayar 46667b6859fbSMintz, Yuval /* Reads the MCP Trace meta data from NVRAM into the specified buffer */ 4667c965db44STomer Tayar static enum dbg_status qed_mcp_trace_read_meta(struct qed_hwfn *p_hwfn, 4668c965db44STomer Tayar struct qed_ptt *p_ptt, 4669c965db44STomer Tayar u32 nvram_offset_in_bytes, 4670c965db44STomer Tayar u32 size_in_bytes, u32 *buf) 4671c965db44STomer Tayar { 46727b6859fbSMintz, Yuval u8 modules_num, module_len, i, *byte_buf = (u8 *)buf; 46737b6859fbSMintz, Yuval enum dbg_status status; 4674c965db44STomer Tayar u32 signature; 4675c965db44STomer Tayar 4676c965db44STomer Tayar /* Read meta data from NVRAM */ 46777b6859fbSMintz, Yuval status = qed_nvram_read(p_hwfn, 4678c965db44STomer Tayar p_ptt, 46797b6859fbSMintz, Yuval nvram_offset_in_bytes, size_in_bytes, buf); 4680c965db44STomer Tayar if (status != DBG_STATUS_OK) 4681c965db44STomer Tayar return status; 4682c965db44STomer Tayar 4683c965db44STomer Tayar /* Extract and check first signature */ 4684c965db44STomer Tayar signature = qed_read_unaligned_dword(byte_buf); 46857b6859fbSMintz, Yuval byte_buf += sizeof(signature); 46867b6859fbSMintz, Yuval if (signature != NVM_MAGIC_VALUE) 4687c965db44STomer Tayar return DBG_STATUS_INVALID_TRACE_SIGNATURE; 4688c965db44STomer Tayar 4689c965db44STomer Tayar /* Extract number of modules */ 4690c965db44STomer Tayar modules_num = *(byte_buf++); 4691c965db44STomer Tayar 4692c965db44STomer Tayar /* Skip all modules */ 4693c965db44STomer Tayar for (i = 0; i < modules_num; i++) { 46947b6859fbSMintz, Yuval module_len = *(byte_buf++); 4695c965db44STomer Tayar byte_buf += module_len; 4696c965db44STomer Tayar } 4697c965db44STomer Tayar 4698c965db44STomer Tayar /* Extract and check second signature */ 4699c965db44STomer Tayar signature = qed_read_unaligned_dword(byte_buf); 47007b6859fbSMintz, Yuval byte_buf += sizeof(signature); 47017b6859fbSMintz, Yuval if (signature != NVM_MAGIC_VALUE) 4702c965db44STomer Tayar return DBG_STATUS_INVALID_TRACE_SIGNATURE; 47037b6859fbSMintz, Yuval 4704c965db44STomer Tayar return DBG_STATUS_OK; 4705c965db44STomer Tayar } 4706c965db44STomer Tayar 4707c965db44STomer Tayar /* Dump MCP Trace */ 47088c93beafSYuval Mintz static enum dbg_status qed_mcp_trace_dump(struct qed_hwfn *p_hwfn, 4709c965db44STomer Tayar struct qed_ptt *p_ptt, 4710c965db44STomer Tayar u32 *dump_buf, 4711c965db44STomer Tayar bool dump, u32 *num_dumped_dwords) 4712c965db44STomer Tayar { 4713c965db44STomer Tayar u32 trace_data_grc_addr, trace_data_size_bytes, trace_data_size_dwords; 4714be086e7cSMintz, Yuval u32 trace_meta_size_dwords = 0, running_bundle_id, offset = 0; 4715be086e7cSMintz, Yuval u32 trace_meta_offset_bytes = 0, trace_meta_size_bytes = 0; 4716c965db44STomer Tayar enum dbg_status status; 4717be086e7cSMintz, Yuval bool mcp_access; 4718c965db44STomer Tayar int halted = 0; 4719c965db44STomer Tayar 4720c965db44STomer Tayar *num_dumped_dwords = 0; 4721c965db44STomer Tayar 47227b6859fbSMintz, Yuval mcp_access = !qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_NO_MCP); 47237b6859fbSMintz, Yuval 4724c965db44STomer Tayar /* Get trace data info */ 4725c965db44STomer Tayar status = qed_mcp_trace_get_data_info(p_hwfn, 4726c965db44STomer Tayar p_ptt, 4727c965db44STomer Tayar &trace_data_grc_addr, 4728c965db44STomer Tayar &trace_data_size_bytes); 4729c965db44STomer Tayar if (status != DBG_STATUS_OK) 4730c965db44STomer Tayar return status; 4731c965db44STomer Tayar 4732c965db44STomer Tayar /* Dump global params */ 4733c965db44STomer Tayar offset += qed_dump_common_global_params(p_hwfn, 4734c965db44STomer Tayar p_ptt, 4735c965db44STomer Tayar dump_buf + offset, dump, 1); 4736c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 4737c965db44STomer Tayar dump, "dump-type", "mcp-trace"); 4738c965db44STomer Tayar 4739c965db44STomer Tayar /* Halt MCP while reading from scratchpad so the read data will be 47407b6859fbSMintz, Yuval * consistent. if halt fails, MCP trace is taken anyway, with a small 4741c965db44STomer Tayar * risk that it may be corrupt. 4742c965db44STomer Tayar */ 4743be086e7cSMintz, Yuval if (dump && mcp_access) { 4744c965db44STomer Tayar halted = !qed_mcp_halt(p_hwfn, p_ptt); 4745c965db44STomer Tayar if (!halted) 4746c965db44STomer Tayar DP_NOTICE(p_hwfn, "MCP halt failed!\n"); 4747c965db44STomer Tayar } 4748c965db44STomer Tayar 4749c965db44STomer Tayar /* Find trace data size */ 4750c965db44STomer Tayar trace_data_size_dwords = 4751c965db44STomer Tayar DIV_ROUND_UP(trace_data_size_bytes + sizeof(struct mcp_trace), 4752c965db44STomer Tayar BYTES_IN_DWORD); 4753c965db44STomer Tayar 4754c965db44STomer Tayar /* Dump trace data section header and param */ 4755c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, 4756c965db44STomer Tayar dump, "mcp_trace_data", 1); 4757c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, 4758c965db44STomer Tayar dump, "size", trace_data_size_dwords); 4759c965db44STomer Tayar 4760c965db44STomer Tayar /* Read trace data from scratchpad into dump buffer */ 4761be086e7cSMintz, Yuval offset += qed_grc_dump_addr_range(p_hwfn, 4762c965db44STomer Tayar p_ptt, 4763be086e7cSMintz, Yuval dump_buf + offset, 4764be086e7cSMintz, Yuval dump, 4765be086e7cSMintz, Yuval BYTES_TO_DWORDS(trace_data_grc_addr), 4766d52c89f1SMichal Kalderon trace_data_size_dwords, false, 4767d52c89f1SMichal Kalderon SPLIT_TYPE_NONE, 0); 4768c965db44STomer Tayar 4769c965db44STomer Tayar /* Resume MCP (only if halt succeeded) */ 47707b6859fbSMintz, Yuval if (halted && qed_mcp_resume(p_hwfn, p_ptt)) 4771c965db44STomer Tayar DP_NOTICE(p_hwfn, "Failed to resume MCP after halt!\n"); 4772c965db44STomer Tayar 4773c965db44STomer Tayar /* Dump trace meta section header */ 4774c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, 4775c965db44STomer Tayar dump, "mcp_trace_meta", 1); 4776c965db44STomer Tayar 477750bc60cbSMichal Kalderon /* If MCP Trace meta size parameter was set, use it. 477850bc60cbSMichal Kalderon * Otherwise, read trace meta. 477950bc60cbSMichal Kalderon * trace_meta_size_bytes is dword-aligned. 478050bc60cbSMichal Kalderon */ 478150bc60cbSMichal Kalderon trace_meta_size_bytes = 478250bc60cbSMichal Kalderon qed_grc_get_param(p_hwfn, DBG_GRC_PARAM_MCP_TRACE_META_SIZE); 478350bc60cbSMichal Kalderon if ((!trace_meta_size_bytes || dump) && mcp_access) { 4784c965db44STomer Tayar status = qed_mcp_trace_get_meta_info(p_hwfn, 4785c965db44STomer Tayar p_ptt, 4786c965db44STomer Tayar trace_data_size_bytes, 4787c965db44STomer Tayar &running_bundle_id, 4788c965db44STomer Tayar &trace_meta_offset_bytes, 4789c965db44STomer Tayar &trace_meta_size_bytes); 4790be086e7cSMintz, Yuval if (status == DBG_STATUS_OK) 4791be086e7cSMintz, Yuval trace_meta_size_dwords = 4792be086e7cSMintz, Yuval BYTES_TO_DWORDS(trace_meta_size_bytes); 4793be086e7cSMintz, Yuval } 4794c965db44STomer Tayar 4795be086e7cSMintz, Yuval /* Dump trace meta size param */ 4796be086e7cSMintz, Yuval offset += qed_dump_num_param(dump_buf + offset, 4797be086e7cSMintz, Yuval dump, "size", trace_meta_size_dwords); 4798c965db44STomer Tayar 4799c965db44STomer Tayar /* Read trace meta image into dump buffer */ 4800be086e7cSMintz, Yuval if (dump && trace_meta_size_dwords) 4801c965db44STomer Tayar status = qed_mcp_trace_read_meta(p_hwfn, 4802c965db44STomer Tayar p_ptt, 4803c965db44STomer Tayar trace_meta_offset_bytes, 4804c965db44STomer Tayar trace_meta_size_bytes, 4805c965db44STomer Tayar dump_buf + offset); 4806be086e7cSMintz, Yuval if (status == DBG_STATUS_OK) 4807c965db44STomer Tayar offset += trace_meta_size_dwords; 4808c965db44STomer Tayar 48097b6859fbSMintz, Yuval /* Dump last section */ 4810da090917STomer Tayar offset += qed_dump_last_section(dump_buf, offset, dump); 48117b6859fbSMintz, Yuval 4812c965db44STomer Tayar *num_dumped_dwords = offset; 4813c965db44STomer Tayar 4814be086e7cSMintz, Yuval /* If no mcp access, indicate that the dump doesn't contain the meta 4815be086e7cSMintz, Yuval * data from NVRAM. 4816be086e7cSMintz, Yuval */ 4817be086e7cSMintz, Yuval return mcp_access ? status : DBG_STATUS_NVRAM_GET_IMAGE_FAILED; 4818c965db44STomer Tayar } 4819c965db44STomer Tayar 4820c965db44STomer Tayar /* Dump GRC FIFO */ 48218c93beafSYuval Mintz static enum dbg_status qed_reg_fifo_dump(struct qed_hwfn *p_hwfn, 4822c965db44STomer Tayar struct qed_ptt *p_ptt, 4823c965db44STomer Tayar u32 *dump_buf, 4824c965db44STomer Tayar bool dump, u32 *num_dumped_dwords) 4825c965db44STomer Tayar { 4826da090917STomer Tayar u32 dwords_read, size_param_offset, offset = 0, addr, len; 4827c965db44STomer Tayar bool fifo_has_data; 4828c965db44STomer Tayar 4829c965db44STomer Tayar *num_dumped_dwords = 0; 4830c965db44STomer Tayar 4831c965db44STomer Tayar /* Dump global params */ 4832c965db44STomer Tayar offset += qed_dump_common_global_params(p_hwfn, 4833c965db44STomer Tayar p_ptt, 4834c965db44STomer Tayar dump_buf + offset, dump, 1); 4835c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 4836c965db44STomer Tayar dump, "dump-type", "reg-fifo"); 4837c965db44STomer Tayar 48387b6859fbSMintz, Yuval /* Dump fifo data section header and param. The size param is 0 for 48397b6859fbSMintz, Yuval * now, and is overwritten after reading the FIFO. 4840c965db44STomer Tayar */ 4841c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, 4842c965db44STomer Tayar dump, "reg_fifo_data", 1); 4843c965db44STomer Tayar size_param_offset = offset; 4844c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, dump, "size", 0); 4845c965db44STomer Tayar 4846c965db44STomer Tayar if (!dump) { 4847c965db44STomer Tayar /* FIFO max size is REG_FIFO_DEPTH_DWORDS. There is no way to 4848c965db44STomer Tayar * test how much data is available, except for reading it. 4849c965db44STomer Tayar */ 4850c965db44STomer Tayar offset += REG_FIFO_DEPTH_DWORDS; 48517b6859fbSMintz, Yuval goto out; 4852c965db44STomer Tayar } 4853c965db44STomer Tayar 4854c965db44STomer Tayar fifo_has_data = qed_rd(p_hwfn, p_ptt, 4855c965db44STomer Tayar GRC_REG_TRACE_FIFO_VALID_DATA) > 0; 4856c965db44STomer Tayar 4857c965db44STomer Tayar /* Pull available data from fifo. Use DMAE since this is widebus memory 4858c965db44STomer Tayar * and must be accessed atomically. Test for dwords_read not passing 4859c965db44STomer Tayar * buffer size since more entries could be added to the buffer as we are 4860c965db44STomer Tayar * emptying it. 4861c965db44STomer Tayar */ 4862da090917STomer Tayar addr = BYTES_TO_DWORDS(GRC_REG_TRACE_FIFO); 4863da090917STomer Tayar len = REG_FIFO_ELEMENT_DWORDS; 4864c965db44STomer Tayar for (dwords_read = 0; 4865c965db44STomer Tayar fifo_has_data && dwords_read < REG_FIFO_DEPTH_DWORDS; 4866da090917STomer Tayar dwords_read += REG_FIFO_ELEMENT_DWORDS) { 4867da090917STomer Tayar offset += qed_grc_dump_addr_range(p_hwfn, 4868da090917STomer Tayar p_ptt, 4869da090917STomer Tayar dump_buf + offset, 4870da090917STomer Tayar true, 4871da090917STomer Tayar addr, 4872da090917STomer Tayar len, 4873d52c89f1SMichal Kalderon true, SPLIT_TYPE_NONE, 4874d52c89f1SMichal Kalderon 0); 4875c965db44STomer Tayar fifo_has_data = qed_rd(p_hwfn, p_ptt, 4876c965db44STomer Tayar GRC_REG_TRACE_FIFO_VALID_DATA) > 0; 4877c965db44STomer Tayar } 4878c965db44STomer Tayar 4879c965db44STomer Tayar qed_dump_num_param(dump_buf + size_param_offset, dump, "size", 4880c965db44STomer Tayar dwords_read); 48817b6859fbSMintz, Yuval out: 48827b6859fbSMintz, Yuval /* Dump last section */ 4883da090917STomer Tayar offset += qed_dump_last_section(dump_buf, offset, dump); 4884c965db44STomer Tayar 4885c965db44STomer Tayar *num_dumped_dwords = offset; 48867b6859fbSMintz, Yuval 4887c965db44STomer Tayar return DBG_STATUS_OK; 4888c965db44STomer Tayar } 4889c965db44STomer Tayar 4890c965db44STomer Tayar /* Dump IGU FIFO */ 48918c93beafSYuval Mintz static enum dbg_status qed_igu_fifo_dump(struct qed_hwfn *p_hwfn, 4892c965db44STomer Tayar struct qed_ptt *p_ptt, 4893c965db44STomer Tayar u32 *dump_buf, 4894c965db44STomer Tayar bool dump, u32 *num_dumped_dwords) 4895c965db44STomer Tayar { 4896da090917STomer Tayar u32 dwords_read, size_param_offset, offset = 0, addr, len; 4897c965db44STomer Tayar bool fifo_has_data; 4898c965db44STomer Tayar 4899c965db44STomer Tayar *num_dumped_dwords = 0; 4900c965db44STomer Tayar 4901c965db44STomer Tayar /* Dump global params */ 4902c965db44STomer Tayar offset += qed_dump_common_global_params(p_hwfn, 4903c965db44STomer Tayar p_ptt, 4904c965db44STomer Tayar dump_buf + offset, dump, 1); 4905c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 4906c965db44STomer Tayar dump, "dump-type", "igu-fifo"); 4907c965db44STomer Tayar 49087b6859fbSMintz, Yuval /* Dump fifo data section header and param. The size param is 0 for 49097b6859fbSMintz, Yuval * now, and is overwritten after reading the FIFO. 4910c965db44STomer Tayar */ 4911c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, 4912c965db44STomer Tayar dump, "igu_fifo_data", 1); 4913c965db44STomer Tayar size_param_offset = offset; 4914c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, dump, "size", 0); 4915c965db44STomer Tayar 4916c965db44STomer Tayar if (!dump) { 4917c965db44STomer Tayar /* FIFO max size is IGU_FIFO_DEPTH_DWORDS. There is no way to 4918c965db44STomer Tayar * test how much data is available, except for reading it. 4919c965db44STomer Tayar */ 4920c965db44STomer Tayar offset += IGU_FIFO_DEPTH_DWORDS; 49217b6859fbSMintz, Yuval goto out; 4922c965db44STomer Tayar } 4923c965db44STomer Tayar 4924c965db44STomer Tayar fifo_has_data = qed_rd(p_hwfn, p_ptt, 4925c965db44STomer Tayar IGU_REG_ERROR_HANDLING_DATA_VALID) > 0; 4926c965db44STomer Tayar 4927c965db44STomer Tayar /* Pull available data from fifo. Use DMAE since this is widebus memory 4928c965db44STomer Tayar * and must be accessed atomically. Test for dwords_read not passing 4929c965db44STomer Tayar * buffer size since more entries could be added to the buffer as we are 4930c965db44STomer Tayar * emptying it. 4931c965db44STomer Tayar */ 4932da090917STomer Tayar addr = BYTES_TO_DWORDS(IGU_REG_ERROR_HANDLING_MEMORY); 4933da090917STomer Tayar len = IGU_FIFO_ELEMENT_DWORDS; 4934c965db44STomer Tayar for (dwords_read = 0; 4935c965db44STomer Tayar fifo_has_data && dwords_read < IGU_FIFO_DEPTH_DWORDS; 4936da090917STomer Tayar dwords_read += IGU_FIFO_ELEMENT_DWORDS) { 4937da090917STomer Tayar offset += qed_grc_dump_addr_range(p_hwfn, 4938da090917STomer Tayar p_ptt, 4939da090917STomer Tayar dump_buf + offset, 4940da090917STomer Tayar true, 4941da090917STomer Tayar addr, 4942da090917STomer Tayar len, 4943d52c89f1SMichal Kalderon true, SPLIT_TYPE_NONE, 4944d52c89f1SMichal Kalderon 0); 4945c965db44STomer Tayar fifo_has_data = qed_rd(p_hwfn, p_ptt, 4946c965db44STomer Tayar IGU_REG_ERROR_HANDLING_DATA_VALID) > 0; 4947c965db44STomer Tayar } 4948c965db44STomer Tayar 4949c965db44STomer Tayar qed_dump_num_param(dump_buf + size_param_offset, dump, "size", 4950c965db44STomer Tayar dwords_read); 49517b6859fbSMintz, Yuval out: 49527b6859fbSMintz, Yuval /* Dump last section */ 4953da090917STomer Tayar offset += qed_dump_last_section(dump_buf, offset, dump); 4954c965db44STomer Tayar 4955c965db44STomer Tayar *num_dumped_dwords = offset; 49567b6859fbSMintz, Yuval 4957c965db44STomer Tayar return DBG_STATUS_OK; 4958c965db44STomer Tayar } 4959c965db44STomer Tayar 4960c965db44STomer Tayar /* Protection Override dump */ 49618c93beafSYuval Mintz static enum dbg_status qed_protection_override_dump(struct qed_hwfn *p_hwfn, 4962c965db44STomer Tayar struct qed_ptt *p_ptt, 4963c965db44STomer Tayar u32 *dump_buf, 49648c93beafSYuval Mintz bool dump, 49658c93beafSYuval Mintz u32 *num_dumped_dwords) 4966c965db44STomer Tayar { 4967da090917STomer Tayar u32 size_param_offset, override_window_dwords, offset = 0, addr; 4968c965db44STomer Tayar 4969c965db44STomer Tayar *num_dumped_dwords = 0; 4970c965db44STomer Tayar 4971c965db44STomer Tayar /* Dump global params */ 4972c965db44STomer Tayar offset += qed_dump_common_global_params(p_hwfn, 4973c965db44STomer Tayar p_ptt, 4974c965db44STomer Tayar dump_buf + offset, dump, 1); 4975c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 4976c965db44STomer Tayar dump, "dump-type", "protection-override"); 4977c965db44STomer Tayar 49787b6859fbSMintz, Yuval /* Dump data section header and param. The size param is 0 for now, 49797b6859fbSMintz, Yuval * and is overwritten after reading the data. 4980c965db44STomer Tayar */ 4981c965db44STomer Tayar offset += qed_dump_section_hdr(dump_buf + offset, 4982c965db44STomer Tayar dump, "protection_override_data", 1); 4983c965db44STomer Tayar size_param_offset = offset; 4984c965db44STomer Tayar offset += qed_dump_num_param(dump_buf + offset, dump, "size", 0); 4985c965db44STomer Tayar 4986c965db44STomer Tayar if (!dump) { 4987c965db44STomer Tayar offset += PROTECTION_OVERRIDE_DEPTH_DWORDS; 49887b6859fbSMintz, Yuval goto out; 4989c965db44STomer Tayar } 4990c965db44STomer Tayar 4991c965db44STomer Tayar /* Add override window info to buffer */ 4992c965db44STomer Tayar override_window_dwords = 4993da090917STomer Tayar qed_rd(p_hwfn, p_ptt, GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW) * 4994c965db44STomer Tayar PROTECTION_OVERRIDE_ELEMENT_DWORDS; 4995da090917STomer Tayar addr = BYTES_TO_DWORDS(GRC_REG_PROTECTION_OVERRIDE_WINDOW); 4996da090917STomer Tayar offset += qed_grc_dump_addr_range(p_hwfn, 4997da090917STomer Tayar p_ptt, 4998da090917STomer Tayar dump_buf + offset, 4999da090917STomer Tayar true, 5000da090917STomer Tayar addr, 5001da090917STomer Tayar override_window_dwords, 5002d52c89f1SMichal Kalderon true, SPLIT_TYPE_NONE, 0); 5003c965db44STomer Tayar qed_dump_num_param(dump_buf + size_param_offset, dump, "size", 5004c965db44STomer Tayar override_window_dwords); 50057b6859fbSMintz, Yuval out: 50067b6859fbSMintz, Yuval /* Dump last section */ 5007da090917STomer Tayar offset += qed_dump_last_section(dump_buf, offset, dump); 5008c965db44STomer Tayar 5009c965db44STomer Tayar *num_dumped_dwords = offset; 50107b6859fbSMintz, Yuval 5011c965db44STomer Tayar return DBG_STATUS_OK; 5012c965db44STomer Tayar } 5013c965db44STomer Tayar 5014c965db44STomer Tayar /* Performs FW Asserts Dump to the specified buffer. 5015c965db44STomer Tayar * Returns the dumped size in dwords. 5016c965db44STomer Tayar */ 5017c965db44STomer Tayar static u32 qed_fw_asserts_dump(struct qed_hwfn *p_hwfn, 5018c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *dump_buf, bool dump) 5019c965db44STomer Tayar { 5020c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5021be086e7cSMintz, Yuval struct fw_asserts_ram_section *asserts; 5022c965db44STomer Tayar char storm_letter_str[2] = "?"; 5023c965db44STomer Tayar struct fw_info fw_info; 5024be086e7cSMintz, Yuval u32 offset = 0; 5025c965db44STomer Tayar u8 storm_id; 5026c965db44STomer Tayar 5027c965db44STomer Tayar /* Dump global params */ 5028c965db44STomer Tayar offset += qed_dump_common_global_params(p_hwfn, 5029c965db44STomer Tayar p_ptt, 5030c965db44STomer Tayar dump_buf + offset, dump, 1); 5031c965db44STomer Tayar offset += qed_dump_str_param(dump_buf + offset, 5032c965db44STomer Tayar dump, "dump-type", "fw-asserts"); 50337b6859fbSMintz, Yuval 50347b6859fbSMintz, Yuval /* Find Storm dump size */ 5035c965db44STomer Tayar for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 5036be086e7cSMintz, Yuval u32 fw_asserts_section_addr, next_list_idx_addr, next_list_idx; 50377b6859fbSMintz, Yuval struct storm_defs *storm = &s_storm_defs[storm_id]; 5038be086e7cSMintz, Yuval u32 last_list_idx, addr; 5039c965db44STomer Tayar 50407b6859fbSMintz, Yuval if (dev_data->block_in_reset[storm->block_id]) 5041c965db44STomer Tayar continue; 5042c965db44STomer Tayar 5043c965db44STomer Tayar /* Read FW info for the current Storm */ 5044d52c89f1SMichal Kalderon qed_read_storm_fw_info(p_hwfn, p_ptt, storm_id, &fw_info); 5045c965db44STomer Tayar 5046be086e7cSMintz, Yuval asserts = &fw_info.fw_asserts_section; 5047be086e7cSMintz, Yuval 5048c965db44STomer Tayar /* Dump FW Asserts section header and params */ 50497b6859fbSMintz, Yuval storm_letter_str[0] = storm->letter; 50507b6859fbSMintz, Yuval offset += qed_dump_section_hdr(dump_buf + offset, 50517b6859fbSMintz, Yuval dump, "fw_asserts", 2); 50527b6859fbSMintz, Yuval offset += qed_dump_str_param(dump_buf + offset, 50537b6859fbSMintz, Yuval dump, "storm", storm_letter_str); 50547b6859fbSMintz, Yuval offset += qed_dump_num_param(dump_buf + offset, 50557b6859fbSMintz, Yuval dump, 50567b6859fbSMintz, Yuval "size", 5057be086e7cSMintz, Yuval asserts->list_element_dword_size); 5058c965db44STomer Tayar 50597b6859fbSMintz, Yuval /* Read and dump FW Asserts data */ 5060c965db44STomer Tayar if (!dump) { 5061be086e7cSMintz, Yuval offset += asserts->list_element_dword_size; 5062c965db44STomer Tayar continue; 5063c965db44STomer Tayar } 5064c965db44STomer Tayar 50657b6859fbSMintz, Yuval fw_asserts_section_addr = storm->sem_fast_mem_addr + 5066c965db44STomer Tayar SEM_FAST_REG_INT_RAM + 5067be086e7cSMintz, Yuval RAM_LINES_TO_BYTES(asserts->section_ram_line_offset); 50687b6859fbSMintz, Yuval next_list_idx_addr = fw_asserts_section_addr + 5069be086e7cSMintz, Yuval DWORDS_TO_BYTES(asserts->list_next_index_dword_offset); 5070c965db44STomer Tayar next_list_idx = qed_rd(p_hwfn, p_ptt, next_list_idx_addr); 5071da090917STomer Tayar last_list_idx = (next_list_idx > 0 ? 5072da090917STomer Tayar next_list_idx : 5073da090917STomer Tayar asserts->list_num_elements) - 1; 5074be086e7cSMintz, Yuval addr = BYTES_TO_DWORDS(fw_asserts_section_addr) + 5075be086e7cSMintz, Yuval asserts->list_dword_offset + 5076be086e7cSMintz, Yuval last_list_idx * asserts->list_element_dword_size; 5077be086e7cSMintz, Yuval offset += 5078be086e7cSMintz, Yuval qed_grc_dump_addr_range(p_hwfn, p_ptt, 5079be086e7cSMintz, Yuval dump_buf + offset, 5080be086e7cSMintz, Yuval dump, addr, 50817b6859fbSMintz, Yuval asserts->list_element_dword_size, 5082d52c89f1SMichal Kalderon false, SPLIT_TYPE_NONE, 0); 5083c965db44STomer Tayar } 5084c965db44STomer Tayar 5085c965db44STomer Tayar /* Dump last section */ 5086da090917STomer Tayar offset += qed_dump_last_section(dump_buf, offset, dump); 50877b6859fbSMintz, Yuval 5088c965db44STomer Tayar return offset; 5089c965db44STomer Tayar } 5090c965db44STomer Tayar 5091c965db44STomer Tayar /***************************** Public Functions *******************************/ 5092c965db44STomer Tayar 5093c965db44STomer Tayar enum dbg_status qed_dbg_set_bin_ptr(const u8 * const bin_ptr) 5094c965db44STomer Tayar { 5095be086e7cSMintz, Yuval struct bin_buffer_hdr *buf_array = (struct bin_buffer_hdr *)bin_ptr; 5096c965db44STomer Tayar u8 buf_id; 5097c965db44STomer Tayar 50987b6859fbSMintz, Yuval /* convert binary data to debug arrays */ 5099be086e7cSMintz, Yuval for (buf_id = 0; buf_id < MAX_BIN_DBG_BUFFER_TYPE; buf_id++) { 5100c965db44STomer Tayar s_dbg_arrays[buf_id].ptr = 5101c965db44STomer Tayar (u32 *)(bin_ptr + buf_array[buf_id].offset); 5102c965db44STomer Tayar s_dbg_arrays[buf_id].size_in_dwords = 5103c965db44STomer Tayar BYTES_TO_DWORDS(buf_array[buf_id].length); 5104c965db44STomer Tayar } 5105c965db44STomer Tayar 5106c965db44STomer Tayar return DBG_STATUS_OK; 5107c965db44STomer Tayar } 5108c965db44STomer Tayar 5109d52c89f1SMichal Kalderon bool qed_read_fw_info(struct qed_hwfn *p_hwfn, 5110d52c89f1SMichal Kalderon struct qed_ptt *p_ptt, struct fw_info *fw_info) 5111d52c89f1SMichal Kalderon { 5112d52c89f1SMichal Kalderon struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5113d52c89f1SMichal Kalderon u8 storm_id; 5114d52c89f1SMichal Kalderon 5115d52c89f1SMichal Kalderon for (storm_id = 0; storm_id < MAX_DBG_STORMS; storm_id++) { 5116d52c89f1SMichal Kalderon struct storm_defs *storm = &s_storm_defs[storm_id]; 5117d52c89f1SMichal Kalderon 5118d52c89f1SMichal Kalderon /* Skip Storm if it's in reset */ 5119d52c89f1SMichal Kalderon if (dev_data->block_in_reset[storm->block_id]) 5120d52c89f1SMichal Kalderon continue; 5121d52c89f1SMichal Kalderon 5122d52c89f1SMichal Kalderon /* Read FW info for the current Storm */ 5123d52c89f1SMichal Kalderon qed_read_storm_fw_info(p_hwfn, p_ptt, storm_id, fw_info); 5124d52c89f1SMichal Kalderon 5125d52c89f1SMichal Kalderon return true; 5126d52c89f1SMichal Kalderon } 5127d52c89f1SMichal Kalderon 5128d52c89f1SMichal Kalderon return false; 5129d52c89f1SMichal Kalderon } 5130d52c89f1SMichal Kalderon 51313b86bd07SSudarsana Reddy Kalluru enum dbg_status qed_dbg_grc_config(struct qed_hwfn *p_hwfn, 51323b86bd07SSudarsana Reddy Kalluru struct qed_ptt *p_ptt, 51333b86bd07SSudarsana Reddy Kalluru enum dbg_grc_params grc_param, u32 val) 51343b86bd07SSudarsana Reddy Kalluru { 51353b86bd07SSudarsana Reddy Kalluru enum dbg_status status; 51363b86bd07SSudarsana Reddy Kalluru int i; 51373b86bd07SSudarsana Reddy Kalluru 51383b86bd07SSudarsana Reddy Kalluru DP_VERBOSE(p_hwfn, QED_MSG_DEBUG, 51393b86bd07SSudarsana Reddy Kalluru "dbg_grc_config: paramId = %d, val = %d\n", grc_param, val); 51403b86bd07SSudarsana Reddy Kalluru 51413b86bd07SSudarsana Reddy Kalluru status = qed_dbg_dev_init(p_hwfn, p_ptt); 51423b86bd07SSudarsana Reddy Kalluru if (status != DBG_STATUS_OK) 51433b86bd07SSudarsana Reddy Kalluru return status; 51443b86bd07SSudarsana Reddy Kalluru 51453b86bd07SSudarsana Reddy Kalluru /* Initializes the GRC parameters (if not initialized). Needed in order 51463b86bd07SSudarsana Reddy Kalluru * to set the default parameter values for the first time. 51473b86bd07SSudarsana Reddy Kalluru */ 51483b86bd07SSudarsana Reddy Kalluru qed_dbg_grc_init_params(p_hwfn); 51493b86bd07SSudarsana Reddy Kalluru 51503b86bd07SSudarsana Reddy Kalluru if (grc_param >= MAX_DBG_GRC_PARAMS) 51513b86bd07SSudarsana Reddy Kalluru return DBG_STATUS_INVALID_ARGS; 51523b86bd07SSudarsana Reddy Kalluru if (val < s_grc_param_defs[grc_param].min || 51533b86bd07SSudarsana Reddy Kalluru val > s_grc_param_defs[grc_param].max) 51543b86bd07SSudarsana Reddy Kalluru return DBG_STATUS_INVALID_ARGS; 51553b86bd07SSudarsana Reddy Kalluru 51563b86bd07SSudarsana Reddy Kalluru if (s_grc_param_defs[grc_param].is_preset) { 51573b86bd07SSudarsana Reddy Kalluru /* Preset param */ 51583b86bd07SSudarsana Reddy Kalluru 51593b86bd07SSudarsana Reddy Kalluru /* Disabling a preset is not allowed. Call 51603b86bd07SSudarsana Reddy Kalluru * dbg_grc_set_params_default instead. 51613b86bd07SSudarsana Reddy Kalluru */ 51623b86bd07SSudarsana Reddy Kalluru if (!val) 51633b86bd07SSudarsana Reddy Kalluru return DBG_STATUS_INVALID_ARGS; 51643b86bd07SSudarsana Reddy Kalluru 51653b86bd07SSudarsana Reddy Kalluru /* Update all params with the preset values */ 51663b86bd07SSudarsana Reddy Kalluru for (i = 0; i < MAX_DBG_GRC_PARAMS; i++) { 51673b86bd07SSudarsana Reddy Kalluru u32 preset_val; 51683b86bd07SSudarsana Reddy Kalluru 51693b86bd07SSudarsana Reddy Kalluru /* Skip persistent params */ 51703b86bd07SSudarsana Reddy Kalluru if (s_grc_param_defs[i].is_persistent) 51713b86bd07SSudarsana Reddy Kalluru continue; 51723b86bd07SSudarsana Reddy Kalluru 51733b86bd07SSudarsana Reddy Kalluru /* Find preset value */ 51743b86bd07SSudarsana Reddy Kalluru if (grc_param == DBG_GRC_PARAM_EXCLUDE_ALL) 51753b86bd07SSudarsana Reddy Kalluru preset_val = 51763b86bd07SSudarsana Reddy Kalluru s_grc_param_defs[i].exclude_all_preset_val; 51773b86bd07SSudarsana Reddy Kalluru else if (grc_param == DBG_GRC_PARAM_CRASH) 51783b86bd07SSudarsana Reddy Kalluru preset_val = 51793b86bd07SSudarsana Reddy Kalluru s_grc_param_defs[i].crash_preset_val; 51803b86bd07SSudarsana Reddy Kalluru else 51813b86bd07SSudarsana Reddy Kalluru return DBG_STATUS_INVALID_ARGS; 51823b86bd07SSudarsana Reddy Kalluru 51833b86bd07SSudarsana Reddy Kalluru qed_grc_set_param(p_hwfn, 51843b86bd07SSudarsana Reddy Kalluru (enum dbg_grc_params)i, preset_val); 51853b86bd07SSudarsana Reddy Kalluru } 51863b86bd07SSudarsana Reddy Kalluru } else { 51873b86bd07SSudarsana Reddy Kalluru /* Regular param - set its value */ 51883b86bd07SSudarsana Reddy Kalluru qed_grc_set_param(p_hwfn, grc_param, val); 51893b86bd07SSudarsana Reddy Kalluru } 51903b86bd07SSudarsana Reddy Kalluru 51913b86bd07SSudarsana Reddy Kalluru return DBG_STATUS_OK; 51923b86bd07SSudarsana Reddy Kalluru } 51933b86bd07SSudarsana Reddy Kalluru 5194be086e7cSMintz, Yuval /* Assign default GRC param values */ 5195be086e7cSMintz, Yuval void qed_dbg_grc_set_params_default(struct qed_hwfn *p_hwfn) 5196be086e7cSMintz, Yuval { 5197be086e7cSMintz, Yuval struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 5198be086e7cSMintz, Yuval u32 i; 5199be086e7cSMintz, Yuval 5200be086e7cSMintz, Yuval for (i = 0; i < MAX_DBG_GRC_PARAMS; i++) 520150bc60cbSMichal Kalderon if (!s_grc_param_defs[i].is_persistent) 5202be086e7cSMintz, Yuval dev_data->grc.param_val[i] = 5203be086e7cSMintz, Yuval s_grc_param_defs[i].default_val[dev_data->chip_id]; 5204be086e7cSMintz, Yuval } 5205be086e7cSMintz, Yuval 5206c965db44STomer Tayar enum dbg_status qed_dbg_grc_get_dump_buf_size(struct qed_hwfn *p_hwfn, 5207c965db44STomer Tayar struct qed_ptt *p_ptt, 5208c965db44STomer Tayar u32 *buf_size) 5209c965db44STomer Tayar { 5210c965db44STomer Tayar enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt); 5211c965db44STomer Tayar 5212c965db44STomer Tayar *buf_size = 0; 52137b6859fbSMintz, Yuval 5214c965db44STomer Tayar if (status != DBG_STATUS_OK) 5215c965db44STomer Tayar return status; 52167b6859fbSMintz, Yuval 5217c965db44STomer Tayar if (!s_dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr || 5218c965db44STomer Tayar !s_dbg_arrays[BIN_BUF_DBG_DUMP_REG].ptr || 5219c965db44STomer Tayar !s_dbg_arrays[BIN_BUF_DBG_DUMP_MEM].ptr || 5220c965db44STomer Tayar !s_dbg_arrays[BIN_BUF_DBG_ATTN_BLOCKS].ptr || 5221c965db44STomer Tayar !s_dbg_arrays[BIN_BUF_DBG_ATTN_REGS].ptr) 5222c965db44STomer Tayar return DBG_STATUS_DBG_ARRAY_NOT_SET; 52237b6859fbSMintz, Yuval 5224c965db44STomer Tayar return qed_grc_dump(p_hwfn, p_ptt, NULL, false, buf_size); 5225c965db44STomer Tayar } 5226c965db44STomer Tayar 5227c965db44STomer Tayar enum dbg_status qed_dbg_grc_dump(struct qed_hwfn *p_hwfn, 5228c965db44STomer Tayar struct qed_ptt *p_ptt, 5229c965db44STomer Tayar u32 *dump_buf, 5230c965db44STomer Tayar u32 buf_size_in_dwords, 5231c965db44STomer Tayar u32 *num_dumped_dwords) 5232c965db44STomer Tayar { 5233c965db44STomer Tayar u32 needed_buf_size_in_dwords; 5234c965db44STomer Tayar enum dbg_status status; 5235c965db44STomer Tayar 5236c965db44STomer Tayar *num_dumped_dwords = 0; 52377b6859fbSMintz, Yuval 52387b6859fbSMintz, Yuval status = qed_dbg_grc_get_dump_buf_size(p_hwfn, 52397b6859fbSMintz, Yuval p_ptt, 52407b6859fbSMintz, Yuval &needed_buf_size_in_dwords); 5241c965db44STomer Tayar if (status != DBG_STATUS_OK) 5242c965db44STomer Tayar return status; 52437b6859fbSMintz, Yuval 5244c965db44STomer Tayar if (buf_size_in_dwords < needed_buf_size_in_dwords) 5245c965db44STomer Tayar return DBG_STATUS_DUMP_BUF_TOO_SMALL; 5246c965db44STomer Tayar 5247c965db44STomer Tayar /* GRC Dump */ 5248c965db44STomer Tayar status = qed_grc_dump(p_hwfn, p_ptt, dump_buf, true, num_dumped_dwords); 5249c965db44STomer Tayar 5250be086e7cSMintz, Yuval /* Revert GRC params to their default */ 5251be086e7cSMintz, Yuval qed_dbg_grc_set_params_default(p_hwfn); 5252be086e7cSMintz, Yuval 5253c965db44STomer Tayar return status; 5254c965db44STomer Tayar } 5255c965db44STomer Tayar 5256c965db44STomer Tayar enum dbg_status qed_dbg_idle_chk_get_dump_buf_size(struct qed_hwfn *p_hwfn, 5257c965db44STomer Tayar struct qed_ptt *p_ptt, 5258c965db44STomer Tayar u32 *buf_size) 5259c965db44STomer Tayar { 5260c965db44STomer Tayar struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 52617b6859fbSMintz, Yuval struct idle_chk_data *idle_chk; 52627b6859fbSMintz, Yuval enum dbg_status status; 5263c965db44STomer Tayar 52647b6859fbSMintz, Yuval idle_chk = &dev_data->idle_chk; 5265c965db44STomer Tayar *buf_size = 0; 52667b6859fbSMintz, Yuval 52677b6859fbSMintz, Yuval status = qed_dbg_dev_init(p_hwfn, p_ptt); 5268c965db44STomer Tayar if (status != DBG_STATUS_OK) 5269c965db44STomer Tayar return status; 52707b6859fbSMintz, Yuval 5271c965db44STomer Tayar if (!s_dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr || 5272c965db44STomer Tayar !s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_REGS].ptr || 5273c965db44STomer Tayar !s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_IMMS].ptr || 5274c965db44STomer Tayar !s_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_RULES].ptr) 5275c965db44STomer Tayar return DBG_STATUS_DBG_ARRAY_NOT_SET; 52767b6859fbSMintz, Yuval 52777b6859fbSMintz, Yuval if (!idle_chk->buf_size_set) { 52787b6859fbSMintz, Yuval idle_chk->buf_size = qed_idle_chk_dump(p_hwfn, 52797b6859fbSMintz, Yuval p_ptt, NULL, false); 52807b6859fbSMintz, Yuval idle_chk->buf_size_set = true; 5281c965db44STomer Tayar } 5282c965db44STomer Tayar 52837b6859fbSMintz, Yuval *buf_size = idle_chk->buf_size; 52847b6859fbSMintz, Yuval 5285c965db44STomer Tayar return DBG_STATUS_OK; 5286c965db44STomer Tayar } 5287c965db44STomer Tayar 5288c965db44STomer Tayar enum dbg_status qed_dbg_idle_chk_dump(struct qed_hwfn *p_hwfn, 5289c965db44STomer Tayar struct qed_ptt *p_ptt, 5290c965db44STomer Tayar u32 *dump_buf, 5291c965db44STomer Tayar u32 buf_size_in_dwords, 5292c965db44STomer Tayar u32 *num_dumped_dwords) 5293c965db44STomer Tayar { 5294c965db44STomer Tayar u32 needed_buf_size_in_dwords; 5295c965db44STomer Tayar enum dbg_status status; 5296c965db44STomer Tayar 5297c965db44STomer Tayar *num_dumped_dwords = 0; 52987b6859fbSMintz, Yuval 52997b6859fbSMintz, Yuval status = qed_dbg_idle_chk_get_dump_buf_size(p_hwfn, 53007b6859fbSMintz, Yuval p_ptt, 53017b6859fbSMintz, Yuval &needed_buf_size_in_dwords); 5302c965db44STomer Tayar if (status != DBG_STATUS_OK) 5303c965db44STomer Tayar return status; 53047b6859fbSMintz, Yuval 5305c965db44STomer Tayar if (buf_size_in_dwords < needed_buf_size_in_dwords) 5306c965db44STomer Tayar return DBG_STATUS_DUMP_BUF_TOO_SMALL; 5307c965db44STomer Tayar 5308c965db44STomer Tayar /* Update reset state */ 5309c965db44STomer Tayar qed_update_blocks_reset_state(p_hwfn, p_ptt); 5310c965db44STomer Tayar 5311c965db44STomer Tayar /* Idle Check Dump */ 5312c965db44STomer Tayar *num_dumped_dwords = qed_idle_chk_dump(p_hwfn, p_ptt, dump_buf, true); 5313be086e7cSMintz, Yuval 5314be086e7cSMintz, Yuval /* Revert GRC params to their default */ 5315be086e7cSMintz, Yuval qed_dbg_grc_set_params_default(p_hwfn); 5316be086e7cSMintz, Yuval 5317c965db44STomer Tayar return DBG_STATUS_OK; 5318c965db44STomer Tayar } 5319c965db44STomer Tayar 5320c965db44STomer Tayar enum dbg_status qed_dbg_mcp_trace_get_dump_buf_size(struct qed_hwfn *p_hwfn, 5321c965db44STomer Tayar struct qed_ptt *p_ptt, 5322c965db44STomer Tayar u32 *buf_size) 5323c965db44STomer Tayar { 5324c965db44STomer Tayar enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt); 5325c965db44STomer Tayar 5326c965db44STomer Tayar *buf_size = 0; 53277b6859fbSMintz, Yuval 5328c965db44STomer Tayar if (status != DBG_STATUS_OK) 5329c965db44STomer Tayar return status; 53307b6859fbSMintz, Yuval 5331c965db44STomer Tayar return qed_mcp_trace_dump(p_hwfn, p_ptt, NULL, false, buf_size); 5332c965db44STomer Tayar } 5333c965db44STomer Tayar 5334c965db44STomer Tayar enum dbg_status qed_dbg_mcp_trace_dump(struct qed_hwfn *p_hwfn, 5335c965db44STomer Tayar struct qed_ptt *p_ptt, 5336c965db44STomer Tayar u32 *dump_buf, 5337c965db44STomer Tayar u32 buf_size_in_dwords, 5338c965db44STomer Tayar u32 *num_dumped_dwords) 5339c965db44STomer Tayar { 5340c965db44STomer Tayar u32 needed_buf_size_in_dwords; 5341c965db44STomer Tayar enum dbg_status status; 5342c965db44STomer Tayar 5343be086e7cSMintz, Yuval status = 53447b6859fbSMintz, Yuval qed_dbg_mcp_trace_get_dump_buf_size(p_hwfn, 53457b6859fbSMintz, Yuval p_ptt, 5346c965db44STomer Tayar &needed_buf_size_in_dwords); 53477b6859fbSMintz, Yuval if (status != DBG_STATUS_OK && status != 53487b6859fbSMintz, Yuval DBG_STATUS_NVRAM_GET_IMAGE_FAILED) 5349c965db44STomer Tayar return status; 5350be086e7cSMintz, Yuval 5351c965db44STomer Tayar if (buf_size_in_dwords < needed_buf_size_in_dwords) 5352c965db44STomer Tayar return DBG_STATUS_DUMP_BUF_TOO_SMALL; 5353c965db44STomer Tayar 5354c965db44STomer Tayar /* Update reset state */ 5355c965db44STomer Tayar qed_update_blocks_reset_state(p_hwfn, p_ptt); 5356c965db44STomer Tayar 5357c965db44STomer Tayar /* Perform dump */ 5358be086e7cSMintz, Yuval status = qed_mcp_trace_dump(p_hwfn, 5359c965db44STomer Tayar p_ptt, dump_buf, true, num_dumped_dwords); 5360be086e7cSMintz, Yuval 5361be086e7cSMintz, Yuval /* Revert GRC params to their default */ 5362be086e7cSMintz, Yuval qed_dbg_grc_set_params_default(p_hwfn); 5363be086e7cSMintz, Yuval 5364be086e7cSMintz, Yuval return status; 5365c965db44STomer Tayar } 5366c965db44STomer Tayar 5367c965db44STomer Tayar enum dbg_status qed_dbg_reg_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn, 5368c965db44STomer Tayar struct qed_ptt *p_ptt, 5369c965db44STomer Tayar u32 *buf_size) 5370c965db44STomer Tayar { 5371c965db44STomer Tayar enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt); 5372c965db44STomer Tayar 5373c965db44STomer Tayar *buf_size = 0; 53747b6859fbSMintz, Yuval 5375c965db44STomer Tayar if (status != DBG_STATUS_OK) 5376c965db44STomer Tayar return status; 53777b6859fbSMintz, Yuval 5378c965db44STomer Tayar return qed_reg_fifo_dump(p_hwfn, p_ptt, NULL, false, buf_size); 5379c965db44STomer Tayar } 5380c965db44STomer Tayar 5381c965db44STomer Tayar enum dbg_status qed_dbg_reg_fifo_dump(struct qed_hwfn *p_hwfn, 5382c965db44STomer Tayar struct qed_ptt *p_ptt, 5383c965db44STomer Tayar u32 *dump_buf, 5384c965db44STomer Tayar u32 buf_size_in_dwords, 5385c965db44STomer Tayar u32 *num_dumped_dwords) 5386c965db44STomer Tayar { 5387c965db44STomer Tayar u32 needed_buf_size_in_dwords; 5388c965db44STomer Tayar enum dbg_status status; 5389c965db44STomer Tayar 5390c965db44STomer Tayar *num_dumped_dwords = 0; 53917b6859fbSMintz, Yuval 53927b6859fbSMintz, Yuval status = qed_dbg_reg_fifo_get_dump_buf_size(p_hwfn, 53937b6859fbSMintz, Yuval p_ptt, 53947b6859fbSMintz, Yuval &needed_buf_size_in_dwords); 5395c965db44STomer Tayar if (status != DBG_STATUS_OK) 5396c965db44STomer Tayar return status; 53977b6859fbSMintz, Yuval 5398c965db44STomer Tayar if (buf_size_in_dwords < needed_buf_size_in_dwords) 5399c965db44STomer Tayar return DBG_STATUS_DUMP_BUF_TOO_SMALL; 5400c965db44STomer Tayar 5401c965db44STomer Tayar /* Update reset state */ 5402c965db44STomer Tayar qed_update_blocks_reset_state(p_hwfn, p_ptt); 5403be086e7cSMintz, Yuval 5404be086e7cSMintz, Yuval status = qed_reg_fifo_dump(p_hwfn, 5405c965db44STomer Tayar p_ptt, dump_buf, true, num_dumped_dwords); 5406be086e7cSMintz, Yuval 5407be086e7cSMintz, Yuval /* Revert GRC params to their default */ 5408be086e7cSMintz, Yuval qed_dbg_grc_set_params_default(p_hwfn); 5409be086e7cSMintz, Yuval 5410be086e7cSMintz, Yuval return status; 5411c965db44STomer Tayar } 5412c965db44STomer Tayar 5413c965db44STomer Tayar enum dbg_status qed_dbg_igu_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn, 5414c965db44STomer Tayar struct qed_ptt *p_ptt, 5415c965db44STomer Tayar u32 *buf_size) 5416c965db44STomer Tayar { 5417c965db44STomer Tayar enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt); 5418c965db44STomer Tayar 5419c965db44STomer Tayar *buf_size = 0; 54207b6859fbSMintz, Yuval 5421c965db44STomer Tayar if (status != DBG_STATUS_OK) 5422c965db44STomer Tayar return status; 54237b6859fbSMintz, Yuval 5424c965db44STomer Tayar return qed_igu_fifo_dump(p_hwfn, p_ptt, NULL, false, buf_size); 5425c965db44STomer Tayar } 5426c965db44STomer Tayar 5427c965db44STomer Tayar enum dbg_status qed_dbg_igu_fifo_dump(struct qed_hwfn *p_hwfn, 5428c965db44STomer Tayar struct qed_ptt *p_ptt, 5429c965db44STomer Tayar u32 *dump_buf, 5430c965db44STomer Tayar u32 buf_size_in_dwords, 5431c965db44STomer Tayar u32 *num_dumped_dwords) 5432c965db44STomer Tayar { 5433c965db44STomer Tayar u32 needed_buf_size_in_dwords; 5434c965db44STomer Tayar enum dbg_status status; 5435c965db44STomer Tayar 5436c965db44STomer Tayar *num_dumped_dwords = 0; 54377b6859fbSMintz, Yuval 54387b6859fbSMintz, Yuval status = qed_dbg_igu_fifo_get_dump_buf_size(p_hwfn, 54397b6859fbSMintz, Yuval p_ptt, 54407b6859fbSMintz, Yuval &needed_buf_size_in_dwords); 5441c965db44STomer Tayar if (status != DBG_STATUS_OK) 5442c965db44STomer Tayar return status; 54437b6859fbSMintz, Yuval 5444c965db44STomer Tayar if (buf_size_in_dwords < needed_buf_size_in_dwords) 5445c965db44STomer Tayar return DBG_STATUS_DUMP_BUF_TOO_SMALL; 5446c965db44STomer Tayar 5447c965db44STomer Tayar /* Update reset state */ 5448c965db44STomer Tayar qed_update_blocks_reset_state(p_hwfn, p_ptt); 5449be086e7cSMintz, Yuval 5450be086e7cSMintz, Yuval status = qed_igu_fifo_dump(p_hwfn, 5451c965db44STomer Tayar p_ptt, dump_buf, true, num_dumped_dwords); 5452be086e7cSMintz, Yuval /* Revert GRC params to their default */ 5453be086e7cSMintz, Yuval qed_dbg_grc_set_params_default(p_hwfn); 5454be086e7cSMintz, Yuval 5455be086e7cSMintz, Yuval return status; 5456c965db44STomer Tayar } 5457c965db44STomer Tayar 5458c965db44STomer Tayar enum dbg_status 5459c965db44STomer Tayar qed_dbg_protection_override_get_dump_buf_size(struct qed_hwfn *p_hwfn, 5460c965db44STomer Tayar struct qed_ptt *p_ptt, 5461c965db44STomer Tayar u32 *buf_size) 5462c965db44STomer Tayar { 5463c965db44STomer Tayar enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt); 5464c965db44STomer Tayar 5465c965db44STomer Tayar *buf_size = 0; 54667b6859fbSMintz, Yuval 5467c965db44STomer Tayar if (status != DBG_STATUS_OK) 5468c965db44STomer Tayar return status; 54697b6859fbSMintz, Yuval 5470c965db44STomer Tayar return qed_protection_override_dump(p_hwfn, 5471c965db44STomer Tayar p_ptt, NULL, false, buf_size); 5472c965db44STomer Tayar } 5473c965db44STomer Tayar 5474c965db44STomer Tayar enum dbg_status qed_dbg_protection_override_dump(struct qed_hwfn *p_hwfn, 5475c965db44STomer Tayar struct qed_ptt *p_ptt, 5476c965db44STomer Tayar u32 *dump_buf, 5477c965db44STomer Tayar u32 buf_size_in_dwords, 5478c965db44STomer Tayar u32 *num_dumped_dwords) 5479c965db44STomer Tayar { 54807b6859fbSMintz, Yuval u32 needed_buf_size_in_dwords, *p_size = &needed_buf_size_in_dwords; 5481c965db44STomer Tayar enum dbg_status status; 5482c965db44STomer Tayar 5483c965db44STomer Tayar *num_dumped_dwords = 0; 54847b6859fbSMintz, Yuval 54857b6859fbSMintz, Yuval status = 54867b6859fbSMintz, Yuval qed_dbg_protection_override_get_dump_buf_size(p_hwfn, 54877b6859fbSMintz, Yuval p_ptt, 54887b6859fbSMintz, Yuval p_size); 5489c965db44STomer Tayar if (status != DBG_STATUS_OK) 5490c965db44STomer Tayar return status; 54917b6859fbSMintz, Yuval 5492c965db44STomer Tayar if (buf_size_in_dwords < needed_buf_size_in_dwords) 5493c965db44STomer Tayar return DBG_STATUS_DUMP_BUF_TOO_SMALL; 5494c965db44STomer Tayar 5495c965db44STomer Tayar /* Update reset state */ 5496c965db44STomer Tayar qed_update_blocks_reset_state(p_hwfn, p_ptt); 5497be086e7cSMintz, Yuval 5498be086e7cSMintz, Yuval status = qed_protection_override_dump(p_hwfn, 5499c965db44STomer Tayar p_ptt, 5500be086e7cSMintz, Yuval dump_buf, 5501be086e7cSMintz, Yuval true, num_dumped_dwords); 5502be086e7cSMintz, Yuval 5503be086e7cSMintz, Yuval /* Revert GRC params to their default */ 5504be086e7cSMintz, Yuval qed_dbg_grc_set_params_default(p_hwfn); 5505be086e7cSMintz, Yuval 5506be086e7cSMintz, Yuval return status; 5507c965db44STomer Tayar } 5508c965db44STomer Tayar 5509c965db44STomer Tayar enum dbg_status qed_dbg_fw_asserts_get_dump_buf_size(struct qed_hwfn *p_hwfn, 5510c965db44STomer Tayar struct qed_ptt *p_ptt, 5511c965db44STomer Tayar u32 *buf_size) 5512c965db44STomer Tayar { 5513c965db44STomer Tayar enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt); 5514c965db44STomer Tayar 5515c965db44STomer Tayar *buf_size = 0; 55167b6859fbSMintz, Yuval 5517c965db44STomer Tayar if (status != DBG_STATUS_OK) 5518c965db44STomer Tayar return status; 5519c965db44STomer Tayar 5520c965db44STomer Tayar /* Update reset state */ 5521c965db44STomer Tayar qed_update_blocks_reset_state(p_hwfn, p_ptt); 55227b6859fbSMintz, Yuval 5523c965db44STomer Tayar *buf_size = qed_fw_asserts_dump(p_hwfn, p_ptt, NULL, false); 55247b6859fbSMintz, Yuval 5525c965db44STomer Tayar return DBG_STATUS_OK; 5526c965db44STomer Tayar } 5527c965db44STomer Tayar 5528c965db44STomer Tayar enum dbg_status qed_dbg_fw_asserts_dump(struct qed_hwfn *p_hwfn, 5529c965db44STomer Tayar struct qed_ptt *p_ptt, 5530c965db44STomer Tayar u32 *dump_buf, 5531c965db44STomer Tayar u32 buf_size_in_dwords, 5532c965db44STomer Tayar u32 *num_dumped_dwords) 5533c965db44STomer Tayar { 55347b6859fbSMintz, Yuval u32 needed_buf_size_in_dwords, *p_size = &needed_buf_size_in_dwords; 5535c965db44STomer Tayar enum dbg_status status; 5536c965db44STomer Tayar 5537c965db44STomer Tayar *num_dumped_dwords = 0; 55387b6859fbSMintz, Yuval 55397b6859fbSMintz, Yuval status = 55407b6859fbSMintz, Yuval qed_dbg_fw_asserts_get_dump_buf_size(p_hwfn, 55417b6859fbSMintz, Yuval p_ptt, 55427b6859fbSMintz, Yuval p_size); 5543c965db44STomer Tayar if (status != DBG_STATUS_OK) 5544c965db44STomer Tayar return status; 55457b6859fbSMintz, Yuval 5546c965db44STomer Tayar if (buf_size_in_dwords < needed_buf_size_in_dwords) 5547c965db44STomer Tayar return DBG_STATUS_DUMP_BUF_TOO_SMALL; 5548c965db44STomer Tayar 5549c965db44STomer Tayar *num_dumped_dwords = qed_fw_asserts_dump(p_hwfn, p_ptt, dump_buf, true); 55507b6859fbSMintz, Yuval 55517b6859fbSMintz, Yuval /* Revert GRC params to their default */ 55527b6859fbSMintz, Yuval qed_dbg_grc_set_params_default(p_hwfn); 55537b6859fbSMintz, Yuval 5554c965db44STomer Tayar return DBG_STATUS_OK; 5555c965db44STomer Tayar } 5556c965db44STomer Tayar 55570ebbd1c8SMintz, Yuval enum dbg_status qed_dbg_read_attn(struct qed_hwfn *p_hwfn, 55580ebbd1c8SMintz, Yuval struct qed_ptt *p_ptt, 55590ebbd1c8SMintz, Yuval enum block_id block_id, 55600ebbd1c8SMintz, Yuval enum dbg_attn_type attn_type, 55610ebbd1c8SMintz, Yuval bool clear_status, 55620ebbd1c8SMintz, Yuval struct dbg_attn_block_result *results) 55630ebbd1c8SMintz, Yuval { 55640ebbd1c8SMintz, Yuval enum dbg_status status = qed_dbg_dev_init(p_hwfn, p_ptt); 55650ebbd1c8SMintz, Yuval u8 reg_idx, num_attn_regs, num_result_regs = 0; 55660ebbd1c8SMintz, Yuval const struct dbg_attn_reg *attn_reg_arr; 55670ebbd1c8SMintz, Yuval 55680ebbd1c8SMintz, Yuval if (status != DBG_STATUS_OK) 55690ebbd1c8SMintz, Yuval return status; 55700ebbd1c8SMintz, Yuval 55710ebbd1c8SMintz, Yuval if (!s_dbg_arrays[BIN_BUF_DBG_MODE_TREE].ptr || 55720ebbd1c8SMintz, Yuval !s_dbg_arrays[BIN_BUF_DBG_ATTN_BLOCKS].ptr || 55730ebbd1c8SMintz, Yuval !s_dbg_arrays[BIN_BUF_DBG_ATTN_REGS].ptr) 55740ebbd1c8SMintz, Yuval return DBG_STATUS_DBG_ARRAY_NOT_SET; 55750ebbd1c8SMintz, Yuval 55760ebbd1c8SMintz, Yuval attn_reg_arr = qed_get_block_attn_regs(block_id, 55770ebbd1c8SMintz, Yuval attn_type, &num_attn_regs); 55780ebbd1c8SMintz, Yuval 55790ebbd1c8SMintz, Yuval for (reg_idx = 0; reg_idx < num_attn_regs; reg_idx++) { 55800ebbd1c8SMintz, Yuval const struct dbg_attn_reg *reg_data = &attn_reg_arr[reg_idx]; 55810ebbd1c8SMintz, Yuval struct dbg_attn_reg_result *reg_result; 55820ebbd1c8SMintz, Yuval u32 sts_addr, sts_val; 55830ebbd1c8SMintz, Yuval u16 modes_buf_offset; 55840ebbd1c8SMintz, Yuval bool eval_mode; 55850ebbd1c8SMintz, Yuval 55860ebbd1c8SMintz, Yuval /* Check mode */ 55870ebbd1c8SMintz, Yuval eval_mode = GET_FIELD(reg_data->mode.data, 55880ebbd1c8SMintz, Yuval DBG_MODE_HDR_EVAL_MODE) > 0; 55890ebbd1c8SMintz, Yuval modes_buf_offset = GET_FIELD(reg_data->mode.data, 55900ebbd1c8SMintz, Yuval DBG_MODE_HDR_MODES_BUF_OFFSET); 55910ebbd1c8SMintz, Yuval if (eval_mode && !qed_is_mode_match(p_hwfn, &modes_buf_offset)) 55920ebbd1c8SMintz, Yuval continue; 55930ebbd1c8SMintz, Yuval 55940ebbd1c8SMintz, Yuval /* Mode match - read attention status register */ 55950ebbd1c8SMintz, Yuval sts_addr = DWORDS_TO_BYTES(clear_status ? 55960ebbd1c8SMintz, Yuval reg_data->sts_clr_address : 55970ebbd1c8SMintz, Yuval GET_FIELD(reg_data->data, 55980ebbd1c8SMintz, Yuval DBG_ATTN_REG_STS_ADDRESS)); 55990ebbd1c8SMintz, Yuval sts_val = qed_rd(p_hwfn, p_ptt, sts_addr); 56000ebbd1c8SMintz, Yuval if (!sts_val) 56010ebbd1c8SMintz, Yuval continue; 56020ebbd1c8SMintz, Yuval 56030ebbd1c8SMintz, Yuval /* Non-zero attention status - add to results */ 56040ebbd1c8SMintz, Yuval reg_result = &results->reg_results[num_result_regs]; 56050ebbd1c8SMintz, Yuval SET_FIELD(reg_result->data, 56060ebbd1c8SMintz, Yuval DBG_ATTN_REG_RESULT_STS_ADDRESS, sts_addr); 56070ebbd1c8SMintz, Yuval SET_FIELD(reg_result->data, 56080ebbd1c8SMintz, Yuval DBG_ATTN_REG_RESULT_NUM_REG_ATTN, 56090ebbd1c8SMintz, Yuval GET_FIELD(reg_data->data, DBG_ATTN_REG_NUM_REG_ATTN)); 56100ebbd1c8SMintz, Yuval reg_result->block_attn_offset = reg_data->block_attn_offset; 56110ebbd1c8SMintz, Yuval reg_result->sts_val = sts_val; 56120ebbd1c8SMintz, Yuval reg_result->mask_val = qed_rd(p_hwfn, 56130ebbd1c8SMintz, Yuval p_ptt, 56140ebbd1c8SMintz, Yuval DWORDS_TO_BYTES 56150ebbd1c8SMintz, Yuval (reg_data->mask_address)); 56160ebbd1c8SMintz, Yuval num_result_regs++; 56170ebbd1c8SMintz, Yuval } 56180ebbd1c8SMintz, Yuval 56190ebbd1c8SMintz, Yuval results->block_id = (u8)block_id; 56200ebbd1c8SMintz, Yuval results->names_offset = 56210ebbd1c8SMintz, Yuval qed_get_block_attn_data(block_id, attn_type)->names_offset; 56220ebbd1c8SMintz, Yuval SET_FIELD(results->data, DBG_ATTN_BLOCK_RESULT_ATTN_TYPE, attn_type); 56230ebbd1c8SMintz, Yuval SET_FIELD(results->data, 56240ebbd1c8SMintz, Yuval DBG_ATTN_BLOCK_RESULT_NUM_REGS, num_result_regs); 56250ebbd1c8SMintz, Yuval 56260ebbd1c8SMintz, Yuval return DBG_STATUS_OK; 56270ebbd1c8SMintz, Yuval } 56280ebbd1c8SMintz, Yuval 5629c965db44STomer Tayar /******************************* Data Types **********************************/ 5630c965db44STomer Tayar 56310ebbd1c8SMintz, Yuval struct block_info { 56320ebbd1c8SMintz, Yuval const char *name; 56330ebbd1c8SMintz, Yuval enum block_id id; 56340ebbd1c8SMintz, Yuval }; 56350ebbd1c8SMintz, Yuval 56367b6859fbSMintz, Yuval /* REG fifo element */ 5637c965db44STomer Tayar struct reg_fifo_element { 5638c965db44STomer Tayar u64 data; 5639c965db44STomer Tayar #define REG_FIFO_ELEMENT_ADDRESS_SHIFT 0 5640c965db44STomer Tayar #define REG_FIFO_ELEMENT_ADDRESS_MASK 0x7fffff 5641c965db44STomer Tayar #define REG_FIFO_ELEMENT_ACCESS_SHIFT 23 5642c965db44STomer Tayar #define REG_FIFO_ELEMENT_ACCESS_MASK 0x1 5643c965db44STomer Tayar #define REG_FIFO_ELEMENT_PF_SHIFT 24 5644c965db44STomer Tayar #define REG_FIFO_ELEMENT_PF_MASK 0xf 5645c965db44STomer Tayar #define REG_FIFO_ELEMENT_VF_SHIFT 28 5646c965db44STomer Tayar #define REG_FIFO_ELEMENT_VF_MASK 0xff 5647c965db44STomer Tayar #define REG_FIFO_ELEMENT_PORT_SHIFT 36 5648c965db44STomer Tayar #define REG_FIFO_ELEMENT_PORT_MASK 0x3 5649c965db44STomer Tayar #define REG_FIFO_ELEMENT_PRIVILEGE_SHIFT 38 5650c965db44STomer Tayar #define REG_FIFO_ELEMENT_PRIVILEGE_MASK 0x3 5651c965db44STomer Tayar #define REG_FIFO_ELEMENT_PROTECTION_SHIFT 40 5652c965db44STomer Tayar #define REG_FIFO_ELEMENT_PROTECTION_MASK 0x7 5653c965db44STomer Tayar #define REG_FIFO_ELEMENT_MASTER_SHIFT 43 5654c965db44STomer Tayar #define REG_FIFO_ELEMENT_MASTER_MASK 0xf 5655c965db44STomer Tayar #define REG_FIFO_ELEMENT_ERROR_SHIFT 47 5656c965db44STomer Tayar #define REG_FIFO_ELEMENT_ERROR_MASK 0x1f 5657c965db44STomer Tayar }; 5658c965db44STomer Tayar 5659c965db44STomer Tayar /* IGU fifo element */ 5660c965db44STomer Tayar struct igu_fifo_element { 5661c965db44STomer Tayar u32 dword0; 5662c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_FID_SHIFT 0 5663c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_FID_MASK 0xff 5664c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_IS_PF_SHIFT 8 5665c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_IS_PF_MASK 0x1 5666c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_SOURCE_SHIFT 9 5667c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_SOURCE_MASK 0xf 5668c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_ERR_TYPE_SHIFT 13 5669c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_ERR_TYPE_MASK 0xf 5670c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_CMD_ADDR_SHIFT 17 5671c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD0_CMD_ADDR_MASK 0x7fff 5672c965db44STomer Tayar u32 dword1; 5673c965db44STomer Tayar u32 dword2; 5674c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD12_IS_WR_CMD_SHIFT 0 5675c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD12_IS_WR_CMD_MASK 0x1 5676c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD12_WR_DATA_SHIFT 1 5677c965db44STomer Tayar #define IGU_FIFO_ELEMENT_DWORD12_WR_DATA_MASK 0xffffffff 5678c965db44STomer Tayar u32 reserved; 5679c965db44STomer Tayar }; 5680c965db44STomer Tayar 5681c965db44STomer Tayar struct igu_fifo_wr_data { 5682c965db44STomer Tayar u32 data; 5683c965db44STomer Tayar #define IGU_FIFO_WR_DATA_PROD_CONS_SHIFT 0 5684c965db44STomer Tayar #define IGU_FIFO_WR_DATA_PROD_CONS_MASK 0xffffff 5685c965db44STomer Tayar #define IGU_FIFO_WR_DATA_UPDATE_FLAG_SHIFT 24 5686c965db44STomer Tayar #define IGU_FIFO_WR_DATA_UPDATE_FLAG_MASK 0x1 5687c965db44STomer Tayar #define IGU_FIFO_WR_DATA_EN_DIS_INT_FOR_SB_SHIFT 25 5688c965db44STomer Tayar #define IGU_FIFO_WR_DATA_EN_DIS_INT_FOR_SB_MASK 0x3 5689c965db44STomer Tayar #define IGU_FIFO_WR_DATA_SEGMENT_SHIFT 27 5690c965db44STomer Tayar #define IGU_FIFO_WR_DATA_SEGMENT_MASK 0x1 5691c965db44STomer Tayar #define IGU_FIFO_WR_DATA_TIMER_MASK_SHIFT 28 5692c965db44STomer Tayar #define IGU_FIFO_WR_DATA_TIMER_MASK_MASK 0x1 5693c965db44STomer Tayar #define IGU_FIFO_WR_DATA_CMD_TYPE_SHIFT 31 5694c965db44STomer Tayar #define IGU_FIFO_WR_DATA_CMD_TYPE_MASK 0x1 5695c965db44STomer Tayar }; 5696c965db44STomer Tayar 5697c965db44STomer Tayar struct igu_fifo_cleanup_wr_data { 5698c965db44STomer Tayar u32 data; 5699c965db44STomer Tayar #define IGU_FIFO_CLEANUP_WR_DATA_RESERVED_SHIFT 0 5700c965db44STomer Tayar #define IGU_FIFO_CLEANUP_WR_DATA_RESERVED_MASK 0x7ffffff 5701c965db44STomer Tayar #define IGU_FIFO_CLEANUP_WR_DATA_CLEANUP_VAL_SHIFT 27 5702c965db44STomer Tayar #define IGU_FIFO_CLEANUP_WR_DATA_CLEANUP_VAL_MASK 0x1 5703c965db44STomer Tayar #define IGU_FIFO_CLEANUP_WR_DATA_CLEANUP_TYPE_SHIFT 28 5704c965db44STomer Tayar #define IGU_FIFO_CLEANUP_WR_DATA_CLEANUP_TYPE_MASK 0x7 5705c965db44STomer Tayar #define IGU_FIFO_CLEANUP_WR_DATA_CMD_TYPE_SHIFT 31 5706c965db44STomer Tayar #define IGU_FIFO_CLEANUP_WR_DATA_CMD_TYPE_MASK 0x1 5707c965db44STomer Tayar }; 5708c965db44STomer Tayar 5709c965db44STomer Tayar /* Protection override element */ 5710c965db44STomer Tayar struct protection_override_element { 5711c965db44STomer Tayar u64 data; 5712c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_ADDRESS_SHIFT 0 5713c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_ADDRESS_MASK 0x7fffff 5714c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_WINDOW_SIZE_SHIFT 23 5715c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_WINDOW_SIZE_MASK 0xffffff 5716c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_READ_SHIFT 47 5717c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_READ_MASK 0x1 5718c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_WRITE_SHIFT 48 5719c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_WRITE_MASK 0x1 5720c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_READ_PROTECTION_SHIFT 49 5721c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_READ_PROTECTION_MASK 0x7 5722c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_WRITE_PROTECTION_SHIFT 52 5723c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_WRITE_PROTECTION_MASK 0x7 5724c965db44STomer Tayar }; 5725c965db44STomer Tayar 5726c965db44STomer Tayar enum igu_fifo_sources { 5727c965db44STomer Tayar IGU_SRC_PXP0, 5728c965db44STomer Tayar IGU_SRC_PXP1, 5729c965db44STomer Tayar IGU_SRC_PXP2, 5730c965db44STomer Tayar IGU_SRC_PXP3, 5731c965db44STomer Tayar IGU_SRC_PXP4, 5732c965db44STomer Tayar IGU_SRC_PXP5, 5733c965db44STomer Tayar IGU_SRC_PXP6, 5734c965db44STomer Tayar IGU_SRC_PXP7, 5735c965db44STomer Tayar IGU_SRC_CAU, 5736c965db44STomer Tayar IGU_SRC_ATTN, 5737c965db44STomer Tayar IGU_SRC_GRC 5738c965db44STomer Tayar }; 5739c965db44STomer Tayar 5740c965db44STomer Tayar enum igu_fifo_addr_types { 5741c965db44STomer Tayar IGU_ADDR_TYPE_MSIX_MEM, 5742c965db44STomer Tayar IGU_ADDR_TYPE_WRITE_PBA, 5743c965db44STomer Tayar IGU_ADDR_TYPE_WRITE_INT_ACK, 5744c965db44STomer Tayar IGU_ADDR_TYPE_WRITE_ATTN_BITS, 5745c965db44STomer Tayar IGU_ADDR_TYPE_READ_INT, 5746c965db44STomer Tayar IGU_ADDR_TYPE_WRITE_PROD_UPDATE, 5747c965db44STomer Tayar IGU_ADDR_TYPE_RESERVED 5748c965db44STomer Tayar }; 5749c965db44STomer Tayar 5750c965db44STomer Tayar struct igu_fifo_addr_data { 5751c965db44STomer Tayar u16 start_addr; 5752c965db44STomer Tayar u16 end_addr; 5753c965db44STomer Tayar char *desc; 5754c965db44STomer Tayar char *vf_desc; 5755c965db44STomer Tayar enum igu_fifo_addr_types type; 5756c965db44STomer Tayar }; 5757c965db44STomer Tayar 5758a3f72307SDenis Bolotin struct mcp_trace_meta { 5759a3f72307SDenis Bolotin u32 modules_num; 5760a3f72307SDenis Bolotin char **modules; 5761a3f72307SDenis Bolotin u32 formats_num; 5762a3f72307SDenis Bolotin struct mcp_trace_format *formats; 5763a3f72307SDenis Bolotin bool is_allocated; 5764a3f72307SDenis Bolotin }; 5765a3f72307SDenis Bolotin 5766a3f72307SDenis Bolotin /* Debug Tools user data */ 5767a3f72307SDenis Bolotin struct dbg_tools_user_data { 5768a3f72307SDenis Bolotin struct mcp_trace_meta mcp_trace_meta; 5769a3f72307SDenis Bolotin const u32 *mcp_trace_user_meta_buf; 5770a3f72307SDenis Bolotin }; 5771a3f72307SDenis Bolotin 5772c965db44STomer Tayar /******************************** Constants **********************************/ 5773c965db44STomer Tayar 5774c965db44STomer Tayar #define MAX_MSG_LEN 1024 57757b6859fbSMintz, Yuval 5776c965db44STomer Tayar #define MCP_TRACE_MAX_MODULE_LEN 8 5777c965db44STomer Tayar #define MCP_TRACE_FORMAT_MAX_PARAMS 3 5778c965db44STomer Tayar #define MCP_TRACE_FORMAT_PARAM_WIDTH \ 5779c965db44STomer Tayar (MCP_TRACE_FORMAT_P2_SIZE_SHIFT - MCP_TRACE_FORMAT_P1_SIZE_SHIFT) 57807b6859fbSMintz, Yuval 5781c965db44STomer Tayar #define REG_FIFO_ELEMENT_ADDR_FACTOR 4 5782c965db44STomer Tayar #define REG_FIFO_ELEMENT_IS_PF_VF_VAL 127 57837b6859fbSMintz, Yuval 5784c965db44STomer Tayar #define PROTECTION_OVERRIDE_ELEMENT_ADDR_FACTOR 4 5785c965db44STomer Tayar 5786c965db44STomer Tayar /***************************** Constant Arrays *******************************/ 5787c965db44STomer Tayar 57887b6859fbSMintz, Yuval struct user_dbg_array { 57897b6859fbSMintz, Yuval const u32 *ptr; 57907b6859fbSMintz, Yuval u32 size_in_dwords; 57917b6859fbSMintz, Yuval }; 57927b6859fbSMintz, Yuval 57937b6859fbSMintz, Yuval /* Debug arrays */ 57947b6859fbSMintz, Yuval static struct user_dbg_array 57957b6859fbSMintz, Yuval s_user_dbg_arrays[MAX_BIN_DBG_BUFFER_TYPE] = { {NULL} }; 57967b6859fbSMintz, Yuval 57970ebbd1c8SMintz, Yuval /* Block names array */ 57980ebbd1c8SMintz, Yuval static struct block_info s_block_info_arr[] = { 57990ebbd1c8SMintz, Yuval {"grc", BLOCK_GRC}, 58000ebbd1c8SMintz, Yuval {"miscs", BLOCK_MISCS}, 58010ebbd1c8SMintz, Yuval {"misc", BLOCK_MISC}, 58020ebbd1c8SMintz, Yuval {"dbu", BLOCK_DBU}, 58030ebbd1c8SMintz, Yuval {"pglue_b", BLOCK_PGLUE_B}, 58040ebbd1c8SMintz, Yuval {"cnig", BLOCK_CNIG}, 58050ebbd1c8SMintz, Yuval {"cpmu", BLOCK_CPMU}, 58060ebbd1c8SMintz, Yuval {"ncsi", BLOCK_NCSI}, 58070ebbd1c8SMintz, Yuval {"opte", BLOCK_OPTE}, 58080ebbd1c8SMintz, Yuval {"bmb", BLOCK_BMB}, 58090ebbd1c8SMintz, Yuval {"pcie", BLOCK_PCIE}, 58100ebbd1c8SMintz, Yuval {"mcp", BLOCK_MCP}, 58110ebbd1c8SMintz, Yuval {"mcp2", BLOCK_MCP2}, 58120ebbd1c8SMintz, Yuval {"pswhst", BLOCK_PSWHST}, 58130ebbd1c8SMintz, Yuval {"pswhst2", BLOCK_PSWHST2}, 58140ebbd1c8SMintz, Yuval {"pswrd", BLOCK_PSWRD}, 58150ebbd1c8SMintz, Yuval {"pswrd2", BLOCK_PSWRD2}, 58160ebbd1c8SMintz, Yuval {"pswwr", BLOCK_PSWWR}, 58170ebbd1c8SMintz, Yuval {"pswwr2", BLOCK_PSWWR2}, 58180ebbd1c8SMintz, Yuval {"pswrq", BLOCK_PSWRQ}, 58190ebbd1c8SMintz, Yuval {"pswrq2", BLOCK_PSWRQ2}, 58200ebbd1c8SMintz, Yuval {"pglcs", BLOCK_PGLCS}, 58210ebbd1c8SMintz, Yuval {"ptu", BLOCK_PTU}, 58220ebbd1c8SMintz, Yuval {"dmae", BLOCK_DMAE}, 58230ebbd1c8SMintz, Yuval {"tcm", BLOCK_TCM}, 58240ebbd1c8SMintz, Yuval {"mcm", BLOCK_MCM}, 58250ebbd1c8SMintz, Yuval {"ucm", BLOCK_UCM}, 58260ebbd1c8SMintz, Yuval {"xcm", BLOCK_XCM}, 58270ebbd1c8SMintz, Yuval {"ycm", BLOCK_YCM}, 58280ebbd1c8SMintz, Yuval {"pcm", BLOCK_PCM}, 58290ebbd1c8SMintz, Yuval {"qm", BLOCK_QM}, 58300ebbd1c8SMintz, Yuval {"tm", BLOCK_TM}, 58310ebbd1c8SMintz, Yuval {"dorq", BLOCK_DORQ}, 58320ebbd1c8SMintz, Yuval {"brb", BLOCK_BRB}, 58330ebbd1c8SMintz, Yuval {"src", BLOCK_SRC}, 58340ebbd1c8SMintz, Yuval {"prs", BLOCK_PRS}, 58350ebbd1c8SMintz, Yuval {"tsdm", BLOCK_TSDM}, 58360ebbd1c8SMintz, Yuval {"msdm", BLOCK_MSDM}, 58370ebbd1c8SMintz, Yuval {"usdm", BLOCK_USDM}, 58380ebbd1c8SMintz, Yuval {"xsdm", BLOCK_XSDM}, 58390ebbd1c8SMintz, Yuval {"ysdm", BLOCK_YSDM}, 58400ebbd1c8SMintz, Yuval {"psdm", BLOCK_PSDM}, 58410ebbd1c8SMintz, Yuval {"tsem", BLOCK_TSEM}, 58420ebbd1c8SMintz, Yuval {"msem", BLOCK_MSEM}, 58430ebbd1c8SMintz, Yuval {"usem", BLOCK_USEM}, 58440ebbd1c8SMintz, Yuval {"xsem", BLOCK_XSEM}, 58450ebbd1c8SMintz, Yuval {"ysem", BLOCK_YSEM}, 58460ebbd1c8SMintz, Yuval {"psem", BLOCK_PSEM}, 58470ebbd1c8SMintz, Yuval {"rss", BLOCK_RSS}, 58480ebbd1c8SMintz, Yuval {"tmld", BLOCK_TMLD}, 58490ebbd1c8SMintz, Yuval {"muld", BLOCK_MULD}, 58500ebbd1c8SMintz, Yuval {"yuld", BLOCK_YULD}, 58510ebbd1c8SMintz, Yuval {"xyld", BLOCK_XYLD}, 58520ebbd1c8SMintz, Yuval {"ptld", BLOCK_PTLD}, 58530ebbd1c8SMintz, Yuval {"ypld", BLOCK_YPLD}, 58540ebbd1c8SMintz, Yuval {"prm", BLOCK_PRM}, 58550ebbd1c8SMintz, Yuval {"pbf_pb1", BLOCK_PBF_PB1}, 58560ebbd1c8SMintz, Yuval {"pbf_pb2", BLOCK_PBF_PB2}, 58570ebbd1c8SMintz, Yuval {"rpb", BLOCK_RPB}, 58580ebbd1c8SMintz, Yuval {"btb", BLOCK_BTB}, 58590ebbd1c8SMintz, Yuval {"pbf", BLOCK_PBF}, 58600ebbd1c8SMintz, Yuval {"rdif", BLOCK_RDIF}, 58610ebbd1c8SMintz, Yuval {"tdif", BLOCK_TDIF}, 58620ebbd1c8SMintz, Yuval {"cdu", BLOCK_CDU}, 58630ebbd1c8SMintz, Yuval {"ccfc", BLOCK_CCFC}, 58640ebbd1c8SMintz, Yuval {"tcfc", BLOCK_TCFC}, 58650ebbd1c8SMintz, Yuval {"igu", BLOCK_IGU}, 58660ebbd1c8SMintz, Yuval {"cau", BLOCK_CAU}, 58670ebbd1c8SMintz, Yuval {"rgfs", BLOCK_RGFS}, 58680ebbd1c8SMintz, Yuval {"rgsrc", BLOCK_RGSRC}, 58690ebbd1c8SMintz, Yuval {"tgfs", BLOCK_TGFS}, 58700ebbd1c8SMintz, Yuval {"tgsrc", BLOCK_TGSRC}, 58710ebbd1c8SMintz, Yuval {"umac", BLOCK_UMAC}, 58720ebbd1c8SMintz, Yuval {"xmac", BLOCK_XMAC}, 58730ebbd1c8SMintz, Yuval {"dbg", BLOCK_DBG}, 58740ebbd1c8SMintz, Yuval {"nig", BLOCK_NIG}, 58750ebbd1c8SMintz, Yuval {"wol", BLOCK_WOL}, 58760ebbd1c8SMintz, Yuval {"bmbn", BLOCK_BMBN}, 58770ebbd1c8SMintz, Yuval {"ipc", BLOCK_IPC}, 58780ebbd1c8SMintz, Yuval {"nwm", BLOCK_NWM}, 58790ebbd1c8SMintz, Yuval {"nws", BLOCK_NWS}, 58800ebbd1c8SMintz, Yuval {"ms", BLOCK_MS}, 58810ebbd1c8SMintz, Yuval {"phy_pcie", BLOCK_PHY_PCIE}, 58820ebbd1c8SMintz, Yuval {"led", BLOCK_LED}, 58830ebbd1c8SMintz, Yuval {"avs_wrap", BLOCK_AVS_WRAP}, 5884da090917STomer Tayar {"pxpreqbus", BLOCK_PXPREQBUS}, 58850ebbd1c8SMintz, Yuval {"misc_aeu", BLOCK_MISC_AEU}, 58860ebbd1c8SMintz, Yuval {"bar0_map", BLOCK_BAR0_MAP} 58870ebbd1c8SMintz, Yuval }; 58880ebbd1c8SMintz, Yuval 5889c965db44STomer Tayar /* Status string array */ 5890c965db44STomer Tayar static const char * const s_status_str[] = { 58917b6859fbSMintz, Yuval /* DBG_STATUS_OK */ 5892c965db44STomer Tayar "Operation completed successfully", 58937b6859fbSMintz, Yuval 58947b6859fbSMintz, Yuval /* DBG_STATUS_APP_VERSION_NOT_SET */ 5895c965db44STomer Tayar "Debug application version wasn't set", 58967b6859fbSMintz, Yuval 58977b6859fbSMintz, Yuval /* DBG_STATUS_UNSUPPORTED_APP_VERSION */ 5898c965db44STomer Tayar "Unsupported debug application version", 58997b6859fbSMintz, Yuval 59007b6859fbSMintz, Yuval /* DBG_STATUS_DBG_BLOCK_NOT_RESET */ 5901c965db44STomer Tayar "The debug block wasn't reset since the last recording", 59027b6859fbSMintz, Yuval 59037b6859fbSMintz, Yuval /* DBG_STATUS_INVALID_ARGS */ 5904c965db44STomer Tayar "Invalid arguments", 59057b6859fbSMintz, Yuval 59067b6859fbSMintz, Yuval /* DBG_STATUS_OUTPUT_ALREADY_SET */ 5907c965db44STomer Tayar "The debug output was already set", 59087b6859fbSMintz, Yuval 59097b6859fbSMintz, Yuval /* DBG_STATUS_INVALID_PCI_BUF_SIZE */ 5910c965db44STomer Tayar "Invalid PCI buffer size", 59117b6859fbSMintz, Yuval 59127b6859fbSMintz, Yuval /* DBG_STATUS_PCI_BUF_ALLOC_FAILED */ 5913c965db44STomer Tayar "PCI buffer allocation failed", 59147b6859fbSMintz, Yuval 59157b6859fbSMintz, Yuval /* DBG_STATUS_PCI_BUF_NOT_ALLOCATED */ 5916c965db44STomer Tayar "A PCI buffer wasn't allocated", 59177b6859fbSMintz, Yuval 59187b6859fbSMintz, Yuval /* DBG_STATUS_TOO_MANY_INPUTS */ 5919c965db44STomer Tayar "Too many inputs were enabled. Enabled less inputs, or set 'unifyInputs' to true", 59207b6859fbSMintz, Yuval 59217b6859fbSMintz, Yuval /* DBG_STATUS_INPUT_OVERLAP */ 59227b6859fbSMintz, Yuval "Overlapping debug bus inputs", 59237b6859fbSMintz, Yuval 59247b6859fbSMintz, Yuval /* DBG_STATUS_HW_ONLY_RECORDING */ 5925c965db44STomer Tayar "Cannot record Storm data since the entire recording cycle is used by HW", 59267b6859fbSMintz, Yuval 59277b6859fbSMintz, Yuval /* DBG_STATUS_STORM_ALREADY_ENABLED */ 5928c965db44STomer Tayar "The Storm was already enabled", 59297b6859fbSMintz, Yuval 59307b6859fbSMintz, Yuval /* DBG_STATUS_STORM_NOT_ENABLED */ 5931c965db44STomer Tayar "The specified Storm wasn't enabled", 59327b6859fbSMintz, Yuval 59337b6859fbSMintz, Yuval /* DBG_STATUS_BLOCK_ALREADY_ENABLED */ 5934c965db44STomer Tayar "The block was already enabled", 59357b6859fbSMintz, Yuval 59367b6859fbSMintz, Yuval /* DBG_STATUS_BLOCK_NOT_ENABLED */ 5937c965db44STomer Tayar "The specified block wasn't enabled", 59387b6859fbSMintz, Yuval 59397b6859fbSMintz, Yuval /* DBG_STATUS_NO_INPUT_ENABLED */ 5940c965db44STomer Tayar "No input was enabled for recording", 59417b6859fbSMintz, Yuval 59427b6859fbSMintz, Yuval /* DBG_STATUS_NO_FILTER_TRIGGER_64B */ 5943c965db44STomer Tayar "Filters and triggers are not allowed when recording in 64b units", 59447b6859fbSMintz, Yuval 59457b6859fbSMintz, Yuval /* DBG_STATUS_FILTER_ALREADY_ENABLED */ 5946c965db44STomer Tayar "The filter was already enabled", 59477b6859fbSMintz, Yuval 59487b6859fbSMintz, Yuval /* DBG_STATUS_TRIGGER_ALREADY_ENABLED */ 5949c965db44STomer Tayar "The trigger was already enabled", 59507b6859fbSMintz, Yuval 59517b6859fbSMintz, Yuval /* DBG_STATUS_TRIGGER_NOT_ENABLED */ 5952c965db44STomer Tayar "The trigger wasn't enabled", 59537b6859fbSMintz, Yuval 59547b6859fbSMintz, Yuval /* DBG_STATUS_CANT_ADD_CONSTRAINT */ 5955c965db44STomer Tayar "A constraint can be added only after a filter was enabled or a trigger state was added", 59567b6859fbSMintz, Yuval 59577b6859fbSMintz, Yuval /* DBG_STATUS_TOO_MANY_TRIGGER_STATES */ 5958c965db44STomer Tayar "Cannot add more than 3 trigger states", 59597b6859fbSMintz, Yuval 59607b6859fbSMintz, Yuval /* DBG_STATUS_TOO_MANY_CONSTRAINTS */ 5961c965db44STomer Tayar "Cannot add more than 4 constraints per filter or trigger state", 59627b6859fbSMintz, Yuval 59637b6859fbSMintz, Yuval /* DBG_STATUS_RECORDING_NOT_STARTED */ 5964c965db44STomer Tayar "The recording wasn't started", 59657b6859fbSMintz, Yuval 59667b6859fbSMintz, Yuval /* DBG_STATUS_DATA_DIDNT_TRIGGER */ 5967c965db44STomer Tayar "A trigger was configured, but it didn't trigger", 59687b6859fbSMintz, Yuval 59697b6859fbSMintz, Yuval /* DBG_STATUS_NO_DATA_RECORDED */ 5970c965db44STomer Tayar "No data was recorded", 59717b6859fbSMintz, Yuval 59727b6859fbSMintz, Yuval /* DBG_STATUS_DUMP_BUF_TOO_SMALL */ 5973c965db44STomer Tayar "Dump buffer is too small", 59747b6859fbSMintz, Yuval 59757b6859fbSMintz, Yuval /* DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED */ 5976c965db44STomer Tayar "Dumped data is not aligned to chunks", 59777b6859fbSMintz, Yuval 59787b6859fbSMintz, Yuval /* DBG_STATUS_UNKNOWN_CHIP */ 5979c965db44STomer Tayar "Unknown chip", 59807b6859fbSMintz, Yuval 59817b6859fbSMintz, Yuval /* DBG_STATUS_VIRT_MEM_ALLOC_FAILED */ 5982c965db44STomer Tayar "Failed allocating virtual memory", 59837b6859fbSMintz, Yuval 59847b6859fbSMintz, Yuval /* DBG_STATUS_BLOCK_IN_RESET */ 5985c965db44STomer Tayar "The input block is in reset", 59867b6859fbSMintz, Yuval 59877b6859fbSMintz, Yuval /* DBG_STATUS_INVALID_TRACE_SIGNATURE */ 5988c965db44STomer Tayar "Invalid MCP trace signature found in NVRAM", 59897b6859fbSMintz, Yuval 59907b6859fbSMintz, Yuval /* DBG_STATUS_INVALID_NVRAM_BUNDLE */ 5991c965db44STomer Tayar "Invalid bundle ID found in NVRAM", 59927b6859fbSMintz, Yuval 59937b6859fbSMintz, Yuval /* DBG_STATUS_NVRAM_GET_IMAGE_FAILED */ 5994c965db44STomer Tayar "Failed getting NVRAM image", 59957b6859fbSMintz, Yuval 59967b6859fbSMintz, Yuval /* DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE */ 5997c965db44STomer Tayar "NVRAM image is not dword-aligned", 59987b6859fbSMintz, Yuval 59997b6859fbSMintz, Yuval /* DBG_STATUS_NVRAM_READ_FAILED */ 6000c965db44STomer Tayar "Failed reading from NVRAM", 60017b6859fbSMintz, Yuval 60027b6859fbSMintz, Yuval /* DBG_STATUS_IDLE_CHK_PARSE_FAILED */ 6003c965db44STomer Tayar "Idle check parsing failed", 60047b6859fbSMintz, Yuval 60057b6859fbSMintz, Yuval /* DBG_STATUS_MCP_TRACE_BAD_DATA */ 6006c965db44STomer Tayar "MCP Trace data is corrupt", 60077b6859fbSMintz, Yuval 60087b6859fbSMintz, Yuval /* DBG_STATUS_MCP_TRACE_NO_META */ 60097b6859fbSMintz, Yuval "Dump doesn't contain meta data - it must be provided in image file", 60107b6859fbSMintz, Yuval 60117b6859fbSMintz, Yuval /* DBG_STATUS_MCP_COULD_NOT_HALT */ 6012c965db44STomer Tayar "Failed to halt MCP", 60137b6859fbSMintz, Yuval 60147b6859fbSMintz, Yuval /* DBG_STATUS_MCP_COULD_NOT_RESUME */ 6015c965db44STomer Tayar "Failed to resume MCP after halt", 60167b6859fbSMintz, Yuval 6017da090917STomer Tayar /* DBG_STATUS_RESERVED2 */ 6018da090917STomer Tayar "Reserved debug status - shouldn't be returned", 60197b6859fbSMintz, Yuval 60207b6859fbSMintz, Yuval /* DBG_STATUS_SEMI_FIFO_NOT_EMPTY */ 6021c965db44STomer Tayar "Failed to empty SEMI sync FIFO", 60227b6859fbSMintz, Yuval 60237b6859fbSMintz, Yuval /* DBG_STATUS_IGU_FIFO_BAD_DATA */ 6024c965db44STomer Tayar "IGU FIFO data is corrupt", 60257b6859fbSMintz, Yuval 60267b6859fbSMintz, Yuval /* DBG_STATUS_MCP_COULD_NOT_MASK_PRTY */ 6027c965db44STomer Tayar "MCP failed to mask parities", 60287b6859fbSMintz, Yuval 60297b6859fbSMintz, Yuval /* DBG_STATUS_FW_ASSERTS_PARSE_FAILED */ 6030c965db44STomer Tayar "FW Asserts parsing failed", 60317b6859fbSMintz, Yuval 60327b6859fbSMintz, Yuval /* DBG_STATUS_REG_FIFO_BAD_DATA */ 6033c965db44STomer Tayar "GRC FIFO data is corrupt", 60347b6859fbSMintz, Yuval 60357b6859fbSMintz, Yuval /* DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA */ 6036c965db44STomer Tayar "Protection Override data is corrupt", 60377b6859fbSMintz, Yuval 60387b6859fbSMintz, Yuval /* DBG_STATUS_DBG_ARRAY_NOT_SET */ 6039c965db44STomer Tayar "Debug arrays were not set (when using binary files, dbg_set_bin_ptr must be called)", 60407b6859fbSMintz, Yuval 60417b6859fbSMintz, Yuval /* DBG_STATUS_FILTER_BUG */ 60427b6859fbSMintz, Yuval "Debug Bus filtering requires the -unifyInputs option (due to a HW bug)", 60437b6859fbSMintz, Yuval 60447b6859fbSMintz, Yuval /* DBG_STATUS_NON_MATCHING_LINES */ 60457b6859fbSMintz, Yuval "Non-matching debug lines - all lines must be of the same type (either 128b or 256b)", 60467b6859fbSMintz, Yuval 60477b6859fbSMintz, Yuval /* DBG_STATUS_INVALID_TRIGGER_DWORD_OFFSET */ 60487b6859fbSMintz, Yuval "The selected trigger dword offset wasn't enabled in the recorded HW block", 60497b6859fbSMintz, Yuval 60507b6859fbSMintz, Yuval /* DBG_STATUS_DBG_BUS_IN_USE */ 60517b6859fbSMintz, Yuval "The debug bus is in use" 6052c965db44STomer Tayar }; 6053c965db44STomer Tayar 6054c965db44STomer Tayar /* Idle check severity names array */ 6055c965db44STomer Tayar static const char * const s_idle_chk_severity_str[] = { 6056c965db44STomer Tayar "Error", 6057c965db44STomer Tayar "Error if no traffic", 6058c965db44STomer Tayar "Warning" 6059c965db44STomer Tayar }; 6060c965db44STomer Tayar 6061c965db44STomer Tayar /* MCP Trace level names array */ 6062c965db44STomer Tayar static const char * const s_mcp_trace_level_str[] = { 6063c965db44STomer Tayar "ERROR", 6064c965db44STomer Tayar "TRACE", 6065c965db44STomer Tayar "DEBUG" 6066c965db44STomer Tayar }; 6067c965db44STomer Tayar 60687b6859fbSMintz, Yuval /* Access type names array */ 6069c965db44STomer Tayar static const char * const s_access_strs[] = { 6070c965db44STomer Tayar "read", 6071c965db44STomer Tayar "write" 6072c965db44STomer Tayar }; 6073c965db44STomer Tayar 60747b6859fbSMintz, Yuval /* Privilege type names array */ 6075c965db44STomer Tayar static const char * const s_privilege_strs[] = { 6076c965db44STomer Tayar "VF", 6077c965db44STomer Tayar "PDA", 6078c965db44STomer Tayar "HV", 6079c965db44STomer Tayar "UA" 6080c965db44STomer Tayar }; 6081c965db44STomer Tayar 60827b6859fbSMintz, Yuval /* Protection type names array */ 6083c965db44STomer Tayar static const char * const s_protection_strs[] = { 6084c965db44STomer Tayar "(default)", 6085c965db44STomer Tayar "(default)", 6086c965db44STomer Tayar "(default)", 6087c965db44STomer Tayar "(default)", 6088c965db44STomer Tayar "override VF", 6089c965db44STomer Tayar "override PDA", 6090c965db44STomer Tayar "override HV", 6091c965db44STomer Tayar "override UA" 6092c965db44STomer Tayar }; 6093c965db44STomer Tayar 60947b6859fbSMintz, Yuval /* Master type names array */ 6095c965db44STomer Tayar static const char * const s_master_strs[] = { 6096c965db44STomer Tayar "???", 6097c965db44STomer Tayar "pxp", 6098c965db44STomer Tayar "mcp", 6099c965db44STomer Tayar "msdm", 6100c965db44STomer Tayar "psdm", 6101c965db44STomer Tayar "ysdm", 6102c965db44STomer Tayar "usdm", 6103c965db44STomer Tayar "tsdm", 6104c965db44STomer Tayar "xsdm", 6105c965db44STomer Tayar "dbu", 6106c965db44STomer Tayar "dmae", 6107c965db44STomer Tayar "???", 6108c965db44STomer Tayar "???", 6109c965db44STomer Tayar "???", 6110c965db44STomer Tayar "???", 6111c965db44STomer Tayar "???" 6112c965db44STomer Tayar }; 6113c965db44STomer Tayar 61147b6859fbSMintz, Yuval /* REG FIFO error messages array */ 6115c965db44STomer Tayar static const char * const s_reg_fifo_error_strs[] = { 6116c965db44STomer Tayar "grc timeout", 6117c965db44STomer Tayar "address doesn't belong to any block", 6118c965db44STomer Tayar "reserved address in block or write to read-only address", 6119c965db44STomer Tayar "privilege/protection mismatch", 6120c965db44STomer Tayar "path isolation error" 6121c965db44STomer Tayar }; 6122c965db44STomer Tayar 61237b6859fbSMintz, Yuval /* IGU FIFO sources array */ 6124c965db44STomer Tayar static const char * const s_igu_fifo_source_strs[] = { 6125c965db44STomer Tayar "TSTORM", 6126c965db44STomer Tayar "MSTORM", 6127c965db44STomer Tayar "USTORM", 6128c965db44STomer Tayar "XSTORM", 6129c965db44STomer Tayar "YSTORM", 6130c965db44STomer Tayar "PSTORM", 6131c965db44STomer Tayar "PCIE", 6132c965db44STomer Tayar "NIG_QM_PBF", 6133c965db44STomer Tayar "CAU", 6134c965db44STomer Tayar "ATTN", 6135c965db44STomer Tayar "GRC", 6136c965db44STomer Tayar }; 6137c965db44STomer Tayar 61387b6859fbSMintz, Yuval /* IGU FIFO error messages */ 6139c965db44STomer Tayar static const char * const s_igu_fifo_error_strs[] = { 6140c965db44STomer Tayar "no error", 6141c965db44STomer Tayar "length error", 6142c965db44STomer Tayar "function disabled", 61431d510657SColin Ian King "VF sent command to attention address", 6144c965db44STomer Tayar "host sent prod update command", 6145c965db44STomer Tayar "read of during interrupt register while in MIMD mode", 6146c965db44STomer Tayar "access to PXP BAR reserved address", 6147c965db44STomer Tayar "producer update command to attention index", 6148c965db44STomer Tayar "unknown error", 6149c965db44STomer Tayar "SB index not valid", 6150c965db44STomer Tayar "SB relative index and FID not found", 6151c965db44STomer Tayar "FID not match", 6152c965db44STomer Tayar "command with error flag asserted (PCI error or CAU discard)", 6153c965db44STomer Tayar "VF sent cleanup and RF cleanup is disabled", 6154c965db44STomer Tayar "cleanup command on type bigger than 4" 6155c965db44STomer Tayar }; 6156c965db44STomer Tayar 6157c965db44STomer Tayar /* IGU FIFO address data */ 6158c965db44STomer Tayar static const struct igu_fifo_addr_data s_igu_fifo_addr_data[] = { 61597b6859fbSMintz, Yuval {0x0, 0x101, "MSI-X Memory", NULL, 61607b6859fbSMintz, Yuval IGU_ADDR_TYPE_MSIX_MEM}, 61617b6859fbSMintz, Yuval {0x102, 0x1ff, "reserved", NULL, 61627b6859fbSMintz, Yuval IGU_ADDR_TYPE_RESERVED}, 61637b6859fbSMintz, Yuval {0x200, 0x200, "Write PBA[0:63]", NULL, 61647b6859fbSMintz, Yuval IGU_ADDR_TYPE_WRITE_PBA}, 6165c965db44STomer Tayar {0x201, 0x201, "Write PBA[64:127]", "reserved", 6166c965db44STomer Tayar IGU_ADDR_TYPE_WRITE_PBA}, 61677b6859fbSMintz, Yuval {0x202, 0x202, "Write PBA[128]", "reserved", 61687b6859fbSMintz, Yuval IGU_ADDR_TYPE_WRITE_PBA}, 61697b6859fbSMintz, Yuval {0x203, 0x3ff, "reserved", NULL, 61707b6859fbSMintz, Yuval IGU_ADDR_TYPE_RESERVED}, 6171c965db44STomer Tayar {0x400, 0x5ef, "Write interrupt acknowledgment", NULL, 6172c965db44STomer Tayar IGU_ADDR_TYPE_WRITE_INT_ACK}, 6173c965db44STomer Tayar {0x5f0, 0x5f0, "Attention bits update", NULL, 6174c965db44STomer Tayar IGU_ADDR_TYPE_WRITE_ATTN_BITS}, 6175c965db44STomer Tayar {0x5f1, 0x5f1, "Attention bits set", NULL, 6176c965db44STomer Tayar IGU_ADDR_TYPE_WRITE_ATTN_BITS}, 6177c965db44STomer Tayar {0x5f2, 0x5f2, "Attention bits clear", NULL, 6178c965db44STomer Tayar IGU_ADDR_TYPE_WRITE_ATTN_BITS}, 6179c965db44STomer Tayar {0x5f3, 0x5f3, "Read interrupt 0:63 with mask", NULL, 6180c965db44STomer Tayar IGU_ADDR_TYPE_READ_INT}, 6181c965db44STomer Tayar {0x5f4, 0x5f4, "Read interrupt 0:31 with mask", NULL, 6182c965db44STomer Tayar IGU_ADDR_TYPE_READ_INT}, 6183c965db44STomer Tayar {0x5f5, 0x5f5, "Read interrupt 32:63 with mask", NULL, 6184c965db44STomer Tayar IGU_ADDR_TYPE_READ_INT}, 6185c965db44STomer Tayar {0x5f6, 0x5f6, "Read interrupt 0:63 without mask", NULL, 6186c965db44STomer Tayar IGU_ADDR_TYPE_READ_INT}, 61877b6859fbSMintz, Yuval {0x5f7, 0x5ff, "reserved", NULL, 61887b6859fbSMintz, Yuval IGU_ADDR_TYPE_RESERVED}, 61897b6859fbSMintz, Yuval {0x600, 0x7ff, "Producer update", NULL, 61907b6859fbSMintz, Yuval IGU_ADDR_TYPE_WRITE_PROD_UPDATE} 6191c965db44STomer Tayar }; 6192c965db44STomer Tayar 6193c965db44STomer Tayar /******************************** Variables **********************************/ 6194c965db44STomer Tayar 6195c965db44STomer Tayar /* Temporary buffer, used for print size calculations */ 6196c965db44STomer Tayar static char s_temp_buf[MAX_MSG_LEN]; 6197c965db44STomer Tayar 61987b6859fbSMintz, Yuval /**************************** Private Functions ******************************/ 6199c965db44STomer Tayar 6200c965db44STomer Tayar static u32 qed_cyclic_add(u32 a, u32 b, u32 size) 6201c965db44STomer Tayar { 6202c965db44STomer Tayar return (a + b) % size; 6203c965db44STomer Tayar } 6204c965db44STomer Tayar 6205c965db44STomer Tayar static u32 qed_cyclic_sub(u32 a, u32 b, u32 size) 6206c965db44STomer Tayar { 6207c965db44STomer Tayar return (size + a - b) % size; 6208c965db44STomer Tayar } 6209c965db44STomer Tayar 6210c965db44STomer Tayar /* Reads the specified number of bytes from the specified cyclic buffer (up to 4 6211c965db44STomer Tayar * bytes) and returns them as a dword value. the specified buffer offset is 6212c965db44STomer Tayar * updated. 6213c965db44STomer Tayar */ 6214c965db44STomer Tayar static u32 qed_read_from_cyclic_buf(void *buf, 6215c965db44STomer Tayar u32 *offset, 6216c965db44STomer Tayar u32 buf_size, u8 num_bytes_to_read) 6217c965db44STomer Tayar { 62187b6859fbSMintz, Yuval u8 i, *val_ptr, *bytes_buf = (u8 *)buf; 6219c965db44STomer Tayar u32 val = 0; 6220c965db44STomer Tayar 6221c965db44STomer Tayar val_ptr = (u8 *)&val; 6222c965db44STomer Tayar 622350bc60cbSMichal Kalderon /* Assume running on a LITTLE ENDIAN and the buffer is network order 622450bc60cbSMichal Kalderon * (BIG ENDIAN), as high order bytes are placed in lower memory address. 622550bc60cbSMichal Kalderon */ 6226c965db44STomer Tayar for (i = 0; i < num_bytes_to_read; i++) { 6227c965db44STomer Tayar val_ptr[i] = bytes_buf[*offset]; 6228c965db44STomer Tayar *offset = qed_cyclic_add(*offset, 1, buf_size); 6229c965db44STomer Tayar } 6230c965db44STomer Tayar 6231c965db44STomer Tayar return val; 6232c965db44STomer Tayar } 6233c965db44STomer Tayar 6234c965db44STomer Tayar /* Reads and returns the next byte from the specified buffer. 6235c965db44STomer Tayar * The specified buffer offset is updated. 6236c965db44STomer Tayar */ 6237c965db44STomer Tayar static u8 qed_read_byte_from_buf(void *buf, u32 *offset) 6238c965db44STomer Tayar { 6239c965db44STomer Tayar return ((u8 *)buf)[(*offset)++]; 6240c965db44STomer Tayar } 6241c965db44STomer Tayar 6242c965db44STomer Tayar /* Reads and returns the next dword from the specified buffer. 6243c965db44STomer Tayar * The specified buffer offset is updated. 6244c965db44STomer Tayar */ 6245c965db44STomer Tayar static u32 qed_read_dword_from_buf(void *buf, u32 *offset) 6246c965db44STomer Tayar { 6247c965db44STomer Tayar u32 dword_val = *(u32 *)&((u8 *)buf)[*offset]; 6248c965db44STomer Tayar 6249c965db44STomer Tayar *offset += 4; 62507b6859fbSMintz, Yuval 6251c965db44STomer Tayar return dword_val; 6252c965db44STomer Tayar } 6253c965db44STomer Tayar 6254c965db44STomer Tayar /* Reads the next string from the specified buffer, and copies it to the 6255c965db44STomer Tayar * specified pointer. The specified buffer offset is updated. 6256c965db44STomer Tayar */ 6257c965db44STomer Tayar static void qed_read_str_from_buf(void *buf, u32 *offset, u32 size, char *dest) 6258c965db44STomer Tayar { 6259c965db44STomer Tayar const char *source_str = &((const char *)buf)[*offset]; 6260c965db44STomer Tayar 6261c965db44STomer Tayar strncpy(dest, source_str, size); 6262c965db44STomer Tayar dest[size - 1] = '\0'; 6263c965db44STomer Tayar *offset += size; 6264c965db44STomer Tayar } 6265c965db44STomer Tayar 6266c965db44STomer Tayar /* Returns a pointer to the specified offset (in bytes) of the specified buffer. 6267c965db44STomer Tayar * If the specified buffer in NULL, a temporary buffer pointer is returned. 6268c965db44STomer Tayar */ 6269c965db44STomer Tayar static char *qed_get_buf_ptr(void *buf, u32 offset) 6270c965db44STomer Tayar { 6271c965db44STomer Tayar return buf ? (char *)buf + offset : s_temp_buf; 6272c965db44STomer Tayar } 6273c965db44STomer Tayar 6274c965db44STomer Tayar /* Reads a param from the specified buffer. Returns the number of dwords read. 6275c965db44STomer Tayar * If the returned str_param is NULL, the param is numeric and its value is 6276c965db44STomer Tayar * returned in num_param. 6277c965db44STomer Tayar * Otheriwise, the param is a string and its pointer is returned in str_param. 6278c965db44STomer Tayar */ 6279c965db44STomer Tayar static u32 qed_read_param(u32 *dump_buf, 6280c965db44STomer Tayar const char **param_name, 6281c965db44STomer Tayar const char **param_str_val, u32 *param_num_val) 6282c965db44STomer Tayar { 6283c965db44STomer Tayar char *char_buf = (char *)dump_buf; 62847b6859fbSMintz, Yuval size_t offset = 0; 6285c965db44STomer Tayar 6286c965db44STomer Tayar /* Extract param name */ 6287c965db44STomer Tayar *param_name = char_buf; 6288c965db44STomer Tayar offset += strlen(*param_name) + 1; 6289c965db44STomer Tayar 6290c965db44STomer Tayar /* Check param type */ 6291c965db44STomer Tayar if (*(char_buf + offset++)) { 6292c965db44STomer Tayar /* String param */ 6293c965db44STomer Tayar *param_str_val = char_buf + offset; 6294da090917STomer Tayar *param_num_val = 0; 6295c965db44STomer Tayar offset += strlen(*param_str_val) + 1; 6296c965db44STomer Tayar if (offset & 0x3) 6297c965db44STomer Tayar offset += (4 - (offset & 0x3)); 6298c965db44STomer Tayar } else { 6299c965db44STomer Tayar /* Numeric param */ 6300c965db44STomer Tayar *param_str_val = NULL; 6301c965db44STomer Tayar if (offset & 0x3) 6302c965db44STomer Tayar offset += (4 - (offset & 0x3)); 6303c965db44STomer Tayar *param_num_val = *(u32 *)(char_buf + offset); 6304c965db44STomer Tayar offset += 4; 6305c965db44STomer Tayar } 6306c965db44STomer Tayar 630750bc60cbSMichal Kalderon return (u32)offset / 4; 6308c965db44STomer Tayar } 6309c965db44STomer Tayar 6310c965db44STomer Tayar /* Reads a section header from the specified buffer. 6311c965db44STomer Tayar * Returns the number of dwords read. 6312c965db44STomer Tayar */ 6313c965db44STomer Tayar static u32 qed_read_section_hdr(u32 *dump_buf, 6314c965db44STomer Tayar const char **section_name, 6315c965db44STomer Tayar u32 *num_section_params) 6316c965db44STomer Tayar { 6317c965db44STomer Tayar const char *param_str_val; 6318c965db44STomer Tayar 6319c965db44STomer Tayar return qed_read_param(dump_buf, 6320c965db44STomer Tayar section_name, ¶m_str_val, num_section_params); 6321c965db44STomer Tayar } 6322c965db44STomer Tayar 6323c965db44STomer Tayar /* Reads section params from the specified buffer and prints them to the results 6324c965db44STomer Tayar * buffer. Returns the number of dwords read. 6325c965db44STomer Tayar */ 6326c965db44STomer Tayar static u32 qed_print_section_params(u32 *dump_buf, 6327c965db44STomer Tayar u32 num_section_params, 6328c965db44STomer Tayar char *results_buf, u32 *num_chars_printed) 6329c965db44STomer Tayar { 6330c965db44STomer Tayar u32 i, dump_offset = 0, results_offset = 0; 6331c965db44STomer Tayar 6332c965db44STomer Tayar for (i = 0; i < num_section_params; i++) { 63337b6859fbSMintz, Yuval const char *param_name, *param_str_val; 6334c965db44STomer Tayar u32 param_num_val = 0; 6335c965db44STomer Tayar 6336c965db44STomer Tayar dump_offset += qed_read_param(dump_buf + dump_offset, 6337c965db44STomer Tayar ¶m_name, 6338c965db44STomer Tayar ¶m_str_val, ¶m_num_val); 63397b6859fbSMintz, Yuval 6340c965db44STomer Tayar if (param_str_val) 6341c965db44STomer Tayar results_offset += 6342c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6343c965db44STomer Tayar results_offset), 6344c965db44STomer Tayar "%s: %s\n", param_name, param_str_val); 6345c965db44STomer Tayar else if (strcmp(param_name, "fw-timestamp")) 6346c965db44STomer Tayar results_offset += 6347c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6348c965db44STomer Tayar results_offset), 6349c965db44STomer Tayar "%s: %d\n", param_name, param_num_val); 6350c965db44STomer Tayar } 6351c965db44STomer Tayar 63527b6859fbSMintz, Yuval results_offset += sprintf(qed_get_buf_ptr(results_buf, results_offset), 63537b6859fbSMintz, Yuval "\n"); 6354c965db44STomer Tayar 63557b6859fbSMintz, Yuval *num_chars_printed = results_offset; 63567b6859fbSMintz, Yuval 63577b6859fbSMintz, Yuval return dump_offset; 6358c965db44STomer Tayar } 6359c965db44STomer Tayar 6360a3f72307SDenis Bolotin static struct dbg_tools_user_data * 6361a3f72307SDenis Bolotin qed_dbg_get_user_data(struct qed_hwfn *p_hwfn) 6362a3f72307SDenis Bolotin { 6363a3f72307SDenis Bolotin return (struct dbg_tools_user_data *)p_hwfn->dbg_user_info; 6364a3f72307SDenis Bolotin } 6365a3f72307SDenis Bolotin 6366c965db44STomer Tayar /* Parses the idle check rules and returns the number of characters printed. 6367c965db44STomer Tayar * In case of parsing error, returns 0. 6368c965db44STomer Tayar */ 6369da090917STomer Tayar static u32 qed_parse_idle_chk_dump_rules(u32 *dump_buf, 6370c965db44STomer Tayar u32 *dump_buf_end, 6371c965db44STomer Tayar u32 num_rules, 6372c965db44STomer Tayar bool print_fw_idle_chk, 6373c965db44STomer Tayar char *results_buf, 6374c965db44STomer Tayar u32 *num_errors, u32 *num_warnings) 6375c965db44STomer Tayar { 63767b6859fbSMintz, Yuval /* Offset in results_buf in bytes */ 63777b6859fbSMintz, Yuval u32 results_offset = 0; 63787b6859fbSMintz, Yuval 63797b6859fbSMintz, Yuval u32 rule_idx; 6380c965db44STomer Tayar u16 i, j; 6381c965db44STomer Tayar 6382c965db44STomer Tayar *num_errors = 0; 6383c965db44STomer Tayar *num_warnings = 0; 6384c965db44STomer Tayar 6385c965db44STomer Tayar /* Go over dumped results */ 6386c965db44STomer Tayar for (rule_idx = 0; rule_idx < num_rules && dump_buf < dump_buf_end; 6387c965db44STomer Tayar rule_idx++) { 6388c965db44STomer Tayar const struct dbg_idle_chk_rule_parsing_data *rule_parsing_data; 6389c965db44STomer Tayar struct dbg_idle_chk_result_hdr *hdr; 63907b6859fbSMintz, Yuval const char *parsing_str, *lsi_msg; 6391c965db44STomer Tayar u32 parsing_str_offset; 6392c965db44STomer Tayar bool has_fw_msg; 63937b6859fbSMintz, Yuval u8 curr_reg_id; 6394c965db44STomer Tayar 6395c965db44STomer Tayar hdr = (struct dbg_idle_chk_result_hdr *)dump_buf; 6396c965db44STomer Tayar rule_parsing_data = 6397c965db44STomer Tayar (const struct dbg_idle_chk_rule_parsing_data *) 63987b6859fbSMintz, Yuval &s_user_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_PARSING_DATA]. 6399c965db44STomer Tayar ptr[hdr->rule_id]; 6400c965db44STomer Tayar parsing_str_offset = 6401c965db44STomer Tayar GET_FIELD(rule_parsing_data->data, 6402c965db44STomer Tayar DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET); 6403c965db44STomer Tayar has_fw_msg = 6404c965db44STomer Tayar GET_FIELD(rule_parsing_data->data, 6405c965db44STomer Tayar DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG) > 0; 64067b6859fbSMintz, Yuval parsing_str = 64077b6859fbSMintz, Yuval &((const char *) 64087b6859fbSMintz, Yuval s_user_dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS].ptr) 6409c965db44STomer Tayar [parsing_str_offset]; 6410c965db44STomer Tayar lsi_msg = parsing_str; 64117b6859fbSMintz, Yuval curr_reg_id = 0; 6412c965db44STomer Tayar 6413c965db44STomer Tayar if (hdr->severity >= MAX_DBG_IDLE_CHK_SEVERITY_TYPES) 6414c965db44STomer Tayar return 0; 6415c965db44STomer Tayar 6416c965db44STomer Tayar /* Skip rule header */ 64177b6859fbSMintz, Yuval dump_buf += BYTES_TO_DWORDS(sizeof(*hdr)); 6418c965db44STomer Tayar 6419c965db44STomer Tayar /* Update errors/warnings count */ 6420c965db44STomer Tayar if (hdr->severity == IDLE_CHK_SEVERITY_ERROR || 6421c965db44STomer Tayar hdr->severity == IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC) 6422c965db44STomer Tayar (*num_errors)++; 6423c965db44STomer Tayar else 6424c965db44STomer Tayar (*num_warnings)++; 6425c965db44STomer Tayar 6426c965db44STomer Tayar /* Print rule severity */ 6427c965db44STomer Tayar results_offset += 6428c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6429c965db44STomer Tayar results_offset), "%s: ", 6430c965db44STomer Tayar s_idle_chk_severity_str[hdr->severity]); 6431c965db44STomer Tayar 6432c965db44STomer Tayar /* Print rule message */ 6433c965db44STomer Tayar if (has_fw_msg) 6434c965db44STomer Tayar parsing_str += strlen(parsing_str) + 1; 6435c965db44STomer Tayar results_offset += 6436c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6437c965db44STomer Tayar results_offset), "%s.", 6438c965db44STomer Tayar has_fw_msg && 6439c965db44STomer Tayar print_fw_idle_chk ? parsing_str : lsi_msg); 6440c965db44STomer Tayar parsing_str += strlen(parsing_str) + 1; 6441c965db44STomer Tayar 6442c965db44STomer Tayar /* Print register values */ 6443c965db44STomer Tayar results_offset += 6444c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6445c965db44STomer Tayar results_offset), " Registers:"); 6446c965db44STomer Tayar for (i = 0; 6447c965db44STomer Tayar i < hdr->num_dumped_cond_regs + hdr->num_dumped_info_regs; 6448c965db44STomer Tayar i++) { 64497b6859fbSMintz, Yuval struct dbg_idle_chk_result_reg_hdr *reg_hdr; 64507b6859fbSMintz, Yuval bool is_mem; 64517b6859fbSMintz, Yuval u8 reg_id; 64527b6859fbSMintz, Yuval 64537b6859fbSMintz, Yuval reg_hdr = 64547b6859fbSMintz, Yuval (struct dbg_idle_chk_result_reg_hdr *)dump_buf; 64557b6859fbSMintz, Yuval is_mem = GET_FIELD(reg_hdr->data, 6456c965db44STomer Tayar DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM); 64577b6859fbSMintz, Yuval reg_id = GET_FIELD(reg_hdr->data, 6458c965db44STomer Tayar DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID); 6459c965db44STomer Tayar 6460c965db44STomer Tayar /* Skip reg header */ 64617b6859fbSMintz, Yuval dump_buf += BYTES_TO_DWORDS(sizeof(*reg_hdr)); 6462c965db44STomer Tayar 6463c965db44STomer Tayar /* Skip register names until the required reg_id is 6464c965db44STomer Tayar * reached. 6465c965db44STomer Tayar */ 6466c965db44STomer Tayar for (; reg_id > curr_reg_id; 6467c965db44STomer Tayar curr_reg_id++, 6468c965db44STomer Tayar parsing_str += strlen(parsing_str) + 1); 6469c965db44STomer Tayar 6470c965db44STomer Tayar results_offset += 6471c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6472c965db44STomer Tayar results_offset), " %s", 6473c965db44STomer Tayar parsing_str); 6474c965db44STomer Tayar if (i < hdr->num_dumped_cond_regs && is_mem) 6475c965db44STomer Tayar results_offset += 6476c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6477c965db44STomer Tayar results_offset), 6478c965db44STomer Tayar "[%d]", hdr->mem_entry_id + 6479c965db44STomer Tayar reg_hdr->start_entry); 6480c965db44STomer Tayar results_offset += 6481c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6482c965db44STomer Tayar results_offset), "="); 6483c965db44STomer Tayar for (j = 0; j < reg_hdr->size; j++, dump_buf++) { 6484c965db44STomer Tayar results_offset += 6485c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6486c965db44STomer Tayar results_offset), 6487c965db44STomer Tayar "0x%x", *dump_buf); 6488c965db44STomer Tayar if (j < reg_hdr->size - 1) 6489c965db44STomer Tayar results_offset += 6490c965db44STomer Tayar sprintf(qed_get_buf_ptr 6491c965db44STomer Tayar (results_buf, 6492c965db44STomer Tayar results_offset), ","); 6493c965db44STomer Tayar } 6494c965db44STomer Tayar } 6495c965db44STomer Tayar 6496c965db44STomer Tayar results_offset += 6497c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, results_offset), "\n"); 6498c965db44STomer Tayar } 6499c965db44STomer Tayar 6500c965db44STomer Tayar /* Check if end of dump buffer was exceeded */ 6501c965db44STomer Tayar if (dump_buf > dump_buf_end) 6502c965db44STomer Tayar return 0; 65037b6859fbSMintz, Yuval 6504c965db44STomer Tayar return results_offset; 6505c965db44STomer Tayar } 6506c965db44STomer Tayar 6507c965db44STomer Tayar /* Parses an idle check dump buffer. 6508c965db44STomer Tayar * If result_buf is not NULL, the idle check results are printed to it. 6509c965db44STomer Tayar * In any case, the required results buffer size is assigned to 6510c965db44STomer Tayar * parsed_results_bytes. 6511c965db44STomer Tayar * The parsing status is returned. 6512c965db44STomer Tayar */ 6513da090917STomer Tayar static enum dbg_status qed_parse_idle_chk_dump(u32 *dump_buf, 6514c965db44STomer Tayar u32 num_dumped_dwords, 6515c965db44STomer Tayar char *results_buf, 6516c965db44STomer Tayar u32 *parsed_results_bytes, 6517c965db44STomer Tayar u32 *num_errors, 6518c965db44STomer Tayar u32 *num_warnings) 6519c965db44STomer Tayar { 6520c965db44STomer Tayar const char *section_name, *param_name, *param_str_val; 6521c965db44STomer Tayar u32 *dump_buf_end = dump_buf + num_dumped_dwords; 6522c965db44STomer Tayar u32 num_section_params = 0, num_rules; 65237b6859fbSMintz, Yuval 65247b6859fbSMintz, Yuval /* Offset in results_buf in bytes */ 65257b6859fbSMintz, Yuval u32 results_offset = 0; 6526c965db44STomer Tayar 6527c965db44STomer Tayar *parsed_results_bytes = 0; 6528c965db44STomer Tayar *num_errors = 0; 6529c965db44STomer Tayar *num_warnings = 0; 65307b6859fbSMintz, Yuval 65317b6859fbSMintz, Yuval if (!s_user_dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS].ptr || 65327b6859fbSMintz, Yuval !s_user_dbg_arrays[BIN_BUF_DBG_IDLE_CHK_PARSING_DATA].ptr) 6533c965db44STomer Tayar return DBG_STATUS_DBG_ARRAY_NOT_SET; 6534c965db44STomer Tayar 6535c965db44STomer Tayar /* Read global_params section */ 6536c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 6537c965db44STomer Tayar §ion_name, &num_section_params); 6538c965db44STomer Tayar if (strcmp(section_name, "global_params")) 6539c965db44STomer Tayar return DBG_STATUS_IDLE_CHK_PARSE_FAILED; 6540c965db44STomer Tayar 6541c965db44STomer Tayar /* Print global params */ 6542c965db44STomer Tayar dump_buf += qed_print_section_params(dump_buf, 6543c965db44STomer Tayar num_section_params, 6544c965db44STomer Tayar results_buf, &results_offset); 6545c965db44STomer Tayar 6546c965db44STomer Tayar /* Read idle_chk section */ 6547c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 6548c965db44STomer Tayar §ion_name, &num_section_params); 6549c965db44STomer Tayar if (strcmp(section_name, "idle_chk") || num_section_params != 1) 6550c965db44STomer Tayar return DBG_STATUS_IDLE_CHK_PARSE_FAILED; 6551c965db44STomer Tayar dump_buf += qed_read_param(dump_buf, 6552c965db44STomer Tayar ¶m_name, ¶m_str_val, &num_rules); 65537b6859fbSMintz, Yuval if (strcmp(param_name, "num_rules")) 6554c965db44STomer Tayar return DBG_STATUS_IDLE_CHK_PARSE_FAILED; 6555c965db44STomer Tayar 6556c965db44STomer Tayar if (num_rules) { 6557c965db44STomer Tayar u32 rules_print_size; 6558c965db44STomer Tayar 6559c965db44STomer Tayar /* Print FW output */ 6560c965db44STomer Tayar results_offset += 6561c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6562c965db44STomer Tayar results_offset), 6563c965db44STomer Tayar "FW_IDLE_CHECK:\n"); 6564c965db44STomer Tayar rules_print_size = 6565da090917STomer Tayar qed_parse_idle_chk_dump_rules(dump_buf, 6566da090917STomer Tayar dump_buf_end, 6567da090917STomer Tayar num_rules, 6568c965db44STomer Tayar true, 6569c965db44STomer Tayar results_buf ? 6570c965db44STomer Tayar results_buf + 6571da090917STomer Tayar results_offset : 6572da090917STomer Tayar NULL, 6573da090917STomer Tayar num_errors, 6574da090917STomer Tayar num_warnings); 6575c965db44STomer Tayar results_offset += rules_print_size; 65767b6859fbSMintz, Yuval if (!rules_print_size) 6577c965db44STomer Tayar return DBG_STATUS_IDLE_CHK_PARSE_FAILED; 6578c965db44STomer Tayar 6579c965db44STomer Tayar /* Print LSI output */ 6580c965db44STomer Tayar results_offset += 6581c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6582c965db44STomer Tayar results_offset), 6583c965db44STomer Tayar "\nLSI_IDLE_CHECK:\n"); 6584c965db44STomer Tayar rules_print_size = 6585da090917STomer Tayar qed_parse_idle_chk_dump_rules(dump_buf, 6586da090917STomer Tayar dump_buf_end, 6587da090917STomer Tayar num_rules, 6588c965db44STomer Tayar false, 6589c965db44STomer Tayar results_buf ? 6590c965db44STomer Tayar results_buf + 6591da090917STomer Tayar results_offset : 6592da090917STomer Tayar NULL, 6593da090917STomer Tayar num_errors, 6594da090917STomer Tayar num_warnings); 6595c965db44STomer Tayar results_offset += rules_print_size; 65967b6859fbSMintz, Yuval if (!rules_print_size) 6597c965db44STomer Tayar return DBG_STATUS_IDLE_CHK_PARSE_FAILED; 6598c965db44STomer Tayar } 6599c965db44STomer Tayar 6600c965db44STomer Tayar /* Print errors/warnings count */ 66017b6859fbSMintz, Yuval if (*num_errors) 6602c965db44STomer Tayar results_offset += 6603c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6604c965db44STomer Tayar results_offset), 6605c965db44STomer Tayar "\nIdle Check failed!!! (with %d errors and %d warnings)\n", 6606c965db44STomer Tayar *num_errors, *num_warnings); 66077b6859fbSMintz, Yuval else if (*num_warnings) 6608c965db44STomer Tayar results_offset += 6609c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6610c965db44STomer Tayar results_offset), 66117b6859fbSMintz, Yuval "\nIdle Check completed successfully (with %d warnings)\n", 6612c965db44STomer Tayar *num_warnings); 66137b6859fbSMintz, Yuval else 6614c965db44STomer Tayar results_offset += 6615c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 6616c965db44STomer Tayar results_offset), 66177b6859fbSMintz, Yuval "\nIdle Check completed successfully\n"); 6618c965db44STomer Tayar 6619c965db44STomer Tayar /* Add 1 for string NULL termination */ 6620c965db44STomer Tayar *parsed_results_bytes = results_offset + 1; 66217b6859fbSMintz, Yuval 6622c965db44STomer Tayar return DBG_STATUS_OK; 6623c965db44STomer Tayar } 6624c965db44STomer Tayar 6625c965db44STomer Tayar /* Allocates and fills MCP Trace meta data based on the specified meta data 6626c965db44STomer Tayar * dump buffer. 6627c965db44STomer Tayar * Returns debug status code. 6628c965db44STomer Tayar */ 6629a3f72307SDenis Bolotin static enum dbg_status 6630a3f72307SDenis Bolotin qed_mcp_trace_alloc_meta_data(struct qed_hwfn *p_hwfn, 6631a3f72307SDenis Bolotin const u32 *meta_buf) 6632c965db44STomer Tayar { 6633a3f72307SDenis Bolotin struct dbg_tools_user_data *dev_user_data; 6634c965db44STomer Tayar u32 offset = 0, signature, i; 6635a3f72307SDenis Bolotin struct mcp_trace_meta *meta; 6636a3f72307SDenis Bolotin u8 *meta_buf_bytes; 6637a3f72307SDenis Bolotin 6638a3f72307SDenis Bolotin dev_user_data = qed_dbg_get_user_data(p_hwfn); 6639a3f72307SDenis Bolotin meta = &dev_user_data->mcp_trace_meta; 6640a3f72307SDenis Bolotin meta_buf_bytes = (u8 *)meta_buf; 6641c965db44STomer Tayar 664250bc60cbSMichal Kalderon /* Free the previous meta before loading a new one. */ 6643a3f72307SDenis Bolotin if (meta->is_allocated) 6644a3f72307SDenis Bolotin qed_mcp_trace_free_meta_data(p_hwfn); 664550bc60cbSMichal Kalderon 6646c965db44STomer Tayar memset(meta, 0, sizeof(*meta)); 6647c965db44STomer Tayar 6648c965db44STomer Tayar /* Read first signature */ 6649c965db44STomer Tayar signature = qed_read_dword_from_buf(meta_buf_bytes, &offset); 66507b6859fbSMintz, Yuval if (signature != NVM_MAGIC_VALUE) 6651c965db44STomer Tayar return DBG_STATUS_INVALID_TRACE_SIGNATURE; 6652c965db44STomer Tayar 66537b6859fbSMintz, Yuval /* Read no. of modules and allocate memory for their pointers */ 6654c965db44STomer Tayar meta->modules_num = qed_read_byte_from_buf(meta_buf_bytes, &offset); 66556396bb22SKees Cook meta->modules = kcalloc(meta->modules_num, sizeof(char *), 66566396bb22SKees Cook GFP_KERNEL); 6657c965db44STomer Tayar if (!meta->modules) 6658c965db44STomer Tayar return DBG_STATUS_VIRT_MEM_ALLOC_FAILED; 6659c965db44STomer Tayar 6660c965db44STomer Tayar /* Allocate and read all module strings */ 6661c965db44STomer Tayar for (i = 0; i < meta->modules_num; i++) { 6662c965db44STomer Tayar u8 module_len = qed_read_byte_from_buf(meta_buf_bytes, &offset); 6663c965db44STomer Tayar 6664c965db44STomer Tayar *(meta->modules + i) = kzalloc(module_len, GFP_KERNEL); 6665c965db44STomer Tayar if (!(*(meta->modules + i))) { 6666c965db44STomer Tayar /* Update number of modules to be released */ 6667c965db44STomer Tayar meta->modules_num = i ? i - 1 : 0; 6668c965db44STomer Tayar return DBG_STATUS_VIRT_MEM_ALLOC_FAILED; 6669c965db44STomer Tayar } 6670c965db44STomer Tayar 6671c965db44STomer Tayar qed_read_str_from_buf(meta_buf_bytes, &offset, module_len, 6672c965db44STomer Tayar *(meta->modules + i)); 6673c965db44STomer Tayar if (module_len > MCP_TRACE_MAX_MODULE_LEN) 6674c965db44STomer Tayar (*(meta->modules + i))[MCP_TRACE_MAX_MODULE_LEN] = '\0'; 6675c965db44STomer Tayar } 6676c965db44STomer Tayar 6677c965db44STomer Tayar /* Read second signature */ 6678c965db44STomer Tayar signature = qed_read_dword_from_buf(meta_buf_bytes, &offset); 66797b6859fbSMintz, Yuval if (signature != NVM_MAGIC_VALUE) 6680c965db44STomer Tayar return DBG_STATUS_INVALID_TRACE_SIGNATURE; 6681c965db44STomer Tayar 6682c965db44STomer Tayar /* Read number of formats and allocate memory for all formats */ 6683c965db44STomer Tayar meta->formats_num = qed_read_dword_from_buf(meta_buf_bytes, &offset); 66846396bb22SKees Cook meta->formats = kcalloc(meta->formats_num, 6685c965db44STomer Tayar sizeof(struct mcp_trace_format), 6686c965db44STomer Tayar GFP_KERNEL); 6687c965db44STomer Tayar if (!meta->formats) 6688c965db44STomer Tayar return DBG_STATUS_VIRT_MEM_ALLOC_FAILED; 6689c965db44STomer Tayar 6690c965db44STomer Tayar /* Allocate and read all strings */ 6691c965db44STomer Tayar for (i = 0; i < meta->formats_num; i++) { 6692c965db44STomer Tayar struct mcp_trace_format *format_ptr = &meta->formats[i]; 6693c965db44STomer Tayar u8 format_len; 6694c965db44STomer Tayar 6695c965db44STomer Tayar format_ptr->data = qed_read_dword_from_buf(meta_buf_bytes, 6696c965db44STomer Tayar &offset); 6697c965db44STomer Tayar format_len = 6698c965db44STomer Tayar (format_ptr->data & 6699c965db44STomer Tayar MCP_TRACE_FORMAT_LEN_MASK) >> MCP_TRACE_FORMAT_LEN_SHIFT; 6700c965db44STomer Tayar format_ptr->format_str = kzalloc(format_len, GFP_KERNEL); 6701c965db44STomer Tayar if (!format_ptr->format_str) { 6702c965db44STomer Tayar /* Update number of modules to be released */ 6703c965db44STomer Tayar meta->formats_num = i ? i - 1 : 0; 6704c965db44STomer Tayar return DBG_STATUS_VIRT_MEM_ALLOC_FAILED; 6705c965db44STomer Tayar } 6706c965db44STomer Tayar 6707c965db44STomer Tayar qed_read_str_from_buf(meta_buf_bytes, 6708c965db44STomer Tayar &offset, 6709c965db44STomer Tayar format_len, format_ptr->format_str); 6710c965db44STomer Tayar } 6711c965db44STomer Tayar 6712a3f72307SDenis Bolotin meta->is_allocated = true; 6713c965db44STomer Tayar return DBG_STATUS_OK; 6714c965db44STomer Tayar } 6715c965db44STomer Tayar 671650bc60cbSMichal Kalderon /* Parses an MCP trace buffer. If result_buf is not NULL, the MCP Trace results 671750bc60cbSMichal Kalderon * are printed to it. The parsing status is returned. 671850bc60cbSMichal Kalderon * Arguments: 671950bc60cbSMichal Kalderon * trace_buf - MCP trace cyclic buffer 672050bc60cbSMichal Kalderon * trace_buf_size - MCP trace cyclic buffer size in bytes 672150bc60cbSMichal Kalderon * data_offset - offset in bytes of the data to parse in the MCP trace cyclic 672250bc60cbSMichal Kalderon * buffer. 672350bc60cbSMichal Kalderon * data_size - size in bytes of data to parse. 672450bc60cbSMichal Kalderon * parsed_buf - destination buffer for parsed data. 6725a3f72307SDenis Bolotin * parsed_results_bytes - size of parsed data in bytes. 672650bc60cbSMichal Kalderon */ 6727a3f72307SDenis Bolotin static enum dbg_status qed_parse_mcp_trace_buf(struct qed_hwfn *p_hwfn, 6728a3f72307SDenis Bolotin u8 *trace_buf, 672950bc60cbSMichal Kalderon u32 trace_buf_size, 673050bc60cbSMichal Kalderon u32 data_offset, 673150bc60cbSMichal Kalderon u32 data_size, 673250bc60cbSMichal Kalderon char *parsed_buf, 6733a3f72307SDenis Bolotin u32 *parsed_results_bytes) 673450bc60cbSMichal Kalderon { 6735a3f72307SDenis Bolotin struct dbg_tools_user_data *dev_user_data; 6736a3f72307SDenis Bolotin struct mcp_trace_meta *meta; 673750bc60cbSMichal Kalderon u32 param_mask, param_shift; 673850bc60cbSMichal Kalderon enum dbg_status status; 673950bc60cbSMichal Kalderon 6740a3f72307SDenis Bolotin dev_user_data = qed_dbg_get_user_data(p_hwfn); 6741a3f72307SDenis Bolotin meta = &dev_user_data->mcp_trace_meta; 6742a3f72307SDenis Bolotin *parsed_results_bytes = 0; 674350bc60cbSMichal Kalderon 6744a3f72307SDenis Bolotin if (!meta->is_allocated) 674550bc60cbSMichal Kalderon return DBG_STATUS_MCP_TRACE_BAD_DATA; 674650bc60cbSMichal Kalderon 674750bc60cbSMichal Kalderon status = DBG_STATUS_OK; 674850bc60cbSMichal Kalderon 674950bc60cbSMichal Kalderon while (data_size) { 675050bc60cbSMichal Kalderon struct mcp_trace_format *format_ptr; 675150bc60cbSMichal Kalderon u8 format_level, format_module; 675250bc60cbSMichal Kalderon u32 params[3] = { 0, 0, 0 }; 675350bc60cbSMichal Kalderon u32 header, format_idx, i; 675450bc60cbSMichal Kalderon 675550bc60cbSMichal Kalderon if (data_size < MFW_TRACE_ENTRY_SIZE) 675650bc60cbSMichal Kalderon return DBG_STATUS_MCP_TRACE_BAD_DATA; 675750bc60cbSMichal Kalderon 675850bc60cbSMichal Kalderon header = qed_read_from_cyclic_buf(trace_buf, 675950bc60cbSMichal Kalderon &data_offset, 676050bc60cbSMichal Kalderon trace_buf_size, 676150bc60cbSMichal Kalderon MFW_TRACE_ENTRY_SIZE); 676250bc60cbSMichal Kalderon data_size -= MFW_TRACE_ENTRY_SIZE; 676350bc60cbSMichal Kalderon format_idx = header & MFW_TRACE_EVENTID_MASK; 676450bc60cbSMichal Kalderon 676550bc60cbSMichal Kalderon /* Skip message if its index doesn't exist in the meta data */ 6766a3f72307SDenis Bolotin if (format_idx >= meta->formats_num) { 676750bc60cbSMichal Kalderon u8 format_size = 676850bc60cbSMichal Kalderon (u8)((header & MFW_TRACE_PRM_SIZE_MASK) >> 676950bc60cbSMichal Kalderon MFW_TRACE_PRM_SIZE_SHIFT); 677050bc60cbSMichal Kalderon 677150bc60cbSMichal Kalderon if (data_size < format_size) 677250bc60cbSMichal Kalderon return DBG_STATUS_MCP_TRACE_BAD_DATA; 677350bc60cbSMichal Kalderon 677450bc60cbSMichal Kalderon data_offset = qed_cyclic_add(data_offset, 677550bc60cbSMichal Kalderon format_size, 677650bc60cbSMichal Kalderon trace_buf_size); 677750bc60cbSMichal Kalderon data_size -= format_size; 677850bc60cbSMichal Kalderon continue; 677950bc60cbSMichal Kalderon } 678050bc60cbSMichal Kalderon 6781a3f72307SDenis Bolotin format_ptr = &meta->formats[format_idx]; 678250bc60cbSMichal Kalderon 678350bc60cbSMichal Kalderon for (i = 0, 678450bc60cbSMichal Kalderon param_mask = MCP_TRACE_FORMAT_P1_SIZE_MASK, 678550bc60cbSMichal Kalderon param_shift = MCP_TRACE_FORMAT_P1_SIZE_SHIFT; 678650bc60cbSMichal Kalderon i < MCP_TRACE_FORMAT_MAX_PARAMS; 678750bc60cbSMichal Kalderon i++, 678850bc60cbSMichal Kalderon param_mask <<= MCP_TRACE_FORMAT_PARAM_WIDTH, 678950bc60cbSMichal Kalderon param_shift += MCP_TRACE_FORMAT_PARAM_WIDTH) { 679050bc60cbSMichal Kalderon /* Extract param size (0..3) */ 679150bc60cbSMichal Kalderon u8 param_size = (u8)((format_ptr->data & param_mask) >> 679250bc60cbSMichal Kalderon param_shift); 679350bc60cbSMichal Kalderon 679450bc60cbSMichal Kalderon /* If the param size is zero, there are no other 679550bc60cbSMichal Kalderon * parameters. 679650bc60cbSMichal Kalderon */ 679750bc60cbSMichal Kalderon if (!param_size) 679850bc60cbSMichal Kalderon break; 679950bc60cbSMichal Kalderon 680050bc60cbSMichal Kalderon /* Size is encoded using 2 bits, where 3 is used to 680150bc60cbSMichal Kalderon * encode 4. 680250bc60cbSMichal Kalderon */ 680350bc60cbSMichal Kalderon if (param_size == 3) 680450bc60cbSMichal Kalderon param_size = 4; 680550bc60cbSMichal Kalderon 680650bc60cbSMichal Kalderon if (data_size < param_size) 680750bc60cbSMichal Kalderon return DBG_STATUS_MCP_TRACE_BAD_DATA; 680850bc60cbSMichal Kalderon 680950bc60cbSMichal Kalderon params[i] = qed_read_from_cyclic_buf(trace_buf, 681050bc60cbSMichal Kalderon &data_offset, 681150bc60cbSMichal Kalderon trace_buf_size, 681250bc60cbSMichal Kalderon param_size); 681350bc60cbSMichal Kalderon data_size -= param_size; 681450bc60cbSMichal Kalderon } 681550bc60cbSMichal Kalderon 681650bc60cbSMichal Kalderon format_level = (u8)((format_ptr->data & 681750bc60cbSMichal Kalderon MCP_TRACE_FORMAT_LEVEL_MASK) >> 681850bc60cbSMichal Kalderon MCP_TRACE_FORMAT_LEVEL_SHIFT); 681950bc60cbSMichal Kalderon format_module = (u8)((format_ptr->data & 682050bc60cbSMichal Kalderon MCP_TRACE_FORMAT_MODULE_MASK) >> 682150bc60cbSMichal Kalderon MCP_TRACE_FORMAT_MODULE_SHIFT); 682250bc60cbSMichal Kalderon if (format_level >= ARRAY_SIZE(s_mcp_trace_level_str)) 682350bc60cbSMichal Kalderon return DBG_STATUS_MCP_TRACE_BAD_DATA; 682450bc60cbSMichal Kalderon 682550bc60cbSMichal Kalderon /* Print current message to results buffer */ 6826a3f72307SDenis Bolotin *parsed_results_bytes += 6827a3f72307SDenis Bolotin sprintf(qed_get_buf_ptr(parsed_buf, 6828a3f72307SDenis Bolotin *parsed_results_bytes), 682950bc60cbSMichal Kalderon "%s %-8s: ", 683050bc60cbSMichal Kalderon s_mcp_trace_level_str[format_level], 6831a3f72307SDenis Bolotin meta->modules[format_module]); 6832a3f72307SDenis Bolotin *parsed_results_bytes += 6833a3f72307SDenis Bolotin sprintf(qed_get_buf_ptr(parsed_buf, *parsed_results_bytes), 683450bc60cbSMichal Kalderon format_ptr->format_str, 683550bc60cbSMichal Kalderon params[0], params[1], params[2]); 683650bc60cbSMichal Kalderon } 683750bc60cbSMichal Kalderon 683850bc60cbSMichal Kalderon /* Add string NULL terminator */ 6839a3f72307SDenis Bolotin (*parsed_results_bytes)++; 684050bc60cbSMichal Kalderon 684150bc60cbSMichal Kalderon return status; 684250bc60cbSMichal Kalderon } 684350bc60cbSMichal Kalderon 6844c965db44STomer Tayar /* Parses an MCP Trace dump buffer. 6845c965db44STomer Tayar * If result_buf is not NULL, the MCP Trace results are printed to it. 6846c965db44STomer Tayar * In any case, the required results buffer size is assigned to 6847a3f72307SDenis Bolotin * parsed_results_bytes. 6848c965db44STomer Tayar * The parsing status is returned. 6849c965db44STomer Tayar */ 6850c965db44STomer Tayar static enum dbg_status qed_parse_mcp_trace_dump(struct qed_hwfn *p_hwfn, 6851c965db44STomer Tayar u32 *dump_buf, 6852a3f72307SDenis Bolotin char *results_buf, 6853a3f72307SDenis Bolotin u32 *parsed_results_bytes, 6854a3f72307SDenis Bolotin bool free_meta_data) 6855c965db44STomer Tayar { 6856c965db44STomer Tayar const char *section_name, *param_name, *param_str_val; 685750bc60cbSMichal Kalderon u32 data_size, trace_data_dwords, trace_meta_dwords; 6858a3f72307SDenis Bolotin u32 offset, results_offset, results_buf_bytes; 685950bc60cbSMichal Kalderon u32 param_num_val, num_section_params; 6860c965db44STomer Tayar struct mcp_trace *trace; 6861c965db44STomer Tayar enum dbg_status status; 6862c965db44STomer Tayar const u32 *meta_buf; 6863c965db44STomer Tayar u8 *trace_buf; 6864c965db44STomer Tayar 6865a3f72307SDenis Bolotin *parsed_results_bytes = 0; 6866c965db44STomer Tayar 6867c965db44STomer Tayar /* Read global_params section */ 6868c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 6869c965db44STomer Tayar §ion_name, &num_section_params); 6870c965db44STomer Tayar if (strcmp(section_name, "global_params")) 6871c965db44STomer Tayar return DBG_STATUS_MCP_TRACE_BAD_DATA; 6872c965db44STomer Tayar 6873c965db44STomer Tayar /* Print global params */ 6874c965db44STomer Tayar dump_buf += qed_print_section_params(dump_buf, 6875c965db44STomer Tayar num_section_params, 6876a3f72307SDenis Bolotin results_buf, &results_offset); 6877c965db44STomer Tayar 6878c965db44STomer Tayar /* Read trace_data section */ 6879c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 6880c965db44STomer Tayar §ion_name, &num_section_params); 6881c965db44STomer Tayar if (strcmp(section_name, "mcp_trace_data") || num_section_params != 1) 6882c965db44STomer Tayar return DBG_STATUS_MCP_TRACE_BAD_DATA; 6883c965db44STomer Tayar dump_buf += qed_read_param(dump_buf, 6884c965db44STomer Tayar ¶m_name, ¶m_str_val, ¶m_num_val); 6885c965db44STomer Tayar if (strcmp(param_name, "size")) 6886c965db44STomer Tayar return DBG_STATUS_MCP_TRACE_BAD_DATA; 6887c965db44STomer Tayar trace_data_dwords = param_num_val; 6888c965db44STomer Tayar 6889c965db44STomer Tayar /* Prepare trace info */ 6890c965db44STomer Tayar trace = (struct mcp_trace *)dump_buf; 6891a3f72307SDenis Bolotin if (trace->signature != MFW_TRACE_SIGNATURE || !trace->size) 6892a3f72307SDenis Bolotin return DBG_STATUS_MCP_TRACE_BAD_DATA; 6893a3f72307SDenis Bolotin 68947b6859fbSMintz, Yuval trace_buf = (u8 *)dump_buf + sizeof(*trace); 6895c965db44STomer Tayar offset = trace->trace_oldest; 689650bc60cbSMichal Kalderon data_size = qed_cyclic_sub(trace->trace_prod, offset, trace->size); 6897c965db44STomer Tayar dump_buf += trace_data_dwords; 6898c965db44STomer Tayar 6899c965db44STomer Tayar /* Read meta_data section */ 6900c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 6901c965db44STomer Tayar §ion_name, &num_section_params); 6902c965db44STomer Tayar if (strcmp(section_name, "mcp_trace_meta")) 6903c965db44STomer Tayar return DBG_STATUS_MCP_TRACE_BAD_DATA; 6904c965db44STomer Tayar dump_buf += qed_read_param(dump_buf, 6905c965db44STomer Tayar ¶m_name, ¶m_str_val, ¶m_num_val); 69067b6859fbSMintz, Yuval if (strcmp(param_name, "size")) 6907c965db44STomer Tayar return DBG_STATUS_MCP_TRACE_BAD_DATA; 6908c965db44STomer Tayar trace_meta_dwords = param_num_val; 6909c965db44STomer Tayar 6910c965db44STomer Tayar /* Choose meta data buffer */ 6911c965db44STomer Tayar if (!trace_meta_dwords) { 6912c965db44STomer Tayar /* Dump doesn't include meta data */ 6913a3f72307SDenis Bolotin struct dbg_tools_user_data *dev_user_data = 6914a3f72307SDenis Bolotin qed_dbg_get_user_data(p_hwfn); 6915a3f72307SDenis Bolotin 6916a3f72307SDenis Bolotin if (!dev_user_data->mcp_trace_user_meta_buf) 6917c965db44STomer Tayar return DBG_STATUS_MCP_TRACE_NO_META; 6918a3f72307SDenis Bolotin 6919a3f72307SDenis Bolotin meta_buf = dev_user_data->mcp_trace_user_meta_buf; 6920c965db44STomer Tayar } else { 6921c965db44STomer Tayar /* Dump includes meta data */ 6922c965db44STomer Tayar meta_buf = dump_buf; 6923c965db44STomer Tayar } 6924c965db44STomer Tayar 6925c965db44STomer Tayar /* Allocate meta data memory */ 6926a3f72307SDenis Bolotin status = qed_mcp_trace_alloc_meta_data(p_hwfn, meta_buf); 6927c965db44STomer Tayar if (status != DBG_STATUS_OK) 6928c965db44STomer Tayar return status; 692950bc60cbSMichal Kalderon 6930a3f72307SDenis Bolotin status = qed_parse_mcp_trace_buf(p_hwfn, 6931a3f72307SDenis Bolotin trace_buf, 693250bc60cbSMichal Kalderon trace->size, 693350bc60cbSMichal Kalderon offset, 693450bc60cbSMichal Kalderon data_size, 6935a3f72307SDenis Bolotin results_buf ? 6936a3f72307SDenis Bolotin results_buf + results_offset : 693750bc60cbSMichal Kalderon NULL, 6938a3f72307SDenis Bolotin &results_buf_bytes); 693950bc60cbSMichal Kalderon if (status != DBG_STATUS_OK) 694050bc60cbSMichal Kalderon return status; 694150bc60cbSMichal Kalderon 6942a3f72307SDenis Bolotin if (free_meta_data) 6943a3f72307SDenis Bolotin qed_mcp_trace_free_meta_data(p_hwfn); 6944a3f72307SDenis Bolotin 6945a3f72307SDenis Bolotin *parsed_results_bytes = results_offset + results_buf_bytes; 694650bc60cbSMichal Kalderon 694750bc60cbSMichal Kalderon return DBG_STATUS_OK; 6948c965db44STomer Tayar } 6949c965db44STomer Tayar 6950c965db44STomer Tayar /* Parses a Reg FIFO dump buffer. 6951c965db44STomer Tayar * If result_buf is not NULL, the Reg FIFO results are printed to it. 6952c965db44STomer Tayar * In any case, the required results buffer size is assigned to 6953c965db44STomer Tayar * parsed_results_bytes. 6954c965db44STomer Tayar * The parsing status is returned. 6955c965db44STomer Tayar */ 6956da090917STomer Tayar static enum dbg_status qed_parse_reg_fifo_dump(u32 *dump_buf, 6957c965db44STomer Tayar char *results_buf, 6958c965db44STomer Tayar u32 *parsed_results_bytes) 6959c965db44STomer Tayar { 6960c965db44STomer Tayar const char *section_name, *param_name, *param_str_val; 69617b6859fbSMintz, Yuval u32 param_num_val, num_section_params, num_elements; 6962c965db44STomer Tayar struct reg_fifo_element *elements; 6963c965db44STomer Tayar u8 i, j, err_val, vf_val; 69647b6859fbSMintz, Yuval u32 results_offset = 0; 6965c965db44STomer Tayar char vf_str[4]; 6966c965db44STomer Tayar 6967c965db44STomer Tayar /* Read global_params section */ 6968c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 6969c965db44STomer Tayar §ion_name, &num_section_params); 6970c965db44STomer Tayar if (strcmp(section_name, "global_params")) 6971c965db44STomer Tayar return DBG_STATUS_REG_FIFO_BAD_DATA; 6972c965db44STomer Tayar 6973c965db44STomer Tayar /* Print global params */ 6974c965db44STomer Tayar dump_buf += qed_print_section_params(dump_buf, 6975c965db44STomer Tayar num_section_params, 6976c965db44STomer Tayar results_buf, &results_offset); 6977c965db44STomer Tayar 6978c965db44STomer Tayar /* Read reg_fifo_data section */ 6979c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 6980c965db44STomer Tayar §ion_name, &num_section_params); 6981c965db44STomer Tayar if (strcmp(section_name, "reg_fifo_data")) 6982c965db44STomer Tayar return DBG_STATUS_REG_FIFO_BAD_DATA; 6983c965db44STomer Tayar dump_buf += qed_read_param(dump_buf, 6984c965db44STomer Tayar ¶m_name, ¶m_str_val, ¶m_num_val); 6985c965db44STomer Tayar if (strcmp(param_name, "size")) 6986c965db44STomer Tayar return DBG_STATUS_REG_FIFO_BAD_DATA; 6987c965db44STomer Tayar if (param_num_val % REG_FIFO_ELEMENT_DWORDS) 6988c965db44STomer Tayar return DBG_STATUS_REG_FIFO_BAD_DATA; 6989c965db44STomer Tayar num_elements = param_num_val / REG_FIFO_ELEMENT_DWORDS; 6990c965db44STomer Tayar elements = (struct reg_fifo_element *)dump_buf; 6991c965db44STomer Tayar 6992c965db44STomer Tayar /* Decode elements */ 6993c965db44STomer Tayar for (i = 0; i < num_elements; i++) { 6994c965db44STomer Tayar bool err_printed = false; 6995c965db44STomer Tayar 6996c965db44STomer Tayar /* Discover if element belongs to a VF or a PF */ 6997c965db44STomer Tayar vf_val = GET_FIELD(elements[i].data, REG_FIFO_ELEMENT_VF); 6998c965db44STomer Tayar if (vf_val == REG_FIFO_ELEMENT_IS_PF_VF_VAL) 6999c965db44STomer Tayar sprintf(vf_str, "%s", "N/A"); 7000c965db44STomer Tayar else 7001c965db44STomer Tayar sprintf(vf_str, "%d", vf_val); 7002c965db44STomer Tayar 7003c965db44STomer Tayar /* Add parsed element to parsed buffer */ 7004c965db44STomer Tayar results_offset += 7005c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 7006c965db44STomer Tayar results_offset), 7007be086e7cSMintz, Yuval "raw: 0x%016llx, address: 0x%07x, access: %-5s, pf: %2d, vf: %s, port: %d, privilege: %-3s, protection: %-12s, master: %-4s, errors: ", 7008c965db44STomer Tayar elements[i].data, 7009be086e7cSMintz, Yuval (u32)GET_FIELD(elements[i].data, 7010c965db44STomer Tayar REG_FIFO_ELEMENT_ADDRESS) * 7011c965db44STomer Tayar REG_FIFO_ELEMENT_ADDR_FACTOR, 7012c965db44STomer Tayar s_access_strs[GET_FIELD(elements[i].data, 7013c965db44STomer Tayar REG_FIFO_ELEMENT_ACCESS)], 7014be086e7cSMintz, Yuval (u32)GET_FIELD(elements[i].data, 70157b6859fbSMintz, Yuval REG_FIFO_ELEMENT_PF), 70167b6859fbSMintz, Yuval vf_str, 7017be086e7cSMintz, Yuval (u32)GET_FIELD(elements[i].data, 7018c965db44STomer Tayar REG_FIFO_ELEMENT_PORT), 70197b6859fbSMintz, Yuval s_privilege_strs[GET_FIELD(elements[i].data, 7020c965db44STomer Tayar REG_FIFO_ELEMENT_PRIVILEGE)], 7021c965db44STomer Tayar s_protection_strs[GET_FIELD(elements[i].data, 7022c965db44STomer Tayar REG_FIFO_ELEMENT_PROTECTION)], 7023c965db44STomer Tayar s_master_strs[GET_FIELD(elements[i].data, 7024c965db44STomer Tayar REG_FIFO_ELEMENT_MASTER)]); 7025c965db44STomer Tayar 7026c965db44STomer Tayar /* Print errors */ 7027c965db44STomer Tayar for (j = 0, 7028c965db44STomer Tayar err_val = GET_FIELD(elements[i].data, 7029c965db44STomer Tayar REG_FIFO_ELEMENT_ERROR); 7030c965db44STomer Tayar j < ARRAY_SIZE(s_reg_fifo_error_strs); 7031c965db44STomer Tayar j++, err_val >>= 1) { 70327b6859fbSMintz, Yuval if (err_val & 0x1) { 7033c965db44STomer Tayar if (err_printed) 7034c965db44STomer Tayar results_offset += 70357b6859fbSMintz, Yuval sprintf(qed_get_buf_ptr 70367b6859fbSMintz, Yuval (results_buf, 70377b6859fbSMintz, Yuval results_offset), ", "); 7038c965db44STomer Tayar results_offset += 70397b6859fbSMintz, Yuval sprintf(qed_get_buf_ptr 70407b6859fbSMintz, Yuval (results_buf, results_offset), "%s", 7041c965db44STomer Tayar s_reg_fifo_error_strs[j]); 7042c965db44STomer Tayar err_printed = true; 7043c965db44STomer Tayar } 70447b6859fbSMintz, Yuval } 7045c965db44STomer Tayar 7046c965db44STomer Tayar results_offset += 7047c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, results_offset), "\n"); 7048c965db44STomer Tayar } 7049c965db44STomer Tayar 7050c965db44STomer Tayar results_offset += sprintf(qed_get_buf_ptr(results_buf, 7051c965db44STomer Tayar results_offset), 7052c965db44STomer Tayar "fifo contained %d elements", num_elements); 7053c965db44STomer Tayar 7054c965db44STomer Tayar /* Add 1 for string NULL termination */ 7055c965db44STomer Tayar *parsed_results_bytes = results_offset + 1; 70567b6859fbSMintz, Yuval 7057c965db44STomer Tayar return DBG_STATUS_OK; 7058c965db44STomer Tayar } 7059c965db44STomer Tayar 70607b6859fbSMintz, Yuval static enum dbg_status qed_parse_igu_fifo_element(struct igu_fifo_element 70617b6859fbSMintz, Yuval *element, char 70627b6859fbSMintz, Yuval *results_buf, 7063da090917STomer Tayar u32 *results_offset) 7064c965db44STomer Tayar { 70657b6859fbSMintz, Yuval const struct igu_fifo_addr_data *found_addr = NULL; 70667b6859fbSMintz, Yuval u8 source, err_type, i, is_cleanup; 70677b6859fbSMintz, Yuval char parsed_addr_data[32]; 70687b6859fbSMintz, Yuval char parsed_wr_data[256]; 70697b6859fbSMintz, Yuval u32 wr_data, prod_cons; 70707b6859fbSMintz, Yuval bool is_wr_cmd, is_pf; 70717b6859fbSMintz, Yuval u16 cmd_addr; 70727b6859fbSMintz, Yuval u64 dword12; 70737b6859fbSMintz, Yuval 70747b6859fbSMintz, Yuval /* Dword12 (dword index 1 and 2) contains bits 32..95 of the 70757b6859fbSMintz, Yuval * FIFO element. 70767b6859fbSMintz, Yuval */ 70777b6859fbSMintz, Yuval dword12 = ((u64)element->dword2 << 32) | element->dword1; 70787b6859fbSMintz, Yuval is_wr_cmd = GET_FIELD(dword12, IGU_FIFO_ELEMENT_DWORD12_IS_WR_CMD); 70797b6859fbSMintz, Yuval is_pf = GET_FIELD(element->dword0, IGU_FIFO_ELEMENT_DWORD0_IS_PF); 70807b6859fbSMintz, Yuval cmd_addr = GET_FIELD(element->dword0, IGU_FIFO_ELEMENT_DWORD0_CMD_ADDR); 70817b6859fbSMintz, Yuval source = GET_FIELD(element->dword0, IGU_FIFO_ELEMENT_DWORD0_SOURCE); 70827b6859fbSMintz, Yuval err_type = GET_FIELD(element->dword0, IGU_FIFO_ELEMENT_DWORD0_ERR_TYPE); 70837b6859fbSMintz, Yuval 70847b6859fbSMintz, Yuval if (source >= ARRAY_SIZE(s_igu_fifo_source_strs)) 70857b6859fbSMintz, Yuval return DBG_STATUS_IGU_FIFO_BAD_DATA; 70867b6859fbSMintz, Yuval if (err_type >= ARRAY_SIZE(s_igu_fifo_error_strs)) 70877b6859fbSMintz, Yuval return DBG_STATUS_IGU_FIFO_BAD_DATA; 70887b6859fbSMintz, Yuval 70897b6859fbSMintz, Yuval /* Find address data */ 70907b6859fbSMintz, Yuval for (i = 0; i < ARRAY_SIZE(s_igu_fifo_addr_data) && !found_addr; i++) { 70917b6859fbSMintz, Yuval const struct igu_fifo_addr_data *curr_addr = 70927b6859fbSMintz, Yuval &s_igu_fifo_addr_data[i]; 70937b6859fbSMintz, Yuval 70947b6859fbSMintz, Yuval if (cmd_addr >= curr_addr->start_addr && cmd_addr <= 70957b6859fbSMintz, Yuval curr_addr->end_addr) 70967b6859fbSMintz, Yuval found_addr = curr_addr; 7097c965db44STomer Tayar } 7098c965db44STomer Tayar 70997b6859fbSMintz, Yuval if (!found_addr) 71007b6859fbSMintz, Yuval return DBG_STATUS_IGU_FIFO_BAD_DATA; 7101c965db44STomer Tayar 71027b6859fbSMintz, Yuval /* Prepare parsed address data */ 71037b6859fbSMintz, Yuval switch (found_addr->type) { 71047b6859fbSMintz, Yuval case IGU_ADDR_TYPE_MSIX_MEM: 71057b6859fbSMintz, Yuval sprintf(parsed_addr_data, " vector_num = 0x%x", cmd_addr / 2); 71067b6859fbSMintz, Yuval break; 71077b6859fbSMintz, Yuval case IGU_ADDR_TYPE_WRITE_INT_ACK: 71087b6859fbSMintz, Yuval case IGU_ADDR_TYPE_WRITE_PROD_UPDATE: 71097b6859fbSMintz, Yuval sprintf(parsed_addr_data, 71107b6859fbSMintz, Yuval " SB = 0x%x", cmd_addr - found_addr->start_addr); 71117b6859fbSMintz, Yuval break; 71127b6859fbSMintz, Yuval default: 71137b6859fbSMintz, Yuval parsed_addr_data[0] = '\0'; 71147b6859fbSMintz, Yuval } 71157b6859fbSMintz, Yuval 71167b6859fbSMintz, Yuval if (!is_wr_cmd) { 71177b6859fbSMintz, Yuval parsed_wr_data[0] = '\0'; 71187b6859fbSMintz, Yuval goto out; 71197b6859fbSMintz, Yuval } 71207b6859fbSMintz, Yuval 71217b6859fbSMintz, Yuval /* Prepare parsed write data */ 71227b6859fbSMintz, Yuval wr_data = GET_FIELD(dword12, IGU_FIFO_ELEMENT_DWORD12_WR_DATA); 71237b6859fbSMintz, Yuval prod_cons = GET_FIELD(wr_data, IGU_FIFO_WR_DATA_PROD_CONS); 71247b6859fbSMintz, Yuval is_cleanup = GET_FIELD(wr_data, IGU_FIFO_WR_DATA_CMD_TYPE); 71257b6859fbSMintz, Yuval 71267b6859fbSMintz, Yuval if (source == IGU_SRC_ATTN) { 71277b6859fbSMintz, Yuval sprintf(parsed_wr_data, "prod: 0x%x, ", prod_cons); 71287b6859fbSMintz, Yuval } else { 71297b6859fbSMintz, Yuval if (is_cleanup) { 71307b6859fbSMintz, Yuval u8 cleanup_val, cleanup_type; 71317b6859fbSMintz, Yuval 71327b6859fbSMintz, Yuval cleanup_val = 71337b6859fbSMintz, Yuval GET_FIELD(wr_data, 71347b6859fbSMintz, Yuval IGU_FIFO_CLEANUP_WR_DATA_CLEANUP_VAL); 71357b6859fbSMintz, Yuval cleanup_type = 71367b6859fbSMintz, Yuval GET_FIELD(wr_data, 71377b6859fbSMintz, Yuval IGU_FIFO_CLEANUP_WR_DATA_CLEANUP_TYPE); 71387b6859fbSMintz, Yuval 71397b6859fbSMintz, Yuval sprintf(parsed_wr_data, 71407b6859fbSMintz, Yuval "cmd_type: cleanup, cleanup_val: %s, cleanup_type : %d, ", 71417b6859fbSMintz, Yuval cleanup_val ? "set" : "clear", 71427b6859fbSMintz, Yuval cleanup_type); 71437b6859fbSMintz, Yuval } else { 71447b6859fbSMintz, Yuval u8 update_flag, en_dis_int_for_sb, segment; 71457b6859fbSMintz, Yuval u8 timer_mask; 71467b6859fbSMintz, Yuval 71477b6859fbSMintz, Yuval update_flag = GET_FIELD(wr_data, 71487b6859fbSMintz, Yuval IGU_FIFO_WR_DATA_UPDATE_FLAG); 71497b6859fbSMintz, Yuval en_dis_int_for_sb = 71507b6859fbSMintz, Yuval GET_FIELD(wr_data, 71517b6859fbSMintz, Yuval IGU_FIFO_WR_DATA_EN_DIS_INT_FOR_SB); 71527b6859fbSMintz, Yuval segment = GET_FIELD(wr_data, 71537b6859fbSMintz, Yuval IGU_FIFO_WR_DATA_SEGMENT); 71547b6859fbSMintz, Yuval timer_mask = GET_FIELD(wr_data, 71557b6859fbSMintz, Yuval IGU_FIFO_WR_DATA_TIMER_MASK); 71567b6859fbSMintz, Yuval 71577b6859fbSMintz, Yuval sprintf(parsed_wr_data, 71587b6859fbSMintz, Yuval "cmd_type: prod/cons update, prod/cons: 0x%x, update_flag: %s, en_dis_int_for_sb : %s, segment : %s, timer_mask = %d, ", 71597b6859fbSMintz, Yuval prod_cons, 71607b6859fbSMintz, Yuval update_flag ? "update" : "nop", 7161da090917STomer Tayar en_dis_int_for_sb ? 7162da090917STomer Tayar (en_dis_int_for_sb == 1 ? "disable" : "nop") : 7163da090917STomer Tayar "enable", 71647b6859fbSMintz, Yuval segment ? "attn" : "regular", 71657b6859fbSMintz, Yuval timer_mask); 71667b6859fbSMintz, Yuval } 71677b6859fbSMintz, Yuval } 71687b6859fbSMintz, Yuval out: 71697b6859fbSMintz, Yuval /* Add parsed element to parsed buffer */ 71707b6859fbSMintz, Yuval *results_offset += sprintf(qed_get_buf_ptr(results_buf, 71717b6859fbSMintz, Yuval *results_offset), 71727b6859fbSMintz, Yuval "raw: 0x%01x%08x%08x, %s: %d, source : %s, type : %s, cmd_addr : 0x%x(%s%s), %serror: %s\n", 71737b6859fbSMintz, Yuval element->dword2, element->dword1, 71747b6859fbSMintz, Yuval element->dword0, 71757b6859fbSMintz, Yuval is_pf ? "pf" : "vf", 71767b6859fbSMintz, Yuval GET_FIELD(element->dword0, 71777b6859fbSMintz, Yuval IGU_FIFO_ELEMENT_DWORD0_FID), 71787b6859fbSMintz, Yuval s_igu_fifo_source_strs[source], 71797b6859fbSMintz, Yuval is_wr_cmd ? "wr" : "rd", 71807b6859fbSMintz, Yuval cmd_addr, 71817b6859fbSMintz, Yuval (!is_pf && found_addr->vf_desc) 71827b6859fbSMintz, Yuval ? found_addr->vf_desc 71837b6859fbSMintz, Yuval : found_addr->desc, 71847b6859fbSMintz, Yuval parsed_addr_data, 71857b6859fbSMintz, Yuval parsed_wr_data, 71867b6859fbSMintz, Yuval s_igu_fifo_error_strs[err_type]); 71877b6859fbSMintz, Yuval 71887b6859fbSMintz, Yuval return DBG_STATUS_OK; 7189c965db44STomer Tayar } 7190c965db44STomer Tayar 7191c965db44STomer Tayar /* Parses an IGU FIFO dump buffer. 7192c965db44STomer Tayar * If result_buf is not NULL, the IGU FIFO results are printed to it. 7193c965db44STomer Tayar * In any case, the required results buffer size is assigned to 7194c965db44STomer Tayar * parsed_results_bytes. 7195c965db44STomer Tayar * The parsing status is returned. 7196c965db44STomer Tayar */ 7197da090917STomer Tayar static enum dbg_status qed_parse_igu_fifo_dump(u32 *dump_buf, 7198c965db44STomer Tayar char *results_buf, 7199c965db44STomer Tayar u32 *parsed_results_bytes) 7200c965db44STomer Tayar { 7201c965db44STomer Tayar const char *section_name, *param_name, *param_str_val; 72027b6859fbSMintz, Yuval u32 param_num_val, num_section_params, num_elements; 7203c965db44STomer Tayar struct igu_fifo_element *elements; 72047b6859fbSMintz, Yuval enum dbg_status status; 72057b6859fbSMintz, Yuval u32 results_offset = 0; 72067b6859fbSMintz, Yuval u8 i; 7207c965db44STomer Tayar 7208c965db44STomer Tayar /* Read global_params section */ 7209c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 7210c965db44STomer Tayar §ion_name, &num_section_params); 7211c965db44STomer Tayar if (strcmp(section_name, "global_params")) 7212c965db44STomer Tayar return DBG_STATUS_IGU_FIFO_BAD_DATA; 7213c965db44STomer Tayar 7214c965db44STomer Tayar /* Print global params */ 7215c965db44STomer Tayar dump_buf += qed_print_section_params(dump_buf, 7216c965db44STomer Tayar num_section_params, 7217c965db44STomer Tayar results_buf, &results_offset); 7218c965db44STomer Tayar 7219c965db44STomer Tayar /* Read igu_fifo_data section */ 7220c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 7221c965db44STomer Tayar §ion_name, &num_section_params); 7222c965db44STomer Tayar if (strcmp(section_name, "igu_fifo_data")) 7223c965db44STomer Tayar return DBG_STATUS_IGU_FIFO_BAD_DATA; 7224c965db44STomer Tayar dump_buf += qed_read_param(dump_buf, 7225c965db44STomer Tayar ¶m_name, ¶m_str_val, ¶m_num_val); 7226c965db44STomer Tayar if (strcmp(param_name, "size")) 7227c965db44STomer Tayar return DBG_STATUS_IGU_FIFO_BAD_DATA; 7228c965db44STomer Tayar if (param_num_val % IGU_FIFO_ELEMENT_DWORDS) 7229c965db44STomer Tayar return DBG_STATUS_IGU_FIFO_BAD_DATA; 7230c965db44STomer Tayar num_elements = param_num_val / IGU_FIFO_ELEMENT_DWORDS; 7231c965db44STomer Tayar elements = (struct igu_fifo_element *)dump_buf; 7232c965db44STomer Tayar 7233c965db44STomer Tayar /* Decode elements */ 7234c965db44STomer Tayar for (i = 0; i < num_elements; i++) { 72357b6859fbSMintz, Yuval status = qed_parse_igu_fifo_element(&elements[i], 72367b6859fbSMintz, Yuval results_buf, 7237da090917STomer Tayar &results_offset); 72387b6859fbSMintz, Yuval if (status != DBG_STATUS_OK) 72397b6859fbSMintz, Yuval return status; 7240c965db44STomer Tayar } 7241c965db44STomer Tayar 7242c965db44STomer Tayar results_offset += sprintf(qed_get_buf_ptr(results_buf, 7243c965db44STomer Tayar results_offset), 7244c965db44STomer Tayar "fifo contained %d elements", num_elements); 7245c965db44STomer Tayar 7246c965db44STomer Tayar /* Add 1 for string NULL termination */ 7247c965db44STomer Tayar *parsed_results_bytes = results_offset + 1; 72487b6859fbSMintz, Yuval 7249c965db44STomer Tayar return DBG_STATUS_OK; 7250c965db44STomer Tayar } 7251c965db44STomer Tayar 7252c965db44STomer Tayar static enum dbg_status 7253da090917STomer Tayar qed_parse_protection_override_dump(u32 *dump_buf, 7254c965db44STomer Tayar char *results_buf, 7255c965db44STomer Tayar u32 *parsed_results_bytes) 7256c965db44STomer Tayar { 7257c965db44STomer Tayar const char *section_name, *param_name, *param_str_val; 72587b6859fbSMintz, Yuval u32 param_num_val, num_section_params, num_elements; 7259c965db44STomer Tayar struct protection_override_element *elements; 72607b6859fbSMintz, Yuval u32 results_offset = 0; 7261c965db44STomer Tayar u8 i; 7262c965db44STomer Tayar 7263c965db44STomer Tayar /* Read global_params section */ 7264c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 7265c965db44STomer Tayar §ion_name, &num_section_params); 7266c965db44STomer Tayar if (strcmp(section_name, "global_params")) 7267c965db44STomer Tayar return DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA; 7268c965db44STomer Tayar 7269c965db44STomer Tayar /* Print global params */ 7270c965db44STomer Tayar dump_buf += qed_print_section_params(dump_buf, 7271c965db44STomer Tayar num_section_params, 7272c965db44STomer Tayar results_buf, &results_offset); 7273c965db44STomer Tayar 7274c965db44STomer Tayar /* Read protection_override_data section */ 7275c965db44STomer Tayar dump_buf += qed_read_section_hdr(dump_buf, 7276c965db44STomer Tayar §ion_name, &num_section_params); 7277c965db44STomer Tayar if (strcmp(section_name, "protection_override_data")) 7278c965db44STomer Tayar return DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA; 7279c965db44STomer Tayar dump_buf += qed_read_param(dump_buf, 7280c965db44STomer Tayar ¶m_name, ¶m_str_val, ¶m_num_val); 7281c965db44STomer Tayar if (strcmp(param_name, "size")) 7282c965db44STomer Tayar return DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA; 72837b6859fbSMintz, Yuval if (param_num_val % PROTECTION_OVERRIDE_ELEMENT_DWORDS) 7284c965db44STomer Tayar return DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA; 7285c965db44STomer Tayar num_elements = param_num_val / PROTECTION_OVERRIDE_ELEMENT_DWORDS; 7286c965db44STomer Tayar elements = (struct protection_override_element *)dump_buf; 7287c965db44STomer Tayar 7288c965db44STomer Tayar /* Decode elements */ 7289c965db44STomer Tayar for (i = 0; i < num_elements; i++) { 7290c965db44STomer Tayar u32 address = GET_FIELD(elements[i].data, 7291c965db44STomer Tayar PROTECTION_OVERRIDE_ELEMENT_ADDRESS) * 7292c965db44STomer Tayar PROTECTION_OVERRIDE_ELEMENT_ADDR_FACTOR; 7293c965db44STomer Tayar 7294c965db44STomer Tayar results_offset += 7295c965db44STomer Tayar sprintf(qed_get_buf_ptr(results_buf, 7296c965db44STomer Tayar results_offset), 7297be086e7cSMintz, Yuval "window %2d, address: 0x%07x, size: %7d regs, read: %d, write: %d, read protection: %-12s, write protection: %-12s\n", 7298c965db44STomer Tayar i, address, 7299be086e7cSMintz, Yuval (u32)GET_FIELD(elements[i].data, 7300c965db44STomer Tayar PROTECTION_OVERRIDE_ELEMENT_WINDOW_SIZE), 7301be086e7cSMintz, Yuval (u32)GET_FIELD(elements[i].data, 7302c965db44STomer Tayar PROTECTION_OVERRIDE_ELEMENT_READ), 7303be086e7cSMintz, Yuval (u32)GET_FIELD(elements[i].data, 7304c965db44STomer Tayar PROTECTION_OVERRIDE_ELEMENT_WRITE), 7305c965db44STomer Tayar s_protection_strs[GET_FIELD(elements[i].data, 7306c965db44STomer Tayar PROTECTION_OVERRIDE_ELEMENT_READ_PROTECTION)], 7307c965db44STomer Tayar s_protection_strs[GET_FIELD(elements[i].data, 7308c965db44STomer Tayar PROTECTION_OVERRIDE_ELEMENT_WRITE_PROTECTION)]); 7309c965db44STomer Tayar } 7310c965db44STomer Tayar 7311c965db44STomer Tayar results_offset += sprintf(qed_get_buf_ptr(results_buf, 7312c965db44STomer Tayar results_offset), 7313c965db44STomer Tayar "protection override contained %d elements", 7314c965db44STomer Tayar num_elements); 7315c965db44STomer Tayar 7316c965db44STomer Tayar /* Add 1 for string NULL termination */ 7317c965db44STomer Tayar *parsed_results_bytes = results_offset + 1; 73187b6859fbSMintz, Yuval 7319c965db44STomer Tayar return DBG_STATUS_OK; 7320c965db44STomer Tayar } 7321c965db44STomer Tayar 73227b6859fbSMintz, Yuval /* Parses a FW Asserts dump buffer. 73237b6859fbSMintz, Yuval * If result_buf is not NULL, the FW Asserts results are printed to it. 73247b6859fbSMintz, Yuval * In any case, the required results buffer size is assigned to 73257b6859fbSMintz, Yuval * parsed_results_bytes. 73267b6859fbSMintz, Yuval * The parsing status is returned. 73277b6859fbSMintz, Yuval */ 7328da090917STomer Tayar static enum dbg_status qed_parse_fw_asserts_dump(u32 *dump_buf, 73297b6859fbSMintz, Yuval char *results_buf, 73307b6859fbSMintz, Yuval u32 *parsed_results_bytes) 73317b6859fbSMintz, Yuval { 73327b6859fbSMintz, Yuval u32 num_section_params, param_num_val, i, results_offset = 0; 73337b6859fbSMintz, Yuval const char *param_name, *param_str_val, *section_name; 73347b6859fbSMintz, Yuval bool last_section_found = false; 73357b6859fbSMintz, Yuval 73367b6859fbSMintz, Yuval *parsed_results_bytes = 0; 73377b6859fbSMintz, Yuval 73387b6859fbSMintz, Yuval /* Read global_params section */ 73397b6859fbSMintz, Yuval dump_buf += qed_read_section_hdr(dump_buf, 73407b6859fbSMintz, Yuval §ion_name, &num_section_params); 73417b6859fbSMintz, Yuval if (strcmp(section_name, "global_params")) 73427b6859fbSMintz, Yuval return DBG_STATUS_FW_ASSERTS_PARSE_FAILED; 73437b6859fbSMintz, Yuval 73447b6859fbSMintz, Yuval /* Print global params */ 73457b6859fbSMintz, Yuval dump_buf += qed_print_section_params(dump_buf, 73467b6859fbSMintz, Yuval num_section_params, 73477b6859fbSMintz, Yuval results_buf, &results_offset); 73487b6859fbSMintz, Yuval 73497b6859fbSMintz, Yuval while (!last_section_found) { 73507b6859fbSMintz, Yuval dump_buf += qed_read_section_hdr(dump_buf, 73517b6859fbSMintz, Yuval §ion_name, 73527b6859fbSMintz, Yuval &num_section_params); 73537b6859fbSMintz, Yuval if (!strcmp(section_name, "fw_asserts")) { 73547b6859fbSMintz, Yuval /* Extract params */ 73557b6859fbSMintz, Yuval const char *storm_letter = NULL; 73567b6859fbSMintz, Yuval u32 storm_dump_size = 0; 73577b6859fbSMintz, Yuval 73587b6859fbSMintz, Yuval for (i = 0; i < num_section_params; i++) { 73597b6859fbSMintz, Yuval dump_buf += qed_read_param(dump_buf, 73607b6859fbSMintz, Yuval ¶m_name, 73617b6859fbSMintz, Yuval ¶m_str_val, 73627b6859fbSMintz, Yuval ¶m_num_val); 73637b6859fbSMintz, Yuval if (!strcmp(param_name, "storm")) 73647b6859fbSMintz, Yuval storm_letter = param_str_val; 73657b6859fbSMintz, Yuval else if (!strcmp(param_name, "size")) 73667b6859fbSMintz, Yuval storm_dump_size = param_num_val; 73677b6859fbSMintz, Yuval else 73687b6859fbSMintz, Yuval return 73697b6859fbSMintz, Yuval DBG_STATUS_FW_ASSERTS_PARSE_FAILED; 73707b6859fbSMintz, Yuval } 73717b6859fbSMintz, Yuval 73727b6859fbSMintz, Yuval if (!storm_letter || !storm_dump_size) 73737b6859fbSMintz, Yuval return DBG_STATUS_FW_ASSERTS_PARSE_FAILED; 73747b6859fbSMintz, Yuval 73757b6859fbSMintz, Yuval /* Print data */ 73767b6859fbSMintz, Yuval results_offset += 73777b6859fbSMintz, Yuval sprintf(qed_get_buf_ptr(results_buf, 73787b6859fbSMintz, Yuval results_offset), 73797b6859fbSMintz, Yuval "\n%sSTORM_ASSERT: size=%d\n", 73807b6859fbSMintz, Yuval storm_letter, storm_dump_size); 73817b6859fbSMintz, Yuval for (i = 0; i < storm_dump_size; i++, dump_buf++) 73827b6859fbSMintz, Yuval results_offset += 73837b6859fbSMintz, Yuval sprintf(qed_get_buf_ptr(results_buf, 73847b6859fbSMintz, Yuval results_offset), 73857b6859fbSMintz, Yuval "%08x\n", *dump_buf); 73867b6859fbSMintz, Yuval } else if (!strcmp(section_name, "last")) { 73877b6859fbSMintz, Yuval last_section_found = true; 73887b6859fbSMintz, Yuval } else { 73897b6859fbSMintz, Yuval return DBG_STATUS_FW_ASSERTS_PARSE_FAILED; 73907b6859fbSMintz, Yuval } 73917b6859fbSMintz, Yuval } 73927b6859fbSMintz, Yuval 73937b6859fbSMintz, Yuval /* Add 1 for string NULL termination */ 73947b6859fbSMintz, Yuval *parsed_results_bytes = results_offset + 1; 73957b6859fbSMintz, Yuval 73967b6859fbSMintz, Yuval return DBG_STATUS_OK; 73977b6859fbSMintz, Yuval } 73987b6859fbSMintz, Yuval 73997b6859fbSMintz, Yuval /***************************** Public Functions *******************************/ 74007b6859fbSMintz, Yuval 74017b6859fbSMintz, Yuval enum dbg_status qed_dbg_user_set_bin_ptr(const u8 * const bin_ptr) 74027b6859fbSMintz, Yuval { 74037b6859fbSMintz, Yuval struct bin_buffer_hdr *buf_array = (struct bin_buffer_hdr *)bin_ptr; 74047b6859fbSMintz, Yuval u8 buf_id; 74057b6859fbSMintz, Yuval 74067b6859fbSMintz, Yuval /* Convert binary data to debug arrays */ 74077b6859fbSMintz, Yuval for (buf_id = 0; buf_id < MAX_BIN_DBG_BUFFER_TYPE; buf_id++) { 74087b6859fbSMintz, Yuval s_user_dbg_arrays[buf_id].ptr = 74097b6859fbSMintz, Yuval (u32 *)(bin_ptr + buf_array[buf_id].offset); 74107b6859fbSMintz, Yuval s_user_dbg_arrays[buf_id].size_in_dwords = 74117b6859fbSMintz, Yuval BYTES_TO_DWORDS(buf_array[buf_id].length); 74127b6859fbSMintz, Yuval } 74137b6859fbSMintz, Yuval 74147b6859fbSMintz, Yuval return DBG_STATUS_OK; 74157b6859fbSMintz, Yuval } 74167b6859fbSMintz, Yuval 7417a3f72307SDenis Bolotin enum dbg_status qed_dbg_alloc_user_data(struct qed_hwfn *p_hwfn) 7418a3f72307SDenis Bolotin { 7419a3f72307SDenis Bolotin p_hwfn->dbg_user_info = kzalloc(sizeof(struct dbg_tools_user_data), 7420a3f72307SDenis Bolotin GFP_KERNEL); 7421a3f72307SDenis Bolotin if (!p_hwfn->dbg_user_info) 7422a3f72307SDenis Bolotin return DBG_STATUS_VIRT_MEM_ALLOC_FAILED; 7423a3f72307SDenis Bolotin 7424a3f72307SDenis Bolotin return DBG_STATUS_OK; 7425a3f72307SDenis Bolotin } 7426a3f72307SDenis Bolotin 74277b6859fbSMintz, Yuval const char *qed_dbg_get_status_str(enum dbg_status status) 74287b6859fbSMintz, Yuval { 74297b6859fbSMintz, Yuval return (status < 74307b6859fbSMintz, Yuval MAX_DBG_STATUS) ? s_status_str[status] : "Invalid debug status"; 74317b6859fbSMintz, Yuval } 74327b6859fbSMintz, Yuval 74337b6859fbSMintz, Yuval enum dbg_status qed_get_idle_chk_results_buf_size(struct qed_hwfn *p_hwfn, 74347b6859fbSMintz, Yuval u32 *dump_buf, 74357b6859fbSMintz, Yuval u32 num_dumped_dwords, 74367b6859fbSMintz, Yuval u32 *results_buf_size) 74377b6859fbSMintz, Yuval { 74387b6859fbSMintz, Yuval u32 num_errors, num_warnings; 74397b6859fbSMintz, Yuval 7440da090917STomer Tayar return qed_parse_idle_chk_dump(dump_buf, 74417b6859fbSMintz, Yuval num_dumped_dwords, 74427b6859fbSMintz, Yuval NULL, 74437b6859fbSMintz, Yuval results_buf_size, 74447b6859fbSMintz, Yuval &num_errors, &num_warnings); 74457b6859fbSMintz, Yuval } 74467b6859fbSMintz, Yuval 74477b6859fbSMintz, Yuval enum dbg_status qed_print_idle_chk_results(struct qed_hwfn *p_hwfn, 74487b6859fbSMintz, Yuval u32 *dump_buf, 74497b6859fbSMintz, Yuval u32 num_dumped_dwords, 74507b6859fbSMintz, Yuval char *results_buf, 7451da090917STomer Tayar u32 *num_errors, 7452da090917STomer Tayar u32 *num_warnings) 74537b6859fbSMintz, Yuval { 74547b6859fbSMintz, Yuval u32 parsed_buf_size; 74557b6859fbSMintz, Yuval 7456da090917STomer Tayar return qed_parse_idle_chk_dump(dump_buf, 74577b6859fbSMintz, Yuval num_dumped_dwords, 74587b6859fbSMintz, Yuval results_buf, 74597b6859fbSMintz, Yuval &parsed_buf_size, 74607b6859fbSMintz, Yuval num_errors, num_warnings); 74617b6859fbSMintz, Yuval } 74627b6859fbSMintz, Yuval 7463a3f72307SDenis Bolotin void qed_dbg_mcp_trace_set_meta_data(struct qed_hwfn *p_hwfn, 7464a3f72307SDenis Bolotin const u32 *meta_buf) 74657b6859fbSMintz, Yuval { 7466a3f72307SDenis Bolotin struct dbg_tools_user_data *dev_user_data = 7467a3f72307SDenis Bolotin qed_dbg_get_user_data(p_hwfn); 7468a3f72307SDenis Bolotin 7469a3f72307SDenis Bolotin dev_user_data->mcp_trace_user_meta_buf = meta_buf; 74707b6859fbSMintz, Yuval } 74717b6859fbSMintz, Yuval 74727b6859fbSMintz, Yuval enum dbg_status qed_get_mcp_trace_results_buf_size(struct qed_hwfn *p_hwfn, 74737b6859fbSMintz, Yuval u32 *dump_buf, 74747b6859fbSMintz, Yuval u32 num_dumped_dwords, 74757b6859fbSMintz, Yuval u32 *results_buf_size) 74767b6859fbSMintz, Yuval { 74777b6859fbSMintz, Yuval return qed_parse_mcp_trace_dump(p_hwfn, 7478a3f72307SDenis Bolotin dump_buf, NULL, results_buf_size, true); 74797b6859fbSMintz, Yuval } 74807b6859fbSMintz, Yuval 74817b6859fbSMintz, Yuval enum dbg_status qed_print_mcp_trace_results(struct qed_hwfn *p_hwfn, 74827b6859fbSMintz, Yuval u32 *dump_buf, 74837b6859fbSMintz, Yuval u32 num_dumped_dwords, 74847b6859fbSMintz, Yuval char *results_buf) 74857b6859fbSMintz, Yuval { 74867b6859fbSMintz, Yuval u32 parsed_buf_size; 74877b6859fbSMintz, Yuval 74887b6859fbSMintz, Yuval return qed_parse_mcp_trace_dump(p_hwfn, 74897b6859fbSMintz, Yuval dump_buf, 7490a3f72307SDenis Bolotin results_buf, &parsed_buf_size, true); 74917b6859fbSMintz, Yuval } 74927b6859fbSMintz, Yuval 7493a3f72307SDenis Bolotin enum dbg_status qed_print_mcp_trace_results_cont(struct qed_hwfn *p_hwfn, 7494a3f72307SDenis Bolotin u32 *dump_buf, 7495a3f72307SDenis Bolotin char *results_buf) 7496a3f72307SDenis Bolotin { 7497a3f72307SDenis Bolotin u32 parsed_buf_size; 7498a3f72307SDenis Bolotin 7499a3f72307SDenis Bolotin return qed_parse_mcp_trace_dump(p_hwfn, dump_buf, results_buf, 7500a3f72307SDenis Bolotin &parsed_buf_size, false); 7501a3f72307SDenis Bolotin } 7502a3f72307SDenis Bolotin 7503a3f72307SDenis Bolotin enum dbg_status qed_print_mcp_trace_line(struct qed_hwfn *p_hwfn, 7504a3f72307SDenis Bolotin u8 *dump_buf, 750550bc60cbSMichal Kalderon u32 num_dumped_bytes, 750650bc60cbSMichal Kalderon char *results_buf) 750750bc60cbSMichal Kalderon { 7508a3f72307SDenis Bolotin u32 parsed_results_bytes; 750950bc60cbSMichal Kalderon 7510a3f72307SDenis Bolotin return qed_parse_mcp_trace_buf(p_hwfn, 7511a3f72307SDenis Bolotin dump_buf, 751250bc60cbSMichal Kalderon num_dumped_bytes, 751350bc60cbSMichal Kalderon 0, 751450bc60cbSMichal Kalderon num_dumped_bytes, 7515a3f72307SDenis Bolotin results_buf, &parsed_results_bytes); 7516a3f72307SDenis Bolotin } 7517a3f72307SDenis Bolotin 7518a3f72307SDenis Bolotin /* Frees the specified MCP Trace meta data */ 7519a3f72307SDenis Bolotin void qed_mcp_trace_free_meta_data(struct qed_hwfn *p_hwfn) 7520a3f72307SDenis Bolotin { 7521a3f72307SDenis Bolotin struct dbg_tools_user_data *dev_user_data; 7522a3f72307SDenis Bolotin struct mcp_trace_meta *meta; 7523a3f72307SDenis Bolotin u32 i; 7524a3f72307SDenis Bolotin 7525a3f72307SDenis Bolotin dev_user_data = qed_dbg_get_user_data(p_hwfn); 7526a3f72307SDenis Bolotin meta = &dev_user_data->mcp_trace_meta; 7527a3f72307SDenis Bolotin if (!meta->is_allocated) 7528a3f72307SDenis Bolotin return; 7529a3f72307SDenis Bolotin 7530a3f72307SDenis Bolotin /* Release modules */ 7531a3f72307SDenis Bolotin if (meta->modules) { 7532a3f72307SDenis Bolotin for (i = 0; i < meta->modules_num; i++) 7533a3f72307SDenis Bolotin kfree(meta->modules[i]); 7534a3f72307SDenis Bolotin kfree(meta->modules); 7535a3f72307SDenis Bolotin } 7536a3f72307SDenis Bolotin 7537a3f72307SDenis Bolotin /* Release formats */ 7538a3f72307SDenis Bolotin if (meta->formats) { 7539a3f72307SDenis Bolotin for (i = 0; i < meta->formats_num; i++) 7540a3f72307SDenis Bolotin kfree(meta->formats[i].format_str); 7541a3f72307SDenis Bolotin kfree(meta->formats); 7542a3f72307SDenis Bolotin } 7543a3f72307SDenis Bolotin 7544a3f72307SDenis Bolotin meta->is_allocated = false; 754550bc60cbSMichal Kalderon } 754650bc60cbSMichal Kalderon 75477b6859fbSMintz, Yuval enum dbg_status qed_get_reg_fifo_results_buf_size(struct qed_hwfn *p_hwfn, 75487b6859fbSMintz, Yuval u32 *dump_buf, 75497b6859fbSMintz, Yuval u32 num_dumped_dwords, 75507b6859fbSMintz, Yuval u32 *results_buf_size) 75517b6859fbSMintz, Yuval { 7552da090917STomer Tayar return qed_parse_reg_fifo_dump(dump_buf, NULL, results_buf_size); 75537b6859fbSMintz, Yuval } 75547b6859fbSMintz, Yuval 75557b6859fbSMintz, Yuval enum dbg_status qed_print_reg_fifo_results(struct qed_hwfn *p_hwfn, 75567b6859fbSMintz, Yuval u32 *dump_buf, 75577b6859fbSMintz, Yuval u32 num_dumped_dwords, 75587b6859fbSMintz, Yuval char *results_buf) 75597b6859fbSMintz, Yuval { 75607b6859fbSMintz, Yuval u32 parsed_buf_size; 75617b6859fbSMintz, Yuval 7562da090917STomer Tayar return qed_parse_reg_fifo_dump(dump_buf, results_buf, &parsed_buf_size); 75637b6859fbSMintz, Yuval } 75647b6859fbSMintz, Yuval 75657b6859fbSMintz, Yuval enum dbg_status qed_get_igu_fifo_results_buf_size(struct qed_hwfn *p_hwfn, 75667b6859fbSMintz, Yuval u32 *dump_buf, 75677b6859fbSMintz, Yuval u32 num_dumped_dwords, 75687b6859fbSMintz, Yuval u32 *results_buf_size) 75697b6859fbSMintz, Yuval { 7570da090917STomer Tayar return qed_parse_igu_fifo_dump(dump_buf, NULL, results_buf_size); 75717b6859fbSMintz, Yuval } 75727b6859fbSMintz, Yuval 75737b6859fbSMintz, Yuval enum dbg_status qed_print_igu_fifo_results(struct qed_hwfn *p_hwfn, 75747b6859fbSMintz, Yuval u32 *dump_buf, 75757b6859fbSMintz, Yuval u32 num_dumped_dwords, 75767b6859fbSMintz, Yuval char *results_buf) 75777b6859fbSMintz, Yuval { 75787b6859fbSMintz, Yuval u32 parsed_buf_size; 75797b6859fbSMintz, Yuval 7580da090917STomer Tayar return qed_parse_igu_fifo_dump(dump_buf, results_buf, &parsed_buf_size); 75817b6859fbSMintz, Yuval } 75827b6859fbSMintz, Yuval 7583c965db44STomer Tayar enum dbg_status 7584c965db44STomer Tayar qed_get_protection_override_results_buf_size(struct qed_hwfn *p_hwfn, 7585c965db44STomer Tayar u32 *dump_buf, 7586c965db44STomer Tayar u32 num_dumped_dwords, 7587c965db44STomer Tayar u32 *results_buf_size) 7588c965db44STomer Tayar { 7589da090917STomer Tayar return qed_parse_protection_override_dump(dump_buf, 7590c965db44STomer Tayar NULL, results_buf_size); 7591c965db44STomer Tayar } 7592c965db44STomer Tayar 7593c965db44STomer Tayar enum dbg_status qed_print_protection_override_results(struct qed_hwfn *p_hwfn, 7594c965db44STomer Tayar u32 *dump_buf, 7595c965db44STomer Tayar u32 num_dumped_dwords, 7596c965db44STomer Tayar char *results_buf) 7597c965db44STomer Tayar { 7598c965db44STomer Tayar u32 parsed_buf_size; 7599c965db44STomer Tayar 7600da090917STomer Tayar return qed_parse_protection_override_dump(dump_buf, 7601c965db44STomer Tayar results_buf, 7602c965db44STomer Tayar &parsed_buf_size); 7603c965db44STomer Tayar } 7604c965db44STomer Tayar 7605c965db44STomer Tayar enum dbg_status qed_get_fw_asserts_results_buf_size(struct qed_hwfn *p_hwfn, 7606c965db44STomer Tayar u32 *dump_buf, 7607c965db44STomer Tayar u32 num_dumped_dwords, 7608c965db44STomer Tayar u32 *results_buf_size) 7609c965db44STomer Tayar { 7610da090917STomer Tayar return qed_parse_fw_asserts_dump(dump_buf, NULL, results_buf_size); 7611c965db44STomer Tayar } 7612c965db44STomer Tayar 7613c965db44STomer Tayar enum dbg_status qed_print_fw_asserts_results(struct qed_hwfn *p_hwfn, 7614c965db44STomer Tayar u32 *dump_buf, 7615c965db44STomer Tayar u32 num_dumped_dwords, 7616c965db44STomer Tayar char *results_buf) 7617c965db44STomer Tayar { 7618c965db44STomer Tayar u32 parsed_buf_size; 7619c965db44STomer Tayar 7620da090917STomer Tayar return qed_parse_fw_asserts_dump(dump_buf, 7621c965db44STomer Tayar results_buf, &parsed_buf_size); 7622c965db44STomer Tayar } 7623c965db44STomer Tayar 76240ebbd1c8SMintz, Yuval enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn, 76250ebbd1c8SMintz, Yuval struct dbg_attn_block_result *results) 76260ebbd1c8SMintz, Yuval { 76270ebbd1c8SMintz, Yuval struct user_dbg_array *block_attn, *pstrings; 76280ebbd1c8SMintz, Yuval const u32 *block_attn_name_offsets; 76290ebbd1c8SMintz, Yuval enum dbg_attn_type attn_type; 76300ebbd1c8SMintz, Yuval const char *block_name; 76310ebbd1c8SMintz, Yuval u8 num_regs, i, j; 76320ebbd1c8SMintz, Yuval 76330ebbd1c8SMintz, Yuval num_regs = GET_FIELD(results->data, DBG_ATTN_BLOCK_RESULT_NUM_REGS); 76340ebbd1c8SMintz, Yuval attn_type = (enum dbg_attn_type) 76350ebbd1c8SMintz, Yuval GET_FIELD(results->data, 76360ebbd1c8SMintz, Yuval DBG_ATTN_BLOCK_RESULT_ATTN_TYPE); 76370ebbd1c8SMintz, Yuval block_name = s_block_info_arr[results->block_id].name; 76380ebbd1c8SMintz, Yuval 76390ebbd1c8SMintz, Yuval if (!s_user_dbg_arrays[BIN_BUF_DBG_ATTN_INDEXES].ptr || 76400ebbd1c8SMintz, Yuval !s_user_dbg_arrays[BIN_BUF_DBG_ATTN_NAME_OFFSETS].ptr || 76410ebbd1c8SMintz, Yuval !s_user_dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS].ptr) 76420ebbd1c8SMintz, Yuval return DBG_STATUS_DBG_ARRAY_NOT_SET; 76430ebbd1c8SMintz, Yuval 76440ebbd1c8SMintz, Yuval block_attn = &s_user_dbg_arrays[BIN_BUF_DBG_ATTN_NAME_OFFSETS]; 76450ebbd1c8SMintz, Yuval block_attn_name_offsets = &block_attn->ptr[results->names_offset]; 76460ebbd1c8SMintz, Yuval 76470ebbd1c8SMintz, Yuval /* Go over registers with a non-zero attention status */ 76480ebbd1c8SMintz, Yuval for (i = 0; i < num_regs; i++) { 7649da090917STomer Tayar struct dbg_attn_bit_mapping *bit_mapping; 76500ebbd1c8SMintz, Yuval struct dbg_attn_reg_result *reg_result; 76510ebbd1c8SMintz, Yuval u8 num_reg_attn, bit_idx = 0; 76520ebbd1c8SMintz, Yuval 76530ebbd1c8SMintz, Yuval reg_result = &results->reg_results[i]; 76540ebbd1c8SMintz, Yuval num_reg_attn = GET_FIELD(reg_result->data, 76550ebbd1c8SMintz, Yuval DBG_ATTN_REG_RESULT_NUM_REG_ATTN); 76560ebbd1c8SMintz, Yuval block_attn = &s_user_dbg_arrays[BIN_BUF_DBG_ATTN_INDEXES]; 7657da090917STomer Tayar bit_mapping = &((struct dbg_attn_bit_mapping *) 76580ebbd1c8SMintz, Yuval block_attn->ptr)[reg_result->block_attn_offset]; 76590ebbd1c8SMintz, Yuval 76600ebbd1c8SMintz, Yuval pstrings = &s_user_dbg_arrays[BIN_BUF_DBG_PARSING_STRINGS]; 76610ebbd1c8SMintz, Yuval 76620ebbd1c8SMintz, Yuval /* Go over attention status bits */ 76630ebbd1c8SMintz, Yuval for (j = 0; j < num_reg_attn; j++) { 7664da090917STomer Tayar u16 attn_idx_val = GET_FIELD(bit_mapping[j].data, 76650ebbd1c8SMintz, Yuval DBG_ATTN_BIT_MAPPING_VAL); 76660ebbd1c8SMintz, Yuval const char *attn_name, *attn_type_str, *masked_str; 7667da090917STomer Tayar u32 attn_name_offset, sts_addr; 76680ebbd1c8SMintz, Yuval 76690ebbd1c8SMintz, Yuval /* Check if bit mask should be advanced (due to unused 76700ebbd1c8SMintz, Yuval * bits). 76710ebbd1c8SMintz, Yuval */ 7672da090917STomer Tayar if (GET_FIELD(bit_mapping[j].data, 76730ebbd1c8SMintz, Yuval DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT)) { 76740ebbd1c8SMintz, Yuval bit_idx += (u8)attn_idx_val; 76750ebbd1c8SMintz, Yuval continue; 76760ebbd1c8SMintz, Yuval } 76770ebbd1c8SMintz, Yuval 76780ebbd1c8SMintz, Yuval /* Check current bit index */ 76790ebbd1c8SMintz, Yuval if (!(reg_result->sts_val & BIT(bit_idx))) { 76800ebbd1c8SMintz, Yuval bit_idx++; 76810ebbd1c8SMintz, Yuval continue; 76820ebbd1c8SMintz, Yuval } 76830ebbd1c8SMintz, Yuval 76840ebbd1c8SMintz, Yuval /* Find attention name */ 7685da090917STomer Tayar attn_name_offset = 7686da090917STomer Tayar block_attn_name_offsets[attn_idx_val]; 76870ebbd1c8SMintz, Yuval attn_name = &((const char *) 7688da090917STomer Tayar pstrings->ptr)[attn_name_offset]; 76890ebbd1c8SMintz, Yuval attn_type_str = attn_type == ATTN_TYPE_INTERRUPT ? 76900ebbd1c8SMintz, Yuval "Interrupt" : "Parity"; 76910ebbd1c8SMintz, Yuval masked_str = reg_result->mask_val & BIT(bit_idx) ? 76920ebbd1c8SMintz, Yuval " [masked]" : ""; 76930ebbd1c8SMintz, Yuval sts_addr = GET_FIELD(reg_result->data, 76940ebbd1c8SMintz, Yuval DBG_ATTN_REG_RESULT_STS_ADDRESS); 76950ebbd1c8SMintz, Yuval DP_NOTICE(p_hwfn, 76960ebbd1c8SMintz, Yuval "%s (%s) : %s [address 0x%08x, bit %d]%s\n", 76970ebbd1c8SMintz, Yuval block_name, attn_type_str, attn_name, 76980ebbd1c8SMintz, Yuval sts_addr, bit_idx, masked_str); 76990ebbd1c8SMintz, Yuval 77000ebbd1c8SMintz, Yuval bit_idx++; 77010ebbd1c8SMintz, Yuval } 77020ebbd1c8SMintz, Yuval } 77030ebbd1c8SMintz, Yuval 77040ebbd1c8SMintz, Yuval return DBG_STATUS_OK; 77050ebbd1c8SMintz, Yuval } 77060ebbd1c8SMintz, Yuval 7707c965db44STomer Tayar /* Wrapper for unifying the idle_chk and mcp_trace api */ 77088c93beafSYuval Mintz static enum dbg_status 77098c93beafSYuval Mintz qed_print_idle_chk_results_wrapper(struct qed_hwfn *p_hwfn, 7710c965db44STomer Tayar u32 *dump_buf, 7711c965db44STomer Tayar u32 num_dumped_dwords, 7712c965db44STomer Tayar char *results_buf) 7713c965db44STomer Tayar { 7714c965db44STomer Tayar u32 num_errors, num_warnnings; 7715c965db44STomer Tayar 7716c965db44STomer Tayar return qed_print_idle_chk_results(p_hwfn, dump_buf, num_dumped_dwords, 7717c965db44STomer Tayar results_buf, &num_errors, 7718c965db44STomer Tayar &num_warnnings); 7719c965db44STomer Tayar } 7720c965db44STomer Tayar 7721c965db44STomer Tayar /* Feature meta data lookup table */ 7722c965db44STomer Tayar static struct { 7723c965db44STomer Tayar char *name; 7724c965db44STomer Tayar enum dbg_status (*get_size)(struct qed_hwfn *p_hwfn, 7725c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *size); 7726c965db44STomer Tayar enum dbg_status (*perform_dump)(struct qed_hwfn *p_hwfn, 7727c965db44STomer Tayar struct qed_ptt *p_ptt, u32 *dump_buf, 7728c965db44STomer Tayar u32 buf_size, u32 *dumped_dwords); 7729c965db44STomer Tayar enum dbg_status (*print_results)(struct qed_hwfn *p_hwfn, 7730c965db44STomer Tayar u32 *dump_buf, u32 num_dumped_dwords, 7731c965db44STomer Tayar char *results_buf); 7732c965db44STomer Tayar enum dbg_status (*results_buf_size)(struct qed_hwfn *p_hwfn, 7733c965db44STomer Tayar u32 *dump_buf, 7734c965db44STomer Tayar u32 num_dumped_dwords, 7735c965db44STomer Tayar u32 *results_buf_size); 7736c965db44STomer Tayar } qed_features_lookup[] = { 7737c965db44STomer Tayar { 7738c965db44STomer Tayar "grc", qed_dbg_grc_get_dump_buf_size, 7739c965db44STomer Tayar qed_dbg_grc_dump, NULL, NULL}, { 7740c965db44STomer Tayar "idle_chk", 7741c965db44STomer Tayar qed_dbg_idle_chk_get_dump_buf_size, 7742c965db44STomer Tayar qed_dbg_idle_chk_dump, 7743c965db44STomer Tayar qed_print_idle_chk_results_wrapper, 7744c965db44STomer Tayar qed_get_idle_chk_results_buf_size}, { 7745c965db44STomer Tayar "mcp_trace", 7746c965db44STomer Tayar qed_dbg_mcp_trace_get_dump_buf_size, 7747c965db44STomer Tayar qed_dbg_mcp_trace_dump, qed_print_mcp_trace_results, 7748c965db44STomer Tayar qed_get_mcp_trace_results_buf_size}, { 7749c965db44STomer Tayar "reg_fifo", 7750c965db44STomer Tayar qed_dbg_reg_fifo_get_dump_buf_size, 7751c965db44STomer Tayar qed_dbg_reg_fifo_dump, qed_print_reg_fifo_results, 7752c965db44STomer Tayar qed_get_reg_fifo_results_buf_size}, { 7753c965db44STomer Tayar "igu_fifo", 7754c965db44STomer Tayar qed_dbg_igu_fifo_get_dump_buf_size, 7755c965db44STomer Tayar qed_dbg_igu_fifo_dump, qed_print_igu_fifo_results, 7756c965db44STomer Tayar qed_get_igu_fifo_results_buf_size}, { 7757c965db44STomer Tayar "protection_override", 7758c965db44STomer Tayar qed_dbg_protection_override_get_dump_buf_size, 7759c965db44STomer Tayar qed_dbg_protection_override_dump, 7760c965db44STomer Tayar qed_print_protection_override_results, 7761c965db44STomer Tayar qed_get_protection_override_results_buf_size}, { 7762c965db44STomer Tayar "fw_asserts", 7763c965db44STomer Tayar qed_dbg_fw_asserts_get_dump_buf_size, 7764c965db44STomer Tayar qed_dbg_fw_asserts_dump, 7765c965db44STomer Tayar qed_print_fw_asserts_results, 7766c965db44STomer Tayar qed_get_fw_asserts_results_buf_size},}; 7767c965db44STomer Tayar 7768c965db44STomer Tayar static void qed_dbg_print_feature(u8 *p_text_buf, u32 text_size) 7769c965db44STomer Tayar { 7770c965db44STomer Tayar u32 i, precision = 80; 7771c965db44STomer Tayar 7772c965db44STomer Tayar if (!p_text_buf) 7773c965db44STomer Tayar return; 7774c965db44STomer Tayar 7775c965db44STomer Tayar pr_notice("\n%.*s", precision, p_text_buf); 7776c965db44STomer Tayar for (i = precision; i < text_size; i += precision) 7777c965db44STomer Tayar pr_cont("%.*s", precision, p_text_buf + i); 7778c965db44STomer Tayar pr_cont("\n"); 7779c965db44STomer Tayar } 7780c965db44STomer Tayar 7781c965db44STomer Tayar #define QED_RESULTS_BUF_MIN_SIZE 16 7782c965db44STomer Tayar /* Generic function for decoding debug feature info */ 77838c93beafSYuval Mintz static enum dbg_status format_feature(struct qed_hwfn *p_hwfn, 7784c965db44STomer Tayar enum qed_dbg_features feature_idx) 7785c965db44STomer Tayar { 7786c965db44STomer Tayar struct qed_dbg_feature *feature = 7787c965db44STomer Tayar &p_hwfn->cdev->dbg_params.features[feature_idx]; 7788c965db44STomer Tayar u32 text_size_bytes, null_char_pos, i; 7789c965db44STomer Tayar enum dbg_status rc; 7790c965db44STomer Tayar char *text_buf; 7791c965db44STomer Tayar 7792c965db44STomer Tayar /* Check if feature supports formatting capability */ 7793c965db44STomer Tayar if (!qed_features_lookup[feature_idx].results_buf_size) 7794c965db44STomer Tayar return DBG_STATUS_OK; 7795c965db44STomer Tayar 7796c965db44STomer Tayar /* Obtain size of formatted output */ 7797c965db44STomer Tayar rc = qed_features_lookup[feature_idx]. 7798c965db44STomer Tayar results_buf_size(p_hwfn, (u32 *)feature->dump_buf, 7799c965db44STomer Tayar feature->dumped_dwords, &text_size_bytes); 7800c965db44STomer Tayar if (rc != DBG_STATUS_OK) 7801c965db44STomer Tayar return rc; 7802c965db44STomer Tayar 7803c965db44STomer Tayar /* Make sure that the allocated size is a multiple of dword (4 bytes) */ 7804c965db44STomer Tayar null_char_pos = text_size_bytes - 1; 7805c965db44STomer Tayar text_size_bytes = (text_size_bytes + 3) & ~0x3; 7806c965db44STomer Tayar 7807c965db44STomer Tayar if (text_size_bytes < QED_RESULTS_BUF_MIN_SIZE) { 7808c965db44STomer Tayar DP_NOTICE(p_hwfn->cdev, 7809c965db44STomer Tayar "formatted size of feature was too small %d. Aborting\n", 7810c965db44STomer Tayar text_size_bytes); 7811c965db44STomer Tayar return DBG_STATUS_INVALID_ARGS; 7812c965db44STomer Tayar } 7813c965db44STomer Tayar 7814c965db44STomer Tayar /* Allocate temp text buf */ 7815c965db44STomer Tayar text_buf = vzalloc(text_size_bytes); 7816c965db44STomer Tayar if (!text_buf) 7817c965db44STomer Tayar return DBG_STATUS_VIRT_MEM_ALLOC_FAILED; 7818c965db44STomer Tayar 7819c965db44STomer Tayar /* Decode feature opcodes to string on temp buf */ 7820c965db44STomer Tayar rc = qed_features_lookup[feature_idx]. 7821c965db44STomer Tayar print_results(p_hwfn, (u32 *)feature->dump_buf, 7822c965db44STomer Tayar feature->dumped_dwords, text_buf); 7823c965db44STomer Tayar if (rc != DBG_STATUS_OK) { 7824c965db44STomer Tayar vfree(text_buf); 7825c965db44STomer Tayar return rc; 7826c965db44STomer Tayar } 7827c965db44STomer Tayar 7828c965db44STomer Tayar /* Replace the original null character with a '\n' character. 7829c965db44STomer Tayar * The bytes that were added as a result of the dword alignment are also 7830c965db44STomer Tayar * padded with '\n' characters. 7831c965db44STomer Tayar */ 7832c965db44STomer Tayar for (i = null_char_pos; i < text_size_bytes; i++) 7833c965db44STomer Tayar text_buf[i] = '\n'; 7834c965db44STomer Tayar 7835c965db44STomer Tayar /* Dump printable feature to log */ 7836c965db44STomer Tayar if (p_hwfn->cdev->dbg_params.print_data) 7837c965db44STomer Tayar qed_dbg_print_feature(text_buf, text_size_bytes); 7838c965db44STomer Tayar 7839c965db44STomer Tayar /* Free the old dump_buf and point the dump_buf to the newly allocagted 7840c965db44STomer Tayar * and formatted text buffer. 7841c965db44STomer Tayar */ 7842c965db44STomer Tayar vfree(feature->dump_buf); 7843c965db44STomer Tayar feature->dump_buf = text_buf; 7844c965db44STomer Tayar feature->buf_size = text_size_bytes; 7845c965db44STomer Tayar feature->dumped_dwords = text_size_bytes / 4; 7846c965db44STomer Tayar return rc; 7847c965db44STomer Tayar } 7848c965db44STomer Tayar 7849c965db44STomer Tayar /* Generic function for performing the dump of a debug feature. */ 78508c93beafSYuval Mintz static enum dbg_status qed_dbg_dump(struct qed_hwfn *p_hwfn, 78518c93beafSYuval Mintz struct qed_ptt *p_ptt, 7852c965db44STomer Tayar enum qed_dbg_features feature_idx) 7853c965db44STomer Tayar { 7854c965db44STomer Tayar struct qed_dbg_feature *feature = 7855c965db44STomer Tayar &p_hwfn->cdev->dbg_params.features[feature_idx]; 7856c965db44STomer Tayar u32 buf_size_dwords; 7857c965db44STomer Tayar enum dbg_status rc; 7858c965db44STomer Tayar 7859c965db44STomer Tayar DP_NOTICE(p_hwfn->cdev, "Collecting a debug feature [\"%s\"]\n", 7860c965db44STomer Tayar qed_features_lookup[feature_idx].name); 7861c965db44STomer Tayar 7862c965db44STomer Tayar /* Dump_buf was already allocated need to free (this can happen if dump 7863c965db44STomer Tayar * was called but file was never read). 7864c965db44STomer Tayar * We can't use the buffer as is since size may have changed. 7865c965db44STomer Tayar */ 7866c965db44STomer Tayar if (feature->dump_buf) { 7867c965db44STomer Tayar vfree(feature->dump_buf); 7868c965db44STomer Tayar feature->dump_buf = NULL; 7869c965db44STomer Tayar } 7870c965db44STomer Tayar 7871c965db44STomer Tayar /* Get buffer size from hsi, allocate accordingly, and perform the 7872c965db44STomer Tayar * dump. 7873c965db44STomer Tayar */ 7874c965db44STomer Tayar rc = qed_features_lookup[feature_idx].get_size(p_hwfn, p_ptt, 7875c965db44STomer Tayar &buf_size_dwords); 7876be086e7cSMintz, Yuval if (rc != DBG_STATUS_OK && rc != DBG_STATUS_NVRAM_GET_IMAGE_FAILED) 7877c965db44STomer Tayar return rc; 7878c965db44STomer Tayar feature->buf_size = buf_size_dwords * sizeof(u32); 7879c965db44STomer Tayar feature->dump_buf = vmalloc(feature->buf_size); 7880c965db44STomer Tayar if (!feature->dump_buf) 7881c965db44STomer Tayar return DBG_STATUS_VIRT_MEM_ALLOC_FAILED; 7882c965db44STomer Tayar 7883c965db44STomer Tayar rc = qed_features_lookup[feature_idx]. 7884c965db44STomer Tayar perform_dump(p_hwfn, p_ptt, (u32 *)feature->dump_buf, 7885c965db44STomer Tayar feature->buf_size / sizeof(u32), 7886c965db44STomer Tayar &feature->dumped_dwords); 7887c965db44STomer Tayar 7888c965db44STomer Tayar /* If mcp is stuck we get DBG_STATUS_NVRAM_GET_IMAGE_FAILED error. 7889c965db44STomer Tayar * In this case the buffer holds valid binary data, but we wont able 7890c965db44STomer Tayar * to parse it (since parsing relies on data in NVRAM which is only 7891c965db44STomer Tayar * accessible when MFW is responsive). skip the formatting but return 7892c965db44STomer Tayar * success so that binary data is provided. 7893c965db44STomer Tayar */ 7894c965db44STomer Tayar if (rc == DBG_STATUS_NVRAM_GET_IMAGE_FAILED) 7895c965db44STomer Tayar return DBG_STATUS_OK; 7896c965db44STomer Tayar 7897c965db44STomer Tayar if (rc != DBG_STATUS_OK) 7898c965db44STomer Tayar return rc; 7899c965db44STomer Tayar 7900c965db44STomer Tayar /* Format output */ 7901c965db44STomer Tayar rc = format_feature(p_hwfn, feature_idx); 7902c965db44STomer Tayar return rc; 7903c965db44STomer Tayar } 7904c965db44STomer Tayar 7905c965db44STomer Tayar int qed_dbg_grc(struct qed_dev *cdev, void *buffer, u32 *num_dumped_bytes) 7906c965db44STomer Tayar { 7907c965db44STomer Tayar return qed_dbg_feature(cdev, buffer, DBG_FEATURE_GRC, num_dumped_bytes); 7908c965db44STomer Tayar } 7909c965db44STomer Tayar 7910c965db44STomer Tayar int qed_dbg_grc_size(struct qed_dev *cdev) 7911c965db44STomer Tayar { 7912c965db44STomer Tayar return qed_dbg_feature_size(cdev, DBG_FEATURE_GRC); 7913c965db44STomer Tayar } 7914c965db44STomer Tayar 7915c965db44STomer Tayar int qed_dbg_idle_chk(struct qed_dev *cdev, void *buffer, u32 *num_dumped_bytes) 7916c965db44STomer Tayar { 7917c965db44STomer Tayar return qed_dbg_feature(cdev, buffer, DBG_FEATURE_IDLE_CHK, 7918c965db44STomer Tayar num_dumped_bytes); 7919c965db44STomer Tayar } 7920c965db44STomer Tayar 7921c965db44STomer Tayar int qed_dbg_idle_chk_size(struct qed_dev *cdev) 7922c965db44STomer Tayar { 7923c965db44STomer Tayar return qed_dbg_feature_size(cdev, DBG_FEATURE_IDLE_CHK); 7924c965db44STomer Tayar } 7925c965db44STomer Tayar 7926c965db44STomer Tayar int qed_dbg_reg_fifo(struct qed_dev *cdev, void *buffer, u32 *num_dumped_bytes) 7927c965db44STomer Tayar { 7928c965db44STomer Tayar return qed_dbg_feature(cdev, buffer, DBG_FEATURE_REG_FIFO, 7929c965db44STomer Tayar num_dumped_bytes); 7930c965db44STomer Tayar } 7931c965db44STomer Tayar 7932c965db44STomer Tayar int qed_dbg_reg_fifo_size(struct qed_dev *cdev) 7933c965db44STomer Tayar { 7934c965db44STomer Tayar return qed_dbg_feature_size(cdev, DBG_FEATURE_REG_FIFO); 7935c965db44STomer Tayar } 7936c965db44STomer Tayar 7937c965db44STomer Tayar int qed_dbg_igu_fifo(struct qed_dev *cdev, void *buffer, u32 *num_dumped_bytes) 7938c965db44STomer Tayar { 7939c965db44STomer Tayar return qed_dbg_feature(cdev, buffer, DBG_FEATURE_IGU_FIFO, 7940c965db44STomer Tayar num_dumped_bytes); 7941c965db44STomer Tayar } 7942c965db44STomer Tayar 7943c965db44STomer Tayar int qed_dbg_igu_fifo_size(struct qed_dev *cdev) 7944c965db44STomer Tayar { 7945c965db44STomer Tayar return qed_dbg_feature_size(cdev, DBG_FEATURE_IGU_FIFO); 7946c965db44STomer Tayar } 7947c965db44STomer Tayar 7948bf774d14SYueHaibing static int qed_dbg_nvm_image_length(struct qed_hwfn *p_hwfn, 79491ac4329aSDenis Bolotin enum qed_nvm_images image_id, u32 *length) 79501ac4329aSDenis Bolotin { 79511ac4329aSDenis Bolotin struct qed_nvm_image_att image_att; 79521ac4329aSDenis Bolotin int rc; 79531ac4329aSDenis Bolotin 79541ac4329aSDenis Bolotin *length = 0; 79551ac4329aSDenis Bolotin rc = qed_mcp_get_nvm_image_att(p_hwfn, image_id, &image_att); 79561ac4329aSDenis Bolotin if (rc) 79571ac4329aSDenis Bolotin return rc; 79581ac4329aSDenis Bolotin 79591ac4329aSDenis Bolotin *length = image_att.length; 79601ac4329aSDenis Bolotin 79611ac4329aSDenis Bolotin return rc; 79621ac4329aSDenis Bolotin } 79631ac4329aSDenis Bolotin 7964bf774d14SYueHaibing static int qed_dbg_nvm_image(struct qed_dev *cdev, void *buffer, 7965bf774d14SYueHaibing u32 *num_dumped_bytes, 7966bf774d14SYueHaibing enum qed_nvm_images image_id) 79671ac4329aSDenis Bolotin { 79681ac4329aSDenis Bolotin struct qed_hwfn *p_hwfn = 79691ac4329aSDenis Bolotin &cdev->hwfns[cdev->dbg_params.engine_for_debug]; 79701ac4329aSDenis Bolotin u32 len_rounded, i; 79711ac4329aSDenis Bolotin __be32 val; 79721ac4329aSDenis Bolotin int rc; 79731ac4329aSDenis Bolotin 79741ac4329aSDenis Bolotin *num_dumped_bytes = 0; 79751ac4329aSDenis Bolotin rc = qed_dbg_nvm_image_length(p_hwfn, image_id, &len_rounded); 79761ac4329aSDenis Bolotin if (rc) 79771ac4329aSDenis Bolotin return rc; 79781ac4329aSDenis Bolotin 79791ac4329aSDenis Bolotin DP_NOTICE(p_hwfn->cdev, 79801ac4329aSDenis Bolotin "Collecting a debug feature [\"nvram image %d\"]\n", 79811ac4329aSDenis Bolotin image_id); 79821ac4329aSDenis Bolotin 79831ac4329aSDenis Bolotin len_rounded = roundup(len_rounded, sizeof(u32)); 79841ac4329aSDenis Bolotin rc = qed_mcp_get_nvm_image(p_hwfn, image_id, buffer, len_rounded); 79851ac4329aSDenis Bolotin if (rc) 79861ac4329aSDenis Bolotin return rc; 79871ac4329aSDenis Bolotin 79881ac4329aSDenis Bolotin /* QED_NVM_IMAGE_NVM_META image is not swapped like other images */ 79891ac4329aSDenis Bolotin if (image_id != QED_NVM_IMAGE_NVM_META) 79901ac4329aSDenis Bolotin for (i = 0; i < len_rounded; i += 4) { 79911ac4329aSDenis Bolotin val = cpu_to_be32(*(u32 *)(buffer + i)); 79921ac4329aSDenis Bolotin *(u32 *)(buffer + i) = val; 79931ac4329aSDenis Bolotin } 79941ac4329aSDenis Bolotin 79951ac4329aSDenis Bolotin *num_dumped_bytes = len_rounded; 79961ac4329aSDenis Bolotin 79971ac4329aSDenis Bolotin return rc; 79981ac4329aSDenis Bolotin } 79991ac4329aSDenis Bolotin 8000c965db44STomer Tayar int qed_dbg_protection_override(struct qed_dev *cdev, void *buffer, 8001c965db44STomer Tayar u32 *num_dumped_bytes) 8002c965db44STomer Tayar { 8003c965db44STomer Tayar return qed_dbg_feature(cdev, buffer, DBG_FEATURE_PROTECTION_OVERRIDE, 8004c965db44STomer Tayar num_dumped_bytes); 8005c965db44STomer Tayar } 8006c965db44STomer Tayar 8007c965db44STomer Tayar int qed_dbg_protection_override_size(struct qed_dev *cdev) 8008c965db44STomer Tayar { 8009c965db44STomer Tayar return qed_dbg_feature_size(cdev, DBG_FEATURE_PROTECTION_OVERRIDE); 8010c965db44STomer Tayar } 8011c965db44STomer Tayar 8012c965db44STomer Tayar int qed_dbg_fw_asserts(struct qed_dev *cdev, void *buffer, 8013c965db44STomer Tayar u32 *num_dumped_bytes) 8014c965db44STomer Tayar { 8015c965db44STomer Tayar return qed_dbg_feature(cdev, buffer, DBG_FEATURE_FW_ASSERTS, 8016c965db44STomer Tayar num_dumped_bytes); 8017c965db44STomer Tayar } 8018c965db44STomer Tayar 8019c965db44STomer Tayar int qed_dbg_fw_asserts_size(struct qed_dev *cdev) 8020c965db44STomer Tayar { 8021c965db44STomer Tayar return qed_dbg_feature_size(cdev, DBG_FEATURE_FW_ASSERTS); 8022c965db44STomer Tayar } 8023c965db44STomer Tayar 8024c965db44STomer Tayar int qed_dbg_mcp_trace(struct qed_dev *cdev, void *buffer, 8025c965db44STomer Tayar u32 *num_dumped_bytes) 8026c965db44STomer Tayar { 8027c965db44STomer Tayar return qed_dbg_feature(cdev, buffer, DBG_FEATURE_MCP_TRACE, 8028c965db44STomer Tayar num_dumped_bytes); 8029c965db44STomer Tayar } 8030c965db44STomer Tayar 8031c965db44STomer Tayar int qed_dbg_mcp_trace_size(struct qed_dev *cdev) 8032c965db44STomer Tayar { 8033c965db44STomer Tayar return qed_dbg_feature_size(cdev, DBG_FEATURE_MCP_TRACE); 8034c965db44STomer Tayar } 8035c965db44STomer Tayar 8036c965db44STomer Tayar /* Defines the amount of bytes allocated for recording the length of debugfs 8037c965db44STomer Tayar * feature buffer. 8038c965db44STomer Tayar */ 8039c965db44STomer Tayar #define REGDUMP_HEADER_SIZE sizeof(u32) 8040c965db44STomer Tayar #define REGDUMP_HEADER_FEATURE_SHIFT 24 8041c965db44STomer Tayar #define REGDUMP_HEADER_ENGINE_SHIFT 31 8042c965db44STomer Tayar #define REGDUMP_HEADER_OMIT_ENGINE_SHIFT 30 8043c965db44STomer Tayar enum debug_print_features { 8044c965db44STomer Tayar OLD_MODE = 0, 8045c965db44STomer Tayar IDLE_CHK = 1, 8046c965db44STomer Tayar GRC_DUMP = 2, 8047c965db44STomer Tayar MCP_TRACE = 3, 8048c965db44STomer Tayar REG_FIFO = 4, 8049c965db44STomer Tayar PROTECTION_OVERRIDE = 5, 8050c965db44STomer Tayar IGU_FIFO = 6, 8051c965db44STomer Tayar PHY = 7, 8052c965db44STomer Tayar FW_ASSERTS = 8, 80531ac4329aSDenis Bolotin NVM_CFG1 = 9, 80541ac4329aSDenis Bolotin DEFAULT_CFG = 10, 80551ac4329aSDenis Bolotin NVM_META = 11, 8056c965db44STomer Tayar }; 8057c965db44STomer Tayar 8058c965db44STomer Tayar static u32 qed_calc_regdump_header(enum debug_print_features feature, 8059c965db44STomer Tayar int engine, u32 feature_size, u8 omit_engine) 8060c965db44STomer Tayar { 8061c965db44STomer Tayar /* Insert the engine, feature and mode inside the header and combine it 8062c965db44STomer Tayar * with feature size. 8063c965db44STomer Tayar */ 8064c965db44STomer Tayar return feature_size | (feature << REGDUMP_HEADER_FEATURE_SHIFT) | 8065c965db44STomer Tayar (omit_engine << REGDUMP_HEADER_OMIT_ENGINE_SHIFT) | 8066c965db44STomer Tayar (engine << REGDUMP_HEADER_ENGINE_SHIFT); 8067c965db44STomer Tayar } 8068c965db44STomer Tayar 8069c965db44STomer Tayar int qed_dbg_all_data(struct qed_dev *cdev, void *buffer) 8070c965db44STomer Tayar { 8071c965db44STomer Tayar u8 cur_engine, omit_engine = 0, org_engine; 80723b86bd07SSudarsana Reddy Kalluru struct qed_hwfn *p_hwfn = 80733b86bd07SSudarsana Reddy Kalluru &cdev->hwfns[cdev->dbg_params.engine_for_debug]; 80743b86bd07SSudarsana Reddy Kalluru struct dbg_tools_data *dev_data = &p_hwfn->dbg_info; 80753b86bd07SSudarsana Reddy Kalluru int grc_params[MAX_DBG_GRC_PARAMS], i; 8076c965db44STomer Tayar u32 offset = 0, feature_size; 8077c965db44STomer Tayar int rc; 8078c965db44STomer Tayar 80793b86bd07SSudarsana Reddy Kalluru for (i = 0; i < MAX_DBG_GRC_PARAMS; i++) 80803b86bd07SSudarsana Reddy Kalluru grc_params[i] = dev_data->grc.param_val[i]; 80813b86bd07SSudarsana Reddy Kalluru 8082c965db44STomer Tayar if (cdev->num_hwfns == 1) 8083c965db44STomer Tayar omit_engine = 1; 8084c965db44STomer Tayar 8085c965db44STomer Tayar org_engine = qed_get_debug_engine(cdev); 8086c965db44STomer Tayar for (cur_engine = 0; cur_engine < cdev->num_hwfns; cur_engine++) { 8087c965db44STomer Tayar /* Collect idle_chks and grcDump for each hw function */ 8088c965db44STomer Tayar DP_VERBOSE(cdev, QED_MSG_DEBUG, 8089c965db44STomer Tayar "obtaining idle_chk and grcdump for current engine\n"); 8090c965db44STomer Tayar qed_set_debug_engine(cdev, cur_engine); 8091c965db44STomer Tayar 8092c965db44STomer Tayar /* First idle_chk */ 8093c965db44STomer Tayar rc = qed_dbg_idle_chk(cdev, (u8 *)buffer + offset + 8094c965db44STomer Tayar REGDUMP_HEADER_SIZE, &feature_size); 8095c965db44STomer Tayar if (!rc) { 8096c965db44STomer Tayar *(u32 *)((u8 *)buffer + offset) = 8097c965db44STomer Tayar qed_calc_regdump_header(IDLE_CHK, cur_engine, 8098c965db44STomer Tayar feature_size, omit_engine); 8099c965db44STomer Tayar offset += (feature_size + REGDUMP_HEADER_SIZE); 8100c965db44STomer Tayar } else { 8101c965db44STomer Tayar DP_ERR(cdev, "qed_dbg_idle_chk failed. rc = %d\n", rc); 8102c965db44STomer Tayar } 8103c965db44STomer Tayar 8104c965db44STomer Tayar /* Second idle_chk */ 8105c965db44STomer Tayar rc = qed_dbg_idle_chk(cdev, (u8 *)buffer + offset + 8106c965db44STomer Tayar REGDUMP_HEADER_SIZE, &feature_size); 8107c965db44STomer Tayar if (!rc) { 8108c965db44STomer Tayar *(u32 *)((u8 *)buffer + offset) = 8109c965db44STomer Tayar qed_calc_regdump_header(IDLE_CHK, cur_engine, 8110c965db44STomer Tayar feature_size, omit_engine); 8111c965db44STomer Tayar offset += (feature_size + REGDUMP_HEADER_SIZE); 8112c965db44STomer Tayar } else { 8113c965db44STomer Tayar DP_ERR(cdev, "qed_dbg_idle_chk failed. rc = %d\n", rc); 8114c965db44STomer Tayar } 8115c965db44STomer Tayar 8116c965db44STomer Tayar /* reg_fifo dump */ 8117c965db44STomer Tayar rc = qed_dbg_reg_fifo(cdev, (u8 *)buffer + offset + 8118c965db44STomer Tayar REGDUMP_HEADER_SIZE, &feature_size); 8119c965db44STomer Tayar if (!rc) { 8120c965db44STomer Tayar *(u32 *)((u8 *)buffer + offset) = 8121c965db44STomer Tayar qed_calc_regdump_header(REG_FIFO, cur_engine, 8122c965db44STomer Tayar feature_size, omit_engine); 8123c965db44STomer Tayar offset += (feature_size + REGDUMP_HEADER_SIZE); 8124c965db44STomer Tayar } else { 8125c965db44STomer Tayar DP_ERR(cdev, "qed_dbg_reg_fifo failed. rc = %d\n", rc); 8126c965db44STomer Tayar } 8127c965db44STomer Tayar 8128c965db44STomer Tayar /* igu_fifo dump */ 8129c965db44STomer Tayar rc = qed_dbg_igu_fifo(cdev, (u8 *)buffer + offset + 8130c965db44STomer Tayar REGDUMP_HEADER_SIZE, &feature_size); 8131c965db44STomer Tayar if (!rc) { 8132c965db44STomer Tayar *(u32 *)((u8 *)buffer + offset) = 8133c965db44STomer Tayar qed_calc_regdump_header(IGU_FIFO, cur_engine, 8134c965db44STomer Tayar feature_size, omit_engine); 8135c965db44STomer Tayar offset += (feature_size + REGDUMP_HEADER_SIZE); 8136c965db44STomer Tayar } else { 8137c965db44STomer Tayar DP_ERR(cdev, "qed_dbg_igu_fifo failed. rc = %d", rc); 8138c965db44STomer Tayar } 8139c965db44STomer Tayar 8140c965db44STomer Tayar /* protection_override dump */ 8141c965db44STomer Tayar rc = qed_dbg_protection_override(cdev, (u8 *)buffer + offset + 8142c965db44STomer Tayar REGDUMP_HEADER_SIZE, 8143c965db44STomer Tayar &feature_size); 8144c965db44STomer Tayar if (!rc) { 8145c965db44STomer Tayar *(u32 *)((u8 *)buffer + offset) = 8146c965db44STomer Tayar qed_calc_regdump_header(PROTECTION_OVERRIDE, 8147c965db44STomer Tayar cur_engine, 8148c965db44STomer Tayar feature_size, omit_engine); 8149c965db44STomer Tayar offset += (feature_size + REGDUMP_HEADER_SIZE); 8150c965db44STomer Tayar } else { 8151c965db44STomer Tayar DP_ERR(cdev, 8152c965db44STomer Tayar "qed_dbg_protection_override failed. rc = %d\n", 8153c965db44STomer Tayar rc); 8154c965db44STomer Tayar } 8155c965db44STomer Tayar 8156c965db44STomer Tayar /* fw_asserts dump */ 8157c965db44STomer Tayar rc = qed_dbg_fw_asserts(cdev, (u8 *)buffer + offset + 8158c965db44STomer Tayar REGDUMP_HEADER_SIZE, &feature_size); 8159c965db44STomer Tayar if (!rc) { 8160c965db44STomer Tayar *(u32 *)((u8 *)buffer + offset) = 8161c965db44STomer Tayar qed_calc_regdump_header(FW_ASSERTS, cur_engine, 8162c965db44STomer Tayar feature_size, omit_engine); 8163c965db44STomer Tayar offset += (feature_size + REGDUMP_HEADER_SIZE); 8164c965db44STomer Tayar } else { 8165c965db44STomer Tayar DP_ERR(cdev, "qed_dbg_fw_asserts failed. rc = %d\n", 8166c965db44STomer Tayar rc); 8167c965db44STomer Tayar } 8168c965db44STomer Tayar 81693b86bd07SSudarsana Reddy Kalluru for (i = 0; i < MAX_DBG_GRC_PARAMS; i++) 81703b86bd07SSudarsana Reddy Kalluru dev_data->grc.param_val[i] = grc_params[i]; 81713b86bd07SSudarsana Reddy Kalluru 8172c965db44STomer Tayar /* GRC dump - must be last because when mcp stuck it will 8173c965db44STomer Tayar * clutter idle_chk, reg_fifo, ... 8174c965db44STomer Tayar */ 8175c965db44STomer Tayar rc = qed_dbg_grc(cdev, (u8 *)buffer + offset + 8176c965db44STomer Tayar REGDUMP_HEADER_SIZE, &feature_size); 8177c965db44STomer Tayar if (!rc) { 8178c965db44STomer Tayar *(u32 *)((u8 *)buffer + offset) = 8179c965db44STomer Tayar qed_calc_regdump_header(GRC_DUMP, cur_engine, 8180c965db44STomer Tayar feature_size, omit_engine); 8181c965db44STomer Tayar offset += (feature_size + REGDUMP_HEADER_SIZE); 8182c965db44STomer Tayar } else { 8183c965db44STomer Tayar DP_ERR(cdev, "qed_dbg_grc failed. rc = %d", rc); 8184c965db44STomer Tayar } 8185c965db44STomer Tayar } 8186c965db44STomer Tayar 818750bc60cbSMichal Kalderon qed_set_debug_engine(cdev, org_engine); 8188c965db44STomer Tayar /* mcp_trace */ 8189c965db44STomer Tayar rc = qed_dbg_mcp_trace(cdev, (u8 *)buffer + offset + 8190c965db44STomer Tayar REGDUMP_HEADER_SIZE, &feature_size); 8191c965db44STomer Tayar if (!rc) { 8192c965db44STomer Tayar *(u32 *)((u8 *)buffer + offset) = 8193c965db44STomer Tayar qed_calc_regdump_header(MCP_TRACE, cur_engine, 8194c965db44STomer Tayar feature_size, omit_engine); 8195c965db44STomer Tayar offset += (feature_size + REGDUMP_HEADER_SIZE); 8196c965db44STomer Tayar } else { 8197c965db44STomer Tayar DP_ERR(cdev, "qed_dbg_mcp_trace failed. rc = %d\n", rc); 8198c965db44STomer Tayar } 8199c965db44STomer Tayar 82001ac4329aSDenis Bolotin /* nvm cfg1 */ 82011ac4329aSDenis Bolotin rc = qed_dbg_nvm_image(cdev, 82021ac4329aSDenis Bolotin (u8 *)buffer + offset + REGDUMP_HEADER_SIZE, 82031ac4329aSDenis Bolotin &feature_size, QED_NVM_IMAGE_NVM_CFG1); 82041ac4329aSDenis Bolotin if (!rc) { 82051ac4329aSDenis Bolotin *(u32 *)((u8 *)buffer + offset) = 82061ac4329aSDenis Bolotin qed_calc_regdump_header(NVM_CFG1, cur_engine, 82071ac4329aSDenis Bolotin feature_size, omit_engine); 82081ac4329aSDenis Bolotin offset += (feature_size + REGDUMP_HEADER_SIZE); 82091ac4329aSDenis Bolotin } else if (rc != -ENOENT) { 82101ac4329aSDenis Bolotin DP_ERR(cdev, 82111ac4329aSDenis Bolotin "qed_dbg_nvm_image failed for image %d (%s), rc = %d\n", 82121ac4329aSDenis Bolotin QED_NVM_IMAGE_NVM_CFG1, "QED_NVM_IMAGE_NVM_CFG1", rc); 82131ac4329aSDenis Bolotin } 82141ac4329aSDenis Bolotin 82151ac4329aSDenis Bolotin /* nvm default */ 82161ac4329aSDenis Bolotin rc = qed_dbg_nvm_image(cdev, 82171ac4329aSDenis Bolotin (u8 *)buffer + offset + REGDUMP_HEADER_SIZE, 82181ac4329aSDenis Bolotin &feature_size, QED_NVM_IMAGE_DEFAULT_CFG); 82191ac4329aSDenis Bolotin if (!rc) { 82201ac4329aSDenis Bolotin *(u32 *)((u8 *)buffer + offset) = 82211ac4329aSDenis Bolotin qed_calc_regdump_header(DEFAULT_CFG, cur_engine, 82221ac4329aSDenis Bolotin feature_size, omit_engine); 82231ac4329aSDenis Bolotin offset += (feature_size + REGDUMP_HEADER_SIZE); 82241ac4329aSDenis Bolotin } else if (rc != -ENOENT) { 82251ac4329aSDenis Bolotin DP_ERR(cdev, 82261ac4329aSDenis Bolotin "qed_dbg_nvm_image failed for image %d (%s), rc = %d\n", 82271ac4329aSDenis Bolotin QED_NVM_IMAGE_DEFAULT_CFG, "QED_NVM_IMAGE_DEFAULT_CFG", 82281ac4329aSDenis Bolotin rc); 82291ac4329aSDenis Bolotin } 82301ac4329aSDenis Bolotin 82311ac4329aSDenis Bolotin /* nvm meta */ 82321ac4329aSDenis Bolotin rc = qed_dbg_nvm_image(cdev, 82331ac4329aSDenis Bolotin (u8 *)buffer + offset + REGDUMP_HEADER_SIZE, 82341ac4329aSDenis Bolotin &feature_size, QED_NVM_IMAGE_NVM_META); 82351ac4329aSDenis Bolotin if (!rc) { 82361ac4329aSDenis Bolotin *(u32 *)((u8 *)buffer + offset) = 82371ac4329aSDenis Bolotin qed_calc_regdump_header(NVM_META, cur_engine, 82381ac4329aSDenis Bolotin feature_size, omit_engine); 82391ac4329aSDenis Bolotin offset += (feature_size + REGDUMP_HEADER_SIZE); 82401ac4329aSDenis Bolotin } else if (rc != -ENOENT) { 82411ac4329aSDenis Bolotin DP_ERR(cdev, 82421ac4329aSDenis Bolotin "qed_dbg_nvm_image failed for image %d (%s), rc = %d\n", 82431ac4329aSDenis Bolotin QED_NVM_IMAGE_NVM_META, "QED_NVM_IMAGE_NVM_META", rc); 82441ac4329aSDenis Bolotin } 82451ac4329aSDenis Bolotin 8246c965db44STomer Tayar return 0; 8247c965db44STomer Tayar } 8248c965db44STomer Tayar 8249c965db44STomer Tayar int qed_dbg_all_data_size(struct qed_dev *cdev) 8250c965db44STomer Tayar { 82511ac4329aSDenis Bolotin struct qed_hwfn *p_hwfn = 82521ac4329aSDenis Bolotin &cdev->hwfns[cdev->dbg_params.engine_for_debug]; 82531ac4329aSDenis Bolotin u32 regs_len = 0, image_len = 0; 8254c965db44STomer Tayar u8 cur_engine, org_engine; 8255c965db44STomer Tayar 8256c965db44STomer Tayar org_engine = qed_get_debug_engine(cdev); 8257c965db44STomer Tayar for (cur_engine = 0; cur_engine < cdev->num_hwfns; cur_engine++) { 8258c965db44STomer Tayar /* Engine specific */ 8259c965db44STomer Tayar DP_VERBOSE(cdev, QED_MSG_DEBUG, 8260c965db44STomer Tayar "calculating idle_chk and grcdump register length for current engine\n"); 8261c965db44STomer Tayar qed_set_debug_engine(cdev, cur_engine); 8262c965db44STomer Tayar regs_len += REGDUMP_HEADER_SIZE + qed_dbg_idle_chk_size(cdev) + 8263c965db44STomer Tayar REGDUMP_HEADER_SIZE + qed_dbg_idle_chk_size(cdev) + 8264c965db44STomer Tayar REGDUMP_HEADER_SIZE + qed_dbg_grc_size(cdev) + 8265c965db44STomer Tayar REGDUMP_HEADER_SIZE + qed_dbg_reg_fifo_size(cdev) + 8266c965db44STomer Tayar REGDUMP_HEADER_SIZE + qed_dbg_igu_fifo_size(cdev) + 8267c965db44STomer Tayar REGDUMP_HEADER_SIZE + 8268c965db44STomer Tayar qed_dbg_protection_override_size(cdev) + 8269c965db44STomer Tayar REGDUMP_HEADER_SIZE + qed_dbg_fw_asserts_size(cdev); 8270c965db44STomer Tayar } 8271c965db44STomer Tayar 827250bc60cbSMichal Kalderon qed_set_debug_engine(cdev, org_engine); 827350bc60cbSMichal Kalderon 8274c965db44STomer Tayar /* Engine common */ 8275c965db44STomer Tayar regs_len += REGDUMP_HEADER_SIZE + qed_dbg_mcp_trace_size(cdev); 82761ac4329aSDenis Bolotin qed_dbg_nvm_image_length(p_hwfn, QED_NVM_IMAGE_NVM_CFG1, &image_len); 82771ac4329aSDenis Bolotin if (image_len) 82781ac4329aSDenis Bolotin regs_len += REGDUMP_HEADER_SIZE + image_len; 82791ac4329aSDenis Bolotin qed_dbg_nvm_image_length(p_hwfn, QED_NVM_IMAGE_DEFAULT_CFG, &image_len); 82801ac4329aSDenis Bolotin if (image_len) 82811ac4329aSDenis Bolotin regs_len += REGDUMP_HEADER_SIZE + image_len; 82821ac4329aSDenis Bolotin qed_dbg_nvm_image_length(p_hwfn, QED_NVM_IMAGE_NVM_META, &image_len); 82831ac4329aSDenis Bolotin if (image_len) 82841ac4329aSDenis Bolotin regs_len += REGDUMP_HEADER_SIZE + image_len; 8285c965db44STomer Tayar 8286c965db44STomer Tayar return regs_len; 8287c965db44STomer Tayar } 8288c965db44STomer Tayar 8289c965db44STomer Tayar int qed_dbg_feature(struct qed_dev *cdev, void *buffer, 8290c965db44STomer Tayar enum qed_dbg_features feature, u32 *num_dumped_bytes) 8291c965db44STomer Tayar { 8292c965db44STomer Tayar struct qed_hwfn *p_hwfn = 8293c965db44STomer Tayar &cdev->hwfns[cdev->dbg_params.engine_for_debug]; 8294c965db44STomer Tayar struct qed_dbg_feature *qed_feature = 8295c965db44STomer Tayar &cdev->dbg_params.features[feature]; 8296c965db44STomer Tayar enum dbg_status dbg_rc; 8297c965db44STomer Tayar struct qed_ptt *p_ptt; 8298c965db44STomer Tayar int rc = 0; 8299c965db44STomer Tayar 8300c965db44STomer Tayar /* Acquire ptt */ 8301c965db44STomer Tayar p_ptt = qed_ptt_acquire(p_hwfn); 8302c965db44STomer Tayar if (!p_ptt) 8303c965db44STomer Tayar return -EINVAL; 8304c965db44STomer Tayar 8305c965db44STomer Tayar /* Get dump */ 8306c965db44STomer Tayar dbg_rc = qed_dbg_dump(p_hwfn, p_ptt, feature); 8307c965db44STomer Tayar if (dbg_rc != DBG_STATUS_OK) { 8308c965db44STomer Tayar DP_VERBOSE(cdev, QED_MSG_DEBUG, "%s\n", 8309c965db44STomer Tayar qed_dbg_get_status_str(dbg_rc)); 8310c965db44STomer Tayar *num_dumped_bytes = 0; 8311c965db44STomer Tayar rc = -EINVAL; 8312c965db44STomer Tayar goto out; 8313c965db44STomer Tayar } 8314c965db44STomer Tayar 8315c965db44STomer Tayar DP_VERBOSE(cdev, QED_MSG_DEBUG, 8316c965db44STomer Tayar "copying debugfs feature to external buffer\n"); 8317c965db44STomer Tayar memcpy(buffer, qed_feature->dump_buf, qed_feature->buf_size); 8318c965db44STomer Tayar *num_dumped_bytes = cdev->dbg_params.features[feature].dumped_dwords * 8319c965db44STomer Tayar 4; 8320c965db44STomer Tayar 8321c965db44STomer Tayar out: 8322c965db44STomer Tayar qed_ptt_release(p_hwfn, p_ptt); 8323c965db44STomer Tayar return rc; 8324c965db44STomer Tayar } 8325c965db44STomer Tayar 8326c965db44STomer Tayar int qed_dbg_feature_size(struct qed_dev *cdev, enum qed_dbg_features feature) 8327c965db44STomer Tayar { 8328c965db44STomer Tayar struct qed_hwfn *p_hwfn = 8329c965db44STomer Tayar &cdev->hwfns[cdev->dbg_params.engine_for_debug]; 8330c965db44STomer Tayar struct qed_ptt *p_ptt = qed_ptt_acquire(p_hwfn); 8331c965db44STomer Tayar struct qed_dbg_feature *qed_feature = 8332c965db44STomer Tayar &cdev->dbg_params.features[feature]; 8333c965db44STomer Tayar u32 buf_size_dwords; 8334c965db44STomer Tayar enum dbg_status rc; 8335c965db44STomer Tayar 8336c965db44STomer Tayar if (!p_ptt) 8337c965db44STomer Tayar return -EINVAL; 8338c965db44STomer Tayar 8339c965db44STomer Tayar rc = qed_features_lookup[feature].get_size(p_hwfn, p_ptt, 8340c965db44STomer Tayar &buf_size_dwords); 8341c965db44STomer Tayar if (rc != DBG_STATUS_OK) 8342c965db44STomer Tayar buf_size_dwords = 0; 8343c965db44STomer Tayar 8344c965db44STomer Tayar qed_ptt_release(p_hwfn, p_ptt); 8345c965db44STomer Tayar qed_feature->buf_size = buf_size_dwords * sizeof(u32); 8346c965db44STomer Tayar return qed_feature->buf_size; 8347c965db44STomer Tayar } 8348c965db44STomer Tayar 8349c965db44STomer Tayar u8 qed_get_debug_engine(struct qed_dev *cdev) 8350c965db44STomer Tayar { 8351c965db44STomer Tayar return cdev->dbg_params.engine_for_debug; 8352c965db44STomer Tayar } 8353c965db44STomer Tayar 8354c965db44STomer Tayar void qed_set_debug_engine(struct qed_dev *cdev, int engine_number) 8355c965db44STomer Tayar { 8356c965db44STomer Tayar DP_VERBOSE(cdev, QED_MSG_DEBUG, "set debug engine to %d\n", 8357c965db44STomer Tayar engine_number); 8358c965db44STomer Tayar cdev->dbg_params.engine_for_debug = engine_number; 8359c965db44STomer Tayar } 8360c965db44STomer Tayar 8361c965db44STomer Tayar void qed_dbg_pf_init(struct qed_dev *cdev) 8362c965db44STomer Tayar { 8363c965db44STomer Tayar const u8 *dbg_values; 8364c965db44STomer Tayar 8365c965db44STomer Tayar /* Debug values are after init values. 8366c965db44STomer Tayar * The offset is the first dword of the file. 8367c965db44STomer Tayar */ 8368c965db44STomer Tayar dbg_values = cdev->firmware->data + *(u32 *)cdev->firmware->data; 8369c965db44STomer Tayar qed_dbg_set_bin_ptr((u8 *)dbg_values); 8370c965db44STomer Tayar qed_dbg_user_set_bin_ptr((u8 *)dbg_values); 8371c965db44STomer Tayar } 8372c965db44STomer Tayar 8373c965db44STomer Tayar void qed_dbg_pf_exit(struct qed_dev *cdev) 8374c965db44STomer Tayar { 8375c965db44STomer Tayar struct qed_dbg_feature *feature = NULL; 8376c965db44STomer Tayar enum qed_dbg_features feature_idx; 8377c965db44STomer Tayar 8378c965db44STomer Tayar /* Debug features' buffers may be allocated if debug feature was used 8379c965db44STomer Tayar * but dump wasn't called. 8380c965db44STomer Tayar */ 8381c965db44STomer Tayar for (feature_idx = 0; feature_idx < DBG_FEATURE_NUM; feature_idx++) { 8382c965db44STomer Tayar feature = &cdev->dbg_params.features[feature_idx]; 8383c965db44STomer Tayar if (feature->dump_buf) { 8384c965db44STomer Tayar vfree(feature->dump_buf); 8385c965db44STomer Tayar feature->dump_buf = NULL; 8386c965db44STomer Tayar } 8387c965db44STomer Tayar } 8388c965db44STomer Tayar } 8389