1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/types.h> 34 #include <linux/bitops.h> 35 #include <linux/dma-mapping.h> 36 #include <linux/errno.h> 37 #include <linux/kernel.h> 38 #include <linux/list.h> 39 #include <linux/log2.h> 40 #include <linux/pci.h> 41 #include <linux/slab.h> 42 #include <linux/string.h> 43 #include <linux/bitops.h> 44 #include "qed.h" 45 #include "qed_cxt.h" 46 #include "qed_dev_api.h" 47 #include "qed_hsi.h" 48 #include "qed_hw.h" 49 #include "qed_init_ops.h" 50 #include "qed_reg_addr.h" 51 #include "qed_sriov.h" 52 53 /* Max number of connection types in HW (DQ/CDU etc.) */ 54 #define MAX_CONN_TYPES PROTOCOLID_COMMON 55 #define NUM_TASK_TYPES 2 56 #define NUM_TASK_PF_SEGMENTS 4 57 #define NUM_TASK_VF_SEGMENTS 1 58 59 /* QM constants */ 60 #define QM_PQ_ELEMENT_SIZE 4 /* in bytes */ 61 62 /* Doorbell-Queue constants */ 63 #define DQ_RANGE_SHIFT 4 64 #define DQ_RANGE_ALIGN BIT(DQ_RANGE_SHIFT) 65 66 /* Searcher constants */ 67 #define SRC_MIN_NUM_ELEMS 256 68 69 /* Timers constants */ 70 #define TM_SHIFT 7 71 #define TM_ALIGN BIT(TM_SHIFT) 72 #define TM_ELEM_SIZE 4 73 74 #define ILT_DEFAULT_HW_P_SIZE 4 75 76 #define ILT_PAGE_IN_BYTES(hw_p_size) (1U << ((hw_p_size) + 12)) 77 #define ILT_CFG_REG(cli, reg) PSWRQ2_REG_ ## cli ## _ ## reg ## _RT_OFFSET 78 79 /* ILT entry structure */ 80 #define ILT_ENTRY_PHY_ADDR_MASK 0x000FFFFFFFFFFFULL 81 #define ILT_ENTRY_PHY_ADDR_SHIFT 0 82 #define ILT_ENTRY_VALID_MASK 0x1ULL 83 #define ILT_ENTRY_VALID_SHIFT 52 84 #define ILT_ENTRY_IN_REGS 2 85 #define ILT_REG_SIZE_IN_BYTES 4 86 87 /* connection context union */ 88 union conn_context { 89 struct core_conn_context core_ctx; 90 struct eth_conn_context eth_ctx; 91 struct iscsi_conn_context iscsi_ctx; 92 struct fcoe_conn_context fcoe_ctx; 93 struct roce_conn_context roce_ctx; 94 }; 95 96 /* TYPE-0 task context - iSCSI, FCOE */ 97 union type0_task_context { 98 struct iscsi_task_context iscsi_ctx; 99 struct fcoe_task_context fcoe_ctx; 100 }; 101 102 /* TYPE-1 task context - ROCE */ 103 union type1_task_context { 104 struct rdma_task_context roce_ctx; 105 }; 106 107 struct src_ent { 108 u8 opaque[56]; 109 u64 next; 110 }; 111 112 #define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */ 113 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12)) 114 115 #define CONN_CXT_SIZE(p_hwfn) \ 116 ALIGNED_TYPE_SIZE(union conn_context, p_hwfn) 117 118 #define SRQ_CXT_SIZE (sizeof(struct rdma_srq_context)) 119 120 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \ 121 ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn) 122 123 /* Alignment is inherent to the type1_task_context structure */ 124 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context) 125 126 /* PF per protocl configuration object */ 127 #define TASK_SEGMENTS (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS) 128 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS) 129 130 struct qed_tid_seg { 131 u32 count; 132 u8 type; 133 bool has_fl_mem; 134 }; 135 136 struct qed_conn_type_cfg { 137 u32 cid_count; 138 u32 cids_per_vf; 139 struct qed_tid_seg tid_seg[TASK_SEGMENTS]; 140 }; 141 142 /* ILT Client configuration, Per connection type (protocol) resources. */ 143 #define ILT_CLI_PF_BLOCKS (1 + NUM_TASK_PF_SEGMENTS * 2) 144 #define ILT_CLI_VF_BLOCKS (1 + NUM_TASK_VF_SEGMENTS * 2) 145 #define CDUC_BLK (0) 146 #define SRQ_BLK (0) 147 #define CDUT_SEG_BLK(n) (1 + (u8)(n)) 148 #define CDUT_FL_SEG_BLK(n, X) (1 + (n) + NUM_TASK_ ## X ## _SEGMENTS) 149 150 enum ilt_clients { 151 ILT_CLI_CDUC, 152 ILT_CLI_CDUT, 153 ILT_CLI_QM, 154 ILT_CLI_TM, 155 ILT_CLI_SRC, 156 ILT_CLI_TSDM, 157 ILT_CLI_MAX 158 }; 159 160 struct ilt_cfg_pair { 161 u32 reg; 162 u32 val; 163 }; 164 165 struct qed_ilt_cli_blk { 166 u32 total_size; /* 0 means not active */ 167 u32 real_size_in_page; 168 u32 start_line; 169 u32 dynamic_line_cnt; 170 }; 171 172 struct qed_ilt_client_cfg { 173 bool active; 174 175 /* ILT boundaries */ 176 struct ilt_cfg_pair first; 177 struct ilt_cfg_pair last; 178 struct ilt_cfg_pair p_size; 179 180 /* ILT client blocks for PF */ 181 struct qed_ilt_cli_blk pf_blks[ILT_CLI_PF_BLOCKS]; 182 u32 pf_total_lines; 183 184 /* ILT client blocks for VFs */ 185 struct qed_ilt_cli_blk vf_blks[ILT_CLI_VF_BLOCKS]; 186 u32 vf_total_lines; 187 }; 188 189 /* Per Path - 190 * ILT shadow table 191 * Protocol acquired CID lists 192 * PF start line in ILT 193 */ 194 struct qed_dma_mem { 195 dma_addr_t p_phys; 196 void *p_virt; 197 size_t size; 198 }; 199 200 struct qed_cid_acquired_map { 201 u32 start_cid; 202 u32 max_count; 203 unsigned long *cid_map; 204 }; 205 206 struct qed_cxt_mngr { 207 /* Per protocl configuration */ 208 struct qed_conn_type_cfg conn_cfg[MAX_CONN_TYPES]; 209 210 /* computed ILT structure */ 211 struct qed_ilt_client_cfg clients[ILT_CLI_MAX]; 212 213 /* Task type sizes */ 214 u32 task_type_size[NUM_TASK_TYPES]; 215 216 /* total number of VFs for this hwfn - 217 * ALL VFs are symmetric in terms of HW resources 218 */ 219 u32 vf_count; 220 221 /* Acquired CIDs */ 222 struct qed_cid_acquired_map acquired[MAX_CONN_TYPES]; 223 224 struct qed_cid_acquired_map 225 acquired_vf[MAX_CONN_TYPES][MAX_NUM_VFS]; 226 227 /* ILT shadow table */ 228 struct qed_dma_mem *ilt_shadow; 229 u32 pf_start_line; 230 231 /* Mutex for a dynamic ILT allocation */ 232 struct mutex mutex; 233 234 /* SRC T2 */ 235 struct qed_dma_mem *t2; 236 u32 t2_num_pages; 237 u64 first_free; 238 u64 last_free; 239 240 /* total number of SRQ's for this hwfn */ 241 u32 srq_count; 242 243 /* Maximal number of L2 steering filters */ 244 u32 arfs_count; 245 }; 246 static bool src_proto(enum protocol_type type) 247 { 248 return type == PROTOCOLID_ISCSI || 249 type == PROTOCOLID_FCOE || 250 type == PROTOCOLID_IWARP; 251 } 252 253 static bool tm_cid_proto(enum protocol_type type) 254 { 255 return type == PROTOCOLID_ISCSI || 256 type == PROTOCOLID_FCOE || 257 type == PROTOCOLID_ROCE || 258 type == PROTOCOLID_IWARP; 259 } 260 261 static bool tm_tid_proto(enum protocol_type type) 262 { 263 return type == PROTOCOLID_FCOE; 264 } 265 266 /* counts the iids for the CDU/CDUC ILT client configuration */ 267 struct qed_cdu_iids { 268 u32 pf_cids; 269 u32 per_vf_cids; 270 }; 271 272 static void qed_cxt_cdu_iids(struct qed_cxt_mngr *p_mngr, 273 struct qed_cdu_iids *iids) 274 { 275 u32 type; 276 277 for (type = 0; type < MAX_CONN_TYPES; type++) { 278 iids->pf_cids += p_mngr->conn_cfg[type].cid_count; 279 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf; 280 } 281 } 282 283 /* counts the iids for the Searcher block configuration */ 284 struct qed_src_iids { 285 u32 pf_cids; 286 u32 per_vf_cids; 287 }; 288 289 static void qed_cxt_src_iids(struct qed_cxt_mngr *p_mngr, 290 struct qed_src_iids *iids) 291 { 292 u32 i; 293 294 for (i = 0; i < MAX_CONN_TYPES; i++) { 295 if (!src_proto(i)) 296 continue; 297 298 iids->pf_cids += p_mngr->conn_cfg[i].cid_count; 299 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf; 300 } 301 302 /* Add L2 filtering filters in addition */ 303 iids->pf_cids += p_mngr->arfs_count; 304 } 305 306 /* counts the iids for the Timers block configuration */ 307 struct qed_tm_iids { 308 u32 pf_cids; 309 u32 pf_tids[NUM_TASK_PF_SEGMENTS]; /* per segment */ 310 u32 pf_tids_total; 311 u32 per_vf_cids; 312 u32 per_vf_tids; 313 }; 314 315 static void qed_cxt_tm_iids(struct qed_hwfn *p_hwfn, 316 struct qed_cxt_mngr *p_mngr, 317 struct qed_tm_iids *iids) 318 { 319 bool tm_vf_required = false; 320 bool tm_required = false; 321 int i, j; 322 323 /* Timers is a special case -> we don't count how many cids require 324 * timers but what's the max cid that will be used by the timer block. 325 * therefore we traverse in reverse order, and once we hit a protocol 326 * that requires the timers memory, we'll sum all the protocols up 327 * to that one. 328 */ 329 for (i = MAX_CONN_TYPES - 1; i >= 0; i--) { 330 struct qed_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i]; 331 332 if (tm_cid_proto(i) || tm_required) { 333 if (p_cfg->cid_count) 334 tm_required = true; 335 336 iids->pf_cids += p_cfg->cid_count; 337 } 338 339 if (tm_cid_proto(i) || tm_vf_required) { 340 if (p_cfg->cids_per_vf) 341 tm_vf_required = true; 342 343 iids->per_vf_cids += p_cfg->cids_per_vf; 344 } 345 346 if (tm_tid_proto(i)) { 347 struct qed_tid_seg *segs = p_cfg->tid_seg; 348 349 /* for each segment there is at most one 350 * protocol for which count is not 0. 351 */ 352 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++) 353 iids->pf_tids[j] += segs[j].count; 354 355 /* The last array elelment is for the VFs. As for PF 356 * segments there can be only one protocol for 357 * which this value is not 0. 358 */ 359 iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count; 360 } 361 } 362 363 iids->pf_cids = roundup(iids->pf_cids, TM_ALIGN); 364 iids->per_vf_cids = roundup(iids->per_vf_cids, TM_ALIGN); 365 iids->per_vf_tids = roundup(iids->per_vf_tids, TM_ALIGN); 366 367 for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) { 368 iids->pf_tids[j] = roundup(iids->pf_tids[j], TM_ALIGN); 369 iids->pf_tids_total += iids->pf_tids[j]; 370 } 371 } 372 373 static void qed_cxt_qm_iids(struct qed_hwfn *p_hwfn, 374 struct qed_qm_iids *iids) 375 { 376 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 377 struct qed_tid_seg *segs; 378 u32 vf_cids = 0, type, j; 379 u32 vf_tids = 0; 380 381 for (type = 0; type < MAX_CONN_TYPES; type++) { 382 iids->cids += p_mngr->conn_cfg[type].cid_count; 383 vf_cids += p_mngr->conn_cfg[type].cids_per_vf; 384 385 segs = p_mngr->conn_cfg[type].tid_seg; 386 /* for each segment there is at most one 387 * protocol for which count is not 0. 388 */ 389 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++) 390 iids->tids += segs[j].count; 391 392 /* The last array elelment is for the VFs. As for PF 393 * segments there can be only one protocol for 394 * which this value is not 0. 395 */ 396 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count; 397 } 398 399 iids->vf_cids += vf_cids * p_mngr->vf_count; 400 iids->tids += vf_tids * p_mngr->vf_count; 401 402 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 403 "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n", 404 iids->cids, iids->vf_cids, iids->tids, vf_tids); 405 } 406 407 static struct qed_tid_seg *qed_cxt_tid_seg_info(struct qed_hwfn *p_hwfn, 408 u32 seg) 409 { 410 struct qed_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr; 411 u32 i; 412 413 /* Find the protocol with tid count > 0 for this segment. 414 * Note: there can only be one and this is already validated. 415 */ 416 for (i = 0; i < MAX_CONN_TYPES; i++) 417 if (p_cfg->conn_cfg[i].tid_seg[seg].count) 418 return &p_cfg->conn_cfg[i].tid_seg[seg]; 419 return NULL; 420 } 421 422 static void qed_cxt_set_srq_count(struct qed_hwfn *p_hwfn, u32 num_srqs) 423 { 424 struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; 425 426 p_mgr->srq_count = num_srqs; 427 } 428 429 static u32 qed_cxt_get_srq_count(struct qed_hwfn *p_hwfn) 430 { 431 struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; 432 433 return p_mgr->srq_count; 434 } 435 436 /* set the iids count per protocol */ 437 static void qed_cxt_set_proto_cid_count(struct qed_hwfn *p_hwfn, 438 enum protocol_type type, 439 u32 cid_count, u32 vf_cid_cnt) 440 { 441 struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; 442 struct qed_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type]; 443 444 p_conn->cid_count = roundup(cid_count, DQ_RANGE_ALIGN); 445 p_conn->cids_per_vf = roundup(vf_cid_cnt, DQ_RANGE_ALIGN); 446 447 if (type == PROTOCOLID_ROCE) { 448 u32 page_sz = p_mgr->clients[ILT_CLI_CDUC].p_size.val; 449 u32 cxt_size = CONN_CXT_SIZE(p_hwfn); 450 u32 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 451 u32 align = elems_per_page * DQ_RANGE_ALIGN; 452 453 p_conn->cid_count = roundup(p_conn->cid_count, align); 454 } 455 } 456 457 u32 qed_cxt_get_proto_cid_count(struct qed_hwfn *p_hwfn, 458 enum protocol_type type, u32 *vf_cid) 459 { 460 if (vf_cid) 461 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf; 462 463 return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count; 464 } 465 466 u32 qed_cxt_get_proto_cid_start(struct qed_hwfn *p_hwfn, 467 enum protocol_type type) 468 { 469 return p_hwfn->p_cxt_mngr->acquired[type].start_cid; 470 } 471 472 u32 qed_cxt_get_proto_tid_count(struct qed_hwfn *p_hwfn, 473 enum protocol_type type) 474 { 475 u32 cnt = 0; 476 int i; 477 478 for (i = 0; i < TASK_SEGMENTS; i++) 479 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count; 480 481 return cnt; 482 } 483 484 static void qed_cxt_set_proto_tid_count(struct qed_hwfn *p_hwfn, 485 enum protocol_type proto, 486 u8 seg, 487 u8 seg_type, u32 count, bool has_fl) 488 { 489 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 490 struct qed_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg]; 491 492 p_seg->count = count; 493 p_seg->has_fl_mem = has_fl; 494 p_seg->type = seg_type; 495 } 496 497 static void qed_ilt_cli_blk_fill(struct qed_ilt_client_cfg *p_cli, 498 struct qed_ilt_cli_blk *p_blk, 499 u32 start_line, u32 total_size, u32 elem_size) 500 { 501 u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val); 502 503 /* verify thatits called only once for each block */ 504 if (p_blk->total_size) 505 return; 506 507 p_blk->total_size = total_size; 508 p_blk->real_size_in_page = 0; 509 if (elem_size) 510 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size; 511 p_blk->start_line = start_line; 512 } 513 514 static void qed_ilt_cli_adv_line(struct qed_hwfn *p_hwfn, 515 struct qed_ilt_client_cfg *p_cli, 516 struct qed_ilt_cli_blk *p_blk, 517 u32 *p_line, enum ilt_clients client_id) 518 { 519 if (!p_blk->total_size) 520 return; 521 522 if (!p_cli->active) 523 p_cli->first.val = *p_line; 524 525 p_cli->active = true; 526 *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page); 527 p_cli->last.val = *p_line - 1; 528 529 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 530 "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x [Real %08x] Start line %d\n", 531 client_id, p_cli->first.val, 532 p_cli->last.val, p_blk->total_size, 533 p_blk->real_size_in_page, p_blk->start_line); 534 } 535 536 static u32 qed_ilt_get_dynamic_line_cnt(struct qed_hwfn *p_hwfn, 537 enum ilt_clients ilt_client) 538 { 539 u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count; 540 struct qed_ilt_client_cfg *p_cli; 541 u32 lines_to_skip = 0; 542 u32 cxts_per_p; 543 544 if (ilt_client == ILT_CLI_CDUC) { 545 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 546 547 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) / 548 (u32) CONN_CXT_SIZE(p_hwfn); 549 550 lines_to_skip = cid_count / cxts_per_p; 551 } 552 553 return lines_to_skip; 554 } 555 556 static struct qed_ilt_client_cfg *qed_cxt_set_cli(struct qed_ilt_client_cfg 557 *p_cli) 558 { 559 p_cli->active = false; 560 p_cli->first.val = 0; 561 p_cli->last.val = 0; 562 return p_cli; 563 } 564 565 static struct qed_ilt_cli_blk *qed_cxt_set_blk(struct qed_ilt_cli_blk *p_blk) 566 { 567 p_blk->total_size = 0; 568 return p_blk; 569 } 570 571 int qed_cxt_cfg_ilt_compute(struct qed_hwfn *p_hwfn, u32 *line_count) 572 { 573 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 574 u32 curr_line, total, i, task_size, line; 575 struct qed_ilt_client_cfg *p_cli; 576 struct qed_ilt_cli_blk *p_blk; 577 struct qed_cdu_iids cdu_iids; 578 struct qed_src_iids src_iids; 579 struct qed_qm_iids qm_iids; 580 struct qed_tm_iids tm_iids; 581 struct qed_tid_seg *p_seg; 582 583 memset(&qm_iids, 0, sizeof(qm_iids)); 584 memset(&cdu_iids, 0, sizeof(cdu_iids)); 585 memset(&src_iids, 0, sizeof(src_iids)); 586 memset(&tm_iids, 0, sizeof(tm_iids)); 587 588 p_mngr->pf_start_line = RESC_START(p_hwfn, QED_ILT); 589 590 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 591 "hwfn [%d] - Set context manager starting line to be 0x%08x\n", 592 p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line); 593 594 /* CDUC */ 595 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_CDUC]); 596 597 curr_line = p_mngr->pf_start_line; 598 599 /* CDUC PF */ 600 p_cli->pf_total_lines = 0; 601 602 /* get the counters for the CDUC and QM clients */ 603 qed_cxt_cdu_iids(p_mngr, &cdu_iids); 604 605 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[CDUC_BLK]); 606 607 total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn); 608 609 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 610 total, CONN_CXT_SIZE(p_hwfn)); 611 612 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC); 613 p_cli->pf_total_lines = curr_line - p_blk->start_line; 614 615 p_blk->dynamic_line_cnt = qed_ilt_get_dynamic_line_cnt(p_hwfn, 616 ILT_CLI_CDUC); 617 618 /* CDUC VF */ 619 p_blk = qed_cxt_set_blk(&p_cli->vf_blks[CDUC_BLK]); 620 total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn); 621 622 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 623 total, CONN_CXT_SIZE(p_hwfn)); 624 625 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC); 626 p_cli->vf_total_lines = curr_line - p_blk->start_line; 627 628 for (i = 1; i < p_mngr->vf_count; i++) 629 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 630 ILT_CLI_CDUC); 631 632 /* CDUT PF */ 633 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_CDUT]); 634 p_cli->first.val = curr_line; 635 636 /* first the 'working' task memory */ 637 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 638 p_seg = qed_cxt_tid_seg_info(p_hwfn, i); 639 if (!p_seg || p_seg->count == 0) 640 continue; 641 642 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[CDUT_SEG_BLK(i)]); 643 total = p_seg->count * p_mngr->task_type_size[p_seg->type]; 644 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total, 645 p_mngr->task_type_size[p_seg->type]); 646 647 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 648 ILT_CLI_CDUT); 649 } 650 651 /* next the 'init' task memory (forced load memory) */ 652 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 653 p_seg = qed_cxt_tid_seg_info(p_hwfn, i); 654 if (!p_seg || p_seg->count == 0) 655 continue; 656 657 p_blk = 658 qed_cxt_set_blk(&p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)]); 659 660 if (!p_seg->has_fl_mem) { 661 /* The segment is active (total size pf 'working' 662 * memory is > 0) but has no FL (forced-load, Init) 663 * memory. Thus: 664 * 665 * 1. The total-size in the corrsponding FL block of 666 * the ILT client is set to 0 - No ILT line are 667 * provisioned and no ILT memory allocated. 668 * 669 * 2. The start-line of said block is set to the 670 * start line of the matching working memory 671 * block in the ILT client. This is later used to 672 * configure the CDU segment offset registers and 673 * results in an FL command for TIDs of this 674 * segement behaves as regular load commands 675 * (loading TIDs from the working memory). 676 */ 677 line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line; 678 679 qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0); 680 continue; 681 } 682 total = p_seg->count * p_mngr->task_type_size[p_seg->type]; 683 684 qed_ilt_cli_blk_fill(p_cli, p_blk, 685 curr_line, total, 686 p_mngr->task_type_size[p_seg->type]); 687 688 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 689 ILT_CLI_CDUT); 690 } 691 p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line; 692 693 /* CDUT VF */ 694 p_seg = qed_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF); 695 if (p_seg && p_seg->count) { 696 /* Stricly speaking we need to iterate over all VF 697 * task segment types, but a VF has only 1 segment 698 */ 699 700 /* 'working' memory */ 701 total = p_seg->count * p_mngr->task_type_size[p_seg->type]; 702 703 p_blk = qed_cxt_set_blk(&p_cli->vf_blks[CDUT_SEG_BLK(0)]); 704 qed_ilt_cli_blk_fill(p_cli, p_blk, 705 curr_line, total, 706 p_mngr->task_type_size[p_seg->type]); 707 708 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 709 ILT_CLI_CDUT); 710 711 /* 'init' memory */ 712 p_blk = 713 qed_cxt_set_blk(&p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)]); 714 if (!p_seg->has_fl_mem) { 715 /* see comment above */ 716 line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line; 717 qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0); 718 } else { 719 task_size = p_mngr->task_type_size[p_seg->type]; 720 qed_ilt_cli_blk_fill(p_cli, p_blk, 721 curr_line, total, task_size); 722 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 723 ILT_CLI_CDUT); 724 } 725 p_cli->vf_total_lines = curr_line - 726 p_cli->vf_blks[0].start_line; 727 728 /* Now for the rest of the VFs */ 729 for (i = 1; i < p_mngr->vf_count; i++) { 730 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)]; 731 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 732 ILT_CLI_CDUT); 733 734 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)]; 735 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 736 ILT_CLI_CDUT); 737 } 738 } 739 740 /* QM */ 741 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_QM]); 742 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[0]); 743 744 qed_cxt_qm_iids(p_hwfn, &qm_iids); 745 total = qed_qm_pf_mem_size(p_hwfn->rel_pf_id, qm_iids.cids, 746 qm_iids.vf_cids, qm_iids.tids, 747 p_hwfn->qm_info.num_pqs, 748 p_hwfn->qm_info.num_vf_pqs); 749 750 DP_VERBOSE(p_hwfn, 751 QED_MSG_ILT, 752 "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d, num_vf_pqs=%d, memory_size=%d)\n", 753 qm_iids.cids, 754 qm_iids.vf_cids, 755 qm_iids.tids, 756 p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total); 757 758 qed_ilt_cli_blk_fill(p_cli, p_blk, 759 curr_line, total * 0x1000, 760 QM_PQ_ELEMENT_SIZE); 761 762 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM); 763 p_cli->pf_total_lines = curr_line - p_blk->start_line; 764 765 /* SRC */ 766 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_SRC]); 767 qed_cxt_src_iids(p_mngr, &src_iids); 768 769 /* Both the PF and VFs searcher connections are stored in the per PF 770 * database. Thus sum the PF searcher cids and all the VFs searcher 771 * cids. 772 */ 773 total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count; 774 if (total) { 775 u32 local_max = max_t(u32, total, 776 SRC_MIN_NUM_ELEMS); 777 778 total = roundup_pow_of_two(local_max); 779 780 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[0]); 781 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 782 total * sizeof(struct src_ent), 783 sizeof(struct src_ent)); 784 785 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 786 ILT_CLI_SRC); 787 p_cli->pf_total_lines = curr_line - p_blk->start_line; 788 } 789 790 /* TM PF */ 791 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_TM]); 792 qed_cxt_tm_iids(p_hwfn, p_mngr, &tm_iids); 793 total = tm_iids.pf_cids + tm_iids.pf_tids_total; 794 if (total) { 795 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[0]); 796 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 797 total * TM_ELEM_SIZE, TM_ELEM_SIZE); 798 799 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 800 ILT_CLI_TM); 801 p_cli->pf_total_lines = curr_line - p_blk->start_line; 802 } 803 804 /* TM VF */ 805 total = tm_iids.per_vf_cids + tm_iids.per_vf_tids; 806 if (total) { 807 p_blk = qed_cxt_set_blk(&p_cli->vf_blks[0]); 808 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 809 total * TM_ELEM_SIZE, TM_ELEM_SIZE); 810 811 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 812 ILT_CLI_TM); 813 814 p_cli->vf_total_lines = curr_line - p_blk->start_line; 815 for (i = 1; i < p_mngr->vf_count; i++) 816 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 817 ILT_CLI_TM); 818 } 819 820 /* TSDM (SRQ CONTEXT) */ 821 total = qed_cxt_get_srq_count(p_hwfn); 822 823 if (total) { 824 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_TSDM]); 825 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[SRQ_BLK]); 826 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 827 total * SRQ_CXT_SIZE, SRQ_CXT_SIZE); 828 829 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 830 ILT_CLI_TSDM); 831 p_cli->pf_total_lines = curr_line - p_blk->start_line; 832 } 833 834 *line_count = curr_line - p_hwfn->p_cxt_mngr->pf_start_line; 835 836 if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line > 837 RESC_NUM(p_hwfn, QED_ILT)) 838 return -EINVAL; 839 840 return 0; 841 } 842 843 u32 qed_cxt_cfg_ilt_compute_excess(struct qed_hwfn *p_hwfn, u32 used_lines) 844 { 845 struct qed_ilt_client_cfg *p_cli; 846 u32 excess_lines, available_lines; 847 struct qed_cxt_mngr *p_mngr; 848 u32 ilt_page_size, elem_size; 849 struct qed_tid_seg *p_seg; 850 int i; 851 852 available_lines = RESC_NUM(p_hwfn, QED_ILT); 853 excess_lines = used_lines - available_lines; 854 855 if (!excess_lines) 856 return 0; 857 858 if (!QED_IS_RDMA_PERSONALITY(p_hwfn)) 859 return 0; 860 861 p_mngr = p_hwfn->p_cxt_mngr; 862 p_cli = &p_mngr->clients[ILT_CLI_CDUT]; 863 ilt_page_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val); 864 865 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 866 p_seg = qed_cxt_tid_seg_info(p_hwfn, i); 867 if (!p_seg || p_seg->count == 0) 868 continue; 869 870 elem_size = p_mngr->task_type_size[p_seg->type]; 871 if (!elem_size) 872 continue; 873 874 return (ilt_page_size / elem_size) * excess_lines; 875 } 876 877 DP_NOTICE(p_hwfn, "failed computing excess ILT lines\n"); 878 return 0; 879 } 880 881 static void qed_cxt_src_t2_free(struct qed_hwfn *p_hwfn) 882 { 883 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 884 u32 i; 885 886 if (!p_mngr->t2) 887 return; 888 889 for (i = 0; i < p_mngr->t2_num_pages; i++) 890 if (p_mngr->t2[i].p_virt) 891 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 892 p_mngr->t2[i].size, 893 p_mngr->t2[i].p_virt, 894 p_mngr->t2[i].p_phys); 895 896 kfree(p_mngr->t2); 897 p_mngr->t2 = NULL; 898 } 899 900 static int qed_cxt_src_t2_alloc(struct qed_hwfn *p_hwfn) 901 { 902 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 903 u32 conn_num, total_size, ent_per_page, psz, i; 904 struct qed_ilt_client_cfg *p_src; 905 struct qed_src_iids src_iids; 906 struct qed_dma_mem *p_t2; 907 int rc; 908 909 memset(&src_iids, 0, sizeof(src_iids)); 910 911 /* if the SRC ILT client is inactive - there are no connection 912 * requiring the searcer, leave. 913 */ 914 p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC]; 915 if (!p_src->active) 916 return 0; 917 918 qed_cxt_src_iids(p_mngr, &src_iids); 919 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count; 920 total_size = conn_num * sizeof(struct src_ent); 921 922 /* use the same page size as the SRC ILT client */ 923 psz = ILT_PAGE_IN_BYTES(p_src->p_size.val); 924 p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz); 925 926 /* allocate t2 */ 927 p_mngr->t2 = kcalloc(p_mngr->t2_num_pages, sizeof(struct qed_dma_mem), 928 GFP_KERNEL); 929 if (!p_mngr->t2) { 930 rc = -ENOMEM; 931 goto t2_fail; 932 } 933 934 /* allocate t2 pages */ 935 for (i = 0; i < p_mngr->t2_num_pages; i++) { 936 u32 size = min_t(u32, total_size, psz); 937 void **p_virt = &p_mngr->t2[i].p_virt; 938 939 *p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 940 size, 941 &p_mngr->t2[i].p_phys, GFP_KERNEL); 942 if (!p_mngr->t2[i].p_virt) { 943 rc = -ENOMEM; 944 goto t2_fail; 945 } 946 memset(*p_virt, 0, size); 947 p_mngr->t2[i].size = size; 948 total_size -= size; 949 } 950 951 /* Set the t2 pointers */ 952 953 /* entries per page - must be a power of two */ 954 ent_per_page = psz / sizeof(struct src_ent); 955 956 p_mngr->first_free = (u64) p_mngr->t2[0].p_phys; 957 958 p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page]; 959 p_mngr->last_free = (u64) p_t2->p_phys + 960 ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent); 961 962 for (i = 0; i < p_mngr->t2_num_pages; i++) { 963 u32 ent_num = min_t(u32, 964 ent_per_page, 965 conn_num); 966 struct src_ent *entries = p_mngr->t2[i].p_virt; 967 u64 p_ent_phys = (u64) p_mngr->t2[i].p_phys, val; 968 u32 j; 969 970 for (j = 0; j < ent_num - 1; j++) { 971 val = p_ent_phys + (j + 1) * sizeof(struct src_ent); 972 entries[j].next = cpu_to_be64(val); 973 } 974 975 if (i < p_mngr->t2_num_pages - 1) 976 val = (u64) p_mngr->t2[i + 1].p_phys; 977 else 978 val = 0; 979 entries[j].next = cpu_to_be64(val); 980 981 conn_num -= ent_num; 982 } 983 984 return 0; 985 986 t2_fail: 987 qed_cxt_src_t2_free(p_hwfn); 988 return rc; 989 } 990 991 #define for_each_ilt_valid_client(pos, clients) \ 992 for (pos = 0; pos < ILT_CLI_MAX; pos++) \ 993 if (!clients[pos].active) { \ 994 continue; \ 995 } else \ 996 997 /* Total number of ILT lines used by this PF */ 998 static u32 qed_cxt_ilt_shadow_size(struct qed_ilt_client_cfg *ilt_clients) 999 { 1000 u32 size = 0; 1001 u32 i; 1002 1003 for_each_ilt_valid_client(i, ilt_clients) 1004 size += (ilt_clients[i].last.val - ilt_clients[i].first.val + 1); 1005 1006 return size; 1007 } 1008 1009 static void qed_ilt_shadow_free(struct qed_hwfn *p_hwfn) 1010 { 1011 struct qed_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients; 1012 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1013 u32 ilt_size, i; 1014 1015 ilt_size = qed_cxt_ilt_shadow_size(p_cli); 1016 1017 for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) { 1018 struct qed_dma_mem *p_dma = &p_mngr->ilt_shadow[i]; 1019 1020 if (p_dma->p_virt) 1021 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 1022 p_dma->size, p_dma->p_virt, 1023 p_dma->p_phys); 1024 p_dma->p_virt = NULL; 1025 } 1026 kfree(p_mngr->ilt_shadow); 1027 } 1028 1029 static int qed_ilt_blk_alloc(struct qed_hwfn *p_hwfn, 1030 struct qed_ilt_cli_blk *p_blk, 1031 enum ilt_clients ilt_client, 1032 u32 start_line_offset) 1033 { 1034 struct qed_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow; 1035 u32 lines, line, sz_left, lines_to_skip = 0; 1036 1037 /* Special handling for RoCE that supports dynamic allocation */ 1038 if (QED_IS_RDMA_PERSONALITY(p_hwfn) && 1039 ((ilt_client == ILT_CLI_CDUT) || ilt_client == ILT_CLI_TSDM)) 1040 return 0; 1041 1042 lines_to_skip = p_blk->dynamic_line_cnt; 1043 1044 if (!p_blk->total_size) 1045 return 0; 1046 1047 sz_left = p_blk->total_size; 1048 lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip; 1049 line = p_blk->start_line + start_line_offset - 1050 p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip; 1051 1052 for (; lines; lines--) { 1053 dma_addr_t p_phys; 1054 void *p_virt; 1055 u32 size; 1056 1057 size = min_t(u32, sz_left, p_blk->real_size_in_page); 1058 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 1059 size, &p_phys, GFP_KERNEL); 1060 if (!p_virt) 1061 return -ENOMEM; 1062 memset(p_virt, 0, size); 1063 1064 ilt_shadow[line].p_phys = p_phys; 1065 ilt_shadow[line].p_virt = p_virt; 1066 ilt_shadow[line].size = size; 1067 1068 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 1069 "ILT shadow: Line [%d] Physical 0x%llx Virtual %p Size %d\n", 1070 line, (u64)p_phys, p_virt, size); 1071 1072 sz_left -= size; 1073 line++; 1074 } 1075 1076 return 0; 1077 } 1078 1079 static int qed_ilt_shadow_alloc(struct qed_hwfn *p_hwfn) 1080 { 1081 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1082 struct qed_ilt_client_cfg *clients = p_mngr->clients; 1083 struct qed_ilt_cli_blk *p_blk; 1084 u32 size, i, j, k; 1085 int rc; 1086 1087 size = qed_cxt_ilt_shadow_size(clients); 1088 p_mngr->ilt_shadow = kcalloc(size, sizeof(struct qed_dma_mem), 1089 GFP_KERNEL); 1090 if (!p_mngr->ilt_shadow) { 1091 rc = -ENOMEM; 1092 goto ilt_shadow_fail; 1093 } 1094 1095 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 1096 "Allocated 0x%x bytes for ilt shadow\n", 1097 (u32)(size * sizeof(struct qed_dma_mem))); 1098 1099 for_each_ilt_valid_client(i, clients) { 1100 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) { 1101 p_blk = &clients[i].pf_blks[j]; 1102 rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, 0); 1103 if (rc) 1104 goto ilt_shadow_fail; 1105 } 1106 for (k = 0; k < p_mngr->vf_count; k++) { 1107 for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) { 1108 u32 lines = clients[i].vf_total_lines * k; 1109 1110 p_blk = &clients[i].vf_blks[j]; 1111 rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, lines); 1112 if (rc) 1113 goto ilt_shadow_fail; 1114 } 1115 } 1116 } 1117 1118 return 0; 1119 1120 ilt_shadow_fail: 1121 qed_ilt_shadow_free(p_hwfn); 1122 return rc; 1123 } 1124 1125 static void qed_cid_map_free(struct qed_hwfn *p_hwfn) 1126 { 1127 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1128 u32 type, vf; 1129 1130 for (type = 0; type < MAX_CONN_TYPES; type++) { 1131 kfree(p_mngr->acquired[type].cid_map); 1132 p_mngr->acquired[type].max_count = 0; 1133 p_mngr->acquired[type].start_cid = 0; 1134 1135 for (vf = 0; vf < MAX_NUM_VFS; vf++) { 1136 kfree(p_mngr->acquired_vf[type][vf].cid_map); 1137 p_mngr->acquired_vf[type][vf].max_count = 0; 1138 p_mngr->acquired_vf[type][vf].start_cid = 0; 1139 } 1140 } 1141 } 1142 1143 static int 1144 qed_cid_map_alloc_single(struct qed_hwfn *p_hwfn, 1145 u32 type, 1146 u32 cid_start, 1147 u32 cid_count, struct qed_cid_acquired_map *p_map) 1148 { 1149 u32 size; 1150 1151 if (!cid_count) 1152 return 0; 1153 1154 size = DIV_ROUND_UP(cid_count, 1155 sizeof(unsigned long) * BITS_PER_BYTE) * 1156 sizeof(unsigned long); 1157 p_map->cid_map = kzalloc(size, GFP_KERNEL); 1158 if (!p_map->cid_map) 1159 return -ENOMEM; 1160 1161 p_map->max_count = cid_count; 1162 p_map->start_cid = cid_start; 1163 1164 DP_VERBOSE(p_hwfn, QED_MSG_CXT, 1165 "Type %08x start: %08x count %08x\n", 1166 type, p_map->start_cid, p_map->max_count); 1167 1168 return 0; 1169 } 1170 1171 static int qed_cid_map_alloc(struct qed_hwfn *p_hwfn) 1172 { 1173 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1174 u32 start_cid = 0, vf_start_cid = 0; 1175 u32 type, vf; 1176 1177 for (type = 0; type < MAX_CONN_TYPES; type++) { 1178 struct qed_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[type]; 1179 struct qed_cid_acquired_map *p_map; 1180 1181 /* Handle PF maps */ 1182 p_map = &p_mngr->acquired[type]; 1183 if (qed_cid_map_alloc_single(p_hwfn, type, start_cid, 1184 p_cfg->cid_count, p_map)) 1185 goto cid_map_fail; 1186 1187 /* Handle VF maps */ 1188 for (vf = 0; vf < MAX_NUM_VFS; vf++) { 1189 p_map = &p_mngr->acquired_vf[type][vf]; 1190 if (qed_cid_map_alloc_single(p_hwfn, type, 1191 vf_start_cid, 1192 p_cfg->cids_per_vf, p_map)) 1193 goto cid_map_fail; 1194 } 1195 1196 start_cid += p_cfg->cid_count; 1197 vf_start_cid += p_cfg->cids_per_vf; 1198 } 1199 1200 return 0; 1201 1202 cid_map_fail: 1203 qed_cid_map_free(p_hwfn); 1204 return -ENOMEM; 1205 } 1206 1207 int qed_cxt_mngr_alloc(struct qed_hwfn *p_hwfn) 1208 { 1209 struct qed_ilt_client_cfg *clients; 1210 struct qed_cxt_mngr *p_mngr; 1211 u32 i; 1212 1213 p_mngr = kzalloc(sizeof(*p_mngr), GFP_KERNEL); 1214 if (!p_mngr) 1215 return -ENOMEM; 1216 1217 /* Initialize ILT client registers */ 1218 clients = p_mngr->clients; 1219 clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT); 1220 clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT); 1221 clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE); 1222 1223 clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT); 1224 clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT); 1225 clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE); 1226 1227 clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT); 1228 clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT); 1229 clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE); 1230 1231 clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT); 1232 clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT); 1233 clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE); 1234 1235 clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT); 1236 clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT); 1237 clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE); 1238 1239 clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT); 1240 clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT); 1241 clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE); 1242 /* default ILT page size for all clients is 64K */ 1243 for (i = 0; i < ILT_CLI_MAX; i++) 1244 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE; 1245 1246 /* Initialize task sizes */ 1247 p_mngr->task_type_size[0] = TYPE0_TASK_CXT_SIZE(p_hwfn); 1248 p_mngr->task_type_size[1] = TYPE1_TASK_CXT_SIZE(p_hwfn); 1249 1250 if (p_hwfn->cdev->p_iov_info) 1251 p_mngr->vf_count = p_hwfn->cdev->p_iov_info->total_vfs; 1252 /* Initialize the dynamic ILT allocation mutex */ 1253 mutex_init(&p_mngr->mutex); 1254 1255 /* Set the cxt mangr pointer priori to further allocations */ 1256 p_hwfn->p_cxt_mngr = p_mngr; 1257 1258 return 0; 1259 } 1260 1261 int qed_cxt_tables_alloc(struct qed_hwfn *p_hwfn) 1262 { 1263 int rc; 1264 1265 /* Allocate the ILT shadow table */ 1266 rc = qed_ilt_shadow_alloc(p_hwfn); 1267 if (rc) 1268 goto tables_alloc_fail; 1269 1270 /* Allocate the T2 table */ 1271 rc = qed_cxt_src_t2_alloc(p_hwfn); 1272 if (rc) 1273 goto tables_alloc_fail; 1274 1275 /* Allocate and initialize the acquired cids bitmaps */ 1276 rc = qed_cid_map_alloc(p_hwfn); 1277 if (rc) 1278 goto tables_alloc_fail; 1279 1280 return 0; 1281 1282 tables_alloc_fail: 1283 qed_cxt_mngr_free(p_hwfn); 1284 return rc; 1285 } 1286 1287 void qed_cxt_mngr_free(struct qed_hwfn *p_hwfn) 1288 { 1289 if (!p_hwfn->p_cxt_mngr) 1290 return; 1291 1292 qed_cid_map_free(p_hwfn); 1293 qed_cxt_src_t2_free(p_hwfn); 1294 qed_ilt_shadow_free(p_hwfn); 1295 kfree(p_hwfn->p_cxt_mngr); 1296 1297 p_hwfn->p_cxt_mngr = NULL; 1298 } 1299 1300 void qed_cxt_mngr_setup(struct qed_hwfn *p_hwfn) 1301 { 1302 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1303 struct qed_cid_acquired_map *p_map; 1304 struct qed_conn_type_cfg *p_cfg; 1305 int type; 1306 u32 len; 1307 1308 /* Reset acquired cids */ 1309 for (type = 0; type < MAX_CONN_TYPES; type++) { 1310 u32 vf; 1311 1312 p_cfg = &p_mngr->conn_cfg[type]; 1313 if (p_cfg->cid_count) { 1314 p_map = &p_mngr->acquired[type]; 1315 len = DIV_ROUND_UP(p_map->max_count, 1316 sizeof(unsigned long) * 1317 BITS_PER_BYTE) * 1318 sizeof(unsigned long); 1319 memset(p_map->cid_map, 0, len); 1320 } 1321 1322 if (!p_cfg->cids_per_vf) 1323 continue; 1324 1325 for (vf = 0; vf < MAX_NUM_VFS; vf++) { 1326 p_map = &p_mngr->acquired_vf[type][vf]; 1327 len = DIV_ROUND_UP(p_map->max_count, 1328 sizeof(unsigned long) * 1329 BITS_PER_BYTE) * 1330 sizeof(unsigned long); 1331 memset(p_map->cid_map, 0, len); 1332 } 1333 } 1334 } 1335 1336 /* CDU Common */ 1337 #define CDUC_CXT_SIZE_SHIFT \ 1338 CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT 1339 1340 #define CDUC_CXT_SIZE_MASK \ 1341 (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT) 1342 1343 #define CDUC_BLOCK_WASTE_SHIFT \ 1344 CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT 1345 1346 #define CDUC_BLOCK_WASTE_MASK \ 1347 (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT) 1348 1349 #define CDUC_NCIB_SHIFT \ 1350 CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT 1351 1352 #define CDUC_NCIB_MASK \ 1353 (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT) 1354 1355 #define CDUT_TYPE0_CXT_SIZE_SHIFT \ 1356 CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT 1357 1358 #define CDUT_TYPE0_CXT_SIZE_MASK \ 1359 (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >> \ 1360 CDUT_TYPE0_CXT_SIZE_SHIFT) 1361 1362 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT \ 1363 CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT 1364 1365 #define CDUT_TYPE0_BLOCK_WASTE_MASK \ 1366 (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >> \ 1367 CDUT_TYPE0_BLOCK_WASTE_SHIFT) 1368 1369 #define CDUT_TYPE0_NCIB_SHIFT \ 1370 CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT 1371 1372 #define CDUT_TYPE0_NCIB_MASK \ 1373 (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >> \ 1374 CDUT_TYPE0_NCIB_SHIFT) 1375 1376 #define CDUT_TYPE1_CXT_SIZE_SHIFT \ 1377 CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT 1378 1379 #define CDUT_TYPE1_CXT_SIZE_MASK \ 1380 (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >> \ 1381 CDUT_TYPE1_CXT_SIZE_SHIFT) 1382 1383 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT \ 1384 CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT 1385 1386 #define CDUT_TYPE1_BLOCK_WASTE_MASK \ 1387 (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >> \ 1388 CDUT_TYPE1_BLOCK_WASTE_SHIFT) 1389 1390 #define CDUT_TYPE1_NCIB_SHIFT \ 1391 CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT 1392 1393 #define CDUT_TYPE1_NCIB_MASK \ 1394 (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >> \ 1395 CDUT_TYPE1_NCIB_SHIFT) 1396 1397 static void qed_cdu_init_common(struct qed_hwfn *p_hwfn) 1398 { 1399 u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0; 1400 1401 /* CDUC - connection configuration */ 1402 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val; 1403 cxt_size = CONN_CXT_SIZE(p_hwfn); 1404 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 1405 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size; 1406 1407 SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size); 1408 SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste); 1409 SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page); 1410 STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params); 1411 1412 /* CDUT - type-0 tasks configuration */ 1413 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val; 1414 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0]; 1415 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 1416 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size; 1417 1418 /* cxt size and block-waste are multipes of 8 */ 1419 cdu_params = 0; 1420 SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3)); 1421 SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3)); 1422 SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page); 1423 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params); 1424 1425 /* CDUT - type-1 tasks configuration */ 1426 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1]; 1427 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 1428 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size; 1429 1430 /* cxt size and block-waste are multipes of 8 */ 1431 cdu_params = 0; 1432 SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3)); 1433 SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3)); 1434 SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page); 1435 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params); 1436 } 1437 1438 /* CDU PF */ 1439 #define CDU_SEG_REG_TYPE_SHIFT CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT 1440 #define CDU_SEG_REG_TYPE_MASK 0x1 1441 #define CDU_SEG_REG_OFFSET_SHIFT 0 1442 #define CDU_SEG_REG_OFFSET_MASK CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK 1443 1444 static void qed_cdu_init_pf(struct qed_hwfn *p_hwfn) 1445 { 1446 struct qed_ilt_client_cfg *p_cli; 1447 struct qed_tid_seg *p_seg; 1448 u32 cdu_seg_params, offset; 1449 int i; 1450 1451 static const u32 rt_type_offset_arr[] = { 1452 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET, 1453 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET, 1454 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET, 1455 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 1456 }; 1457 1458 static const u32 rt_type_offset_fl_arr[] = { 1459 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET, 1460 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET, 1461 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET, 1462 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 1463 }; 1464 1465 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 1466 1467 /* There are initializations only for CDUT during pf Phase */ 1468 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 1469 /* Segment 0 */ 1470 p_seg = qed_cxt_tid_seg_info(p_hwfn, i); 1471 if (!p_seg) 1472 continue; 1473 1474 /* Note: start_line is already adjusted for the CDU 1475 * segment register granularity, so we just need to 1476 * divide. Adjustment is implicit as we assume ILT 1477 * Page size is larger than 32K! 1478 */ 1479 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) * 1480 (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line - 1481 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES; 1482 1483 cdu_seg_params = 0; 1484 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type); 1485 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset); 1486 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params); 1487 1488 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) * 1489 (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line - 1490 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES; 1491 1492 cdu_seg_params = 0; 1493 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type); 1494 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset); 1495 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params); 1496 } 1497 } 1498 1499 void qed_qm_init_pf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1500 { 1501 struct qed_qm_pf_rt_init_params params; 1502 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1503 struct qed_qm_iids iids; 1504 1505 memset(&iids, 0, sizeof(iids)); 1506 qed_cxt_qm_iids(p_hwfn, &iids); 1507 1508 memset(¶ms, 0, sizeof(params)); 1509 params.port_id = p_hwfn->port_id; 1510 params.pf_id = p_hwfn->rel_pf_id; 1511 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port; 1512 params.is_first_pf = p_hwfn->first_on_engine; 1513 params.num_pf_cids = iids.cids; 1514 params.num_vf_cids = iids.vf_cids; 1515 params.num_tids = iids.tids; 1516 params.start_pq = qm_info->start_pq; 1517 params.num_pf_pqs = qm_info->num_pqs - qm_info->num_vf_pqs; 1518 params.num_vf_pqs = qm_info->num_vf_pqs; 1519 params.start_vport = qm_info->start_vport; 1520 params.num_vports = qm_info->num_vports; 1521 params.pf_wfq = qm_info->pf_wfq; 1522 params.pf_rl = qm_info->pf_rl; 1523 params.pq_params = qm_info->qm_pq_params; 1524 params.vport_params = qm_info->qm_vport_params; 1525 1526 qed_qm_pf_rt_init(p_hwfn, p_ptt, ¶ms); 1527 } 1528 1529 /* CM PF */ 1530 void qed_cm_init_pf(struct qed_hwfn *p_hwfn) 1531 { 1532 /* XCM pure-LB queue */ 1533 STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET, 1534 qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB)); 1535 } 1536 1537 /* DQ PF */ 1538 static void qed_dq_init_pf(struct qed_hwfn *p_hwfn) 1539 { 1540 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1541 u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0; 1542 1543 dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT); 1544 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid); 1545 1546 dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT); 1547 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid); 1548 1549 dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT); 1550 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid); 1551 1552 dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT); 1553 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid); 1554 1555 dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT); 1556 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid); 1557 1558 dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT); 1559 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid); 1560 1561 dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT); 1562 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid); 1563 1564 dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT); 1565 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid); 1566 1567 dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT); 1568 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid); 1569 1570 dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT); 1571 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid); 1572 1573 dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT); 1574 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid); 1575 1576 dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT); 1577 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid); 1578 1579 /* Connection types 6 & 7 are not in use, yet they must be configured 1580 * as the highest possible connection. Not configuring them means the 1581 * defaults will be used, and with a large number of cids a bug may 1582 * occur, if the defaults will be smaller than dq_pf_max_cid / 1583 * dq_vf_max_cid. 1584 */ 1585 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid); 1586 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid); 1587 1588 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid); 1589 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid); 1590 } 1591 1592 static void qed_ilt_bounds_init(struct qed_hwfn *p_hwfn) 1593 { 1594 struct qed_ilt_client_cfg *ilt_clients; 1595 int i; 1596 1597 ilt_clients = p_hwfn->p_cxt_mngr->clients; 1598 for_each_ilt_valid_client(i, ilt_clients) { 1599 STORE_RT_REG(p_hwfn, 1600 ilt_clients[i].first.reg, 1601 ilt_clients[i].first.val); 1602 STORE_RT_REG(p_hwfn, 1603 ilt_clients[i].last.reg, ilt_clients[i].last.val); 1604 STORE_RT_REG(p_hwfn, 1605 ilt_clients[i].p_size.reg, 1606 ilt_clients[i].p_size.val); 1607 } 1608 } 1609 1610 static void qed_ilt_vf_bounds_init(struct qed_hwfn *p_hwfn) 1611 { 1612 struct qed_ilt_client_cfg *p_cli; 1613 u32 blk_factor; 1614 1615 /* For simplicty we set the 'block' to be an ILT page */ 1616 if (p_hwfn->cdev->p_iov_info) { 1617 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info; 1618 1619 STORE_RT_REG(p_hwfn, 1620 PSWRQ2_REG_VF_BASE_RT_OFFSET, 1621 p_iov->first_vf_in_pf); 1622 STORE_RT_REG(p_hwfn, 1623 PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET, 1624 p_iov->first_vf_in_pf + p_iov->total_vfs); 1625 } 1626 1627 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 1628 blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10); 1629 if (p_cli->active) { 1630 STORE_RT_REG(p_hwfn, 1631 PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET, 1632 blk_factor); 1633 STORE_RT_REG(p_hwfn, 1634 PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET, 1635 p_cli->pf_total_lines); 1636 STORE_RT_REG(p_hwfn, 1637 PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET, 1638 p_cli->vf_total_lines); 1639 } 1640 1641 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 1642 blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10); 1643 if (p_cli->active) { 1644 STORE_RT_REG(p_hwfn, 1645 PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET, 1646 blk_factor); 1647 STORE_RT_REG(p_hwfn, 1648 PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET, 1649 p_cli->pf_total_lines); 1650 STORE_RT_REG(p_hwfn, 1651 PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET, 1652 p_cli->vf_total_lines); 1653 } 1654 1655 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM]; 1656 blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10); 1657 if (p_cli->active) { 1658 STORE_RT_REG(p_hwfn, 1659 PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor); 1660 STORE_RT_REG(p_hwfn, 1661 PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET, 1662 p_cli->pf_total_lines); 1663 STORE_RT_REG(p_hwfn, 1664 PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET, 1665 p_cli->vf_total_lines); 1666 } 1667 } 1668 1669 /* ILT (PSWRQ2) PF */ 1670 static void qed_ilt_init_pf(struct qed_hwfn *p_hwfn) 1671 { 1672 struct qed_ilt_client_cfg *clients; 1673 struct qed_cxt_mngr *p_mngr; 1674 struct qed_dma_mem *p_shdw; 1675 u32 line, rt_offst, i; 1676 1677 qed_ilt_bounds_init(p_hwfn); 1678 qed_ilt_vf_bounds_init(p_hwfn); 1679 1680 p_mngr = p_hwfn->p_cxt_mngr; 1681 p_shdw = p_mngr->ilt_shadow; 1682 clients = p_hwfn->p_cxt_mngr->clients; 1683 1684 for_each_ilt_valid_client(i, clients) { 1685 /** Client's 1st val and RT array are absolute, ILT shadows' 1686 * lines are relative. 1687 */ 1688 line = clients[i].first.val - p_mngr->pf_start_line; 1689 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET + 1690 clients[i].first.val * ILT_ENTRY_IN_REGS; 1691 1692 for (; line <= clients[i].last.val - p_mngr->pf_start_line; 1693 line++, rt_offst += ILT_ENTRY_IN_REGS) { 1694 u64 ilt_hw_entry = 0; 1695 1696 /** p_virt could be NULL incase of dynamic 1697 * allocation 1698 */ 1699 if (p_shdw[line].p_virt) { 1700 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL); 1701 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR, 1702 (p_shdw[line].p_phys >> 12)); 1703 1704 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 1705 "Setting RT[0x%08x] from ILT[0x%08x] [Client is %d] to Physical addr: 0x%llx\n", 1706 rt_offst, line, i, 1707 (u64)(p_shdw[line].p_phys >> 12)); 1708 } 1709 1710 STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry); 1711 } 1712 } 1713 } 1714 1715 /* SRC (Searcher) PF */ 1716 static void qed_src_init_pf(struct qed_hwfn *p_hwfn) 1717 { 1718 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1719 u32 rounded_conn_num, conn_num, conn_max; 1720 struct qed_src_iids src_iids; 1721 1722 memset(&src_iids, 0, sizeof(src_iids)); 1723 qed_cxt_src_iids(p_mngr, &src_iids); 1724 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count; 1725 if (!conn_num) 1726 return; 1727 1728 conn_max = max_t(u32, conn_num, SRC_MIN_NUM_ELEMS); 1729 rounded_conn_num = roundup_pow_of_two(conn_max); 1730 1731 STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num); 1732 STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET, 1733 ilog2(rounded_conn_num)); 1734 1735 STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET, 1736 p_hwfn->p_cxt_mngr->first_free); 1737 STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET, 1738 p_hwfn->p_cxt_mngr->last_free); 1739 } 1740 1741 /* Timers PF */ 1742 #define TM_CFG_NUM_IDS_SHIFT 0 1743 #define TM_CFG_NUM_IDS_MASK 0xFFFFULL 1744 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT 16 1745 #define TM_CFG_PRE_SCAN_OFFSET_MASK 0x1FFULL 1746 #define TM_CFG_PARENT_PF_SHIFT 25 1747 #define TM_CFG_PARENT_PF_MASK 0x7ULL 1748 1749 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT 30 1750 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK 0x1FFULL 1751 1752 #define TM_CFG_TID_OFFSET_SHIFT 30 1753 #define TM_CFG_TID_OFFSET_MASK 0x7FFFFULL 1754 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT 49 1755 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK 0x1FFULL 1756 1757 static void qed_tm_init_pf(struct qed_hwfn *p_hwfn) 1758 { 1759 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1760 u32 active_seg_mask = 0, tm_offset, rt_reg; 1761 struct qed_tm_iids tm_iids; 1762 u64 cfg_word; 1763 u8 i; 1764 1765 memset(&tm_iids, 0, sizeof(tm_iids)); 1766 qed_cxt_tm_iids(p_hwfn, p_mngr, &tm_iids); 1767 1768 /* @@@TBD No pre-scan for now */ 1769 1770 /* Note: We assume consecutive VFs for a PF */ 1771 for (i = 0; i < p_mngr->vf_count; i++) { 1772 cfg_word = 0; 1773 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids); 1774 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1775 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id); 1776 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); 1777 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET + 1778 (sizeof(cfg_word) / sizeof(u32)) * 1779 (p_hwfn->cdev->p_iov_info->first_vf_in_pf + i); 1780 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1781 } 1782 1783 cfg_word = 0; 1784 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids); 1785 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1786 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); /* n/a for PF */ 1787 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */ 1788 1789 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET + 1790 (sizeof(cfg_word) / sizeof(u32)) * 1791 (NUM_OF_VFS(p_hwfn->cdev) + p_hwfn->rel_pf_id); 1792 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1793 1794 /* enale scan */ 1795 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET, 1796 tm_iids.pf_cids ? 0x1 : 0x0); 1797 1798 /* @@@TBD how to enable the scan for the VFs */ 1799 1800 tm_offset = tm_iids.per_vf_cids; 1801 1802 /* Note: We assume consecutive VFs for a PF */ 1803 for (i = 0; i < p_mngr->vf_count; i++) { 1804 cfg_word = 0; 1805 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids); 1806 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1807 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id); 1808 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset); 1809 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0); 1810 1811 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET + 1812 (sizeof(cfg_word) / sizeof(u32)) * 1813 (p_hwfn->cdev->p_iov_info->first_vf_in_pf + i); 1814 1815 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1816 } 1817 1818 tm_offset = tm_iids.pf_cids; 1819 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 1820 cfg_word = 0; 1821 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]); 1822 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1823 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); 1824 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset); 1825 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0); 1826 1827 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET + 1828 (sizeof(cfg_word) / sizeof(u32)) * 1829 (NUM_OF_VFS(p_hwfn->cdev) + 1830 p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i); 1831 1832 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1833 active_seg_mask |= (tm_iids.pf_tids[i] ? BIT(i) : 0); 1834 1835 tm_offset += tm_iids.pf_tids[i]; 1836 } 1837 1838 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) 1839 active_seg_mask = 0; 1840 1841 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask); 1842 1843 /* @@@TBD how to enable the scan for the VFs */ 1844 } 1845 1846 static void qed_prs_init_common(struct qed_hwfn *p_hwfn) 1847 { 1848 if ((p_hwfn->hw_info.personality == QED_PCI_FCOE) && 1849 p_hwfn->pf_params.fcoe_pf_params.is_target) 1850 STORE_RT_REG(p_hwfn, 1851 PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET, 0); 1852 } 1853 1854 static void qed_prs_init_pf(struct qed_hwfn *p_hwfn) 1855 { 1856 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1857 struct qed_conn_type_cfg *p_fcoe; 1858 struct qed_tid_seg *p_tid; 1859 1860 p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE]; 1861 1862 /* If FCoE is active set the MAX OX_ID (tid) in the Parser */ 1863 if (!p_fcoe->cid_count) 1864 return; 1865 1866 p_tid = &p_fcoe->tid_seg[QED_CXT_FCOE_TID_SEG]; 1867 if (p_hwfn->pf_params.fcoe_pf_params.is_target) { 1868 STORE_RT_REG_AGG(p_hwfn, 1869 PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET, 1870 p_tid->count); 1871 } else { 1872 STORE_RT_REG_AGG(p_hwfn, 1873 PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET, 1874 p_tid->count); 1875 } 1876 } 1877 1878 void qed_cxt_hw_init_common(struct qed_hwfn *p_hwfn) 1879 { 1880 qed_cdu_init_common(p_hwfn); 1881 qed_prs_init_common(p_hwfn); 1882 } 1883 1884 void qed_cxt_hw_init_pf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1885 { 1886 qed_qm_init_pf(p_hwfn, p_ptt); 1887 qed_cm_init_pf(p_hwfn); 1888 qed_dq_init_pf(p_hwfn); 1889 qed_cdu_init_pf(p_hwfn); 1890 qed_ilt_init_pf(p_hwfn); 1891 qed_src_init_pf(p_hwfn); 1892 qed_tm_init_pf(p_hwfn); 1893 qed_prs_init_pf(p_hwfn); 1894 } 1895 1896 int _qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn, 1897 enum protocol_type type, u32 *p_cid, u8 vfid) 1898 { 1899 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1900 struct qed_cid_acquired_map *p_map; 1901 u32 rel_cid; 1902 1903 if (type >= MAX_CONN_TYPES) { 1904 DP_NOTICE(p_hwfn, "Invalid protocol type %d", type); 1905 return -EINVAL; 1906 } 1907 1908 if (vfid >= MAX_NUM_VFS && vfid != QED_CXT_PF_CID) { 1909 DP_NOTICE(p_hwfn, "VF [%02x] is out of range\n", vfid); 1910 return -EINVAL; 1911 } 1912 1913 /* Determine the right map to take this CID from */ 1914 if (vfid == QED_CXT_PF_CID) 1915 p_map = &p_mngr->acquired[type]; 1916 else 1917 p_map = &p_mngr->acquired_vf[type][vfid]; 1918 1919 if (!p_map->cid_map) { 1920 DP_NOTICE(p_hwfn, "Invalid protocol type %d", type); 1921 return -EINVAL; 1922 } 1923 1924 rel_cid = find_first_zero_bit(p_map->cid_map, p_map->max_count); 1925 1926 if (rel_cid >= p_map->max_count) { 1927 DP_NOTICE(p_hwfn, "no CID available for protocol %d\n", type); 1928 return -EINVAL; 1929 } 1930 1931 __set_bit(rel_cid, p_map->cid_map); 1932 1933 *p_cid = rel_cid + p_map->start_cid; 1934 1935 DP_VERBOSE(p_hwfn, QED_MSG_CXT, 1936 "Acquired cid 0x%08x [rel. %08x] vfid %02x type %d\n", 1937 *p_cid, rel_cid, vfid, type); 1938 1939 return 0; 1940 } 1941 1942 int qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn, 1943 enum protocol_type type, u32 *p_cid) 1944 { 1945 return _qed_cxt_acquire_cid(p_hwfn, type, p_cid, QED_CXT_PF_CID); 1946 } 1947 1948 static bool qed_cxt_test_cid_acquired(struct qed_hwfn *p_hwfn, 1949 u32 cid, 1950 u8 vfid, 1951 enum protocol_type *p_type, 1952 struct qed_cid_acquired_map **pp_map) 1953 { 1954 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1955 u32 rel_cid; 1956 1957 /* Iterate over protocols and find matching cid range */ 1958 for (*p_type = 0; *p_type < MAX_CONN_TYPES; (*p_type)++) { 1959 if (vfid == QED_CXT_PF_CID) 1960 *pp_map = &p_mngr->acquired[*p_type]; 1961 else 1962 *pp_map = &p_mngr->acquired_vf[*p_type][vfid]; 1963 1964 if (!((*pp_map)->cid_map)) 1965 continue; 1966 if (cid >= (*pp_map)->start_cid && 1967 cid < (*pp_map)->start_cid + (*pp_map)->max_count) 1968 break; 1969 } 1970 1971 if (*p_type == MAX_CONN_TYPES) { 1972 DP_NOTICE(p_hwfn, "Invalid CID %d vfid %02x", cid, vfid); 1973 goto fail; 1974 } 1975 1976 rel_cid = cid - (*pp_map)->start_cid; 1977 if (!test_bit(rel_cid, (*pp_map)->cid_map)) { 1978 DP_NOTICE(p_hwfn, "CID %d [vifd %02x] not acquired", 1979 cid, vfid); 1980 goto fail; 1981 } 1982 1983 return true; 1984 fail: 1985 *p_type = MAX_CONN_TYPES; 1986 *pp_map = NULL; 1987 return false; 1988 } 1989 1990 void _qed_cxt_release_cid(struct qed_hwfn *p_hwfn, u32 cid, u8 vfid) 1991 { 1992 struct qed_cid_acquired_map *p_map = NULL; 1993 enum protocol_type type; 1994 bool b_acquired; 1995 u32 rel_cid; 1996 1997 if (vfid != QED_CXT_PF_CID && vfid > MAX_NUM_VFS) { 1998 DP_NOTICE(p_hwfn, 1999 "Trying to return incorrect CID belonging to VF %02x\n", 2000 vfid); 2001 return; 2002 } 2003 2004 /* Test acquired and find matching per-protocol map */ 2005 b_acquired = qed_cxt_test_cid_acquired(p_hwfn, cid, vfid, 2006 &type, &p_map); 2007 2008 if (!b_acquired) 2009 return; 2010 2011 rel_cid = cid - p_map->start_cid; 2012 clear_bit(rel_cid, p_map->cid_map); 2013 2014 DP_VERBOSE(p_hwfn, QED_MSG_CXT, 2015 "Released CID 0x%08x [rel. %08x] vfid %02x type %d\n", 2016 cid, rel_cid, vfid, type); 2017 } 2018 2019 void qed_cxt_release_cid(struct qed_hwfn *p_hwfn, u32 cid) 2020 { 2021 _qed_cxt_release_cid(p_hwfn, cid, QED_CXT_PF_CID); 2022 } 2023 2024 int qed_cxt_get_cid_info(struct qed_hwfn *p_hwfn, struct qed_cxt_info *p_info) 2025 { 2026 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 2027 struct qed_cid_acquired_map *p_map = NULL; 2028 u32 conn_cxt_size, hw_p_size, cxts_per_p, line; 2029 enum protocol_type type; 2030 bool b_acquired; 2031 2032 /* Test acquired and find matching per-protocol map */ 2033 b_acquired = qed_cxt_test_cid_acquired(p_hwfn, p_info->iid, 2034 QED_CXT_PF_CID, &type, &p_map); 2035 2036 if (!b_acquired) 2037 return -EINVAL; 2038 2039 /* set the protocl type */ 2040 p_info->type = type; 2041 2042 /* compute context virtual pointer */ 2043 hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val; 2044 2045 conn_cxt_size = CONN_CXT_SIZE(p_hwfn); 2046 cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size; 2047 line = p_info->iid / cxts_per_p; 2048 2049 /* Make sure context is allocated (dynamic allocation) */ 2050 if (!p_mngr->ilt_shadow[line].p_virt) 2051 return -EINVAL; 2052 2053 p_info->p_cxt = p_mngr->ilt_shadow[line].p_virt + 2054 p_info->iid % cxts_per_p * conn_cxt_size; 2055 2056 DP_VERBOSE(p_hwfn, (QED_MSG_ILT | QED_MSG_CXT), 2057 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n", 2058 p_info->iid / cxts_per_p, p_info->p_cxt, p_info->iid); 2059 2060 return 0; 2061 } 2062 2063 static void qed_rdma_set_pf_params(struct qed_hwfn *p_hwfn, 2064 struct qed_rdma_pf_params *p_params, 2065 u32 num_tasks) 2066 { 2067 u32 num_cons, num_qps, num_srqs; 2068 enum protocol_type proto; 2069 2070 num_srqs = min_t(u32, 32 * 1024, p_params->num_srqs); 2071 2072 switch (p_hwfn->hw_info.personality) { 2073 case QED_PCI_ETH_IWARP: 2074 /* Each QP requires one connection */ 2075 num_cons = min_t(u32, IWARP_MAX_QPS, p_params->num_qps); 2076 proto = PROTOCOLID_IWARP; 2077 break; 2078 case QED_PCI_ETH_ROCE: 2079 num_qps = min_t(u32, ROCE_MAX_QPS, p_params->num_qps); 2080 num_cons = num_qps * 2; /* each QP requires two connections */ 2081 proto = PROTOCOLID_ROCE; 2082 break; 2083 default: 2084 return; 2085 } 2086 2087 if (num_cons && num_tasks) { 2088 qed_cxt_set_proto_cid_count(p_hwfn, proto, num_cons, 0); 2089 2090 /* Deliberatly passing ROCE for tasks id. This is because 2091 * iWARP / RoCE share the task id. 2092 */ 2093 qed_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_ROCE, 2094 QED_CXT_ROCE_TID_SEG, 1, 2095 num_tasks, false); 2096 qed_cxt_set_srq_count(p_hwfn, num_srqs); 2097 } else { 2098 DP_INFO(p_hwfn->cdev, 2099 "RDMA personality used without setting params!\n"); 2100 } 2101 } 2102 2103 int qed_cxt_set_pf_params(struct qed_hwfn *p_hwfn, u32 rdma_tasks) 2104 { 2105 /* Set the number of required CORE connections */ 2106 u32 core_cids = 1; /* SPQ */ 2107 2108 if (p_hwfn->using_ll2) 2109 core_cids += 4; 2110 qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0); 2111 2112 switch (p_hwfn->hw_info.personality) { 2113 case QED_PCI_ETH_RDMA: 2114 case QED_PCI_ETH_IWARP: 2115 case QED_PCI_ETH_ROCE: 2116 { 2117 qed_rdma_set_pf_params(p_hwfn, 2118 &p_hwfn-> 2119 pf_params.rdma_pf_params, 2120 rdma_tasks); 2121 /* no need for break since RoCE coexist with Ethernet */ 2122 } 2123 case QED_PCI_ETH: 2124 { 2125 struct qed_eth_pf_params *p_params = 2126 &p_hwfn->pf_params.eth_pf_params; 2127 2128 if (!p_params->num_vf_cons) 2129 p_params->num_vf_cons = 2130 ETH_PF_PARAMS_VF_CONS_DEFAULT; 2131 qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH, 2132 p_params->num_cons, 2133 p_params->num_vf_cons); 2134 p_hwfn->p_cxt_mngr->arfs_count = p_params->num_arfs_filters; 2135 break; 2136 } 2137 case QED_PCI_FCOE: 2138 { 2139 struct qed_fcoe_pf_params *p_params; 2140 2141 p_params = &p_hwfn->pf_params.fcoe_pf_params; 2142 2143 if (p_params->num_cons && p_params->num_tasks) { 2144 qed_cxt_set_proto_cid_count(p_hwfn, 2145 PROTOCOLID_FCOE, 2146 p_params->num_cons, 2147 0); 2148 2149 qed_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_FCOE, 2150 QED_CXT_FCOE_TID_SEG, 0, 2151 p_params->num_tasks, true); 2152 } else { 2153 DP_INFO(p_hwfn->cdev, 2154 "Fcoe personality used without setting params!\n"); 2155 } 2156 break; 2157 } 2158 case QED_PCI_ISCSI: 2159 { 2160 struct qed_iscsi_pf_params *p_params; 2161 2162 p_params = &p_hwfn->pf_params.iscsi_pf_params; 2163 2164 if (p_params->num_cons && p_params->num_tasks) { 2165 qed_cxt_set_proto_cid_count(p_hwfn, 2166 PROTOCOLID_ISCSI, 2167 p_params->num_cons, 2168 0); 2169 2170 qed_cxt_set_proto_tid_count(p_hwfn, 2171 PROTOCOLID_ISCSI, 2172 QED_CXT_ISCSI_TID_SEG, 2173 0, 2174 p_params->num_tasks, 2175 true); 2176 } else { 2177 DP_INFO(p_hwfn->cdev, 2178 "Iscsi personality used without setting params!\n"); 2179 } 2180 break; 2181 } 2182 default: 2183 return -EINVAL; 2184 } 2185 2186 return 0; 2187 } 2188 2189 int qed_cxt_get_tid_mem_info(struct qed_hwfn *p_hwfn, 2190 struct qed_tid_mem *p_info) 2191 { 2192 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 2193 u32 proto, seg, total_lines, i, shadow_line; 2194 struct qed_ilt_client_cfg *p_cli; 2195 struct qed_ilt_cli_blk *p_fl_seg; 2196 struct qed_tid_seg *p_seg_info; 2197 2198 /* Verify the personality */ 2199 switch (p_hwfn->hw_info.personality) { 2200 case QED_PCI_FCOE: 2201 proto = PROTOCOLID_FCOE; 2202 seg = QED_CXT_FCOE_TID_SEG; 2203 break; 2204 case QED_PCI_ISCSI: 2205 proto = PROTOCOLID_ISCSI; 2206 seg = QED_CXT_ISCSI_TID_SEG; 2207 break; 2208 default: 2209 return -EINVAL; 2210 } 2211 2212 p_cli = &p_mngr->clients[ILT_CLI_CDUT]; 2213 if (!p_cli->active) 2214 return -EINVAL; 2215 2216 p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg]; 2217 if (!p_seg_info->has_fl_mem) 2218 return -EINVAL; 2219 2220 p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)]; 2221 total_lines = DIV_ROUND_UP(p_fl_seg->total_size, 2222 p_fl_seg->real_size_in_page); 2223 2224 for (i = 0; i < total_lines; i++) { 2225 shadow_line = i + p_fl_seg->start_line - 2226 p_hwfn->p_cxt_mngr->pf_start_line; 2227 p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].p_virt; 2228 } 2229 p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) - 2230 p_fl_seg->real_size_in_page; 2231 p_info->tid_size = p_mngr->task_type_size[p_seg_info->type]; 2232 p_info->num_tids_per_block = p_fl_seg->real_size_in_page / 2233 p_info->tid_size; 2234 2235 return 0; 2236 } 2237 2238 /* This function is very RoCE oriented, if another protocol in the future 2239 * will want this feature we'll need to modify the function to be more generic 2240 */ 2241 int 2242 qed_cxt_dynamic_ilt_alloc(struct qed_hwfn *p_hwfn, 2243 enum qed_cxt_elem_type elem_type, u32 iid) 2244 { 2245 u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line; 2246 struct qed_ilt_client_cfg *p_cli; 2247 struct qed_ilt_cli_blk *p_blk; 2248 struct qed_ptt *p_ptt; 2249 dma_addr_t p_phys; 2250 u64 ilt_hw_entry; 2251 void *p_virt; 2252 int rc = 0; 2253 2254 switch (elem_type) { 2255 case QED_ELEM_CXT: 2256 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 2257 elem_size = CONN_CXT_SIZE(p_hwfn); 2258 p_blk = &p_cli->pf_blks[CDUC_BLK]; 2259 break; 2260 case QED_ELEM_SRQ: 2261 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM]; 2262 elem_size = SRQ_CXT_SIZE; 2263 p_blk = &p_cli->pf_blks[SRQ_BLK]; 2264 break; 2265 case QED_ELEM_TASK: 2266 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2267 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn); 2268 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)]; 2269 break; 2270 default: 2271 DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type); 2272 return -EINVAL; 2273 } 2274 2275 /* Calculate line in ilt */ 2276 hw_p_size = p_cli->p_size.val; 2277 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size; 2278 line = p_blk->start_line + (iid / elems_per_p); 2279 shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line; 2280 2281 /* If line is already allocated, do nothing, otherwise allocate it and 2282 * write it to the PSWRQ2 registers. 2283 * This section can be run in parallel from different contexts and thus 2284 * a mutex protection is needed. 2285 */ 2286 2287 mutex_lock(&p_hwfn->p_cxt_mngr->mutex); 2288 2289 if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt) 2290 goto out0; 2291 2292 p_ptt = qed_ptt_acquire(p_hwfn); 2293 if (!p_ptt) { 2294 DP_NOTICE(p_hwfn, 2295 "QED_TIME_OUT on ptt acquire - dynamic allocation"); 2296 rc = -EBUSY; 2297 goto out0; 2298 } 2299 2300 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 2301 p_blk->real_size_in_page, 2302 &p_phys, GFP_KERNEL); 2303 if (!p_virt) { 2304 rc = -ENOMEM; 2305 goto out1; 2306 } 2307 memset(p_virt, 0, p_blk->real_size_in_page); 2308 2309 /* configuration of refTagMask to 0xF is required for RoCE DIF MR only, 2310 * to compensate for a HW bug, but it is configured even if DIF is not 2311 * enabled. This is harmless and allows us to avoid a dedicated API. We 2312 * configure the field for all of the contexts on the newly allocated 2313 * page. 2314 */ 2315 if (elem_type == QED_ELEM_TASK) { 2316 u32 elem_i; 2317 u8 *elem_start = (u8 *)p_virt; 2318 union type1_task_context *elem; 2319 2320 for (elem_i = 0; elem_i < elems_per_p; elem_i++) { 2321 elem = (union type1_task_context *)elem_start; 2322 SET_FIELD(elem->roce_ctx.tdif_context.flags1, 2323 TDIF_TASK_CONTEXT_REFTAGMASK, 0xf); 2324 elem_start += TYPE1_TASK_CXT_SIZE(p_hwfn); 2325 } 2326 } 2327 2328 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt; 2329 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys; 2330 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size = 2331 p_blk->real_size_in_page; 2332 2333 /* compute absolute offset */ 2334 reg_offset = PSWRQ2_REG_ILT_MEMORY + 2335 (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS); 2336 2337 ilt_hw_entry = 0; 2338 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL); 2339 SET_FIELD(ilt_hw_entry, 2340 ILT_ENTRY_PHY_ADDR, 2341 (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12)); 2342 2343 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */ 2344 qed_dmae_host2grc(p_hwfn, p_ptt, (u64) (uintptr_t)&ilt_hw_entry, 2345 reg_offset, sizeof(ilt_hw_entry) / sizeof(u32), 0); 2346 2347 if (elem_type == QED_ELEM_CXT) { 2348 u32 last_cid_allocated = (1 + (iid / elems_per_p)) * 2349 elems_per_p; 2350 2351 /* Update the relevant register in the parser */ 2352 qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 2353 last_cid_allocated - 1); 2354 2355 if (!p_hwfn->b_rdma_enabled_in_prs) { 2356 /* Enable RDMA search */ 2357 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1); 2358 p_hwfn->b_rdma_enabled_in_prs = true; 2359 } 2360 } 2361 2362 out1: 2363 qed_ptt_release(p_hwfn, p_ptt); 2364 out0: 2365 mutex_unlock(&p_hwfn->p_cxt_mngr->mutex); 2366 2367 return rc; 2368 } 2369 2370 /* This function is very RoCE oriented, if another protocol in the future 2371 * will want this feature we'll need to modify the function to be more generic 2372 */ 2373 static int 2374 qed_cxt_free_ilt_range(struct qed_hwfn *p_hwfn, 2375 enum qed_cxt_elem_type elem_type, 2376 u32 start_iid, u32 count) 2377 { 2378 u32 start_line, end_line, shadow_start_line, shadow_end_line; 2379 u32 reg_offset, elem_size, hw_p_size, elems_per_p; 2380 struct qed_ilt_client_cfg *p_cli; 2381 struct qed_ilt_cli_blk *p_blk; 2382 u32 end_iid = start_iid + count; 2383 struct qed_ptt *p_ptt; 2384 u64 ilt_hw_entry = 0; 2385 u32 i; 2386 2387 switch (elem_type) { 2388 case QED_ELEM_CXT: 2389 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 2390 elem_size = CONN_CXT_SIZE(p_hwfn); 2391 p_blk = &p_cli->pf_blks[CDUC_BLK]; 2392 break; 2393 case QED_ELEM_SRQ: 2394 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM]; 2395 elem_size = SRQ_CXT_SIZE; 2396 p_blk = &p_cli->pf_blks[SRQ_BLK]; 2397 break; 2398 case QED_ELEM_TASK: 2399 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2400 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn); 2401 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)]; 2402 break; 2403 default: 2404 DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type); 2405 return -EINVAL; 2406 } 2407 2408 /* Calculate line in ilt */ 2409 hw_p_size = p_cli->p_size.val; 2410 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size; 2411 start_line = p_blk->start_line + (start_iid / elems_per_p); 2412 end_line = p_blk->start_line + (end_iid / elems_per_p); 2413 if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p)) 2414 end_line--; 2415 2416 shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line; 2417 shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line; 2418 2419 p_ptt = qed_ptt_acquire(p_hwfn); 2420 if (!p_ptt) { 2421 DP_NOTICE(p_hwfn, 2422 "QED_TIME_OUT on ptt acquire - dynamic allocation"); 2423 return -EBUSY; 2424 } 2425 2426 for (i = shadow_start_line; i < shadow_end_line; i++) { 2427 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt) 2428 continue; 2429 2430 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 2431 p_hwfn->p_cxt_mngr->ilt_shadow[i].size, 2432 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt, 2433 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys); 2434 2435 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = NULL; 2436 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0; 2437 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0; 2438 2439 /* compute absolute offset */ 2440 reg_offset = PSWRQ2_REG_ILT_MEMORY + 2441 ((start_line++) * ILT_REG_SIZE_IN_BYTES * 2442 ILT_ENTRY_IN_REGS); 2443 2444 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a 2445 * wide-bus. 2446 */ 2447 qed_dmae_host2grc(p_hwfn, p_ptt, 2448 (u64) (uintptr_t) &ilt_hw_entry, 2449 reg_offset, 2450 sizeof(ilt_hw_entry) / sizeof(u32), 2451 0); 2452 } 2453 2454 qed_ptt_release(p_hwfn, p_ptt); 2455 2456 return 0; 2457 } 2458 2459 int qed_cxt_free_proto_ilt(struct qed_hwfn *p_hwfn, enum protocol_type proto) 2460 { 2461 int rc; 2462 u32 cid; 2463 2464 /* Free Connection CXT */ 2465 rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_CXT, 2466 qed_cxt_get_proto_cid_start(p_hwfn, 2467 proto), 2468 qed_cxt_get_proto_cid_count(p_hwfn, 2469 proto, &cid)); 2470 2471 if (rc) 2472 return rc; 2473 2474 /* Free Task CXT */ 2475 rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_TASK, 0, 2476 qed_cxt_get_proto_tid_count(p_hwfn, proto)); 2477 if (rc) 2478 return rc; 2479 2480 /* Free TSDM CXT */ 2481 rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_SRQ, 0, 2482 qed_cxt_get_srq_count(p_hwfn)); 2483 2484 return rc; 2485 } 2486 2487 int qed_cxt_get_task_ctx(struct qed_hwfn *p_hwfn, 2488 u32 tid, u8 ctx_type, void **pp_task_ctx) 2489 { 2490 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 2491 struct qed_ilt_client_cfg *p_cli; 2492 struct qed_tid_seg *p_seg_info; 2493 struct qed_ilt_cli_blk *p_seg; 2494 u32 num_tids_per_block; 2495 u32 tid_size, ilt_idx; 2496 u32 total_lines; 2497 u32 proto, seg; 2498 2499 /* Verify the personality */ 2500 switch (p_hwfn->hw_info.personality) { 2501 case QED_PCI_FCOE: 2502 proto = PROTOCOLID_FCOE; 2503 seg = QED_CXT_FCOE_TID_SEG; 2504 break; 2505 case QED_PCI_ISCSI: 2506 proto = PROTOCOLID_ISCSI; 2507 seg = QED_CXT_ISCSI_TID_SEG; 2508 break; 2509 default: 2510 return -EINVAL; 2511 } 2512 2513 p_cli = &p_mngr->clients[ILT_CLI_CDUT]; 2514 if (!p_cli->active) 2515 return -EINVAL; 2516 2517 p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg]; 2518 2519 if (ctx_type == QED_CTX_WORKING_MEM) { 2520 p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)]; 2521 } else if (ctx_type == QED_CTX_FL_MEM) { 2522 if (!p_seg_info->has_fl_mem) 2523 return -EINVAL; 2524 p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)]; 2525 } else { 2526 return -EINVAL; 2527 } 2528 total_lines = DIV_ROUND_UP(p_seg->total_size, p_seg->real_size_in_page); 2529 tid_size = p_mngr->task_type_size[p_seg_info->type]; 2530 num_tids_per_block = p_seg->real_size_in_page / tid_size; 2531 2532 if (total_lines < tid / num_tids_per_block) 2533 return -EINVAL; 2534 2535 ilt_idx = tid / num_tids_per_block + p_seg->start_line - 2536 p_mngr->pf_start_line; 2537 *pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].p_virt + 2538 (tid % num_tids_per_block) * tid_size; 2539 2540 return 0; 2541 } 2542