1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/types.h> 34 #include <linux/bitops.h> 35 #include <linux/dma-mapping.h> 36 #include <linux/errno.h> 37 #include <linux/kernel.h> 38 #include <linux/list.h> 39 #include <linux/log2.h> 40 #include <linux/pci.h> 41 #include <linux/slab.h> 42 #include <linux/string.h> 43 #include "qed.h" 44 #include "qed_cxt.h" 45 #include "qed_dev_api.h" 46 #include "qed_hsi.h" 47 #include "qed_hw.h" 48 #include "qed_init_ops.h" 49 #include "qed_rdma.h" 50 #include "qed_reg_addr.h" 51 #include "qed_sriov.h" 52 53 /* QM constants */ 54 #define QM_PQ_ELEMENT_SIZE 4 /* in bytes */ 55 56 /* Doorbell-Queue constants */ 57 #define DQ_RANGE_SHIFT 4 58 #define DQ_RANGE_ALIGN BIT(DQ_RANGE_SHIFT) 59 60 /* Searcher constants */ 61 #define SRC_MIN_NUM_ELEMS 256 62 63 /* Timers constants */ 64 #define TM_SHIFT 7 65 #define TM_ALIGN BIT(TM_SHIFT) 66 #define TM_ELEM_SIZE 4 67 68 #define ILT_DEFAULT_HW_P_SIZE 4 69 70 #define ILT_PAGE_IN_BYTES(hw_p_size) (1U << ((hw_p_size) + 12)) 71 #define ILT_CFG_REG(cli, reg) PSWRQ2_REG_ ## cli ## _ ## reg ## _RT_OFFSET 72 73 /* ILT entry structure */ 74 #define ILT_ENTRY_PHY_ADDR_MASK (~0ULL >> 12) 75 #define ILT_ENTRY_PHY_ADDR_SHIFT 0 76 #define ILT_ENTRY_VALID_MASK 0x1ULL 77 #define ILT_ENTRY_VALID_SHIFT 52 78 #define ILT_ENTRY_IN_REGS 2 79 #define ILT_REG_SIZE_IN_BYTES 4 80 81 /* connection context union */ 82 union conn_context { 83 struct e4_core_conn_context core_ctx; 84 struct e4_eth_conn_context eth_ctx; 85 struct e4_iscsi_conn_context iscsi_ctx; 86 struct e4_fcoe_conn_context fcoe_ctx; 87 struct e4_roce_conn_context roce_ctx; 88 }; 89 90 /* TYPE-0 task context - iSCSI, FCOE */ 91 union type0_task_context { 92 struct e4_iscsi_task_context iscsi_ctx; 93 struct e4_fcoe_task_context fcoe_ctx; 94 }; 95 96 /* TYPE-1 task context - ROCE */ 97 union type1_task_context { 98 struct e4_rdma_task_context roce_ctx; 99 }; 100 101 struct src_ent { 102 u8 opaque[56]; 103 u64 next; 104 }; 105 106 #define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */ 107 #define CDUT_SEG_ALIGNMET_IN_BYTES BIT(CDUT_SEG_ALIGNMET + 12) 108 109 #define CONN_CXT_SIZE(p_hwfn) \ 110 ALIGNED_TYPE_SIZE(union conn_context, p_hwfn) 111 112 #define SRQ_CXT_SIZE (sizeof(struct rdma_srq_context)) 113 114 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \ 115 ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn) 116 117 /* Alignment is inherent to the type1_task_context structure */ 118 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context) 119 120 static bool src_proto(enum protocol_type type) 121 { 122 return type == PROTOCOLID_ISCSI || 123 type == PROTOCOLID_FCOE || 124 type == PROTOCOLID_IWARP; 125 } 126 127 static bool tm_cid_proto(enum protocol_type type) 128 { 129 return type == PROTOCOLID_ISCSI || 130 type == PROTOCOLID_FCOE || 131 type == PROTOCOLID_ROCE || 132 type == PROTOCOLID_IWARP; 133 } 134 135 static bool tm_tid_proto(enum protocol_type type) 136 { 137 return type == PROTOCOLID_FCOE; 138 } 139 140 /* counts the iids for the CDU/CDUC ILT client configuration */ 141 struct qed_cdu_iids { 142 u32 pf_cids; 143 u32 per_vf_cids; 144 }; 145 146 static void qed_cxt_cdu_iids(struct qed_cxt_mngr *p_mngr, 147 struct qed_cdu_iids *iids) 148 { 149 u32 type; 150 151 for (type = 0; type < MAX_CONN_TYPES; type++) { 152 iids->pf_cids += p_mngr->conn_cfg[type].cid_count; 153 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf; 154 } 155 } 156 157 /* counts the iids for the Searcher block configuration */ 158 struct qed_src_iids { 159 u32 pf_cids; 160 u32 per_vf_cids; 161 }; 162 163 static void qed_cxt_src_iids(struct qed_cxt_mngr *p_mngr, 164 struct qed_src_iids *iids) 165 { 166 u32 i; 167 168 for (i = 0; i < MAX_CONN_TYPES; i++) { 169 if (!src_proto(i)) 170 continue; 171 172 iids->pf_cids += p_mngr->conn_cfg[i].cid_count; 173 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf; 174 } 175 176 /* Add L2 filtering filters in addition */ 177 iids->pf_cids += p_mngr->arfs_count; 178 } 179 180 /* counts the iids for the Timers block configuration */ 181 struct qed_tm_iids { 182 u32 pf_cids; 183 u32 pf_tids[NUM_TASK_PF_SEGMENTS]; /* per segment */ 184 u32 pf_tids_total; 185 u32 per_vf_cids; 186 u32 per_vf_tids; 187 }; 188 189 static void qed_cxt_tm_iids(struct qed_hwfn *p_hwfn, 190 struct qed_cxt_mngr *p_mngr, 191 struct qed_tm_iids *iids) 192 { 193 bool tm_vf_required = false; 194 bool tm_required = false; 195 int i, j; 196 197 /* Timers is a special case -> we don't count how many cids require 198 * timers but what's the max cid that will be used by the timer block. 199 * therefore we traverse in reverse order, and once we hit a protocol 200 * that requires the timers memory, we'll sum all the protocols up 201 * to that one. 202 */ 203 for (i = MAX_CONN_TYPES - 1; i >= 0; i--) { 204 struct qed_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i]; 205 206 if (tm_cid_proto(i) || tm_required) { 207 if (p_cfg->cid_count) 208 tm_required = true; 209 210 iids->pf_cids += p_cfg->cid_count; 211 } 212 213 if (tm_cid_proto(i) || tm_vf_required) { 214 if (p_cfg->cids_per_vf) 215 tm_vf_required = true; 216 217 iids->per_vf_cids += p_cfg->cids_per_vf; 218 } 219 220 if (tm_tid_proto(i)) { 221 struct qed_tid_seg *segs = p_cfg->tid_seg; 222 223 /* for each segment there is at most one 224 * protocol for which count is not 0. 225 */ 226 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++) 227 iids->pf_tids[j] += segs[j].count; 228 229 /* The last array elelment is for the VFs. As for PF 230 * segments there can be only one protocol for 231 * which this value is not 0. 232 */ 233 iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count; 234 } 235 } 236 237 iids->pf_cids = roundup(iids->pf_cids, TM_ALIGN); 238 iids->per_vf_cids = roundup(iids->per_vf_cids, TM_ALIGN); 239 iids->per_vf_tids = roundup(iids->per_vf_tids, TM_ALIGN); 240 241 for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) { 242 iids->pf_tids[j] = roundup(iids->pf_tids[j], TM_ALIGN); 243 iids->pf_tids_total += iids->pf_tids[j]; 244 } 245 } 246 247 static void qed_cxt_qm_iids(struct qed_hwfn *p_hwfn, 248 struct qed_qm_iids *iids) 249 { 250 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 251 struct qed_tid_seg *segs; 252 u32 vf_cids = 0, type, j; 253 u32 vf_tids = 0; 254 255 for (type = 0; type < MAX_CONN_TYPES; type++) { 256 iids->cids += p_mngr->conn_cfg[type].cid_count; 257 vf_cids += p_mngr->conn_cfg[type].cids_per_vf; 258 259 segs = p_mngr->conn_cfg[type].tid_seg; 260 /* for each segment there is at most one 261 * protocol for which count is not 0. 262 */ 263 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++) 264 iids->tids += segs[j].count; 265 266 /* The last array elelment is for the VFs. As for PF 267 * segments there can be only one protocol for 268 * which this value is not 0. 269 */ 270 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count; 271 } 272 273 iids->vf_cids += vf_cids * p_mngr->vf_count; 274 iids->tids += vf_tids * p_mngr->vf_count; 275 276 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 277 "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n", 278 iids->cids, iids->vf_cids, iids->tids, vf_tids); 279 } 280 281 static struct qed_tid_seg *qed_cxt_tid_seg_info(struct qed_hwfn *p_hwfn, 282 u32 seg) 283 { 284 struct qed_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr; 285 u32 i; 286 287 /* Find the protocol with tid count > 0 for this segment. 288 * Note: there can only be one and this is already validated. 289 */ 290 for (i = 0; i < MAX_CONN_TYPES; i++) 291 if (p_cfg->conn_cfg[i].tid_seg[seg].count) 292 return &p_cfg->conn_cfg[i].tid_seg[seg]; 293 return NULL; 294 } 295 296 static void qed_cxt_set_srq_count(struct qed_hwfn *p_hwfn, u32 num_srqs) 297 { 298 struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; 299 300 p_mgr->srq_count = num_srqs; 301 } 302 303 u32 qed_cxt_get_srq_count(struct qed_hwfn *p_hwfn) 304 { 305 struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; 306 307 return p_mgr->srq_count; 308 } 309 310 /* set the iids count per protocol */ 311 static void qed_cxt_set_proto_cid_count(struct qed_hwfn *p_hwfn, 312 enum protocol_type type, 313 u32 cid_count, u32 vf_cid_cnt) 314 { 315 struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; 316 struct qed_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type]; 317 318 p_conn->cid_count = roundup(cid_count, DQ_RANGE_ALIGN); 319 p_conn->cids_per_vf = roundup(vf_cid_cnt, DQ_RANGE_ALIGN); 320 321 if (type == PROTOCOLID_ROCE) { 322 u32 page_sz = p_mgr->clients[ILT_CLI_CDUC].p_size.val; 323 u32 cxt_size = CONN_CXT_SIZE(p_hwfn); 324 u32 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 325 u32 align = elems_per_page * DQ_RANGE_ALIGN; 326 327 p_conn->cid_count = roundup(p_conn->cid_count, align); 328 } 329 } 330 331 u32 qed_cxt_get_proto_cid_count(struct qed_hwfn *p_hwfn, 332 enum protocol_type type, u32 *vf_cid) 333 { 334 if (vf_cid) 335 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf; 336 337 return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count; 338 } 339 340 u32 qed_cxt_get_proto_cid_start(struct qed_hwfn *p_hwfn, 341 enum protocol_type type) 342 { 343 return p_hwfn->p_cxt_mngr->acquired[type].start_cid; 344 } 345 346 u32 qed_cxt_get_proto_tid_count(struct qed_hwfn *p_hwfn, 347 enum protocol_type type) 348 { 349 u32 cnt = 0; 350 int i; 351 352 for (i = 0; i < TASK_SEGMENTS; i++) 353 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count; 354 355 return cnt; 356 } 357 358 static void qed_cxt_set_proto_tid_count(struct qed_hwfn *p_hwfn, 359 enum protocol_type proto, 360 u8 seg, 361 u8 seg_type, u32 count, bool has_fl) 362 { 363 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 364 struct qed_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg]; 365 366 p_seg->count = count; 367 p_seg->has_fl_mem = has_fl; 368 p_seg->type = seg_type; 369 } 370 371 static void qed_ilt_cli_blk_fill(struct qed_ilt_client_cfg *p_cli, 372 struct qed_ilt_cli_blk *p_blk, 373 u32 start_line, u32 total_size, u32 elem_size) 374 { 375 u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val); 376 377 /* verify thatits called only once for each block */ 378 if (p_blk->total_size) 379 return; 380 381 p_blk->total_size = total_size; 382 p_blk->real_size_in_page = 0; 383 if (elem_size) 384 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size; 385 p_blk->start_line = start_line; 386 } 387 388 static void qed_ilt_cli_adv_line(struct qed_hwfn *p_hwfn, 389 struct qed_ilt_client_cfg *p_cli, 390 struct qed_ilt_cli_blk *p_blk, 391 u32 *p_line, enum ilt_clients client_id) 392 { 393 if (!p_blk->total_size) 394 return; 395 396 if (!p_cli->active) 397 p_cli->first.val = *p_line; 398 399 p_cli->active = true; 400 *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page); 401 p_cli->last.val = *p_line - 1; 402 403 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 404 "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x [Real %08x] Start line %d\n", 405 client_id, p_cli->first.val, 406 p_cli->last.val, p_blk->total_size, 407 p_blk->real_size_in_page, p_blk->start_line); 408 } 409 410 static u32 qed_ilt_get_dynamic_line_cnt(struct qed_hwfn *p_hwfn, 411 enum ilt_clients ilt_client) 412 { 413 u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count; 414 struct qed_ilt_client_cfg *p_cli; 415 u32 lines_to_skip = 0; 416 u32 cxts_per_p; 417 418 if (ilt_client == ILT_CLI_CDUC) { 419 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 420 421 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) / 422 (u32) CONN_CXT_SIZE(p_hwfn); 423 424 lines_to_skip = cid_count / cxts_per_p; 425 } 426 427 return lines_to_skip; 428 } 429 430 static struct qed_ilt_client_cfg *qed_cxt_set_cli(struct qed_ilt_client_cfg 431 *p_cli) 432 { 433 p_cli->active = false; 434 p_cli->first.val = 0; 435 p_cli->last.val = 0; 436 return p_cli; 437 } 438 439 static struct qed_ilt_cli_blk *qed_cxt_set_blk(struct qed_ilt_cli_blk *p_blk) 440 { 441 p_blk->total_size = 0; 442 return p_blk; 443 } 444 445 int qed_cxt_cfg_ilt_compute(struct qed_hwfn *p_hwfn, u32 *line_count) 446 { 447 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 448 u32 curr_line, total, i, task_size, line; 449 struct qed_ilt_client_cfg *p_cli; 450 struct qed_ilt_cli_blk *p_blk; 451 struct qed_cdu_iids cdu_iids; 452 struct qed_src_iids src_iids; 453 struct qed_qm_iids qm_iids; 454 struct qed_tm_iids tm_iids; 455 struct qed_tid_seg *p_seg; 456 457 memset(&qm_iids, 0, sizeof(qm_iids)); 458 memset(&cdu_iids, 0, sizeof(cdu_iids)); 459 memset(&src_iids, 0, sizeof(src_iids)); 460 memset(&tm_iids, 0, sizeof(tm_iids)); 461 462 p_mngr->pf_start_line = RESC_START(p_hwfn, QED_ILT); 463 464 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 465 "hwfn [%d] - Set context manager starting line to be 0x%08x\n", 466 p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line); 467 468 /* CDUC */ 469 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_CDUC]); 470 471 curr_line = p_mngr->pf_start_line; 472 473 /* CDUC PF */ 474 p_cli->pf_total_lines = 0; 475 476 /* get the counters for the CDUC and QM clients */ 477 qed_cxt_cdu_iids(p_mngr, &cdu_iids); 478 479 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[CDUC_BLK]); 480 481 total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn); 482 483 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 484 total, CONN_CXT_SIZE(p_hwfn)); 485 486 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC); 487 p_cli->pf_total_lines = curr_line - p_blk->start_line; 488 489 p_blk->dynamic_line_cnt = qed_ilt_get_dynamic_line_cnt(p_hwfn, 490 ILT_CLI_CDUC); 491 492 /* CDUC VF */ 493 p_blk = qed_cxt_set_blk(&p_cli->vf_blks[CDUC_BLK]); 494 total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn); 495 496 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 497 total, CONN_CXT_SIZE(p_hwfn)); 498 499 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC); 500 p_cli->vf_total_lines = curr_line - p_blk->start_line; 501 502 for (i = 1; i < p_mngr->vf_count; i++) 503 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 504 ILT_CLI_CDUC); 505 506 /* CDUT PF */ 507 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_CDUT]); 508 p_cli->first.val = curr_line; 509 510 /* first the 'working' task memory */ 511 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 512 p_seg = qed_cxt_tid_seg_info(p_hwfn, i); 513 if (!p_seg || p_seg->count == 0) 514 continue; 515 516 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[CDUT_SEG_BLK(i)]); 517 total = p_seg->count * p_mngr->task_type_size[p_seg->type]; 518 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total, 519 p_mngr->task_type_size[p_seg->type]); 520 521 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 522 ILT_CLI_CDUT); 523 } 524 525 /* next the 'init' task memory (forced load memory) */ 526 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 527 p_seg = qed_cxt_tid_seg_info(p_hwfn, i); 528 if (!p_seg || p_seg->count == 0) 529 continue; 530 531 p_blk = 532 qed_cxt_set_blk(&p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)]); 533 534 if (!p_seg->has_fl_mem) { 535 /* The segment is active (total size pf 'working' 536 * memory is > 0) but has no FL (forced-load, Init) 537 * memory. Thus: 538 * 539 * 1. The total-size in the corrsponding FL block of 540 * the ILT client is set to 0 - No ILT line are 541 * provisioned and no ILT memory allocated. 542 * 543 * 2. The start-line of said block is set to the 544 * start line of the matching working memory 545 * block in the ILT client. This is later used to 546 * configure the CDU segment offset registers and 547 * results in an FL command for TIDs of this 548 * segement behaves as regular load commands 549 * (loading TIDs from the working memory). 550 */ 551 line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line; 552 553 qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0); 554 continue; 555 } 556 total = p_seg->count * p_mngr->task_type_size[p_seg->type]; 557 558 qed_ilt_cli_blk_fill(p_cli, p_blk, 559 curr_line, total, 560 p_mngr->task_type_size[p_seg->type]); 561 562 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 563 ILT_CLI_CDUT); 564 } 565 p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line; 566 567 /* CDUT VF */ 568 p_seg = qed_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF); 569 if (p_seg && p_seg->count) { 570 /* Stricly speaking we need to iterate over all VF 571 * task segment types, but a VF has only 1 segment 572 */ 573 574 /* 'working' memory */ 575 total = p_seg->count * p_mngr->task_type_size[p_seg->type]; 576 577 p_blk = qed_cxt_set_blk(&p_cli->vf_blks[CDUT_SEG_BLK(0)]); 578 qed_ilt_cli_blk_fill(p_cli, p_blk, 579 curr_line, total, 580 p_mngr->task_type_size[p_seg->type]); 581 582 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 583 ILT_CLI_CDUT); 584 585 /* 'init' memory */ 586 p_blk = 587 qed_cxt_set_blk(&p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)]); 588 if (!p_seg->has_fl_mem) { 589 /* see comment above */ 590 line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line; 591 qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0); 592 } else { 593 task_size = p_mngr->task_type_size[p_seg->type]; 594 qed_ilt_cli_blk_fill(p_cli, p_blk, 595 curr_line, total, task_size); 596 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 597 ILT_CLI_CDUT); 598 } 599 p_cli->vf_total_lines = curr_line - 600 p_cli->vf_blks[0].start_line; 601 602 /* Now for the rest of the VFs */ 603 for (i = 1; i < p_mngr->vf_count; i++) { 604 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)]; 605 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 606 ILT_CLI_CDUT); 607 608 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)]; 609 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 610 ILT_CLI_CDUT); 611 } 612 } 613 614 /* QM */ 615 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_QM]); 616 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[0]); 617 618 qed_cxt_qm_iids(p_hwfn, &qm_iids); 619 total = qed_qm_pf_mem_size(qm_iids.cids, 620 qm_iids.vf_cids, qm_iids.tids, 621 p_hwfn->qm_info.num_pqs, 622 p_hwfn->qm_info.num_vf_pqs); 623 624 DP_VERBOSE(p_hwfn, 625 QED_MSG_ILT, 626 "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d, num_vf_pqs=%d, memory_size=%d)\n", 627 qm_iids.cids, 628 qm_iids.vf_cids, 629 qm_iids.tids, 630 p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total); 631 632 qed_ilt_cli_blk_fill(p_cli, p_blk, 633 curr_line, total * 0x1000, 634 QM_PQ_ELEMENT_SIZE); 635 636 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM); 637 p_cli->pf_total_lines = curr_line - p_blk->start_line; 638 639 /* SRC */ 640 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_SRC]); 641 qed_cxt_src_iids(p_mngr, &src_iids); 642 643 /* Both the PF and VFs searcher connections are stored in the per PF 644 * database. Thus sum the PF searcher cids and all the VFs searcher 645 * cids. 646 */ 647 total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count; 648 if (total) { 649 u32 local_max = max_t(u32, total, 650 SRC_MIN_NUM_ELEMS); 651 652 total = roundup_pow_of_two(local_max); 653 654 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[0]); 655 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 656 total * sizeof(struct src_ent), 657 sizeof(struct src_ent)); 658 659 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 660 ILT_CLI_SRC); 661 p_cli->pf_total_lines = curr_line - p_blk->start_line; 662 } 663 664 /* TM PF */ 665 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_TM]); 666 qed_cxt_tm_iids(p_hwfn, p_mngr, &tm_iids); 667 total = tm_iids.pf_cids + tm_iids.pf_tids_total; 668 if (total) { 669 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[0]); 670 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 671 total * TM_ELEM_SIZE, TM_ELEM_SIZE); 672 673 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 674 ILT_CLI_TM); 675 p_cli->pf_total_lines = curr_line - p_blk->start_line; 676 } 677 678 /* TM VF */ 679 total = tm_iids.per_vf_cids + tm_iids.per_vf_tids; 680 if (total) { 681 p_blk = qed_cxt_set_blk(&p_cli->vf_blks[0]); 682 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 683 total * TM_ELEM_SIZE, TM_ELEM_SIZE); 684 685 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 686 ILT_CLI_TM); 687 688 p_cli->vf_total_lines = curr_line - p_blk->start_line; 689 for (i = 1; i < p_mngr->vf_count; i++) 690 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 691 ILT_CLI_TM); 692 } 693 694 /* TSDM (SRQ CONTEXT) */ 695 total = qed_cxt_get_srq_count(p_hwfn); 696 697 if (total) { 698 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_TSDM]); 699 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[SRQ_BLK]); 700 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 701 total * SRQ_CXT_SIZE, SRQ_CXT_SIZE); 702 703 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 704 ILT_CLI_TSDM); 705 p_cli->pf_total_lines = curr_line - p_blk->start_line; 706 } 707 708 *line_count = curr_line - p_hwfn->p_cxt_mngr->pf_start_line; 709 710 if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line > 711 RESC_NUM(p_hwfn, QED_ILT)) 712 return -EINVAL; 713 714 return 0; 715 } 716 717 u32 qed_cxt_cfg_ilt_compute_excess(struct qed_hwfn *p_hwfn, u32 used_lines) 718 { 719 struct qed_ilt_client_cfg *p_cli; 720 u32 excess_lines, available_lines; 721 struct qed_cxt_mngr *p_mngr; 722 u32 ilt_page_size, elem_size; 723 struct qed_tid_seg *p_seg; 724 int i; 725 726 available_lines = RESC_NUM(p_hwfn, QED_ILT); 727 excess_lines = used_lines - available_lines; 728 729 if (!excess_lines) 730 return 0; 731 732 if (!QED_IS_RDMA_PERSONALITY(p_hwfn)) 733 return 0; 734 735 p_mngr = p_hwfn->p_cxt_mngr; 736 p_cli = &p_mngr->clients[ILT_CLI_CDUT]; 737 ilt_page_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val); 738 739 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 740 p_seg = qed_cxt_tid_seg_info(p_hwfn, i); 741 if (!p_seg || p_seg->count == 0) 742 continue; 743 744 elem_size = p_mngr->task_type_size[p_seg->type]; 745 if (!elem_size) 746 continue; 747 748 return (ilt_page_size / elem_size) * excess_lines; 749 } 750 751 DP_NOTICE(p_hwfn, "failed computing excess ILT lines\n"); 752 return 0; 753 } 754 755 static void qed_cxt_src_t2_free(struct qed_hwfn *p_hwfn) 756 { 757 struct qed_src_t2 *p_t2 = &p_hwfn->p_cxt_mngr->src_t2; 758 u32 i; 759 760 if (!p_t2 || !p_t2->dma_mem) 761 return; 762 763 for (i = 0; i < p_t2->num_pages; i++) 764 if (p_t2->dma_mem[i].virt_addr) 765 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 766 p_t2->dma_mem[i].size, 767 p_t2->dma_mem[i].virt_addr, 768 p_t2->dma_mem[i].phys_addr); 769 770 kfree(p_t2->dma_mem); 771 p_t2->dma_mem = NULL; 772 } 773 774 static int 775 qed_cxt_t2_alloc_pages(struct qed_hwfn *p_hwfn, 776 struct qed_src_t2 *p_t2, u32 total_size, u32 page_size) 777 { 778 void **p_virt; 779 u32 size, i; 780 781 if (!p_t2 || !p_t2->dma_mem) 782 return -EINVAL; 783 784 for (i = 0; i < p_t2->num_pages; i++) { 785 size = min_t(u32, total_size, page_size); 786 p_virt = &p_t2->dma_mem[i].virt_addr; 787 788 *p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 789 size, 790 &p_t2->dma_mem[i].phys_addr, 791 GFP_KERNEL); 792 if (!p_t2->dma_mem[i].virt_addr) 793 return -ENOMEM; 794 795 memset(*p_virt, 0, size); 796 p_t2->dma_mem[i].size = size; 797 total_size -= size; 798 } 799 800 return 0; 801 } 802 803 static int qed_cxt_src_t2_alloc(struct qed_hwfn *p_hwfn) 804 { 805 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 806 u32 conn_num, total_size, ent_per_page, psz, i; 807 struct phys_mem_desc *p_t2_last_page; 808 struct qed_ilt_client_cfg *p_src; 809 struct qed_src_iids src_iids; 810 struct qed_src_t2 *p_t2; 811 int rc; 812 813 memset(&src_iids, 0, sizeof(src_iids)); 814 815 /* if the SRC ILT client is inactive - there are no connection 816 * requiring the searcer, leave. 817 */ 818 p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC]; 819 if (!p_src->active) 820 return 0; 821 822 qed_cxt_src_iids(p_mngr, &src_iids); 823 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count; 824 total_size = conn_num * sizeof(struct src_ent); 825 826 /* use the same page size as the SRC ILT client */ 827 psz = ILT_PAGE_IN_BYTES(p_src->p_size.val); 828 p_t2 = &p_mngr->src_t2; 829 p_t2->num_pages = DIV_ROUND_UP(total_size, psz); 830 831 /* allocate t2 */ 832 p_t2->dma_mem = kcalloc(p_t2->num_pages, sizeof(struct phys_mem_desc), 833 GFP_KERNEL); 834 if (!p_t2->dma_mem) { 835 DP_NOTICE(p_hwfn, "Failed to allocate t2 table\n"); 836 rc = -ENOMEM; 837 goto t2_fail; 838 } 839 840 rc = qed_cxt_t2_alloc_pages(p_hwfn, p_t2, total_size, psz); 841 if (rc) 842 goto t2_fail; 843 844 /* Set the t2 pointers */ 845 846 /* entries per page - must be a power of two */ 847 ent_per_page = psz / sizeof(struct src_ent); 848 849 p_t2->first_free = (u64)p_t2->dma_mem[0].phys_addr; 850 851 p_t2_last_page = &p_t2->dma_mem[(conn_num - 1) / ent_per_page]; 852 p_t2->last_free = (u64)p_t2_last_page->phys_addr + 853 ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent); 854 855 for (i = 0; i < p_t2->num_pages; i++) { 856 u32 ent_num = min_t(u32, 857 ent_per_page, 858 conn_num); 859 struct src_ent *entries = p_t2->dma_mem[i].virt_addr; 860 u64 p_ent_phys = (u64)p_t2->dma_mem[i].phys_addr, val; 861 u32 j; 862 863 for (j = 0; j < ent_num - 1; j++) { 864 val = p_ent_phys + (j + 1) * sizeof(struct src_ent); 865 entries[j].next = cpu_to_be64(val); 866 } 867 868 if (i < p_t2->num_pages - 1) 869 val = (u64)p_t2->dma_mem[i + 1].phys_addr; 870 else 871 val = 0; 872 entries[j].next = cpu_to_be64(val); 873 874 conn_num -= ent_num; 875 } 876 877 return 0; 878 879 t2_fail: 880 qed_cxt_src_t2_free(p_hwfn); 881 return rc; 882 } 883 884 #define for_each_ilt_valid_client(pos, clients) \ 885 for (pos = 0; pos < MAX_ILT_CLIENTS; pos++) \ 886 if (!clients[pos].active) { \ 887 continue; \ 888 } else \ 889 890 /* Total number of ILT lines used by this PF */ 891 static u32 qed_cxt_ilt_shadow_size(struct qed_ilt_client_cfg *ilt_clients) 892 { 893 u32 size = 0; 894 u32 i; 895 896 for_each_ilt_valid_client(i, ilt_clients) 897 size += (ilt_clients[i].last.val - ilt_clients[i].first.val + 1); 898 899 return size; 900 } 901 902 static void qed_ilt_shadow_free(struct qed_hwfn *p_hwfn) 903 { 904 struct qed_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients; 905 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 906 u32 ilt_size, i; 907 908 ilt_size = qed_cxt_ilt_shadow_size(p_cli); 909 910 for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) { 911 struct phys_mem_desc *p_dma = &p_mngr->ilt_shadow[i]; 912 913 if (p_dma->virt_addr) 914 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 915 p_dma->size, p_dma->virt_addr, 916 p_dma->phys_addr); 917 p_dma->virt_addr = NULL; 918 } 919 kfree(p_mngr->ilt_shadow); 920 } 921 922 static int qed_ilt_blk_alloc(struct qed_hwfn *p_hwfn, 923 struct qed_ilt_cli_blk *p_blk, 924 enum ilt_clients ilt_client, 925 u32 start_line_offset) 926 { 927 struct phys_mem_desc *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow; 928 u32 lines, line, sz_left, lines_to_skip = 0; 929 930 /* Special handling for RoCE that supports dynamic allocation */ 931 if (QED_IS_RDMA_PERSONALITY(p_hwfn) && 932 ((ilt_client == ILT_CLI_CDUT) || ilt_client == ILT_CLI_TSDM)) 933 return 0; 934 935 lines_to_skip = p_blk->dynamic_line_cnt; 936 937 if (!p_blk->total_size) 938 return 0; 939 940 sz_left = p_blk->total_size; 941 lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip; 942 line = p_blk->start_line + start_line_offset - 943 p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip; 944 945 for (; lines; lines--) { 946 dma_addr_t p_phys; 947 void *p_virt; 948 u32 size; 949 950 size = min_t(u32, sz_left, p_blk->real_size_in_page); 951 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, size, 952 &p_phys, GFP_KERNEL); 953 if (!p_virt) 954 return -ENOMEM; 955 956 ilt_shadow[line].phys_addr = p_phys; 957 ilt_shadow[line].virt_addr = p_virt; 958 ilt_shadow[line].size = size; 959 960 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 961 "ILT shadow: Line [%d] Physical 0x%llx Virtual %p Size %d\n", 962 line, (u64)p_phys, p_virt, size); 963 964 sz_left -= size; 965 line++; 966 } 967 968 return 0; 969 } 970 971 static int qed_ilt_shadow_alloc(struct qed_hwfn *p_hwfn) 972 { 973 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 974 struct qed_ilt_client_cfg *clients = p_mngr->clients; 975 struct qed_ilt_cli_blk *p_blk; 976 u32 size, i, j, k; 977 int rc; 978 979 size = qed_cxt_ilt_shadow_size(clients); 980 p_mngr->ilt_shadow = kcalloc(size, sizeof(struct phys_mem_desc), 981 GFP_KERNEL); 982 if (!p_mngr->ilt_shadow) { 983 rc = -ENOMEM; 984 goto ilt_shadow_fail; 985 } 986 987 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 988 "Allocated 0x%x bytes for ilt shadow\n", 989 (u32)(size * sizeof(struct phys_mem_desc))); 990 991 for_each_ilt_valid_client(i, clients) { 992 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) { 993 p_blk = &clients[i].pf_blks[j]; 994 rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, 0); 995 if (rc) 996 goto ilt_shadow_fail; 997 } 998 for (k = 0; k < p_mngr->vf_count; k++) { 999 for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) { 1000 u32 lines = clients[i].vf_total_lines * k; 1001 1002 p_blk = &clients[i].vf_blks[j]; 1003 rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, lines); 1004 if (rc) 1005 goto ilt_shadow_fail; 1006 } 1007 } 1008 } 1009 1010 return 0; 1011 1012 ilt_shadow_fail: 1013 qed_ilt_shadow_free(p_hwfn); 1014 return rc; 1015 } 1016 1017 static void qed_cid_map_free(struct qed_hwfn *p_hwfn) 1018 { 1019 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1020 u32 type, vf; 1021 1022 for (type = 0; type < MAX_CONN_TYPES; type++) { 1023 kfree(p_mngr->acquired[type].cid_map); 1024 p_mngr->acquired[type].max_count = 0; 1025 p_mngr->acquired[type].start_cid = 0; 1026 1027 for (vf = 0; vf < MAX_NUM_VFS; vf++) { 1028 kfree(p_mngr->acquired_vf[type][vf].cid_map); 1029 p_mngr->acquired_vf[type][vf].max_count = 0; 1030 p_mngr->acquired_vf[type][vf].start_cid = 0; 1031 } 1032 } 1033 } 1034 1035 static int 1036 qed_cid_map_alloc_single(struct qed_hwfn *p_hwfn, 1037 u32 type, 1038 u32 cid_start, 1039 u32 cid_count, struct qed_cid_acquired_map *p_map) 1040 { 1041 u32 size; 1042 1043 if (!cid_count) 1044 return 0; 1045 1046 size = DIV_ROUND_UP(cid_count, 1047 sizeof(unsigned long) * BITS_PER_BYTE) * 1048 sizeof(unsigned long); 1049 p_map->cid_map = kzalloc(size, GFP_KERNEL); 1050 if (!p_map->cid_map) 1051 return -ENOMEM; 1052 1053 p_map->max_count = cid_count; 1054 p_map->start_cid = cid_start; 1055 1056 DP_VERBOSE(p_hwfn, QED_MSG_CXT, 1057 "Type %08x start: %08x count %08x\n", 1058 type, p_map->start_cid, p_map->max_count); 1059 1060 return 0; 1061 } 1062 1063 static int qed_cid_map_alloc(struct qed_hwfn *p_hwfn) 1064 { 1065 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1066 u32 start_cid = 0, vf_start_cid = 0; 1067 u32 type, vf; 1068 1069 for (type = 0; type < MAX_CONN_TYPES; type++) { 1070 struct qed_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[type]; 1071 struct qed_cid_acquired_map *p_map; 1072 1073 /* Handle PF maps */ 1074 p_map = &p_mngr->acquired[type]; 1075 if (qed_cid_map_alloc_single(p_hwfn, type, start_cid, 1076 p_cfg->cid_count, p_map)) 1077 goto cid_map_fail; 1078 1079 /* Handle VF maps */ 1080 for (vf = 0; vf < MAX_NUM_VFS; vf++) { 1081 p_map = &p_mngr->acquired_vf[type][vf]; 1082 if (qed_cid_map_alloc_single(p_hwfn, type, 1083 vf_start_cid, 1084 p_cfg->cids_per_vf, p_map)) 1085 goto cid_map_fail; 1086 } 1087 1088 start_cid += p_cfg->cid_count; 1089 vf_start_cid += p_cfg->cids_per_vf; 1090 } 1091 1092 return 0; 1093 1094 cid_map_fail: 1095 qed_cid_map_free(p_hwfn); 1096 return -ENOMEM; 1097 } 1098 1099 int qed_cxt_mngr_alloc(struct qed_hwfn *p_hwfn) 1100 { 1101 struct qed_ilt_client_cfg *clients; 1102 struct qed_cxt_mngr *p_mngr; 1103 u32 i; 1104 1105 p_mngr = kzalloc(sizeof(*p_mngr), GFP_KERNEL); 1106 if (!p_mngr) 1107 return -ENOMEM; 1108 1109 /* Initialize ILT client registers */ 1110 clients = p_mngr->clients; 1111 clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT); 1112 clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT); 1113 clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE); 1114 1115 clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT); 1116 clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT); 1117 clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE); 1118 1119 clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT); 1120 clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT); 1121 clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE); 1122 1123 clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT); 1124 clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT); 1125 clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE); 1126 1127 clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT); 1128 clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT); 1129 clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE); 1130 1131 clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT); 1132 clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT); 1133 clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE); 1134 /* default ILT page size for all clients is 64K */ 1135 for (i = 0; i < MAX_ILT_CLIENTS; i++) 1136 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE; 1137 1138 p_mngr->conn_ctx_size = CONN_CXT_SIZE(p_hwfn); 1139 1140 /* Initialize task sizes */ 1141 p_mngr->task_type_size[0] = TYPE0_TASK_CXT_SIZE(p_hwfn); 1142 p_mngr->task_type_size[1] = TYPE1_TASK_CXT_SIZE(p_hwfn); 1143 1144 if (p_hwfn->cdev->p_iov_info) { 1145 p_mngr->vf_count = p_hwfn->cdev->p_iov_info->total_vfs; 1146 p_mngr->first_vf_in_pf = 1147 p_hwfn->cdev->p_iov_info->first_vf_in_pf; 1148 } 1149 /* Initialize the dynamic ILT allocation mutex */ 1150 mutex_init(&p_mngr->mutex); 1151 1152 /* Set the cxt mangr pointer priori to further allocations */ 1153 p_hwfn->p_cxt_mngr = p_mngr; 1154 1155 return 0; 1156 } 1157 1158 int qed_cxt_tables_alloc(struct qed_hwfn *p_hwfn) 1159 { 1160 int rc; 1161 1162 /* Allocate the ILT shadow table */ 1163 rc = qed_ilt_shadow_alloc(p_hwfn); 1164 if (rc) 1165 goto tables_alloc_fail; 1166 1167 /* Allocate the T2 table */ 1168 rc = qed_cxt_src_t2_alloc(p_hwfn); 1169 if (rc) 1170 goto tables_alloc_fail; 1171 1172 /* Allocate and initialize the acquired cids bitmaps */ 1173 rc = qed_cid_map_alloc(p_hwfn); 1174 if (rc) 1175 goto tables_alloc_fail; 1176 1177 return 0; 1178 1179 tables_alloc_fail: 1180 qed_cxt_mngr_free(p_hwfn); 1181 return rc; 1182 } 1183 1184 void qed_cxt_mngr_free(struct qed_hwfn *p_hwfn) 1185 { 1186 if (!p_hwfn->p_cxt_mngr) 1187 return; 1188 1189 qed_cid_map_free(p_hwfn); 1190 qed_cxt_src_t2_free(p_hwfn); 1191 qed_ilt_shadow_free(p_hwfn); 1192 kfree(p_hwfn->p_cxt_mngr); 1193 1194 p_hwfn->p_cxt_mngr = NULL; 1195 } 1196 1197 void qed_cxt_mngr_setup(struct qed_hwfn *p_hwfn) 1198 { 1199 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1200 struct qed_cid_acquired_map *p_map; 1201 struct qed_conn_type_cfg *p_cfg; 1202 int type; 1203 u32 len; 1204 1205 /* Reset acquired cids */ 1206 for (type = 0; type < MAX_CONN_TYPES; type++) { 1207 u32 vf; 1208 1209 p_cfg = &p_mngr->conn_cfg[type]; 1210 if (p_cfg->cid_count) { 1211 p_map = &p_mngr->acquired[type]; 1212 len = DIV_ROUND_UP(p_map->max_count, 1213 sizeof(unsigned long) * 1214 BITS_PER_BYTE) * 1215 sizeof(unsigned long); 1216 memset(p_map->cid_map, 0, len); 1217 } 1218 1219 if (!p_cfg->cids_per_vf) 1220 continue; 1221 1222 for (vf = 0; vf < MAX_NUM_VFS; vf++) { 1223 p_map = &p_mngr->acquired_vf[type][vf]; 1224 len = DIV_ROUND_UP(p_map->max_count, 1225 sizeof(unsigned long) * 1226 BITS_PER_BYTE) * 1227 sizeof(unsigned long); 1228 memset(p_map->cid_map, 0, len); 1229 } 1230 } 1231 } 1232 1233 /* CDU Common */ 1234 #define CDUC_CXT_SIZE_SHIFT \ 1235 CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT 1236 1237 #define CDUC_CXT_SIZE_MASK \ 1238 (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT) 1239 1240 #define CDUC_BLOCK_WASTE_SHIFT \ 1241 CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT 1242 1243 #define CDUC_BLOCK_WASTE_MASK \ 1244 (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT) 1245 1246 #define CDUC_NCIB_SHIFT \ 1247 CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT 1248 1249 #define CDUC_NCIB_MASK \ 1250 (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT) 1251 1252 #define CDUT_TYPE0_CXT_SIZE_SHIFT \ 1253 CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT 1254 1255 #define CDUT_TYPE0_CXT_SIZE_MASK \ 1256 (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >> \ 1257 CDUT_TYPE0_CXT_SIZE_SHIFT) 1258 1259 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT \ 1260 CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT 1261 1262 #define CDUT_TYPE0_BLOCK_WASTE_MASK \ 1263 (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >> \ 1264 CDUT_TYPE0_BLOCK_WASTE_SHIFT) 1265 1266 #define CDUT_TYPE0_NCIB_SHIFT \ 1267 CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT 1268 1269 #define CDUT_TYPE0_NCIB_MASK \ 1270 (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >> \ 1271 CDUT_TYPE0_NCIB_SHIFT) 1272 1273 #define CDUT_TYPE1_CXT_SIZE_SHIFT \ 1274 CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT 1275 1276 #define CDUT_TYPE1_CXT_SIZE_MASK \ 1277 (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >> \ 1278 CDUT_TYPE1_CXT_SIZE_SHIFT) 1279 1280 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT \ 1281 CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT 1282 1283 #define CDUT_TYPE1_BLOCK_WASTE_MASK \ 1284 (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >> \ 1285 CDUT_TYPE1_BLOCK_WASTE_SHIFT) 1286 1287 #define CDUT_TYPE1_NCIB_SHIFT \ 1288 CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT 1289 1290 #define CDUT_TYPE1_NCIB_MASK \ 1291 (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >> \ 1292 CDUT_TYPE1_NCIB_SHIFT) 1293 1294 static void qed_cdu_init_common(struct qed_hwfn *p_hwfn) 1295 { 1296 u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0; 1297 1298 /* CDUC - connection configuration */ 1299 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val; 1300 cxt_size = CONN_CXT_SIZE(p_hwfn); 1301 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 1302 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size; 1303 1304 SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size); 1305 SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste); 1306 SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page); 1307 STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params); 1308 1309 /* CDUT - type-0 tasks configuration */ 1310 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val; 1311 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0]; 1312 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 1313 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size; 1314 1315 /* cxt size and block-waste are multipes of 8 */ 1316 cdu_params = 0; 1317 SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3)); 1318 SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3)); 1319 SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page); 1320 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params); 1321 1322 /* CDUT - type-1 tasks configuration */ 1323 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1]; 1324 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 1325 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size; 1326 1327 /* cxt size and block-waste are multipes of 8 */ 1328 cdu_params = 0; 1329 SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3)); 1330 SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3)); 1331 SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page); 1332 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params); 1333 } 1334 1335 /* CDU PF */ 1336 #define CDU_SEG_REG_TYPE_SHIFT CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT 1337 #define CDU_SEG_REG_TYPE_MASK 0x1 1338 #define CDU_SEG_REG_OFFSET_SHIFT 0 1339 #define CDU_SEG_REG_OFFSET_MASK CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK 1340 1341 static void qed_cdu_init_pf(struct qed_hwfn *p_hwfn) 1342 { 1343 struct qed_ilt_client_cfg *p_cli; 1344 struct qed_tid_seg *p_seg; 1345 u32 cdu_seg_params, offset; 1346 int i; 1347 1348 static const u32 rt_type_offset_arr[] = { 1349 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET, 1350 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET, 1351 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET, 1352 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 1353 }; 1354 1355 static const u32 rt_type_offset_fl_arr[] = { 1356 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET, 1357 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET, 1358 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET, 1359 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 1360 }; 1361 1362 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 1363 1364 /* There are initializations only for CDUT during pf Phase */ 1365 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 1366 /* Segment 0 */ 1367 p_seg = qed_cxt_tid_seg_info(p_hwfn, i); 1368 if (!p_seg) 1369 continue; 1370 1371 /* Note: start_line is already adjusted for the CDU 1372 * segment register granularity, so we just need to 1373 * divide. Adjustment is implicit as we assume ILT 1374 * Page size is larger than 32K! 1375 */ 1376 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) * 1377 (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line - 1378 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES; 1379 1380 cdu_seg_params = 0; 1381 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type); 1382 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset); 1383 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params); 1384 1385 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) * 1386 (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line - 1387 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES; 1388 1389 cdu_seg_params = 0; 1390 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type); 1391 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset); 1392 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params); 1393 } 1394 } 1395 1396 void qed_qm_init_pf(struct qed_hwfn *p_hwfn, 1397 struct qed_ptt *p_ptt, bool is_pf_loading) 1398 { 1399 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1400 struct qed_qm_pf_rt_init_params params; 1401 struct qed_qm_iids iids; 1402 1403 memset(&iids, 0, sizeof(iids)); 1404 qed_cxt_qm_iids(p_hwfn, &iids); 1405 1406 memset(¶ms, 0, sizeof(params)); 1407 params.port_id = p_hwfn->port_id; 1408 params.pf_id = p_hwfn->rel_pf_id; 1409 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port; 1410 params.is_pf_loading = is_pf_loading; 1411 params.num_pf_cids = iids.cids; 1412 params.num_vf_cids = iids.vf_cids; 1413 params.num_tids = iids.tids; 1414 params.start_pq = qm_info->start_pq; 1415 params.num_pf_pqs = qm_info->num_pqs - qm_info->num_vf_pqs; 1416 params.num_vf_pqs = qm_info->num_vf_pqs; 1417 params.start_vport = qm_info->start_vport; 1418 params.num_vports = qm_info->num_vports; 1419 params.pf_wfq = qm_info->pf_wfq; 1420 params.pf_rl = qm_info->pf_rl; 1421 params.pq_params = qm_info->qm_pq_params; 1422 params.vport_params = qm_info->qm_vport_params; 1423 1424 qed_qm_pf_rt_init(p_hwfn, p_ptt, ¶ms); 1425 } 1426 1427 /* CM PF */ 1428 static void qed_cm_init_pf(struct qed_hwfn *p_hwfn) 1429 { 1430 /* XCM pure-LB queue */ 1431 STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET, 1432 qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB)); 1433 } 1434 1435 /* DQ PF */ 1436 static void qed_dq_init_pf(struct qed_hwfn *p_hwfn) 1437 { 1438 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1439 u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0; 1440 1441 dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT); 1442 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid); 1443 1444 dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT); 1445 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid); 1446 1447 dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT); 1448 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid); 1449 1450 dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT); 1451 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid); 1452 1453 dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT); 1454 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid); 1455 1456 dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT); 1457 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid); 1458 1459 dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT); 1460 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid); 1461 1462 dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT); 1463 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid); 1464 1465 dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT); 1466 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid); 1467 1468 dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT); 1469 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid); 1470 1471 dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT); 1472 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid); 1473 1474 dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT); 1475 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid); 1476 1477 /* Connection types 6 & 7 are not in use, yet they must be configured 1478 * as the highest possible connection. Not configuring them means the 1479 * defaults will be used, and with a large number of cids a bug may 1480 * occur, if the defaults will be smaller than dq_pf_max_cid / 1481 * dq_vf_max_cid. 1482 */ 1483 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid); 1484 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid); 1485 1486 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid); 1487 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid); 1488 } 1489 1490 static void qed_ilt_bounds_init(struct qed_hwfn *p_hwfn) 1491 { 1492 struct qed_ilt_client_cfg *ilt_clients; 1493 int i; 1494 1495 ilt_clients = p_hwfn->p_cxt_mngr->clients; 1496 for_each_ilt_valid_client(i, ilt_clients) { 1497 STORE_RT_REG(p_hwfn, 1498 ilt_clients[i].first.reg, 1499 ilt_clients[i].first.val); 1500 STORE_RT_REG(p_hwfn, 1501 ilt_clients[i].last.reg, ilt_clients[i].last.val); 1502 STORE_RT_REG(p_hwfn, 1503 ilt_clients[i].p_size.reg, 1504 ilt_clients[i].p_size.val); 1505 } 1506 } 1507 1508 static void qed_ilt_vf_bounds_init(struct qed_hwfn *p_hwfn) 1509 { 1510 struct qed_ilt_client_cfg *p_cli; 1511 u32 blk_factor; 1512 1513 /* For simplicty we set the 'block' to be an ILT page */ 1514 if (p_hwfn->cdev->p_iov_info) { 1515 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info; 1516 1517 STORE_RT_REG(p_hwfn, 1518 PSWRQ2_REG_VF_BASE_RT_OFFSET, 1519 p_iov->first_vf_in_pf); 1520 STORE_RT_REG(p_hwfn, 1521 PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET, 1522 p_iov->first_vf_in_pf + p_iov->total_vfs); 1523 } 1524 1525 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 1526 blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10); 1527 if (p_cli->active) { 1528 STORE_RT_REG(p_hwfn, 1529 PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET, 1530 blk_factor); 1531 STORE_RT_REG(p_hwfn, 1532 PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET, 1533 p_cli->pf_total_lines); 1534 STORE_RT_REG(p_hwfn, 1535 PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET, 1536 p_cli->vf_total_lines); 1537 } 1538 1539 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 1540 blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10); 1541 if (p_cli->active) { 1542 STORE_RT_REG(p_hwfn, 1543 PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET, 1544 blk_factor); 1545 STORE_RT_REG(p_hwfn, 1546 PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET, 1547 p_cli->pf_total_lines); 1548 STORE_RT_REG(p_hwfn, 1549 PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET, 1550 p_cli->vf_total_lines); 1551 } 1552 1553 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM]; 1554 blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10); 1555 if (p_cli->active) { 1556 STORE_RT_REG(p_hwfn, 1557 PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor); 1558 STORE_RT_REG(p_hwfn, 1559 PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET, 1560 p_cli->pf_total_lines); 1561 STORE_RT_REG(p_hwfn, 1562 PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET, 1563 p_cli->vf_total_lines); 1564 } 1565 } 1566 1567 /* ILT (PSWRQ2) PF */ 1568 static void qed_ilt_init_pf(struct qed_hwfn *p_hwfn) 1569 { 1570 struct qed_ilt_client_cfg *clients; 1571 struct qed_cxt_mngr *p_mngr; 1572 struct phys_mem_desc *p_shdw; 1573 u32 line, rt_offst, i; 1574 1575 qed_ilt_bounds_init(p_hwfn); 1576 qed_ilt_vf_bounds_init(p_hwfn); 1577 1578 p_mngr = p_hwfn->p_cxt_mngr; 1579 p_shdw = p_mngr->ilt_shadow; 1580 clients = p_hwfn->p_cxt_mngr->clients; 1581 1582 for_each_ilt_valid_client(i, clients) { 1583 /** Client's 1st val and RT array are absolute, ILT shadows' 1584 * lines are relative. 1585 */ 1586 line = clients[i].first.val - p_mngr->pf_start_line; 1587 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET + 1588 clients[i].first.val * ILT_ENTRY_IN_REGS; 1589 1590 for (; line <= clients[i].last.val - p_mngr->pf_start_line; 1591 line++, rt_offst += ILT_ENTRY_IN_REGS) { 1592 u64 ilt_hw_entry = 0; 1593 1594 /** p_virt could be NULL incase of dynamic 1595 * allocation 1596 */ 1597 if (p_shdw[line].virt_addr) { 1598 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL); 1599 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR, 1600 (p_shdw[line].phys_addr >> 12)); 1601 1602 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 1603 "Setting RT[0x%08x] from ILT[0x%08x] [Client is %d] to Physical addr: 0x%llx\n", 1604 rt_offst, line, i, 1605 (u64)(p_shdw[line].phys_addr >> 12)); 1606 } 1607 1608 STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry); 1609 } 1610 } 1611 } 1612 1613 /* SRC (Searcher) PF */ 1614 static void qed_src_init_pf(struct qed_hwfn *p_hwfn) 1615 { 1616 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1617 u32 rounded_conn_num, conn_num, conn_max; 1618 struct qed_src_iids src_iids; 1619 1620 memset(&src_iids, 0, sizeof(src_iids)); 1621 qed_cxt_src_iids(p_mngr, &src_iids); 1622 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count; 1623 if (!conn_num) 1624 return; 1625 1626 conn_max = max_t(u32, conn_num, SRC_MIN_NUM_ELEMS); 1627 rounded_conn_num = roundup_pow_of_two(conn_max); 1628 1629 STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num); 1630 STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET, 1631 ilog2(rounded_conn_num)); 1632 1633 STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET, 1634 p_hwfn->p_cxt_mngr->first_free); 1635 STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET, 1636 p_hwfn->p_cxt_mngr->last_free); 1637 } 1638 1639 /* Timers PF */ 1640 #define TM_CFG_NUM_IDS_SHIFT 0 1641 #define TM_CFG_NUM_IDS_MASK 0xFFFFULL 1642 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT 16 1643 #define TM_CFG_PRE_SCAN_OFFSET_MASK 0x1FFULL 1644 #define TM_CFG_PARENT_PF_SHIFT 25 1645 #define TM_CFG_PARENT_PF_MASK 0x7ULL 1646 1647 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT 30 1648 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK 0x1FFULL 1649 1650 #define TM_CFG_TID_OFFSET_SHIFT 30 1651 #define TM_CFG_TID_OFFSET_MASK 0x7FFFFULL 1652 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT 49 1653 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK 0x1FFULL 1654 1655 static void qed_tm_init_pf(struct qed_hwfn *p_hwfn) 1656 { 1657 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1658 u32 active_seg_mask = 0, tm_offset, rt_reg; 1659 struct qed_tm_iids tm_iids; 1660 u64 cfg_word; 1661 u8 i; 1662 1663 memset(&tm_iids, 0, sizeof(tm_iids)); 1664 qed_cxt_tm_iids(p_hwfn, p_mngr, &tm_iids); 1665 1666 /* @@@TBD No pre-scan for now */ 1667 1668 /* Note: We assume consecutive VFs for a PF */ 1669 for (i = 0; i < p_mngr->vf_count; i++) { 1670 cfg_word = 0; 1671 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids); 1672 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1673 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id); 1674 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); 1675 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET + 1676 (sizeof(cfg_word) / sizeof(u32)) * 1677 (p_hwfn->cdev->p_iov_info->first_vf_in_pf + i); 1678 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1679 } 1680 1681 cfg_word = 0; 1682 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids); 1683 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1684 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); /* n/a for PF */ 1685 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */ 1686 1687 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET + 1688 (sizeof(cfg_word) / sizeof(u32)) * 1689 (NUM_OF_VFS(p_hwfn->cdev) + p_hwfn->rel_pf_id); 1690 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1691 1692 /* enale scan */ 1693 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET, 1694 tm_iids.pf_cids ? 0x1 : 0x0); 1695 1696 /* @@@TBD how to enable the scan for the VFs */ 1697 1698 tm_offset = tm_iids.per_vf_cids; 1699 1700 /* Note: We assume consecutive VFs for a PF */ 1701 for (i = 0; i < p_mngr->vf_count; i++) { 1702 cfg_word = 0; 1703 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids); 1704 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1705 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id); 1706 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset); 1707 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0); 1708 1709 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET + 1710 (sizeof(cfg_word) / sizeof(u32)) * 1711 (p_hwfn->cdev->p_iov_info->first_vf_in_pf + i); 1712 1713 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1714 } 1715 1716 tm_offset = tm_iids.pf_cids; 1717 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 1718 cfg_word = 0; 1719 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]); 1720 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1721 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); 1722 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset); 1723 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0); 1724 1725 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET + 1726 (sizeof(cfg_word) / sizeof(u32)) * 1727 (NUM_OF_VFS(p_hwfn->cdev) + 1728 p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i); 1729 1730 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1731 active_seg_mask |= (tm_iids.pf_tids[i] ? BIT(i) : 0); 1732 1733 tm_offset += tm_iids.pf_tids[i]; 1734 } 1735 1736 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) 1737 active_seg_mask = 0; 1738 1739 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask); 1740 1741 /* @@@TBD how to enable the scan for the VFs */ 1742 } 1743 1744 static void qed_prs_init_common(struct qed_hwfn *p_hwfn) 1745 { 1746 if ((p_hwfn->hw_info.personality == QED_PCI_FCOE) && 1747 p_hwfn->pf_params.fcoe_pf_params.is_target) 1748 STORE_RT_REG(p_hwfn, 1749 PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET, 0); 1750 } 1751 1752 static void qed_prs_init_pf(struct qed_hwfn *p_hwfn) 1753 { 1754 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1755 struct qed_conn_type_cfg *p_fcoe; 1756 struct qed_tid_seg *p_tid; 1757 1758 p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE]; 1759 1760 /* If FCoE is active set the MAX OX_ID (tid) in the Parser */ 1761 if (!p_fcoe->cid_count) 1762 return; 1763 1764 p_tid = &p_fcoe->tid_seg[QED_CXT_FCOE_TID_SEG]; 1765 if (p_hwfn->pf_params.fcoe_pf_params.is_target) { 1766 STORE_RT_REG_AGG(p_hwfn, 1767 PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET, 1768 p_tid->count); 1769 } else { 1770 STORE_RT_REG_AGG(p_hwfn, 1771 PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET, 1772 p_tid->count); 1773 } 1774 } 1775 1776 void qed_cxt_hw_init_common(struct qed_hwfn *p_hwfn) 1777 { 1778 qed_cdu_init_common(p_hwfn); 1779 qed_prs_init_common(p_hwfn); 1780 } 1781 1782 void qed_cxt_hw_init_pf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1783 { 1784 qed_qm_init_pf(p_hwfn, p_ptt, true); 1785 qed_cm_init_pf(p_hwfn); 1786 qed_dq_init_pf(p_hwfn); 1787 qed_cdu_init_pf(p_hwfn); 1788 qed_ilt_init_pf(p_hwfn); 1789 qed_src_init_pf(p_hwfn); 1790 qed_tm_init_pf(p_hwfn); 1791 qed_prs_init_pf(p_hwfn); 1792 } 1793 1794 int _qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn, 1795 enum protocol_type type, u32 *p_cid, u8 vfid) 1796 { 1797 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1798 struct qed_cid_acquired_map *p_map; 1799 u32 rel_cid; 1800 1801 if (type >= MAX_CONN_TYPES) { 1802 DP_NOTICE(p_hwfn, "Invalid protocol type %d", type); 1803 return -EINVAL; 1804 } 1805 1806 if (vfid >= MAX_NUM_VFS && vfid != QED_CXT_PF_CID) { 1807 DP_NOTICE(p_hwfn, "VF [%02x] is out of range\n", vfid); 1808 return -EINVAL; 1809 } 1810 1811 /* Determine the right map to take this CID from */ 1812 if (vfid == QED_CXT_PF_CID) 1813 p_map = &p_mngr->acquired[type]; 1814 else 1815 p_map = &p_mngr->acquired_vf[type][vfid]; 1816 1817 if (!p_map->cid_map) { 1818 DP_NOTICE(p_hwfn, "Invalid protocol type %d", type); 1819 return -EINVAL; 1820 } 1821 1822 rel_cid = find_first_zero_bit(p_map->cid_map, p_map->max_count); 1823 1824 if (rel_cid >= p_map->max_count) { 1825 DP_NOTICE(p_hwfn, "no CID available for protocol %d\n", type); 1826 return -EINVAL; 1827 } 1828 1829 __set_bit(rel_cid, p_map->cid_map); 1830 1831 *p_cid = rel_cid + p_map->start_cid; 1832 1833 DP_VERBOSE(p_hwfn, QED_MSG_CXT, 1834 "Acquired cid 0x%08x [rel. %08x] vfid %02x type %d\n", 1835 *p_cid, rel_cid, vfid, type); 1836 1837 return 0; 1838 } 1839 1840 int qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn, 1841 enum protocol_type type, u32 *p_cid) 1842 { 1843 return _qed_cxt_acquire_cid(p_hwfn, type, p_cid, QED_CXT_PF_CID); 1844 } 1845 1846 static bool qed_cxt_test_cid_acquired(struct qed_hwfn *p_hwfn, 1847 u32 cid, 1848 u8 vfid, 1849 enum protocol_type *p_type, 1850 struct qed_cid_acquired_map **pp_map) 1851 { 1852 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1853 u32 rel_cid; 1854 1855 /* Iterate over protocols and find matching cid range */ 1856 for (*p_type = 0; *p_type < MAX_CONN_TYPES; (*p_type)++) { 1857 if (vfid == QED_CXT_PF_CID) 1858 *pp_map = &p_mngr->acquired[*p_type]; 1859 else 1860 *pp_map = &p_mngr->acquired_vf[*p_type][vfid]; 1861 1862 if (!((*pp_map)->cid_map)) 1863 continue; 1864 if (cid >= (*pp_map)->start_cid && 1865 cid < (*pp_map)->start_cid + (*pp_map)->max_count) 1866 break; 1867 } 1868 1869 if (*p_type == MAX_CONN_TYPES) { 1870 DP_NOTICE(p_hwfn, "Invalid CID %d vfid %02x", cid, vfid); 1871 goto fail; 1872 } 1873 1874 rel_cid = cid - (*pp_map)->start_cid; 1875 if (!test_bit(rel_cid, (*pp_map)->cid_map)) { 1876 DP_NOTICE(p_hwfn, "CID %d [vifd %02x] not acquired", 1877 cid, vfid); 1878 goto fail; 1879 } 1880 1881 return true; 1882 fail: 1883 *p_type = MAX_CONN_TYPES; 1884 *pp_map = NULL; 1885 return false; 1886 } 1887 1888 void _qed_cxt_release_cid(struct qed_hwfn *p_hwfn, u32 cid, u8 vfid) 1889 { 1890 struct qed_cid_acquired_map *p_map = NULL; 1891 enum protocol_type type; 1892 bool b_acquired; 1893 u32 rel_cid; 1894 1895 if (vfid != QED_CXT_PF_CID && vfid > MAX_NUM_VFS) { 1896 DP_NOTICE(p_hwfn, 1897 "Trying to return incorrect CID belonging to VF %02x\n", 1898 vfid); 1899 return; 1900 } 1901 1902 /* Test acquired and find matching per-protocol map */ 1903 b_acquired = qed_cxt_test_cid_acquired(p_hwfn, cid, vfid, 1904 &type, &p_map); 1905 1906 if (!b_acquired) 1907 return; 1908 1909 rel_cid = cid - p_map->start_cid; 1910 clear_bit(rel_cid, p_map->cid_map); 1911 1912 DP_VERBOSE(p_hwfn, QED_MSG_CXT, 1913 "Released CID 0x%08x [rel. %08x] vfid %02x type %d\n", 1914 cid, rel_cid, vfid, type); 1915 } 1916 1917 void qed_cxt_release_cid(struct qed_hwfn *p_hwfn, u32 cid) 1918 { 1919 _qed_cxt_release_cid(p_hwfn, cid, QED_CXT_PF_CID); 1920 } 1921 1922 int qed_cxt_get_cid_info(struct qed_hwfn *p_hwfn, struct qed_cxt_info *p_info) 1923 { 1924 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1925 struct qed_cid_acquired_map *p_map = NULL; 1926 u32 conn_cxt_size, hw_p_size, cxts_per_p, line; 1927 enum protocol_type type; 1928 bool b_acquired; 1929 1930 /* Test acquired and find matching per-protocol map */ 1931 b_acquired = qed_cxt_test_cid_acquired(p_hwfn, p_info->iid, 1932 QED_CXT_PF_CID, &type, &p_map); 1933 1934 if (!b_acquired) 1935 return -EINVAL; 1936 1937 /* set the protocl type */ 1938 p_info->type = type; 1939 1940 /* compute context virtual pointer */ 1941 hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val; 1942 1943 conn_cxt_size = CONN_CXT_SIZE(p_hwfn); 1944 cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size; 1945 line = p_info->iid / cxts_per_p; 1946 1947 /* Make sure context is allocated (dynamic allocation) */ 1948 if (!p_mngr->ilt_shadow[line].virt_addr) 1949 return -EINVAL; 1950 1951 p_info->p_cxt = p_mngr->ilt_shadow[line].virt_addr + 1952 p_info->iid % cxts_per_p * conn_cxt_size; 1953 1954 DP_VERBOSE(p_hwfn, (QED_MSG_ILT | QED_MSG_CXT), 1955 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n", 1956 p_info->iid / cxts_per_p, p_info->p_cxt, p_info->iid); 1957 1958 return 0; 1959 } 1960 1961 static void qed_rdma_set_pf_params(struct qed_hwfn *p_hwfn, 1962 struct qed_rdma_pf_params *p_params, 1963 u32 num_tasks) 1964 { 1965 u32 num_cons, num_qps, num_srqs; 1966 enum protocol_type proto; 1967 1968 num_srqs = min_t(u32, QED_RDMA_MAX_SRQS, p_params->num_srqs); 1969 1970 if (p_hwfn->mcp_info->func_info.protocol == QED_PCI_ETH_RDMA) { 1971 DP_NOTICE(p_hwfn, 1972 "Current day drivers don't support RoCE & iWARP simultaneously on the same PF. Default to RoCE-only\n"); 1973 p_hwfn->hw_info.personality = QED_PCI_ETH_ROCE; 1974 } 1975 1976 switch (p_hwfn->hw_info.personality) { 1977 case QED_PCI_ETH_IWARP: 1978 /* Each QP requires one connection */ 1979 num_cons = min_t(u32, IWARP_MAX_QPS, p_params->num_qps); 1980 proto = PROTOCOLID_IWARP; 1981 break; 1982 case QED_PCI_ETH_ROCE: 1983 num_qps = min_t(u32, ROCE_MAX_QPS, p_params->num_qps); 1984 num_cons = num_qps * 2; /* each QP requires two connections */ 1985 proto = PROTOCOLID_ROCE; 1986 break; 1987 default: 1988 return; 1989 } 1990 1991 if (num_cons && num_tasks) { 1992 qed_cxt_set_proto_cid_count(p_hwfn, proto, num_cons, 0); 1993 1994 /* Deliberatly passing ROCE for tasks id. This is because 1995 * iWARP / RoCE share the task id. 1996 */ 1997 qed_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_ROCE, 1998 QED_CXT_ROCE_TID_SEG, 1, 1999 num_tasks, false); 2000 qed_cxt_set_srq_count(p_hwfn, num_srqs); 2001 } else { 2002 DP_INFO(p_hwfn->cdev, 2003 "RDMA personality used without setting params!\n"); 2004 } 2005 } 2006 2007 int qed_cxt_set_pf_params(struct qed_hwfn *p_hwfn, u32 rdma_tasks) 2008 { 2009 /* Set the number of required CORE connections */ 2010 u32 core_cids = 1; /* SPQ */ 2011 2012 if (p_hwfn->using_ll2) 2013 core_cids += 4; 2014 qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0); 2015 2016 switch (p_hwfn->hw_info.personality) { 2017 case QED_PCI_ETH_RDMA: 2018 case QED_PCI_ETH_IWARP: 2019 case QED_PCI_ETH_ROCE: 2020 { 2021 qed_rdma_set_pf_params(p_hwfn, 2022 &p_hwfn-> 2023 pf_params.rdma_pf_params, 2024 rdma_tasks); 2025 /* no need for break since RoCE coexist with Ethernet */ 2026 } 2027 /* fall through */ 2028 case QED_PCI_ETH: 2029 { 2030 struct qed_eth_pf_params *p_params = 2031 &p_hwfn->pf_params.eth_pf_params; 2032 2033 if (!p_params->num_vf_cons) 2034 p_params->num_vf_cons = 2035 ETH_PF_PARAMS_VF_CONS_DEFAULT; 2036 qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH, 2037 p_params->num_cons, 2038 p_params->num_vf_cons); 2039 p_hwfn->p_cxt_mngr->arfs_count = p_params->num_arfs_filters; 2040 break; 2041 } 2042 case QED_PCI_FCOE: 2043 { 2044 struct qed_fcoe_pf_params *p_params; 2045 2046 p_params = &p_hwfn->pf_params.fcoe_pf_params; 2047 2048 if (p_params->num_cons && p_params->num_tasks) { 2049 qed_cxt_set_proto_cid_count(p_hwfn, 2050 PROTOCOLID_FCOE, 2051 p_params->num_cons, 2052 0); 2053 2054 qed_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_FCOE, 2055 QED_CXT_FCOE_TID_SEG, 0, 2056 p_params->num_tasks, true); 2057 } else { 2058 DP_INFO(p_hwfn->cdev, 2059 "Fcoe personality used without setting params!\n"); 2060 } 2061 break; 2062 } 2063 case QED_PCI_ISCSI: 2064 { 2065 struct qed_iscsi_pf_params *p_params; 2066 2067 p_params = &p_hwfn->pf_params.iscsi_pf_params; 2068 2069 if (p_params->num_cons && p_params->num_tasks) { 2070 qed_cxt_set_proto_cid_count(p_hwfn, 2071 PROTOCOLID_ISCSI, 2072 p_params->num_cons, 2073 0); 2074 2075 qed_cxt_set_proto_tid_count(p_hwfn, 2076 PROTOCOLID_ISCSI, 2077 QED_CXT_ISCSI_TID_SEG, 2078 0, 2079 p_params->num_tasks, 2080 true); 2081 } else { 2082 DP_INFO(p_hwfn->cdev, 2083 "Iscsi personality used without setting params!\n"); 2084 } 2085 break; 2086 } 2087 default: 2088 return -EINVAL; 2089 } 2090 2091 return 0; 2092 } 2093 2094 int qed_cxt_get_tid_mem_info(struct qed_hwfn *p_hwfn, 2095 struct qed_tid_mem *p_info) 2096 { 2097 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 2098 u32 proto, seg, total_lines, i, shadow_line; 2099 struct qed_ilt_client_cfg *p_cli; 2100 struct qed_ilt_cli_blk *p_fl_seg; 2101 struct qed_tid_seg *p_seg_info; 2102 2103 /* Verify the personality */ 2104 switch (p_hwfn->hw_info.personality) { 2105 case QED_PCI_FCOE: 2106 proto = PROTOCOLID_FCOE; 2107 seg = QED_CXT_FCOE_TID_SEG; 2108 break; 2109 case QED_PCI_ISCSI: 2110 proto = PROTOCOLID_ISCSI; 2111 seg = QED_CXT_ISCSI_TID_SEG; 2112 break; 2113 default: 2114 return -EINVAL; 2115 } 2116 2117 p_cli = &p_mngr->clients[ILT_CLI_CDUT]; 2118 if (!p_cli->active) 2119 return -EINVAL; 2120 2121 p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg]; 2122 if (!p_seg_info->has_fl_mem) 2123 return -EINVAL; 2124 2125 p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)]; 2126 total_lines = DIV_ROUND_UP(p_fl_seg->total_size, 2127 p_fl_seg->real_size_in_page); 2128 2129 for (i = 0; i < total_lines; i++) { 2130 shadow_line = i + p_fl_seg->start_line - 2131 p_hwfn->p_cxt_mngr->pf_start_line; 2132 p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].virt_addr; 2133 } 2134 p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) - 2135 p_fl_seg->real_size_in_page; 2136 p_info->tid_size = p_mngr->task_type_size[p_seg_info->type]; 2137 p_info->num_tids_per_block = p_fl_seg->real_size_in_page / 2138 p_info->tid_size; 2139 2140 return 0; 2141 } 2142 2143 /* This function is very RoCE oriented, if another protocol in the future 2144 * will want this feature we'll need to modify the function to be more generic 2145 */ 2146 int 2147 qed_cxt_dynamic_ilt_alloc(struct qed_hwfn *p_hwfn, 2148 enum qed_cxt_elem_type elem_type, u32 iid) 2149 { 2150 u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line; 2151 struct qed_ilt_client_cfg *p_cli; 2152 struct qed_ilt_cli_blk *p_blk; 2153 struct qed_ptt *p_ptt; 2154 dma_addr_t p_phys; 2155 u64 ilt_hw_entry; 2156 void *p_virt; 2157 int rc = 0; 2158 2159 switch (elem_type) { 2160 case QED_ELEM_CXT: 2161 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 2162 elem_size = CONN_CXT_SIZE(p_hwfn); 2163 p_blk = &p_cli->pf_blks[CDUC_BLK]; 2164 break; 2165 case QED_ELEM_SRQ: 2166 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM]; 2167 elem_size = SRQ_CXT_SIZE; 2168 p_blk = &p_cli->pf_blks[SRQ_BLK]; 2169 break; 2170 case QED_ELEM_TASK: 2171 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2172 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn); 2173 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)]; 2174 break; 2175 default: 2176 DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type); 2177 return -EINVAL; 2178 } 2179 2180 /* Calculate line in ilt */ 2181 hw_p_size = p_cli->p_size.val; 2182 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size; 2183 line = p_blk->start_line + (iid / elems_per_p); 2184 shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line; 2185 2186 /* If line is already allocated, do nothing, otherwise allocate it and 2187 * write it to the PSWRQ2 registers. 2188 * This section can be run in parallel from different contexts and thus 2189 * a mutex protection is needed. 2190 */ 2191 2192 mutex_lock(&p_hwfn->p_cxt_mngr->mutex); 2193 2194 if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].virt_addr) 2195 goto out0; 2196 2197 p_ptt = qed_ptt_acquire(p_hwfn); 2198 if (!p_ptt) { 2199 DP_NOTICE(p_hwfn, 2200 "QED_TIME_OUT on ptt acquire - dynamic allocation"); 2201 rc = -EBUSY; 2202 goto out0; 2203 } 2204 2205 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 2206 p_blk->real_size_in_page, &p_phys, 2207 GFP_KERNEL); 2208 if (!p_virt) { 2209 rc = -ENOMEM; 2210 goto out1; 2211 } 2212 2213 /* configuration of refTagMask to 0xF is required for RoCE DIF MR only, 2214 * to compensate for a HW bug, but it is configured even if DIF is not 2215 * enabled. This is harmless and allows us to avoid a dedicated API. We 2216 * configure the field for all of the contexts on the newly allocated 2217 * page. 2218 */ 2219 if (elem_type == QED_ELEM_TASK) { 2220 u32 elem_i; 2221 u8 *elem_start = (u8 *)p_virt; 2222 union type1_task_context *elem; 2223 2224 for (elem_i = 0; elem_i < elems_per_p; elem_i++) { 2225 elem = (union type1_task_context *)elem_start; 2226 SET_FIELD(elem->roce_ctx.tdif_context.flags1, 2227 TDIF_TASK_CONTEXT_REF_TAG_MASK, 0xf); 2228 elem_start += TYPE1_TASK_CXT_SIZE(p_hwfn); 2229 } 2230 } 2231 2232 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].virt_addr = p_virt; 2233 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].phys_addr = p_phys; 2234 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size = 2235 p_blk->real_size_in_page; 2236 2237 /* compute absolute offset */ 2238 reg_offset = PSWRQ2_REG_ILT_MEMORY + 2239 (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS); 2240 2241 ilt_hw_entry = 0; 2242 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL); 2243 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR, 2244 (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].phys_addr 2245 >> 12)); 2246 2247 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */ 2248 qed_dmae_host2grc(p_hwfn, p_ptt, (u64) (uintptr_t)&ilt_hw_entry, 2249 reg_offset, sizeof(ilt_hw_entry) / sizeof(u32), 2250 NULL); 2251 2252 if (elem_type == QED_ELEM_CXT) { 2253 u32 last_cid_allocated = (1 + (iid / elems_per_p)) * 2254 elems_per_p; 2255 2256 /* Update the relevant register in the parser */ 2257 qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 2258 last_cid_allocated - 1); 2259 2260 if (!p_hwfn->b_rdma_enabled_in_prs) { 2261 /* Enable RDMA search */ 2262 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1); 2263 p_hwfn->b_rdma_enabled_in_prs = true; 2264 } 2265 } 2266 2267 out1: 2268 qed_ptt_release(p_hwfn, p_ptt); 2269 out0: 2270 mutex_unlock(&p_hwfn->p_cxt_mngr->mutex); 2271 2272 return rc; 2273 } 2274 2275 /* This function is very RoCE oriented, if another protocol in the future 2276 * will want this feature we'll need to modify the function to be more generic 2277 */ 2278 static int 2279 qed_cxt_free_ilt_range(struct qed_hwfn *p_hwfn, 2280 enum qed_cxt_elem_type elem_type, 2281 u32 start_iid, u32 count) 2282 { 2283 u32 start_line, end_line, shadow_start_line, shadow_end_line; 2284 u32 reg_offset, elem_size, hw_p_size, elems_per_p; 2285 struct qed_ilt_client_cfg *p_cli; 2286 struct qed_ilt_cli_blk *p_blk; 2287 u32 end_iid = start_iid + count; 2288 struct qed_ptt *p_ptt; 2289 u64 ilt_hw_entry = 0; 2290 u32 i; 2291 2292 switch (elem_type) { 2293 case QED_ELEM_CXT: 2294 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 2295 elem_size = CONN_CXT_SIZE(p_hwfn); 2296 p_blk = &p_cli->pf_blks[CDUC_BLK]; 2297 break; 2298 case QED_ELEM_SRQ: 2299 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM]; 2300 elem_size = SRQ_CXT_SIZE; 2301 p_blk = &p_cli->pf_blks[SRQ_BLK]; 2302 break; 2303 case QED_ELEM_TASK: 2304 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2305 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn); 2306 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)]; 2307 break; 2308 default: 2309 DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type); 2310 return -EINVAL; 2311 } 2312 2313 /* Calculate line in ilt */ 2314 hw_p_size = p_cli->p_size.val; 2315 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size; 2316 start_line = p_blk->start_line + (start_iid / elems_per_p); 2317 end_line = p_blk->start_line + (end_iid / elems_per_p); 2318 if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p)) 2319 end_line--; 2320 2321 shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line; 2322 shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line; 2323 2324 p_ptt = qed_ptt_acquire(p_hwfn); 2325 if (!p_ptt) { 2326 DP_NOTICE(p_hwfn, 2327 "QED_TIME_OUT on ptt acquire - dynamic allocation"); 2328 return -EBUSY; 2329 } 2330 2331 for (i = shadow_start_line; i < shadow_end_line; i++) { 2332 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].virt_addr) 2333 continue; 2334 2335 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 2336 p_hwfn->p_cxt_mngr->ilt_shadow[i].size, 2337 p_hwfn->p_cxt_mngr->ilt_shadow[i].virt_addr, 2338 p_hwfn->p_cxt_mngr->ilt_shadow[i].phys_addr); 2339 2340 p_hwfn->p_cxt_mngr->ilt_shadow[i].virt_addr = NULL; 2341 p_hwfn->p_cxt_mngr->ilt_shadow[i].phys_addr = 0; 2342 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0; 2343 2344 /* compute absolute offset */ 2345 reg_offset = PSWRQ2_REG_ILT_MEMORY + 2346 ((start_line++) * ILT_REG_SIZE_IN_BYTES * 2347 ILT_ENTRY_IN_REGS); 2348 2349 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a 2350 * wide-bus. 2351 */ 2352 qed_dmae_host2grc(p_hwfn, p_ptt, 2353 (u64) (uintptr_t) &ilt_hw_entry, 2354 reg_offset, 2355 sizeof(ilt_hw_entry) / sizeof(u32), 2356 NULL); 2357 } 2358 2359 qed_ptt_release(p_hwfn, p_ptt); 2360 2361 return 0; 2362 } 2363 2364 int qed_cxt_free_proto_ilt(struct qed_hwfn *p_hwfn, enum protocol_type proto) 2365 { 2366 int rc; 2367 u32 cid; 2368 2369 /* Free Connection CXT */ 2370 rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_CXT, 2371 qed_cxt_get_proto_cid_start(p_hwfn, 2372 proto), 2373 qed_cxt_get_proto_cid_count(p_hwfn, 2374 proto, &cid)); 2375 2376 if (rc) 2377 return rc; 2378 2379 /* Free Task CXT ( Intentionally RoCE as task-id is shared between 2380 * RoCE and iWARP ) 2381 */ 2382 proto = PROTOCOLID_ROCE; 2383 rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_TASK, 0, 2384 qed_cxt_get_proto_tid_count(p_hwfn, proto)); 2385 if (rc) 2386 return rc; 2387 2388 /* Free TSDM CXT */ 2389 rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_SRQ, 0, 2390 qed_cxt_get_srq_count(p_hwfn)); 2391 2392 return rc; 2393 } 2394 2395 int qed_cxt_get_task_ctx(struct qed_hwfn *p_hwfn, 2396 u32 tid, u8 ctx_type, void **pp_task_ctx) 2397 { 2398 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 2399 struct qed_ilt_client_cfg *p_cli; 2400 struct qed_tid_seg *p_seg_info; 2401 struct qed_ilt_cli_blk *p_seg; 2402 u32 num_tids_per_block; 2403 u32 tid_size, ilt_idx; 2404 u32 total_lines; 2405 u32 proto, seg; 2406 2407 /* Verify the personality */ 2408 switch (p_hwfn->hw_info.personality) { 2409 case QED_PCI_FCOE: 2410 proto = PROTOCOLID_FCOE; 2411 seg = QED_CXT_FCOE_TID_SEG; 2412 break; 2413 case QED_PCI_ISCSI: 2414 proto = PROTOCOLID_ISCSI; 2415 seg = QED_CXT_ISCSI_TID_SEG; 2416 break; 2417 default: 2418 return -EINVAL; 2419 } 2420 2421 p_cli = &p_mngr->clients[ILT_CLI_CDUT]; 2422 if (!p_cli->active) 2423 return -EINVAL; 2424 2425 p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg]; 2426 2427 if (ctx_type == QED_CTX_WORKING_MEM) { 2428 p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)]; 2429 } else if (ctx_type == QED_CTX_FL_MEM) { 2430 if (!p_seg_info->has_fl_mem) 2431 return -EINVAL; 2432 p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)]; 2433 } else { 2434 return -EINVAL; 2435 } 2436 total_lines = DIV_ROUND_UP(p_seg->total_size, p_seg->real_size_in_page); 2437 tid_size = p_mngr->task_type_size[p_seg_info->type]; 2438 num_tids_per_block = p_seg->real_size_in_page / tid_size; 2439 2440 if (total_lines < tid / num_tids_per_block) 2441 return -EINVAL; 2442 2443 ilt_idx = tid / num_tids_per_block + p_seg->start_line - 2444 p_mngr->pf_start_line; 2445 *pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].virt_addr + 2446 (tid % num_tids_per_block) * tid_size; 2447 2448 return 0; 2449 } 2450 2451 static u16 qed_blk_calculate_pages(struct qed_ilt_cli_blk *p_blk) 2452 { 2453 if (p_blk->real_size_in_page == 0) 2454 return 0; 2455 2456 return DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page); 2457 } 2458 2459 u16 qed_get_cdut_num_pf_init_pages(struct qed_hwfn *p_hwfn) 2460 { 2461 struct qed_ilt_client_cfg *p_cli; 2462 struct qed_ilt_cli_blk *p_blk; 2463 u16 i, pages = 0; 2464 2465 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2466 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 2467 p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)]; 2468 pages += qed_blk_calculate_pages(p_blk); 2469 } 2470 2471 return pages; 2472 } 2473 2474 u16 qed_get_cdut_num_vf_init_pages(struct qed_hwfn *p_hwfn) 2475 { 2476 struct qed_ilt_client_cfg *p_cli; 2477 struct qed_ilt_cli_blk *p_blk; 2478 u16 i, pages = 0; 2479 2480 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2481 for (i = 0; i < NUM_TASK_VF_SEGMENTS; i++) { 2482 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(i, VF)]; 2483 pages += qed_blk_calculate_pages(p_blk); 2484 } 2485 2486 return pages; 2487 } 2488 2489 u16 qed_get_cdut_num_pf_work_pages(struct qed_hwfn *p_hwfn) 2490 { 2491 struct qed_ilt_client_cfg *p_cli; 2492 struct qed_ilt_cli_blk *p_blk; 2493 u16 i, pages = 0; 2494 2495 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2496 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 2497 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)]; 2498 pages += qed_blk_calculate_pages(p_blk); 2499 } 2500 2501 return pages; 2502 } 2503 2504 u16 qed_get_cdut_num_vf_work_pages(struct qed_hwfn *p_hwfn) 2505 { 2506 struct qed_ilt_client_cfg *p_cli; 2507 struct qed_ilt_cli_blk *p_blk; 2508 u16 pages = 0, i; 2509 2510 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2511 for (i = 0; i < NUM_TASK_VF_SEGMENTS; i++) { 2512 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(i)]; 2513 pages += qed_blk_calculate_pages(p_blk); 2514 } 2515 2516 return pages; 2517 } 2518