1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #include <linux/types.h> 34 #include <linux/bitops.h> 35 #include <linux/dma-mapping.h> 36 #include <linux/errno.h> 37 #include <linux/kernel.h> 38 #include <linux/list.h> 39 #include <linux/log2.h> 40 #include <linux/pci.h> 41 #include <linux/slab.h> 42 #include <linux/string.h> 43 #include "qed.h" 44 #include "qed_cxt.h" 45 #include "qed_dev_api.h" 46 #include "qed_hsi.h" 47 #include "qed_hw.h" 48 #include "qed_init_ops.h" 49 #include "qed_rdma.h" 50 #include "qed_reg_addr.h" 51 #include "qed_sriov.h" 52 53 /* QM constants */ 54 #define QM_PQ_ELEMENT_SIZE 4 /* in bytes */ 55 56 /* Doorbell-Queue constants */ 57 #define DQ_RANGE_SHIFT 4 58 #define DQ_RANGE_ALIGN BIT(DQ_RANGE_SHIFT) 59 60 /* Searcher constants */ 61 #define SRC_MIN_NUM_ELEMS 256 62 63 /* Timers constants */ 64 #define TM_SHIFT 7 65 #define TM_ALIGN BIT(TM_SHIFT) 66 #define TM_ELEM_SIZE 4 67 68 #define ILT_DEFAULT_HW_P_SIZE 4 69 70 #define ILT_PAGE_IN_BYTES(hw_p_size) (1U << ((hw_p_size) + 12)) 71 #define ILT_CFG_REG(cli, reg) PSWRQ2_REG_ ## cli ## _ ## reg ## _RT_OFFSET 72 73 /* ILT entry structure */ 74 #define ILT_ENTRY_PHY_ADDR_MASK (~0ULL >> 12) 75 #define ILT_ENTRY_PHY_ADDR_SHIFT 0 76 #define ILT_ENTRY_VALID_MASK 0x1ULL 77 #define ILT_ENTRY_VALID_SHIFT 52 78 #define ILT_ENTRY_IN_REGS 2 79 #define ILT_REG_SIZE_IN_BYTES 4 80 81 /* connection context union */ 82 union conn_context { 83 struct e4_core_conn_context core_ctx; 84 struct e4_eth_conn_context eth_ctx; 85 struct e4_iscsi_conn_context iscsi_ctx; 86 struct e4_fcoe_conn_context fcoe_ctx; 87 struct e4_roce_conn_context roce_ctx; 88 }; 89 90 /* TYPE-0 task context - iSCSI, FCOE */ 91 union type0_task_context { 92 struct e4_iscsi_task_context iscsi_ctx; 93 struct e4_fcoe_task_context fcoe_ctx; 94 }; 95 96 /* TYPE-1 task context - ROCE */ 97 union type1_task_context { 98 struct e4_rdma_task_context roce_ctx; 99 }; 100 101 struct src_ent { 102 u8 opaque[56]; 103 u64 next; 104 }; 105 106 #define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */ 107 #define CDUT_SEG_ALIGNMET_IN_BYTES BIT(CDUT_SEG_ALIGNMET + 12) 108 109 #define CONN_CXT_SIZE(p_hwfn) \ 110 ALIGNED_TYPE_SIZE(union conn_context, p_hwfn) 111 112 #define SRQ_CXT_SIZE (sizeof(struct rdma_srq_context)) 113 #define XRC_SRQ_CXT_SIZE (sizeof(struct rdma_xrc_srq_context)) 114 115 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \ 116 ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn) 117 118 /* Alignment is inherent to the type1_task_context structure */ 119 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context) 120 121 static bool src_proto(enum protocol_type type) 122 { 123 return type == PROTOCOLID_ISCSI || 124 type == PROTOCOLID_FCOE || 125 type == PROTOCOLID_IWARP; 126 } 127 128 static bool tm_cid_proto(enum protocol_type type) 129 { 130 return type == PROTOCOLID_ISCSI || 131 type == PROTOCOLID_FCOE || 132 type == PROTOCOLID_ROCE || 133 type == PROTOCOLID_IWARP; 134 } 135 136 static bool tm_tid_proto(enum protocol_type type) 137 { 138 return type == PROTOCOLID_FCOE; 139 } 140 141 /* counts the iids for the CDU/CDUC ILT client configuration */ 142 struct qed_cdu_iids { 143 u32 pf_cids; 144 u32 per_vf_cids; 145 }; 146 147 static void qed_cxt_cdu_iids(struct qed_cxt_mngr *p_mngr, 148 struct qed_cdu_iids *iids) 149 { 150 u32 type; 151 152 for (type = 0; type < MAX_CONN_TYPES; type++) { 153 iids->pf_cids += p_mngr->conn_cfg[type].cid_count; 154 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf; 155 } 156 } 157 158 /* counts the iids for the Searcher block configuration */ 159 struct qed_src_iids { 160 u32 pf_cids; 161 u32 per_vf_cids; 162 }; 163 164 static void qed_cxt_src_iids(struct qed_cxt_mngr *p_mngr, 165 struct qed_src_iids *iids) 166 { 167 u32 i; 168 169 for (i = 0; i < MAX_CONN_TYPES; i++) { 170 if (!src_proto(i)) 171 continue; 172 173 iids->pf_cids += p_mngr->conn_cfg[i].cid_count; 174 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf; 175 } 176 177 /* Add L2 filtering filters in addition */ 178 iids->pf_cids += p_mngr->arfs_count; 179 } 180 181 /* counts the iids for the Timers block configuration */ 182 struct qed_tm_iids { 183 u32 pf_cids; 184 u32 pf_tids[NUM_TASK_PF_SEGMENTS]; /* per segment */ 185 u32 pf_tids_total; 186 u32 per_vf_cids; 187 u32 per_vf_tids; 188 }; 189 190 static void qed_cxt_tm_iids(struct qed_hwfn *p_hwfn, 191 struct qed_cxt_mngr *p_mngr, 192 struct qed_tm_iids *iids) 193 { 194 bool tm_vf_required = false; 195 bool tm_required = false; 196 int i, j; 197 198 /* Timers is a special case -> we don't count how many cids require 199 * timers but what's the max cid that will be used by the timer block. 200 * therefore we traverse in reverse order, and once we hit a protocol 201 * that requires the timers memory, we'll sum all the protocols up 202 * to that one. 203 */ 204 for (i = MAX_CONN_TYPES - 1; i >= 0; i--) { 205 struct qed_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i]; 206 207 if (tm_cid_proto(i) || tm_required) { 208 if (p_cfg->cid_count) 209 tm_required = true; 210 211 iids->pf_cids += p_cfg->cid_count; 212 } 213 214 if (tm_cid_proto(i) || tm_vf_required) { 215 if (p_cfg->cids_per_vf) 216 tm_vf_required = true; 217 218 iids->per_vf_cids += p_cfg->cids_per_vf; 219 } 220 221 if (tm_tid_proto(i)) { 222 struct qed_tid_seg *segs = p_cfg->tid_seg; 223 224 /* for each segment there is at most one 225 * protocol for which count is not 0. 226 */ 227 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++) 228 iids->pf_tids[j] += segs[j].count; 229 230 /* The last array elelment is for the VFs. As for PF 231 * segments there can be only one protocol for 232 * which this value is not 0. 233 */ 234 iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count; 235 } 236 } 237 238 iids->pf_cids = roundup(iids->pf_cids, TM_ALIGN); 239 iids->per_vf_cids = roundup(iids->per_vf_cids, TM_ALIGN); 240 iids->per_vf_tids = roundup(iids->per_vf_tids, TM_ALIGN); 241 242 for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) { 243 iids->pf_tids[j] = roundup(iids->pf_tids[j], TM_ALIGN); 244 iids->pf_tids_total += iids->pf_tids[j]; 245 } 246 } 247 248 static void qed_cxt_qm_iids(struct qed_hwfn *p_hwfn, 249 struct qed_qm_iids *iids) 250 { 251 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 252 struct qed_tid_seg *segs; 253 u32 vf_cids = 0, type, j; 254 u32 vf_tids = 0; 255 256 for (type = 0; type < MAX_CONN_TYPES; type++) { 257 iids->cids += p_mngr->conn_cfg[type].cid_count; 258 vf_cids += p_mngr->conn_cfg[type].cids_per_vf; 259 260 segs = p_mngr->conn_cfg[type].tid_seg; 261 /* for each segment there is at most one 262 * protocol for which count is not 0. 263 */ 264 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++) 265 iids->tids += segs[j].count; 266 267 /* The last array elelment is for the VFs. As for PF 268 * segments there can be only one protocol for 269 * which this value is not 0. 270 */ 271 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count; 272 } 273 274 iids->vf_cids += vf_cids * p_mngr->vf_count; 275 iids->tids += vf_tids * p_mngr->vf_count; 276 277 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 278 "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n", 279 iids->cids, iids->vf_cids, iids->tids, vf_tids); 280 } 281 282 static struct qed_tid_seg *qed_cxt_tid_seg_info(struct qed_hwfn *p_hwfn, 283 u32 seg) 284 { 285 struct qed_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr; 286 u32 i; 287 288 /* Find the protocol with tid count > 0 for this segment. 289 * Note: there can only be one and this is already validated. 290 */ 291 for (i = 0; i < MAX_CONN_TYPES; i++) 292 if (p_cfg->conn_cfg[i].tid_seg[seg].count) 293 return &p_cfg->conn_cfg[i].tid_seg[seg]; 294 return NULL; 295 } 296 297 static void qed_cxt_set_srq_count(struct qed_hwfn *p_hwfn, 298 u32 num_srqs, u32 num_xrc_srqs) 299 { 300 struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; 301 302 p_mgr->srq_count = num_srqs; 303 p_mgr->xrc_srq_count = num_xrc_srqs; 304 } 305 306 u32 qed_cxt_get_ilt_page_size(struct qed_hwfn *p_hwfn, 307 enum ilt_clients ilt_client) 308 { 309 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 310 struct qed_ilt_client_cfg *p_cli = &p_mngr->clients[ilt_client]; 311 312 return ILT_PAGE_IN_BYTES(p_cli->p_size.val); 313 } 314 315 static u32 qed_cxt_xrc_srqs_per_page(struct qed_hwfn *p_hwfn) 316 { 317 u32 page_size; 318 319 page_size = qed_cxt_get_ilt_page_size(p_hwfn, ILT_CLI_TSDM); 320 return page_size / XRC_SRQ_CXT_SIZE; 321 } 322 323 u32 qed_cxt_get_total_srq_count(struct qed_hwfn *p_hwfn) 324 { 325 struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; 326 u32 total_srqs; 327 328 total_srqs = p_mgr->srq_count + p_mgr->xrc_srq_count; 329 330 return total_srqs; 331 } 332 333 /* set the iids count per protocol */ 334 static void qed_cxt_set_proto_cid_count(struct qed_hwfn *p_hwfn, 335 enum protocol_type type, 336 u32 cid_count, u32 vf_cid_cnt) 337 { 338 struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; 339 struct qed_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type]; 340 341 p_conn->cid_count = roundup(cid_count, DQ_RANGE_ALIGN); 342 p_conn->cids_per_vf = roundup(vf_cid_cnt, DQ_RANGE_ALIGN); 343 344 if (type == PROTOCOLID_ROCE) { 345 u32 page_sz = p_mgr->clients[ILT_CLI_CDUC].p_size.val; 346 u32 cxt_size = CONN_CXT_SIZE(p_hwfn); 347 u32 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 348 u32 align = elems_per_page * DQ_RANGE_ALIGN; 349 350 p_conn->cid_count = roundup(p_conn->cid_count, align); 351 } 352 } 353 354 u32 qed_cxt_get_proto_cid_count(struct qed_hwfn *p_hwfn, 355 enum protocol_type type, u32 *vf_cid) 356 { 357 if (vf_cid) 358 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf; 359 360 return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count; 361 } 362 363 u32 qed_cxt_get_proto_cid_start(struct qed_hwfn *p_hwfn, 364 enum protocol_type type) 365 { 366 return p_hwfn->p_cxt_mngr->acquired[type].start_cid; 367 } 368 369 u32 qed_cxt_get_proto_tid_count(struct qed_hwfn *p_hwfn, 370 enum protocol_type type) 371 { 372 u32 cnt = 0; 373 int i; 374 375 for (i = 0; i < TASK_SEGMENTS; i++) 376 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count; 377 378 return cnt; 379 } 380 381 static void qed_cxt_set_proto_tid_count(struct qed_hwfn *p_hwfn, 382 enum protocol_type proto, 383 u8 seg, 384 u8 seg_type, u32 count, bool has_fl) 385 { 386 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 387 struct qed_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg]; 388 389 p_seg->count = count; 390 p_seg->has_fl_mem = has_fl; 391 p_seg->type = seg_type; 392 } 393 394 static void qed_ilt_cli_blk_fill(struct qed_ilt_client_cfg *p_cli, 395 struct qed_ilt_cli_blk *p_blk, 396 u32 start_line, u32 total_size, u32 elem_size) 397 { 398 u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val); 399 400 /* verify thatits called only once for each block */ 401 if (p_blk->total_size) 402 return; 403 404 p_blk->total_size = total_size; 405 p_blk->real_size_in_page = 0; 406 if (elem_size) 407 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size; 408 p_blk->start_line = start_line; 409 } 410 411 static void qed_ilt_cli_adv_line(struct qed_hwfn *p_hwfn, 412 struct qed_ilt_client_cfg *p_cli, 413 struct qed_ilt_cli_blk *p_blk, 414 u32 *p_line, enum ilt_clients client_id) 415 { 416 if (!p_blk->total_size) 417 return; 418 419 if (!p_cli->active) 420 p_cli->first.val = *p_line; 421 422 p_cli->active = true; 423 *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page); 424 p_cli->last.val = *p_line - 1; 425 426 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 427 "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x [Real %08x] Start line %d\n", 428 client_id, p_cli->first.val, 429 p_cli->last.val, p_blk->total_size, 430 p_blk->real_size_in_page, p_blk->start_line); 431 } 432 433 static u32 qed_ilt_get_dynamic_line_cnt(struct qed_hwfn *p_hwfn, 434 enum ilt_clients ilt_client) 435 { 436 u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count; 437 struct qed_ilt_client_cfg *p_cli; 438 u32 lines_to_skip = 0; 439 u32 cxts_per_p; 440 441 if (ilt_client == ILT_CLI_CDUC) { 442 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 443 444 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) / 445 (u32) CONN_CXT_SIZE(p_hwfn); 446 447 lines_to_skip = cid_count / cxts_per_p; 448 } 449 450 return lines_to_skip; 451 } 452 453 static struct qed_ilt_client_cfg *qed_cxt_set_cli(struct qed_ilt_client_cfg 454 *p_cli) 455 { 456 p_cli->active = false; 457 p_cli->first.val = 0; 458 p_cli->last.val = 0; 459 return p_cli; 460 } 461 462 static struct qed_ilt_cli_blk *qed_cxt_set_blk(struct qed_ilt_cli_blk *p_blk) 463 { 464 p_blk->total_size = 0; 465 return p_blk; 466 } 467 468 int qed_cxt_cfg_ilt_compute(struct qed_hwfn *p_hwfn, u32 *line_count) 469 { 470 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 471 u32 curr_line, total, i, task_size, line; 472 struct qed_ilt_client_cfg *p_cli; 473 struct qed_ilt_cli_blk *p_blk; 474 struct qed_cdu_iids cdu_iids; 475 struct qed_src_iids src_iids; 476 struct qed_qm_iids qm_iids; 477 struct qed_tm_iids tm_iids; 478 struct qed_tid_seg *p_seg; 479 480 memset(&qm_iids, 0, sizeof(qm_iids)); 481 memset(&cdu_iids, 0, sizeof(cdu_iids)); 482 memset(&src_iids, 0, sizeof(src_iids)); 483 memset(&tm_iids, 0, sizeof(tm_iids)); 484 485 p_mngr->pf_start_line = RESC_START(p_hwfn, QED_ILT); 486 487 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 488 "hwfn [%d] - Set context manager starting line to be 0x%08x\n", 489 p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line); 490 491 /* CDUC */ 492 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_CDUC]); 493 494 curr_line = p_mngr->pf_start_line; 495 496 /* CDUC PF */ 497 p_cli->pf_total_lines = 0; 498 499 /* get the counters for the CDUC and QM clients */ 500 qed_cxt_cdu_iids(p_mngr, &cdu_iids); 501 502 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[CDUC_BLK]); 503 504 total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn); 505 506 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 507 total, CONN_CXT_SIZE(p_hwfn)); 508 509 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC); 510 p_cli->pf_total_lines = curr_line - p_blk->start_line; 511 512 p_blk->dynamic_line_cnt = qed_ilt_get_dynamic_line_cnt(p_hwfn, 513 ILT_CLI_CDUC); 514 515 /* CDUC VF */ 516 p_blk = qed_cxt_set_blk(&p_cli->vf_blks[CDUC_BLK]); 517 total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn); 518 519 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 520 total, CONN_CXT_SIZE(p_hwfn)); 521 522 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC); 523 p_cli->vf_total_lines = curr_line - p_blk->start_line; 524 525 for (i = 1; i < p_mngr->vf_count; i++) 526 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 527 ILT_CLI_CDUC); 528 529 /* CDUT PF */ 530 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_CDUT]); 531 p_cli->first.val = curr_line; 532 533 /* first the 'working' task memory */ 534 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 535 p_seg = qed_cxt_tid_seg_info(p_hwfn, i); 536 if (!p_seg || p_seg->count == 0) 537 continue; 538 539 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[CDUT_SEG_BLK(i)]); 540 total = p_seg->count * p_mngr->task_type_size[p_seg->type]; 541 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total, 542 p_mngr->task_type_size[p_seg->type]); 543 544 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 545 ILT_CLI_CDUT); 546 } 547 548 /* next the 'init' task memory (forced load memory) */ 549 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 550 p_seg = qed_cxt_tid_seg_info(p_hwfn, i); 551 if (!p_seg || p_seg->count == 0) 552 continue; 553 554 p_blk = 555 qed_cxt_set_blk(&p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)]); 556 557 if (!p_seg->has_fl_mem) { 558 /* The segment is active (total size pf 'working' 559 * memory is > 0) but has no FL (forced-load, Init) 560 * memory. Thus: 561 * 562 * 1. The total-size in the corrsponding FL block of 563 * the ILT client is set to 0 - No ILT line are 564 * provisioned and no ILT memory allocated. 565 * 566 * 2. The start-line of said block is set to the 567 * start line of the matching working memory 568 * block in the ILT client. This is later used to 569 * configure the CDU segment offset registers and 570 * results in an FL command for TIDs of this 571 * segement behaves as regular load commands 572 * (loading TIDs from the working memory). 573 */ 574 line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line; 575 576 qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0); 577 continue; 578 } 579 total = p_seg->count * p_mngr->task_type_size[p_seg->type]; 580 581 qed_ilt_cli_blk_fill(p_cli, p_blk, 582 curr_line, total, 583 p_mngr->task_type_size[p_seg->type]); 584 585 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 586 ILT_CLI_CDUT); 587 } 588 p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line; 589 590 /* CDUT VF */ 591 p_seg = qed_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF); 592 if (p_seg && p_seg->count) { 593 /* Stricly speaking we need to iterate over all VF 594 * task segment types, but a VF has only 1 segment 595 */ 596 597 /* 'working' memory */ 598 total = p_seg->count * p_mngr->task_type_size[p_seg->type]; 599 600 p_blk = qed_cxt_set_blk(&p_cli->vf_blks[CDUT_SEG_BLK(0)]); 601 qed_ilt_cli_blk_fill(p_cli, p_blk, 602 curr_line, total, 603 p_mngr->task_type_size[p_seg->type]); 604 605 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 606 ILT_CLI_CDUT); 607 608 /* 'init' memory */ 609 p_blk = 610 qed_cxt_set_blk(&p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)]); 611 if (!p_seg->has_fl_mem) { 612 /* see comment above */ 613 line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line; 614 qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0); 615 } else { 616 task_size = p_mngr->task_type_size[p_seg->type]; 617 qed_ilt_cli_blk_fill(p_cli, p_blk, 618 curr_line, total, task_size); 619 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 620 ILT_CLI_CDUT); 621 } 622 p_cli->vf_total_lines = curr_line - 623 p_cli->vf_blks[0].start_line; 624 625 /* Now for the rest of the VFs */ 626 for (i = 1; i < p_mngr->vf_count; i++) { 627 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)]; 628 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 629 ILT_CLI_CDUT); 630 631 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)]; 632 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 633 ILT_CLI_CDUT); 634 } 635 } 636 637 /* QM */ 638 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_QM]); 639 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[0]); 640 641 qed_cxt_qm_iids(p_hwfn, &qm_iids); 642 total = qed_qm_pf_mem_size(qm_iids.cids, 643 qm_iids.vf_cids, qm_iids.tids, 644 p_hwfn->qm_info.num_pqs, 645 p_hwfn->qm_info.num_vf_pqs); 646 647 DP_VERBOSE(p_hwfn, 648 QED_MSG_ILT, 649 "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d, num_vf_pqs=%d, memory_size=%d)\n", 650 qm_iids.cids, 651 qm_iids.vf_cids, 652 qm_iids.tids, 653 p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total); 654 655 qed_ilt_cli_blk_fill(p_cli, p_blk, 656 curr_line, total * 0x1000, 657 QM_PQ_ELEMENT_SIZE); 658 659 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM); 660 p_cli->pf_total_lines = curr_line - p_blk->start_line; 661 662 /* SRC */ 663 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_SRC]); 664 qed_cxt_src_iids(p_mngr, &src_iids); 665 666 /* Both the PF and VFs searcher connections are stored in the per PF 667 * database. Thus sum the PF searcher cids and all the VFs searcher 668 * cids. 669 */ 670 total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count; 671 if (total) { 672 u32 local_max = max_t(u32, total, 673 SRC_MIN_NUM_ELEMS); 674 675 total = roundup_pow_of_two(local_max); 676 677 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[0]); 678 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 679 total * sizeof(struct src_ent), 680 sizeof(struct src_ent)); 681 682 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 683 ILT_CLI_SRC); 684 p_cli->pf_total_lines = curr_line - p_blk->start_line; 685 } 686 687 /* TM PF */ 688 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_TM]); 689 qed_cxt_tm_iids(p_hwfn, p_mngr, &tm_iids); 690 total = tm_iids.pf_cids + tm_iids.pf_tids_total; 691 if (total) { 692 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[0]); 693 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 694 total * TM_ELEM_SIZE, TM_ELEM_SIZE); 695 696 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 697 ILT_CLI_TM); 698 p_cli->pf_total_lines = curr_line - p_blk->start_line; 699 } 700 701 /* TM VF */ 702 total = tm_iids.per_vf_cids + tm_iids.per_vf_tids; 703 if (total) { 704 p_blk = qed_cxt_set_blk(&p_cli->vf_blks[0]); 705 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 706 total * TM_ELEM_SIZE, TM_ELEM_SIZE); 707 708 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 709 ILT_CLI_TM); 710 711 p_cli->vf_total_lines = curr_line - p_blk->start_line; 712 for (i = 1; i < p_mngr->vf_count; i++) 713 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 714 ILT_CLI_TM); 715 } 716 717 /* TSDM (SRQ CONTEXT) */ 718 total = qed_cxt_get_total_srq_count(p_hwfn); 719 720 if (total) { 721 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_TSDM]); 722 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[SRQ_BLK]); 723 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 724 total * SRQ_CXT_SIZE, SRQ_CXT_SIZE); 725 726 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 727 ILT_CLI_TSDM); 728 p_cli->pf_total_lines = curr_line - p_blk->start_line; 729 } 730 731 *line_count = curr_line - p_hwfn->p_cxt_mngr->pf_start_line; 732 733 if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line > 734 RESC_NUM(p_hwfn, QED_ILT)) 735 return -EINVAL; 736 737 return 0; 738 } 739 740 u32 qed_cxt_cfg_ilt_compute_excess(struct qed_hwfn *p_hwfn, u32 used_lines) 741 { 742 struct qed_ilt_client_cfg *p_cli; 743 u32 excess_lines, available_lines; 744 struct qed_cxt_mngr *p_mngr; 745 u32 ilt_page_size, elem_size; 746 struct qed_tid_seg *p_seg; 747 int i; 748 749 available_lines = RESC_NUM(p_hwfn, QED_ILT); 750 excess_lines = used_lines - available_lines; 751 752 if (!excess_lines) 753 return 0; 754 755 if (!QED_IS_RDMA_PERSONALITY(p_hwfn)) 756 return 0; 757 758 p_mngr = p_hwfn->p_cxt_mngr; 759 p_cli = &p_mngr->clients[ILT_CLI_CDUT]; 760 ilt_page_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val); 761 762 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 763 p_seg = qed_cxt_tid_seg_info(p_hwfn, i); 764 if (!p_seg || p_seg->count == 0) 765 continue; 766 767 elem_size = p_mngr->task_type_size[p_seg->type]; 768 if (!elem_size) 769 continue; 770 771 return (ilt_page_size / elem_size) * excess_lines; 772 } 773 774 DP_NOTICE(p_hwfn, "failed computing excess ILT lines\n"); 775 return 0; 776 } 777 778 static void qed_cxt_src_t2_free(struct qed_hwfn *p_hwfn) 779 { 780 struct qed_src_t2 *p_t2 = &p_hwfn->p_cxt_mngr->src_t2; 781 u32 i; 782 783 if (!p_t2 || !p_t2->dma_mem) 784 return; 785 786 for (i = 0; i < p_t2->num_pages; i++) 787 if (p_t2->dma_mem[i].virt_addr) 788 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 789 p_t2->dma_mem[i].size, 790 p_t2->dma_mem[i].virt_addr, 791 p_t2->dma_mem[i].phys_addr); 792 793 kfree(p_t2->dma_mem); 794 p_t2->dma_mem = NULL; 795 } 796 797 static int 798 qed_cxt_t2_alloc_pages(struct qed_hwfn *p_hwfn, 799 struct qed_src_t2 *p_t2, u32 total_size, u32 page_size) 800 { 801 void **p_virt; 802 u32 size, i; 803 804 if (!p_t2 || !p_t2->dma_mem) 805 return -EINVAL; 806 807 for (i = 0; i < p_t2->num_pages; i++) { 808 size = min_t(u32, total_size, page_size); 809 p_virt = &p_t2->dma_mem[i].virt_addr; 810 811 *p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 812 size, 813 &p_t2->dma_mem[i].phys_addr, 814 GFP_KERNEL); 815 if (!p_t2->dma_mem[i].virt_addr) 816 return -ENOMEM; 817 818 memset(*p_virt, 0, size); 819 p_t2->dma_mem[i].size = size; 820 total_size -= size; 821 } 822 823 return 0; 824 } 825 826 static int qed_cxt_src_t2_alloc(struct qed_hwfn *p_hwfn) 827 { 828 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 829 u32 conn_num, total_size, ent_per_page, psz, i; 830 struct phys_mem_desc *p_t2_last_page; 831 struct qed_ilt_client_cfg *p_src; 832 struct qed_src_iids src_iids; 833 struct qed_src_t2 *p_t2; 834 int rc; 835 836 memset(&src_iids, 0, sizeof(src_iids)); 837 838 /* if the SRC ILT client is inactive - there are no connection 839 * requiring the searcer, leave. 840 */ 841 p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC]; 842 if (!p_src->active) 843 return 0; 844 845 qed_cxt_src_iids(p_mngr, &src_iids); 846 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count; 847 total_size = conn_num * sizeof(struct src_ent); 848 849 /* use the same page size as the SRC ILT client */ 850 psz = ILT_PAGE_IN_BYTES(p_src->p_size.val); 851 p_t2 = &p_mngr->src_t2; 852 p_t2->num_pages = DIV_ROUND_UP(total_size, psz); 853 854 /* allocate t2 */ 855 p_t2->dma_mem = kcalloc(p_t2->num_pages, sizeof(struct phys_mem_desc), 856 GFP_KERNEL); 857 if (!p_t2->dma_mem) { 858 DP_NOTICE(p_hwfn, "Failed to allocate t2 table\n"); 859 rc = -ENOMEM; 860 goto t2_fail; 861 } 862 863 rc = qed_cxt_t2_alloc_pages(p_hwfn, p_t2, total_size, psz); 864 if (rc) 865 goto t2_fail; 866 867 /* Set the t2 pointers */ 868 869 /* entries per page - must be a power of two */ 870 ent_per_page = psz / sizeof(struct src_ent); 871 872 p_t2->first_free = (u64)p_t2->dma_mem[0].phys_addr; 873 874 p_t2_last_page = &p_t2->dma_mem[(conn_num - 1) / ent_per_page]; 875 p_t2->last_free = (u64)p_t2_last_page->phys_addr + 876 ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent); 877 878 for (i = 0; i < p_t2->num_pages; i++) { 879 u32 ent_num = min_t(u32, 880 ent_per_page, 881 conn_num); 882 struct src_ent *entries = p_t2->dma_mem[i].virt_addr; 883 u64 p_ent_phys = (u64)p_t2->dma_mem[i].phys_addr, val; 884 u32 j; 885 886 for (j = 0; j < ent_num - 1; j++) { 887 val = p_ent_phys + (j + 1) * sizeof(struct src_ent); 888 entries[j].next = cpu_to_be64(val); 889 } 890 891 if (i < p_t2->num_pages - 1) 892 val = (u64)p_t2->dma_mem[i + 1].phys_addr; 893 else 894 val = 0; 895 entries[j].next = cpu_to_be64(val); 896 897 conn_num -= ent_num; 898 } 899 900 return 0; 901 902 t2_fail: 903 qed_cxt_src_t2_free(p_hwfn); 904 return rc; 905 } 906 907 #define for_each_ilt_valid_client(pos, clients) \ 908 for (pos = 0; pos < MAX_ILT_CLIENTS; pos++) \ 909 if (!clients[pos].active) { \ 910 continue; \ 911 } else \ 912 913 /* Total number of ILT lines used by this PF */ 914 static u32 qed_cxt_ilt_shadow_size(struct qed_ilt_client_cfg *ilt_clients) 915 { 916 u32 size = 0; 917 u32 i; 918 919 for_each_ilt_valid_client(i, ilt_clients) 920 size += (ilt_clients[i].last.val - ilt_clients[i].first.val + 1); 921 922 return size; 923 } 924 925 static void qed_ilt_shadow_free(struct qed_hwfn *p_hwfn) 926 { 927 struct qed_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients; 928 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 929 u32 ilt_size, i; 930 931 ilt_size = qed_cxt_ilt_shadow_size(p_cli); 932 933 for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) { 934 struct phys_mem_desc *p_dma = &p_mngr->ilt_shadow[i]; 935 936 if (p_dma->virt_addr) 937 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 938 p_dma->size, p_dma->virt_addr, 939 p_dma->phys_addr); 940 p_dma->virt_addr = NULL; 941 } 942 kfree(p_mngr->ilt_shadow); 943 } 944 945 static int qed_ilt_blk_alloc(struct qed_hwfn *p_hwfn, 946 struct qed_ilt_cli_blk *p_blk, 947 enum ilt_clients ilt_client, 948 u32 start_line_offset) 949 { 950 struct phys_mem_desc *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow; 951 u32 lines, line, sz_left, lines_to_skip = 0; 952 953 /* Special handling for RoCE that supports dynamic allocation */ 954 if (QED_IS_RDMA_PERSONALITY(p_hwfn) && 955 ((ilt_client == ILT_CLI_CDUT) || ilt_client == ILT_CLI_TSDM)) 956 return 0; 957 958 lines_to_skip = p_blk->dynamic_line_cnt; 959 960 if (!p_blk->total_size) 961 return 0; 962 963 sz_left = p_blk->total_size; 964 lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip; 965 line = p_blk->start_line + start_line_offset - 966 p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip; 967 968 for (; lines; lines--) { 969 dma_addr_t p_phys; 970 void *p_virt; 971 u32 size; 972 973 size = min_t(u32, sz_left, p_blk->real_size_in_page); 974 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, size, 975 &p_phys, GFP_KERNEL); 976 if (!p_virt) 977 return -ENOMEM; 978 979 ilt_shadow[line].phys_addr = p_phys; 980 ilt_shadow[line].virt_addr = p_virt; 981 ilt_shadow[line].size = size; 982 983 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 984 "ILT shadow: Line [%d] Physical 0x%llx Virtual %p Size %d\n", 985 line, (u64)p_phys, p_virt, size); 986 987 sz_left -= size; 988 line++; 989 } 990 991 return 0; 992 } 993 994 static int qed_ilt_shadow_alloc(struct qed_hwfn *p_hwfn) 995 { 996 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 997 struct qed_ilt_client_cfg *clients = p_mngr->clients; 998 struct qed_ilt_cli_blk *p_blk; 999 u32 size, i, j, k; 1000 int rc; 1001 1002 size = qed_cxt_ilt_shadow_size(clients); 1003 p_mngr->ilt_shadow = kcalloc(size, sizeof(struct phys_mem_desc), 1004 GFP_KERNEL); 1005 if (!p_mngr->ilt_shadow) { 1006 rc = -ENOMEM; 1007 goto ilt_shadow_fail; 1008 } 1009 1010 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 1011 "Allocated 0x%x bytes for ilt shadow\n", 1012 (u32)(size * sizeof(struct phys_mem_desc))); 1013 1014 for_each_ilt_valid_client(i, clients) { 1015 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) { 1016 p_blk = &clients[i].pf_blks[j]; 1017 rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, 0); 1018 if (rc) 1019 goto ilt_shadow_fail; 1020 } 1021 for (k = 0; k < p_mngr->vf_count; k++) { 1022 for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) { 1023 u32 lines = clients[i].vf_total_lines * k; 1024 1025 p_blk = &clients[i].vf_blks[j]; 1026 rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, lines); 1027 if (rc) 1028 goto ilt_shadow_fail; 1029 } 1030 } 1031 } 1032 1033 return 0; 1034 1035 ilt_shadow_fail: 1036 qed_ilt_shadow_free(p_hwfn); 1037 return rc; 1038 } 1039 1040 static void qed_cid_map_free(struct qed_hwfn *p_hwfn) 1041 { 1042 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1043 u32 type, vf; 1044 1045 for (type = 0; type < MAX_CONN_TYPES; type++) { 1046 kfree(p_mngr->acquired[type].cid_map); 1047 p_mngr->acquired[type].max_count = 0; 1048 p_mngr->acquired[type].start_cid = 0; 1049 1050 for (vf = 0; vf < MAX_NUM_VFS; vf++) { 1051 kfree(p_mngr->acquired_vf[type][vf].cid_map); 1052 p_mngr->acquired_vf[type][vf].max_count = 0; 1053 p_mngr->acquired_vf[type][vf].start_cid = 0; 1054 } 1055 } 1056 } 1057 1058 static int 1059 qed_cid_map_alloc_single(struct qed_hwfn *p_hwfn, 1060 u32 type, 1061 u32 cid_start, 1062 u32 cid_count, struct qed_cid_acquired_map *p_map) 1063 { 1064 u32 size; 1065 1066 if (!cid_count) 1067 return 0; 1068 1069 size = DIV_ROUND_UP(cid_count, 1070 sizeof(unsigned long) * BITS_PER_BYTE) * 1071 sizeof(unsigned long); 1072 p_map->cid_map = kzalloc(size, GFP_KERNEL); 1073 if (!p_map->cid_map) 1074 return -ENOMEM; 1075 1076 p_map->max_count = cid_count; 1077 p_map->start_cid = cid_start; 1078 1079 DP_VERBOSE(p_hwfn, QED_MSG_CXT, 1080 "Type %08x start: %08x count %08x\n", 1081 type, p_map->start_cid, p_map->max_count); 1082 1083 return 0; 1084 } 1085 1086 static int qed_cid_map_alloc(struct qed_hwfn *p_hwfn) 1087 { 1088 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1089 u32 start_cid = 0, vf_start_cid = 0; 1090 u32 type, vf; 1091 1092 for (type = 0; type < MAX_CONN_TYPES; type++) { 1093 struct qed_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[type]; 1094 struct qed_cid_acquired_map *p_map; 1095 1096 /* Handle PF maps */ 1097 p_map = &p_mngr->acquired[type]; 1098 if (qed_cid_map_alloc_single(p_hwfn, type, start_cid, 1099 p_cfg->cid_count, p_map)) 1100 goto cid_map_fail; 1101 1102 /* Handle VF maps */ 1103 for (vf = 0; vf < MAX_NUM_VFS; vf++) { 1104 p_map = &p_mngr->acquired_vf[type][vf]; 1105 if (qed_cid_map_alloc_single(p_hwfn, type, 1106 vf_start_cid, 1107 p_cfg->cids_per_vf, p_map)) 1108 goto cid_map_fail; 1109 } 1110 1111 start_cid += p_cfg->cid_count; 1112 vf_start_cid += p_cfg->cids_per_vf; 1113 } 1114 1115 return 0; 1116 1117 cid_map_fail: 1118 qed_cid_map_free(p_hwfn); 1119 return -ENOMEM; 1120 } 1121 1122 int qed_cxt_mngr_alloc(struct qed_hwfn *p_hwfn) 1123 { 1124 struct qed_ilt_client_cfg *clients; 1125 struct qed_cxt_mngr *p_mngr; 1126 u32 i; 1127 1128 p_mngr = kzalloc(sizeof(*p_mngr), GFP_KERNEL); 1129 if (!p_mngr) 1130 return -ENOMEM; 1131 1132 /* Initialize ILT client registers */ 1133 clients = p_mngr->clients; 1134 clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT); 1135 clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT); 1136 clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE); 1137 1138 clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT); 1139 clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT); 1140 clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE); 1141 1142 clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT); 1143 clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT); 1144 clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE); 1145 1146 clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT); 1147 clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT); 1148 clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE); 1149 1150 clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT); 1151 clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT); 1152 clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE); 1153 1154 clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT); 1155 clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT); 1156 clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE); 1157 /* default ILT page size for all clients is 64K */ 1158 for (i = 0; i < MAX_ILT_CLIENTS; i++) 1159 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE; 1160 1161 p_mngr->conn_ctx_size = CONN_CXT_SIZE(p_hwfn); 1162 1163 /* Initialize task sizes */ 1164 p_mngr->task_type_size[0] = TYPE0_TASK_CXT_SIZE(p_hwfn); 1165 p_mngr->task_type_size[1] = TYPE1_TASK_CXT_SIZE(p_hwfn); 1166 1167 if (p_hwfn->cdev->p_iov_info) { 1168 p_mngr->vf_count = p_hwfn->cdev->p_iov_info->total_vfs; 1169 p_mngr->first_vf_in_pf = 1170 p_hwfn->cdev->p_iov_info->first_vf_in_pf; 1171 } 1172 /* Initialize the dynamic ILT allocation mutex */ 1173 mutex_init(&p_mngr->mutex); 1174 1175 /* Set the cxt mangr pointer priori to further allocations */ 1176 p_hwfn->p_cxt_mngr = p_mngr; 1177 1178 return 0; 1179 } 1180 1181 int qed_cxt_tables_alloc(struct qed_hwfn *p_hwfn) 1182 { 1183 int rc; 1184 1185 /* Allocate the ILT shadow table */ 1186 rc = qed_ilt_shadow_alloc(p_hwfn); 1187 if (rc) 1188 goto tables_alloc_fail; 1189 1190 /* Allocate the T2 table */ 1191 rc = qed_cxt_src_t2_alloc(p_hwfn); 1192 if (rc) 1193 goto tables_alloc_fail; 1194 1195 /* Allocate and initialize the acquired cids bitmaps */ 1196 rc = qed_cid_map_alloc(p_hwfn); 1197 if (rc) 1198 goto tables_alloc_fail; 1199 1200 return 0; 1201 1202 tables_alloc_fail: 1203 qed_cxt_mngr_free(p_hwfn); 1204 return rc; 1205 } 1206 1207 void qed_cxt_mngr_free(struct qed_hwfn *p_hwfn) 1208 { 1209 if (!p_hwfn->p_cxt_mngr) 1210 return; 1211 1212 qed_cid_map_free(p_hwfn); 1213 qed_cxt_src_t2_free(p_hwfn); 1214 qed_ilt_shadow_free(p_hwfn); 1215 kfree(p_hwfn->p_cxt_mngr); 1216 1217 p_hwfn->p_cxt_mngr = NULL; 1218 } 1219 1220 void qed_cxt_mngr_setup(struct qed_hwfn *p_hwfn) 1221 { 1222 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1223 struct qed_cid_acquired_map *p_map; 1224 struct qed_conn_type_cfg *p_cfg; 1225 int type; 1226 u32 len; 1227 1228 /* Reset acquired cids */ 1229 for (type = 0; type < MAX_CONN_TYPES; type++) { 1230 u32 vf; 1231 1232 p_cfg = &p_mngr->conn_cfg[type]; 1233 if (p_cfg->cid_count) { 1234 p_map = &p_mngr->acquired[type]; 1235 len = DIV_ROUND_UP(p_map->max_count, 1236 sizeof(unsigned long) * 1237 BITS_PER_BYTE) * 1238 sizeof(unsigned long); 1239 memset(p_map->cid_map, 0, len); 1240 } 1241 1242 if (!p_cfg->cids_per_vf) 1243 continue; 1244 1245 for (vf = 0; vf < MAX_NUM_VFS; vf++) { 1246 p_map = &p_mngr->acquired_vf[type][vf]; 1247 len = DIV_ROUND_UP(p_map->max_count, 1248 sizeof(unsigned long) * 1249 BITS_PER_BYTE) * 1250 sizeof(unsigned long); 1251 memset(p_map->cid_map, 0, len); 1252 } 1253 } 1254 } 1255 1256 /* CDU Common */ 1257 #define CDUC_CXT_SIZE_SHIFT \ 1258 CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT 1259 1260 #define CDUC_CXT_SIZE_MASK \ 1261 (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT) 1262 1263 #define CDUC_BLOCK_WASTE_SHIFT \ 1264 CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT 1265 1266 #define CDUC_BLOCK_WASTE_MASK \ 1267 (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT) 1268 1269 #define CDUC_NCIB_SHIFT \ 1270 CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT 1271 1272 #define CDUC_NCIB_MASK \ 1273 (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT) 1274 1275 #define CDUT_TYPE0_CXT_SIZE_SHIFT \ 1276 CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT 1277 1278 #define CDUT_TYPE0_CXT_SIZE_MASK \ 1279 (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >> \ 1280 CDUT_TYPE0_CXT_SIZE_SHIFT) 1281 1282 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT \ 1283 CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT 1284 1285 #define CDUT_TYPE0_BLOCK_WASTE_MASK \ 1286 (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >> \ 1287 CDUT_TYPE0_BLOCK_WASTE_SHIFT) 1288 1289 #define CDUT_TYPE0_NCIB_SHIFT \ 1290 CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT 1291 1292 #define CDUT_TYPE0_NCIB_MASK \ 1293 (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >> \ 1294 CDUT_TYPE0_NCIB_SHIFT) 1295 1296 #define CDUT_TYPE1_CXT_SIZE_SHIFT \ 1297 CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT 1298 1299 #define CDUT_TYPE1_CXT_SIZE_MASK \ 1300 (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >> \ 1301 CDUT_TYPE1_CXT_SIZE_SHIFT) 1302 1303 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT \ 1304 CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT 1305 1306 #define CDUT_TYPE1_BLOCK_WASTE_MASK \ 1307 (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >> \ 1308 CDUT_TYPE1_BLOCK_WASTE_SHIFT) 1309 1310 #define CDUT_TYPE1_NCIB_SHIFT \ 1311 CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT 1312 1313 #define CDUT_TYPE1_NCIB_MASK \ 1314 (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >> \ 1315 CDUT_TYPE1_NCIB_SHIFT) 1316 1317 static void qed_cdu_init_common(struct qed_hwfn *p_hwfn) 1318 { 1319 u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0; 1320 1321 /* CDUC - connection configuration */ 1322 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val; 1323 cxt_size = CONN_CXT_SIZE(p_hwfn); 1324 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 1325 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size; 1326 1327 SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size); 1328 SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste); 1329 SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page); 1330 STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params); 1331 1332 /* CDUT - type-0 tasks configuration */ 1333 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val; 1334 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0]; 1335 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 1336 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size; 1337 1338 /* cxt size and block-waste are multipes of 8 */ 1339 cdu_params = 0; 1340 SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3)); 1341 SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3)); 1342 SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page); 1343 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params); 1344 1345 /* CDUT - type-1 tasks configuration */ 1346 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1]; 1347 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 1348 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size; 1349 1350 /* cxt size and block-waste are multipes of 8 */ 1351 cdu_params = 0; 1352 SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3)); 1353 SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3)); 1354 SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page); 1355 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params); 1356 } 1357 1358 /* CDU PF */ 1359 #define CDU_SEG_REG_TYPE_SHIFT CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT 1360 #define CDU_SEG_REG_TYPE_MASK 0x1 1361 #define CDU_SEG_REG_OFFSET_SHIFT 0 1362 #define CDU_SEG_REG_OFFSET_MASK CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK 1363 1364 static void qed_cdu_init_pf(struct qed_hwfn *p_hwfn) 1365 { 1366 struct qed_ilt_client_cfg *p_cli; 1367 struct qed_tid_seg *p_seg; 1368 u32 cdu_seg_params, offset; 1369 int i; 1370 1371 static const u32 rt_type_offset_arr[] = { 1372 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET, 1373 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET, 1374 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET, 1375 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 1376 }; 1377 1378 static const u32 rt_type_offset_fl_arr[] = { 1379 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET, 1380 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET, 1381 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET, 1382 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 1383 }; 1384 1385 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 1386 1387 /* There are initializations only for CDUT during pf Phase */ 1388 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 1389 /* Segment 0 */ 1390 p_seg = qed_cxt_tid_seg_info(p_hwfn, i); 1391 if (!p_seg) 1392 continue; 1393 1394 /* Note: start_line is already adjusted for the CDU 1395 * segment register granularity, so we just need to 1396 * divide. Adjustment is implicit as we assume ILT 1397 * Page size is larger than 32K! 1398 */ 1399 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) * 1400 (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line - 1401 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES; 1402 1403 cdu_seg_params = 0; 1404 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type); 1405 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset); 1406 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params); 1407 1408 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) * 1409 (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line - 1410 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES; 1411 1412 cdu_seg_params = 0; 1413 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type); 1414 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset); 1415 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params); 1416 } 1417 } 1418 1419 void qed_qm_init_pf(struct qed_hwfn *p_hwfn, 1420 struct qed_ptt *p_ptt, bool is_pf_loading) 1421 { 1422 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1423 struct qed_qm_pf_rt_init_params params; 1424 struct qed_qm_iids iids; 1425 1426 memset(&iids, 0, sizeof(iids)); 1427 qed_cxt_qm_iids(p_hwfn, &iids); 1428 1429 memset(¶ms, 0, sizeof(params)); 1430 params.port_id = p_hwfn->port_id; 1431 params.pf_id = p_hwfn->rel_pf_id; 1432 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port; 1433 params.is_pf_loading = is_pf_loading; 1434 params.num_pf_cids = iids.cids; 1435 params.num_vf_cids = iids.vf_cids; 1436 params.num_tids = iids.tids; 1437 params.start_pq = qm_info->start_pq; 1438 params.num_pf_pqs = qm_info->num_pqs - qm_info->num_vf_pqs; 1439 params.num_vf_pqs = qm_info->num_vf_pqs; 1440 params.start_vport = qm_info->start_vport; 1441 params.num_vports = qm_info->num_vports; 1442 params.pf_wfq = qm_info->pf_wfq; 1443 params.pf_rl = qm_info->pf_rl; 1444 params.pq_params = qm_info->qm_pq_params; 1445 params.vport_params = qm_info->qm_vport_params; 1446 1447 qed_qm_pf_rt_init(p_hwfn, p_ptt, ¶ms); 1448 } 1449 1450 /* CM PF */ 1451 static void qed_cm_init_pf(struct qed_hwfn *p_hwfn) 1452 { 1453 /* XCM pure-LB queue */ 1454 STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET, 1455 qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB)); 1456 } 1457 1458 /* DQ PF */ 1459 static void qed_dq_init_pf(struct qed_hwfn *p_hwfn) 1460 { 1461 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1462 u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0; 1463 1464 dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT); 1465 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid); 1466 1467 dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT); 1468 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid); 1469 1470 dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT); 1471 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid); 1472 1473 dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT); 1474 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid); 1475 1476 dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT); 1477 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid); 1478 1479 dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT); 1480 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid); 1481 1482 dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT); 1483 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid); 1484 1485 dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT); 1486 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid); 1487 1488 dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT); 1489 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid); 1490 1491 dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT); 1492 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid); 1493 1494 dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT); 1495 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid); 1496 1497 dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT); 1498 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid); 1499 1500 /* Connection types 6 & 7 are not in use, yet they must be configured 1501 * as the highest possible connection. Not configuring them means the 1502 * defaults will be used, and with a large number of cids a bug may 1503 * occur, if the defaults will be smaller than dq_pf_max_cid / 1504 * dq_vf_max_cid. 1505 */ 1506 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid); 1507 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid); 1508 1509 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid); 1510 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid); 1511 } 1512 1513 static void qed_ilt_bounds_init(struct qed_hwfn *p_hwfn) 1514 { 1515 struct qed_ilt_client_cfg *ilt_clients; 1516 int i; 1517 1518 ilt_clients = p_hwfn->p_cxt_mngr->clients; 1519 for_each_ilt_valid_client(i, ilt_clients) { 1520 STORE_RT_REG(p_hwfn, 1521 ilt_clients[i].first.reg, 1522 ilt_clients[i].first.val); 1523 STORE_RT_REG(p_hwfn, 1524 ilt_clients[i].last.reg, ilt_clients[i].last.val); 1525 STORE_RT_REG(p_hwfn, 1526 ilt_clients[i].p_size.reg, 1527 ilt_clients[i].p_size.val); 1528 } 1529 } 1530 1531 static void qed_ilt_vf_bounds_init(struct qed_hwfn *p_hwfn) 1532 { 1533 struct qed_ilt_client_cfg *p_cli; 1534 u32 blk_factor; 1535 1536 /* For simplicty we set the 'block' to be an ILT page */ 1537 if (p_hwfn->cdev->p_iov_info) { 1538 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info; 1539 1540 STORE_RT_REG(p_hwfn, 1541 PSWRQ2_REG_VF_BASE_RT_OFFSET, 1542 p_iov->first_vf_in_pf); 1543 STORE_RT_REG(p_hwfn, 1544 PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET, 1545 p_iov->first_vf_in_pf + p_iov->total_vfs); 1546 } 1547 1548 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 1549 blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10); 1550 if (p_cli->active) { 1551 STORE_RT_REG(p_hwfn, 1552 PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET, 1553 blk_factor); 1554 STORE_RT_REG(p_hwfn, 1555 PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET, 1556 p_cli->pf_total_lines); 1557 STORE_RT_REG(p_hwfn, 1558 PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET, 1559 p_cli->vf_total_lines); 1560 } 1561 1562 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 1563 blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10); 1564 if (p_cli->active) { 1565 STORE_RT_REG(p_hwfn, 1566 PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET, 1567 blk_factor); 1568 STORE_RT_REG(p_hwfn, 1569 PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET, 1570 p_cli->pf_total_lines); 1571 STORE_RT_REG(p_hwfn, 1572 PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET, 1573 p_cli->vf_total_lines); 1574 } 1575 1576 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM]; 1577 blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10); 1578 if (p_cli->active) { 1579 STORE_RT_REG(p_hwfn, 1580 PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor); 1581 STORE_RT_REG(p_hwfn, 1582 PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET, 1583 p_cli->pf_total_lines); 1584 STORE_RT_REG(p_hwfn, 1585 PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET, 1586 p_cli->vf_total_lines); 1587 } 1588 } 1589 1590 /* ILT (PSWRQ2) PF */ 1591 static void qed_ilt_init_pf(struct qed_hwfn *p_hwfn) 1592 { 1593 struct qed_ilt_client_cfg *clients; 1594 struct qed_cxt_mngr *p_mngr; 1595 struct phys_mem_desc *p_shdw; 1596 u32 line, rt_offst, i; 1597 1598 qed_ilt_bounds_init(p_hwfn); 1599 qed_ilt_vf_bounds_init(p_hwfn); 1600 1601 p_mngr = p_hwfn->p_cxt_mngr; 1602 p_shdw = p_mngr->ilt_shadow; 1603 clients = p_hwfn->p_cxt_mngr->clients; 1604 1605 for_each_ilt_valid_client(i, clients) { 1606 /** Client's 1st val and RT array are absolute, ILT shadows' 1607 * lines are relative. 1608 */ 1609 line = clients[i].first.val - p_mngr->pf_start_line; 1610 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET + 1611 clients[i].first.val * ILT_ENTRY_IN_REGS; 1612 1613 for (; line <= clients[i].last.val - p_mngr->pf_start_line; 1614 line++, rt_offst += ILT_ENTRY_IN_REGS) { 1615 u64 ilt_hw_entry = 0; 1616 1617 /** p_virt could be NULL incase of dynamic 1618 * allocation 1619 */ 1620 if (p_shdw[line].virt_addr) { 1621 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL); 1622 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR, 1623 (p_shdw[line].phys_addr >> 12)); 1624 1625 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 1626 "Setting RT[0x%08x] from ILT[0x%08x] [Client is %d] to Physical addr: 0x%llx\n", 1627 rt_offst, line, i, 1628 (u64)(p_shdw[line].phys_addr >> 12)); 1629 } 1630 1631 STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry); 1632 } 1633 } 1634 } 1635 1636 /* SRC (Searcher) PF */ 1637 static void qed_src_init_pf(struct qed_hwfn *p_hwfn) 1638 { 1639 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1640 u32 rounded_conn_num, conn_num, conn_max; 1641 struct qed_src_iids src_iids; 1642 1643 memset(&src_iids, 0, sizeof(src_iids)); 1644 qed_cxt_src_iids(p_mngr, &src_iids); 1645 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count; 1646 if (!conn_num) 1647 return; 1648 1649 conn_max = max_t(u32, conn_num, SRC_MIN_NUM_ELEMS); 1650 rounded_conn_num = roundup_pow_of_two(conn_max); 1651 1652 STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num); 1653 STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET, 1654 ilog2(rounded_conn_num)); 1655 1656 STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET, 1657 p_hwfn->p_cxt_mngr->first_free); 1658 STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET, 1659 p_hwfn->p_cxt_mngr->last_free); 1660 } 1661 1662 /* Timers PF */ 1663 #define TM_CFG_NUM_IDS_SHIFT 0 1664 #define TM_CFG_NUM_IDS_MASK 0xFFFFULL 1665 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT 16 1666 #define TM_CFG_PRE_SCAN_OFFSET_MASK 0x1FFULL 1667 #define TM_CFG_PARENT_PF_SHIFT 25 1668 #define TM_CFG_PARENT_PF_MASK 0x7ULL 1669 1670 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT 30 1671 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK 0x1FFULL 1672 1673 #define TM_CFG_TID_OFFSET_SHIFT 30 1674 #define TM_CFG_TID_OFFSET_MASK 0x7FFFFULL 1675 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT 49 1676 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK 0x1FFULL 1677 1678 static void qed_tm_init_pf(struct qed_hwfn *p_hwfn) 1679 { 1680 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1681 u32 active_seg_mask = 0, tm_offset, rt_reg; 1682 struct qed_tm_iids tm_iids; 1683 u64 cfg_word; 1684 u8 i; 1685 1686 memset(&tm_iids, 0, sizeof(tm_iids)); 1687 qed_cxt_tm_iids(p_hwfn, p_mngr, &tm_iids); 1688 1689 /* @@@TBD No pre-scan for now */ 1690 1691 /* Note: We assume consecutive VFs for a PF */ 1692 for (i = 0; i < p_mngr->vf_count; i++) { 1693 cfg_word = 0; 1694 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids); 1695 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1696 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id); 1697 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); 1698 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET + 1699 (sizeof(cfg_word) / sizeof(u32)) * 1700 (p_hwfn->cdev->p_iov_info->first_vf_in_pf + i); 1701 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1702 } 1703 1704 cfg_word = 0; 1705 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids); 1706 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1707 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); /* n/a for PF */ 1708 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */ 1709 1710 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET + 1711 (sizeof(cfg_word) / sizeof(u32)) * 1712 (NUM_OF_VFS(p_hwfn->cdev) + p_hwfn->rel_pf_id); 1713 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1714 1715 /* enale scan */ 1716 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET, 1717 tm_iids.pf_cids ? 0x1 : 0x0); 1718 1719 /* @@@TBD how to enable the scan for the VFs */ 1720 1721 tm_offset = tm_iids.per_vf_cids; 1722 1723 /* Note: We assume consecutive VFs for a PF */ 1724 for (i = 0; i < p_mngr->vf_count; i++) { 1725 cfg_word = 0; 1726 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids); 1727 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1728 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id); 1729 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset); 1730 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0); 1731 1732 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET + 1733 (sizeof(cfg_word) / sizeof(u32)) * 1734 (p_hwfn->cdev->p_iov_info->first_vf_in_pf + i); 1735 1736 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1737 } 1738 1739 tm_offset = tm_iids.pf_cids; 1740 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 1741 cfg_word = 0; 1742 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]); 1743 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1744 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); 1745 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset); 1746 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0); 1747 1748 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET + 1749 (sizeof(cfg_word) / sizeof(u32)) * 1750 (NUM_OF_VFS(p_hwfn->cdev) + 1751 p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i); 1752 1753 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1754 active_seg_mask |= (tm_iids.pf_tids[i] ? BIT(i) : 0); 1755 1756 tm_offset += tm_iids.pf_tids[i]; 1757 } 1758 1759 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) 1760 active_seg_mask = 0; 1761 1762 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask); 1763 1764 /* @@@TBD how to enable the scan for the VFs */ 1765 } 1766 1767 static void qed_prs_init_common(struct qed_hwfn *p_hwfn) 1768 { 1769 if ((p_hwfn->hw_info.personality == QED_PCI_FCOE) && 1770 p_hwfn->pf_params.fcoe_pf_params.is_target) 1771 STORE_RT_REG(p_hwfn, 1772 PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET, 0); 1773 } 1774 1775 static void qed_prs_init_pf(struct qed_hwfn *p_hwfn) 1776 { 1777 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1778 struct qed_conn_type_cfg *p_fcoe; 1779 struct qed_tid_seg *p_tid; 1780 1781 p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE]; 1782 1783 /* If FCoE is active set the MAX OX_ID (tid) in the Parser */ 1784 if (!p_fcoe->cid_count) 1785 return; 1786 1787 p_tid = &p_fcoe->tid_seg[QED_CXT_FCOE_TID_SEG]; 1788 if (p_hwfn->pf_params.fcoe_pf_params.is_target) { 1789 STORE_RT_REG_AGG(p_hwfn, 1790 PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET, 1791 p_tid->count); 1792 } else { 1793 STORE_RT_REG_AGG(p_hwfn, 1794 PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET, 1795 p_tid->count); 1796 } 1797 } 1798 1799 void qed_cxt_hw_init_common(struct qed_hwfn *p_hwfn) 1800 { 1801 qed_cdu_init_common(p_hwfn); 1802 qed_prs_init_common(p_hwfn); 1803 } 1804 1805 void qed_cxt_hw_init_pf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1806 { 1807 qed_qm_init_pf(p_hwfn, p_ptt, true); 1808 qed_cm_init_pf(p_hwfn); 1809 qed_dq_init_pf(p_hwfn); 1810 qed_cdu_init_pf(p_hwfn); 1811 qed_ilt_init_pf(p_hwfn); 1812 qed_src_init_pf(p_hwfn); 1813 qed_tm_init_pf(p_hwfn); 1814 qed_prs_init_pf(p_hwfn); 1815 } 1816 1817 int _qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn, 1818 enum protocol_type type, u32 *p_cid, u8 vfid) 1819 { 1820 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1821 struct qed_cid_acquired_map *p_map; 1822 u32 rel_cid; 1823 1824 if (type >= MAX_CONN_TYPES) { 1825 DP_NOTICE(p_hwfn, "Invalid protocol type %d", type); 1826 return -EINVAL; 1827 } 1828 1829 if (vfid >= MAX_NUM_VFS && vfid != QED_CXT_PF_CID) { 1830 DP_NOTICE(p_hwfn, "VF [%02x] is out of range\n", vfid); 1831 return -EINVAL; 1832 } 1833 1834 /* Determine the right map to take this CID from */ 1835 if (vfid == QED_CXT_PF_CID) 1836 p_map = &p_mngr->acquired[type]; 1837 else 1838 p_map = &p_mngr->acquired_vf[type][vfid]; 1839 1840 if (!p_map->cid_map) { 1841 DP_NOTICE(p_hwfn, "Invalid protocol type %d", type); 1842 return -EINVAL; 1843 } 1844 1845 rel_cid = find_first_zero_bit(p_map->cid_map, p_map->max_count); 1846 1847 if (rel_cid >= p_map->max_count) { 1848 DP_NOTICE(p_hwfn, "no CID available for protocol %d\n", type); 1849 return -EINVAL; 1850 } 1851 1852 __set_bit(rel_cid, p_map->cid_map); 1853 1854 *p_cid = rel_cid + p_map->start_cid; 1855 1856 DP_VERBOSE(p_hwfn, QED_MSG_CXT, 1857 "Acquired cid 0x%08x [rel. %08x] vfid %02x type %d\n", 1858 *p_cid, rel_cid, vfid, type); 1859 1860 return 0; 1861 } 1862 1863 int qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn, 1864 enum protocol_type type, u32 *p_cid) 1865 { 1866 return _qed_cxt_acquire_cid(p_hwfn, type, p_cid, QED_CXT_PF_CID); 1867 } 1868 1869 static bool qed_cxt_test_cid_acquired(struct qed_hwfn *p_hwfn, 1870 u32 cid, 1871 u8 vfid, 1872 enum protocol_type *p_type, 1873 struct qed_cid_acquired_map **pp_map) 1874 { 1875 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1876 u32 rel_cid; 1877 1878 /* Iterate over protocols and find matching cid range */ 1879 for (*p_type = 0; *p_type < MAX_CONN_TYPES; (*p_type)++) { 1880 if (vfid == QED_CXT_PF_CID) 1881 *pp_map = &p_mngr->acquired[*p_type]; 1882 else 1883 *pp_map = &p_mngr->acquired_vf[*p_type][vfid]; 1884 1885 if (!((*pp_map)->cid_map)) 1886 continue; 1887 if (cid >= (*pp_map)->start_cid && 1888 cid < (*pp_map)->start_cid + (*pp_map)->max_count) 1889 break; 1890 } 1891 1892 if (*p_type == MAX_CONN_TYPES) { 1893 DP_NOTICE(p_hwfn, "Invalid CID %d vfid %02x", cid, vfid); 1894 goto fail; 1895 } 1896 1897 rel_cid = cid - (*pp_map)->start_cid; 1898 if (!test_bit(rel_cid, (*pp_map)->cid_map)) { 1899 DP_NOTICE(p_hwfn, "CID %d [vifd %02x] not acquired", 1900 cid, vfid); 1901 goto fail; 1902 } 1903 1904 return true; 1905 fail: 1906 *p_type = MAX_CONN_TYPES; 1907 *pp_map = NULL; 1908 return false; 1909 } 1910 1911 void _qed_cxt_release_cid(struct qed_hwfn *p_hwfn, u32 cid, u8 vfid) 1912 { 1913 struct qed_cid_acquired_map *p_map = NULL; 1914 enum protocol_type type; 1915 bool b_acquired; 1916 u32 rel_cid; 1917 1918 if (vfid != QED_CXT_PF_CID && vfid > MAX_NUM_VFS) { 1919 DP_NOTICE(p_hwfn, 1920 "Trying to return incorrect CID belonging to VF %02x\n", 1921 vfid); 1922 return; 1923 } 1924 1925 /* Test acquired and find matching per-protocol map */ 1926 b_acquired = qed_cxt_test_cid_acquired(p_hwfn, cid, vfid, 1927 &type, &p_map); 1928 1929 if (!b_acquired) 1930 return; 1931 1932 rel_cid = cid - p_map->start_cid; 1933 clear_bit(rel_cid, p_map->cid_map); 1934 1935 DP_VERBOSE(p_hwfn, QED_MSG_CXT, 1936 "Released CID 0x%08x [rel. %08x] vfid %02x type %d\n", 1937 cid, rel_cid, vfid, type); 1938 } 1939 1940 void qed_cxt_release_cid(struct qed_hwfn *p_hwfn, u32 cid) 1941 { 1942 _qed_cxt_release_cid(p_hwfn, cid, QED_CXT_PF_CID); 1943 } 1944 1945 int qed_cxt_get_cid_info(struct qed_hwfn *p_hwfn, struct qed_cxt_info *p_info) 1946 { 1947 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1948 struct qed_cid_acquired_map *p_map = NULL; 1949 u32 conn_cxt_size, hw_p_size, cxts_per_p, line; 1950 enum protocol_type type; 1951 bool b_acquired; 1952 1953 /* Test acquired and find matching per-protocol map */ 1954 b_acquired = qed_cxt_test_cid_acquired(p_hwfn, p_info->iid, 1955 QED_CXT_PF_CID, &type, &p_map); 1956 1957 if (!b_acquired) 1958 return -EINVAL; 1959 1960 /* set the protocl type */ 1961 p_info->type = type; 1962 1963 /* compute context virtual pointer */ 1964 hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val; 1965 1966 conn_cxt_size = CONN_CXT_SIZE(p_hwfn); 1967 cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size; 1968 line = p_info->iid / cxts_per_p; 1969 1970 /* Make sure context is allocated (dynamic allocation) */ 1971 if (!p_mngr->ilt_shadow[line].virt_addr) 1972 return -EINVAL; 1973 1974 p_info->p_cxt = p_mngr->ilt_shadow[line].virt_addr + 1975 p_info->iid % cxts_per_p * conn_cxt_size; 1976 1977 DP_VERBOSE(p_hwfn, (QED_MSG_ILT | QED_MSG_CXT), 1978 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n", 1979 p_info->iid / cxts_per_p, p_info->p_cxt, p_info->iid); 1980 1981 return 0; 1982 } 1983 1984 static void qed_rdma_set_pf_params(struct qed_hwfn *p_hwfn, 1985 struct qed_rdma_pf_params *p_params, 1986 u32 num_tasks) 1987 { 1988 u32 num_cons, num_qps; 1989 enum protocol_type proto; 1990 1991 if (p_hwfn->mcp_info->func_info.protocol == QED_PCI_ETH_RDMA) { 1992 DP_NOTICE(p_hwfn, 1993 "Current day drivers don't support RoCE & iWARP simultaneously on the same PF. Default to RoCE-only\n"); 1994 p_hwfn->hw_info.personality = QED_PCI_ETH_ROCE; 1995 } 1996 1997 switch (p_hwfn->hw_info.personality) { 1998 case QED_PCI_ETH_IWARP: 1999 /* Each QP requires one connection */ 2000 num_cons = min_t(u32, IWARP_MAX_QPS, p_params->num_qps); 2001 proto = PROTOCOLID_IWARP; 2002 break; 2003 case QED_PCI_ETH_ROCE: 2004 num_qps = min_t(u32, ROCE_MAX_QPS, p_params->num_qps); 2005 num_cons = num_qps * 2; /* each QP requires two connections */ 2006 proto = PROTOCOLID_ROCE; 2007 break; 2008 default: 2009 return; 2010 } 2011 2012 if (num_cons && num_tasks) { 2013 u32 num_srqs, num_xrc_srqs; 2014 2015 qed_cxt_set_proto_cid_count(p_hwfn, proto, num_cons, 0); 2016 2017 /* Deliberatly passing ROCE for tasks id. This is because 2018 * iWARP / RoCE share the task id. 2019 */ 2020 qed_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_ROCE, 2021 QED_CXT_ROCE_TID_SEG, 1, 2022 num_tasks, false); 2023 2024 num_srqs = min_t(u32, QED_RDMA_MAX_SRQS, p_params->num_srqs); 2025 2026 /* XRC SRQs populate a single ILT page */ 2027 num_xrc_srqs = qed_cxt_xrc_srqs_per_page(p_hwfn); 2028 2029 qed_cxt_set_srq_count(p_hwfn, num_srqs, num_xrc_srqs); 2030 } else { 2031 DP_INFO(p_hwfn->cdev, 2032 "RDMA personality used without setting params!\n"); 2033 } 2034 } 2035 2036 int qed_cxt_set_pf_params(struct qed_hwfn *p_hwfn, u32 rdma_tasks) 2037 { 2038 /* Set the number of required CORE connections */ 2039 u32 core_cids = 1; /* SPQ */ 2040 2041 if (p_hwfn->using_ll2) 2042 core_cids += 4; 2043 qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0); 2044 2045 switch (p_hwfn->hw_info.personality) { 2046 case QED_PCI_ETH_RDMA: 2047 case QED_PCI_ETH_IWARP: 2048 case QED_PCI_ETH_ROCE: 2049 { 2050 qed_rdma_set_pf_params(p_hwfn, 2051 &p_hwfn-> 2052 pf_params.rdma_pf_params, 2053 rdma_tasks); 2054 /* no need for break since RoCE coexist with Ethernet */ 2055 } 2056 /* fall through */ 2057 case QED_PCI_ETH: 2058 { 2059 struct qed_eth_pf_params *p_params = 2060 &p_hwfn->pf_params.eth_pf_params; 2061 2062 if (!p_params->num_vf_cons) 2063 p_params->num_vf_cons = 2064 ETH_PF_PARAMS_VF_CONS_DEFAULT; 2065 qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH, 2066 p_params->num_cons, 2067 p_params->num_vf_cons); 2068 p_hwfn->p_cxt_mngr->arfs_count = p_params->num_arfs_filters; 2069 break; 2070 } 2071 case QED_PCI_FCOE: 2072 { 2073 struct qed_fcoe_pf_params *p_params; 2074 2075 p_params = &p_hwfn->pf_params.fcoe_pf_params; 2076 2077 if (p_params->num_cons && p_params->num_tasks) { 2078 qed_cxt_set_proto_cid_count(p_hwfn, 2079 PROTOCOLID_FCOE, 2080 p_params->num_cons, 2081 0); 2082 2083 qed_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_FCOE, 2084 QED_CXT_FCOE_TID_SEG, 0, 2085 p_params->num_tasks, true); 2086 } else { 2087 DP_INFO(p_hwfn->cdev, 2088 "Fcoe personality used without setting params!\n"); 2089 } 2090 break; 2091 } 2092 case QED_PCI_ISCSI: 2093 { 2094 struct qed_iscsi_pf_params *p_params; 2095 2096 p_params = &p_hwfn->pf_params.iscsi_pf_params; 2097 2098 if (p_params->num_cons && p_params->num_tasks) { 2099 qed_cxt_set_proto_cid_count(p_hwfn, 2100 PROTOCOLID_ISCSI, 2101 p_params->num_cons, 2102 0); 2103 2104 qed_cxt_set_proto_tid_count(p_hwfn, 2105 PROTOCOLID_ISCSI, 2106 QED_CXT_ISCSI_TID_SEG, 2107 0, 2108 p_params->num_tasks, 2109 true); 2110 } else { 2111 DP_INFO(p_hwfn->cdev, 2112 "Iscsi personality used without setting params!\n"); 2113 } 2114 break; 2115 } 2116 default: 2117 return -EINVAL; 2118 } 2119 2120 return 0; 2121 } 2122 2123 int qed_cxt_get_tid_mem_info(struct qed_hwfn *p_hwfn, 2124 struct qed_tid_mem *p_info) 2125 { 2126 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 2127 u32 proto, seg, total_lines, i, shadow_line; 2128 struct qed_ilt_client_cfg *p_cli; 2129 struct qed_ilt_cli_blk *p_fl_seg; 2130 struct qed_tid_seg *p_seg_info; 2131 2132 /* Verify the personality */ 2133 switch (p_hwfn->hw_info.personality) { 2134 case QED_PCI_FCOE: 2135 proto = PROTOCOLID_FCOE; 2136 seg = QED_CXT_FCOE_TID_SEG; 2137 break; 2138 case QED_PCI_ISCSI: 2139 proto = PROTOCOLID_ISCSI; 2140 seg = QED_CXT_ISCSI_TID_SEG; 2141 break; 2142 default: 2143 return -EINVAL; 2144 } 2145 2146 p_cli = &p_mngr->clients[ILT_CLI_CDUT]; 2147 if (!p_cli->active) 2148 return -EINVAL; 2149 2150 p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg]; 2151 if (!p_seg_info->has_fl_mem) 2152 return -EINVAL; 2153 2154 p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)]; 2155 total_lines = DIV_ROUND_UP(p_fl_seg->total_size, 2156 p_fl_seg->real_size_in_page); 2157 2158 for (i = 0; i < total_lines; i++) { 2159 shadow_line = i + p_fl_seg->start_line - 2160 p_hwfn->p_cxt_mngr->pf_start_line; 2161 p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].virt_addr; 2162 } 2163 p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) - 2164 p_fl_seg->real_size_in_page; 2165 p_info->tid_size = p_mngr->task_type_size[p_seg_info->type]; 2166 p_info->num_tids_per_block = p_fl_seg->real_size_in_page / 2167 p_info->tid_size; 2168 2169 return 0; 2170 } 2171 2172 /* This function is very RoCE oriented, if another protocol in the future 2173 * will want this feature we'll need to modify the function to be more generic 2174 */ 2175 int 2176 qed_cxt_dynamic_ilt_alloc(struct qed_hwfn *p_hwfn, 2177 enum qed_cxt_elem_type elem_type, u32 iid) 2178 { 2179 u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line; 2180 struct qed_ilt_client_cfg *p_cli; 2181 struct qed_ilt_cli_blk *p_blk; 2182 struct qed_ptt *p_ptt; 2183 dma_addr_t p_phys; 2184 u64 ilt_hw_entry; 2185 void *p_virt; 2186 int rc = 0; 2187 2188 switch (elem_type) { 2189 case QED_ELEM_CXT: 2190 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 2191 elem_size = CONN_CXT_SIZE(p_hwfn); 2192 p_blk = &p_cli->pf_blks[CDUC_BLK]; 2193 break; 2194 case QED_ELEM_SRQ: 2195 /* The first ILT page is not used for regular SRQs. Skip it. */ 2196 iid += p_hwfn->p_cxt_mngr->xrc_srq_count; 2197 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM]; 2198 elem_size = SRQ_CXT_SIZE; 2199 p_blk = &p_cli->pf_blks[SRQ_BLK]; 2200 break; 2201 case QED_ELEM_XRC_SRQ: 2202 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM]; 2203 elem_size = XRC_SRQ_CXT_SIZE; 2204 p_blk = &p_cli->pf_blks[SRQ_BLK]; 2205 break; 2206 case QED_ELEM_TASK: 2207 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2208 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn); 2209 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)]; 2210 break; 2211 default: 2212 DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type); 2213 return -EINVAL; 2214 } 2215 2216 /* Calculate line in ilt */ 2217 hw_p_size = p_cli->p_size.val; 2218 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size; 2219 line = p_blk->start_line + (iid / elems_per_p); 2220 shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line; 2221 2222 /* If line is already allocated, do nothing, otherwise allocate it and 2223 * write it to the PSWRQ2 registers. 2224 * This section can be run in parallel from different contexts and thus 2225 * a mutex protection is needed. 2226 */ 2227 2228 mutex_lock(&p_hwfn->p_cxt_mngr->mutex); 2229 2230 if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].virt_addr) 2231 goto out0; 2232 2233 p_ptt = qed_ptt_acquire(p_hwfn); 2234 if (!p_ptt) { 2235 DP_NOTICE(p_hwfn, 2236 "QED_TIME_OUT on ptt acquire - dynamic allocation"); 2237 rc = -EBUSY; 2238 goto out0; 2239 } 2240 2241 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 2242 p_blk->real_size_in_page, &p_phys, 2243 GFP_KERNEL); 2244 if (!p_virt) { 2245 rc = -ENOMEM; 2246 goto out1; 2247 } 2248 2249 /* configuration of refTagMask to 0xF is required for RoCE DIF MR only, 2250 * to compensate for a HW bug, but it is configured even if DIF is not 2251 * enabled. This is harmless and allows us to avoid a dedicated API. We 2252 * configure the field for all of the contexts on the newly allocated 2253 * page. 2254 */ 2255 if (elem_type == QED_ELEM_TASK) { 2256 u32 elem_i; 2257 u8 *elem_start = (u8 *)p_virt; 2258 union type1_task_context *elem; 2259 2260 for (elem_i = 0; elem_i < elems_per_p; elem_i++) { 2261 elem = (union type1_task_context *)elem_start; 2262 SET_FIELD(elem->roce_ctx.tdif_context.flags1, 2263 TDIF_TASK_CONTEXT_REF_TAG_MASK, 0xf); 2264 elem_start += TYPE1_TASK_CXT_SIZE(p_hwfn); 2265 } 2266 } 2267 2268 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].virt_addr = p_virt; 2269 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].phys_addr = p_phys; 2270 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size = 2271 p_blk->real_size_in_page; 2272 2273 /* compute absolute offset */ 2274 reg_offset = PSWRQ2_REG_ILT_MEMORY + 2275 (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS); 2276 2277 ilt_hw_entry = 0; 2278 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL); 2279 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR, 2280 (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].phys_addr 2281 >> 12)); 2282 2283 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */ 2284 qed_dmae_host2grc(p_hwfn, p_ptt, (u64) (uintptr_t)&ilt_hw_entry, 2285 reg_offset, sizeof(ilt_hw_entry) / sizeof(u32), 2286 NULL); 2287 2288 if (elem_type == QED_ELEM_CXT) { 2289 u32 last_cid_allocated = (1 + (iid / elems_per_p)) * 2290 elems_per_p; 2291 2292 /* Update the relevant register in the parser */ 2293 qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 2294 last_cid_allocated - 1); 2295 2296 if (!p_hwfn->b_rdma_enabled_in_prs) { 2297 /* Enable RDMA search */ 2298 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1); 2299 p_hwfn->b_rdma_enabled_in_prs = true; 2300 } 2301 } 2302 2303 out1: 2304 qed_ptt_release(p_hwfn, p_ptt); 2305 out0: 2306 mutex_unlock(&p_hwfn->p_cxt_mngr->mutex); 2307 2308 return rc; 2309 } 2310 2311 /* This function is very RoCE oriented, if another protocol in the future 2312 * will want this feature we'll need to modify the function to be more generic 2313 */ 2314 static int 2315 qed_cxt_free_ilt_range(struct qed_hwfn *p_hwfn, 2316 enum qed_cxt_elem_type elem_type, 2317 u32 start_iid, u32 count) 2318 { 2319 u32 start_line, end_line, shadow_start_line, shadow_end_line; 2320 u32 reg_offset, elem_size, hw_p_size, elems_per_p; 2321 struct qed_ilt_client_cfg *p_cli; 2322 struct qed_ilt_cli_blk *p_blk; 2323 u32 end_iid = start_iid + count; 2324 struct qed_ptt *p_ptt; 2325 u64 ilt_hw_entry = 0; 2326 u32 i; 2327 2328 switch (elem_type) { 2329 case QED_ELEM_CXT: 2330 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 2331 elem_size = CONN_CXT_SIZE(p_hwfn); 2332 p_blk = &p_cli->pf_blks[CDUC_BLK]; 2333 break; 2334 case QED_ELEM_SRQ: 2335 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM]; 2336 elem_size = SRQ_CXT_SIZE; 2337 p_blk = &p_cli->pf_blks[SRQ_BLK]; 2338 break; 2339 case QED_ELEM_TASK: 2340 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2341 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn); 2342 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)]; 2343 break; 2344 default: 2345 DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type); 2346 return -EINVAL; 2347 } 2348 2349 /* Calculate line in ilt */ 2350 hw_p_size = p_cli->p_size.val; 2351 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size; 2352 start_line = p_blk->start_line + (start_iid / elems_per_p); 2353 end_line = p_blk->start_line + (end_iid / elems_per_p); 2354 if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p)) 2355 end_line--; 2356 2357 shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line; 2358 shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line; 2359 2360 p_ptt = qed_ptt_acquire(p_hwfn); 2361 if (!p_ptt) { 2362 DP_NOTICE(p_hwfn, 2363 "QED_TIME_OUT on ptt acquire - dynamic allocation"); 2364 return -EBUSY; 2365 } 2366 2367 for (i = shadow_start_line; i < shadow_end_line; i++) { 2368 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].virt_addr) 2369 continue; 2370 2371 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 2372 p_hwfn->p_cxt_mngr->ilt_shadow[i].size, 2373 p_hwfn->p_cxt_mngr->ilt_shadow[i].virt_addr, 2374 p_hwfn->p_cxt_mngr->ilt_shadow[i].phys_addr); 2375 2376 p_hwfn->p_cxt_mngr->ilt_shadow[i].virt_addr = NULL; 2377 p_hwfn->p_cxt_mngr->ilt_shadow[i].phys_addr = 0; 2378 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0; 2379 2380 /* compute absolute offset */ 2381 reg_offset = PSWRQ2_REG_ILT_MEMORY + 2382 ((start_line++) * ILT_REG_SIZE_IN_BYTES * 2383 ILT_ENTRY_IN_REGS); 2384 2385 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a 2386 * wide-bus. 2387 */ 2388 qed_dmae_host2grc(p_hwfn, p_ptt, 2389 (u64) (uintptr_t) &ilt_hw_entry, 2390 reg_offset, 2391 sizeof(ilt_hw_entry) / sizeof(u32), 2392 NULL); 2393 } 2394 2395 qed_ptt_release(p_hwfn, p_ptt); 2396 2397 return 0; 2398 } 2399 2400 int qed_cxt_free_proto_ilt(struct qed_hwfn *p_hwfn, enum protocol_type proto) 2401 { 2402 int rc; 2403 u32 cid; 2404 2405 /* Free Connection CXT */ 2406 rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_CXT, 2407 qed_cxt_get_proto_cid_start(p_hwfn, 2408 proto), 2409 qed_cxt_get_proto_cid_count(p_hwfn, 2410 proto, &cid)); 2411 2412 if (rc) 2413 return rc; 2414 2415 /* Free Task CXT ( Intentionally RoCE as task-id is shared between 2416 * RoCE and iWARP ) 2417 */ 2418 proto = PROTOCOLID_ROCE; 2419 rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_TASK, 0, 2420 qed_cxt_get_proto_tid_count(p_hwfn, proto)); 2421 if (rc) 2422 return rc; 2423 2424 /* Free TSDM CXT */ 2425 rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_XRC_SRQ, 0, 2426 p_hwfn->p_cxt_mngr->xrc_srq_count); 2427 2428 rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_SRQ, 2429 p_hwfn->p_cxt_mngr->xrc_srq_count, 2430 p_hwfn->p_cxt_mngr->srq_count); 2431 2432 return rc; 2433 } 2434 2435 int qed_cxt_get_task_ctx(struct qed_hwfn *p_hwfn, 2436 u32 tid, u8 ctx_type, void **pp_task_ctx) 2437 { 2438 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 2439 struct qed_ilt_client_cfg *p_cli; 2440 struct qed_tid_seg *p_seg_info; 2441 struct qed_ilt_cli_blk *p_seg; 2442 u32 num_tids_per_block; 2443 u32 tid_size, ilt_idx; 2444 u32 total_lines; 2445 u32 proto, seg; 2446 2447 /* Verify the personality */ 2448 switch (p_hwfn->hw_info.personality) { 2449 case QED_PCI_FCOE: 2450 proto = PROTOCOLID_FCOE; 2451 seg = QED_CXT_FCOE_TID_SEG; 2452 break; 2453 case QED_PCI_ISCSI: 2454 proto = PROTOCOLID_ISCSI; 2455 seg = QED_CXT_ISCSI_TID_SEG; 2456 break; 2457 default: 2458 return -EINVAL; 2459 } 2460 2461 p_cli = &p_mngr->clients[ILT_CLI_CDUT]; 2462 if (!p_cli->active) 2463 return -EINVAL; 2464 2465 p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg]; 2466 2467 if (ctx_type == QED_CTX_WORKING_MEM) { 2468 p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)]; 2469 } else if (ctx_type == QED_CTX_FL_MEM) { 2470 if (!p_seg_info->has_fl_mem) 2471 return -EINVAL; 2472 p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)]; 2473 } else { 2474 return -EINVAL; 2475 } 2476 total_lines = DIV_ROUND_UP(p_seg->total_size, p_seg->real_size_in_page); 2477 tid_size = p_mngr->task_type_size[p_seg_info->type]; 2478 num_tids_per_block = p_seg->real_size_in_page / tid_size; 2479 2480 if (total_lines < tid / num_tids_per_block) 2481 return -EINVAL; 2482 2483 ilt_idx = tid / num_tids_per_block + p_seg->start_line - 2484 p_mngr->pf_start_line; 2485 *pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].virt_addr + 2486 (tid % num_tids_per_block) * tid_size; 2487 2488 return 0; 2489 } 2490 2491 static u16 qed_blk_calculate_pages(struct qed_ilt_cli_blk *p_blk) 2492 { 2493 if (p_blk->real_size_in_page == 0) 2494 return 0; 2495 2496 return DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page); 2497 } 2498 2499 u16 qed_get_cdut_num_pf_init_pages(struct qed_hwfn *p_hwfn) 2500 { 2501 struct qed_ilt_client_cfg *p_cli; 2502 struct qed_ilt_cli_blk *p_blk; 2503 u16 i, pages = 0; 2504 2505 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2506 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 2507 p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)]; 2508 pages += qed_blk_calculate_pages(p_blk); 2509 } 2510 2511 return pages; 2512 } 2513 2514 u16 qed_get_cdut_num_vf_init_pages(struct qed_hwfn *p_hwfn) 2515 { 2516 struct qed_ilt_client_cfg *p_cli; 2517 struct qed_ilt_cli_blk *p_blk; 2518 u16 i, pages = 0; 2519 2520 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2521 for (i = 0; i < NUM_TASK_VF_SEGMENTS; i++) { 2522 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(i, VF)]; 2523 pages += qed_blk_calculate_pages(p_blk); 2524 } 2525 2526 return pages; 2527 } 2528 2529 u16 qed_get_cdut_num_pf_work_pages(struct qed_hwfn *p_hwfn) 2530 { 2531 struct qed_ilt_client_cfg *p_cli; 2532 struct qed_ilt_cli_blk *p_blk; 2533 u16 i, pages = 0; 2534 2535 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2536 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 2537 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)]; 2538 pages += qed_blk_calculate_pages(p_blk); 2539 } 2540 2541 return pages; 2542 } 2543 2544 u16 qed_get_cdut_num_vf_work_pages(struct qed_hwfn *p_hwfn) 2545 { 2546 struct qed_ilt_client_cfg *p_cli; 2547 struct qed_ilt_cli_blk *p_blk; 2548 u16 pages = 0, i; 2549 2550 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2551 for (i = 0; i < NUM_TASK_VF_SEGMENTS; i++) { 2552 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(i)]; 2553 pages += qed_blk_calculate_pages(p_blk); 2554 } 2555 2556 return pages; 2557 } 2558