1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) 2 /* QLogic qed NIC Driver 3 * Copyright (c) 2015-2017 QLogic Corporation 4 */ 5 6 #include <linux/types.h> 7 #include <linux/bitops.h> 8 #include <linux/dma-mapping.h> 9 #include <linux/errno.h> 10 #include <linux/kernel.h> 11 #include <linux/list.h> 12 #include <linux/log2.h> 13 #include <linux/pci.h> 14 #include <linux/slab.h> 15 #include <linux/string.h> 16 #include "qed.h" 17 #include "qed_cxt.h" 18 #include "qed_dev_api.h" 19 #include "qed_hsi.h" 20 #include "qed_hw.h" 21 #include "qed_init_ops.h" 22 #include "qed_rdma.h" 23 #include "qed_reg_addr.h" 24 #include "qed_sriov.h" 25 26 /* QM constants */ 27 #define QM_PQ_ELEMENT_SIZE 4 /* in bytes */ 28 29 /* Doorbell-Queue constants */ 30 #define DQ_RANGE_SHIFT 4 31 #define DQ_RANGE_ALIGN BIT(DQ_RANGE_SHIFT) 32 33 /* Searcher constants */ 34 #define SRC_MIN_NUM_ELEMS 256 35 36 /* Timers constants */ 37 #define TM_SHIFT 7 38 #define TM_ALIGN BIT(TM_SHIFT) 39 #define TM_ELEM_SIZE 4 40 41 #define ILT_DEFAULT_HW_P_SIZE 4 42 43 #define ILT_PAGE_IN_BYTES(hw_p_size) (1U << ((hw_p_size) + 12)) 44 #define ILT_CFG_REG(cli, reg) PSWRQ2_REG_ ## cli ## _ ## reg ## _RT_OFFSET 45 46 /* ILT entry structure */ 47 #define ILT_ENTRY_PHY_ADDR_MASK (~0ULL >> 12) 48 #define ILT_ENTRY_PHY_ADDR_SHIFT 0 49 #define ILT_ENTRY_VALID_MASK 0x1ULL 50 #define ILT_ENTRY_VALID_SHIFT 52 51 #define ILT_ENTRY_IN_REGS 2 52 #define ILT_REG_SIZE_IN_BYTES 4 53 54 /* connection context union */ 55 union conn_context { 56 struct e4_core_conn_context core_ctx; 57 struct e4_eth_conn_context eth_ctx; 58 struct e4_iscsi_conn_context iscsi_ctx; 59 struct e4_fcoe_conn_context fcoe_ctx; 60 struct e4_roce_conn_context roce_ctx; 61 }; 62 63 /* TYPE-0 task context - iSCSI, FCOE */ 64 union type0_task_context { 65 struct e4_iscsi_task_context iscsi_ctx; 66 struct e4_fcoe_task_context fcoe_ctx; 67 }; 68 69 /* TYPE-1 task context - ROCE */ 70 union type1_task_context { 71 struct e4_rdma_task_context roce_ctx; 72 }; 73 74 struct src_ent { 75 u8 opaque[56]; 76 u64 next; 77 }; 78 79 #define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */ 80 #define CDUT_SEG_ALIGNMET_IN_BYTES BIT(CDUT_SEG_ALIGNMET + 12) 81 82 #define CONN_CXT_SIZE(p_hwfn) \ 83 ALIGNED_TYPE_SIZE(union conn_context, p_hwfn) 84 85 #define SRQ_CXT_SIZE (sizeof(struct rdma_srq_context)) 86 #define XRC_SRQ_CXT_SIZE (sizeof(struct rdma_xrc_srq_context)) 87 88 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \ 89 ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn) 90 91 /* Alignment is inherent to the type1_task_context structure */ 92 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context) 93 94 static bool src_proto(enum protocol_type type) 95 { 96 return type == PROTOCOLID_ISCSI || 97 type == PROTOCOLID_FCOE || 98 type == PROTOCOLID_IWARP; 99 } 100 101 static bool tm_cid_proto(enum protocol_type type) 102 { 103 return type == PROTOCOLID_ISCSI || 104 type == PROTOCOLID_FCOE || 105 type == PROTOCOLID_ROCE || 106 type == PROTOCOLID_IWARP; 107 } 108 109 static bool tm_tid_proto(enum protocol_type type) 110 { 111 return type == PROTOCOLID_FCOE; 112 } 113 114 /* counts the iids for the CDU/CDUC ILT client configuration */ 115 struct qed_cdu_iids { 116 u32 pf_cids; 117 u32 per_vf_cids; 118 }; 119 120 static void qed_cxt_cdu_iids(struct qed_cxt_mngr *p_mngr, 121 struct qed_cdu_iids *iids) 122 { 123 u32 type; 124 125 for (type = 0; type < MAX_CONN_TYPES; type++) { 126 iids->pf_cids += p_mngr->conn_cfg[type].cid_count; 127 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf; 128 } 129 } 130 131 /* counts the iids for the Searcher block configuration */ 132 struct qed_src_iids { 133 u32 pf_cids; 134 u32 per_vf_cids; 135 }; 136 137 static void qed_cxt_src_iids(struct qed_cxt_mngr *p_mngr, 138 struct qed_src_iids *iids) 139 { 140 u32 i; 141 142 for (i = 0; i < MAX_CONN_TYPES; i++) { 143 if (!src_proto(i)) 144 continue; 145 146 iids->pf_cids += p_mngr->conn_cfg[i].cid_count; 147 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf; 148 } 149 150 /* Add L2 filtering filters in addition */ 151 iids->pf_cids += p_mngr->arfs_count; 152 } 153 154 /* counts the iids for the Timers block configuration */ 155 struct qed_tm_iids { 156 u32 pf_cids; 157 u32 pf_tids[NUM_TASK_PF_SEGMENTS]; /* per segment */ 158 u32 pf_tids_total; 159 u32 per_vf_cids; 160 u32 per_vf_tids; 161 }; 162 163 static void qed_cxt_tm_iids(struct qed_hwfn *p_hwfn, 164 struct qed_cxt_mngr *p_mngr, 165 struct qed_tm_iids *iids) 166 { 167 bool tm_vf_required = false; 168 bool tm_required = false; 169 int i, j; 170 171 /* Timers is a special case -> we don't count how many cids require 172 * timers but what's the max cid that will be used by the timer block. 173 * therefore we traverse in reverse order, and once we hit a protocol 174 * that requires the timers memory, we'll sum all the protocols up 175 * to that one. 176 */ 177 for (i = MAX_CONN_TYPES - 1; i >= 0; i--) { 178 struct qed_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i]; 179 180 if (tm_cid_proto(i) || tm_required) { 181 if (p_cfg->cid_count) 182 tm_required = true; 183 184 iids->pf_cids += p_cfg->cid_count; 185 } 186 187 if (tm_cid_proto(i) || tm_vf_required) { 188 if (p_cfg->cids_per_vf) 189 tm_vf_required = true; 190 191 iids->per_vf_cids += p_cfg->cids_per_vf; 192 } 193 194 if (tm_tid_proto(i)) { 195 struct qed_tid_seg *segs = p_cfg->tid_seg; 196 197 /* for each segment there is at most one 198 * protocol for which count is not 0. 199 */ 200 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++) 201 iids->pf_tids[j] += segs[j].count; 202 203 /* The last array elelment is for the VFs. As for PF 204 * segments there can be only one protocol for 205 * which this value is not 0. 206 */ 207 iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count; 208 } 209 } 210 211 iids->pf_cids = roundup(iids->pf_cids, TM_ALIGN); 212 iids->per_vf_cids = roundup(iids->per_vf_cids, TM_ALIGN); 213 iids->per_vf_tids = roundup(iids->per_vf_tids, TM_ALIGN); 214 215 for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) { 216 iids->pf_tids[j] = roundup(iids->pf_tids[j], TM_ALIGN); 217 iids->pf_tids_total += iids->pf_tids[j]; 218 } 219 } 220 221 static void qed_cxt_qm_iids(struct qed_hwfn *p_hwfn, 222 struct qed_qm_iids *iids) 223 { 224 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 225 struct qed_tid_seg *segs; 226 u32 vf_cids = 0, type, j; 227 u32 vf_tids = 0; 228 229 for (type = 0; type < MAX_CONN_TYPES; type++) { 230 iids->cids += p_mngr->conn_cfg[type].cid_count; 231 vf_cids += p_mngr->conn_cfg[type].cids_per_vf; 232 233 segs = p_mngr->conn_cfg[type].tid_seg; 234 /* for each segment there is at most one 235 * protocol for which count is not 0. 236 */ 237 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++) 238 iids->tids += segs[j].count; 239 240 /* The last array elelment is for the VFs. As for PF 241 * segments there can be only one protocol for 242 * which this value is not 0. 243 */ 244 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count; 245 } 246 247 iids->vf_cids = vf_cids; 248 iids->tids += vf_tids * p_mngr->vf_count; 249 250 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 251 "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n", 252 iids->cids, iids->vf_cids, iids->tids, vf_tids); 253 } 254 255 static struct qed_tid_seg *qed_cxt_tid_seg_info(struct qed_hwfn *p_hwfn, 256 u32 seg) 257 { 258 struct qed_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr; 259 u32 i; 260 261 /* Find the protocol with tid count > 0 for this segment. 262 * Note: there can only be one and this is already validated. 263 */ 264 for (i = 0; i < MAX_CONN_TYPES; i++) 265 if (p_cfg->conn_cfg[i].tid_seg[seg].count) 266 return &p_cfg->conn_cfg[i].tid_seg[seg]; 267 return NULL; 268 } 269 270 static void qed_cxt_set_srq_count(struct qed_hwfn *p_hwfn, 271 u32 num_srqs, u32 num_xrc_srqs) 272 { 273 struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; 274 275 p_mgr->srq_count = num_srqs; 276 p_mgr->xrc_srq_count = num_xrc_srqs; 277 } 278 279 u32 qed_cxt_get_ilt_page_size(struct qed_hwfn *p_hwfn, 280 enum ilt_clients ilt_client) 281 { 282 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 283 struct qed_ilt_client_cfg *p_cli = &p_mngr->clients[ilt_client]; 284 285 return ILT_PAGE_IN_BYTES(p_cli->p_size.val); 286 } 287 288 static u32 qed_cxt_xrc_srqs_per_page(struct qed_hwfn *p_hwfn) 289 { 290 u32 page_size; 291 292 page_size = qed_cxt_get_ilt_page_size(p_hwfn, ILT_CLI_TSDM); 293 return page_size / XRC_SRQ_CXT_SIZE; 294 } 295 296 u32 qed_cxt_get_total_srq_count(struct qed_hwfn *p_hwfn) 297 { 298 struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; 299 u32 total_srqs; 300 301 total_srqs = p_mgr->srq_count + p_mgr->xrc_srq_count; 302 303 return total_srqs; 304 } 305 306 /* set the iids count per protocol */ 307 static void qed_cxt_set_proto_cid_count(struct qed_hwfn *p_hwfn, 308 enum protocol_type type, 309 u32 cid_count, u32 vf_cid_cnt) 310 { 311 struct qed_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr; 312 struct qed_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type]; 313 314 p_conn->cid_count = roundup(cid_count, DQ_RANGE_ALIGN); 315 p_conn->cids_per_vf = roundup(vf_cid_cnt, DQ_RANGE_ALIGN); 316 317 if (type == PROTOCOLID_ROCE) { 318 u32 page_sz = p_mgr->clients[ILT_CLI_CDUC].p_size.val; 319 u32 cxt_size = CONN_CXT_SIZE(p_hwfn); 320 u32 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 321 u32 align = elems_per_page * DQ_RANGE_ALIGN; 322 323 p_conn->cid_count = roundup(p_conn->cid_count, align); 324 } 325 } 326 327 u32 qed_cxt_get_proto_cid_count(struct qed_hwfn *p_hwfn, 328 enum protocol_type type, u32 *vf_cid) 329 { 330 if (vf_cid) 331 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf; 332 333 return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count; 334 } 335 336 u32 qed_cxt_get_proto_cid_start(struct qed_hwfn *p_hwfn, 337 enum protocol_type type) 338 { 339 return p_hwfn->p_cxt_mngr->acquired[type].start_cid; 340 } 341 342 u32 qed_cxt_get_proto_tid_count(struct qed_hwfn *p_hwfn, 343 enum protocol_type type) 344 { 345 u32 cnt = 0; 346 int i; 347 348 for (i = 0; i < TASK_SEGMENTS; i++) 349 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count; 350 351 return cnt; 352 } 353 354 static void qed_cxt_set_proto_tid_count(struct qed_hwfn *p_hwfn, 355 enum protocol_type proto, 356 u8 seg, 357 u8 seg_type, u32 count, bool has_fl) 358 { 359 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 360 struct qed_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg]; 361 362 p_seg->count = count; 363 p_seg->has_fl_mem = has_fl; 364 p_seg->type = seg_type; 365 } 366 367 static void qed_ilt_cli_blk_fill(struct qed_ilt_client_cfg *p_cli, 368 struct qed_ilt_cli_blk *p_blk, 369 u32 start_line, u32 total_size, u32 elem_size) 370 { 371 u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val); 372 373 /* verify thatits called only once for each block */ 374 if (p_blk->total_size) 375 return; 376 377 p_blk->total_size = total_size; 378 p_blk->real_size_in_page = 0; 379 if (elem_size) 380 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size; 381 p_blk->start_line = start_line; 382 } 383 384 static void qed_ilt_cli_adv_line(struct qed_hwfn *p_hwfn, 385 struct qed_ilt_client_cfg *p_cli, 386 struct qed_ilt_cli_blk *p_blk, 387 u32 *p_line, enum ilt_clients client_id) 388 { 389 if (!p_blk->total_size) 390 return; 391 392 if (!p_cli->active) 393 p_cli->first.val = *p_line; 394 395 p_cli->active = true; 396 *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page); 397 p_cli->last.val = *p_line - 1; 398 399 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 400 "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x [Real %08x] Start line %d\n", 401 client_id, p_cli->first.val, 402 p_cli->last.val, p_blk->total_size, 403 p_blk->real_size_in_page, p_blk->start_line); 404 } 405 406 static u32 qed_ilt_get_dynamic_line_cnt(struct qed_hwfn *p_hwfn, 407 enum ilt_clients ilt_client) 408 { 409 u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count; 410 struct qed_ilt_client_cfg *p_cli; 411 u32 lines_to_skip = 0; 412 u32 cxts_per_p; 413 414 if (ilt_client == ILT_CLI_CDUC) { 415 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 416 417 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) / 418 (u32) CONN_CXT_SIZE(p_hwfn); 419 420 lines_to_skip = cid_count / cxts_per_p; 421 } 422 423 return lines_to_skip; 424 } 425 426 static struct qed_ilt_client_cfg *qed_cxt_set_cli(struct qed_ilt_client_cfg 427 *p_cli) 428 { 429 p_cli->active = false; 430 p_cli->first.val = 0; 431 p_cli->last.val = 0; 432 return p_cli; 433 } 434 435 static struct qed_ilt_cli_blk *qed_cxt_set_blk(struct qed_ilt_cli_blk *p_blk) 436 { 437 p_blk->total_size = 0; 438 return p_blk; 439 } 440 441 static void qed_cxt_ilt_blk_reset(struct qed_hwfn *p_hwfn) 442 { 443 struct qed_ilt_client_cfg *clients = p_hwfn->p_cxt_mngr->clients; 444 u32 cli_idx, blk_idx; 445 446 for (cli_idx = 0; cli_idx < MAX_ILT_CLIENTS; cli_idx++) { 447 for (blk_idx = 0; blk_idx < ILT_CLI_PF_BLOCKS; blk_idx++) 448 clients[cli_idx].pf_blks[blk_idx].total_size = 0; 449 450 for (blk_idx = 0; blk_idx < ILT_CLI_VF_BLOCKS; blk_idx++) 451 clients[cli_idx].vf_blks[blk_idx].total_size = 0; 452 } 453 } 454 455 int qed_cxt_cfg_ilt_compute(struct qed_hwfn *p_hwfn, u32 *line_count) 456 { 457 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 458 u32 curr_line, total, i, task_size, line; 459 struct qed_ilt_client_cfg *p_cli; 460 struct qed_ilt_cli_blk *p_blk; 461 struct qed_cdu_iids cdu_iids; 462 struct qed_src_iids src_iids; 463 struct qed_qm_iids qm_iids; 464 struct qed_tm_iids tm_iids; 465 struct qed_tid_seg *p_seg; 466 467 memset(&qm_iids, 0, sizeof(qm_iids)); 468 memset(&cdu_iids, 0, sizeof(cdu_iids)); 469 memset(&src_iids, 0, sizeof(src_iids)); 470 memset(&tm_iids, 0, sizeof(tm_iids)); 471 472 p_mngr->pf_start_line = RESC_START(p_hwfn, QED_ILT); 473 474 /* Reset all ILT blocks at the beginning of ILT computing in order 475 * to prevent memory allocation for irrelevant blocks afterwards. 476 */ 477 qed_cxt_ilt_blk_reset(p_hwfn); 478 479 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 480 "hwfn [%d] - Set context manager starting line to be 0x%08x\n", 481 p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line); 482 483 /* CDUC */ 484 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_CDUC]); 485 486 curr_line = p_mngr->pf_start_line; 487 488 /* CDUC PF */ 489 p_cli->pf_total_lines = 0; 490 491 /* get the counters for the CDUC and QM clients */ 492 qed_cxt_cdu_iids(p_mngr, &cdu_iids); 493 494 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[CDUC_BLK]); 495 496 total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn); 497 498 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 499 total, CONN_CXT_SIZE(p_hwfn)); 500 501 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC); 502 p_cli->pf_total_lines = curr_line - p_blk->start_line; 503 504 p_blk->dynamic_line_cnt = qed_ilt_get_dynamic_line_cnt(p_hwfn, 505 ILT_CLI_CDUC); 506 507 /* CDUC VF */ 508 p_blk = qed_cxt_set_blk(&p_cli->vf_blks[CDUC_BLK]); 509 total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn); 510 511 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 512 total, CONN_CXT_SIZE(p_hwfn)); 513 514 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC); 515 p_cli->vf_total_lines = curr_line - p_blk->start_line; 516 517 for (i = 1; i < p_mngr->vf_count; i++) 518 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 519 ILT_CLI_CDUC); 520 521 /* CDUT PF */ 522 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_CDUT]); 523 p_cli->first.val = curr_line; 524 525 /* first the 'working' task memory */ 526 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 527 p_seg = qed_cxt_tid_seg_info(p_hwfn, i); 528 if (!p_seg || p_seg->count == 0) 529 continue; 530 531 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[CDUT_SEG_BLK(i)]); 532 total = p_seg->count * p_mngr->task_type_size[p_seg->type]; 533 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total, 534 p_mngr->task_type_size[p_seg->type]); 535 536 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 537 ILT_CLI_CDUT); 538 } 539 540 /* next the 'init' task memory (forced load memory) */ 541 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 542 p_seg = qed_cxt_tid_seg_info(p_hwfn, i); 543 if (!p_seg || p_seg->count == 0) 544 continue; 545 546 p_blk = 547 qed_cxt_set_blk(&p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)]); 548 549 if (!p_seg->has_fl_mem) { 550 /* The segment is active (total size pf 'working' 551 * memory is > 0) but has no FL (forced-load, Init) 552 * memory. Thus: 553 * 554 * 1. The total-size in the corrsponding FL block of 555 * the ILT client is set to 0 - No ILT line are 556 * provisioned and no ILT memory allocated. 557 * 558 * 2. The start-line of said block is set to the 559 * start line of the matching working memory 560 * block in the ILT client. This is later used to 561 * configure the CDU segment offset registers and 562 * results in an FL command for TIDs of this 563 * segement behaves as regular load commands 564 * (loading TIDs from the working memory). 565 */ 566 line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line; 567 568 qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0); 569 continue; 570 } 571 total = p_seg->count * p_mngr->task_type_size[p_seg->type]; 572 573 qed_ilt_cli_blk_fill(p_cli, p_blk, 574 curr_line, total, 575 p_mngr->task_type_size[p_seg->type]); 576 577 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 578 ILT_CLI_CDUT); 579 } 580 p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line; 581 582 /* CDUT VF */ 583 p_seg = qed_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF); 584 if (p_seg && p_seg->count) { 585 /* Stricly speaking we need to iterate over all VF 586 * task segment types, but a VF has only 1 segment 587 */ 588 589 /* 'working' memory */ 590 total = p_seg->count * p_mngr->task_type_size[p_seg->type]; 591 592 p_blk = qed_cxt_set_blk(&p_cli->vf_blks[CDUT_SEG_BLK(0)]); 593 qed_ilt_cli_blk_fill(p_cli, p_blk, 594 curr_line, total, 595 p_mngr->task_type_size[p_seg->type]); 596 597 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 598 ILT_CLI_CDUT); 599 600 /* 'init' memory */ 601 p_blk = 602 qed_cxt_set_blk(&p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)]); 603 if (!p_seg->has_fl_mem) { 604 /* see comment above */ 605 line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line; 606 qed_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0); 607 } else { 608 task_size = p_mngr->task_type_size[p_seg->type]; 609 qed_ilt_cli_blk_fill(p_cli, p_blk, 610 curr_line, total, task_size); 611 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 612 ILT_CLI_CDUT); 613 } 614 p_cli->vf_total_lines = curr_line - 615 p_cli->vf_blks[0].start_line; 616 617 /* Now for the rest of the VFs */ 618 for (i = 1; i < p_mngr->vf_count; i++) { 619 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)]; 620 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 621 ILT_CLI_CDUT); 622 623 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)]; 624 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 625 ILT_CLI_CDUT); 626 } 627 } 628 629 /* QM */ 630 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_QM]); 631 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[0]); 632 633 qed_cxt_qm_iids(p_hwfn, &qm_iids); 634 total = qed_qm_pf_mem_size(qm_iids.cids, 635 qm_iids.vf_cids, qm_iids.tids, 636 p_hwfn->qm_info.num_pqs, 637 p_hwfn->qm_info.num_vf_pqs); 638 639 DP_VERBOSE(p_hwfn, 640 QED_MSG_ILT, 641 "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d, num_vf_pqs=%d, memory_size=%d)\n", 642 qm_iids.cids, 643 qm_iids.vf_cids, 644 qm_iids.tids, 645 p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total); 646 647 qed_ilt_cli_blk_fill(p_cli, p_blk, 648 curr_line, total * 0x1000, 649 QM_PQ_ELEMENT_SIZE); 650 651 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM); 652 p_cli->pf_total_lines = curr_line - p_blk->start_line; 653 654 /* SRC */ 655 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_SRC]); 656 qed_cxt_src_iids(p_mngr, &src_iids); 657 658 /* Both the PF and VFs searcher connections are stored in the per PF 659 * database. Thus sum the PF searcher cids and all the VFs searcher 660 * cids. 661 */ 662 total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count; 663 if (total) { 664 u32 local_max = max_t(u32, total, 665 SRC_MIN_NUM_ELEMS); 666 667 total = roundup_pow_of_two(local_max); 668 669 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[0]); 670 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 671 total * sizeof(struct src_ent), 672 sizeof(struct src_ent)); 673 674 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 675 ILT_CLI_SRC); 676 p_cli->pf_total_lines = curr_line - p_blk->start_line; 677 } 678 679 /* TM PF */ 680 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_TM]); 681 qed_cxt_tm_iids(p_hwfn, p_mngr, &tm_iids); 682 total = tm_iids.pf_cids + tm_iids.pf_tids_total; 683 if (total) { 684 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[0]); 685 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 686 total * TM_ELEM_SIZE, TM_ELEM_SIZE); 687 688 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 689 ILT_CLI_TM); 690 p_cli->pf_total_lines = curr_line - p_blk->start_line; 691 } 692 693 /* TM VF */ 694 total = tm_iids.per_vf_cids + tm_iids.per_vf_tids; 695 if (total) { 696 p_blk = qed_cxt_set_blk(&p_cli->vf_blks[0]); 697 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 698 total * TM_ELEM_SIZE, TM_ELEM_SIZE); 699 700 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 701 ILT_CLI_TM); 702 703 p_cli->vf_total_lines = curr_line - p_blk->start_line; 704 for (i = 1; i < p_mngr->vf_count; i++) 705 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 706 ILT_CLI_TM); 707 } 708 709 /* TSDM (SRQ CONTEXT) */ 710 total = qed_cxt_get_total_srq_count(p_hwfn); 711 712 if (total) { 713 p_cli = qed_cxt_set_cli(&p_mngr->clients[ILT_CLI_TSDM]); 714 p_blk = qed_cxt_set_blk(&p_cli->pf_blks[SRQ_BLK]); 715 qed_ilt_cli_blk_fill(p_cli, p_blk, curr_line, 716 total * SRQ_CXT_SIZE, SRQ_CXT_SIZE); 717 718 qed_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, 719 ILT_CLI_TSDM); 720 p_cli->pf_total_lines = curr_line - p_blk->start_line; 721 } 722 723 *line_count = curr_line - p_hwfn->p_cxt_mngr->pf_start_line; 724 725 if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line > 726 RESC_NUM(p_hwfn, QED_ILT)) 727 return -EINVAL; 728 729 return 0; 730 } 731 732 u32 qed_cxt_cfg_ilt_compute_excess(struct qed_hwfn *p_hwfn, u32 used_lines) 733 { 734 struct qed_ilt_client_cfg *p_cli; 735 u32 excess_lines, available_lines; 736 struct qed_cxt_mngr *p_mngr; 737 u32 ilt_page_size, elem_size; 738 struct qed_tid_seg *p_seg; 739 int i; 740 741 available_lines = RESC_NUM(p_hwfn, QED_ILT); 742 excess_lines = used_lines - available_lines; 743 744 if (!excess_lines) 745 return 0; 746 747 if (!QED_IS_RDMA_PERSONALITY(p_hwfn)) 748 return 0; 749 750 p_mngr = p_hwfn->p_cxt_mngr; 751 p_cli = &p_mngr->clients[ILT_CLI_CDUT]; 752 ilt_page_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val); 753 754 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 755 p_seg = qed_cxt_tid_seg_info(p_hwfn, i); 756 if (!p_seg || p_seg->count == 0) 757 continue; 758 759 elem_size = p_mngr->task_type_size[p_seg->type]; 760 if (!elem_size) 761 continue; 762 763 return (ilt_page_size / elem_size) * excess_lines; 764 } 765 766 DP_NOTICE(p_hwfn, "failed computing excess ILT lines\n"); 767 return 0; 768 } 769 770 static void qed_cxt_src_t2_free(struct qed_hwfn *p_hwfn) 771 { 772 struct qed_src_t2 *p_t2 = &p_hwfn->p_cxt_mngr->src_t2; 773 u32 i; 774 775 if (!p_t2 || !p_t2->dma_mem) 776 return; 777 778 for (i = 0; i < p_t2->num_pages; i++) 779 if (p_t2->dma_mem[i].virt_addr) 780 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 781 p_t2->dma_mem[i].size, 782 p_t2->dma_mem[i].virt_addr, 783 p_t2->dma_mem[i].phys_addr); 784 785 kfree(p_t2->dma_mem); 786 p_t2->dma_mem = NULL; 787 } 788 789 static int 790 qed_cxt_t2_alloc_pages(struct qed_hwfn *p_hwfn, 791 struct qed_src_t2 *p_t2, u32 total_size, u32 page_size) 792 { 793 void **p_virt; 794 u32 size, i; 795 796 if (!p_t2 || !p_t2->dma_mem) 797 return -EINVAL; 798 799 for (i = 0; i < p_t2->num_pages; i++) { 800 size = min_t(u32, total_size, page_size); 801 p_virt = &p_t2->dma_mem[i].virt_addr; 802 803 *p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 804 size, 805 &p_t2->dma_mem[i].phys_addr, 806 GFP_KERNEL); 807 if (!p_t2->dma_mem[i].virt_addr) 808 return -ENOMEM; 809 810 memset(*p_virt, 0, size); 811 p_t2->dma_mem[i].size = size; 812 total_size -= size; 813 } 814 815 return 0; 816 } 817 818 static int qed_cxt_src_t2_alloc(struct qed_hwfn *p_hwfn) 819 { 820 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 821 u32 conn_num, total_size, ent_per_page, psz, i; 822 struct phys_mem_desc *p_t2_last_page; 823 struct qed_ilt_client_cfg *p_src; 824 struct qed_src_iids src_iids; 825 struct qed_src_t2 *p_t2; 826 int rc; 827 828 memset(&src_iids, 0, sizeof(src_iids)); 829 830 /* if the SRC ILT client is inactive - there are no connection 831 * requiring the searcer, leave. 832 */ 833 p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC]; 834 if (!p_src->active) 835 return 0; 836 837 qed_cxt_src_iids(p_mngr, &src_iids); 838 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count; 839 total_size = conn_num * sizeof(struct src_ent); 840 841 /* use the same page size as the SRC ILT client */ 842 psz = ILT_PAGE_IN_BYTES(p_src->p_size.val); 843 p_t2 = &p_mngr->src_t2; 844 p_t2->num_pages = DIV_ROUND_UP(total_size, psz); 845 846 /* allocate t2 */ 847 p_t2->dma_mem = kcalloc(p_t2->num_pages, sizeof(struct phys_mem_desc), 848 GFP_KERNEL); 849 if (!p_t2->dma_mem) { 850 DP_NOTICE(p_hwfn, "Failed to allocate t2 table\n"); 851 rc = -ENOMEM; 852 goto t2_fail; 853 } 854 855 rc = qed_cxt_t2_alloc_pages(p_hwfn, p_t2, total_size, psz); 856 if (rc) 857 goto t2_fail; 858 859 /* Set the t2 pointers */ 860 861 /* entries per page - must be a power of two */ 862 ent_per_page = psz / sizeof(struct src_ent); 863 864 p_t2->first_free = (u64)p_t2->dma_mem[0].phys_addr; 865 866 p_t2_last_page = &p_t2->dma_mem[(conn_num - 1) / ent_per_page]; 867 p_t2->last_free = (u64)p_t2_last_page->phys_addr + 868 ((conn_num - 1) & (ent_per_page - 1)) * sizeof(struct src_ent); 869 870 for (i = 0; i < p_t2->num_pages; i++) { 871 u32 ent_num = min_t(u32, 872 ent_per_page, 873 conn_num); 874 struct src_ent *entries = p_t2->dma_mem[i].virt_addr; 875 u64 p_ent_phys = (u64)p_t2->dma_mem[i].phys_addr, val; 876 u32 j; 877 878 for (j = 0; j < ent_num - 1; j++) { 879 val = p_ent_phys + (j + 1) * sizeof(struct src_ent); 880 entries[j].next = cpu_to_be64(val); 881 } 882 883 if (i < p_t2->num_pages - 1) 884 val = (u64)p_t2->dma_mem[i + 1].phys_addr; 885 else 886 val = 0; 887 entries[j].next = cpu_to_be64(val); 888 889 conn_num -= ent_num; 890 } 891 892 return 0; 893 894 t2_fail: 895 qed_cxt_src_t2_free(p_hwfn); 896 return rc; 897 } 898 899 #define for_each_ilt_valid_client(pos, clients) \ 900 for (pos = 0; pos < MAX_ILT_CLIENTS; pos++) \ 901 if (!clients[pos].active) { \ 902 continue; \ 903 } else \ 904 905 /* Total number of ILT lines used by this PF */ 906 static u32 qed_cxt_ilt_shadow_size(struct qed_ilt_client_cfg *ilt_clients) 907 { 908 u32 size = 0; 909 u32 i; 910 911 for_each_ilt_valid_client(i, ilt_clients) 912 size += (ilt_clients[i].last.val - ilt_clients[i].first.val + 1); 913 914 return size; 915 } 916 917 static void qed_ilt_shadow_free(struct qed_hwfn *p_hwfn) 918 { 919 struct qed_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients; 920 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 921 u32 ilt_size, i; 922 923 ilt_size = qed_cxt_ilt_shadow_size(p_cli); 924 925 for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) { 926 struct phys_mem_desc *p_dma = &p_mngr->ilt_shadow[i]; 927 928 if (p_dma->virt_addr) 929 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 930 p_dma->size, p_dma->virt_addr, 931 p_dma->phys_addr); 932 p_dma->virt_addr = NULL; 933 } 934 kfree(p_mngr->ilt_shadow); 935 } 936 937 static int qed_ilt_blk_alloc(struct qed_hwfn *p_hwfn, 938 struct qed_ilt_cli_blk *p_blk, 939 enum ilt_clients ilt_client, 940 u32 start_line_offset) 941 { 942 struct phys_mem_desc *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow; 943 u32 lines, line, sz_left, lines_to_skip = 0; 944 945 /* Special handling for RoCE that supports dynamic allocation */ 946 if (QED_IS_RDMA_PERSONALITY(p_hwfn) && 947 ((ilt_client == ILT_CLI_CDUT) || ilt_client == ILT_CLI_TSDM)) 948 return 0; 949 950 lines_to_skip = p_blk->dynamic_line_cnt; 951 952 if (!p_blk->total_size) 953 return 0; 954 955 sz_left = p_blk->total_size; 956 lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) - lines_to_skip; 957 line = p_blk->start_line + start_line_offset - 958 p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip; 959 960 for (; lines; lines--) { 961 dma_addr_t p_phys; 962 void *p_virt; 963 u32 size; 964 965 size = min_t(u32, sz_left, p_blk->real_size_in_page); 966 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, size, 967 &p_phys, GFP_KERNEL); 968 if (!p_virt) 969 return -ENOMEM; 970 971 ilt_shadow[line].phys_addr = p_phys; 972 ilt_shadow[line].virt_addr = p_virt; 973 ilt_shadow[line].size = size; 974 975 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 976 "ILT shadow: Line [%d] Physical 0x%llx Virtual %p Size %d\n", 977 line, (u64)p_phys, p_virt, size); 978 979 sz_left -= size; 980 line++; 981 } 982 983 return 0; 984 } 985 986 static int qed_ilt_shadow_alloc(struct qed_hwfn *p_hwfn) 987 { 988 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 989 struct qed_ilt_client_cfg *clients = p_mngr->clients; 990 struct qed_ilt_cli_blk *p_blk; 991 u32 size, i, j, k; 992 int rc; 993 994 size = qed_cxt_ilt_shadow_size(clients); 995 p_mngr->ilt_shadow = kcalloc(size, sizeof(struct phys_mem_desc), 996 GFP_KERNEL); 997 if (!p_mngr->ilt_shadow) { 998 rc = -ENOMEM; 999 goto ilt_shadow_fail; 1000 } 1001 1002 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 1003 "Allocated 0x%x bytes for ilt shadow\n", 1004 (u32)(size * sizeof(struct phys_mem_desc))); 1005 1006 for_each_ilt_valid_client(i, clients) { 1007 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) { 1008 p_blk = &clients[i].pf_blks[j]; 1009 rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, 0); 1010 if (rc) 1011 goto ilt_shadow_fail; 1012 } 1013 for (k = 0; k < p_mngr->vf_count; k++) { 1014 for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) { 1015 u32 lines = clients[i].vf_total_lines * k; 1016 1017 p_blk = &clients[i].vf_blks[j]; 1018 rc = qed_ilt_blk_alloc(p_hwfn, p_blk, i, lines); 1019 if (rc) 1020 goto ilt_shadow_fail; 1021 } 1022 } 1023 } 1024 1025 return 0; 1026 1027 ilt_shadow_fail: 1028 qed_ilt_shadow_free(p_hwfn); 1029 return rc; 1030 } 1031 1032 static void qed_cid_map_free(struct qed_hwfn *p_hwfn) 1033 { 1034 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1035 u32 type, vf; 1036 1037 for (type = 0; type < MAX_CONN_TYPES; type++) { 1038 kfree(p_mngr->acquired[type].cid_map); 1039 p_mngr->acquired[type].max_count = 0; 1040 p_mngr->acquired[type].start_cid = 0; 1041 1042 for (vf = 0; vf < MAX_NUM_VFS; vf++) { 1043 kfree(p_mngr->acquired_vf[type][vf].cid_map); 1044 p_mngr->acquired_vf[type][vf].max_count = 0; 1045 p_mngr->acquired_vf[type][vf].start_cid = 0; 1046 } 1047 } 1048 } 1049 1050 static int 1051 qed_cid_map_alloc_single(struct qed_hwfn *p_hwfn, 1052 u32 type, 1053 u32 cid_start, 1054 u32 cid_count, struct qed_cid_acquired_map *p_map) 1055 { 1056 u32 size; 1057 1058 if (!cid_count) 1059 return 0; 1060 1061 size = DIV_ROUND_UP(cid_count, 1062 sizeof(unsigned long) * BITS_PER_BYTE) * 1063 sizeof(unsigned long); 1064 p_map->cid_map = kzalloc(size, GFP_KERNEL); 1065 if (!p_map->cid_map) 1066 return -ENOMEM; 1067 1068 p_map->max_count = cid_count; 1069 p_map->start_cid = cid_start; 1070 1071 DP_VERBOSE(p_hwfn, QED_MSG_CXT, 1072 "Type %08x start: %08x count %08x\n", 1073 type, p_map->start_cid, p_map->max_count); 1074 1075 return 0; 1076 } 1077 1078 static int qed_cid_map_alloc(struct qed_hwfn *p_hwfn) 1079 { 1080 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1081 u32 start_cid = 0, vf_start_cid = 0; 1082 u32 type, vf; 1083 1084 for (type = 0; type < MAX_CONN_TYPES; type++) { 1085 struct qed_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[type]; 1086 struct qed_cid_acquired_map *p_map; 1087 1088 /* Handle PF maps */ 1089 p_map = &p_mngr->acquired[type]; 1090 if (qed_cid_map_alloc_single(p_hwfn, type, start_cid, 1091 p_cfg->cid_count, p_map)) 1092 goto cid_map_fail; 1093 1094 /* Handle VF maps */ 1095 for (vf = 0; vf < MAX_NUM_VFS; vf++) { 1096 p_map = &p_mngr->acquired_vf[type][vf]; 1097 if (qed_cid_map_alloc_single(p_hwfn, type, 1098 vf_start_cid, 1099 p_cfg->cids_per_vf, p_map)) 1100 goto cid_map_fail; 1101 } 1102 1103 start_cid += p_cfg->cid_count; 1104 vf_start_cid += p_cfg->cids_per_vf; 1105 } 1106 1107 return 0; 1108 1109 cid_map_fail: 1110 qed_cid_map_free(p_hwfn); 1111 return -ENOMEM; 1112 } 1113 1114 int qed_cxt_mngr_alloc(struct qed_hwfn *p_hwfn) 1115 { 1116 struct qed_ilt_client_cfg *clients; 1117 struct qed_cxt_mngr *p_mngr; 1118 u32 i; 1119 1120 p_mngr = kzalloc(sizeof(*p_mngr), GFP_KERNEL); 1121 if (!p_mngr) 1122 return -ENOMEM; 1123 1124 /* Initialize ILT client registers */ 1125 clients = p_mngr->clients; 1126 clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT); 1127 clients[ILT_CLI_CDUC].last.reg = ILT_CFG_REG(CDUC, LAST_ILT); 1128 clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE); 1129 1130 clients[ILT_CLI_QM].first.reg = ILT_CFG_REG(QM, FIRST_ILT); 1131 clients[ILT_CLI_QM].last.reg = ILT_CFG_REG(QM, LAST_ILT); 1132 clients[ILT_CLI_QM].p_size.reg = ILT_CFG_REG(QM, P_SIZE); 1133 1134 clients[ILT_CLI_TM].first.reg = ILT_CFG_REG(TM, FIRST_ILT); 1135 clients[ILT_CLI_TM].last.reg = ILT_CFG_REG(TM, LAST_ILT); 1136 clients[ILT_CLI_TM].p_size.reg = ILT_CFG_REG(TM, P_SIZE); 1137 1138 clients[ILT_CLI_SRC].first.reg = ILT_CFG_REG(SRC, FIRST_ILT); 1139 clients[ILT_CLI_SRC].last.reg = ILT_CFG_REG(SRC, LAST_ILT); 1140 clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE); 1141 1142 clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT); 1143 clients[ILT_CLI_CDUT].last.reg = ILT_CFG_REG(CDUT, LAST_ILT); 1144 clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE); 1145 1146 clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT); 1147 clients[ILT_CLI_TSDM].last.reg = ILT_CFG_REG(TSDM, LAST_ILT); 1148 clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE); 1149 /* default ILT page size for all clients is 64K */ 1150 for (i = 0; i < MAX_ILT_CLIENTS; i++) 1151 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE; 1152 1153 p_mngr->conn_ctx_size = CONN_CXT_SIZE(p_hwfn); 1154 1155 /* Initialize task sizes */ 1156 p_mngr->task_type_size[0] = TYPE0_TASK_CXT_SIZE(p_hwfn); 1157 p_mngr->task_type_size[1] = TYPE1_TASK_CXT_SIZE(p_hwfn); 1158 1159 if (p_hwfn->cdev->p_iov_info) { 1160 p_mngr->vf_count = p_hwfn->cdev->p_iov_info->total_vfs; 1161 p_mngr->first_vf_in_pf = 1162 p_hwfn->cdev->p_iov_info->first_vf_in_pf; 1163 } 1164 /* Initialize the dynamic ILT allocation mutex */ 1165 mutex_init(&p_mngr->mutex); 1166 1167 /* Set the cxt mangr pointer priori to further allocations */ 1168 p_hwfn->p_cxt_mngr = p_mngr; 1169 1170 return 0; 1171 } 1172 1173 int qed_cxt_tables_alloc(struct qed_hwfn *p_hwfn) 1174 { 1175 int rc; 1176 1177 /* Allocate the ILT shadow table */ 1178 rc = qed_ilt_shadow_alloc(p_hwfn); 1179 if (rc) 1180 goto tables_alloc_fail; 1181 1182 /* Allocate the T2 table */ 1183 rc = qed_cxt_src_t2_alloc(p_hwfn); 1184 if (rc) 1185 goto tables_alloc_fail; 1186 1187 /* Allocate and initialize the acquired cids bitmaps */ 1188 rc = qed_cid_map_alloc(p_hwfn); 1189 if (rc) 1190 goto tables_alloc_fail; 1191 1192 return 0; 1193 1194 tables_alloc_fail: 1195 qed_cxt_mngr_free(p_hwfn); 1196 return rc; 1197 } 1198 1199 void qed_cxt_mngr_free(struct qed_hwfn *p_hwfn) 1200 { 1201 if (!p_hwfn->p_cxt_mngr) 1202 return; 1203 1204 qed_cid_map_free(p_hwfn); 1205 qed_cxt_src_t2_free(p_hwfn); 1206 qed_ilt_shadow_free(p_hwfn); 1207 kfree(p_hwfn->p_cxt_mngr); 1208 1209 p_hwfn->p_cxt_mngr = NULL; 1210 } 1211 1212 void qed_cxt_mngr_setup(struct qed_hwfn *p_hwfn) 1213 { 1214 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1215 struct qed_cid_acquired_map *p_map; 1216 struct qed_conn_type_cfg *p_cfg; 1217 int type; 1218 u32 len; 1219 1220 /* Reset acquired cids */ 1221 for (type = 0; type < MAX_CONN_TYPES; type++) { 1222 u32 vf; 1223 1224 p_cfg = &p_mngr->conn_cfg[type]; 1225 if (p_cfg->cid_count) { 1226 p_map = &p_mngr->acquired[type]; 1227 len = DIV_ROUND_UP(p_map->max_count, 1228 sizeof(unsigned long) * 1229 BITS_PER_BYTE) * 1230 sizeof(unsigned long); 1231 memset(p_map->cid_map, 0, len); 1232 } 1233 1234 if (!p_cfg->cids_per_vf) 1235 continue; 1236 1237 for (vf = 0; vf < MAX_NUM_VFS; vf++) { 1238 p_map = &p_mngr->acquired_vf[type][vf]; 1239 len = DIV_ROUND_UP(p_map->max_count, 1240 sizeof(unsigned long) * 1241 BITS_PER_BYTE) * 1242 sizeof(unsigned long); 1243 memset(p_map->cid_map, 0, len); 1244 } 1245 } 1246 } 1247 1248 /* CDU Common */ 1249 #define CDUC_CXT_SIZE_SHIFT \ 1250 CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT 1251 1252 #define CDUC_CXT_SIZE_MASK \ 1253 (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT) 1254 1255 #define CDUC_BLOCK_WASTE_SHIFT \ 1256 CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT 1257 1258 #define CDUC_BLOCK_WASTE_MASK \ 1259 (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT) 1260 1261 #define CDUC_NCIB_SHIFT \ 1262 CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT 1263 1264 #define CDUC_NCIB_MASK \ 1265 (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT) 1266 1267 #define CDUT_TYPE0_CXT_SIZE_SHIFT \ 1268 CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT 1269 1270 #define CDUT_TYPE0_CXT_SIZE_MASK \ 1271 (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >> \ 1272 CDUT_TYPE0_CXT_SIZE_SHIFT) 1273 1274 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT \ 1275 CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT 1276 1277 #define CDUT_TYPE0_BLOCK_WASTE_MASK \ 1278 (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >> \ 1279 CDUT_TYPE0_BLOCK_WASTE_SHIFT) 1280 1281 #define CDUT_TYPE0_NCIB_SHIFT \ 1282 CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT 1283 1284 #define CDUT_TYPE0_NCIB_MASK \ 1285 (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >> \ 1286 CDUT_TYPE0_NCIB_SHIFT) 1287 1288 #define CDUT_TYPE1_CXT_SIZE_SHIFT \ 1289 CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT 1290 1291 #define CDUT_TYPE1_CXT_SIZE_MASK \ 1292 (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >> \ 1293 CDUT_TYPE1_CXT_SIZE_SHIFT) 1294 1295 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT \ 1296 CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT 1297 1298 #define CDUT_TYPE1_BLOCK_WASTE_MASK \ 1299 (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >> \ 1300 CDUT_TYPE1_BLOCK_WASTE_SHIFT) 1301 1302 #define CDUT_TYPE1_NCIB_SHIFT \ 1303 CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT 1304 1305 #define CDUT_TYPE1_NCIB_MASK \ 1306 (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >> \ 1307 CDUT_TYPE1_NCIB_SHIFT) 1308 1309 static void qed_cdu_init_common(struct qed_hwfn *p_hwfn) 1310 { 1311 u32 page_sz, elems_per_page, block_waste, cxt_size, cdu_params = 0; 1312 1313 /* CDUC - connection configuration */ 1314 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val; 1315 cxt_size = CONN_CXT_SIZE(p_hwfn); 1316 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 1317 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size; 1318 1319 SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size); 1320 SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste); 1321 SET_FIELD(cdu_params, CDUC_NCIB, elems_per_page); 1322 STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params); 1323 1324 /* CDUT - type-0 tasks configuration */ 1325 page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val; 1326 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0]; 1327 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 1328 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size; 1329 1330 /* cxt size and block-waste are multipes of 8 */ 1331 cdu_params = 0; 1332 SET_FIELD(cdu_params, CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3)); 1333 SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3)); 1334 SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page); 1335 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params); 1336 1337 /* CDUT - type-1 tasks configuration */ 1338 cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1]; 1339 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size; 1340 block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size; 1341 1342 /* cxt size and block-waste are multipes of 8 */ 1343 cdu_params = 0; 1344 SET_FIELD(cdu_params, CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3)); 1345 SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3)); 1346 SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page); 1347 STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params); 1348 } 1349 1350 /* CDU PF */ 1351 #define CDU_SEG_REG_TYPE_SHIFT CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT 1352 #define CDU_SEG_REG_TYPE_MASK 0x1 1353 #define CDU_SEG_REG_OFFSET_SHIFT 0 1354 #define CDU_SEG_REG_OFFSET_MASK CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK 1355 1356 static void qed_cdu_init_pf(struct qed_hwfn *p_hwfn) 1357 { 1358 struct qed_ilt_client_cfg *p_cli; 1359 struct qed_tid_seg *p_seg; 1360 u32 cdu_seg_params, offset; 1361 int i; 1362 1363 static const u32 rt_type_offset_arr[] = { 1364 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET, 1365 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET, 1366 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET, 1367 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET 1368 }; 1369 1370 static const u32 rt_type_offset_fl_arr[] = { 1371 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET, 1372 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET, 1373 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET, 1374 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET 1375 }; 1376 1377 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 1378 1379 /* There are initializations only for CDUT during pf Phase */ 1380 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 1381 /* Segment 0 */ 1382 p_seg = qed_cxt_tid_seg_info(p_hwfn, i); 1383 if (!p_seg) 1384 continue; 1385 1386 /* Note: start_line is already adjusted for the CDU 1387 * segment register granularity, so we just need to 1388 * divide. Adjustment is implicit as we assume ILT 1389 * Page size is larger than 32K! 1390 */ 1391 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) * 1392 (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line - 1393 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES; 1394 1395 cdu_seg_params = 0; 1396 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type); 1397 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset); 1398 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i], cdu_seg_params); 1399 1400 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) * 1401 (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line - 1402 p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES; 1403 1404 cdu_seg_params = 0; 1405 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type); 1406 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset); 1407 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i], cdu_seg_params); 1408 } 1409 } 1410 1411 void qed_qm_init_pf(struct qed_hwfn *p_hwfn, 1412 struct qed_ptt *p_ptt, bool is_pf_loading) 1413 { 1414 struct qed_qm_info *qm_info = &p_hwfn->qm_info; 1415 struct qed_qm_pf_rt_init_params params; 1416 struct qed_qm_iids iids; 1417 1418 memset(&iids, 0, sizeof(iids)); 1419 qed_cxt_qm_iids(p_hwfn, &iids); 1420 1421 memset(¶ms, 0, sizeof(params)); 1422 params.port_id = p_hwfn->port_id; 1423 params.pf_id = p_hwfn->rel_pf_id; 1424 params.max_phys_tcs_per_port = qm_info->max_phys_tcs_per_port; 1425 params.is_pf_loading = is_pf_loading; 1426 params.num_pf_cids = iids.cids; 1427 params.num_vf_cids = iids.vf_cids; 1428 params.num_tids = iids.tids; 1429 params.start_pq = qm_info->start_pq; 1430 params.num_pf_pqs = qm_info->num_pqs - qm_info->num_vf_pqs; 1431 params.num_vf_pqs = qm_info->num_vf_pqs; 1432 params.start_vport = qm_info->start_vport; 1433 params.num_vports = qm_info->num_vports; 1434 params.pf_wfq = qm_info->pf_wfq; 1435 params.pf_rl = qm_info->pf_rl; 1436 params.pq_params = qm_info->qm_pq_params; 1437 params.vport_params = qm_info->qm_vport_params; 1438 1439 qed_qm_pf_rt_init(p_hwfn, p_ptt, ¶ms); 1440 } 1441 1442 /* CM PF */ 1443 static void qed_cm_init_pf(struct qed_hwfn *p_hwfn) 1444 { 1445 /* XCM pure-LB queue */ 1446 STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET, 1447 qed_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB)); 1448 } 1449 1450 /* DQ PF */ 1451 static void qed_dq_init_pf(struct qed_hwfn *p_hwfn) 1452 { 1453 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1454 u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0; 1455 1456 dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT); 1457 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid); 1458 1459 dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT); 1460 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid); 1461 1462 dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT); 1463 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid); 1464 1465 dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT); 1466 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid); 1467 1468 dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT); 1469 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid); 1470 1471 dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT); 1472 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid); 1473 1474 dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT); 1475 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid); 1476 1477 dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT); 1478 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid); 1479 1480 dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT); 1481 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid); 1482 1483 dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT); 1484 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid); 1485 1486 dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT); 1487 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid); 1488 1489 dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT); 1490 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid); 1491 1492 /* Connection types 6 & 7 are not in use, yet they must be configured 1493 * as the highest possible connection. Not configuring them means the 1494 * defaults will be used, and with a large number of cids a bug may 1495 * occur, if the defaults will be smaller than dq_pf_max_cid / 1496 * dq_vf_max_cid. 1497 */ 1498 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid); 1499 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid); 1500 1501 STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid); 1502 STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid); 1503 } 1504 1505 static void qed_ilt_bounds_init(struct qed_hwfn *p_hwfn) 1506 { 1507 struct qed_ilt_client_cfg *ilt_clients; 1508 int i; 1509 1510 ilt_clients = p_hwfn->p_cxt_mngr->clients; 1511 for_each_ilt_valid_client(i, ilt_clients) { 1512 STORE_RT_REG(p_hwfn, 1513 ilt_clients[i].first.reg, 1514 ilt_clients[i].first.val); 1515 STORE_RT_REG(p_hwfn, 1516 ilt_clients[i].last.reg, ilt_clients[i].last.val); 1517 STORE_RT_REG(p_hwfn, 1518 ilt_clients[i].p_size.reg, 1519 ilt_clients[i].p_size.val); 1520 } 1521 } 1522 1523 static void qed_ilt_vf_bounds_init(struct qed_hwfn *p_hwfn) 1524 { 1525 struct qed_ilt_client_cfg *p_cli; 1526 u32 blk_factor; 1527 1528 /* For simplicty we set the 'block' to be an ILT page */ 1529 if (p_hwfn->cdev->p_iov_info) { 1530 struct qed_hw_sriov_info *p_iov = p_hwfn->cdev->p_iov_info; 1531 1532 STORE_RT_REG(p_hwfn, 1533 PSWRQ2_REG_VF_BASE_RT_OFFSET, 1534 p_iov->first_vf_in_pf); 1535 STORE_RT_REG(p_hwfn, 1536 PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET, 1537 p_iov->first_vf_in_pf + p_iov->total_vfs); 1538 } 1539 1540 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 1541 blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10); 1542 if (p_cli->active) { 1543 STORE_RT_REG(p_hwfn, 1544 PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET, 1545 blk_factor); 1546 STORE_RT_REG(p_hwfn, 1547 PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET, 1548 p_cli->pf_total_lines); 1549 STORE_RT_REG(p_hwfn, 1550 PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET, 1551 p_cli->vf_total_lines); 1552 } 1553 1554 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 1555 blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10); 1556 if (p_cli->active) { 1557 STORE_RT_REG(p_hwfn, 1558 PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET, 1559 blk_factor); 1560 STORE_RT_REG(p_hwfn, 1561 PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET, 1562 p_cli->pf_total_lines); 1563 STORE_RT_REG(p_hwfn, 1564 PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET, 1565 p_cli->vf_total_lines); 1566 } 1567 1568 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM]; 1569 blk_factor = ilog2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10); 1570 if (p_cli->active) { 1571 STORE_RT_REG(p_hwfn, 1572 PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET, blk_factor); 1573 STORE_RT_REG(p_hwfn, 1574 PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET, 1575 p_cli->pf_total_lines); 1576 STORE_RT_REG(p_hwfn, 1577 PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET, 1578 p_cli->vf_total_lines); 1579 } 1580 } 1581 1582 /* ILT (PSWRQ2) PF */ 1583 static void qed_ilt_init_pf(struct qed_hwfn *p_hwfn) 1584 { 1585 struct qed_ilt_client_cfg *clients; 1586 struct qed_cxt_mngr *p_mngr; 1587 struct phys_mem_desc *p_shdw; 1588 u32 line, rt_offst, i; 1589 1590 qed_ilt_bounds_init(p_hwfn); 1591 qed_ilt_vf_bounds_init(p_hwfn); 1592 1593 p_mngr = p_hwfn->p_cxt_mngr; 1594 p_shdw = p_mngr->ilt_shadow; 1595 clients = p_hwfn->p_cxt_mngr->clients; 1596 1597 for_each_ilt_valid_client(i, clients) { 1598 /** Client's 1st val and RT array are absolute, ILT shadows' 1599 * lines are relative. 1600 */ 1601 line = clients[i].first.val - p_mngr->pf_start_line; 1602 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET + 1603 clients[i].first.val * ILT_ENTRY_IN_REGS; 1604 1605 for (; line <= clients[i].last.val - p_mngr->pf_start_line; 1606 line++, rt_offst += ILT_ENTRY_IN_REGS) { 1607 u64 ilt_hw_entry = 0; 1608 1609 /** p_virt could be NULL incase of dynamic 1610 * allocation 1611 */ 1612 if (p_shdw[line].virt_addr) { 1613 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL); 1614 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR, 1615 (p_shdw[line].phys_addr >> 12)); 1616 1617 DP_VERBOSE(p_hwfn, QED_MSG_ILT, 1618 "Setting RT[0x%08x] from ILT[0x%08x] [Client is %d] to Physical addr: 0x%llx\n", 1619 rt_offst, line, i, 1620 (u64)(p_shdw[line].phys_addr >> 12)); 1621 } 1622 1623 STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry); 1624 } 1625 } 1626 } 1627 1628 /* SRC (Searcher) PF */ 1629 static void qed_src_init_pf(struct qed_hwfn *p_hwfn) 1630 { 1631 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1632 u32 rounded_conn_num, conn_num, conn_max; 1633 struct qed_src_iids src_iids; 1634 1635 memset(&src_iids, 0, sizeof(src_iids)); 1636 qed_cxt_src_iids(p_mngr, &src_iids); 1637 conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count; 1638 if (!conn_num) 1639 return; 1640 1641 conn_max = max_t(u32, conn_num, SRC_MIN_NUM_ELEMS); 1642 rounded_conn_num = roundup_pow_of_two(conn_max); 1643 1644 STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num); 1645 STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET, 1646 ilog2(rounded_conn_num)); 1647 1648 STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET, 1649 p_hwfn->p_cxt_mngr->first_free); 1650 STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET, 1651 p_hwfn->p_cxt_mngr->last_free); 1652 } 1653 1654 /* Timers PF */ 1655 #define TM_CFG_NUM_IDS_SHIFT 0 1656 #define TM_CFG_NUM_IDS_MASK 0xFFFFULL 1657 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT 16 1658 #define TM_CFG_PRE_SCAN_OFFSET_MASK 0x1FFULL 1659 #define TM_CFG_PARENT_PF_SHIFT 25 1660 #define TM_CFG_PARENT_PF_MASK 0x7ULL 1661 1662 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT 30 1663 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK 0x1FFULL 1664 1665 #define TM_CFG_TID_OFFSET_SHIFT 30 1666 #define TM_CFG_TID_OFFSET_MASK 0x7FFFFULL 1667 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT 49 1668 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK 0x1FFULL 1669 1670 static void qed_tm_init_pf(struct qed_hwfn *p_hwfn) 1671 { 1672 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1673 u32 active_seg_mask = 0, tm_offset, rt_reg; 1674 struct qed_tm_iids tm_iids; 1675 u64 cfg_word; 1676 u8 i; 1677 1678 memset(&tm_iids, 0, sizeof(tm_iids)); 1679 qed_cxt_tm_iids(p_hwfn, p_mngr, &tm_iids); 1680 1681 /* @@@TBD No pre-scan for now */ 1682 1683 /* Note: We assume consecutive VFs for a PF */ 1684 for (i = 0; i < p_mngr->vf_count; i++) { 1685 cfg_word = 0; 1686 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids); 1687 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1688 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id); 1689 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); 1690 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET + 1691 (sizeof(cfg_word) / sizeof(u32)) * 1692 (p_hwfn->cdev->p_iov_info->first_vf_in_pf + i); 1693 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1694 } 1695 1696 cfg_word = 0; 1697 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids); 1698 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1699 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); /* n/a for PF */ 1700 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */ 1701 1702 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET + 1703 (sizeof(cfg_word) / sizeof(u32)) * 1704 (NUM_OF_VFS(p_hwfn->cdev) + p_hwfn->rel_pf_id); 1705 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1706 1707 /* enale scan */ 1708 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET, 1709 tm_iids.pf_cids ? 0x1 : 0x0); 1710 1711 /* @@@TBD how to enable the scan for the VFs */ 1712 1713 tm_offset = tm_iids.per_vf_cids; 1714 1715 /* Note: We assume consecutive VFs for a PF */ 1716 for (i = 0; i < p_mngr->vf_count; i++) { 1717 cfg_word = 0; 1718 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids); 1719 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1720 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id); 1721 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset); 1722 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0); 1723 1724 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET + 1725 (sizeof(cfg_word) / sizeof(u32)) * 1726 (p_hwfn->cdev->p_iov_info->first_vf_in_pf + i); 1727 1728 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1729 } 1730 1731 tm_offset = tm_iids.pf_cids; 1732 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 1733 cfg_word = 0; 1734 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]); 1735 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0); 1736 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0); 1737 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset); 1738 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64) 0); 1739 1740 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET + 1741 (sizeof(cfg_word) / sizeof(u32)) * 1742 (NUM_OF_VFS(p_hwfn->cdev) + 1743 p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i); 1744 1745 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word); 1746 active_seg_mask |= (tm_iids.pf_tids[i] ? BIT(i) : 0); 1747 1748 tm_offset += tm_iids.pf_tids[i]; 1749 } 1750 1751 if (QED_IS_RDMA_PERSONALITY(p_hwfn)) 1752 active_seg_mask = 0; 1753 1754 STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask); 1755 1756 /* @@@TBD how to enable the scan for the VFs */ 1757 } 1758 1759 static void qed_prs_init_common(struct qed_hwfn *p_hwfn) 1760 { 1761 if ((p_hwfn->hw_info.personality == QED_PCI_FCOE) && 1762 p_hwfn->pf_params.fcoe_pf_params.is_target) 1763 STORE_RT_REG(p_hwfn, 1764 PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET, 0); 1765 } 1766 1767 static void qed_prs_init_pf(struct qed_hwfn *p_hwfn) 1768 { 1769 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1770 struct qed_conn_type_cfg *p_fcoe; 1771 struct qed_tid_seg *p_tid; 1772 1773 p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE]; 1774 1775 /* If FCoE is active set the MAX OX_ID (tid) in the Parser */ 1776 if (!p_fcoe->cid_count) 1777 return; 1778 1779 p_tid = &p_fcoe->tid_seg[QED_CXT_FCOE_TID_SEG]; 1780 if (p_hwfn->pf_params.fcoe_pf_params.is_target) { 1781 STORE_RT_REG_AGG(p_hwfn, 1782 PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET, 1783 p_tid->count); 1784 } else { 1785 STORE_RT_REG_AGG(p_hwfn, 1786 PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET, 1787 p_tid->count); 1788 } 1789 } 1790 1791 void qed_cxt_hw_init_common(struct qed_hwfn *p_hwfn) 1792 { 1793 qed_cdu_init_common(p_hwfn); 1794 qed_prs_init_common(p_hwfn); 1795 } 1796 1797 void qed_cxt_hw_init_pf(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) 1798 { 1799 qed_qm_init_pf(p_hwfn, p_ptt, true); 1800 qed_cm_init_pf(p_hwfn); 1801 qed_dq_init_pf(p_hwfn); 1802 qed_cdu_init_pf(p_hwfn); 1803 qed_ilt_init_pf(p_hwfn); 1804 qed_src_init_pf(p_hwfn); 1805 qed_tm_init_pf(p_hwfn); 1806 qed_prs_init_pf(p_hwfn); 1807 } 1808 1809 int _qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn, 1810 enum protocol_type type, u32 *p_cid, u8 vfid) 1811 { 1812 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1813 struct qed_cid_acquired_map *p_map; 1814 u32 rel_cid; 1815 1816 if (type >= MAX_CONN_TYPES) { 1817 DP_NOTICE(p_hwfn, "Invalid protocol type %d", type); 1818 return -EINVAL; 1819 } 1820 1821 if (vfid >= MAX_NUM_VFS && vfid != QED_CXT_PF_CID) { 1822 DP_NOTICE(p_hwfn, "VF [%02x] is out of range\n", vfid); 1823 return -EINVAL; 1824 } 1825 1826 /* Determine the right map to take this CID from */ 1827 if (vfid == QED_CXT_PF_CID) 1828 p_map = &p_mngr->acquired[type]; 1829 else 1830 p_map = &p_mngr->acquired_vf[type][vfid]; 1831 1832 if (!p_map->cid_map) { 1833 DP_NOTICE(p_hwfn, "Invalid protocol type %d", type); 1834 return -EINVAL; 1835 } 1836 1837 rel_cid = find_first_zero_bit(p_map->cid_map, p_map->max_count); 1838 1839 if (rel_cid >= p_map->max_count) { 1840 DP_NOTICE(p_hwfn, "no CID available for protocol %d\n", type); 1841 return -EINVAL; 1842 } 1843 1844 __set_bit(rel_cid, p_map->cid_map); 1845 1846 *p_cid = rel_cid + p_map->start_cid; 1847 1848 DP_VERBOSE(p_hwfn, QED_MSG_CXT, 1849 "Acquired cid 0x%08x [rel. %08x] vfid %02x type %d\n", 1850 *p_cid, rel_cid, vfid, type); 1851 1852 return 0; 1853 } 1854 1855 int qed_cxt_acquire_cid(struct qed_hwfn *p_hwfn, 1856 enum protocol_type type, u32 *p_cid) 1857 { 1858 return _qed_cxt_acquire_cid(p_hwfn, type, p_cid, QED_CXT_PF_CID); 1859 } 1860 1861 static bool qed_cxt_test_cid_acquired(struct qed_hwfn *p_hwfn, 1862 u32 cid, 1863 u8 vfid, 1864 enum protocol_type *p_type, 1865 struct qed_cid_acquired_map **pp_map) 1866 { 1867 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1868 u32 rel_cid; 1869 1870 /* Iterate over protocols and find matching cid range */ 1871 for (*p_type = 0; *p_type < MAX_CONN_TYPES; (*p_type)++) { 1872 if (vfid == QED_CXT_PF_CID) 1873 *pp_map = &p_mngr->acquired[*p_type]; 1874 else 1875 *pp_map = &p_mngr->acquired_vf[*p_type][vfid]; 1876 1877 if (!((*pp_map)->cid_map)) 1878 continue; 1879 if (cid >= (*pp_map)->start_cid && 1880 cid < (*pp_map)->start_cid + (*pp_map)->max_count) 1881 break; 1882 } 1883 1884 if (*p_type == MAX_CONN_TYPES) { 1885 DP_NOTICE(p_hwfn, "Invalid CID %d vfid %02x", cid, vfid); 1886 goto fail; 1887 } 1888 1889 rel_cid = cid - (*pp_map)->start_cid; 1890 if (!test_bit(rel_cid, (*pp_map)->cid_map)) { 1891 DP_NOTICE(p_hwfn, "CID %d [vifd %02x] not acquired", 1892 cid, vfid); 1893 goto fail; 1894 } 1895 1896 return true; 1897 fail: 1898 *p_type = MAX_CONN_TYPES; 1899 *pp_map = NULL; 1900 return false; 1901 } 1902 1903 void _qed_cxt_release_cid(struct qed_hwfn *p_hwfn, u32 cid, u8 vfid) 1904 { 1905 struct qed_cid_acquired_map *p_map = NULL; 1906 enum protocol_type type; 1907 bool b_acquired; 1908 u32 rel_cid; 1909 1910 if (vfid != QED_CXT_PF_CID && vfid > MAX_NUM_VFS) { 1911 DP_NOTICE(p_hwfn, 1912 "Trying to return incorrect CID belonging to VF %02x\n", 1913 vfid); 1914 return; 1915 } 1916 1917 /* Test acquired and find matching per-protocol map */ 1918 b_acquired = qed_cxt_test_cid_acquired(p_hwfn, cid, vfid, 1919 &type, &p_map); 1920 1921 if (!b_acquired) 1922 return; 1923 1924 rel_cid = cid - p_map->start_cid; 1925 clear_bit(rel_cid, p_map->cid_map); 1926 1927 DP_VERBOSE(p_hwfn, QED_MSG_CXT, 1928 "Released CID 0x%08x [rel. %08x] vfid %02x type %d\n", 1929 cid, rel_cid, vfid, type); 1930 } 1931 1932 void qed_cxt_release_cid(struct qed_hwfn *p_hwfn, u32 cid) 1933 { 1934 _qed_cxt_release_cid(p_hwfn, cid, QED_CXT_PF_CID); 1935 } 1936 1937 int qed_cxt_get_cid_info(struct qed_hwfn *p_hwfn, struct qed_cxt_info *p_info) 1938 { 1939 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 1940 struct qed_cid_acquired_map *p_map = NULL; 1941 u32 conn_cxt_size, hw_p_size, cxts_per_p, line; 1942 enum protocol_type type; 1943 bool b_acquired; 1944 1945 /* Test acquired and find matching per-protocol map */ 1946 b_acquired = qed_cxt_test_cid_acquired(p_hwfn, p_info->iid, 1947 QED_CXT_PF_CID, &type, &p_map); 1948 1949 if (!b_acquired) 1950 return -EINVAL; 1951 1952 /* set the protocl type */ 1953 p_info->type = type; 1954 1955 /* compute context virtual pointer */ 1956 hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val; 1957 1958 conn_cxt_size = CONN_CXT_SIZE(p_hwfn); 1959 cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size; 1960 line = p_info->iid / cxts_per_p; 1961 1962 /* Make sure context is allocated (dynamic allocation) */ 1963 if (!p_mngr->ilt_shadow[line].virt_addr) 1964 return -EINVAL; 1965 1966 p_info->p_cxt = p_mngr->ilt_shadow[line].virt_addr + 1967 p_info->iid % cxts_per_p * conn_cxt_size; 1968 1969 DP_VERBOSE(p_hwfn, (QED_MSG_ILT | QED_MSG_CXT), 1970 "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n", 1971 p_info->iid / cxts_per_p, p_info->p_cxt, p_info->iid); 1972 1973 return 0; 1974 } 1975 1976 static void qed_rdma_set_pf_params(struct qed_hwfn *p_hwfn, 1977 struct qed_rdma_pf_params *p_params, 1978 u32 num_tasks) 1979 { 1980 u32 num_cons, num_qps; 1981 enum protocol_type proto; 1982 1983 if (p_hwfn->mcp_info->func_info.protocol == QED_PCI_ETH_RDMA) { 1984 DP_NOTICE(p_hwfn, 1985 "Current day drivers don't support RoCE & iWARP simultaneously on the same PF. Default to RoCE-only\n"); 1986 p_hwfn->hw_info.personality = QED_PCI_ETH_ROCE; 1987 } 1988 1989 switch (p_hwfn->hw_info.personality) { 1990 case QED_PCI_ETH_IWARP: 1991 /* Each QP requires one connection */ 1992 num_cons = min_t(u32, IWARP_MAX_QPS, p_params->num_qps); 1993 proto = PROTOCOLID_IWARP; 1994 break; 1995 case QED_PCI_ETH_ROCE: 1996 num_qps = min_t(u32, ROCE_MAX_QPS, p_params->num_qps); 1997 num_cons = num_qps * 2; /* each QP requires two connections */ 1998 proto = PROTOCOLID_ROCE; 1999 break; 2000 default: 2001 return; 2002 } 2003 2004 if (num_cons && num_tasks) { 2005 u32 num_srqs, num_xrc_srqs; 2006 2007 qed_cxt_set_proto_cid_count(p_hwfn, proto, num_cons, 0); 2008 2009 /* Deliberatly passing ROCE for tasks id. This is because 2010 * iWARP / RoCE share the task id. 2011 */ 2012 qed_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_ROCE, 2013 QED_CXT_ROCE_TID_SEG, 1, 2014 num_tasks, false); 2015 2016 num_srqs = min_t(u32, QED_RDMA_MAX_SRQS, p_params->num_srqs); 2017 2018 /* XRC SRQs populate a single ILT page */ 2019 num_xrc_srqs = qed_cxt_xrc_srqs_per_page(p_hwfn); 2020 2021 qed_cxt_set_srq_count(p_hwfn, num_srqs, num_xrc_srqs); 2022 } else { 2023 DP_INFO(p_hwfn->cdev, 2024 "RDMA personality used without setting params!\n"); 2025 } 2026 } 2027 2028 int qed_cxt_set_pf_params(struct qed_hwfn *p_hwfn, u32 rdma_tasks) 2029 { 2030 /* Set the number of required CORE connections */ 2031 u32 core_cids = 1; /* SPQ */ 2032 2033 if (p_hwfn->using_ll2) 2034 core_cids += 4; 2035 qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0); 2036 2037 switch (p_hwfn->hw_info.personality) { 2038 case QED_PCI_ETH_RDMA: 2039 case QED_PCI_ETH_IWARP: 2040 case QED_PCI_ETH_ROCE: 2041 { 2042 qed_rdma_set_pf_params(p_hwfn, 2043 &p_hwfn-> 2044 pf_params.rdma_pf_params, 2045 rdma_tasks); 2046 /* no need for break since RoCE coexist with Ethernet */ 2047 } 2048 /* fall through */ 2049 case QED_PCI_ETH: 2050 { 2051 struct qed_eth_pf_params *p_params = 2052 &p_hwfn->pf_params.eth_pf_params; 2053 2054 if (!p_params->num_vf_cons) 2055 p_params->num_vf_cons = 2056 ETH_PF_PARAMS_VF_CONS_DEFAULT; 2057 qed_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH, 2058 p_params->num_cons, 2059 p_params->num_vf_cons); 2060 p_hwfn->p_cxt_mngr->arfs_count = p_params->num_arfs_filters; 2061 break; 2062 } 2063 case QED_PCI_FCOE: 2064 { 2065 struct qed_fcoe_pf_params *p_params; 2066 2067 p_params = &p_hwfn->pf_params.fcoe_pf_params; 2068 2069 if (p_params->num_cons && p_params->num_tasks) { 2070 qed_cxt_set_proto_cid_count(p_hwfn, 2071 PROTOCOLID_FCOE, 2072 p_params->num_cons, 2073 0); 2074 2075 qed_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_FCOE, 2076 QED_CXT_FCOE_TID_SEG, 0, 2077 p_params->num_tasks, true); 2078 } else { 2079 DP_INFO(p_hwfn->cdev, 2080 "Fcoe personality used without setting params!\n"); 2081 } 2082 break; 2083 } 2084 case QED_PCI_ISCSI: 2085 { 2086 struct qed_iscsi_pf_params *p_params; 2087 2088 p_params = &p_hwfn->pf_params.iscsi_pf_params; 2089 2090 if (p_params->num_cons && p_params->num_tasks) { 2091 qed_cxt_set_proto_cid_count(p_hwfn, 2092 PROTOCOLID_ISCSI, 2093 p_params->num_cons, 2094 0); 2095 2096 qed_cxt_set_proto_tid_count(p_hwfn, 2097 PROTOCOLID_ISCSI, 2098 QED_CXT_ISCSI_TID_SEG, 2099 0, 2100 p_params->num_tasks, 2101 true); 2102 } else { 2103 DP_INFO(p_hwfn->cdev, 2104 "Iscsi personality used without setting params!\n"); 2105 } 2106 break; 2107 } 2108 default: 2109 return -EINVAL; 2110 } 2111 2112 return 0; 2113 } 2114 2115 int qed_cxt_get_tid_mem_info(struct qed_hwfn *p_hwfn, 2116 struct qed_tid_mem *p_info) 2117 { 2118 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 2119 u32 proto, seg, total_lines, i, shadow_line; 2120 struct qed_ilt_client_cfg *p_cli; 2121 struct qed_ilt_cli_blk *p_fl_seg; 2122 struct qed_tid_seg *p_seg_info; 2123 2124 /* Verify the personality */ 2125 switch (p_hwfn->hw_info.personality) { 2126 case QED_PCI_FCOE: 2127 proto = PROTOCOLID_FCOE; 2128 seg = QED_CXT_FCOE_TID_SEG; 2129 break; 2130 case QED_PCI_ISCSI: 2131 proto = PROTOCOLID_ISCSI; 2132 seg = QED_CXT_ISCSI_TID_SEG; 2133 break; 2134 default: 2135 return -EINVAL; 2136 } 2137 2138 p_cli = &p_mngr->clients[ILT_CLI_CDUT]; 2139 if (!p_cli->active) 2140 return -EINVAL; 2141 2142 p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg]; 2143 if (!p_seg_info->has_fl_mem) 2144 return -EINVAL; 2145 2146 p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)]; 2147 total_lines = DIV_ROUND_UP(p_fl_seg->total_size, 2148 p_fl_seg->real_size_in_page); 2149 2150 for (i = 0; i < total_lines; i++) { 2151 shadow_line = i + p_fl_seg->start_line - 2152 p_hwfn->p_cxt_mngr->pf_start_line; 2153 p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].virt_addr; 2154 } 2155 p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) - 2156 p_fl_seg->real_size_in_page; 2157 p_info->tid_size = p_mngr->task_type_size[p_seg_info->type]; 2158 p_info->num_tids_per_block = p_fl_seg->real_size_in_page / 2159 p_info->tid_size; 2160 2161 return 0; 2162 } 2163 2164 /* This function is very RoCE oriented, if another protocol in the future 2165 * will want this feature we'll need to modify the function to be more generic 2166 */ 2167 int 2168 qed_cxt_dynamic_ilt_alloc(struct qed_hwfn *p_hwfn, 2169 enum qed_cxt_elem_type elem_type, u32 iid) 2170 { 2171 u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line; 2172 struct qed_ilt_client_cfg *p_cli; 2173 struct qed_ilt_cli_blk *p_blk; 2174 struct qed_ptt *p_ptt; 2175 dma_addr_t p_phys; 2176 u64 ilt_hw_entry; 2177 void *p_virt; 2178 int rc = 0; 2179 2180 switch (elem_type) { 2181 case QED_ELEM_CXT: 2182 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 2183 elem_size = CONN_CXT_SIZE(p_hwfn); 2184 p_blk = &p_cli->pf_blks[CDUC_BLK]; 2185 break; 2186 case QED_ELEM_SRQ: 2187 /* The first ILT page is not used for regular SRQs. Skip it. */ 2188 iid += p_hwfn->p_cxt_mngr->xrc_srq_count; 2189 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM]; 2190 elem_size = SRQ_CXT_SIZE; 2191 p_blk = &p_cli->pf_blks[SRQ_BLK]; 2192 break; 2193 case QED_ELEM_XRC_SRQ: 2194 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM]; 2195 elem_size = XRC_SRQ_CXT_SIZE; 2196 p_blk = &p_cli->pf_blks[SRQ_BLK]; 2197 break; 2198 case QED_ELEM_TASK: 2199 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2200 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn); 2201 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)]; 2202 break; 2203 default: 2204 DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type); 2205 return -EINVAL; 2206 } 2207 2208 /* Calculate line in ilt */ 2209 hw_p_size = p_cli->p_size.val; 2210 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size; 2211 line = p_blk->start_line + (iid / elems_per_p); 2212 shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line; 2213 2214 /* If line is already allocated, do nothing, otherwise allocate it and 2215 * write it to the PSWRQ2 registers. 2216 * This section can be run in parallel from different contexts and thus 2217 * a mutex protection is needed. 2218 */ 2219 2220 mutex_lock(&p_hwfn->p_cxt_mngr->mutex); 2221 2222 if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].virt_addr) 2223 goto out0; 2224 2225 p_ptt = qed_ptt_acquire(p_hwfn); 2226 if (!p_ptt) { 2227 DP_NOTICE(p_hwfn, 2228 "QED_TIME_OUT on ptt acquire - dynamic allocation"); 2229 rc = -EBUSY; 2230 goto out0; 2231 } 2232 2233 p_virt = dma_alloc_coherent(&p_hwfn->cdev->pdev->dev, 2234 p_blk->real_size_in_page, &p_phys, 2235 GFP_KERNEL); 2236 if (!p_virt) { 2237 rc = -ENOMEM; 2238 goto out1; 2239 } 2240 2241 /* configuration of refTagMask to 0xF is required for RoCE DIF MR only, 2242 * to compensate for a HW bug, but it is configured even if DIF is not 2243 * enabled. This is harmless and allows us to avoid a dedicated API. We 2244 * configure the field for all of the contexts on the newly allocated 2245 * page. 2246 */ 2247 if (elem_type == QED_ELEM_TASK) { 2248 u32 elem_i; 2249 u8 *elem_start = (u8 *)p_virt; 2250 union type1_task_context *elem; 2251 2252 for (elem_i = 0; elem_i < elems_per_p; elem_i++) { 2253 elem = (union type1_task_context *)elem_start; 2254 SET_FIELD(elem->roce_ctx.tdif_context.flags1, 2255 TDIF_TASK_CONTEXT_REF_TAG_MASK, 0xf); 2256 elem_start += TYPE1_TASK_CXT_SIZE(p_hwfn); 2257 } 2258 } 2259 2260 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].virt_addr = p_virt; 2261 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].phys_addr = p_phys; 2262 p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size = 2263 p_blk->real_size_in_page; 2264 2265 /* compute absolute offset */ 2266 reg_offset = PSWRQ2_REG_ILT_MEMORY + 2267 (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS); 2268 2269 ilt_hw_entry = 0; 2270 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL); 2271 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR, 2272 (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].phys_addr 2273 >> 12)); 2274 2275 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */ 2276 qed_dmae_host2grc(p_hwfn, p_ptt, (u64) (uintptr_t)&ilt_hw_entry, 2277 reg_offset, sizeof(ilt_hw_entry) / sizeof(u32), 2278 NULL); 2279 2280 if (elem_type == QED_ELEM_CXT) { 2281 u32 last_cid_allocated = (1 + (iid / elems_per_p)) * 2282 elems_per_p; 2283 2284 /* Update the relevant register in the parser */ 2285 qed_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF, 2286 last_cid_allocated - 1); 2287 2288 if (!p_hwfn->b_rdma_enabled_in_prs) { 2289 /* Enable RDMA search */ 2290 qed_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1); 2291 p_hwfn->b_rdma_enabled_in_prs = true; 2292 } 2293 } 2294 2295 out1: 2296 qed_ptt_release(p_hwfn, p_ptt); 2297 out0: 2298 mutex_unlock(&p_hwfn->p_cxt_mngr->mutex); 2299 2300 return rc; 2301 } 2302 2303 /* This function is very RoCE oriented, if another protocol in the future 2304 * will want this feature we'll need to modify the function to be more generic 2305 */ 2306 static int 2307 qed_cxt_free_ilt_range(struct qed_hwfn *p_hwfn, 2308 enum qed_cxt_elem_type elem_type, 2309 u32 start_iid, u32 count) 2310 { 2311 u32 start_line, end_line, shadow_start_line, shadow_end_line; 2312 u32 reg_offset, elem_size, hw_p_size, elems_per_p; 2313 struct qed_ilt_client_cfg *p_cli; 2314 struct qed_ilt_cli_blk *p_blk; 2315 u32 end_iid = start_iid + count; 2316 struct qed_ptt *p_ptt; 2317 u64 ilt_hw_entry = 0; 2318 u32 i; 2319 2320 switch (elem_type) { 2321 case QED_ELEM_CXT: 2322 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC]; 2323 elem_size = CONN_CXT_SIZE(p_hwfn); 2324 p_blk = &p_cli->pf_blks[CDUC_BLK]; 2325 break; 2326 case QED_ELEM_SRQ: 2327 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM]; 2328 elem_size = SRQ_CXT_SIZE; 2329 p_blk = &p_cli->pf_blks[SRQ_BLK]; 2330 break; 2331 case QED_ELEM_TASK: 2332 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2333 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn); 2334 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(QED_CXT_ROCE_TID_SEG)]; 2335 break; 2336 default: 2337 DP_NOTICE(p_hwfn, "-EINVALID elem type = %d", elem_type); 2338 return -EINVAL; 2339 } 2340 2341 /* Calculate line in ilt */ 2342 hw_p_size = p_cli->p_size.val; 2343 elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size; 2344 start_line = p_blk->start_line + (start_iid / elems_per_p); 2345 end_line = p_blk->start_line + (end_iid / elems_per_p); 2346 if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p)) 2347 end_line--; 2348 2349 shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line; 2350 shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line; 2351 2352 p_ptt = qed_ptt_acquire(p_hwfn); 2353 if (!p_ptt) { 2354 DP_NOTICE(p_hwfn, 2355 "QED_TIME_OUT on ptt acquire - dynamic allocation"); 2356 return -EBUSY; 2357 } 2358 2359 for (i = shadow_start_line; i < shadow_end_line; i++) { 2360 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].virt_addr) 2361 continue; 2362 2363 dma_free_coherent(&p_hwfn->cdev->pdev->dev, 2364 p_hwfn->p_cxt_mngr->ilt_shadow[i].size, 2365 p_hwfn->p_cxt_mngr->ilt_shadow[i].virt_addr, 2366 p_hwfn->p_cxt_mngr->ilt_shadow[i].phys_addr); 2367 2368 p_hwfn->p_cxt_mngr->ilt_shadow[i].virt_addr = NULL; 2369 p_hwfn->p_cxt_mngr->ilt_shadow[i].phys_addr = 0; 2370 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0; 2371 2372 /* compute absolute offset */ 2373 reg_offset = PSWRQ2_REG_ILT_MEMORY + 2374 ((start_line++) * ILT_REG_SIZE_IN_BYTES * 2375 ILT_ENTRY_IN_REGS); 2376 2377 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a 2378 * wide-bus. 2379 */ 2380 qed_dmae_host2grc(p_hwfn, p_ptt, 2381 (u64) (uintptr_t) &ilt_hw_entry, 2382 reg_offset, 2383 sizeof(ilt_hw_entry) / sizeof(u32), 2384 NULL); 2385 } 2386 2387 qed_ptt_release(p_hwfn, p_ptt); 2388 2389 return 0; 2390 } 2391 2392 int qed_cxt_free_proto_ilt(struct qed_hwfn *p_hwfn, enum protocol_type proto) 2393 { 2394 int rc; 2395 u32 cid; 2396 2397 /* Free Connection CXT */ 2398 rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_CXT, 2399 qed_cxt_get_proto_cid_start(p_hwfn, 2400 proto), 2401 qed_cxt_get_proto_cid_count(p_hwfn, 2402 proto, &cid)); 2403 2404 if (rc) 2405 return rc; 2406 2407 /* Free Task CXT ( Intentionally RoCE as task-id is shared between 2408 * RoCE and iWARP ) 2409 */ 2410 proto = PROTOCOLID_ROCE; 2411 rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_TASK, 0, 2412 qed_cxt_get_proto_tid_count(p_hwfn, proto)); 2413 if (rc) 2414 return rc; 2415 2416 /* Free TSDM CXT */ 2417 rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_XRC_SRQ, 0, 2418 p_hwfn->p_cxt_mngr->xrc_srq_count); 2419 2420 rc = qed_cxt_free_ilt_range(p_hwfn, QED_ELEM_SRQ, 2421 p_hwfn->p_cxt_mngr->xrc_srq_count, 2422 p_hwfn->p_cxt_mngr->srq_count); 2423 2424 return rc; 2425 } 2426 2427 int qed_cxt_get_task_ctx(struct qed_hwfn *p_hwfn, 2428 u32 tid, u8 ctx_type, void **pp_task_ctx) 2429 { 2430 struct qed_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr; 2431 struct qed_ilt_client_cfg *p_cli; 2432 struct qed_tid_seg *p_seg_info; 2433 struct qed_ilt_cli_blk *p_seg; 2434 u32 num_tids_per_block; 2435 u32 tid_size, ilt_idx; 2436 u32 total_lines; 2437 u32 proto, seg; 2438 2439 /* Verify the personality */ 2440 switch (p_hwfn->hw_info.personality) { 2441 case QED_PCI_FCOE: 2442 proto = PROTOCOLID_FCOE; 2443 seg = QED_CXT_FCOE_TID_SEG; 2444 break; 2445 case QED_PCI_ISCSI: 2446 proto = PROTOCOLID_ISCSI; 2447 seg = QED_CXT_ISCSI_TID_SEG; 2448 break; 2449 default: 2450 return -EINVAL; 2451 } 2452 2453 p_cli = &p_mngr->clients[ILT_CLI_CDUT]; 2454 if (!p_cli->active) 2455 return -EINVAL; 2456 2457 p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg]; 2458 2459 if (ctx_type == QED_CTX_WORKING_MEM) { 2460 p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)]; 2461 } else if (ctx_type == QED_CTX_FL_MEM) { 2462 if (!p_seg_info->has_fl_mem) 2463 return -EINVAL; 2464 p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)]; 2465 } else { 2466 return -EINVAL; 2467 } 2468 total_lines = DIV_ROUND_UP(p_seg->total_size, p_seg->real_size_in_page); 2469 tid_size = p_mngr->task_type_size[p_seg_info->type]; 2470 num_tids_per_block = p_seg->real_size_in_page / tid_size; 2471 2472 if (total_lines < tid / num_tids_per_block) 2473 return -EINVAL; 2474 2475 ilt_idx = tid / num_tids_per_block + p_seg->start_line - 2476 p_mngr->pf_start_line; 2477 *pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].virt_addr + 2478 (tid % num_tids_per_block) * tid_size; 2479 2480 return 0; 2481 } 2482 2483 static u16 qed_blk_calculate_pages(struct qed_ilt_cli_blk *p_blk) 2484 { 2485 if (p_blk->real_size_in_page == 0) 2486 return 0; 2487 2488 return DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page); 2489 } 2490 2491 u16 qed_get_cdut_num_pf_init_pages(struct qed_hwfn *p_hwfn) 2492 { 2493 struct qed_ilt_client_cfg *p_cli; 2494 struct qed_ilt_cli_blk *p_blk; 2495 u16 i, pages = 0; 2496 2497 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2498 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 2499 p_blk = &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)]; 2500 pages += qed_blk_calculate_pages(p_blk); 2501 } 2502 2503 return pages; 2504 } 2505 2506 u16 qed_get_cdut_num_vf_init_pages(struct qed_hwfn *p_hwfn) 2507 { 2508 struct qed_ilt_client_cfg *p_cli; 2509 struct qed_ilt_cli_blk *p_blk; 2510 u16 i, pages = 0; 2511 2512 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2513 for (i = 0; i < NUM_TASK_VF_SEGMENTS; i++) { 2514 p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(i, VF)]; 2515 pages += qed_blk_calculate_pages(p_blk); 2516 } 2517 2518 return pages; 2519 } 2520 2521 u16 qed_get_cdut_num_pf_work_pages(struct qed_hwfn *p_hwfn) 2522 { 2523 struct qed_ilt_client_cfg *p_cli; 2524 struct qed_ilt_cli_blk *p_blk; 2525 u16 i, pages = 0; 2526 2527 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2528 for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) { 2529 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(i)]; 2530 pages += qed_blk_calculate_pages(p_blk); 2531 } 2532 2533 return pages; 2534 } 2535 2536 u16 qed_get_cdut_num_vf_work_pages(struct qed_hwfn *p_hwfn) 2537 { 2538 struct qed_ilt_client_cfg *p_cli; 2539 struct qed_ilt_cli_blk *p_blk; 2540 u16 pages = 0, i; 2541 2542 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT]; 2543 for (i = 0; i < NUM_TASK_VF_SEGMENTS; i++) { 2544 p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(i)]; 2545 pages += qed_blk_calculate_pages(p_blk); 2546 } 2547 2548 return pages; 2549 } 2550