1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015 QLogic Corporation 3 * 4 * This software is available under the terms of the GNU General Public License 5 * (GPL) Version 2, available from the file COPYING in the main directory of 6 * this source tree. 7 */ 8 9 #ifndef _QED_H 10 #define _QED_H 11 12 #include <linux/types.h> 13 #include <linux/io.h> 14 #include <linux/delay.h> 15 #include <linux/firmware.h> 16 #include <linux/interrupt.h> 17 #include <linux/list.h> 18 #include <linux/mutex.h> 19 #include <linux/pci.h> 20 #include <linux/slab.h> 21 #include <linux/string.h> 22 #include <linux/workqueue.h> 23 #include <linux/zlib.h> 24 #include <linux/hashtable.h> 25 #include <linux/qed/qed_if.h> 26 #include "qed_debug.h" 27 #include "qed_hsi.h" 28 29 extern const struct qed_common_ops qed_common_ops_pass; 30 #define DRV_MODULE_VERSION "8.10.9.20" 31 32 #define MAX_HWFNS_PER_DEVICE (4) 33 #define NAME_SIZE 16 34 #define VER_SIZE 16 35 36 #define QED_WFQ_UNIT 100 37 38 #define QED_WID_SIZE (1024) 39 #define QED_PF_DEMS_SIZE (4) 40 41 /* cau states */ 42 enum qed_coalescing_mode { 43 QED_COAL_MODE_DISABLE, 44 QED_COAL_MODE_ENABLE 45 }; 46 47 struct qed_eth_cb_ops; 48 struct qed_dev_info; 49 union qed_mcp_protocol_stats; 50 enum qed_mcp_protocol_type; 51 52 /* helpers */ 53 static inline u32 qed_db_addr(u32 cid, u32 DEMS) 54 { 55 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 56 (cid * QED_PF_DEMS_SIZE); 57 58 return db_addr; 59 } 60 61 static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS) 62 { 63 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 64 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); 65 66 return db_addr; 67 } 68 69 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ 70 ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \ 71 ~((1 << (p_hwfn->cdev->cache_shift)) - 1)) 72 73 #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++) 74 75 #define D_TRINE(val, cond1, cond2, true1, true2, def) \ 76 (val == (cond1) ? true1 : \ 77 (val == (cond2) ? true2 : def)) 78 79 /* forward */ 80 struct qed_ptt_pool; 81 struct qed_spq; 82 struct qed_sb_info; 83 struct qed_sb_attn_info; 84 struct qed_cxt_mngr; 85 struct qed_sb_sp_info; 86 struct qed_ll2_info; 87 struct qed_mcp_info; 88 89 struct qed_rt_data { 90 u32 *init_val; 91 bool *b_valid; 92 }; 93 94 enum qed_tunn_mode { 95 QED_MODE_L2GENEVE_TUNN, 96 QED_MODE_IPGENEVE_TUNN, 97 QED_MODE_L2GRE_TUNN, 98 QED_MODE_IPGRE_TUNN, 99 QED_MODE_VXLAN_TUNN, 100 }; 101 102 enum qed_tunn_clss { 103 QED_TUNN_CLSS_MAC_VLAN, 104 QED_TUNN_CLSS_MAC_VNI, 105 QED_TUNN_CLSS_INNER_MAC_VLAN, 106 QED_TUNN_CLSS_INNER_MAC_VNI, 107 MAX_QED_TUNN_CLSS, 108 }; 109 110 struct qed_tunn_start_params { 111 unsigned long tunn_mode; 112 u16 vxlan_udp_port; 113 u16 geneve_udp_port; 114 u8 update_vxlan_udp_port; 115 u8 update_geneve_udp_port; 116 u8 tunn_clss_vxlan; 117 u8 tunn_clss_l2geneve; 118 u8 tunn_clss_ipgeneve; 119 u8 tunn_clss_l2gre; 120 u8 tunn_clss_ipgre; 121 }; 122 123 struct qed_tunn_update_params { 124 unsigned long tunn_mode_update_mask; 125 unsigned long tunn_mode; 126 u16 vxlan_udp_port; 127 u16 geneve_udp_port; 128 u8 update_rx_pf_clss; 129 u8 update_tx_pf_clss; 130 u8 update_vxlan_udp_port; 131 u8 update_geneve_udp_port; 132 u8 tunn_clss_vxlan; 133 u8 tunn_clss_l2geneve; 134 u8 tunn_clss_ipgeneve; 135 u8 tunn_clss_l2gre; 136 u8 tunn_clss_ipgre; 137 }; 138 139 /* The PCI personality is not quite synonymous to protocol ID: 140 * 1. All personalities need CORE connections 141 * 2. The Ethernet personality may support also the RoCE protocol 142 */ 143 enum qed_pci_personality { 144 QED_PCI_ETH, 145 QED_PCI_ISCSI, 146 QED_PCI_ETH_ROCE, 147 QED_PCI_DEFAULT /* default in shmem */ 148 }; 149 150 /* All VFs are symmetric, all counters are PF + all VFs */ 151 struct qed_qm_iids { 152 u32 cids; 153 u32 vf_cids; 154 u32 tids; 155 }; 156 157 enum QED_RESOURCES { 158 QED_SB, 159 QED_L2_QUEUE, 160 QED_VPORT, 161 QED_RSS_ENG, 162 QED_PQ, 163 QED_RL, 164 QED_MAC, 165 QED_VLAN, 166 QED_RDMA_CNQ_RAM, 167 QED_ILT, 168 QED_LL2_QUEUE, 169 QED_RDMA_STATS_QUEUE, 170 QED_MAX_RESC, 171 }; 172 173 enum QED_FEATURE { 174 QED_PF_L2_QUE, 175 QED_VF, 176 QED_RDMA_CNQ, 177 QED_MAX_FEATURES, 178 }; 179 180 enum QED_PORT_MODE { 181 QED_PORT_MODE_DE_2X40G, 182 QED_PORT_MODE_DE_2X50G, 183 QED_PORT_MODE_DE_1X100G, 184 QED_PORT_MODE_DE_4X10G_F, 185 QED_PORT_MODE_DE_4X10G_E, 186 QED_PORT_MODE_DE_4X20G, 187 QED_PORT_MODE_DE_1X40G, 188 QED_PORT_MODE_DE_2X25G, 189 QED_PORT_MODE_DE_1X25G 190 }; 191 192 enum qed_dev_cap { 193 QED_DEV_CAP_ETH, 194 QED_DEV_CAP_ISCSI, 195 QED_DEV_CAP_ROCE, 196 }; 197 198 struct qed_hw_info { 199 /* PCI personality */ 200 enum qed_pci_personality personality; 201 202 /* Resource Allocation scheme results */ 203 u32 resc_start[QED_MAX_RESC]; 204 u32 resc_num[QED_MAX_RESC]; 205 u32 feat_num[QED_MAX_FEATURES]; 206 207 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) 208 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) 209 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ 210 RESC_NUM(_p_hwfn, resc)) 211 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) 212 213 u8 num_tc; 214 u8 offload_tc; 215 u8 non_offload_tc; 216 217 u32 concrete_fid; 218 u16 opaque_fid; 219 u16 ovlan; 220 u32 part_num[4]; 221 222 unsigned char hw_mac_addr[ETH_ALEN]; 223 224 struct qed_igu_info *p_igu_info; 225 226 u32 port_mode; 227 u32 hw_mode; 228 unsigned long device_capabilities; 229 }; 230 231 struct qed_hw_cid_data { 232 u32 cid; 233 bool b_cid_allocated; 234 235 /* Additional identifiers */ 236 u16 opaque_fid; 237 u8 vport_id; 238 }; 239 240 /* maximun size of read/write commands (HW limit) */ 241 #define DMAE_MAX_RW_SIZE 0x2000 242 243 struct qed_dmae_info { 244 /* Mutex for synchronizing access to functions */ 245 struct mutex mutex; 246 247 u8 channel; 248 249 dma_addr_t completion_word_phys_addr; 250 251 /* The memory location where the DMAE writes the completion 252 * value when an operation is finished on this context. 253 */ 254 u32 *p_completion_word; 255 256 dma_addr_t intermediate_buffer_phys_addr; 257 258 /* An intermediate buffer for DMAE operations that use virtual 259 * addresses - data is DMA'd to/from this buffer and then 260 * memcpy'd to/from the virtual address 261 */ 262 u32 *p_intermediate_buffer; 263 264 dma_addr_t dmae_cmd_phys_addr; 265 struct dmae_cmd *p_dmae_cmd; 266 }; 267 268 struct qed_wfq_data { 269 /* when feature is configured for at least 1 vport */ 270 u32 min_speed; 271 bool configured; 272 }; 273 274 struct qed_qm_info { 275 struct init_qm_pq_params *qm_pq_params; 276 struct init_qm_vport_params *qm_vport_params; 277 struct init_qm_port_params *qm_port_params; 278 u16 start_pq; 279 u8 start_vport; 280 u8 pure_lb_pq; 281 u8 offload_pq; 282 u8 pure_ack_pq; 283 u8 ooo_pq; 284 u8 vf_queues_offset; 285 u16 num_pqs; 286 u16 num_vf_pqs; 287 u8 num_vports; 288 u8 max_phys_tcs_per_port; 289 bool pf_rl_en; 290 bool pf_wfq_en; 291 bool vport_rl_en; 292 bool vport_wfq_en; 293 u8 pf_wfq; 294 u32 pf_rl; 295 struct qed_wfq_data *wfq_data; 296 u8 num_pf_rls; 297 }; 298 299 struct storm_stats { 300 u32 address; 301 u32 len; 302 }; 303 304 struct qed_storm_stats { 305 struct storm_stats mstats; 306 struct storm_stats pstats; 307 struct storm_stats tstats; 308 struct storm_stats ustats; 309 }; 310 311 struct qed_fw_data { 312 struct fw_ver_info *fw_ver_info; 313 const u8 *modes_tree_buf; 314 union init_op *init_ops; 315 const u32 *arr_data; 316 u32 init_ops_size; 317 }; 318 319 struct qed_simd_fp_handler { 320 void *token; 321 void (*func)(void *); 322 }; 323 324 struct qed_hwfn { 325 struct qed_dev *cdev; 326 u8 my_id; /* ID inside the PF */ 327 #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) 328 u8 rel_pf_id; /* Relative to engine*/ 329 u8 abs_pf_id; 330 #define QED_PATH_ID(_p_hwfn) ((_p_hwfn)->abs_pf_id & 1) 331 u8 port_id; 332 bool b_active; 333 334 u32 dp_module; 335 u8 dp_level; 336 char name[NAME_SIZE]; 337 338 bool first_on_engine; 339 bool hw_init_done; 340 341 u8 num_funcs_on_engine; 342 u8 enabled_func_idx; 343 344 /* BAR access */ 345 void __iomem *regview; 346 void __iomem *doorbells; 347 u64 db_phys_addr; 348 unsigned long db_size; 349 350 /* PTT pool */ 351 struct qed_ptt_pool *p_ptt_pool; 352 353 /* HW info */ 354 struct qed_hw_info hw_info; 355 356 /* rt_array (for init-tool) */ 357 struct qed_rt_data rt_data; 358 359 /* SPQ */ 360 struct qed_spq *p_spq; 361 362 /* EQ */ 363 struct qed_eq *p_eq; 364 365 /* Consolidate Q*/ 366 struct qed_consq *p_consq; 367 368 /* Slow-Path definitions */ 369 struct tasklet_struct *sp_dpc; 370 bool b_sp_dpc_enabled; 371 372 struct qed_ptt *p_main_ptt; 373 struct qed_ptt *p_dpc_ptt; 374 375 struct qed_sb_sp_info *p_sp_sb; 376 struct qed_sb_attn_info *p_sb_attn; 377 378 /* Protocol related */ 379 bool using_ll2; 380 struct qed_ll2_info *p_ll2_info; 381 struct qed_rdma_info *p_rdma_info; 382 struct qed_pf_params pf_params; 383 384 bool b_rdma_enabled_in_prs; 385 u32 rdma_prs_search_reg; 386 387 /* Array of sb_info of all status blocks */ 388 struct qed_sb_info *sbs_info[MAX_SB_PER_PF_MIMD]; 389 u16 num_sbs; 390 391 struct qed_cxt_mngr *p_cxt_mngr; 392 393 /* Flag indicating whether interrupts are enabled or not*/ 394 bool b_int_enabled; 395 bool b_int_requested; 396 397 /* True if the driver requests for the link */ 398 bool b_drv_link_init; 399 400 struct qed_vf_iov *vf_iov_info; 401 struct qed_pf_iov *pf_iov_info; 402 struct qed_mcp_info *mcp_info; 403 404 struct qed_dcbx_info *p_dcbx_info; 405 406 struct qed_hw_cid_data *p_tx_cids; 407 struct qed_hw_cid_data *p_rx_cids; 408 409 struct qed_dmae_info dmae_info; 410 411 /* QM init */ 412 struct qed_qm_info qm_info; 413 struct qed_storm_stats storm_stats; 414 415 /* Buffer for unzipping firmware data */ 416 void *unzip_buf; 417 418 struct dbg_tools_data dbg_info; 419 420 /* PWM region specific data */ 421 u32 dpi_size; 422 u32 dpi_count; 423 424 /* This is used to calculate the doorbell address */ 425 u32 dpi_start_offset; 426 427 /* If one of the following is set then EDPM shouldn't be used */ 428 u8 dcbx_no_edpm; 429 u8 db_bar_no_edpm; 430 431 struct qed_simd_fp_handler simd_proto_handler[64]; 432 433 #ifdef CONFIG_QED_SRIOV 434 struct workqueue_struct *iov_wq; 435 struct delayed_work iov_task; 436 unsigned long iov_task_flags; 437 #endif 438 439 struct z_stream_s *stream; 440 struct qed_roce_ll2_info *ll2; 441 }; 442 443 struct pci_params { 444 int pm_cap; 445 446 unsigned long mem_start; 447 unsigned long mem_end; 448 unsigned int irq; 449 u8 pf_num; 450 }; 451 452 struct qed_int_param { 453 u32 int_mode; 454 u8 num_vectors; 455 u8 min_msix_cnt; /* for minimal functionality */ 456 }; 457 458 struct qed_int_params { 459 struct qed_int_param in; 460 struct qed_int_param out; 461 struct msix_entry *msix_table; 462 bool fp_initialized; 463 u8 fp_msix_base; 464 u8 fp_msix_cnt; 465 u8 rdma_msix_base; 466 u8 rdma_msix_cnt; 467 }; 468 469 struct qed_dbg_feature { 470 struct dentry *dentry; 471 u8 *dump_buf; 472 u32 buf_size; 473 u32 dumped_dwords; 474 }; 475 476 struct qed_dbg_params { 477 struct qed_dbg_feature features[DBG_FEATURE_NUM]; 478 u8 engine_for_debug; 479 bool print_data; 480 }; 481 482 struct qed_dev { 483 u32 dp_module; 484 u8 dp_level; 485 char name[NAME_SIZE]; 486 487 u8 type; 488 #define QED_DEV_TYPE_BB (0 << 0) 489 #define QED_DEV_TYPE_AH BIT(0) 490 /* Translate type/revision combo into the proper conditions */ 491 #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB) 492 #define QED_IS_BB_A0(dev) (QED_IS_BB(dev) && \ 493 CHIP_REV_IS_A0(dev)) 494 #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \ 495 CHIP_REV_IS_B0(dev)) 496 #define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH) 497 #define QED_IS_K2(dev) QED_IS_AH(dev) 498 499 #define QED_GET_TYPE(dev) (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \ 500 QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2) 501 502 u16 vendor_id; 503 u16 device_id; 504 505 u16 chip_num; 506 #define CHIP_NUM_MASK 0xffff 507 #define CHIP_NUM_SHIFT 16 508 509 u16 chip_rev; 510 #define CHIP_REV_MASK 0xf 511 #define CHIP_REV_SHIFT 12 512 #define CHIP_REV_IS_A0(_cdev) (!(_cdev)->chip_rev) 513 #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1) 514 515 u16 chip_metal; 516 #define CHIP_METAL_MASK 0xff 517 #define CHIP_METAL_SHIFT 4 518 519 u16 chip_bond_id; 520 #define CHIP_BOND_ID_MASK 0xf 521 #define CHIP_BOND_ID_SHIFT 0 522 523 u8 num_engines; 524 u8 num_ports_in_engines; 525 u8 num_funcs_in_port; 526 527 u8 path_id; 528 enum qed_mf_mode mf_mode; 529 #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT) 530 #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR) 531 #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN) 532 533 int pcie_width; 534 int pcie_speed; 535 u8 ver_str[VER_SIZE]; 536 537 /* Add MF related configuration */ 538 u8 mcp_rev; 539 u8 boot_mode; 540 541 u8 wol; 542 543 u32 int_mode; 544 enum qed_coalescing_mode int_coalescing_mode; 545 u16 rx_coalesce_usecs; 546 u16 tx_coalesce_usecs; 547 548 /* Start Bar offset of first hwfn */ 549 void __iomem *regview; 550 void __iomem *doorbells; 551 u64 db_phys_addr; 552 unsigned long db_size; 553 554 /* PCI */ 555 u8 cache_shift; 556 557 /* Init */ 558 const struct iro *iro_arr; 559 #define IRO (p_hwfn->cdev->iro_arr) 560 561 /* HW functions */ 562 u8 num_hwfns; 563 struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; 564 565 /* SRIOV */ 566 struct qed_hw_sriov_info *p_iov_info; 567 #define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info) 568 569 unsigned long tunn_mode; 570 571 bool b_is_vf; 572 u32 drv_type; 573 struct qed_eth_stats *reset_stats; 574 struct qed_fw_data *fw_data; 575 576 u32 mcp_nvm_resp; 577 578 /* Linux specific here */ 579 struct qede_dev *edev; 580 struct pci_dev *pdev; 581 int msg_enable; 582 583 struct pci_params pci_params; 584 585 struct qed_int_params int_params; 586 587 u8 protocol; 588 #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH) 589 590 /* Callbacks to protocol driver */ 591 union { 592 struct qed_common_cb_ops *common; 593 struct qed_eth_cb_ops *eth; 594 } protocol_ops; 595 void *ops_cookie; 596 597 struct qed_dbg_params dbg_params; 598 599 #ifdef CONFIG_QED_LL2 600 struct qed_cb_ll2_info *ll2; 601 u8 ll2_mac_address[ETH_ALEN]; 602 #endif 603 604 const struct firmware *firmware; 605 606 u32 rdma_max_sge; 607 u32 rdma_max_inline; 608 u32 rdma_max_srq_sge; 609 }; 610 611 #define NUM_OF_VFS(dev) MAX_NUM_VFS_BB 612 #define NUM_OF_L2_QUEUES(dev) MAX_NUM_L2_QUEUES_BB 613 #define NUM_OF_SBS(dev) MAX_SB_PER_PATH_BB 614 #define NUM_OF_ENG_PFS(dev) MAX_NUM_PFS_BB 615 616 /** 617 * @brief qed_concrete_to_sw_fid - get the sw function id from 618 * the concrete value. 619 * 620 * @param concrete_fid 621 * 622 * @return inline u8 623 */ 624 static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev, 625 u32 concrete_fid) 626 { 627 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); 628 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); 629 u8 vf_valid = GET_FIELD(concrete_fid, 630 PXP_CONCRETE_FID_VFVALID); 631 u8 sw_fid; 632 633 if (vf_valid) 634 sw_fid = vfid + MAX_NUM_PFS; 635 else 636 sw_fid = pfid; 637 638 return sw_fid; 639 } 640 641 #define PURE_LB_TC 8 642 #define OOO_LB_TC 9 643 644 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate); 645 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate); 646 647 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 648 #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) 649 650 /* Other Linux specific common definitions */ 651 #define DP_NAME(cdev) ((cdev)->name) 652 653 #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\ 654 (cdev->regview) + \ 655 (offset)) 656 657 #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset)) 658 #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset)) 659 #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset)) 660 661 #define DOORBELL(cdev, db_addr, val) \ 662 writel((u32)val, (void __iomem *)((u8 __iomem *)\ 663 (cdev->doorbells) + (db_addr))) 664 665 /* Prototypes */ 666 int qed_fill_dev_info(struct qed_dev *cdev, 667 struct qed_dev_info *dev_info); 668 void qed_link_update(struct qed_hwfn *hwfn); 669 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, 670 u32 input_len, u8 *input_buf, 671 u32 max_size, u8 *unzip_buf); 672 void qed_get_protocol_stats(struct qed_dev *cdev, 673 enum qed_mcp_protocol_type type, 674 union qed_mcp_protocol_stats *stats); 675 int qed_slowpath_irq_req(struct qed_hwfn *hwfn); 676 677 #endif /* _QED_H */ 678