1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _QED_H 34 #define _QED_H 35 36 #include <linux/types.h> 37 #include <linux/io.h> 38 #include <linux/delay.h> 39 #include <linux/firmware.h> 40 #include <linux/interrupt.h> 41 #include <linux/list.h> 42 #include <linux/mutex.h> 43 #include <linux/pci.h> 44 #include <linux/slab.h> 45 #include <linux/string.h> 46 #include <linux/workqueue.h> 47 #include <linux/zlib.h> 48 #include <linux/hashtable.h> 49 #include <linux/qed/qed_if.h> 50 #include "qed_debug.h" 51 #include "qed_hsi.h" 52 53 extern const struct qed_common_ops qed_common_ops_pass; 54 55 #define QED_MAJOR_VERSION 8 56 #define QED_MINOR_VERSION 33 57 #define QED_REVISION_VERSION 0 58 #define QED_ENGINEERING_VERSION 20 59 60 #define QED_VERSION \ 61 ((QED_MAJOR_VERSION << 24) | (QED_MINOR_VERSION << 16) | \ 62 (QED_REVISION_VERSION << 8) | QED_ENGINEERING_VERSION) 63 64 #define STORM_FW_VERSION \ 65 ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \ 66 (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION) 67 68 #define MAX_HWFNS_PER_DEVICE (4) 69 #define NAME_SIZE 16 70 #define VER_SIZE 16 71 72 #define QED_WFQ_UNIT 100 73 74 #define QED_WID_SIZE (1024) 75 #define QED_MIN_WIDS (4) 76 #define QED_PF_DEMS_SIZE (4) 77 78 /* cau states */ 79 enum qed_coalescing_mode { 80 QED_COAL_MODE_DISABLE, 81 QED_COAL_MODE_ENABLE 82 }; 83 84 enum qed_nvm_cmd { 85 QED_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, 86 QED_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA, 87 QED_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM, 88 QED_GET_MCP_NVM_RESP = 0xFFFFFF00 89 }; 90 91 struct qed_eth_cb_ops; 92 struct qed_dev_info; 93 union qed_mcp_protocol_stats; 94 enum qed_mcp_protocol_type; 95 enum qed_mfw_tlv_type; 96 union qed_mfw_tlv_data; 97 98 /* helpers */ 99 #define QED_MFW_GET_FIELD(name, field) \ 100 (((name) & (field ## _MASK)) >> (field ## _SHIFT)) 101 102 #define QED_MFW_SET_FIELD(name, field, value) \ 103 do { \ 104 (name) &= ~(field ## _MASK); \ 105 (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\ 106 } while (0) 107 108 static inline u32 qed_db_addr(u32 cid, u32 DEMS) 109 { 110 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 111 (cid * QED_PF_DEMS_SIZE); 112 113 return db_addr; 114 } 115 116 static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS) 117 { 118 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 119 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); 120 121 return db_addr; 122 } 123 124 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ 125 ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \ 126 ~((1 << (p_hwfn->cdev->cache_shift)) - 1)) 127 128 #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++) 129 130 #define D_TRINE(val, cond1, cond2, true1, true2, def) \ 131 (val == (cond1) ? true1 : \ 132 (val == (cond2) ? true2 : def)) 133 134 /* forward */ 135 struct qed_ptt_pool; 136 struct qed_spq; 137 struct qed_sb_info; 138 struct qed_sb_attn_info; 139 struct qed_cxt_mngr; 140 struct qed_sb_sp_info; 141 struct qed_ll2_info; 142 struct qed_mcp_info; 143 144 struct qed_rt_data { 145 u32 *init_val; 146 bool *b_valid; 147 }; 148 149 enum qed_tunn_mode { 150 QED_MODE_L2GENEVE_TUNN, 151 QED_MODE_IPGENEVE_TUNN, 152 QED_MODE_L2GRE_TUNN, 153 QED_MODE_IPGRE_TUNN, 154 QED_MODE_VXLAN_TUNN, 155 }; 156 157 enum qed_tunn_clss { 158 QED_TUNN_CLSS_MAC_VLAN, 159 QED_TUNN_CLSS_MAC_VNI, 160 QED_TUNN_CLSS_INNER_MAC_VLAN, 161 QED_TUNN_CLSS_INNER_MAC_VNI, 162 QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE, 163 MAX_QED_TUNN_CLSS, 164 }; 165 166 struct qed_tunn_update_type { 167 bool b_update_mode; 168 bool b_mode_enabled; 169 enum qed_tunn_clss tun_cls; 170 }; 171 172 struct qed_tunn_update_udp_port { 173 bool b_update_port; 174 u16 port; 175 }; 176 177 struct qed_tunnel_info { 178 struct qed_tunn_update_type vxlan; 179 struct qed_tunn_update_type l2_geneve; 180 struct qed_tunn_update_type ip_geneve; 181 struct qed_tunn_update_type l2_gre; 182 struct qed_tunn_update_type ip_gre; 183 184 struct qed_tunn_update_udp_port vxlan_port; 185 struct qed_tunn_update_udp_port geneve_port; 186 187 bool b_update_rx_cls; 188 bool b_update_tx_cls; 189 }; 190 191 struct qed_tunn_start_params { 192 unsigned long tunn_mode; 193 u16 vxlan_udp_port; 194 u16 geneve_udp_port; 195 u8 update_vxlan_udp_port; 196 u8 update_geneve_udp_port; 197 u8 tunn_clss_vxlan; 198 u8 tunn_clss_l2geneve; 199 u8 tunn_clss_ipgeneve; 200 u8 tunn_clss_l2gre; 201 u8 tunn_clss_ipgre; 202 }; 203 204 struct qed_tunn_update_params { 205 unsigned long tunn_mode_update_mask; 206 unsigned long tunn_mode; 207 u16 vxlan_udp_port; 208 u16 geneve_udp_port; 209 u8 update_rx_pf_clss; 210 u8 update_tx_pf_clss; 211 u8 update_vxlan_udp_port; 212 u8 update_geneve_udp_port; 213 u8 tunn_clss_vxlan; 214 u8 tunn_clss_l2geneve; 215 u8 tunn_clss_ipgeneve; 216 u8 tunn_clss_l2gre; 217 u8 tunn_clss_ipgre; 218 }; 219 220 /* The PCI personality is not quite synonymous to protocol ID: 221 * 1. All personalities need CORE connections 222 * 2. The Ethernet personality may support also the RoCE/iWARP protocol 223 */ 224 enum qed_pci_personality { 225 QED_PCI_ETH, 226 QED_PCI_FCOE, 227 QED_PCI_ISCSI, 228 QED_PCI_ETH_ROCE, 229 QED_PCI_ETH_IWARP, 230 QED_PCI_ETH_RDMA, 231 QED_PCI_DEFAULT, /* default in shmem */ 232 }; 233 234 /* All VFs are symmetric, all counters are PF + all VFs */ 235 struct qed_qm_iids { 236 u32 cids; 237 u32 vf_cids; 238 u32 tids; 239 }; 240 241 /* HW / FW resources, output of features supported below, most information 242 * is received from MFW. 243 */ 244 enum qed_resources { 245 QED_SB, 246 QED_L2_QUEUE, 247 QED_VPORT, 248 QED_RSS_ENG, 249 QED_PQ, 250 QED_RL, 251 QED_MAC, 252 QED_VLAN, 253 QED_RDMA_CNQ_RAM, 254 QED_ILT, 255 QED_LL2_QUEUE, 256 QED_CMDQS_CQS, 257 QED_RDMA_STATS_QUEUE, 258 QED_BDQ, 259 QED_MAX_RESC, 260 }; 261 262 enum QED_FEATURE { 263 QED_PF_L2_QUE, 264 QED_VF, 265 QED_RDMA_CNQ, 266 QED_ISCSI_CQ, 267 QED_FCOE_CQ, 268 QED_VF_L2_QUE, 269 QED_MAX_FEATURES, 270 }; 271 272 enum QED_PORT_MODE { 273 QED_PORT_MODE_DE_2X40G, 274 QED_PORT_MODE_DE_2X50G, 275 QED_PORT_MODE_DE_1X100G, 276 QED_PORT_MODE_DE_4X10G_F, 277 QED_PORT_MODE_DE_4X10G_E, 278 QED_PORT_MODE_DE_4X20G, 279 QED_PORT_MODE_DE_1X40G, 280 QED_PORT_MODE_DE_2X25G, 281 QED_PORT_MODE_DE_1X25G, 282 QED_PORT_MODE_DE_4X25G, 283 QED_PORT_MODE_DE_2X10G, 284 }; 285 286 enum qed_dev_cap { 287 QED_DEV_CAP_ETH, 288 QED_DEV_CAP_FCOE, 289 QED_DEV_CAP_ISCSI, 290 QED_DEV_CAP_ROCE, 291 QED_DEV_CAP_IWARP, 292 }; 293 294 enum qed_wol_support { 295 QED_WOL_SUPPORT_NONE, 296 QED_WOL_SUPPORT_PME, 297 }; 298 299 struct qed_hw_info { 300 /* PCI personality */ 301 enum qed_pci_personality personality; 302 #define QED_IS_RDMA_PERSONALITY(dev) \ 303 ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \ 304 (dev)->hw_info.personality == QED_PCI_ETH_IWARP || \ 305 (dev)->hw_info.personality == QED_PCI_ETH_RDMA) 306 #define QED_IS_ROCE_PERSONALITY(dev) \ 307 ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \ 308 (dev)->hw_info.personality == QED_PCI_ETH_RDMA) 309 #define QED_IS_IWARP_PERSONALITY(dev) \ 310 ((dev)->hw_info.personality == QED_PCI_ETH_IWARP || \ 311 (dev)->hw_info.personality == QED_PCI_ETH_RDMA) 312 #define QED_IS_L2_PERSONALITY(dev) \ 313 ((dev)->hw_info.personality == QED_PCI_ETH || \ 314 QED_IS_RDMA_PERSONALITY(dev)) 315 #define QED_IS_FCOE_PERSONALITY(dev) \ 316 ((dev)->hw_info.personality == QED_PCI_FCOE) 317 #define QED_IS_ISCSI_PERSONALITY(dev) \ 318 ((dev)->hw_info.personality == QED_PCI_ISCSI) 319 320 /* Resource Allocation scheme results */ 321 u32 resc_start[QED_MAX_RESC]; 322 u32 resc_num[QED_MAX_RESC]; 323 u32 feat_num[QED_MAX_FEATURES]; 324 325 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) 326 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) 327 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ 328 RESC_NUM(_p_hwfn, resc)) 329 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) 330 331 /* Amount of traffic classes HW supports */ 332 u8 num_hw_tc; 333 334 /* Amount of TCs which should be active according to DCBx or upper 335 * layer driver configuration. 336 */ 337 u8 num_active_tc; 338 u8 offload_tc; 339 340 u32 concrete_fid; 341 u16 opaque_fid; 342 u16 ovlan; 343 u32 part_num[4]; 344 345 unsigned char hw_mac_addr[ETH_ALEN]; 346 u64 node_wwn; 347 u64 port_wwn; 348 349 u16 num_fcoe_conns; 350 351 struct qed_igu_info *p_igu_info; 352 353 u32 port_mode; 354 u32 hw_mode; 355 unsigned long device_capabilities; 356 u16 mtu; 357 358 enum qed_wol_support b_wol_support; 359 }; 360 361 /* maximun size of read/write commands (HW limit) */ 362 #define DMAE_MAX_RW_SIZE 0x2000 363 364 struct qed_dmae_info { 365 /* Mutex for synchronizing access to functions */ 366 struct mutex mutex; 367 368 u8 channel; 369 370 dma_addr_t completion_word_phys_addr; 371 372 /* The memory location where the DMAE writes the completion 373 * value when an operation is finished on this context. 374 */ 375 u32 *p_completion_word; 376 377 dma_addr_t intermediate_buffer_phys_addr; 378 379 /* An intermediate buffer for DMAE operations that use virtual 380 * addresses - data is DMA'd to/from this buffer and then 381 * memcpy'd to/from the virtual address 382 */ 383 u32 *p_intermediate_buffer; 384 385 dma_addr_t dmae_cmd_phys_addr; 386 struct dmae_cmd *p_dmae_cmd; 387 }; 388 389 struct qed_wfq_data { 390 /* when feature is configured for at least 1 vport */ 391 u32 min_speed; 392 bool configured; 393 }; 394 395 struct qed_qm_info { 396 struct init_qm_pq_params *qm_pq_params; 397 struct init_qm_vport_params *qm_vport_params; 398 struct init_qm_port_params *qm_port_params; 399 u16 start_pq; 400 u8 start_vport; 401 u16 pure_lb_pq; 402 u16 offload_pq; 403 u16 low_latency_pq; 404 u16 pure_ack_pq; 405 u16 ooo_pq; 406 u16 first_vf_pq; 407 u16 first_mcos_pq; 408 u16 first_rl_pq; 409 u16 num_pqs; 410 u16 num_vf_pqs; 411 u8 num_vports; 412 u8 max_phys_tcs_per_port; 413 u8 ooo_tc; 414 bool pf_rl_en; 415 bool pf_wfq_en; 416 bool vport_rl_en; 417 bool vport_wfq_en; 418 u8 pf_wfq; 419 u32 pf_rl; 420 struct qed_wfq_data *wfq_data; 421 u8 num_pf_rls; 422 }; 423 424 struct storm_stats { 425 u32 address; 426 u32 len; 427 }; 428 429 struct qed_storm_stats { 430 struct storm_stats mstats; 431 struct storm_stats pstats; 432 struct storm_stats tstats; 433 struct storm_stats ustats; 434 }; 435 436 struct qed_fw_data { 437 struct fw_ver_info *fw_ver_info; 438 const u8 *modes_tree_buf; 439 union init_op *init_ops; 440 const u32 *arr_data; 441 u32 init_ops_size; 442 }; 443 444 enum qed_mf_mode_bit { 445 /* Supports PF-classification based on tag */ 446 QED_MF_OVLAN_CLSS, 447 448 /* Supports PF-classification based on MAC */ 449 QED_MF_LLH_MAC_CLSS, 450 451 /* Supports PF-classification based on protocol type */ 452 QED_MF_LLH_PROTO_CLSS, 453 454 /* Requires a default PF to be set */ 455 QED_MF_NEED_DEF_PF, 456 457 /* Allow LL2 to multicast/broadcast */ 458 QED_MF_LL2_NON_UNICAST, 459 460 /* Allow Cross-PF [& child VFs] Tx-switching */ 461 QED_MF_INTER_PF_SWITCH, 462 463 /* Unified Fabtic Port support enabled */ 464 QED_MF_UFP_SPECIFIC, 465 466 /* Disable Accelerated Receive Flow Steering (aRFS) */ 467 QED_MF_DISABLE_ARFS, 468 469 /* Use vlan for steering */ 470 QED_MF_8021Q_TAGGING, 471 472 /* Use stag for steering */ 473 QED_MF_8021AD_TAGGING, 474 475 /* Allow DSCP to TC mapping */ 476 QED_MF_DSCP_TO_TC_MAP, 477 }; 478 479 enum qed_ufp_mode { 480 QED_UFP_MODE_ETS, 481 QED_UFP_MODE_VNIC_BW, 482 QED_UFP_MODE_UNKNOWN 483 }; 484 485 enum qed_ufp_pri_type { 486 QED_UFP_PRI_OS, 487 QED_UFP_PRI_VNIC, 488 QED_UFP_PRI_UNKNOWN 489 }; 490 491 struct qed_ufp_info { 492 enum qed_ufp_pri_type pri_type; 493 enum qed_ufp_mode mode; 494 u8 tc; 495 }; 496 497 enum BAR_ID { 498 BAR_ID_0, /* used for GRC */ 499 BAR_ID_1 /* Used for doorbells */ 500 }; 501 502 struct qed_nvm_image_info { 503 u32 num_images; 504 struct bist_nvm_image_att *image_att; 505 }; 506 507 #define DRV_MODULE_VERSION \ 508 __stringify(QED_MAJOR_VERSION) "." \ 509 __stringify(QED_MINOR_VERSION) "." \ 510 __stringify(QED_REVISION_VERSION) "." \ 511 __stringify(QED_ENGINEERING_VERSION) 512 513 struct qed_simd_fp_handler { 514 void *token; 515 void (*func)(void *); 516 }; 517 518 enum qed_slowpath_wq_flag { 519 QED_SLOWPATH_MFW_TLV_REQ, 520 }; 521 522 struct qed_hwfn { 523 struct qed_dev *cdev; 524 u8 my_id; /* ID inside the PF */ 525 #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) 526 u8 rel_pf_id; /* Relative to engine*/ 527 u8 abs_pf_id; 528 #define QED_PATH_ID(_p_hwfn) \ 529 (QED_IS_K2((_p_hwfn)->cdev) ? 0 : ((_p_hwfn)->abs_pf_id & 1)) 530 u8 port_id; 531 bool b_active; 532 533 u32 dp_module; 534 u8 dp_level; 535 char name[NAME_SIZE]; 536 537 bool first_on_engine; 538 bool hw_init_done; 539 540 u8 num_funcs_on_engine; 541 u8 enabled_func_idx; 542 543 /* BAR access */ 544 void __iomem *regview; 545 void __iomem *doorbells; 546 u64 db_phys_addr; 547 unsigned long db_size; 548 549 /* PTT pool */ 550 struct qed_ptt_pool *p_ptt_pool; 551 552 /* HW info */ 553 struct qed_hw_info hw_info; 554 555 /* rt_array (for init-tool) */ 556 struct qed_rt_data rt_data; 557 558 /* SPQ */ 559 struct qed_spq *p_spq; 560 561 /* EQ */ 562 struct qed_eq *p_eq; 563 564 /* Consolidate Q*/ 565 struct qed_consq *p_consq; 566 567 /* Slow-Path definitions */ 568 struct tasklet_struct *sp_dpc; 569 bool b_sp_dpc_enabled; 570 571 struct qed_ptt *p_main_ptt; 572 struct qed_ptt *p_dpc_ptt; 573 574 /* PTP will be used only by the leading function. 575 * Usage of all PTP-apis should be synchronized as result. 576 */ 577 struct qed_ptt *p_ptp_ptt; 578 579 struct qed_sb_sp_info *p_sp_sb; 580 struct qed_sb_attn_info *p_sb_attn; 581 582 /* Protocol related */ 583 bool using_ll2; 584 struct qed_ll2_info *p_ll2_info; 585 struct qed_ooo_info *p_ooo_info; 586 struct qed_rdma_info *p_rdma_info; 587 struct qed_iscsi_info *p_iscsi_info; 588 struct qed_fcoe_info *p_fcoe_info; 589 struct qed_pf_params pf_params; 590 591 bool b_rdma_enabled_in_prs; 592 u32 rdma_prs_search_reg; 593 594 struct qed_cxt_mngr *p_cxt_mngr; 595 596 /* Flag indicating whether interrupts are enabled or not*/ 597 bool b_int_enabled; 598 bool b_int_requested; 599 600 /* True if the driver requests for the link */ 601 bool b_drv_link_init; 602 603 struct qed_vf_iov *vf_iov_info; 604 struct qed_pf_iov *pf_iov_info; 605 struct qed_mcp_info *mcp_info; 606 607 struct qed_dcbx_info *p_dcbx_info; 608 609 struct qed_ufp_info ufp_info; 610 611 struct qed_dmae_info dmae_info; 612 613 /* QM init */ 614 struct qed_qm_info qm_info; 615 struct qed_storm_stats storm_stats; 616 617 /* Buffer for unzipping firmware data */ 618 void *unzip_buf; 619 620 struct dbg_tools_data dbg_info; 621 622 /* PWM region specific data */ 623 u16 wid_count; 624 u32 dpi_size; 625 u32 dpi_count; 626 627 /* This is used to calculate the doorbell address */ 628 u32 dpi_start_offset; 629 630 /* If one of the following is set then EDPM shouldn't be used */ 631 u8 dcbx_no_edpm; 632 u8 db_bar_no_edpm; 633 634 /* L2-related */ 635 struct qed_l2_info *p_l2_info; 636 637 /* Nvm images number and attributes */ 638 struct qed_nvm_image_info nvm_info; 639 640 struct qed_ptt *p_arfs_ptt; 641 642 struct qed_simd_fp_handler simd_proto_handler[64]; 643 644 #ifdef CONFIG_QED_SRIOV 645 struct workqueue_struct *iov_wq; 646 struct delayed_work iov_task; 647 unsigned long iov_task_flags; 648 #endif 649 650 struct z_stream_s *stream; 651 struct workqueue_struct *slowpath_wq; 652 struct delayed_work slowpath_task; 653 unsigned long slowpath_task_flags; 654 }; 655 656 struct pci_params { 657 int pm_cap; 658 659 unsigned long mem_start; 660 unsigned long mem_end; 661 unsigned int irq; 662 u8 pf_num; 663 }; 664 665 struct qed_int_param { 666 u32 int_mode; 667 u8 num_vectors; 668 u8 min_msix_cnt; /* for minimal functionality */ 669 }; 670 671 struct qed_int_params { 672 struct qed_int_param in; 673 struct qed_int_param out; 674 struct msix_entry *msix_table; 675 bool fp_initialized; 676 u8 fp_msix_base; 677 u8 fp_msix_cnt; 678 u8 rdma_msix_base; 679 u8 rdma_msix_cnt; 680 }; 681 682 struct qed_dbg_feature { 683 struct dentry *dentry; 684 u8 *dump_buf; 685 u32 buf_size; 686 u32 dumped_dwords; 687 }; 688 689 struct qed_dbg_params { 690 struct qed_dbg_feature features[DBG_FEATURE_NUM]; 691 u8 engine_for_debug; 692 bool print_data; 693 }; 694 695 struct qed_dev { 696 u32 dp_module; 697 u8 dp_level; 698 char name[NAME_SIZE]; 699 700 enum qed_dev_type type; 701 /* Translate type/revision combo into the proper conditions */ 702 #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB) 703 #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \ 704 CHIP_REV_IS_B0(dev)) 705 #define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH) 706 #define QED_IS_K2(dev) QED_IS_AH(dev) 707 708 u16 vendor_id; 709 u16 device_id; 710 #define QED_DEV_ID_MASK 0xff00 711 #define QED_DEV_ID_MASK_BB 0x1600 712 #define QED_DEV_ID_MASK_AH 0x8000 713 714 u16 chip_num; 715 #define CHIP_NUM_MASK 0xffff 716 #define CHIP_NUM_SHIFT 16 717 718 u16 chip_rev; 719 #define CHIP_REV_MASK 0xf 720 #define CHIP_REV_SHIFT 12 721 #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1) 722 723 u16 chip_metal; 724 #define CHIP_METAL_MASK 0xff 725 #define CHIP_METAL_SHIFT 4 726 727 u16 chip_bond_id; 728 #define CHIP_BOND_ID_MASK 0xf 729 #define CHIP_BOND_ID_SHIFT 0 730 731 u8 num_engines; 732 u8 num_ports_in_engine; 733 u8 num_funcs_in_port; 734 735 u8 path_id; 736 737 unsigned long mf_bits; 738 739 int pcie_width; 740 int pcie_speed; 741 742 /* Add MF related configuration */ 743 u8 mcp_rev; 744 u8 boot_mode; 745 746 /* WoL related configurations */ 747 u8 wol_config; 748 u8 wol_mac[ETH_ALEN]; 749 750 u32 int_mode; 751 enum qed_coalescing_mode int_coalescing_mode; 752 u16 rx_coalesce_usecs; 753 u16 tx_coalesce_usecs; 754 755 /* Start Bar offset of first hwfn */ 756 void __iomem *regview; 757 void __iomem *doorbells; 758 u64 db_phys_addr; 759 unsigned long db_size; 760 761 /* PCI */ 762 u8 cache_shift; 763 764 /* Init */ 765 const struct iro *iro_arr; 766 #define IRO (p_hwfn->cdev->iro_arr) 767 768 /* HW functions */ 769 u8 num_hwfns; 770 struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; 771 772 /* SRIOV */ 773 struct qed_hw_sriov_info *p_iov_info; 774 #define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info) 775 struct qed_tunnel_info tunnel; 776 bool b_is_vf; 777 u32 drv_type; 778 struct qed_eth_stats *reset_stats; 779 struct qed_fw_data *fw_data; 780 781 u32 mcp_nvm_resp; 782 783 /* Linux specific here */ 784 struct qede_dev *edev; 785 struct pci_dev *pdev; 786 u32 flags; 787 #define QED_FLAG_STORAGE_STARTED (BIT(0)) 788 int msg_enable; 789 790 struct pci_params pci_params; 791 792 struct qed_int_params int_params; 793 794 u8 protocol; 795 #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH) 796 #define IS_QED_FCOE_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_FCOE) 797 798 /* Callbacks to protocol driver */ 799 union { 800 struct qed_common_cb_ops *common; 801 struct qed_eth_cb_ops *eth; 802 struct qed_fcoe_cb_ops *fcoe; 803 struct qed_iscsi_cb_ops *iscsi; 804 } protocol_ops; 805 void *ops_cookie; 806 807 struct qed_dbg_params dbg_params; 808 809 #ifdef CONFIG_QED_LL2 810 struct qed_cb_ll2_info *ll2; 811 u8 ll2_mac_address[ETH_ALEN]; 812 #endif 813 DECLARE_HASHTABLE(connections, 10); 814 const struct firmware *firmware; 815 816 u32 rdma_max_sge; 817 u32 rdma_max_inline; 818 u32 rdma_max_srq_sge; 819 u16 tunn_feature_mask; 820 }; 821 822 #define NUM_OF_VFS(dev) (QED_IS_BB(dev) ? MAX_NUM_VFS_BB \ 823 : MAX_NUM_VFS_K2) 824 #define NUM_OF_L2_QUEUES(dev) (QED_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \ 825 : MAX_NUM_L2_QUEUES_K2) 826 #define NUM_OF_PORTS(dev) (QED_IS_BB(dev) ? MAX_NUM_PORTS_BB \ 827 : MAX_NUM_PORTS_K2) 828 #define NUM_OF_SBS(dev) (QED_IS_BB(dev) ? MAX_SB_PER_PATH_BB \ 829 : MAX_SB_PER_PATH_K2) 830 #define NUM_OF_ENG_PFS(dev) (QED_IS_BB(dev) ? MAX_NUM_PFS_BB \ 831 : MAX_NUM_PFS_K2) 832 833 /** 834 * @brief qed_concrete_to_sw_fid - get the sw function id from 835 * the concrete value. 836 * 837 * @param concrete_fid 838 * 839 * @return inline u8 840 */ 841 static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev, 842 u32 concrete_fid) 843 { 844 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); 845 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); 846 u8 vf_valid = GET_FIELD(concrete_fid, 847 PXP_CONCRETE_FID_VFVALID); 848 u8 sw_fid; 849 850 if (vf_valid) 851 sw_fid = vfid + MAX_NUM_PFS; 852 else 853 sw_fid = pfid; 854 855 return sw_fid; 856 } 857 858 #define PKT_LB_TC 9 859 #define MAX_NUM_VOQS_E4 20 860 861 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate); 862 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, 863 struct qed_ptt *p_ptt, 864 u32 min_pf_rate); 865 866 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 867 int qed_device_num_engines(struct qed_dev *cdev); 868 int qed_device_get_port_id(struct qed_dev *cdev); 869 void qed_set_fw_mac_addr(__le16 *fw_msb, 870 __le16 *fw_mid, __le16 *fw_lsb, u8 *mac); 871 872 #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) 873 874 /* Flags for indication of required queues */ 875 #define PQ_FLAGS_RLS (BIT(0)) 876 #define PQ_FLAGS_MCOS (BIT(1)) 877 #define PQ_FLAGS_LB (BIT(2)) 878 #define PQ_FLAGS_OOO (BIT(3)) 879 #define PQ_FLAGS_ACK (BIT(4)) 880 #define PQ_FLAGS_OFLD (BIT(5)) 881 #define PQ_FLAGS_VFS (BIT(6)) 882 #define PQ_FLAGS_LLT (BIT(7)) 883 884 /* physical queue index for cm context intialization */ 885 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags); 886 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc); 887 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf); 888 889 #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) 890 891 /* Other Linux specific common definitions */ 892 #define DP_NAME(cdev) ((cdev)->name) 893 894 #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\ 895 (cdev->regview) + \ 896 (offset)) 897 898 #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset)) 899 #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset)) 900 #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset)) 901 902 #define DOORBELL(cdev, db_addr, val) \ 903 writel((u32)val, (void __iomem *)((u8 __iomem *)\ 904 (cdev->doorbells) + (db_addr))) 905 906 /* Prototypes */ 907 int qed_fill_dev_info(struct qed_dev *cdev, 908 struct qed_dev_info *dev_info); 909 void qed_link_update(struct qed_hwfn *hwfn); 910 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, 911 u32 input_len, u8 *input_buf, 912 u32 max_size, u8 *unzip_buf); 913 void qed_get_protocol_stats(struct qed_dev *cdev, 914 enum qed_mcp_protocol_type type, 915 union qed_mcp_protocol_stats *stats); 916 int qed_slowpath_irq_req(struct qed_hwfn *hwfn); 917 void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn); 918 int qed_mfw_tlv_req(struct qed_hwfn *hwfn); 919 920 int qed_mfw_fill_tlv_data(struct qed_hwfn *hwfn, 921 enum qed_mfw_tlv_type type, 922 union qed_mfw_tlv_data *tlv_data); 923 #endif /* _QED_H */ 924