1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _QED_H 34 #define _QED_H 35 36 #include <linux/types.h> 37 #include <linux/io.h> 38 #include <linux/delay.h> 39 #include <linux/firmware.h> 40 #include <linux/interrupt.h> 41 #include <linux/list.h> 42 #include <linux/mutex.h> 43 #include <linux/pci.h> 44 #include <linux/slab.h> 45 #include <linux/string.h> 46 #include <linux/workqueue.h> 47 #include <linux/zlib.h> 48 #include <linux/hashtable.h> 49 #include <linux/qed/qed_if.h> 50 #include "qed_debug.h" 51 #include "qed_hsi.h" 52 53 extern const struct qed_common_ops qed_common_ops_pass; 54 55 #define QED_MAJOR_VERSION 8 56 #define QED_MINOR_VERSION 37 57 #define QED_REVISION_VERSION 0 58 #define QED_ENGINEERING_VERSION 20 59 60 #define QED_VERSION \ 61 ((QED_MAJOR_VERSION << 24) | (QED_MINOR_VERSION << 16) | \ 62 (QED_REVISION_VERSION << 8) | QED_ENGINEERING_VERSION) 63 64 #define STORM_FW_VERSION \ 65 ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \ 66 (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION) 67 68 #define MAX_HWFNS_PER_DEVICE (4) 69 #define NAME_SIZE 16 70 #define VER_SIZE 16 71 72 #define QED_WFQ_UNIT 100 73 74 #define QED_WID_SIZE (1024) 75 #define QED_MIN_WIDS (4) 76 #define QED_PF_DEMS_SIZE (4) 77 78 /* cau states */ 79 enum qed_coalescing_mode { 80 QED_COAL_MODE_DISABLE, 81 QED_COAL_MODE_ENABLE 82 }; 83 84 enum qed_nvm_cmd { 85 QED_PUT_FILE_BEGIN = DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, 86 QED_PUT_FILE_DATA = DRV_MSG_CODE_NVM_PUT_FILE_DATA, 87 QED_NVM_WRITE_NVRAM = DRV_MSG_CODE_NVM_WRITE_NVRAM, 88 QED_GET_MCP_NVM_RESP = 0xFFFFFF00 89 }; 90 91 struct qed_eth_cb_ops; 92 struct qed_dev_info; 93 union qed_mcp_protocol_stats; 94 enum qed_mcp_protocol_type; 95 enum qed_mfw_tlv_type; 96 union qed_mfw_tlv_data; 97 98 /* helpers */ 99 #define QED_MFW_GET_FIELD(name, field) \ 100 (((name) & (field ## _MASK)) >> (field ## _SHIFT)) 101 102 #define QED_MFW_SET_FIELD(name, field, value) \ 103 do { \ 104 (name) &= ~(field ## _MASK); \ 105 (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\ 106 } while (0) 107 108 static inline u32 qed_db_addr(u32 cid, u32 DEMS) 109 { 110 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 111 (cid * QED_PF_DEMS_SIZE); 112 113 return db_addr; 114 } 115 116 static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS) 117 { 118 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 119 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); 120 121 return db_addr; 122 } 123 124 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ 125 ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \ 126 ~((1 << (p_hwfn->cdev->cache_shift)) - 1)) 127 128 #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++) 129 130 #define D_TRINE(val, cond1, cond2, true1, true2, def) \ 131 (val == (cond1) ? true1 : \ 132 (val == (cond2) ? true2 : def)) 133 134 /* forward */ 135 struct qed_ptt_pool; 136 struct qed_spq; 137 struct qed_sb_info; 138 struct qed_sb_attn_info; 139 struct qed_cxt_mngr; 140 struct qed_sb_sp_info; 141 struct qed_ll2_info; 142 struct qed_mcp_info; 143 struct qed_llh_info; 144 145 struct qed_rt_data { 146 u32 *init_val; 147 bool *b_valid; 148 }; 149 150 enum qed_tunn_mode { 151 QED_MODE_L2GENEVE_TUNN, 152 QED_MODE_IPGENEVE_TUNN, 153 QED_MODE_L2GRE_TUNN, 154 QED_MODE_IPGRE_TUNN, 155 QED_MODE_VXLAN_TUNN, 156 }; 157 158 enum qed_tunn_clss { 159 QED_TUNN_CLSS_MAC_VLAN, 160 QED_TUNN_CLSS_MAC_VNI, 161 QED_TUNN_CLSS_INNER_MAC_VLAN, 162 QED_TUNN_CLSS_INNER_MAC_VNI, 163 QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE, 164 MAX_QED_TUNN_CLSS, 165 }; 166 167 struct qed_tunn_update_type { 168 bool b_update_mode; 169 bool b_mode_enabled; 170 enum qed_tunn_clss tun_cls; 171 }; 172 173 struct qed_tunn_update_udp_port { 174 bool b_update_port; 175 u16 port; 176 }; 177 178 struct qed_tunnel_info { 179 struct qed_tunn_update_type vxlan; 180 struct qed_tunn_update_type l2_geneve; 181 struct qed_tunn_update_type ip_geneve; 182 struct qed_tunn_update_type l2_gre; 183 struct qed_tunn_update_type ip_gre; 184 185 struct qed_tunn_update_udp_port vxlan_port; 186 struct qed_tunn_update_udp_port geneve_port; 187 188 bool b_update_rx_cls; 189 bool b_update_tx_cls; 190 }; 191 192 struct qed_tunn_start_params { 193 unsigned long tunn_mode; 194 u16 vxlan_udp_port; 195 u16 geneve_udp_port; 196 u8 update_vxlan_udp_port; 197 u8 update_geneve_udp_port; 198 u8 tunn_clss_vxlan; 199 u8 tunn_clss_l2geneve; 200 u8 tunn_clss_ipgeneve; 201 u8 tunn_clss_l2gre; 202 u8 tunn_clss_ipgre; 203 }; 204 205 struct qed_tunn_update_params { 206 unsigned long tunn_mode_update_mask; 207 unsigned long tunn_mode; 208 u16 vxlan_udp_port; 209 u16 geneve_udp_port; 210 u8 update_rx_pf_clss; 211 u8 update_tx_pf_clss; 212 u8 update_vxlan_udp_port; 213 u8 update_geneve_udp_port; 214 u8 tunn_clss_vxlan; 215 u8 tunn_clss_l2geneve; 216 u8 tunn_clss_ipgeneve; 217 u8 tunn_clss_l2gre; 218 u8 tunn_clss_ipgre; 219 }; 220 221 /* The PCI personality is not quite synonymous to protocol ID: 222 * 1. All personalities need CORE connections 223 * 2. The Ethernet personality may support also the RoCE/iWARP protocol 224 */ 225 enum qed_pci_personality { 226 QED_PCI_ETH, 227 QED_PCI_FCOE, 228 QED_PCI_ISCSI, 229 QED_PCI_ETH_ROCE, 230 QED_PCI_ETH_IWARP, 231 QED_PCI_ETH_RDMA, 232 QED_PCI_DEFAULT, /* default in shmem */ 233 }; 234 235 /* All VFs are symmetric, all counters are PF + all VFs */ 236 struct qed_qm_iids { 237 u32 cids; 238 u32 vf_cids; 239 u32 tids; 240 }; 241 242 /* HW / FW resources, output of features supported below, most information 243 * is received from MFW. 244 */ 245 enum qed_resources { 246 QED_SB, 247 QED_L2_QUEUE, 248 QED_VPORT, 249 QED_RSS_ENG, 250 QED_PQ, 251 QED_RL, 252 QED_MAC, 253 QED_VLAN, 254 QED_RDMA_CNQ_RAM, 255 QED_ILT, 256 QED_LL2_QUEUE, 257 QED_CMDQS_CQS, 258 QED_RDMA_STATS_QUEUE, 259 QED_BDQ, 260 QED_MAX_RESC, 261 }; 262 263 enum QED_FEATURE { 264 QED_PF_L2_QUE, 265 QED_VF, 266 QED_RDMA_CNQ, 267 QED_ISCSI_CQ, 268 QED_FCOE_CQ, 269 QED_VF_L2_QUE, 270 QED_MAX_FEATURES, 271 }; 272 273 enum QED_PORT_MODE { 274 QED_PORT_MODE_DE_2X40G, 275 QED_PORT_MODE_DE_2X50G, 276 QED_PORT_MODE_DE_1X100G, 277 QED_PORT_MODE_DE_4X10G_F, 278 QED_PORT_MODE_DE_4X10G_E, 279 QED_PORT_MODE_DE_4X20G, 280 QED_PORT_MODE_DE_1X40G, 281 QED_PORT_MODE_DE_2X25G, 282 QED_PORT_MODE_DE_1X25G, 283 QED_PORT_MODE_DE_4X25G, 284 QED_PORT_MODE_DE_2X10G, 285 }; 286 287 enum qed_dev_cap { 288 QED_DEV_CAP_ETH, 289 QED_DEV_CAP_FCOE, 290 QED_DEV_CAP_ISCSI, 291 QED_DEV_CAP_ROCE, 292 QED_DEV_CAP_IWARP, 293 }; 294 295 enum qed_wol_support { 296 QED_WOL_SUPPORT_NONE, 297 QED_WOL_SUPPORT_PME, 298 }; 299 300 enum qed_db_rec_exec { 301 DB_REC_DRY_RUN, 302 DB_REC_REAL_DEAL, 303 DB_REC_ONCE, 304 }; 305 306 struct qed_hw_info { 307 /* PCI personality */ 308 enum qed_pci_personality personality; 309 #define QED_IS_RDMA_PERSONALITY(dev) \ 310 ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \ 311 (dev)->hw_info.personality == QED_PCI_ETH_IWARP || \ 312 (dev)->hw_info.personality == QED_PCI_ETH_RDMA) 313 #define QED_IS_ROCE_PERSONALITY(dev) \ 314 ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \ 315 (dev)->hw_info.personality == QED_PCI_ETH_RDMA) 316 #define QED_IS_IWARP_PERSONALITY(dev) \ 317 ((dev)->hw_info.personality == QED_PCI_ETH_IWARP || \ 318 (dev)->hw_info.personality == QED_PCI_ETH_RDMA) 319 #define QED_IS_L2_PERSONALITY(dev) \ 320 ((dev)->hw_info.personality == QED_PCI_ETH || \ 321 QED_IS_RDMA_PERSONALITY(dev)) 322 #define QED_IS_FCOE_PERSONALITY(dev) \ 323 ((dev)->hw_info.personality == QED_PCI_FCOE) 324 #define QED_IS_ISCSI_PERSONALITY(dev) \ 325 ((dev)->hw_info.personality == QED_PCI_ISCSI) 326 327 /* Resource Allocation scheme results */ 328 u32 resc_start[QED_MAX_RESC]; 329 u32 resc_num[QED_MAX_RESC]; 330 u32 feat_num[QED_MAX_FEATURES]; 331 332 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) 333 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) 334 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ 335 RESC_NUM(_p_hwfn, resc)) 336 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) 337 338 /* Amount of traffic classes HW supports */ 339 u8 num_hw_tc; 340 341 /* Amount of TCs which should be active according to DCBx or upper 342 * layer driver configuration. 343 */ 344 u8 num_active_tc; 345 u8 offload_tc; 346 bool offload_tc_set; 347 348 bool multi_tc_roce_en; 349 #define IS_QED_MULTI_TC_ROCE(p_hwfn) (((p_hwfn)->hw_info.multi_tc_roce_en)) 350 351 u32 concrete_fid; 352 u16 opaque_fid; 353 u16 ovlan; 354 u32 part_num[4]; 355 356 unsigned char hw_mac_addr[ETH_ALEN]; 357 u64 node_wwn; 358 u64 port_wwn; 359 360 u16 num_fcoe_conns; 361 362 struct qed_igu_info *p_igu_info; 363 364 u32 port_mode; 365 u32 hw_mode; 366 unsigned long device_capabilities; 367 u16 mtu; 368 369 enum qed_wol_support b_wol_support; 370 }; 371 372 /* maximun size of read/write commands (HW limit) */ 373 #define DMAE_MAX_RW_SIZE 0x2000 374 375 struct qed_dmae_info { 376 /* Mutex for synchronizing access to functions */ 377 struct mutex mutex; 378 379 u8 channel; 380 381 dma_addr_t completion_word_phys_addr; 382 383 /* The memory location where the DMAE writes the completion 384 * value when an operation is finished on this context. 385 */ 386 u32 *p_completion_word; 387 388 dma_addr_t intermediate_buffer_phys_addr; 389 390 /* An intermediate buffer for DMAE operations that use virtual 391 * addresses - data is DMA'd to/from this buffer and then 392 * memcpy'd to/from the virtual address 393 */ 394 u32 *p_intermediate_buffer; 395 396 dma_addr_t dmae_cmd_phys_addr; 397 struct dmae_cmd *p_dmae_cmd; 398 }; 399 400 struct qed_wfq_data { 401 /* when feature is configured for at least 1 vport */ 402 u32 min_speed; 403 bool configured; 404 }; 405 406 struct qed_qm_info { 407 struct init_qm_pq_params *qm_pq_params; 408 struct init_qm_vport_params *qm_vport_params; 409 struct init_qm_port_params *qm_port_params; 410 u16 start_pq; 411 u8 start_vport; 412 u16 pure_lb_pq; 413 u16 first_ofld_pq; 414 u16 first_llt_pq; 415 u16 pure_ack_pq; 416 u16 ooo_pq; 417 u16 first_vf_pq; 418 u16 first_mcos_pq; 419 u16 first_rl_pq; 420 u16 num_pqs; 421 u16 num_vf_pqs; 422 u8 num_vports; 423 u8 max_phys_tcs_per_port; 424 u8 ooo_tc; 425 bool pf_rl_en; 426 bool pf_wfq_en; 427 bool vport_rl_en; 428 bool vport_wfq_en; 429 u8 pf_wfq; 430 u32 pf_rl; 431 struct qed_wfq_data *wfq_data; 432 u8 num_pf_rls; 433 }; 434 435 #define QED_OVERFLOW_BIT 1 436 437 struct qed_db_recovery_info { 438 struct list_head list; 439 440 /* Lock to protect the doorbell recovery mechanism list */ 441 spinlock_t lock; 442 bool dorq_attn; 443 u32 db_recovery_counter; 444 unsigned long overflow; 445 }; 446 447 struct storm_stats { 448 u32 address; 449 u32 len; 450 }; 451 452 struct qed_storm_stats { 453 struct storm_stats mstats; 454 struct storm_stats pstats; 455 struct storm_stats tstats; 456 struct storm_stats ustats; 457 }; 458 459 struct qed_fw_data { 460 struct fw_ver_info *fw_ver_info; 461 const u8 *modes_tree_buf; 462 union init_op *init_ops; 463 const u32 *arr_data; 464 u32 init_ops_size; 465 }; 466 467 enum qed_mf_mode_bit { 468 /* Supports PF-classification based on tag */ 469 QED_MF_OVLAN_CLSS, 470 471 /* Supports PF-classification based on MAC */ 472 QED_MF_LLH_MAC_CLSS, 473 474 /* Supports PF-classification based on protocol type */ 475 QED_MF_LLH_PROTO_CLSS, 476 477 /* Requires a default PF to be set */ 478 QED_MF_NEED_DEF_PF, 479 480 /* Allow LL2 to multicast/broadcast */ 481 QED_MF_LL2_NON_UNICAST, 482 483 /* Allow Cross-PF [& child VFs] Tx-switching */ 484 QED_MF_INTER_PF_SWITCH, 485 486 /* Unified Fabtic Port support enabled */ 487 QED_MF_UFP_SPECIFIC, 488 489 /* Disable Accelerated Receive Flow Steering (aRFS) */ 490 QED_MF_DISABLE_ARFS, 491 492 /* Use vlan for steering */ 493 QED_MF_8021Q_TAGGING, 494 495 /* Use stag for steering */ 496 QED_MF_8021AD_TAGGING, 497 498 /* Allow DSCP to TC mapping */ 499 QED_MF_DSCP_TO_TC_MAP, 500 501 /* Do not insert a vlan tag with id 0 */ 502 QED_MF_DONT_ADD_VLAN0_TAG, 503 }; 504 505 enum qed_ufp_mode { 506 QED_UFP_MODE_ETS, 507 QED_UFP_MODE_VNIC_BW, 508 QED_UFP_MODE_UNKNOWN 509 }; 510 511 enum qed_ufp_pri_type { 512 QED_UFP_PRI_OS, 513 QED_UFP_PRI_VNIC, 514 QED_UFP_PRI_UNKNOWN 515 }; 516 517 struct qed_ufp_info { 518 enum qed_ufp_pri_type pri_type; 519 enum qed_ufp_mode mode; 520 u8 tc; 521 }; 522 523 enum BAR_ID { 524 BAR_ID_0, /* used for GRC */ 525 BAR_ID_1 /* Used for doorbells */ 526 }; 527 528 struct qed_nvm_image_info { 529 u32 num_images; 530 struct bist_nvm_image_att *image_att; 531 bool valid; 532 }; 533 534 #define DRV_MODULE_VERSION \ 535 __stringify(QED_MAJOR_VERSION) "." \ 536 __stringify(QED_MINOR_VERSION) "." \ 537 __stringify(QED_REVISION_VERSION) "." \ 538 __stringify(QED_ENGINEERING_VERSION) 539 540 struct qed_simd_fp_handler { 541 void *token; 542 void (*func)(void *); 543 }; 544 545 enum qed_slowpath_wq_flag { 546 QED_SLOWPATH_MFW_TLV_REQ, 547 QED_SLOWPATH_PERIODIC_DB_REC, 548 }; 549 550 struct qed_hwfn { 551 struct qed_dev *cdev; 552 u8 my_id; /* ID inside the PF */ 553 #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) 554 u8 rel_pf_id; /* Relative to engine*/ 555 u8 abs_pf_id; 556 #define QED_PATH_ID(_p_hwfn) \ 557 (QED_IS_K2((_p_hwfn)->cdev) ? 0 : ((_p_hwfn)->abs_pf_id & 1)) 558 u8 port_id; 559 bool b_active; 560 561 u32 dp_module; 562 u8 dp_level; 563 char name[NAME_SIZE]; 564 565 bool hw_init_done; 566 567 u8 num_funcs_on_engine; 568 u8 enabled_func_idx; 569 570 /* BAR access */ 571 void __iomem *regview; 572 void __iomem *doorbells; 573 u64 db_phys_addr; 574 unsigned long db_size; 575 576 /* PTT pool */ 577 struct qed_ptt_pool *p_ptt_pool; 578 579 /* HW info */ 580 struct qed_hw_info hw_info; 581 582 /* rt_array (for init-tool) */ 583 struct qed_rt_data rt_data; 584 585 /* SPQ */ 586 struct qed_spq *p_spq; 587 588 /* EQ */ 589 struct qed_eq *p_eq; 590 591 /* Consolidate Q*/ 592 struct qed_consq *p_consq; 593 594 /* Slow-Path definitions */ 595 struct tasklet_struct *sp_dpc; 596 bool b_sp_dpc_enabled; 597 598 struct qed_ptt *p_main_ptt; 599 struct qed_ptt *p_dpc_ptt; 600 601 /* PTP will be used only by the leading function. 602 * Usage of all PTP-apis should be synchronized as result. 603 */ 604 struct qed_ptt *p_ptp_ptt; 605 606 struct qed_sb_sp_info *p_sp_sb; 607 struct qed_sb_attn_info *p_sb_attn; 608 609 /* Protocol related */ 610 bool using_ll2; 611 struct qed_ll2_info *p_ll2_info; 612 struct qed_ooo_info *p_ooo_info; 613 struct qed_rdma_info *p_rdma_info; 614 struct qed_iscsi_info *p_iscsi_info; 615 struct qed_fcoe_info *p_fcoe_info; 616 struct qed_pf_params pf_params; 617 618 bool b_rdma_enabled_in_prs; 619 u32 rdma_prs_search_reg; 620 621 struct qed_cxt_mngr *p_cxt_mngr; 622 623 /* Flag indicating whether interrupts are enabled or not*/ 624 bool b_int_enabled; 625 bool b_int_requested; 626 627 /* True if the driver requests for the link */ 628 bool b_drv_link_init; 629 630 struct qed_vf_iov *vf_iov_info; 631 struct qed_pf_iov *pf_iov_info; 632 struct qed_mcp_info *mcp_info; 633 634 struct qed_dcbx_info *p_dcbx_info; 635 636 struct qed_ufp_info ufp_info; 637 638 struct qed_dmae_info dmae_info; 639 640 /* QM init */ 641 struct qed_qm_info qm_info; 642 struct qed_storm_stats storm_stats; 643 644 /* Buffer for unzipping firmware data */ 645 void *unzip_buf; 646 647 struct dbg_tools_data dbg_info; 648 void *dbg_user_info; 649 650 /* PWM region specific data */ 651 u16 wid_count; 652 u32 dpi_size; 653 u32 dpi_count; 654 655 /* This is used to calculate the doorbell address */ 656 u32 dpi_start_offset; 657 658 /* If one of the following is set then EDPM shouldn't be used */ 659 u8 dcbx_no_edpm; 660 u8 db_bar_no_edpm; 661 662 /* L2-related */ 663 struct qed_l2_info *p_l2_info; 664 665 /* Mechanism for recovering from doorbell drop */ 666 struct qed_db_recovery_info db_recovery_info; 667 668 /* Nvm images number and attributes */ 669 struct qed_nvm_image_info nvm_info; 670 671 struct qed_ptt *p_arfs_ptt; 672 673 struct qed_simd_fp_handler simd_proto_handler[64]; 674 675 #ifdef CONFIG_QED_SRIOV 676 struct workqueue_struct *iov_wq; 677 struct delayed_work iov_task; 678 unsigned long iov_task_flags; 679 #endif 680 struct z_stream_s *stream; 681 bool slowpath_wq_active; 682 struct workqueue_struct *slowpath_wq; 683 struct delayed_work slowpath_task; 684 unsigned long slowpath_task_flags; 685 u32 periodic_db_rec_count; 686 }; 687 688 struct pci_params { 689 int pm_cap; 690 691 unsigned long mem_start; 692 unsigned long mem_end; 693 unsigned int irq; 694 u8 pf_num; 695 }; 696 697 struct qed_int_param { 698 u32 int_mode; 699 u8 num_vectors; 700 u8 min_msix_cnt; /* for minimal functionality */ 701 }; 702 703 struct qed_int_params { 704 struct qed_int_param in; 705 struct qed_int_param out; 706 struct msix_entry *msix_table; 707 bool fp_initialized; 708 u8 fp_msix_base; 709 u8 fp_msix_cnt; 710 u8 rdma_msix_base; 711 u8 rdma_msix_cnt; 712 }; 713 714 struct qed_dbg_feature { 715 struct dentry *dentry; 716 u8 *dump_buf; 717 u32 buf_size; 718 u32 dumped_dwords; 719 }; 720 721 struct qed_dbg_params { 722 struct qed_dbg_feature features[DBG_FEATURE_NUM]; 723 u8 engine_for_debug; 724 bool print_data; 725 }; 726 727 struct qed_dev { 728 u32 dp_module; 729 u8 dp_level; 730 char name[NAME_SIZE]; 731 732 enum qed_dev_type type; 733 /* Translate type/revision combo into the proper conditions */ 734 #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB) 735 #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \ 736 CHIP_REV_IS_B0(dev)) 737 #define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH) 738 #define QED_IS_K2(dev) QED_IS_AH(dev) 739 740 u16 vendor_id; 741 u16 device_id; 742 #define QED_DEV_ID_MASK 0xff00 743 #define QED_DEV_ID_MASK_BB 0x1600 744 #define QED_DEV_ID_MASK_AH 0x8000 745 #define QED_IS_E4(dev) (QED_IS_BB(dev) || QED_IS_AH(dev)) 746 747 u16 chip_num; 748 #define CHIP_NUM_MASK 0xffff 749 #define CHIP_NUM_SHIFT 16 750 751 u16 chip_rev; 752 #define CHIP_REV_MASK 0xf 753 #define CHIP_REV_SHIFT 12 754 #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1) 755 756 u16 chip_metal; 757 #define CHIP_METAL_MASK 0xff 758 #define CHIP_METAL_SHIFT 4 759 760 u16 chip_bond_id; 761 #define CHIP_BOND_ID_MASK 0xf 762 #define CHIP_BOND_ID_SHIFT 0 763 764 u8 num_engines; 765 u8 num_ports; 766 u8 num_ports_in_engine; 767 u8 num_funcs_in_port; 768 769 u8 path_id; 770 771 unsigned long mf_bits; 772 773 int pcie_width; 774 int pcie_speed; 775 776 /* Add MF related configuration */ 777 u8 mcp_rev; 778 u8 boot_mode; 779 780 /* WoL related configurations */ 781 u8 wol_config; 782 u8 wol_mac[ETH_ALEN]; 783 784 u32 int_mode; 785 enum qed_coalescing_mode int_coalescing_mode; 786 u16 rx_coalesce_usecs; 787 u16 tx_coalesce_usecs; 788 789 /* Start Bar offset of first hwfn */ 790 void __iomem *regview; 791 void __iomem *doorbells; 792 u64 db_phys_addr; 793 unsigned long db_size; 794 795 /* PCI */ 796 u8 cache_shift; 797 798 /* Init */ 799 const struct iro *iro_arr; 800 #define IRO (p_hwfn->cdev->iro_arr) 801 802 /* HW functions */ 803 u8 num_hwfns; 804 struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; 805 806 /* Engine affinity */ 807 u8 l2_affin_hint; 808 u8 fir_affin; 809 u8 iwarp_affin; 810 811 /* SRIOV */ 812 struct qed_hw_sriov_info *p_iov_info; 813 #define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info) 814 struct qed_tunnel_info tunnel; 815 bool b_is_vf; 816 u32 drv_type; 817 struct qed_eth_stats *reset_stats; 818 struct qed_fw_data *fw_data; 819 820 u32 mcp_nvm_resp; 821 822 /* Recovery */ 823 bool recov_in_prog; 824 825 /* LLH info */ 826 u8 ppfid_bitmap; 827 struct qed_llh_info *p_llh_info; 828 829 /* Linux specific here */ 830 struct qede_dev *edev; 831 struct pci_dev *pdev; 832 u32 flags; 833 #define QED_FLAG_STORAGE_STARTED (BIT(0)) 834 int msg_enable; 835 836 struct pci_params pci_params; 837 838 struct qed_int_params int_params; 839 840 u8 protocol; 841 #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH) 842 #define IS_QED_FCOE_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_FCOE) 843 844 /* Callbacks to protocol driver */ 845 union { 846 struct qed_common_cb_ops *common; 847 struct qed_eth_cb_ops *eth; 848 struct qed_fcoe_cb_ops *fcoe; 849 struct qed_iscsi_cb_ops *iscsi; 850 } protocol_ops; 851 void *ops_cookie; 852 853 struct qed_dbg_params dbg_params; 854 855 #ifdef CONFIG_QED_LL2 856 struct qed_cb_ll2_info *ll2; 857 u8 ll2_mac_address[ETH_ALEN]; 858 #endif 859 DECLARE_HASHTABLE(connections, 10); 860 const struct firmware *firmware; 861 862 u32 rdma_max_sge; 863 u32 rdma_max_inline; 864 u32 rdma_max_srq_sge; 865 u16 tunn_feature_mask; 866 867 struct devlink *dl; 868 bool iwarp_cmt; 869 }; 870 871 #define NUM_OF_VFS(dev) (QED_IS_BB(dev) ? MAX_NUM_VFS_BB \ 872 : MAX_NUM_VFS_K2) 873 #define NUM_OF_L2_QUEUES(dev) (QED_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \ 874 : MAX_NUM_L2_QUEUES_K2) 875 #define NUM_OF_PORTS(dev) (QED_IS_BB(dev) ? MAX_NUM_PORTS_BB \ 876 : MAX_NUM_PORTS_K2) 877 #define NUM_OF_SBS(dev) (QED_IS_BB(dev) ? MAX_SB_PER_PATH_BB \ 878 : MAX_SB_PER_PATH_K2) 879 #define NUM_OF_ENG_PFS(dev) (QED_IS_BB(dev) ? MAX_NUM_PFS_BB \ 880 : MAX_NUM_PFS_K2) 881 882 /** 883 * @brief qed_concrete_to_sw_fid - get the sw function id from 884 * the concrete value. 885 * 886 * @param concrete_fid 887 * 888 * @return inline u8 889 */ 890 static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev, 891 u32 concrete_fid) 892 { 893 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); 894 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); 895 u8 vf_valid = GET_FIELD(concrete_fid, 896 PXP_CONCRETE_FID_VFVALID); 897 u8 sw_fid; 898 899 if (vf_valid) 900 sw_fid = vfid + MAX_NUM_PFS; 901 else 902 sw_fid = pfid; 903 904 return sw_fid; 905 } 906 907 #define PKT_LB_TC 9 908 #define MAX_NUM_VOQS_E4 20 909 910 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate); 911 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, 912 struct qed_ptt *p_ptt, 913 u32 min_pf_rate); 914 915 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 916 int qed_device_num_engines(struct qed_dev *cdev); 917 void qed_set_fw_mac_addr(__le16 *fw_msb, 918 __le16 *fw_mid, __le16 *fw_lsb, u8 *mac); 919 920 #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) 921 #define QED_IS_CMT(dev) ((dev)->num_hwfns > 1) 922 /* Macros for getting the engine-affinitized hwfn (FIR: fcoe,iscsi,roce) */ 923 #define QED_FIR_AFFIN_HWFN(dev) (&(dev)->hwfns[dev->fir_affin]) 924 #define QED_IWARP_AFFIN_HWFN(dev) (&(dev)->hwfns[dev->iwarp_affin]) 925 #define QED_AFFIN_HWFN(dev) \ 926 (QED_IS_IWARP_PERSONALITY(QED_LEADING_HWFN(dev)) ? \ 927 QED_IWARP_AFFIN_HWFN(dev) : QED_FIR_AFFIN_HWFN(dev)) 928 #define QED_AFFIN_HWFN_IDX(dev) (IS_LEAD_HWFN(QED_AFFIN_HWFN(dev)) ? 0 : 1) 929 930 /* Flags for indication of required queues */ 931 #define PQ_FLAGS_RLS (BIT(0)) 932 #define PQ_FLAGS_MCOS (BIT(1)) 933 #define PQ_FLAGS_LB (BIT(2)) 934 #define PQ_FLAGS_OOO (BIT(3)) 935 #define PQ_FLAGS_ACK (BIT(4)) 936 #define PQ_FLAGS_OFLD (BIT(5)) 937 #define PQ_FLAGS_VFS (BIT(6)) 938 #define PQ_FLAGS_LLT (BIT(7)) 939 #define PQ_FLAGS_MTC (BIT(8)) 940 941 /* physical queue index for cm context intialization */ 942 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags); 943 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc); 944 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf); 945 u16 qed_get_cm_pq_idx_ofld_mtc(struct qed_hwfn *p_hwfn, u8 tc); 946 u16 qed_get_cm_pq_idx_llt_mtc(struct qed_hwfn *p_hwfn, u8 tc); 947 948 /* doorbell recovery mechanism */ 949 void qed_db_recovery_dp(struct qed_hwfn *p_hwfn); 950 void qed_db_recovery_execute(struct qed_hwfn *p_hwfn); 951 bool qed_edpm_enabled(struct qed_hwfn *p_hwfn); 952 953 /* Other Linux specific common definitions */ 954 #define DP_NAME(cdev) ((cdev)->name) 955 956 #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\ 957 (cdev->regview) + \ 958 (offset)) 959 960 #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset)) 961 #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset)) 962 #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset)) 963 964 #define DOORBELL(cdev, db_addr, val) \ 965 writel((u32)val, (void __iomem *)((u8 __iomem *)\ 966 (cdev->doorbells) + (db_addr))) 967 968 #define MFW_PORT(_p_hwfn) ((_p_hwfn)->abs_pf_id % \ 969 qed_device_num_ports((_p_hwfn)->cdev)) 970 int qed_device_num_ports(struct qed_dev *cdev); 971 972 /* Prototypes */ 973 int qed_fill_dev_info(struct qed_dev *cdev, 974 struct qed_dev_info *dev_info); 975 void qed_link_update(struct qed_hwfn *hwfn, struct qed_ptt *ptt); 976 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, 977 u32 input_len, u8 *input_buf, 978 u32 max_size, u8 *unzip_buf); 979 void qed_schedule_recovery_handler(struct qed_hwfn *p_hwfn); 980 void qed_get_protocol_stats(struct qed_dev *cdev, 981 enum qed_mcp_protocol_type type, 982 union qed_mcp_protocol_stats *stats); 983 int qed_slowpath_irq_req(struct qed_hwfn *hwfn); 984 void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn); 985 int qed_mfw_tlv_req(struct qed_hwfn *hwfn); 986 987 int qed_mfw_fill_tlv_data(struct qed_hwfn *hwfn, 988 enum qed_mfw_tlv_type type, 989 union qed_mfw_tlv_data *tlv_data); 990 991 void qed_hw_info_set_offload_tc(struct qed_hw_info *p_info, u8 tc); 992 993 void qed_periodic_db_rec_start(struct qed_hwfn *p_hwfn); 994 #endif /* _QED_H */ 995