1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _QED_H 34 #define _QED_H 35 36 #include <linux/types.h> 37 #include <linux/io.h> 38 #include <linux/delay.h> 39 #include <linux/firmware.h> 40 #include <linux/interrupt.h> 41 #include <linux/list.h> 42 #include <linux/mutex.h> 43 #include <linux/pci.h> 44 #include <linux/slab.h> 45 #include <linux/string.h> 46 #include <linux/workqueue.h> 47 #include <linux/zlib.h> 48 #include <linux/hashtable.h> 49 #include <linux/qed/qed_if.h> 50 #include "qed_debug.h" 51 #include "qed_hsi.h" 52 53 extern const struct qed_common_ops qed_common_ops_pass; 54 55 #define QED_MAJOR_VERSION 8 56 #define QED_MINOR_VERSION 10 57 #define QED_REVISION_VERSION 10 58 #define QED_ENGINEERING_VERSION 21 59 60 #define QED_VERSION \ 61 ((QED_MAJOR_VERSION << 24) | (QED_MINOR_VERSION << 16) | \ 62 (QED_REVISION_VERSION << 8) | QED_ENGINEERING_VERSION) 63 64 #define STORM_FW_VERSION \ 65 ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \ 66 (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION) 67 68 #define MAX_HWFNS_PER_DEVICE (4) 69 #define NAME_SIZE 16 70 #define VER_SIZE 16 71 72 #define QED_WFQ_UNIT 100 73 74 #define QED_WID_SIZE (1024) 75 #define QED_MIN_WIDS (4) 76 #define QED_PF_DEMS_SIZE (4) 77 78 /* cau states */ 79 enum qed_coalescing_mode { 80 QED_COAL_MODE_DISABLE, 81 QED_COAL_MODE_ENABLE 82 }; 83 84 struct qed_eth_cb_ops; 85 struct qed_dev_info; 86 union qed_mcp_protocol_stats; 87 enum qed_mcp_protocol_type; 88 89 /* helpers */ 90 #define QED_MFW_GET_FIELD(name, field) \ 91 (((name) & (field ## _MASK)) >> (field ## _SHIFT)) 92 93 #define QED_MFW_SET_FIELD(name, field, value) \ 94 do { \ 95 (name) &= ~((field ## _MASK) << (field ## _SHIFT)); \ 96 (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\ 97 } while (0) 98 99 static inline u32 qed_db_addr(u32 cid, u32 DEMS) 100 { 101 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 102 (cid * QED_PF_DEMS_SIZE); 103 104 return db_addr; 105 } 106 107 static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS) 108 { 109 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 110 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); 111 112 return db_addr; 113 } 114 115 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ 116 ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \ 117 ~((1 << (p_hwfn->cdev->cache_shift)) - 1)) 118 119 #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++) 120 121 #define D_TRINE(val, cond1, cond2, true1, true2, def) \ 122 (val == (cond1) ? true1 : \ 123 (val == (cond2) ? true2 : def)) 124 125 /* forward */ 126 struct qed_ptt_pool; 127 struct qed_spq; 128 struct qed_sb_info; 129 struct qed_sb_attn_info; 130 struct qed_cxt_mngr; 131 struct qed_sb_sp_info; 132 struct qed_ll2_info; 133 struct qed_mcp_info; 134 135 struct qed_rt_data { 136 u32 *init_val; 137 bool *b_valid; 138 }; 139 140 enum qed_tunn_mode { 141 QED_MODE_L2GENEVE_TUNN, 142 QED_MODE_IPGENEVE_TUNN, 143 QED_MODE_L2GRE_TUNN, 144 QED_MODE_IPGRE_TUNN, 145 QED_MODE_VXLAN_TUNN, 146 }; 147 148 enum qed_tunn_clss { 149 QED_TUNN_CLSS_MAC_VLAN, 150 QED_TUNN_CLSS_MAC_VNI, 151 QED_TUNN_CLSS_INNER_MAC_VLAN, 152 QED_TUNN_CLSS_INNER_MAC_VNI, 153 QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE, 154 MAX_QED_TUNN_CLSS, 155 }; 156 157 struct qed_tunn_update_type { 158 bool b_update_mode; 159 bool b_mode_enabled; 160 enum qed_tunn_clss tun_cls; 161 }; 162 163 struct qed_tunn_update_udp_port { 164 bool b_update_port; 165 u16 port; 166 }; 167 168 struct qed_tunnel_info { 169 struct qed_tunn_update_type vxlan; 170 struct qed_tunn_update_type l2_geneve; 171 struct qed_tunn_update_type ip_geneve; 172 struct qed_tunn_update_type l2_gre; 173 struct qed_tunn_update_type ip_gre; 174 175 struct qed_tunn_update_udp_port vxlan_port; 176 struct qed_tunn_update_udp_port geneve_port; 177 178 bool b_update_rx_cls; 179 bool b_update_tx_cls; 180 }; 181 182 struct qed_tunn_start_params { 183 unsigned long tunn_mode; 184 u16 vxlan_udp_port; 185 u16 geneve_udp_port; 186 u8 update_vxlan_udp_port; 187 u8 update_geneve_udp_port; 188 u8 tunn_clss_vxlan; 189 u8 tunn_clss_l2geneve; 190 u8 tunn_clss_ipgeneve; 191 u8 tunn_clss_l2gre; 192 u8 tunn_clss_ipgre; 193 }; 194 195 struct qed_tunn_update_params { 196 unsigned long tunn_mode_update_mask; 197 unsigned long tunn_mode; 198 u16 vxlan_udp_port; 199 u16 geneve_udp_port; 200 u8 update_rx_pf_clss; 201 u8 update_tx_pf_clss; 202 u8 update_vxlan_udp_port; 203 u8 update_geneve_udp_port; 204 u8 tunn_clss_vxlan; 205 u8 tunn_clss_l2geneve; 206 u8 tunn_clss_ipgeneve; 207 u8 tunn_clss_l2gre; 208 u8 tunn_clss_ipgre; 209 }; 210 211 /* The PCI personality is not quite synonymous to protocol ID: 212 * 1. All personalities need CORE connections 213 * 2. The Ethernet personality may support also the RoCE protocol 214 */ 215 enum qed_pci_personality { 216 QED_PCI_ETH, 217 QED_PCI_FCOE, 218 QED_PCI_ISCSI, 219 QED_PCI_ETH_ROCE, 220 QED_PCI_DEFAULT /* default in shmem */ 221 }; 222 223 /* All VFs are symmetric, all counters are PF + all VFs */ 224 struct qed_qm_iids { 225 u32 cids; 226 u32 vf_cids; 227 u32 tids; 228 }; 229 230 /* HW / FW resources, output of features supported below, most information 231 * is received from MFW. 232 */ 233 enum qed_resources { 234 QED_SB, 235 QED_L2_QUEUE, 236 QED_VPORT, 237 QED_RSS_ENG, 238 QED_PQ, 239 QED_RL, 240 QED_MAC, 241 QED_VLAN, 242 QED_RDMA_CNQ_RAM, 243 QED_ILT, 244 QED_LL2_QUEUE, 245 QED_CMDQS_CQS, 246 QED_RDMA_STATS_QUEUE, 247 QED_BDQ, 248 QED_MAX_RESC, 249 }; 250 251 enum QED_FEATURE { 252 QED_PF_L2_QUE, 253 QED_VF, 254 QED_RDMA_CNQ, 255 QED_ISCSI_CQ, 256 QED_FCOE_CQ, 257 QED_VF_L2_QUE, 258 QED_MAX_FEATURES, 259 }; 260 261 enum QED_PORT_MODE { 262 QED_PORT_MODE_DE_2X40G, 263 QED_PORT_MODE_DE_2X50G, 264 QED_PORT_MODE_DE_1X100G, 265 QED_PORT_MODE_DE_4X10G_F, 266 QED_PORT_MODE_DE_4X10G_E, 267 QED_PORT_MODE_DE_4X20G, 268 QED_PORT_MODE_DE_1X40G, 269 QED_PORT_MODE_DE_2X25G, 270 QED_PORT_MODE_DE_1X25G, 271 QED_PORT_MODE_DE_4X25G, 272 QED_PORT_MODE_DE_2X10G, 273 }; 274 275 enum qed_dev_cap { 276 QED_DEV_CAP_ETH, 277 QED_DEV_CAP_FCOE, 278 QED_DEV_CAP_ISCSI, 279 QED_DEV_CAP_ROCE, 280 }; 281 282 enum qed_wol_support { 283 QED_WOL_SUPPORT_NONE, 284 QED_WOL_SUPPORT_PME, 285 }; 286 287 struct qed_hw_info { 288 /* PCI personality */ 289 enum qed_pci_personality personality; 290 291 /* Resource Allocation scheme results */ 292 u32 resc_start[QED_MAX_RESC]; 293 u32 resc_num[QED_MAX_RESC]; 294 u32 feat_num[QED_MAX_FEATURES]; 295 296 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) 297 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) 298 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ 299 RESC_NUM(_p_hwfn, resc)) 300 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) 301 302 /* Amount of traffic classes HW supports */ 303 u8 num_hw_tc; 304 305 /* Amount of TCs which should be active according to DCBx or upper 306 * layer driver configuration. 307 */ 308 u8 num_active_tc; 309 u8 offload_tc; 310 311 u32 concrete_fid; 312 u16 opaque_fid; 313 u16 ovlan; 314 u32 part_num[4]; 315 316 unsigned char hw_mac_addr[ETH_ALEN]; 317 u64 node_wwn; 318 u64 port_wwn; 319 320 u16 num_fcoe_conns; 321 322 struct qed_igu_info *p_igu_info; 323 324 u32 port_mode; 325 u32 hw_mode; 326 unsigned long device_capabilities; 327 u16 mtu; 328 329 enum qed_wol_support b_wol_support; 330 }; 331 332 /* maximun size of read/write commands (HW limit) */ 333 #define DMAE_MAX_RW_SIZE 0x2000 334 335 struct qed_dmae_info { 336 /* Mutex for synchronizing access to functions */ 337 struct mutex mutex; 338 339 u8 channel; 340 341 dma_addr_t completion_word_phys_addr; 342 343 /* The memory location where the DMAE writes the completion 344 * value when an operation is finished on this context. 345 */ 346 u32 *p_completion_word; 347 348 dma_addr_t intermediate_buffer_phys_addr; 349 350 /* An intermediate buffer for DMAE operations that use virtual 351 * addresses - data is DMA'd to/from this buffer and then 352 * memcpy'd to/from the virtual address 353 */ 354 u32 *p_intermediate_buffer; 355 356 dma_addr_t dmae_cmd_phys_addr; 357 struct dmae_cmd *p_dmae_cmd; 358 }; 359 360 struct qed_wfq_data { 361 /* when feature is configured for at least 1 vport */ 362 u32 min_speed; 363 bool configured; 364 }; 365 366 struct qed_qm_info { 367 struct init_qm_pq_params *qm_pq_params; 368 struct init_qm_vport_params *qm_vport_params; 369 struct init_qm_port_params *qm_port_params; 370 u16 start_pq; 371 u8 start_vport; 372 u16 pure_lb_pq; 373 u16 offload_pq; 374 u16 low_latency_pq; 375 u16 pure_ack_pq; 376 u16 ooo_pq; 377 u16 first_vf_pq; 378 u16 first_mcos_pq; 379 u16 first_rl_pq; 380 u16 num_pqs; 381 u16 num_vf_pqs; 382 u8 num_vports; 383 u8 max_phys_tcs_per_port; 384 u8 ooo_tc; 385 bool pf_rl_en; 386 bool pf_wfq_en; 387 bool vport_rl_en; 388 bool vport_wfq_en; 389 u8 pf_wfq; 390 u32 pf_rl; 391 struct qed_wfq_data *wfq_data; 392 u8 num_pf_rls; 393 }; 394 395 struct storm_stats { 396 u32 address; 397 u32 len; 398 }; 399 400 struct qed_storm_stats { 401 struct storm_stats mstats; 402 struct storm_stats pstats; 403 struct storm_stats tstats; 404 struct storm_stats ustats; 405 }; 406 407 struct qed_fw_data { 408 struct fw_ver_info *fw_ver_info; 409 const u8 *modes_tree_buf; 410 union init_op *init_ops; 411 const u32 *arr_data; 412 u32 init_ops_size; 413 }; 414 415 #define DRV_MODULE_VERSION \ 416 __stringify(QED_MAJOR_VERSION) "." \ 417 __stringify(QED_MINOR_VERSION) "." \ 418 __stringify(QED_REVISION_VERSION) "." \ 419 __stringify(QED_ENGINEERING_VERSION) 420 421 struct qed_simd_fp_handler { 422 void *token; 423 void (*func)(void *); 424 }; 425 426 struct qed_hwfn { 427 struct qed_dev *cdev; 428 u8 my_id; /* ID inside the PF */ 429 #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) 430 u8 rel_pf_id; /* Relative to engine*/ 431 u8 abs_pf_id; 432 #define QED_PATH_ID(_p_hwfn) \ 433 (QED_IS_K2((_p_hwfn)->cdev) ? 0 : ((_p_hwfn)->abs_pf_id & 1)) 434 u8 port_id; 435 bool b_active; 436 437 u32 dp_module; 438 u8 dp_level; 439 char name[NAME_SIZE]; 440 441 bool first_on_engine; 442 bool hw_init_done; 443 444 u8 num_funcs_on_engine; 445 u8 enabled_func_idx; 446 447 /* BAR access */ 448 void __iomem *regview; 449 void __iomem *doorbells; 450 u64 db_phys_addr; 451 unsigned long db_size; 452 453 /* PTT pool */ 454 struct qed_ptt_pool *p_ptt_pool; 455 456 /* HW info */ 457 struct qed_hw_info hw_info; 458 459 /* rt_array (for init-tool) */ 460 struct qed_rt_data rt_data; 461 462 /* SPQ */ 463 struct qed_spq *p_spq; 464 465 /* EQ */ 466 struct qed_eq *p_eq; 467 468 /* Consolidate Q*/ 469 struct qed_consq *p_consq; 470 471 /* Slow-Path definitions */ 472 struct tasklet_struct *sp_dpc; 473 bool b_sp_dpc_enabled; 474 475 struct qed_ptt *p_main_ptt; 476 struct qed_ptt *p_dpc_ptt; 477 478 /* PTP will be used only by the leading function. 479 * Usage of all PTP-apis should be synchronized as result. 480 */ 481 struct qed_ptt *p_ptp_ptt; 482 483 struct qed_sb_sp_info *p_sp_sb; 484 struct qed_sb_attn_info *p_sb_attn; 485 486 /* Protocol related */ 487 bool using_ll2; 488 struct qed_ll2_info *p_ll2_info; 489 struct qed_ooo_info *p_ooo_info; 490 struct qed_rdma_info *p_rdma_info; 491 struct qed_iscsi_info *p_iscsi_info; 492 struct qed_fcoe_info *p_fcoe_info; 493 struct qed_pf_params pf_params; 494 495 bool b_rdma_enabled_in_prs; 496 u32 rdma_prs_search_reg; 497 498 /* Array of sb_info of all status blocks */ 499 struct qed_sb_info *sbs_info[MAX_SB_PER_PF_MIMD]; 500 u16 num_sbs; 501 502 struct qed_cxt_mngr *p_cxt_mngr; 503 504 /* Flag indicating whether interrupts are enabled or not*/ 505 bool b_int_enabled; 506 bool b_int_requested; 507 508 /* True if the driver requests for the link */ 509 bool b_drv_link_init; 510 511 struct qed_vf_iov *vf_iov_info; 512 struct qed_pf_iov *pf_iov_info; 513 struct qed_mcp_info *mcp_info; 514 515 struct qed_dcbx_info *p_dcbx_info; 516 517 struct qed_dmae_info dmae_info; 518 519 /* QM init */ 520 struct qed_qm_info qm_info; 521 struct qed_storm_stats storm_stats; 522 523 /* Buffer for unzipping firmware data */ 524 void *unzip_buf; 525 526 struct dbg_tools_data dbg_info; 527 528 /* PWM region specific data */ 529 u16 wid_count; 530 u32 dpi_size; 531 u32 dpi_count; 532 533 /* This is used to calculate the doorbell address */ 534 u32 dpi_start_offset; 535 536 /* If one of the following is set then EDPM shouldn't be used */ 537 u8 dcbx_no_edpm; 538 u8 db_bar_no_edpm; 539 540 struct qed_ptt *p_arfs_ptt; 541 542 struct qed_simd_fp_handler simd_proto_handler[64]; 543 544 #ifdef CONFIG_QED_SRIOV 545 struct workqueue_struct *iov_wq; 546 struct delayed_work iov_task; 547 unsigned long iov_task_flags; 548 #endif 549 550 struct z_stream_s *stream; 551 struct qed_roce_ll2_info *ll2; 552 }; 553 554 struct pci_params { 555 int pm_cap; 556 557 unsigned long mem_start; 558 unsigned long mem_end; 559 unsigned int irq; 560 u8 pf_num; 561 }; 562 563 struct qed_int_param { 564 u32 int_mode; 565 u8 num_vectors; 566 u8 min_msix_cnt; /* for minimal functionality */ 567 }; 568 569 struct qed_int_params { 570 struct qed_int_param in; 571 struct qed_int_param out; 572 struct msix_entry *msix_table; 573 bool fp_initialized; 574 u8 fp_msix_base; 575 u8 fp_msix_cnt; 576 u8 rdma_msix_base; 577 u8 rdma_msix_cnt; 578 }; 579 580 struct qed_dbg_feature { 581 struct dentry *dentry; 582 u8 *dump_buf; 583 u32 buf_size; 584 u32 dumped_dwords; 585 }; 586 587 struct qed_dbg_params { 588 struct qed_dbg_feature features[DBG_FEATURE_NUM]; 589 u8 engine_for_debug; 590 bool print_data; 591 }; 592 593 struct qed_dev { 594 u32 dp_module; 595 u8 dp_level; 596 char name[NAME_SIZE]; 597 598 enum qed_dev_type type; 599 /* Translate type/revision combo into the proper conditions */ 600 #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB) 601 #define QED_IS_BB_A0(dev) (QED_IS_BB(dev) && \ 602 CHIP_REV_IS_A0(dev)) 603 #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \ 604 CHIP_REV_IS_B0(dev)) 605 #define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH) 606 #define QED_IS_K2(dev) QED_IS_AH(dev) 607 608 #define QED_GET_TYPE(dev) (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \ 609 QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2) 610 611 u16 vendor_id; 612 u16 device_id; 613 #define QED_DEV_ID_MASK 0xff00 614 #define QED_DEV_ID_MASK_BB 0x1600 615 #define QED_DEV_ID_MASK_AH 0x8000 616 617 u16 chip_num; 618 #define CHIP_NUM_MASK 0xffff 619 #define CHIP_NUM_SHIFT 16 620 621 u16 chip_rev; 622 #define CHIP_REV_MASK 0xf 623 #define CHIP_REV_SHIFT 12 624 #define CHIP_REV_IS_A0(_cdev) (!(_cdev)->chip_rev) 625 #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1) 626 627 u16 chip_metal; 628 #define CHIP_METAL_MASK 0xff 629 #define CHIP_METAL_SHIFT 4 630 631 u16 chip_bond_id; 632 #define CHIP_BOND_ID_MASK 0xf 633 #define CHIP_BOND_ID_SHIFT 0 634 635 u8 num_engines; 636 u8 num_ports_in_engines; 637 u8 num_funcs_in_port; 638 639 u8 path_id; 640 enum qed_mf_mode mf_mode; 641 #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT) 642 #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR) 643 #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN) 644 645 int pcie_width; 646 int pcie_speed; 647 u8 ver_str[VER_SIZE]; 648 649 /* Add MF related configuration */ 650 u8 mcp_rev; 651 u8 boot_mode; 652 653 /* WoL related configurations */ 654 u8 wol_config; 655 u8 wol_mac[ETH_ALEN]; 656 657 u32 int_mode; 658 enum qed_coalescing_mode int_coalescing_mode; 659 u16 rx_coalesce_usecs; 660 u16 tx_coalesce_usecs; 661 662 /* Start Bar offset of first hwfn */ 663 void __iomem *regview; 664 void __iomem *doorbells; 665 u64 db_phys_addr; 666 unsigned long db_size; 667 668 /* PCI */ 669 u8 cache_shift; 670 671 /* Init */ 672 const struct iro *iro_arr; 673 #define IRO (p_hwfn->cdev->iro_arr) 674 675 /* HW functions */ 676 u8 num_hwfns; 677 struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; 678 679 /* SRIOV */ 680 struct qed_hw_sriov_info *p_iov_info; 681 #define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info) 682 struct qed_tunnel_info tunnel; 683 bool b_is_vf; 684 u32 drv_type; 685 struct qed_eth_stats *reset_stats; 686 struct qed_fw_data *fw_data; 687 688 u32 mcp_nvm_resp; 689 690 /* Linux specific here */ 691 struct qede_dev *edev; 692 struct pci_dev *pdev; 693 u32 flags; 694 #define QED_FLAG_STORAGE_STARTED (BIT(0)) 695 int msg_enable; 696 697 struct pci_params pci_params; 698 699 struct qed_int_params int_params; 700 701 u8 protocol; 702 #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH) 703 #define IS_QED_FCOE_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_FCOE) 704 705 /* Callbacks to protocol driver */ 706 union { 707 struct qed_common_cb_ops *common; 708 struct qed_eth_cb_ops *eth; 709 struct qed_fcoe_cb_ops *fcoe; 710 struct qed_iscsi_cb_ops *iscsi; 711 } protocol_ops; 712 void *ops_cookie; 713 714 struct qed_dbg_params dbg_params; 715 716 #ifdef CONFIG_QED_LL2 717 struct qed_cb_ll2_info *ll2; 718 u8 ll2_mac_address[ETH_ALEN]; 719 #endif 720 DECLARE_HASHTABLE(connections, 10); 721 const struct firmware *firmware; 722 723 u32 rdma_max_sge; 724 u32 rdma_max_inline; 725 u32 rdma_max_srq_sge; 726 u16 tunn_feature_mask; 727 }; 728 729 #define NUM_OF_VFS(dev) (QED_IS_BB(dev) ? MAX_NUM_VFS_BB \ 730 : MAX_NUM_VFS_K2) 731 #define NUM_OF_L2_QUEUES(dev) (QED_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \ 732 : MAX_NUM_L2_QUEUES_K2) 733 #define NUM_OF_PORTS(dev) (QED_IS_BB(dev) ? MAX_NUM_PORTS_BB \ 734 : MAX_NUM_PORTS_K2) 735 #define NUM_OF_SBS(dev) (QED_IS_BB(dev) ? MAX_SB_PER_PATH_BB \ 736 : MAX_SB_PER_PATH_K2) 737 #define NUM_OF_ENG_PFS(dev) (QED_IS_BB(dev) ? MAX_NUM_PFS_BB \ 738 : MAX_NUM_PFS_K2) 739 740 /** 741 * @brief qed_concrete_to_sw_fid - get the sw function id from 742 * the concrete value. 743 * 744 * @param concrete_fid 745 * 746 * @return inline u8 747 */ 748 static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev, 749 u32 concrete_fid) 750 { 751 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); 752 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); 753 u8 vf_valid = GET_FIELD(concrete_fid, 754 PXP_CONCRETE_FID_VFVALID); 755 u8 sw_fid; 756 757 if (vf_valid) 758 sw_fid = vfid + MAX_NUM_PFS; 759 else 760 sw_fid = pfid; 761 762 return sw_fid; 763 } 764 765 #define PURE_LB_TC 8 766 #define OOO_LB_TC 9 767 768 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate); 769 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, 770 struct qed_ptt *p_ptt, 771 u32 min_pf_rate); 772 773 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 774 int qed_device_num_engines(struct qed_dev *cdev); 775 int qed_device_get_port_id(struct qed_dev *cdev); 776 777 #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) 778 779 /* Flags for indication of required queues */ 780 #define PQ_FLAGS_RLS (BIT(0)) 781 #define PQ_FLAGS_MCOS (BIT(1)) 782 #define PQ_FLAGS_LB (BIT(2)) 783 #define PQ_FLAGS_OOO (BIT(3)) 784 #define PQ_FLAGS_ACK (BIT(4)) 785 #define PQ_FLAGS_OFLD (BIT(5)) 786 #define PQ_FLAGS_VFS (BIT(6)) 787 #define PQ_FLAGS_LLT (BIT(7)) 788 789 /* physical queue index for cm context intialization */ 790 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags); 791 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc); 792 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf); 793 794 #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) 795 796 /* Other Linux specific common definitions */ 797 #define DP_NAME(cdev) ((cdev)->name) 798 799 #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\ 800 (cdev->regview) + \ 801 (offset)) 802 803 #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset)) 804 #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset)) 805 #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset)) 806 807 #define DOORBELL(cdev, db_addr, val) \ 808 writel((u32)val, (void __iomem *)((u8 __iomem *)\ 809 (cdev->doorbells) + (db_addr))) 810 811 /* Prototypes */ 812 int qed_fill_dev_info(struct qed_dev *cdev, 813 struct qed_dev_info *dev_info); 814 void qed_link_update(struct qed_hwfn *hwfn); 815 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, 816 u32 input_len, u8 *input_buf, 817 u32 max_size, u8 *unzip_buf); 818 void qed_get_protocol_stats(struct qed_dev *cdev, 819 enum qed_mcp_protocol_type type, 820 union qed_mcp_protocol_stats *stats); 821 int qed_slowpath_irq_req(struct qed_hwfn *hwfn); 822 void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn); 823 824 #endif /* _QED_H */ 825