1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015 QLogic Corporation 3 * 4 * This software is available under the terms of the GNU General Public License 5 * (GPL) Version 2, available from the file COPYING in the main directory of 6 * this source tree. 7 */ 8 9 #ifndef _QED_H 10 #define _QED_H 11 12 #include <linux/types.h> 13 #include <linux/io.h> 14 #include <linux/delay.h> 15 #include <linux/firmware.h> 16 #include <linux/interrupt.h> 17 #include <linux/list.h> 18 #include <linux/mutex.h> 19 #include <linux/pci.h> 20 #include <linux/slab.h> 21 #include <linux/string.h> 22 #include <linux/workqueue.h> 23 #include <linux/zlib.h> 24 #include <linux/hashtable.h> 25 #include <linux/qed/qed_if.h> 26 #include "qed_debug.h" 27 #include "qed_hsi.h" 28 29 extern const struct qed_common_ops qed_common_ops_pass; 30 #define DRV_MODULE_VERSION "8.10.9.20" 31 32 #define MAX_HWFNS_PER_DEVICE (4) 33 #define NAME_SIZE 16 34 #define VER_SIZE 16 35 36 #define QED_WFQ_UNIT 100 37 38 #define ISCSI_BDQ_ID(_port_id) (_port_id) 39 #define QED_WID_SIZE (1024) 40 #define QED_PF_DEMS_SIZE (4) 41 42 /* cau states */ 43 enum qed_coalescing_mode { 44 QED_COAL_MODE_DISABLE, 45 QED_COAL_MODE_ENABLE 46 }; 47 48 struct qed_eth_cb_ops; 49 struct qed_dev_info; 50 union qed_mcp_protocol_stats; 51 enum qed_mcp_protocol_type; 52 53 /* helpers */ 54 static inline u32 qed_db_addr(u32 cid, u32 DEMS) 55 { 56 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 57 (cid * QED_PF_DEMS_SIZE); 58 59 return db_addr; 60 } 61 62 static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS) 63 { 64 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 65 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); 66 67 return db_addr; 68 } 69 70 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ 71 ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \ 72 ~((1 << (p_hwfn->cdev->cache_shift)) - 1)) 73 74 #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++) 75 76 #define D_TRINE(val, cond1, cond2, true1, true2, def) \ 77 (val == (cond1) ? true1 : \ 78 (val == (cond2) ? true2 : def)) 79 80 /* forward */ 81 struct qed_ptt_pool; 82 struct qed_spq; 83 struct qed_sb_info; 84 struct qed_sb_attn_info; 85 struct qed_cxt_mngr; 86 struct qed_sb_sp_info; 87 struct qed_ll2_info; 88 struct qed_mcp_info; 89 90 struct qed_rt_data { 91 u32 *init_val; 92 bool *b_valid; 93 }; 94 95 enum qed_tunn_mode { 96 QED_MODE_L2GENEVE_TUNN, 97 QED_MODE_IPGENEVE_TUNN, 98 QED_MODE_L2GRE_TUNN, 99 QED_MODE_IPGRE_TUNN, 100 QED_MODE_VXLAN_TUNN, 101 }; 102 103 enum qed_tunn_clss { 104 QED_TUNN_CLSS_MAC_VLAN, 105 QED_TUNN_CLSS_MAC_VNI, 106 QED_TUNN_CLSS_INNER_MAC_VLAN, 107 QED_TUNN_CLSS_INNER_MAC_VNI, 108 MAX_QED_TUNN_CLSS, 109 }; 110 111 struct qed_tunn_start_params { 112 unsigned long tunn_mode; 113 u16 vxlan_udp_port; 114 u16 geneve_udp_port; 115 u8 update_vxlan_udp_port; 116 u8 update_geneve_udp_port; 117 u8 tunn_clss_vxlan; 118 u8 tunn_clss_l2geneve; 119 u8 tunn_clss_ipgeneve; 120 u8 tunn_clss_l2gre; 121 u8 tunn_clss_ipgre; 122 }; 123 124 struct qed_tunn_update_params { 125 unsigned long tunn_mode_update_mask; 126 unsigned long tunn_mode; 127 u16 vxlan_udp_port; 128 u16 geneve_udp_port; 129 u8 update_rx_pf_clss; 130 u8 update_tx_pf_clss; 131 u8 update_vxlan_udp_port; 132 u8 update_geneve_udp_port; 133 u8 tunn_clss_vxlan; 134 u8 tunn_clss_l2geneve; 135 u8 tunn_clss_ipgeneve; 136 u8 tunn_clss_l2gre; 137 u8 tunn_clss_ipgre; 138 }; 139 140 /* The PCI personality is not quite synonymous to protocol ID: 141 * 1. All personalities need CORE connections 142 * 2. The Ethernet personality may support also the RoCE protocol 143 */ 144 enum qed_pci_personality { 145 QED_PCI_ETH, 146 QED_PCI_ISCSI, 147 QED_PCI_ETH_ROCE, 148 QED_PCI_DEFAULT /* default in shmem */ 149 }; 150 151 /* All VFs are symmetric, all counters are PF + all VFs */ 152 struct qed_qm_iids { 153 u32 cids; 154 u32 vf_cids; 155 u32 tids; 156 }; 157 158 /* HW / FW resources, output of features supported below, most information 159 * is received from MFW. 160 */ 161 enum qed_resources { 162 QED_SB, 163 QED_L2_QUEUE, 164 QED_VPORT, 165 QED_RSS_ENG, 166 QED_PQ, 167 QED_RL, 168 QED_MAC, 169 QED_VLAN, 170 QED_RDMA_CNQ_RAM, 171 QED_ILT, 172 QED_LL2_QUEUE, 173 QED_CMDQS_CQS, 174 QED_RDMA_STATS_QUEUE, 175 QED_MAX_RESC, 176 }; 177 178 enum QED_FEATURE { 179 QED_PF_L2_QUE, 180 QED_VF, 181 QED_RDMA_CNQ, 182 QED_VF_L2_QUE, 183 QED_MAX_FEATURES, 184 }; 185 186 enum QED_PORT_MODE { 187 QED_PORT_MODE_DE_2X40G, 188 QED_PORT_MODE_DE_2X50G, 189 QED_PORT_MODE_DE_1X100G, 190 QED_PORT_MODE_DE_4X10G_F, 191 QED_PORT_MODE_DE_4X10G_E, 192 QED_PORT_MODE_DE_4X20G, 193 QED_PORT_MODE_DE_1X40G, 194 QED_PORT_MODE_DE_2X25G, 195 QED_PORT_MODE_DE_1X25G 196 }; 197 198 enum qed_dev_cap { 199 QED_DEV_CAP_ETH, 200 QED_DEV_CAP_ISCSI, 201 QED_DEV_CAP_ROCE, 202 }; 203 204 enum qed_wol_support { 205 QED_WOL_SUPPORT_NONE, 206 QED_WOL_SUPPORT_PME, 207 }; 208 209 struct qed_hw_info { 210 /* PCI personality */ 211 enum qed_pci_personality personality; 212 213 /* Resource Allocation scheme results */ 214 u32 resc_start[QED_MAX_RESC]; 215 u32 resc_num[QED_MAX_RESC]; 216 u32 feat_num[QED_MAX_FEATURES]; 217 218 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) 219 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) 220 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ 221 RESC_NUM(_p_hwfn, resc)) 222 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) 223 224 u8 num_tc; 225 u8 offload_tc; 226 u8 non_offload_tc; 227 228 u32 concrete_fid; 229 u16 opaque_fid; 230 u16 ovlan; 231 u32 part_num[4]; 232 233 unsigned char hw_mac_addr[ETH_ALEN]; 234 235 struct qed_igu_info *p_igu_info; 236 237 u32 port_mode; 238 u32 hw_mode; 239 unsigned long device_capabilities; 240 u16 mtu; 241 242 enum qed_wol_support b_wol_support; 243 }; 244 245 /* maximun size of read/write commands (HW limit) */ 246 #define DMAE_MAX_RW_SIZE 0x2000 247 248 struct qed_dmae_info { 249 /* Mutex for synchronizing access to functions */ 250 struct mutex mutex; 251 252 u8 channel; 253 254 dma_addr_t completion_word_phys_addr; 255 256 /* The memory location where the DMAE writes the completion 257 * value when an operation is finished on this context. 258 */ 259 u32 *p_completion_word; 260 261 dma_addr_t intermediate_buffer_phys_addr; 262 263 /* An intermediate buffer for DMAE operations that use virtual 264 * addresses - data is DMA'd to/from this buffer and then 265 * memcpy'd to/from the virtual address 266 */ 267 u32 *p_intermediate_buffer; 268 269 dma_addr_t dmae_cmd_phys_addr; 270 struct dmae_cmd *p_dmae_cmd; 271 }; 272 273 struct qed_wfq_data { 274 /* when feature is configured for at least 1 vport */ 275 u32 min_speed; 276 bool configured; 277 }; 278 279 struct qed_qm_info { 280 struct init_qm_pq_params *qm_pq_params; 281 struct init_qm_vport_params *qm_vport_params; 282 struct init_qm_port_params *qm_port_params; 283 u16 start_pq; 284 u8 start_vport; 285 u8 pure_lb_pq; 286 u8 offload_pq; 287 u8 pure_ack_pq; 288 u8 ooo_pq; 289 u8 vf_queues_offset; 290 u16 num_pqs; 291 u16 num_vf_pqs; 292 u8 num_vports; 293 u8 max_phys_tcs_per_port; 294 bool pf_rl_en; 295 bool pf_wfq_en; 296 bool vport_rl_en; 297 bool vport_wfq_en; 298 u8 pf_wfq; 299 u32 pf_rl; 300 struct qed_wfq_data *wfq_data; 301 u8 num_pf_rls; 302 }; 303 304 struct storm_stats { 305 u32 address; 306 u32 len; 307 }; 308 309 struct qed_storm_stats { 310 struct storm_stats mstats; 311 struct storm_stats pstats; 312 struct storm_stats tstats; 313 struct storm_stats ustats; 314 }; 315 316 struct qed_fw_data { 317 struct fw_ver_info *fw_ver_info; 318 const u8 *modes_tree_buf; 319 union init_op *init_ops; 320 const u32 *arr_data; 321 u32 init_ops_size; 322 }; 323 324 struct qed_simd_fp_handler { 325 void *token; 326 void (*func)(void *); 327 }; 328 329 struct qed_hwfn { 330 struct qed_dev *cdev; 331 u8 my_id; /* ID inside the PF */ 332 #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) 333 u8 rel_pf_id; /* Relative to engine*/ 334 u8 abs_pf_id; 335 #define QED_PATH_ID(_p_hwfn) ((_p_hwfn)->abs_pf_id & 1) 336 u8 port_id; 337 bool b_active; 338 339 u32 dp_module; 340 u8 dp_level; 341 char name[NAME_SIZE]; 342 343 bool first_on_engine; 344 bool hw_init_done; 345 346 u8 num_funcs_on_engine; 347 u8 enabled_func_idx; 348 349 /* BAR access */ 350 void __iomem *regview; 351 void __iomem *doorbells; 352 u64 db_phys_addr; 353 unsigned long db_size; 354 355 /* PTT pool */ 356 struct qed_ptt_pool *p_ptt_pool; 357 358 /* HW info */ 359 struct qed_hw_info hw_info; 360 361 /* rt_array (for init-tool) */ 362 struct qed_rt_data rt_data; 363 364 /* SPQ */ 365 struct qed_spq *p_spq; 366 367 /* EQ */ 368 struct qed_eq *p_eq; 369 370 /* Consolidate Q*/ 371 struct qed_consq *p_consq; 372 373 /* Slow-Path definitions */ 374 struct tasklet_struct *sp_dpc; 375 bool b_sp_dpc_enabled; 376 377 struct qed_ptt *p_main_ptt; 378 struct qed_ptt *p_dpc_ptt; 379 380 struct qed_sb_sp_info *p_sp_sb; 381 struct qed_sb_attn_info *p_sb_attn; 382 383 /* Protocol related */ 384 bool using_ll2; 385 struct qed_ll2_info *p_ll2_info; 386 struct qed_ooo_info *p_ooo_info; 387 struct qed_rdma_info *p_rdma_info; 388 struct qed_iscsi_info *p_iscsi_info; 389 struct qed_pf_params pf_params; 390 391 bool b_rdma_enabled_in_prs; 392 u32 rdma_prs_search_reg; 393 394 /* Array of sb_info of all status blocks */ 395 struct qed_sb_info *sbs_info[MAX_SB_PER_PF_MIMD]; 396 u16 num_sbs; 397 398 struct qed_cxt_mngr *p_cxt_mngr; 399 400 /* Flag indicating whether interrupts are enabled or not*/ 401 bool b_int_enabled; 402 bool b_int_requested; 403 404 /* True if the driver requests for the link */ 405 bool b_drv_link_init; 406 407 struct qed_vf_iov *vf_iov_info; 408 struct qed_pf_iov *pf_iov_info; 409 struct qed_mcp_info *mcp_info; 410 411 struct qed_dcbx_info *p_dcbx_info; 412 413 struct qed_dmae_info dmae_info; 414 415 /* QM init */ 416 struct qed_qm_info qm_info; 417 struct qed_storm_stats storm_stats; 418 419 /* Buffer for unzipping firmware data */ 420 void *unzip_buf; 421 422 struct dbg_tools_data dbg_info; 423 424 /* PWM region specific data */ 425 u32 dpi_size; 426 u32 dpi_count; 427 428 /* This is used to calculate the doorbell address */ 429 u32 dpi_start_offset; 430 431 /* If one of the following is set then EDPM shouldn't be used */ 432 u8 dcbx_no_edpm; 433 u8 db_bar_no_edpm; 434 435 struct qed_simd_fp_handler simd_proto_handler[64]; 436 437 #ifdef CONFIG_QED_SRIOV 438 struct workqueue_struct *iov_wq; 439 struct delayed_work iov_task; 440 unsigned long iov_task_flags; 441 #endif 442 443 struct z_stream_s *stream; 444 struct qed_roce_ll2_info *ll2; 445 }; 446 447 struct pci_params { 448 int pm_cap; 449 450 unsigned long mem_start; 451 unsigned long mem_end; 452 unsigned int irq; 453 u8 pf_num; 454 }; 455 456 struct qed_int_param { 457 u32 int_mode; 458 u8 num_vectors; 459 u8 min_msix_cnt; /* for minimal functionality */ 460 }; 461 462 struct qed_int_params { 463 struct qed_int_param in; 464 struct qed_int_param out; 465 struct msix_entry *msix_table; 466 bool fp_initialized; 467 u8 fp_msix_base; 468 u8 fp_msix_cnt; 469 u8 rdma_msix_base; 470 u8 rdma_msix_cnt; 471 }; 472 473 struct qed_dbg_feature { 474 struct dentry *dentry; 475 u8 *dump_buf; 476 u32 buf_size; 477 u32 dumped_dwords; 478 }; 479 480 struct qed_dbg_params { 481 struct qed_dbg_feature features[DBG_FEATURE_NUM]; 482 u8 engine_for_debug; 483 bool print_data; 484 }; 485 486 struct qed_dev { 487 u32 dp_module; 488 u8 dp_level; 489 char name[NAME_SIZE]; 490 491 u8 type; 492 #define QED_DEV_TYPE_BB (0 << 0) 493 #define QED_DEV_TYPE_AH BIT(0) 494 /* Translate type/revision combo into the proper conditions */ 495 #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB) 496 #define QED_IS_BB_A0(dev) (QED_IS_BB(dev) && \ 497 CHIP_REV_IS_A0(dev)) 498 #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \ 499 CHIP_REV_IS_B0(dev)) 500 #define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH) 501 #define QED_IS_K2(dev) QED_IS_AH(dev) 502 503 #define QED_GET_TYPE(dev) (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \ 504 QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2) 505 506 u16 vendor_id; 507 u16 device_id; 508 509 u16 chip_num; 510 #define CHIP_NUM_MASK 0xffff 511 #define CHIP_NUM_SHIFT 16 512 513 u16 chip_rev; 514 #define CHIP_REV_MASK 0xf 515 #define CHIP_REV_SHIFT 12 516 #define CHIP_REV_IS_A0(_cdev) (!(_cdev)->chip_rev) 517 #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1) 518 519 u16 chip_metal; 520 #define CHIP_METAL_MASK 0xff 521 #define CHIP_METAL_SHIFT 4 522 523 u16 chip_bond_id; 524 #define CHIP_BOND_ID_MASK 0xf 525 #define CHIP_BOND_ID_SHIFT 0 526 527 u8 num_engines; 528 u8 num_ports_in_engines; 529 u8 num_funcs_in_port; 530 531 u8 path_id; 532 enum qed_mf_mode mf_mode; 533 #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT) 534 #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR) 535 #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN) 536 537 int pcie_width; 538 int pcie_speed; 539 u8 ver_str[VER_SIZE]; 540 541 /* Add MF related configuration */ 542 u8 mcp_rev; 543 u8 boot_mode; 544 545 /* WoL related configurations */ 546 u8 wol_config; 547 u8 wol_mac[ETH_ALEN]; 548 549 u32 int_mode; 550 enum qed_coalescing_mode int_coalescing_mode; 551 u16 rx_coalesce_usecs; 552 u16 tx_coalesce_usecs; 553 554 /* Start Bar offset of first hwfn */ 555 void __iomem *regview; 556 void __iomem *doorbells; 557 u64 db_phys_addr; 558 unsigned long db_size; 559 560 /* PCI */ 561 u8 cache_shift; 562 563 /* Init */ 564 const struct iro *iro_arr; 565 #define IRO (p_hwfn->cdev->iro_arr) 566 567 /* HW functions */ 568 u8 num_hwfns; 569 struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; 570 571 /* SRIOV */ 572 struct qed_hw_sriov_info *p_iov_info; 573 #define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info) 574 575 unsigned long tunn_mode; 576 577 bool b_is_vf; 578 u32 drv_type; 579 struct qed_eth_stats *reset_stats; 580 struct qed_fw_data *fw_data; 581 582 u32 mcp_nvm_resp; 583 584 /* Linux specific here */ 585 struct qede_dev *edev; 586 struct pci_dev *pdev; 587 u32 flags; 588 #define QED_FLAG_STORAGE_STARTED (BIT(0)) 589 int msg_enable; 590 591 struct pci_params pci_params; 592 593 struct qed_int_params int_params; 594 595 u8 protocol; 596 #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH) 597 598 /* Callbacks to protocol driver */ 599 union { 600 struct qed_common_cb_ops *common; 601 struct qed_eth_cb_ops *eth; 602 struct qed_iscsi_cb_ops *iscsi; 603 } protocol_ops; 604 void *ops_cookie; 605 606 struct qed_dbg_params dbg_params; 607 608 #ifdef CONFIG_QED_LL2 609 struct qed_cb_ll2_info *ll2; 610 u8 ll2_mac_address[ETH_ALEN]; 611 #endif 612 DECLARE_HASHTABLE(connections, 10); 613 const struct firmware *firmware; 614 615 u32 rdma_max_sge; 616 u32 rdma_max_inline; 617 u32 rdma_max_srq_sge; 618 }; 619 620 #define NUM_OF_VFS(dev) MAX_NUM_VFS_BB 621 #define NUM_OF_L2_QUEUES(dev) MAX_NUM_L2_QUEUES_BB 622 #define NUM_OF_SBS(dev) MAX_SB_PER_PATH_BB 623 #define NUM_OF_ENG_PFS(dev) MAX_NUM_PFS_BB 624 625 /** 626 * @brief qed_concrete_to_sw_fid - get the sw function id from 627 * the concrete value. 628 * 629 * @param concrete_fid 630 * 631 * @return inline u8 632 */ 633 static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev, 634 u32 concrete_fid) 635 { 636 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); 637 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); 638 u8 vf_valid = GET_FIELD(concrete_fid, 639 PXP_CONCRETE_FID_VFVALID); 640 u8 sw_fid; 641 642 if (vf_valid) 643 sw_fid = vfid + MAX_NUM_PFS; 644 else 645 sw_fid = pfid; 646 647 return sw_fid; 648 } 649 650 #define PURE_LB_TC 8 651 #define OOO_LB_TC 9 652 653 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate); 654 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate); 655 656 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 657 #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) 658 659 /* Other Linux specific common definitions */ 660 #define DP_NAME(cdev) ((cdev)->name) 661 662 #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\ 663 (cdev->regview) + \ 664 (offset)) 665 666 #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset)) 667 #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset)) 668 #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset)) 669 670 #define DOORBELL(cdev, db_addr, val) \ 671 writel((u32)val, (void __iomem *)((u8 __iomem *)\ 672 (cdev->doorbells) + (db_addr))) 673 674 /* Prototypes */ 675 int qed_fill_dev_info(struct qed_dev *cdev, 676 struct qed_dev_info *dev_info); 677 void qed_link_update(struct qed_hwfn *hwfn); 678 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, 679 u32 input_len, u8 *input_buf, 680 u32 max_size, u8 *unzip_buf); 681 void qed_get_protocol_stats(struct qed_dev *cdev, 682 enum qed_mcp_protocol_type type, 683 union qed_mcp_protocol_stats *stats); 684 int qed_slowpath_irq_req(struct qed_hwfn *hwfn); 685 686 #endif /* _QED_H */ 687