1 /* QLogic qed NIC Driver 2 * Copyright (c) 2015-2017 QLogic Corporation 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and /or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef _QED_H 34 #define _QED_H 35 36 #include <linux/types.h> 37 #include <linux/io.h> 38 #include <linux/delay.h> 39 #include <linux/firmware.h> 40 #include <linux/interrupt.h> 41 #include <linux/list.h> 42 #include <linux/mutex.h> 43 #include <linux/pci.h> 44 #include <linux/slab.h> 45 #include <linux/string.h> 46 #include <linux/workqueue.h> 47 #include <linux/zlib.h> 48 #include <linux/hashtable.h> 49 #include <linux/qed/qed_if.h> 50 #include "qed_debug.h" 51 #include "qed_hsi.h" 52 53 extern const struct qed_common_ops qed_common_ops_pass; 54 55 #define QED_MAJOR_VERSION 8 56 #define QED_MINOR_VERSION 10 57 #define QED_REVISION_VERSION 11 58 #define QED_ENGINEERING_VERSION 21 59 60 #define QED_VERSION \ 61 ((QED_MAJOR_VERSION << 24) | (QED_MINOR_VERSION << 16) | \ 62 (QED_REVISION_VERSION << 8) | QED_ENGINEERING_VERSION) 63 64 #define STORM_FW_VERSION \ 65 ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \ 66 (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION) 67 68 #define MAX_HWFNS_PER_DEVICE (4) 69 #define NAME_SIZE 16 70 #define VER_SIZE 16 71 72 #define QED_WFQ_UNIT 100 73 74 #define QED_WID_SIZE (1024) 75 #define QED_MIN_WIDS (4) 76 #define QED_PF_DEMS_SIZE (4) 77 78 /* cau states */ 79 enum qed_coalescing_mode { 80 QED_COAL_MODE_DISABLE, 81 QED_COAL_MODE_ENABLE 82 }; 83 84 struct qed_eth_cb_ops; 85 struct qed_dev_info; 86 union qed_mcp_protocol_stats; 87 enum qed_mcp_protocol_type; 88 89 /* helpers */ 90 #define QED_MFW_GET_FIELD(name, field) \ 91 (((name) & (field ## _MASK)) >> (field ## _SHIFT)) 92 93 #define QED_MFW_SET_FIELD(name, field, value) \ 94 do { \ 95 (name) &= ~(field ## _MASK); \ 96 (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\ 97 } while (0) 98 99 static inline u32 qed_db_addr(u32 cid, u32 DEMS) 100 { 101 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 102 (cid * QED_PF_DEMS_SIZE); 103 104 return db_addr; 105 } 106 107 static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS) 108 { 109 u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 110 FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); 111 112 return db_addr; 113 } 114 115 #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ 116 ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \ 117 ~((1 << (p_hwfn->cdev->cache_shift)) - 1)) 118 119 #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++) 120 121 #define D_TRINE(val, cond1, cond2, true1, true2, def) \ 122 (val == (cond1) ? true1 : \ 123 (val == (cond2) ? true2 : def)) 124 125 /* forward */ 126 struct qed_ptt_pool; 127 struct qed_spq; 128 struct qed_sb_info; 129 struct qed_sb_attn_info; 130 struct qed_cxt_mngr; 131 struct qed_sb_sp_info; 132 struct qed_ll2_info; 133 struct qed_mcp_info; 134 135 struct qed_rt_data { 136 u32 *init_val; 137 bool *b_valid; 138 }; 139 140 enum qed_tunn_mode { 141 QED_MODE_L2GENEVE_TUNN, 142 QED_MODE_IPGENEVE_TUNN, 143 QED_MODE_L2GRE_TUNN, 144 QED_MODE_IPGRE_TUNN, 145 QED_MODE_VXLAN_TUNN, 146 }; 147 148 enum qed_tunn_clss { 149 QED_TUNN_CLSS_MAC_VLAN, 150 QED_TUNN_CLSS_MAC_VNI, 151 QED_TUNN_CLSS_INNER_MAC_VLAN, 152 QED_TUNN_CLSS_INNER_MAC_VNI, 153 QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE, 154 MAX_QED_TUNN_CLSS, 155 }; 156 157 struct qed_tunn_update_type { 158 bool b_update_mode; 159 bool b_mode_enabled; 160 enum qed_tunn_clss tun_cls; 161 }; 162 163 struct qed_tunn_update_udp_port { 164 bool b_update_port; 165 u16 port; 166 }; 167 168 struct qed_tunnel_info { 169 struct qed_tunn_update_type vxlan; 170 struct qed_tunn_update_type l2_geneve; 171 struct qed_tunn_update_type ip_geneve; 172 struct qed_tunn_update_type l2_gre; 173 struct qed_tunn_update_type ip_gre; 174 175 struct qed_tunn_update_udp_port vxlan_port; 176 struct qed_tunn_update_udp_port geneve_port; 177 178 bool b_update_rx_cls; 179 bool b_update_tx_cls; 180 }; 181 182 struct qed_tunn_start_params { 183 unsigned long tunn_mode; 184 u16 vxlan_udp_port; 185 u16 geneve_udp_port; 186 u8 update_vxlan_udp_port; 187 u8 update_geneve_udp_port; 188 u8 tunn_clss_vxlan; 189 u8 tunn_clss_l2geneve; 190 u8 tunn_clss_ipgeneve; 191 u8 tunn_clss_l2gre; 192 u8 tunn_clss_ipgre; 193 }; 194 195 struct qed_tunn_update_params { 196 unsigned long tunn_mode_update_mask; 197 unsigned long tunn_mode; 198 u16 vxlan_udp_port; 199 u16 geneve_udp_port; 200 u8 update_rx_pf_clss; 201 u8 update_tx_pf_clss; 202 u8 update_vxlan_udp_port; 203 u8 update_geneve_udp_port; 204 u8 tunn_clss_vxlan; 205 u8 tunn_clss_l2geneve; 206 u8 tunn_clss_ipgeneve; 207 u8 tunn_clss_l2gre; 208 u8 tunn_clss_ipgre; 209 }; 210 211 /* The PCI personality is not quite synonymous to protocol ID: 212 * 1. All personalities need CORE connections 213 * 2. The Ethernet personality may support also the RoCE/iWARP protocol 214 */ 215 enum qed_pci_personality { 216 QED_PCI_ETH, 217 QED_PCI_FCOE, 218 QED_PCI_ISCSI, 219 QED_PCI_ETH_ROCE, 220 QED_PCI_ETH_IWARP, 221 QED_PCI_ETH_RDMA, 222 QED_PCI_DEFAULT, /* default in shmem */ 223 }; 224 225 /* All VFs are symmetric, all counters are PF + all VFs */ 226 struct qed_qm_iids { 227 u32 cids; 228 u32 vf_cids; 229 u32 tids; 230 }; 231 232 /* HW / FW resources, output of features supported below, most information 233 * is received from MFW. 234 */ 235 enum qed_resources { 236 QED_SB, 237 QED_L2_QUEUE, 238 QED_VPORT, 239 QED_RSS_ENG, 240 QED_PQ, 241 QED_RL, 242 QED_MAC, 243 QED_VLAN, 244 QED_RDMA_CNQ_RAM, 245 QED_ILT, 246 QED_LL2_QUEUE, 247 QED_CMDQS_CQS, 248 QED_RDMA_STATS_QUEUE, 249 QED_BDQ, 250 QED_MAX_RESC, 251 }; 252 253 enum QED_FEATURE { 254 QED_PF_L2_QUE, 255 QED_VF, 256 QED_RDMA_CNQ, 257 QED_ISCSI_CQ, 258 QED_FCOE_CQ, 259 QED_VF_L2_QUE, 260 QED_MAX_FEATURES, 261 }; 262 263 enum QED_PORT_MODE { 264 QED_PORT_MODE_DE_2X40G, 265 QED_PORT_MODE_DE_2X50G, 266 QED_PORT_MODE_DE_1X100G, 267 QED_PORT_MODE_DE_4X10G_F, 268 QED_PORT_MODE_DE_4X10G_E, 269 QED_PORT_MODE_DE_4X20G, 270 QED_PORT_MODE_DE_1X40G, 271 QED_PORT_MODE_DE_2X25G, 272 QED_PORT_MODE_DE_1X25G, 273 QED_PORT_MODE_DE_4X25G, 274 QED_PORT_MODE_DE_2X10G, 275 }; 276 277 enum qed_dev_cap { 278 QED_DEV_CAP_ETH, 279 QED_DEV_CAP_FCOE, 280 QED_DEV_CAP_ISCSI, 281 QED_DEV_CAP_ROCE, 282 QED_DEV_CAP_IWARP, 283 }; 284 285 enum qed_wol_support { 286 QED_WOL_SUPPORT_NONE, 287 QED_WOL_SUPPORT_PME, 288 }; 289 290 struct qed_hw_info { 291 /* PCI personality */ 292 enum qed_pci_personality personality; 293 #define QED_IS_RDMA_PERSONALITY(dev) \ 294 ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \ 295 (dev)->hw_info.personality == QED_PCI_ETH_IWARP || \ 296 (dev)->hw_info.personality == QED_PCI_ETH_RDMA) 297 #define QED_IS_ROCE_PERSONALITY(dev) \ 298 ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \ 299 (dev)->hw_info.personality == QED_PCI_ETH_RDMA) 300 #define QED_IS_IWARP_PERSONALITY(dev) \ 301 ((dev)->hw_info.personality == QED_PCI_ETH_IWARP || \ 302 (dev)->hw_info.personality == QED_PCI_ETH_RDMA) 303 #define QED_IS_L2_PERSONALITY(dev) \ 304 ((dev)->hw_info.personality == QED_PCI_ETH || \ 305 QED_IS_RDMA_PERSONALITY(dev)) 306 #define QED_IS_FCOE_PERSONALITY(dev) \ 307 ((dev)->hw_info.personality == QED_PCI_FCOE) 308 #define QED_IS_ISCSI_PERSONALITY(dev) \ 309 ((dev)->hw_info.personality == QED_PCI_ISCSI) 310 311 /* Resource Allocation scheme results */ 312 u32 resc_start[QED_MAX_RESC]; 313 u32 resc_num[QED_MAX_RESC]; 314 u32 feat_num[QED_MAX_FEATURES]; 315 316 #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) 317 #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) 318 #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ 319 RESC_NUM(_p_hwfn, resc)) 320 #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) 321 322 /* Amount of traffic classes HW supports */ 323 u8 num_hw_tc; 324 325 /* Amount of TCs which should be active according to DCBx or upper 326 * layer driver configuration. 327 */ 328 u8 num_active_tc; 329 u8 offload_tc; 330 331 u32 concrete_fid; 332 u16 opaque_fid; 333 u16 ovlan; 334 u32 part_num[4]; 335 336 unsigned char hw_mac_addr[ETH_ALEN]; 337 u64 node_wwn; 338 u64 port_wwn; 339 340 u16 num_fcoe_conns; 341 342 struct qed_igu_info *p_igu_info; 343 344 u32 port_mode; 345 u32 hw_mode; 346 unsigned long device_capabilities; 347 u16 mtu; 348 349 enum qed_wol_support b_wol_support; 350 }; 351 352 /* maximun size of read/write commands (HW limit) */ 353 #define DMAE_MAX_RW_SIZE 0x2000 354 355 struct qed_dmae_info { 356 /* Mutex for synchronizing access to functions */ 357 struct mutex mutex; 358 359 u8 channel; 360 361 dma_addr_t completion_word_phys_addr; 362 363 /* The memory location where the DMAE writes the completion 364 * value when an operation is finished on this context. 365 */ 366 u32 *p_completion_word; 367 368 dma_addr_t intermediate_buffer_phys_addr; 369 370 /* An intermediate buffer for DMAE operations that use virtual 371 * addresses - data is DMA'd to/from this buffer and then 372 * memcpy'd to/from the virtual address 373 */ 374 u32 *p_intermediate_buffer; 375 376 dma_addr_t dmae_cmd_phys_addr; 377 struct dmae_cmd *p_dmae_cmd; 378 }; 379 380 struct qed_wfq_data { 381 /* when feature is configured for at least 1 vport */ 382 u32 min_speed; 383 bool configured; 384 }; 385 386 struct qed_qm_info { 387 struct init_qm_pq_params *qm_pq_params; 388 struct init_qm_vport_params *qm_vport_params; 389 struct init_qm_port_params *qm_port_params; 390 u16 start_pq; 391 u8 start_vport; 392 u16 pure_lb_pq; 393 u16 offload_pq; 394 u16 low_latency_pq; 395 u16 pure_ack_pq; 396 u16 ooo_pq; 397 u16 first_vf_pq; 398 u16 first_mcos_pq; 399 u16 first_rl_pq; 400 u16 num_pqs; 401 u16 num_vf_pqs; 402 u8 num_vports; 403 u8 max_phys_tcs_per_port; 404 u8 ooo_tc; 405 bool pf_rl_en; 406 bool pf_wfq_en; 407 bool vport_rl_en; 408 bool vport_wfq_en; 409 u8 pf_wfq; 410 u32 pf_rl; 411 struct qed_wfq_data *wfq_data; 412 u8 num_pf_rls; 413 }; 414 415 struct storm_stats { 416 u32 address; 417 u32 len; 418 }; 419 420 struct qed_storm_stats { 421 struct storm_stats mstats; 422 struct storm_stats pstats; 423 struct storm_stats tstats; 424 struct storm_stats ustats; 425 }; 426 427 struct qed_fw_data { 428 struct fw_ver_info *fw_ver_info; 429 const u8 *modes_tree_buf; 430 union init_op *init_ops; 431 const u32 *arr_data; 432 u32 init_ops_size; 433 }; 434 435 enum BAR_ID { 436 BAR_ID_0, /* used for GRC */ 437 BAR_ID_1 /* Used for doorbells */ 438 }; 439 440 #define DRV_MODULE_VERSION \ 441 __stringify(QED_MAJOR_VERSION) "." \ 442 __stringify(QED_MINOR_VERSION) "." \ 443 __stringify(QED_REVISION_VERSION) "." \ 444 __stringify(QED_ENGINEERING_VERSION) 445 446 struct qed_simd_fp_handler { 447 void *token; 448 void (*func)(void *); 449 }; 450 451 struct qed_hwfn { 452 struct qed_dev *cdev; 453 u8 my_id; /* ID inside the PF */ 454 #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) 455 u8 rel_pf_id; /* Relative to engine*/ 456 u8 abs_pf_id; 457 #define QED_PATH_ID(_p_hwfn) \ 458 (QED_IS_K2((_p_hwfn)->cdev) ? 0 : ((_p_hwfn)->abs_pf_id & 1)) 459 u8 port_id; 460 bool b_active; 461 462 u32 dp_module; 463 u8 dp_level; 464 char name[NAME_SIZE]; 465 466 bool first_on_engine; 467 bool hw_init_done; 468 469 u8 num_funcs_on_engine; 470 u8 enabled_func_idx; 471 472 /* BAR access */ 473 void __iomem *regview; 474 void __iomem *doorbells; 475 u64 db_phys_addr; 476 unsigned long db_size; 477 478 /* PTT pool */ 479 struct qed_ptt_pool *p_ptt_pool; 480 481 /* HW info */ 482 struct qed_hw_info hw_info; 483 484 /* rt_array (for init-tool) */ 485 struct qed_rt_data rt_data; 486 487 /* SPQ */ 488 struct qed_spq *p_spq; 489 490 /* EQ */ 491 struct qed_eq *p_eq; 492 493 /* Consolidate Q*/ 494 struct qed_consq *p_consq; 495 496 /* Slow-Path definitions */ 497 struct tasklet_struct *sp_dpc; 498 bool b_sp_dpc_enabled; 499 500 struct qed_ptt *p_main_ptt; 501 struct qed_ptt *p_dpc_ptt; 502 503 /* PTP will be used only by the leading function. 504 * Usage of all PTP-apis should be synchronized as result. 505 */ 506 struct qed_ptt *p_ptp_ptt; 507 508 struct qed_sb_sp_info *p_sp_sb; 509 struct qed_sb_attn_info *p_sb_attn; 510 511 /* Protocol related */ 512 bool using_ll2; 513 struct qed_ll2_info *p_ll2_info; 514 struct qed_ooo_info *p_ooo_info; 515 struct qed_rdma_info *p_rdma_info; 516 struct qed_iscsi_info *p_iscsi_info; 517 struct qed_fcoe_info *p_fcoe_info; 518 struct qed_pf_params pf_params; 519 520 bool b_rdma_enabled_in_prs; 521 u32 rdma_prs_search_reg; 522 523 struct qed_cxt_mngr *p_cxt_mngr; 524 525 /* Flag indicating whether interrupts are enabled or not*/ 526 bool b_int_enabled; 527 bool b_int_requested; 528 529 /* True if the driver requests for the link */ 530 bool b_drv_link_init; 531 532 struct qed_vf_iov *vf_iov_info; 533 struct qed_pf_iov *pf_iov_info; 534 struct qed_mcp_info *mcp_info; 535 536 struct qed_dcbx_info *p_dcbx_info; 537 538 struct qed_dmae_info dmae_info; 539 540 /* QM init */ 541 struct qed_qm_info qm_info; 542 struct qed_storm_stats storm_stats; 543 544 /* Buffer for unzipping firmware data */ 545 void *unzip_buf; 546 547 struct dbg_tools_data dbg_info; 548 549 /* PWM region specific data */ 550 u16 wid_count; 551 u32 dpi_size; 552 u32 dpi_count; 553 554 /* This is used to calculate the doorbell address */ 555 u32 dpi_start_offset; 556 557 /* If one of the following is set then EDPM shouldn't be used */ 558 u8 dcbx_no_edpm; 559 u8 db_bar_no_edpm; 560 561 /* L2-related */ 562 struct qed_l2_info *p_l2_info; 563 564 struct qed_ptt *p_arfs_ptt; 565 566 struct qed_simd_fp_handler simd_proto_handler[64]; 567 568 #ifdef CONFIG_QED_SRIOV 569 struct workqueue_struct *iov_wq; 570 struct delayed_work iov_task; 571 unsigned long iov_task_flags; 572 #endif 573 574 struct z_stream_s *stream; 575 }; 576 577 struct pci_params { 578 int pm_cap; 579 580 unsigned long mem_start; 581 unsigned long mem_end; 582 unsigned int irq; 583 u8 pf_num; 584 }; 585 586 struct qed_int_param { 587 u32 int_mode; 588 u8 num_vectors; 589 u8 min_msix_cnt; /* for minimal functionality */ 590 }; 591 592 struct qed_int_params { 593 struct qed_int_param in; 594 struct qed_int_param out; 595 struct msix_entry *msix_table; 596 bool fp_initialized; 597 u8 fp_msix_base; 598 u8 fp_msix_cnt; 599 u8 rdma_msix_base; 600 u8 rdma_msix_cnt; 601 }; 602 603 struct qed_dbg_feature { 604 struct dentry *dentry; 605 u8 *dump_buf; 606 u32 buf_size; 607 u32 dumped_dwords; 608 }; 609 610 struct qed_dbg_params { 611 struct qed_dbg_feature features[DBG_FEATURE_NUM]; 612 u8 engine_for_debug; 613 bool print_data; 614 }; 615 616 struct qed_dev { 617 u32 dp_module; 618 u8 dp_level; 619 char name[NAME_SIZE]; 620 621 enum qed_dev_type type; 622 /* Translate type/revision combo into the proper conditions */ 623 #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB) 624 #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \ 625 CHIP_REV_IS_B0(dev)) 626 #define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH) 627 #define QED_IS_K2(dev) QED_IS_AH(dev) 628 629 u16 vendor_id; 630 u16 device_id; 631 #define QED_DEV_ID_MASK 0xff00 632 #define QED_DEV_ID_MASK_BB 0x1600 633 #define QED_DEV_ID_MASK_AH 0x8000 634 635 u16 chip_num; 636 #define CHIP_NUM_MASK 0xffff 637 #define CHIP_NUM_SHIFT 16 638 639 u16 chip_rev; 640 #define CHIP_REV_MASK 0xf 641 #define CHIP_REV_SHIFT 12 642 #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1) 643 644 u16 chip_metal; 645 #define CHIP_METAL_MASK 0xff 646 #define CHIP_METAL_SHIFT 4 647 648 u16 chip_bond_id; 649 #define CHIP_BOND_ID_MASK 0xf 650 #define CHIP_BOND_ID_SHIFT 0 651 652 u8 num_engines; 653 u8 num_ports_in_engine; 654 u8 num_funcs_in_port; 655 656 u8 path_id; 657 enum qed_mf_mode mf_mode; 658 #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT) 659 #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR) 660 #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN) 661 662 int pcie_width; 663 int pcie_speed; 664 665 /* Add MF related configuration */ 666 u8 mcp_rev; 667 u8 boot_mode; 668 669 /* WoL related configurations */ 670 u8 wol_config; 671 u8 wol_mac[ETH_ALEN]; 672 673 u32 int_mode; 674 enum qed_coalescing_mode int_coalescing_mode; 675 u16 rx_coalesce_usecs; 676 u16 tx_coalesce_usecs; 677 678 /* Start Bar offset of first hwfn */ 679 void __iomem *regview; 680 void __iomem *doorbells; 681 u64 db_phys_addr; 682 unsigned long db_size; 683 684 /* PCI */ 685 u8 cache_shift; 686 687 /* Init */ 688 const struct iro *iro_arr; 689 #define IRO (p_hwfn->cdev->iro_arr) 690 691 /* HW functions */ 692 u8 num_hwfns; 693 struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; 694 695 /* SRIOV */ 696 struct qed_hw_sriov_info *p_iov_info; 697 #define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info) 698 struct qed_tunnel_info tunnel; 699 bool b_is_vf; 700 u32 drv_type; 701 struct qed_eth_stats *reset_stats; 702 struct qed_fw_data *fw_data; 703 704 u32 mcp_nvm_resp; 705 706 /* Linux specific here */ 707 struct qede_dev *edev; 708 struct pci_dev *pdev; 709 u32 flags; 710 #define QED_FLAG_STORAGE_STARTED (BIT(0)) 711 int msg_enable; 712 713 struct pci_params pci_params; 714 715 struct qed_int_params int_params; 716 717 u8 protocol; 718 #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH) 719 #define IS_QED_FCOE_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_FCOE) 720 721 /* Callbacks to protocol driver */ 722 union { 723 struct qed_common_cb_ops *common; 724 struct qed_eth_cb_ops *eth; 725 struct qed_fcoe_cb_ops *fcoe; 726 struct qed_iscsi_cb_ops *iscsi; 727 } protocol_ops; 728 void *ops_cookie; 729 730 struct qed_dbg_params dbg_params; 731 732 #ifdef CONFIG_QED_LL2 733 struct qed_cb_ll2_info *ll2; 734 u8 ll2_mac_address[ETH_ALEN]; 735 #endif 736 DECLARE_HASHTABLE(connections, 10); 737 const struct firmware *firmware; 738 739 u32 rdma_max_sge; 740 u32 rdma_max_inline; 741 u32 rdma_max_srq_sge; 742 u16 tunn_feature_mask; 743 }; 744 745 #define NUM_OF_VFS(dev) (QED_IS_BB(dev) ? MAX_NUM_VFS_BB \ 746 : MAX_NUM_VFS_K2) 747 #define NUM_OF_L2_QUEUES(dev) (QED_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \ 748 : MAX_NUM_L2_QUEUES_K2) 749 #define NUM_OF_PORTS(dev) (QED_IS_BB(dev) ? MAX_NUM_PORTS_BB \ 750 : MAX_NUM_PORTS_K2) 751 #define NUM_OF_SBS(dev) (QED_IS_BB(dev) ? MAX_SB_PER_PATH_BB \ 752 : MAX_SB_PER_PATH_K2) 753 #define NUM_OF_ENG_PFS(dev) (QED_IS_BB(dev) ? MAX_NUM_PFS_BB \ 754 : MAX_NUM_PFS_K2) 755 756 /** 757 * @brief qed_concrete_to_sw_fid - get the sw function id from 758 * the concrete value. 759 * 760 * @param concrete_fid 761 * 762 * @return inline u8 763 */ 764 static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev, 765 u32 concrete_fid) 766 { 767 u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); 768 u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); 769 u8 vf_valid = GET_FIELD(concrete_fid, 770 PXP_CONCRETE_FID_VFVALID); 771 u8 sw_fid; 772 773 if (vf_valid) 774 sw_fid = vfid + MAX_NUM_PFS; 775 else 776 sw_fid = pfid; 777 778 return sw_fid; 779 } 780 781 #define PURE_LB_TC 8 782 #define PKT_LB_TC 9 783 784 int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate); 785 void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, 786 struct qed_ptt *p_ptt, 787 u32 min_pf_rate); 788 789 void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 790 int qed_device_num_engines(struct qed_dev *cdev); 791 int qed_device_get_port_id(struct qed_dev *cdev); 792 void qed_set_fw_mac_addr(__le16 *fw_msb, 793 __le16 *fw_mid, __le16 *fw_lsb, u8 *mac); 794 795 #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) 796 797 /* Flags for indication of required queues */ 798 #define PQ_FLAGS_RLS (BIT(0)) 799 #define PQ_FLAGS_MCOS (BIT(1)) 800 #define PQ_FLAGS_LB (BIT(2)) 801 #define PQ_FLAGS_OOO (BIT(3)) 802 #define PQ_FLAGS_ACK (BIT(4)) 803 #define PQ_FLAGS_OFLD (BIT(5)) 804 #define PQ_FLAGS_VFS (BIT(6)) 805 #define PQ_FLAGS_LLT (BIT(7)) 806 807 /* physical queue index for cm context intialization */ 808 u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags); 809 u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc); 810 u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf); 811 812 #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) 813 814 /* Other Linux specific common definitions */ 815 #define DP_NAME(cdev) ((cdev)->name) 816 817 #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\ 818 (cdev->regview) + \ 819 (offset)) 820 821 #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset)) 822 #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset)) 823 #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset)) 824 825 #define DOORBELL(cdev, db_addr, val) \ 826 writel((u32)val, (void __iomem *)((u8 __iomem *)\ 827 (cdev->doorbells) + (db_addr))) 828 829 /* Prototypes */ 830 int qed_fill_dev_info(struct qed_dev *cdev, 831 struct qed_dev_info *dev_info); 832 void qed_link_update(struct qed_hwfn *hwfn); 833 u32 qed_unzip_data(struct qed_hwfn *p_hwfn, 834 u32 input_len, u8 *input_buf, 835 u32 max_size, u8 *unzip_buf); 836 void qed_get_protocol_stats(struct qed_dev *cdev, 837 enum qed_mcp_protocol_type type, 838 union qed_mcp_protocol_stats *stats); 839 int qed_slowpath_irq_req(struct qed_hwfn *hwfn); 840 void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn); 841 842 #endif /* _QED_H */ 843