1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #ifndef _QED_H 34fe56b9e6SYuval Mintz #define _QED_H 35fe56b9e6SYuval Mintz 36fe56b9e6SYuval Mintz #include <linux/types.h> 37fe56b9e6SYuval Mintz #include <linux/io.h> 38fe56b9e6SYuval Mintz #include <linux/delay.h> 39fe56b9e6SYuval Mintz #include <linux/firmware.h> 40fe56b9e6SYuval Mintz #include <linux/interrupt.h> 41fe56b9e6SYuval Mintz #include <linux/list.h> 42fe56b9e6SYuval Mintz #include <linux/mutex.h> 43fe56b9e6SYuval Mintz #include <linux/pci.h> 44fe56b9e6SYuval Mintz #include <linux/slab.h> 45fe56b9e6SYuval Mintz #include <linux/string.h> 46fe56b9e6SYuval Mintz #include <linux/workqueue.h> 47fe56b9e6SYuval Mintz #include <linux/zlib.h> 48fe56b9e6SYuval Mintz #include <linux/hashtable.h> 49fe56b9e6SYuval Mintz #include <linux/qed/qed_if.h> 50c965db44STomer Tayar #include "qed_debug.h" 51fe56b9e6SYuval Mintz #include "qed_hsi.h" 52fe56b9e6SYuval Mintz 5325c089d7SYuval Mintz extern const struct qed_common_ops qed_common_ops_pass; 5405fafbfbSYuval Mintz #define DRV_MODULE_VERSION "8.10.9.20" 55fe56b9e6SYuval Mintz 56fe56b9e6SYuval Mintz #define MAX_HWFNS_PER_DEVICE (4) 57fe56b9e6SYuval Mintz #define NAME_SIZE 16 58fe56b9e6SYuval Mintz #define VER_SIZE 16 59fe56b9e6SYuval Mintz 60bcd197c8SManish Chopra #define QED_WFQ_UNIT 100 61bcd197c8SManish Chopra 62fc831825SYuval Mintz #define ISCSI_BDQ_ID(_port_id) (_port_id) 6351ff1725SRam Amrani #define QED_WID_SIZE (1024) 6451ff1725SRam Amrani #define QED_PF_DEMS_SIZE (4) 6551ff1725SRam Amrani 66fe56b9e6SYuval Mintz /* cau states */ 67fe56b9e6SYuval Mintz enum qed_coalescing_mode { 68fe56b9e6SYuval Mintz QED_COAL_MODE_DISABLE, 69fe56b9e6SYuval Mintz QED_COAL_MODE_ENABLE 70fe56b9e6SYuval Mintz }; 71fe56b9e6SYuval Mintz 72fe56b9e6SYuval Mintz struct qed_eth_cb_ops; 73fe56b9e6SYuval Mintz struct qed_dev_info; 746c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats; 756c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type; 76fe56b9e6SYuval Mintz 77fe56b9e6SYuval Mintz /* helpers */ 78fe56b9e6SYuval Mintz static inline u32 qed_db_addr(u32 cid, u32 DEMS) 79fe56b9e6SYuval Mintz { 80fe56b9e6SYuval Mintz u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 8151ff1725SRam Amrani (cid * QED_PF_DEMS_SIZE); 8251ff1725SRam Amrani 8351ff1725SRam Amrani return db_addr; 8451ff1725SRam Amrani } 8551ff1725SRam Amrani 8651ff1725SRam Amrani static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS) 8751ff1725SRam Amrani { 8851ff1725SRam Amrani u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 89fe56b9e6SYuval Mintz FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); 90fe56b9e6SYuval Mintz 91fe56b9e6SYuval Mintz return db_addr; 92fe56b9e6SYuval Mintz } 93fe56b9e6SYuval Mintz 94fe56b9e6SYuval Mintz #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ 95fe56b9e6SYuval Mintz ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \ 96fe56b9e6SYuval Mintz ~((1 << (p_hwfn->cdev->cache_shift)) - 1)) 97fe56b9e6SYuval Mintz 98fe56b9e6SYuval Mintz #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++) 99fe56b9e6SYuval Mintz 100fe56b9e6SYuval Mintz #define D_TRINE(val, cond1, cond2, true1, true2, def) \ 101fe56b9e6SYuval Mintz (val == (cond1) ? true1 : \ 102fe56b9e6SYuval Mintz (val == (cond2) ? true2 : def)) 103fe56b9e6SYuval Mintz 104fe56b9e6SYuval Mintz /* forward */ 105fe56b9e6SYuval Mintz struct qed_ptt_pool; 106fe56b9e6SYuval Mintz struct qed_spq; 107fe56b9e6SYuval Mintz struct qed_sb_info; 108fe56b9e6SYuval Mintz struct qed_sb_attn_info; 109fe56b9e6SYuval Mintz struct qed_cxt_mngr; 110fe56b9e6SYuval Mintz struct qed_sb_sp_info; 1110a7fb11cSYuval Mintz struct qed_ll2_info; 112fe56b9e6SYuval Mintz struct qed_mcp_info; 113fe56b9e6SYuval Mintz 114fe56b9e6SYuval Mintz struct qed_rt_data { 115fc48b7a6SYuval Mintz u32 *init_val; 116fc48b7a6SYuval Mintz bool *b_valid; 117fe56b9e6SYuval Mintz }; 118fe56b9e6SYuval Mintz 119464f6645SManish Chopra enum qed_tunn_mode { 120464f6645SManish Chopra QED_MODE_L2GENEVE_TUNN, 121464f6645SManish Chopra QED_MODE_IPGENEVE_TUNN, 122464f6645SManish Chopra QED_MODE_L2GRE_TUNN, 123464f6645SManish Chopra QED_MODE_IPGRE_TUNN, 124464f6645SManish Chopra QED_MODE_VXLAN_TUNN, 125464f6645SManish Chopra }; 126464f6645SManish Chopra 127464f6645SManish Chopra enum qed_tunn_clss { 128464f6645SManish Chopra QED_TUNN_CLSS_MAC_VLAN, 129464f6645SManish Chopra QED_TUNN_CLSS_MAC_VNI, 130464f6645SManish Chopra QED_TUNN_CLSS_INNER_MAC_VLAN, 131464f6645SManish Chopra QED_TUNN_CLSS_INNER_MAC_VNI, 132464f6645SManish Chopra MAX_QED_TUNN_CLSS, 133464f6645SManish Chopra }; 134464f6645SManish Chopra 135464f6645SManish Chopra struct qed_tunn_start_params { 136464f6645SManish Chopra unsigned long tunn_mode; 137464f6645SManish Chopra u16 vxlan_udp_port; 138464f6645SManish Chopra u16 geneve_udp_port; 139464f6645SManish Chopra u8 update_vxlan_udp_port; 140464f6645SManish Chopra u8 update_geneve_udp_port; 141464f6645SManish Chopra u8 tunn_clss_vxlan; 142464f6645SManish Chopra u8 tunn_clss_l2geneve; 143464f6645SManish Chopra u8 tunn_clss_ipgeneve; 144464f6645SManish Chopra u8 tunn_clss_l2gre; 145464f6645SManish Chopra u8 tunn_clss_ipgre; 146464f6645SManish Chopra }; 147464f6645SManish Chopra 148464f6645SManish Chopra struct qed_tunn_update_params { 149464f6645SManish Chopra unsigned long tunn_mode_update_mask; 150464f6645SManish Chopra unsigned long tunn_mode; 151464f6645SManish Chopra u16 vxlan_udp_port; 152464f6645SManish Chopra u16 geneve_udp_port; 153464f6645SManish Chopra u8 update_rx_pf_clss; 154464f6645SManish Chopra u8 update_tx_pf_clss; 155464f6645SManish Chopra u8 update_vxlan_udp_port; 156464f6645SManish Chopra u8 update_geneve_udp_port; 157464f6645SManish Chopra u8 tunn_clss_vxlan; 158464f6645SManish Chopra u8 tunn_clss_l2geneve; 159464f6645SManish Chopra u8 tunn_clss_ipgeneve; 160464f6645SManish Chopra u8 tunn_clss_l2gre; 161464f6645SManish Chopra u8 tunn_clss_ipgre; 162464f6645SManish Chopra }; 163464f6645SManish Chopra 164fe56b9e6SYuval Mintz /* The PCI personality is not quite synonymous to protocol ID: 165fe56b9e6SYuval Mintz * 1. All personalities need CORE connections 166fe56b9e6SYuval Mintz * 2. The Ethernet personality may support also the RoCE protocol 167fe56b9e6SYuval Mintz */ 168fe56b9e6SYuval Mintz enum qed_pci_personality { 169fe56b9e6SYuval Mintz QED_PCI_ETH, 170c5ac9319SYuval Mintz QED_PCI_ISCSI, 171c5ac9319SYuval Mintz QED_PCI_ETH_ROCE, 172fe56b9e6SYuval Mintz QED_PCI_DEFAULT /* default in shmem */ 173fe56b9e6SYuval Mintz }; 174fe56b9e6SYuval Mintz 175fe56b9e6SYuval Mintz /* All VFs are symmetric, all counters are PF + all VFs */ 176fe56b9e6SYuval Mintz struct qed_qm_iids { 177fe56b9e6SYuval Mintz u32 cids; 178fe56b9e6SYuval Mintz u32 vf_cids; 179fe56b9e6SYuval Mintz u32 tids; 180fe56b9e6SYuval Mintz }; 181fe56b9e6SYuval Mintz 1822edbff8dSTomer Tayar /* HW / FW resources, output of features supported below, most information 1832edbff8dSTomer Tayar * is received from MFW. 1842edbff8dSTomer Tayar */ 1852edbff8dSTomer Tayar enum qed_resources { 186fe56b9e6SYuval Mintz QED_SB, 18725c089d7SYuval Mintz QED_L2_QUEUE, 188fe56b9e6SYuval Mintz QED_VPORT, 18925c089d7SYuval Mintz QED_RSS_ENG, 190fe56b9e6SYuval Mintz QED_PQ, 191fe56b9e6SYuval Mintz QED_RL, 19225c089d7SYuval Mintz QED_MAC, 19325c089d7SYuval Mintz QED_VLAN, 19451ff1725SRam Amrani QED_RDMA_CNQ_RAM, 195fe56b9e6SYuval Mintz QED_ILT, 1960a7fb11cSYuval Mintz QED_LL2_QUEUE, 1972edbff8dSTomer Tayar QED_CMDQS_CQS, 19851ff1725SRam Amrani QED_RDMA_STATS_QUEUE, 199fe56b9e6SYuval Mintz QED_MAX_RESC, 200fe56b9e6SYuval Mintz }; 201fe56b9e6SYuval Mintz 20225c089d7SYuval Mintz enum QED_FEATURE { 20325c089d7SYuval Mintz QED_PF_L2_QUE, 20432a47e72SYuval Mintz QED_VF, 20551ff1725SRam Amrani QED_RDMA_CNQ, 2065a1f965aSMintz, Yuval QED_VF_L2_QUE, 20725c089d7SYuval Mintz QED_MAX_FEATURES, 20825c089d7SYuval Mintz }; 20925c089d7SYuval Mintz 210cc875c2eSYuval Mintz enum QED_PORT_MODE { 211cc875c2eSYuval Mintz QED_PORT_MODE_DE_2X40G, 212cc875c2eSYuval Mintz QED_PORT_MODE_DE_2X50G, 213cc875c2eSYuval Mintz QED_PORT_MODE_DE_1X100G, 214cc875c2eSYuval Mintz QED_PORT_MODE_DE_4X10G_F, 215cc875c2eSYuval Mintz QED_PORT_MODE_DE_4X10G_E, 216cc875c2eSYuval Mintz QED_PORT_MODE_DE_4X20G, 217cc875c2eSYuval Mintz QED_PORT_MODE_DE_1X40G, 218cc875c2eSYuval Mintz QED_PORT_MODE_DE_2X25G, 219cc875c2eSYuval Mintz QED_PORT_MODE_DE_1X25G 220cc875c2eSYuval Mintz }; 221cc875c2eSYuval Mintz 222fc48b7a6SYuval Mintz enum qed_dev_cap { 223fc48b7a6SYuval Mintz QED_DEV_CAP_ETH, 224c5ac9319SYuval Mintz QED_DEV_CAP_ISCSI, 225c5ac9319SYuval Mintz QED_DEV_CAP_ROCE, 226fc48b7a6SYuval Mintz }; 227fc48b7a6SYuval Mintz 22814d39648SMintz, Yuval enum qed_wol_support { 22914d39648SMintz, Yuval QED_WOL_SUPPORT_NONE, 23014d39648SMintz, Yuval QED_WOL_SUPPORT_PME, 23114d39648SMintz, Yuval }; 23214d39648SMintz, Yuval 233fe56b9e6SYuval Mintz struct qed_hw_info { 234fe56b9e6SYuval Mintz /* PCI personality */ 235fe56b9e6SYuval Mintz enum qed_pci_personality personality; 236fe56b9e6SYuval Mintz 237fe56b9e6SYuval Mintz /* Resource Allocation scheme results */ 238fe56b9e6SYuval Mintz u32 resc_start[QED_MAX_RESC]; 239fe56b9e6SYuval Mintz u32 resc_num[QED_MAX_RESC]; 24025c089d7SYuval Mintz u32 feat_num[QED_MAX_FEATURES]; 241fe56b9e6SYuval Mintz 242fe56b9e6SYuval Mintz #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) 243fe56b9e6SYuval Mintz #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) 244dbb799c3SYuval Mintz #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ 245dbb799c3SYuval Mintz RESC_NUM(_p_hwfn, resc)) 246fe56b9e6SYuval Mintz #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) 247fe56b9e6SYuval Mintz 248fe56b9e6SYuval Mintz u8 num_tc; 249fe56b9e6SYuval Mintz u8 offload_tc; 250fe56b9e6SYuval Mintz u8 non_offload_tc; 251fe56b9e6SYuval Mintz 252fe56b9e6SYuval Mintz u32 concrete_fid; 253fe56b9e6SYuval Mintz u16 opaque_fid; 254fe56b9e6SYuval Mintz u16 ovlan; 255fe56b9e6SYuval Mintz u32 part_num[4]; 256fe56b9e6SYuval Mintz 257fe56b9e6SYuval Mintz unsigned char hw_mac_addr[ETH_ALEN]; 258fe56b9e6SYuval Mintz 259fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 260fe56b9e6SYuval Mintz 261fe56b9e6SYuval Mintz u32 port_mode; 262fe56b9e6SYuval Mintz u32 hw_mode; 263fc48b7a6SYuval Mintz unsigned long device_capabilities; 2640fefbfbaSSudarsana Kalluru u16 mtu; 26514d39648SMintz, Yuval 26614d39648SMintz, Yuval enum qed_wol_support b_wol_support; 267fe56b9e6SYuval Mintz }; 268fe56b9e6SYuval Mintz 269fe56b9e6SYuval Mintz /* maximun size of read/write commands (HW limit) */ 270fe56b9e6SYuval Mintz #define DMAE_MAX_RW_SIZE 0x2000 271fe56b9e6SYuval Mintz 272fe56b9e6SYuval Mintz struct qed_dmae_info { 273fe56b9e6SYuval Mintz /* Mutex for synchronizing access to functions */ 274fe56b9e6SYuval Mintz struct mutex mutex; 275fe56b9e6SYuval Mintz 276fe56b9e6SYuval Mintz u8 channel; 277fe56b9e6SYuval Mintz 278fe56b9e6SYuval Mintz dma_addr_t completion_word_phys_addr; 279fe56b9e6SYuval Mintz 280fe56b9e6SYuval Mintz /* The memory location where the DMAE writes the completion 281fe56b9e6SYuval Mintz * value when an operation is finished on this context. 282fe56b9e6SYuval Mintz */ 283fe56b9e6SYuval Mintz u32 *p_completion_word; 284fe56b9e6SYuval Mintz 285fe56b9e6SYuval Mintz dma_addr_t intermediate_buffer_phys_addr; 286fe56b9e6SYuval Mintz 287fe56b9e6SYuval Mintz /* An intermediate buffer for DMAE operations that use virtual 288fe56b9e6SYuval Mintz * addresses - data is DMA'd to/from this buffer and then 289fe56b9e6SYuval Mintz * memcpy'd to/from the virtual address 290fe56b9e6SYuval Mintz */ 291fe56b9e6SYuval Mintz u32 *p_intermediate_buffer; 292fe56b9e6SYuval Mintz 293fe56b9e6SYuval Mintz dma_addr_t dmae_cmd_phys_addr; 294fe56b9e6SYuval Mintz struct dmae_cmd *p_dmae_cmd; 295fe56b9e6SYuval Mintz }; 296fe56b9e6SYuval Mintz 297bcd197c8SManish Chopra struct qed_wfq_data { 298bcd197c8SManish Chopra /* when feature is configured for at least 1 vport */ 299bcd197c8SManish Chopra u32 min_speed; 300bcd197c8SManish Chopra bool configured; 301bcd197c8SManish Chopra }; 302bcd197c8SManish Chopra 303fe56b9e6SYuval Mintz struct qed_qm_info { 304fe56b9e6SYuval Mintz struct init_qm_pq_params *qm_pq_params; 305fe56b9e6SYuval Mintz struct init_qm_vport_params *qm_vport_params; 306fe56b9e6SYuval Mintz struct init_qm_port_params *qm_port_params; 307fe56b9e6SYuval Mintz u16 start_pq; 308fe56b9e6SYuval Mintz u8 start_vport; 309fe56b9e6SYuval Mintz u8 pure_lb_pq; 310fe56b9e6SYuval Mintz u8 offload_pq; 311fe56b9e6SYuval Mintz u8 pure_ack_pq; 312dbb799c3SYuval Mintz u8 ooo_pq; 313fe56b9e6SYuval Mintz u8 vf_queues_offset; 314fe56b9e6SYuval Mintz u16 num_pqs; 315fe56b9e6SYuval Mintz u16 num_vf_pqs; 316fe56b9e6SYuval Mintz u8 num_vports; 317fe56b9e6SYuval Mintz u8 max_phys_tcs_per_port; 318fe56b9e6SYuval Mintz bool pf_rl_en; 319fe56b9e6SYuval Mintz bool pf_wfq_en; 320fe56b9e6SYuval Mintz bool vport_rl_en; 321fe56b9e6SYuval Mintz bool vport_wfq_en; 322fe56b9e6SYuval Mintz u8 pf_wfq; 323fe56b9e6SYuval Mintz u32 pf_rl; 324bcd197c8SManish Chopra struct qed_wfq_data *wfq_data; 325dbb799c3SYuval Mintz u8 num_pf_rls; 326fe56b9e6SYuval Mintz }; 327fe56b9e6SYuval Mintz 3289df2ed04SManish Chopra struct storm_stats { 3299df2ed04SManish Chopra u32 address; 3309df2ed04SManish Chopra u32 len; 3319df2ed04SManish Chopra }; 3329df2ed04SManish Chopra 3339df2ed04SManish Chopra struct qed_storm_stats { 3349df2ed04SManish Chopra struct storm_stats mstats; 3359df2ed04SManish Chopra struct storm_stats pstats; 3369df2ed04SManish Chopra struct storm_stats tstats; 3379df2ed04SManish Chopra struct storm_stats ustats; 3389df2ed04SManish Chopra }; 3399df2ed04SManish Chopra 340fe56b9e6SYuval Mintz struct qed_fw_data { 3419df2ed04SManish Chopra struct fw_ver_info *fw_ver_info; 342fe56b9e6SYuval Mintz const u8 *modes_tree_buf; 343fe56b9e6SYuval Mintz union init_op *init_ops; 344fe56b9e6SYuval Mintz const u32 *arr_data; 345fe56b9e6SYuval Mintz u32 init_ops_size; 346fe56b9e6SYuval Mintz }; 347fe56b9e6SYuval Mintz 348fe56b9e6SYuval Mintz struct qed_simd_fp_handler { 349fe56b9e6SYuval Mintz void *token; 350fe56b9e6SYuval Mintz void (*func)(void *); 351fe56b9e6SYuval Mintz }; 352fe56b9e6SYuval Mintz 353fe56b9e6SYuval Mintz struct qed_hwfn { 354fe56b9e6SYuval Mintz struct qed_dev *cdev; 355fe56b9e6SYuval Mintz u8 my_id; /* ID inside the PF */ 356fe56b9e6SYuval Mintz #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) 357fe56b9e6SYuval Mintz u8 rel_pf_id; /* Relative to engine*/ 358fe56b9e6SYuval Mintz u8 abs_pf_id; 359fe56b9e6SYuval Mintz #define QED_PATH_ID(_p_hwfn) ((_p_hwfn)->abs_pf_id & 1) 360fe56b9e6SYuval Mintz u8 port_id; 361fe56b9e6SYuval Mintz bool b_active; 362fe56b9e6SYuval Mintz 363fe56b9e6SYuval Mintz u32 dp_module; 364fe56b9e6SYuval Mintz u8 dp_level; 365fe56b9e6SYuval Mintz char name[NAME_SIZE]; 366fe56b9e6SYuval Mintz 367fe56b9e6SYuval Mintz bool first_on_engine; 368fe56b9e6SYuval Mintz bool hw_init_done; 369fe56b9e6SYuval Mintz 3701408cc1fSYuval Mintz u8 num_funcs_on_engine; 371dbb799c3SYuval Mintz u8 enabled_func_idx; 3721408cc1fSYuval Mintz 373fe56b9e6SYuval Mintz /* BAR access */ 374fe56b9e6SYuval Mintz void __iomem *regview; 375fe56b9e6SYuval Mintz void __iomem *doorbells; 376fe56b9e6SYuval Mintz u64 db_phys_addr; 377fe56b9e6SYuval Mintz unsigned long db_size; 378fe56b9e6SYuval Mintz 379fe56b9e6SYuval Mintz /* PTT pool */ 380fe56b9e6SYuval Mintz struct qed_ptt_pool *p_ptt_pool; 381fe56b9e6SYuval Mintz 382fe56b9e6SYuval Mintz /* HW info */ 383fe56b9e6SYuval Mintz struct qed_hw_info hw_info; 384fe56b9e6SYuval Mintz 385fe56b9e6SYuval Mintz /* rt_array (for init-tool) */ 386fc48b7a6SYuval Mintz struct qed_rt_data rt_data; 387fe56b9e6SYuval Mintz 388fe56b9e6SYuval Mintz /* SPQ */ 389fe56b9e6SYuval Mintz struct qed_spq *p_spq; 390fe56b9e6SYuval Mintz 391fe56b9e6SYuval Mintz /* EQ */ 392fe56b9e6SYuval Mintz struct qed_eq *p_eq; 393fe56b9e6SYuval Mintz 394fe56b9e6SYuval Mintz /* Consolidate Q*/ 395fe56b9e6SYuval Mintz struct qed_consq *p_consq; 396fe56b9e6SYuval Mintz 397fe56b9e6SYuval Mintz /* Slow-Path definitions */ 398fe56b9e6SYuval Mintz struct tasklet_struct *sp_dpc; 399fe56b9e6SYuval Mintz bool b_sp_dpc_enabled; 400fe56b9e6SYuval Mintz 401fe56b9e6SYuval Mintz struct qed_ptt *p_main_ptt; 402fe56b9e6SYuval Mintz struct qed_ptt *p_dpc_ptt; 403fe56b9e6SYuval Mintz 404fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb; 405fe56b9e6SYuval Mintz struct qed_sb_attn_info *p_sb_attn; 406fe56b9e6SYuval Mintz 407fe56b9e6SYuval Mintz /* Protocol related */ 4080a7fb11cSYuval Mintz bool using_ll2; 4090a7fb11cSYuval Mintz struct qed_ll2_info *p_ll2_info; 4101d6cff4fSYuval Mintz struct qed_ooo_info *p_ooo_info; 41151ff1725SRam Amrani struct qed_rdma_info *p_rdma_info; 412fc831825SYuval Mintz struct qed_iscsi_info *p_iscsi_info; 413fe56b9e6SYuval Mintz struct qed_pf_params pf_params; 414fe56b9e6SYuval Mintz 415dbb799c3SYuval Mintz bool b_rdma_enabled_in_prs; 416dbb799c3SYuval Mintz u32 rdma_prs_search_reg; 417dbb799c3SYuval Mintz 418fe56b9e6SYuval Mintz /* Array of sb_info of all status blocks */ 419fe56b9e6SYuval Mintz struct qed_sb_info *sbs_info[MAX_SB_PER_PF_MIMD]; 420fe56b9e6SYuval Mintz u16 num_sbs; 421fe56b9e6SYuval Mintz 422fe56b9e6SYuval Mintz struct qed_cxt_mngr *p_cxt_mngr; 423fe56b9e6SYuval Mintz 424fe56b9e6SYuval Mintz /* Flag indicating whether interrupts are enabled or not*/ 425fe56b9e6SYuval Mintz bool b_int_enabled; 4268f16bc97SSudarsana Kalluru bool b_int_requested; 427fe56b9e6SYuval Mintz 428fc916ff2SSudarsana Reddy Kalluru /* True if the driver requests for the link */ 429fc916ff2SSudarsana Reddy Kalluru bool b_drv_link_init; 430fc916ff2SSudarsana Reddy Kalluru 4311408cc1fSYuval Mintz struct qed_vf_iov *vf_iov_info; 43232a47e72SYuval Mintz struct qed_pf_iov *pf_iov_info; 433fe56b9e6SYuval Mintz struct qed_mcp_info *mcp_info; 434fe56b9e6SYuval Mintz 43539651abdSSudarsana Reddy Kalluru struct qed_dcbx_info *p_dcbx_info; 43639651abdSSudarsana Reddy Kalluru 437fe56b9e6SYuval Mintz struct qed_dmae_info dmae_info; 438fe56b9e6SYuval Mintz 439fe56b9e6SYuval Mintz /* QM init */ 440fe56b9e6SYuval Mintz struct qed_qm_info qm_info; 4419df2ed04SManish Chopra struct qed_storm_stats storm_stats; 442fe56b9e6SYuval Mintz 443fe56b9e6SYuval Mintz /* Buffer for unzipping firmware data */ 444fe56b9e6SYuval Mintz void *unzip_buf; 445fe56b9e6SYuval Mintz 446c965db44STomer Tayar struct dbg_tools_data dbg_info; 447c965db44STomer Tayar 44851ff1725SRam Amrani /* PWM region specific data */ 44951ff1725SRam Amrani u32 dpi_size; 45051ff1725SRam Amrani u32 dpi_count; 45151ff1725SRam Amrani 45251ff1725SRam Amrani /* This is used to calculate the doorbell address */ 45351ff1725SRam Amrani u32 dpi_start_offset; 45451ff1725SRam Amrani 45551ff1725SRam Amrani /* If one of the following is set then EDPM shouldn't be used */ 45651ff1725SRam Amrani u8 dcbx_no_edpm; 45751ff1725SRam Amrani u8 db_bar_no_edpm; 45851ff1725SRam Amrani 459fe56b9e6SYuval Mintz struct qed_simd_fp_handler simd_proto_handler[64]; 460fe56b9e6SYuval Mintz 46137bff2b9SYuval Mintz #ifdef CONFIG_QED_SRIOV 46237bff2b9SYuval Mintz struct workqueue_struct *iov_wq; 46337bff2b9SYuval Mintz struct delayed_work iov_task; 46437bff2b9SYuval Mintz unsigned long iov_task_flags; 46537bff2b9SYuval Mintz #endif 46637bff2b9SYuval Mintz 467fe56b9e6SYuval Mintz struct z_stream_s *stream; 468abd49676SRam Amrani struct qed_roce_ll2_info *ll2; 469fe56b9e6SYuval Mintz }; 470fe56b9e6SYuval Mintz 471fe56b9e6SYuval Mintz struct pci_params { 472fe56b9e6SYuval Mintz int pm_cap; 473fe56b9e6SYuval Mintz 474fe56b9e6SYuval Mintz unsigned long mem_start; 475fe56b9e6SYuval Mintz unsigned long mem_end; 476fe56b9e6SYuval Mintz unsigned int irq; 477fe56b9e6SYuval Mintz u8 pf_num; 478fe56b9e6SYuval Mintz }; 479fe56b9e6SYuval Mintz 480fe56b9e6SYuval Mintz struct qed_int_param { 481fe56b9e6SYuval Mintz u32 int_mode; 482fe56b9e6SYuval Mintz u8 num_vectors; 483fe56b9e6SYuval Mintz u8 min_msix_cnt; /* for minimal functionality */ 484fe56b9e6SYuval Mintz }; 485fe56b9e6SYuval Mintz 486fe56b9e6SYuval Mintz struct qed_int_params { 487fe56b9e6SYuval Mintz struct qed_int_param in; 488fe56b9e6SYuval Mintz struct qed_int_param out; 489fe56b9e6SYuval Mintz struct msix_entry *msix_table; 490fe56b9e6SYuval Mintz bool fp_initialized; 491fe56b9e6SYuval Mintz u8 fp_msix_base; 492fe56b9e6SYuval Mintz u8 fp_msix_cnt; 49351ff1725SRam Amrani u8 rdma_msix_base; 49451ff1725SRam Amrani u8 rdma_msix_cnt; 495fe56b9e6SYuval Mintz }; 496fe56b9e6SYuval Mintz 497c965db44STomer Tayar struct qed_dbg_feature { 498c965db44STomer Tayar struct dentry *dentry; 499c965db44STomer Tayar u8 *dump_buf; 500c965db44STomer Tayar u32 buf_size; 501c965db44STomer Tayar u32 dumped_dwords; 502c965db44STomer Tayar }; 503c965db44STomer Tayar 504c965db44STomer Tayar struct qed_dbg_params { 505c965db44STomer Tayar struct qed_dbg_feature features[DBG_FEATURE_NUM]; 506c965db44STomer Tayar u8 engine_for_debug; 507c965db44STomer Tayar bool print_data; 508c965db44STomer Tayar }; 509c965db44STomer Tayar 510fe56b9e6SYuval Mintz struct qed_dev { 511fe56b9e6SYuval Mintz u32 dp_module; 512fe56b9e6SYuval Mintz u8 dp_level; 513fe56b9e6SYuval Mintz char name[NAME_SIZE]; 514fe56b9e6SYuval Mintz 515fe56b9e6SYuval Mintz u8 type; 516fc48b7a6SYuval Mintz #define QED_DEV_TYPE_BB (0 << 0) 517fc48b7a6SYuval Mintz #define QED_DEV_TYPE_AH BIT(0) 518fc48b7a6SYuval Mintz /* Translate type/revision combo into the proper conditions */ 519fc48b7a6SYuval Mintz #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB) 520fc48b7a6SYuval Mintz #define QED_IS_BB_A0(dev) (QED_IS_BB(dev) && \ 521fc48b7a6SYuval Mintz CHIP_REV_IS_A0(dev)) 522fc48b7a6SYuval Mintz #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \ 523fc48b7a6SYuval Mintz CHIP_REV_IS_B0(dev)) 524c965db44STomer Tayar #define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH) 525c965db44STomer Tayar #define QED_IS_K2(dev) QED_IS_AH(dev) 526fc48b7a6SYuval Mintz 527fc48b7a6SYuval Mintz #define QED_GET_TYPE(dev) (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \ 528fc48b7a6SYuval Mintz QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2) 529fc48b7a6SYuval Mintz 530fc48b7a6SYuval Mintz u16 vendor_id; 531fc48b7a6SYuval Mintz u16 device_id; 532fe56b9e6SYuval Mintz 533fe56b9e6SYuval Mintz u16 chip_num; 534fe56b9e6SYuval Mintz #define CHIP_NUM_MASK 0xffff 535fe56b9e6SYuval Mintz #define CHIP_NUM_SHIFT 16 536fe56b9e6SYuval Mintz 537fe56b9e6SYuval Mintz u16 chip_rev; 538fe56b9e6SYuval Mintz #define CHIP_REV_MASK 0xf 539fe56b9e6SYuval Mintz #define CHIP_REV_SHIFT 12 540fc48b7a6SYuval Mintz #define CHIP_REV_IS_A0(_cdev) (!(_cdev)->chip_rev) 541fc48b7a6SYuval Mintz #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1) 542fe56b9e6SYuval Mintz 543fe56b9e6SYuval Mintz u16 chip_metal; 544fe56b9e6SYuval Mintz #define CHIP_METAL_MASK 0xff 545fe56b9e6SYuval Mintz #define CHIP_METAL_SHIFT 4 546fe56b9e6SYuval Mintz 547fe56b9e6SYuval Mintz u16 chip_bond_id; 548fe56b9e6SYuval Mintz #define CHIP_BOND_ID_MASK 0xf 549fe56b9e6SYuval Mintz #define CHIP_BOND_ID_SHIFT 0 550fe56b9e6SYuval Mintz 551fe56b9e6SYuval Mintz u8 num_engines; 552fe56b9e6SYuval Mintz u8 num_ports_in_engines; 553fe56b9e6SYuval Mintz u8 num_funcs_in_port; 554fe56b9e6SYuval Mintz 555fe56b9e6SYuval Mintz u8 path_id; 556fc48b7a6SYuval Mintz enum qed_mf_mode mf_mode; 557fc48b7a6SYuval Mintz #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT) 558fc48b7a6SYuval Mintz #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR) 559fc48b7a6SYuval Mintz #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN) 560fe56b9e6SYuval Mintz 561fe56b9e6SYuval Mintz int pcie_width; 562fe56b9e6SYuval Mintz int pcie_speed; 563fe56b9e6SYuval Mintz u8 ver_str[VER_SIZE]; 564fe56b9e6SYuval Mintz 565fe56b9e6SYuval Mintz /* Add MF related configuration */ 566fe56b9e6SYuval Mintz u8 mcp_rev; 567fe56b9e6SYuval Mintz u8 boot_mode; 568fe56b9e6SYuval Mintz 56914d39648SMintz, Yuval /* WoL related configurations */ 57014d39648SMintz, Yuval u8 wol_config; 57114d39648SMintz, Yuval u8 wol_mac[ETH_ALEN]; 572fe56b9e6SYuval Mintz 573fe56b9e6SYuval Mintz u32 int_mode; 574fe56b9e6SYuval Mintz enum qed_coalescing_mode int_coalescing_mode; 57551d99880SSudarsana Reddy Kalluru u16 rx_coalesce_usecs; 57651d99880SSudarsana Reddy Kalluru u16 tx_coalesce_usecs; 577fe56b9e6SYuval Mintz 578fe56b9e6SYuval Mintz /* Start Bar offset of first hwfn */ 579fe56b9e6SYuval Mintz void __iomem *regview; 580fe56b9e6SYuval Mintz void __iomem *doorbells; 581fe56b9e6SYuval Mintz u64 db_phys_addr; 582fe56b9e6SYuval Mintz unsigned long db_size; 583fe56b9e6SYuval Mintz 584fe56b9e6SYuval Mintz /* PCI */ 585fe56b9e6SYuval Mintz u8 cache_shift; 586fe56b9e6SYuval Mintz 587fe56b9e6SYuval Mintz /* Init */ 588fe56b9e6SYuval Mintz const struct iro *iro_arr; 589fe56b9e6SYuval Mintz #define IRO (p_hwfn->cdev->iro_arr) 590fe56b9e6SYuval Mintz 591fe56b9e6SYuval Mintz /* HW functions */ 592fe56b9e6SYuval Mintz u8 num_hwfns; 593fe56b9e6SYuval Mintz struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; 594fe56b9e6SYuval Mintz 59532a47e72SYuval Mintz /* SRIOV */ 59632a47e72SYuval Mintz struct qed_hw_sriov_info *p_iov_info; 59732a47e72SYuval Mintz #define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info) 59832a47e72SYuval Mintz 599464f6645SManish Chopra unsigned long tunn_mode; 6001408cc1fSYuval Mintz 6011408cc1fSYuval Mintz bool b_is_vf; 602fe56b9e6SYuval Mintz u32 drv_type; 603fe56b9e6SYuval Mintz struct qed_eth_stats *reset_stats; 604fe56b9e6SYuval Mintz struct qed_fw_data *fw_data; 605fe56b9e6SYuval Mintz 606fe56b9e6SYuval Mintz u32 mcp_nvm_resp; 607fe56b9e6SYuval Mintz 608fe56b9e6SYuval Mintz /* Linux specific here */ 609fe56b9e6SYuval Mintz struct qede_dev *edev; 610fe56b9e6SYuval Mintz struct pci_dev *pdev; 611fc831825SYuval Mintz u32 flags; 612fc831825SYuval Mintz #define QED_FLAG_STORAGE_STARTED (BIT(0)) 613fe56b9e6SYuval Mintz int msg_enable; 614fe56b9e6SYuval Mintz 615fe56b9e6SYuval Mintz struct pci_params pci_params; 616fe56b9e6SYuval Mintz 617fe56b9e6SYuval Mintz struct qed_int_params int_params; 618fe56b9e6SYuval Mintz 619fe56b9e6SYuval Mintz u8 protocol; 620fe56b9e6SYuval Mintz #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH) 621fe56b9e6SYuval Mintz 622cc875c2eSYuval Mintz /* Callbacks to protocol driver */ 623cc875c2eSYuval Mintz union { 624cc875c2eSYuval Mintz struct qed_common_cb_ops *common; 625cc875c2eSYuval Mintz struct qed_eth_cb_ops *eth; 626fc831825SYuval Mintz struct qed_iscsi_cb_ops *iscsi; 627cc875c2eSYuval Mintz } protocol_ops; 628cc875c2eSYuval Mintz void *ops_cookie; 629cc875c2eSYuval Mintz 630c965db44STomer Tayar struct qed_dbg_params dbg_params; 631c965db44STomer Tayar 6320a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 6330a7fb11cSYuval Mintz struct qed_cb_ll2_info *ll2; 6340a7fb11cSYuval Mintz u8 ll2_mac_address[ETH_ALEN]; 6350a7fb11cSYuval Mintz #endif 636fc831825SYuval Mintz DECLARE_HASHTABLE(connections, 10); 637fe56b9e6SYuval Mintz const struct firmware *firmware; 63851ff1725SRam Amrani 63951ff1725SRam Amrani u32 rdma_max_sge; 64051ff1725SRam Amrani u32 rdma_max_inline; 64151ff1725SRam Amrani u32 rdma_max_srq_sge; 642fe56b9e6SYuval Mintz }; 643fe56b9e6SYuval Mintz 64432a47e72SYuval Mintz #define NUM_OF_VFS(dev) MAX_NUM_VFS_BB 645dacd88d6SYuval Mintz #define NUM_OF_L2_QUEUES(dev) MAX_NUM_L2_QUEUES_BB 646fe56b9e6SYuval Mintz #define NUM_OF_SBS(dev) MAX_SB_PER_PATH_BB 647fe56b9e6SYuval Mintz #define NUM_OF_ENG_PFS(dev) MAX_NUM_PFS_BB 648fe56b9e6SYuval Mintz 649fe56b9e6SYuval Mintz /** 650fe56b9e6SYuval Mintz * @brief qed_concrete_to_sw_fid - get the sw function id from 651fe56b9e6SYuval Mintz * the concrete value. 652fe56b9e6SYuval Mintz * 653fe56b9e6SYuval Mintz * @param concrete_fid 654fe56b9e6SYuval Mintz * 655fe56b9e6SYuval Mintz * @return inline u8 656fe56b9e6SYuval Mintz */ 657fe56b9e6SYuval Mintz static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev, 658fe56b9e6SYuval Mintz u32 concrete_fid) 659fe56b9e6SYuval Mintz { 6604870e704SYuval Mintz u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); 661fe56b9e6SYuval Mintz u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); 6624870e704SYuval Mintz u8 vf_valid = GET_FIELD(concrete_fid, 6634870e704SYuval Mintz PXP_CONCRETE_FID_VFVALID); 6644870e704SYuval Mintz u8 sw_fid; 665fe56b9e6SYuval Mintz 6664870e704SYuval Mintz if (vf_valid) 6674870e704SYuval Mintz sw_fid = vfid + MAX_NUM_PFS; 6684870e704SYuval Mintz else 6694870e704SYuval Mintz sw_fid = pfid; 6704870e704SYuval Mintz 6714870e704SYuval Mintz return sw_fid; 672fe56b9e6SYuval Mintz } 673fe56b9e6SYuval Mintz 674fe56b9e6SYuval Mintz #define PURE_LB_TC 8 675dbb799c3SYuval Mintz #define OOO_LB_TC 9 676fe56b9e6SYuval Mintz 677733def6aSYuval Mintz int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate); 678bcd197c8SManish Chopra void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, u32 min_pf_rate); 679bcd197c8SManish Chopra 680733def6aSYuval Mintz void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 681fe56b9e6SYuval Mintz #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) 682fe56b9e6SYuval Mintz 683fe56b9e6SYuval Mintz /* Other Linux specific common definitions */ 684fe56b9e6SYuval Mintz #define DP_NAME(cdev) ((cdev)->name) 685fe56b9e6SYuval Mintz 686fe56b9e6SYuval Mintz #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\ 687fe56b9e6SYuval Mintz (cdev->regview) + \ 688fe56b9e6SYuval Mintz (offset)) 689fe56b9e6SYuval Mintz 690fe56b9e6SYuval Mintz #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset)) 691fe56b9e6SYuval Mintz #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset)) 692fe56b9e6SYuval Mintz #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset)) 693fe56b9e6SYuval Mintz 694fe56b9e6SYuval Mintz #define DOORBELL(cdev, db_addr, val) \ 695fe56b9e6SYuval Mintz writel((u32)val, (void __iomem *)((u8 __iomem *)\ 696fe56b9e6SYuval Mintz (cdev->doorbells) + (db_addr))) 697fe56b9e6SYuval Mintz 698fe56b9e6SYuval Mintz /* Prototypes */ 699fe56b9e6SYuval Mintz int qed_fill_dev_info(struct qed_dev *cdev, 700fe56b9e6SYuval Mintz struct qed_dev_info *dev_info); 701cc875c2eSYuval Mintz void qed_link_update(struct qed_hwfn *hwfn); 702fe56b9e6SYuval Mintz u32 qed_unzip_data(struct qed_hwfn *p_hwfn, 703fe56b9e6SYuval Mintz u32 input_len, u8 *input_buf, 704fe56b9e6SYuval Mintz u32 max_size, u8 *unzip_buf); 7056c754246SSudarsana Reddy Kalluru void qed_get_protocol_stats(struct qed_dev *cdev, 7066c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type type, 7076c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats *stats); 7088f16bc97SSudarsana Kalluru int qed_slowpath_irq_req(struct qed_hwfn *hwfn); 7098f16bc97SSudarsana Kalluru 710fe56b9e6SYuval Mintz #endif /* _QED_H */ 711