1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #ifndef _QED_H 34fe56b9e6SYuval Mintz #define _QED_H 35fe56b9e6SYuval Mintz 36fe56b9e6SYuval Mintz #include <linux/types.h> 37fe56b9e6SYuval Mintz #include <linux/io.h> 38fe56b9e6SYuval Mintz #include <linux/delay.h> 39fe56b9e6SYuval Mintz #include <linux/firmware.h> 40fe56b9e6SYuval Mintz #include <linux/interrupt.h> 41fe56b9e6SYuval Mintz #include <linux/list.h> 42fe56b9e6SYuval Mintz #include <linux/mutex.h> 43fe56b9e6SYuval Mintz #include <linux/pci.h> 44fe56b9e6SYuval Mintz #include <linux/slab.h> 45fe56b9e6SYuval Mintz #include <linux/string.h> 46fe56b9e6SYuval Mintz #include <linux/workqueue.h> 47fe56b9e6SYuval Mintz #include <linux/zlib.h> 48fe56b9e6SYuval Mintz #include <linux/hashtable.h> 49fe56b9e6SYuval Mintz #include <linux/qed/qed_if.h> 50c965db44STomer Tayar #include "qed_debug.h" 51fe56b9e6SYuval Mintz #include "qed_hsi.h" 52fe56b9e6SYuval Mintz 5325c089d7SYuval Mintz extern const struct qed_common_ops qed_common_ops_pass; 545d24bcf1STomer Tayar 555d24bcf1STomer Tayar #define QED_MAJOR_VERSION 8 565d24bcf1STomer Tayar #define QED_MINOR_VERSION 10 575d24bcf1STomer Tayar #define QED_REVISION_VERSION 10 585d24bcf1STomer Tayar #define QED_ENGINEERING_VERSION 21 595d24bcf1STomer Tayar 605d24bcf1STomer Tayar #define QED_VERSION \ 615d24bcf1STomer Tayar ((QED_MAJOR_VERSION << 24) | (QED_MINOR_VERSION << 16) | \ 625d24bcf1STomer Tayar (QED_REVISION_VERSION << 8) | QED_ENGINEERING_VERSION) 635d24bcf1STomer Tayar 645d24bcf1STomer Tayar #define STORM_FW_VERSION \ 655d24bcf1STomer Tayar ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \ 665d24bcf1STomer Tayar (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION) 67fe56b9e6SYuval Mintz 68fe56b9e6SYuval Mintz #define MAX_HWFNS_PER_DEVICE (4) 69fe56b9e6SYuval Mintz #define NAME_SIZE 16 70fe56b9e6SYuval Mintz #define VER_SIZE 16 71fe56b9e6SYuval Mintz 72bcd197c8SManish Chopra #define QED_WFQ_UNIT 100 73bcd197c8SManish Chopra 7451ff1725SRam Amrani #define QED_WID_SIZE (1024) 7551ff1725SRam Amrani #define QED_PF_DEMS_SIZE (4) 7651ff1725SRam Amrani 77fe56b9e6SYuval Mintz /* cau states */ 78fe56b9e6SYuval Mintz enum qed_coalescing_mode { 79fe56b9e6SYuval Mintz QED_COAL_MODE_DISABLE, 80fe56b9e6SYuval Mintz QED_COAL_MODE_ENABLE 81fe56b9e6SYuval Mintz }; 82fe56b9e6SYuval Mintz 83fe56b9e6SYuval Mintz struct qed_eth_cb_ops; 84fe56b9e6SYuval Mintz struct qed_dev_info; 856c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats; 866c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type; 87fe56b9e6SYuval Mintz 88fe56b9e6SYuval Mintz /* helpers */ 895d24bcf1STomer Tayar #define QED_MFW_GET_FIELD(name, field) \ 905d24bcf1STomer Tayar (((name) & (field ## _MASK)) >> (field ## _SHIFT)) 915d24bcf1STomer Tayar 925d24bcf1STomer Tayar #define QED_MFW_SET_FIELD(name, field, value) \ 935d24bcf1STomer Tayar do { \ 945d24bcf1STomer Tayar (name) &= ~((field ## _MASK) << (field ## _SHIFT)); \ 955d24bcf1STomer Tayar (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\ 965d24bcf1STomer Tayar } while (0) 975d24bcf1STomer Tayar 98fe56b9e6SYuval Mintz static inline u32 qed_db_addr(u32 cid, u32 DEMS) 99fe56b9e6SYuval Mintz { 100fe56b9e6SYuval Mintz u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 10151ff1725SRam Amrani (cid * QED_PF_DEMS_SIZE); 10251ff1725SRam Amrani 10351ff1725SRam Amrani return db_addr; 10451ff1725SRam Amrani } 10551ff1725SRam Amrani 10651ff1725SRam Amrani static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS) 10751ff1725SRam Amrani { 10851ff1725SRam Amrani u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 109fe56b9e6SYuval Mintz FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); 110fe56b9e6SYuval Mintz 111fe56b9e6SYuval Mintz return db_addr; 112fe56b9e6SYuval Mintz } 113fe56b9e6SYuval Mintz 114fe56b9e6SYuval Mintz #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ 115fe56b9e6SYuval Mintz ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \ 116fe56b9e6SYuval Mintz ~((1 << (p_hwfn->cdev->cache_shift)) - 1)) 117fe56b9e6SYuval Mintz 118fe56b9e6SYuval Mintz #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++) 119fe56b9e6SYuval Mintz 120fe56b9e6SYuval Mintz #define D_TRINE(val, cond1, cond2, true1, true2, def) \ 121fe56b9e6SYuval Mintz (val == (cond1) ? true1 : \ 122fe56b9e6SYuval Mintz (val == (cond2) ? true2 : def)) 123fe56b9e6SYuval Mintz 124fe56b9e6SYuval Mintz /* forward */ 125fe56b9e6SYuval Mintz struct qed_ptt_pool; 126fe56b9e6SYuval Mintz struct qed_spq; 127fe56b9e6SYuval Mintz struct qed_sb_info; 128fe56b9e6SYuval Mintz struct qed_sb_attn_info; 129fe56b9e6SYuval Mintz struct qed_cxt_mngr; 130fe56b9e6SYuval Mintz struct qed_sb_sp_info; 1310a7fb11cSYuval Mintz struct qed_ll2_info; 132fe56b9e6SYuval Mintz struct qed_mcp_info; 133fe56b9e6SYuval Mintz 134fe56b9e6SYuval Mintz struct qed_rt_data { 135fc48b7a6SYuval Mintz u32 *init_val; 136fc48b7a6SYuval Mintz bool *b_valid; 137fe56b9e6SYuval Mintz }; 138fe56b9e6SYuval Mintz 139464f6645SManish Chopra enum qed_tunn_mode { 140464f6645SManish Chopra QED_MODE_L2GENEVE_TUNN, 141464f6645SManish Chopra QED_MODE_IPGENEVE_TUNN, 142464f6645SManish Chopra QED_MODE_L2GRE_TUNN, 143464f6645SManish Chopra QED_MODE_IPGRE_TUNN, 144464f6645SManish Chopra QED_MODE_VXLAN_TUNN, 145464f6645SManish Chopra }; 146464f6645SManish Chopra 147464f6645SManish Chopra enum qed_tunn_clss { 148464f6645SManish Chopra QED_TUNN_CLSS_MAC_VLAN, 149464f6645SManish Chopra QED_TUNN_CLSS_MAC_VNI, 150464f6645SManish Chopra QED_TUNN_CLSS_INNER_MAC_VLAN, 151464f6645SManish Chopra QED_TUNN_CLSS_INNER_MAC_VNI, 15219968430SChopra, Manish QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE, 153464f6645SManish Chopra MAX_QED_TUNN_CLSS, 154464f6645SManish Chopra }; 155464f6645SManish Chopra 15619968430SChopra, Manish struct qed_tunn_update_type { 15719968430SChopra, Manish bool b_update_mode; 15819968430SChopra, Manish bool b_mode_enabled; 15919968430SChopra, Manish enum qed_tunn_clss tun_cls; 16019968430SChopra, Manish }; 16119968430SChopra, Manish 16219968430SChopra, Manish struct qed_tunn_update_udp_port { 16319968430SChopra, Manish bool b_update_port; 16419968430SChopra, Manish u16 port; 16519968430SChopra, Manish }; 16619968430SChopra, Manish 16719968430SChopra, Manish struct qed_tunnel_info { 16819968430SChopra, Manish struct qed_tunn_update_type vxlan; 16919968430SChopra, Manish struct qed_tunn_update_type l2_geneve; 17019968430SChopra, Manish struct qed_tunn_update_type ip_geneve; 17119968430SChopra, Manish struct qed_tunn_update_type l2_gre; 17219968430SChopra, Manish struct qed_tunn_update_type ip_gre; 17319968430SChopra, Manish 17419968430SChopra, Manish struct qed_tunn_update_udp_port vxlan_port; 17519968430SChopra, Manish struct qed_tunn_update_udp_port geneve_port; 17619968430SChopra, Manish 17719968430SChopra, Manish bool b_update_rx_cls; 17819968430SChopra, Manish bool b_update_tx_cls; 17919968430SChopra, Manish }; 18019968430SChopra, Manish 181464f6645SManish Chopra struct qed_tunn_start_params { 182464f6645SManish Chopra unsigned long tunn_mode; 183464f6645SManish Chopra u16 vxlan_udp_port; 184464f6645SManish Chopra u16 geneve_udp_port; 185464f6645SManish Chopra u8 update_vxlan_udp_port; 186464f6645SManish Chopra u8 update_geneve_udp_port; 187464f6645SManish Chopra u8 tunn_clss_vxlan; 188464f6645SManish Chopra u8 tunn_clss_l2geneve; 189464f6645SManish Chopra u8 tunn_clss_ipgeneve; 190464f6645SManish Chopra u8 tunn_clss_l2gre; 191464f6645SManish Chopra u8 tunn_clss_ipgre; 192464f6645SManish Chopra }; 193464f6645SManish Chopra 194464f6645SManish Chopra struct qed_tunn_update_params { 195464f6645SManish Chopra unsigned long tunn_mode_update_mask; 196464f6645SManish Chopra unsigned long tunn_mode; 197464f6645SManish Chopra u16 vxlan_udp_port; 198464f6645SManish Chopra u16 geneve_udp_port; 199464f6645SManish Chopra u8 update_rx_pf_clss; 200464f6645SManish Chopra u8 update_tx_pf_clss; 201464f6645SManish Chopra u8 update_vxlan_udp_port; 202464f6645SManish Chopra u8 update_geneve_udp_port; 203464f6645SManish Chopra u8 tunn_clss_vxlan; 204464f6645SManish Chopra u8 tunn_clss_l2geneve; 205464f6645SManish Chopra u8 tunn_clss_ipgeneve; 206464f6645SManish Chopra u8 tunn_clss_l2gre; 207464f6645SManish Chopra u8 tunn_clss_ipgre; 208464f6645SManish Chopra }; 209464f6645SManish Chopra 210fe56b9e6SYuval Mintz /* The PCI personality is not quite synonymous to protocol ID: 211fe56b9e6SYuval Mintz * 1. All personalities need CORE connections 212fe56b9e6SYuval Mintz * 2. The Ethernet personality may support also the RoCE protocol 213fe56b9e6SYuval Mintz */ 214fe56b9e6SYuval Mintz enum qed_pci_personality { 215fe56b9e6SYuval Mintz QED_PCI_ETH, 2161e128c81SArun Easi QED_PCI_FCOE, 217c5ac9319SYuval Mintz QED_PCI_ISCSI, 218c5ac9319SYuval Mintz QED_PCI_ETH_ROCE, 219fe56b9e6SYuval Mintz QED_PCI_DEFAULT /* default in shmem */ 220fe56b9e6SYuval Mintz }; 221fe56b9e6SYuval Mintz 222fe56b9e6SYuval Mintz /* All VFs are symmetric, all counters are PF + all VFs */ 223fe56b9e6SYuval Mintz struct qed_qm_iids { 224fe56b9e6SYuval Mintz u32 cids; 225fe56b9e6SYuval Mintz u32 vf_cids; 226fe56b9e6SYuval Mintz u32 tids; 227fe56b9e6SYuval Mintz }; 228fe56b9e6SYuval Mintz 2292edbff8dSTomer Tayar /* HW / FW resources, output of features supported below, most information 2302edbff8dSTomer Tayar * is received from MFW. 2312edbff8dSTomer Tayar */ 2322edbff8dSTomer Tayar enum qed_resources { 233fe56b9e6SYuval Mintz QED_SB, 23425c089d7SYuval Mintz QED_L2_QUEUE, 235fe56b9e6SYuval Mintz QED_VPORT, 23625c089d7SYuval Mintz QED_RSS_ENG, 237fe56b9e6SYuval Mintz QED_PQ, 238fe56b9e6SYuval Mintz QED_RL, 23925c089d7SYuval Mintz QED_MAC, 24025c089d7SYuval Mintz QED_VLAN, 24151ff1725SRam Amrani QED_RDMA_CNQ_RAM, 242fe56b9e6SYuval Mintz QED_ILT, 2430a7fb11cSYuval Mintz QED_LL2_QUEUE, 2442edbff8dSTomer Tayar QED_CMDQS_CQS, 24551ff1725SRam Amrani QED_RDMA_STATS_QUEUE, 2469c8517c4STomer Tayar QED_BDQ, 247fe56b9e6SYuval Mintz QED_MAX_RESC, 248fe56b9e6SYuval Mintz }; 249fe56b9e6SYuval Mintz 25025c089d7SYuval Mintz enum QED_FEATURE { 25125c089d7SYuval Mintz QED_PF_L2_QUE, 25232a47e72SYuval Mintz QED_VF, 25351ff1725SRam Amrani QED_RDMA_CNQ, 25408737a3fSMintz, Yuval QED_ISCSI_CQ, 2551e128c81SArun Easi QED_FCOE_CQ, 25608737a3fSMintz, Yuval QED_VF_L2_QUE, 25725c089d7SYuval Mintz QED_MAX_FEATURES, 25825c089d7SYuval Mintz }; 25925c089d7SYuval Mintz 260cc875c2eSYuval Mintz enum QED_PORT_MODE { 261cc875c2eSYuval Mintz QED_PORT_MODE_DE_2X40G, 262cc875c2eSYuval Mintz QED_PORT_MODE_DE_2X50G, 263cc875c2eSYuval Mintz QED_PORT_MODE_DE_1X100G, 264cc875c2eSYuval Mintz QED_PORT_MODE_DE_4X10G_F, 265cc875c2eSYuval Mintz QED_PORT_MODE_DE_4X10G_E, 266cc875c2eSYuval Mintz QED_PORT_MODE_DE_4X20G, 267cc875c2eSYuval Mintz QED_PORT_MODE_DE_1X40G, 268cc875c2eSYuval Mintz QED_PORT_MODE_DE_2X25G, 2699c79ddaaSMintz, Yuval QED_PORT_MODE_DE_1X25G, 2709c79ddaaSMintz, Yuval QED_PORT_MODE_DE_4X25G, 2719c79ddaaSMintz, Yuval QED_PORT_MODE_DE_2X10G, 272cc875c2eSYuval Mintz }; 273cc875c2eSYuval Mintz 274fc48b7a6SYuval Mintz enum qed_dev_cap { 275fc48b7a6SYuval Mintz QED_DEV_CAP_ETH, 2761e128c81SArun Easi QED_DEV_CAP_FCOE, 277c5ac9319SYuval Mintz QED_DEV_CAP_ISCSI, 278c5ac9319SYuval Mintz QED_DEV_CAP_ROCE, 279fc48b7a6SYuval Mintz }; 280fc48b7a6SYuval Mintz 28114d39648SMintz, Yuval enum qed_wol_support { 28214d39648SMintz, Yuval QED_WOL_SUPPORT_NONE, 28314d39648SMintz, Yuval QED_WOL_SUPPORT_PME, 28414d39648SMintz, Yuval }; 28514d39648SMintz, Yuval 286fe56b9e6SYuval Mintz struct qed_hw_info { 287fe56b9e6SYuval Mintz /* PCI personality */ 288fe56b9e6SYuval Mintz enum qed_pci_personality personality; 289fe56b9e6SYuval Mintz 290fe56b9e6SYuval Mintz /* Resource Allocation scheme results */ 291fe56b9e6SYuval Mintz u32 resc_start[QED_MAX_RESC]; 292fe56b9e6SYuval Mintz u32 resc_num[QED_MAX_RESC]; 29325c089d7SYuval Mintz u32 feat_num[QED_MAX_FEATURES]; 294fe56b9e6SYuval Mintz 295fe56b9e6SYuval Mintz #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) 296fe56b9e6SYuval Mintz #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) 297dbb799c3SYuval Mintz #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ 298dbb799c3SYuval Mintz RESC_NUM(_p_hwfn, resc)) 299fe56b9e6SYuval Mintz #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) 300fe56b9e6SYuval Mintz 301b5a9ee7cSAriel Elior /* Amount of traffic classes HW supports */ 302b5a9ee7cSAriel Elior u8 num_hw_tc; 303b5a9ee7cSAriel Elior 304b5a9ee7cSAriel Elior /* Amount of TCs which should be active according to DCBx or upper 305b5a9ee7cSAriel Elior * layer driver configuration. 306b5a9ee7cSAriel Elior */ 307b5a9ee7cSAriel Elior u8 num_active_tc; 308fe56b9e6SYuval Mintz u8 offload_tc; 309fe56b9e6SYuval Mintz 310fe56b9e6SYuval Mintz u32 concrete_fid; 311fe56b9e6SYuval Mintz u16 opaque_fid; 312fe56b9e6SYuval Mintz u16 ovlan; 313fe56b9e6SYuval Mintz u32 part_num[4]; 314fe56b9e6SYuval Mintz 315fe56b9e6SYuval Mintz unsigned char hw_mac_addr[ETH_ALEN]; 3161e128c81SArun Easi u64 node_wwn; 3171e128c81SArun Easi u64 port_wwn; 3181e128c81SArun Easi 3191e128c81SArun Easi u16 num_fcoe_conns; 320fe56b9e6SYuval Mintz 321fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 322fe56b9e6SYuval Mintz 323fe56b9e6SYuval Mintz u32 port_mode; 324fe56b9e6SYuval Mintz u32 hw_mode; 325fc48b7a6SYuval Mintz unsigned long device_capabilities; 3260fefbfbaSSudarsana Kalluru u16 mtu; 32714d39648SMintz, Yuval 32814d39648SMintz, Yuval enum qed_wol_support b_wol_support; 329fe56b9e6SYuval Mintz }; 330fe56b9e6SYuval Mintz 331fe56b9e6SYuval Mintz /* maximun size of read/write commands (HW limit) */ 332fe56b9e6SYuval Mintz #define DMAE_MAX_RW_SIZE 0x2000 333fe56b9e6SYuval Mintz 334fe56b9e6SYuval Mintz struct qed_dmae_info { 335fe56b9e6SYuval Mintz /* Mutex for synchronizing access to functions */ 336fe56b9e6SYuval Mintz struct mutex mutex; 337fe56b9e6SYuval Mintz 338fe56b9e6SYuval Mintz u8 channel; 339fe56b9e6SYuval Mintz 340fe56b9e6SYuval Mintz dma_addr_t completion_word_phys_addr; 341fe56b9e6SYuval Mintz 342fe56b9e6SYuval Mintz /* The memory location where the DMAE writes the completion 343fe56b9e6SYuval Mintz * value when an operation is finished on this context. 344fe56b9e6SYuval Mintz */ 345fe56b9e6SYuval Mintz u32 *p_completion_word; 346fe56b9e6SYuval Mintz 347fe56b9e6SYuval Mintz dma_addr_t intermediate_buffer_phys_addr; 348fe56b9e6SYuval Mintz 349fe56b9e6SYuval Mintz /* An intermediate buffer for DMAE operations that use virtual 350fe56b9e6SYuval Mintz * addresses - data is DMA'd to/from this buffer and then 351fe56b9e6SYuval Mintz * memcpy'd to/from the virtual address 352fe56b9e6SYuval Mintz */ 353fe56b9e6SYuval Mintz u32 *p_intermediate_buffer; 354fe56b9e6SYuval Mintz 355fe56b9e6SYuval Mintz dma_addr_t dmae_cmd_phys_addr; 356fe56b9e6SYuval Mintz struct dmae_cmd *p_dmae_cmd; 357fe56b9e6SYuval Mintz }; 358fe56b9e6SYuval Mintz 359bcd197c8SManish Chopra struct qed_wfq_data { 360bcd197c8SManish Chopra /* when feature is configured for at least 1 vport */ 361bcd197c8SManish Chopra u32 min_speed; 362bcd197c8SManish Chopra bool configured; 363bcd197c8SManish Chopra }; 364bcd197c8SManish Chopra 365fe56b9e6SYuval Mintz struct qed_qm_info { 366fe56b9e6SYuval Mintz struct init_qm_pq_params *qm_pq_params; 367fe56b9e6SYuval Mintz struct init_qm_vport_params *qm_vport_params; 368fe56b9e6SYuval Mintz struct init_qm_port_params *qm_port_params; 369fe56b9e6SYuval Mintz u16 start_pq; 370fe56b9e6SYuval Mintz u8 start_vport; 371b5a9ee7cSAriel Elior u16 pure_lb_pq; 372b5a9ee7cSAriel Elior u16 offload_pq; 373b5a9ee7cSAriel Elior u16 low_latency_pq; 374b5a9ee7cSAriel Elior u16 pure_ack_pq; 375b5a9ee7cSAriel Elior u16 ooo_pq; 376b5a9ee7cSAriel Elior u16 first_vf_pq; 377b5a9ee7cSAriel Elior u16 first_mcos_pq; 378b5a9ee7cSAriel Elior u16 first_rl_pq; 379fe56b9e6SYuval Mintz u16 num_pqs; 380fe56b9e6SYuval Mintz u16 num_vf_pqs; 381fe56b9e6SYuval Mintz u8 num_vports; 382fe56b9e6SYuval Mintz u8 max_phys_tcs_per_port; 383b5a9ee7cSAriel Elior u8 ooo_tc; 384fe56b9e6SYuval Mintz bool pf_rl_en; 385fe56b9e6SYuval Mintz bool pf_wfq_en; 386fe56b9e6SYuval Mintz bool vport_rl_en; 387fe56b9e6SYuval Mintz bool vport_wfq_en; 388fe56b9e6SYuval Mintz u8 pf_wfq; 389fe56b9e6SYuval Mintz u32 pf_rl; 390bcd197c8SManish Chopra struct qed_wfq_data *wfq_data; 391dbb799c3SYuval Mintz u8 num_pf_rls; 392fe56b9e6SYuval Mintz }; 393fe56b9e6SYuval Mintz 3949df2ed04SManish Chopra struct storm_stats { 3959df2ed04SManish Chopra u32 address; 3969df2ed04SManish Chopra u32 len; 3979df2ed04SManish Chopra }; 3989df2ed04SManish Chopra 3999df2ed04SManish Chopra struct qed_storm_stats { 4009df2ed04SManish Chopra struct storm_stats mstats; 4019df2ed04SManish Chopra struct storm_stats pstats; 4029df2ed04SManish Chopra struct storm_stats tstats; 4039df2ed04SManish Chopra struct storm_stats ustats; 4049df2ed04SManish Chopra }; 4059df2ed04SManish Chopra 406fe56b9e6SYuval Mintz struct qed_fw_data { 4079df2ed04SManish Chopra struct fw_ver_info *fw_ver_info; 408fe56b9e6SYuval Mintz const u8 *modes_tree_buf; 409fe56b9e6SYuval Mintz union init_op *init_ops; 410fe56b9e6SYuval Mintz const u32 *arr_data; 411fe56b9e6SYuval Mintz u32 init_ops_size; 412fe56b9e6SYuval Mintz }; 413fe56b9e6SYuval Mintz 4145d24bcf1STomer Tayar #define DRV_MODULE_VERSION \ 4155d24bcf1STomer Tayar __stringify(QED_MAJOR_VERSION) "." \ 4165d24bcf1STomer Tayar __stringify(QED_MINOR_VERSION) "." \ 4175d24bcf1STomer Tayar __stringify(QED_REVISION_VERSION) "." \ 4185d24bcf1STomer Tayar __stringify(QED_ENGINEERING_VERSION) 4195d24bcf1STomer Tayar 420fe56b9e6SYuval Mintz struct qed_simd_fp_handler { 421fe56b9e6SYuval Mintz void *token; 422fe56b9e6SYuval Mintz void (*func)(void *); 423fe56b9e6SYuval Mintz }; 424fe56b9e6SYuval Mintz 425fe56b9e6SYuval Mintz struct qed_hwfn { 426fe56b9e6SYuval Mintz struct qed_dev *cdev; 427fe56b9e6SYuval Mintz u8 my_id; /* ID inside the PF */ 428fe56b9e6SYuval Mintz #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) 429fe56b9e6SYuval Mintz u8 rel_pf_id; /* Relative to engine*/ 430fe56b9e6SYuval Mintz u8 abs_pf_id; 4319c79ddaaSMintz, Yuval #define QED_PATH_ID(_p_hwfn) \ 4329c79ddaaSMintz, Yuval (QED_IS_K2((_p_hwfn)->cdev) ? 0 : ((_p_hwfn)->abs_pf_id & 1)) 433fe56b9e6SYuval Mintz u8 port_id; 434fe56b9e6SYuval Mintz bool b_active; 435fe56b9e6SYuval Mintz 436fe56b9e6SYuval Mintz u32 dp_module; 437fe56b9e6SYuval Mintz u8 dp_level; 438fe56b9e6SYuval Mintz char name[NAME_SIZE]; 439fe56b9e6SYuval Mintz 440fe56b9e6SYuval Mintz bool first_on_engine; 441fe56b9e6SYuval Mintz bool hw_init_done; 442fe56b9e6SYuval Mintz 4431408cc1fSYuval Mintz u8 num_funcs_on_engine; 444dbb799c3SYuval Mintz u8 enabled_func_idx; 4451408cc1fSYuval Mintz 446fe56b9e6SYuval Mintz /* BAR access */ 447fe56b9e6SYuval Mintz void __iomem *regview; 448fe56b9e6SYuval Mintz void __iomem *doorbells; 449fe56b9e6SYuval Mintz u64 db_phys_addr; 450fe56b9e6SYuval Mintz unsigned long db_size; 451fe56b9e6SYuval Mintz 452fe56b9e6SYuval Mintz /* PTT pool */ 453fe56b9e6SYuval Mintz struct qed_ptt_pool *p_ptt_pool; 454fe56b9e6SYuval Mintz 455fe56b9e6SYuval Mintz /* HW info */ 456fe56b9e6SYuval Mintz struct qed_hw_info hw_info; 457fe56b9e6SYuval Mintz 458fe56b9e6SYuval Mintz /* rt_array (for init-tool) */ 459fc48b7a6SYuval Mintz struct qed_rt_data rt_data; 460fe56b9e6SYuval Mintz 461fe56b9e6SYuval Mintz /* SPQ */ 462fe56b9e6SYuval Mintz struct qed_spq *p_spq; 463fe56b9e6SYuval Mintz 464fe56b9e6SYuval Mintz /* EQ */ 465fe56b9e6SYuval Mintz struct qed_eq *p_eq; 466fe56b9e6SYuval Mintz 467fe56b9e6SYuval Mintz /* Consolidate Q*/ 468fe56b9e6SYuval Mintz struct qed_consq *p_consq; 469fe56b9e6SYuval Mintz 470fe56b9e6SYuval Mintz /* Slow-Path definitions */ 471fe56b9e6SYuval Mintz struct tasklet_struct *sp_dpc; 472fe56b9e6SYuval Mintz bool b_sp_dpc_enabled; 473fe56b9e6SYuval Mintz 474fe56b9e6SYuval Mintz struct qed_ptt *p_main_ptt; 475fe56b9e6SYuval Mintz struct qed_ptt *p_dpc_ptt; 476fe56b9e6SYuval Mintz 477d179bd16Ssudarsana.kalluru@cavium.com /* PTP will be used only by the leading function. 478d179bd16Ssudarsana.kalluru@cavium.com * Usage of all PTP-apis should be synchronized as result. 479d179bd16Ssudarsana.kalluru@cavium.com */ 480d179bd16Ssudarsana.kalluru@cavium.com struct qed_ptt *p_ptp_ptt; 481d179bd16Ssudarsana.kalluru@cavium.com 482fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb; 483fe56b9e6SYuval Mintz struct qed_sb_attn_info *p_sb_attn; 484fe56b9e6SYuval Mintz 485fe56b9e6SYuval Mintz /* Protocol related */ 4860a7fb11cSYuval Mintz bool using_ll2; 4870a7fb11cSYuval Mintz struct qed_ll2_info *p_ll2_info; 4881d6cff4fSYuval Mintz struct qed_ooo_info *p_ooo_info; 48951ff1725SRam Amrani struct qed_rdma_info *p_rdma_info; 490fc831825SYuval Mintz struct qed_iscsi_info *p_iscsi_info; 4911e128c81SArun Easi struct qed_fcoe_info *p_fcoe_info; 492fe56b9e6SYuval Mintz struct qed_pf_params pf_params; 493fe56b9e6SYuval Mintz 494dbb799c3SYuval Mintz bool b_rdma_enabled_in_prs; 495dbb799c3SYuval Mintz u32 rdma_prs_search_reg; 496dbb799c3SYuval Mintz 497fe56b9e6SYuval Mintz /* Array of sb_info of all status blocks */ 498fe56b9e6SYuval Mintz struct qed_sb_info *sbs_info[MAX_SB_PER_PF_MIMD]; 499fe56b9e6SYuval Mintz u16 num_sbs; 500fe56b9e6SYuval Mintz 501fe56b9e6SYuval Mintz struct qed_cxt_mngr *p_cxt_mngr; 502fe56b9e6SYuval Mintz 503fe56b9e6SYuval Mintz /* Flag indicating whether interrupts are enabled or not*/ 504fe56b9e6SYuval Mintz bool b_int_enabled; 5058f16bc97SSudarsana Kalluru bool b_int_requested; 506fe56b9e6SYuval Mintz 507fc916ff2SSudarsana Reddy Kalluru /* True if the driver requests for the link */ 508fc916ff2SSudarsana Reddy Kalluru bool b_drv_link_init; 509fc916ff2SSudarsana Reddy Kalluru 5101408cc1fSYuval Mintz struct qed_vf_iov *vf_iov_info; 51132a47e72SYuval Mintz struct qed_pf_iov *pf_iov_info; 512fe56b9e6SYuval Mintz struct qed_mcp_info *mcp_info; 513fe56b9e6SYuval Mintz 51439651abdSSudarsana Reddy Kalluru struct qed_dcbx_info *p_dcbx_info; 51539651abdSSudarsana Reddy Kalluru 516fe56b9e6SYuval Mintz struct qed_dmae_info dmae_info; 517fe56b9e6SYuval Mintz 518fe56b9e6SYuval Mintz /* QM init */ 519fe56b9e6SYuval Mintz struct qed_qm_info qm_info; 5209df2ed04SManish Chopra struct qed_storm_stats storm_stats; 521fe56b9e6SYuval Mintz 522fe56b9e6SYuval Mintz /* Buffer for unzipping firmware data */ 523fe56b9e6SYuval Mintz void *unzip_buf; 524fe56b9e6SYuval Mintz 525c965db44STomer Tayar struct dbg_tools_data dbg_info; 526c965db44STomer Tayar 52751ff1725SRam Amrani /* PWM region specific data */ 52851ff1725SRam Amrani u32 dpi_size; 52951ff1725SRam Amrani u32 dpi_count; 53051ff1725SRam Amrani 53151ff1725SRam Amrani /* This is used to calculate the doorbell address */ 53251ff1725SRam Amrani u32 dpi_start_offset; 53351ff1725SRam Amrani 53451ff1725SRam Amrani /* If one of the following is set then EDPM shouldn't be used */ 53551ff1725SRam Amrani u8 dcbx_no_edpm; 53651ff1725SRam Amrani u8 db_bar_no_edpm; 53751ff1725SRam Amrani 538d51e4af5SChopra, Manish struct qed_ptt *p_arfs_ptt; 539d51e4af5SChopra, Manish 540fe56b9e6SYuval Mintz struct qed_simd_fp_handler simd_proto_handler[64]; 541fe56b9e6SYuval Mintz 54237bff2b9SYuval Mintz #ifdef CONFIG_QED_SRIOV 54337bff2b9SYuval Mintz struct workqueue_struct *iov_wq; 54437bff2b9SYuval Mintz struct delayed_work iov_task; 54537bff2b9SYuval Mintz unsigned long iov_task_flags; 54637bff2b9SYuval Mintz #endif 54737bff2b9SYuval Mintz 548fe56b9e6SYuval Mintz struct z_stream_s *stream; 549abd49676SRam Amrani struct qed_roce_ll2_info *ll2; 550fe56b9e6SYuval Mintz }; 551fe56b9e6SYuval Mintz 552fe56b9e6SYuval Mintz struct pci_params { 553fe56b9e6SYuval Mintz int pm_cap; 554fe56b9e6SYuval Mintz 555fe56b9e6SYuval Mintz unsigned long mem_start; 556fe56b9e6SYuval Mintz unsigned long mem_end; 557fe56b9e6SYuval Mintz unsigned int irq; 558fe56b9e6SYuval Mintz u8 pf_num; 559fe56b9e6SYuval Mintz }; 560fe56b9e6SYuval Mintz 561fe56b9e6SYuval Mintz struct qed_int_param { 562fe56b9e6SYuval Mintz u32 int_mode; 563fe56b9e6SYuval Mintz u8 num_vectors; 564fe56b9e6SYuval Mintz u8 min_msix_cnt; /* for minimal functionality */ 565fe56b9e6SYuval Mintz }; 566fe56b9e6SYuval Mintz 567fe56b9e6SYuval Mintz struct qed_int_params { 568fe56b9e6SYuval Mintz struct qed_int_param in; 569fe56b9e6SYuval Mintz struct qed_int_param out; 570fe56b9e6SYuval Mintz struct msix_entry *msix_table; 571fe56b9e6SYuval Mintz bool fp_initialized; 572fe56b9e6SYuval Mintz u8 fp_msix_base; 573fe56b9e6SYuval Mintz u8 fp_msix_cnt; 57451ff1725SRam Amrani u8 rdma_msix_base; 57551ff1725SRam Amrani u8 rdma_msix_cnt; 576fe56b9e6SYuval Mintz }; 577fe56b9e6SYuval Mintz 578c965db44STomer Tayar struct qed_dbg_feature { 579c965db44STomer Tayar struct dentry *dentry; 580c965db44STomer Tayar u8 *dump_buf; 581c965db44STomer Tayar u32 buf_size; 582c965db44STomer Tayar u32 dumped_dwords; 583c965db44STomer Tayar }; 584c965db44STomer Tayar 585c965db44STomer Tayar struct qed_dbg_params { 586c965db44STomer Tayar struct qed_dbg_feature features[DBG_FEATURE_NUM]; 587c965db44STomer Tayar u8 engine_for_debug; 588c965db44STomer Tayar bool print_data; 589c965db44STomer Tayar }; 590c965db44STomer Tayar 591fe56b9e6SYuval Mintz struct qed_dev { 592fe56b9e6SYuval Mintz u32 dp_module; 593fe56b9e6SYuval Mintz u8 dp_level; 594fe56b9e6SYuval Mintz char name[NAME_SIZE]; 595fe56b9e6SYuval Mintz 5969c79ddaaSMintz, Yuval enum qed_dev_type type; 597fc48b7a6SYuval Mintz /* Translate type/revision combo into the proper conditions */ 598fc48b7a6SYuval Mintz #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB) 599fc48b7a6SYuval Mintz #define QED_IS_BB_A0(dev) (QED_IS_BB(dev) && \ 600fc48b7a6SYuval Mintz CHIP_REV_IS_A0(dev)) 601fc48b7a6SYuval Mintz #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \ 602fc48b7a6SYuval Mintz CHIP_REV_IS_B0(dev)) 603c965db44STomer Tayar #define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH) 604c965db44STomer Tayar #define QED_IS_K2(dev) QED_IS_AH(dev) 605fc48b7a6SYuval Mintz 606fc48b7a6SYuval Mintz #define QED_GET_TYPE(dev) (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \ 607fc48b7a6SYuval Mintz QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2) 608fc48b7a6SYuval Mintz 609fc48b7a6SYuval Mintz u16 vendor_id; 610fc48b7a6SYuval Mintz u16 device_id; 6119c79ddaaSMintz, Yuval #define QED_DEV_ID_MASK 0xff00 6129c79ddaaSMintz, Yuval #define QED_DEV_ID_MASK_BB 0x1600 6139c79ddaaSMintz, Yuval #define QED_DEV_ID_MASK_AH 0x8000 614fe56b9e6SYuval Mintz 615fe56b9e6SYuval Mintz u16 chip_num; 616fe56b9e6SYuval Mintz #define CHIP_NUM_MASK 0xffff 617fe56b9e6SYuval Mintz #define CHIP_NUM_SHIFT 16 618fe56b9e6SYuval Mintz 619fe56b9e6SYuval Mintz u16 chip_rev; 620fe56b9e6SYuval Mintz #define CHIP_REV_MASK 0xf 621fe56b9e6SYuval Mintz #define CHIP_REV_SHIFT 12 622fc48b7a6SYuval Mintz #define CHIP_REV_IS_A0(_cdev) (!(_cdev)->chip_rev) 623fc48b7a6SYuval Mintz #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1) 624fe56b9e6SYuval Mintz 625fe56b9e6SYuval Mintz u16 chip_metal; 626fe56b9e6SYuval Mintz #define CHIP_METAL_MASK 0xff 627fe56b9e6SYuval Mintz #define CHIP_METAL_SHIFT 4 628fe56b9e6SYuval Mintz 629fe56b9e6SYuval Mintz u16 chip_bond_id; 630fe56b9e6SYuval Mintz #define CHIP_BOND_ID_MASK 0xf 631fe56b9e6SYuval Mintz #define CHIP_BOND_ID_SHIFT 0 632fe56b9e6SYuval Mintz 633fe56b9e6SYuval Mintz u8 num_engines; 634fe56b9e6SYuval Mintz u8 num_ports_in_engines; 635fe56b9e6SYuval Mintz u8 num_funcs_in_port; 636fe56b9e6SYuval Mintz 637fe56b9e6SYuval Mintz u8 path_id; 638fc48b7a6SYuval Mintz enum qed_mf_mode mf_mode; 639fc48b7a6SYuval Mintz #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT) 640fc48b7a6SYuval Mintz #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR) 641fc48b7a6SYuval Mintz #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN) 642fe56b9e6SYuval Mintz 643fe56b9e6SYuval Mintz int pcie_width; 644fe56b9e6SYuval Mintz int pcie_speed; 645fe56b9e6SYuval Mintz u8 ver_str[VER_SIZE]; 646fe56b9e6SYuval Mintz 647fe56b9e6SYuval Mintz /* Add MF related configuration */ 648fe56b9e6SYuval Mintz u8 mcp_rev; 649fe56b9e6SYuval Mintz u8 boot_mode; 650fe56b9e6SYuval Mintz 65114d39648SMintz, Yuval /* WoL related configurations */ 65214d39648SMintz, Yuval u8 wol_config; 65314d39648SMintz, Yuval u8 wol_mac[ETH_ALEN]; 654fe56b9e6SYuval Mintz 655fe56b9e6SYuval Mintz u32 int_mode; 656fe56b9e6SYuval Mintz enum qed_coalescing_mode int_coalescing_mode; 65751d99880SSudarsana Reddy Kalluru u16 rx_coalesce_usecs; 65851d99880SSudarsana Reddy Kalluru u16 tx_coalesce_usecs; 659fe56b9e6SYuval Mintz 660fe56b9e6SYuval Mintz /* Start Bar offset of first hwfn */ 661fe56b9e6SYuval Mintz void __iomem *regview; 662fe56b9e6SYuval Mintz void __iomem *doorbells; 663fe56b9e6SYuval Mintz u64 db_phys_addr; 664fe56b9e6SYuval Mintz unsigned long db_size; 665fe56b9e6SYuval Mintz 666fe56b9e6SYuval Mintz /* PCI */ 667fe56b9e6SYuval Mintz u8 cache_shift; 668fe56b9e6SYuval Mintz 669fe56b9e6SYuval Mintz /* Init */ 670fe56b9e6SYuval Mintz const struct iro *iro_arr; 671fe56b9e6SYuval Mintz #define IRO (p_hwfn->cdev->iro_arr) 672fe56b9e6SYuval Mintz 673fe56b9e6SYuval Mintz /* HW functions */ 674fe56b9e6SYuval Mintz u8 num_hwfns; 675fe56b9e6SYuval Mintz struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; 676fe56b9e6SYuval Mintz 67732a47e72SYuval Mintz /* SRIOV */ 67832a47e72SYuval Mintz struct qed_hw_sriov_info *p_iov_info; 67932a47e72SYuval Mintz #define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info) 68019968430SChopra, Manish struct qed_tunnel_info tunnel; 6811408cc1fSYuval Mintz bool b_is_vf; 682fe56b9e6SYuval Mintz u32 drv_type; 683fe56b9e6SYuval Mintz struct qed_eth_stats *reset_stats; 684fe56b9e6SYuval Mintz struct qed_fw_data *fw_data; 685fe56b9e6SYuval Mintz 686fe56b9e6SYuval Mintz u32 mcp_nvm_resp; 687fe56b9e6SYuval Mintz 688fe56b9e6SYuval Mintz /* Linux specific here */ 689fe56b9e6SYuval Mintz struct qede_dev *edev; 690fe56b9e6SYuval Mintz struct pci_dev *pdev; 691fc831825SYuval Mintz u32 flags; 692fc831825SYuval Mintz #define QED_FLAG_STORAGE_STARTED (BIT(0)) 693fe56b9e6SYuval Mintz int msg_enable; 694fe56b9e6SYuval Mintz 695fe56b9e6SYuval Mintz struct pci_params pci_params; 696fe56b9e6SYuval Mintz 697fe56b9e6SYuval Mintz struct qed_int_params int_params; 698fe56b9e6SYuval Mintz 699fe56b9e6SYuval Mintz u8 protocol; 700fe56b9e6SYuval Mintz #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH) 7011e128c81SArun Easi #define IS_QED_FCOE_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_FCOE) 702fe56b9e6SYuval Mintz 703cc875c2eSYuval Mintz /* Callbacks to protocol driver */ 704cc875c2eSYuval Mintz union { 705cc875c2eSYuval Mintz struct qed_common_cb_ops *common; 706cc875c2eSYuval Mintz struct qed_eth_cb_ops *eth; 7071e128c81SArun Easi struct qed_fcoe_cb_ops *fcoe; 708fc831825SYuval Mintz struct qed_iscsi_cb_ops *iscsi; 709cc875c2eSYuval Mintz } protocol_ops; 710cc875c2eSYuval Mintz void *ops_cookie; 711cc875c2eSYuval Mintz 712c965db44STomer Tayar struct qed_dbg_params dbg_params; 713c965db44STomer Tayar 7140a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 7150a7fb11cSYuval Mintz struct qed_cb_ll2_info *ll2; 7160a7fb11cSYuval Mintz u8 ll2_mac_address[ETH_ALEN]; 7170a7fb11cSYuval Mintz #endif 718fc831825SYuval Mintz DECLARE_HASHTABLE(connections, 10); 719fe56b9e6SYuval Mintz const struct firmware *firmware; 72051ff1725SRam Amrani 72151ff1725SRam Amrani u32 rdma_max_sge; 72251ff1725SRam Amrani u32 rdma_max_inline; 72351ff1725SRam Amrani u32 rdma_max_srq_sge; 724eaf3c0c6SChopra, Manish u16 tunn_feature_mask; 725fe56b9e6SYuval Mintz }; 726fe56b9e6SYuval Mintz 7279c79ddaaSMintz, Yuval #define NUM_OF_VFS(dev) (QED_IS_BB(dev) ? MAX_NUM_VFS_BB \ 7289c79ddaaSMintz, Yuval : MAX_NUM_VFS_K2) 7299c79ddaaSMintz, Yuval #define NUM_OF_L2_QUEUES(dev) (QED_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \ 7309c79ddaaSMintz, Yuval : MAX_NUM_L2_QUEUES_K2) 7319c79ddaaSMintz, Yuval #define NUM_OF_PORTS(dev) (QED_IS_BB(dev) ? MAX_NUM_PORTS_BB \ 7329c79ddaaSMintz, Yuval : MAX_NUM_PORTS_K2) 7339c79ddaaSMintz, Yuval #define NUM_OF_SBS(dev) (QED_IS_BB(dev) ? MAX_SB_PER_PATH_BB \ 7349c79ddaaSMintz, Yuval : MAX_SB_PER_PATH_K2) 7359c79ddaaSMintz, Yuval #define NUM_OF_ENG_PFS(dev) (QED_IS_BB(dev) ? MAX_NUM_PFS_BB \ 7369c79ddaaSMintz, Yuval : MAX_NUM_PFS_K2) 737fe56b9e6SYuval Mintz 738fe56b9e6SYuval Mintz /** 739fe56b9e6SYuval Mintz * @brief qed_concrete_to_sw_fid - get the sw function id from 740fe56b9e6SYuval Mintz * the concrete value. 741fe56b9e6SYuval Mintz * 742fe56b9e6SYuval Mintz * @param concrete_fid 743fe56b9e6SYuval Mintz * 744fe56b9e6SYuval Mintz * @return inline u8 745fe56b9e6SYuval Mintz */ 746fe56b9e6SYuval Mintz static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev, 747fe56b9e6SYuval Mintz u32 concrete_fid) 748fe56b9e6SYuval Mintz { 7494870e704SYuval Mintz u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); 750fe56b9e6SYuval Mintz u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); 7514870e704SYuval Mintz u8 vf_valid = GET_FIELD(concrete_fid, 7524870e704SYuval Mintz PXP_CONCRETE_FID_VFVALID); 7534870e704SYuval Mintz u8 sw_fid; 754fe56b9e6SYuval Mintz 7554870e704SYuval Mintz if (vf_valid) 7564870e704SYuval Mintz sw_fid = vfid + MAX_NUM_PFS; 7574870e704SYuval Mintz else 7584870e704SYuval Mintz sw_fid = pfid; 7594870e704SYuval Mintz 7604870e704SYuval Mintz return sw_fid; 761fe56b9e6SYuval Mintz } 762fe56b9e6SYuval Mintz 763fe56b9e6SYuval Mintz #define PURE_LB_TC 8 764dbb799c3SYuval Mintz #define OOO_LB_TC 9 765fe56b9e6SYuval Mintz 766733def6aSYuval Mintz int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate); 7676f437d43SMintz, Yuval void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, 7686f437d43SMintz, Yuval struct qed_ptt *p_ptt, 7696f437d43SMintz, Yuval u32 min_pf_rate); 770bcd197c8SManish Chopra 771733def6aSYuval Mintz void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 7729c79ddaaSMintz, Yuval int qed_device_num_engines(struct qed_dev *cdev); 773db82f70eSsudarsana.kalluru@cavium.com int qed_device_get_port_id(struct qed_dev *cdev); 774fe56b9e6SYuval Mintz 775b5a9ee7cSAriel Elior #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) 776b5a9ee7cSAriel Elior 777b5a9ee7cSAriel Elior /* Flags for indication of required queues */ 778b5a9ee7cSAriel Elior #define PQ_FLAGS_RLS (BIT(0)) 779b5a9ee7cSAriel Elior #define PQ_FLAGS_MCOS (BIT(1)) 780b5a9ee7cSAriel Elior #define PQ_FLAGS_LB (BIT(2)) 781b5a9ee7cSAriel Elior #define PQ_FLAGS_OOO (BIT(3)) 782b5a9ee7cSAriel Elior #define PQ_FLAGS_ACK (BIT(4)) 783b5a9ee7cSAriel Elior #define PQ_FLAGS_OFLD (BIT(5)) 784b5a9ee7cSAriel Elior #define PQ_FLAGS_VFS (BIT(6)) 785b5a9ee7cSAriel Elior #define PQ_FLAGS_LLT (BIT(7)) 786b5a9ee7cSAriel Elior 787b5a9ee7cSAriel Elior /* physical queue index for cm context intialization */ 788b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags); 789b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc); 790b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf); 791b5a9ee7cSAriel Elior 792b5a9ee7cSAriel Elior #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) 793b5a9ee7cSAriel Elior 794fe56b9e6SYuval Mintz /* Other Linux specific common definitions */ 795fe56b9e6SYuval Mintz #define DP_NAME(cdev) ((cdev)->name) 796fe56b9e6SYuval Mintz 797fe56b9e6SYuval Mintz #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\ 798fe56b9e6SYuval Mintz (cdev->regview) + \ 799fe56b9e6SYuval Mintz (offset)) 800fe56b9e6SYuval Mintz 801fe56b9e6SYuval Mintz #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset)) 802fe56b9e6SYuval Mintz #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset)) 803fe56b9e6SYuval Mintz #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset)) 804fe56b9e6SYuval Mintz 805fe56b9e6SYuval Mintz #define DOORBELL(cdev, db_addr, val) \ 806fe56b9e6SYuval Mintz writel((u32)val, (void __iomem *)((u8 __iomem *)\ 807fe56b9e6SYuval Mintz (cdev->doorbells) + (db_addr))) 808fe56b9e6SYuval Mintz 809fe56b9e6SYuval Mintz /* Prototypes */ 810fe56b9e6SYuval Mintz int qed_fill_dev_info(struct qed_dev *cdev, 811fe56b9e6SYuval Mintz struct qed_dev_info *dev_info); 812cc875c2eSYuval Mintz void qed_link_update(struct qed_hwfn *hwfn); 813fe56b9e6SYuval Mintz u32 qed_unzip_data(struct qed_hwfn *p_hwfn, 814fe56b9e6SYuval Mintz u32 input_len, u8 *input_buf, 815fe56b9e6SYuval Mintz u32 max_size, u8 *unzip_buf); 8166c754246SSudarsana Reddy Kalluru void qed_get_protocol_stats(struct qed_dev *cdev, 8176c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type type, 8186c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats *stats); 8198f16bc97SSudarsana Kalluru int qed_slowpath_irq_req(struct qed_hwfn *hwfn); 8201226337aSTomer Tayar void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn); 8218f16bc97SSudarsana Kalluru 822fe56b9e6SYuval Mintz #endif /* _QED_H */ 823