1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2fe56b9e6SYuval Mintz * Copyright (c) 2015 QLogic Corporation 3fe56b9e6SYuval Mintz * 4fe56b9e6SYuval Mintz * This software is available under the terms of the GNU General Public License 5fe56b9e6SYuval Mintz * (GPL) Version 2, available from the file COPYING in the main directory of 6fe56b9e6SYuval Mintz * this source tree. 7fe56b9e6SYuval Mintz */ 8fe56b9e6SYuval Mintz 9fe56b9e6SYuval Mintz #ifndef _QED_H 10fe56b9e6SYuval Mintz #define _QED_H 11fe56b9e6SYuval Mintz 12fe56b9e6SYuval Mintz #include <linux/types.h> 13fe56b9e6SYuval Mintz #include <linux/io.h> 14fe56b9e6SYuval Mintz #include <linux/delay.h> 15fe56b9e6SYuval Mintz #include <linux/firmware.h> 16fe56b9e6SYuval Mintz #include <linux/interrupt.h> 17fe56b9e6SYuval Mintz #include <linux/list.h> 18fe56b9e6SYuval Mintz #include <linux/mutex.h> 19fe56b9e6SYuval Mintz #include <linux/pci.h> 20fe56b9e6SYuval Mintz #include <linux/slab.h> 21fe56b9e6SYuval Mintz #include <linux/string.h> 22fe56b9e6SYuval Mintz #include <linux/workqueue.h> 23fe56b9e6SYuval Mintz #include <linux/zlib.h> 24fe56b9e6SYuval Mintz #include <linux/hashtable.h> 25fe56b9e6SYuval Mintz #include <linux/qed/qed_if.h> 26fe56b9e6SYuval Mintz #include "qed_hsi.h" 27fe56b9e6SYuval Mintz 2825c089d7SYuval Mintz extern const struct qed_common_ops qed_common_ops_pass; 29fe56b9e6SYuval Mintz #define DRV_MODULE_VERSION "8.4.0.0" 30fe56b9e6SYuval Mintz 31fe56b9e6SYuval Mintz #define MAX_HWFNS_PER_DEVICE (4) 32fe56b9e6SYuval Mintz #define NAME_SIZE 16 33fe56b9e6SYuval Mintz #define VER_SIZE 16 34fe56b9e6SYuval Mintz 35fe56b9e6SYuval Mintz /* cau states */ 36fe56b9e6SYuval Mintz enum qed_coalescing_mode { 37fe56b9e6SYuval Mintz QED_COAL_MODE_DISABLE, 38fe56b9e6SYuval Mintz QED_COAL_MODE_ENABLE 39fe56b9e6SYuval Mintz }; 40fe56b9e6SYuval Mintz 41fe56b9e6SYuval Mintz struct qed_eth_cb_ops; 42fe56b9e6SYuval Mintz struct qed_dev_info; 43fe56b9e6SYuval Mintz 44fe56b9e6SYuval Mintz /* helpers */ 45fe56b9e6SYuval Mintz static inline u32 qed_db_addr(u32 cid, u32 DEMS) 46fe56b9e6SYuval Mintz { 47fe56b9e6SYuval Mintz u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 48fe56b9e6SYuval Mintz FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); 49fe56b9e6SYuval Mintz 50fe56b9e6SYuval Mintz return db_addr; 51fe56b9e6SYuval Mintz } 52fe56b9e6SYuval Mintz 53fe56b9e6SYuval Mintz #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ 54fe56b9e6SYuval Mintz ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \ 55fe56b9e6SYuval Mintz ~((1 << (p_hwfn->cdev->cache_shift)) - 1)) 56fe56b9e6SYuval Mintz 57fe56b9e6SYuval Mintz #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++) 58fe56b9e6SYuval Mintz 59fe56b9e6SYuval Mintz #define D_TRINE(val, cond1, cond2, true1, true2, def) \ 60fe56b9e6SYuval Mintz (val == (cond1) ? true1 : \ 61fe56b9e6SYuval Mintz (val == (cond2) ? true2 : def)) 62fe56b9e6SYuval Mintz 63fe56b9e6SYuval Mintz /* forward */ 64fe56b9e6SYuval Mintz struct qed_ptt_pool; 65fe56b9e6SYuval Mintz struct qed_spq; 66fe56b9e6SYuval Mintz struct qed_sb_info; 67fe56b9e6SYuval Mintz struct qed_sb_attn_info; 68fe56b9e6SYuval Mintz struct qed_cxt_mngr; 69fe56b9e6SYuval Mintz struct qed_sb_sp_info; 70fe56b9e6SYuval Mintz struct qed_mcp_info; 71fe56b9e6SYuval Mintz 72fe56b9e6SYuval Mintz struct qed_rt_data { 73fe56b9e6SYuval Mintz u32 init_val; 74fe56b9e6SYuval Mintz bool b_valid; 75fe56b9e6SYuval Mintz }; 76fe56b9e6SYuval Mintz 77fe56b9e6SYuval Mintz /* The PCI personality is not quite synonymous to protocol ID: 78fe56b9e6SYuval Mintz * 1. All personalities need CORE connections 79fe56b9e6SYuval Mintz * 2. The Ethernet personality may support also the RoCE protocol 80fe56b9e6SYuval Mintz */ 81fe56b9e6SYuval Mintz enum qed_pci_personality { 82fe56b9e6SYuval Mintz QED_PCI_ETH, 83fe56b9e6SYuval Mintz QED_PCI_DEFAULT /* default in shmem */ 84fe56b9e6SYuval Mintz }; 85fe56b9e6SYuval Mintz 86fe56b9e6SYuval Mintz /* All VFs are symmetric, all counters are PF + all VFs */ 87fe56b9e6SYuval Mintz struct qed_qm_iids { 88fe56b9e6SYuval Mintz u32 cids; 89fe56b9e6SYuval Mintz u32 vf_cids; 90fe56b9e6SYuval Mintz u32 tids; 91fe56b9e6SYuval Mintz }; 92fe56b9e6SYuval Mintz 93fe56b9e6SYuval Mintz enum QED_RESOURCES { 94fe56b9e6SYuval Mintz QED_SB, 9525c089d7SYuval Mintz QED_L2_QUEUE, 96fe56b9e6SYuval Mintz QED_VPORT, 9725c089d7SYuval Mintz QED_RSS_ENG, 98fe56b9e6SYuval Mintz QED_PQ, 99fe56b9e6SYuval Mintz QED_RL, 10025c089d7SYuval Mintz QED_MAC, 10125c089d7SYuval Mintz QED_VLAN, 102fe56b9e6SYuval Mintz QED_ILT, 103fe56b9e6SYuval Mintz QED_MAX_RESC, 104fe56b9e6SYuval Mintz }; 105fe56b9e6SYuval Mintz 10625c089d7SYuval Mintz enum QED_FEATURE { 10725c089d7SYuval Mintz QED_PF_L2_QUE, 10825c089d7SYuval Mintz QED_MAX_FEATURES, 10925c089d7SYuval Mintz }; 11025c089d7SYuval Mintz 111cc875c2eSYuval Mintz enum QED_PORT_MODE { 112cc875c2eSYuval Mintz QED_PORT_MODE_DE_2X40G, 113cc875c2eSYuval Mintz QED_PORT_MODE_DE_2X50G, 114cc875c2eSYuval Mintz QED_PORT_MODE_DE_1X100G, 115cc875c2eSYuval Mintz QED_PORT_MODE_DE_4X10G_F, 116cc875c2eSYuval Mintz QED_PORT_MODE_DE_4X10G_E, 117cc875c2eSYuval Mintz QED_PORT_MODE_DE_4X20G, 118cc875c2eSYuval Mintz QED_PORT_MODE_DE_1X40G, 119cc875c2eSYuval Mintz QED_PORT_MODE_DE_2X25G, 120cc875c2eSYuval Mintz QED_PORT_MODE_DE_1X25G 121cc875c2eSYuval Mintz }; 122cc875c2eSYuval Mintz 123fe56b9e6SYuval Mintz struct qed_hw_info { 124fe56b9e6SYuval Mintz /* PCI personality */ 125fe56b9e6SYuval Mintz enum qed_pci_personality personality; 126fe56b9e6SYuval Mintz 127fe56b9e6SYuval Mintz /* Resource Allocation scheme results */ 128fe56b9e6SYuval Mintz u32 resc_start[QED_MAX_RESC]; 129fe56b9e6SYuval Mintz u32 resc_num[QED_MAX_RESC]; 13025c089d7SYuval Mintz u32 feat_num[QED_MAX_FEATURES]; 131fe56b9e6SYuval Mintz 132fe56b9e6SYuval Mintz #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) 133fe56b9e6SYuval Mintz #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) 134fe56b9e6SYuval Mintz #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) 135fe56b9e6SYuval Mintz 136fe56b9e6SYuval Mintz u8 num_tc; 137fe56b9e6SYuval Mintz u8 offload_tc; 138fe56b9e6SYuval Mintz u8 non_offload_tc; 139fe56b9e6SYuval Mintz 140fe56b9e6SYuval Mintz u32 concrete_fid; 141fe56b9e6SYuval Mintz u16 opaque_fid; 142fe56b9e6SYuval Mintz u16 ovlan; 143fe56b9e6SYuval Mintz u32 part_num[4]; 144fe56b9e6SYuval Mintz 145fe56b9e6SYuval Mintz u32 vendor_id; 146fe56b9e6SYuval Mintz u32 device_id; 147fe56b9e6SYuval Mintz 148fe56b9e6SYuval Mintz unsigned char hw_mac_addr[ETH_ALEN]; 149fe56b9e6SYuval Mintz 150fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 151fe56b9e6SYuval Mintz 152fe56b9e6SYuval Mintz u32 port_mode; 153fe56b9e6SYuval Mintz u32 hw_mode; 154fe56b9e6SYuval Mintz }; 155fe56b9e6SYuval Mintz 156fe56b9e6SYuval Mintz struct qed_hw_cid_data { 157fe56b9e6SYuval Mintz u32 cid; 158fe56b9e6SYuval Mintz bool b_cid_allocated; 159fe56b9e6SYuval Mintz 160fe56b9e6SYuval Mintz /* Additional identifiers */ 161fe56b9e6SYuval Mintz u16 opaque_fid; 162fe56b9e6SYuval Mintz u8 vport_id; 163fe56b9e6SYuval Mintz }; 164fe56b9e6SYuval Mintz 165fe56b9e6SYuval Mintz /* maximun size of read/write commands (HW limit) */ 166fe56b9e6SYuval Mintz #define DMAE_MAX_RW_SIZE 0x2000 167fe56b9e6SYuval Mintz 168fe56b9e6SYuval Mintz struct qed_dmae_info { 169fe56b9e6SYuval Mintz /* Mutex for synchronizing access to functions */ 170fe56b9e6SYuval Mintz struct mutex mutex; 171fe56b9e6SYuval Mintz 172fe56b9e6SYuval Mintz u8 channel; 173fe56b9e6SYuval Mintz 174fe56b9e6SYuval Mintz dma_addr_t completion_word_phys_addr; 175fe56b9e6SYuval Mintz 176fe56b9e6SYuval Mintz /* The memory location where the DMAE writes the completion 177fe56b9e6SYuval Mintz * value when an operation is finished on this context. 178fe56b9e6SYuval Mintz */ 179fe56b9e6SYuval Mintz u32 *p_completion_word; 180fe56b9e6SYuval Mintz 181fe56b9e6SYuval Mintz dma_addr_t intermediate_buffer_phys_addr; 182fe56b9e6SYuval Mintz 183fe56b9e6SYuval Mintz /* An intermediate buffer for DMAE operations that use virtual 184fe56b9e6SYuval Mintz * addresses - data is DMA'd to/from this buffer and then 185fe56b9e6SYuval Mintz * memcpy'd to/from the virtual address 186fe56b9e6SYuval Mintz */ 187fe56b9e6SYuval Mintz u32 *p_intermediate_buffer; 188fe56b9e6SYuval Mintz 189fe56b9e6SYuval Mintz dma_addr_t dmae_cmd_phys_addr; 190fe56b9e6SYuval Mintz struct dmae_cmd *p_dmae_cmd; 191fe56b9e6SYuval Mintz }; 192fe56b9e6SYuval Mintz 193fe56b9e6SYuval Mintz struct qed_qm_info { 194fe56b9e6SYuval Mintz struct init_qm_pq_params *qm_pq_params; 195fe56b9e6SYuval Mintz struct init_qm_vport_params *qm_vport_params; 196fe56b9e6SYuval Mintz struct init_qm_port_params *qm_port_params; 197fe56b9e6SYuval Mintz u16 start_pq; 198fe56b9e6SYuval Mintz u8 start_vport; 199fe56b9e6SYuval Mintz u8 pure_lb_pq; 200fe56b9e6SYuval Mintz u8 offload_pq; 201fe56b9e6SYuval Mintz u8 pure_ack_pq; 202fe56b9e6SYuval Mintz u8 vf_queues_offset; 203fe56b9e6SYuval Mintz u16 num_pqs; 204fe56b9e6SYuval Mintz u16 num_vf_pqs; 205fe56b9e6SYuval Mintz u8 num_vports; 206fe56b9e6SYuval Mintz u8 max_phys_tcs_per_port; 207fe56b9e6SYuval Mintz bool pf_rl_en; 208fe56b9e6SYuval Mintz bool pf_wfq_en; 209fe56b9e6SYuval Mintz bool vport_rl_en; 210fe56b9e6SYuval Mintz bool vport_wfq_en; 211fe56b9e6SYuval Mintz u8 pf_wfq; 212fe56b9e6SYuval Mintz u32 pf_rl; 213fe56b9e6SYuval Mintz }; 214fe56b9e6SYuval Mintz 215fe56b9e6SYuval Mintz struct qed_fw_data { 216fe56b9e6SYuval Mintz const u8 *modes_tree_buf; 217fe56b9e6SYuval Mintz union init_op *init_ops; 218fe56b9e6SYuval Mintz const u32 *arr_data; 219fe56b9e6SYuval Mintz u32 init_ops_size; 220fe56b9e6SYuval Mintz }; 221fe56b9e6SYuval Mintz 222fe56b9e6SYuval Mintz struct qed_simd_fp_handler { 223fe56b9e6SYuval Mintz void *token; 224fe56b9e6SYuval Mintz void (*func)(void *); 225fe56b9e6SYuval Mintz }; 226fe56b9e6SYuval Mintz 227fe56b9e6SYuval Mintz struct qed_hwfn { 228fe56b9e6SYuval Mintz struct qed_dev *cdev; 229fe56b9e6SYuval Mintz u8 my_id; /* ID inside the PF */ 230fe56b9e6SYuval Mintz #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) 231fe56b9e6SYuval Mintz u8 rel_pf_id; /* Relative to engine*/ 232fe56b9e6SYuval Mintz u8 abs_pf_id; 233fe56b9e6SYuval Mintz #define QED_PATH_ID(_p_hwfn) ((_p_hwfn)->abs_pf_id & 1) 234fe56b9e6SYuval Mintz u8 port_id; 235fe56b9e6SYuval Mintz bool b_active; 236fe56b9e6SYuval Mintz 237fe56b9e6SYuval Mintz u32 dp_module; 238fe56b9e6SYuval Mintz u8 dp_level; 239fe56b9e6SYuval Mintz char name[NAME_SIZE]; 240fe56b9e6SYuval Mintz 241fe56b9e6SYuval Mintz bool first_on_engine; 242fe56b9e6SYuval Mintz bool hw_init_done; 243fe56b9e6SYuval Mintz 244fe56b9e6SYuval Mintz /* BAR access */ 245fe56b9e6SYuval Mintz void __iomem *regview; 246fe56b9e6SYuval Mintz void __iomem *doorbells; 247fe56b9e6SYuval Mintz u64 db_phys_addr; 248fe56b9e6SYuval Mintz unsigned long db_size; 249fe56b9e6SYuval Mintz 250fe56b9e6SYuval Mintz /* PTT pool */ 251fe56b9e6SYuval Mintz struct qed_ptt_pool *p_ptt_pool; 252fe56b9e6SYuval Mintz 253fe56b9e6SYuval Mintz /* HW info */ 254fe56b9e6SYuval Mintz struct qed_hw_info hw_info; 255fe56b9e6SYuval Mintz 256fe56b9e6SYuval Mintz /* rt_array (for init-tool) */ 257fe56b9e6SYuval Mintz struct qed_rt_data *rt_data; 258fe56b9e6SYuval Mintz 259fe56b9e6SYuval Mintz /* SPQ */ 260fe56b9e6SYuval Mintz struct qed_spq *p_spq; 261fe56b9e6SYuval Mintz 262fe56b9e6SYuval Mintz /* EQ */ 263fe56b9e6SYuval Mintz struct qed_eq *p_eq; 264fe56b9e6SYuval Mintz 265fe56b9e6SYuval Mintz /* Consolidate Q*/ 266fe56b9e6SYuval Mintz struct qed_consq *p_consq; 267fe56b9e6SYuval Mintz 268fe56b9e6SYuval Mintz /* Slow-Path definitions */ 269fe56b9e6SYuval Mintz struct tasklet_struct *sp_dpc; 270fe56b9e6SYuval Mintz bool b_sp_dpc_enabled; 271fe56b9e6SYuval Mintz 272fe56b9e6SYuval Mintz struct qed_ptt *p_main_ptt; 273fe56b9e6SYuval Mintz struct qed_ptt *p_dpc_ptt; 274fe56b9e6SYuval Mintz 275fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb; 276fe56b9e6SYuval Mintz struct qed_sb_attn_info *p_sb_attn; 277fe56b9e6SYuval Mintz 278fe56b9e6SYuval Mintz /* Protocol related */ 279fe56b9e6SYuval Mintz struct qed_pf_params pf_params; 280fe56b9e6SYuval Mintz 281fe56b9e6SYuval Mintz /* Array of sb_info of all status blocks */ 282fe56b9e6SYuval Mintz struct qed_sb_info *sbs_info[MAX_SB_PER_PF_MIMD]; 283fe56b9e6SYuval Mintz u16 num_sbs; 284fe56b9e6SYuval Mintz 285fe56b9e6SYuval Mintz struct qed_cxt_mngr *p_cxt_mngr; 286fe56b9e6SYuval Mintz 287fe56b9e6SYuval Mintz /* Flag indicating whether interrupts are enabled or not*/ 288fe56b9e6SYuval Mintz bool b_int_enabled; 289fe56b9e6SYuval Mintz 290fe56b9e6SYuval Mintz struct qed_mcp_info *mcp_info; 291fe56b9e6SYuval Mintz 29225c089d7SYuval Mintz struct qed_hw_cid_data *p_tx_cids; 29325c089d7SYuval Mintz struct qed_hw_cid_data *p_rx_cids; 29425c089d7SYuval Mintz 295fe56b9e6SYuval Mintz struct qed_dmae_info dmae_info; 296fe56b9e6SYuval Mintz 297fe56b9e6SYuval Mintz /* QM init */ 298fe56b9e6SYuval Mintz struct qed_qm_info qm_info; 299fe56b9e6SYuval Mintz 300fe56b9e6SYuval Mintz /* Buffer for unzipping firmware data */ 301fe56b9e6SYuval Mintz void *unzip_buf; 302fe56b9e6SYuval Mintz 303fe56b9e6SYuval Mintz struct qed_simd_fp_handler simd_proto_handler[64]; 304fe56b9e6SYuval Mintz 305fe56b9e6SYuval Mintz struct z_stream_s *stream; 306fe56b9e6SYuval Mintz }; 307fe56b9e6SYuval Mintz 308fe56b9e6SYuval Mintz struct pci_params { 309fe56b9e6SYuval Mintz int pm_cap; 310fe56b9e6SYuval Mintz 311fe56b9e6SYuval Mintz unsigned long mem_start; 312fe56b9e6SYuval Mintz unsigned long mem_end; 313fe56b9e6SYuval Mintz unsigned int irq; 314fe56b9e6SYuval Mintz u8 pf_num; 315fe56b9e6SYuval Mintz }; 316fe56b9e6SYuval Mintz 317fe56b9e6SYuval Mintz struct qed_int_param { 318fe56b9e6SYuval Mintz u32 int_mode; 319fe56b9e6SYuval Mintz u8 num_vectors; 320fe56b9e6SYuval Mintz u8 min_msix_cnt; /* for minimal functionality */ 321fe56b9e6SYuval Mintz }; 322fe56b9e6SYuval Mintz 323fe56b9e6SYuval Mintz struct qed_int_params { 324fe56b9e6SYuval Mintz struct qed_int_param in; 325fe56b9e6SYuval Mintz struct qed_int_param out; 326fe56b9e6SYuval Mintz struct msix_entry *msix_table; 327fe56b9e6SYuval Mintz bool fp_initialized; 328fe56b9e6SYuval Mintz u8 fp_msix_base; 329fe56b9e6SYuval Mintz u8 fp_msix_cnt; 330fe56b9e6SYuval Mintz }; 331fe56b9e6SYuval Mintz 332fe56b9e6SYuval Mintz struct qed_dev { 333fe56b9e6SYuval Mintz u32 dp_module; 334fe56b9e6SYuval Mintz u8 dp_level; 335fe56b9e6SYuval Mintz char name[NAME_SIZE]; 336fe56b9e6SYuval Mintz 337fe56b9e6SYuval Mintz u8 type; 338fe56b9e6SYuval Mintz #define QED_DEV_TYPE_BB_A0 (0 << 0) 339fe56b9e6SYuval Mintz #define QED_DEV_TYPE_MASK (0x3) 340fe56b9e6SYuval Mintz #define QED_DEV_TYPE_SHIFT (0) 341fe56b9e6SYuval Mintz 342fe56b9e6SYuval Mintz u16 chip_num; 343fe56b9e6SYuval Mintz #define CHIP_NUM_MASK 0xffff 344fe56b9e6SYuval Mintz #define CHIP_NUM_SHIFT 16 345fe56b9e6SYuval Mintz 346fe56b9e6SYuval Mintz u16 chip_rev; 347fe56b9e6SYuval Mintz #define CHIP_REV_MASK 0xf 348fe56b9e6SYuval Mintz #define CHIP_REV_SHIFT 12 349fe56b9e6SYuval Mintz 350fe56b9e6SYuval Mintz u16 chip_metal; 351fe56b9e6SYuval Mintz #define CHIP_METAL_MASK 0xff 352fe56b9e6SYuval Mintz #define CHIP_METAL_SHIFT 4 353fe56b9e6SYuval Mintz 354fe56b9e6SYuval Mintz u16 chip_bond_id; 355fe56b9e6SYuval Mintz #define CHIP_BOND_ID_MASK 0xf 356fe56b9e6SYuval Mintz #define CHIP_BOND_ID_SHIFT 0 357fe56b9e6SYuval Mintz 358fe56b9e6SYuval Mintz u8 num_engines; 359fe56b9e6SYuval Mintz u8 num_ports_in_engines; 360fe56b9e6SYuval Mintz u8 num_funcs_in_port; 361fe56b9e6SYuval Mintz 362fe56b9e6SYuval Mintz u8 path_id; 363fe56b9e6SYuval Mintz enum mf_mode mf_mode; 364fe56b9e6SYuval Mintz #define IS_MF(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode != SF) 365fe56b9e6SYuval Mintz #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == MF_NPAR) 366fe56b9e6SYuval Mintz #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == MF_OVLAN) 367fe56b9e6SYuval Mintz 368fe56b9e6SYuval Mintz int pcie_width; 369fe56b9e6SYuval Mintz int pcie_speed; 370fe56b9e6SYuval Mintz u8 ver_str[VER_SIZE]; 371fe56b9e6SYuval Mintz 372fe56b9e6SYuval Mintz /* Add MF related configuration */ 373fe56b9e6SYuval Mintz u8 mcp_rev; 374fe56b9e6SYuval Mintz u8 boot_mode; 375fe56b9e6SYuval Mintz 376fe56b9e6SYuval Mintz u8 wol; 377fe56b9e6SYuval Mintz 378fe56b9e6SYuval Mintz u32 int_mode; 379fe56b9e6SYuval Mintz enum qed_coalescing_mode int_coalescing_mode; 380fe56b9e6SYuval Mintz u8 rx_coalesce_usecs; 381fe56b9e6SYuval Mintz u8 tx_coalesce_usecs; 382fe56b9e6SYuval Mintz 383fe56b9e6SYuval Mintz /* Start Bar offset of first hwfn */ 384fe56b9e6SYuval Mintz void __iomem *regview; 385fe56b9e6SYuval Mintz void __iomem *doorbells; 386fe56b9e6SYuval Mintz u64 db_phys_addr; 387fe56b9e6SYuval Mintz unsigned long db_size; 388fe56b9e6SYuval Mintz 389fe56b9e6SYuval Mintz /* PCI */ 390fe56b9e6SYuval Mintz u8 cache_shift; 391fe56b9e6SYuval Mintz 392fe56b9e6SYuval Mintz /* Init */ 393fe56b9e6SYuval Mintz const struct iro *iro_arr; 394fe56b9e6SYuval Mintz #define IRO (p_hwfn->cdev->iro_arr) 395fe56b9e6SYuval Mintz 396fe56b9e6SYuval Mintz /* HW functions */ 397fe56b9e6SYuval Mintz u8 num_hwfns; 398fe56b9e6SYuval Mintz struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; 399fe56b9e6SYuval Mintz 400fe56b9e6SYuval Mintz u32 drv_type; 401fe56b9e6SYuval Mintz 402fe56b9e6SYuval Mintz struct qed_eth_stats *reset_stats; 403fe56b9e6SYuval Mintz struct qed_fw_data *fw_data; 404fe56b9e6SYuval Mintz 405fe56b9e6SYuval Mintz u32 mcp_nvm_resp; 406fe56b9e6SYuval Mintz 407fe56b9e6SYuval Mintz /* Linux specific here */ 408fe56b9e6SYuval Mintz struct qede_dev *edev; 409fe56b9e6SYuval Mintz struct pci_dev *pdev; 410fe56b9e6SYuval Mintz int msg_enable; 411fe56b9e6SYuval Mintz 412fe56b9e6SYuval Mintz struct pci_params pci_params; 413fe56b9e6SYuval Mintz 414fe56b9e6SYuval Mintz struct qed_int_params int_params; 415fe56b9e6SYuval Mintz 416fe56b9e6SYuval Mintz u8 protocol; 417fe56b9e6SYuval Mintz #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH) 418fe56b9e6SYuval Mintz 419cc875c2eSYuval Mintz /* Callbacks to protocol driver */ 420cc875c2eSYuval Mintz union { 421cc875c2eSYuval Mintz struct qed_common_cb_ops *common; 422cc875c2eSYuval Mintz struct qed_eth_cb_ops *eth; 423cc875c2eSYuval Mintz } protocol_ops; 424cc875c2eSYuval Mintz void *ops_cookie; 425cc875c2eSYuval Mintz 426fe56b9e6SYuval Mintz const struct firmware *firmware; 427fe56b9e6SYuval Mintz }; 428fe56b9e6SYuval Mintz 429fe56b9e6SYuval Mintz #define QED_GET_TYPE(dev) (((dev)->type & QED_DEV_TYPE_MASK) >> \ 430fe56b9e6SYuval Mintz QED_DEV_TYPE_SHIFT) 431fe56b9e6SYuval Mintz #define QED_IS_BB_A0(dev) (QED_GET_TYPE(dev) == QED_DEV_TYPE_BB_A0) 432fe56b9e6SYuval Mintz #define QED_IS_BB(dev) (QED_IS_BB_A0(dev)) 433fe56b9e6SYuval Mintz 434fe56b9e6SYuval Mintz #define NUM_OF_SBS(dev) MAX_SB_PER_PATH_BB 435fe56b9e6SYuval Mintz #define NUM_OF_ENG_PFS(dev) MAX_NUM_PFS_BB 436fe56b9e6SYuval Mintz 437fe56b9e6SYuval Mintz /** 438fe56b9e6SYuval Mintz * @brief qed_concrete_to_sw_fid - get the sw function id from 439fe56b9e6SYuval Mintz * the concrete value. 440fe56b9e6SYuval Mintz * 441fe56b9e6SYuval Mintz * @param concrete_fid 442fe56b9e6SYuval Mintz * 443fe56b9e6SYuval Mintz * @return inline u8 444fe56b9e6SYuval Mintz */ 445fe56b9e6SYuval Mintz static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev, 446fe56b9e6SYuval Mintz u32 concrete_fid) 447fe56b9e6SYuval Mintz { 448fe56b9e6SYuval Mintz u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); 449fe56b9e6SYuval Mintz 450fe56b9e6SYuval Mintz return pfid; 451fe56b9e6SYuval Mintz } 452fe56b9e6SYuval Mintz 453fe56b9e6SYuval Mintz #define PURE_LB_TC 8 454fe56b9e6SYuval Mintz 455fe56b9e6SYuval Mintz #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) 456fe56b9e6SYuval Mintz 457fe56b9e6SYuval Mintz /* Other Linux specific common definitions */ 458fe56b9e6SYuval Mintz #define DP_NAME(cdev) ((cdev)->name) 459fe56b9e6SYuval Mintz 460fe56b9e6SYuval Mintz #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\ 461fe56b9e6SYuval Mintz (cdev->regview) + \ 462fe56b9e6SYuval Mintz (offset)) 463fe56b9e6SYuval Mintz 464fe56b9e6SYuval Mintz #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset)) 465fe56b9e6SYuval Mintz #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset)) 466fe56b9e6SYuval Mintz #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset)) 467fe56b9e6SYuval Mintz 468fe56b9e6SYuval Mintz #define DOORBELL(cdev, db_addr, val) \ 469fe56b9e6SYuval Mintz writel((u32)val, (void __iomem *)((u8 __iomem *)\ 470fe56b9e6SYuval Mintz (cdev->doorbells) + (db_addr))) 471fe56b9e6SYuval Mintz 472fe56b9e6SYuval Mintz /* Prototypes */ 473fe56b9e6SYuval Mintz int qed_fill_dev_info(struct qed_dev *cdev, 474fe56b9e6SYuval Mintz struct qed_dev_info *dev_info); 475cc875c2eSYuval Mintz void qed_link_update(struct qed_hwfn *hwfn); 476fe56b9e6SYuval Mintz u32 qed_unzip_data(struct qed_hwfn *p_hwfn, 477fe56b9e6SYuval Mintz u32 input_len, u8 *input_buf, 478fe56b9e6SYuval Mintz u32 max_size, u8 *unzip_buf); 479fe56b9e6SYuval Mintz 480fe56b9e6SYuval Mintz #define QED_ETH_INTERFACE_VERSION 300 481fe56b9e6SYuval Mintz 482fe56b9e6SYuval Mintz #endif /* _QED_H */ 483