1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #ifndef _QED_H 34fe56b9e6SYuval Mintz #define _QED_H 35fe56b9e6SYuval Mintz 36fe56b9e6SYuval Mintz #include <linux/types.h> 37fe56b9e6SYuval Mintz #include <linux/io.h> 38fe56b9e6SYuval Mintz #include <linux/delay.h> 39fe56b9e6SYuval Mintz #include <linux/firmware.h> 40fe56b9e6SYuval Mintz #include <linux/interrupt.h> 41fe56b9e6SYuval Mintz #include <linux/list.h> 42fe56b9e6SYuval Mintz #include <linux/mutex.h> 43fe56b9e6SYuval Mintz #include <linux/pci.h> 44fe56b9e6SYuval Mintz #include <linux/slab.h> 45fe56b9e6SYuval Mintz #include <linux/string.h> 46fe56b9e6SYuval Mintz #include <linux/workqueue.h> 47fe56b9e6SYuval Mintz #include <linux/zlib.h> 48fe56b9e6SYuval Mintz #include <linux/hashtable.h> 49fe56b9e6SYuval Mintz #include <linux/qed/qed_if.h> 50c965db44STomer Tayar #include "qed_debug.h" 51fe56b9e6SYuval Mintz #include "qed_hsi.h" 52fe56b9e6SYuval Mintz 5325c089d7SYuval Mintz extern const struct qed_common_ops qed_common_ops_pass; 545d24bcf1STomer Tayar 555d24bcf1STomer Tayar #define QED_MAJOR_VERSION 8 565d24bcf1STomer Tayar #define QED_MINOR_VERSION 10 577b6859fbSMintz, Yuval #define QED_REVISION_VERSION 11 585d24bcf1STomer Tayar #define QED_ENGINEERING_VERSION 21 595d24bcf1STomer Tayar 605d24bcf1STomer Tayar #define QED_VERSION \ 615d24bcf1STomer Tayar ((QED_MAJOR_VERSION << 24) | (QED_MINOR_VERSION << 16) | \ 625d24bcf1STomer Tayar (QED_REVISION_VERSION << 8) | QED_ENGINEERING_VERSION) 635d24bcf1STomer Tayar 645d24bcf1STomer Tayar #define STORM_FW_VERSION \ 655d24bcf1STomer Tayar ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \ 665d24bcf1STomer Tayar (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION) 67fe56b9e6SYuval Mintz 68fe56b9e6SYuval Mintz #define MAX_HWFNS_PER_DEVICE (4) 69fe56b9e6SYuval Mintz #define NAME_SIZE 16 70fe56b9e6SYuval Mintz #define VER_SIZE 16 71fe56b9e6SYuval Mintz 72bcd197c8SManish Chopra #define QED_WFQ_UNIT 100 73bcd197c8SManish Chopra 7451ff1725SRam Amrani #define QED_WID_SIZE (1024) 75107392b7SRam Amrani #define QED_MIN_WIDS (4) 7651ff1725SRam Amrani #define QED_PF_DEMS_SIZE (4) 7751ff1725SRam Amrani 78fe56b9e6SYuval Mintz /* cau states */ 79fe56b9e6SYuval Mintz enum qed_coalescing_mode { 80fe56b9e6SYuval Mintz QED_COAL_MODE_DISABLE, 81fe56b9e6SYuval Mintz QED_COAL_MODE_ENABLE 82fe56b9e6SYuval Mintz }; 83fe56b9e6SYuval Mintz 84fe56b9e6SYuval Mintz struct qed_eth_cb_ops; 85fe56b9e6SYuval Mintz struct qed_dev_info; 866c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats; 876c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type; 88fe56b9e6SYuval Mintz 89fe56b9e6SYuval Mintz /* helpers */ 905d24bcf1STomer Tayar #define QED_MFW_GET_FIELD(name, field) \ 915d24bcf1STomer Tayar (((name) & (field ## _MASK)) >> (field ## _SHIFT)) 925d24bcf1STomer Tayar 935d24bcf1STomer Tayar #define QED_MFW_SET_FIELD(name, field, value) \ 945d24bcf1STomer Tayar do { \ 95b19601bbSTomer Tayar (name) &= ~(field ## _MASK); \ 965d24bcf1STomer Tayar (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\ 975d24bcf1STomer Tayar } while (0) 985d24bcf1STomer Tayar 99fe56b9e6SYuval Mintz static inline u32 qed_db_addr(u32 cid, u32 DEMS) 100fe56b9e6SYuval Mintz { 101fe56b9e6SYuval Mintz u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 10251ff1725SRam Amrani (cid * QED_PF_DEMS_SIZE); 10351ff1725SRam Amrani 10451ff1725SRam Amrani return db_addr; 10551ff1725SRam Amrani } 10651ff1725SRam Amrani 10751ff1725SRam Amrani static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS) 10851ff1725SRam Amrani { 10951ff1725SRam Amrani u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 110fe56b9e6SYuval Mintz FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); 111fe56b9e6SYuval Mintz 112fe56b9e6SYuval Mintz return db_addr; 113fe56b9e6SYuval Mintz } 114fe56b9e6SYuval Mintz 115fe56b9e6SYuval Mintz #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ 116fe56b9e6SYuval Mintz ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \ 117fe56b9e6SYuval Mintz ~((1 << (p_hwfn->cdev->cache_shift)) - 1)) 118fe56b9e6SYuval Mintz 119fe56b9e6SYuval Mintz #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++) 120fe56b9e6SYuval Mintz 121fe56b9e6SYuval Mintz #define D_TRINE(val, cond1, cond2, true1, true2, def) \ 122fe56b9e6SYuval Mintz (val == (cond1) ? true1 : \ 123fe56b9e6SYuval Mintz (val == (cond2) ? true2 : def)) 124fe56b9e6SYuval Mintz 125fe56b9e6SYuval Mintz /* forward */ 126fe56b9e6SYuval Mintz struct qed_ptt_pool; 127fe56b9e6SYuval Mintz struct qed_spq; 128fe56b9e6SYuval Mintz struct qed_sb_info; 129fe56b9e6SYuval Mintz struct qed_sb_attn_info; 130fe56b9e6SYuval Mintz struct qed_cxt_mngr; 131fe56b9e6SYuval Mintz struct qed_sb_sp_info; 1320a7fb11cSYuval Mintz struct qed_ll2_info; 133fe56b9e6SYuval Mintz struct qed_mcp_info; 134fe56b9e6SYuval Mintz 135fe56b9e6SYuval Mintz struct qed_rt_data { 136fc48b7a6SYuval Mintz u32 *init_val; 137fc48b7a6SYuval Mintz bool *b_valid; 138fe56b9e6SYuval Mintz }; 139fe56b9e6SYuval Mintz 140464f6645SManish Chopra enum qed_tunn_mode { 141464f6645SManish Chopra QED_MODE_L2GENEVE_TUNN, 142464f6645SManish Chopra QED_MODE_IPGENEVE_TUNN, 143464f6645SManish Chopra QED_MODE_L2GRE_TUNN, 144464f6645SManish Chopra QED_MODE_IPGRE_TUNN, 145464f6645SManish Chopra QED_MODE_VXLAN_TUNN, 146464f6645SManish Chopra }; 147464f6645SManish Chopra 148464f6645SManish Chopra enum qed_tunn_clss { 149464f6645SManish Chopra QED_TUNN_CLSS_MAC_VLAN, 150464f6645SManish Chopra QED_TUNN_CLSS_MAC_VNI, 151464f6645SManish Chopra QED_TUNN_CLSS_INNER_MAC_VLAN, 152464f6645SManish Chopra QED_TUNN_CLSS_INNER_MAC_VNI, 15319968430SChopra, Manish QED_TUNN_CLSS_MAC_VLAN_DUAL_STAGE, 154464f6645SManish Chopra MAX_QED_TUNN_CLSS, 155464f6645SManish Chopra }; 156464f6645SManish Chopra 15719968430SChopra, Manish struct qed_tunn_update_type { 15819968430SChopra, Manish bool b_update_mode; 15919968430SChopra, Manish bool b_mode_enabled; 16019968430SChopra, Manish enum qed_tunn_clss tun_cls; 16119968430SChopra, Manish }; 16219968430SChopra, Manish 16319968430SChopra, Manish struct qed_tunn_update_udp_port { 16419968430SChopra, Manish bool b_update_port; 16519968430SChopra, Manish u16 port; 16619968430SChopra, Manish }; 16719968430SChopra, Manish 16819968430SChopra, Manish struct qed_tunnel_info { 16919968430SChopra, Manish struct qed_tunn_update_type vxlan; 17019968430SChopra, Manish struct qed_tunn_update_type l2_geneve; 17119968430SChopra, Manish struct qed_tunn_update_type ip_geneve; 17219968430SChopra, Manish struct qed_tunn_update_type l2_gre; 17319968430SChopra, Manish struct qed_tunn_update_type ip_gre; 17419968430SChopra, Manish 17519968430SChopra, Manish struct qed_tunn_update_udp_port vxlan_port; 17619968430SChopra, Manish struct qed_tunn_update_udp_port geneve_port; 17719968430SChopra, Manish 17819968430SChopra, Manish bool b_update_rx_cls; 17919968430SChopra, Manish bool b_update_tx_cls; 18019968430SChopra, Manish }; 18119968430SChopra, Manish 182464f6645SManish Chopra struct qed_tunn_start_params { 183464f6645SManish Chopra unsigned long tunn_mode; 184464f6645SManish Chopra u16 vxlan_udp_port; 185464f6645SManish Chopra u16 geneve_udp_port; 186464f6645SManish Chopra u8 update_vxlan_udp_port; 187464f6645SManish Chopra u8 update_geneve_udp_port; 188464f6645SManish Chopra u8 tunn_clss_vxlan; 189464f6645SManish Chopra u8 tunn_clss_l2geneve; 190464f6645SManish Chopra u8 tunn_clss_ipgeneve; 191464f6645SManish Chopra u8 tunn_clss_l2gre; 192464f6645SManish Chopra u8 tunn_clss_ipgre; 193464f6645SManish Chopra }; 194464f6645SManish Chopra 195464f6645SManish Chopra struct qed_tunn_update_params { 196464f6645SManish Chopra unsigned long tunn_mode_update_mask; 197464f6645SManish Chopra unsigned long tunn_mode; 198464f6645SManish Chopra u16 vxlan_udp_port; 199464f6645SManish Chopra u16 geneve_udp_port; 200464f6645SManish Chopra u8 update_rx_pf_clss; 201464f6645SManish Chopra u8 update_tx_pf_clss; 202464f6645SManish Chopra u8 update_vxlan_udp_port; 203464f6645SManish Chopra u8 update_geneve_udp_port; 204464f6645SManish Chopra u8 tunn_clss_vxlan; 205464f6645SManish Chopra u8 tunn_clss_l2geneve; 206464f6645SManish Chopra u8 tunn_clss_ipgeneve; 207464f6645SManish Chopra u8 tunn_clss_l2gre; 208464f6645SManish Chopra u8 tunn_clss_ipgre; 209464f6645SManish Chopra }; 210464f6645SManish Chopra 211fe56b9e6SYuval Mintz /* The PCI personality is not quite synonymous to protocol ID: 212fe56b9e6SYuval Mintz * 1. All personalities need CORE connections 213c851a9dcSKalderon, Michal * 2. The Ethernet personality may support also the RoCE/iWARP protocol 214fe56b9e6SYuval Mintz */ 215fe56b9e6SYuval Mintz enum qed_pci_personality { 216fe56b9e6SYuval Mintz QED_PCI_ETH, 2171e128c81SArun Easi QED_PCI_FCOE, 218c5ac9319SYuval Mintz QED_PCI_ISCSI, 219c5ac9319SYuval Mintz QED_PCI_ETH_ROCE, 220c851a9dcSKalderon, Michal QED_PCI_ETH_IWARP, 221c851a9dcSKalderon, Michal QED_PCI_ETH_RDMA, 222c851a9dcSKalderon, Michal QED_PCI_DEFAULT, /* default in shmem */ 223fe56b9e6SYuval Mintz }; 224fe56b9e6SYuval Mintz 225fe56b9e6SYuval Mintz /* All VFs are symmetric, all counters are PF + all VFs */ 226fe56b9e6SYuval Mintz struct qed_qm_iids { 227fe56b9e6SYuval Mintz u32 cids; 228fe56b9e6SYuval Mintz u32 vf_cids; 229fe56b9e6SYuval Mintz u32 tids; 230fe56b9e6SYuval Mintz }; 231fe56b9e6SYuval Mintz 2322edbff8dSTomer Tayar /* HW / FW resources, output of features supported below, most information 2332edbff8dSTomer Tayar * is received from MFW. 2342edbff8dSTomer Tayar */ 2352edbff8dSTomer Tayar enum qed_resources { 236fe56b9e6SYuval Mintz QED_SB, 23725c089d7SYuval Mintz QED_L2_QUEUE, 238fe56b9e6SYuval Mintz QED_VPORT, 23925c089d7SYuval Mintz QED_RSS_ENG, 240fe56b9e6SYuval Mintz QED_PQ, 241fe56b9e6SYuval Mintz QED_RL, 24225c089d7SYuval Mintz QED_MAC, 24325c089d7SYuval Mintz QED_VLAN, 24451ff1725SRam Amrani QED_RDMA_CNQ_RAM, 245fe56b9e6SYuval Mintz QED_ILT, 2460a7fb11cSYuval Mintz QED_LL2_QUEUE, 2472edbff8dSTomer Tayar QED_CMDQS_CQS, 24851ff1725SRam Amrani QED_RDMA_STATS_QUEUE, 2499c8517c4STomer Tayar QED_BDQ, 250fe56b9e6SYuval Mintz QED_MAX_RESC, 251fe56b9e6SYuval Mintz }; 252fe56b9e6SYuval Mintz 25325c089d7SYuval Mintz enum QED_FEATURE { 25425c089d7SYuval Mintz QED_PF_L2_QUE, 25532a47e72SYuval Mintz QED_VF, 25651ff1725SRam Amrani QED_RDMA_CNQ, 25708737a3fSMintz, Yuval QED_ISCSI_CQ, 2581e128c81SArun Easi QED_FCOE_CQ, 25908737a3fSMintz, Yuval QED_VF_L2_QUE, 26025c089d7SYuval Mintz QED_MAX_FEATURES, 26125c089d7SYuval Mintz }; 26225c089d7SYuval Mintz 263cc875c2eSYuval Mintz enum QED_PORT_MODE { 264cc875c2eSYuval Mintz QED_PORT_MODE_DE_2X40G, 265cc875c2eSYuval Mintz QED_PORT_MODE_DE_2X50G, 266cc875c2eSYuval Mintz QED_PORT_MODE_DE_1X100G, 267cc875c2eSYuval Mintz QED_PORT_MODE_DE_4X10G_F, 268cc875c2eSYuval Mintz QED_PORT_MODE_DE_4X10G_E, 269cc875c2eSYuval Mintz QED_PORT_MODE_DE_4X20G, 270cc875c2eSYuval Mintz QED_PORT_MODE_DE_1X40G, 271cc875c2eSYuval Mintz QED_PORT_MODE_DE_2X25G, 2729c79ddaaSMintz, Yuval QED_PORT_MODE_DE_1X25G, 2739c79ddaaSMintz, Yuval QED_PORT_MODE_DE_4X25G, 2749c79ddaaSMintz, Yuval QED_PORT_MODE_DE_2X10G, 275cc875c2eSYuval Mintz }; 276cc875c2eSYuval Mintz 277fc48b7a6SYuval Mintz enum qed_dev_cap { 278fc48b7a6SYuval Mintz QED_DEV_CAP_ETH, 2791e128c81SArun Easi QED_DEV_CAP_FCOE, 280c5ac9319SYuval Mintz QED_DEV_CAP_ISCSI, 281c5ac9319SYuval Mintz QED_DEV_CAP_ROCE, 282c851a9dcSKalderon, Michal QED_DEV_CAP_IWARP, 283fc48b7a6SYuval Mintz }; 284fc48b7a6SYuval Mintz 28514d39648SMintz, Yuval enum qed_wol_support { 28614d39648SMintz, Yuval QED_WOL_SUPPORT_NONE, 28714d39648SMintz, Yuval QED_WOL_SUPPORT_PME, 28814d39648SMintz, Yuval }; 28914d39648SMintz, Yuval 290fe56b9e6SYuval Mintz struct qed_hw_info { 291fe56b9e6SYuval Mintz /* PCI personality */ 292fe56b9e6SYuval Mintz enum qed_pci_personality personality; 293c851a9dcSKalderon, Michal #define QED_IS_RDMA_PERSONALITY(dev) \ 294c851a9dcSKalderon, Michal ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \ 295c851a9dcSKalderon, Michal (dev)->hw_info.personality == QED_PCI_ETH_IWARP || \ 296c851a9dcSKalderon, Michal (dev)->hw_info.personality == QED_PCI_ETH_RDMA) 297c851a9dcSKalderon, Michal #define QED_IS_ROCE_PERSONALITY(dev) \ 298c851a9dcSKalderon, Michal ((dev)->hw_info.personality == QED_PCI_ETH_ROCE || \ 299c851a9dcSKalderon, Michal (dev)->hw_info.personality == QED_PCI_ETH_RDMA) 300c851a9dcSKalderon, Michal #define QED_IS_IWARP_PERSONALITY(dev) \ 301c851a9dcSKalderon, Michal ((dev)->hw_info.personality == QED_PCI_ETH_IWARP || \ 302c851a9dcSKalderon, Michal (dev)->hw_info.personality == QED_PCI_ETH_RDMA) 303c851a9dcSKalderon, Michal #define QED_IS_L2_PERSONALITY(dev) \ 304c851a9dcSKalderon, Michal ((dev)->hw_info.personality == QED_PCI_ETH || \ 305c851a9dcSKalderon, Michal QED_IS_RDMA_PERSONALITY(dev)) 306c851a9dcSKalderon, Michal #define QED_IS_FCOE_PERSONALITY(dev) \ 307c851a9dcSKalderon, Michal ((dev)->hw_info.personality == QED_PCI_FCOE) 308c851a9dcSKalderon, Michal #define QED_IS_ISCSI_PERSONALITY(dev) \ 309c851a9dcSKalderon, Michal ((dev)->hw_info.personality == QED_PCI_ISCSI) 310fe56b9e6SYuval Mintz 311fe56b9e6SYuval Mintz /* Resource Allocation scheme results */ 312fe56b9e6SYuval Mintz u32 resc_start[QED_MAX_RESC]; 313fe56b9e6SYuval Mintz u32 resc_num[QED_MAX_RESC]; 31425c089d7SYuval Mintz u32 feat_num[QED_MAX_FEATURES]; 315fe56b9e6SYuval Mintz 316fe56b9e6SYuval Mintz #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) 317fe56b9e6SYuval Mintz #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) 318dbb799c3SYuval Mintz #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ 319dbb799c3SYuval Mintz RESC_NUM(_p_hwfn, resc)) 320fe56b9e6SYuval Mintz #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) 321fe56b9e6SYuval Mintz 322b5a9ee7cSAriel Elior /* Amount of traffic classes HW supports */ 323b5a9ee7cSAriel Elior u8 num_hw_tc; 324b5a9ee7cSAriel Elior 325b5a9ee7cSAriel Elior /* Amount of TCs which should be active according to DCBx or upper 326b5a9ee7cSAriel Elior * layer driver configuration. 327b5a9ee7cSAriel Elior */ 328b5a9ee7cSAriel Elior u8 num_active_tc; 329fe56b9e6SYuval Mintz u8 offload_tc; 330fe56b9e6SYuval Mintz 331fe56b9e6SYuval Mintz u32 concrete_fid; 332fe56b9e6SYuval Mintz u16 opaque_fid; 333fe56b9e6SYuval Mintz u16 ovlan; 334fe56b9e6SYuval Mintz u32 part_num[4]; 335fe56b9e6SYuval Mintz 336fe56b9e6SYuval Mintz unsigned char hw_mac_addr[ETH_ALEN]; 3371e128c81SArun Easi u64 node_wwn; 3381e128c81SArun Easi u64 port_wwn; 3391e128c81SArun Easi 3401e128c81SArun Easi u16 num_fcoe_conns; 341fe56b9e6SYuval Mintz 342fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 343fe56b9e6SYuval Mintz 344fe56b9e6SYuval Mintz u32 port_mode; 345fe56b9e6SYuval Mintz u32 hw_mode; 346fc48b7a6SYuval Mintz unsigned long device_capabilities; 3470fefbfbaSSudarsana Kalluru u16 mtu; 34814d39648SMintz, Yuval 34914d39648SMintz, Yuval enum qed_wol_support b_wol_support; 350fe56b9e6SYuval Mintz }; 351fe56b9e6SYuval Mintz 352fe56b9e6SYuval Mintz /* maximun size of read/write commands (HW limit) */ 353fe56b9e6SYuval Mintz #define DMAE_MAX_RW_SIZE 0x2000 354fe56b9e6SYuval Mintz 355fe56b9e6SYuval Mintz struct qed_dmae_info { 356fe56b9e6SYuval Mintz /* Mutex for synchronizing access to functions */ 357fe56b9e6SYuval Mintz struct mutex mutex; 358fe56b9e6SYuval Mintz 359fe56b9e6SYuval Mintz u8 channel; 360fe56b9e6SYuval Mintz 361fe56b9e6SYuval Mintz dma_addr_t completion_word_phys_addr; 362fe56b9e6SYuval Mintz 363fe56b9e6SYuval Mintz /* The memory location where the DMAE writes the completion 364fe56b9e6SYuval Mintz * value when an operation is finished on this context. 365fe56b9e6SYuval Mintz */ 366fe56b9e6SYuval Mintz u32 *p_completion_word; 367fe56b9e6SYuval Mintz 368fe56b9e6SYuval Mintz dma_addr_t intermediate_buffer_phys_addr; 369fe56b9e6SYuval Mintz 370fe56b9e6SYuval Mintz /* An intermediate buffer for DMAE operations that use virtual 371fe56b9e6SYuval Mintz * addresses - data is DMA'd to/from this buffer and then 372fe56b9e6SYuval Mintz * memcpy'd to/from the virtual address 373fe56b9e6SYuval Mintz */ 374fe56b9e6SYuval Mintz u32 *p_intermediate_buffer; 375fe56b9e6SYuval Mintz 376fe56b9e6SYuval Mintz dma_addr_t dmae_cmd_phys_addr; 377fe56b9e6SYuval Mintz struct dmae_cmd *p_dmae_cmd; 378fe56b9e6SYuval Mintz }; 379fe56b9e6SYuval Mintz 380bcd197c8SManish Chopra struct qed_wfq_data { 381bcd197c8SManish Chopra /* when feature is configured for at least 1 vport */ 382bcd197c8SManish Chopra u32 min_speed; 383bcd197c8SManish Chopra bool configured; 384bcd197c8SManish Chopra }; 385bcd197c8SManish Chopra 386fe56b9e6SYuval Mintz struct qed_qm_info { 387fe56b9e6SYuval Mintz struct init_qm_pq_params *qm_pq_params; 388fe56b9e6SYuval Mintz struct init_qm_vport_params *qm_vport_params; 389fe56b9e6SYuval Mintz struct init_qm_port_params *qm_port_params; 390fe56b9e6SYuval Mintz u16 start_pq; 391fe56b9e6SYuval Mintz u8 start_vport; 392b5a9ee7cSAriel Elior u16 pure_lb_pq; 393b5a9ee7cSAriel Elior u16 offload_pq; 394b5a9ee7cSAriel Elior u16 low_latency_pq; 395b5a9ee7cSAriel Elior u16 pure_ack_pq; 396b5a9ee7cSAriel Elior u16 ooo_pq; 397b5a9ee7cSAriel Elior u16 first_vf_pq; 398b5a9ee7cSAriel Elior u16 first_mcos_pq; 399b5a9ee7cSAriel Elior u16 first_rl_pq; 400fe56b9e6SYuval Mintz u16 num_pqs; 401fe56b9e6SYuval Mintz u16 num_vf_pqs; 402fe56b9e6SYuval Mintz u8 num_vports; 403fe56b9e6SYuval Mintz u8 max_phys_tcs_per_port; 404b5a9ee7cSAriel Elior u8 ooo_tc; 405fe56b9e6SYuval Mintz bool pf_rl_en; 406fe56b9e6SYuval Mintz bool pf_wfq_en; 407fe56b9e6SYuval Mintz bool vport_rl_en; 408fe56b9e6SYuval Mintz bool vport_wfq_en; 409fe56b9e6SYuval Mintz u8 pf_wfq; 410fe56b9e6SYuval Mintz u32 pf_rl; 411bcd197c8SManish Chopra struct qed_wfq_data *wfq_data; 412dbb799c3SYuval Mintz u8 num_pf_rls; 413fe56b9e6SYuval Mintz }; 414fe56b9e6SYuval Mintz 4159df2ed04SManish Chopra struct storm_stats { 4169df2ed04SManish Chopra u32 address; 4179df2ed04SManish Chopra u32 len; 4189df2ed04SManish Chopra }; 4199df2ed04SManish Chopra 4209df2ed04SManish Chopra struct qed_storm_stats { 4219df2ed04SManish Chopra struct storm_stats mstats; 4229df2ed04SManish Chopra struct storm_stats pstats; 4239df2ed04SManish Chopra struct storm_stats tstats; 4249df2ed04SManish Chopra struct storm_stats ustats; 4259df2ed04SManish Chopra }; 4269df2ed04SManish Chopra 427fe56b9e6SYuval Mintz struct qed_fw_data { 4289df2ed04SManish Chopra struct fw_ver_info *fw_ver_info; 429fe56b9e6SYuval Mintz const u8 *modes_tree_buf; 430fe56b9e6SYuval Mintz union init_op *init_ops; 431fe56b9e6SYuval Mintz const u32 *arr_data; 432fe56b9e6SYuval Mintz u32 init_ops_size; 433fe56b9e6SYuval Mintz }; 434fe56b9e6SYuval Mintz 4351a850bfcSMintz, Yuval enum BAR_ID { 4361a850bfcSMintz, Yuval BAR_ID_0, /* used for GRC */ 4371a850bfcSMintz, Yuval BAR_ID_1 /* Used for doorbells */ 4381a850bfcSMintz, Yuval }; 4391a850bfcSMintz, Yuval 4405d24bcf1STomer Tayar #define DRV_MODULE_VERSION \ 4415d24bcf1STomer Tayar __stringify(QED_MAJOR_VERSION) "." \ 4425d24bcf1STomer Tayar __stringify(QED_MINOR_VERSION) "." \ 4435d24bcf1STomer Tayar __stringify(QED_REVISION_VERSION) "." \ 4445d24bcf1STomer Tayar __stringify(QED_ENGINEERING_VERSION) 4455d24bcf1STomer Tayar 446fe56b9e6SYuval Mintz struct qed_simd_fp_handler { 447fe56b9e6SYuval Mintz void *token; 448fe56b9e6SYuval Mintz void (*func)(void *); 449fe56b9e6SYuval Mintz }; 450fe56b9e6SYuval Mintz 451fe56b9e6SYuval Mintz struct qed_hwfn { 452fe56b9e6SYuval Mintz struct qed_dev *cdev; 453fe56b9e6SYuval Mintz u8 my_id; /* ID inside the PF */ 454fe56b9e6SYuval Mintz #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) 455fe56b9e6SYuval Mintz u8 rel_pf_id; /* Relative to engine*/ 456fe56b9e6SYuval Mintz u8 abs_pf_id; 4579c79ddaaSMintz, Yuval #define QED_PATH_ID(_p_hwfn) \ 4589c79ddaaSMintz, Yuval (QED_IS_K2((_p_hwfn)->cdev) ? 0 : ((_p_hwfn)->abs_pf_id & 1)) 459fe56b9e6SYuval Mintz u8 port_id; 460fe56b9e6SYuval Mintz bool b_active; 461fe56b9e6SYuval Mintz 462fe56b9e6SYuval Mintz u32 dp_module; 463fe56b9e6SYuval Mintz u8 dp_level; 464fe56b9e6SYuval Mintz char name[NAME_SIZE]; 465fe56b9e6SYuval Mintz 466fe56b9e6SYuval Mintz bool first_on_engine; 467fe56b9e6SYuval Mintz bool hw_init_done; 468fe56b9e6SYuval Mintz 4691408cc1fSYuval Mintz u8 num_funcs_on_engine; 470dbb799c3SYuval Mintz u8 enabled_func_idx; 4711408cc1fSYuval Mintz 472fe56b9e6SYuval Mintz /* BAR access */ 473fe56b9e6SYuval Mintz void __iomem *regview; 474fe56b9e6SYuval Mintz void __iomem *doorbells; 475fe56b9e6SYuval Mintz u64 db_phys_addr; 476fe56b9e6SYuval Mintz unsigned long db_size; 477fe56b9e6SYuval Mintz 478fe56b9e6SYuval Mintz /* PTT pool */ 479fe56b9e6SYuval Mintz struct qed_ptt_pool *p_ptt_pool; 480fe56b9e6SYuval Mintz 481fe56b9e6SYuval Mintz /* HW info */ 482fe56b9e6SYuval Mintz struct qed_hw_info hw_info; 483fe56b9e6SYuval Mintz 484fe56b9e6SYuval Mintz /* rt_array (for init-tool) */ 485fc48b7a6SYuval Mintz struct qed_rt_data rt_data; 486fe56b9e6SYuval Mintz 487fe56b9e6SYuval Mintz /* SPQ */ 488fe56b9e6SYuval Mintz struct qed_spq *p_spq; 489fe56b9e6SYuval Mintz 490fe56b9e6SYuval Mintz /* EQ */ 491fe56b9e6SYuval Mintz struct qed_eq *p_eq; 492fe56b9e6SYuval Mintz 493fe56b9e6SYuval Mintz /* Consolidate Q*/ 494fe56b9e6SYuval Mintz struct qed_consq *p_consq; 495fe56b9e6SYuval Mintz 496fe56b9e6SYuval Mintz /* Slow-Path definitions */ 497fe56b9e6SYuval Mintz struct tasklet_struct *sp_dpc; 498fe56b9e6SYuval Mintz bool b_sp_dpc_enabled; 499fe56b9e6SYuval Mintz 500fe56b9e6SYuval Mintz struct qed_ptt *p_main_ptt; 501fe56b9e6SYuval Mintz struct qed_ptt *p_dpc_ptt; 502fe56b9e6SYuval Mintz 503d179bd16Ssudarsana.kalluru@cavium.com /* PTP will be used only by the leading function. 504d179bd16Ssudarsana.kalluru@cavium.com * Usage of all PTP-apis should be synchronized as result. 505d179bd16Ssudarsana.kalluru@cavium.com */ 506d179bd16Ssudarsana.kalluru@cavium.com struct qed_ptt *p_ptp_ptt; 507d179bd16Ssudarsana.kalluru@cavium.com 508fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb; 509fe56b9e6SYuval Mintz struct qed_sb_attn_info *p_sb_attn; 510fe56b9e6SYuval Mintz 511fe56b9e6SYuval Mintz /* Protocol related */ 5120a7fb11cSYuval Mintz bool using_ll2; 5130a7fb11cSYuval Mintz struct qed_ll2_info *p_ll2_info; 5141d6cff4fSYuval Mintz struct qed_ooo_info *p_ooo_info; 51551ff1725SRam Amrani struct qed_rdma_info *p_rdma_info; 516fc831825SYuval Mintz struct qed_iscsi_info *p_iscsi_info; 5171e128c81SArun Easi struct qed_fcoe_info *p_fcoe_info; 518fe56b9e6SYuval Mintz struct qed_pf_params pf_params; 519fe56b9e6SYuval Mintz 520dbb799c3SYuval Mintz bool b_rdma_enabled_in_prs; 521dbb799c3SYuval Mintz u32 rdma_prs_search_reg; 522dbb799c3SYuval Mintz 523fe56b9e6SYuval Mintz struct qed_cxt_mngr *p_cxt_mngr; 524fe56b9e6SYuval Mintz 525fe56b9e6SYuval Mintz /* Flag indicating whether interrupts are enabled or not*/ 526fe56b9e6SYuval Mintz bool b_int_enabled; 5278f16bc97SSudarsana Kalluru bool b_int_requested; 528fe56b9e6SYuval Mintz 529fc916ff2SSudarsana Reddy Kalluru /* True if the driver requests for the link */ 530fc916ff2SSudarsana Reddy Kalluru bool b_drv_link_init; 531fc916ff2SSudarsana Reddy Kalluru 5321408cc1fSYuval Mintz struct qed_vf_iov *vf_iov_info; 53332a47e72SYuval Mintz struct qed_pf_iov *pf_iov_info; 534fe56b9e6SYuval Mintz struct qed_mcp_info *mcp_info; 535fe56b9e6SYuval Mintz 53639651abdSSudarsana Reddy Kalluru struct qed_dcbx_info *p_dcbx_info; 53739651abdSSudarsana Reddy Kalluru 538fe56b9e6SYuval Mintz struct qed_dmae_info dmae_info; 539fe56b9e6SYuval Mintz 540fe56b9e6SYuval Mintz /* QM init */ 541fe56b9e6SYuval Mintz struct qed_qm_info qm_info; 5429df2ed04SManish Chopra struct qed_storm_stats storm_stats; 543fe56b9e6SYuval Mintz 544fe56b9e6SYuval Mintz /* Buffer for unzipping firmware data */ 545fe56b9e6SYuval Mintz void *unzip_buf; 546fe56b9e6SYuval Mintz 547c965db44STomer Tayar struct dbg_tools_data dbg_info; 548c965db44STomer Tayar 54951ff1725SRam Amrani /* PWM region specific data */ 55020b1bd96SRam Amrani u16 wid_count; 55151ff1725SRam Amrani u32 dpi_size; 55251ff1725SRam Amrani u32 dpi_count; 55351ff1725SRam Amrani 55451ff1725SRam Amrani /* This is used to calculate the doorbell address */ 55551ff1725SRam Amrani u32 dpi_start_offset; 55651ff1725SRam Amrani 55751ff1725SRam Amrani /* If one of the following is set then EDPM shouldn't be used */ 55851ff1725SRam Amrani u8 dcbx_no_edpm; 55951ff1725SRam Amrani u8 db_bar_no_edpm; 56051ff1725SRam Amrani 5610db711bbSMintz, Yuval /* L2-related */ 5620db711bbSMintz, Yuval struct qed_l2_info *p_l2_info; 5630db711bbSMintz, Yuval 564d51e4af5SChopra, Manish struct qed_ptt *p_arfs_ptt; 565d51e4af5SChopra, Manish 566fe56b9e6SYuval Mintz struct qed_simd_fp_handler simd_proto_handler[64]; 567fe56b9e6SYuval Mintz 56837bff2b9SYuval Mintz #ifdef CONFIG_QED_SRIOV 56937bff2b9SYuval Mintz struct workqueue_struct *iov_wq; 57037bff2b9SYuval Mintz struct delayed_work iov_task; 57137bff2b9SYuval Mintz unsigned long iov_task_flags; 57237bff2b9SYuval Mintz #endif 57337bff2b9SYuval Mintz 574fe56b9e6SYuval Mintz struct z_stream_s *stream; 575fe56b9e6SYuval Mintz }; 576fe56b9e6SYuval Mintz 577fe56b9e6SYuval Mintz struct pci_params { 578fe56b9e6SYuval Mintz int pm_cap; 579fe56b9e6SYuval Mintz 580fe56b9e6SYuval Mintz unsigned long mem_start; 581fe56b9e6SYuval Mintz unsigned long mem_end; 582fe56b9e6SYuval Mintz unsigned int irq; 583fe56b9e6SYuval Mintz u8 pf_num; 584fe56b9e6SYuval Mintz }; 585fe56b9e6SYuval Mintz 586fe56b9e6SYuval Mintz struct qed_int_param { 587fe56b9e6SYuval Mintz u32 int_mode; 588fe56b9e6SYuval Mintz u8 num_vectors; 589fe56b9e6SYuval Mintz u8 min_msix_cnt; /* for minimal functionality */ 590fe56b9e6SYuval Mintz }; 591fe56b9e6SYuval Mintz 592fe56b9e6SYuval Mintz struct qed_int_params { 593fe56b9e6SYuval Mintz struct qed_int_param in; 594fe56b9e6SYuval Mintz struct qed_int_param out; 595fe56b9e6SYuval Mintz struct msix_entry *msix_table; 596fe56b9e6SYuval Mintz bool fp_initialized; 597fe56b9e6SYuval Mintz u8 fp_msix_base; 598fe56b9e6SYuval Mintz u8 fp_msix_cnt; 59951ff1725SRam Amrani u8 rdma_msix_base; 60051ff1725SRam Amrani u8 rdma_msix_cnt; 601fe56b9e6SYuval Mintz }; 602fe56b9e6SYuval Mintz 603c965db44STomer Tayar struct qed_dbg_feature { 604c965db44STomer Tayar struct dentry *dentry; 605c965db44STomer Tayar u8 *dump_buf; 606c965db44STomer Tayar u32 buf_size; 607c965db44STomer Tayar u32 dumped_dwords; 608c965db44STomer Tayar }; 609c965db44STomer Tayar 610c965db44STomer Tayar struct qed_dbg_params { 611c965db44STomer Tayar struct qed_dbg_feature features[DBG_FEATURE_NUM]; 612c965db44STomer Tayar u8 engine_for_debug; 613c965db44STomer Tayar bool print_data; 614c965db44STomer Tayar }; 615c965db44STomer Tayar 616fe56b9e6SYuval Mintz struct qed_dev { 617fe56b9e6SYuval Mintz u32 dp_module; 618fe56b9e6SYuval Mintz u8 dp_level; 619fe56b9e6SYuval Mintz char name[NAME_SIZE]; 620fe56b9e6SYuval Mintz 6219c79ddaaSMintz, Yuval enum qed_dev_type type; 622fc48b7a6SYuval Mintz /* Translate type/revision combo into the proper conditions */ 623fc48b7a6SYuval Mintz #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB) 624fc48b7a6SYuval Mintz #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \ 625fc48b7a6SYuval Mintz CHIP_REV_IS_B0(dev)) 626c965db44STomer Tayar #define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH) 627c965db44STomer Tayar #define QED_IS_K2(dev) QED_IS_AH(dev) 628fc48b7a6SYuval Mintz 629fc48b7a6SYuval Mintz u16 vendor_id; 630fc48b7a6SYuval Mintz u16 device_id; 6319c79ddaaSMintz, Yuval #define QED_DEV_ID_MASK 0xff00 6329c79ddaaSMintz, Yuval #define QED_DEV_ID_MASK_BB 0x1600 6339c79ddaaSMintz, Yuval #define QED_DEV_ID_MASK_AH 0x8000 634fe56b9e6SYuval Mintz 635fe56b9e6SYuval Mintz u16 chip_num; 636fe56b9e6SYuval Mintz #define CHIP_NUM_MASK 0xffff 637fe56b9e6SYuval Mintz #define CHIP_NUM_SHIFT 16 638fe56b9e6SYuval Mintz 639fe56b9e6SYuval Mintz u16 chip_rev; 640fe56b9e6SYuval Mintz #define CHIP_REV_MASK 0xf 641fe56b9e6SYuval Mintz #define CHIP_REV_SHIFT 12 642fc48b7a6SYuval Mintz #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1) 643fe56b9e6SYuval Mintz 644fe56b9e6SYuval Mintz u16 chip_metal; 645fe56b9e6SYuval Mintz #define CHIP_METAL_MASK 0xff 646fe56b9e6SYuval Mintz #define CHIP_METAL_SHIFT 4 647fe56b9e6SYuval Mintz 648fe56b9e6SYuval Mintz u16 chip_bond_id; 649fe56b9e6SYuval Mintz #define CHIP_BOND_ID_MASK 0xf 650fe56b9e6SYuval Mintz #define CHIP_BOND_ID_SHIFT 0 651fe56b9e6SYuval Mintz 652fe56b9e6SYuval Mintz u8 num_engines; 65378cea9ffSTomer Tayar u8 num_ports_in_engine; 654fe56b9e6SYuval Mintz u8 num_funcs_in_port; 655fe56b9e6SYuval Mintz 656fe56b9e6SYuval Mintz u8 path_id; 657fc48b7a6SYuval Mintz enum qed_mf_mode mf_mode; 658fc48b7a6SYuval Mintz #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT) 659fc48b7a6SYuval Mintz #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR) 660fc48b7a6SYuval Mintz #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN) 661fe56b9e6SYuval Mintz 662fe56b9e6SYuval Mintz int pcie_width; 663fe56b9e6SYuval Mintz int pcie_speed; 664fe56b9e6SYuval Mintz 665fe56b9e6SYuval Mintz /* Add MF related configuration */ 666fe56b9e6SYuval Mintz u8 mcp_rev; 667fe56b9e6SYuval Mintz u8 boot_mode; 668fe56b9e6SYuval Mintz 66914d39648SMintz, Yuval /* WoL related configurations */ 67014d39648SMintz, Yuval u8 wol_config; 67114d39648SMintz, Yuval u8 wol_mac[ETH_ALEN]; 672fe56b9e6SYuval Mintz 673fe56b9e6SYuval Mintz u32 int_mode; 674fe56b9e6SYuval Mintz enum qed_coalescing_mode int_coalescing_mode; 67551d99880SSudarsana Reddy Kalluru u16 rx_coalesce_usecs; 67651d99880SSudarsana Reddy Kalluru u16 tx_coalesce_usecs; 677fe56b9e6SYuval Mintz 678fe56b9e6SYuval Mintz /* Start Bar offset of first hwfn */ 679fe56b9e6SYuval Mintz void __iomem *regview; 680fe56b9e6SYuval Mintz void __iomem *doorbells; 681fe56b9e6SYuval Mintz u64 db_phys_addr; 682fe56b9e6SYuval Mintz unsigned long db_size; 683fe56b9e6SYuval Mintz 684fe56b9e6SYuval Mintz /* PCI */ 685fe56b9e6SYuval Mintz u8 cache_shift; 686fe56b9e6SYuval Mintz 687fe56b9e6SYuval Mintz /* Init */ 688fe56b9e6SYuval Mintz const struct iro *iro_arr; 689fe56b9e6SYuval Mintz #define IRO (p_hwfn->cdev->iro_arr) 690fe56b9e6SYuval Mintz 691fe56b9e6SYuval Mintz /* HW functions */ 692fe56b9e6SYuval Mintz u8 num_hwfns; 693fe56b9e6SYuval Mintz struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; 694fe56b9e6SYuval Mintz 69532a47e72SYuval Mintz /* SRIOV */ 69632a47e72SYuval Mintz struct qed_hw_sriov_info *p_iov_info; 69732a47e72SYuval Mintz #define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info) 69819968430SChopra, Manish struct qed_tunnel_info tunnel; 6991408cc1fSYuval Mintz bool b_is_vf; 700fe56b9e6SYuval Mintz u32 drv_type; 701fe56b9e6SYuval Mintz struct qed_eth_stats *reset_stats; 702fe56b9e6SYuval Mintz struct qed_fw_data *fw_data; 703fe56b9e6SYuval Mintz 704fe56b9e6SYuval Mintz u32 mcp_nvm_resp; 705fe56b9e6SYuval Mintz 706fe56b9e6SYuval Mintz /* Linux specific here */ 707fe56b9e6SYuval Mintz struct qede_dev *edev; 708fe56b9e6SYuval Mintz struct pci_dev *pdev; 709fc831825SYuval Mintz u32 flags; 710fc831825SYuval Mintz #define QED_FLAG_STORAGE_STARTED (BIT(0)) 711fe56b9e6SYuval Mintz int msg_enable; 712fe56b9e6SYuval Mintz 713fe56b9e6SYuval Mintz struct pci_params pci_params; 714fe56b9e6SYuval Mintz 715fe56b9e6SYuval Mintz struct qed_int_params int_params; 716fe56b9e6SYuval Mintz 717fe56b9e6SYuval Mintz u8 protocol; 718fe56b9e6SYuval Mintz #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH) 7191e128c81SArun Easi #define IS_QED_FCOE_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_FCOE) 720fe56b9e6SYuval Mintz 721cc875c2eSYuval Mintz /* Callbacks to protocol driver */ 722cc875c2eSYuval Mintz union { 723cc875c2eSYuval Mintz struct qed_common_cb_ops *common; 724cc875c2eSYuval Mintz struct qed_eth_cb_ops *eth; 7251e128c81SArun Easi struct qed_fcoe_cb_ops *fcoe; 726fc831825SYuval Mintz struct qed_iscsi_cb_ops *iscsi; 727cc875c2eSYuval Mintz } protocol_ops; 728cc875c2eSYuval Mintz void *ops_cookie; 729cc875c2eSYuval Mintz 730c965db44STomer Tayar struct qed_dbg_params dbg_params; 731c965db44STomer Tayar 7320a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 7330a7fb11cSYuval Mintz struct qed_cb_ll2_info *ll2; 7340a7fb11cSYuval Mintz u8 ll2_mac_address[ETH_ALEN]; 7350a7fb11cSYuval Mintz #endif 736fc831825SYuval Mintz DECLARE_HASHTABLE(connections, 10); 737fe56b9e6SYuval Mintz const struct firmware *firmware; 73851ff1725SRam Amrani 73951ff1725SRam Amrani u32 rdma_max_sge; 74051ff1725SRam Amrani u32 rdma_max_inline; 74151ff1725SRam Amrani u32 rdma_max_srq_sge; 742eaf3c0c6SChopra, Manish u16 tunn_feature_mask; 743fe56b9e6SYuval Mintz }; 744fe56b9e6SYuval Mintz 7459c79ddaaSMintz, Yuval #define NUM_OF_VFS(dev) (QED_IS_BB(dev) ? MAX_NUM_VFS_BB \ 7469c79ddaaSMintz, Yuval : MAX_NUM_VFS_K2) 7479c79ddaaSMintz, Yuval #define NUM_OF_L2_QUEUES(dev) (QED_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \ 7489c79ddaaSMintz, Yuval : MAX_NUM_L2_QUEUES_K2) 7499c79ddaaSMintz, Yuval #define NUM_OF_PORTS(dev) (QED_IS_BB(dev) ? MAX_NUM_PORTS_BB \ 7509c79ddaaSMintz, Yuval : MAX_NUM_PORTS_K2) 7519c79ddaaSMintz, Yuval #define NUM_OF_SBS(dev) (QED_IS_BB(dev) ? MAX_SB_PER_PATH_BB \ 7529c79ddaaSMintz, Yuval : MAX_SB_PER_PATH_K2) 7539c79ddaaSMintz, Yuval #define NUM_OF_ENG_PFS(dev) (QED_IS_BB(dev) ? MAX_NUM_PFS_BB \ 7549c79ddaaSMintz, Yuval : MAX_NUM_PFS_K2) 755fe56b9e6SYuval Mintz 756fe56b9e6SYuval Mintz /** 757fe56b9e6SYuval Mintz * @brief qed_concrete_to_sw_fid - get the sw function id from 758fe56b9e6SYuval Mintz * the concrete value. 759fe56b9e6SYuval Mintz * 760fe56b9e6SYuval Mintz * @param concrete_fid 761fe56b9e6SYuval Mintz * 762fe56b9e6SYuval Mintz * @return inline u8 763fe56b9e6SYuval Mintz */ 764fe56b9e6SYuval Mintz static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev, 765fe56b9e6SYuval Mintz u32 concrete_fid) 766fe56b9e6SYuval Mintz { 7674870e704SYuval Mintz u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); 768fe56b9e6SYuval Mintz u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); 7694870e704SYuval Mintz u8 vf_valid = GET_FIELD(concrete_fid, 7704870e704SYuval Mintz PXP_CONCRETE_FID_VFVALID); 7714870e704SYuval Mintz u8 sw_fid; 772fe56b9e6SYuval Mintz 7734870e704SYuval Mintz if (vf_valid) 7744870e704SYuval Mintz sw_fid = vfid + MAX_NUM_PFS; 7754870e704SYuval Mintz else 7764870e704SYuval Mintz sw_fid = pfid; 7774870e704SYuval Mintz 7784870e704SYuval Mintz return sw_fid; 779fe56b9e6SYuval Mintz } 780fe56b9e6SYuval Mintz 781fe56b9e6SYuval Mintz #define PURE_LB_TC 8 782dbb799c3SYuval Mintz #define OOO_LB_TC 9 783fe56b9e6SYuval Mintz 784733def6aSYuval Mintz int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate); 7856f437d43SMintz, Yuval void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, 7866f437d43SMintz, Yuval struct qed_ptt *p_ptt, 7876f437d43SMintz, Yuval u32 min_pf_rate); 788bcd197c8SManish Chopra 789733def6aSYuval Mintz void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 7909c79ddaaSMintz, Yuval int qed_device_num_engines(struct qed_dev *cdev); 791db82f70eSsudarsana.kalluru@cavium.com int qed_device_get_port_id(struct qed_dev *cdev); 792fe56b9e6SYuval Mintz 793b5a9ee7cSAriel Elior #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) 794b5a9ee7cSAriel Elior 795b5a9ee7cSAriel Elior /* Flags for indication of required queues */ 796b5a9ee7cSAriel Elior #define PQ_FLAGS_RLS (BIT(0)) 797b5a9ee7cSAriel Elior #define PQ_FLAGS_MCOS (BIT(1)) 798b5a9ee7cSAriel Elior #define PQ_FLAGS_LB (BIT(2)) 799b5a9ee7cSAriel Elior #define PQ_FLAGS_OOO (BIT(3)) 800b5a9ee7cSAriel Elior #define PQ_FLAGS_ACK (BIT(4)) 801b5a9ee7cSAriel Elior #define PQ_FLAGS_OFLD (BIT(5)) 802b5a9ee7cSAriel Elior #define PQ_FLAGS_VFS (BIT(6)) 803b5a9ee7cSAriel Elior #define PQ_FLAGS_LLT (BIT(7)) 804b5a9ee7cSAriel Elior 805b5a9ee7cSAriel Elior /* physical queue index for cm context intialization */ 806b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx(struct qed_hwfn *p_hwfn, u32 pq_flags); 807b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx_mcos(struct qed_hwfn *p_hwfn, u8 tc); 808b5a9ee7cSAriel Elior u16 qed_get_cm_pq_idx_vf(struct qed_hwfn *p_hwfn, u16 vf); 809b5a9ee7cSAriel Elior 810b5a9ee7cSAriel Elior #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) 811b5a9ee7cSAriel Elior 812fe56b9e6SYuval Mintz /* Other Linux specific common definitions */ 813fe56b9e6SYuval Mintz #define DP_NAME(cdev) ((cdev)->name) 814fe56b9e6SYuval Mintz 815fe56b9e6SYuval Mintz #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\ 816fe56b9e6SYuval Mintz (cdev->regview) + \ 817fe56b9e6SYuval Mintz (offset)) 818fe56b9e6SYuval Mintz 819fe56b9e6SYuval Mintz #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset)) 820fe56b9e6SYuval Mintz #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset)) 821fe56b9e6SYuval Mintz #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset)) 822fe56b9e6SYuval Mintz 823fe56b9e6SYuval Mintz #define DOORBELL(cdev, db_addr, val) \ 824fe56b9e6SYuval Mintz writel((u32)val, (void __iomem *)((u8 __iomem *)\ 825fe56b9e6SYuval Mintz (cdev->doorbells) + (db_addr))) 826fe56b9e6SYuval Mintz 827fe56b9e6SYuval Mintz /* Prototypes */ 828fe56b9e6SYuval Mintz int qed_fill_dev_info(struct qed_dev *cdev, 829fe56b9e6SYuval Mintz struct qed_dev_info *dev_info); 830cc875c2eSYuval Mintz void qed_link_update(struct qed_hwfn *hwfn); 831fe56b9e6SYuval Mintz u32 qed_unzip_data(struct qed_hwfn *p_hwfn, 832fe56b9e6SYuval Mintz u32 input_len, u8 *input_buf, 833fe56b9e6SYuval Mintz u32 max_size, u8 *unzip_buf); 8346c754246SSudarsana Reddy Kalluru void qed_get_protocol_stats(struct qed_dev *cdev, 8356c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type type, 8366c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats *stats); 8378f16bc97SSudarsana Kalluru int qed_slowpath_irq_req(struct qed_hwfn *hwfn); 8381226337aSTomer Tayar void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn); 8398f16bc97SSudarsana Kalluru 840fe56b9e6SYuval Mintz #endif /* _QED_H */ 841