1fe56b9e6SYuval Mintz /* QLogic qed NIC Driver 2e8f1cb50SMintz, Yuval * Copyright (c) 2015-2017 QLogic Corporation 3fe56b9e6SYuval Mintz * 4e8f1cb50SMintz, Yuval * This software is available to you under a choice of one of two 5e8f1cb50SMintz, Yuval * licenses. You may choose to be licensed under the terms of the GNU 6e8f1cb50SMintz, Yuval * General Public License (GPL) Version 2, available from the file 7e8f1cb50SMintz, Yuval * COPYING in the main directory of this source tree, or the 8e8f1cb50SMintz, Yuval * OpenIB.org BSD license below: 9e8f1cb50SMintz, Yuval * 10e8f1cb50SMintz, Yuval * Redistribution and use in source and binary forms, with or 11e8f1cb50SMintz, Yuval * without modification, are permitted provided that the following 12e8f1cb50SMintz, Yuval * conditions are met: 13e8f1cb50SMintz, Yuval * 14e8f1cb50SMintz, Yuval * - Redistributions of source code must retain the above 15e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 16e8f1cb50SMintz, Yuval * disclaimer. 17e8f1cb50SMintz, Yuval * 18e8f1cb50SMintz, Yuval * - Redistributions in binary form must reproduce the above 19e8f1cb50SMintz, Yuval * copyright notice, this list of conditions and the following 20e8f1cb50SMintz, Yuval * disclaimer in the documentation and /or other materials 21e8f1cb50SMintz, Yuval * provided with the distribution. 22e8f1cb50SMintz, Yuval * 23e8f1cb50SMintz, Yuval * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24e8f1cb50SMintz, Yuval * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25e8f1cb50SMintz, Yuval * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26e8f1cb50SMintz, Yuval * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27e8f1cb50SMintz, Yuval * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28e8f1cb50SMintz, Yuval * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29e8f1cb50SMintz, Yuval * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30e8f1cb50SMintz, Yuval * SOFTWARE. 31fe56b9e6SYuval Mintz */ 32fe56b9e6SYuval Mintz 33fe56b9e6SYuval Mintz #ifndef _QED_H 34fe56b9e6SYuval Mintz #define _QED_H 35fe56b9e6SYuval Mintz 36fe56b9e6SYuval Mintz #include <linux/types.h> 37fe56b9e6SYuval Mintz #include <linux/io.h> 38fe56b9e6SYuval Mintz #include <linux/delay.h> 39fe56b9e6SYuval Mintz #include <linux/firmware.h> 40fe56b9e6SYuval Mintz #include <linux/interrupt.h> 41fe56b9e6SYuval Mintz #include <linux/list.h> 42fe56b9e6SYuval Mintz #include <linux/mutex.h> 43fe56b9e6SYuval Mintz #include <linux/pci.h> 44fe56b9e6SYuval Mintz #include <linux/slab.h> 45fe56b9e6SYuval Mintz #include <linux/string.h> 46fe56b9e6SYuval Mintz #include <linux/workqueue.h> 47fe56b9e6SYuval Mintz #include <linux/zlib.h> 48fe56b9e6SYuval Mintz #include <linux/hashtable.h> 49fe56b9e6SYuval Mintz #include <linux/qed/qed_if.h> 50c965db44STomer Tayar #include "qed_debug.h" 51fe56b9e6SYuval Mintz #include "qed_hsi.h" 52fe56b9e6SYuval Mintz 5325c089d7SYuval Mintz extern const struct qed_common_ops qed_common_ops_pass; 545d24bcf1STomer Tayar 555d24bcf1STomer Tayar #define QED_MAJOR_VERSION 8 565d24bcf1STomer Tayar #define QED_MINOR_VERSION 10 575d24bcf1STomer Tayar #define QED_REVISION_VERSION 10 585d24bcf1STomer Tayar #define QED_ENGINEERING_VERSION 21 595d24bcf1STomer Tayar 605d24bcf1STomer Tayar #define QED_VERSION \ 615d24bcf1STomer Tayar ((QED_MAJOR_VERSION << 24) | (QED_MINOR_VERSION << 16) | \ 625d24bcf1STomer Tayar (QED_REVISION_VERSION << 8) | QED_ENGINEERING_VERSION) 635d24bcf1STomer Tayar 645d24bcf1STomer Tayar #define STORM_FW_VERSION \ 655d24bcf1STomer Tayar ((FW_MAJOR_VERSION << 24) | (FW_MINOR_VERSION << 16) | \ 665d24bcf1STomer Tayar (FW_REVISION_VERSION << 8) | FW_ENGINEERING_VERSION) 67fe56b9e6SYuval Mintz 68fe56b9e6SYuval Mintz #define MAX_HWFNS_PER_DEVICE (4) 69fe56b9e6SYuval Mintz #define NAME_SIZE 16 70fe56b9e6SYuval Mintz #define VER_SIZE 16 71fe56b9e6SYuval Mintz 72bcd197c8SManish Chopra #define QED_WFQ_UNIT 100 73bcd197c8SManish Chopra 74fc831825SYuval Mintz #define ISCSI_BDQ_ID(_port_id) (_port_id) 751e128c81SArun Easi #define FCOE_BDQ_ID(_port_id) ((_port_id) + 2) 7651ff1725SRam Amrani #define QED_WID_SIZE (1024) 7751ff1725SRam Amrani #define QED_PF_DEMS_SIZE (4) 7851ff1725SRam Amrani 79fe56b9e6SYuval Mintz /* cau states */ 80fe56b9e6SYuval Mintz enum qed_coalescing_mode { 81fe56b9e6SYuval Mintz QED_COAL_MODE_DISABLE, 82fe56b9e6SYuval Mintz QED_COAL_MODE_ENABLE 83fe56b9e6SYuval Mintz }; 84fe56b9e6SYuval Mintz 85fe56b9e6SYuval Mintz struct qed_eth_cb_ops; 86fe56b9e6SYuval Mintz struct qed_dev_info; 876c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats; 886c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type; 89fe56b9e6SYuval Mintz 90fe56b9e6SYuval Mintz /* helpers */ 915d24bcf1STomer Tayar #define QED_MFW_GET_FIELD(name, field) \ 925d24bcf1STomer Tayar (((name) & (field ## _MASK)) >> (field ## _SHIFT)) 935d24bcf1STomer Tayar 945d24bcf1STomer Tayar #define QED_MFW_SET_FIELD(name, field, value) \ 955d24bcf1STomer Tayar do { \ 965d24bcf1STomer Tayar (name) &= ~((field ## _MASK) << (field ## _SHIFT)); \ 975d24bcf1STomer Tayar (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\ 985d24bcf1STomer Tayar } while (0) 995d24bcf1STomer Tayar 100fe56b9e6SYuval Mintz static inline u32 qed_db_addr(u32 cid, u32 DEMS) 101fe56b9e6SYuval Mintz { 102fe56b9e6SYuval Mintz u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 10351ff1725SRam Amrani (cid * QED_PF_DEMS_SIZE); 10451ff1725SRam Amrani 10551ff1725SRam Amrani return db_addr; 10651ff1725SRam Amrani } 10751ff1725SRam Amrani 10851ff1725SRam Amrani static inline u32 qed_db_addr_vf(u32 cid, u32 DEMS) 10951ff1725SRam Amrani { 11051ff1725SRam Amrani u32 db_addr = FIELD_VALUE(DB_LEGACY_ADDR_DEMS, DEMS) | 111fe56b9e6SYuval Mintz FIELD_VALUE(DB_LEGACY_ADDR_ICID, cid); 112fe56b9e6SYuval Mintz 113fe56b9e6SYuval Mintz return db_addr; 114fe56b9e6SYuval Mintz } 115fe56b9e6SYuval Mintz 116fe56b9e6SYuval Mintz #define ALIGNED_TYPE_SIZE(type_name, p_hwfn) \ 117fe56b9e6SYuval Mintz ((sizeof(type_name) + (u32)(1 << (p_hwfn->cdev->cache_shift)) - 1) & \ 118fe56b9e6SYuval Mintz ~((1 << (p_hwfn->cdev->cache_shift)) - 1)) 119fe56b9e6SYuval Mintz 120fe56b9e6SYuval Mintz #define for_each_hwfn(cdev, i) for (i = 0; i < cdev->num_hwfns; i++) 121fe56b9e6SYuval Mintz 122fe56b9e6SYuval Mintz #define D_TRINE(val, cond1, cond2, true1, true2, def) \ 123fe56b9e6SYuval Mintz (val == (cond1) ? true1 : \ 124fe56b9e6SYuval Mintz (val == (cond2) ? true2 : def)) 125fe56b9e6SYuval Mintz 126fe56b9e6SYuval Mintz /* forward */ 127fe56b9e6SYuval Mintz struct qed_ptt_pool; 128fe56b9e6SYuval Mintz struct qed_spq; 129fe56b9e6SYuval Mintz struct qed_sb_info; 130fe56b9e6SYuval Mintz struct qed_sb_attn_info; 131fe56b9e6SYuval Mintz struct qed_cxt_mngr; 132fe56b9e6SYuval Mintz struct qed_sb_sp_info; 1330a7fb11cSYuval Mintz struct qed_ll2_info; 134fe56b9e6SYuval Mintz struct qed_mcp_info; 135fe56b9e6SYuval Mintz 136fe56b9e6SYuval Mintz struct qed_rt_data { 137fc48b7a6SYuval Mintz u32 *init_val; 138fc48b7a6SYuval Mintz bool *b_valid; 139fe56b9e6SYuval Mintz }; 140fe56b9e6SYuval Mintz 141464f6645SManish Chopra enum qed_tunn_mode { 142464f6645SManish Chopra QED_MODE_L2GENEVE_TUNN, 143464f6645SManish Chopra QED_MODE_IPGENEVE_TUNN, 144464f6645SManish Chopra QED_MODE_L2GRE_TUNN, 145464f6645SManish Chopra QED_MODE_IPGRE_TUNN, 146464f6645SManish Chopra QED_MODE_VXLAN_TUNN, 147464f6645SManish Chopra }; 148464f6645SManish Chopra 149464f6645SManish Chopra enum qed_tunn_clss { 150464f6645SManish Chopra QED_TUNN_CLSS_MAC_VLAN, 151464f6645SManish Chopra QED_TUNN_CLSS_MAC_VNI, 152464f6645SManish Chopra QED_TUNN_CLSS_INNER_MAC_VLAN, 153464f6645SManish Chopra QED_TUNN_CLSS_INNER_MAC_VNI, 154464f6645SManish Chopra MAX_QED_TUNN_CLSS, 155464f6645SManish Chopra }; 156464f6645SManish Chopra 157464f6645SManish Chopra struct qed_tunn_start_params { 158464f6645SManish Chopra unsigned long tunn_mode; 159464f6645SManish Chopra u16 vxlan_udp_port; 160464f6645SManish Chopra u16 geneve_udp_port; 161464f6645SManish Chopra u8 update_vxlan_udp_port; 162464f6645SManish Chopra u8 update_geneve_udp_port; 163464f6645SManish Chopra u8 tunn_clss_vxlan; 164464f6645SManish Chopra u8 tunn_clss_l2geneve; 165464f6645SManish Chopra u8 tunn_clss_ipgeneve; 166464f6645SManish Chopra u8 tunn_clss_l2gre; 167464f6645SManish Chopra u8 tunn_clss_ipgre; 168464f6645SManish Chopra }; 169464f6645SManish Chopra 170464f6645SManish Chopra struct qed_tunn_update_params { 171464f6645SManish Chopra unsigned long tunn_mode_update_mask; 172464f6645SManish Chopra unsigned long tunn_mode; 173464f6645SManish Chopra u16 vxlan_udp_port; 174464f6645SManish Chopra u16 geneve_udp_port; 175464f6645SManish Chopra u8 update_rx_pf_clss; 176464f6645SManish Chopra u8 update_tx_pf_clss; 177464f6645SManish Chopra u8 update_vxlan_udp_port; 178464f6645SManish Chopra u8 update_geneve_udp_port; 179464f6645SManish Chopra u8 tunn_clss_vxlan; 180464f6645SManish Chopra u8 tunn_clss_l2geneve; 181464f6645SManish Chopra u8 tunn_clss_ipgeneve; 182464f6645SManish Chopra u8 tunn_clss_l2gre; 183464f6645SManish Chopra u8 tunn_clss_ipgre; 184464f6645SManish Chopra }; 185464f6645SManish Chopra 186fe56b9e6SYuval Mintz /* The PCI personality is not quite synonymous to protocol ID: 187fe56b9e6SYuval Mintz * 1. All personalities need CORE connections 188fe56b9e6SYuval Mintz * 2. The Ethernet personality may support also the RoCE protocol 189fe56b9e6SYuval Mintz */ 190fe56b9e6SYuval Mintz enum qed_pci_personality { 191fe56b9e6SYuval Mintz QED_PCI_ETH, 1921e128c81SArun Easi QED_PCI_FCOE, 193c5ac9319SYuval Mintz QED_PCI_ISCSI, 194c5ac9319SYuval Mintz QED_PCI_ETH_ROCE, 195fe56b9e6SYuval Mintz QED_PCI_DEFAULT /* default in shmem */ 196fe56b9e6SYuval Mintz }; 197fe56b9e6SYuval Mintz 198fe56b9e6SYuval Mintz /* All VFs are symmetric, all counters are PF + all VFs */ 199fe56b9e6SYuval Mintz struct qed_qm_iids { 200fe56b9e6SYuval Mintz u32 cids; 201fe56b9e6SYuval Mintz u32 vf_cids; 202fe56b9e6SYuval Mintz u32 tids; 203fe56b9e6SYuval Mintz }; 204fe56b9e6SYuval Mintz 2052edbff8dSTomer Tayar /* HW / FW resources, output of features supported below, most information 2062edbff8dSTomer Tayar * is received from MFW. 2072edbff8dSTomer Tayar */ 2082edbff8dSTomer Tayar enum qed_resources { 209fe56b9e6SYuval Mintz QED_SB, 21025c089d7SYuval Mintz QED_L2_QUEUE, 211fe56b9e6SYuval Mintz QED_VPORT, 21225c089d7SYuval Mintz QED_RSS_ENG, 213fe56b9e6SYuval Mintz QED_PQ, 214fe56b9e6SYuval Mintz QED_RL, 21525c089d7SYuval Mintz QED_MAC, 21625c089d7SYuval Mintz QED_VLAN, 21751ff1725SRam Amrani QED_RDMA_CNQ_RAM, 218fe56b9e6SYuval Mintz QED_ILT, 2190a7fb11cSYuval Mintz QED_LL2_QUEUE, 2202edbff8dSTomer Tayar QED_CMDQS_CQS, 22151ff1725SRam Amrani QED_RDMA_STATS_QUEUE, 2229c8517c4STomer Tayar QED_BDQ, 223fe56b9e6SYuval Mintz QED_MAX_RESC, 224fe56b9e6SYuval Mintz }; 225fe56b9e6SYuval Mintz 22625c089d7SYuval Mintz enum QED_FEATURE { 22725c089d7SYuval Mintz QED_PF_L2_QUE, 22832a47e72SYuval Mintz QED_VF, 22951ff1725SRam Amrani QED_RDMA_CNQ, 2305a1f965aSMintz, Yuval QED_VF_L2_QUE, 2311e128c81SArun Easi QED_FCOE_CQ, 23225c089d7SYuval Mintz QED_MAX_FEATURES, 23325c089d7SYuval Mintz }; 23425c089d7SYuval Mintz 235cc875c2eSYuval Mintz enum QED_PORT_MODE { 236cc875c2eSYuval Mintz QED_PORT_MODE_DE_2X40G, 237cc875c2eSYuval Mintz QED_PORT_MODE_DE_2X50G, 238cc875c2eSYuval Mintz QED_PORT_MODE_DE_1X100G, 239cc875c2eSYuval Mintz QED_PORT_MODE_DE_4X10G_F, 240cc875c2eSYuval Mintz QED_PORT_MODE_DE_4X10G_E, 241cc875c2eSYuval Mintz QED_PORT_MODE_DE_4X20G, 242cc875c2eSYuval Mintz QED_PORT_MODE_DE_1X40G, 243cc875c2eSYuval Mintz QED_PORT_MODE_DE_2X25G, 2449c79ddaaSMintz, Yuval QED_PORT_MODE_DE_1X25G, 2459c79ddaaSMintz, Yuval QED_PORT_MODE_DE_4X25G, 2469c79ddaaSMintz, Yuval QED_PORT_MODE_DE_2X10G, 247cc875c2eSYuval Mintz }; 248cc875c2eSYuval Mintz 249fc48b7a6SYuval Mintz enum qed_dev_cap { 250fc48b7a6SYuval Mintz QED_DEV_CAP_ETH, 2511e128c81SArun Easi QED_DEV_CAP_FCOE, 252c5ac9319SYuval Mintz QED_DEV_CAP_ISCSI, 253c5ac9319SYuval Mintz QED_DEV_CAP_ROCE, 254fc48b7a6SYuval Mintz }; 255fc48b7a6SYuval Mintz 25614d39648SMintz, Yuval enum qed_wol_support { 25714d39648SMintz, Yuval QED_WOL_SUPPORT_NONE, 25814d39648SMintz, Yuval QED_WOL_SUPPORT_PME, 25914d39648SMintz, Yuval }; 26014d39648SMintz, Yuval 261fe56b9e6SYuval Mintz struct qed_hw_info { 262fe56b9e6SYuval Mintz /* PCI personality */ 263fe56b9e6SYuval Mintz enum qed_pci_personality personality; 264fe56b9e6SYuval Mintz 265fe56b9e6SYuval Mintz /* Resource Allocation scheme results */ 266fe56b9e6SYuval Mintz u32 resc_start[QED_MAX_RESC]; 267fe56b9e6SYuval Mintz u32 resc_num[QED_MAX_RESC]; 26825c089d7SYuval Mintz u32 feat_num[QED_MAX_FEATURES]; 269fe56b9e6SYuval Mintz 270fe56b9e6SYuval Mintz #define RESC_START(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_start[resc]) 271fe56b9e6SYuval Mintz #define RESC_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.resc_num[resc]) 272dbb799c3SYuval Mintz #define RESC_END(_p_hwfn, resc) (RESC_START(_p_hwfn, resc) + \ 273dbb799c3SYuval Mintz RESC_NUM(_p_hwfn, resc)) 274fe56b9e6SYuval Mintz #define FEAT_NUM(_p_hwfn, resc) ((_p_hwfn)->hw_info.feat_num[resc]) 275fe56b9e6SYuval Mintz 276fe56b9e6SYuval Mintz u8 num_tc; 277fe56b9e6SYuval Mintz u8 offload_tc; 278fe56b9e6SYuval Mintz u8 non_offload_tc; 279fe56b9e6SYuval Mintz 280fe56b9e6SYuval Mintz u32 concrete_fid; 281fe56b9e6SYuval Mintz u16 opaque_fid; 282fe56b9e6SYuval Mintz u16 ovlan; 283fe56b9e6SYuval Mintz u32 part_num[4]; 284fe56b9e6SYuval Mintz 285fe56b9e6SYuval Mintz unsigned char hw_mac_addr[ETH_ALEN]; 2861e128c81SArun Easi u64 node_wwn; 2871e128c81SArun Easi u64 port_wwn; 2881e128c81SArun Easi 2891e128c81SArun Easi u16 num_fcoe_conns; 290fe56b9e6SYuval Mintz 291fe56b9e6SYuval Mintz struct qed_igu_info *p_igu_info; 292fe56b9e6SYuval Mintz 293fe56b9e6SYuval Mintz u32 port_mode; 294fe56b9e6SYuval Mintz u32 hw_mode; 295fc48b7a6SYuval Mintz unsigned long device_capabilities; 2960fefbfbaSSudarsana Kalluru u16 mtu; 29714d39648SMintz, Yuval 29814d39648SMintz, Yuval enum qed_wol_support b_wol_support; 299fe56b9e6SYuval Mintz }; 300fe56b9e6SYuval Mintz 301fe56b9e6SYuval Mintz /* maximun size of read/write commands (HW limit) */ 302fe56b9e6SYuval Mintz #define DMAE_MAX_RW_SIZE 0x2000 303fe56b9e6SYuval Mintz 304fe56b9e6SYuval Mintz struct qed_dmae_info { 305fe56b9e6SYuval Mintz /* Mutex for synchronizing access to functions */ 306fe56b9e6SYuval Mintz struct mutex mutex; 307fe56b9e6SYuval Mintz 308fe56b9e6SYuval Mintz u8 channel; 309fe56b9e6SYuval Mintz 310fe56b9e6SYuval Mintz dma_addr_t completion_word_phys_addr; 311fe56b9e6SYuval Mintz 312fe56b9e6SYuval Mintz /* The memory location where the DMAE writes the completion 313fe56b9e6SYuval Mintz * value when an operation is finished on this context. 314fe56b9e6SYuval Mintz */ 315fe56b9e6SYuval Mintz u32 *p_completion_word; 316fe56b9e6SYuval Mintz 317fe56b9e6SYuval Mintz dma_addr_t intermediate_buffer_phys_addr; 318fe56b9e6SYuval Mintz 319fe56b9e6SYuval Mintz /* An intermediate buffer for DMAE operations that use virtual 320fe56b9e6SYuval Mintz * addresses - data is DMA'd to/from this buffer and then 321fe56b9e6SYuval Mintz * memcpy'd to/from the virtual address 322fe56b9e6SYuval Mintz */ 323fe56b9e6SYuval Mintz u32 *p_intermediate_buffer; 324fe56b9e6SYuval Mintz 325fe56b9e6SYuval Mintz dma_addr_t dmae_cmd_phys_addr; 326fe56b9e6SYuval Mintz struct dmae_cmd *p_dmae_cmd; 327fe56b9e6SYuval Mintz }; 328fe56b9e6SYuval Mintz 329bcd197c8SManish Chopra struct qed_wfq_data { 330bcd197c8SManish Chopra /* when feature is configured for at least 1 vport */ 331bcd197c8SManish Chopra u32 min_speed; 332bcd197c8SManish Chopra bool configured; 333bcd197c8SManish Chopra }; 334bcd197c8SManish Chopra 335fe56b9e6SYuval Mintz struct qed_qm_info { 336fe56b9e6SYuval Mintz struct init_qm_pq_params *qm_pq_params; 337fe56b9e6SYuval Mintz struct init_qm_vport_params *qm_vport_params; 338fe56b9e6SYuval Mintz struct init_qm_port_params *qm_port_params; 339fe56b9e6SYuval Mintz u16 start_pq; 340fe56b9e6SYuval Mintz u8 start_vport; 341fe56b9e6SYuval Mintz u8 pure_lb_pq; 342fe56b9e6SYuval Mintz u8 offload_pq; 343fe56b9e6SYuval Mintz u8 pure_ack_pq; 344dbb799c3SYuval Mintz u8 ooo_pq; 345fe56b9e6SYuval Mintz u8 vf_queues_offset; 346fe56b9e6SYuval Mintz u16 num_pqs; 347fe56b9e6SYuval Mintz u16 num_vf_pqs; 348fe56b9e6SYuval Mintz u8 num_vports; 349fe56b9e6SYuval Mintz u8 max_phys_tcs_per_port; 350fe56b9e6SYuval Mintz bool pf_rl_en; 351fe56b9e6SYuval Mintz bool pf_wfq_en; 352fe56b9e6SYuval Mintz bool vport_rl_en; 353fe56b9e6SYuval Mintz bool vport_wfq_en; 354fe56b9e6SYuval Mintz u8 pf_wfq; 355fe56b9e6SYuval Mintz u32 pf_rl; 356bcd197c8SManish Chopra struct qed_wfq_data *wfq_data; 357dbb799c3SYuval Mintz u8 num_pf_rls; 358fe56b9e6SYuval Mintz }; 359fe56b9e6SYuval Mintz 3609df2ed04SManish Chopra struct storm_stats { 3619df2ed04SManish Chopra u32 address; 3629df2ed04SManish Chopra u32 len; 3639df2ed04SManish Chopra }; 3649df2ed04SManish Chopra 3659df2ed04SManish Chopra struct qed_storm_stats { 3669df2ed04SManish Chopra struct storm_stats mstats; 3679df2ed04SManish Chopra struct storm_stats pstats; 3689df2ed04SManish Chopra struct storm_stats tstats; 3699df2ed04SManish Chopra struct storm_stats ustats; 3709df2ed04SManish Chopra }; 3719df2ed04SManish Chopra 372fe56b9e6SYuval Mintz struct qed_fw_data { 3739df2ed04SManish Chopra struct fw_ver_info *fw_ver_info; 374fe56b9e6SYuval Mintz const u8 *modes_tree_buf; 375fe56b9e6SYuval Mintz union init_op *init_ops; 376fe56b9e6SYuval Mintz const u32 *arr_data; 377fe56b9e6SYuval Mintz u32 init_ops_size; 378fe56b9e6SYuval Mintz }; 379fe56b9e6SYuval Mintz 3805d24bcf1STomer Tayar #define DRV_MODULE_VERSION \ 3815d24bcf1STomer Tayar __stringify(QED_MAJOR_VERSION) "." \ 3825d24bcf1STomer Tayar __stringify(QED_MINOR_VERSION) "." \ 3835d24bcf1STomer Tayar __stringify(QED_REVISION_VERSION) "." \ 3845d24bcf1STomer Tayar __stringify(QED_ENGINEERING_VERSION) 3855d24bcf1STomer Tayar 386fe56b9e6SYuval Mintz struct qed_simd_fp_handler { 387fe56b9e6SYuval Mintz void *token; 388fe56b9e6SYuval Mintz void (*func)(void *); 389fe56b9e6SYuval Mintz }; 390fe56b9e6SYuval Mintz 391fe56b9e6SYuval Mintz struct qed_hwfn { 392fe56b9e6SYuval Mintz struct qed_dev *cdev; 393fe56b9e6SYuval Mintz u8 my_id; /* ID inside the PF */ 394fe56b9e6SYuval Mintz #define IS_LEAD_HWFN(edev) (!((edev)->my_id)) 395fe56b9e6SYuval Mintz u8 rel_pf_id; /* Relative to engine*/ 396fe56b9e6SYuval Mintz u8 abs_pf_id; 3979c79ddaaSMintz, Yuval #define QED_PATH_ID(_p_hwfn) \ 3989c79ddaaSMintz, Yuval (QED_IS_K2((_p_hwfn)->cdev) ? 0 : ((_p_hwfn)->abs_pf_id & 1)) 399fe56b9e6SYuval Mintz u8 port_id; 400fe56b9e6SYuval Mintz bool b_active; 401fe56b9e6SYuval Mintz 402fe56b9e6SYuval Mintz u32 dp_module; 403fe56b9e6SYuval Mintz u8 dp_level; 404fe56b9e6SYuval Mintz char name[NAME_SIZE]; 405fe56b9e6SYuval Mintz 406fe56b9e6SYuval Mintz bool first_on_engine; 407fe56b9e6SYuval Mintz bool hw_init_done; 408fe56b9e6SYuval Mintz 4091408cc1fSYuval Mintz u8 num_funcs_on_engine; 410dbb799c3SYuval Mintz u8 enabled_func_idx; 4111408cc1fSYuval Mintz 412fe56b9e6SYuval Mintz /* BAR access */ 413fe56b9e6SYuval Mintz void __iomem *regview; 414fe56b9e6SYuval Mintz void __iomem *doorbells; 415fe56b9e6SYuval Mintz u64 db_phys_addr; 416fe56b9e6SYuval Mintz unsigned long db_size; 417fe56b9e6SYuval Mintz 418fe56b9e6SYuval Mintz /* PTT pool */ 419fe56b9e6SYuval Mintz struct qed_ptt_pool *p_ptt_pool; 420fe56b9e6SYuval Mintz 421fe56b9e6SYuval Mintz /* HW info */ 422fe56b9e6SYuval Mintz struct qed_hw_info hw_info; 423fe56b9e6SYuval Mintz 424fe56b9e6SYuval Mintz /* rt_array (for init-tool) */ 425fc48b7a6SYuval Mintz struct qed_rt_data rt_data; 426fe56b9e6SYuval Mintz 427fe56b9e6SYuval Mintz /* SPQ */ 428fe56b9e6SYuval Mintz struct qed_spq *p_spq; 429fe56b9e6SYuval Mintz 430fe56b9e6SYuval Mintz /* EQ */ 431fe56b9e6SYuval Mintz struct qed_eq *p_eq; 432fe56b9e6SYuval Mintz 433fe56b9e6SYuval Mintz /* Consolidate Q*/ 434fe56b9e6SYuval Mintz struct qed_consq *p_consq; 435fe56b9e6SYuval Mintz 436fe56b9e6SYuval Mintz /* Slow-Path definitions */ 437fe56b9e6SYuval Mintz struct tasklet_struct *sp_dpc; 438fe56b9e6SYuval Mintz bool b_sp_dpc_enabled; 439fe56b9e6SYuval Mintz 440fe56b9e6SYuval Mintz struct qed_ptt *p_main_ptt; 441fe56b9e6SYuval Mintz struct qed_ptt *p_dpc_ptt; 442fe56b9e6SYuval Mintz 443fe56b9e6SYuval Mintz struct qed_sb_sp_info *p_sp_sb; 444fe56b9e6SYuval Mintz struct qed_sb_attn_info *p_sb_attn; 445fe56b9e6SYuval Mintz 446fe56b9e6SYuval Mintz /* Protocol related */ 4470a7fb11cSYuval Mintz bool using_ll2; 4480a7fb11cSYuval Mintz struct qed_ll2_info *p_ll2_info; 4491d6cff4fSYuval Mintz struct qed_ooo_info *p_ooo_info; 45051ff1725SRam Amrani struct qed_rdma_info *p_rdma_info; 451fc831825SYuval Mintz struct qed_iscsi_info *p_iscsi_info; 4521e128c81SArun Easi struct qed_fcoe_info *p_fcoe_info; 453fe56b9e6SYuval Mintz struct qed_pf_params pf_params; 454fe56b9e6SYuval Mintz 455dbb799c3SYuval Mintz bool b_rdma_enabled_in_prs; 456dbb799c3SYuval Mintz u32 rdma_prs_search_reg; 457dbb799c3SYuval Mintz 458fe56b9e6SYuval Mintz /* Array of sb_info of all status blocks */ 459fe56b9e6SYuval Mintz struct qed_sb_info *sbs_info[MAX_SB_PER_PF_MIMD]; 460fe56b9e6SYuval Mintz u16 num_sbs; 461fe56b9e6SYuval Mintz 462fe56b9e6SYuval Mintz struct qed_cxt_mngr *p_cxt_mngr; 463fe56b9e6SYuval Mintz 464fe56b9e6SYuval Mintz /* Flag indicating whether interrupts are enabled or not*/ 465fe56b9e6SYuval Mintz bool b_int_enabled; 4668f16bc97SSudarsana Kalluru bool b_int_requested; 467fe56b9e6SYuval Mintz 468fc916ff2SSudarsana Reddy Kalluru /* True if the driver requests for the link */ 469fc916ff2SSudarsana Reddy Kalluru bool b_drv_link_init; 470fc916ff2SSudarsana Reddy Kalluru 4711408cc1fSYuval Mintz struct qed_vf_iov *vf_iov_info; 47232a47e72SYuval Mintz struct qed_pf_iov *pf_iov_info; 473fe56b9e6SYuval Mintz struct qed_mcp_info *mcp_info; 474fe56b9e6SYuval Mintz 47539651abdSSudarsana Reddy Kalluru struct qed_dcbx_info *p_dcbx_info; 47639651abdSSudarsana Reddy Kalluru 477fe56b9e6SYuval Mintz struct qed_dmae_info dmae_info; 478fe56b9e6SYuval Mintz 479fe56b9e6SYuval Mintz /* QM init */ 480fe56b9e6SYuval Mintz struct qed_qm_info qm_info; 4819df2ed04SManish Chopra struct qed_storm_stats storm_stats; 482fe56b9e6SYuval Mintz 483fe56b9e6SYuval Mintz /* Buffer for unzipping firmware data */ 484fe56b9e6SYuval Mintz void *unzip_buf; 485fe56b9e6SYuval Mintz 486c965db44STomer Tayar struct dbg_tools_data dbg_info; 487c965db44STomer Tayar 48851ff1725SRam Amrani /* PWM region specific data */ 48951ff1725SRam Amrani u32 dpi_size; 49051ff1725SRam Amrani u32 dpi_count; 49151ff1725SRam Amrani 49251ff1725SRam Amrani /* This is used to calculate the doorbell address */ 49351ff1725SRam Amrani u32 dpi_start_offset; 49451ff1725SRam Amrani 49551ff1725SRam Amrani /* If one of the following is set then EDPM shouldn't be used */ 49651ff1725SRam Amrani u8 dcbx_no_edpm; 49751ff1725SRam Amrani u8 db_bar_no_edpm; 49851ff1725SRam Amrani 499c78c70faSSudarsana Reddy Kalluru /* p_ptp_ptt is valid for leading HWFN only */ 500c78c70faSSudarsana Reddy Kalluru struct qed_ptt *p_ptp_ptt; 501fe56b9e6SYuval Mintz struct qed_simd_fp_handler simd_proto_handler[64]; 502fe56b9e6SYuval Mintz 50337bff2b9SYuval Mintz #ifdef CONFIG_QED_SRIOV 50437bff2b9SYuval Mintz struct workqueue_struct *iov_wq; 50537bff2b9SYuval Mintz struct delayed_work iov_task; 50637bff2b9SYuval Mintz unsigned long iov_task_flags; 50737bff2b9SYuval Mintz #endif 50837bff2b9SYuval Mintz 509fe56b9e6SYuval Mintz struct z_stream_s *stream; 510abd49676SRam Amrani struct qed_roce_ll2_info *ll2; 511fe56b9e6SYuval Mintz }; 512fe56b9e6SYuval Mintz 513fe56b9e6SYuval Mintz struct pci_params { 514fe56b9e6SYuval Mintz int pm_cap; 515fe56b9e6SYuval Mintz 516fe56b9e6SYuval Mintz unsigned long mem_start; 517fe56b9e6SYuval Mintz unsigned long mem_end; 518fe56b9e6SYuval Mintz unsigned int irq; 519fe56b9e6SYuval Mintz u8 pf_num; 520fe56b9e6SYuval Mintz }; 521fe56b9e6SYuval Mintz 522fe56b9e6SYuval Mintz struct qed_int_param { 523fe56b9e6SYuval Mintz u32 int_mode; 524fe56b9e6SYuval Mintz u8 num_vectors; 525fe56b9e6SYuval Mintz u8 min_msix_cnt; /* for minimal functionality */ 526fe56b9e6SYuval Mintz }; 527fe56b9e6SYuval Mintz 528fe56b9e6SYuval Mintz struct qed_int_params { 529fe56b9e6SYuval Mintz struct qed_int_param in; 530fe56b9e6SYuval Mintz struct qed_int_param out; 531fe56b9e6SYuval Mintz struct msix_entry *msix_table; 532fe56b9e6SYuval Mintz bool fp_initialized; 533fe56b9e6SYuval Mintz u8 fp_msix_base; 534fe56b9e6SYuval Mintz u8 fp_msix_cnt; 53551ff1725SRam Amrani u8 rdma_msix_base; 53651ff1725SRam Amrani u8 rdma_msix_cnt; 537fe56b9e6SYuval Mintz }; 538fe56b9e6SYuval Mintz 539c965db44STomer Tayar struct qed_dbg_feature { 540c965db44STomer Tayar struct dentry *dentry; 541c965db44STomer Tayar u8 *dump_buf; 542c965db44STomer Tayar u32 buf_size; 543c965db44STomer Tayar u32 dumped_dwords; 544c965db44STomer Tayar }; 545c965db44STomer Tayar 546c965db44STomer Tayar struct qed_dbg_params { 547c965db44STomer Tayar struct qed_dbg_feature features[DBG_FEATURE_NUM]; 548c965db44STomer Tayar u8 engine_for_debug; 549c965db44STomer Tayar bool print_data; 550c965db44STomer Tayar }; 551c965db44STomer Tayar 552fe56b9e6SYuval Mintz struct qed_dev { 553fe56b9e6SYuval Mintz u32 dp_module; 554fe56b9e6SYuval Mintz u8 dp_level; 555fe56b9e6SYuval Mintz char name[NAME_SIZE]; 556fe56b9e6SYuval Mintz 5579c79ddaaSMintz, Yuval enum qed_dev_type type; 558fc48b7a6SYuval Mintz /* Translate type/revision combo into the proper conditions */ 559fc48b7a6SYuval Mintz #define QED_IS_BB(dev) ((dev)->type == QED_DEV_TYPE_BB) 560fc48b7a6SYuval Mintz #define QED_IS_BB_A0(dev) (QED_IS_BB(dev) && \ 561fc48b7a6SYuval Mintz CHIP_REV_IS_A0(dev)) 562fc48b7a6SYuval Mintz #define QED_IS_BB_B0(dev) (QED_IS_BB(dev) && \ 563fc48b7a6SYuval Mintz CHIP_REV_IS_B0(dev)) 564c965db44STomer Tayar #define QED_IS_AH(dev) ((dev)->type == QED_DEV_TYPE_AH) 565c965db44STomer Tayar #define QED_IS_K2(dev) QED_IS_AH(dev) 566fc48b7a6SYuval Mintz 567fc48b7a6SYuval Mintz #define QED_GET_TYPE(dev) (QED_IS_BB_A0(dev) ? CHIP_BB_A0 : \ 568fc48b7a6SYuval Mintz QED_IS_BB_B0(dev) ? CHIP_BB_B0 : CHIP_K2) 569fc48b7a6SYuval Mintz 570fc48b7a6SYuval Mintz u16 vendor_id; 571fc48b7a6SYuval Mintz u16 device_id; 5729c79ddaaSMintz, Yuval #define QED_DEV_ID_MASK 0xff00 5739c79ddaaSMintz, Yuval #define QED_DEV_ID_MASK_BB 0x1600 5749c79ddaaSMintz, Yuval #define QED_DEV_ID_MASK_AH 0x8000 575fe56b9e6SYuval Mintz 576fe56b9e6SYuval Mintz u16 chip_num; 577fe56b9e6SYuval Mintz #define CHIP_NUM_MASK 0xffff 578fe56b9e6SYuval Mintz #define CHIP_NUM_SHIFT 16 579fe56b9e6SYuval Mintz 580fe56b9e6SYuval Mintz u16 chip_rev; 581fe56b9e6SYuval Mintz #define CHIP_REV_MASK 0xf 582fe56b9e6SYuval Mintz #define CHIP_REV_SHIFT 12 583fc48b7a6SYuval Mintz #define CHIP_REV_IS_A0(_cdev) (!(_cdev)->chip_rev) 584fc48b7a6SYuval Mintz #define CHIP_REV_IS_B0(_cdev) ((_cdev)->chip_rev == 1) 585fe56b9e6SYuval Mintz 586fe56b9e6SYuval Mintz u16 chip_metal; 587fe56b9e6SYuval Mintz #define CHIP_METAL_MASK 0xff 588fe56b9e6SYuval Mintz #define CHIP_METAL_SHIFT 4 589fe56b9e6SYuval Mintz 590fe56b9e6SYuval Mintz u16 chip_bond_id; 591fe56b9e6SYuval Mintz #define CHIP_BOND_ID_MASK 0xf 592fe56b9e6SYuval Mintz #define CHIP_BOND_ID_SHIFT 0 593fe56b9e6SYuval Mintz 594fe56b9e6SYuval Mintz u8 num_engines; 595fe56b9e6SYuval Mintz u8 num_ports_in_engines; 596fe56b9e6SYuval Mintz u8 num_funcs_in_port; 597fe56b9e6SYuval Mintz 598fe56b9e6SYuval Mintz u8 path_id; 599fc48b7a6SYuval Mintz enum qed_mf_mode mf_mode; 600fc48b7a6SYuval Mintz #define IS_MF_DEFAULT(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_DEFAULT) 601fc48b7a6SYuval Mintz #define IS_MF_SI(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_NPAR) 602fc48b7a6SYuval Mintz #define IS_MF_SD(_p_hwfn) (((_p_hwfn)->cdev)->mf_mode == QED_MF_OVLAN) 603fe56b9e6SYuval Mintz 604fe56b9e6SYuval Mintz int pcie_width; 605fe56b9e6SYuval Mintz int pcie_speed; 606fe56b9e6SYuval Mintz u8 ver_str[VER_SIZE]; 607fe56b9e6SYuval Mintz 608fe56b9e6SYuval Mintz /* Add MF related configuration */ 609fe56b9e6SYuval Mintz u8 mcp_rev; 610fe56b9e6SYuval Mintz u8 boot_mode; 611fe56b9e6SYuval Mintz 61214d39648SMintz, Yuval /* WoL related configurations */ 61314d39648SMintz, Yuval u8 wol_config; 61414d39648SMintz, Yuval u8 wol_mac[ETH_ALEN]; 615fe56b9e6SYuval Mintz 616fe56b9e6SYuval Mintz u32 int_mode; 617fe56b9e6SYuval Mintz enum qed_coalescing_mode int_coalescing_mode; 61851d99880SSudarsana Reddy Kalluru u16 rx_coalesce_usecs; 61951d99880SSudarsana Reddy Kalluru u16 tx_coalesce_usecs; 620fe56b9e6SYuval Mintz 621fe56b9e6SYuval Mintz /* Start Bar offset of first hwfn */ 622fe56b9e6SYuval Mintz void __iomem *regview; 623fe56b9e6SYuval Mintz void __iomem *doorbells; 624fe56b9e6SYuval Mintz u64 db_phys_addr; 625fe56b9e6SYuval Mintz unsigned long db_size; 626fe56b9e6SYuval Mintz 627fe56b9e6SYuval Mintz /* PCI */ 628fe56b9e6SYuval Mintz u8 cache_shift; 629fe56b9e6SYuval Mintz 630fe56b9e6SYuval Mintz /* Init */ 631fe56b9e6SYuval Mintz const struct iro *iro_arr; 632fe56b9e6SYuval Mintz #define IRO (p_hwfn->cdev->iro_arr) 633fe56b9e6SYuval Mintz 634fe56b9e6SYuval Mintz /* HW functions */ 635fe56b9e6SYuval Mintz u8 num_hwfns; 636fe56b9e6SYuval Mintz struct qed_hwfn hwfns[MAX_HWFNS_PER_DEVICE]; 637fe56b9e6SYuval Mintz 63832a47e72SYuval Mintz /* SRIOV */ 63932a47e72SYuval Mintz struct qed_hw_sriov_info *p_iov_info; 64032a47e72SYuval Mintz #define IS_QED_SRIOV(cdev) (!!(cdev)->p_iov_info) 64132a47e72SYuval Mintz 642464f6645SManish Chopra unsigned long tunn_mode; 6431408cc1fSYuval Mintz 6441408cc1fSYuval Mintz bool b_is_vf; 645fe56b9e6SYuval Mintz u32 drv_type; 646fe56b9e6SYuval Mintz struct qed_eth_stats *reset_stats; 647fe56b9e6SYuval Mintz struct qed_fw_data *fw_data; 648fe56b9e6SYuval Mintz 649fe56b9e6SYuval Mintz u32 mcp_nvm_resp; 650fe56b9e6SYuval Mintz 651fe56b9e6SYuval Mintz /* Linux specific here */ 652fe56b9e6SYuval Mintz struct qede_dev *edev; 653fe56b9e6SYuval Mintz struct pci_dev *pdev; 654fc831825SYuval Mintz u32 flags; 655fc831825SYuval Mintz #define QED_FLAG_STORAGE_STARTED (BIT(0)) 656fe56b9e6SYuval Mintz int msg_enable; 657fe56b9e6SYuval Mintz 658fe56b9e6SYuval Mintz struct pci_params pci_params; 659fe56b9e6SYuval Mintz 660fe56b9e6SYuval Mintz struct qed_int_params int_params; 661fe56b9e6SYuval Mintz 662fe56b9e6SYuval Mintz u8 protocol; 663fe56b9e6SYuval Mintz #define IS_QED_ETH_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_ETH) 6641e128c81SArun Easi #define IS_QED_FCOE_IF(cdev) ((cdev)->protocol == QED_PROTOCOL_FCOE) 665fe56b9e6SYuval Mintz 666cc875c2eSYuval Mintz /* Callbacks to protocol driver */ 667cc875c2eSYuval Mintz union { 668cc875c2eSYuval Mintz struct qed_common_cb_ops *common; 669cc875c2eSYuval Mintz struct qed_eth_cb_ops *eth; 6701e128c81SArun Easi struct qed_fcoe_cb_ops *fcoe; 671fc831825SYuval Mintz struct qed_iscsi_cb_ops *iscsi; 672cc875c2eSYuval Mintz } protocol_ops; 673cc875c2eSYuval Mintz void *ops_cookie; 674cc875c2eSYuval Mintz 675c965db44STomer Tayar struct qed_dbg_params dbg_params; 676c965db44STomer Tayar 6770a7fb11cSYuval Mintz #ifdef CONFIG_QED_LL2 6780a7fb11cSYuval Mintz struct qed_cb_ll2_info *ll2; 6790a7fb11cSYuval Mintz u8 ll2_mac_address[ETH_ALEN]; 6800a7fb11cSYuval Mintz #endif 681fc831825SYuval Mintz DECLARE_HASHTABLE(connections, 10); 682fe56b9e6SYuval Mintz const struct firmware *firmware; 68351ff1725SRam Amrani 68451ff1725SRam Amrani u32 rdma_max_sge; 68551ff1725SRam Amrani u32 rdma_max_inline; 68651ff1725SRam Amrani u32 rdma_max_srq_sge; 687fe56b9e6SYuval Mintz }; 688fe56b9e6SYuval Mintz 6899c79ddaaSMintz, Yuval #define NUM_OF_VFS(dev) (QED_IS_BB(dev) ? MAX_NUM_VFS_BB \ 6909c79ddaaSMintz, Yuval : MAX_NUM_VFS_K2) 6919c79ddaaSMintz, Yuval #define NUM_OF_L2_QUEUES(dev) (QED_IS_BB(dev) ? MAX_NUM_L2_QUEUES_BB \ 6929c79ddaaSMintz, Yuval : MAX_NUM_L2_QUEUES_K2) 6939c79ddaaSMintz, Yuval #define NUM_OF_PORTS(dev) (QED_IS_BB(dev) ? MAX_NUM_PORTS_BB \ 6949c79ddaaSMintz, Yuval : MAX_NUM_PORTS_K2) 6959c79ddaaSMintz, Yuval #define NUM_OF_SBS(dev) (QED_IS_BB(dev) ? MAX_SB_PER_PATH_BB \ 6969c79ddaaSMintz, Yuval : MAX_SB_PER_PATH_K2) 6979c79ddaaSMintz, Yuval #define NUM_OF_ENG_PFS(dev) (QED_IS_BB(dev) ? MAX_NUM_PFS_BB \ 6989c79ddaaSMintz, Yuval : MAX_NUM_PFS_K2) 699fe56b9e6SYuval Mintz 700fe56b9e6SYuval Mintz /** 701fe56b9e6SYuval Mintz * @brief qed_concrete_to_sw_fid - get the sw function id from 702fe56b9e6SYuval Mintz * the concrete value. 703fe56b9e6SYuval Mintz * 704fe56b9e6SYuval Mintz * @param concrete_fid 705fe56b9e6SYuval Mintz * 706fe56b9e6SYuval Mintz * @return inline u8 707fe56b9e6SYuval Mintz */ 708fe56b9e6SYuval Mintz static inline u8 qed_concrete_to_sw_fid(struct qed_dev *cdev, 709fe56b9e6SYuval Mintz u32 concrete_fid) 710fe56b9e6SYuval Mintz { 7114870e704SYuval Mintz u8 vfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_VFID); 712fe56b9e6SYuval Mintz u8 pfid = GET_FIELD(concrete_fid, PXP_CONCRETE_FID_PFID); 7134870e704SYuval Mintz u8 vf_valid = GET_FIELD(concrete_fid, 7144870e704SYuval Mintz PXP_CONCRETE_FID_VFVALID); 7154870e704SYuval Mintz u8 sw_fid; 716fe56b9e6SYuval Mintz 7174870e704SYuval Mintz if (vf_valid) 7184870e704SYuval Mintz sw_fid = vfid + MAX_NUM_PFS; 7194870e704SYuval Mintz else 7204870e704SYuval Mintz sw_fid = pfid; 7214870e704SYuval Mintz 7224870e704SYuval Mintz return sw_fid; 723fe56b9e6SYuval Mintz } 724fe56b9e6SYuval Mintz 725fe56b9e6SYuval Mintz #define PURE_LB_TC 8 726dbb799c3SYuval Mintz #define OOO_LB_TC 9 727fe56b9e6SYuval Mintz 728733def6aSYuval Mintz int qed_configure_vport_wfq(struct qed_dev *cdev, u16 vp_id, u32 rate); 7296f437d43SMintz, Yuval void qed_configure_vp_wfq_on_link_change(struct qed_dev *cdev, 7306f437d43SMintz, Yuval struct qed_ptt *p_ptt, 7316f437d43SMintz, Yuval u32 min_pf_rate); 732bcd197c8SManish Chopra 733733def6aSYuval Mintz void qed_clean_wfq_db(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt); 734fe56b9e6SYuval Mintz #define QED_LEADING_HWFN(dev) (&dev->hwfns[0]) 7359c79ddaaSMintz, Yuval int qed_device_num_engines(struct qed_dev *cdev); 736fe56b9e6SYuval Mintz 737fe56b9e6SYuval Mintz /* Other Linux specific common definitions */ 738fe56b9e6SYuval Mintz #define DP_NAME(cdev) ((cdev)->name) 739fe56b9e6SYuval Mintz 740fe56b9e6SYuval Mintz #define REG_ADDR(cdev, offset) (void __iomem *)((u8 __iomem *)\ 741fe56b9e6SYuval Mintz (cdev->regview) + \ 742fe56b9e6SYuval Mintz (offset)) 743fe56b9e6SYuval Mintz 744fe56b9e6SYuval Mintz #define REG_RD(cdev, offset) readl(REG_ADDR(cdev, offset)) 745fe56b9e6SYuval Mintz #define REG_WR(cdev, offset, val) writel((u32)val, REG_ADDR(cdev, offset)) 746fe56b9e6SYuval Mintz #define REG_WR16(cdev, offset, val) writew((u16)val, REG_ADDR(cdev, offset)) 747fe56b9e6SYuval Mintz 748fe56b9e6SYuval Mintz #define DOORBELL(cdev, db_addr, val) \ 749fe56b9e6SYuval Mintz writel((u32)val, (void __iomem *)((u8 __iomem *)\ 750fe56b9e6SYuval Mintz (cdev->doorbells) + (db_addr))) 751fe56b9e6SYuval Mintz 752fe56b9e6SYuval Mintz /* Prototypes */ 753fe56b9e6SYuval Mintz int qed_fill_dev_info(struct qed_dev *cdev, 754fe56b9e6SYuval Mintz struct qed_dev_info *dev_info); 755cc875c2eSYuval Mintz void qed_link_update(struct qed_hwfn *hwfn); 756fe56b9e6SYuval Mintz u32 qed_unzip_data(struct qed_hwfn *p_hwfn, 757fe56b9e6SYuval Mintz u32 input_len, u8 *input_buf, 758fe56b9e6SYuval Mintz u32 max_size, u8 *unzip_buf); 7596c754246SSudarsana Reddy Kalluru void qed_get_protocol_stats(struct qed_dev *cdev, 7606c754246SSudarsana Reddy Kalluru enum qed_mcp_protocol_type type, 7616c754246SSudarsana Reddy Kalluru union qed_mcp_protocol_stats *stats); 7628f16bc97SSudarsana Kalluru int qed_slowpath_irq_req(struct qed_hwfn *hwfn); 7631226337aSTomer Tayar void qed_slowpath_irq_sync(struct qed_hwfn *p_hwfn); 7648f16bc97SSudarsana Kalluru 765fe56b9e6SYuval Mintz #endif /* _QED_H */ 766